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kevintownsend/R3 | coregen/fifo_fwft_64x512/simulation/fg_tb_top.vhd | 2 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 69
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | 4c208c7f97234abfda0c3c5b299ca01e | 0.616306 | 4.175735 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512_hf/example_design/fifo_64x512_hf_top.vhd | 1 | 5,116 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_64x512_hf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_64x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_64x512_hf_top;
architecture xilinx of fifo_64x512_hf_top is
SIGNAL clk_i : std_logic;
component fifo_64x512_hf is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_64x512_hf PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | ec13bd171166abba56212286652e8ca5 | 0.515637 | 4.872381 | false | false | false | false |
Wynjones1/VHDL-Tests | simu/alu_tb.vhd | 1 | 1,173 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types.all;
entity alu_tb is
end;
architecture rtl of alu_tb is
component alu is
port( op : in alu_op_t;
i0 : in reg_t;
i1 : in reg_t;
q : out reg_t;
flags_in : in reg_t;
flags_out : out reg_t);
end component;
signal clk : std_logic;
signal op : alu_op_t;
signal input : std_logic_vector(16 downto 0) := (others => '0');
signal i0 : reg_t := (others => '0');
signal i1 : reg_t := (others => '0');
signal q : reg_t := (others => '0');
signal flags_in : reg_t := (others => '0');
signal flags_out : reg_t := (others => '0');
begin
alu0: alu
port map (op, i0, i1, q, flags_in, flags_out);
clkgen:
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
gen_data:
process(clk)
begin
if rising_edge(clk) then
op <= alu_op_or;
input <= std_logic_vector( unsigned(input) + 1);
end if;
end process;
i0 <= input( 7 downto 0);
i1 <= input(15 downto 8);
flags_in(CARRY_BIT) <= input(16);
end rtl;
| mit | 1cdd9a814bc53ae54c2b7906ff898cc1 | 0.55243 | 2.618304 | false | false | false | false |
capitanov/MinesweeperFPGA | src/top_level/ctrl_main_block.vhd | 1 | 2,623 | --------------------------------------------------------------------------------
--
-- Title : ctrl_main_block.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Main block for VGA game
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.all;
entity ctrl_main_block is
port(
-- system signals
reset : in std_logic; -- SW(0)
clk : in std_logic; -- Pixel clk - DCM should generate 25 MHz freq;
-- ps/2 signals
ps2_clk : in std_logic; -- PS/2 CLOCK
ps2_data : in std_logic; -- PS/2 SERIAL DATA
-- vga output signals
h_vga : out std_logic; -- horizontal
v_vga : out std_logic; -- vertical
rgb : out std_logic_vector(2 downto 0); -- (R-G-B)
-- test leds signals
leds : out std_logic_vector(8 downto 1)
);
end ctrl_main_block;
architecture ctrl_main_block of ctrl_main_block is
signal data_keyboard : key_data;
signal data_new : std_logic;
signal disp : std_logic;
signal h_sync : std_logic;
signal v_sync : std_logic;
signal dataX : std_logic_vector(9 downto 0);
signal dataY : std_logic_vector(8 downto 0);
signal led : std_logic_vector(8 downto 1);
begin
leds(6 downto 1) <= led(6 downto 1);
leds(7) <= ps2_data;
leds(8) <= data_new;
h_vga <= h_sync after 1 ns when rising_edge(clk);
v_vga <= v_sync after 1 ns when rising_edge(clk);
---------------- stage 0: KEYBOARD CTRL ----------------
x_keyboard: ctrl_key_decoder
port map(
-- system signals:
clk => clk,
-- keyboard in:
ps2_clk => ps2_clk,
ps2_data => ps2_data,
-- keyboard out:
keys_out => data_keyboard,
new_key => data_new
);
---------------- stage 1: VGA CTRL ----------------
x_vga_ctrl640x480 : vga_ctrl640x480
port map(
-- system signals:
clk => clk,
reset => reset,
-- Horizontal and Vertical sync:
h_sync => h_sync,
v_sync => v_sync,
-- Display
disp => disp,
-- vga XoY coordinates:
x_out => dataX,
y_out => dataY
);
---------------- stage 2: MAIN BLOCK ----------------
x_ctrl_game_block : ctrl_game_block
port map(
-- system signals:
clk => clk,
reset => reset,
-- keyboard:
push_keys => data_keyboard,
-- vga XoY coordinates:
display => disp,
x_char => dataX,
y_char => dataY,
-- output vga scheme:
rgb => rgb,
leds => led
);
end ctrl_main_block; | mit | 10c485d9cfcd9ac71178c24ec2c3025d | 0.532596 | 2.898343 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/simulation/fg_tb_pkg.vhd | 1 | 11,307 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_fwft_64x1024_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 81c34b9d3a2c248a315bfb75b086a805 | 0.503847 | 3.93287 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/MAR.vhd | 2 | 614 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MAR is
port(
clk, lat: in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16: out std_logic_vector(15 downto 0);
M_ad8: out std_logic_vector(7 downto 0)
);
end MAR;
architecture BEHAVIOR of MAR is
signal rst:std_logic_vector(15 downto 0);
begin
M_ad16 <= rst;
M_ad8 <= rst(7 downto 0);
process(clk)begin
if (clk'event and (clk = '1') and (lat ='1')) then
rst <= busC;
else
null;
end if;
end process;
end BEHAVIOR;
| mit | 21d1015c9ced2fcb83b32907ec6d8324 | 0.579805 | 2.966184 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_36x512_hf/simulation/fg_tb_pkg.vhd | 1 | 11,358 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_36x512_hf_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(36-1 DOWNTO 0);
DOUT : OUT std_logic_vector(36-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 8af9b21317bdd4283a018e8e83b98bac | 0.503082 | 3.935551 | false | false | false | false |
znuh/open-nexys | bscan_la/top.vhd | 1 | 2,516 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity la is
Port(
xtalClock : in std_logic;
Led : out std_logic_vector(7 downto 0);
sw : in std_logic_vector(7 downto 0);
btn : in std_logic_vector(3 downto 0)
);
end la;
architecture Behavioral of la is
COMPONENT clockman
PORT(
clkin : in STD_LOGIC;
clk0 : out std_logic
);
END COMPONENT;
component bscan_la is
Port(
clock : in std_logic;
exClock : in std_logic;
input : in std_logic_vector(31 downto 0);
reset : in std_logic;
CAPTURE : in std_logic;
DRCK : in std_logic;
SEL : in std_logic;
SHIFT : in std_logic;
UPDATE : in std_logic;
TDO : out std_logic;
TDI : in std_logic
);
end component;
signal CAPTURE : std_logic;
signal DRCK : std_logic;
signal SEL : std_logic;
signal SHIFT : std_logic;
signal UPDATE : std_logic;
signal TDO : std_logic;
signal TDI : std_logic;
signal clock : std_logic;
signal test_counter : std_logic_vector(31 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
test_counter <= test_counter + 1;
end if;
end process;
-- there's nothing useful here to put on the LEDs...
Led <= x"00";
-- instantiated in toplevel module
-- as the 2nd user instruction may be used for another thing
BSCAN_SPARTAN3_inst : BSCAN_SPARTAN3
port map (
CAPTURE => CAPTURE, -- CAPTURE output from TAP controller
DRCK1 => DRCK, -- Data register output for USER1 functions
DRCK2 => open, -- Data register output for USER2 functions
RESET => open, -- Reset output from TAP controller
SEL1 => SEL, -- USER1 active output
SEL2 => open, -- USER2 active output
SHIFT => SHIFT, -- SHIFT output from TAP controller
TDI => TDI, -- TDI output from TAP controller
UPDATE => UPDATE, -- UPDATE output from TAP controller
TDO1 => TDO, -- Data input for USER1 function
TDO2 => open -- Data input for USER2 function
);
-- instantiated in toplevel module
-- as there might be more components needind the system clock
Inst_clockman: clockman PORT MAP(
clkin => xtalClock,
clk0 => clock
);
bscan_la_inst: bscan_la
port map (
clock => clock,
exClock => '0',
input => test_counter,
reset => btn(0),
CAPTURE => CAPTURE,
DRCK => DRCK,
SEL => SEL,
SHIFT => SHIFT,
UPDATE => UPDATE,
TDO => TDO,
TDI => TDI
);
end Behavioral;
| gpl-2.0 | 767532ff2bd25ab3be8137dd4ae1574b | 0.647456 | 3.288889 | false | false | false | false |
capitanov/MinesweeperFPGA | src/game_cores/cl_select_text.vhd | 1 | 12,396 | --------------------------------------------------------------------------------
--
-- Title : cl_select_text.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Text selector
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity cl_select_text is
port(
x_char : in std_logic_vector(6 downto 0); -- X line: 0:79
y_char : in std_logic_vector(4 downto 0); -- Y line: 0:29
win : in std_logic;
lose : in std_logic;
game : in std_logic;
cntgames: in std_logic;
addr_rnd: in std_logic_vector(4 downto 0);
ch_data : out std_logic_vector(7 downto 0) -- selected data
);
end cl_select_text;
architecture cl_select_text of cl_select_text is
signal x_int : integer range 0 to 79 :=0;
signal y_int : integer range 0 to 29 :=0;
signal addr : integer range 0 to 31 :=0;
begin
x_int <= to_integer(unsigned(x_char));
y_int <= to_integer(unsigned(y_char));
addr <= to_integer(unsigned(addr_rnd));
process(y_int, x_int, addr, win, lose, game, cntgames) is
begin
if y_int = 5 then
case x_int is
when 16 => ch_data <= x"54"; -- T
when 17 => ch_data <= x"68"; -- h
when 18 => ch_data <= x"65"; -- e
when 19 => ch_data <= x"00"; --
when 20 => ch_data <= x"4D"; -- M
when 21 => ch_data <= x"69"; -- i
when 22 => ch_data <= x"6E"; -- n
when 23 => ch_data <= x"65"; -- e
when 24 => ch_data <= x"73"; -- s
when 25 => ch_data <= x"77"; -- w
when 26 => ch_data <= x"65"; -- e
when 27 => ch_data <= x"65"; -- e
when 28 => ch_data <= x"70"; -- p
when 29 => ch_data <= x"65"; -- e
when 30 => ch_data <= x"72"; -- r
when 31 => ch_data <= x"00"; --
when 32 => ch_data <= x"67"; -- g
when 33 => ch_data <= x"61"; -- a
when 34 => ch_data <= x"6D"; -- m
when 35 => ch_data <= x"65"; -- e
when 36 => ch_data <= x"00"; --
when 37 => ch_data <= x"6F"; -- o
when 38 => ch_data <= x"6E"; -- n
when 39 => ch_data <= x"00"; --
when 40 => ch_data <= x"46"; -- F
when 41 => ch_data <= x"50"; -- P
when 42 => ch_data <= x"47"; -- G
when 43 => ch_data <= x"41"; -- A
when 44 => ch_data <= x"00"; --
when 45 => ch_data <= x"58"; -- X
when 46 => ch_data <= x"43"; -- C
when 47 => ch_data <= x"33"; -- 3
when 48 => ch_data <= x"35"; -- 5
when 49 => ch_data <= x"30"; -- 0
when 50 => ch_data <= x"30"; -- 0
when 51 => ch_data <= x"45"; -- E
when others => ch_data <= x"00";
end case;
elsif y_int = 6 then
case x_int is
when 32 => ch_data <= x"62"; -- b
when 33 => ch_data <= x"79"; -- y
when 34 => ch_data <= x"00"; --
when 35 => ch_data <= x"4B"; -- K
when 36 => ch_data <= x"61"; -- a
when 37 => ch_data <= x"70"; -- p
when 38 => ch_data <= x"69"; -- i
when 39 => ch_data <= x"74"; -- t
when 40 => ch_data <= x"61"; -- a
when 41 => ch_data <= x"6E"; -- n
when 42 => ch_data <= x"6F"; -- o
when 43 => ch_data <= x"76"; -- v
when 44 => ch_data <= x"00"; --
when 45 => ch_data <= x"41"; -- A
when 46 => ch_data <= x"6C"; -- l
when 47 => ch_data <= x"65"; -- e
when 48 => ch_data <= x"78"; -- x
when 49 => ch_data <= x"61"; -- a
when 50 => ch_data <= x"6E"; -- n
when 51 => ch_data <= x"64"; -- d
when 52 => ch_data <= x"65"; -- e
when 53 => ch_data <= x"72"; -- r
when 54 => ch_data <= x"00"; --
when 55 => ch_data <= x"2A"; -- $
when others => ch_data <= x"00";
end case;
elsif y_int = 7 then
case x_int is
when 16 => ch_data <= x"52"; -- R
when 17 => ch_data <= x"75"; -- u
when 18 => ch_data <= x"6C"; -- l
when 19 => ch_data <= x"65"; -- e
when 20 => ch_data <= x"73"; -- s
when 21 => ch_data <= x"3A"; -- :
when others => ch_data <= x"00";
end case;
elsif y_int = 8 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"53"; -- S
when 20 => ch_data <= x"50"; -- P
when 21 => ch_data <= x"41"; -- A
when 22 => ch_data <= x"43"; -- C
when 23 => ch_data <= x"45"; -- E
when 24 => ch_data <= x"00"; --
when 25 => ch_data <= x"2D"; -- -
when 26 => ch_data <= x"00"; --
when 27 => ch_data <= x"73"; -- s
when 28 => ch_data <= x"74"; -- t
when 29 => ch_data <= x"61"; -- a
when 30 => ch_data <= x"72"; -- r
when 31 => ch_data <= x"74"; -- t
when 32 => ch_data <= x"00"; --
when 33 => ch_data <= x"6e"; -- n
when 34 => ch_data <= x"65"; -- e
when 35 => ch_data <= x"77"; -- w
when 36 => ch_data <= x"00"; --
when 37 => ch_data <= x"67"; -- g
when 38 => ch_data <= x"61"; -- a
when 39 => ch_data <= x"6D"; -- m
when 40 => ch_data <= x"65"; -- e
when 41 => ch_data <= x"2C"; -- ,
when others => ch_data <= x"00";
end case;
elsif y_int = 9 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"45"; -- E
when 20 => ch_data <= x"4E"; -- N
when 21 => ch_data <= x"54"; -- T
when 22 => ch_data <= x"45"; -- E
when 23 => ch_data <= x"52"; -- R
when 24 => ch_data <= x"00"; --
when 25 => ch_data <= x"2D"; -- -
when 26 => ch_data <= x"00"; --
when 27 => ch_data <= x"63"; -- c
when 28 => ch_data <= x"68"; -- h
when 29 => ch_data <= x"65"; -- e
when 30 => ch_data <= x"63"; -- c
when 31 => ch_data <= x"6B"; -- k
when 32 => ch_data <= x"00"; --
when 33 => ch_data <= x"61"; -- a
when 34 => ch_data <= x"00"; --
when 35 => ch_data <= x"66"; -- f
when 36 => ch_data <= x"69"; -- i
when 37 => ch_data <= x"65"; -- e
when 38 => ch_data <= x"6C"; -- l
when 39 => ch_data <= x"64"; -- d
when 40 => ch_data <= x"2C"; -- ,
when others => ch_data <= x"00";
end case;
elsif y_int = 10 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"27"; -- "
when 20 => ch_data <= x"57"; -- W
when 21 => ch_data <= x"53"; -- S
when 22 => ch_data <= x"41"; -- A
when 23 => ch_data <= x"44"; -- D
when 24 => ch_data <= x"27"; -- "
-- when 25 => ch_data <= x"00"; --
when 25 => ch_data <= x"2D"; -- -
when 26 => ch_data <= x"00"; --
when 27 => ch_data <= x"6B"; -- k
when 28 => ch_data <= x"65"; -- e
when 29 => ch_data <= x"79"; -- y
when 30 => ch_data <= x"73"; -- s
when 31 => ch_data <= x"00"; --
when 32 => ch_data <= x"66"; -- f
when 33 => ch_data <= x"6F"; -- o
when 34 => ch_data <= x"72"; -- r
when 35 => ch_data <= x"00"; --
when 36 => ch_data <= x"6D"; -- m
when 37 => ch_data <= x"6F"; -- o
when 38 => ch_data <= x"76"; -- v
when 39 => ch_data <= x"69"; -- i
when 40 => ch_data <= x"6E"; -- n
when 41 => ch_data <= x"67"; -- g
when 42 => ch_data <= x"2C"; -- ,
when others => ch_data <= x"00";
end case;
elsif y_int = 11 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"45"; -- E
when 20 => ch_data <= x"53"; -- S
when 21 => ch_data <= x"43"; -- C
when 22 => ch_data <= x"00"; --
when 23 => ch_data <= x"2D"; -- -
when 24 => ch_data <= x"00"; --
when 25 => ch_data <= x"65"; -- e
when 26 => ch_data <= x"78"; -- x
when 27 => ch_data <= x"69"; -- i
when 28 => ch_data <= x"74"; -- t
when 29 => ch_data <= x"2C"; -- .
when others => ch_data <= x"00";
end case;
elsif y_int = 12 then
case x_int is
when 17 => ch_data <= x"3E"; -- >
when 18 => ch_data <= x"00"; --
when 19 => ch_data <= x"38"; -- 8
when 20 => ch_data <= x"00"; --
when 21 => ch_data <= x"6D"; -- m
when 22 => ch_data <= x"69"; -- i
when 23 => ch_data <= x"6E"; -- n
when 24 => ch_data <= x"65"; -- e
when 25 => ch_data <= x"73"; -- s
when 26 => ch_data <= x"00"; --
when 27 => ch_data <= x"6F"; -- o
when 28 => ch_data <= x"6E"; -- n
when 29 => ch_data <= x"6C"; -- l
when 30 => ch_data <= x"79"; -- y
when 31 => ch_data <= x"2E"; -- .
when others => ch_data <= x"00";
end case;
elsif y_int = 14 then
case x_int is
when 16 => ch_data <= x"47"; -- G
when 17 => ch_data <= x"41"; -- A
when 18 => ch_data <= x"4D"; -- M
when 19 => ch_data <= x"45"; -- E
when 20 => ch_data <= x"00"; --
when 21 =>
if cntgames = '1' then
if (addr < 10) then
ch_data <= x"30";
elsif ((10 <= addr) and (addr < 20)) then
ch_data <= x"31";
elsif ((20 <= addr) and (addr < 30)) then
ch_data <= x"32";
else
ch_data <= x"33";
end if;
else
ch_data <= x"05";
end if;
when 22 =>
if cntgames = '1' then
if ((addr = 0) or (addr = 10) or (addr = 20) or (addr = 30)) then
ch_data <= x"30";
elsif ((addr = 1) or (addr = 11) or (addr = 21) or (addr = 31)) then
ch_data <= x"31";
elsif ((addr = 2) or (addr = 12) or (addr = 22)) then
ch_data <= x"32";
elsif ((addr = 3) or (addr = 13) or (addr = 23)) then
ch_data <= x"33";
elsif ((addr = 4) or (addr = 14) or (addr = 24)) then
ch_data <= x"34";
elsif ((addr = 5) or (addr = 15) or (addr = 25)) then
ch_data <= x"35";
elsif ((addr = 6) or (addr = 16) or (addr = 26)) then
ch_data <= x"36";
elsif ((addr = 7) or (addr = 17) or (addr = 27)) then
ch_data <= x"37";
elsif ((addr = 8) or (addr = 18) or (addr = 28)) then
ch_data <= x"38";
elsif ((addr = 9) or (addr = 19) or (addr = 29)) then
ch_data <= x"39";
else
null;
end if;
else
ch_data <= x"05";
end if;
when others => ch_data <= x"00";
end case;
elsif y_int = 16 then
if lose = '1' then
case x_int is
when 26 => ch_data <= x"0F"; -- :(
when 27 => ch_data <= x"00"; --
when 28 => ch_data <= x"47"; -- G
when 29 => ch_data <= x"41"; -- A
when 30 => ch_data <= x"4D"; -- M
when 31 => ch_data <= x"45"; -- E
when 32 => ch_data <= x"00"; --
when 33 => ch_data <= x"4F"; -- O
when 34 => ch_data <= x"56"; -- V
when 35 => ch_data <= x"45"; -- E
when 36 => ch_data <= x"52"; -- R
when 37 => ch_data <= x"00"; --
when 38 => ch_data <= x"0F"; -- :(
when others => ch_data <= x"00";
end case;
elsif win = '1' then
case x_int is
when 26 => ch_data <= x"01"; -- :)
when 27 => ch_data <= x"00"; --
when 28 => ch_data <= x"59"; -- Y
when 29 => ch_data <= x"4F"; -- O
when 30 => ch_data <= x"55"; -- U
when 31 => ch_data <= x"00"; --
when 32 => ch_data <= x"57"; -- W
when 33 => ch_data <= x"49"; -- I
when 34 => ch_data <= x"4E"; -- N
when 35 => ch_data <= x"21"; -- !
when 36 => ch_data <= x"21"; -- !
when 37 => ch_data <= x"00"; --
when 38 => ch_data <= x"01"; -- :)
when others => ch_data <= x"00";
end case;
else
ch_data <= x"00";
end if;
elsif y_int = 19 then
if game = '1' then
case x_int is
when 26 => ch_data <= x"4E"; -- N
when 27 => ch_data <= x"65"; -- e
when 28 => ch_data <= x"77"; -- w
when 29 => ch_data <= x"00"; --
when 30 => ch_data <= x"67"; -- g
when 31 => ch_data <= x"61"; -- a
when 32 => ch_data <= x"6D"; -- m
when 33 => ch_data <= x"65"; -- e
when 34 => ch_data <= x"00"; --
when 35 => ch_data <= x"7b"; -- {
when 36 => ch_data <= x"59"; -- Y
when 37 => ch_data <= x"2F"; -- /
when 38 => ch_data <= x"4e"; -- N
when 39 => ch_data <= x"7d"; -- }
when 40 => ch_data <= x"3F"; -- ?
when others => ch_data <= x"00";
end case;
else
ch_data <= x"00";
end if;
else
ch_data <= x"00";
end if;
end process;
end cl_select_text; | mit | 9368fc8a5c1e6f29a6327f3877ddcf15 | 0.432317 | 2.648718 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512/simulation/fg_tb_synth.vhd | 1 | 10,351 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(96-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 96,
C_DOUT_WIDTH => 96,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 96,
C_DIN_WIDTH => 96,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 96,
C_DIN_WIDTH => 96,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_fwft_96x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | e3a377215d94a7e33bccbf0b24559692 | 0.460439 | 4.10754 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_36x512_hf/example_design/fifo_36x512_hf_top.vhd | 1 | 5,116 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_36x512_hf_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_36x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(36-1 DOWNTO 0);
DOUT : OUT std_logic_vector(36-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_36x512_hf_top;
architecture xilinx of fifo_36x512_hf_top is
SIGNAL clk_i : std_logic;
component fifo_36x512_hf is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(36-1 DOWNTO 0);
DOUT : OUT std_logic_vector(36-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_36x512_hf PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 4aa12479f50a339e7948ac75891cc923 | 0.515637 | 4.872381 | false | false | false | false |
zeruniverse/Single-cycle_CPU | ISE project/ipcore_dir/Ins_Mem.vhd | 1 | 5,717 | --------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file Ins_Mem.vhd when simulating
-- the core, Ins_Mem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY Ins_Mem IS
port (
a: in std_logic_vector(9 downto 0);
spo: out std_logic_vector(31 downto 0));
END Ins_Mem;
ARCHITECTURE Ins_Mem_a OF Ins_Mem IS
-- synthesis translate_off
component wrapped_Ins_Mem
port (
a: in std_logic_vector(9 downto 0);
spo: out std_logic_vector(31 downto 0));
end component;
-- Configuration specification
for all : wrapped_Ins_Mem use entity XilinxCoreLib.dist_mem_gen_v5_1(behavioral)
generic map(
c_has_clk => 0,
c_has_qdpo_clk => 0,
c_has_qdpo_ce => 0,
c_parser_type => 1,
c_has_d => 0,
c_has_spo => 1,
c_read_mif => 1,
c_has_qspo => 0,
c_width => 32,
c_reg_a_d_inputs => 0,
c_has_we => 0,
c_pipeline_stages => 0,
c_has_qdpo_rst => 0,
c_reg_dpra_input => 0,
c_qualify_we => 0,
c_family => "spartan3",
c_sync_enable => 1,
c_depth => 1024,
c_has_qspo_srst => 0,
c_has_qdpo_srst => 0,
c_has_dpra => 0,
c_qce_joined => 0,
c_mem_type => 0,
c_has_i_ce => 0,
c_has_dpo => 0,
c_mem_init_file => "Ins_Mem.mif",
c_default_data => "0",
c_has_spra => 0,
c_has_qspo_ce => 0,
c_addr_width => 10,
c_has_qspo_rst => 0,
c_has_qdpo => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_Ins_Mem
port map (
a => a,
spo => spo);
-- synthesis translate_on
END Ins_Mem_a;
| gpl-3.0 | 243c0c1807fa88cd6c5eedc8b91f3f1e | 0.512157 | 4.418083 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_64x512/simulation/fg_tb_synth.vhd | 1 | 9,294 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_fwft_64x512_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | 483d582db9ab56d857ca504b6d22e7d3 | 0.452658 | 4.203528 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/M9K_RAM.vhd | 1 | 7,140 | -- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: M9K_RAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY M9K_RAM IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
init_phase : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
input : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rden : IN STD_LOGIC := '1';
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END M9K_RAM;
ARCHITECTURE SYN OF m9k_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal a : std_logic_vector(7 downto 0);
signal d : std_logic_vector(15 downto 0);
signal w : std_logic;
BEGIN
a <= X"00" when (init_phase = X"1") else address;
d <= input when (init_phase = X"1") else data;
w <= '1' when (init_phase = X"1") else wren;
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../content.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
maximum_depth => 256,
numwords_a => 256,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
ram_block_type => "M9K",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 8,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => a,
clock0 => clock,
data_a => d,
wren_a => w,
rden_a => rden,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256"
-- Retrieval info: PRIVATE: MIFfilename STRING "../content.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../content.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "256"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
| mit | 7bb777775f1a4dcc1e70dd97bdab425e | 0.669888 | 3.5086 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_32x512/simulation/fg_tb_pkg.vhd | 1 | 11,247 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_32x512_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 7fe710447d36da3cf452c6d3b02e6158 | 0.504401 | 3.929769 | false | false | false | false |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/YM2149/YM2149_linmix.vhd | 1 | 21,390 | --
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email [email protected]
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
-- accurate for designs where the outputs are buffered and not simply wired together.
-- The ouput level is more complex in that case and requires a larger table.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity YM2149 is
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic;
I_A8 : in std_logic;
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
I_SEL_L : in std_logic;
O_AUDIO : out std_logic_vector(7 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end;
architecture RTL of YM2149 is
type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal addr : std_logic_vector(7 downto 0);
signal busctrl_addr : std_logic;
signal busctrl_we : std_logic;
signal busctrl_re : std_logic;
signal reg : array_16x8;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : std_logic_vector(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal tone_ena_l : std_logic;
signal tone_src : std_logic;
signal noise_ena_l : std_logic;
signal chan_vol : std_logic_vector(4 downto 0);
signal dac_amp : std_logic_vector(7 downto 0);
signal audio_mix : std_logic_vector(9 downto 0);
signal audio_final : std_logic_vector(9 downto 0);
begin
-- cpu i/f
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
variable cs : std_logic;
variable sel : std_logic_vector(2 downto 0);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
busctrl_addr <= '0';
busctrl_we <= '0';
busctrl_re <= '0';
cs := '0';
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
cs := '1';
end if;
sel := (I_BDIR & I_BC2 & I_BC1);
case sel is
when "000" => null;
when "001" => busctrl_addr <= '1';
when "010" => null;
when "011" => busctrl_re <= cs;
when "100" => busctrl_addr <= '1';
when "101" => null;
when "110" => busctrl_we <= cs;
when "111" => busctrl_addr <= '1';
when others => null;
end case;
end process;
p_oe : process(busctrl_re)
begin
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
O_DA_OE_L <= not (busctrl_re);
end process;
--
-- CLOCKED
--
--p_waddr : process
--begin
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
--wait until rising_edge(CLK);
--if (RESET_L = '0') then
--addr <= (others => '0');
--else
--if (busctrl_addr = '1') then
--addr <= I_DA;
--end if;
--end if;
--end process;
--p_wdata : process
--begin
---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
--wait until rising_edge(CLK);
--env_reset <= '0';
--if (RESET_L = '0') then
--reg <= (others => (others => '0'));
--env_reset <= '1';
--else
--env_reset <= '0';
--if (busctrl_we = '1') then
--case addr(3 downto 0) is
--when x"0" => reg(0) <= I_DA;
--when x"1" => reg(1) <= I_DA;
--when x"2" => reg(2) <= I_DA;
--when x"3" => reg(3) <= I_DA;
--when x"4" => reg(4) <= I_DA;
--when x"5" => reg(5) <= I_DA;
--when x"6" => reg(6) <= I_DA;
--when x"7" => reg(7) <= I_DA;
--when x"8" => reg(8) <= I_DA;
--when x"9" => reg(9) <= I_DA;
--when x"A" => reg(10) <= I_DA;
--when x"B" => reg(11) <= I_DA;
--when x"C" => reg(12) <= I_DA;
--when x"D" => reg(13) <= I_DA; env_reset <= '1';
--when x"E" => reg(14) <= I_DA;
--when x"F" => reg(15) <= I_DA;
--when others => null;
--end case;
--end if;
--end if;
--end process;
--
-- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
--
p_waddr : process(reset_l, busctrl_addr)
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
if (RESET_L = '0') then
addr <= (others => '0');
elsif falling_edge(busctrl_addr) then -- yuk
addr <= I_DA;
end if;
end process;
p_wdata : process(reset_l, busctrl_we, addr)
begin
if (RESET_L = '0') then
reg <= (others => (others => '0'));
elsif falling_edge(busctrl_we) then
case addr(3 downto 0) is
when x"0" => reg(0) <= I_DA;
when x"1" => reg(1) <= I_DA;
when x"2" => reg(2) <= I_DA;
when x"3" => reg(3) <= I_DA;
when x"4" => reg(4) <= I_DA;
when x"5" => reg(5) <= I_DA;
when x"6" => reg(6) <= I_DA;
when x"7" => reg(7) <= I_DA;
when x"8" => reg(8) <= I_DA;
when x"9" => reg(9) <= I_DA;
when x"A" => reg(10) <= I_DA;
when x"B" => reg(11) <= I_DA;
when x"C" => reg(12) <= I_DA;
when x"D" => reg(13) <= I_DA;
when x"E" => reg(14) <= I_DA;
when x"F" => reg(15) <= I_DA;
when others => null;
end case;
end if;
env_reset <= '0';
if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
env_reset <= '1';
end if;
end process;
p_rdata : process(busctrl_re, addr, reg)
begin
O_DA <= (others => '0'); -- 'X'
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case addr(3 downto 0) is
when x"0" => O_DA <= reg(0) ;
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
when x"2" => O_DA <= reg(2) ;
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
when x"4" => O_DA <= reg(4) ;
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
when x"7" => O_DA <= reg(7) ;
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
when x"B" => O_DA <= reg(11);
when x"C" => O_DA <= reg(12);
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
when x"E" => if (reg(7)(6) = '0') then -- input
O_DA <= ioa_inreg;
else
O_DA <= reg(14); -- read output reg
end if;
when x"F" => if (Reg(7)(7) = '0') then
O_DA <= iob_inreg;
else
O_DA <= reg(15);
end if;
when others => null;
end case;
end if;
end process;
--
p_divider : process
begin
wait until rising_edge(CLK);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(CLK);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(CLK);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(CLK);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process(env_reset, CLK)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
elsif rising_edge(CLK) then
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
begin
tone_ena_l <= '1'; tone_src <= '1';
noise_ena_l <= '1'; chan_vol <= "00000";
case cnt_div(1 downto 0) is
when "00" =>
tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
noise_ena_l <= reg(7)(3);
when "01" =>
tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
noise_ena_l <= reg(7)(4);
when "10" =>
tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
noise_ena_l <= reg(7)(5);
when "11" => null; -- tone gen outputs become valid on this clock
when others => null;
end case;
end process;
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if (ENA = '1') then
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
chan_amp := (others => '0');
if (chan_mixed = '1') then
if (chan_vol(4) = '0') then
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
chan_amp := "00000";
else
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
end if;
else
chan_amp := env_vol(4 downto 0);
end if;
end if;
dac_amp <= x"00";
case chan_amp is
when "11111" => dac_amp <= x"FF";
when "11110" => dac_amp <= x"D9";
when "11101" => dac_amp <= x"BA";
when "11100" => dac_amp <= x"9F";
when "11011" => dac_amp <= x"88";
when "11010" => dac_amp <= x"74";
when "11001" => dac_amp <= x"63";
when "11000" => dac_amp <= x"54";
when "10111" => dac_amp <= x"48";
when "10110" => dac_amp <= x"3D";
when "10101" => dac_amp <= x"34";
when "10100" => dac_amp <= x"2C";
when "10011" => dac_amp <= x"25";
when "10010" => dac_amp <= x"1F";
when "10001" => dac_amp <= x"1A";
when "10000" => dac_amp <= x"16";
when "01111" => dac_amp <= x"13";
when "01110" => dac_amp <= x"10";
when "01101" => dac_amp <= x"0D";
when "01100" => dac_amp <= x"0B";
when "01011" => dac_amp <= x"09";
when "01010" => dac_amp <= x"08";
when "01001" => dac_amp <= x"07";
when "01000" => dac_amp <= x"06";
when "00111" => dac_amp <= x"05";
when "00110" => dac_amp <= x"04";
when "00101" => dac_amp <= x"03";
when "00100" => dac_amp <= x"03";
when "00011" => dac_amp <= x"02";
when "00010" => dac_amp <= x"02";
when "00001" => dac_amp <= x"01";
when "00000" => dac_amp <= x"00";
when others => null;
end case;
if (cnt_div(1 downto 0) = "10") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & dac_amp);
end if;
if (RESET_L = '0') then
O_AUDIO(7 downto 0) <= "00000000";
else
if (audio_final(9) = '0') then
O_AUDIO(7 downto 0) <= audio_final(8 downto 1);
else -- clip
O_AUDIO(7 downto 0) <= x"FF";
end if;
end if;
end if;
end process;
p_io_ports : process(reg)
begin
O_IOA <= reg(14);
O_IOA_OE_L <= not reg(7)(6);
O_IOB <= reg(15);
O_IOB_OE_L <= not reg(7)(7);
end process;
p_io_ports_inreg : process
begin
wait until rising_edge(CLK);
ioa_inreg <= I_IOA;
iob_inreg <= I_IOB;
end process;
end architecture RTL;
| gpl-3.0 | 69b21a0ea615e31738f18f1fc7d727f2 | 0.483076 | 3.296348 | false | false | false | false |
mzakharo/usb-de2-fpga | src/lib/template.vhd | 1 | 1,921 | -- ENTITY_NAME.vhd
-- -----------------------------------------------------------------------
-- brief description
-- -----------------------------------------------------------------------
-- Version : 0.0
-- Date : Jan 1999
-- Author : First Last
-- Web : http://website.com
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- 1. point 1
-- 2. point 2
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ENTITY_NAME_inc is -- component declaration package
type ENTITY_NAME_in_t is record
en : bit;
end record;
type ENTITY_NAME_out_t is record
rdy: bit;
end record;
component ENTITY_NAME is
port(
clk : in std_logic;
reset : in std_logic;
d : in ENTITY_NAME_in_t;
q : out ENTITY_NAME_out_t);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ENTITY_NAME_inc.all;
entity ENTITY_NAME is
port(
clk : in std_logic;
reset : in std_logic;
d : in ENTITY_NAME_in_t;
q : out ENTITY_NAME_out_t);
end ENTITY_NAME;
architecture handler of ENTITY_NAME is
type not_reset_t is record
dummy : bit;
end record;
type state_t is (idle );
type reg_t is record
nr : not_reset_t;
state : state_t;
end record;
signal r, rin : reg_t;
begin --architecture
comb : process(r,d)
variable v : reg_t;
begin
--parameters
v := r;
--algorithm goes here
rin <= v; --return (v);
end process;
seq : process(reset, clk)
begin
if (reset= '1') then
r.state <= idle;
elsif rising_edge(clk) then
r.state <= rin.state;
end if;
end process;
--everything in iface does not need to be reset
seq_nrst : process
begin
wait until rising_edge(clk);
r.nr <= rin.nr;
end process;
end architecture;
| gpl-3.0 | fa64b2b756aa19fdc3b4226a274f19b8 | 0.533576 | 3.128664 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_96x512/simulation/fg_tb_pkg.vhd | 1 | 11,247 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_96x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | c8b55d41383ca426dbade848378c7df8 | 0.50449 | 3.929769 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_64x512/example_design/fifo_fwft_64x512_top.vhd | 1 | 4,968 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_64x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_64x512_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_fwft_64x512_top;
architecture xilinx of fifo_fwft_64x512_top is
SIGNAL clk_i : std_logic;
component fifo_fwft_64x512 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_fwft_64x512 PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 199c798772bc7730bde83cd7e202563f | 0.521739 | 4.880157 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_96x512/example_design/fifo_96x512_top.vhd | 1 | 4,780 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_96x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_96x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_96x512_top;
architecture xilinx of fifo_96x512_top is
SIGNAL clk_i : std_logic;
component fifo_96x512 is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_96x512 PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 5ba02facb00e5bc1d76e8ce92b7ba181 | 0.526778 | 4.907598 | false | false | false | false |
Mafus1/bluetooth-receiver | source/shiftreg.vhd | 1 | 1,479 | -- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY shiftreg IS
PORT(
clk : IN std_logic;
baud_tick : IN std_logic;
ser_data : IN std_logic;
reset_n : IN std_logic;
start_bit : IN std_logic;
wlkng_one : OUT std_logic;
par_data : OUT std_logic_vector(7 downto 0)
);
END shiftreg;
-- Architecture Declaration
ARCHITECTURE rtl OF shiftreg IS
-- Signals & Constants Declaration
SIGNAL data, next_data : std_logic_vector(8 downto 0);
CONSTANT default_data : std_logic_vector(8 downto 0) := "100000000";
-- Begin Architecture
BEGIN
input_logic: PROCESS(data, start_bit, baud_tick, ser_data)
BEGIN
-- write the walking one, followed by zeros, when we receive a start bit
IF start_bit = '1' THEN
next_data <= default_data;
-- shift the serial input to the par output, if we have a baud tick
ELSIF baud_tick = '1' THEN
next_data(7 downto 0) <= data(8 downto 1);
next_data(8) <= ser_data;
-- else, dont touch the flip flops
ELSE
next_data <= data;
END IF;
END PROCESS input_logic;
flip_flops : PROCESS(clk, reset_n)
BEGIN
IF reset_n = '0' THEN
data <= default_data;
ELSIF (rising_edge(clk)) THEN
data <= next_data;
END IF;
END PROCESS flip_flops;
output_logic: PROCESS(data)
BEGIN
par_data <= data(8 downto 1);
wlkng_one <= data(0);
END PROCESS output_logic;
END rtl;
| mit | bd4240624f4d2731631fed8bb21256ed | 0.637102 | 2.989879 | false | false | false | false |
kevintownsend/R3 | coregen/block_ram_64x1024/simulation/bmg_tb_synth.vhd | 1 | 8,375 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_TB IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE BMG_TB_ARCH OF BMG_TB IS
COMPONENT block_ram_64x1024_top
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC;
SIGNAL RESET_SYNC_R2 : STD_LOGIC;
SIGNAL RESET_SYNC_R3 : STD_LOGIC;
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC;
SIGNAL RESETB_SYNC_R2 : STD_LOGIC;
SIGNAL RESETB_SYNC_R3 : STD_LOGIC;
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_buf: bufg
PORT map(
i => CLK_IN,
o => clk_in_i
);
CLKA <= clk_in_i;
clkb_buf: bufg
PORT map(
i => CLKB_IN,
o => clkb_in_i
);
CLKB <= clkb_in_i;
RSTA <= RESET_IN;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESET_IN;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 64 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECK_DATA_TDP(0),
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 64 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECK_DATA_TDP(1),
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
BMG_PORT: block_ram_64x1024_top PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| mit | 3f5634a23d4294bedee5a9da6a0b8f14 | 0.57003 | 3.702476 | false | false | false | false |
RowdyRajan/GestureControlInterfaceCapstone | SerialDe2Code/DE2Component.vhd | 1 | 11,247 | -- Group 2: Gesture Control Interface top level file
-- Eric Smith, Chris Chmilar, Rajan Jassal
-- This file is a modified version of the top level file provided in lab 1
-- Nancy Minderman
-- [email protected]
-- This file makes extensive use of Altera template structures.
-- This file is the top-level file for lab 1 winter 2014 for version 12.1sp1 on Windows 7
-- A library clause declares a name as a library. It
-- does not create the library; it simply forward declares
-- it.
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
use work.DE2_CONSTANTS.all;
entity DE2Component is
port
(
-- Input ports and 50 MHz Clock --
-- Push Buttons
KEY : in std_logic_vector (3 downto 0);
-- Switches
SW : in std_logic_vector (7 downto 0);
-- Clock
CLOCK_50 : in std_logic;
-- Green leds on board --
LEDG : out DE2_LED_GREEN;
--LCD on board
--LCD_BLON : out std_logic;
--LCD_ON : out std_logic;
--LCD_DATA : inout DE2_LCD_DATA_BUS;
--LCD_RS : out std_logic;
--LCD_EN : out std_logic;
--LCD_RW : out std_logic;
--UART interface
UART_TXD : out std_logic; -- UART Transmitter
UART_RXD : in std_logic; -- UART Receiver
--SDRAM on board
--DRAM_ADDR : out std_logic_vector (11 downto 0);
DRAM_ADDR : out DE2_SDRAM_ADDR_BUS;
DRAM_BA_0 : out std_logic;
DRAM_BA_1 : out std_logic;
DRAM_CAS_N : out std_logic;
DRAM_CKE : out std_logic;
DRAM_CLK : out std_logic;
DRAM_CS_N : out std_logic;
--DRAM_DQ : inout std_logic_vector (15 downto 0);
DRAM_DQ : inout DE2_SDRAM_DATA_BUS;
DRAM_LDQM : out std_logic;
DRAM_UDQM : out std_logic;
DRAM_RAS_N : out std_logic;
DRAM_WE_N : out std_logic;
-- SRAM on board
SRAM_ADDR : out DE2_SRAM_ADDR_BUS;
SRAM_DQ : inout DE2_SRAM_DATA_BUS;
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
--Serial port pins made by us
--UART_RXD : in std_LOGIC_VECTOR(7 downto 0);
--UART_TXD : out std_LOGIC_VECTOR(7 downto 0);
-- ISP1362 USB core interface
OTG_DATA : inout std_logic_vector(15 downto 0); -- ISP1362 Data bus 16 Bits
OTG_ADDR : out std_logic_vector(1 downto 0); -- ISP1362 Address 2 Bits
OTG_CS_N : out std_logic; -- ISP1362 Chip Select
OTG_RD_N : out std_logic; -- ISP1362 Write
OTG_WR_N : out std_logic; -- ISP1362 Read
OTG_RST_N : out std_logic; -- ISP1362 Reset
OTG_INT0 : in std_logic; -- ISP1362 Interrupt 0 (for DC)
OTG_INT1 : in std_logic; -- ISP1362 Interrupt 1 (for HC)
OTG_FSPEED : out std_logic; -- USB Full Speed, 0 = Enable, Z = Disable
OTG_LSPEED : out std_logic; -- USB Low Speed, 0 = Enable, Z = Disable
OTG_DREQ0 : in std_logic; -- ISP1362 DMA Request 0
OTG_DREQ1 : in std_logic; -- ISP1362 DMA Request 1
OTG_DACK0_N : out std_logic_vector(0 downto 0) := "Z"; -- ISP1362 DMA Acknowledge 0 (not used)
OTG_DACK1_N : out std_logic_vector(0 downto 0) := "Z" -- ISP1362 DMA Acknowledge 1 (not used)
);
end DE2Component;
architecture structure of DE2Component is
component niosII_system is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
--sdram
sdram_0_wire_addr : out DE2_SDRAM_ADDR_BUS; -- addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_0_wire_cas_n : out std_logic; -- cas_n
sdram_0_wire_cke : out std_logic; -- cke
sdram_0_wire_cs_n : out std_logic; -- cs_n
sdram_0_wire_dq : inout DE2_SDRAM_DATA_BUS := (others => 'X'); -- dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_0_wire_ras_n : out std_logic; -- ras_n
sdram_0_wire_we_n : out std_logic; -- we_n
altpll_0_c0_clk : out std_logic; -- clk
green_leds_external_connection_export : out DE2_LED_GREEN; -- export
switches_external_connection_export : in std_logic := 'X'; -- export
--sram
sram_0_external_interface_DQ : inout DE2_SRAM_DATA_BUS := (others => 'X'); -- DQ
sram_0_external_interface_ADDR : out DE2_SRAM_ADDR_BUS; -- ADDR
sram_0_external_interface_LB_N : out std_logic; -- LB_N
sram_0_external_interface_UB_N : out std_logic; -- UB_N
sram_0_external_interface_CE_N : out std_logic; -- CE_N
sram_0_external_interface_OE_N : out std_logic; -- OE_N
sram_0_external_interface_WE_N : out std_logic; -- WE_N
--Serial port
rs232_0_external_interface_RXD : in std_lOGIC;
rs232_0_external_interface_TXD : out std_LOGIC;
--uart_0_external_connection_rxd : in std_lOGIC;
--uart_0_external_connection_txd : out std_lOGIC;
--ISP1362 Interface
usb_component_0_conduit_DATA : inout std_logic_vector(15 downto 0);
usb_component_0_conduit_ADDR : out std_logic_vector(1 downto 0);
usb_component_0_conduit_CS_N : out std_logic;
usb_component_0_conduit_RD_N : out std_logic;
usb_component_0_conduit_WR_N : out std_logic;
usb_component_0_conduit_RST_N : out std_logic;
usb_component_0_conduit_INT0 : in std_logic;
usb_component_0_conduit_INT1 : in std_logic
--LCD interface
--character_lcd_0_external_interface_DATA : inout DE2_LCD_DATA_BUS := (others => 'X'); -- DATA
--character_lcd_0_external_interface_ON : out std_logic; -- ON
--character_lcd_0_external_interface_BLON : out std_logic; -- BLON
--character_lcd_0_external_interface_EN : out std_logic; -- EN
--character_lcd_0_external_interface_RS : out std_logic; -- RS
--character_lcd_0_external_interface_RW : out std_logic -- RW
);
end component niosII_system;
-- These signals are for matching the provided IP core to
-- The specific SDRAM chip in our system
signal BA : std_logic_vector (1 downto 0);
signal DQM : std_logic_vector (1 downto 0);
begin
--Setting USB Speed config
OTG_FSPEED <= '0';
OTG_LSPEED <= 'Z';
--Memory related signal settings. Appears to be used for combining two signals into a singal interface.
DRAM_BA_1 <= BA(1);
DRAM_BA_0 <= BA(0);
DRAM_UDQM <= DQM(1);
DRAM_LDQM <= DQM(0);
-- Component Instantiation Statement (optional)
u0 : component niosII_system
port map (
clk_clk => CLOCK_50,
reset_reset_n => KEY(0),
sdram_0_wire_addr => DRAM_ADDR,
sdram_0_wire_ba => BA,
sdram_0_wire_cas_n => DRAM_CAS_N,
sdram_0_wire_cke => DRAM_CKE,
sdram_0_wire_cs_n => DRAM_CS_N,
sdram_0_wire_dq => DRAM_DQ,
sdram_0_wire_dqm => DQM,
sdram_0_wire_ras_n => DRAM_RAS_N,
sdram_0_wire_we_n => DRAM_WE_N,
altpll_0_c0_clk => DRAM_CLK,
green_leds_external_connection_export => LEDG,
switches_external_connection_export => SW(0),
sram_0_external_interface_DQ => SRAM_DQ,
sram_0_external_interface_ADDR => SRAM_ADDR,
sram_0_external_interface_LB_N => SRAM_LB_N,
sram_0_external_interface_UB_N => SRAM_UB_N,
sram_0_external_interface_CE_N => SRAM_CE_N,
sram_0_external_interface_OE_N => SRAM_OE_N,
sram_0_external_interface_WE_N => SRAM_WE_N,
--character_lcd_0_external_interface_DATA => LCD_DATA,
--character_lcd_0_external_interface_ON => LCD_ON,
--character_lcd_0_external_interface_BLON => LCD_BLON,
--character_lcd_0_external_interface_EN => LCD_EN,
--character_lcd_0_external_interface_RS => LCD_RS,
--character_lcd_0_external_interface_RW => LCD_RW,
usb_component_0_conduit_DATA => OTG_DATA,
usb_component_0_conduit_ADDR => OTG_ADDR,
usb_component_0_conduit_CS_N => OTG_CS_N,
usb_component_0_conduit_RD_N => OTG_RD_N,
usb_component_0_conduit_WR_N => OTG_WR_N,
usb_component_0_conduit_RST_N => OTG_RST_N,
usb_component_0_conduit_INT0 => OTG_INT0,
usb_component_0_conduit_INT1 => OTG_INT1,
rs232_0_external_interface_RXD => UART_RXD,
rs232_0_external_interface_TXD => UART_TXD
--uart_0_external_connection_txd => UART_TXD,
--uart_0_external_connection_rxd => UART_RXD
);
end structure;
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
end DE2_CONSTANTS;
| gpl-3.0 | 154029969f203a760229071e2e22f371 | 0.511514 | 3.462746 | false | false | false | false |
Mafus1/bluetooth-receiver | source/baud_tick.vhd | 1 | 2,660 | -- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- Entity Declaration
ENTITY baud_tick IS
PORT(
clk : IN std_logic;
baud_tick : OUT std_logic;
reset_n : IN std_logic;
start_bit : in std_logic
);
END baud_tick;
-- Architecture Declaration
ARCHITECTURE rtl OF baud_tick IS
CONSTANT period : unsigned(9 downto 0) := to_unsigned(434, 10);
CONSTANT init_period : unsigned(9 downto 0) := to_unsigned(651, 10);
-- length of a byte (8) for byte countdown
CONSTANT byte_countdown_length : unsigned(3 downto 0) := to_unsigned(8, 4);
-- signals for baud tick period counter
SIGNAL count, next_count : unsigned(9 downto 0);
-- signals for byte counter
SIGNAL byte_countdown : unsigned(3 downto 0);
SIGNAL next_byte_countdown : unsigned(3 downto 0);
-- Begin Architecture
BEGIN
-- input logic for baud tick
input_logic: PROCESS(count, start_bit)
BEGIN
IF start_bit = '1' THEN
next_count <= init_period;
-- decrement
ELSIF count > 0 THEN
next_count <= count - 1 ;
-- start new period
ELSE
next_count <= period;
END IF;
END PROCESS input_logic;
-- baud tick period countdown
baud_flip_flops : PROCESS(clk, reset_n)
BEGIN
IF reset_n = '0' THEN
count <= init_period;
ELSIF rising_edge(clk) THEN
count <= next_count;
END IF;
END PROCESS baud_flip_flops;
-- baud tick output logic
output_logic: PROCESS(count, byte_countdown)
BEGIN
-- send a baud tick, if we reached zero from the counter
-- only send a baud tick, if we didnt count down from 8 ticks yet
IF (count = 0 AND byte_countdown > 0) THEN
baud_tick <= '1';
-- send no baud tick, if we didnt reach the next baud tick yet
ELSE
baud_tick <= '0';
END IF;
END PROCESS output_logic;
-- byte countdown logic
countdown_logic: PROCESS(start_bit, count, byte_countdown)
BEGIN
IF start_bit = '1' THEN
next_byte_countdown <= byte_countdown_length;
-- decrement
ELSIF (count = 0 AND byte_countdown > 0) THEN
next_byte_countdown <= byte_countdown - 1;
-- freeze
ELSIF (count = 0 AND byte_countdown = 0) THEN
next_byte_countdown <= to_unsigned(0, 4);
-- else dont touch the flip flops
ELSE
next_byte_countdown <= byte_countdown;
END IF;
END PROCESS countdown_logic;
-- byte countdown flip flops
countdown_flop_flops: PROCESS(clk, count, reset_n)
BEGIN
IF reset_n = '0' THEN
byte_countdown <= to_unsigned(0, 4);
ELSIF rising_edge(clk) THEN
byte_countdown <= next_byte_countdown;
END IF;
END PROCESS countdown_flop_flops;
END rtl;
| mit | d48b1414f890b25d32fd5a6842341e3a | 0.658894 | 3.13192 | false | false | false | false |
e8johan/jamcpu | mau.vhd | 1 | 2,822 | ---------------------------------------------------------
-- JAM CPU
-- Memory access unit
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
-- Note: we could use the inverted CLK signal as DM_WRITE to avoid
-- two cycle write
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
Entity mau is
port (
---- Signalas from/to CPU/CONTROLL ----------------------------
CLK: in std_logic;
CTRL_R: in std_logic; -- Read Mem
CTRL_W: in std_logic; -- Write Mem
RESET: in std_logic;
STALL: out std_logic; -- Used to stall one cycle on write
IN_ADDR: in std_logic_vector(31 downto 0); -- Adress Buss from CPU
IN_DATA: in std_logic_vector(31 downto 0); -- Data Buss from CPU
OUT_DATA: out std_logic_vector(31 downto 0); -- Data Buss to CPU
---------------------------------------------------------------
---- Signals from/to MEM---------------------------------------
DM_CS: out std_logic_vector(7 downto 0); -- Chip Select Low-active.
DM_OE: out std_logic; -- Output Enable Low-active.
DM_WRITE: out std_logic; -- Write Data, Mem (data -> HighZ). Low-active.
DM_ADDR: out std_logic_vector(16 downto 0); -- Address Buss to mem
DM_DATA: inout std_logic_vector(63 downto 0) -- Mem Data Buss (Bidirectional)
---------------------------------------------------------------
);
end;
Architecture behav of mau is
signal intern_stall: std_logic;
signal GO: std_logic;
begin
DM_DATA <=
(Others => 'Z') when intern_stall = '0' else
"--------------------------------" & IN_DATA when IN_ADDR(0) = '0' else
IN_DATA & "--------------------------------";
DM_OE <= '0';
DM_CS <=
(Others => '0') when CTRL_W = '0' else
"11110000" when IN_ADDR(0) = '0' else
"00001111";
DM_ADDR <= IN_ADDR(17 downto 1);
intern_stall <=
'1' when ( (CTRL_W = '1') and (GO = '0') ) else
'0';
STALL <= intern_stall;
OUT_DATA <=
(Others => '-') when CTRL_R = '0' else
DM_DATA(31 downto 0) when (IN_ADDR(0) = '0') else
DM_DATA(63 downto 32);
DM_WRITE <= not intern_stall;
process(CLK)
begin
if CLK'event and CLK = '1' then
if intern_stall = '1' then
GO <= '1';
else
GO <= '0';
end if;
if RESET = '1' then
GO <= '0';
end if;
end if;
end process;
end;
| lgpl-2.1 | 25448117a8c2f9589ad5a87e56242c73 | 0.509568 | 3.412334 | false | false | false | false |
capitanov/MinesweeperFPGA | src/game_cores/ctrl_game_block.vhd | 1 | 9,564 | --------------------------------------------------------------------------------
--
-- Title : ctrl_game_block.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Main game block for minesweeper
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.key_data;
use work.ctrl_types_pkg.data8x8;
use work.ctrl_types_pkg.data3x8;
use work.ctrl_types_pkg.array8x8;
use work.ctrl_comp_pkg.all;
entity ctrl_game_block is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- keyboard:
push_keys : in key_data;
-- vga XoY coordinates:
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0);
leds : out std_logic_vector(8 downto 1)
);
end ctrl_game_block;
architecture ctrl_game_block of ctrl_game_block is
function conv8x8to64 (data_in : array8x8) return std_logic_vector is
variable vector64 : std_logic_vector(63 downto 0);
begin
x_loop8: for jj in 0 to 7 loop
y_loop8 :for ii in 0 to 7 loop
vector64(ii+jj*8) := data_in(jj)(ii);
end loop;
end loop;
return vector64;
end conv8x8to64;
component ctrl_8x16_rom is
port(
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end component;
type game_fsm is (WAIT_START, PLAY, CHECK, GAME_OVER, RST);
signal game_status : game_fsm;
signal addr_rnd : std_logic_vector(4 downto 0):="00000";
signal show_field, show_bad_msg, display_text: std_logic;
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal x_inz : std_logic_vector(6 downto 0);
signal x_inzz : std_logic_vector(6 downto 0);
signal y_inz : std_logic_vector(4 downto 0);
signal y_inzz : std_logic_vector(4 downto 0);
signal cnt_yy : std_logic_vector(2 downto 0);
signal cnt_xx : std_logic_vector(2 downto 0);
signal comp_yy : std_logic_vector(6 downto 0);
signal comp_xx : std_logic_vector(4 downto 0);
signal rgb1 : std_logic_vector(2 downto 0):="000";
signal rgb2 : std_logic_vector(2 downto 0):="000";
signal rgb3 : std_logic_vector(2 downto 0):="000";
signal rgb4 : std_logic_vector(2 downto 0):="000";
signal rgb5 : std_logic_vector(2 downto 0):="000";
signal kw, ks, ka, kd : std_logic;
signal kenter : std_logic;
signal kspace : std_logic;
signal ky, kn : std_logic;
signal kesc : std_logic;
signal data_box : std_logic_vector(7 downto 0);
signal cnt_mines : std_logic_vector(6 downto 0);
signal show_disp : array8x8;
signal show_dispz : std_logic_vector(63 downto 0);
signal win, lose, game : std_logic;
signal cntg : std_logic;
signal cnt_flash : std_logic_vector(23 downto 0);
begin
---------------- SUMMARY RGB ON DISPLAY ----------------
rgb <= rgb1 or rgb2 or rgb3 or rgb4 or rgb5;
---------------- KEYBOARD ----------------
kw <= push_keys.WSAD(3) after 1 ns when rising_edge(clk);
ks <= push_keys.WSAD(2) after 1 ns when rising_edge(clk);
ka <= push_keys.WSAD(0) after 1 ns when rising_edge(clk);
kd <= push_keys.WSAD(1) after 1 ns when rising_edge(clk);
ky <= push_keys.ky after 1 ns when rising_edge(clk);
kn <= push_keys.kn after 1 ns when rising_edge(clk);
kspace <= push_keys.Space after 1 ns when rising_edge(clk);
kenter <= push_keys.Enter after 1 ns when rising_edge(clk);
kesc <= push_keys.Esc after 1 ns when rising_edge(clk);
---------------- LEDS ON DISPLAY ----------------
leds(1) <= kenter;
leds(2) <= kw or ks or ka or kd;
leds(3) <= ky or kn;
leds(4) <= show_field;
leds(5) <= display;
leds(6) <= cnt_flash(23);
---------------- MOVING COUNTERS ----------------
pr_start: process(reset, clk) is
begin
if reset = '0' then
cnt_xx <= "000";
cnt_yy <= "000";
elsif rising_edge(clk) then
case game_status is
when PLAY =>
if kw = '1' then
cnt_yy <= cnt_yy - 1;
elsif ks = '1' then
cnt_yy <= cnt_yy + 1;
else
null;
end if;
if ka = '1' then
cnt_xx <= cnt_xx + 1;
elsif kd = '1' then
cnt_xx <= cnt_xx - 1;
else
null;
end if;
when RST | GAME_OVER | WAIT_START =>
cnt_xx <= "000";
cnt_yy <= "000";
when others =>
null;
end case;
end if;
end process;
comp_yy <= "0000" & cnt_yy;
comp_xx <= "00" & cnt_xx;
---------------- XoY COORDINATES ----------------
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
x_inz <= x_in after 1 ns when rising_edge(clk);
y_inz <= y_in after 1 ns when rising_edge(clk);
x_inzz <= x_inz after 1 ns when rising_edge(clk);
y_inzz <= y_inz after 1 ns when rising_edge(clk);
---------------- GLOABAL FSM ----------------
pr_game_status: process(clk, reset) is
begin
if reset = '0' then
game_status <= WAIT_START;
show_field <= '0';
show_bad_msg <= '0';
addr_rnd <= (others => '0');
display_text <= '0';
win <= '0';
lose <= '0';
game <= '0';
cntg <= '0';
cnt_flash <= (others => '0');
elsif rising_edge(clk) then
case game_status is
when WAIT_START =>
display_text <= '1';
show_bad_msg <= '0';
win <= '0';
game <= '0';
lose <= '0';
cntg <= '0';
addr_rnd <= addr_rnd + '1'; -- UNCOMMENT LATER!!
if kspace = '1' then
game_status <= PLAY;
show_field <= '1';
end if;
when PLAY =>
cntg <= '1';
if kesc = '1' then
game_status <= WAIT_START;
else
if cnt_mines = "111000" then
show_bad_msg <= '0';
game_status <= GAME_OVER;
else
if kenter = '1' then
game_status <= CHECK;
else
null;
end if;
end if;
end if;
when CHECK =>
if (x_inzz = (xstart + comp_xx)) and (y_inzz = (ystart + comp_yy)) then
if data_box = x"0F" then
show_bad_msg <= '1';
game_status <= GAME_OVER;
else
game_status <= PLAY;
end if;
end if;
when GAME_OVER =>
cnt_flash <= cnt_flash + '1';
if show_bad_msg = '1' then
win <= '0';
lose <= '1';
else
win <= '1';
lose <= '0';
end if;
game <= '1';
if ky = '1' then
game_status <= WAIT_START;
elsif kn = '1' then
game_status <= RST;
else
null;
end if;
when RST =>
cntg <= '0';
game <= '0';
win <= '0';
lose <= '0';
show_field <= '0';
display_text <= '0';
show_bad_msg <= '0';
cnt_flash <= (others => '0');
addr_rnd <= (others => '0');
when others => null;
end case;
end if;
end process;
pr_display8x8: process(clk, reset) is
begin
if reset = '0' then
show_disp <= (others=>(others=>'0'));
cnt_mines <= (others => '0');
show_dispz <= (others => '0');
elsif rising_edge(clk) then
case game_status is
when PLAY =>
if kenter = '1' then
show_disp(conv_integer(cnt_xx))(conv_integer(cnt_yy)) <= '1';
else
null;
end if;
-- x_loop: for ii in 0 to 62 loop
-- show_dispz(ii+1) <= show_dispz(ii);
-- end loop;
-- show_dispz(0) <= '0';
show_dispz(63 downto 0) <= show_dispz(62 downto 0) & '0';
if show_dispz(63) = '1' then
cnt_mines <= cnt_mines + '1';
else
null;
end if;
when CHECK =>
show_dispz <= conv8x8to64(show_disp);
cnt_mines <= (others => '0');
when RST | GAME_OVER | WAIT_START =>
show_dispz <= (others => '0');
show_disp <= (others=>(others=>'0'));
cnt_mines <= (others => '0');
when others =>
null;
end case;
end if;
end process;
---------------- COMPONENTS MAPPING ----------------
x_check: cl_check
generic map(
yend => yend,
ystart => ystart,
xend => xend,
xstart => xstart
)
port map(
clk => clk,
reset => reset,
cnt_yy => cnt_yy,
cnt_xx => cnt_xx,
display => show_field,
x_char => x_char,
y_char => y_char,
rgb => rgb1
);
x_mines: cl_mines
generic map(
yend => yend,
ystart => ystart,
xend => xend,
xstart => xstart
)
port map(
clk => clk,
reset => reset,
addr_rnd => addr_rnd,
show_disp => show_disp,
display => show_field,
x_char => x_char,
y_char => y_char,
data_out => data_box,
rgb => rgb2
);
x_square: cl_square
generic map(
yend => yend,
ystart => ystart,
xend => xend,
xstart => xstart
)
port map(
clk => clk,
reset => reset,
show_disp => show_disp,
display => show_field,
x_char => x_char,
y_char => y_char,
rgb => rgb3
);
x_borders: cl_borders
generic map(
yend => yend,
ystart => ystart,
xend => xend,
xstart => xstart
)
port map(
clk => clk,
reset => reset,
display => show_field,
x_char => x_char,
y_char => y_char,
rgb => rgb4
);
x_text: cl_text
port map(
clk => clk,
reset => reset,
addr_rnd => addr_rnd,
display => display_text,
cntgames => cntg,
win => win,
lose => lose,
game => game,
flash => cnt_flash(23 downto 21),
x_char => x_char,
y_char => y_char,
rgb => rgb5
);
end ctrl_game_block; | mit | 05df5ead3bdaaec135f771338af065dd | 0.552488 | 2.626751 | false | false | false | false |
laurivosandi/vhdl-exercise | alu_testbench.vhd | 1 | 6,446 | use work.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu_testbench is
end;
architecture behavioral of alu_testbench is
signal a, b, q : std_logic_vector(3 downto 0);
signal ctrl : std_logic_vector (1 DOWNTO 0);
signal cout, cin : std_logic := '0';
component alu
port (
n : in std_logic_vector (3 downto 0);
m : in std_logic_vector (3 downto 0);
opcode : in std_logic_vector ( 1 downto 0);
cout : out std_logic;
d : out std_logic_vector (3 downto 0));
end component;
function to_std_logicvector(a: integer; length: natural) return std_logic_vector IS
begin
return std_logic_vector(to_signed(a,length));
end;
procedure behave_alu(a: integer; b: integer; ctrl: integer; q: out std_logic_vector(3 downto 0); cout: out std_logic) is
variable ret: std_logic_vector(4 downto 0);
begin
case ctrl is
when 0 => ret := std_logic_vector(to_signed(a+b, 5));
when 1 => ret := std_logic_vector(to_signed(a-b, 5));
when 2 => ret := '0' & (std_logic_vector(to_signed(a,4))) nand std_logic_vector(to_signed(b,4));
when 3 => ret := '0' & (std_logic_vector(to_signed(a,4))) nor std_logic_vector(to_signed(b,4));
when others =>
assert false
report "ctrl out of range, testbench error"
severity error;
end case;
q := ret(3 downto 0);
cout := ret(4);
end;
begin process
variable res: std_logic_vector ( 3 downto 0);
variable c: std_logic;
begin
ctrl <= "00";
for i in 0 to 7 loop
a <= std_logic_vector(to_signed(i,4));
for j in 0 to 7-i loop
b <= std_logic_vector(to_signed(j,4));
wait for 10 ns;
behave_alu(i,j,0,res,c);
--assert "0" & q = "1" & res
assert q = res
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=add" &
" wrong result from ALU:" & integer'image(to_integer(signed(q))) &
" expected:" & integer'image(to_integer(signed(res)))
severity warning;
assert cout = c
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=add" &
" wrong carry from ALU:" & std_logic'image(cout) &
" expected:" & std_logic'image(c)
severity warning;
end loop;
end loop;
report "Finished testing addition operation of ALU";
ctrl <= "01";
for i in 0 to 7 loop
a <= std_logic_vector(to_signed(i,4));
for j in 0 to 7 loop
b <= std_logic_vector(to_signed(j,4));
wait for 10 ns;
behave_alu(i,j,1,res,c);
--assert "0" & q = "1" & res
assert q = res
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=sub" &
" wrong result from ALU:" & integer'image(to_integer(signed(q))) &
" expected:" & integer'image(to_integer(signed(res)))
severity warning;
assert cout = c
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=sub" &
" wrong carry from ALU:" & std_logic'image(cout) &
" expected:" & std_logic'image(c)
severity warning;
end loop;
end loop;
report "Finished testing subtraction operation of ALU";
ctrl <= "10";
for i in 0 to 7 loop
a <= std_logic_vector(to_signed(i,4));
for j in 0 to 7 loop
b <= std_logic_vector(to_signed(j,4));
wait for 10 ns;
assert (a nand b) = q
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=nand " &
" wrong result from ALU:" & integer'image(to_integer(signed(q))) &
" expected:" & integer'image(to_integer(signed(a nand b)))
severity warning;
assert cout = '0'
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=nand" &
" wrong carry from ALU:" & std_logic'image(cout) &
" expected: 0"
severity warning;
end loop;
end loop;
report "Finished testing NAND operation of ALU";
ctrl <= "11";
for i in 0 to 7 loop
a <= std_logic_vector(to_unsigned(i,4));
for j in 0 to 7 loop
b <= std_logic_vector(to_unsigned(j,4));
wait for 10 ns;
assert (a nor b) = q
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=nor " &
" wrong result from ALU:" & integer'image(to_integer(signed(q))) &
" expected:" & integer'image(to_integer(signed(a nor b)))
severity warning;
assert cout = '0'
report
" n=" & integer'image(to_integer(signed(a))) &
" m=" & integer'image(to_integer(signed(b))) &
" opcode=nor" &
" wrong carry from ALU:" & std_logic'image(cout) &
" expected: 0"
severity warning;
end loop;
end loop;
report "Finished testing NOR operation of ALU";
wait;
end process;
uut: alu port map (a, b, ctrl, cout, q);
end behavioral;
| mit | 547e428f905ffc6e9789e295af9aab2f | 0.466025 | 4.02121 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/busA.vhd | 2 | 673 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
---SI=[MDR,GR,ADDRESS]
entity busA is
port(
clock: in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(15 downto 0);
ADDR : in std_logic_vector( 7 downto 0);
SI : in std_logic_vector( 2 downto 0);
busA_out : out std_logic_vector(15 downto 0)
);
end busA;
---architecture
architecture BEHAVIOR of busA is
begin
busA_out <= MDR when SI = "001"
else GR when SI = "010"
else "00000000" & ADDR when SI = "100"
else "XXXXXXXXXXXXXXXX";
end BEHAVIOR;
| mit | b8fe792446f8cb4ba531bcf81bd7ba93 | 0.576523 | 3.38191 | false | false | false | false |
Mafus1/bluetooth-receiver | source/hex2sevseg.vhd | 1 | 2,680 | -------------------------------------------
-- Block code: <filename>.vhd
-- History: 24.Sep.2013 - 1st version (dqtm)
-- <date> - <changes> (<author>)
-- Function: Hexa to seven-seg converter
-- plain functionality
-- implemented with comb logic outside process
-------------------------------------------
-- Library & Use Statements
LIBRARY ieee;
use ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY hex2sevseg IS
PORT(
hexa_i : IN std_logic_vector(3 downto 0);
seg_o : OUT std_logic_vector(6 downto 0)); -- Sequence is "gfedcba" (MSB is seg_g)
END hex2sevseg ;
-- Architecture Declaration
ARCHITECTURE rtl OF hex2sevseg IS
-- Signals & Constants Declaration
CONSTANT display_0 : std_logic_vector(6 downto 0):= "0111111";
CONSTANT display_1 : std_logic_vector(6 downto 0):= "0000110";
CONSTANT display_2 : std_logic_vector(6 downto 0):= "1011011";
CONSTANT display_3 : std_logic_vector(6 downto 0):= "1001111";
CONSTANT display_4 : std_logic_vector(6 downto 0):= "1100110";
CONSTANT display_5 : std_logic_vector(6 downto 0):= "1101101";
CONSTANT display_6 : std_logic_vector(6 downto 0):= "1111101";
CONSTANT display_7 : std_logic_vector(6 downto 0):= "0000111";
CONSTANT display_8 : std_logic_vector(6 downto 0):= "1111111";
CONSTANT display_9 : std_logic_vector(6 downto 0):= "1101111";
CONSTANT display_A : std_logic_vector(6 downto 0):= "1110111";
CONSTANT display_B : std_logic_vector(6 downto 0):= "1111100";
CONSTANT display_C : std_logic_vector(6 downto 0):= "0111001";
CONSTANT display_D : std_logic_vector(6 downto 0):= "1011110";
CONSTANT display_E : std_logic_vector(6 downto 0):= "1111001";
CONSTANT display_F : std_logic_vector(6 downto 0):= "1110001";
CONSTANT display_blank : std_logic_vector(6 downto 0):= (others =>'0');
-- Begin Architecture
BEGIN
-------------------------------------------
-- Concurrent Assignments
-------------------------------------------
-- Implementation option: concurrent comb logic with with/select/when
WITH hexa_i SELECT
seg_o <= NOT(display_0) WHEN x"0",
NOT(display_1) WHEN x"1",
NOT(display_2) WHEN x"2",
NOT(display_3) WHEN x"3",
NOT(display_4) WHEN x"4",
NOT(display_5) WHEN x"5",
NOT(display_6) WHEN x"6",
NOT(display_7) WHEN x"7",
NOT(display_8) WHEN x"8",
NOT(display_9) WHEN x"9",
NOT(display_A) WHEN x"A",
NOT(display_B) WHEN x"B",
NOT(display_C) WHEN x"C",
NOT(display_D) WHEN x"D",
NOT(display_E) WHEN x"E",
NOT(display_F) WHEN x"F",
NOT(display_blank) WHEN OTHERS;
END rtl;
| mit | cf90e7b820a9bbc075636fd2c5c7c769 | 0.602315 | 3.199522 | false | false | false | false |
capitanov/MinesweeperFPGA | src/keyboard/ps2_keyboard.vhd | 2 | 5,116 | --------------------------------------------------------------------------------
--
-- FileName: ps2_keyboard.vhd
-- Dependencies: debounce.vhd
-- Design Software: Quartus II 32-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/25/2013 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ps2_keyboard IS
GENERIC(
clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
debounce_counter_size : INTEGER := 8); --set such that (2^size)/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock
ps2_clk : IN STD_LOGIC; --clock signal from PS/2 keyboard
ps2_data : IN STD_LOGIC; --data signal from PS/2 keyboard
ps2_code_new : OUT STD_LOGIC; --flag that new PS/2 code is available on ps2_code bus
ps2_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --code received from PS/2
END ps2_keyboard;
ARCHITECTURE logic OF ps2_keyboard IS
SIGNAL sync_ffs : STD_LOGIC_VECTOR(1 DOWNTO 0); --synchronizer flip-flops for PS/2 signals
SIGNAL ps2_clk_int : STD_LOGIC; --debounced clock signal from PS/2 keyboard
SIGNAL ps2_data_int : STD_LOGIC; --debounced data signal from PS/2 keyboard
SIGNAL ps2_word : STD_LOGIC_VECTOR(10 DOWNTO 0); --stores the ps2 data word
SIGNAL error : STD_LOGIC; --validate parity, start, and stop bits
SIGNAL count_idle : INTEGER RANGE 0 TO clk_freq/18_000; --counter to determine PS/2 is idle
--declare debounce component for debouncing PS2 input signals
COMPONENT debounce IS
GENERIC(
counter_size : INTEGER); --debounce period (in seconds) = 2^counter_size/(clk freq in Hz)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END COMPONENT;
BEGIN
--synchronizer flip-flops
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
sync_ffs(0) <= ps2_clk; --synchronize PS/2 clock signal
sync_ffs(1) <= ps2_data; --synchronize PS/2 data signal
END IF;
END PROCESS;
--debounce PS2 input signals
debounce_ps2_clk: debounce
GENERIC MAP(counter_size => debounce_counter_size)
PORT MAP(clk => clk, button => sync_ffs(0), result => ps2_clk_int);
debounce_ps2_data: debounce
GENERIC MAP(counter_size => debounce_counter_size)
PORT MAP(clk => clk, button => sync_ffs(1), result => ps2_data_int);
--input PS2 data
PROCESS(ps2_clk_int)
BEGIN
IF(ps2_clk_int'EVENT AND ps2_clk_int = '0') THEN --falling edge of PS2 clock
ps2_word <= ps2_data_int & ps2_word(10 DOWNTO 1); --shift in PS2 data bit
END IF;
END PROCESS;
--verify that parity, start, and stop bits are all correct
error <= NOT (NOT ps2_word(0) AND ps2_word(10) AND (ps2_word(9) XOR ps2_word(8) XOR
ps2_word(7) XOR ps2_word(6) XOR ps2_word(5) XOR ps2_word(4) XOR ps2_word(3) XOR
ps2_word(2) XOR ps2_word(1)));
--determine if PS2 port is idle (i.e. last transaction is finished) and output result
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
IF(ps2_clk_int = '0') THEN --low PS2 clock, PS/2 is active
count_idle <= 0; --reset idle counter
ELSIF(count_idle /= clk_freq/18_000) THEN --PS2 clock has been high less than a half clock period (<55us)
count_idle <= count_idle + 1; --continue counting
END IF;
IF(count_idle = clk_freq/18_000 AND error = '0') THEN --idle threshold reached and no errors detected
ps2_code_new <= '1'; --set flag that new PS/2 code is available
ps2_code <= ps2_word(8 DOWNTO 1); --output new PS/2 code
ELSE --PS/2 port active or error detected
ps2_code_new <= '0'; --set flag that PS/2 transaction is in progress
END IF;
END IF;
END PROCESS;
END logic;
| mit | 5f0e253d308d436d519a1d35feb41c47 | 0.589719 | 3.837959 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512/example_design/fifo_64x512_top_wrapper.vhd | 1 | 18,992 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_64x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_64x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(64-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(64-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_64x512_top_wrapper;
architecture xilinx of fifo_64x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_64x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_64x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 14e6da503857a5c35a822b0718fd1dea | 0.48631 | 3.964099 | false | false | false | false |
fabianschuiki/moore | test/vhdl/choices.vhd | 1 | 343 | entity foo is end;
architecture bar of foo is
type BIT is ('0', '1');
procedure prok is begin
case 0 is
-- expression
when 1 => null;
when not 3 => null;
-- discrete range
when 0 to 4 => wait;
when bit => wait;
-- element name
when asdf => null;
-- others
when others => null;
end case;
end;
begin end;
| apache-2.0 | faea1faf7ce030ee2e1da11ab6714602 | 0.588921 | 3.09009 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_32x512/example_design/fifo_32x512_top_wrapper.vhd | 1 | 18,991 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_32x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_32x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(32-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(32-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_32x512_top_wrapper;
architecture xilinx of fifo_32x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_32x512_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_32x512_top
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 93ee0d9445042a76ee6dcd4728158ef2 | 0.486178 | 3.963891 | false | false | false | false |
fabianschuiki/moore | test/vhdl/aggregates.vhd | 1 | 499 | entity foo is end;
architecture bar of foo is
type BIT is ('0', '1');
type COMP is record
a : BIT;
b : BIT;
end record;
procedure prok is begin
-- name
X := '0';
-- positional array aggregate
(X,Y) := "00";
-- named array aggregate
(1 => X, 0 => Y) := "00";
-- mixed array aggregate
(X, 1 => Y) := "00";
-- positional record aggregate
(X,Y) := Z;
-- named record aggregate
(a => X, b => Y) := Z;
-- mixed record aggregate
(X, b => Y) := Z;
end;
begin end;
| apache-2.0 | dd831c52b9a443e093456875357b4dcd | 0.543086 | 2.726776 | false | false | false | false |
znuh/open-nexys | fx2_fifo_test/bscan_sreg.vhd | 3 | 1,799 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bscan_sreg is
GENERIC (
SREG_LEN : integer := 8
);
Port (
CAPTURE_i : in std_logic;
DRCK_i : in std_logic;
SEL_i : in std_logic;
SHIFT_i : in std_logic;
UPDATE_i : in std_logic;
TDI_i : in std_logic;
TDO_o: out std_logic;
clk_i : in std_logic;
Data_i : in std_logic_vector((SREG_LEN - 1) downto 0);
Data_o : out std_logic_vector((SREG_LEN - 1) downto 0);
strobe_o : out std_logic
);
end bscan_sreg;
architecture Behavioral of bscan_sreg is
signal SREG: std_logic_vector((SREG_LEN - 1) downto 0);
signal UPDATE_s1 : std_logic := '0';
signal UPDATE_s2 : std_logic := '0';
signal UPDATE_s3 : std_logic := '0';
signal SEL_s1 : std_logic := '0';
signal SEL_s2 : std_logic := '0';
begin
process(clk_i)
begin
if rising_edge(clk_i) then
strobe_o <= '0';
-- synchronize
UPDATE_s1 <= UPDATE_i;
UPDATE_s2 <= UPDATE_s1;
UPDATE_s3 <= UPDATE_s2;
SEL_s1 <= SEL_i;
SEL_s2 <= SEL_s1;
-- detect a rising edge on UPDATE
if UPDATE_s2 = '1' and UPDATE_s3 = '0' and SEL_s2 = '1' then
Data_o <= SREG;
strobe_o <= '1';
end if;
end if;
end process;
-------------------------------
process(DRCK_i, CAPTURE_i, SEL_i)
begin
TDO_o <= SREG(SREG_LEN - 1);
if SEL_i = '1' then
if CAPTURE_i = '1' then
SREG <= Data_i;
elsif rising_edge(DRCK_i) then
if SHIFT_i = '1' and UPDATE_i /= '1' then
SREG <= SREG((SREG_LEN - 2) downto 0) & TDI_i;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | ddea73fd2f870cb13f8b9fa7c86d295a | 0.594775 | 2.701201 | false | false | false | false |
znuh/open-nexys | fx2_usb/top.vhd | 1 | 3,552 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port (
sys_clk : in std_logic;
Led: out std_logic_vector(7 downto 0);
sw: in std_logic_vector(7 downto 0);
fx2_wr_full_i : in std_logic;
fx2_rd_empty_i : in std_logic;
fx2_data_io : inout std_logic_vector(7 downto 0);
fx2_clk_i : in std_logic;
fx2_slcs_o : out std_logic;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slwr_o : out std_logic;
fx2_pktend_o : out std_logic;
fx2_fifo_addr_o : out std_logic_vector(1 downto 0);
btn : in std_logic_vector(3 downto 0);
JA : in std_logic_vector(4 downto 1);
JB : in std_logic_vector(4 downto 1);
JC : out std_logic_vector(4 downto 1);
JD : out std_logic_vector(4 downto 1)
);
end top;
architecture Behavioral of top is
component fx2_usb is
Port (
clk_i : in std_logic;
rst_i : in std_logic;
fx2_wr_full_i : in std_logic;
fx2_rd_empty_i : in std_logic;
fx2_data_io : inout std_logic_vector(7 downto 0);
fx2_clk_i : in std_logic;
fx2_slcs_o : out std_logic;
fx2_slrd_o : out std_logic;
fx2_sloe_o : out std_logic;
fx2_slwr_o : out std_logic;
fx2_pktend_o : out std_logic;
fx2_fifo_addr_o : out std_logic_vector(1 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
wr_full : out std_logic;
rd_empty : out std_logic;
pktend_i : in std_logic;
sync : out std_logic
);
end component;
COMPONENT mydcm
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
CLK2X_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
signal clk_int : std_logic;
signal rst : std_logic;
signal usb_pktend : std_logic;
signal usb_din, usb_dout : std_logic_vector(7 downto 0);
signal usb_wr_en, usb_rd_en : std_logic;
signal usb_wr_full, usb_rd_empty : std_logic;
signal sync : std_logic;
begin
JC <= x"0";
JD <= x"0";
rst <= btn(0);
usb_pktend <= btn(1);
Led(7 downto 1) <= usb_wr_en & usb_rd_en & usb_wr_full & usb_rd_empty & "000";
Led(0) <= not sync;
-------- reply code---------
usb_din <= usb_dout;
process(clk_int)
begin
if rising_edge(clk_int) then
usb_rd_en <= '0';
usb_wr_en <= '0';
------------ reply code -------------
if usb_rd_empty = '0' and usb_wr_full = '0' and usb_wr_en = '0' and usb_rd_en = '0' then
usb_rd_en <= '1';
end if;
if usb_rd_en = '1' then
usb_wr_en <= '1';
end if;
----------- counter code -----------
-- if usb_wr_full = '0' and usb_wr_en = '0' then
-- usb_wr_en <= '1';
-- end if;
-- if usb_wr_en = '1' then
-- usb_din <= usb_din + 1;
-- end if;
end if;
end process;
Inst_mydcm: mydcm PORT MAP(
CLKIN_IN => sys_clk,
RST_IN => btn(0),
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
CLK2X_OUT => clk_int,
LOCKED_OUT => open
);
Inst_fx2_usb : fx2_usb PORT MAP(
clk_i => clk_int,
rst_i => rst,
fx2_wr_full_i => fx2_wr_full_i,
fx2_rd_empty_i => fx2_rd_empty_i,
fx2_data_io => fx2_data_io,
fx2_clk_i => fx2_clk_i,
fx2_slcs_o => fx2_slcs_o,
fx2_slrd_o => fx2_slrd_o,
fx2_sloe_o => fx2_sloe_o,
fx2_slwr_o => fx2_slwr_o,
fx2_pktend_o => fx2_pktend_o,
fx2_fifo_addr_o => fx2_fifo_addr_o,
din => usb_din,
dout => usb_dout,
wr_en => usb_wr_en,
rd_en => usb_rd_en,
wr_full => usb_wr_full,
rd_empty => usb_rd_empty,
pktend_i => usb_pktend,
sync => sync
);
end Behavioral;
| gpl-2.0 | b4b1c16ea0c8d9ccd2e20da44bb182d8 | 0.598255 | 2.343008 | false | false | false | false |
Mafus1/bluetooth-receiver | source/edge_detect.vhd | 1 | 1,401 | -- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY edge_detect IS
PORT(
clk : IN std_logic;
data_in : IN std_logic;
reset_n : IN std_logic;
rise : OUT std_logic;
fall : OUT std_logic
);
END edge_detect;
-- Architecture Declaration
ARCHITECTURE rtl OF edge_detect IS
-- Signals & Constants Declaration
SIGNAL q1: std_logic;
SIGNAL q2: std_logic;
-- Begin Architecture
BEGIN
-------------------------------------------
-- Process for combinatorial logic
-------------------------------------------
-- not needed in this file, using concurrent logic
-------------------------------------------
-- Process for registers (flip-flops)
-------------------------------------------
flip_flops : PROCESS(clk, reset_n)
BEGIN
IF reset_n = '0' THEN
q1 <= '0';
q2 <= '0';
ELSIF (rising_edge(clk)) THEN
q1 <= data_in;
q2 <= q1;
END IF;
END PROCESS flip_flops;
-------------------------------------------
-- Concurrent Assignments
-------------------------------------------
edge_detector_logic: PROCESS(q1, q2)
BEGIN
-- Default for rise und fall
rise <= '0';
fall <= '0';
IF q1 = '1' AND q2 = '0' THEN
rise <= '1';
ELSIF q1 = '0' AND q2 = '1' THEN
fall <= '1';
END IF;
END PROCESS edge_detector_logic;
END rtl;
| mit | 99fb95c853fe7c620df0c4fcedace023 | 0.486776 | 3.568878 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_69x512/simulation/fg_tb_pkg.vhd | 1 | 11,247 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_69x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 2a065981e00c20eb60dc98a2ae1b830d | 0.50449 | 3.929769 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512/example_design/fifo_64x512_top.vhd | 1 | 4,780 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_64x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_64x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_64x512_top;
architecture xilinx of fifo_64x512_top is
SIGNAL clk_i : std_logic;
component fifo_64x512 is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_64x512 PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | caff1decc4bf304f210377f1b9bb13ec | 0.526778 | 4.907598 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/gr_32.vhd | 1 | 3,706 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gr is
port(clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(31 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(31 downto 0);
GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : out std_logic_vector(31 downto 0));
end gr;
architecture BEHAVIOR of gr is
signal S_GR0_F, S_GR1_F, S_GR2_F, S_GR3_F, S_GR4_F, S_GR5_F, S_GR6_F, S_GR7_F,
S_GR8_F, S_GR9_F, S_GR10_F, S_GR11_F, S_GR12_F, S_GR13_F, S_GR14_F, S_GR15_F
: std_logic_vector(31 downto 0);
begin
GR0_View <= S_GR0_F; GR1_View <= S_GR1_F; GR2_View <= S_GR2_F; GR3_View <= S_GR3_F;
GR4_View <= S_GR4_F; GR5_View <= S_GR5_F; GR6_View <= S_GR6_F; GR7_View <= S_GR7_F;
GR8_View <= S_GR8_F; GR9_View <= S_GR9_F; GR10_View <= S_GR10_F; GR11_View <= S_GR11_F;
GR12_View <= S_GR12_F; GR13_View <= S_GR13_F; GR14_View <= S_GR14_F; GR15_View <= S_GR15_F;
process(clk) begin
if clk'event and (clk and S_GRlat) = '1' then
case S_ctl_c is
when "0000" => S_GR0_F <= S_BUS_C;
when "0001" => S_GR1_F <= S_BUS_C;
when "0010" => S_GR2_F <= S_BUS_C;
when "0011" => S_GR3_F <= S_BUS_C;
when "0100" => S_GR4_F <= S_BUS_C;
when "0101" => S_GR5_F <= S_BUS_C;
when "0110" => S_GR6_F <= S_BUS_C;
when "0111" => S_GR7_F <= S_BUS_C;
when "1000" => S_GR8_F <= S_BUS_C;
when "1001" => S_GR9_F <= S_BUS_C;
when "1010" => S_GR10_F <= S_BUS_C;
when "1011" => S_GR11_F <= S_BUS_C;
when "1100" => S_GR12_F <= S_BUS_C;
when "1101" => S_GR13_F <= S_BUS_C;
when "1110" => S_GR14_F <= S_BUS_C;
when "1111" => S_GR15_F <= S_BUS_C;
when others => null;
end case;
end if;
end process;
process(S_GR0_F, S_GR1_F, S_GR2_F, S_GR3_F, S_GR4_F, S_GR5_F, S_GR6_F,
S_GR7_F, S_GR8_F, S_GR9_F, S_GR10_F, S_GR11_F, S_GR12_F, S_GR13_F,
S_GR14_F, S_GR15_F, S_ctl_a, S_ctl_b) begin
case S_ctl_a is
when "0000" => S_BUS_A <= S_GR0_F;
when "0001" => S_BUS_A <= S_GR1_F;
when "0010" => S_BUS_A <= S_GR2_F;
when "0011" => S_BUS_A <= S_GR3_F;
when "0100" => S_BUS_A <= S_GR4_F;
when "0101" => S_BUS_A <= S_GR5_F;
when "0110" => S_BUS_A <= S_GR6_F;
when "0111" => S_BUS_A <= S_GR7_F;
when "1000" => S_BUS_A <= S_GR8_F;
when "1001" => S_BUS_A <= S_GR9_F;
when "1010" => S_BUS_A <= S_GR10_F;
when "1011" => S_BUS_A <= S_GR11_F;
when "1100" => S_BUS_A <= S_GR12_F;
when "1101" => S_BUS_A <= S_GR13_F;
when "1110" => S_BUS_A <= S_GR14_F;
when "1111" => S_BUS_A <= S_GR15_F;
when others => null;
end case;
case S_ctl_b is
when "0000" => S_BUS_B <= S_GR0_F;
when "0001" => S_BUS_B <= S_GR1_F;
when "0010" => S_BUS_B <= S_GR2_F;
when "0011" => S_BUS_B <= S_GR3_F;
when "0100" => S_BUS_B <= S_GR4_F;
when "0101" => S_BUS_B <= S_GR5_F;
when "0110" => S_BUS_B <= S_GR6_F;
when "0111" => S_BUS_B <= S_GR7_F;
when "1000" => S_BUS_B <= S_GR8_F;
when "1001" => S_BUS_B <= S_GR9_F;
when "1010" => S_BUS_B <= S_GR10_F;
when "1011" => S_BUS_B <= S_GR11_F;
when "1100" => S_BUS_B <= S_GR12_F;
when "1101" => S_BUS_B <= S_GR13_F;
when "1110" => S_BUS_B <= S_GR14_F;
when "1111" => S_BUS_B <= S_GR15_F;
when others => null;
end case;
end process;
end BEHAVIOR;
| mit | 3891e7ae029439c638e322cf3dbdbe02 | 0.502698 | 2.173607 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/simulation/fg_tb_synth.vhd | 1 | 9,297 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_fwft_64x1024_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | e4fd4defb8eecac3b82f9ea5d109ccc5 | 0.452834 | 4.204885 | false | false | false | false |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/asmi/asmi_inst.vhd | 1 | 1,225 | component asmi is
port (
clkin : in std_logic := 'X'; -- clk
read : in std_logic := 'X'; -- read
rden : in std_logic := 'X'; -- rden
addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- addr
reset : in std_logic := 'X'; -- reset
dataout : out std_logic_vector(7 downto 0); -- dataout
busy : out std_logic; -- busy
data_valid : out std_logic -- data_valid
);
end component asmi;
u0 : component asmi
port map (
clkin => CONNECTED_TO_clkin, -- clkin.clk
read => CONNECTED_TO_read, -- read.read
rden => CONNECTED_TO_rden, -- rden.rden
addr => CONNECTED_TO_addr, -- addr.addr
reset => CONNECTED_TO_reset, -- reset.reset
dataout => CONNECTED_TO_dataout, -- dataout.dataout
busy => CONNECTED_TO_busy, -- busy.busy
data_valid => CONNECTED_TO_data_valid -- data_valid.data_valid
);
| gpl-3.0 | c7eba27b57294a8bbe134a8dc4a81026 | 0.421224 | 3.840125 | false | false | false | false |
e8johan/jamcpu | regs.vhd | 1 | 1,350 | ---------------------------------------------------------
-- JAM CPU
-- Register bank
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.conv_integer;
entity regs is
port (
ra, rb, rw : in std_logic_vector (4 downto 0);
value_w : in std_logic_vector (31 downto 0);
clk : in std_logic;
value_a, value_b : out std_logic_vector (31 downto 0) );
end;
architecture rev1 of regs is
type mem_array is array (31 downto 0) of std_logic_vector (31 downto 0);
signal mem : mem_array := (others => (others => '0'));
begin
value_a <=
(others=>'0') when ra = "00000" else
value_w when ra = rw else
mem(conv_integer(ra));
value_b <=
(others=>'0') when rb = "00000" else
value_w when rb = rw else
mem(conv_integer(rb));
process (clk)
begin
if clk'event and clk = '1' then
if rw /= "00000" then
mem(conv_integer(rw)) <= value_w;
end if;
end if;
end process;
end;
| lgpl-2.1 | 667a4bf1f76ab446e9aa065bdafdb11d | 0.60963 | 3.292683 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512_hf/simulation/fg_tb_pkg.vhd | 1 | 11,358 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_64x512_hf_top IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 09c3272190eae5d6cfb42ad6f31c6519 | 0.503082 | 3.935551 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_32x512/example_design/fifo_32x512_top.vhd | 1 | 4,779 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_32x512_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_32x512_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_32x512_top;
architecture xilinx of fifo_32x512_top is
SIGNAL clk_i : std_logic;
component fifo_32x512 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_32x512 PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | cb5befd4aa30f2c9f8308543bc11d7a3 | 0.526051 | 4.906571 | false | false | false | false |
e8johan/jamcpu | cpu.vhd | 1 | 26,878 | ---------------------------------------------------------
-- JAM CPU core
-- Simple 32bit RISC CPU
--
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned.conv_integer;
entity CPU is
port(
--clock and reset
clk, reset : in std_logic;
--in and out ports
inport : in std_logic_vector(31 downto 0);
outport : out std_logic_vector(31 downto 0);
--IO interface
synctrap : in std_logic;
put : out std_logic;
curpsw11_31 : out std_logic_vector(31 downto 11);
curpsw0_7 : out std_logic_vector(7 downto 0);
newpsw11_31 : in std_logic_vector(31 downto 11);
newpsw0_7 : in std_logic_vector(7 downto 0);
--IM
im_cs : out std_logic_vector(7 downto 0);
im_oe : out std_logic;
im_wri : out std_logic;
im_adr : out std_logic_vector( 16 downto 0 );
im_dat : inout std_logic_vector( 63 downto 0 );
--DM
dm_cs : out std_logic_vector(7 downto 0);
dm_oe : out std_logic;
dm_wri : out std_logic;
dm_adr : out std_logic_vector( 16 downto 0 );
dm_dat : inout std_logic_vector( 63 downto 0 ));
end;
architecture rev1 of CPU is
--The location of the traphandler
constant trap_vector : std_logic_vector(31 downto 0) := (others => '0');
--PC is reset to this value on reset
constant start_vector : std_logic_vector(31 downto 0) := (others => '0');
---------------------------------------------------
-- Pipelineregisters declarative part
--
-- foo_reg - signals out from pipelineregister
-- foo_in - signals to be clocked into the reg
-- foo_reset - output zeros next tick
-- foo_hold - hold signal out next tick
---------------------------------------------------
-- IF/ID
type ifid_struct is record
iword : std_logic_vector(31 downto 0); --instruction word
pc : std_logic_vector(31 downto 0); --pc for this instruction
cm_hw_int : std_logic; --hw interupt
end record;
signal ifid_reg : ifid_struct;
signal ifid_in : ifid_struct;
signal ifid_reset : std_logic;
signal ifid_hold : std_logic;
-- ID/EX
type idex_struct is record
-- data
pc : std_logic_vector(31 downto 0);
areg : std_logic_vector(31 downto 0);
breg : std_logic_vector(31 downto 0);
imm : std_logic_vector(31 downto 0);
-- reg index
src1 : std_logic_vector(4 downto 0);
src2 : std_logic_vector(4 downto 0);
dest : std_logic_vector(4 downto 0);
-- control signals to EX stage
cex_asel : std_logic;
cex_bsel : std_logic;
cex_ressel : std_logic;
cex_regsel : std_logic_vector(1 downto 0);
cex_aluop : std_logic_vector(2 downto 0);
cex_domult : std_logic;
cex_multop : std_logic;
cex_invin2 : std_logic;
cex_valid_reg : std_logic;
cex_valid_res : std_logic;
cex_psw_enable: std_logic;
cex_put : std_logic;
-- control signals to MEM stage
cm_valid_mem : std_logic;
cm_valid_reg : std_logic;
cm_write : std_logic;
cm_read : std_logic;
cm_hw_int : std_logic;
cm_bad_op : std_logic;
cm_sw_int : std_logic;
cm_jump : std_logic;
-- control signals to WB stage
cwb_sel : std_logic;
cwb_enable : std_logic;
cwb_valid : std_logic;
cwb_branch : std_logic;
end record;
signal idex_reg : idex_struct;
signal idex_in : idex_struct;
signal idex_reset : std_logic;
signal idex_hold : std_logic;
-- EX/MEM
type exmem_struct is record
pc : std_logic_vector(31 downto 0);
res : std_logic_vector(31 downto 0);
reg : std_logic_vector(31 downto 0);
dest : std_logic_vector(4 downto 0);
cm_write : std_logic;
cm_read : std_logic;
cm_valid_mem : std_logic;
cm_valid_reg : std_logic;
cm_hw_int : std_logic;
cm_bad_op : std_logic;
cm_sw_int : std_logic;
cm_jump : std_logic;
cm_ovf : std_logic;
cwb_sel : std_logic;
cwb_enable : std_logic;
cwb_valid : std_logic;
cwb_branch : std_logic;
end record;
signal exmem_reg : exmem_struct;
signal exmem_in : exmem_struct;
signal exmem_reset : std_logic;
signal exmem_hold : std_logic;
-- MEM/WB
type memwb_struct is record
mem : std_logic_vector(31 downto 0);
reg : std_logic_vector(31 downto 0);
dest : std_logic_vector(4 downto 0);
cwb_sel : std_logic;
cwb_enable : std_logic;
cwb_valid : std_logic;
cwb_branch : std_logic;
end record;
signal memwb_reg : memwb_struct;
signal memwb_in : memwb_struct;
signal memwb_reset : std_logic;
signal memwb_hold : std_logic;
---------------------------------------------------
-- IF declarative part
---------------------------------------------------
-- memory access unit (IM)
component MAU
port(
-- Signalas from/to CPU/CONTROLL
CLK : in std_logic;
CTRL_R : in std_logic; -- Read Mem
CTRL_W : in std_logic; -- Write Mem
RESET : in std_logic;
STALL : out std_logic; -- Used to stall one cycle on write
IN_ADDR : in std_logic_vector(31 downto 0); -- Adress Buss from CPU
IN_DATA : in std_logic_vector(31 downto 0); -- Data Buss from CPU
OUT_DATA : out std_logic_vector(31 downto 0); -- Data Buss to CPU
-- Signals from/to MEM
DM_CS : out std_logic_vector(7 downto 0); -- Chip Select (active low)
DM_OE : out std_logic; -- Output Enable (active low)
DM_WRITE : out std_logic; -- Write Data, Mem (data -> HighZ) (active low)
DM_ADDR : out std_logic_vector(16 downto 0); -- Address Buss to mem
DM_DATA : inout std_logic_vector(63 downto 0) -- Mem Data Buss (Bidirectional)
);
end component;
for if_mau: MAU use entity work.MAU;
signal if_pc : std_logic_vector(31 downto 0); -- current PC register
signal if_pc_word : std_logic_vector(31 downto 0);
signal if_int : std_logic;
signal if_iword : std_logic_vector(31 downto 0);
signal if_zero : std_logic;
signal if_one : std_logic;
signal if_zero32 : std_logic_vector(31 downto 0);
---------------------------------------------------
-- ID declarative part
---------------------------------------------------
-- Register file
component regs
port (
ra, rb, rw : in std_logic_vector(4 downto 0);
value_w : in std_logic_vector(31 downto 0);
clk : in std_logic;
value_a, value_b : out std_logic_vector(31 downto 0) );
end component;
-- The format handler
component imm_ext
port (
mode : in std_logic_vector(1 downto 0);
op5 : in std_logic;
imm : in std_logic_vector(15 downto 0);
r : out std_logic_vector(31 downto 0) );
end component;
-- Control unit
component control
port (
op : in std_logic_vector (5 downto 0); -- The op code
ex_asel : out std_logic; -- (ra,psw)
ex_bsel : out std_logic; -- (rb,imm)
ex_ressel : out std_logic; -- (res,sign)
ex_regsel : out std_logic_vector (1 downto 0); -- (psw,pc,b,in)
ex_aluop : out std_logic_vector (2 downto 0); -- (nop,add,sub,op,and,xor,shz,shs)
ex_domult : out std_logic; -- (off,on)
ex_multop : out std_logic; -- (low,high)
ex_invin2 : out std_logic; -- (off,on)
ex_valid_reg : out std_logic; -- valid data
ex_valid_res : out std_logic; -- valid data
ex_psw_enable: out std_logic; -- write to psw?
ex_put : out std_logic; -- write to outport
m_read : out std_logic; -- DM read
m_write : out std_logic; -- DM write
m_valid_reg : out std_logic; -- valid data
m_valid_mem : out std_logic; -- valid data
wb_sel : out std_logic; -- (mem,reg)
wb_enable : out std_logic; -- (off,on)
id_bsel : out std_logic; -- '1' if rd is used as r2
id_beq : out std_logic; -- '1' if the op is a branch
id_bne : out std_logic; -- '1' if the op is a branch n.eq.
illegal_op : out std_logic; -- '1' when illegal op
trap : out std_logic; -- trap
jump : out std_logic); -- jump instr.
end component;
for id_regs: regs use entity work.regs(rev1);
for id_ix: imm_ext use entity work.imm_ext(rev1);
for id_ctrl: control use entity work.control(rev1);
signal id_rb : std_logic_vector(4 downto 0);
signal id_branchadr : std_logic_vector(31 downto 0);
signal id_a : std_logic_vector(31 downto 0);
signal id_b : std_logic_vector(31 downto 0);
signal id_stalling : std_logic;
signal cid_branch : std_logic; -- branch?
signal cid_cmp : std_logic; -- High when a == b
signal cid_bsel : std_logic;
signal cid_beq : std_logic;
signal cid_bne : std_logic;
-- Valid signals from control
signal cex_valid_reg : std_logic;
signal cex_valid_res : std_logic;
signal cm_valid_mem : std_logic;
signal cm_valid_reg : std_logic;
---------------------------------------------------
-- EX declarative part
---------------------------------------------------
-- integer unit (ALU + mult)
component IU
port(
a_in, b_in : in std_logic_vector(31 downto 0); -- IU input
do_mult : in std_logic; -- Do multicycle mult?
mult_op : in std_logic; -- Return [0=LSW] or [1=MSW) of mult result
alu_op : in std_logic_vector(2 downto 0); -- ALU op
inv_in2 : in std_logic; -- Invert operator in2 in ALU
clk : in std_logic; -- Global clock
reset : in std_logic; -- Global reset
ovf : out std_logic; -- Overflow
result : out std_logic_vector(31 downto 0); -- IU result
mc : out std_logic); -- Goes high during the last cycle of a multicycle op
end component;
for ex_iu: IU use entity work.IU(rev1);
signal ex_ain : std_logic_vector(31 downto 0);
signal ex_bin : std_logic_vector(31 downto 0);
signal ex_breg : std_logic_vector(31 downto 0);
signal ex_psw : std_logic_vector(31 downto 0);
signal ex_result : std_logic_vector(31 downto 0);
signal ex_wb_data_buf : std_logic_vector(31 downto 0);
signal ex_wb_dest_buf : std_logic_vector(4 downto 0);
signal ex_wb_valid_buf : std_logic;
signal ex_stalling : std_logic;
signal ex_lw_hazard : std_logic;
signal ex_mc_finished : std_logic;
signal ex_do_mult : std_logic;
---------------------------------------------------
-- MEM declarative part
---------------------------------------------------
-- memory access unit (DM)
for mem_mau: MAU use entity work.MAU;
signal mem_stalling : std_logic;
signal mem_clear : std_logic;
signal mem_res : std_logic_vector(31 downto 0);
signal mem_data : std_logic_vector(31 downto 0);
signal mem_adr_word : std_logic_vector(31 downto 0);
signal mem_jump_trap : std_logic;
---------------------------------------------------
-- WB declarative part
---------------------------------------------------
signal wb_rw : std_logic_vector(4 downto 0);
signal wb_value : std_logic_vector (31 downto 0);
begin
---------------------------------------------------
-- Pipeline registers
---------------------------------------------------
--IF/ID
process(clk)
begin
if clk'event and clk='1' then
if ( (ifid_reset = '1') or (reset = '1') ) then
ifid_reg <= ((others => '0'), (others => '0'), '0');
elsif ifid_hold /= '1' then
ifid_reg <= ifid_in;
end if;
end if;
end process;
-- Stall/nop logic
ifid_hold <=
'1' when ( (id_stalling = '1') or (ex_stalling = '1') or (mem_stalling = '1') ) else
'0';
ifid_reset <= mem_clear;
--ID/EX
process(clk)
begin
if clk'event and clk='1' then
if ( (idex_reset = '1') or (reset = '1') ) then
idex_reg <= ((others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),(others => '0'),'0','0','0',(others => '0'),(others => '0'),'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','0');
elsif idex_hold /= '1' then
idex_reg <= idex_in;
end if;
end if;
end process;
-- Stall/nop logic
idex_hold <=
'1' when ( (ex_stalling = '1') or (mem_stalling = '1') ) else
'0';
idex_reset <=
'1' when ( ( (id_stalling = '1') and (idex_hold = '0') ) or (mem_clear = '1') ) else
'0';
--EX/MEM
process(clk)
begin
if clk'event and clk='1' then
if ( (exmem_reset = '1') or (reset = '1') ) then
exmem_reg <= ((others => '0'),(others => '0'),(others => '0'),(others => '0'),'0','0','0','0','0','0','0','0','0','0','0','0','0');
elsif exmem_hold /= '1' then
exmem_reg <= exmem_in;
end if;
end if;
end process;
-- Stall/nop logic
exmem_hold <=
'1' when (mem_stalling = '1') else
'0';
exmem_reset <=
'1' when mem_clear = '1' else
'1' when ( (ex_stalling = '1') and (mem_stalling = '0') ) else
'0';
--MEM/WB latch
process(clk)
begin
if clk'event and clk='1' then
if ( (memwb_reset = '1') or (reset = '1') ) then
memwb_reg <= ((others => '0'),(others => '0'),(others => '0'),'0','0','0','0');
elsif memwb_hold /= '1' then
memwb_reg <= memwb_in;
end if;
end if;
end process;
-- Stall/nop logic
memwb_hold <=
'1' when (mem_stalling = '1') else
'0';
memwb_reset <= '0';
---------------------------------------------------
-- IF Stage
---------------------------------------------------
-- IM is read only
if_zero <= '0';
if_one <= '1';
if_zero32 <= (others => '0');
if_pc_word <= "00" & if_pc(31 downto 2);
-- [PORTMAP] IM
if_mau : MAU port map(
CLK => clk,
RESET => reset,
CTRL_W => if_zero,
CTRL_R => if_one,
--STALL =>
IN_ADDR => if_pc_word,
IN_DATA => if_zero32,
OUT_DATA => if_iword,
DM_CS => im_cs,
DM_OE => im_oe,
DM_WRITE => im_wri,
DM_ADDR => im_adr,
DM_DATA => im_dat
);
ifid_in.pc <= if_pc;
--ifid_in.iword <= rom_image(conv_integer(if_pc(31 downto 2))); --fetch instruction from ROM (in simcpu nowdays)
ifid_in.iword <=
if_iword when if_int = '0' else
"10100100000000000000000000000000"; --inject trap
-- HW interupt injector
ifid_in.cm_hw_int <= if_int;
-- handle PC
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
if_pc <= start_vector;
--Update PC
elsif ifid_hold = '0' then
if exmem_reg.cm_jump = '1' then
if_pc <= exmem_reg.res;
elsif mem_jump_trap = '1' then
if_pc <= trap_vector;
elsif cid_branch = '1' then
if_pc <= id_branchadr;
else
if_pc <= if_pc + "100"; -- pc+=4
end if;
end if;
end if;
end process;
-- Interupt injector
process(clk)
begin
if clk'event and clk='1' then
if ( (reset = '1') or (exmem_reg.cm_hw_int = '1') ) then
if_int <= '0';
elsif ( (synctrap='1') or (if_int = '1') ) then
if_int <= '1';
end if;
end if;
end process;
---------------------------------------------------
-- ID Stage
---------------------------------------------------
-- Some stupid instructions use dest for regb, this handles them!
-- We can let control handle this or do it ourself.
id_rb <=
--ifid_reg.iword(25 downto 21) when cid_bsel = '0' else
ifid_reg.iword(25 downto 21) when (ifid_reg.iword(31 downto 26) = "100111") else --SW
ifid_reg.iword(25 downto 21) when (ifid_reg.iword(31 downto 26) = "010111") else --BNE
ifid_reg.iword(25 downto 21) when (ifid_reg.iword(31 downto 26) = "010011") else --BEQ
ifid_reg.iword(15 downto 11);
-- Destination field in the iword
idex_in.dest <= ifid_reg.iword(25 downto 21);
-- [PORTMAP] The register bank
id_regs : regs port map(
ra => ifid_reg.iword(20 downto 16),
rb => id_rb,
rw => wb_rw,
value_w => wb_value,
clk => clk,
value_a => idex_in.areg,
value_b => idex_in.breg);
-- Send sourceregs. to idex reg (used for forwarding logic)
idex_in.src1 <= ifid_reg.iword(20 downto 16);
idex_in.src2 <= id_rb;
-- [PORTMAP] The immediate extender unit, does magic to the imm field
id_ix : imm_ext port map(
mode => ifid_reg.iword(27 downto 26),
op5 => ifid_reg.iword(31),
imm => ifid_reg.iword(15 downto 0),
r => idex_in.imm);
-- Forwarding logic for branch compare
id_a <=
--exmem_in.res when ( (idex_in.src1 = idex_reg.dest) and (idex_reg.cex_valid_res = '1') ) else -- critical path
--exmem_in.reg when ( (idex_in.src1 = idex_reg.dest) and (idex_reg.cex_valid_reg = '1') ) else -- we stall instead
exmem_reg.res when ( (idex_in.src1 = exmem_reg.dest) and (exmem_reg.cm_valid_mem = '1') ) else
exmem_reg.reg when ( (idex_in.src1 = exmem_reg.dest) and (exmem_reg.cm_valid_reg = '1') ) else
idex_in.areg;
id_b <=
--exmem_in.res when ( (idex_in.src2 = idex_reg.dest) and (idex_reg.cex_valid_res = '1') ) else
--exmem_in.reg when ( (idex_in.src2 = idex_reg.dest) and (idex_reg.cex_valid_reg = '1') ) else
exmem_reg.res when ( (idex_in.src2 = exmem_reg.dest) and (exmem_reg.cm_valid_mem = '1') ) else
exmem_reg.reg when ( (idex_in.src2 = exmem_reg.dest) and (exmem_reg.cm_valid_reg = '1') ) else
idex_in.breg;
--Stall when we need data from EX in branch logic
id_stalling <=
'0' when ( (cid_bne = '0') and (cid_beq = '0') ) else
'1' when ( (idex_in.src1 = idex_reg.dest) and ( (idex_reg.cex_valid_res = '1') or (idex_reg.cex_valid_reg = '1') ) ) else
'1' when ( (idex_in.src2 = idex_reg.dest) and ( (idex_reg.cex_valid_res = '1') or (idex_reg.cex_valid_reg = '1') ) ) else
'0';
-- The branch logic
cid_cmp <=
'1' when (id_a = id_b) else
'0';
cid_branch <=
'1' when ( (cid_cmp = '0') and (cid_bne = '1') ) else
'1' when ( (cid_cmp = '1') and (cid_beq = '1') ) else
'0';
-- Save branch flag for branch delay slot detection by trap handler
idex_in.cwb_branch <= cid_branch;
-- Jumpdestination calc.
id_branchadr <= idex_in.imm + ifid_reg.pc;
-- [PORTMAP] The control unit
id_ctrl : control port map(
op => ifid_reg.iword(31 downto 26),
ex_asel => idex_in.cex_asel,
ex_bsel => idex_in.cex_bsel,
ex_ressel => idex_in.cex_ressel,
ex_regsel => idex_in.cex_regsel,
ex_aluop => idex_in.cex_aluop,
ex_domult => idex_in.cex_domult,
ex_multop => idex_in.cex_multop,
ex_invin2 => idex_in.cex_invin2,
ex_valid_res => cex_valid_res,
ex_valid_reg => cex_valid_reg,
ex_psw_enable => idex_in.cex_psw_enable,
ex_put => idex_in.cex_put,
m_write => idex_in.cm_write,
m_read => idex_in.cm_read,
m_valid_mem => cm_valid_mem,
m_valid_reg => cm_valid_reg,
wb_sel => idex_in.cwb_sel,
wb_enable => idex_in.cwb_enable,
id_bsel => cid_bsel,
id_beq => cid_beq,
id_bne => cid_bne,
illegal_op => idex_in.cm_bad_op,
trap => idex_in.cm_sw_int,
jump => idex_in.cm_jump
);
-- The valid data control signals
idex_in.cex_valid_reg <=
'0' when ifid_reg.iword(25 downto 21) = "00000" else
cex_valid_reg;
idex_in.cex_valid_res <=
'0' when ifid_reg.iword(25 downto 21) = "00000" else
cex_valid_res;
idex_in.cm_valid_mem <=
'0' when ifid_reg.iword(25 downto 21) = "00000" else
cm_valid_mem;
idex_in.cm_valid_reg <=
'0' when ifid_reg.iword(25 downto 21) = "00000" else
cm_valid_reg;
idex_in.cwb_valid <=
'0' when idex_in.dest = "00000" else --R0
'0' when idex_in.cwb_enable = '0' else --No valid data
'1';
-- copy to next pipeline stage
idex_in.pc <= ifid_reg.pc;
idex_in.cm_hw_int <= ifid_reg.cm_hw_int;
---------------------------------------------------
-- EX Stage
---------------------------------------------------
-- [PORTMAP] Integer unit
ex_iu : IU port map(
a_in => ex_ain,
b_in => ex_bin,
do_mult => ex_do_mult,
mult_op => idex_reg.cex_multop,
alu_op => idex_reg.cex_aluop,
inv_in2 => idex_reg.cex_invin2,
clk => clk,
reset => reset,
ovf => exmem_in.cm_ovf,
result => ex_result,
mc => ex_mc_finished
);
-- LW hazard (we need the result from a LW)?
ex_lw_hazard <=
'0' when exmem_reg.cm_read = '0' else
'1' when ((exmem_reg.dest = idex_reg.src1) or (exmem_reg.dest = idex_reg.src2)) else
'0';
-- EX stall logic
ex_stalling <=
--stall on mult
'0' when ex_mc_finished = '1' else
'1' when idex_reg.cex_domult = '1' else
-- stall on LW (and we need the result)
'1' when ex_lw_hazard = '1' else
'0';
-- don't start mult on LW stall
ex_do_mult <=
'0' when ex_lw_hazard = '1' else
idex_reg.cex_domult;
-- copy signals to next pipeline stage
exmem_in.pc <= idex_reg.pc;
exmem_in.dest <= idex_reg.dest;
exmem_in.cm_read <= idex_reg.cm_read;
exmem_in.cm_write <= idex_reg.cm_write;
exmem_in.cm_valid_mem <= idex_reg.cm_valid_mem;
exmem_in.cm_valid_reg <= idex_reg.cm_valid_reg;
exmem_in.cm_hw_int <= idex_reg.cm_hw_int;
exmem_in.cm_bad_op <= idex_reg.cm_bad_op;
exmem_in.cm_sw_int <= idex_reg.cm_sw_int;
exmem_in.cm_jump <= idex_reg.cm_jump;
exmem_in.cwb_sel <= idex_reg.cwb_sel;
exmem_in.cwb_enable <= idex_reg.cwb_enable;
exmem_in.cwb_valid <= idex_reg.cwb_valid;
exmem_in.cwb_branch <= idex_reg.cwb_branch;
-- outport pins on CPU
outport <= idex_reg.areg;
put <= idex_reg.cex_put;
-- A input to IU
ex_ain <=
ex_psw when idex_reg.cex_asel = '1' else
exmem_reg.res when ( (idex_reg.src1 = exmem_reg.dest) and (exmem_reg.cm_valid_mem = '1') ) else -- Forwarding from mem to ex
exmem_reg.reg when ( (idex_reg.src1 = exmem_reg.dest) and (exmem_reg.cm_valid_reg = '1') ) else -- Forwarding from mem to ex
wb_value when ( (idex_reg.src1 = memwb_reg.dest) and (memwb_reg.cwb_valid = '1') ) else -- Forwarding from wb to ex
ex_wb_data_buf when ( (idex_reg.src1 = ex_wb_dest_buf) and (ex_wb_valid_buf ='1') ) else
idex_reg.areg;
-- Forwarding logic for breg data
ex_breg <=
exmem_reg.res when ( (idex_reg.src2 = exmem_reg.dest) and (exmem_reg.cm_valid_mem = '1') ) else -- Forwarding from mem to ex
exmem_reg.reg when ( (idex_reg.src2 = exmem_reg.dest) and (exmem_reg.cm_valid_reg = '1') ) else -- Forwarding from mem to ex
wb_value when ( (idex_reg.src2 = memwb_reg.dest) and (memwb_reg.cwb_valid = '1') ) else -- Forwarding from wb to ex
ex_wb_data_buf when ( (idex_reg.src2 = ex_wb_dest_buf) and (ex_wb_valid_buf ='1') ) else
idex_reg.breg;
-- B input on IU
ex_bin <=
idex_reg.imm when idex_reg.cex_bsel = '1' else
ex_breg;
-- Mux after IU
exmem_in.res <=
(0 => ex_result(31), others => '0') when idex_reg.cex_ressel = '1' else
ex_result;
-- Data for reg
exmem_in.reg <=
ex_psw when idex_reg.cex_regsel = "00" else
idex_reg.pc when idex_reg.cex_regsel = "01" else
ex_breg when idex_reg.cex_regsel = "10" else
inport;
-- Mirror PSW to outside world
curpsw11_31 <= ex_psw(31 downto 11);
curpsw0_7 <= ex_psw(7 downto 0);
process(clk)
begin
if clk'event and clk='1' then
if reset = '1' then
-- reset PSW
ex_psw <= "11111111111111111111111100000000";
ex_wb_valid_buf <= '0';
else
--We must buffer the WB stage data on LW hazards
if ex_lw_hazard = '1' then
ex_wb_valid_buf <= memwb_reg.cwb_valid;
ex_wb_dest_buf <= wb_rw;
ex_wb_data_buf <= wb_value;
else
ex_wb_valid_buf <= '0';
end if;
--Update psw
if exmem_reg.cm_bad_op = '1' then
ex_psw(9) <= '1';
elsif exmem_reg.cm_ovf = '1' then
ex_psw(8) <= '1';
elsif idex_reg.cex_psw_enable = '1' then
ex_psw <= ex_result;
end if;
if ifid_reg.cm_hw_int = '1' then
ex_psw(31 downto 11) <= newpsw11_31;
ex_psw(7 downto 0) <= newpsw0_7;
end if;
end if;
end if;
end process;
---------------------------------------------------
-- MEM Stage
---------------------------------------------------
mem_adr_word <= "00" & exmem_reg.res(31 downto 2);
--[PORTMAP] DM
mem_mau : MAU port map(
CLK => clk,
RESET => reset,
CTRL_W => exmem_reg.cm_write,
CTRL_R => exmem_reg.cm_read,
STALL => mem_stalling,
IN_ADDR => mem_adr_word,
IN_DATA => mem_data, -- To forw. mux
OUT_DATA => mem_res,
DM_CS => dm_cs,
DM_OE => dm_oe,
DM_WRITE => dm_wri,
DM_ADDR => dm_adr,
DM_DATA => dm_dat
);
-- copy signals and regs to next pipe stage
memwb_in.cwb_enable <= exmem_reg.cwb_enable;
memwb_in.cwb_valid <= exmem_reg.cwb_valid;
memwb_in.cwb_branch <= exmem_reg.cwb_branch;
-- Forwarding from wb to mem only when SW.
mem_data <=
wb_value when ( (exmem_reg.cm_write = '1') and (exmem_reg.dest = memwb_reg.dest) and (memwb_reg.cwb_valid = '1') ) else
exmem_reg.reg;
-- Mux, selecting mem-result or IU-result.
memwb_in.mem <=
mem_res when exmem_reg.cm_read = '1' else
exmem_reg.res;
-- Jump to trap handler?
mem_jump_trap <=
'0' when memwb_reg.cwb_branch = '1' else --this is a delay slot (ignore trap)
'1' when exmem_reg.cm_hw_int = '1' else
'1' when exmem_reg.cm_bad_op = '1' else
'1' when exmem_reg.cm_sw_int = '1' else
'1' when exmem_reg.cm_ovf = '1' else
'0';
-- Make WB write PC to R31 on trap (else copy normal values)
memwb_in.dest <=
"11111" when mem_jump_trap = '1' else
exmem_reg.dest;
memwb_in.cwb_sel <=
'1' when mem_jump_trap = '1' else
exmem_reg.cwb_sel;
memwb_in.reg <=
exmem_reg.pc when mem_jump_trap = '1' else
exmem_reg.reg;
-- Clear IF/ID, ID/EX and EX/MEM
mem_clear <=
'1' when ( (exmem_reg.cm_jump = '1') or (mem_jump_trap = '1') ) else
'0';
---------------------------------------------------
-- WB Stage
---------------------------------------------------
-- Write what to regs?
wb_value <=
memwb_reg.mem when memwb_reg.cwb_sel = '0' else
memwb_reg.reg;
-- Write or not to write, that is the question...
wb_rw <=
"00000" when memwb_reg.cwb_enable = '0' else
memwb_reg.dest;
end;
| lgpl-2.1 | 0f48038c9809a22c2a0a549630f2abe3 | 0.55231 | 2.893219 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/mdr_32.vhd | 1 | 857 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(31 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0)
);
end mdr;
architecture BEHAVIOR of mdr is
begin
process(clock) begin
if(clock'event and clock = '1')then
if(latch = '1')then
if(sel = '0')then
data <= busC(15 downto 0);
elsif(sel = '1')then
data <= memo;
else
null;
end if;
else
null;
end if;
else
null;
end if;
end process;
end BEHAVIOR;
| mit | 6da8c031ba0ce7c0615746b5546692c6 | 0.472579 | 3.86036 | false | false | false | false |
mzakharo/usb-de2-fpga | src/isp_inc.vhd | 1 | 11,513 | -- isp_inc.vhd
-- -----------------------------------------------------------------------
-- Copyright © 2012 Mikhail Zakharov
-- -----------------------------------------------------------------------
--
-- This file is part of "ISP1362 VHDL interface for DE2"
--
-- "ISP1362 VHDL interface for DE2" is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3
--
-- "ISP1362 VHDL interface for DE2" is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with "ISP1362 VHDL interface for DE2". If not, see <http://www.gnu.org/licenses/>.
-- -----------------------------------------------------------------------
-- ISP1362 register definitions and bit field constants
-- -----------------------------------------------------------------------
-- Version : 1.0
-- Date : Sept 2012
-- Author : Mikhail Zakharov
-- Web : http://ca.linkedin.com/in/mzakharo
-- Contact : [email protected]
-- -----------------------------------------------------------------------
-- FUNCTION :
-- VHDL translation of constants, defined in ISP1362 Datasheet, Ch 15
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package isp_inc is
--=-=-=-=-=-COMMANDS-=-=-=-=-=--
constant Wr_DcEndpointConfiguration : std_logic_vector(15 downto 4) := x"002"; --20h = control out
constant Rd_DcEndpointConfiguration : std_logic_vector(15 downto 4) := x"003"; --30h = control out
constant Wr_DcAddress : std_logic_vector(15 downto 0) := x"00B6"; --B6h
constant Rd_DcAddress : std_logic_vector(15 downto 0) := x"00B7"; --B7h
constant Wr_DcMode : std_logic_vector(15 downto 0) := x"00B8"; --B8h
constant Rd_DcMode : std_logic_vector(15 downto 0) := x"00B9"; --B9h
constant Wr_DcHardwareConfiguration : std_logic_vector(15 downto 0) := x"00BA"; --BAh
constant Rd_DcHardwareConfiguration : std_logic_vector(15 downto 0) := x"00BB"; --BBh
constant Wr_DcInterruptEnable : std_logic_vector(15 downto 0) := x"00C2"; --C2h
constant Rd_DcInterruptEnable : std_logic_vector(15 downto 0) := x"00C3"; --C3h
constant Wr_DcDMAConfiguration : std_logic_vector(15 downto 0) := x"00F0"; --F0h
constant Rd_DcDMAConfiguration : std_logic_vector(15 downto 0) := x"00F1"; --F1h
constant Wr_DcDMACounter : std_logic_vector(15 downto 0) := x"00F2"; --F2h
constant Rd_DcDMACounter : std_logic_vector(15 downto 0) := x"00F3"; --F3h
constant Reset : std_logic_vector(15 downto 0) := x"00F6"; --F6h
constant Wr_Buffer : std_logic_vector(15 downto 4) := x"000"; --00h = control out (0 illegal)
constant Rd_Buffer : std_logic_vector(15 downto 4) := x"001"; --10h = control out (1 illegal)
constant Rd_ESR : std_logic_vector(15 downto 4) := x"005"; --50h = control out
constant EPSTS_STALL : std_logic_vector(15 downto 4) := x"004"; --40h = control out
constant EPSTS_UNSTALL : std_logic_vector(15 downto 4) := x"008"; --80h = control out
constant Validate : std_logic_vector(15 downto 4) := x"006"; --60h = control out (0 illegal)
constant ClearBuffer : std_logic_vector(15 downto 4) := x"007"; --70h = control out (1 illegal)
constant Rd_DcEndpointStatusImage : std_logic_vector(15 downto 4) := x"00D"; --D0h = control out
constant AcknowledgeSetup : std_logic_vector(15 downto 0) := x"00F4"; --F4h (must ack setups sec12.3.6)
constant Rd_ErrorCode : std_logic_vector(15 downto 4) := x"00A"; --A0h = control out
constant UnlockDevice : std_logic_vector(15 downto 0) := x"00B0"; --B0h
constant Wr_DcScratchRegister : std_logic_vector(15 downto 0) := x"00B2"; --B2h
constant Rd_DcScratchRegister : std_logic_vector(15 downto 0) := x"00B3"; --B3h
constant Rd_DcFrameNumber : std_logic_vector(15 downto 0) := x"00B4"; --B4h
constant Rd_DcChipID : std_logic_vector(15 downto 0) := x"00B5"; --B5h
constant Rd_DcInterrupt : std_logic_vector(15 downto 0) := x"00C0"; --C0h
--From hal.h
constant EPINDEX4EP0_CONTROL_OUT : std_logic_vector(3 downto 0) := x"0";
constant EPINDEX4EP0_CONTROL_IN : std_logic_vector(3 downto 0) := x"1";
constant EPINDEX4EP01 : std_logic_vector(3 downto 0) := x"2";
constant EPINDEX4EP02 : std_logic_vector(3 downto 0) := x"3";
constant EPINDEX4EP03 : std_logic_vector(3 downto 0) := x"4";
constant EPINDEX4EP04 : std_logic_vector(3 downto 0) := x"5";
constant EPINDEX4EP05 : std_logic_vector(3 downto 0) := x"6";
constant EPINDEX4EP06 : std_logic_vector(3 downto 0) := x"7";
constant EPINDEX4EP07 : std_logic_vector(3 downto 0) := x"8";
constant EPINDEX4EP08 : std_logic_vector(3 downto 0) := x"9";
constant EPINDEX4EP09 : std_logic_vector(3 downto 0) := x"A";
constant EPINDEX4EP0A : std_logic_vector(3 downto 0) := x"B";
constant EPINDEX4EP0B : std_logic_vector(3 downto 0) := x"C";
constant EPINDEX4EP0C : std_logic_vector(3 downto 0) := x"D";
constant EPINDEX4EP0D : std_logic_vector(3 downto 0) := x"E";
constant EPINDEX4EP0E : std_logic_vector(3 downto 0) := x"F";
constant DEVADDR_MASK : std_logic_vector(15 downto 0) := x"007F";
constant DEVADDR_EN : std_logic_vector(15 downto 0) := x"0080";
constant EP_DISABLE : std_logic_vector(15 downto 0) := "--------0-------";
constant EPCNFG_FIFO_EN : std_logic_vector(15 downto 0) := x"0080";
constant EPCNFG_IN_EN : std_logic_vector(15 downto 0) := x"0040";
constant EPCNFG_DBLBUF_EN : std_logic_vector(15 downto 0) := x"0020";
constant EPCNFG_ISO_EN : std_logic_vector(15 downto 0) := x"0010";
constant EPCNFG_ISOSZ_MASK : std_logic_vector(15 downto 0) := x"000F";
constant EPCNFG_NONISOSZ_MASK : std_logic_vector(15 downto 0) := x"0007";
constant EPCNFG_RFB_EN : std_logic_vector(15 downto 0) := x"0008";
constant EPCNFG_NONISOSZ_8 : std_logic_vector(15 downto 0) := x"0000";
constant EPCNFG_NONISOSZ_16 : std_logic_vector(15 downto 0) := x"0001";
constant EPCNFG_NONISOSZ_32 : std_logic_vector(15 downto 0) := x"0002";
constant EPCNFG_NONISOSZ_64 : std_logic_vector(15 downto 0) := x"0003";
constant EPCNFG_ISOSZ_16 : std_logic_vector(15 downto 0) := x"0000";
constant EPCNFG_ISOSZ_32 : std_logic_vector(15 downto 0) := x"0001";
constant EPCNFG_ISOSZ_48 : std_logic_vector(15 downto 0) := x"0002";
constant EPCNFG_ISOSZ_64 : std_logic_vector(15 downto 0) := x"0003";
constant EPCNFG_ISOSZ_96 : std_logic_vector(15 downto 0) := x"0004";
constant EPCNFG_ISOSZ_128 : std_logic_vector(15 downto 0) := x"0005";
constant EPCNFG_ISOSZ_160 : std_logic_vector(15 downto 0) := x"0006";
constant EPCNFG_ISOSZ_192 : std_logic_vector(15 downto 0) := x"0007";
constant EPCNFG_ISOSZ_256 : std_logic_vector(15 downto 0) := x"0008";
constant EPCNFG_ISOSZ_320 : std_logic_vector(15 downto 0) := x"0009";
constant EPCNFG_ISOSZ_384 : std_logic_vector(15 downto 0) := x"000A";
constant EPCNFG_ISOSZ_512 : std_logic_vector(15 downto 0) := x"000B";
constant EPCNFG_ISOSZ_640 : std_logic_vector(15 downto 0) := x"000C";
constant EPCNFG_ISOSZ_768 : std_logic_vector(15 downto 0) := x"000D";
constant EPCNFG_ISOSZ_896 : std_logic_vector(15 downto 0) := x"000E";
constant EPCNFG_ISOSZ_1023 : std_logic_vector(15 downto 0) := x"000F";
--constant EPSTS_STALL : std_logic_vector(15 downto 0) := x"0080";
constant EPSTS_DBF1 : std_logic_vector(15 downto 0) := x"0040";
constant EPSTS_DBF0 : std_logic_vector(15 downto 0) := x"0020";
constant EPSTS_OVWR : std_logic_vector(15 downto 0) := x"0008";
constant EPSTS_SETUP : std_logic_vector(15 downto 0) := x"0004";
constant EPSTS_DBFIDX : std_logic_vector(15 downto 0) := x"0002";
constant ERRCODE_RXTX : std_logic_vector(15 downto 0) := x"0001";
constant ERRCODE_DPID : std_logic_vector(15 downto 0) := x"0040";
constant ERRCODE_OVRLP : std_logic_vector(15 downto 0) := x"0080";
constant ERRCODE_MASK : std_logic_vector(15 downto 0) := x"001E";
constant ERRCODE_OK : std_logic_vector(15 downto 0) := x"0000";
constant ERRCODE_PIDERR : std_logic_vector(15 downto 0) := x"0002";
constant ERRCODE_PIDNEW : std_logic_vector(15 downto 0) := x"0004";
constant ERRCODE_PKTTYP : std_logic_vector(15 downto 0) := x"0006";
constant ERRCODE_TKCRC : std_logic_vector(15 downto 0) := x"0008";
constant ERRCODE_DATACRC : std_logic_vector(15 downto 0) := x"000A";
constant ERRCODE_TIMEOUT : std_logic_vector(15 downto 0) := x"000C";
constant ERRCODE_RSRV0 : std_logic_vector(15 downto 0) := x"000E";
constant ERRCODE_EOP : std_logic_vector(15 downto 0) := x"0010";
constant ERRCODE_NAK : std_logic_vector(15 downto 0) := x"0012";
constant ERRCODE_STALL : std_logic_vector(15 downto 0) := x"0014";
constant ERRCODE_OVRFL : std_logic_vector(15 downto 0) := x"0016";
constant ERRCODE_RSRV1 : std_logic_vector(15 downto 0) := x"0018";
constant ERRCODE_BITSTUFF : std_logic_vector(15 downto 0) := x"001A";
constant ERRCODE_RSRV2 : std_logic_vector(15 downto 0) := x"001C";
constant ERRCODE_DATAPID : std_logic_vector(15 downto 0) := x"001E";
constant LOCK_IOEN : std_logic_vector(15 downto 0) := x"0001";
constant MODE_SOFTCONNECT : std_logic_vector(15 downto 0) := x"0001";
constant MODE_DBG : std_logic_vector(15 downto 0) := x"0004";
constant MODE_INT_EN : std_logic_vector(15 downto 0) := x"0008";
constant MODE_SUSPND : std_logic_vector(15 downto 0) := x"0020";
constant DEVCNFG_INTPOL : std_logic_vector(15 downto 0) := x"0001";
constant DEVCNFG_INTEDGE : std_logic_vector(15 downto 0) := x"0002";
constant DEVCNFG_PWROFF : std_logic_vector(15 downto 0) := x"0004";
constant DEVCNFG_WAKEUPBY_CS : std_logic_vector(15 downto 0) := x"0008";
constant DEVCNFG_EOTPOL : std_logic_vector(15 downto 0) := x"0010";
constant DEVCNFG_DMAACKPOL : std_logic_vector(15 downto 0) := x"0020";
constant DEVCNFG_DMARQPOL : std_logic_vector(15 downto 0) := x"0040";
constant DEVCNFG_DMAACKONLY : std_logic_vector(15 downto 0) := x"0080";
constant DEVCNFG_CLOCKDIV_MASK : std_logic_vector(15 downto 0) := x"0F00";
constant DEVCNFG_CLOCKRUNNING : std_logic_vector(15 downto 0) := x"1000";
constant DEVCNFG_NOLAZYCLOCK : std_logic_vector(15 downto 0) := x"2000";
constant DEVCNFG_EXPULLUP : std_logic_vector(15 downto 0) := x"4000";
constant INTSRC_BUSRESET : std_logic_vector(15 downto 0) := x"0001";
constant INTSRC_RESUME : std_logic_vector(15 downto 0) := x"0002";
constant INTSRC_SUSPEND : std_logic_vector(15 downto 0) := x"0004";
constant INTSRC_EOT : std_logic_vector(15 downto 0) := x"0008";
constant INTSRC_SOF : std_logic_vector(15 downto 0) := x"0010";
constant INTSRC_PSEUDO_SOF : std_logic_vector(15 downto 0) := x"0020";
constant INTSRC_SHORT_PACKET : std_logic_vector(15 downto 0) := x"0040";
constant INTSRC_EP0OUT : std_logic_vector(15 downto 0) := x"0100";
constant INTSRC_EP0IN : std_logic_vector(15 downto 0) := x"0200";
constant INTSRC_EP01 : std_logic_vector(15 downto 0) := x"0400";
constant INTSRC_EP02 : std_logic_vector(15 downto 0) := x"0800";
constant INTSRC_EP03 : std_logic_vector(15 downto 0) := x"1000";
constant INTSRC_EP04 : std_logic_vector(15 downto 0) := x"2000";
constant INTSRC_EP05 : std_logic_vector(15 downto 0) := x"4000";
constant INTSRC_EP06 : std_logic_vector(15 downto 0) := x"8000";
end package; | gpl-3.0 | 04f335195167de1505a7da445b47e2ea | 0.664293 | 2.978013 | false | false | false | false |
dugagjinll/MIPS | MIPS/MIPS.vhd | 1 | 1,379 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY MIPS IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC
);
END MIPS;
ARCHITECTURE Behavioral OF MIPS IS
SIGNAL se_in : std_logic_vector(15 DOWNTO 0) := x"7FFF";
SIGNAL se_out : std_logic_vector(31 DOWNTO 0) := x"00000000";
SIGNAL reg2 : std_logic_vector(31 DOWNTO 0) := x"12345678";
SIGNAL mux_ctl : std_logic := '1';
SIGNAL mux_out : std_logic_vector(31 DOWNTO 0) := x"00000000";
SIGNAL readAdress : std_logic_vector(31 DOWNTO 0) := x"00000000";
SIGNAL instruction : std_logic_vector(31 DOWNTO 0) := x"00000000";
SIGNAL programCounterIn : std_logic_vector(31 DOWNTO 0) := x"00400000";
SIGNAL programCounterOut : std_logic_vector(31 DOWNTO 0) := x"00000000";
BEGIN
--instantiate the ALU source mux
U1 : ENTITY work.Mux(Behavioral)
PORT MAP(
mux_in0 => reg2,
mux_in1 => se_out,
mux_ctl => mux_ctl,
mux_out => mux_out
);
-- instantiate a sign extender
U2 : ENTITY work.SignExtender(Behavioral)
PORT MAP(
se_in => instruction (15 downto 0),
se_out => se_out
);
U3 : ENTITY work.instructionMemory(Behavioral)
PORT MAP(
readAddress => readAdress,
instruction => programCounterOut
);
U4 : ENTITY work.programCounter(Behavioral)
PORT MAP(
programCounterIn => programCounterIn,
programCounterOut => programCounterOut
);
END Behavioral; | mit | e701a53fbd1f5339cdb41943a973be01 | 0.690355 | 3.11991 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/bB_32.vhd | 1 | 781 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bB is
port(S_GRB : in std_logic_vector(31 downto 0);
S_PR_F, S_MAR_F, S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(31 downto 0));
end bB;
architecture BEHAVIOR of bB is
begin
S_BUS_B <= S_GRB when S_s_ctl = "10000"
else "0000000000000000" & S_PR_F when S_s_ctl = "01000"
else "0000000000000000" & S_MAR_F when S_s_ctl = "00100"
else "0000000000000000" & S_MDR_F when S_s_ctl = "00010"
else "000000000000000000000000" & addr when S_s_ctl = "00001"
else "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end BEHAVIOR;
| mit | f75809596d32fbd4115b7d90260730b0 | 0.636364 | 2.969582 | false | false | false | false |
capitanov/MinesweeperFPGA | src/vga_main/ctrl_vga640x480.vhd | 1 | 5,417 | --------------------------------------------------------------------------------
--
-- Title : k_vga_controller
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : VGA controller for 60 Hz, 640x480 VGA Display
--
-- R G B Color
-- 0 0 0 Black
-- 0 0 1 Blue
-- 0 1 0 Green
-- 0 1 1 Cyan
-- 1 0 0 Red
-- 1 0 1 Magenta
-- 1 1 0 Yellow
-- 1 1 1 White
--
-- Sync:
--
-- Ts + Tbp + Tdisp + Tfp = Ttotal
-- T1 = Tbp + Tdisp + Tfp -- logic '1' for display time and front/back porch;
-- T0 = Ts -- logic '0' for sync impulse;
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity vga_ctrl640x480 is
port(
clk : in std_logic; -- pixel clk - DCM should generate 25 MHz freq;
reset : in std_logic; -- asycnchronous reset
h_sync : out std_logic; -- horiztonal sync pulse
v_sync : out std_logic; -- vertical sync pulse
disp : out std_logic; -- display enable '1'
x_out : out std_logic_vector(9 downto 0); -- x axis
y_out : out std_logic_vector(8 downto 0) -- y axis
);
end vga_ctrl640x480;
architecture vga640x480 of vga_ctrl640x480 is
-- horizontal
constant h_disp : integer := 640; -- display
constant h_s : integer := 96; -- sync pulse
constant h_fp : integer := 16; -- front porch
constant h_bp : integer := 48; -- back porch
constant h_t : integer := h_s + h_bp + h_disp + h_fp;
-- vertical
constant v_disp : integer := 480; -- display
constant v_s : integer := 2; -- sync pulse
constant v_fp : integer := 10; -- front porch
constant v_bp : integer := 36; -- back porch ( --29 - XilinX, 33 -- VESA standard)
constant v_t : integer := v_s + v_bp + v_disp + v_fp;
-- counters
signal cnt_h : integer range 0 to h_t - 1 := 0;
signal cnt_v : integer range 0 to v_t - 1 := 0;
signal vt, ht : std_logic;
-- synopsys translate_off
signal Tfp_h : std_logic;
signal Tbp_h : std_logic;
signal Tdi_h : std_logic;
signal Tsc_h : std_logic;
signal Ton_h : std_logic;
signal Tfp_v : std_logic;
signal Tbp_v : std_logic;
signal Tdi_v : std_logic;
signal Tsc_v : std_logic;
signal Ton_v : std_logic;
signal column : integer range 0 to 640-1 := 0; -- horizontal
signal row : integer range 0 to 480-1 := 0; -- vertical
-- synopsys translate_on
begin
pr_vga: process(reset, clk) is
begin
if reset = '0' then
cnt_h <= 0;
cnt_v <= 0;
vt <= '1';--'Z'; -- 1
ht <= '1';--'Z'; -- 1
disp <= '0';
x_out <= (others => '0');
y_out <= (others => '0');
elsif rising_edge(clk) then
-- counters
if (cnt_h < h_t - 1) then
cnt_h <= cnt_h + 1;
else
cnt_h <= 0;
if(cnt_v < v_t - 1) then
cnt_v <= cnt_v + 1;
else
cnt_v <= 0;
end if;
end if;
-- sync pulses
if (cnt_h < h_disp + h_fp or cnt_h >= h_disp + h_fp + h_s) then
ht <= '1' after 1 ns;
else
ht <= '0' after 1 ns;
end if;
if (cnt_v < v_disp + v_fp or cnt_v >= v_disp + v_fp + v_s) then
vt <= '1' after 1 ns;
else
vt <= '0' after 1 ns;
end if;
-- enable
if(cnt_h < h_disp and cnt_v < v_disp) then
disp <= '1' after 1 ns;
else
disp <= '0' after 1 ns;
end if;
-- row and colomn
if(cnt_h < h_disp) then
x_out <= std_logic_vector(to_unsigned(cnt_h,10)) after 1 ns;
end if;
if(cnt_v < v_disp) then
y_out <= std_logic_vector(to_unsigned(cnt_v,9)) after 1 ns;
end if;
end if;
end process;
h_sync <= ht;
v_sync <= vt;
-- synopsys translate_off
pr_coordinate: process(reset, clk) is
begin
if reset = '0' then
column <= 0;
row <= 0;
elsif rising_edge(clk) then
if(cnt_h < h_disp) then
column <= cnt_h;
end if;
if(cnt_v < v_disp) then
row <= cnt_v;
end if;
end if;
end process;
Ton_h <= Tfp_h or Tbp_h or Tdi_h;
pr_Thoriz: process(reset, clk) is
begin
if reset = '0' then
Tfp_h <= 'X';
Tbp_h <= 'X';
Tdi_h <= 'X';
Tsc_h <= 'X';
elsif rising_edge(clk) then
-- display
if (cnt_h < h_disp) then
Tdi_h <= '1';
else
Tdi_h <= '0';
end if;
-- back porch
if (cnt_h >= h_fp + h_disp + h_s) then
Tbp_h <= '1';
else
Tbp_h <= '0';
end if;
-- front porch
if (cnt_h >= h_disp and cnt_h < h_fp + h_disp) then
Tfp_h <= '1';
else
Tfp_h <= '0';
end if;
-- sync pulse
if (cnt_h >= h_disp + h_fp and cnt_h < h_fp + h_disp + h_s) then
Tsc_h <= '0';
else
Tsc_h <= 'Z';
end if;
end if;
end process;
Ton_v <= Tfp_v or Tbp_v or Tdi_v;
pr_Tvert: process(reset, clk) is
begin
if reset = '0' then
Tfp_v <= 'X';
Tbp_v <= 'X';
Tdi_v <= 'X';
Tsc_v <= 'X';
elsif rising_edge(clk) then
-- display
if (cnt_v < v_disp) then
Tdi_v <= '1';
else
Tdi_v <= '0';
end if;
-- back porch
if (cnt_v >= v_fp + v_disp + v_s) then
Tbp_v <= '1';
else
Tbp_v <= '0';
end if;
-- front porch
if (cnt_v >= v_disp and cnt_v < v_fp + v_disp) then
Tfp_v <= '1';
else
Tfp_v <= '0';
end if;
-- sync pulse
if (cnt_v >= v_disp + v_fp and cnt_v < v_fp + v_disp + v_s) then
Tsc_v <= '0';
else
Tsc_v <= 'Z';
end if;
end if;
end process;
-- synopsys translate_on
end vga640x480; | mit | bbf5a85fa34066a0e1efe37bcc1a4780 | 0.522245 | 2.472387 | false | false | false | false |
laurivosandi/vhdl-exercise | full_adder_testbench.vhd | 1 | 1,426 | library ieee;
use ieee.std_logic_1164.all;
entity full_adder_testbench is
end full_adder_testbench;
architecture behavior of full_adder_testbench is
component full_adder is
port (
a : in std_logic;
b : in std_logic;
ci : in std_logic;
s : out std_logic;
co : out std_logic);
end component;
signal input : std_logic_vector(2 downto 0);
signal output : std_logic_vector(1 downto 0);
begin
uut: full_adder port map (
a => input(0),
b => input(1),
ci => input(2),
s => output(0),
co => output(1)
);
stim_proc: process
begin
input <= "000"; wait for 10 ns; assert output = "00" report "0+0+0 failed";
input <= "001"; wait for 10 ns; assert output = "01" report "0+0+1 failed";
input <= "010"; wait for 10 ns; assert output = "01" report "0+1+0 failed";
input <= "100"; wait for 10 ns; assert output = "01" report "1+0+0 failed";
input <= "011"; wait for 10 ns; assert output = "10" report "0+1+1 failed";
input <= "110"; wait for 10 ns; assert output = "10" report "1+1+0 failed";
input <= "101"; wait for 10 ns; assert output = "10" report "1+0+1 failed";
input <= "111"; wait for 10 ns; assert output = "11" report "1+1+1 failed";
report "Full adder testbench finished";
wait;
end process;
end;
| mit | ea28e81f5e6df27546e9b47e30b3c498 | 0.56101 | 3.444444 | false | true | false | false |
fabianschuiki/moore | test/vhdl/seq_signal_assignment_0.vhd | 1 | 632 | entity foo is
end;
architecture bar of foo is
type bit is range 0 to 1;
type index is range 7 downto 0;
--type bits is array (index) of bit;
signal a,b : bit;
--signal c : bits;
begin
stim : process
begin
a <= 0;
b <= 0;
--c(7 downto 0) <= 0;
--(a, b) <= (0, 0);
-- simple assignment
a <= 0;
a <= 0 after 10 ns;
a <= null;
a <= null after 10 ns;
a <= unaffected;
a <= 0, 1;
a <= transport 0;
a <= inertial 0;
a <= reject 10 ns inertial 0;
a <= force in 0;
a <= force out 0;
a <= release in;
a <= release out;
-- conditional assignment
-- selected assignment
end process;
end;
| apache-2.0 | f17378662b1fe70f766d699e55942d18 | 0.568038 | 2.724138 | false | false | false | false |
Wynjones1/VHDL-Tests | src/cpu.vhd | 1 | 937 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.types.all;
entity cpu is
port(clk : in std_logic;
reset : in std_logic;
read_data : in reg_t;
addr : out reg16_t;
we : out std_logic;
write_data : out reg_t);
end entity;
architecture rtl of cpu is
type state_t is (state_idle, state_read_instr, state_decode_instr);
signal a, f, b, c, d, e, h, l : reg_t;
signal af, bc, de, hl, sp, pc : reg16_t;
signal state : state_t;
begin
datapath_proc:
process(clk, reset)
begin
end process;
control_proc:
process(clk, reset)
begin
if reset = '1' then
elsif rising_edge(clk) then
case state is
when state_idle =>
when state_read_instr =>
addr <= pc;
state <= state_decode_instr;
when state_decode_instr =>
end case;
end if;
end process;
af <= a & f;
bc <= b & c;
de <= d & e;
hl <= h & l;
end architecture;
| mit | 41e139edeb8caa4a0f6d7a9015eb94d7 | 0.599787 | 2.661932 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/gr.vhd | 1 | 3,721 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity gr is
port(clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(15 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(15 downto 0);
GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : out std_logic_vector(15 downto 0));
end gr;
architecture BEHAVIOR of gr is
signal S_GR0_F, S_GR1_F, S_GR2_F, S_GR3_F, S_GR4_F, S_GR5_F, S_GR6_F, S_GR7_F,
S_GR8_F, S_GR9_F, S_GR10_F, S_GR11_F, S_GR12_F, S_GR13_F, S_GR14_F, S_GR15_F
: std_logic_vector(15 downto 0);
begin
GR0_View <= S_GR0_F; GR1_View <= S_GR1_F; GR2_View <= S_GR2_F; GR3_View <= S_GR3_F;
GR4_View <= S_GR4_F; GR5_View <= S_GR5_F; GR6_View <= S_GR6_F; GR7_View <= S_GR7_F;
GR8_View <= S_GR8_F; GR9_View <= S_GR9_F; GR10_View <= S_GR10_F; GR11_View <= S_GR11_F;
GR12_View <= S_GR12_F; GR13_View <= S_GR13_F; GR14_View <= S_GR14_F; GR15_View <= S_GR15_F;
process(clk) begin
if clk'event and (clk = '1') and (S_GRlat = '1') then
case S_ctl_c is
when "0000" => S_GR0_F <= S_BUS_C;
when "0001" => S_GR1_F <= S_BUS_C;
when "0010" => S_GR2_F <= S_BUS_C;
when "0011" => S_GR3_F <= S_BUS_C;
when "0100" => S_GR4_F <= S_BUS_C;
when "0101" => S_GR5_F <= S_BUS_C;
when "0110" => S_GR6_F <= S_BUS_C;
when "0111" => S_GR7_F <= S_BUS_C;
when "1000" => S_GR8_F <= S_BUS_C;
when "1001" => S_GR9_F <= S_BUS_C;
when "1010" => S_GR10_F <= S_BUS_C;
when "1011" => S_GR11_F <= S_BUS_C;
when "1100" => S_GR12_F <= S_BUS_C;
when "1101" => S_GR13_F <= S_BUS_C;
when "1110" => S_GR14_F <= S_BUS_C;
when "1111" => S_GR15_F <= S_BUS_C;
when others => null;
end case;
end if;
end process;
process(S_GR0_F, S_GR1_F, S_GR2_F, S_GR3_F, S_GR4_F, S_GR5_F, S_GR6_F,
S_GR7_F, S_GR8_F, S_GR9_F, S_GR10_F, S_GR11_F, S_GR12_F, S_GR13_F,
S_GR14_F, S_GR15_F, S_ctl_a, S_ctl_b) begin
case S_ctl_a is
when "0000" => S_BUS_A <= S_GR0_F;
when "0001" => S_BUS_A <= S_GR1_F;
when "0010" => S_BUS_A <= S_GR2_F;
when "0011" => S_BUS_A <= S_GR3_F;
when "0100" => S_BUS_A <= S_GR4_F;
when "0101" => S_BUS_A <= S_GR5_F;
when "0110" => S_BUS_A <= S_GR6_F;
when "0111" => S_BUS_A <= S_GR7_F;
when "1000" => S_BUS_A <= S_GR8_F;
when "1001" => S_BUS_A <= S_GR9_F;
when "1010" => S_BUS_A <= S_GR10_F;
when "1011" => S_BUS_A <= S_GR11_F;
when "1100" => S_BUS_A <= S_GR12_F;
when "1101" => S_BUS_A <= S_GR13_F;
when "1110" => S_BUS_A <= S_GR14_F;
when "1111" => S_BUS_A <= S_GR15_F;
when others => null;
end case;
case S_ctl_b is
when "0000" => S_BUS_B <= S_GR0_F;
when "0001" => S_BUS_B <= S_GR1_F;
when "0010" => S_BUS_B <= S_GR2_F;
when "0011" => S_BUS_B <= S_GR3_F;
when "0100" => S_BUS_B <= S_GR4_F;
when "0101" => S_BUS_B <= S_GR5_F;
when "0110" => S_BUS_B <= S_GR6_F;
when "0111" => S_BUS_B <= S_GR7_F;
when "1000" => S_BUS_B <= S_GR8_F;
when "1001" => S_BUS_B <= S_GR9_F;
when "1010" => S_BUS_B <= S_GR10_F;
when "1011" => S_BUS_B <= S_GR11_F;
when "1100" => S_BUS_B <= S_GR12_F;
when "1101" => S_BUS_B <= S_GR13_F;
when "1110" => S_BUS_B <= S_GR14_F;
when "1111" => S_BUS_B <= S_GR15_F;
when others => null;
end case;
end process;
end BEHAVIOR;
| mit | 0119684f01a9fad4983b77f22143de77 | 0.500941 | 2.177297 | false | false | false | false |
fabianschuiki/moore | test/vhdl/seq_signal_assignment_2.vhd | 1 | 701 | entity foo is
end;
architecture bar of foo is
type bit is ('0','1');
type index is range 3 downto 0;
type bits is array (index) of bit;
signal a : bits;
--signal c : bits;
begin
stim : process
begin
a <= (others => '0');
a <= "0000";
--a <= 0;
--b <= 0;
----c(7 downto 0) <= 0;
----(a, b) <= (0, 0);
---- simple assignment
--a <= 0;
--a <= 0 after 10 ns;
--a <= null;
--a <= null after 10 ns;
--a <= unaffected;
--a <= 0, 1;
--a <= transport 0;
--a <= inertial 0;
--a <= reject 10 ns inertial 0;
--a <= force in 0;
--a <= force out 0;
--a <= release in;
--a <= release out;
-- conditional assignment
-- selected assignment
end process;
end;
| apache-2.0 | bd522b3b9fad80b06718a3a82cbe017f | 0.520685 | 2.675573 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/busA_32.vhd | 1 | 742 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
---SI=[MDR,GR,ADDRESS]
entity busA is
port(
clock: in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(31 downto 0);
ADDR : in std_logic_vector( 7 downto 0);
SI : in std_logic_vector( 2 downto 0);
busA_out : out std_logic_vector(31 downto 0)
);
end busA;
---architecture
architecture BEHAVIOR of busA is
begin
busA_out <= "0000000000000000" & MDR when SI = "001"
else GR when SI = "010"
else "000000000000000000000000" & ADDR when SI = "100"
else "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end BEHAVIOR;
| mit | 3eb0528bd962d1ce7c91a5e7b9119d0d | 0.587601 | 3.637255 | false | false | false | false |
fabianschuiki/moore | test/vhdl/type_decl.vhd | 1 | 1,943 | package foo is
-- enum_type_def
type foo;
type MULTI_LEVEL_LOGIC is (LOW, HIGH, RISING, FALLING, AMBIGUOUS);
type BIT is ('0','1');
type SWITCH_LEVEL is ('0','1','X');
-- integer_type_def
type TWOS_COMPLEMENT_INTEGER is range -32768 to 32767;
type BYTE_LENGTH_INTEGER is range 0 to 255;
type WORD_INDEX is range 31 downto 0;
-- floating_type_def
type bubba is range -1E18 to 1E18;
-- physical_type_def
type DURATION is range -1E18 to 1E18
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
end units;
type DISTANCE is range 0 to 1E16
units
-- primary unit:
Å;
-- metric lengths:
nm = 10 Å;
um = 1000 nm;
mm = 1000 um;
cm = 10 mm;
m = 1000 mm;
km = 1000 m;
-- English lengths:
mil = 254000 Å;
inch = 1000 mil;
ft = 12 inch;
yd = 3 ft;
fm = 6 ft;
mi = 5280 ft;
lg = 3 mi;
end units DISTANCE;
-- array_type_def
type MY_WORD is array (0 to 31) of BIT;
type DATA_IN is array (7 downto 0) of FIVE_LEVEL_LOGIC;
type MEMORY is array (INTEGER range <>) of MY_WORD;
type SIGNED_FXPT is array (INTEGER range <>) of BIT;
type SIGNED_FXPT_VECTOR is array (NATURAL range <>) of SIGNED_FXPT;
type SIGNED_FXPT_5x4 is array (1 to 5, 1 to 4) of SIGNED_FXPT;
type Word is array (NATURAL range <>) of BIT;
type Memory is array (NATURAL range <>) of Word (31 downto 0);
type E is array (NATURAL range <>) of INTEGER;
type T is array (1 to 10) of E (1 to 0);
-- record_type_def
type DATE is record
DAY : INTEGER range 1 to 31;
MONTH : MONTH_NAME;
YEAR : INTEGER range 0 to 4000;
end record;
type SIGNED_FXPT_COMPLEX is record
RE : SIGNED_FXPT;
IM : SIGNED_FXPT;
end record;
-- access_type_def
type ADDRESS is access MEMORY;
type BUFFER_PTR is access TEMP_BUFFER;
-- file_type_def
type A is file of STRING;
type B is file of NATURAL;
end;
| apache-2.0 | 2fefa9b991e65d8fbb0f34f47fae9d1a | 0.629897 | 2.836257 | false | false | false | false |
fabianschuiki/moore | test/vhdl/std_integer.vhd | 1 | 455 | entity foo is end;
architecture bar of foo is
constant xA : std.standard.INTEGER;
constant xB : INTEGER := -128;
constant xC : INTEGER := 127;
constant yA : std.standard.NATURAL;
constant yB : NATURAL := 0;
constant yC : NATURAL := 127;
constant zA : std.standard.POSITIVE;
constant zB : POSITIVE := 1;
constant zC : POSITIVE := 127;
constant uA : std.standard.INTEGER_VECTOR;
constant uB : INTEGER_VECTOR(0 to 1) := (-42, 42);
begin end;
| apache-2.0 | 51a7eb43db88836321d4764c7a8099f5 | 0.685714 | 3.116438 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_69x512_hf/example_design/fifo_69x512_hf_top_wrapper.vhd | 1 | 19,114 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_69x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_69x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(69-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(69-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_69x512_hf_top_wrapper;
architecture xilinx of fifo_69x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_69x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_69x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 26b72f4dd1054715ad0ea7e258ec5998 | 0.485508 | 3.962272 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_64x1024/example_design/fifo_fwft_64x1024_top.vhd | 1 | 4,974 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_64x1024_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_64x1024_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo_fwft_64x1024_top;
architecture xilinx of fifo_fwft_64x1024_top is
SIGNAL clk_i : std_logic;
component fifo_fwft_64x1024 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
fg0 : fifo_fwft_64x1024 PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 120040f0b186402863e6df2e97cb6a47 | 0.522316 | 4.886051 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x512/example_design/fifo_138x512_top_wrapper.vhd | 1 | 19,002 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_138x512_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_138x512_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(138-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(138-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_138x512_top_wrapper;
architecture xilinx of fifo_138x512_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_138x512_top is
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_138x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 4f00c9d164fd0a7acb0d6bcbeb387380 | 0.48658 | 3.966187 | false | false | false | false |
Mafus1/bluetooth-receiver | source/infrastructure.vhd | 1 | 812 | -- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY infrastructure IS
PORT(
clk : IN std_logic;
reset_n : IN std_logic;
serdata_in : IN std_logic;
serdata_out : OUT std_logic
);
END infrastructure;
-- Architecture Declaration
ARCHITECTURE rtl OF infrastructure IS
-- Signals & Constants Declaration
SIGNAL q1, q2: std_logic:= '0';
-- Begin Architecture
BEGIN
-------------------------------------------
-- Process for registers (flip-flops)
-------------------------------------------
flip_flops : PROCESS(clk, reset_n, q1)
BEGIN
IF reset_n = '0' THEN
q1 <= '0';
q2 <= '0';
ELSIF rising_edge(clk) THEN
q1 <= serdata_in;
q2 <= q1;
END IF;
END PROCESS flip_flops;
serdata_out <= q2;
END rtl;
| mit | c6de196929bb186eea8be783655857f3 | 0.57284 | 3.103448 | false | false | false | false |
Wynjones1/VHDL-Tests | simu/memory_tb.vhd | 1 | 1,737 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
entity memory_tb is
end memory_tb ;
architecture rtl of memory_tb is
signal clk : std_logic := '0';
signal reset : std_logic := '1';
signal address : std_logic_vector(15 downto 0);
signal we : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_out : std_logic_vector(7 downto 0) := (others => '0');
component memory is
port( clk : in std_logic;
address : in std_logic_vector;
we : in std_logic;
data_in : in std_logic_vector;
data_out : out std_logic_vector);
end component;
begin
mem0 : memory port map (clk, address, we, data_in, data_out);
-- Generate reset signal
process begin
reset <= '1';
wait for 30 ns;
reset <= '0';
wait;
end process;
-- Generate the clock signal
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
process(clk)
variable next_address : std_logic_vector(15 downto 0);
variable state : integer := 0;
begin
if reset = '1' then
we <= '0';
data_in <= (others => '0');
address <= (others => '0');
state := 0;
elsif rising_edge(clk) then
if state = 0 then
next_address := std_logic_vector(unsigned(address) + 1);
we <= '1';
data_in <= next_address(7 downto 0);
address <= next_address;
if unsigned(next_address) = 0 then
state := 1;
end if;
else
next_address := std_logic_vector(unsigned(address) + 1);
we <= '0';
address <= next_address;
if unsigned(next_address) = 0 then
state := 0;
end if;
end if;
end if;
end process;
end rtl;
| mit | e9c09144ccdd85456453dbc5312bec36 | 0.590098 | 2.91443 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_36x512_hf/example_design/fifo_36x512_hf_top_wrapper.vhd | 1 | 19,220 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_36x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_36x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(36-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(36-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_36x512_hf_top_wrapper;
architecture xilinx of fifo_36x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_36x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(36-1 DOWNTO 0);
DOUT : OUT std_logic_vector(36-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_36x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 78beea9d8df8eeda1fa3910480835492 | 0.484807 | 3.966976 | false | false | false | false |
Mafus1/bluetooth-receiver | source/start_bit_detect.vhd | 1 | 1,605 | -- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- Entity Declaration
ENTITY start_bit_detect IS
PORT(
clk : IN std_logic;
baud_tick : IN std_logic;
reset_n : IN std_logic;
edge : IN std_logic;
start_bit : OUT std_logic
);
END start_bit_detect;
-- Architecture Declaration
ARCHITECTURE rtl OF start_bit_detect IS
CONSTANT count_from : unsigned(3 downto 0) := to_unsigned(8,4);
CONSTANT count_to : unsigned(3 downto 0) := to_unsigned(0,4);
SIGNAL count, next_count : unsigned(3 downto 0);
-- Begin Architecture
BEGIN
--------------------------------------------------
-- PROCESS FOR COMBINATORIAL LOGIC
--------------------------------------------------
comb_logic: PROCESS(count, edge, baud_tick)
BEGIN
IF (count = count_to AND edge = '1') THEN
next_count <= count_from;
-- decrement
ELSIF (count > count_to AND baud_tick = '1') THEN
next_count <= count - 1 ;
-- freezes
ELSE
next_count <= count;
END IF;
END PROCESS comb_logic;
comb_logic_out: PROCESS(count, edge)
BEGIN
if(count = count_to AND edge = '1') THEN
start_bit <= '1';
ELSE
start_bit <= '0';
END IF;
END PROCESS comb_logic_out;
-------------------------------------------
-- Process for registers
-------------------------------------------
flip_flops : PROCESS(clk, reset_n)
BEGIN
IF reset_n = '0' THEN
count <= count_to; -- convert integer value 0 to unsigned with 4bits
ELSIF rising_edge(clk) THEN
count <= next_count;
END IF;
END PROCESS flip_flops;
END rtl;
| mit | eb95c9213c56e264f833fb6b5434fab4 | 0.572319 | 3.176238 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/core_32.vhd | 1 | 10,169 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity core is
end core;
architecture BEHAVIOR of core is
component clock is
port(
pulse : out std_logic
);
end component;
component alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(31 downto 0);
busB : in std_logic_vector(31 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(31 downto 0)
);
end component;
component bB is
port(
S_GRB : in std_logic_vector(31 downto 0);
S_PR_F, S_MAR_F, S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(31 downto 0)
);
end component;
component bC is
port(
S_BUS_C : inout std_logic_vector(31 downto 0)
);
end component;
component busA is
port(
clock : in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(31 downto 0);
ADDR : in std_logic_vector(7 downto 0);
SI : in std_logic_vector(2 downto 0);
busA_out : out std_logic_vector(31 downto 0)
);
end component;
component csgc is
port(
clk : in std_logic;
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0)
);
end component;
component fr is
port(
clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic
);
end component;
component gr is
port(
clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(31 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(31 downto 0);
GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : out std_logic_vector(31 downto 0)
);
end component;
component inst is
port(
clock : in std_logic;
busA : in std_logic_vector(31 downto 0);
latch : in std_logic;
Mlang : out std_logic_vector(15 downto 0)
);
end component;
component MAR is
port(
clk, lat : in std_logic;
busC : in std_logic_vector(31 downto 0);
M_ad16 : out std_logic_vector(15 downto 0);
M_ad8 : out std_logic_vector(7 downto 0)
);
end component;
component mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(31 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0)
);
end component;
component mem is
port(
clk, read, write : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0)
);
end component;
component pr is
port(
clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(31 downto 0);
S_PR_F : out std_logic_vector(15 downto 0)
);
end component;
-- clock
signal pulse : std_logic;
-- alu
signal alu_fr_z : std_logic;
signal alu_fr_s : std_logic;
signal alu_fr_o : std_logic;
-- bB
signal busb_alu : std_logic_vector(31 downto 0);
-- bC
signal alu_busc_others : std_logic_vector(31 downto 0);
-- busA
signal busa_alu_ir: std_logic_vector(31 downto 0);
-- csgc
signal csgc_busa_ctl : std_logic_vector(2 downto 0);
signal csgc_busb_ctl : std_logic_vector(4 downto 0);
signal csgc_busab_addr : std_logic_vector(7 downto 0);
signal csgc_gr_lat : std_logic;
signal csgc_gr_asel : std_logic_vector(3 downto 0);
signal csgc_gr_bsel : std_logic_vector(3 downto 0);
signal csgc_gr_csel : std_logic_vector(3 downto 0);
signal csgc_ir_lat : std_logic;
signal csgc_fr_lat : std_logic;
signal csgc_pr_lat : std_logic;
signal csgc_pr_cntup : std_logic;
signal csgc_mar_lat : std_logic;
signal csgc_mdr_lat : std_logic;
signal csgc_mdr_sel : std_logic;
signal csgc_mem_read : std_logic;
signal csgc_mem_write : std_logic;
signal csgc_alu_func : std_logic_vector(3 downto 0);
signal phaseView : std_logic_vector(3 downto 0);
-- fr
signal fr_alu_z : std_logic;
signal fr_alu_s : std_logic;
signal fr_alu_o : std_logic;
-- gr
signal gr_busa : std_logic_vector(31 downto 0);
signal gr_busb : std_logic_vector(31 downto 0);
signal GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : std_logic_vector(31 downto 0);
-- inst
signal ir_csgc : std_logic_vector(15 downto 0);
-- MAR
signal mar_busb : std_logic_vector(15 downto 0);
signal mar_mem : std_logic_vector(7 downto 0);
-- mdr
signal mdr_busab_mem : std_logic_vector(15 downto 0);
-- memory
signal mem_mdr : std_logic_vector(15 downto 0);
-- pr
signal pr_busb : std_logic_vector(15 downto 0);
begin
clock_a : clock port map(
pulse => pulse
);
alu_a : alu port map(
func => csgc_alu_func,
busA => busa_alu_ir,
busB => busb_alu,
inZ => fr_alu_z,
inS => fr_alu_s,
inO => fr_alu_o,
outZ => alu_fr_z,
outS => alu_fr_s,
outO => alu_fr_o,
busC => alu_busc_others
);
bB_a : bB port map(
S_GRB => gr_busb,
S_PR_F => pr_busb,
S_MAR_F => mar_busb,
S_MDR_F => mdr_busab_mem,
addr => csgc_busab_addr,
S_s_ctl => csgc_busb_ctl,
S_BUS_B => busb_alu
);
-- bC_a : bC port map(
-- S_BUS_C => alu_busc_others
-- );
busA_a : busA port map(
clock => pulse,
MDR => mdr_busab_mem,
GR => gr_busa,
ADDR => csgc_busab_addr,
SI => csgc_busa_ctl,
busA_out => busa_alu_ir
);
csgc_a : csgc port map(
clk => pulse,
mlang => ir_csgc,
ba_ctl => csgc_busa_ctl,
bb_ctl => csgc_busb_ctl,
address => csgc_busab_addr,
gr_lat => csgc_gr_lat,
gra => csgc_gr_asel,
grb => csgc_gr_bsel,
grc => csgc_gr_csel,
ir_lat => csgc_ir_lat,
fr_lat => csgc_fr_lat,
pr_lat => csgc_pr_lat,
pr_cnt => csgc_pr_cntup,
mar_lat => csgc_mar_lat,
mdr_lat => csgc_mdr_lat,
mdr_sel => csgc_mdr_sel,
m_read => csgc_mem_read,
m_write => csgc_mem_write,
func => csgc_alu_func,
phaseView => phaseView
);
fr_a : fr port map(
clk => pulse,
latch => csgc_fr_lat,
inZF => alu_fr_z,
inSF => alu_fr_s,
inOF => alu_fr_o,
outZF => fr_alu_z,
outSF => fr_alu_s,
outOF => fr_alu_o
);
gr_a : gr port map(
clk => pulse,
S_GRlat => csgc_gr_lat,
S_ctl_a => csgc_gr_asel,
S_ctl_b => csgc_gr_bsel,
S_ctl_c => csgc_gr_csel,
S_BUS_C => alu_busc_others,
S_BUS_A => gr_busa,
S_BUS_B => gr_busb,
GR0_View => GR0_View, GR1_View => GR1_View, GR2_View => GR2_View, GR3_View => GR3_View,
GR4_View => GR4_View, GR5_View => GR5_View, GR6_View => GR6_View, GR7_View => GR7_View,
GR8_View => GR8_View, GR9_View => GR9_View, GR10_View => GR10_View, GR11_View => GR11_View,
GR12_View => GR12_View, GR13_View => GR13_View, GR14_View => GR14_View, GR15_View => GR15_View
);
inst_a : inst port map(
clock => pulse,
busA => busa_alu_ir,
latch => csgc_ir_lat,
Mlang => ir_csgc
);
MAR_a : MAR port map(
clk => pulse,
lat => csgc_mar_lat,
busC => alu_busc_others,
M_ad16 => mar_busb,
M_ad8 => mar_mem
);
mdr_a : mdr port map(
clock => pulse,
busC => alu_busc_others,
latch => csgc_mdr_lat,
memo => mem_mdr,
sel => csgc_mdr_sel,
data => mdr_busab_mem
);
mem_a : mem port map(
clk => pulse,
read => csgc_mem_read,
write => csgc_mem_write,
S_MAR_F => mar_mem,
S_MDR_F => mdr_busab_mem,
data => mem_mdr
);
pr_a : pr port map(
clk => pulse,
S_PRlat => csgc_pr_lat,
S_s_inc => csgc_pr_cntup,
S_BUS_C => alu_busc_others,
S_PR_F => pr_busb
);
end BEHAVIOR;
| mit | 3062e939ed4a785caebd346a3aaa7f77 | 0.516963 | 3.152201 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_32x512/simulation/fg_tb_synth.vhd | 1 | 9,181 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_32x512_top
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | 672dfeb0fd9ae21bfc318bb978a3fdad | 0.453654 | 4.197988 | false | false | false | false |
Wynjones1/VHDL-Tests | src/alu.vhd | 1 | 5,344 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_misc.all;
use work.types.all;
entity alu is
port( op : in alu_op_t;
i0 : in reg_t;
i1 : in reg_t;
q : out reg_t;
flags_in : in reg_t;
flags_out : out reg_t);
end entity;
-- report "res " & integer'image(res);
architecture rtl of alu is
begin
process(op, i0, i1, flags_in)
constant RES_WIDTH : integer := i0'length + 1;
variable res_slv : std_logic_vector(RES_WIDTH - 1 downto 0);
variable res : unsigned(RES_WIDTH - 1 downto 0);
variable i0_int : unsigned(i0'length - 1 downto 0);
variable i1_int : unsigned(i1'length - 1 downto 0);
variable carry : unsigned(0 downto 0);
begin
i0_int := unsigned(i0);
i1_int := unsigned(i1);
carry := unsigned(flags_in(CARRY_BIT downto CARRY_BIT));
flags_out <= flags_in;
case op is
when alu_op_add =>
res := ('0' & i0_int) + i1_int;
res_slv := std_logic_vector(res);
q <= res_slv(7 downto 0);
flags_out(CARRY_BIT) <= res(8);
flags_out(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0));
res(4 downto 0) := ('0' & i0_int(3 downto 0)) + i1_int(3 downto 0);
flags_out(HALF_CARRY_BIT) <= res(4);
when alu_op_adc =>
res := (('0' & i0_int) + i1_int) + carry;
res_slv := std_logic_vector(res);
q <= res_slv(7 downto 0);
flags_out(CARRY_BIT) <= res(8);
flags_out(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0));
res(4 downto 0) := ('0' & i0_int(3 downto 0)) + i1_int(3 downto 0) + carry;
flags_out(HALF_CARRY_BIT) <= res(4);
when alu_op_and =>
q <= i0 and i1;
flags_out(ZERO_BIT) <= nor_reduce(i0 and i1);
flags_out(SUBTRACT_BIT) <= '0';
flags_out(CARRY_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '1';
when alu_op_bit => -- bit test, no output at q
flags_out(ZERO_BIT) <= not i0(to_integer(i1_int(2 downto 0)));
flags_out(SUBTRACT_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '1';
when alu_op_cp => -- compare op, no output at q
if i0_int < i1_int then
flags_out(CARRY_BIT) <= '1';
else
flags_out(CARRY_BIT) <= '0';
end if;
if i0_int(3 downto 0) < i1_int(3 downto 0) then
flags_out(HALF_CARRY_BIT) <= '1';
else
flags_out(HALF_CARRY_BIT) <= '0';
end if;
flags_out(ZERO_BIT) <= nor_reduce(std_logic_vector(i0_int - i1_int));
flags_out(SUBTRACT_BIT) <= '1';
when alu_op_cpl =>
q <= not i0;
flags_out(HALF_CARRY_BIT) <= '1';
flags_out(SUBTRACT_BIT) <= '1';
when alu_op_daa =>
when alu_op_or =>
q <= i0 or i1;
flags_out(ZERO_BIT) <= nor_reduce(i0 or i1);
flags_out(SUBTRACT_BIT) <= '0';
flags_out(CARRY_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '1';
when alu_op_rl =>
q <= i0(6 downto 0) & flags_in(CARRY_BIT);
flags_out(CARRY_BIT) <= i0(7);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= flags_in(CARRY_BIT) nor nor_reduce(i0(6 downto 0));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_rr =>
q <= flags_in(CARRY_BIT) & i0(7 downto 1);
flags_out(CARRY_BIT) <= i0(0);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= flags_in(CARRY_BIT) nor nor_reduce(i0(7 downto 1));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_rrc =>
q <= i0(0) & i0(7 downto 1);
flags_out(CARRY_BIT) <= i0(0);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= nor_reduce(i0);
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_sla =>
q <= i0(6 downto 0) & '0';
flags_out(CARRY_BIT) <= i0(7);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= nor_reduce(i0(6 downto 0));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_sra =>
q <= i0(7) & i0(7 downto 1);
flags_out(CARRY_BIT) <= i0(0);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= nor_reduce(i0(7 downto 1));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_srl =>
q <= '0' & i0(7 downto 1);
flags_out(CARRY_BIT) <= i0(0);
flags_out(HALF_CARRY_BIT) <= '0';
flags_out(ZERO_BIT) <= nor_reduce(i0(7 downto 1));
flags_out(SUBTRACT_BIT) <= '0';
when alu_op_sub =>
res := '0' & (i0_int - i1_int);
res_slv := std_logic_vector(res);
q <= res_slv(7 downto 0);
if i0_int < i1_int then
flags_out(CARRY_BIT) <= '1';
else
flags_out(CARRY_BIT) <= '0';
end if;
if i0_int(3 downto 0) < i1_int(3 downto 0) then
flags_out(HALF_CARRY_BIT) <= '1';
else
flags_out(HALF_CARRY_BIT) <= '0';
end if;
flags_out(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0));
flags_out(SUBTRACT_BIT) <= '1';
when alu_op_swap =>
q(3 downto 0) <= i0(7 downto 4);
q(7 downto 4) <= i0(3 downto 0);
flags_out(ZERO_BIT) <= nor_reduce(i0);
flags_out(CARRY_BIT) <= '0';
flags_out(SUBTRACT_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '0';
when alu_op_xor =>
res_slv(7 downto 0) := i0 xor i1;
flags_out(ZERO_BIT) <= nor_reduce(res_slv(7 downto 0));
flags_out(SUBTRACT_BIT) <= '0';
flags_out(CARRY_BIT) <= '0';
flags_out(HALF_CARRY_BIT) <= '1';
end case;
end process;
end rtl;
| mit | 64ab5c96810e584e9ac48e2cae1a175f | 0.541916 | 2.494865 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512/simulation/fg_tb_top.vhd | 1 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 67
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | e3d99c3976584a691573a0a3b97bdab8 | 0.616306 | 4.175735 | false | false | false | false |
kevintownsend/R3 | coregen/block_ram_64x1024/example_design/block_ram_64x1024_top.vhd | 1 | 5,421 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY block_ram_64x1024_top IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END block_ram_64x1024_top;
ARCHITECTURE xilinx OF block_ram_64x1024_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT block_ram_64x1024 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : block_ram_64x1024
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| mit | e31a8fa284915ac28eb568424a2f16b9 | 0.553588 | 4.525042 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_36x512_hf/simulation/fg_tb_top.vhd | 1 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 37
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | 93863f34ea0f18c85ecb30927d8512e6 | 0.616306 | 4.175735 | false | false | false | false |
Wynjones1/VHDL-Tests | src/vga_counter.vhd | 1 | 1,010 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity vga_counter is
generic( disp : integer;
fp : integer;
pw : integer;
bp : integer);
port( clk : in std_logic;
sync : out std_logic;
pix : out integer;
en : out std_logic);
end entity;
architecture rtl of vga_counter is
signal count_s : integer range 0 to (disp + fp + pw + bp - 1);
begin
process(clk)
begin
if rising_edge(clk) then
if count_s < disp - 1 then
sync <= '1';
en <= '1';
count_s <= count_s + 1;
elsif count_s < disp + fp - 1 then
sync <= '1';
en <= '0';
count_s <= count_s + 1;
elsif count_s < disp + fp + pw - 1 then
sync <= '0';
en <= '0';
count_s <= count_s + 1;
elsif count_s < disp + fp + pw + bp - 1 then
sync <= '1';
en <= '0';
count_s <= count_s + 1;
else
sync <= '1';
en <= '1';
count_s <= 0;
end if;
end if;
end process;
pix <= count_s;
end rtl;
| mit | 36461607bc6dfd6512ea04d8031827df | 0.510891 | 2.707775 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_64x512_hf/simulation/fg_tb_top.vhd | 1 | 5,679 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 480 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 65
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| mit | ea2bfa192c67a6364d6fd4671901a443 | 0.616306 | 4.175735 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/bB.vhd | 2 | 644 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bB is
port(S_GRB, S_PR_F, S_MAR_F, S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0));
end bB;
architecture BEHAVIOR of bB is
begin
S_BUS_B <= S_GRB when S_s_ctl = "10000"
else S_PR_F when S_s_ctl = "01000"
else S_MAR_F when S_s_ctl = "00100"
else S_MDR_F when S_s_ctl = "00010"
else "00000000" & addr when S_s_ctl = "00001"
else "XXXXXXXXXXXXXXXX";
end BEHAVIOR;
| mit | 1df89d4a1ee52343a4bf59adee00b8c6 | 0.608696 | 2.694561 | false | false | false | false |
e8johan/jamcpu | cpu_sys.vhd | 1 | 4,416 | ---------------------------------------------------------
-- JAM CPU
-- System shell wrapper
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
library ieee;
library work;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_unsigned."-";
entity cpu_sys is
port (
clk : in std_logic;
--reset key
k_en : out std_logic;
k_in : in std_logic;
--IM
im_cs : out std_logic_vector(7 downto 0);
im_oe : out std_logic;
im_write : out std_logic;
im_adr : out std_logic_vector( 16 downto 0 );
im_data : inout std_logic_vector( 63 downto 0 );
--DM
dm_cs : out std_logic_vector(7 downto 0);
dm_oe : out std_logic;
dm_write : out std_logic;
dm_adr : out std_logic_vector( 16 downto 0 );
dm_data : inout std_logic_vector( 63 downto 0 ));
end;
architecture rev1 of cpu_sys is
component cpu
port(
--clock and reset
clk, reset : in std_logic;
--in and out ports
inport : in std_logic_vector(31 downto 0);
outport : out std_logic_vector(31 downto 0);
--IO interface
synctrap : in std_logic;
put : out std_logic;
curpsw11_31 : out std_logic_vector(31 downto 11);
curpsw0_7 : out std_logic_vector(7 downto 0);
newpsw11_31 : in std_logic_vector(31 downto 11);
newpsw0_7 : in std_logic_vector(7 downto 0);
--IM
im_cs : out std_logic_vector(7 downto 0);
im_oe : out std_logic;
im_wri : out std_logic;
im_adr : out std_logic_vector( 16 downto 0 );
im_dat : inout std_logic_vector( 63 downto 0 );
--DM
dm_cs : out std_logic_vector(7 downto 0);
dm_oe : out std_logic;
dm_wri : out std_logic;
dm_adr : out std_logic_vector( 16 downto 0 );
dm_dat : inout std_logic_vector( 63 downto 0 ));
end component;
for cpu_core : cpu use entity work.cpu(rev1);
signal slow_clock : std_logic;
signal reset : std_logic;
signal inport : std_logic_vector( 31 downto 0 );
signal outport : std_logic_vector( 31 downto 0 );
signal synctrap : std_logic;
signal curpsw11_31 : std_logic_vector(31 downto 11);
signal curpsw0_7 : std_logic_vector(7 downto 0);
signal newpsw11_31 : std_logic_vector(31 downto 11);
signal newpsw0_7 : std_logic_vector(7 downto 0);
begin
--handle reset key on keypad
k_en <= '1';
reset <= k_in;
cpu_core : cpu port map(
--clock and reset
clk => slow_clock,
reset => reset,
--in and out ports
inport => inport,
outport => outport,
--IO interface
synctrap => synctrap,
curpsw11_31 => curpsw11_31,
curpsw0_7 => curpsw0_7,
newpsw11_31 => newpsw11_31,
newpsw0_7 => newpsw0_7,
--IM
im_cs => im_cs,
im_oe => im_oe,
im_wri => im_write,
im_adr => im_adr,
im_dat => im_data,
--DM
dm_cs => dm_cs,
dm_oe => dm_oe,
dm_wri => dm_write,
dm_adr => dm_adr,
dm_dat => dm_data);
--fake inport
inport <= "00000000000000000000000000101010";
--slow down clock
process(clk)
variable clockc : std_logic_vector(1 downto 0) := "00";
begin
if clk'event and clk='1' then
clockc := clockc + '1';
end if;
slow_clock <= clockc(1);
end process;
--STU timer
newpsw0_7 <= curpsw0_7;
process(slow_clock)
variable cc : std_logic_vector( 25 downto 0 );
begin
if slow_clock'event and slow_clock='1' then
if reset = '1' then
cc := "00000000000000000000000001";
synctrap <= '0';
newpsw11_31 <= curpsw11_31;
else
if cc = "00000000000000000000000000" then
cc(25 downto 10) := curpsw11_31(31 downto 16);
if curpsw11_31(15) = '0' then
synctrap <= '1';
newpsw11_31 <= curpsw11_31;
newpsw11_31(15) <= '1';
else
synctrap <= '0';
newpsw11_31 <= curpsw11_31;
end if;
else
synctrap <= '0';
newpsw11_31 <= curpsw11_31;
end if;
cc := cc - '1';
end if;
end if;
end process;
end;
| lgpl-2.1 | a0a4bf67cc9b052dbfc1a3668020c04f | 0.579257 | 3.022587 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_138x512/simulation/fg_tb_pkg.vhd | 1 | 11,250 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_138x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(138-1 DOWNTO 0);
DOUT : OUT std_logic_vector(138-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | e70e8e4efa597ea5e77bb95ebc1e9b9b | 0.504622 | 3.930818 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/test_core.vhd | 1 | 11,360 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity test_core is
end test_core;
architecture BEHAVIOR of test_core is
component clock is
port(
pulse : out std_logic
);
end component;
component alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0)
);
end component;
component bB is
port(
S_GRB, S_PR_F, S_MAR_F, S_MDR_F : in std_logic_vector(15 downto 0);
addr : in std_logic_vector(7 downto 0);
S_s_ctl : in std_logic_vector(4 downto 0);
S_BUS_B : out std_logic_vector(15 downto 0)
);
end component;
component bC is
port(
S_BUS_C : inout std_logic_vector(15 downto 0)
);
end component;
component busA is
port(
clock : in std_logic;
MDR : in std_logic_vector(15 downto 0);
GR : in std_logic_vector(15 downto 0);
ADDR : in std_logic_vector(7 downto 0);
SI : in std_logic_vector(2 downto 0);
busA_out : out std_logic_vector(15 downto 0)
);
end component;
component csgc is
port(
clk : in std_logic;
mlang : in std_logic_vector(15 downto 0);
ba_ctl : out std_logic_vector(2 downto 0);
bb_ctl : out std_logic_vector(4 downto 0);
address : out std_logic_vector(7 downto 0);
gr_lat : out std_logic;
gra : out std_logic_vector(3 downto 0);
grb : out std_logic_vector(3 downto 0);
grc : out std_logic_vector(3 downto 0);
ir_lat : out std_logic;
fr_lat : out std_logic;
pr_lat : out std_logic;
pr_cnt : out std_logic;
mar_lat : out std_logic;
mdr_lat : out std_logic;
mdr_sel : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
func : out std_logic_vector(3 downto 0);
phaseView : out std_logic_vector(3 downto 0)
);
end component;
component fr is
port(
clk : in std_logic;
latch : in std_logic;
inZF : in std_logic;
inSF : in std_logic;
inOF : in std_logic;
outZF : out std_logic;
outSF : out std_logic;
outOF : out std_logic
);
end component;
component gr is
port(
clk, S_GRlat : in std_logic;
S_ctl_a, S_ctl_b, S_ctl_c : in std_logic_vector(3 downto 0);
S_BUS_C : in std_logic_vector(15 downto 0);
S_BUS_A, S_BUS_B : out std_logic_vector(15 downto 0);
GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : out std_logic_vector(15 downto 0)
);
end component;
component inst is
port(
clock : in std_logic;
busA : in std_logic_vector(15 downto 0);
latch : in std_logic;
Mlang : out std_logic_vector(15 downto 0)
);
end component;
component MAR is
port(
clk, lat : in std_logic;
busC : in std_logic_vector(15 downto 0);
M_ad16 : out std_logic_vector(15 downto 0);
M_ad8 : out std_logic_vector(7 downto 0)
);
end component;
component mdr is
port(
clock : in std_logic;
busC : in std_logic_vector(15 downto 0);
latch : in std_logic;
memo : in std_logic_vector(15 downto 0);
sel : in std_logic;
data : out std_logic_vector(15 downto 0)
);
end component;
component test_mem is
port(
clk, read, write : in std_logic;
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0);
TB_switch : in std_logic;
TB_addr : in std_logic_vector(7 downto 0);
TB_w_data : in std_logic_vector(15 downto 0)
);
end component;
component pr is
port(
clk, S_PRlat, S_s_inc : in std_logic;
S_BUS_C : in std_logic_vector(15 downto 0);
S_PR_F : out std_logic_vector(15 downto 0)
);
end component;
-- clock
signal pulse : std_logic;
-- alu
signal alu_fr_z : std_logic;
signal alu_fr_s : std_logic;
signal alu_fr_o : std_logic;
-- bB
signal busb_alu : std_logic_vector(15 downto 0);
-- bC
signal alu_busc_others : std_logic_vector(15 downto 0);
-- busA
signal busa_alu_ir: std_logic_vector(15 downto 0);
-- csgc
signal csgc_busa_ctl : std_logic_vector(2 downto 0);
signal csgc_busb_ctl : std_logic_vector(4 downto 0);
signal csgc_busab_addr : std_logic_vector(7 downto 0);
signal csgc_gr_lat : std_logic;
signal csgc_gr_asel : std_logic_vector(3 downto 0);
signal csgc_gr_bsel : std_logic_vector(3 downto 0);
signal csgc_gr_csel : std_logic_vector(3 downto 0);
signal csgc_ir_lat : std_logic;
signal csgc_fr_lat : std_logic;
signal csgc_pr_lat : std_logic;
signal csgc_pr_cntup : std_logic;
signal csgc_mar_lat : std_logic;
signal csgc_mdr_lat : std_logic;
signal csgc_mdr_sel : std_logic;
signal csgc_mem_read : std_logic;
signal csgc_mem_write : std_logic;
signal csgc_alu_func : std_logic_vector(3 downto 0);
signal phaseView : std_logic_vector(3 downto 0);
-- fr
signal fr_alu_z : std_logic;
signal fr_alu_s : std_logic;
signal fr_alu_o : std_logic;
-- gr
signal gr_busa : std_logic_vector(15 downto 0);
signal gr_busb : std_logic_vector(15 downto 0);
signal GR0_View, GR1_View, GR2_View, GR3_View,
GR4_View, GR5_View, GR6_View, GR7_View,
GR8_View, GR9_View, GR10_View, GR11_View,
GR12_View, GR13_View, GR14_View, GR15_View : std_logic_vector(15 downto 0);
-- inst
signal ir_csgc : std_logic_vector(15 downto 0);
-- MAR
signal mar_busb : std_logic_vector(15 downto 0);
signal mar_mem : std_logic_vector(7 downto 0);
-- mdr
signal mdr_busab_mem : std_logic_vector(15 downto 0);
-- memory
signal mem_mdr : std_logic_vector(15 downto 0);
signal TB_switch : std_logic;
signal TB_addr : std_logic_vector(7 downto 0);
signal TB_w_data : std_logic_vector(15 downto 0);
-- pr
signal pr_busb : std_logic_vector(15 downto 0);
-- test_core
signal addr_in : std_logic_vector(7 downto 0) := "00000011";
signal switch_in : std_logic := '1';
begin
TB_switch <= switch_in;
clock_a : clock port map(
pulse => pulse
);
alu_a : alu port map(
func => csgc_alu_func,
busA => busa_alu_ir,
busB => busb_alu,
inZ => fr_alu_z,
inS => fr_alu_s,
inO => fr_alu_o,
outZ => alu_fr_z,
outS => alu_fr_s,
outO => alu_fr_o,
busC => alu_busc_others
);
bB_a : bB port map(
S_GRB => gr_busb,
S_PR_F => pr_busb,
S_MAR_F => mar_busb,
S_MDR_F => mdr_busab_mem,
addr => csgc_busab_addr,
S_s_ctl => csgc_busb_ctl,
S_BUS_B => busb_alu
);
-- bC_a : bC port map(
-- S_BUS_C => alu_busc_others
-- );
busA_a : busA port map(
clock => pulse,
MDR => mdr_busab_mem,
GR => gr_busa,
ADDR => csgc_busab_addr,
SI => csgc_busa_ctl,
busA_out => busa_alu_ir
);
csgc_a : csgc port map(
clk => pulse,
mlang => ir_csgc,
ba_ctl => csgc_busa_ctl,
bb_ctl => csgc_busb_ctl,
address => csgc_busab_addr,
gr_lat => csgc_gr_lat,
gra => csgc_gr_asel,
grb => csgc_gr_bsel,
grc => csgc_gr_csel,
ir_lat => csgc_ir_lat,
fr_lat => csgc_fr_lat,
pr_lat => csgc_pr_lat,
pr_cnt => csgc_pr_cntup,
mar_lat => csgc_mar_lat,
mdr_lat => csgc_mdr_lat,
mdr_sel => csgc_mdr_sel,
m_read => csgc_mem_read,
m_write => csgc_mem_write,
func => csgc_alu_func,
phaseView => phaseView
);
fr_a : fr port map(
clk => pulse,
latch => csgc_fr_lat,
inZF => alu_fr_z,
inSF => alu_fr_s,
inOF => alu_fr_o,
outZF => fr_alu_z,
outSF => fr_alu_s,
outOF => fr_alu_o
);
gr_a : gr port map(
clk => pulse,
S_GRlat => csgc_gr_lat,
S_ctl_a => csgc_gr_asel,
S_ctl_b => csgc_gr_bsel,
S_ctl_c => csgc_gr_csel,
S_BUS_C => alu_busc_others,
S_BUS_A => gr_busa,
S_BUS_B => gr_busb,
GR0_View => GR0_View, GR1_View => GR1_View, GR2_View => GR2_View, GR3_View => GR3_View,
GR4_View => GR4_View, GR5_View => GR5_View, GR6_View => GR6_View, GR7_View => GR7_View,
GR8_View => GR8_View, GR9_View => GR9_View, GR10_View => GR10_View, GR11_View => GR11_View,
GR12_View => GR12_View, GR13_View => GR13_View, GR14_View => GR14_View, GR15_View => GR15_View
);
inst_a : inst port map(
clock => pulse,
busA => busa_alu_ir,
latch => csgc_ir_lat,
Mlang => ir_csgc
);
MAR_a : MAR port map(
clk => pulse,
lat => csgc_mar_lat,
busC => alu_busc_others,
M_ad16 => mar_busb,
M_ad8 => mar_mem
);
mdr_a : mdr port map(
clock => pulse,
busC => alu_busc_others,
latch => csgc_mdr_lat,
memo => mem_mdr,
sel => csgc_mdr_sel,
data => mdr_busab_mem
);
mem_a : test_mem port map(
clk => pulse,
read => csgc_mem_read,
write => csgc_mem_write,
S_MAR_F => mar_mem,
S_MDR_F => mdr_busab_mem,
data => mem_mdr,
TB_switch => TB_switch,
TB_addr => TB_addr,
TB_w_data => TB_w_data
);
pr_a : pr port map(
clk => pulse,
S_PRlat => csgc_pr_lat,
S_s_inc => csgc_pr_cntup,
S_BUS_C => alu_busc_others,
S_PR_F => pr_busb
);
process(pulse) begin
if(pulse'event and (pulse and switch_in) = '1') then
TB_addr <= addr_in;
case addr_in is
when "00000000" =>
TB_w_data <= "0011000001110101";
when "00000001" =>
TB_w_data <= "0011000100010101";
when "00000010" =>
TB_w_data <= "0101000000000001";
when "11111111" =>
switch_in <= '0';
when others =>
null;
end case;
addr_in <= addr_in - "00000001";
else
null;
end if;
end process;
end BEHAVIOR;
| mit | 88c537fc96985da10e7770bfb4dba7d1 | 0.5125 | 3.214488 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/alu.vhd | 2 | 7,883 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port(
func : in std_logic_vector(3 downto 0);
busA : in std_logic_vector(15 downto 0);
busB : in std_logic_vector(15 downto 0);
inZ : in std_logic;
inS : in std_logic;
inO : in std_logic;
outZ : out std_logic;
outS : out std_logic;
outO : out std_logic;
busC : out std_logic_vector(15 downto 0)
);
end alu;
architecture BEHAVIOR of alu is
-- Definitions --
signal ans : std_logic_vector(15 downto 0);
signal atop : std_logic;
signal btop : std_logic;
signal ftop : std_logic;
signal shift_ov : std_logic;
-- Main --
begin
busC <= ans;
-- Calculate Process --
process(func, busA, busB) begin
case func is
when "0000" => -- select busA (not only HALT) --
ans <= busA;
when "0001" => -- select busB (not only LD1) --
ans <= busB;
when "0101" => -- ADD --
ans <= busA + busB;
when "0110" => -- SUB --
ans <= busA - busB;
when "0111" => -- SL --
if(busB = "0000000000010000") then
shift_ov <= busA(0); ans <= "0000000000000000";
elsif(busB > "0000000000010000") then
shift_ov <= '0'; ans <= "0000000000000000";
else
case busB(3 downto 0) is
when "0000" => shift_ov <= '0'; ans <= busA;
when "0001" => shift_ov <= busA(15); ans <= busA(14 downto 0) & '0';
when "0010" => shift_ov <= busA(14); ans <= busA(13 downto 0) & "00";
when "0011" => shift_ov <= busA(13); ans <= busA(12 downto 0) & "000";
when "0100" => shift_ov <= busA(12); ans <= busA(11 downto 0) & "0000";
when "0101" => shift_ov <= busA(11); ans <= busA(10 downto 0) & "00000";
when "0110" => shift_ov <= busA(10); ans <= busA( 9 downto 0) & "000000";
when "0111" => shift_ov <= busA( 9); ans <= busA( 8 downto 0) & "0000000";
when "1000" => shift_ov <= busA( 8); ans <= busA( 7 downto 0) & "00000000";
when "1001" => shift_ov <= busA( 7); ans <= busA( 6 downto 0) & "000000000";
when "1010" => shift_ov <= busA( 6); ans <= busA( 5 downto 0) & "0000000000";
when "1011" => shift_ov <= busA( 5); ans <= busA( 4 downto 0) & "00000000000";
when "1100" => shift_ov <= busA( 4); ans <= busA( 3 downto 0) & "000000000000";
when "1101" => shift_ov <= busA( 3); ans <= busA( 2 downto 0) & "0000000000000";
when "1110" => shift_ov <= busA( 2); ans <= busA( 1 downto 0) & "00000000000000";
when "1111" => shift_ov <= busA( 1); ans <= busA(0) & "000000000000000";
when others => shift_ov <= '0'; ans <= busA;
end case;
end if;
when "1000" => -- SR --
if(busB = "0000000000010000") then
shift_ov <= busA(15); ans <= "0000000000000000";
elsif(busB > "0000000000010000") then
shift_ov <= '0'; ans <= "0000000000000000";
else
case busB(3 downto 0) is
when "0000" => shift_ov <= '0'; ans <= busA;
when "0001" => shift_ov <= busA( 0); ans <= '0' & busA(15 downto 1);
when "0010" => shift_ov <= busA( 1); ans <= "00" & busA(15 downto 2);
when "0011" => shift_ov <= busA( 2); ans <= "000" & busA(15 downto 3);
when "0100" => shift_ov <= busA( 3); ans <= "0000" & busA(15 downto 4);
when "0101" => shift_ov <= busA( 4); ans <= "00000" & busA(15 downto 5);
when "0110" => shift_ov <= busA( 5); ans <= "000000" & busA(15 downto 6);
when "0111" => shift_ov <= busA( 6); ans <= "0000000" & busA(15 downto 7);
when "1000" => shift_ov <= busA( 7); ans <= "00000000" & busA(15 downto 8);
when "1001" => shift_ov <= busA( 8); ans <= "000000000" & busA(15 downto 9);
when "1010" => shift_ov <= busA( 9); ans <= "0000000000" & busA(15 downto 10);
when "1011" => shift_ov <= busA(10); ans <= "00000000000" & busA(15 downto 11);
when "1100" => shift_ov <= busA(11); ans <= "000000000000" & busA(15 downto 12);
when "1101" => shift_ov <= busA(12); ans <= "0000000000000" & busA(15 downto 13);
when "1110" => shift_ov <= busA(13); ans <= "00000000000000" & busA(15 downto 14);
when "1111" => shift_ov <= busA(14); ans <= "000000000000000" & busA(15);
when others => shift_ov <= '0'; ans <= busA;
end case;
end if;
when "1001" => -- NAND --
ans <= busA nand busB;
when "1010" => -- JMP --
ans <= busA; --------------------------- effective address
when "1011" => -- JZE --
if(inZ = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1100" => -- JMI --
if(inS = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1101" => -- JOV --
if(inO = '1') then
ans <= busA; ----------------------- effective address
else
ans <= busB + "0000000000000001"; -- program register
end if;
when "1110" => -- RJMP --
ans <= busA; --------------------------- general register
when "1111" => -- DISP --
ans <= "000000000000" & busA(3 downto 0);
when others =>
ans <= "XXXXXXXXXXXXXXXX";
end case;
end process;
-- GetTop Process --
process(busA, busB, ans) begin
atop <= busA(15);
btop <= busB(15);
ftop <= ans(15);
if(ans = "0000000000000000") then
outZ <= '1';
else
outZ <= '0';
end if;
end process;
-- Flag Process --
process(func, atop, btop, ftop) begin
case func is
when "0101" =>
if(((atop and btop) or (atop and not ftop) or (btop and not ftop)) = '1') then
outO <= '1';
else
outO <= '0';
end if;
when "0110" =>
if(((not atop and (btop or ftop)) or (btop and ftop)) = '1') then
outO <= '1';
else
outO <= '0';
end if;
when "0111" =>
outO <= shift_ov;
when "1000" =>
outO <= shift_ov;
when others =>
outO <= '0';
end case;
outS <= ftop;
end process;
end BEHAVIOR;
| mit | 06b75a5b37aae78a124fe4f59785e746 | 0.40378 | 4.377013 | false | false | false | false |
fabianschuiki/moore | test/vhdl/package_body.vhd | 1 | 645 | package body foo is end;
package body foo is end package body;
package body foo is end package body foo;
package body TriState is
function BitVal (Value: Tri) return Bit is
constant Bits : Bit_Vector := "0100";
begin
return Bits(Tri'Pos(Value));
end;
function TriVal (Value: Bit) return Tri is
begin
return Tri'Val(Bit'Pos(Value));
end;
function Resolve (Sources: TriVector) return Tri is
variable V: Tri := 'Z';
begin
for i in Sources'Range loop
if Sources(i) /= 'Z' then
if V = 'Z' then
V := Sources(i);
else
return 'E';
end if;
end if;
end loop;
return V;
end;
end package body TriState;
| apache-2.0 | 9636c62bff6c79d7a856cb73eb431d63 | 0.663566 | 3.042453 | false | false | false | false |
e8johan/jamcpu | sram.vhd | 1 | 2,382 | ---------------------------------------------------------
-- JAM CPU
-- Very simple SRAM model for simulation
--
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity sram is
generic (rom_data_file_name: string := "sram.dat");
port (ncs : in std_logic_vector( 3 downto 0 ); -- not chip select
addr : in std_logic_vector( 16 downto 0 );
data : inout std_logic_vector( 31 downto 0 );
nwe : in std_logic; -- not write enable
noe : in std_logic -- not output enable
);
end sram;
architecture behav of sram is
begin
mem: process
constant low_address: natural := 0;
constant high_address: natural := 131072; -- 128K SRAM
subtype word is std_logic_vector(31 downto 0 );
type memory_array is
array (natural range low_address to high_address) of word;
variable mem: memory_array;
variable address : natural;
begin
data <= (others => 'Z') ;
--
--
-- process memory cycles
--
loop
--
-- wait for chip-select,
--
if (ncs(0) = '0') then
-- decode address
address := conv_integer( addr );
--
if nwe = '0' then
--- write cycle
mem( address ) := data(31 downto 0);
data <= (others => 'Z');
elsif nwe = '1' then
-- read cycle
if noe = '0' then
data <= mem( address );
else
data <= (others => 'Z');
end if;
else
data <= (others => 'Z');
end if;
else
--
-- Chip not selected, disable output
--
data <= (others => 'Z');
end if;
wait on ncs, nwe, noe, addr, data;
end loop;
end process;
end behav;
| lgpl-2.1 | e437c5e229e3abb6bf44f265ee913673 | 0.490344 | 4.419295 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_fwft_96x512_hf/example_design/fifo_fwft_96x512_hf_top_wrapper.vhd | 1 | 19,250 | --------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_fwft_96x512_hf_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo_fwft_96x512_hf_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(96-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(9-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(9-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(96-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(9-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end fifo_fwft_96x512_hf_top_wrapper;
architecture xilinx of fifo_fwft_96x512_hf_top_wrapper is
SIGNAL clk_i : std_logic;
component fifo_fwft_96x512_hf_top is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(96-1 DOWNTO 0);
DOUT : OUT std_logic_vector(96-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : fifo_fwft_96x512_hf_top
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| mit | 678300eaccdd338ededee3809771e111 | 0.485299 | 3.963352 | false | false | false | false |
dugagjinll/MIPS | MIPS/shiftLeft.vhd | 1 | 441 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shiftLeft IS
GENERIC (
N : INTEGER := 2;
W : INTEGER := 32
);
PORT (
input : IN STD_LOGIC_VECTOR(W - 1 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(W - 1 DOWNTO 0)
);
END shiftLeft;
ARCHITECTURE Behavioral OF shiftLeft IS
BEGIN
output(W - 1) <= input(W - 1);
output(W - 2 DOWNTO N) <= input(W - 2 - N DOWNTO 0);
output(N - 1 DOWNTO 0) <= (OTHERS => '0');
END Behavioral; | mit | 9dc05e8d1fd9f328adb8d3f84df20de2 | 0.621315 | 2.882353 | false | false | false | false |
dugagjinll/MIPS | MIPS/registerFile.vhd | 1 | 1,976 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY registerFile IS
GENERIC (
B : INTEGER := 32; --number of bits
W : INTEGER := 5 --number of address bits
);
PORT (
readRegister1 : IN std_logic_vector (W - 1 DOWNTO 0);
readRegister2 : IN std_logic_vector (W - 1 DOWNTO 0);
writeRegister : IN std_logic_vector (W - 1 DOWNTO 0);
writeData : IN std_logic_vector (B - 1 DOWNTO 0);
registerWrite : IN std_logic;
readData1 : OUT std_logic_vector (B - 1 DOWNTO 0);
readData2 : OUT std_logic_vector (B - 1 DOWNTO 0)
);
END registerFile;
ARCHITECTURE Behavioral OF registerFile IS
-- create type 2d array
TYPE reg_file_type IS ARRAY (0 TO 2 ** W - 1) OF std_logic_vector(B - 1 DOWNTO 0);
-- create 32 registers of 32 bits
SIGNAL array_reg : reg_file_type := (
x"00000000", --$zero
x"11111111", --$at
x"22222222", --$v0
x"33333333", --$v1
x"44444444", --$a0
x"55555555", --$a1
x"66666666", --$a2
x"77777777", --$a3
x"88888888", --$t0
x"99999999", --$t1
x"aaaaaaaa", --$t2
x"bbbbbbbb", --$t3
x"cccccccc", --$t4
x"dddddddd", --$t5
x"eeeeeeee", --$t6
x"ffffffff", --$t7
x"00000000", --$s0
x"11111111", --$s1
x"22222222", --$s2
x"33333333", --$s3
x"44444444", --$s4
x"55555555", --$s5
x"66666666", --$s6
x"77777777", --$s7
x"88888888", --$t8
x"99999999", --$t9
x"aaaaaaaa", --$k0
x"bbbbbbbb", --$k1
x"10008000", --$global pointer
x"7FFFF1EC", --$stack pointer
x"eeeeeeee", --$frame pointer
x"ffffffff" --$return address
);
BEGIN
PROCESS (registerWrite) -- pulse on write
BEGIN
-- writeRegister is the register which we want to write to
-- writeData is the data which we dant to save
IF (registerWrite = '1') THEN
array_reg(to_integer(unsigned(writeRegister))) <= writeData;
END IF;
END PROCESS;
-- read port
readData1 <= array_reg(to_integer(unsigned(readRegister1)));
readData2 <= array_reg(to_integer(unsigned(readRegister2)));
END Behavioral; | mit | 4c01c2e1ad2ee2082963ca6e921e434f | 0.639676 | 2.888889 | false | false | false | false |
kevintownsend/R3 | coregen/block_ram_64x1024/example_design/bmg_wrapper.vhd | 1 | 10,520 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex5
-- C_XDEVICEFAMILY : virtex5
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 64
-- C_READ_WIDTH_A : 64
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 64
-- C_READ_WIDTH_B : 64
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT block_ram_64x1024_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : block_ram_64x1024_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| mit | 5cde04de77471487a7af7c39beaf5446 | 0.49097 | 3.838015 | false | false | false | false |
e8johan/jamcpu | alu.vhd | 1 | 3,859 | ---------------------------------------------------------
-- JAM CPU core
-- Simple ALU with shift
--
-- License: LGPL v2+ (see the file LICENSE)
-- Copyright © 2002:
-- Anders Lindström, Johan E. Thelin, Michael Nordseth
---------------------------------------------------------
-- This is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Library General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
entity ALU is
port(
op: in std_logic_vector(2 downto 0); -- ALU operation
inv_in2 : in std_logic; -- Invert operator in2
in1, in2: in std_logic_vector(31 downto 0); -- ALU input
ovf: out std_logic; -- ALU overflow
alu_out: out std_logic_vector(31 downto 0));-- ALU result
end;
architecture rev2 of ALU is
--ALU OPS
constant ALU_NOP: std_logic_vector(2 downto 0) := "000"; --pass in1
constant ALU_ADD: std_logic_vector(2 downto 0) := "001";
constant ALU_SUB: std_logic_vector(2 downto 0) := "010";
constant ALU_OR: std_logic_vector(2 downto 0) := "011";
constant ALU_AND: std_logic_vector(2 downto 0) := "100";
constant ALU_XOR: std_logic_vector(2 downto 0) := "101";
constant ALU_SHZ: std_logic_vector(2 downto 0) := "110"; --shift and fill with zero
constant ALU_SHS: std_logic_vector(2 downto 0) := "111"; --shift and fill with sign
constant zero32: std_logic_vector(31 downto 0) := (others => '0');
begin
process(op, in1, in2, inv_in2)
variable shiftin: std_logic_vector(63 downto 0);
variable shiftcnt: std_logic_vector(4 downto 0);
variable result: std_logic_vector(31 downto 0);
variable b_in: std_logic_vector(31 downto 0);
variable cin: std_logic;
begin
if (inv_in2 = '1') or (op = ALU_SUB) then
b_in := not in2;
cin := '1';
else
b_in := in2;
cin := '0';
end if;
if op = ALU_NOP then
ovf <= '0';
result := in1;
elsif ((op = ALU_ADD) or (op = ALU_SUB)) then
result := in1 + b_in + cin;
--overflow
if op = ALU_ADD then
ovf <= (in1(31) and in2(31) and not result(31)) or (result(31) and (not in1(31)) and (not in2(31)));
else
ovf <= (in1(31) and (not in2(31)) and not result(31)) or (result(31) and (not in1(31)) and in2(31));
end if;
elsif op = ALU_OR then
result := in1 or b_in;
ovf <= '0';
elsif op = ALU_AND then
result := in1 and b_in;
ovf <= '0';
elsif op = ALU_XOR then
result := in1 xor b_in;
ovf <= '0';
else
--shifter
if in2(31) = '1' then
shiftcnt := (not in2(4 downto 0)) + 1; --right
shiftin(31 downto 0) := in1;
if ((op = ALU_SHZ) or (in1(31) = '0')) then
shiftin(63 downto 32) := (others => '0');
else
shiftin(63 downto 32) := (others => '1');
end if;
else
shiftcnt := not in2(4 downto 0); --left
if ((op = ALU_SHZ) or (in1(31) = '0')) then
shiftin(31 downto 0) := (others => '0');
else
shiftin(31 downto 0) := (others => '1');
end if;
shiftin(63 downto 31) := '0' & in1;
end if;
if shiftcnt(4) = '1' then
shiftin(47 downto 0) := shiftin(63 downto 16);
end if;
if shiftcnt(3) = '1' then
shiftin(39 downto 0) := shiftin(47 downto 8);
end if;
if shiftcnt(2) = '1' then
shiftin(35 downto 0) := shiftin(39 downto 4);
end if;
if shiftcnt(1) = '1' then
shiftin(33 downto 0) := shiftin(35 downto 2);
end if;
if shiftcnt(0) = '1' then
shiftin(31 downto 0) := shiftin(32 downto 1);
end if;
result := shiftin(31 downto 0);
ovf <= '0';
end if;
alu_out <= result;
end process;
end;
| lgpl-2.1 | cbbaa9d743864046aa8f21d086ee5425 | 0.56284 | 3.007794 | false | false | false | false |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/YM2149/vol_table.vhd | 1 | 33,961 | -- generated with tablegen by MikeJ
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vol_table is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(9 downto 0)
);
end;
architecture RTL of vol_table is
function romgen_str2slv (str : string) return std_logic_vector is
variable result : std_logic_vector (str'length*4-1 downto 0);
begin
for i in 0 to str'length-1 loop
case str(str'high-i) is
when '0' => result(i*4+3 downto i*4) := x"0";
when '1' => result(i*4+3 downto i*4) := x"1";
when '2' => result(i*4+3 downto i*4) := x"2";
when '3' => result(i*4+3 downto i*4) := x"3";
when '4' => result(i*4+3 downto i*4) := x"4";
when '5' => result(i*4+3 downto i*4) := x"5";
when '6' => result(i*4+3 downto i*4) := x"6";
when '7' => result(i*4+3 downto i*4) := x"7";
when '8' => result(i*4+3 downto i*4) := x"8";
when '9' => result(i*4+3 downto i*4) := x"9";
when 'A' => result(i*4+3 downto i*4) := x"A";
when 'B' => result(i*4+3 downto i*4) := x"B";
when 'C' => result(i*4+3 downto i*4) := x"C";
when 'D' => result(i*4+3 downto i*4) := x"D";
when 'E' => result(i*4+3 downto i*4) := x"E";
when 'F' => result(i*4+3 downto i*4) := x"F";
when others => result(i*4+3 downto i*4) := "XXXX";
end case;
end loop;
return result;
end romgen_str2slv;
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
component RAMB4_S1
--pragma translate_off
generic (
INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"
);
--pragma translate_on
port (
DO : out std_logic_vector (0 downto 0);
DI : in std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (11 downto 0);
WE : in std_logic;
EN : in std_logic;
RST : in std_logic;
CLK : in std_logic
);
end component;
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
rom0 : if true generate
attribute INIT_00 of inst : label is "A3FF3C09E03755DF43AF510A88509D3598CB92F0A961B34BDC9EB90EBC9EF9B0";
attribute INIT_01 of inst : label is "D800C6FA0A6395DFAAAF531A6C54157058DB73B4696057CE5C971A5E7C9F388A";
attribute INIT_02 of inst : label is "6000F915F5986A225C1A2F6F9791E7BDA38FA4709571EB63AD8EC58E9C9EC7B0";
attribute INIT_03 of inst : label is "1C00040D089C9222A41A4F6F179107B5238B047415602B4A6C97654E1C9F478A";
attribute INIT_04 of inst : label is "EFFFF40DE8C91B07B42FCB10946EB44AA074A38B8A9F84B5EB68DAB19B60F875";
attribute INIT_05 of inst : label is "0FFF65D647760C68995AF46E23D44B7042F05F8F359F6BB51C6866716C600075";
attribute INIT_06 of inst : label is "C800CD56163C1C07D4247FF7249045B027F0448F0D9F67B520687C7254641470";
attribute INIT_07 of inst : label is "B4007DFAD1438123C92447EF04947DEB47EE65F07DD0626A45972E8D759B150F";
attribute INIT_08 of inst : label is "4000A1A97389B7E38F201AD0BD60DAB2F5F7B690DBA085CEC0118091B190F08D";
attribute INIT_09 of inst : label is "3C0036FBD8C6C6582120D59571170ECC45107108681076AE715127114210460C";
attribute INIT_0A of inst : label is "9400428534F9414305C03FDEE7E0BF0CCE379E1782AF84D2852FE5EDB4F8D0EC";
attribute INIT_0B of inst : label is "13FF36867E392B873398F6B6FF37BAECDDA8812187CEAE13A9A0F722D637B253";
attribute INIT_0C of inst : label is "24005466854A113B09F36379249B3DA22B9B4C385D743EE536C7403C7B891E9B";
attribute INIT_0D of inst : label is "240059E7958A37B44F343F3A3D395F2550FB40F97FFB3EFB06FB790444B963FB";
attribute INIT_0E of inst : label is "98006ADC7A14CD09F2890774ECAA9486CB4AC4B5865DE475DAA9E570A3829879";
attribute INIT_0F of inst : label is "BFFF4000BFFFA000A000A000A3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FF";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(0 downto 0),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom1 : if true generate
attribute INIT_00 of inst : label is "6000872EB8D53E8A305A5340563544CF31412DCA42242A045945633A5945238A";
attribute INIT_01 of inst : label is "47FFBA234D6A417567A5AEBFCDCABB358EBEB275FDDA95FAA6B29DC5E6BADD45";
attribute INIT_02 of inst : label is "DFFFBCD9470DD4AACC4AFD25A1B4A647D245C9CA9634C224F845A7BA9945E58A";
attribute INIT_03 of inst : label is "BC00472EB0F6BB5593B542DA5E4B59B02DBE363569DA3DFA46B278C566BA1A45";
attribute INIT_04 of inst : label is "A00048D1AF1D448A6C5A394A222525FA51CA4DBE0345694F3DDA22741DDA6230";
attribute INIT_05 of inst : label is "5FFFA727786BA8E2B50ACD2441B56ECA134A11BA7645024F29DA463479DA6230";
attribute INIT_06 of inst : label is "67FFFF27C929788A7C51CD4AC24AE5B591B58E45C1BA89B0B625C1CAD625E9CA";
attribute INIT_07 of inst : label is "D3FF8F230F95E6556AAEF2A5FDB5E25AAE5A91B5CE4AB3DA89B2BE47C9BED645";
attribute INIT_08 of inst : label is "A8006F71EFE2176AEB5574757AD5584A224A7FB5745A4E7A31B40E4B31B54E47";
attribute INIT_09 of inst : label is "F4009EDCA914E972FB55C1354AB53C7962B5594217B57FA5410B6EB4304A0FB9";
attribute INIT_0A of inst : label is "840016A63AEDCC6AB76A588B6B550B7944B51B4A59A5238A1D5A62A75C5D07A6";
attribute INIT_0B of inst : label is "EFFFCB58AC12E5EA610DB52B60555D6630DD73AA3564428A7CD50BAA15552E8A";
attribute INIT_0C of inst : label is "00003C38572CC2EDCDE57E9295F28A14BE0D9A2DDA69E717D0EA99D6A61DB8F2";
attribute INIT_0D of inst : label is "97FF2C475353AF665F19DB139EEDBCE983EDF3EDB3ED8C128BEDF2E9F412CFED";
attribute INIT_0E of inst : label is "E800E060F4581E5190AE25D8128C05570E2C756648D135262E8D0BD90953112E";
attribute INIT_0F of inst : label is "80003FFF7FFF6000600060006000600060006000600060006000600060006000";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(1 downto 1),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom2 : if true generate
attribute INIT_00 of inst : label is "1FFF714F62A6C55386D3982CA919D329A8D2D8D3A5099AD6C729E413F8D6DB6C";
attribute INIT_01 of inst : label is "3FFF7443D233FBD99689C96CBB2C97E69993D519A72CB0D39E648729E193F8D6";
attribute INIT_02 of inst : label is "3FFF7661DA51FA8CB52CCBF6F7668ED69529E72CCEE6A50998D69F6C8729E093";
attribute INIT_03 of inst : label is "7C00CEB09D58BE26F96676D356D22899476C2EE658D3672C219B18D61E6C0529";
attribute INIT_04 of inst : label is "6000C99E8DAE05536AD3302C0909732C68D31893252958D6672C651978D31AE6";
attribute INIT_05 of inst : label is "C0009147223352CC042C0BF7B766C6D3952CF76CAED6A52998D3DEE6E72CE519";
attribute INIT_06 of inst : label is "DFFFB6B85D8EFD53BAD9F42CC92CB366E8999929E76CD899EEF6A72CB10998D3";
attribute INIT_07 of inst : label is "B0004943A2599A26517706893499492C06D36899192C2AD32764192958934ED6";
attribute INIT_08 of inst : label is "5800A941424C8A33D1D9052631266ED3092C696616D3192C289926D217665929";
attribute INIT_09 of inst : label is "AC003860C5A75DDCDE26BB990E99352E3699502C6966168917D23966292C2691";
attribute INIT_0A of inst : label is "13FF083834B19E3355CCBD5391D98E2E8A99AE2CD176F6ACEBD38976952E9688";
attribute INIT_0B of inst : label is "C800AF60685C0E4C72515673DDD9C23782AEFE73C5C88F53B2A6B18CA5D98F53";
attribute INIT_0C of inst : label is "6400EF40E8B0784E76464FA36E5C645824517B8E043123A6334C3A581C5104A3";
attribute INIT_0D of inst : label is "2BFF4887A09CE4B8475E88A3284E284E544E2BB1144E185C1BB16BB16FA3644E";
attribute INIT_0E of inst : label is "5400AE806A9F5161E1CF409FC1CFBB67CEB0BB47B19E84B88E318F618F639F4F";
attribute INIT_0F of inst : label is "8000000000001FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(2 downto 2),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom3 : if true generate
attribute INIT_00 of inst : label is "F3FFB78FE5C7C09C026364B0CB5EE34EF463AB9C8CB19667D34EF35CEB98E8B0";
attribute INIT_01 of inst : label is "F3FFB683C543C49E023174B0CB4FA347D423A35E8CB09C639247934EF3DCEB98";
attribute INIT_02 of inst : label is "F3FFB681C561C5CF00B074B8C347B267DCB1B34FADB88CB19467934F934EF3DC";
attribute INIT_03 of inst : label is "F00086C08760854704B8FD9C626334214CB072472B9C0CB00C231467124F134E";
attribute INIT_04 of inst : label is "EC0080E097303F63959CBB4F34B13CB04B9C5423734E2B980CB00CA114631647";
attribute INIT_05 of inst : label is "CC00C8781ABC3A70FF4F8B473CB80D9C234F5CB07267734E6B9C2DB80CB00CA1";
attribute INIT_06 of inst : label is "CC00C93F38CF389CFA6180B00B4F434734212B4E4CB054217247734F634E6B9C";
attribute INIT_07 of inst : label is "83FF7F836561454744B87DCEC021F4B0CD9CB421AB4F899C8CB894B1D423D267";
attribute INIT_08 of inst : label is "3400207EDA8FBABC3B6180B83B470A6334B04B475D9C54B07421726363472B4E";
attribute INIT_09 of inst : label is "6FFFCE80A7380760C547FB21F5DEBF4FC2219B4FB4B8A231A3638B478B4F8DDE";
attribute INIT_0A of inst : label is "BC000EC0963E86BCCF70F89C7B610AB075DE4AB01B473DCF349C34B820B02230";
attribute INIT_0B of inst : label is "6BFF9180BE9F668F2A9E3143B89EC547FA308543808F8A9CBA38BB30BF61B563";
attribute INIT_0C of inst : label is "80005D800EC051706978E6C3269F5960669E3D3039411AC70A8F029F069E063C";
attribute INIT_0D of inst : label is "FBFF9AF8811FCAC056601EC35E8F2170768F5D3E4970416042C122C126C3268F";
attribute INIT_0E of inst : label is "080074FF58E0DD81BEF0CAE02EF011875F3F6E786EE06AC060C161816183718F";
attribute INIT_0F of inst : label is "800040003C00D7FFABFFA000BBFFBBFFBBFFBBFFBBFFBBFFBBFFBBFFBBFFBBFF";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(3 downto 3),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom4 : if true generate
attribute INIT_00 of inst : label is "9400220F52F8B2E00F7C8D3F799F0E703283391F3D3E2F786E704E6046E046C0";
attribute INIT_01 of inst : label is "94002303727CB2E00F3E8D3F798F4E7812C3319F3D3F2D7C2F782E704EE046E0";
attribute INIT_02 of inst : label is "94002301727EB2F00D3F8D3F71874F7812C1318F3D3F3D3E2D782E702E704EE0";
attribute INIT_03 of inst : label is "97FF1300327FF2780D3F8D1FF083CD3E82C0B087B91FBD3FBD3CAD78AF70AE70";
attribute INIT_04 of inst : label is "87FF1500323F727C0D1FC98FB2C1CD3F86E092C3B18FB91FBD3FBD3EAD7CAF78";
attribute INIT_05 of inst : label is "A7FF1580B73F777F0D8FF987B2C0FD1FCE7092C0B087B18FB91FBD3FBD3FBD3E";
attribute INIT_06 of inst : label is "A7FF15C0B50F751F0881F2C08670F187CD3EC67082C092C1B087B18FB18FB91F";
attribute INIT_07 of inst : label is "EBFF95FCAD814D87B2C072F08D3EF2C0FD1FCD3EC670C6E0C2C0D2C192C39087";
attribute INIT_08 of inst : label is "6800CA7F88F008C0F67E0D3F4987077C32C079876D1F6D3F4D3E4F7C4E784670";
attribute INIT_09 of inst : label is "7800EB00D23FB27FCD8709C172E04D8F0F3E167032C030C131833987398F3D1F";
attribute INIT_0A of inst : label is "17FF14FF3CC0CCC0327FF51F8981873FF2E0F8C0E987CD0FCD1FCD3FCD3FCF3F";
attribute INIT_0B of inst : label is "43FF9A002B1F530FE8E0027CF51FB27888C08D838D0F871FB73FB63FB27EB27C";
attribute INIT_0C of inst : label is "37FF2600EB0085802A7FD303ECE0B580931F8A3F8A7E88F888F088E08CE08CC0";
attribute INIT_0D of inst : label is "33FF5CFF9A1FEB00FC7F4B0334F01580430F4A3F4A7F4A7F48FE68FE6CFC6CF0";
attribute INIT_0E of inst : label is "F000B700DCFFC60124FF6B0054FF45F80BC02B802B002B002B012A012A033A0F";
attribute INIT_0F of inst : label is "DFFFC000300097FF83FF87FF9C009C009C009C009C009C009C009C009C009C00";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(4 downto 4),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom5 : if true generate
attribute INIT_00 of inst : label is "B800140FB4FFF4FF847F79C0021F047F34FC3DE039C03B807B807B807B007B00";
attribute INIT_01 of inst : label is "B8001403B47FF4FF843F79C0020F047F14FC35E039C039803B803B807B007B00";
attribute INIT_02 of inst : label is "B8001401B47FF4FF863F79C00A07047F14FE35F039C039C039803B803B807B00";
attribute INIT_03 of inst : label is "B8003400F47FF47F863F79E00B03063F04FF34F83DE039C039C039803B803B80";
attribute INIT_04 of inst : label is "A8003600F43F747F861F7DF04B01063F04FF14FC35F03DE039C039C039803B80";
attribute INIT_05 of inst : label is "A8003600F43F747F860F7DF84B00061F047F14FF34F835F03DE039C039C039C0";
attribute INIT_06 of inst : label is "A8003600F60F761F830174FF7B800A07063F047F04FF14FE34F835F035F03DE0";
attribute INIT_07 of inst : label is "AC003600E60146078B00F4FF79C00B00061F063F047F04FF04FF14FE14FC14F8";
attribute INIT_08 of inst : label is "2FFF2380C30003008B80863FFDF8FB80CB008207861F863F863F847F847F847F";
attribute INIT_09 of inst : label is "2FFF23FFCBC00B80B9F88201F4FFF9F0FBC0EB80CB00CB01CA03C207C20FC61F";
attribute INIT_0A of inst : label is "47FFC8FF08FF38FF747F89E08201843FF4FFFCFFFDF8F9F0F9E0F9C0F9C0FBC0";
attribute INIT_0B of inst : label is "13FF4C001C1FB40F6300747F89E08B8083008603860F841FB43FB43FB47FB47F";
attribute INIT_0C of inst : label is "5800D7FF23FFC9FF9C7F4BFC67007600741F7C3F7C7F7CFF7CFF7CFF78FF78FF";
attribute INIT_0D of inst : label is "A3FF0F00B3E023FF487F43FC77007600340F3C3F3C7F3C7F3CFF1CFF18FF18FF";
attribute INIT_0E of inst : label is "9FFF58000F00F7FEE8FFA3FFB700B600BC009C009C009C009C019C019C038C0F";
attribute INIT_0F of inst : label is "DFFFA0005FFF87FFAC00A800B000B000B000B000B000B000B000B000B000B000";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(5 downto 5),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom6 : if true generate
attribute INIT_00 of inst : label is "9FFF180F18FFE700E87F91FF93E09780A700AE00AE00AC00EC00EC00EC00EC00";
attribute INIT_01 of inst : label is "9FFF1803187FE700E83F91FF93F097808700A600AE00AE00AC00AC00EC00EC00";
attribute INIT_02 of inst : label is "9FFF1801187FE700E83F91FF93F897808700A600AE00AE00AE00AC00AC00EC00";
attribute INIT_03 of inst : label is "9FFF1800187FE780E83F91FF93FC97C09700A700AE00AE00AE00AE00AC00AC00";
attribute INIT_04 of inst : label is "8FFF1800183F6780E81F91FF93FE97C097008700A600AE00AE00AE00AE00AC00";
attribute INIT_05 of inst : label is "8FFF1800183F6780E80F91FF93FF97E097808700A700A600AE00AE00AE00AE00";
attribute INIT_06 of inst : label is "8FFF1800180F67E0EC0198FF93FF93F897C0978097008700A700A600A600AE00";
attribute INIT_07 of inst : label is "8FFF1800080157F8EC0098FF91FF93FF97E097C0978097009700870087008700";
attribute INIT_08 of inst : label is "0FFF0C002C0013FFEC00E83F91FF93FF93FF93F897E097C097C0978097809780";
attribute INIT_09 of inst : label is "0FFF0C002C0013FFEE00EC0198FF91FF93FF93FF93FF93FE93FC93F893F097E0";
attribute INIT_0A of inst : label is "27FF2F00EF0010FF6780EE00EC01E83F98FF90FF91FF91FF91FF91FF91FF93FF";
attribute INIT_0B of inst : label is "23FF2FFFEFE0180F73FF6780EE00EC00EC00E803E80FE81FD83FD83FD87FD87F";
attribute INIT_0C of inst : label is "200027FFF3FF2E00107F53FF77FF67FF67E06FC06F806F006F006F006F006F00";
attribute INIT_0D of inst : label is "7C00D0009C00F3FFAF80AC0098009800980F903F907F907F90FF90FF90FF90FF";
attribute INIT_0E of inst : label is "A0002000D00027FF0F000C00180018001000100010001000100110011003100F";
attribute INIT_0F of inst : label is "9FFF40002000A7FF8FFF8FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(6 downto 6),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom7 : if true generate
attribute INIT_00 of inst : label is "20005FF0A0FF47FF4F805E005C00580078007000700070003000300030003000";
attribute INIT_01 of inst : label is "20005FFCA07F47FF4FC05E005C00580058007800700070007000700030003000";
attribute INIT_02 of inst : label is "20005FFEA07F47FF4FC05E005C00580058007800700070007000700070003000";
attribute INIT_03 of inst : label is "20005FFFA07F47FF4FC05E005C00580058007800700070007000700070007000";
attribute INIT_04 of inst : label is "30005FFFA03FC7FF4FE05E005C00580058005800780070007000700070007000";
attribute INIT_05 of inst : label is "30005FFFA03FC7FF4FF05E005C00580058005800780078007000700070007000";
attribute INIT_06 of inst : label is "30005FFFA00FC7FF4FFE5F005C005C0058005800580058007800780078007000";
attribute INIT_07 of inst : label is "30005FFFB001E7FF4FFF5F005E005C0058005800580058005800580058005800";
attribute INIT_08 of inst : label is "B0004FFFB000A3FF4FFF4FC05E005C005C005C00580058005800580058005800";
attribute INIT_09 of inst : label is "B0004FFFB000A3FF4FFF4FFE5F005E005C005C005C005C005C005C005C005800";
attribute INIT_0A of inst : label is "B8004FFFB000A0FFC7FF4FFF4FFE4FC05F005F005E005E005E005E005E005C00";
attribute INIT_0B of inst : label is "BC004FFFB000A00FC3FFC7FF4FFF4FFF4FFF4FFC4FF04FE05FC05FC05F805F80";
attribute INIT_0C of inst : label is "BFFF47FFBC00B000A07FE3FFC7FFC7FFC7FFCFFFCFFFCFFFCFFFCFFFCFFFCFFF";
attribute INIT_0D of inst : label is "BFFF6000DFFFBC00B000B000A000A000A00FA03FA07FA07FA0FFA0FFA0FFA0FF";
attribute INIT_0E of inst : label is "C000BFFF600047FF4FFF4FFF5FFF5FFF5FFF5FFF5FFF5FFF5FFE5FFE5FFC5FF0";
attribute INIT_0F of inst : label is "E0008000BFFF3800300030002000200020002000200020002000200020002000";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(7 downto 7),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom8 : if true generate
attribute INIT_00 of inst : label is "C0009FFF3F007800700060006000600040004000400040004000400040004000";
attribute INIT_01 of inst : label is "C0009FFF3F807800700060006000600060004000400040004000400040004000";
attribute INIT_02 of inst : label is "C0009FFF3F807800700060006000600060004000400040004000400040004000";
attribute INIT_03 of inst : label is "C0009FFF3F807800700060006000600060004000400040004000400040004000";
attribute INIT_04 of inst : label is "C0009FFF3FC07800700060006000600060006000400040004000400040004000";
attribute INIT_05 of inst : label is "C0009FFF3FC07800700060006000600060006000400040004000400040004000";
attribute INIT_06 of inst : label is "C0009FFF3FF07800700060006000600060006000600060004000400040004000";
attribute INIT_07 of inst : label is "C0009FFF3FFE7800700060006000600060006000600060006000600060006000";
attribute INIT_08 of inst : label is "C0008FFF3FFF3C00700070006000600060006000600060006000600060006000";
attribute INIT_09 of inst : label is "C0008FFF3FFF3C00700070006000600060006000600060006000600060006000";
attribute INIT_0A of inst : label is "C0008FFF3FFF3F00780070007000700060006000600060006000600060006000";
attribute INIT_0B of inst : label is "C0008FFF3FFF3FF07C0078007000700070007000700070006000600060006000";
attribute INIT_0C of inst : label is "C00087FF3FFF3FFF3F807C007800780078007000700070007000700070007000";
attribute INIT_0D of inst : label is "C00080001FFF3FFF3FFF3FFF3FFF3FFF3FF03FC03F803F803F003F003F003F00";
attribute INIT_0E of inst : label is "FFFFC000800087FF8FFF8FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF";
attribute INIT_0F of inst : label is "FFFFFFFFC000C000C000C000C000C000C000C000C000C000C000C000C000C000";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(8 downto 8),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
rom9 : if true generate
attribute INIT_00 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
attribute INIT_01 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
attribute INIT_02 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
attribute INIT_03 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
attribute INIT_04 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
attribute INIT_05 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
attribute INIT_06 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
attribute INIT_07 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
attribute INIT_08 of inst : label is "FFFFF000C000C000800080008000800080008000800080008000800080008000";
attribute INIT_09 of inst : label is "FFFFF000C000C000800080008000800080008000800080008000800080008000";
attribute INIT_0A of inst : label is "FFFFF000C000C000800080008000800080008000800080008000800080008000";
attribute INIT_0B of inst : label is "FFFFF000C000C000800080008000800080008000800080008000800080008000";
attribute INIT_0C of inst : label is "FFFFF800C000C000C00080008000800080008000800080008000800080008000";
attribute INIT_0D of inst : label is "FFFFFFFFE000C000C000C000C000C000C000C000C000C000C000C000C000C000";
attribute INIT_0E of inst : label is "FFFFFFFFFFFFF800F000F000E000E000E000E000E000E000E000E000E000E000";
attribute INIT_0F of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
begin
inst : ramb4_s1
--pragma translate_off
generic map (
INIT_00 => romgen_str2slv(inst'INIT_00),
INIT_01 => romgen_str2slv(inst'INIT_01),
INIT_02 => romgen_str2slv(inst'INIT_02),
INIT_03 => romgen_str2slv(inst'INIT_03),
INIT_04 => romgen_str2slv(inst'INIT_04),
INIT_05 => romgen_str2slv(inst'INIT_05),
INIT_06 => romgen_str2slv(inst'INIT_06),
INIT_07 => romgen_str2slv(inst'INIT_07),
INIT_08 => romgen_str2slv(inst'INIT_08),
INIT_09 => romgen_str2slv(inst'INIT_09),
INIT_0A => romgen_str2slv(inst'INIT_0A),
INIT_0B => romgen_str2slv(inst'INIT_0B),
INIT_0C => romgen_str2slv(inst'INIT_0C),
INIT_0D => romgen_str2slv(inst'INIT_0D),
INIT_0E => romgen_str2slv(inst'INIT_0E),
INIT_0F => romgen_str2slv(inst'INIT_0F)
)
--pragma translate_on
port map (
DO => DATA(9 downto 9),
DI => "0",
ADDR => rom_addr,
WE => '0',
EN => '1',
RST => '0',
CLK => CLK
);
end generate;
end RTL;
| gpl-3.0 | 2a353a689d04e7db87231b68df27b67b | 0.699214 | 2.972777 | false | false | false | false |
dugagjinll/MIPS | MIPS/tb_alu_control.vhd | 1 | 1,298 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_alu_control IS
END tb_alu_control;
ARCHITECTURE behavior OF tb_alu_control IS
--Inputs
SIGNAL tb_funct : std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_ALUop : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_operation : std_logic_vector(3 DOWNTO 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : ENTITY work.alu_control(Behavioral)
PORT MAP(
funct => tb_funct,
ALUop => tb_ALUop,
operation => tb_operation
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- R-type commands (see green sheet)
tb_ALUop <= "10";
tb_funct <= "100100"; -- and
WAIT FOR 20 ns;
tb_ALUop <= "10";
tb_funct <= "100101"; -- or
WAIT FOR 20 ns;
tb_ALUop <= "10";
tb_funct <= "100000"; -- add
WAIT FOR 20 ns;
tb_ALUop <= "10";
tb_funct <= "100010"; -- sub
WAIT FOR 20 ns;
tb_ALUop <= "10";
tb_funct <= "101010"; -- slt
WAIT FOR 20 ns;
-- I type commands
-- load word command
tb_ALUop <= "00";
tb_funct <= "XXXXXX"; -- and
WAIT FOR 20 ns;
-- store word command
tb_ALUop <= "00";
tb_funct <= "XXXXXX"; -- and
WAIT FOR 20 ns;
-- branch equal command
tb_ALUop <= "00";
tb_funct <= "XXXXXX"; -- and
WAIT FOR 20 ns;
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; | mit | be1acf95780df25cf70625f5b6832f98 | 0.62943 | 2.821739 | false | false | false | false |
TMU-VHDL-team2/sqrt | components/old_data/MAR_32.vhd | 1 | 594 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity MAR is
port(
clk, lat: in std_logic;
busC : in std_logic_vector(31 downto 0);
M_ad16: out std_logic_vector(15 downto 0);
M_ad8: out std_logic_vector(7 downto 0)
);
end MAR;
architecture BEHAVIOR of MAR is
signal rst:std_logic_vector(15 downto 0);
begin
M_ad16 <= rst;
M_ad8 <= rst(7 downto 0);
process(clk)begin
if (clk'event and (clk = '1') and (lat ='1')) then
rst <= busC(15 downto 0);
else
null;
end if;
end process;
end BEHAVIOR;
| mit | aab8dcf07ab31a8f9ccf6fdce2f2fb06 | 0.614478 | 2.869565 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512_hf/simulation/fg_tb_pkg.vhd | 1 | 11,323 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_37x512_hf_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(1-1 DOWNTO 0);
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(37-1 DOWNTO 0);
DOUT : OUT std_logic_vector(37-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
| mit | 0facdbab5434a8236cbeafaf39f75776 | 0.504372 | 3.927506 | false | false | false | false |
mzakharo/usb-de2-fpga | sim/drv_tb.vhd | 1 | 2,428 | library work;
use work.isp_hal.all;
use work.isp_drv.all;
library ieee;
use ieee.NUMERIC_STD.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity drv_tb is
end drv_tb;
architecture TB_ARCHITECTURE of drv_tb is
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal otg_data : STD_LOGIC_VECTOR(15 downto 0);
signal otg_i : isp_hal_in_t;
signal otg_o : isp_hal_out_t;
signal drv_i : isp_drv_in_t;
signal drv_o : isp_drv_out_t;
--local signals
signal slowclk_en : bit;
signal isp_emu_data : std_logic_vector(15 downto 0);
--------------------------------------------------------------
-- clock cycle
constant period : time := 20 ns;
--------------------------------------------------------------
begin
--I/O
otg_i.drv <= drv_o.hal;
h: hal generic map(3) port map (clk, reset, otg_data , otg_i, otg_o);
--driver
drv_i.hal <= otg_o.drv;
d: drv port map(clk,reset, drv_i , drv_o);
----------------------------------------------------
-- clock
process
begin
clk <= '0';
wait for period/2;
clk <= '1';
wait for period/2;
end process;
--produces 25MHz clock enable for OTG
p_slowclk_en: process
begin
wait until rising_edge(clk);
slowclk_en <= not(slowclk_en);
end process;
otg_i.slowclk_en <= slowclk_en;
----------------------------------------------------
-- resets
process
begin
reset <= '1';
wait for period;
reset <= '0';
wait;
end process;
----------------------------------------------------
-- ISP read emulation
----------------------------------------------------
process
begin
otg_data <= (others => 'Z');
wait until falling_edge(otg_o.rd_n);
wait for 22 ns;
otg_data <= isp_emu_data;
wait until rising_edge(otg_o.cs_n);
wait for 3 ns;
end process;
----------------------------------------------------
-- ISP write emulation
----------------------------------------------------
process
begin
wait until falling_edge(otg_o.wr_n);
wait until rising_edge(otg_o.wr_n);
wait for 3 ns;
isp_emu_data <= otg_data;
end process;
end TB_ARCHITECTURE;
| gpl-3.0 | 8dc8c16ad10b436fac1aee80a9e750bf | 0.472405 | 3.68437 | false | false | false | false |
TMU-VHDL-team2/sqrt | fpga/mem.vhd | 1 | 1,587 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
entity mem is
port(clk, read, write : in std_logic;
init_phase : in std_logic_vector(3 downto 0);
input : in std_logic_vector(15 downto 0);
S_MAR_F : in std_logic_vector(7 downto 0);
S_MDR_F : in std_logic_vector(15 downto 0);
data : out std_logic_vector(15 downto 0));
end mem;
architecture BEHAVIOR of mem is
subtype RAM_WORD is std_logic_vector(15 downto 0);
type RAM_TYPE is array (0 to 255) of RAM_WORD;
impure function init_ram_file(RAM_FILE_NAME : in string) return RAM_TYPE is
file RAM_FILE : TEXT is in RAM_FILE_NAME;
variable RAM_FILE_LINE : line;
variable RAM_DIN : RAM_TYPE;
begin
for I in RAM_TYPE'range loop
readline(RAM_FILE, RAM_FILE_LINE);
hread(RAM_FILE_LINE, RAM_DIN(I));
end loop;
return RAM_DIN;
end function;
signal RAM_DATA : RAM_TYPE := init_ram_file("mem_fpga.txt");
signal addr : std_logic_vector(7 downto 0);
signal a : std_logic_vector(7 downto 0);
signal d : std_logic_vector(15 downto 0);
signal w : std_logic;
begin
a <= X"00" when (init_phase = X"1") else S_MAR_F;
d <= input when (init_phase = X"1") else S_MDR_F;
w <= '1' when (init_phase = X"1") else write;
data <= RAM_DATA(conv_integer(addr));
process(clk) begin
if clk'event and clk = '1' then
if w = '1' then
RAM_DATA(conv_integer(a)) <= d;
elsif read = '1' then
addr <= a;
else
null;
end if;
end if;
end process;
end BEHAVIOR;
| mit | 6ab5b52b9013fc6b3c99d63a869941cc | 0.645873 | 2.949814 | false | false | false | false |
kevintownsend/R3 | coregen/fifo_37x512/simulation/fg_tb_synth.vhd | 1 | 10,346 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 37,
C_DOUT_WIDTH => 37,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 37,
C_DIN_WIDTH => 37,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 37,
C_DIN_WIDTH => 37,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_37x512_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| mit | a46a4511face24c139b4f060896adcb6 | 0.460275 | 4.108817 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/switch_port_rx_path.vhd | 2 | 14,213 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 11.11.2013 14:33:32
-- Design Name:
-- Module Name: switch_port_0_rx_path - rtl
--
-- Description: This is the input port to the switch fabric
-- it consists of following modules:
-- - header extraction: extract the destination mac address from the current frame
-- - lookup module and lookup memory: determine the output ports for each incoming frame
-- - input queue module: merge the data and control path, store frame in memory and request access to crossbar matrix
--
-- further information can found in file rxpath.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_port_rx_path is
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer;
DEST_ADDR_WIDTH : integer := 48;
LOOKUP_MEM_ADDR_WIDTH : integer := 9;
LOOKUP_MEM_DATA_WIDTH : integer := 64
);
Port (
rx_path_clock : in std_logic;
rx_path_resetn : in std_logic;
-- mac to rx_path interface
rx_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_in_valid : in std_logic;
rx_in_last : in std_logic;
rx_in_error : in std_logic;
-- rx_path interface to fabric
rx_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
rx_out_valid : out std_logic;
rx_out_last : out std_logic;
rx_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
rx_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
rx_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
rx_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
rx_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- timestamp
rx_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0)
);
end switch_port_rx_path;
architecture rtl of switch_port_rx_path is
component rx_path_header_extraction
Generic (
RECEIVER_DATA_WIDTH : integer;
DEST_ADDR_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
hext_in_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
hext_in_valid : in std_logic;
hext_in_last : in std_logic;
hext_in_timestamp_cnt : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
-- output interface
hext_out_dest : out std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
hext_out_vlan_enable : out std_logic;
hext_out_vlan_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
hext_out_valid : out std_logic;
hext_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
hext_out_ready : in std_logic
);
end component;
component rx_path_lookup
Generic (
DEST_MAC_WIDTH : integer;
NR_PORTS : integer;
PORT_ID : integer;
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface
lookup_in_dest : in std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
lookup_in_vlan_enable : in std_logic;
lookup_in_vlan_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_in_valid : in std_logic;
lookup_in_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_in_ready : out std_logic;
-- output interface
lookup_out_ports : out std_logic_vector(NR_PORTS-1 downto 0);
lookup_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
lookup_out_skip : out std_logic;
lookup_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
lookup_out_valid : out std_logic;
-- lookup memory interface
mem_enable : out std_logic;
mem_addr : out std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0)
);
end component;
component rx_path_lookup_memory
Generic (
LOOKUP_MEM_ADDR_WIDTH : integer;
LOOKUP_MEM_DATA_WIDTH : integer
);
Port (
--Port A -> Processor
mem_in_wenable : in std_logic_vector(0 downto 0);
mem_in_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_in_data : in std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_in_clk : in std_logic;
--Port B -> Lookup module
mem_out_enable : in std_logic; --opt port
mem_out_addr : in std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
mem_out_data : out std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
mem_out_clk : in std_logic
);
end component;
component rx_path_input_queue
Generic (
RECEIVER_DATA_WIDTH : integer;
FABRIC_DATA_WIDTH : integer;
NR_PORTS : integer;
FRAME_LENGTH_WIDTH : integer;
NR_IQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer;
TIMESTAMP_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
-- input interface data
iq_in_mac_data : in std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
iq_in_mac_valid : in std_logic;
iq_in_mac_last : in std_logic;
iq_in_mac_error : in std_logic;
-- input interface control
iq_in_lu_ports : in std_logic_vector(NR_PORTS-1 downto 0);
iq_in_lu_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_in_lu_skip : in std_logic;
iq_in_lu_timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_in_lu_valid : in std_logic;
-- output interface arbitration
iq_out_ports_req : out std_logic_vector(NR_PORTS-1 downto 0);
iq_out_prio : out std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
iq_out_timestamp : out std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
iq_out_length : out std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
iq_out_ports_gnt : in std_logic_vector(NR_PORTS-1 downto 0);
-- output interface data
iq_out_data : out std_logic_vector(FABRIC_DATA_WIDTH-1 downto 0);
iq_out_last : out std_logic;
iq_out_valid : out std_logic
);
end component;
signal hext2lookup_dest : std_logic_vector(DEST_ADDR_WIDTH-1 downto 0);
signal hext2lookup_vlan_enable : std_logic;
signal hext2lookup_vlan_prio : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal hext2lookup_valid : std_logic;
signal hext2lookup_timestamp : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal hext2lookup_ready : std_logic;
signal mem2lookup_enable : std_logic;
signal mem2lookup_addr : std_logic_vector(LOOKUP_MEM_ADDR_WIDTH-1 downto 0);
signal mem2lookup_data : std_logic_vector(LOOKUP_MEM_DATA_WIDTH-1 downto 0);
signal lookup2iq_ports_sig : std_logic_vector(NR_PORTS-1 downto 0);
signal lookup2iq_prio_sig : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
signal lookup2iq_skip_sig : std_logic;
signal lookup2iq_timestamp : std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
signal lookup2iq_valid_sig : std_logic;
signal rx_path_reset : std_logic;
-- attribute mark_debug : string;
-- attribute mark_debug of hext2lookup_header : signal is "true";
-- attribute mark_debug of hext2lookup_valid : signal is "true";
-- attribute mark_debug of hext2lookup_ready : signal is "true";
-- attribute mark_debug of mem2lookup_enable : signal is "true";
-- attribute mark_debug of mem2lookup_addr : signal is "true";
-- attribute mark_debug of mem2lookup_data : signal is "true";
-- attribute mark_debug of lookup2iq_ports_sig : signal is "true";
-- attribute mark_debug of lookup2iq_skip_sig : signal is "true";
-- attribute mark_debug of lookup2iq_valid_sig : signal is "true";
-- attribute mark_debug of lookup2iq_ready_sig : signal is "true";
begin
-- can be moved to a higher layer lateron
rx_path_reset <= not rx_path_resetn;
header_extraction : rx_path_header_extraction
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
DEST_ADDR_WIDTH => DEST_ADDR_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface
hext_in_data => rx_in_data,
hext_in_valid => rx_in_valid,
hext_in_last => rx_in_last,
hext_in_timestamp_cnt => rx_in_timestamp_cnt,
-- output interface
hext_out_dest => hext2lookup_dest,
hext_out_vlan_enable => hext2lookup_vlan_enable,
hext_out_vlan_prio => hext2lookup_vlan_prio,
hext_out_valid => hext2lookup_valid,
hext_out_timestamp => hext2lookup_timestamp,
hext_out_ready => hext2lookup_ready
);
lookup : rx_path_lookup
Generic map(
DEST_MAC_WIDTH => DEST_ADDR_WIDTH,
NR_PORTS => NR_PORTS,
PORT_ID => PORT_ID,
LOOKUP_MEM_ADDR_WIDTH => LOOKUP_MEM_ADDR_WIDTH,
LOOKUP_MEM_DATA_WIDTH => LOOKUP_MEM_DATA_WIDTH,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface
lookup_in_dest => hext2lookup_dest,
lookup_in_vlan_enable => hext2lookup_vlan_enable,
lookup_in_vlan_prio => hext2lookup_vlan_prio,
lookup_in_valid => hext2lookup_valid,
lookup_in_timestamp => hext2lookup_timestamp,
lookup_in_ready => hext2lookup_ready,
-- output interface
lookup_out_ports => lookup2iq_ports_sig,
lookup_out_prio => lookup2iq_prio_sig,
lookup_out_skip => lookup2iq_skip_sig,
lookup_out_timestamp => lookup2iq_timestamp,
lookup_out_valid => lookup2iq_valid_sig,
-- lookup memory interface
mem_enable => mem2lookup_enable,
mem_addr => mem2lookup_addr,
mem_data => mem2lookup_data
);
lookup_memory : rx_path_lookup_memory
Generic map(
LOOKUP_MEM_ADDR_WIDTH => LOOKUP_MEM_ADDR_WIDTH,
LOOKUP_MEM_DATA_WIDTH => LOOKUP_MEM_DATA_WIDTH
)
Port map(
--Port A (write interface) -> Processor
mem_in_wenable => (others => '0'),
mem_in_addr => (others => '0'),
mem_in_data => (others => '0'),
mem_in_clk => '0',
--Port B (read interface) -> Lookup module
mem_out_enable => mem2lookup_enable,
mem_out_addr => mem2lookup_addr,
mem_out_data => mem2lookup_data,
mem_out_clk => rx_path_clock
);
input_queue : rx_path_input_queue
Generic map(
RECEIVER_DATA_WIDTH => RECEIVER_DATA_WIDTH,
FABRIC_DATA_WIDTH => FABRIC_DATA_WIDTH,
NR_PORTS => NR_PORTS,
FRAME_LENGTH_WIDTH => FRAME_LENGTH_WIDTH,
NR_IQ_FIFOS => NR_IQ_FIFOS,
VLAN_PRIO_WIDTH => VLAN_PRIO_WIDTH,
TIMESTAMP_WIDTH => TIMESTAMP_WIDTH
)
Port map(
clk => rx_path_clock,
reset => rx_path_reset,
-- input interface data
iq_in_mac_data => rx_in_data,
iq_in_mac_valid => rx_in_valid,
iq_in_mac_last => rx_in_last,
iq_in_mac_error => rx_in_error,
-- input interface control
iq_in_lu_ports => lookup2iq_ports_sig,
iq_in_lu_prio => lookup2iq_prio_sig,
iq_in_lu_skip => lookup2iq_skip_sig,
iq_in_lu_timestamp => lookup2iq_timestamp,
iq_in_lu_valid => lookup2iq_valid_sig,
-- output interface arbitration
iq_out_ports_req => rx_out_ports_req,
iq_out_prio => rx_out_prio,
iq_out_timestamp => rx_out_timestamp,
iq_out_length => rx_out_length,
iq_out_ports_gnt => rx_out_ports_gnt,
-- output interface data
iq_out_data => rx_out_data,
iq_out_last => rx_out_last,
iq_out_valid => rx_out_valid
);
end rtl;
| mit | d3eb41baea173eb7f4cff5a2395c729f | 0.539999 | 3.741248 | false | false | false | false |
lennartbublies/ecdsa | src/e_uart_transmit_mux.vhd | 1 | 4,672 | ----------------------------------------------------------------------------------------------------
-- ENTITY - Multiplexer for UART
--
-- Autor: Lennart Bublies (inf100434), Leander Schulz (inf102143)
-- Date: 29.06.2017
-- Last change: 22.10.2017
----------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.tld_ecdsa_package.all;
ENTITY e_uart_transmit_mux IS
PORT (
-- Clock and reset
clk_i : IN std_logic;
rst_i : IN std_logic;
-- ECDSA Mode (sign/verify)
mode_i : IN std_logic;
-- Enable flag
enable_i : IN std_logic;
-- Input
r_i : IN std_logic_vector(M-1 DOWNTO 0);
s_i : IN std_logic_vector(M-1 DOWNTO 0);
v_i : IN std_logic;
-- UART
uart_o : OUT std_logic
);
END e_uart_transmit_mux;
ARCHITECTURE rtl OF e_uart_transmit_mux IS
-- Import entity e_posi_register
COMPONENT e_nm_piso_register IS
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
enable_i : IN std_logic;
load_i : IN std_logic;
data_i : IN std_logic_vector(M-1 DOWNTO 0);
data_o : OUT std_logic_vector(U-1 DOWNTO 0)
);
END COMPONENT;
-- IMPORT UART COMPONENT
COMPONENT e_uart_transmit IS
GENERIC(
baud_rate : IN NATURAL RANGE 1200 TO 500000;
M : integer
);
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
mode_i : IN std_logic;
verify_i : IN std_logic;
start_i : IN std_logic;
data_i : IN std_logic_vector (7 DOWNTO 0);
tx_o : OUT std_logic;
reg_o : OUT std_logic;
reg_ena_o : OUT std_logic );
END COMPONENT e_uart_transmit;
-- Internal signals
SIGNAL s_uart_data_r: std_logic_vector(7 DOWNTO 0) := (OTHERS=>'0');
SIGNAL s_uart_data_s: std_logic_vector(7 DOWNTO 0) := (OTHERS=>'0');
SIGNAL s_enable_r, s_enable_s : std_logic := '0';
SIGNAL s_reg_ctrl : std_logic;
SIGNAL s_reg_ena : std_logic;
SIGNAL s_uart_data : std_logic_vector(7 DOWNTO 0) := (OTHERS=>'0');
SIGNAL s_enable_i_curr : std_logic;
SIGNAL s_enable_i_next : std_logic;
SIGNAL s_enable_i : std_logic;
BEGIN
-- Instantiate sipo register entity for r register
r_register: e_nm_piso_register PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => s_enable_r,
load_i => s_enable_i,
data_i => r_i,
data_o => s_uart_data_r
);
-- Instantiate sipo register entity for r register
s_register: e_nm_piso_register PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => s_enable_s,
load_i => s_enable_i,
data_i => s_i,
data_o => s_uart_data_s
);
-- Instantiate uart transmitter
transmit_instance : e_uart_transmit
GENERIC MAP (
baud_rate => BAUD_RATE,
M => M
) PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
mode_i => mode_i,
verify_i => v_i,
start_i => s_enable_i,
data_i => s_uart_data,
tx_o => uart_o,
reg_o => s_reg_ctrl,
reg_ena_o => s_reg_ena
);
-- multiplexer to control register inputs
s_uart_data <= s_uart_data_r WHEN (s_reg_ctrl = '0') ELSE s_uart_data_s;
--s_reg_ena <= enable_r_register WHEN (s_reg_ctrl = '0') ELSE enable_s_register;
-- demux for register enable port
PROCESS(s_reg_ena,s_reg_ctrl)
BEGIN
CASE s_reg_ctrl is
WHEN '0' => s_enable_r <= s_reg_ena;
s_enable_s <= '0';
WHEN OTHERS => s_enable_r <= '0';
s_enable_s <= s_reg_ena;
END CASE;
END PROCESS;
-- detect rising edge of enable_i
s_enable_i <= s_enable_i_next AND NOT s_enable_i_curr;
p_rising_enable : PROCESS(clk_i,rst_i,enable_i,s_enable_i_next)
BEGIN
IF rst_i = '1' THEN
s_enable_i_next <= '1';
s_enable_i_curr <= '1';
ELSIF rising_edge(clk_i) THEN
s_enable_i_next <= enable_i;
s_enable_i_curr <= s_enable_i_next;
END IF;
END PROCESS p_rising_enable;
END rtl;
| gpl-3.0 | 25fff2ea49415768f7089cd2ae6dabd1 | 0.480522 | 3.507508 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/mac/mac_fifo/switch_input_port_fifo.vhd | 2 | 3,520 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 18.11.2013 10:02:58
-- Design Name:
-- Module Name: switch_input_port_fifo - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description:
-- FIFO interface between MAC and switch port on the receive path
-- for decoupling clocks and data widths
-- bandwidth on user interface (read) must be higher than mac interface (write)
-- width = error_width + last_width + data_width
-- depth = 16 entries
-- see switch_mac_rxfifo.svg for further information
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_input_port_fifo is
generic (
GMII_DATA_WIDTH : integer;
RECEIVER_DATA_WIDTH : integer
);
port (
-- User-side interface (read)
rx_fifo_out_clk : in std_logic;
rx_fifo_out_reset : in std_logic;
rx_fifo_out_data : out std_logic_vector(RECEIVER_DATA_WIDTH-1 downto 0);
rx_fifo_out_valid : out std_logic;
rx_fifo_out_last : out std_logic;
rx_fifo_out_error : out std_logic;
-- MAC-side interface (write)
rx_fifo_in_clk : in std_logic;
rx_fifo_in_reset : in std_logic;
rx_fifo_in_data : in std_logic_vector(GMII_DATA_WIDTH-1 downto 0);
rx_fifo_in_valid : in std_logic;
rx_fifo_in_last : in std_logic;
rx_fifo_in_error : in std_logic
);
end switch_input_port_fifo;
architecture rtl of switch_input_port_fifo is
component fifo_generator_0 is
PORT (
wr_clk : IN std_logic := '0';
rd_clk : IN std_logic := '0';
valid : OUT std_logic := '0';
wr_rst : IN std_logic := '0';
rd_rst : IN std_logic := '0';
wr_en : IN std_logic := '0';
rd_en : IN std_logic := '0';
din : IN std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
dout : OUT std_logic_vector(RECEIVER_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
full : OUT std_logic := '0';
empty : OUT std_logic := '1'
);
end component;
signal din_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal dout_sig : std_logic_vector(GMII_DATA_WIDTH+2-1 DOWNTO 0) := (OTHERS => '0');
signal empty_sig : std_logic := '0';
signal rd_en_sig : std_logic := '0';
begin
-- FIFO input ports
din_sig <= rx_fifo_in_error & rx_fifo_in_last & rx_fifo_in_data;
rd_en_sig <= not empty_sig;
-- module output ports
rx_fifo_out_error <= dout_sig(RECEIVER_DATA_WIDTH+2-1);
rx_fifo_out_last <= dout_sig(RECEIVER_DATA_WIDTH+1-1);
rx_fifo_out_data <= dout_sig(RECEIVER_DATA_WIDTH-1 downto 0);
-- connecting the FIFO inputs and outputs
rx_fifo_ip : fifo_generator_0
PORT MAP (
wr_clk => rx_fifo_in_clk,
wr_rst => rx_fifo_in_reset,
wr_en => rx_fifo_in_valid,
din => din_sig,
full => open,
rd_clk => rx_fifo_out_clk,
rd_rst => rx_fifo_out_reset,
valid => rx_fifo_out_valid,
rd_en => rd_en_sig,
dout => dout_sig,
empty => empty_sig
);
end rtl;
| mit | f729d0c0491fd6e10335f03d26562c8f | 0.531534 | 3.220494 | false | false | false | false |
lennartbublies/ecdsa | src/e_sha256_functions.vhd | 1 | 5,121 | -- SHA256 Hashing Module - Functions
-- Kristian Klomsten Skordal <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sha256_types.all;
use work.sha256_constants.all;
package sha256_functions is
-- Function used to index arrays using std_logic_vector:
function index(input : in std_logic_vector) return integer;
-- Resets the intermediate hash values to their initial values:
procedure reset_intermediate(signal a, b, c, d, e, f, g, h : out std_logic_vector);
-- Calculates the j'th word of the message schedule:
function schedule(constant input : in std_logic_vector(31 downto 0);
constant W : in expanded_message_block_array;
constant iteration : in std_logic_vector(5 downto 0))
return std_logic_vector;
-- The SHA256 compression function for iteration j:
procedure compress(
-- Intermediate hash values from the previous iteration:
signal h0, h1, h2, h3, h4, h5, h6, h7 : inout std_logic_vector(31 downto 0);
-- The expanded message block value for this iteration:
constant W : in std_logic_vector(31 downto 0);
constant K : in std_logic_vector(31 downto 0));
-- Random mathematical functions used in SHA256:
function Ch(x, y, z : std_logic_vector) return std_logic_vector;
function Maj(x, y, z : std_logic_vector) return std_logic_vector;
-- Big sigma functions, using S because of lacking Unicode support:
function s0(x : std_logic_vector) return std_logic_vector;
function s1(x : std_logic_vector) return std_logic_vector;
-- Small sigma functions; using o which looks fairly similar:
function o0(x : std_logic_vector) return std_logic_vector;
function o1(x : std_logic_vector) return std_logic_vector;
end package sha256_functions;
package body sha256_functions is
function index(input : in std_logic_vector) return integer is
begin
return to_integer(unsigned(input));
end function index;
procedure reset_intermediate(signal a, b, c, d, e, f, g, h : out std_logic_vector) is
begin
a <= INITIAL_A;
b <= INITIAL_B;
c <= INITIAL_C;
d <= INITIAL_D;
e <= INITIAL_E;
f <= INITIAL_F;
g <= INITIAL_G;
h <= INITIAL_H;
end procedure reset_intermediate;
function schedule(constant input : in std_logic_vector(31 downto 0);
constant W : in expanded_message_block_array;
constant iteration : in std_logic_vector(5 downto 0))
return std_logic_vector
is
variable j : integer := index(iteration);
begin
if j < 16 then -- If j < 16 then W_j = M_j
return input;
else -- Else, W_j = o1(W_j-2) + W_j-7 + o0(W_j-15) + W_j-16
return std_logic_vector(unsigned(o1(W(j - 2))) +
unsigned(W(j - 7)) + unsigned(o0(W(j - 15))) + unsigned(W(j - 16)));
end if;
end function schedule;
procedure compress(
-- Intermediate hash values from the previous iteration:
signal h0, h1, h2, h3, h4, h5, h6, h7 : inout std_logic_vector(31 downto 0);
-- The expanded message block value for this iteration:
constant W : in std_logic_vector(31 downto 0);
-- The constant for this iteration:
constant K : in std_logic_vector(31 downto 0))
is
variable t1, t2 : std_logic_vector(31 downto 0);
variable a, b, c, d, e, f, g, h : std_logic_vector(31 downto 0);
begin
-- Assign intermediate hash values to working variables:
a := h0;
b := h1;
c := h2;
d := h3;
e := h4;
f := h5;
g := h6;
h := h7;
-- Calculate temporary values:
t1 := std_logic_vector(unsigned(h) + unsigned(s1(e))
+ unsigned(Ch(e, f, g)) + unsigned(K) + unsigned(W));
t2 := std_logic_vector(unsigned(s0(a)) + unsigned(Maj(a, b, c)));
-- Assign new values to working variables:
h := g;
g := f;
f := e;
e := std_logic_vector(unsigned(d) + unsigned(t1));
d := c;
c := b;
b := a;
a := std_logic_vector(unsigned(t1) + unsigned(t2));
-- Assign new values to the intermediate hash values:
h0 <= a;
h1 <= b;
h2 <= c;
h3 <= d;
h4 <= e;
h5 <= f;
h6 <= g;
h7 <= h;
end procedure compress;
function Ch(x, y, z : std_logic_vector) return std_logic_vector is
begin
return (x and y) xor ((not x) and z);
end function ch;
function Maj(x, y, z : std_logic_vector) return std_logic_vector is
begin
return (x and y) xor (x and z) xor (y and z);
end function maj;
function s0(x : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(rotate_right(unsigned(x), 2) xor rotate_right(unsigned(x), 13) xor rotate_right(unsigned(x), 22));
end function s0;
function s1(x : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(rotate_right(unsigned(x), 6) xor rotate_right(unsigned(x), 11) xor rotate_right(unsigned(x), 25));
end function s1;
function o0(x : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(rotate_right(unsigned(x), 7) xor rotate_right(unsigned(x), 18) xor shift_right(unsigned(x), 3));
end function o0;
function o1(x : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(rotate_right(unsigned(x), 17) xor rotate_right(unsigned(x), 19) xor shift_right(unsigned(x), 10));
end function o1;
end package body sha256_functions;
| gpl-3.0 | 1b7ad704e251c326b920e2bf72edce64 | 0.684046 | 2.916287 | false | false | false | false |
PhilippMundhenk/AutomotiveEthernetSwitch | aes_zc706/aes_zc706.srcs/sources_1/rtl/switch_port/rx/input_queue_memory.vhd | 2 | 2,738 | ----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 26.11.2013 17:14:16
-- Design Name:
-- Module Name: input_queue_memory - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: wrapper for the input queue memory
-- The input queue memory stores incoming frames until arbitration is succesful
-- input queue control modules handles frame storage for frames received from MAC
-- input queue arbitration handles memory read accesses
-- memory overflow is handled in input queue fifo by deleting the oldest frame in memory
--
-- more detailed information can found in file switch_port_rxpath_input_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity input_queue_memory is
Generic (
IQ_MEM_ADDR_WIDTH_A : integer;
IQ_MEM_ADDR_WIDTH_B : integer;
IQ_MEM_DATA_WIDTH_IN : integer;
IQ_MEM_DATA_WIDTH_OUT : integer
);
Port (
--Port A -> Control module
iqmem_in_wenable : in std_logic_vector;
iqmem_in_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
iqmem_in_data : in std_logic_vector(IQ_MEM_DATA_WIDTH_IN-1 downto 0);
iqmem_in_clk : in std_logic;
--Port B -> arbitration module -> switch fabric
iqmem_out_enable : in std_logic;
iqmem_out_addr : in std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
iqmem_out_data : out std_logic_vector(IQ_MEM_DATA_WIDTH_OUT-1 downto 0);
iqmem_out_clk : in std_logic
);
end input_queue_memory;
architecture rtl of input_queue_memory is
component blk_mem_gen_1 is
Port (
--Port A -> Control module
wea : in std_logic_vector;
addra : in std_logic_vector(IQ_MEM_ADDR_WIDTH_A-1 downto 0);
dina : in std_logic_vector(IQ_MEM_DATA_WIDTH_IN-1 downto 0);
clka : in std_logic;
--Port B -> arbitration module -> switch fabric
enb : in std_logic; --opt port
addrb : in std_logic_vector(IQ_MEM_ADDR_WIDTH_B-1 downto 0);
doutb : out std_logic_vector(IQ_MEM_DATA_WIDTH_OUT-1 downto 0);
clkb : in std_logic
);
end component;
begin
input_queue_mem_ip : blk_mem_gen_1
PORT MAP (
--Port A
wea => iqmem_in_wenable,
addra => iqmem_in_addr,
dina => iqmem_in_data,
clka => iqmem_in_clk,
--Port B
enb => iqmem_out_enable,
addrb => iqmem_out_addr,
doutb => iqmem_out_data,
clkb => iqmem_out_clk
);
end rtl;
| mit | be990bec71608b63fd00f2d98fa90de8 | 0.590942 | 3.435383 | false | false | false | false |
Nic30/hwtHdlParsers | hwtHdlParsers/tests/vhdlCodesign/vhdl/dmaWrap/dma_wrap.vhd | 1 | 414 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.misc_pkg.all;
entity dma_wrap is
generic(
C_BASE : string := "default";
C_ID : array_of_natural := (0 => 0);
C_CTRL_COUNT : positive := 1;
C_MBUS_MAX_ID_WIDTH : natural := 12);
port(
CTRL_INFO : out std_logic_vector(C_CTRL_COUNT - 1 downto 0)
);
end entity;
| mit | 5c4e00d33e86e7fba91a009b883e1b99 | 0.550725 | 2.855172 | false | false | false | false |
lennartbublies/ecdsa | src/e_gf2m_divider.vhd | 1 | 7,054 | ----------------------------------------------------------------------------------------------------
-- ENTITY - GF(2^M) Binary polynomial divider
-- Computes the g/h mod f IN GF(2**m)
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- g_i - First input value
-- h_i - Seccond input value
-- z_o - Output value
-- ready_o - Ready flag after computation
--
-- Example:
-- 1100101 / 1101 = 1001
--
-- BIT-SHIFT and XOR:
-- 1100101 / 1101 = 1001
-- 1101
-- 0011
-- 0000
-- 0110
-- 0000
-- 1101
-- 1101
-- 0 Remainder
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/binary_algorithm_polynomials.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 22.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) binary polynomial divider
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_divider IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0) := ONE
);
PORT(
-- Clock, reset and enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
-- Input signals
g_i: IN std_logic_vector(M-1 DOWNTO 0);
h_i: IN std_logic_vector(M-1 DOWNTO 0);
-- Output signals
z_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_divider;
ARCHITECTURE rtl of e_gf2m_divider IS
-- Internal signals
SIGNAL a : std_logic_vector(M DOWNTO 0);
SIGNAL b, c, d, next_b, next_d: std_logic_vector(M-1 DOWNTO 0);
SIGNAL alpha, beta, next_beta, dec_input: std_logic_vector(logM-1 DOWNTO 0);
SIGNAL ce_ac, ce_bd, load, beta_non_negative, alpha_gt_beta, b_zero: std_logic;
-- Define all available states
type states IS RANGE 0 TO 4;
SIGNAL current_state: states;
BEGIN
-- Load arguments for next computation
registers_ac: PROCESS(clk_i)
BEGIN
IF clk_i'event and clk_i = '1' THEN
-- First computation (global arguments)
IF load = '1' THEN
a <= MODULO;
c <= (OTHERS => '0');
-- Seccond computation
ELSIF ce_ac = '1' THEN
a <= '0'&b;
c <= d;
END IF;
END IF;
END PROCESS registers_ac;
registers_bd: PROCESS(clk_i)
BEGIN
IF clk_i'event and clk_i = '1' THEN
-- First computation (input arguments)
IF load = '1' THEN
b <= h_i;
d <= g_i;
-- Seccond computation
ELSIF ce_bd = '1' THEN
b <= next_b;
d <= next_d;
END IF;
END IF;
END PROCESS registers_bd;
register_alpha: PROCESS(clk_i)
BEGIN
IF clk_i'event and clk_i = '1' THEN
-- First computation (input arguments)
IF load = '1' THEN
alpha <= conv_std_logic_vector(M, logM);
-- Seccond computation
ELSIF ce_ac = '1' THEN
alpha <= beta;
END IF;
END IF;
END PROCESS register_alpha;
register_beta: PROCESS(clk_i)
BEGIN
IF clk_i'event and clk_i = '1' THEN
-- First computation (input arguments)
IF load = '1' THEN
beta <= conv_std_logic_vector(M-1, logM);
-- Seccond computation
ELSIF ce_bd = '1' THEN
beta <= next_beta;
END IF;
END IF;
END PROCESS register_beta;
-- Shift and Add
-- IF b(0)=0 THEN
-- next_b(i) = b(i+1)
-- ELSIF b(0)=1 THEN
-- next_b(i) = b(i+1) + a(i+1)
-- ENDIF
first_iteration: FOR i IN 0 TO M-2 GENERATE
next_b(i) <= (b(0) and (b(i+1) xor a(i+1))) or (not(b(0)) and b(i+1));
END GENERATE;
next_b(M-1) <= b(0) and a(M);
-- Shift and Add
-- IF b(0)=0 THEN
-- next_d(i) = (MODULO(i+1)&next_d(M-1)) + d(i+1) ????? (MODULO(i+1)&next_d(M-1)) ?????
-- ELSIF b(0)=1 THEN
-- next_d(i) = (MODULO(i+1)&next_d(M-1)) + d(i+1) + c(i+1) ????? (MODULO(i+1)&next_d(M-1)) ?????
-- ENDIF
second_iteration: FOR i IN 0 TO M-2 GENERATE
next_d(i) <= (MODULO(i+1) and next_d(M-1)) xor ((b(0) and (d(i+1) xor c(i+1))) or (not(b(0)) and d(i+1)));
END GENERATE;
next_d(M-1) <= (b(0) and (d(0) xor c(0))) or (not(b(0)) and d(0));
WITH ce_ac SELECT dec_input <= beta WHEN '0', alpha WHEN OTHERS;
next_beta <= dec_input - 1;
beta_non_negative <= '1' WHEN beta(logM-1) = '0' ELSE '0';
alpha_gt_beta <= '1' WHEN alpha > beta ELSE '0';
b_zero <= '1' WHEN b(0) = '0' ELSE '0';
-- Set output
z_o <= c;
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state, beta_non_negative, alpha_gt_beta, b_zero)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2 : Load input arguments
-- 3,4 : Calculation...
CASE current_state IS
WHEN 0 TO 1 =>
ce_ac <= '0'; ce_bd <='0'; load <= '0'; ready_o <= '1';
WHEN 2 =>
ce_ac <= '0'; ce_bd <= '0'; load <= '1'; ready_o <= '0';
WHEN 3 =>
IF beta_non_negative = '0' THEN
ce_ac <= '0'; ce_bd <= '0';
ELSIF b_zero = '1' THEN
ce_ac <= '0'; ce_bd <= '1';
ELSIF alpha_gt_beta = '1' THEN
ce_ac <= '1'; ce_bd <= '1';
ELSE
ce_ac <= '0'; ce_bd <= '1';
END IF;
load <= '0'; ready_o <='0';
WHEN 4 =>
ce_ac <= '0'; ce_bd <='0'; load <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF beta_non_negative = '0' THEN
current_state <= 4;
END IF;
WHEN 4 =>
current_state <= 0;
END CASE;
END IF;
END PROCESS control_unit;
END rtl;
| gpl-3.0 | 61a2ad4e29599693ea192d26dc5e1108 | 0.443436 | 3.521717 | false | false | false | false |
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