repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
diecaptain/fuzzy_kalman_mppt | kr_fuzman_Vt.vhd | 1 | 1,156 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Vt is
port
( clock : in std_logic;
Ut : in std_logic_vector(31 downto 0);
Vtminus : in std_logic_vector(31 downto 0);
Vt : out std_logic_vector(31 downto 0)
);
end kr_fuzman_Vt;
architecture struct of kr_fuzman_Vt is
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1 : std_logic_vector(31 downto 0);
signal M : std_logic_vector(31 downto 0) := "00111101010011001100110011001101";
begin
M1 : kn_kalman_mult port map (clock => clock, dataa => M, datab => Ut, result => Z1);
M2 : kn_kalman_add port map (clock => clock, dataa => Z1, datab => Vtminus, result => Vt);
end struct;
| mit | 7793c7d4b60979196e50d42204cd203d | 0.633218 | 3.220056 | false | false | false | false |
bonfireprocessor/bonfire-soc | spi/tb_spi_interface.vhd | 1 | 4,908 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:34 02/18/2017
-- Design Name:
-- Module Name: /home/thomas/riscv/lxp32soc/spi/tb_spi_interface.vhd
-- Project Name: bonfire
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: wb_spi_interface
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_spi_interface IS
END tb_spi_interface;
ARCHITECTURE behavior OF tb_spi_interface IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wb_spi_interface
PORT(
clk_i : IN std_logic;
reset_i : IN std_logic;
slave_cs_o : OUT std_logic;
slave_clk_o : OUT std_logic;
slave_mosi_o : OUT std_logic;
slave_miso_i : IN std_logic;
irq : OUT std_logic;
wb_adr_in : IN std_logic_vector(7 downto 0);
wb_dat_in : IN std_logic_vector(7 downto 0);
wb_dat_out : OUT std_logic_vector(7 downto 0);
wb_we_in : IN std_logic;
wb_cyc_in : IN std_logic;
wb_stb_in : IN std_logic;
wb_ack_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal slave_miso_i : std_logic := '0';
signal wb_adr_in : std_logic_vector(7 downto 0) := (others => '0');
signal wb_dat_in : std_logic_vector(7 downto 0) := (others => '0');
signal wb_we_in : std_logic := '0';
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
--Outputs
signal slave_cs_o : std_logic;
signal slave_clk_o : std_logic;
signal slave_mosi_o : std_logic;
signal irq : std_logic;
signal wb_dat_out : std_logic_vector(7 downto 0);
signal wb_ack_out : std_logic;
-- Clock period definitions
constant clk_i_period : time := 10 ns;
BEGIN
slave_miso_i <= slave_mosi_o; -- loop back
-- Instantiate the Unit Under Test (UUT)
uut: wb_spi_interface PORT MAP (
clk_i => clk_i,
reset_i => reset_i,
slave_cs_o => slave_cs_o,
slave_clk_o => slave_clk_o,
slave_mosi_o => slave_mosi_o,
slave_miso_i => slave_miso_i,
irq => irq,
wb_adr_in => wb_adr_in,
wb_dat_in => wb_dat_in,
wb_dat_out => wb_dat_out,
wb_we_in => wb_we_in,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_ack_out => wb_ack_out
);
-- Clock process definitions
clk_i_process :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- Stimulus process
stim_proc: process
variable d,t : std_logic_vector(7 downto 0);
procedure wb_write(address : in std_logic_vector(7 downto 0); data : in std_logic_vector(7 downto 0)) is
begin
wb_adr_in <= address;
wait until rising_edge(clk_i);
wb_dat_in <= data;
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wait until rising_edge(clk_i) and wb_ack_out = '1' ;
wb_stb_in <= '0';
wb_cyc_in <= '0';
end procedure;
procedure wb_read(address : in std_logic_vector(7 downto 0);
data: out std_logic_vector(7 downto 0) ) is
begin
wb_adr_in <= address;
wait until rising_edge(clk_i);
wb_we_in <= '1';
wb_cyc_in <= '1';
wb_stb_in <= '1';
wb_we_in <= '0';
wait until rising_edge(clk_i) and wb_ack_out = '1';
data:= wb_dat_out;
wb_stb_in <= '0';
wb_cyc_in <= '0';
--wait for clk_period;
end procedure;
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_i_period*10;
wb_write(X"10",X"01"); -- Clock Divider
wb_write(X"00",X"FE"); -- Chip Select
-- send 10 bytes
for i in 0 to 255 loop
t:=std_logic_vector(to_unsigned(i,t'length));
wb_write(X"08",t);
wb_read(X"0C",d);
if d /= t then
report "Failure";
wait;
end if;
end loop;
report "Success";
wait;
end process;
END;
| gpl-3.0 | 754fdd9b4e7cf96de4a3fb5d6f1eafb0 | 0.531581 | 3.361644 | false | false | false | false |
airlog/vhdl-rc4 | src/rc4_initer_tb.vhd | 1 | 5,675 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
ENTITY rc4_initer_tb IS
END rc4_initer_tb;
ARCHITECTURE behavior OF rc4_initer_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT rc4_initer
generic (
width: integer := 8
);
port (
CLK: in std_logic;
GO: in std_logic;
KEYLEN: in std_logic_vector((width - 1) downto 0);
MEMINPUT: in std_logic_vector((width - 1) downto 0);
KEYINPUT: in std_logic_vector((width - 1) downto 0);
KEYINDEX: out std_logic_vector((width - 1) downto 0);
MEMCTRL: out std_logic;
MEMINDEX: out std_logic_vector((width - 1) downto 0);
MEMOUTPUT: out std_logic_vector((width - 1) downto 0);
DONE: out std_logic
);
END COMPONENT;
-- Clock period definitions
constant CLK_period : time := 10 ns;
constant width : integer := 8;
constant permemsize : integer := 256;
constant keymemsize : integer := 2 ** width;
constant realkeylen : integer := 8;
-- Inputs
signal CLK : std_logic := '0';
signal GO : std_logic := '0';
signal KEYLEN : std_logic_vector(7 downto 0) := (others => '0');
signal MEMINPUT : std_logic_vector(7 downto 0) := (others => '0');
signal KEYINPUT : std_logic_vector(7 downto 0) := (others => '0');
-- Outputs
signal KEYINDEX : std_logic_vector(7 downto 0);
signal MEMCTRL : std_logic;
signal MEMINDEX : std_logic_vector(7 downto 0);
signal MEMOUTPUT : std_logic_vector(7 downto 0);
signal DONE : std_logic;
-- TB signals
signal DEBUG_IND : std_logic_vector((width - 1) downto 0);
signal DEBUG_VAL : std_logic_vector((width - 1) downto 0);
subtype rc4int is integer range 0 to 255;
type my_array is array (0 to (permemsize - 1)) of rc4int;
type key_array is array (0 to realkeylen - 1) of rc4int;
-- data
shared variable key : my_array := (
16#46#, 16#37#, 16#28#, 16#19#,
16#00#, 16#DC#, 16#EB#, 16#FA#,
others => 0
);
shared variable sarr : my_array := (others => 0);
-- expected data
shared variable sarr_expected : my_array := (
185, 126, 115, 175, 200, 169, 108, 155,
013, 041, 091, 189, 046, 116, 109, 163,
120, 020, 078, 049, 012, 038, 213, 142,
096, 094, 001, 178, 206, 067, 105, 148,
156, 055, 158, 073, 081, 145, 009, 132,
002, 050, 039, 172, 244, 243, 139, 166,
040, 201, 063, 164, 165, 207, 170, 167,
159, 118, 061, 010, 222, 247, 104, 089,
223, 087, 193, 110, 099, 071, 031, 128,
203, 135, 034, 015, 161, 174, 029, 225,
019, 103, 080, 162, 056, 154, 058, 133,
234, 209, 236, 023, 151, 051, 060, 232,
090, 176, 113, 121, 230, 212, 251, 093,
026, 245, 097, 003, 035, 191, 238, 199,
249, 181, 188, 192, 205, 182, 027, 146,
184, 195, 119, 028, 112, 235, 079, 048,
086, 018, 171, 198, 007, 130, 043, 254,
092, 076, 025, 147, 054, 150, 014, 123,
030, 211, 084, 229, 037, 237, 000, 168,
044, 157, 083, 246, 088, 137, 253, 064,
075, 069, 017, 057, 047, 036, 059, 220,
242, 006, 153, 129, 004, 052, 202, 042,
085, 144, 106, 177, 190, 117, 187, 008,
204, 070, 226, 194, 186, 127, 033, 138,
136, 024, 100, 124, 180, 095, 173, 045,
239, 072, 005, 219, 066, 149, 228, 179,
210, 141, 143, 082, 208, 217, 215, 218,
053, 125, 021, 131, 214, 231, 022, 250,
074, 224, 252, 102, 107, 221, 077, 240,
140, 068, 062, 248, 255, 233, 227, 122,
114, 016, 065, 160, 111, 101, 196, 098,
197, 032, 183, 152, 216, 241, 011, 134
);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc4_initer
generic map (
width => width
)
port map (
CLK => CLK,
GO => GO,
KEYLEN => KEYLEN,
MEMINPUT => MEMINPUT,
KEYINPUT => KEYINPUT,
KEYINDEX => KEYINDEX,
MEMCTRL => MEMCTRL,
MEMINDEX => MEMINDEX,
MEMOUTPUT => MEMOUTPUT,
DONE => DONE
);
-- Clock process definitions
CLK_process: process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- key memory mock
key_mem: process (clk)
variable index : rc4int := 0;
begin
if rising_edge(clk) then
index := conv_integer(unsigned(keyindex));
if index >= realkeylen then
assert False
report "Odczytano zbyt duza wartosc z pamieci klucza!"
severity warning;
end if;
keyinput <= conv_std_logic_vector(key(index), width);
end if;
end process;
-- permutation memory mock
perm_mem: process (clk)
variable index, value : rc4int := 0;
begin
if rising_edge(clk) then
index := conv_integer(unsigned(memindex));
if memctrl = '1' then
value := conv_integer(unsigned(memoutput));
sarr(index) := value;
-- assert False
-- report "value = " & integer'image(sarr(index))
-- severity info;
else
meminput <= conv_std_logic_vector(sarr(index), width);
end if;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
keylen <= conv_std_logic_vector(realkeylen, width);
go <= '1';
wait for 2 * clk_period;
-- czekaj na koniec dzialania
go <= '0';
while done = '0' loop
wait for clk_period / 2;
end loop;
keylen <= conv_std_logic_vector(0, width);
assert done = '1'
report "Praca jeszcze nie skonczona!"
severity failure;
for i in 0 to permemsize - 1 loop
debug_ind <= conv_std_logic_vector(i, width);
debug_val <= conv_std_logic_vector(sarr(i), width);
wait for clk_period;
assert sarr(i) = sarr_expected(i)
report "Niepoprawna wartosc!"
severity warning;
end loop;
wait;
end process;
END;
| mit | a61c8b0a2fc60ba30be19651c376bc6c | 0.602467 | 2.77235 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_fcmp_32ns_32ns_1_1.vhd | 1 | 4,446 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fcmp_32ns_32ns_1_1 is
generic (
ID : integer := 5;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fcmp_32ns_32ns_1_1 is
--------------------- Component ---------------------
component ANN_ap_fcmp_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fcmp_0_no_dsp_32_u : component ANN_ap_fcmp_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
| gpl-3.0 | 7cae5c901829461b6a0496108592520d | 0.51417 | 3.438515 | false | false | false | false |
makestuff/spi-talk | vhdl/fifo-gen/fifo_wrapper_xilinx.vhdl | 1 | 1,923 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_wrapper is
port(
-- Clock and depth
clk_in : in std_logic;
-- Data is clocked into the FIFO on each clock edge where both valid & ready are high
inputData_in : in std_logic_vector(7 downto 0);
inputValid_in : in std_logic;
inputReady_out : out std_logic;
-- Data is clocked out of the FIFO on each clock edge where both valid & ready are high
outputData_out : out std_logic_vector(7 downto 0);
outputValid_out : out std_logic;
outputReady_in : in std_logic
);
end entity;
architecture structural of fifo_wrapper is
signal inputFull : std_logic;
signal outputEmpty : std_logic;
begin
-- Invert "full/empty" signals to give "ready/valid" signals
inputReady_out <= not(inputFull);
outputValid_out <= not(outputEmpty);
-- The encapsulated FIFO
fifo : entity work.xilinx_fifo
port map(
clk => clk_in,
-- Production end
din => inputData_in,
wr_en => inputValid_in,
full => inputFull,
-- Consumption end
dout => outputData_out,
empty => outputEmpty,
rd_en => outputReady_in
);
end architecture;
| gpl-3.0 | 006f964aa21d726d3cd66ed30a86bb44 | 0.691108 | 3.628302 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_ddiv_64ns_64ns_64_31.vhd | 4 | 3,362 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 7;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component feedforward_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_ddiv_29_no_dsp_64_u : component feedforward_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 622877f584fff73918310e6c3ec14bf5 | 0.488995 | 3.527807 | false | false | false | false |
Rookfighter/aes-ss17 | ex03/whole_design.vhd | 1 | 2,899 | -- whole_design.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity whole_design is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
dip: in std_logic_vector(7 downto 0); -- DIP buttons, high active
led: out std_logic_vector(7 downto 0); -- led array, high active
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end entity;
architecture behavioral of whole_design is
-- import i2c slave
component i2c_slave
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0); -- rx, data received
rx_recv: out std_logic; -- rx received, high active
busy: out std_logic; -- busy, high active
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end component;
signal tx_data: std_logic_vector(7 downto 0) := (others => '0');
signal rx_data: std_logic_vector(7 downto 0) := (others => '0');
signal rx_recv: std_logic := '0';
signal i2c_busy: std_logic := '0';
signal dip_z: std_logic_vector(7 downto 0) := (others => '0');
begin
dip_conv:
for i in 0 to 7 generate
dip_z(i) <= 'Z' when dip(i) = '1' else '0';
end generate;
slave1: i2c_slave
generic map(RSTDEF => RSTDEF,
ADDRDEF => "0100000")
port map(rst => rst,
clk => clk,
tx_data => tx_data,
tx_sent => open,
rx_data => rx_data,
rx_recv => rx_recv,
busy => i2c_busy,
sda => sda,
scl => scl);
process(rst, clk)
begin
if rst = RSTDEF then
led <= (others => '0');
elsif rising_edge(clk) then
-- check if slave is not busy
if i2c_busy = '0' then
tx_data <= dip_z;
end if;
-- check if we received a new byte
if rx_recv = '1' then
led <= rx_data;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 6dc01260686d4a897fc3921750beebdd | 0.476716 | 3.839735 | false | false | false | false |
Rookfighter/aes-ss17 | ex04/whole_design.vhd | 1 | 5,921 | -- whole_design.vhd
--
-- Created on: 26 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
entity whole_design is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic;
clk: in std_logic;
gpio: in std_logic_vector(5 downto 0);
lcd_en: out std_logic; -- LCD enable
lcd_rw: out std_logic; -- LCD rw
lcd_rs: out std_logic; -- LCD rs
lcd_bl: out std_logic; -- LCD backlight
lcd_data: inout std_logic_vector(3 downto 0)); -- LCD data
end entity;
architecture behavioral of whole_design is
-- import lcd component
component lcd
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
din: in std_logic_vector(7 downto 0); -- data in, 8 bit ASCII char
posx: in std_logic_vector(3 downto 0); -- x position within a line of LCD
posy: in std_logic; -- y position (line number)
flush: in std_logic; -- flush input, high active
rdy: out std_logic; -- ready, high active
en: out std_logic; -- enable, high active
rw: out std_logic;
rs: out std_logic;
bl: out std_logic; -- backlight, high active
data: inout std_logic_vector(3 downto 0)); -- data, dual direction
end component;
-- states for communication over GPIO
type TState is (SIDLE, SCHAR1, SCHAR2, SPOS);
signal state: TState := SIDLE;
-- character that will be written on the LCD
signal char: std_logic_vector(7 downto 0) := (others => '0');
-- position where char will be written
signal pos: std_logic_vector(4 downto 0) := (others => '0');
signal reinit: std_logic := '0';
signal lcd_char: std_logic_vector(7 downto 0) := (others => '0');
signal lcd_pos: std_logic_vector(4 downto 0) := (others => '0');
signal lcd_flush: std_logic := '0';
signal lcd_rdy: std_logic := '0';
signal lcd_rst: std_logic := '1';
-- gpio clock that keeps track of curr and prev signal
-- used to detect rising edges
signal gpio_clk: std_logic_vector(1 downto 0) := (others => '0');
-- payload of gpios whenever we receive rising edge
signal gpio_cmd: std_logic_vector(4 downto 0) := (others => '0');
begin
-- curr gpio clk is msb of gpio
gpio_clk(0) <= gpio(5);
-- remaining bits hold payload
gpio_cmd <= gpio(4 downto 0);
lcd_rst <= RSTDEF when reinit = '1' else rst;
mylcd: lcd
generic map(RSTDEF => RSTDEF)
port map (rst => lcd_rst,
clk => clk,
din => lcd_char,
posx => lcd_pos(3 downto 0),
posy => lcd_pos(4),
flush => lcd_flush,
rdy => lcd_rdy,
en => lcd_en,
rw => lcd_rw,
rs => lcd_rs,
bl => lcd_bl,
data => lcd_data);
process(rst, clk)
begin
if rst = RSTDEF then
state <= SIDLE;
char <= (others => '0');
pos <= (others => '0');
reinit <= '0';
lcd_char <= (others => '0');
lcd_pos <= (others => '0');
lcd_flush <= '0';
gpio_clk(1) <= '0';
elsif rising_edge(clk) then
-- always keep track of prev gpio_clk
-- so we can detect rising and falling edges
gpio_clk(1) <= gpio_clk(0);
-- keep reinit active for only one cycle
reinit <= '0';
-- flush whenever possible
lcd_flush <= '0';
if lcd_rdy = '1' and lcd_flush = '0' and state = SIDLE then
-- data has to be stored temporarily, so it cannot
-- be changed while LCD is writing
lcd_pos <= pos;
lcd_char <= char;
lcd_flush <= '1';
end if;
-- only process communication state machine if
-- gpio_clk shows rising edge
if gpio_clk = "01" then
case state is
when SIDLE =>
-- possible commands:
-- "00001": reset LCD (reinit)
-- "00010": write new char to LCD
-- "00011": change position of character
if gpio_cmd = "00001" then
reinit <= '1';
elsif gpio_cmd = "00010" then
state <= SCHAR1;
elsif gpio_cmd = "00011" then
state <= SPOS;
end if;
when SCHAR1 =>
-- receive first half of character
-- msb of gpio_cmd is unused here
char(7 downto 4) <= gpio_cmd(3 downto 0);
state <= SCHAR2;
when SCHAR2 =>
-- receive second half of character
-- msb of gpio_cmd is unused here
char(3 downto 0) <= gpio_cmd(3 downto 0);
state <= SIDLE;
when SPOS =>
-- gpio_cmd contains position update
-- msb is posy, remaining are posx
pos <= gpio_cmd;
state <= SIDLE;
end case;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 5295101a16da31be879235e092256f73 | 0.45364 | 4.372969 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kr_fuzman_koft.vhd | 1 | 1,429 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_koft is
port
( clock : in std_logic;
Ztminus : in std_logic_vector (31 downto 0);
Ztcap : out std_logic_vector (31 downto 0);
koft : out std_logic_vector (31 downto 0)
);
end kr_fuzman_koft;
architecture struct of kr_fuzman_koft is
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_inv IS
PORT
( clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector(31 downto 0);
signal I : std_logic_vector(31 downto 0) := "00111111100000000000000000000000";
begin
M1 : kn_kalman_add port map (clock => clock, dataa => Ztminus, datab => I, result => Z1);
M2 : kn_kalman_inv port map (clock => clock, data => Z1, result => Z2);
M3 : kn_kalman_mult port map (clock => clock, dataa => Ztminus, datab => Z2, result => koft);
Ztcap <= Z1;
end struct;
| mit | 15eb7315e0160b1f6bfa3e561b33d362 | 0.642407 | 3.086393 | false | false | false | false |
minijackson/school-vhdl | E2/TP1/laclock.vhd | 1 | 1,097 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clockCounter is
generic (
n : natural := 4;
max : natural := 9
);
port (
dataOut : out std_logic_vector(n-1 downto 0);
equalMax : out std_logic;
enable : in std_logic;
razs : in std_logic;
clk : in std_logic;
reset : in std_logic
);
end clockCounter;
architecture clockCounterArch of clockCounter is
signal inc, eno, D, Q : std_logic_vector(n-1 downto 0);
begin
dataOut <= Q;
process (clk, reset) is
begin
if reset = '1' then Q <= (others => '0');
elsif rising_edge(clk) then Q <= D;
end if;
end process;
inc <= (others => '0') when unsigned(Q) = max else
std_logic_vector(unsigned(Q)+1);
eno <= inc when enable = '1' else
Q;
D <= (others => '0') when razs = '1' else
eno;
equalMax <= '1' when unsigned(Q) = max else
'0';
end clockCounterArch;
| mit | 371e7a7f94e588dd8cc8655134bdf514 | 0.504102 | 3.396285 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_dcmp_64ns_64ns_1_1.vhd | 2 | 4,486 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dcmp_64ns_64ns_1_1 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 1
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
opcode : in std_logic_vector(4 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dcmp_64ns_64ns_1_1 is
--------------------- Component ---------------------
component feedforward_ap_dcmp_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
s_axis_operation_tvalid : in std_logic;
s_axis_operation_tdata : in std_logic_vector(7 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0)
);
end component;
--------------------- Constant ----------------------
-- AutoESL opcode
constant AP_OEQ : std_logic_vector(4 downto 0) := "00001";
constant AP_OGT : std_logic_vector(4 downto 0) := "00010";
constant AP_OGE : std_logic_vector(4 downto 0) := "00011";
constant AP_OLT : std_logic_vector(4 downto 0) := "00100";
constant AP_OLE : std_logic_vector(4 downto 0) := "00101";
constant AP_ONE : std_logic_vector(4 downto 0) := "00110";
constant AP_UNO : std_logic_vector(4 downto 0) := "01000";
-- FPV6 opcode
constant OP_EQ : std_logic_vector(7 downto 0) := "00010100";
constant OP_GT : std_logic_vector(7 downto 0) := "00100100";
constant OP_GE : std_logic_vector(7 downto 0) := "00110100";
constant OP_LT : std_logic_vector(7 downto 0) := "00001100";
constant OP_LE : std_logic_vector(7 downto 0) := "00011100";
constant OP_NE : std_logic_vector(7 downto 0) := "00101100";
constant OP_UO : std_logic_vector(7 downto 0) := "00000100";
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal op_tvalid : std_logic;
signal op_tdata : std_logic_vector(7 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(7 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dcmp_0_no_dsp_64_u : component feedforward_ap_dcmp_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
s_axis_operation_tvalid => op_tvalid,
s_axis_operation_tdata => op_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1;
op_tvalid <= '1';
dout <= r_tdata(0 downto 0);
--------------------- Opcode ------------------------
process (opcode) begin
case (opcode) is
when AP_OEQ => op_tdata <= OP_EQ;
when AP_OGT => op_tdata <= OP_GT;
when AP_OGE => op_tdata <= OP_GE;
when AP_OLT => op_tdata <= OP_LT;
when AP_OLE => op_tdata <= OP_LE;
when AP_ONE => op_tdata <= OP_NE;
when AP_UNO => op_tdata <= OP_UO;
when others => op_tdata <= OP_EQ;
end case;
end process;
end architecture;
| gpl-3.0 | 697dcc5284f91e8f3c41350fa8fed8f3 | 0.518502 | 3.469451 | false | false | false | false |
Rookfighter/aes-ss17 | ex03/i2c_slave_read_tb.vhd | 1 | 6,385 | -- i2c_slave_tb.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
entity i2c_slave_read_tb is
end entity;
architecture behavior of i2c_slave_read_tb is
-- Component Declaration for the Unit Under Test (UUT)
component i2c_slave
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0); -- rx, data received
rx_recv: out std_logic; -- rx received, high active
busy: out std_logic; -- busy, high active
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end component;
--Inputs
signal rst: std_logic := '0';
signal clk: std_logic := '0';
signal tx_data: std_logic_vector(7 downto 0) := (others => '0');
--BiDirs
signal sda: std_logic := '1';
signal scl: std_logic := '1';
--Outputs
signal tx_sent: std_logic;
signal rx_data: std_logic_vector(7 downto 0);
signal rx_recv: std_logic;
signal busy: std_logic;
-- Clock period definitions
constant clk_period: time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: i2c_slave
generic map(RSTDEF => '0',
ADDRDEF => "0010111") -- address 0x17
port map(rst => rst,
clk => clk,
tx_data => tx_data,
tx_sent => tx_sent,
rx_data => rx_data,
rx_recv => rx_recv,
busy => busy,
sda => sda,
scl => scl);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
-- sends a single bit over I2C
procedure send_bit(tosend: std_logic) is
begin
scl <= '0';
sda <= tosend;
-- wait for delay element to take over new value
wait for 24*clk_period;
-- allow slave to read
scl <= '1';
wait for clk_period;
end procedure;
-- receive a single bit over I2C
procedure recv_bit is
begin
scl <= '0';
sda <= 'Z';
wait for clk_period;
scl <= '1';
wait for clk_period;
end procedure;
-- sends start / repeated start condition over I2C
procedure send_start is
begin
send_bit('1');
-- rise sda without changing clk
sda <= '0';
wait for 25*clk_period;
end procedure;
-- sends stop condition over I2C
procedure send_stop is
begin
send_bit('0');
-- rise sda without changing clk
sda <= '1';
wait for 25*clk_period;
end procedure;
-- wait for an ack from slave over I2C
procedure wait_ack is
begin
send_bit('Z');
-- wait additional cycle for slave to release SDA again
scl <= '0';
wait for clk_period;
end procedure;
-- send ack to slave
procedure send_ack is
begin
send_bit('0');
end procedure;
-- send nack to slave
procedure send_nack is
begin
send_bit('1');
end procedure;
begin
-- hold reset state for 100 ns.
wait for clk_period*10;
rst <= '1';
-- init transmission
send_start;
-- send correct address
send_bit('0'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('1'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('1'); -- direction bit
-- set data which should be transmitted to master
tx_data <= "Z00ZZ00Z";
-- receive acknowledge
wait_ack;
-- recv data
-- should match tx_data from above
recv_bit; -- data bit 1
recv_bit; -- data bit 2
recv_bit; -- data bit 3
recv_bit; -- data bit 4
recv_bit; -- data bit 5
recv_bit; -- data bit 6
recv_bit; -- data bit 7
recv_bit; -- data bit 8
-- send acknowledge of first byte to slave
send_ack;
-- set another byte to send to master
tx_data <= "Z0Z00ZZZ";
-- recv data
-- should match tx_data from above
recv_bit; -- data bit 1
recv_bit; -- data bit 2
recv_bit; -- data bit 3
recv_bit; -- data bit 4
recv_bit; -- data bit 5
recv_bit; -- data bit 6
recv_bit; -- data bit 7
recv_bit; -- data bit 8
-- send acknowledge of second byte to slave
send_ack;
-- send repeated start condition
-- with new address
send_start;
-- send wrong address
-- slave should go into idle mode
send_bit('1'); -- address bit 1
send_bit('0'); -- address bit 2
send_bit('1'); -- address bit 3
send_bit('0'); -- address bit 4
send_bit('1'); -- address bit 5
send_bit('1'); -- address bit 6
send_bit('1'); -- address bit 7
send_bit('1'); -- direction bit
-- recv data
-- slave should not send anything
recv_bit; -- data bit 1
recv_bit; -- data bit 2
recv_bit; -- data bit 3
recv_bit; -- data bit 4
recv_bit; -- data bit 5
recv_bit; -- data bit 6
recv_bit; -- data bit 7
recv_bit; -- data bit 8
-- send nack to slave
send_nack;
-- terminate transmission
send_stop;
wait;
end process;
end;
| gpl-3.0 | 76c6e630ef0f70592c832acff39fe8ab | 0.495223 | 4.119355 | false | false | false | false |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_fmul_2_max_dsp_32/synth/ANN_ap_fmul_2_max_dsp_32.vhd | 1 | 12,683 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
| gpl-3.0 | 96c7010723ce4d057121a8fd17ea0484 | 0.649294 | 3.000473 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/axi_utils_v2_0/hdl/axi_utils_v2_0_vh_rfs.vhd | 24 | 292,074 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
kPPWi0fMFUDHx4hSJZXOHx9nvzoK1loLAOMw35vd/HjRjmjDT7gyj1xY+mcTHSLqjBIBfjLlv26d
JZ3IU+wu6w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
V/1TuAflQptypMp0+ukYLRB9lHps3Xc/g3Ljc0UTbNJD2zfWqP0m5rcCo11OdSytZsR/LM/hlA+f
qpfiQvWX2Z+c8WgfPpsz+M/IaWoEBtRgapHt1MwYKInHrzQM0hrn5gxRHXZtkyHLj2T+Hb9pLyrw
a2kv6MRZxll7qiPSaqw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
kl/tMWLyXxSk89lagK7+po8vdYsYgAEPfq+ocdrJUI7Au7sNvcjovO7tFIbnjRGMwoh7Wzz8dSId
N5inCGFAlFI4KTBb1WNzojq8AMO89J6JAfO5ODcxlHN2T8ros6evWjjgRCvWHLNxBypzeAtxp943
rqSbBjANDdZNBoq9eIqE0x2VojUYyXKC80kdCiYhUMNu8WA9cHlJjbBFEX2PTW3y33Tc0ug416lY
k24RRNWYYTQV/Fr7QI1Xm9xpkTeLFcOH2UQDZo6OgP6x0cu1ijxa5YArePRiFX5UkfDuraWX47XS
R2bW9vlQ5KrQpiXLBWPHhlTAn6Xfp/NDkvyBEw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Kevx/7K6us3dccFFQnXHgVz05QfzmOCAuEUoiq4XE52L98NQrfNSAp9SsPmuFVWkSc9v/6JlqV4t
2SIw3lI0g6w+BoIixpCHIgzq+jjQFFAkhVYumIY0+8Rrz2ruRBV2eYZb/OWWNdVS6hcR8HQnCN/U
UZ6YHxR1cS2OmvThZ4A=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
zltaPVBlXfbjfbMl/HV4yzMtJfQeNKqxW3EGACjk9wB1fgYtKhp0WJ4mPob+Geycuyx9KpPBRbCm
iEH0vSuX4Uoogpu6pOb4VkwG/AP1p3RaxG1ABbQb5k1BQOn2RgliXiECEyvSt5l6phjL7XJXG3l1
zHP5FjfaKK1/z/ulsMu+mb3ePv+4K78yIpp4suFxfDLGuaKBEbBnblRPAYcrWPvnqmOi6Z3yObRe
mmcH169/1db2WuFMXO48rfc+h+H0NVevUSbmruo0T0fSd7KBrnaynVMHly6yrMnaiw7mmTAL/0Ni
vPUgcJFMdJLCEuycZsgqHJwSaLRlBRyhDhFuPw==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
XLAfdHUL8txBP0pX+y9ZjLeZ/GFC2NayMSr+HXr3Bc+UFzNhilq6APzx4Wrfu4AKQvhuXh4Lcc7a
ZtjuSFz1YOQuYkCjXKeBAjJKWzV4KxRmjb+e4gnqjKChLnulyWee9JMzW7EI7JxPRPIdjG7XcYB+
+r2B10gnPzr4GQGBYC1jJ1+xSla0XTFwSp5FTXvTnyQ2FIsluC/452NiYjDz7pup965E2MW/6aM8
NvBsCtMyatWrr4Jfz++RaNswWEx0xZT2z4l4H0io7F5FwqGtI9N2zeF2x2Xd9v6hMhxZr6L/OAbT
HLX946gJlyaSJ1EdSzifXaoNVaAfpHjp/5GZZw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214080)
`protect data_block
uW9LKnbZpIqv3I0BGszDbxaic1+kKwZ9ZwnvAK21lVA4HwFNP8Pp1eOmMW4ysynrsEtMAjswQLOx
9m232eYOp6v1kZtF7EkbPfYV8/pbttKghfZ2pejF6ISDAvvM/4Lnt4AC0EYXKX79Twh8ML4+TSdV
09fs9ei1NDXbTqh3T/vSkvCCcDBZle1Yw/59b9qmxPSxV5RufZ/U3oyaklTa0So77MbtLxw2rtCG
q031Lz6Ck93OMMZHkd502eaiKmiohTODqr6IapoXtAkzvvhHxXFma+Odd8OJAc33CAlwRh8qz3bJ
zXX3SJZg5po8QnDo15c1mUXyh1euIcMvDN8kjnZZY4IMY+mhZvI9OiQDcg0rQ118FOUPhtGqJafa
BJwbf6tOfe8XGc7SDU5aAS7uTL17qh4Km8BkkUyYmxnfNfj5748VprvPdZD8WSa//ffe3PsB8Zy7
Qb1dFP+e2YJzETwXSNgCA7FnmakysgxV+4P6g7qMJRNEp5ejBmkkavZRBNWbMXMYn+vky5j5ghRc
j2jo+Jk00KupB7q4dgatI2RimsGfWG3CazSIANphl0U+qgCxeBHhh1d0PZho+jQS6vkzjJxq433L
AYOPnP2CRNj3K0DKzrjkSaUDEBO0j4RQzbk19IBaOibPMfY529eG7LY/UtC3gBbx7q9Vbkf/lxmw
Peoc1B8P4JA/KtjDmKkz/4a7ry93ilB4zLlxKqH1W2NdbPozKP1D1uxEULu7Sa2GIXbTUb20eVD8
6myTCp2733XU1TTJ9yM+3xn/iTxD8rg95hKpx2ZTC+hKPXzIihXY33FP/M+Q800ioMDjQA10rZDF
VOZJKN4qbKofifuW8aKsgh9g1SN8lzJuwEls9W4BIHD+TPqaC72yFtHZSTLjfRdPBcU4rrBIaPqA
cIeuk4BVTHbMbJFSGxyKqsnMsK7oTuGXiMH4yJg2XWJ9manS+4HT4/yMnMNa6zWAA6R3WzTWA9hL
PFuHggSyIgpbnVpqfPJWySOxDYTblc7K+UIhhR4qpkNiBar0Y9ZHrQDTnNbiUgS3w8J2BfA/KQxK
MNfi5fTXeyzrEbyjc8vhcrgt+wiLpD7wDmtRug0IDe+uyepSZRo34i0f14a6/1qKii/x2q6VZy+C
x/I+O0fTEQydrPqW36J4QY1n1rHRRrJuFWAMsq22Ac9exzqSf487NXcfkoIeVGPONFEucENqTLW3
yNoVDzD+c5GJ75EREIZc4OwcpPgxCbVTvfPDpIuACX3n9fo+S+8kudoN6GTbNblx4vy/9gZYzA9m
1ISys6uxEj11zxThHiFDrFTe97QCsX5kqnfxvGyp/3BWCmyenrffo8I/8UN8oQIDa13YAd9U2aIg
oF9h1tYh92PUf1W1AfHXvYnkPSCmlfwhs55Y1wq2HnGOv2bN/4D9B8Sangxs7nTZLOpcNNXuskGo
Jz5NEoE5wPWal1q1LYzfSzTe7lQAWNJPyxPiFIQXrUFKEdNKZc9OWigp4iPLoZLO6khz33J368ao
zXNBN1/iiJRLPhjnv0KqJto/ABttNQ+UeqDcpPI4zI4C+ChwCVNRSmJPBpFyrI7784h5W91ZzN3l
tc6ZnBFfmGckL9MsJljAl/ebr/xyGUmWhippb3N8+uPojrtrHCCTiQwDGGeIKSS2DO5R2WvlIadx
TQ/S0ct36LnlJe55mXaNHNX2/n0iULyK690Fd/YE3J81p8CC0fuY6x+uWEuV66bmo7k9KeLvsRlH
GwUGLjmya7SpP8NAzzsL3yK0yJNJS87oNgUz8r9w6VEmoPH/YsAvVIXnQQIPJlFNNCW3ccaOmIRt
TrxrzjSd2nzw0dCccdEoanHECkrdyYf9YFJUhUQDKpJqdq98lzSewy/9d4gPl5J2HwXF/38MDigr
YDQMEfQK5QQKTuxPHhNz68M+QgQ6j/EvcCU0fPXhtVmvsylhdh4PwM1axTR1ZoPEywDqizf4KZUs
RAi6zhvZrk3skdOEfrNPZRnqyeiXn2G10iGRbpzEA5VdsolEpu+h9JrtFbAjNmUh18rOXVYr5QdJ
k9v58aC/zpVt+uOdvQWMlmSsZhPHpf5oFytuiwTEYOPoH5Y5DxIXlauadHF49A+og+pmJm0OTTN+
Xl6Ycjbfm5F5fBUsLz/g95ACmOopPLyoo8c1Mm5Ageizgk/3i2R12FlIfmVX+a/a+Exl/LCIJT06
WOEMAzyYP9KoKqfGJpQJvuWPxILVZo+ysJr5QzfilsKsohL2aEiD8cJdoXJyHKmCR3XgEvG4pRof
VYKr245SkjSZKn6KxQj01Ag4BNa2W81PTxzp3Vk3NsfPHxX2lpiNl86oQE4nwO6tyGtmAUx9l1S6
JEXgaeGieMz+v0MjhVR7mwhDEs3DQtk7hMZHXXscSz1AX+MCCxcfZXQecdEtXfMpu+uqXoFzj8zi
QhDV6WomyoYLe4g0EJjwkVU8zpE5hyGr4kjSsnNeZvubYg4QrFaaOIWyq/Fg178VyNR1I7Hezin+
omgTgsxWGHj+sAvsVMTKjHmBY4nVne5DAFN/wHTb1ZOPWDr8OXOOmXvJTDdmft504pLuTn8zeea7
EiaOQqv2W8qtY9pKB+cTfEHO7bojgK6BnjsC1rKKYBz28EKkluuNd1M0CoOrtD5EUmtrh2/oyDn8
W3pjm0v9SN3Idr/egtL/7PYTaNVnNaA89WIxlymslhIUo16Ar7+sXFkCVy0vCy5LxknsRCxEYzlf
YuxkZAAHm8mP8m6koOccECXj3GEHfxAOHZF9uiINSXL9O2zy2G5CnF8nwKStlbLaVQgljQfhjfno
IQ7JuVwoRe6MWJWMJTbvoebvPJc2hBTgoLZkXxRuOgmROdfM73tGfUKB5ou8t8HvJ9PxyoW5nRfR
8PqhLkI5JmWjp/YBD3NGz94sCqtl9n6qw+BKPGRQO1qeqI8lgShOo2o5LDNIfG29VKkpv0VThmlr
JI7Edphi9P248MjMzTvYoTh6AsGbJRVMOoUw2O2xNqLC92VKqYvylsLJQQyRYnme53SdTHZNxNkl
1xquTEsqCJTRpzOJ4/nFeZi1wF+jRRJLr0i+uBLXhrcy0NBZ35H0PfzfACpQ/elcz/vngr5WxTcx
qvV9m0Hw55VttBq1yjawzdpUO6e2+siLvlOpiwbSnoX6Fjr99YJCX69GqBbHodcrAxwJVdlt2UjW
gBKsR4yZPL0sRN5/2HUf71tZiA3LwC3QlOfHkzvfi5B1+RekwzMp80CKK71mdTPAqA9WfYN3Dhvg
DnHdtzSLo7rT/9RWwmGkjBsrfyDiRpBjAikbwo/eVt3W7yvq+CP0NiWjwALZbb2wLu+JmHqzCnkC
j7tsH4x3JwlVcVgpev406Ka/QGZ4dS4ludkpdZat6sCPdkpPXA7ZgKsYPhVAt34soqeajVqI3Ptc
7WXRr3cAC55akQmWaNJsfRthNEkh5HJpdmQFpE998vFskXcf4MkaF4vDHnPaNXpz2Lad6199wzwb
ZqsIgXUpNYLuT0p69H8SV7jiAEOw6yfJt/PD2+stk+Fyfl65Zl0Jb0vzPk7Cmmbt4AIjE3rxktF7
QPiRFpZGFnC24mpyLThv7Rv+d0weJgwOIv4luVljWXzk6saTr6p+EprqFnr3T8mB8wt8936lTiNx
w899oVPnHYvO6V6jjIFSSPPnUf4X4GaDNpCQRnhMR9LYpP9DB0mQtX70v+zY5wtdNXfrkEEc+ohf
uG3/ZiTkHNx+ECFDGa5q/kqOLDFp5t/WhGwUodgkNZDFq7UXfv0OodAh1wFnkKN7EwjssUYlYV1U
loeoy5Bedz6R4T8QDUP6vYNQVqUZUAV6EbUKl0u6JcXlVZKCGb0DxDnTmI9TmeNpfMy/EerumebO
a0p91PF2T5XDRgjYLvpcToaGkeKOo2tDzzSVX2nVTqqAT4L1UfQrFCsqB+miTP+zXmJXA+LrDb7V
MRiildWoKQgo40YQVkqdRxsPgstoTHuWLalt36zlR9lEOZS0iHgvQndFeDvB92iE6UWKJsl1g/vF
vay1QQ7vC0T5+3QKk5Ln+AeHD7abeuHMkqAxf3Dq3cCupQYAcZF6fFGTMwldp9i4f5vDY6rYF/UC
KtsnrrkJg3Ltvzt3z051+VrOJETnZ/plXVooABJeEl4xu/zd4nVfsNidqQHhEGawBD0BHBFTOk0Y
QXrrpLdMkfrqMspYPl9pHlQVf0JzkP2L7AU9ziFyhWeTlVFnt+FF3g0E9lKQ7hMngXI4LCaxQmkl
zeLjidXp6zzLm39lrsjwlqBr6KIW0kb/jejf+800xTHbcGbG5kkXYmIE6SL/FKJ2Q7Fx1RQYjLNA
12HEIti57iYvTwB+gnKKpXhFbTrTi1fffFj+eXXBGpfP+xZaIr6EW/QqWBXhCV9RmA3+GbRpfDH6
zPGFz1LRFM5ERIi3NiURqs2h4lkQOF+c6f7BXCH06UUw8wO3iZ0FbDE3RFl+Hz0YA1/u1Ckgnnd9
wi0xCe28UMm9NGy2aLPnuAgCQ6KrZslFPA08iHoZatfA6I1+uW8QBc/iyVbMrQniD2SHk+MGyDml
7r+m1DAej4oEDSYiZqW68VfbKeGg8NOFQIqm/lbmU/md/mXuFttx1PcKEFA944Ws4TMyBPso3HMd
YqWb3EpBUv13x91xANoJB6S4dRKm6B9ePrdEbZX7EEzueFYjpWF1/jCKO5Ti/kq8t2VpLTfj0U9+
SpP05WiJvOdDCSs7w+tGEyXcEJ1WJzITOqFdwirdi/aZpMt3xpRGejBYaYbtKe2Rm+jTMVIwttoj
o/OA96imm4M30hDhFHtKiV+zhBEZZrj9ByCw4FQY4N2ewelQFjYjmF/Z60/aX7zzG+H40BDayH4v
YFbFDzpxZZm/zTxxHjvGM/BuZHJBTORj6/k6wpiOMXU0r0dKaeciqPmpEdFX6vP1PGlM+ET6jHM/
1DGKBsXMfcjwnl4/Iu4g1cY4qv/bC3CJeEHUq+VC4hrD7DF4UIbIuQimgYu2JFv0gHEMw74iAOn+
IR000RotzEepOLOEoWwwrw+yptxs2v+OVQhS/JDBfaqKM0uzPDodbPTYDIwvOTidXtngZVAfO/Rx
K+BYSzDjkYQxiGxrVagUvtslD51poeKou6GZRIJJXZyNFMy06KzPzyxmFjG1lH09rbJ0TD4HqrTN
etjbMacMOWUXvj0x6tl3UPl1PAvHldAFXnrOSPq6icpncVUAW1DY5w143Bek8hBzJdcUjzaeMQjI
0Him1kkgk+IczKF0UnwrNlVfW1ClYkxiv2f/cqPvI1VUFH0orI/cyqrFEyfAMTd6cUEFbvCcDpqm
tCJ+imG/grmJX8DWnkAPUgSsQyg+G1CxuXRhf2VPfF1oexcn0W9kf9aB+XBMQhs7NBq7bPg4bGn/
BPQ38T+9fgLyMjVrnbK/6nVu5NRHOM4mCra+YSi5fFgGJYDRyUx9uHCHt8ng4DwvfpLWW7xaRzqV
NFQAL4pr57bG67mULf6mEu0EKNhbYENzWju6A0sS2fqcoLEHs7Yqpn3tHTSTvqbaUExEUIoxHU1Z
wLOvKr7DcVr8ZvA4J8hz5mkBfEEjQmTrS17lJu5HRNcE89jpyF12RObmecGNW5Rggd38rI20TTpW
tYsCcm2+VHUv30ypz0ZbF2NYQBOeVa72+pZIZNU1/MP0EwywCBDOAcZmoduSiXCa+9k9r8kqLNjJ
KCxFjZbYGw4cj65248BhQIJLX5+DkKQ+VmWsE2L4g21H7y8w1XsNvQd21CVsyMYa+p6uh7w+usg0
M8844+e/FTLntjRfErTku4Fy/AFy+lzDCn9w6JECzqjL7xeBEGLxyXSPZJs58ueZQqjs6zRbs0Ro
HY9WeMvUnzC6V4qWOyEJ/i5W6w3xbwPdE1T1eeMjtzMFz32cVG7djpU+KywsoLvRqfHa8W2q1wjp
l1JqCGdpXAcJoTmsVGF/N5umiURRfepFFCww/HMVoHfzCD2Aqd7yU470L+67lh84scgH6uiq91Rn
cDch+JL9TsPuCJM7bIEGvUVTNctK/bqYkNcR4xohhyWke8d1uo75jOwCNxjB6QOZ1R6+kyR6qk9k
LoJiy3pV0AOHRBNbHeA0AQHt50WT0wnJQpjpnycJYtNr6w2dWx0RW3Rvk1Xg3rGPrnz9HjoGQny3
qfrYEbO3bLOYjtS/8fCKJLkoKbEmKKWkB2YJhKh252ASdNpcLsFj6vJOg8owSBqHUdpHyvtxNq4P
BAycWzQWK6DJDlmNuqv0koT7oMWVEs3R7G4/vSQHWnpGSAVTMl9R8FMfZtUPC8UEMyljZpZcdUWp
meHxYus6nhr7GyA6Oo1gCedo8iBwYV8vwRzlfzMoieyhDft46CQudv7dNP0Y6qXYs/SBWBqkhJx/
1iusmqN4ehl9HtkWLEnRYtBjGiSJ5abkHW7Nvwilz5bU5FUtCHgt+qI9m0eLsyokrw6heY8JHwDi
ai9+yxfGlrQ0KkHxaHriNUTiJIliYNy2p/KYZ+mO9jASX4pA5AV3q1XVG8o6834tTLh2qFyRY39b
ysrC0EcqPECbd2stsVZ3LSTNB3ow4i5GBkpWU/lVxLp6uOkk5gySSzSQOsVUwAM4wT1jQv/jR091
qqFhIbXYvJUUGPan3EDMYQaGMo6jF0NS3s+laXwqkNX3gV4GecqS0LYL5AA6o7BigF3e6x8W/Zm5
NBBihumdbNu1LrEWtg2KBIBu3+YnaOLNZGomBWmTsajR9JRM19vJIZT4xeN+qlOWNtqwr3Qgk81G
8LGkiHm5y+SvXJRu7E6OrtnPNqAMBhsTLLdEMqA1GFAKQCcVIavamcJOIQN1rk+IbpjQcrmB8X1D
SD+qtsrVZyXQD0mvzi7hUzNgMMa5G+MMfeKE4D+xkg50aoHu9Z2XPU9ikYg2Dd5a05Y/ukVFszAo
hblFXi8LCAR+hB4LjAfYFuIp30tY89BMu/rIjnpXAEPGgcyA2SSetnIhi5L0oo71Wxu7NsXarYQi
uFPFKhfBCcwMnp8M350pUkVK0fsHAt8DI/Jhe08gonv/uM4hXlJIp9+kV+sVYdOi3oapopMKwdPf
XNcHNV3QrOW20dFYjuK1IQEb8706Wj7lRurhZuGHVNHVR/wBPTeKeDa6Zx7zad8x9eVLi6Eijyp6
X6UbCrYkYpCM0t8YaycBgSrjq0+OBB/D/ItJtdl6uTOwL8Mzg0Wt+cMviGFXQ63wcRhLe8uHf8Mo
vU3zyWg4bnHKvyEoA1AMklmGs+fPcFp+3cxNpD6DpafCWaeEqIymetKnsno17V5ymo0ACWjr0V5r
opF7sAqep/o3YV9qfhu7qENXmNFQ4qfEc3Hmds1xVNw1fojeG2SfRz4L59FUnPJlCIWG9QJEgUj3
wZBRfGoZ9d2aHfSPGV8gDfduWT2E0W7nGmwYt2Yi0ibYRTrwbfCdJh3sRb1CMdDR3dChO+3kYGyE
3j3JDuOavMP3fVZSSY/KlGTcsuoxnxW9zpRqxNiG5LIvi8Od8llvYqGI+EgMAFmTp9NSXjQXHyAj
zeEEen1xxCuTjNGm+aruNIW2R/cRBgfqcCV6csnI3T5V9TlQNiPatMHZu+LdHL88Gll5ADNq1IpL
kpOijH3puTVVjqSnXVnue93vHCImq1j72mwSlb/Fgbly9cazID8KaJdu1tfENKIrFuJ0QyoVnNns
F7/tcKv/6dgPHznPSAQTNdrmjGq0UmsyPFcQnsg4snjljP8yK6aq3ahqY4+SwTMILYq/YqoqfLOo
DXHiRninid6f2+Kx1olf7sz5WK92QaxCcR+dUEy4Ai9BXthfhSjEwTKXCIjyLrMvUyrKqgE+kSpN
FaBW11AkaTFsRgbzqHz+CEWPEi2foNDu0t8ojuyfVkOfbqcUKmdUF2fhu/xomN4K1NloAdXbU6NL
D1oe0Gs8EoxVRX4iR1XvFUn7oNVagk1ZwpnuTn2Pb12il2VX2GnqOme16q9pXsAGjvy/dWtvZmYu
ZDoSVqyqdhxZWmhs7yHRGq7kiP9jDra6+KQuIQop4FmdeEqpdQOqrE5Wx6It+DZFP6JT8VgXaiDZ
fTDTzagQEzQ40R1Ud5/4u45dy8Ozch7Iqc0ROdNicRn1MjPS2gLljQ/KiwnZZ1HAo35UyYXNQoAB
gPSQcbk4WW1p+V5QiPZ+PFvwW6DmBAPX9r2JiCqYkNhwXUkj0rTRDJSPXC2Iwux4MFJ4Wy4Rg7lv
pn3xMIEhPnvttp2tMzFj3HUYGswae1k4ElILjYLuZCcxOqCcffyhpO6vm1hsBNNkHbQJZu1eH3JW
vXAwZF84da13ElDzwuuFl/fMjKlNSUSy5CNoRI5+Y62RbCbrVpYFs5p/3LJxFHa2hgb5A13iuhoS
IV69vg8Fax6hDEtYdh4fxuHjVvtOLXrD1xUB1ll6Q3zchfO7rMzOLHRSfHhH4dq8fEzu5Sdj/lv6
V7qi9KemlOWSzfp+FZGG+FF67weXne8VXYAs5z82spapNzBmX3sbVPGY2qAPWVfsQyVIK7NgnsPZ
sgy/X2Tpl8KJLkRl8arAqx80j/W/WmA87h8szBQGpoDVNqpAJiem3iUW3sk+Z/w3dxUUgvHq/uyz
uZsQvTMoTYPyWGjvnHC+dRkIhc4HUaHN5mJtagvwCmdadp0FMLNHqWb9phNqTT1nAL1bfZufGCH+
a0M+wr//0W363B0wuEdUd13SBXGrttaMPeqm2baJWuJnnJFdR5nTgd2WEpEiWtZ6K8oWvl8+LGYT
5II13Ul7HpCyUYx+IBsa6zZP7ADssvy3QkOFYWJq91ji2Zca3RYou6UE0T7aZfAyCXyY/yo5TKY1
EdI5QmuC1EqsaRbvQodTotlvdH6f7XVWImLOpQJDw/7Z/R2M3atuzg7dMzH3XVuUs6uLNpHeip+0
IBxN2hN7koSI2r2Sfh3uLdorQdPT2lRMLg2Vybj53+QU1CfjojBpz39YM5VC6H+ZFBe3M85AewTi
kYFwyZgcJzuoKjCnqVFUYJvzvN/iE510k8yl364XCnFuM/jYrDtjFqQaXq4SviV6xY7d6V/YPymR
KSLQZldsQgToKNu2eM9IlXQTy5PDMg1XwnEhSnp3ZeBuwaZPp8JIWpSh4byw6+pXPjMBoAq8DHIp
EfKf/9kpONCQbQ+gdxNAPo0+iH273+TTtUHFySP3fvW4ox2q8CAKufwE1OAJAu5eD2zjoJmAsBvz
JiCm6Ue52s7C5wrCLzBqoqO9h4tFQr1jZTYk+YHB8WkvnBLEf6nxGXc+RLQQn+eD0EuY++gBrcIT
bTpni52IStbESmXzzDc3dKvz4cPxUSAKJ6wppR4NJrt9xzfu+uSbTclrCM2J+vKcAl9qak7dqbiF
So09Ea1+9rAPtOaPwqg1Roi04Lsh4ysOIeua/tM9LsPZnB4baid3gNctNuw90Yhuwe9ENXJG3wa9
qBXclpMBRVasSGBtxI6qamu8/Hla04s9wAqevBtcHDCD+v8n/sAqj0y4QKYTz+M6kly3cgHUDorU
sWxbvq3wOqBNpmkxQP3Kw5/gMqghOpYWM5v+U5NNBBUq6RfiXeHWzVNaurb+aPyj6AqC6s6+UCsM
kGiqMwI+vgND+73o8xthmSOE4O/5FTx4fimqrPuGzo43PoJ+FIEmMxzg5lwqalEZTOgBmK1+vB0u
7EzBa3c8Ynuq2L/J+3Tnezty+cVCy2cAib3dE1DoDF+Q5YjwaxcuBsQq0Gvkio07p2e+MV8qZHDi
Re5ElekZN5t/ffLcSRf6TWtuU9HXpsJJ+6eVfUETnD7QWmr08BfKTO6UjZt4++Fd59/7TohmGaZp
L6/hCB/OH7Equ5tmCxi0EgnCbGO6SOcHm060aqw1e8cFty/wxhZ4CitDwEwIMMahhInGxW8SKRmt
6X2oBfxNK+lkYGIypPlcZdI/Qektjiselq3L40cLY6mm9UNErCnmdLFxrQMiu+RyjUw+6F0pgmTq
KfpXwrkejQyh/QI9pgTgBdS/iavjU5Ro9uT7Q9CVqflvLxze4FMBgWKG5Kh0A4IHUcUAKyq6xxHy
ZOWjIF27KjERIR9/iQtHtNlIHPHcdkYXsluGtUGPOWR8Ctu4LSaQ5Xeh/JNF3juqQX8Y2bKTnwKC
7eVm2NnWAQcRCbhbX5wjIN6RHh8r5QzzmAi4JgSvqumb/ts4MKZRXjLKr13CHqXTvv/fDEdLxo3L
3Lrf1r4Rnn0U88vUsmPKS2ETFlp15uQfaFppO0CuzBQR4nxpY2BTcPu+nEQVh6NkMqPNHAU1sAV7
2oj6yzW5tdfG2MeMaj2eOliDMcfBOpyD2bTfM2X99h5mQMxXX4OvUuT84pyRwRzwnu/Zoee9fS1L
9pJdJepI6gI8Rg+3iAhYw2lgz7Y/LYCwg1bKsSCyGe06nTqFIoXZ6RiXd2EfrgoPIVJEaB8lJvDd
TheVl2cOoqhN80jXxGyY2m7n9IUeGtsYQALlVxD+l+wa/ddi13z/vqRW4ollKSotF1aQN1NktNYQ
aXdRNZrbYWuSWlW08Zead2WpkvMN4zkFxvpgmTcyGZOh8uK7fqe8PKLeD2wqysZHWPxnLW0BYNde
oKXLGf148bPooYnVXo6XNwt0Dvuo7nA4V3juE7zVD89L5UPjN7XRIXI8QowEBavGX5Pacx96xPGl
M0brxHFHQ4y57DRFDWsM9+z1RwC/B70gQvO0cjZuwNNVAE0Z7KkDmFm90PwBtz10l1h/hd+8rMQZ
LkSQMIpWc+Ftf8xvCs4z/bDaFtCMeY2/YwRt86pAY+8a5gkTlLL5U4jCXhbYnZg3dkJCq1D4VLBy
+kzdbmXHjbr1gF01CxkW9vRwTm2WtC5SCaysasblWFxbGm0pyU067GEuYghQtUn64ah+9640UogA
we11HzC89ARlgGLOJJ0fQPdNwffeitU3F7D5Ph/bD+ZdBVhS1DSVQg/SCHi95LQIXKoIC//Q4F1N
Ye1xxWY2JZroj83riNr5hDGo0MOafYvgcZfILNQXwGBLy1InkkIkNOGzJHnfI9yZ0LO1VfigN65d
QS8T9VmOR0K2Klhw3RbBDPbDrDCPaxn4nSJxfRyw9+f8TsLOzXTL9AX3ReH91FYarSa5fVHg8gRo
39ke7wDfGNus88pQEK3cqVwjFdI0GuVLHxm9TDl66qu3ZsvltuLj0UtLvpcu9QstC2ncRNnnfO60
lh5qFJM9DP23z3dyRyLdlsEmvg7xYTRvFVb4epewwSQPhxzpGBq8G5GeoQnLoWkT/FmTGMucZBoV
ZR+bx9NE3JGvi1TmVZBNGHpK5i9QrTJOwJWjpLR+OSIAFNFmFC8TSlnB/ufsfC4ZtgA0i2xursEg
lS75XpEhwxBTIgNKzDEYzSF2Nrb+1E0Am716lAcX04NF48iATvlPIW4iptspVlDJwrS/dByI3mBL
108ZhshgUzzZpKy75QvATu6g84omhBB930wDi9YDAS4IIF3nzAWaMT7uvXyMnDr/zXzCnHFzsjzw
tP/YmCnOZfB1QkCsPSOQ7tInPrH702ZLTi10x5QR0zF7mDeMgF93d5qu32IAxvFqn22vbnZBXbma
+KqVCJXWcnkM2RgQKzE5tYUMdZaHS7J27Rkzznjo12UhkkRPSfm3MOA5DOiVYHQ8hs0e+rS0QeaE
Mf3i6f8g8Hj4hKMq/jWQLWLSc1AR7dk2CguT+j+UVIp7EfctAuplbbcJ5bbtTIaHdlQB6b901s2o
9KAww7X2G+SQ6+73iF7G3nVBunr1jFDeIy+ekp/EQ9KXCRId64BgU8HBxosVNhnLtgleohIZPRCo
7vNC9hT04N7iS9j/7HvB1HfQ9xRC1Z9ctoI3NGAvv0Fpt1pV8V/RRKklMosdw0muKDBAoW+dVw9g
RvXtaZzxpTwqQ8mAMSjcyrqlUVgN8Es0mjJrxVPDF1zolINhIDYPUNRRuL1+ofTBu3ZUMGBagcRt
Li/e4yFEeV6IHwBskSLLipB8fRPReVFjJkbo56DYqgbkANwh7ULWFwmVVfjd3B3qOulxi12p4ULr
O72k48jwz9xTFkxfU2JHFlgAyQ/ny+9fZiZmYBNgz3Dd2dPkVJ/2sySwjYJZUuiQ8sOjgMmtM8sD
cBZmEGKVUSnIiuHy4fXGGQlxKQwneUk+SYmUZprC/5dX0Q51BAjfJWL5I3t+vLr49F+Cp8zDF2mU
2xLwXr1ZUZKk4uCw88Bw6HzcPFveWS3wUpQbIOittfd/FH1nL4pZBrJRmcE4uajhiQacUnBTRmFe
hKC2WjxUR4TIrqJIQXeCbnInq35nyb9Dovt1mlX6eVB27OyYRwEyxqWP3dFJq0e/WWLCuehZHGzc
f/VgHMmoxvxpSJPiyo6KhKFtIvGa5oiB9ba+gbKFZd2w/SruRaD3lQxKFk3WWsWxLAyPBfP8gnvp
Qr8BpRRa1OFwOHQ7SkUW6EtbMuXCLcw8X0OjgHu4vT0jYXClTZyZfIe2GZQXT+Ek0Knn7R01EveP
pidae/bP0Hr/iWeq5uSxoaei7/brEupsYcdeUC6cM8ZOXbBqnTunRaBCy9/3JHVUJjIM/YuVOeVz
4iqpDtDJfccggk+gnvgFifwUmdbN8wfHCP0A3K9PKdUVz8X0j+onPAxG5537VYfoAjOkfLWQsre2
GaZS94evNhIBQ4bcuKGawKjPSSq8CiNVn23nwH7TX+1hfhGA7Wu/H9Bw7SrDfXFQ7X7sPbHOO3Ra
WpngPCtbNjuIBNCRo+b/2mcsp7umxcF6PRwI9GOiyHm8WsBJkHOOw1Pk/yhQSUOHm4Yy5hTPKjfk
pzd4NYQbOmb70U/ln0cYHdp5XhcJ9NMoGFEFTavuGIhXOXKLJyjpKR0ub+F9gRWfQitdSgzj8QPG
IfCAbL4SCiWrYFSz+OLHMTXO7gb/WqWKFp6DeBNPmkyHnHN4EGDmvxR3kly2VBiVLMdB8iSTpaik
tD2iiLHxTvvvJhajBBu7BQKrJiemAjovyb4qzbIEzl2ZI9EfIZHWFVpod/J1orS47SejoypVQF3i
qnxuC4OwFt3LjXbxHO8zyWm9KCHuA8sJHINtpTGvgrxIRmKjZPCoVhUNlFhhb8vcLntkuKd53lV+
n/J+jGbgt28scYRYmMu2khB+tV2R6XTzLYwMw5q0lUQKbzCCPpoZkWt9wHB/iXAaLp8nOV5/AWfs
4l6ySkdxQC8YZF9eO28KusJFozU8f3sDoAdJrj1jxgzl0VizcGKIiTbfW3H76O+/d10fXT4zBL8F
HbXCC8Ugrtm25Gjv5YbBki5TLD1fw7d6Cpxj5c1HTUqtvCsMZVeVKXTM6b6xO7JzXyP/XXAYcgXq
ZG2KrRFtSFjZH3hUV8NEgnHegO5heSNQAKV0NNk1K7Zjnlf+P6oJp2cQwwppqxuLcRiDG+7bN4C9
ZK4gG64FwrJ6mIqnIvx1vZdiKs5Gjc5EFxFwoHdBL2XcH/wtfEJmkSJwBrDw9S6AvAkIns0P1MfL
iQkJ2JkQvjDX8d0zKlPms8NEWOs8r/71zORkcXdJHBh1qjrGPj1xQHICqaSN/836oWRBuk6rSMZG
0GXAc15dCmMJS6wFuXf+4SVNv1knK3VE3LFHLe4Sp54EtlRaH6IFMPmcvdJNrOFj18mdsatULgu1
4o5WPIX6A6oC9EM5zjGKc3dqrI7DdX/BCOpJiOjglH8Z8bGeieA0uRsrrN5zOJPF0k1TVL3VR0kd
Dhrvrd5+TBPaibnqBX+zF5eKe/Rj2KJywnK58HNzmdGFNGQhcx8XS9F1DNtnpgSobRbUQOM3TXro
DkpY+peeaxEiBbcA+h5yPLNq+3lwaBpYI1eqnekABY48F6I0nGoTwuwUb/zRirYdfcCXEZGRblWM
qj6ncdFHbuQoptnAhqto0HUITSfhb4C9riFF4hs/ELH1lp2NYwThn0q+nBxS0ycTbtplH+WaKwmF
TqAaAKlLg1xPqOAFoJ2DwRaaU3OJP4UdYHHlr4l1SSGQo7VleRFyvs1uBG42J2x0pOqn1fau2nhP
yxROMLAYxHIvLJ8tB34nlvSRNrN24YG8OyKLAVlzVuvqQWMD6NudIgkLpIqsavjaB/w0KKaS5v/l
1hlyfXhRpIeFXXJQwqIi8xNkG7GcAFPbgp8nhoGNsoAbhlq1SqiXVDsGju5Jvd6lXpEIpuXCroPE
TIf3qNLtRxssViDHZUkcUrislrzlMmE/US8YodHDx3Mghlj0Ux3fXjj2x4xDj5wFuxqA8TWA1pa7
dRQhHVj/wCKnFGBOYO0DMvAAm6Yjm6DLdfujk5cOqmv9otxef/cbnm8aSI93sp1QcbPHD08Eva1Y
SoW7eXE1tcPsUZFO8i6gvxmeEktPvIrOL/wgCijnZ0dOpHAVMcHhFEudp1hdtJyEN3fcytYYixgV
zI21fWrQ7ntDKqQbyMBeg7mfyw/Ufa0Vv3MdYBq617Ps5rbtjQ8e1axvajpw+lT3I5M2BQHVjGNz
YMLQuYhnbWIc8QC1nwu1lgAXuILzXNc6N5iPKXxM9/eGd/dvXrolryhbH5MC9WpNX8iUGqy5+AWi
deMagdL3inGXT4CDZjVmvJjyk7Tn1pq2UAf4r6xIm3qyNqxfZB7DBVl27ItBc5gAGH1S4b5WcWRn
WxJNESe7yu7Lx5nRNqlB3EqoVZCxEb0FxhO/xbWUXLyWXlV/25Fm8phBowdxbxfbA8QeSbdZsFGo
MDIs6KJVDOva+yctWo7iZ0/uNW1xIWBP2h5PYgdY6PH5XNzdDSXb877zgpHd+J5S6OQ15S3bjNn3
6bsZftYynhVPdAs0SR3x4FO6QZQy/z9e4d03F5jtyzokiz3mDtc5ye43VuUSAkjvZACVY4Qnh5ZT
SrHBfSTHlgynp9BCTpGgn56f1JpUkXxELKzAcMWpIsqIEF/huauDWA7hUvqM9EdhzPUfmlzvbMxg
oJmdXMIGzzErOGuubkSF4auDwrTlaxHncIMvBp0rxLjG6A9wVKhulFr75N7G10OYdtP6sz9VzTMB
VwCS+3/fQrnMrJ/2ASnJzdFWE7wRdjMtpXG0u556ENntCSEkvtoxKqRi4CfDPkScK0neztW2p0TO
W3Yq7OKJZWdNITnyKYVFRupnx5WqBo7YUc3/8ImJZV0RYCxI0c25DOfk2+hj7kKlp+dpjxAX+13N
39M24LCxFV5qzvJX0YZqMP7rw/tvVu/HYkkhx4edidTYwm1G+xDCDggkfoudWs+GUCjFKPpJi4Ca
70vnWWcpNxHq0XKAUHeeMBtizBOMv9xX/9DfDAsFp2eCqY+Q3aK+muwOKnlWPTz8GbnifTNHoByf
hKis4T0ZU52IMhK8k9DTtzXzCPIgM0e5GJfVzHjA6FpV/X6Pro0gAv3hZrYG4cmIfZ2fXRA7mqP6
Ig3R90uhmrmjNXbV6DVS4tmfg0ajDM+2fg203e1kb5JOs/41aM3AMvIWLo0ryIe87z1IqGJQOaJN
0JZ5nxzwUGvYdLeBcidY9orc4BA+Apq563hdCMyEmcInPYEN6wz5zqTKhfE7XcUXwyOh/bZuSCRZ
EdgtB9KuTrLJPH98xM7pueoFCVM+/VT+UqmyxAwt4kyxJEmk4wnFk9A8/eSWxT/9NlLzTUFy/ze3
rmB8FhHdGBdSvzWgMztmuQb/2QDfmCkVtuQruVEpTeQXNOVuVW08MWz55bryTJWNPVMKJbjrZBAW
B0qqpUFc7oOOap9yHC9qaS1vbQVsmse1OoILWMzFyY2qMWZfpUHTBD6kabZ6uhoh5fft8C9vJ0Rs
/jGSqF8FHy1mo5CwPbwSGtpuC2PV+EEAorZuzOBGiWC9Mk62kW619cYt3lTQe8fxnSIKKlY21pH0
AqWNmSw3end/U0TI04ufHV8mgp51Om/yYmMjhthAfukxJIgH4XqAX0jmH12hZnLEsa9uBYYaj9hi
4TuBYBDl0Y8i/7gHI0THpo+XoPO1/K+e9b1M0g7NF6vCNPABYXp15IRZBxgdTHavMQSx7y85xdf2
aSw9SfgXYGXmqpMI+24JHskFH36WBMfrh6iwIYrQNTj7oi9arEquu2LA6Vgn2eK9Kmes98nhw3sb
+krORJn3If/MprbQb5TeSbzY2TttNPEdAayacBfuRpTMemNsdWhTtLYu8ibvgmOA0jsANk3L7EQp
5ESVAKZjOhqq2vTG3u4gEGBSqDwnsBW7Y9dbhSf5+Q18FzHuy6TZJPHYoenap8DQvTnfXvgATUJm
6MuMzsiK6f5o6WZe0XK5v7qOQxgxfigg4z1jy38FzfxUSP4z2sD9oyVlxYgPCNoZGbNrtRDv4raL
JeZLqGplloXqk57lEWLJ0Mcb15ozgVeCStMnXcIvxfccOz0wL6458hJbltni9q5MKuhrObhpah23
x8dsyqgbyZjLV/Khu8pcLnwBSFa7j7psgnQ0TB+l2ZapC9/uTxj/IHr2dEmc2oklLiX6zmNskoY/
5qMfj1VXY4yD/6nE674ePEJgH/sJ50YDDqCR8OtUMzpqAsmAwqdn9YVFyHADBpojqqvPFpQeBZeU
2cJyXgAAVWKV8kUmgFCmgCtpQMetuKgADxd7HLdaJOtEdVvg71NKF92Ok4UjJPtcOJrAz5Ym8MCh
aFwg7z3iD4Wu0mPugKh9lj4g3OQIDofo5O7QhNITuC0n50pKlnl1AudQ+SBJe4tmMojNPyw7NKPf
zyOmFWCp85SWc66LO5hICDD373xkEoajhsOjk/wBbFWZDMBDQ7saWxeI7eY6SrlDtPwaqI/GdI5Z
cOr0xC0kXWJf9lku3pHUiC4bcgdWVO+khyQq3cgrmtA0+1RxeCihXgrT0g4IafwQaE7RsDHfn/qu
TJi7ukpPKhNc1i2rZHbovbKp8phFKeYheOY7cfv1uX80VTDr3eEsaA26d/nZEQfa9FPDL2T5SbaB
nDwJjpcHYvPal9yJ/pPvttUFVr5RhXh5VRAaCrkzwqt6JS5X82GMCyfnVUd5gSjvgWMrhAVSnuyS
le8UPGMJbXNAYKabUSqCvihDNxPIP4epYIOq9S+R8b7je1OrnF3bz7+hnGyUErrblzjM+GbPWPiu
yM5h968nE1A1fDJ7g/VNSN2Mr7a4QdLsfOgbk07lLkWkw37XY/p9BF8hVKfeQa2DXBGpKH5rDy53
aesRznyjQhI78cjzKI1us7q89uzKtum6NvgyBNyiJmRDiEYn/H3zxZbvqqVs9Kgr1OcIdtpznXrg
lhXaVGEC4Q/ZGHmmqn2ftCZzzPtj1HIJWJmZaj26GJp4Jxd/OHlyb+Y992goI15jtWJDnPud+f8s
65VjSY7cFF+AJPX2I7VXM2b+goY6gl8p65Zp4/JIsqE+0JgWKK4XRz+XVBvnl2pGt1Gdd4ue1YQc
UkbLGkz9pkpc78U574NbQFcMn1VrcrThioim9Q9IhHhdbw0CGp2UL3jlz/DPtXrE0KijlpTXW7PK
kwGE60XE8RGIu9hrfiLplQ8tgllQwrh2kO/aMMfcqNYBGzAeH6Ow7c98+pIXwTiSONdlw7M+Pnqi
m9V96DN6zscWcRw0spGlBcgKt2oV/yEHsOanK3ziitkibNtBJel4+vEYVQonnRm/s3WUyLhw7Shd
C6K78zraStpyn/AQmBE3Rg8EZHH1NUsfrthsaRX9WRInWHooQeLSNIn5555pXPYPF9l6mZO5kH5j
F+YaVdD0N16b0DwEB/hXjQ5RIa+MqoSPzANtNifLMvprkg0+V7+SdfsVdaFqDx9vJN1TLlyWFn03
mzqIhuer8lM3HPdrNkSWHucLwI0FWpX9pojGokwc4GfebOC3kUcSbuQXH8AkFdyFw9JrkLHWEbkY
vrU54r5APVX+Ofw8cD8mZkpKAcdYoPLqwmG9MmAXhhASSXJ4KaOw73YtnUbuF0ihR6MLYRIVfm/g
Q55oh8V/LraeeG8w63km/6xtc8bxGYJs2TFBN1S/hO71OV038KylCRTYYM35nxejGo6HbR4kjCSA
VzQyfL2l/ZD5fv1/wl/YlbOV7EjbnNkYO+8c4I7fm1VFXuTFtxHnqSet26pGUNHtkoxvHXlPn8LX
29jNzPYZTB7jYl2tmPSxlldI1jwwIAaCND+/np5MmHcvXYBsOSMF7PInw0PVRzX0emhAsT+YmoBQ
PKj0smqPyt8Bm7nWgoFQsM/WFagTF3MIaWKCdIfM+JRiCi8S4s3P1W/q7Ur71wE4HNRnK5QLeaCC
rsyhKgm6oZ2LSeKiS7FYf+PMWDNmJzmcdJlDIRGhGNUXqlr4TKWrneD+q4VDPTMm9UgbO/6SV8V4
Txl/UXPNexcuJtaOnd1KQfHhYT77S67JqMmJU2MYTcOhGrf7I9KbNZiNsL0FcF6bC9KDF6Rvun4r
Y2aeg4AX2IOUsg8thq5IUIf1efgcpReUhuV23t79sPqsIodTpH51BZsF6oRgjHpSWKqyFg4tPSZU
Ing04C0g9sorENDQon3uGDVVsBed+tQF7DShUxHrq/2jtdYcuzIw5aWPB07Wrsq+7SRiT9ehRS+k
S6gD9iemcbZUFeWmx8eG3xt3CKnB3TIXwz7VHRl3ryr/A/K4blNhY60WV/zgCMrpp+gIEYKVvIh6
m9vDy+KZxSPh8yziXIfh4mOWJVbOmIhrVPmSzVzAwy7OgjO1RwLekTx+qMT33onWfuG/kKUcJOpe
nAPQfpTV3XgIWhl71HV9aOgaS70nkXOiOk7IGr946ZTCMkwyiYIGslaDQ3DXxmka4KySZ7Z+cQym
xAIR5wECeDCeacT3bKSxI733VzdgoasUFzXS/PYpQe8s2WgwFIte4MgP6e8Ki1cz2R45dGk8jwKq
UYQq9+EYT5pjUXzeE4pzBFJ+YiqjyplspGzDuujiS6zvOC4knwZdd75kW0GOuI7cLwuLFjYn//T5
kal1HjekJawp4Yd5ni17FemE7Y6TIUc96eHUWI0dkGDwIYdXU19RhxnaOv74xyuzPv31kTSA1AJP
DGYyEOsofLpqBD10QC76Nnz8501DxT6WXW+pLulKZbS53l4mvu2esH4e4Mq47NmGfo3E8WvMfvOd
mLWLKBbl+QKVYAzacpUVjyr/LAY3wQKaYwAUsB3FR4BK+kXZFLtkqI3MF/yNqvLhTmz5EyBuAnAM
ngpdIsrkWO6/PJu7KVfSajXampj/qExRps7Ceo2lChHZad6Tf9M/G2zzGAip0t2BDxp4cCodvhce
rhzuC2c0CGqOzEkqWrY4xKx5O0OQs/iQTvmUGttRmZM6VLzv+tkPvNczByBdwqQdMI5xnOn6EGHc
0vVMbK/+KBxlDsOGzYXKTSUnhleYST0hErlJEAFnvATGRCleQMqh0icjAOBLazpD8Ezt4AyGaX3o
mmCLdyA6NFBJLHSpQ6RGiknJJ14yMfg0oEmx3G3v2QWmnL9evEOoqlEH6J5wzggv/pqApClAOM+V
mQCKHrCIbbpEt23XnAnUXEn0YQSCIOd9mNB3P1C4TMn1xk19LL4gxSqa6Gfd3F5mvY8ON9iSI0oj
2AVfsTav7GuAZUD1pYvPMHtEuWc3j7DBHcmokXCS5Drig8ENhMW7XWl/INrh+VP2Z7cccAv4w9UE
Vmi1Tnihbp6WNxHwaOdPP9q50edyZGXO9QZn9hDVao7Oq3UV0EN5rjZM1nGa12Z2D9x9vNdNjZJZ
1DBuJ7A16/GUmlTFibTj2JXsc9xaNKPemQBfqdz85WNj6L0uq/3Up+7WIx4JKL1ca14Or/7Q9yfJ
bb2aszT3LtNwF8MVpF42Q80nFpE3pJmNSDDQjxWw4VmE6xVecFqhYtYABrimRdUk6kRgdMPQZX8W
thldsXE4sLCINeFUjDuKVrVVySHDgcw+L4ygKHzBCYhTzEKfEzWnWdjwtbU6v1ApkpvwhjVAScip
9xbEX+tPK85uczzYxLdT6WEvB9tD5n+xhF4zwXB+jHbOU6wNuwFJgz0Lrjw4VQh6wA8r/e4BRWcY
/CokYLmPcSdypR/2bUHOauxrJx+tQ5Acl/ztRQ0E2iPnt1v4yv0wTGmYCQ1ydk3AuuzcCvnypIkf
l+i1izqg0azM4XKB/UKMqtYJIziQIszCPxrHB96yOpnfzE0dHclbNmqdI9x/zyd8S5UXn+iY4Hbg
PS2+rITp9P6Ncn/1D8zmYO6ydTRKtrkfVLlNbZztLGWqbLXcIhRT3jGTQFLXW66Q5vzAlqn1RRrT
VRQNIp2IjcEeJMIvbKLQ9n7Fpx0Ux6X9J/5yBVO/7ZMQ/jFdJvxAQstVVEHGYUWrc+/Dj2i4cYfj
9yDLzrKMmjp1XJLXu/fpsnslaPjOIsLgzM/7MW+Se6b0CeyC/QDMbk4IrAj1vhpNn98UCNtenrvw
UBnTYy6x5HQRCMNjvEYgkVvp4MfFjK19fJA3OdaWH41dXjXpr4dvsL1jLRXJD9GSnEJkdKL3HI66
D22O7JGzHNvwcspbLKKLo+pA1KcVP8Z1rrLO+u0r8/SIgubw+ByOUgbyMb4exc1Ey2tnaCXUrE1I
v0ZfRSnrzL3kmHignExCVF9Z9Pcv+bG+fTcwIRH/fEwIgj5ec2wIjVr2tobcsplVswj+h0SpaARx
C59UFtVLgL7d5NW0R4v6JjoR8KKOxQ4VPxuel8U5vpvgM/PQCzi7/+P7Ci0MiLv4/ZEx5sJgNzII
E5smSHvQJShG9B9kpXLo5K0f+taSj+Q8MFbrQ7+U1m2sCQ27WIYXSsg29JIO4urBGEyfTO2TkEyg
ADNutlojup9HVjqk8Jv6wpPiRpUJoih5lc0hc9TFGIk+63M8q7IjfuLArFVq+8C2L5JfFnB4GyFq
zx1pvY6YclsXCJuX3Yd7KHplR44hIfBeuFl3tFyYn+ugjG0zhp47eR15DCFJD2l85NriBbYXqorj
LzPotSJ244ngE9zyE7Z54O6Q5q+y6yHrWnVrd6m0zohu6Hw3DuaLrq/yLKv/r/biduxLxFmbz/bz
lWBAbu67THfxj8Wg6UUS1zij9Krin/lrA05s3qz/+PcT+nIpxGlCCyhT5E4X4Au83pMtO0LRD8mk
JzGe2HXOjzNAOcBwiLeqtj8uns85AxrMQ2WFr79vKnOQlKwBS04YGhECJvCsmHl5sZOx1hNewzfv
c+AbX5xxZvlCV8xm6A/A6cZKIupYtb0OYjpKuO/vYA7hPbfEvjm1cLQmvqPEQAgzGt1uqZk4taZN
YsJTw4vc+jYmpLze1xdswdlcf+JVBmcTlqmzr5Qd+QJvkkLnQzgbWHakJdOyh5Dq4ZuatGQSyFX9
doEZ4K3b1zWV2W7ucHJP6ZQ9SsmsD6E0UsJ3Exzf225rWs9KmsoxIuQ/2o8L2gSxYTN1WgmSBIdr
RkBvzKr2BerSiw6om5jNhwn2mBKV5+ZMksEI9AxIVzc3Fz6Pt6KEhvgaFdofGQsN/CQTdwtsxVM4
a5jtPwOwbgXFh+I6+4WdJppTeunqtJulYq6R9A6xwQjtiRb6jaqbOm4ERfoRQUai1s3o/f0eRRC0
6Q8fY2eNbxlip+CIcFVEaop105LL42MkDI3cFuzSzxPQvK/NqLW9sjLtVPNd/OtAA+aazoVZ5ry0
3Tea4xtxPcGMt5PKpUfTp/Sy9f2BhOi2t6Gz/8bCPYfB+R/WwEKy+D3cSD7uorMHx7QoYsRKAN/a
4401HuUJH/gkDRKyW2lbVwcIwtavJcByYM6530/hZKkZ0JvJlnwl+ebWuSVmsXDK8OE8mtXjO6dE
+TulIHE0GgUP+X1ow4plw/uMs4WPELKzFdhyYxx6iYv1GSOnNkY2iHQt+bh2UC5XqUNuRLIvC42N
8/6bGvFhLGTEjJtUwN1rVore2h43hFvvZWbP4sQ0B0+6G49JOXAfsOHIPBghw4GGLA6Lopsi3eq+
Lz697Yq+8bhcowfYf/Jdbo2t2D6u7wp4UXhympUsc7n6wBcOjjFI+KkRZBhfsqTmZMMiuOjmRgRW
f1rDb6SLwgM2Zv5b5reZRk7PO2WACDk4Zy75SS8PlN7TTdwv96ay5Oioq9VWmhVNZUbhy8163ASk
E873a5TMLlrcU8qAVl6pkDl4idzJuz6VXf8RmCXeIMv/eZd4JaT16fYOYQEInfvCt4IHQUDBsujq
LRO/O+13Xp2t/G24L5rjez/CexXrubaPusNnGOViOwMxYvX8nAZts8DGhTCASWIQivZhxCpYiCQb
Y9DbAZZHU6u4a35YsGJdjKtMNxgnn33TSGhtBw2CLGYCLd3Jqb6xv1b+7A4vKv5RygSVl/w1ZEs9
bxIaBjJMRTBqlI7MYoRhLWU6gd/SOsSkMAMuMdLKzTpg7l25ntDykn8pUCrgRk/ddPFWysgXZAIy
6mfThdnTkT5nujszjKRg0CSzqooI60LPIFAA6xBOHNdz+D2Xz3Xh7kmGa4st4w+jZEx74ae1sGEu
fLY34wNbrS7rn7/h/oNrLTpJpDbp+SLBIGED6cqhSe1hx/7vGixwOLzowo9Aefx0MUQjbdZDy6el
WuqQB/EMG480UDzGKr9PVCIut529sssPWfIBPJIRU+jeyjDoyJ++uUSDmRL7UjwYaKlgjBEoyH0p
pJLgNx/h59S8+V5Ny3KDPa+KbITzgyjgufU8mpnzpaZAIYKV4T0fq/5A2BWLtRKm+0ej2V8Ry2Pm
NtXn1Y4K4oY9F9sHUIKYOQ63MulXvD2e8siQZEFkal3MfrBBxW17hn5wBVe0FO/BPkWuwuR6zkfx
iEC5OUo8EaCDkGTH8nQ6lshNLC9hajRWC9dzqfKdjoYMABr3WpV7AsM542kPbHalYXLLCWIGPzzv
3NN7PD9mCpEtib4nBA38tQdnK8A6Q/tWj3LkuhSa5kkUJQySTJ/mIg8qomw4oAoc1c6u+LFXGiGK
PINqEwFb3NGzNOrbLZmP17hYcn1SilQVlJaxdK+DV8BW45c2iUdE3I5+LEtgrVlMTO495Mflhj1D
8bUFmBe+lreQuC21mRJs0sCLoA28XPXEZdlnFK54lwxreXjTadj5Yw1/nW2/AO1pUvMWQ16KVNwB
mlMz3mld8aPvuaB3qQ47/mnoZT+2yA4ld9MFTGM6zgX99XSZwSf4jdn8h0MAgxLMmG8V6VvzaAPw
BxdZvDamdlaknSHOv10o5BvzF9/R7hkLbRhrSL4Iyy+gfR1IL78bm5O15Ug6pQ5Oz+e8EdxsSss5
baNMPjd734+zgCdzMw0inFSfmBAl0aEsgKnO3kome/7J9eQoVktPuYLAGPaf/c2anWSZJm8MblFq
zRHKnPZ3o8H4BN5xvbPEliAj0v0v32VSiD6jMIfeTHzLLLRxl+y3thu8xRTDxPX4v371OFfNIA9w
tpqTkGgAYrzvkup8p2NHN/Ho4nmWu8zaytbQeGnuT9K83mzsC6gO6I1SypP3Trgt7r96CWC1LdfG
5zoLm/kx7lSu6J7dGav7hVNxVQ3u5K5Or76IQP6+gyCWN60g2Nh3RKnsV3SExYk+QFKbXSDRzJm0
J0vlTpO6jdXuHZ8mGb8eBFFo/Ci2GHaZSsHc8/3XAonx3SJlK3c1dqWotGgFistkkzdMpcZ6k6hS
bcfqkcdMkRKhMwp2gqzipg5SRGwb7NbfGLefyk/y71qJxIiv4xjKB1VZ9UkaURm2g6kCf7JLT3tg
G2LfO9WY4cG8hZRign5v0PbHC/EeT5gAZeTTVeif6j/8TGOYV4V46LlNZhUcfYBsYcNL7xJuqQEW
10bZKv8BTPJUpdqePtasG+6xauLPgaOfjxwwBOIhhyW6GfhUgb90cSniBx9tAIS12Lb+6Oegu37u
6BDHaZiMX5MgauNcxE3oFIbo8I6j3q9A57vDvQCRZEyZejStxRpPKTnaSCZjI7JJqSZbZt7RRKsA
QJup6fT4pV2xomTU915NMt9Xpp54ZIB8i0HmyKEvBhfKCUB9bdA/ybUqjrqjzFQhiyHG7GRC7w2u
kNzNxB8a6JIa0/IFI6oBt0YOrpKCS0P167ecsEonrE1j4sMwFcN0+7tvADSm47dv4a3/5vgUI4EX
3/m5QUelh5EjItMBpwcWFWOSvkaWyGgI/75cw1wLKtlv05DzrXoWu0XpbQvJgtVgjj93gLU/yNr2
yrKJmnwD9bkmt6c+XG9nNUp0eV+o54Rkxir423NY2rwZPew3Pb4a+Gs/3v5ncIz9ubkInkoVFCZm
18Ib+ByIEZ6HIg+sqT4DfK8ffqMDe2YRohLxyJXTdDexwv9efFxTz48L++lBeIGgNNN27RZOBCmo
hCrpvQvTfrtFNxtElFtHqtHNqVWYvcaappdrLDSA8lLVn28GFJi5Dy8+JHOqpZLzrxbN17LuzVpT
OB18MstFZDDDsW0CjIvbh1zPZd8P+VkV6asUiS6jqXn6ENCqSQ+HmbxM/IsDosh0tZ+QrZLDZFQF
Fs2UQQkSgkifbG9wurcMFF7J3Z+9BEBM8gH2+nDCjeC3mMZ0rdf8iapRWijysC/TjBrsR1UpH5iZ
Cdd0Zl/wCbyH83JyXRLCTPuu8cSdeM0D9X9Uv54LFUL/48JC+4HXqxfNqQuTwaAFI9l5lYVz9JFL
k32ihP6yIC8tkeTEFPymMgrXBNlrGALiuxBcwiRrfPwyw0Jnuk/N8KAbPVo0j4IKmJvmb1idphGs
d3VdnwwByYWvN5s990ckElbKabDkC+BRpTjuPZAC2p/gSugNl34eR1eXdUVEAdf+YKbPdIDxAAnd
jeHZALXb5obTQ3tc0RqtolCd5MAYKPCjeRCHpLh6dq6V8dbZu9uvJ9NYAyWAjwDBILiPz5yNih+4
lQPSqKF+8Xl/v74hCgrOHsFpHNp4CtPuy9EkKQXhdtqdQ9bQ/JpeJTRKvKKqpYUuRLO73++G050J
HYHGJzlGvuwQopz1TkLLr3ePJfcy1Qj9BWPpi6SQzGhI7ZohOWH4/AcvXGLSGCEIrrYeHx0j/uTt
HpsrqJ3TasCRVhadQBpScIc0MHbQgkw6/kCMsW3ZLOkgABlumM7TvOD4ZPITlbMaNS+46eSeOQcs
311LiQ9REWw7FUK6ofjn+z9LiVNEeDgRsxTdLyRVuKCzPU8PjjxrC7tdc3y4UNBsva96ouaGbsmh
vsBT/uIVqMzWGpNhL6EO+OI+2YwdmjqPdl0/UZa0e1MznpO1H2TKeidP+Azs9BisbjvCN9TprSVk
UvH53A8+wwlZDIA0TnvjwuPyF9uTKsOtwqjHpuPpahw3NCzhcMlb1o5nADSlCIK4A/7TWFfwAr3F
awcyU1ZdGNLBXbFvbyw0yXv06NUsFWr0tYnG0PGPj9RJcsmO8Fd2KhEVhUNhar5ZRvyngbwKbnU8
lpprxtrb7m+wc/UFKC20QqtJOEs5XPZHQEXV77+7pQ+eGQL5UINSD3N7Sk9KxP3chRv+h1S3HSD5
e6BD1uhJ1GZMKCfeIuxbxdK2eWOA5qsPjkCSjrtpryuHKqotvQJtiC9SY2bP8ebpiuv+R4+4p42t
o/1LzSefRcoZ3y9GcSJ4uDjU64pC5intN/LJkfAXGell9/vX1mNjJYvXoKUAF7READwPuFA4LJsn
gibIYQ5n9j0kwdkgvW8eCA8DNXCiJLtSwOrzpNoNsYukxi68YyGYQUMouXkNes3rVuPDQ7cwtuP7
hZoaBS4NIAYNgCN2chVY1Sk11Xrxb7Uy3hztGHkiAJ3cA7IWHJc1OXFDtzar/zW9fUIvBOAgk2Ej
LgLdSYL7PDbTJWUtFwV9OrzILsvsptNtu/Qo2cW9puOEfrD8yeBAkaU/1vHyrxop3DPt+tfoJ0K7
7wAzwKWh2AgPGXkGs2kuDanDxYU7phpRf6QdMLYOICxP+EFUVFpRiT1TOoCPhiWUgJn30MQXHeMu
8Sfh9yzMvQGw6DjDK/FyPHvNKGhIwwCFft+uhseMAwoxK3eILyZd53EFB2i698GNXAMfISyEydlB
NBFFOhSLsWqX7nzaj5fvI7hVIlspubowOldBfd3IcfeK7z8zdela+vEsKKGwZAxm6qWEb4b8RE3g
Axn6wingXu30F8ZHYlcO/c96pjDR+A+dL8hBBUmHViq+MVUJNV+ypZgQn4jqKfcRflycVmFTyXix
9cu++wJCBFQs4EcOoXIic21s02D3Fb2MWBtN04OsBTkwlu+4XVPY5OL7xpTFZ9R4FzZCsc8r6RTF
81Lgvk16QOmuy6VHuDJXrvtyr+wLDLJbTCP5LBLZkuvXxs+A/LwlffTO54Jk5Tax0ca/qN+elW60
jOaXdVifKMitym1Wdrixz3uMjzlAZzuRZK/sk+RWqtqKqIN1ll1Nz80GXeBLDZD4eORj0yCZuTYX
Wq3AdyMlsPeuGwhh6IDxDtV/Q5lrzmqwiGESZhmPyz+/ODKJohWueQWdwGdK56n4DP49zaK/eGUP
G8xnKgMNpEQZCw+LXdAROYgvR4JPJs6KxxacqOzXUUZJ/uUlof5OaRXisswnjCjXIFsZv2XzMLde
U3tb7jO6zbk92/ZiSo8MjXOYQTqA6IHIpcx05Q3uGPjEfU98/OED5sYVNwSXw//763sgWeAC3vno
S0+ytuzXLuItI9Hqisk7AO4mTM9wHycYB9oy5jwOg2fRWiFBy4+k53mV9oWspHbgDhhduYYJwFFH
PhafzPw3ZPXreeZjV+5YMhN8Rd1TxNOkZ1r+kE8t1RSvr6/xwtwm1rM/2RPQKw2Km/FlC4WfdNIr
dG6GBmvtd/eTe1HgyApSo7nsCNtORvviJEoGmIFIdUeARhC2nJJYn9Yi0lVZAyy8XN+6HLjkY8hW
0Wsx5sUCzkOAhIEGO+Qg6vWGMBZLkSnzEpBIWMlESwW6qXC9TjyJdHXWW7Z2N4jeUtUXBiAsNf0c
VUBsxVNePdkMa2RIYlauySz5CKbbJ0C950CJeEzfbxXt6fDfoQx6mLXafBCNogUh8rcPsaRjaRQC
JM11RNVyAaoWRd4xZ74SHJZa2QeP8MeJqBEaphC+3oSfmB+YJNkgminnu0FoLyik2qRpy2yVUBTc
Re9qr03gg3OTgpy01d2rIm3ata3X34ULqEraVfGvOCUyXXFXCtP6rDBLaAY61Ia27fbEtK3h0jFJ
zk5x1SXLuoXX13fuGCRYzGUo5yR+HghetFBm+IgFM8Q5pxsqVq7aSBE7lwgqmfNlod0/JicFXhwj
V7VKRUGZF6YhhMz9MUWlV+xiOv1RPJyHpxE7KfSQl3bvATwq7mTR4ezcfAYETR9Uk9Xwp7kxT17v
KxQ05yGf+LrdonejdnD1X1NuVfYz3WksXdwF/VFrengazXeTyFeueApR8viG4wPD4OkmZjgoT68u
wZ7Jn28rEszqk3A9xXb+SqSZt1tjoZOdnA7Y+s+jiWh0r8eD2V9ZfprC7Sunae3gd2MWjb+JKheD
GBkkCNIIfTfqP1tNfzoqDdSWqjPAc8a1TpODCBD9uXB9EcuyOKhNJyRZvu8vTnLkhFYB4Qm3lNJ5
y/KPbrCkBLw2ZVw79VCXofINBkq0mm2h32wTMWOt0qExwJgT2/uU1nr711mwHK+4SgeMbZvaNHBD
6Oejz4zp+tqqTw1dbMvXu2B7R8xvg2tFjXW+COd1SB0JiMBOyfw84zF8nQQk5ZHiTESl0//A9j+z
B7ceNqrlE7grRFDXLs51hYWmb6Wn5sx5+qhTCL2Y47frw6ISSsRxbpBCfkd5lRPKQcEY8b5BNM36
w1O2Mz47NFStRY3harLUwIGSqtC4dwbn0qT1E2JJkGtjD/dBplySMU0hj/GniQt+Br2qDddRmjOA
WH1tamELjr5MRS5GseFjrNrYQepLo8Qu1AeVeKb6kEQUnlykuonkrowws9Vy6rWpeDUFI4ie9BJm
INyfBw3Cic2Sesee4mYdZdfntGTrl5cE/8wIjsHunv6aYp0jx6lXo7NKsZocSrUZXFGFjAK8gxli
iQxwLDbvxhe5Bo/ZZsQXAEsYAN0kFOQAyNHhVz2uCw4IaGZI65cB+VtRFjK7m3p2GUv9vi6pq3hC
VQ2vvJgy/lPLKLCaBMtF88h7gHFNeqqbuJAf6/cIoD6Qa/wthdaaofwVYpiSdY/CD6dGiVGTEPNS
qK1Iufaj6SELvCKWUnFV9MwYouxeN2IhrwUqZPePmSan3az2Ir70NpV6lqddwl1gvIIIxAqyl4Gd
qpuzWEzjmw57wPPo8/VPQvxoyszPcQOKxdGWXBN7V63trD5dfCF2NcRJ0HIzwSNBFFgTSSCmEqlg
uycPvu6kP3KPfGycLOXS5XGjUjwNQ7VQThlocgTJxFVn0BlL6fOyLRYxb0MNFowGse2BMqre12h9
9bmHacwCPSYMk76BkxjgnX1rCd/vLxI+rIZ9nYd4dPv7mb8Z6wNCnk60vR+N0HBwsMrtPDFxVVUz
khia0KVYJ9aMT1sVl5YD2wsiFoPKPLBZsBcZ1gv6/EQrTzPFA2sOqjbiACtVAoii0QeX7qqHwu3m
kh/bFW10Sb/MaXRNq8puLkjeD6tA/IL7UW3pd2GuzRJe8xK+oTY0fbIeUQsnMQUYZYAGWnkOn6rV
Q3KzFlH3Ks0aobvP3khdUMtiVkbCHWRt7KIvbRq5678Fz0A1TjFOc0fTwtxaYKUWR2O1gdaxWoVf
DxYIAa1xVfKWSIT9z9+dOyq6z6Ad0q5DXxiVdpdn+j0UxkRrrXp33A4xijQ2mxn4QvfheXKp59x1
BfQgz4hpfwmCuwrhJTD5si+MnnNG6Ypw1CXtTtixW5hobAGQjgPahZZrdIYEZ1tM9UN/toj9D6/n
25oTx3YxJen850uyw1S+6req2tl+V/AMXhGUsi5k2XeUb0GFue2svx2e1Y0y+DNujICdVIXCK2iP
E3caFMtXXlWjAb6Cn2/jaVNg5jzQEzd/BKIAi5360EgIz5EYs2Ux5Eaj0/wIompNm+I4rDbhD4zB
nnHogiew6PNnmb4na4zaPsyLQ1qyTZFBqLG7p6LhT69G8++9iNDqL68PG7dO1Y+6D+YyoMlCZNXy
L0pRx1LP7T6ecJephJr2rTKGs+7Co1IazGgT3nKdt5XMO7bMU8+JQjKb5pw7kJ3Y6tO/HVWazZ93
KGIJhortQMgKc9DbyW3zEkqtI/urr7n1GBnjA/n6LIVUkM59TeG//u6XJ9bkrJNpfHVAS+PXCxbD
7oUukJ5iX1Y25NIQGWxRKZVJb362+hkUY4UbMoOuaApOF8W114L5G96k28QwIJdyvqjqnl4XhH3R
pH1deJRi8FfWidzIRFJAxjuG2xVpVY8z241sG8bjSg5lnR1Zys+Rbn6IAp9gs8N0ZiyxaJPA3nsM
jDohk0VhSq6z4BjqdXb64965n8j3Uk3FWgifoQbs+c4LO25m190JZ++vdI/tcthw9skwLvLRhxh0
wE60dgKtu5OJtVxT0ghn9s9y8daL7s7Sdss5I5Zplza3Nbq2SyA79bn9kZvbQ1//rF147vZ6xHfr
FDev4qFmxDRPh0SxSfWtXc93fgMzKVWrqscndxlJnyBWrv9uk9jnLOP2NmEUCi+L0uFkQ/vop8OT
j1P34zkyqwOK3fVNaj7XNdqhDd4sO7Kf93hxaVnS3DLDJJZG5Svcmo92WQiNZOdp6BIwJ2+ShBG8
4c6ZUU9kt9BU4Tac3Rmh3N58SCJwphOUL98sy+2WHrDDA4W8C8IV8wYyVtb6JL8eOgnkCCLapAcb
vlA8zH/uzU9qJZf2tqvJvl/6Ew2YTEBIz8tz+Q5YR6GWpAfHj711E0NHmBh5iWXdZE+cJxeqj/sH
aOom/7C4cof7ZS3gcz4dl9whci9gagcGdCBOp0tkomK7Rt6VIq6AwHrcC+tJwTzQZzzdZoduxUyl
QWYbHMmx/O9u1FKxcEF+RJnseT8E+PhhSLkr5cSNdi94L0b0+AeoUWbmZnC57qSunWjwO42ASzW/
V0dhSsmBkY7f+ERhnvMVms/ajA/+ZmNRnK/apdcWIdf/A6p5iShRZx2rftwKD6r2/mByRtCgpQAW
5w8yKrwFIltzfnd8FEKsq0KEzjWMhKvXZkbn/FPs+I9OUDhLvHqVAvip9SdTqrhuxPcH8YId9Ezj
TpvM/0fH6hRz/rlJmrj4vfF6zvkNiUo1YRFOIjogFRc+vz2hZMxuv3Q4Qs1TAwd1WTcsSFZzitHS
t7q+8UW2MSv8avQxOlUqQHkxKfmmJgyit+G0XGf3eK5lKhMyuxHeCTFFX1F1xU37sT31Ah5uM6Oi
wqanUBWNOnXL5Q3w1jN6hWe3UljVATnSgT3TvDYu0kVpSSnnVU6ql854pb1HmciwrM0A9knx4i4t
Izkgyj9O8Xhnx+4p/KtZr2zqSw1AIdB2/CCWSMPJAgJ709fhM1inrj+yXkt4qOQKlr/J5q137qTe
wTConVZdE22aDwh8Ze+IsGzcMqola3C64itfcFC8PJtnei618MPhB9/u8X3REsdHfj2hLrWIKAw7
1kVzNvohcFToiRIRSHmnbpGChLteKrY7NkgFqG3uLj87ycx5luEW5AsbOlLlm2dXvYZV6N79Mi0R
kEUBs7bnjpGEDqn1tml4wFM2VJWcai/jvjpS0a+FoYvrGkNO42XBa3Pqw9Lv5CVAsD8ry/5G+OQG
g2DFgSdKaN70+qrO0ebwq13WGent6sRNnGuFV1hFX4SLtmDZG1uR33d6jcnNfoDpDB++9v6BPVKG
793iCNzGg6mfOCRYjKoS6NQKMuCgpKZe9mdpCh7DhpU4rX5ElO5N1sIr7z7qRZBwVeEo+rv1XiGu
3mA6tOwWUetH+M41Mcj8bur3NtEcTAGdMqpIGUK6p39E6uJIdilNat0E2y7u+abm8Pr+doTukqE4
PJ1XOgUZlWbxPtVYp2aWy0mUIwoPdSQxpZuNnOvwMsRqLiV8CYKgYHp8S0ArPWKkMojZyaRyymmO
ljMUdzuJvtsag5fPIn8hxjLUNjmE1p2szFpThoq1XAIcNQYOU1bOrMygvQI47sohnJzZZDbmwkv3
lBjbbAmq5NpwjiEHwbbRPwR2UGubMct7b6vmHB9/3W52WryoOfzGUQ+bU87vYo2JgOJq6HnADKz7
v+JF57r3gwkbPexy4iO2YrfZVPh0/vVH7Zhn1pHjRVlE26Z6rBAlrVG3sefH1HTilWNV99334VlC
fDSkXTwvMDaOcinhLLxlwtygawi8xtYjJPKUuoThk+CGgX3pxEhx/dmsFvs2Y5deLy84Xp9SiJVN
wvDuNJzNab0mR6eC41emJF7WDD0qwHf5XjlIDXgyCoW+DYE17MpZEdHjp13rnBtbPCH52lKLMpeg
j/gclq+26uCKM1510vBY/maCWwZftThwPnZ05Ah7e4M2pkyU620Gl9Tg1QSDP9ueFvqakFh0Ve6b
ymQtLNX011r/JZxPKx9N9vfdOLIJlmweRDH1qN0TC2LciS23QPs8PYhLJZKuafXiwk24HTBZaDkp
1iD+nXzZtyZEPtcTAqRmHttAJoRG8BuOMD7hZVjI2bAhmeAROZYdjME1KZdTSx3xvl8ab0PsewuA
XouDpaaRjuiSmbPtEocIlz3ZCmIU0IIXIK0K7GsSY0Zf/+DftTK3KegiPK/KdynTnewFNbLslMmT
mZWdZqwaDLTqDfhfjElT9fQgx1Cn+/GMLHO6eSkhdrzhBRj5Q4kkihO/1NgLe4aZx0inf2/wvRNE
xIh64id/X2Eez+luBl0IFNMQmFj878HTo0nO8bKUgsUX717aCKKkayvvF+kNOb0GL85oGyWFV9pf
ZaXDGgrwcohOgJpuDFB1bv5+hAXZHgYTTb6hmQ7vJrfcx7uhObaLX4khG+QY7sj7h58+3M1+ZuFZ
p5/zMbNovaI8yvPD4HA81mFv8//qvkeSn1CXjxLeUCyl8Qc6XwfH2Pvwv1EFU0AyaOGnyNMKn3cX
T1GarbnLe3thuSHvIkdQCTi1QXsRL4+i6IH2yGiV/lTMtCtZaM56u2vKXoBkPz7p2jmBezK9+LJ1
JBNZzPC4qhpPeIV9eA4AwnFfDAmVf4cUnO1P9qhd6OHJhB8hFWxuDViJM1QdL4lXZmsNGYD+RrFu
0axQcN0pEK55RoAz16PCBPtEz76kF3FIVKm39oo1dBJDI87S387R7BxooCqbkZ157n8yXvBrRN77
8CEuqkPaGokIUhcq47VdKC2SarRuF+gUWR1AspDFXutzaFd9tB7hI8o1MwbJjlPzuiDYYKci7/Rg
QW504YRKRJmBN483LRejbGqDt3Ff7WzYmCfH7vKIwoVIFPZMKe9at7rQ66rjcbuZkUX72X91syF3
DfPWDAA5gNMK0TSexdD9SCEThIIzdw6/xC+ScTICVQi82gJI2zz0meaknE5ciTuEqqlKwdP0eRNu
0nYgNDmNwTjyTQg1EubhviHBl5ObVcvgd9sM/gxXzsRij0ZM2sWaEJ060eBNZzfc60+A45DYVm17
vsjjHNRmeIKIdu7t3W8qI3AxTaSOnDa3RDfI3dsqFb71pR+5kb0mYPNX4L6+5qlBw3RKu1CDnIK5
TnYTkOUh5dqOVrChipnvQ6lfdDq+MAUnIRof82xkb35PXlGNyb9h8uodZXoaZ7sPPRBApJDM/FE1
YPb0O1eAHkyQKyozpkY8TgQ+fOLKUs1kvYeFfRT/E4yec06Dko5cfDNPAq27vzBZBhvz1y9hgOx2
CHmYsJZEx21HZ59oGb9qZcGvUh8tN9d6qSeADvJTkbpOYZUNc/Qa74gj4jEfJWCLYxoNlt1T2Fis
bjL/85sueLZnxOW/XEFWtXX3m4RZU5XLR1JtxOCw7pO1l5LElAdRgZrJz5qLDNie5VidaPL1321M
/tf5rquVJOXPfnzlna07tjMW2/0Fl7wuHKyjBN9iE0RGKpaFCuUdavupRzIpJGKem7Mxum8iBGrU
iKH3yPqjVBuAvPswOFZrw8bNe+MPGNwT7r56LerOAZjoqURhEYyKm8jMyBzmtc/gHeOoDOEhwidF
QZIIdD7BYDnEcKxzTo5cQcFKNMuNWnkGM9WCHzTkiNWdcZuXKfUlR4qWOMPFAgMk0Pg5OnGAoKm/
GfUarqxWOBBmq+7a3k6mBcjCy6NATIyFHNf9EufWdEG/MrLJ29CNsQuG2QYVh0LOSoArAUincyB2
MkzruJ57YS7ad6msKEfUmKV7Fm+4XsVlT3RAD37fFB80JMya5CzbaA3nI2+9tj7jzzbPns5bmiB7
anHfx4gxyRG1jQHYrdKPMk0hcxoXqRRWvzCqeIbCQhNDhLR6YEON17VDfRFg+fOEfOcVZgNPn3vs
oUPwSVA4dEeQOYXl7B9CPFBUTd5944N4kJycA/37soNFC2dutmTWX1eu4ajLhvN/X29cxbq/kaix
CObZnfahMGuLee9orgJ5lExlTSh1upfp4yG58cjEWHKDDkFG1Fl9pauavzrBlfKNcZp/hR0lCZZD
Q8i0zjkxtUMMrAg4OI6GgTjOp1PoLtEke/AyJKu+7VVik9bXt4rrz1PTv3CujnIDiGQIoZPRpjvl
F9Ts7cRjnU5XQAnPhVy9webaYAiPQY0JB8tWJU39q6z7PICQmiIuHMCWZgpxfWMTVKLOZMQh36AV
sfNgSzspI1PIEDu9gdIuuy5lnCyQBmmfjWIBgCGUfGMHBVnsB/gH+QLnhBYW+a+DdyJoO6cYEUY3
LbN3JzKl7qkl617NP/WOBwUS3VaNaTNyCMZFy1IaK8u9w8LxCbRRvB66deCZUQbYZNmQjsjbR43G
hDYDvTM5PWKBuduDEEUU065aC31TrM41ZWT3QMEZ8QScZKMR5oG2C13AQfFfqfOS3QG0NmJpRtpc
bRdR9I98pp9Q1lEvecHIdzrmGxeAAaFL22cA/yRchxbDs7eGRfqgeKup2WBKBrDmW9CzU9GZ9Aik
xMHr+TBkHOkmk8DINni1NH1S5MHfcIC2e5grF1TQ1oMbVEvMylsLXhj/d0PBNA5PCpbYB3uFNT31
E6n0WmLCquuWmQgLJMIkqL47pf+Rv5oPDaqdbr8J8zsFwnViEnLHMF5e5SdkmNE963wSbLEchaAl
nj/F9SENhczFC4WsX0tHIq81OfEsUtFk9Z8zR+0qwCgTCqVRab3/p7Zb4blElpYKDefnMf022W+1
jERfPLkVw8eoiC8CKjvUjI6Bgn3lr5fVnMkLDmwsYhmiSDFz58KXUMF/iTxrRW8OLGfiDLLo5WXT
FR2M9dAA2UkNC4A3oyyz1IjVoLYhWJClf3bL50QhjbQgh5U7BabhO1jCZeAB6r8yX3b6mStxAIo4
Lh1q8eZqxdgZH2nSUmXtfjzMp64JJXo4ZWLaYWk+ACK+fLZNDpGaJ7yftoJvB3PF2ihi3cVCIQ/l
/VTPCvsqwaT1QOm9bUORpR+JJ25zD2rwZk3ubri75Bwe14TYDdvaMQuGHCDikVEXwu5ViqECcXot
EkMYECuDCDq6qpdjHw8K9kmNrutmnO3XXwI1T7Qtg3g+CO9P96BdQU2bWtFeZxA+QjR/QRkw9xcm
NZzlV6PHComocboA3DMMfl6umiCEyk76eQcaJPv8ETE7Qo9G0swt6OM4Sv34xWS+1lvPNaQ13Mh8
yi0X14oUNNi/SWbPUzw6jexTbmkqXSuEzxArkBezLevcdDyQPoXvO6DEQR5UxXsWp7OUkSEzJwcC
6USkSbPuMye9kq9G/d/68PIZzsBSny1UDpGjwAhNOvXmHX/+fCSTnxgmzw271IHhmaOkmLiyav7w
Vr9kHOGcc212S32PhaZusxloEl1IOXNqzq1YpQ1Kc39z5NIUFW2xPv08qv/368HDhr+CuB1HhAA+
VA46vhatMlWLE8UN2NblLHBJynxjn7FWCfQ853RD70RG1JdSAQVhB/d5zz9iihfA2ig22ZrvEi37
AhCVkGmQu1pQPe/DmabGy6CZeb8vCtrnfV4xs+GkXSsQkbdDBMZdoPtdfoeGH6kKnnCb/4u4nFO3
qyi4EXPYD8V0ZmF9T9TZN+tqrzug8vDPLKQm8r0JABXDF0ZK8I3/GDyfyO7O2DGaQxEog14FNO7q
qTAiw8w9xtC5sP3eT++EAkQbrGoDx6WhhzsRHlHAIjo49JaffATRbcg5Qz1ekQPYrTbmZWAQ4xBA
B2jGM9rku4qtG6TQ8QTEKUA5rw6lRwhJgEOd84BZk3ClrFck/6NakxwQO5LWml6r9gyFojqnQeWR
wlIeF3eOQ0Zu2hAGVYcNVGwD6u7aZ50neavuHm8au0G942z46bz2Qkm4dd8LWGIxIC60QVgoG2FL
tXOw3zSse3a0PIqCGwCwhg+76mE+gXU64eVqitL9ylXCrobmKHGwh+WmRvT52BesYD+TJ+0CsmDw
fBkXtkw7FQ6f5/cOlfI1TAXtngBvDMqdw3YO/OjtC62PEkpFycCNGxWEMn45454zL/abbW1KD06G
CUduoY34pwIZVP9mn5TT7Sh0suoQLw8Ya9jPXwdwSHgTZEqK+1wc0Mw9jCwemHbnmOL2YqGzrEaG
QQmR7QF4YZwYk/BRVhehqTDyrE64xAdmxOECz1y4bcueuYKFhUzDN3Vu7QMQM3PobC00FO5hOUAh
d7+HXS64a+7B8Fe0YTjkyHpxoVIgT6tN4zsZ/doF2vugKnTBs7Qsoe4vrB89MV8uwEYt4a01rOzi
wrbomHUoaXzGwmQwI6r4aJLMVo6717GK6V+FyYewMvEmn/8tp637nJoBuFFKqR4RP4K4Rk5GHzVC
15Ei1YZTEC77L7JAh+5DvQdG8gsvOAE6wWBotX/zV3bomR4t4OmWmCcFiIa20QeovUcrTiZrOfzV
3iqWsyoYbC6R4oLDeOn01F4/CAYCw91xfVb7nPuNEVaZXFZdPXIZE+ERN79+Q30/Bz80rDcFvTfT
HGSUXoxl/ISMjGOHNmAtgez4SQy7poqhKEg9LYgrqaXfYe9mriquSnWxc6+0VnEcaiVKKUdxPEeo
gYR6dvqZzAoXrBKL3FohEn3VIcYErXpcHvfzRkzwvQFsgObiC/H4dJYbCscjhG1jfOWG8A9e1qnY
7fi2dddxrtckYBrzdmq9imzaiXM++s9fa4FxABMHSChwCwJnqoi0WF5UMg4fd6aOJnSuToWrk71g
R9RoWrKTOxRMR/9VMAvat/3q8aw2FUYdBBu+kzE4ApBumn6urzhA4+dm2++2JVs69AleQJAIkJj/
IYcon1HsRlr0nj++J38cR3eMKdTJIirizIBLUK3UZVx04PXTb7/QtG23NCIK1h6UXIGuXvpz1zCJ
o+P8mIq7B+3C7Hg9ZjWGQxC6NQP80E7MAsDrFlABoMLIm8PkXLjLqKRSEjHz+B7J0LKgppZ3qGy4
uwcgmYjHFusrYfu3SYztwU+VZAyDYK9eBghyiZIUwz2J1rwbbDrsNReGAVm84egdHj28fD2uUipW
wmnngjSCTfdb2E8ihAC1cxPw624PQEXEhoAYaixrnbXo9YOFDDIQDwhH0f43StMNXOQjfU2P+6ON
XMXER2FVOnDyb7PtVdt1kksLJtQBV2G0y3BaLpOj05rojS78Wi1Bno7eBWg1tzYgettfW99tvfR7
J1gfMiXNJwEYhFMu5JBgwQjv7pu1pUheLr1X/OEMO1jhYd3/jFv7EfuXDOZyu4DWt6bPthA04ms7
4KbsZBY2H5mp6GR86Ya0wB91c+LZ6CBa8ZW5v7kwIrGVLU1w1acoHGHdVONgktCQkpgKduiiSEba
xdBWjX2cPrXOAq5AhTLSFVIppZnxk8/do6/gYrmFETXimOIWUQALPz4pThUFxiG4+0d23/Z3Bi06
soWS/CDSvvR2oLE1hTpGfHGHWM8rifEqWJ53p4r7RdzWnsFStNZNI6XXi8O8hTF9l9M73eMNaF7k
zjlIKME8E1UsiHgtu1jlmM7+2jqvGa2WUxTIFRS9S7pgmKBi3kWS/4UJ1TttAk2yoCLVwl3leMav
lWDVfN9FP6xHRkCVlVmNy1278QknDKNbyAk4ohflurh+qf1jaUlhvmSCIDb2bcxb3UNM7HX5R5Im
QudFVmVUk9wNVaOIEQYo1Mi2MxRic5nLTdSgUxJWRZ6WlgvinRhdFNOQC393i4lgLvMJpz1GqO3I
vtBazwCkcXfGGnuhvUkhIYbAtUg1gOt+o3l41KWWOeBr1d7gCqjGtVBNj8oGG/vABFB4/Rk3lYW2
RxymNpBM5lnokBs9mO/zGYCEKLOoMmcaRzr8YiTQl4sKR674GuLr/P0PXmFBLVBAz+04xf90GPGa
yDWDq9jQZH+12YfOIE3k+3bWj7F/D6vWHkj/FRAH5DIiUcK9hbhy8n4J6dAFO3/42p6053uEp3S1
a4qPV+lj35Uh7WrmB699FcHPiTCeD6xDQYqPtA3BHzpAd5BINVPV3KkGhrHgSiysplh9ZQqVwJ71
wk0Rsu9GBqg/wcvJbFNlqdSyLdpuTNht2yrR/AU9GRJu2gp/z2yxVZQqH5jjM1tF0P5aErqpON+i
BDTpKZqdaoXFOwEfeEc8wHyL39dKYOe/sR9LzuTQbeIbyJXCjOWueFhMRVV/P63WHoCisSmcpFmo
ZsVLaLZFubpSSyxtsmO+xbyRsQRDCl9OJgRWzRYvAJsGzNcm9qsWQWdoSZzI/cNAGI3OErEQgtkt
hJFG1y+9hpFGAqZovWKSWMLRetTm/qx/A1YOyPw0zQWH4cTiMnww8fgJpu4Lu9uS77vsMghlSCue
3vQRH5X73QEs1hvuHlLuI90CUhtK9wNxuRXYj2ETdaRJfq9rbJoK/WCmSntsMeswG/zAPvc36kXN
ytoF8EHvcYIDc2invgj/RKTcWj3D0U3gcNDo6fb19PrtmQYs2LOulZ5t69kGeIU+NMP69Itw4nZk
GLsPF9o/LVYXLNk6M1fQyYhGwaCjo4soDTYIb5iQ6mtwH9ZyKi50hhbsJlvLQcnWjpBqNIswJUwv
xRqv/d+MpC27Pm7biV/3UALpFK6ZoHwedzTIBOtCr/xqcnYNLwysPIIuhELUK9CdxVyETFubCGNK
W0hqAkVATCzqk5YlSo3oxtNSZ1U2zy/0PHEfch7bEXsoWQMzMH0yiXL057aFbAhY84OPQb/WVRBe
rY3I8ZzWN4Bt6xicaP2nfHkoEd7D5kJVa1eVANNiL4SP8b3SwtWBC8vqwfnW1FF5lfwX8TNw2kKY
4+DzplSbRezgC8ljfAv3S5HYHB39rTa8J2t/kCNFBr7++1UH3wT61IZgeLip9JtJtApw4vXmqpMI
ViCAl4nVjj80sAZ9pBxocCY/fZbKlEuXUrGIhAl89/pozTvKe6TaZ6tpxvjtLQ2xICCrJVMQzUBV
UVaKYXcy6tjnua1rF5E9ecmcRLrHnrLS6ujcIyE81GG7Uwh7/ODaGpttzb+y0rRmz0Ajhg2WzWiW
5F2Y55w9nQCIfNFyk9/7TPxQHS8y+fEZvejWNMY4k0anM8mQ5kMFwOXeWgBlVBn6H87GoRnoZgom
TNGSX9ARVm91qDb7/88q5j0l7XUxRZn3TQ1ccUzzYWXwD5jNVNcordjiiGVz0JHwZyjEcAaJE4gS
dAjN0Ph7AHY2Y3tpJj6tA9112L7a2gAMzhdIOsnrJZhvtirn7n+35ICok+gkQS/faxBHZSr6+oJ0
z4Kpq6qSCsPFkZIWH16AA08d+AxA6KqEe7PoIQ4GAN0qBWS5EyhOFyCG9rgywhJzns0urlh+CsfU
1Ng3OxBcd1CJQVa+dFjdSAxLGzqZ/adXorjkhjnBfnk2xT7GnvGmYCYWHGbym/S228vkrdh0xWC3
/xKP+dmcbJys+sY6akgjtvmUzdsdEGXsPpllIeLfs3dw0DsJoyaEIfSUAdWIdxS5ZF2a44tlu0Ap
zCq+j1JEDC8aPdLmeNxPwgU6YcUAKGZRCWi26WX2JFaLHnoblq2FThuGmAwffvEgyrskkpG3WnlF
mqOBEJ3cet1zxu/4HUSUaHAdLIXiMlsrLTSDfrLuwD/bjLT9h9zIw84NI3l6BBW6vZ19XtKyW3ea
02mZ1HIL4/dOo8PfKdXZ/KPaVkqWWn13gvZVS/hZUl0PXQN4RETSbS1f0pAmurtdUsxUii+03/n4
wc10GOk2RdZatLgHIPg0n7ZvQ6j2sCSwu2mE3Rusv8urDfmvyLp6Q3LFHoBvwXp3hjmqhagufNHl
hPPynBvyWAjLfRzs3ReIilG/+9KdgB/OnfHWoQlU2/fvWJq0noWL0KauCt85HGjRWEBBeWqEb05N
c8D6twXcPZ79otjMKwaV/kZ6hz8aO3YDBKJn8NAsG1ZBKc7r94N5OA+xVCzyS2E5mMoO2xBC49zQ
V1UyjWJXOjxE5k3CBFopJXmKGQHuPdDCtHk0zgm+a11l0IkjpeSbTbI9V8kAjcxw3P+JAiAR1rvN
CT5PRFK0iHrou1eKfzXrWLMblrP2IhQ6l6iO1CIhHkJKnroOd1PxsnGZ8rcwZWGMm9Wy2qzsbhR5
8ZFNB5jfbkwaRPHU0xTa4Qht3qOLTmYo9iiv4rWL5yRt6ZUsmhnpL+c5bQGXe29NWkDRS//qZpu7
XCtv8TTMewh37D4MNp9vdMMq7mBTjVbXOI2ifSe2FmIRGPaLl7o5lIn8Kx8qI812vUgFUm5CXftN
V9ROZVeud+Qw7z/OsrklLTdW11BZks7V/PKLEpUQsvohniw5O3vhnVyrcWYdra1i0p5KQWgBSAzA
4Pb3lZfVusgxzEhEdtXEoBiGHiCsjIDOp+NHGwHP7IUMmqhC5X/u+Av504n67I4KwZJlKns2ylZH
FORSljMpQqACTwczg1opGg7Jd6fGGuUM/9VSW2T/48sFXcx6Tt94fDPtSVR7XMfq9BkRbJiGczyM
pUVHcnWYhFfLO2CYOQ+oWqw7XElwamHkTv4bkZ/biG2RzLId3eQi8unFfLj9KSzvv2vRHbR7MG/s
OygK3YCRxKI+BOUviJo7Z3w1Kc80iXU/47RlAPuYTJojQNyhwIxwqZ3vX3RK5IsaL6DMVFrRKQ0z
gqnIwnp7Sqrk3aP6wtUuwxqU0bBaZYWx9xC2vLVQirXbtxG2vZ+a0mbDatMW5MvdIVAtjpd34WIf
G33hIQzrzdRj+s9jD48eEPPdeJAWdXqILAKVoGH5Wpyzl/xz7lp0DtneFA/RXfG/iMXNpoTZsnBY
nXz0G/krcZGfneol8GUq5W97aygKO/FLuZNFeql/MJ1eJmyWw3xQd+kGYeBuU1q9mDu+nXSq6gZN
vAPDnJ6BAY/CjL0qRQReBco/GNfMbhxBCqCoRQkU6gXdYGKxrrZe5F6oRLvXYt8JYo5GlrgtM74p
xh9vT1IMYOR1sbxe04734cWEUS+Hoj9yXiWki3qkmRttjnHPpGHp72MPvZSeRim6l8awyfXb5V1N
0QFU7rpoqKPE9TK+R+Lfk8DysKAWD+JEXP6f11GJnZpQjI9YQQWWFF1LBIDV2vl8zvdWF/27K4Bs
LQVXFAw7zdAadGToJ7+KSp5yPk2r+HoTF4OuOpOJIdIWU0996IVBttQJJ21uLircgBwRxof1Fd99
4fDspTIe6cVaFGAaIsc0RTMCFBNGamL0Sz2ZwsienbRRwjWm1/0RRgVbC9pPuFvxEUqNZl7DK0Y7
AqNFuLmF8c/om9gbzGDc9SX/1uYPuQL3tPcNxiV1TTOSvr8d9W65bODFk8E0CZovDGWV8vohWmTG
ho/bWWiVOVKAJMPPkhyXw/68fIapX5uwET513W3cDD15l/4tVeNLuZlzK0jaOBgPceXykcWbyL2f
Xu0xyESl6N/X/kLSsobyjxhaQq6cuhluHI7R71NwRtopqSyHzJlO1/GOI2Emhk1RiD+HP5nGY2n6
f4oJLg5f9CBb6pS0EAklqPmDwrEHUXShURLHo6LXVn03aTgBCufMKGDvs1oxbyXvVS+uFABoGohW
SALJn+f44X8z6gQGAIoLtSFVf8HxdwIf+Fmblvnd9FpcA2CtebIQQy51ZLpIlzbCIjeIS5pDd2O0
JPMa3zhuRewHcuCKRoCh6dn7/gZ86G/jrE/w3tpaXVGZJQPc0W+NTg/5vqoksAOQCUQEcEyeVu1r
xwzjUPwuRzWgfchLxkVmcZikOJZHDRparoyjfvrfTGKQfOtNNn+BexA9FA1zN1rNRoBhp9Le4orG
efub9tl10n7UcZ1txsc9jSphQ9hftjXp2X0uP5hLo9zIbYq42sdm01m2BOevI5tTqhvaobtaKnuo
gCb9wfVp2NGhb7NJjTsMIzyxofgQnVNqeG92H0+I9ofGdTcPDg6EKIgkbLiAfH5fQbZYq+3MdzZK
XoSrW1BWQXInVmZdOfhLKZEgOJKspYGj4M8FIjhBkQaj7zdyx9bCObanlMp7G0JzMCzXwgLMN2Lt
uRkXOU6VDzd2WeyO9zdWhgWHTrj0j+S6HAabP5Wbwg7X1ONrnkcAi/okvUHjvq4xgJQ5atg6EXRE
TbBIDTirXzGuxqY+PaH7clD6eXXZnZEYxVOYIq6qGnP8aTl+6279SVPoADGJBujSkAQI+1wXLvMl
Be3MriT6cwkjlz1ByDTIDEZhGiiJRPGIwBQmV59Q5ZZr1VzQIDtmSPLPCbpzyt+a1v3OOVGOyUXp
97dk5QH/pHXxVYqULE2YdoRLntuTqz3BA24vKe+i2tT6UQSbV9pNuct7ho8qD+whON0cfYKYNSPj
2zHJZaFolAIuhKA3ZjVQCDQw4N6Ehe7Vcpf3z52MRu9Ln8EDIApmId3fIw9O7XCiKkEP3z8PJRpD
yG1JwOD4Mlp1tRQ+bhQxLcap5ih3vUPYd0suQ8HThPhzOCzDAsa7fTyiO/9A2EF5E1YYjKZ0BlqZ
T21FYjE+9ZqjHrm5pQwbD87UC+fb19dhiWpAtKDVBvzVR3drtzWOXDrkDHbv8MPq7W1enkhC9kKi
zY5d1g4y+jubvGxVgcvyShVzng65qT6sP77scEekTtFw8bTS2ue61jZrbtD5JXgAepsXjyxeFgme
97slRPRdCYOjmmFGhmZ8AVMvGF6pX/Xrrxsmu6riuP7jwMt40xyPbg+VRVTJQkrSLdtxN54pRSaC
NFavjXPm7tIHVXxaSLJX/43nnJ5nkDngZFttAR2Plprn23AJH3YCqp55PmJ/zLjJ8kX4D3f1hJ9s
NXzTBSd2DeHpWX7p+vywuRDqlnr8SkjOwz+PlzH5gfLezh7XTng8ZJt0z7D7inwLybwFfAZox6Tg
P7tFBObMJ4WrhPi+MeVUjaVeQsL+ONBwADuLWSe6jvtNYj0rN8B8vpEvAOUF+tYzV57j+WGVWI2c
NVZYzQKa+eiWq+IhBC5qge/CaePg6Xw+VKK4tQWTkwwb9RFqVvd1fMyTlHe6rNCmccN8HOgxf1AB
R9ukcCf1chJBqzePostW5OgcI5j/zUzxTpuikj6JbF9MnTg06TQCEqttD8L/tLwvbsOK5/0XO9ea
Vn9dMI/DJY54jpM7AP+fPhLc5XD8YOttugxmQ9gPppeEYG6IuMvNKNJ7QiKzpHGmNMpyIdRe/4UJ
f5cbcP3nzbqQI7G+Xga2yOidnoYCWkzqNfjtWSGUJRTzraDpFuNUO0v3eJ/3dwR2Rd7CNlKoswJq
31KMHyQhRk2YuWchvI20NwlGaPdGtCuZDZgND8fNODVtTl7rXnqiydJgNeI20ULa8x5yx9ym1D27
OVYC2A+FEwduHcL0jtjD6d1Haf5RoRE2SNoXbwx3dyKAGr8xZdxO6GF5UcTMGXlhR2JPdOEO00NK
VFqj35xOg8idIGLXAyzVyqx771sJya69zFLoGzBiV0U25kpDo//WETwFTG5KR18jQH2OT34p1RY0
CmatubFkvZpGhABlfX05vMlpVAZNwmMKGuXNxtyGeeQr/KRo2zlAfW5It3KNY6hB2A55VhktR0VZ
TtPlz/wTnIEjY28cR4fw4PUJ02lWJcsJGuToXlI2fst73fBrDQg8bLOy0yqgZg4vCdPEu89UEByl
AfZGl8GaWOEJT1TDrGwBqU/na8TVZ0xvTbZhukd/OwDDesDFC9XKoqZeo6eE7TLlf77cB3iHwKxv
RM9qWAU6e2FRCruPNNKO4GST27Z+ngv/SShNkyzbFU5xDv8+IXAYO/f5jXWnNxeoZEPvSxVyd6Ol
aR12M+XJUCv+b0eZlbZwN7FVfTDGzGnVMf8oCchmFWQO84tlk5mm0En+6/FSI6FjB1O5aG0j3fIb
V37jc9mjDpATy5DU0RCxKWfsUjcZOUpW/uh77IJUa/GuLK4BPTe6narMGCWC1bXqRe2ooPWit4Do
oPJPvY+XwpXOsbHiPCkrF0vKKESVA2cQJ4mJOiD5ASadFnQFEYiv7t3g/5oft77s0rHOWbiLxADI
qWjKWHTiajfCwTyzeEHIKk24pxUIcSTiwFshmzSG7dKd6OMlOQH8wVqVdf1C79wnf91f8X+xxNDC
SH6UMZr8F5zrtKTe+221Npzm/QyZximaKzSATSVdO3E8t2X8ioIk89z3q8JGWjAYNaOlvcgoRx0u
9g5mj4LEGvXH3PLIRvClM/ZIq7DT3+qxIrrA2du2bwG4Kz1MkjtkcXggwnhEfE2UgxxmSsfa++rs
BM18agIj0N9U0OL6NQuq6VgVgyOsX6iecZMq6XGlAH6A9KxuCAuGiund6lajhx00osYoQ4PMKsPi
S4cNEdtPYqeySGxaffIYfe41y25DBxtZyTFEVRNM7VyiuqWDain2rIuJr8uue4yccnUtepwTtqto
pSRGLp0t7ayBul4iypJcDdq/tZsAH4nMKFHUbTeQXWdI5sr0GE6RMWg5QP6JDuHomtuXffJlieXV
RHCrsb0QERig20FXXT4jYmBx8v4ihA8SE2kFscybLeKE05qdlj4Q0ZIE0kelFaBPoA96WZgSTfgB
oM22maosHKnhUcMh5Abxc7+3pIjlCgbAzsXFpurZWC7AL6x8Uf4JFovvCmI/dt2uE39BqhCsIhZ7
s5mLjwby9WTtp3OV1VqD3sGDgoZR6Mxbr7Ey1yEdxQ5XBvfqC/qLkuiRTlzQY9L+bggIyfDJjujA
/Sr+dkxa2qTj8Oy+4CPCSvDgO9/4D37YJtAVNCqdB/U1NXyDfbdAQQQVekmSIuYei4/eOn59hwA5
oZynrH3zC9+NHYHxucau2vq/TBwpYCXjd9Fc1lDIpRyhERPeRdsY7vM9TVcxKylT6fb0qN+fW8Z7
2k/o7cE/+clsbdxcbfOtrIkqx9Z340AjNVwC34TQOwiT2mcP+0bYF5Ll5S9umfhU8QWhqvyTilkw
FbXCK9/ih83OuYd/saPkz4SuxEemZZCl+mSjEzbqzqHEouXh4Jz99n5hNeIfeTA5qcrbVAwICMyl
WPBcccG/5OHw21Xo/1Wr5S/B7UrevNBP+/ZtRlMHf6laC+j3h8r7uWGJlaXDRjG5/dY5TNIMHPy7
ojJjHnMb3eHYg67A1jbk1iikmWQuKnhbnTYDDNLx6XX0NJOmnZfGxq+PJQ/Cw1d85WfOsnFuAw96
hsJmHBhPmpjYFk9wKfd6QQEeoB8mAOJDvlwLD6pzhKXVKBLtTdZb7bXc4Z/U2XnpiidMhVVx9/p0
yRi4WZ56FXZ1O9znTM25JyKW6KtKs4Mdv9pnU6wj/BcdVSf3bPmsnwbbaF7mXIVMdadjztgXVpqM
/fnHQlSl0wGQZ15lfxi1sso2JEE89NktSEhhxGs8/nrkwo3lKgbvirDn8Y3Uv04p5Phrbfi/0pXX
Z24F0xZlgUaSkcd/awHURqYG+yK9nDYfiWbhplRF0FUku93xQEVsYz3hVrOsIg/MeVSlFLHus2md
SuQ3GYli0sKlcJcJ9AJFPbXVQNhkb+DIVmBraQr+3kGLQek5EOtKr4w1ZvriaovF/JJ+ubxSOIZ9
/o5DC5JmcoiqmzLk8KREagjdvS7XnrIkv3mGtESWMcn9YC5ln+H0qU+V5ynTnfCCDkSt4PsI4pp2
jb8Xbpv4I7XjwxvM5B/pHVWIjKrMEF57SCHYI0VeA5U/5iEF0hp4aFOBWOtapLmhaOVu7bagyC0V
fVhJYUqzsTmTP7CG4LEjnRSKWOTY8/tg1J1y9dNiklyH0glkegEk3MuA1hcwMJl8L7za3saVipPF
zBJgnuoCYLX7kBDh9LZ3BDr+3ZGpuibqtxgKpcw+3JtjfZ/1WauKIAtcfURJ0Rkq0jCyy4qpuPsS
1TVL3JcU+Ik7ri2ZP1y3LQnBd32FgShlXjX947ySFYUG6+MECCcJ5cpKLTb3/dmWdMAF9GBKoK1s
EXRWo54/ExYHD+8yXAyOGc9WPcaAVNKZCC4PwS2uLqcj6Y9I5rUgJcn5dVKo+oA1V0yjSEZeqda1
J01XZ79ejWkkb0afPWxnbWqC0WIUeAtKzWU5BTFVH8S5G85IobVkTrnTO8EFy9dT/PfEs3ZU/amg
OWXNx1wqoEekWYlwqyVt7qxZGMjffi4OezY8ylbcXrw4Y3ZQS4Xc36eDKemiREM8f92aFCLQNUGQ
H/LHEYugfzkyy6nrMWCb5+plF9oB6PTTmPVDLGlDcEXp5qDOnYJheVJhsjEMbZ5YooxkcbzcmqY0
mqvrKQL7A/V0b4mzpKiveWs/fv1AYedxHTbXaytWuVdNq8BusTZHmT/ZPlGsneos6XUBr0HV3GiW
rO3jSG0FPX7lOolxMBL/FclcaEyVDv+ntaOnp9t8gLxz13e3b08k1lHJHK+sGXbVwEl8cs1M9U+r
thyX9/GPtWFV1xzVw776aCYN93QpI7GF525lyp6zqWJ+FYNtPVIbq1EVwdV+qguh5qylxu3DUkp6
M+Rp9x1ZJ+73sqXqm1L+VlRYxS1wwIx4Za9IQkqmllS2N/H+Vfh167/RNAzQEl63mj4z5UkHWslL
jDJljbO0CVRVYUaKUARlTrQiERymJrHYJ6VJ9ikr8+D26aVMflEVS7HC9DK2I+RDzqK3ccP4mGdT
CoLClHlj1EQuElYsmB1cApe/VkHyw+zyRGwG67q+TFFMkpxB98ATmSmDtSeVbNbrrMyvpBrPaSma
/qFiWSPLHrQX8NHco8PCSLtTwOmtz+rr19u5kSGEpT4LaQQkIRilZLgk1mV5hVUF6AJYTbg8ILcr
ptSo9WpZ2fHQnU+ygdkOkjmIv1HGhYmORcZjW+iT8GiEaF1ELIEv0XSwadeTJvTw9LeRkKx6026X
F3K9Cph8CDPr/v/xjicsFHcZ48bxNzEi3cdu+w3Ow/7tpwlSs1w0kNbx8xivJSaICyyNoY2/obwj
PVv6qgO4cw1bWkyey0DzuxVoK8p7DDgsswrXbJ8bX1mkklsEOOd/PFu0LetcgRS/eQLzc6eZygyf
hJ1QZkIHhj4LouhRSnOTWDwdFCu3Qh0/8+1h2QGOb5JjcFfEVQhrrXeKPERCiF8SdhvD6HJMtgCl
jDjEEzE0rqinl5FSYRX4f03xffU3CwNB3OIopYYMNJffXU2QeitPGA1H1qqDdavWnj/MPVyPBQJK
iawtCKvIq8ckVlTR3088uWQHMMj8NWXJHyscbdEueXeFFBfwXU0tmSD3C1kGLOljsR95SK5TKQU6
dwXB73fiDUDE0i3Vg89KVHdRax8KIvcbFcVzwe4U7dCixctEITzjOFmeKLyay5R2plJUsuNAzbCD
rHKxNDMYYdUFdO6vfh2OUUGi27jhXQgMgQGxezo2oovZOt5yTl57lBNeO7hkjpCDmNMANkIlqXWB
9+Flb9NjxgFK1K62tXm4z1Brsd2MQJMc3iACvSejBg701ddkRDA84rMSlmnl7wKb2jCW0ZtE9xh6
w0T6GxZbJFHN+v/ttTz5nbDP3vthsYk3+xTACdIU+tSNeyVoH8IRSf+WBGkhReLzWWdvi6RKAm0N
h3ff88tLy/VVfKUVV1j1/eNudWglxNTLO3YHa3XiwlNdp5afmK+5dSUACtaqyqIbZttLaO3wiuy3
Q+qUxEugTZzy4L4+divw95ybWzKxV3Z/ulNsE6cebQRJz/+2MT5E8idHyAt9/iqZX6wDP81ZKWx/
fW5m+xQZLMQf0tcjOGG05J8s46p3356SMqwbXSg6cfrwtlNxRptEQ5Dr67u1PiuH6rcNBZxwU4Z+
yTfYv7isJ/TsZO5I6iHBUIcEQKKXgq0cHSjlxP/BtKIwy2w5VtslBSpJD2BFybkFytWudgYSa5ri
e/MjRe2f0CgIDkHVQP7Yr8Ugi6GNEojRZwgBOo9eqK3ntcI/RlTsKfKfO/LqX+g1Hp4dIrJjwqxv
ed5mFWTbL6CQV0FF54xCMB6eYhPlAmHxYnNRMyFBATgPY9kca+eiKYtFpk1U9HrSpVXh57ZFKPeX
WckEF3/pPUBSNPTcwgX1bzalyXc4GyYTMpsvi6/qwbzyCcUidWTtOZv+/ybExx8yr1hsrKkLyqv1
7iJUhrk3WVGGYc7hxCSqOl9WovczdlllW7SAcAXoeskO42TCA0hw9nqjFSA4dK26ZXrbuuGp23Pr
wIbJF+ew14LbwLjYTL2j8dTueV4SxmhqlzMDuYDNGDqnx2M1i3Of+LCvSaYxX0a3D3m4+riYCyS+
FBShaOIfz+kw3JHnBsrcrv2MIxsl0rV5pS3CM8L72WNCrBRzhbmEI5w1VmQYEsyWti/93VoXlDo9
FBlZcUZhxrCWs1inx2jVUPviY+itFiocCTjSKjFBzGdMELlEIlbMC6h5zaMcD/pL6R+U4PIkIuNZ
Rd4Xfh8dsWVYNwPvdDGq2nQCrfOEG13em1D8/nO12RVr5EbYW7bpGKokMn463LIHh78/+0iL+dX2
AbYH6ZZ3RK9HP2BwdEFAlsskM1qgSUx0PX1iOAxRe0fzO+s4C1vUtTeE56b5+Y0LdX0z+yR0IwPE
PkQwstFprbdpX04yoVIDeljYKtjV5D/T3IbYs4NgvsD3shwAq8mm4M/hRr4RkSmTfTWDvjg3avz7
bJ5Vj6vtbn92ojC4nHF1MnDvVmCMLuy8i6gM7jWIv8PQQ56PrbzNMcPn1TroNMOlxj10ihOFL+ge
kSfSkJ9JqG2rwTWLXDD83h27aakS9HXjE4zs1r/T+gDca74rP0yFMGtM/+F7vox6D2An/N76zh81
EW6iixmcwqaVMu/TeaQURACD76wanSQyqDlphz3+JdqD3moe0RDhVZycpv7cgdV4VnFKiZBRwekX
dQP8qGQI/+qJndN+0amBGrfTGDah0gbufiUoDHdDpXgT4KuG0MSD/Mx1WWJgQ8rje83GIzn0jx+G
nbjFstUXObd99r2MqWPH9F3CVCAMWeQzCQtbfPdqyXWSoeg6KKm3bIZ0kSc4TVILRFjnke7fJ5Oq
JtXowrOjNW2yuXrD2KKoI8njW2KJJth5nBO9CAjqHhHrEDX5nWFaVplCYge8JNGx7c69DcDnrMHx
xSzlfNWa5vaH44TvIkuU+4nYa0nhBd0h5+LpLatdgBOqHMGzgixHu0DCDfYaIXdYBKEFGdo7urGY
G96B5In1hoZ9CE7vY+31Cj0YJ3k1gDLAkRLB01TK5x00Hv9jMQf7abXOlaWwp3bvUEN14zW3CYNk
gjxhLaj9YC4oDi+NbvRcXb5RpToB1FqKxGOYo8ZfncJE+Kmn8cNurC3i6II9JgenIp+3zoHXgXHY
vKLTiUeh/IsVb8HDnhHFKyuYQ8g3u8CS6LshXctSdG7hNSjNsd2xRpkzGEx0AtFgqXbCzPl1QI8E
4QtQtzuBHf1YGPCKFlZjqRP/OlPNo1Q6jWWOrAtL17srCkL6amiRkvrNE1+DZ8PtrAShEUr8muA5
rhsRp8VL5ARI4/gDZwX0koELc1U8Lx7dzrHOwb9z1XDGi9k7j+H2H5SI+r4ce4xEE9o+vZKy5vjs
M0bNRDbCmUdZMNQJLXYVpEKt2OmQwdT1mDsBo7oohwwGxU674ucm97BDvD5OeX03nz3YI1c1E/lE
IcwUmLgmfCPmMdkg72XWKRT5HnvZqiWRaTlnjWVTmCcxLHqZgcrl8I354F9ld9i/2KsYRMqnX2Ov
JxsITWmmPlj/uP0tU40WLAU9hY8BMFiqiqoire3jHpGzam3Ncx4kXZ4F3IeK+lymhaj50hJt1nlf
aMKXrhXHG3G2SV/2Pqr/gs6JdM8REW65WclEazkKB+DAZA2Bi750z6WsjKh47uQXFycicxFPPBAU
nD24O5jkZHZQsLXcG61qgJ8xdQGM33YSqPhHbAHXdLIdMZFAu8gHi6oZPIQ+5FIu40FG4cvP6cpS
2Paohf6LSTD66E44fy8JB7HIcGSN+jTtknkwC0QPuD40HYMHMWj9pLRe62uDWhOAAsDvrZI5YWBp
+Ajg5QkxdJdCF4qZWqT3sEjl/bAf1dCC2F6wLwxlbU/mGTpIp1XB5G9Gkkz4pCH2LAKi7/Qd8HGb
raQ5WqedXrmXZzAyHCWfaE565RQ1QvuyBn8emyHnZdYgr6MM38NdOB1iKLwa44nkK4GUQ4iFVukH
eiTvGehl9H/uSfHgVUG567UjM0uAZdIusqbykhIUNXu0GMpyaDjK0V8Z7p/W3kHT1wislmnYSQh5
SIG1pgYXRIfsdLnl/Qi0jDwMHzBXhaU9PdckWEC4XFJEsMOZspaLbj4k0EqP+mwK8Z+iGzSorj6I
J+EwqbqHUcWitAGgrIjQ8W5/a+vvlDxvkafsiIOiNslCI6+GqUt5Lr1FDl0feXsCQS3w0XmqYNNB
ky3QK7gfnRmEole6eAu8+Fgmvt8+4R8x7CtVw/iEmyJNxiQZm28TLOrLe6/RPfruxp6J2CDJejLf
YBDwAWqxIv9rrH99NqOJgbjRACyJ8hC+VVFbNL86Ixaqegqd9lyUlxh23HnvoWv29qhQLqcSz6N4
PCMZ4OOsXF9FwM6Uetyrp1JVo6MEnBXPUnvRkrcl4cb9ZV5BnW1TqwNwK2ubqslVLhJoEIXxzoIi
lRY6O8BuMP+8+9g/HOIRlTZvxuVW9cLsuLyxvnyv87Eg9O6yCQRcJQtRoBxGbXsYBFu7tKmrtxMP
VpJWqV8p/50OctxLR+Ks01Ecf9MlFFja8EvnXwqnOdzJ4mjA/bNuVZ9+2HmiSvMtUkkFs0QXDtlB
j+PJZgajbpNwh20ePVFhgdKgUYR03EZwaqjaWXo8enKEC0HOOkg/68x10jE/2IuCPgGIThyjbMM0
20IEvl8h+dePs2z6oI0h52jGLangLN3XaeUk8NOcV0sktOGA7MSnAfqxK6ZTIP5XU97IUhRO3Ne3
D5ueMfX7TFMmCpAjja9GlaxNE1vzpE7kyGONP+O1hL4KO389AMfnHnimnFirqw6vJSSg8xx4L9hW
If0LMqTSxRmONidwoVfEJ26aAQEexJVtfvkfzWNPe/2DSeGuK47PVH/sc5s5wOHaEnlSihCLm1C1
pND/WrVrvQclHoe8FL2KqwjYuOsIfmHB04MJd8uw/4Gaen7gN8DjWjYksyLGs48vuH5A+BWqZkqO
DQCaHK0mxRX8UPK2eIHrG5o7PfvT9zS/XuyXmkZnGz5bjrwTNj8XkZyn6GvsggNzIpyWzpjE+rdO
aPvt7ZkgVocjjI5x5bpwDsSd892Sc9wZVnbhiuHYc1KblCUKqZEGanCe8KSuLu69N8dl4uZGYk+k
T3weDCW/3U4HdYKv3WnODCQUcAnUkJCLNhMw0B6iGtgbZZOesCGWEd6Vf3YH8GYq64UEyIs4F+hF
Yg+nluwprpHqMHZ8bnxXW68gNk4KPCBj3WCVA7eGCqcSEUSGabp23KV6fjGYNFmZUQqdif4VSL7n
1rP/BVkz/Tu13ru6XKeqOsRePn8/a08rrMKOIHvXFujKyGtokqL1qffIhxB2fNzPsDr3xd2Z37Ls
bl0XWPmF5EWKKPZfLJUwIrfcqfiZTkH29EE8Ops5l/zXA+Uh0CvvCEKB/3GYpBflwKQAzD+kZ3Nz
0VSgYVU8GLzOs2xM04j1vPhibVuMVsqjyp/skUl3ttcOEKcxakVrWdikM8yo3dWrXh28JzxWA5K5
qTl312tNBAIlrIyRw/Ulwr0dj4uFFYHokp0Qvg3tsYDA+vFAmN1AJUyndC4P0QIiX88reyzaGuTv
2JDPUw15Fi59Z6Ybnd1JmVoWOxR4qfx4qpzyIYRgpx6fxr3HkU5H8T+l11NdacbRKJ8yCyWmy1VA
i8eQIObAEaEntHm+944puXC+G370UVFkNZwroquVGTVCaPUnBj71QF7vB3MKiRqr4P6QeIn+8q6Q
8cFeMjwahwfZSB4WSuueq2+sn4zhOH7ZD4F0tF54/mSQf4+JKKJgk7a2lxvx78q3Wq7frgkY6ejD
Gyt6fZhlPkslw5oMi3Sa3BVlKK5w0gfvR+WJdjPFkJX9oaXR8QQPc4IU/PU4zLL27aJg4HsU+27w
KDPZ0CQTdlizsKGxtPzxns/lCrJ2r7iXdScy81+2qcGlAYvTm5fTOBt/unVMvqXazx8bY+c8O1uU
OicoAkG6BMffqzyBHNOdTxOeVp0VujaDtUidoxwpDVfi/3Z3ZMuECg+060UO0iy0NG3P2tT+zBCu
BrryOpW04k7p2KRe/tlN8HMD9YhVQFYFQLaM1YcZ4olirdxJbYVekCd3XymqTBv+vzto+QsI/e7t
vIvsK/b59tp6p0iTyoalek1+q+kQCXTXbQayXpwaNbRVZ5BuXUeddtPDaqFoMvSZjqowX9+RCrOY
K+H2djaI5tK+KjJin92XJtO7sXJhCFV8D9HALZoBD8m3W+m/NjMNW6SiuCsGrFiXqCZBt2O8rjjD
DyjAeQQyRZJ3Uk+0Vzb38yCnzjw9y1at6QEKYHXt33VcxsENoAD3dpC1A5YhFZKpoGSCXgf8dnIC
on2Sm0aUNftNB/DXk/t9asQrJXOqhkbaxilr/S9fbDvfO2Jr3OXyjUpVqVBBQTDPgCIXqyz16Reg
0UvrQNm3Pxr/2LlyzXWZDTZRUi0TxvhhSbSkCtQ3NcH2472iVNzm54F8jZNq7pcVU59Kc5R2yP+z
mj3bsd3Xx0jMWGYeZ/06MiLnN0uykTNdREjVyZO0/doyMBuLrYrtHdhhhy1g5bZspTpqhrY7SdLg
0DQWpa37FTsQfAOEFHuitYQ7YSDduosRS7OhDriwRL7fFje6eKR3LPDSSDkkg4jGxh0FL7slTl15
Qr9MSY4eaNeRZZn5N5PRIoKj7OkPV67pnYJXpZTUOkooJjiSu6toMbTzX/EGV50oxuxtefQ64PNG
HP0TQ2e4LdyVonIiV5tJlkzjAxqGvcMkU2xvCAVhC+I4dUT0fpHI2Ud7GL6nwJy2vIgQSlC5Z/Mp
zNXBdsUSVVuhk7VhNN5dksqOcdAzi9ax//V6noU5q9Q0Ap/1Sn0P2GQuHWNDpsNko0DHXMXBWQ2X
wGvygnQIbczFnVDXXYaRVcNw4pFBZnhQg6yc2fOxJFYI8NdfXC/264eEHXrNlv3x5AFdnjd+D1Yx
jX2rkCc9wmes+IttFU0WfG3xxcSBp8mHSZlJVpnvnPkp0cv44ryqHbAFPJ/9EUXEgukfjhLL/DgU
mC35e5YHEQ1q2PH6XJ9dmmnb+T/G1xMmswDzjURD/oaUHgWuaBv2EtlmdWMhix4RUe/RxSsHCN32
YWvvIjLP99aINpJa8Z1LWPEIac0Z4FAdq95FSINnZZb/+OJFfw55iKUnkysnfwGYfvlyDeAv+7WP
sR0RTZYh3LwGcgY5L8+YIwsdSEOVFh/8Akd3uiygWzW5TiZYTRMgBcbX/DUc0SgltqNdN0VobOir
EardeaZmNYoVy32Jlkj3RQ8ZhJJZxsvY+0GnRjIUwGZmtO0cTpAGfDknDJMmZVLwdN071vj+QpOP
LQyzgPYYLx4Rf+bt3gNQHZ0hqd6bWQY65mjHmKFplDGZ9s579d9xdmAtLo58wWQxid4jllY6T5yG
qZyUPbX+OnGFVf4DYq262V3ISrLxEaq3/4yB+v1c9bxE4j9rfewhOWyJHkRHXDlcPx74K9zn+91F
CFfL4n6ekH29kN9Nncfs4ryahD0l1qT2ughx1Y0JDN18rBYMHuNeZtFW38lM0JcuTVoqHIFHxgh2
bJMx3Qv1k5z2KwLG7xitsXbHrTYmrP5lOWqQbd3ggLujPEd9kW9EqssxcX6YnLW4quH19kgOanh9
jSV8m6+2l0jPRPw1sgP0uxi/cItQzegn34n3QuZOdpdv04PR6HA/+g4W0+wD922dfn01Rt/pHHQR
j9a2JeNNUCwTv8C3xFf9sBTOA9QHq5MlVfo0s788OHhGnT7+5ROCALO+mCIdYIQjo1Wwg2a243XS
r3/SUQq0baOE7h2xipRL1RrvXpy3MdSPnDoolrbSKsdPo/5ZccQf0gUBH4J/rXYnPB5G6JMcaBxc
Br3HHYrjFAaJv5nbSk7adsUAbtU/Y6RWgzg4Ma5XK1Q6BoKUYTHHmXmaPVV6qOg0HZYN6mYlGO5d
BK4CzVHnXoXvAwfoxnKfmfwVTivmjbfvAlAtCb9pfBB/uL4ST27gzXwi9HDH1+TQ5XKlL1/PlnVJ
LN8/2uuccXbDvSLP3iJ27t4WzfObkwiQ6gBHyT00zwEYhM4ULOe+Smi60rz5nMPXFoWNfNjeS2Pb
p5jz5X9UO3/v6gNRFCpTY12UGvomoSmaPrZ4VBfOmvPo6Hnb0Cl0+CQZvPohn0SpNIj53wF/F3gc
VGjnXqrJCfmp5SKjp42/3kBimBqUeEHnSOBCByntMa3NxGtj7HUwByBsVECz/HGSU6V6KWcPhAfo
qmLx5s/Qh+1wTwnLYaFIryXzjQ0I6DsbbP6wCHR7zwZEaaBVpTFrlT/3Xapp8ZgrYak3srV1uXeU
Hwn4uyqSQPDud9QYeelrWMZZSFQ9N/iltYhNCJwB/xDERIYsuMcftWeH+E6PtBjf1KNyjwBq7KBb
Mj8AwH+6ZAAdMO+UO/SSFVBfRsmyiBBYhrQve1eRD7AU6Q3furYJWjd0p8sRmXcK5cpqxDSqby9m
KQ0olP9Tai/jRBr/HsIw7Ulr0fxvhJH+ScNmTIJBaFlQ4IUp6OshCxoyrtlFUN8EcuQnPqXB9QuM
JwxVtgjdbRfOs8ZaO7pYQ+4mz+hQJE/8J/45hXLpxwQYoxMaaBb25IlkoW3Uip7GNd7q0IVuAllq
FdfZ0rwbHCgeI3vrrWUr/HCFQtVBimEgyY0zKHRMZu6ddAved08cddzsyBrnUReSfIoWSXqqTx24
GnKq4wPtUWZfD5/BzQK8423zAYbXIFl72x95m7vs04oIbW5Y6c+//Wz2DzaXnTF7aN+O1Xawdloj
/CSiNjNnGAYu/OKHCcllfQtVW10bSEjvDOk+7tPIdsZaevEkz7Wp1G4tbgIj12tuwGc8nMUQs1K3
fBbfvNqor34J5KgqxcMyKMa7hWSViE8Cc2kHkenJM68Ou0sHSFeNl9Y69T/ubxdRmvbPiW4wxnFi
VxmT8lOyF0/OyECg0cGANOF7HlSMuPNpm9yqRktoA5/ZuWGkBEWzuYzhxfecvYXW8ad7XD4zXWtU
ZOY52DkuSUZeO80tOZdYcRE6Sx3dygF+SGahKPVA0snRIne8OmRAk5KccPPxiPGg9BYjY+1L8Gva
za6DulhzV4xFV/HzCPbuQdslyrXZFuRZ+0Ipvr7VnYiJGp3AQkQ4OsjKWIDckof2wvG9xDG027Vj
fU3Irj649VgeRCfFar4XDh/xSOoXNq1icFnW7u0TW7dYPEURLawb1yMklQB8QjHhS3dswf1QH5gN
EJkcIz5B+XmXfcgFkJoJnsMvPgBrVKP40YYisbn72JY6GB3JYI83Id0TJHu+dHe/xrZ0wNHPPCCt
uW/INZFLCIDZVrAzt8hB6gaRLRV46a59SvyEXHVobHpNNcPlrwtCXW6w0nzzHDP37LQwBzzYhjiB
39wMO1y6SL9wlYurkHNXa/c5+kivf+IXHRZoHGukrSta8iACVOJdwJsWForn37plnZfMHvBr41nv
QBkVTec9G+knC0LMZU3nbLqhsXuZiuKeU9C4F/FfTHVNLq+iSVR+3kJ/7A1m8A7GQ92iDUi6Uolo
wuRMerkX/jHvw2mOhzvXyAjYlyG840z+sfIJ1I+MXUECxbkjktdpURUElUEZOiWvSGV8q2O5l1TZ
94YpUfKee927COpqv5ZCPthIFfJxOGz/9muwFjJv0gW2Uiy98cZ/rzwVZXqKFtnovyaYn1Cc5eqE
1k4zWIXmIcmqIUr8TYozPbI2amw4U1fA7cy6lAG8iCncuGg5bEYmUYJyRidtHDESBmCftZVBZAQ/
eZdceUbMdUTXoVnC17xY0GMGjx9Q7WGR+WbEcYNRBqhq51Md6Bs7eHJxNCtbavCJH5gVXLr/1u4I
3TCttwi2kZcjWN80eTLWHBeiDf9vtqe6utaIwMBssEV4QyjREku10LY9A+6dEu92HUH2bsEfogTQ
MqWCnRdvpkHpN7Mt6xRPed9pldZjF4mUB4BYj4wddeDAzDamlgY6ckNQq4WxLZHebbQqO7sUFo3/
crVXX4jQjqO8DDrVG4zAKZmt4ksYcR8PC/j4Ar5i1prVCeaNP3HwK67l8pO9vEg9EIeszeUdP+uz
h3bh5+J5dLatm7HsAbE2YSFV1HP6UHT+f2mHzmJMgCRTAzmtKMN7ewR32hNWm/fQoXXFGuKOpigF
atq19Lpp3oOOgJoJFnVmFpBQitnp8Lm/e+3SrUKsqCKak+OGbEGbdCXnwx2l79kp/FR1zCUJn+q8
eHObE4nxAPScXJtWuKqQLSM0w2G53AVj+pBsWExajUI9w6s/9FzyBXpc8qElU1CTCx2sET+oSF9N
smSi+9FgZCsNgQnOrN9ahTh18Y8vkxmCqJHqJa+4dGQxY9HNZEgBYvQsrt63o/U0TeVo7QPnixd2
ItmlD17GRZtEI6nAwGa/Z79nEtYdsgpDBKXO4Y9s34BDsuLGqfb3k34QeU4DqoFnAWos2I/e3ljP
VzFe2yFO8oeIBdkT6dIPIm7oVVtlGhsnMW8yfzLD2RMkoTRNf/uVJnpcxSaWUQhgFfSok8ukKyXN
0VX22KL2ziIb4fFMaU9yPZas9MHCbeVDOfmUPXXVrJE0aTxRsF0AiVwmd5gPLfKo2aC+I7AYv5Ll
jnfExT6ZeOdT/mmdJweIfzV77px9L1lqF27yvjZC+E+5mpbi2L0pVhmrBqlpYjioSaj+VwbiaXJ9
SZZ3XvnyTJmOLfQQqDWA7TAH4Z77MH45F3aeBC9E2eK7w3+OE2OMQVn+1+iJ6zcH6uEebLw6kCCo
paFUQsRwL4EqrFEvonHa7PADOCpe2Io7cghUV2hTmLwCMlEFhw6tV0PT8bIeyZ5raSLOv8neKj+9
WrWVBv+asAO7OH5+g3qW2uzQdBN6q2Tf+pLK1UBNQd6GfyTKVzX8Qauvogn/p4BBEBqa+Z3esqT+
DuCLYhyilS26vFK34tV5hsHvCZ/8rEqFMzS4999fgPVBIZe4sR6N9d+B9fJ+fSmcI8mZWW3Y7qHK
kvsYwmSg6h/FmPaW7cnhQSL1mqMQj8nNzl67dtulZ0vD9pZ3N6uzYoW24tBddssgwKzdKDfbq562
ELT4RTr7jup5I7DRb5XIVS66SCWKbhyqS694igi/L45PcPP9p2/nbD9Rdxc12+g2Wtd6fe4y2HP2
mJMB6h84btFEdaN/fEH+aHw+azT19egYyTbvezQa8uhcMgRLypdfE+lxqA1/J6XrhxQig8+ePDh6
/fNwPTfNCgLrhWzkPAUn7TUiNiQ21bTSBo9bJPlfAsAx1o/QCuBJvw9yFulv1maPCmXJOBG6tqfj
XjoQhvcRysIcW2ItLAT75qQscoEBjMsHPuJIP5ZO3H8oSn95KQhLNc70JBVyQJf8oQ9wcARNkn+q
QRaOOLWDJBez+vi1BG31W8FUvh6Ja6qkqvCca/o+e1HI2U0CQLjwXeoDJACWT3ohVLIlbIf6l6lr
2n5LGitXJJM9+8NsWob+CkxbDyUJGWr07yDfQhUrqZkfZqzq9x3aVSF51Vvz5m6PewSIUejp3BO6
HwaX9V7pp46jiLdn8OtO3rixhVklhDZMo9rXNyhYTzRhW8QbpekcaJoTc+jfQBtZsIcsvpofS4gU
zOKdSWz6QrJ8la3JY3ZCJCxjm2GdCVbJONNRrjGirh+AKtx6oE5Xpj+26aNf1p7toWHkUO1Ik9cb
qrxBgPnube9OT0/cQEcCcz/2X8du7uTL1NHt7ViV/YvAphfHz9I71msnKkmsb2eX97LRokv6LUj6
T//tMV6rsG9GamlIYOEq5BuEPnOzizahTPc2ZABav/6Q04zUtwRdax43sKzEMizYvG0lM4vW4QvG
wFnNcWM4MBB0uraTsGqSCXl5kOU/D7zrKxKfbXJZK+YRQ/y6EmSFukJs8ESByYPvRZUAq+GMt8WJ
O+WsrG9Tw0MH2uP4+YgLzcCObGtrDT0wug8HYahEKBxzu7XzDqRdwzntTBfT44yPP+ndjSKoe9g2
w6CJQyW/gkrUjG8TtvKuEsyj+tQoUffWPdSjHBpynJskHslXcm8PDUuWDAqPNJ713IRlBPldRZ0I
IqGInVF29rzhbxRubAdTJ5H+OxILUzadpWac891BQnFASeLy5JVuweNTuD2s8NeOX9C7+GlnJX+I
CMzyYAFbJnhY9+kOuV0/FdshUHC24gjMIocA5Cg1UQ/BuKQFcGJhpYkDvj8Sk0xIU7lWvYa1FYvs
jyt/M9Zyu0HKWfJw5owGyMc7WA/FQDXKf478o0llI9dcwMbToCH+csQAR09iA0KpcX56m57WlQcn
c3qXrv1oy6pKgF4RuG/Iecdo/haeBhYm8AnXrISAC1q4OF6DpUK5hYZhBkbOXey0U0OAb+MEwJXe
fzg+3RssmhEoCli/0kSwTs5Q0ZMI+D0TTsMAwo1ORPuKEO0264uRLd6fFUWgcGZGwFblIT0mn82y
ac5058FbRki6pNjf3GrdtBQpgClT9lm1IptIr6jUZNhE+xFA62zZ/XVUwuW5ZDLq02fUOm6QuX5s
sx/WmZomLexuZjpIEmuJkTCzuRZ/igEL1tmfC5PKZQ771ILY8BoZyIuA8YT+QmX4P7AjdzxwjhOz
CrwNKtzXaZ95A3JrPjeD9BG2hfTigKDxYH5JEvqRpCWYtzI/6LQ0oC+aHBsCrxn4c/28kOfC5mC3
4XcwEWA5x/ZczKXJOB2z3Jfr3qkL1+315bYyEgBt7/SjcF3e0tXqYH42R+oeIj+jkoG1uwkOTdzv
w8DSkD0C5c+Z7ucCkKc5p5YkZMo7m9JKnI0dsN26dlhSJkbrdmBxfDOUGdATmURgcM8ookK4Qb2C
4fXDiMqHlz35zl/vTelNnRcuPv9oTYXa101YUosmO62zHJJM0vCurvx8236nBht3630G8XwAnS0t
P6v8uU/dGJUg1j4jKb0BtL2FT3HrwPCz6RoAgHIOXkLTtI0vL16XmEVJHOdzDH7jXcv6DgzLyqSY
/l/xPlfBKh5ecs2eBdLaR0b+ObF3Ie5T9kryJCEVn/jwGRtlQLMqhzzVb0xtK/Nn8nQ4Gr43XrFg
WMRfPfxt76J9jkkWqOxEUEsH1jaeSeedqwvWsByu6ONGQXI/FvGatDtI19TOjY8oeOVzN3fnfqwg
9SfanqVY24M1H2M9NuGjcBS1jKu50NqgTxeDrJKgnpJ0F4u8yzsqfU1xe2eQSX2bayNXCy9B8Gi4
sPYRWR4dSq0EBEiUd3BD26XpgxoctskXrKtMIf6O1zny9OamWSP+9cBH27hicCvlIv9iTic2X/qE
6caH7qKzggC0YBtT+kfxeVpbrNSmuXOfsweEEcxyfqdltgW0tFLUIX8mITa8pasxdN/oAnC4nhhE
614JLNvGZNfSTwAw1weOJHfAR+FgSM+FLDge9Iy8MPWdKACtRK/19EhKbrsCda68VGrqUegidbVf
Zwl8iprBm5/0OU6RhzG9myl0LsRafmLSA8BEJ3mEDThSsuYfbkHAoen97BkFbxCUjuhUL+7nQwYf
6hDcfz0/euU7w7+UFsTmb3zLKIU/+VAulI+96yehBnBhFytUZ/Kbelw3r9P7T8G/zOnHX4o+Fpgy
RV9w0ACEPYEehBEyM6gmWdUuYJKdGi9/1P7rnhm9Ier278ml4JgAnClJEs/HxMhHmOmQRLzTZ65E
8PAIlF80NbYjjfTYXN/zDQgI+NXeAmVL8tt4+JA3wcYerHSrzBAnDi66UyoWVF+8Pc5GyVvcjAo2
ijJKaddX5mKKcz+aHDi4pZS8Fogmb8MJL6flFt/eLr9Zwr1AW3i6qsg7B2PgWkk03Kh2lzbxRYZS
UPsGHLhxPu6TFmRJoJMLPLxBg7cjrQbPqumEHe5v8c2FuQpH8QvkLIYVvd+BW0L5EFn4ie0yion0
VnSEWz/yyc08vjH3kSiiDZFl9N8Kx+ewSXbpKf0BMTv2GZFmvBC4Npm4ruwvr1URODOwdQWBuMno
XQS8bWaTTdO1+Wa2cU4kIt9jmg8M+2COUf9ripVTa1T0eMiK4gmBgMyUFQdoy1EYBsNHMJiQ2rDo
6z5iezbOfXHVNKCWNB27AJXFXPtlwotn5PB2LvNMo2ALBKNPfMO12M20PwOzNK/5RpmpGfEK3xGU
m6iPeGn5F8Z3Y1eG0TzOv3OiJPddtwREiJVHqqnHt7z3rs9gfutirapTzKQt2o/IQpDD2Vy1kLT9
wXZvhAoMEYFqI8I8LUVMI0+DsQT6Js2defgFGBoS08BS7l/3Sy/t22tNH3U09Oam4Nsr/XKMdGfJ
ecnun4ucf/AOfJPoEsFwPvPIikqF5DzFWsw6h/R8dFQK3Hw5mH/ox/V7bB5tYrFQKjynZUfYWQD6
3kzpkX2dmeBLRDrAZxWuf6xGAxUNFVRCGyRUS7eCRdD3dy5/IJ3EA2Vhz+/SyQ6Ygh/bxUVXxaW7
cf5KR6gWcaHZZAWbeiSaYJRs0stFJNEdxtCyaWCyRjEaXIr8eCIJDta7X2DF55Bcs4Hxt9J0mBqt
t9WRi1qIxVOrubFkc0DtMUCqkGSWH+mrn8LrBnRvSwaN9C8HV/z9pHxwPYDVsb7vjn7G8/2dwwHr
5v4cHfD8HqvpDi1UOVPIzT+xFU7UMY2m2IY8g4x4f9ThzCaSb6EwPhrJGmmCzWCjXE3edDOF4nqZ
oJUQZDByBWqLmyHwGKKaIYF7WSJS+OPONpctOCfugT+v4kO2GGIBrjEHwGh9r3qMdDE8rozhHNOB
J7iwwL+qr8TF1W74CnFMY2g/GIS+QnTfsOkMwOgqW5ulRJvd873sTzoO2nsZ7tg+8mHJCHbljwby
dh9gc880qH8tsjKPgIKP22UdOXO4JIiPwfofFLFhPU5lC4Xjv3dPWfcrQbXEdZ2TrfKClFK5Odde
gwRVmB47zoZyx4FyC2yX64puoejzhXF61D+PytPH3kN32KV2UqQJiRkwfydT5pnWRdRIMwQkQTD7
jNpTu24zsY1JRjgJ6pJ0MyqkB0Bg2gfu9E1WurZaR/5dm2K4yoD+Po9fMJpfR/W3vlTHswoI3MJ3
+LD8HpjLVDbFcKFHXUejzMvMWJ1qIp73QG5DxNDDk+DqcRxwFxyPx/pVwTayFXUErB46EO4uV1MZ
Bd42eFW26VQITvFDjyKqTRZYo+kV0kRxc9QCz1XFvaBGWFh9FdFd91OHFEw+F+7CN0vLBQHyGQAv
YoC0EdpBIy1T5rm5Lh6pK+qlS/TV9BsTTy0V6wBMShgI2CXLRs9ePaj24R5ZivO54hb298tk13s0
3jfy3FgvD7nO+U55tO3cjM2Izjb4psdBxE6JmQTF5CL6fbPSSVZFpUwlIi2u4ASzlo8DjgEQCe1E
eAh3EIeL9bBaAehQ4cDt150V2kETzAXfBNYPAjupvIc/pKCec8EZphiKLXRJ3vZwvP6O9d4sogIg
LPpkf6clYeHLPX9vm6VQLm15te3JgA8V8gcvzKTlDcVrl7BgXenKzLlcF8QmbRU0BXXEMa+SqAQI
Dp8Uyl7VcAK+gPeT5VcmirRmibS+D1e4bX9/rx//xr8Y/iE5SwnBIe3BtDD4XvSHEZdvYq7quNKb
5X5a8Ae06bmTOzyNDxcSLeOEFA5//dr8TFWx9Lxs59mShZ/Wm0s71j9YxnUsGTzj/YSgrNbi7H3f
bjCqzyeruxEzHRB6KFzctjava96VD9OJrfiyTxcOdviGrlQxik6tQxZvefUPWwyNn1MZyya2BRaE
F4ApyDBxG1yQ8LLRwTBhDaU4bvY3GXb5eKi/ZVdiiTZmrH22cJdWaZqw/C+akgAZNN4D/ltPyDiI
UMtPAF9HiM0CMdlxWYONzy75CaHocGkME9kKnLaFohdXUkjjMeGyi153APAdzcAh5foxhfrjr9vy
x68L0QTL+7FRC35MAJhTLuIVTg3qT1Btw3RHhHc+I2/xSzbq//spxnVuZnraNHc3b+iy1+mn2xun
RytsBYdsWOG6sYD9CFhKMA8z+rQa1H2AW2CTn8R2Jq2MzDXP85fthZgf8m0fw7NveVS8jPD+R0vd
4xqDJYWQJ+LSbiyiIq/TMQoC8r8R9Hj/+TIYChbtgRG1J8xfW34AzS9o3gsTvCzAHB9aGRKMvYYU
S5f5EicWBU04ZsO1kAMYm2WXN6Q+fzVWGkMFFXxB3q9igk8Rd9Ksep+CYSNAYcH6RXsiO1xvgYJP
FWwsm+gFdSjTdDvH5Cb8awSWPYVi6ypw6qvOYRQZ91bD4Ir3QGt6w7EtCzU7y/+UBpx2tpxqMR/P
fnKGIzD9LRq/gWmQ9nvo5v7mquZcERAOt2dkVuaG4mtiJLmJWwtUxfpGY7R5PCsoIPBeJDURBpp1
1OXf6KDw6wAfrYW8kUnL4kEBnzO8mn0d6ul3fYtZRkaW9XCGxRMcAf1XF4sBrTgkCumygFGX8pz6
eHd4991iwBI4FsHnydA8KCQp80o3yra6VdwcJ9YdAIN72TH+bXkAkpKIbRpDHN31haowZEoRLuyu
NI64XPWPDM0XHbQFApXlQIQK6w4eUowMtUyrtfNOkBOZahXu6CQCcWD3aaAQVvAZReWYJsgUd6CC
Ym0qolbYgY2jrEMvT1bBq0k9lAeclsgOppiZAGB7pf/rCsFwc6UE8zpXFaFklgpHqGnuETVfhPL6
wwRFRY8ELwwlo0pxTTYAlC/suZbSihTPSw1ZHP2kMUDwLJgi32vMtwkjzYOorCMKZ50FHTfkWpvs
1VwaIOWgCXFcjGmAoIV29j29Qn8VWVvkpS4xJGQjHbj6qwK3XIT7Im4fQb4niz+EKZ4OWjOf/ESp
WTdsTr5A5uLjlREnmVgwxBWCMXnAO+A7ftrjeI4PQS4BFXMLuicZDysqfvvvVGPYnDZLdHlYYrfT
Xfy1ITQZKjiUHkrZzKB1UqLQ9D+lnYcdHYQrYV8YC34yfh3GCttUm9fQA+5eIimZKX6Q1rhWb4gV
/KHDc37KDp/mF3doeZB4y7wheqnFRHBiz7xAyvHajDNKuHFqHJ8Wk+2u8Wc1/bbRW10wDEpvutdL
rdzpaps9u/wARWKFwJfCoBiU53N1EOcN+4CzWcLRrSWh8f9PuUBSPMwM9WTLqHIo61VRz9TrRf+c
9WeyufOaIqnDie/SABFbcrFJrEkAwroFSdxP4F6vHxBFkKtScigRW3rLvCu+ca1zTEf+Y+MfCtk/
YxfZCySag2M1cMyup5OUX+ODYgIVgNvf6gCc/hZRl0aPu+RKEngKuqTnWMlbYHeDXMwpFuXHJ4qV
EiCl7NrBbGYQEZpZt808XkQNLC64Sep4MVoQK0R4ahsEYDKuP/YWte+ndf/SZ58peh5oQ9BPf8q6
3IR3SbukbcBzgfMaZ+K5Jd59rdtufApOmhPcAerQT0hP3QYr4DWFyF9Ktop54BAlvrbCpx9mI42a
I8gZkPkIu0Iw/hekHUr8XVvi6PVUUZK/yNDdNKDPl8yyj7hdZnBDCkNjMmNFZp+3qZ3W3qILraRH
OUbTkFwYJ25zQdIdZomi1Gz7LsFNAZVQiChZsjXGpjhZr6fpL986QpSs05vSo6a2xAUKKEtmJA6y
fe+E50PB5N7o0PQJzxiBCvVfb0LoQAFRoFNZe+60mZ/qPhodveVyaCwqR9mRe/yY052bpsF1MbIL
19iDIHrGra2Zg0BOzTxPGQzr7vRnQpY5ZtKmJD+CyN2ixlH/Vp+O91naQAhKcX32h6XEv4Mnp8UY
uRq5MCGOM2bRTIiivgQUSqDl0tEqrrxLuMUiSRd7PDuGstS3/49DbTw8M2kl7alWmyoWg9ITqHJ4
ssxqCWMCXvCH1Do17Bu+vGqWCtniTmjoSX83n3TvI7qPzJghenzB0uqzH0+ZcwwxmXGtMoVLkMmu
BhxWMG88Zp70EHJLcpc+lNo/rZ+oWBEWUSY5oa4DmIvhbT51WxW8ZdzT5xL0ImEkaPJN4itQRWKY
VabLe8WU7tlKgJ+mq+1CtiueLBfX3raAd3aj2IwTAf7r9rcwJBXxFnWN3qyycbW5ulHHs1OMOvxI
yDOh+3wiQu8EjfJ87CwG3ZEGkd4FR32cj4pGLfaGP/GV0opnGrITtHJRCqYQ+wW6k5/nJUSOj0Zt
JqFnyepQEJQLYtyOYPDNNZ6N4W3l1cniaGNsiEIFvXIsK/C7Ty5IoVm0o+8NdY6tVNaPAwl3KwjZ
Fyj0fZYCZaRJCke8Y/s60HzixEmrICGBMjVzhbKTyi1zBcbXGqpurYKHIoRial0V6GJz59mojvs3
vGu7JCrsvS0m5exrGTWhn+UTTj6ViKeVS05PtQOv34OG8WKd8DyEetSDvOr9JBEsIYLtM5T2WoUn
+mM/JBPXIaE7lLwddhI3ipnbi6ds2qkLqXGT8YnnsDoR+0PEfBX5XCxk4ABRtJIfQQp8e5txpdtb
RS6TExrkrlvFM02Icw7GLPotsciqt/7jyI0eYAl5Uvk5xJjQs9zAwi8JZ/M8wS+gvnSp9ARSCQDc
FKdo1h+eGYKczLTQgwzc3G7Cr3GoXy8vZo1HNJKAYGZCLRhcLGnRGS2D+LpLDpXxDhhdKhMTnJmn
JEqdCvCviYhK7Rq18jZHdKeBM3GUQiJUyKMr/Gj9fMHEBrXpXY9G/gnC1Mj5jvLzo215mVfbVNzJ
I8l37EHzLoG5jD/3Yjhd2a9W1ASTMIzNAnsqmuePIuqZZZP/o77Uh8nBr0n8cD2TuBZW0fW4AShd
1tZy4Zf50Icv8dwurqpnY4rZMSoi6WcZAu0SmYeLVv6CrHxJrsQlrSBPLc7vbaL5wUDIZX0Bgh/s
GZ5LmkQW5vJcJa0QF5P+2M4haWQNfqVzmQ1UZVLrFoCwuJzRjPiXdOJbOaBDaX/2pwGG74xQITkP
Gk11i0kbTkec6/y9PpHk1mJ+7ml0BO3mbVUbgNgPa3UNC6hko5ADLKJQJxFIkNffY4f1LGrVb5hX
QeS9dv02M/0val7ZVXBwrx+b94i1DTymEXczomPGI4Y76+Bkk3SEKBAoNDlpEsfGWo5GxrRSx+jH
L5O7KyBxR3JkrcG7kMZ8ooZI6fZscZOQCZJRkduxUIw0LdFGvwn5NhRVN+WWOchrLklqCifuTVeR
mSDL0GNNtStZOAkXDKh/ndzVPgRsMBJvr6JBP2qvQ3m7ZZjhF3xlhNBh37+AITwuVoPfQaQgZQHX
VWy1BzceOkG90h1c1dfC0p3/8prMUTMsO42Iq2bTNPmEShxCmpGLW1ow6xAMHgM2xqlI1OmBDfsN
gVPdWgvTwf8UZSKVpcNyb/112kThRRA4vKxJY+K8AbIqH/RMdrZ25l5l+HQA9JvHWnu95OljjeFh
4D2XXh3TyZlp5mJwaL/+M6cnrlQXKnJBbzFAjS8CukadR0NJwcbLBk61kmX4rEMqNTH0jrvMrSRq
8huZChCv6M5QhsF5O6Fm1yMNvusYxQC0afOGOmxgLrWNSgNVAzUjfwPQKMeRtZINntPmJK9yBEIw
RCBbND7v0bW+8AMCBFSUZCpm0WllGzYQo1VMV1YsVQXAVMFxjBHMNjMRmpRqa/VgUxmuRpsP9C0p
2p1nzr2hkYG6AeBHomrfkGzT6+3qQvcgD4tfmhxwsq8i5z6kuzQLHIp352drMTHEypXR562TnFL8
RLcfL4pwZJK5zTdTAmODGzrDXzl8bbWui9qFcTWSe67sdL2QhFMfC5KPU7kHCwT0Wx3aKvLAyxk2
Zu/r1AxNV428DxgWa/KCReKoMasMic7Oe6vuKfhlf7VUheIFcvVUQi4D3eheCYR5cEcEUzbQANKP
5bXx5D6sVol/zXmG9kZMP640LKjNycDVs6TXiK9LR3zGWAQXrrNVclmjGanqRat+YZVjfFYbA0v7
gbx15S+Y0++z/FoGcfkUuvLsgHeQFRCkCNAKsl60mij0j0H71sT2VKymxM0OQ5Nq0zU6SMPF2x2P
uUtxc0dfXODaWLHHESrh7gZYu9c1zyOwFmeUQmE1FmYkLvvenYgFKCB9ra1wSRYnhTXTeDAZI7xe
zwUx/vw6Xg1GN1kUytk37y22rmu6xhUrEKjF+0Jp+pLzNyYnxR4QpXGOPcGd7EP9sUUnMaVyIW+q
8BpnqGsiRI+GU2nvMvQzpF8VVQ/bL1m8l2l9cLTutHIsNc6lrVsaCenL01Yb1DPS+TJ8vkdrUETW
NM4qB+NaqMXZ9XIkc3nCInoKAfyT03SPS7FiBh8vSCsxOmi6VGtQJV++SEinisqzz81HgsamE4O8
3PGLN6QPA9P+QvplTMOv5jqKfO5BivDymmlNH654Yuz/CF8Y8mDPibXFf7yuTVh6BYSI2JM/xUAh
ORz/RMYmnA4PRbE/77hcw4Jgk8SPTKzXrmofBOIuKg3EnjOyb61akgb7UkcQeA/wWp+6cuBTlDC6
pFRB3BLqQvEcjSg1YZGJ8vJNcAIrP6xelyVl9zFZl/imC0lyCZvP3dR53Qx4Um5JznYUSVYr12dM
zd6j4FGg4q3HZ4UJ3LGv5S8rNYHtF6k3KkP7kKJmteV/rryrcPWvPWuk4hTgHHBIiYJ0m7x7uS8N
586A2Kj2Zl1MwlQma9K7w/A/2SOEKkt+4vFAlr/N8vFVqa2T3dkl3Pfc8UfuhTrCiazSFpqg5SgG
ZyZJACg9nLBqJ+ZQgTdAlp2HZQZd4FbvMhpAG+/hKYn0Y+zD1IJJ3Utf7Wo+6gFkPvLzWJdrUd8c
W3JupD+J2ACZxOCpKhSPUGRA2G0/yRx+UVgBuuT/3yK9L4VQET/UzaH2laCdTuNf2i+ZQNKsqzAE
MmUJ9it7QmEwFIDOBmseIICcj5wCsoLQoCSnQ1nx4qEh1Sx2OlvJGyuKa/2ceNRnHbAPlg2SqAnX
w0Wf/wDwy0dUnKyzpHX3qv0dUHC8hsE/RjGUZbKpsAWPfiSPeIAiuIsDH9rl0xZMpqEi9vCapsCf
8b05HVIVM6ZOZJHdTkn5XmLOgiABpa+Xrq93w/XNxczU+K1a8+yKTkONPzLI5S3Sx8tSAeRobeim
V+TRwIOS3+0nUu7J3L4GO0M9Qu5/hbUVp/e5tRA0GYlpgq/4B1L3I/JCoKzdyKp9oiymRXf6jUtX
VBzWrF+XaoBb0eqItL0h5inBOzyOyyAfaX+CLcX5xE9/q/QehoOdJO49JB6e8BVLBp1YzZ+AYURq
uzlQjWedlGtxBQFaRr+SWt1eIHgv8MSmf5BYCuddxhZwf6/vZdpRld+mejLgvzRrbpif6TTBgNQk
89WBrCZRDwOWhs8uTEpiqDTKx2kjnd6xSUznrWRg5IEtFDXZFFnUreeTACzm7KMk9yMlQTRdrxzj
DYBCaydF8FlnlzGuiVsE13GoxbfB7nmSFBQ2p7h5WDq8d3EeyJaFaRtu/yvex+vzhyEwjB/fVjKp
uMKz7L7n1CW1bMckoj7kaFKg4nytFGj5qXIE2ZFmsfDig15EB8oR9hlW5u+qA+V0Tr909BiVStSG
CZOolbB7ckw89gRa50v6x7HNXNVp3jCYVgoxgqYZiWkr8DxpGDjWW8FaSZcXqjtDjeoUfDCq445g
6MzRngUJ97FQDCd3cDbRdcNkKgKwvWksE4pK6Wme6r4sh/lDbcy/EAZOUYIiIb9K2DQhfG7Lko2c
6EM5TxpVdDuWbfPtdO8xjFLsTFq2CsIufeTJunSRw1U2+UQ9yd288UMAjealeD0t6TdhnprdffBj
4RaQcz1IE3n9Aif1pYgsjdABRNHC8HYm7CazcENGJVL/XhGBcr4KV48lvUy8pIWDTJkNHCiP6K/B
ioXX88QwHs08UACvUqXQUrJ1NMVQ9fWOjZhmnCHKSfXJvmXETjHE8+VjL74iAdv0Pwe8M6L49MKJ
+FV7vkFfr+kO3+/ShySwGv7e4KLhxS3y9m8jznQTnG0oRryn3y6BMRQtcWW/q3wCpckyljfa6idh
Xld9gqCMQUGFzt7sE4DWYQFuG69ukD71QqHuxP0Q7dQ97wYATA3KHcNHx6rKvBTPOcpWUltQ0rbr
x6g7BsJ1H/F+CeUC4H+CoMyAKrLng8qUx+l+/ruKocnXFDUCUBxMuBvUWcb6SMjfYdNzrDIa/h6B
/D8INQ4nbbtDHPhG17CLoSwf5h22Gx+G+C2mjNfTcj/hBWcvS9tQyOJZpl6vCbiUB6ENiY1cmqwL
iKLtajBVM1zg9jEhT2JrUByqdk/Dc3roLE0BqiLFIRKZqgfr6FiAxtOhCjWGjOjVXJsAwNgEMnjL
8KcdWaXM/t8P1wvQrDogf8+1Zk0ap4sOzVXdvC4XVc3gC5kBzyBBN/xhweypdZh6/2oibBIfk1lr
BoqCcBFTP+qWim/qg6qVjL9rMpPyZ0NgyQwTLSzFd4EMLaxGglN3zsa6S6oPFFQEDak7UfcAc0b0
ABT80jgO4SaboRO8780r910Mn23s6hq5Y9sSI1DyDJALpOHD5FyNCjLMMNzeR7ZYQwkvkzpqoTD6
mM3zOZE+mSrMiXxYz9T2sGZoy2QO1xhur92FCOOt1wATeZbJ2jkLnkjWTVer22+/GUTvljT3orPr
Sm1Mb5b1kOWFavkeG6DHElNycRgIPrzJNTp1ZfGAbL+BAFlxYdX+Va3hoL0tDwVWvmSlVJlU5gGV
zpSwusus0i5hgri/7Whup3w5ax41Lu/o37QuWT6TLirp48rORmC/J0j7LmzVsQWrEBpKvGcDv4ns
GcdVWl+swZG/TLYqtDz90Hwgi0hyPA+oxheql+tEhvQUKkBhVJOp5KY4HhjlpX69ANM3S1CSZqsZ
uJ2GwZHSQVt314azbG8l0egrWXQxNbsiBzZ9jlL5C+w4xPunlwWkI4nWPvTEsZXuUPoqgt5s9oAl
luQw6tD8nbSIPYpzbm6N2Dyq5IEOzAFKPvs+ly/A7verZbN7xEORqL6rrWBDZZlDCtj8VURmioJZ
MMXTCcvsRlV/rqCND14hNNI1oBvvC1GrOjUi5VXsBrhaqHrBb5dzo+YJpM+mu6tVF34h/B+40Ulk
OEGNIgKi0J5NfzXwwe5CqThYst7lGe/53KtehT9rUjVp1gVGmQBoH2GL5eMJdpWSgFaWP7WRWZEU
SkhCp5gBFhkgtiP1ZsSYwMP+A7IhfP7d+GwnLC6BD4iMsnOJicn4U/tBpfBZB9hAdHwKebzL1b7P
/4mHPiDYBt7C91w21LQN8cEEme2bc2V/C17JLya5D+KUTriEBd8pHVBTHPECsS7iWcUqqoiXIzK+
J610DyRXuqFzZvpqy5jeYjLUKB8hnGc1+Ec/YFE2B8dd57IXp90988XfNMjcyi9gX6EhL21j6Jm5
kACINvVGam7mdIXvyX+cO5nmWP+Fff3m3bligIBOaWGZuxrjtmjznroBHBxGu4z1Oa9zI05DHd9r
Vzl06Z2KtYf3mw7g6whBSSx09M8JqYUSIk/7TpoYbBiUzswBZG94H65vNin7MJNXIm+ItO+SQw/I
6gA+IurIPBlXoF37nyLs+jIdJVMVy/AMX8j43LbKlyOYR0RClqPS8NDbRPorHvfxYxGu4TmxgCO3
aunQexxlp8VXlgcdUd2sKK/S1pmXTyxod+8pp8RnLMgSS+Kyz66WlpXOyQQgmVH5lSclo0d5Jqk9
TF915I7nTxz6JWLHfTPBRu5BZRmD194Li9pVLa0AqwujuuIuDaRkn/Wct2pH8pYcPiUNMHWvb/5h
+B7d7w1guNSgmaIMIn2bIZKsrYAW6nY60R4YGbjP2bCKpmjEx0uJqe2SvA6iBpuWFMZGhgJ+fnKD
75KfPSN65k0f1z7soa4WCBMkTTysu4eSQxvTJi6P2239loV0sWWh6FXWwG3o+3SlkrLLVdavjW/1
iUhPJ71qFLz6a0SfdonnUlgzlVqX/aoERXxfAYCi/oZxErc+6mQNObw7ChT5oHsEZq5BNzSsJpe0
6zJj3veO+kHngyWFEycBtXbqUoFWrnh7XgaMaVexflP9/kG0fwqwEzBahzZBiYlaFdVNt7sQKJ+0
6C+uzdKzi0Wz5bnxsoYogwthKm6irJ2hngPqIBLXpQQz2ZHdWabI7FW8jd4wa6mBxREk217dNapq
+qNmmi4NbnWnXV3HA31nEWq8NnKDrHH94YAlW7CT3B06ESlRaPwwnfvnqpz0evi1IQNkNGVwm2IO
glPA34JoQjxXhIWqOThqMF6UQkdZlpDjkskJMHXHW17fmsKr+MENwF5ruQPOoeYgDHoRsgKHjZa6
fqigSDc9N3XVJ/v0eEdq+UxXE34REh+HBuTBYf7vzkQHl2ycD+m9jzK1I6wfWw00BmjDoGsBX8An
25EDUHYZa9SVaYrws5wjg4uibF+1wFcLwRbhJtc2K11Q/4WqT37KjK5k2g9jpQOZ2928IEhjCRA2
eqV8O9pRu6AO6Sum7QwLRu6vFnQQdJULNjqlQgeRFJGpIf6i+gaJCxagDvZDuUgCDFU6Fz99hlda
Dg6J5M+8JnUxfN4fee1jKj+SFYu6mI6LGn51GKM3QByJTkrYPS2tnZ+PijlYmA/VbtIZpYGcfUe2
wj4tclQ/mAzTyXTFs1/oqCIgQtRef1ntEC7GDMrXitwOl3T6GwoVNrIJJde45XZ9J2YIBYvYokzF
8cmnBXAcgbDoTiRG3uqEVn9aWI7bNzQhN4hVGUksXweHobEbQfSt+Z4BnIxOsx/4NQVrpIs2syBr
BH0LugMaxhz41TqW0INi9VG+3YKu0Y5tAfBlrTGJUx7aGgJrg2LJPu+RvDigoHFObdl/Sgg7Almr
AAHF/e0IAIBvxO6Z++1KJiES5bnNXoXy3H+P6wf3qK9UonuoXTPMK57bLyDzUXUAJmUol7G12aBH
tQ+0IWA2EKp9pOeNv+mtqxzSjzhC454+nDncIYEyj5qu7mfPMUTpIEmq+/4RXqbh6UdmuLXxIEfo
fD/pd0fsRGe8GWOHT69n7dh9zqc1gTdm4fn4mjBMwWMagwh/9UMIUUw/Oe+HArr41Xr12+ib4aBn
Lk/Bc4SQpLJ5eHV3NgA2A6dzNFhLCFA6GTlRGDpsrgsykZrrZ8b2sCG6yyFOSl5iDl8Mxhfx8PFA
0JyH3mOCohth/4YpE7dfq9M3tctHiHqb9nkMnfmyf4b7jEduigiJX2rhYls3LiDKgmRUIS67Qf4x
dvNK+v7MgVvBp2Kv32EbY83Ey7+Jho57rnI+xwQAWRsBj5/CgPdB4C+ncmQZS/jQvSdBqJ6DoiTy
SKeYvnxkbk/Jvb6xzVIG5UcCO5c/RlvKT7buSFcVTokpjE+kghzrF6FZljCmZo7JHskdfZj2P9rK
6iqbqbjwLsZL/lfcFrJt2DXgVKvQdQucRZOXeM/JegZ2uJCeoesN+yqrCIvsTGyURaBXDlc/UhEE
DBxj1YMqBQIA+IK+VwuuSg/AYC7A/J9V1RZ9WIJh/6U9LFR54qaqB+32FPTKDhC4fUwncWfl/os+
/HBFY9jlm1V3Gi4zH8gbw40eoWp8YHMOBEt1wvGbjTtHkQC8Nm6d5EKi0fBe5wUFKwOVDkD1MiK+
j8makjyo4dWmwV8vXaS4eX0mU8sXD6zIX+3sMSbTZmpcjMvyolvcR6PUmFqvz4zPeNXmy4gqXerc
1Jlw5hj+Asov/POQwdt/YvJ6H9knILU1S7TDJ7JQhan0zenQkVUag2lglrK3Y46IgfA8Gur1DrUu
RDM9TXwYqR4FggpdC8Hy3OTYQaYv408QOayVK0OHHNvG1mqTNFNHvOXOdgkwK/lIu9O338wVzS4v
74qwTmYbb1SYAoRFVyJ6qyqEptZvRp1RKWBm4O0G7yX0mU+kiP6fRUmApOSf4sodUihTbcdSC+xj
ToIaYTIN5mbKII13CfWrZI6QAf/uK3/hXbqY+Rim4vEHTQo8MQKN6TihlxpBlpG+tC+qegjA+1tX
qUuWvGQ/3z7hNGF+3hLksW64IO7ln89AYciuix4dsfzF7cny4iLNsE4c19tDILdC5It98E3eRtVY
sBXsP7WH95HOnWKXiKTRiuXtJoI5AnZcBCcZ4K5BC+0QUy+/0ohUyZl2edQIaXS0q8zaz+3NgOeY
dOoHBJYgLeNApFyhxpTpAuUcIi9/Gj/sNYqYWtpib59bd6CImmPVSTr5I2l9jEOQYMAzkuQwC2Th
rn1WNhp5U3PmkUgd9fbLIFij4YzL/BGfyZksPWYxx2lyl/9pA42a2KXHE5Tz2iSRgDcATiFDqyhr
zbKm3VLSeKMsNK7h36YpY4wqpmQAmNAXCkDr44h71nSw5MpnP5Jr5k7c7KwvNun8L/ngPEFFG4Gy
kpEb1607Gs8R/Z86f4/JtYIO0255I9D1McmSNpbwzCugJcIW1ZFKHSxP235hPUt7DPrvdo5uu+po
QicFiFWg5O/+ZVs+8nYHHls8Tzva2O+gkf0nFnEozcyjHmNg9JHBrsCGY0AbV3nHJxjqGKAf5Nus
db/yirriVmLlovD/orJ4s1aqdjnDu86MtsaDrvQXvPb37Tacv0Eeomkhlj/njsnnDmXihnLx6QVu
P+/prqxqeTlkxUf8jcyHfAahMQG3/9o6NZcdB1FdJ1y7Ghpu8hyyQn+mFOLt/ZW1dI4ByqPuf7uQ
21QmhhUlk91riUGBkMSJgHjER/8k5LBre2gA7K/L+zvH5pqtGIgbSDNB2z4aStmaDbWkVPij1KU1
+y6nf780eD92Ps8wYcMcvexWYD4nDcsepWUszw/tgkYvppSu7OW6b/MHhsjkAg7CDmiNvTUy27F6
LH59O9U7Fs/+W3hW45fQEUWRqszzL6LB8syKflXPg0vQbxUpL3TqHwbWJfyORkq2e5Zeh4wMfVhb
zuQSY5Tw9L1EkJDnKkz81K4kTXeBfKGAr9l7xPCWA3AliJy0ZhjMCm3WSGjg9mqHiTArpEifdevg
YmmWg0pFXAd/uBQ8vMC7ju0NgBVbYrUlHcal8XnxoqBmO/qiR7orbI3KdfUd0/hsu3clh2UDYq/M
pXtuQrvpOhGy+cniinY7gKmXCWW2HfFS0e4fn7dpiKw+NfuETVdGE+Nwp6UM7G7Do1T4RUErJt7z
ribHwDgqGQEbdGLI2dY+GvPjOYeIIvThmF37SEFQEJraFbaYj0IKL1k0KtTIVXecERTyasMzJquZ
Wk4g0RvNIZdZAF3q66B4Qf+Unjx8omBrCVyZTzM+7jqbIQVRo+N3v678OL112donAc2W/2JLngDq
KBtu40g2s3SRpDQb591Dxld69wfMdxuX9JLE0D6cLrV+3w9sgeME22a1LlcGo4qA8eVkgQi+XicR
iO1LZ1Vt9msU4lJUB+N63PU3qd7tAjwXO/pXV5zHASB68GEQ6AoDIvOMhRWzHxlsf+bXkrUXeq94
KnjTPwYPWwkBl9Dy/CB1WdS1JYQUg5BlqvbBzEK6aZc10/rx6ZhV27hCkjlZrZkpcW6g4sZnTsyL
Wp5QBOq0/to/KSV5wfWaXuIPscfEezRbwvcR4jlCjAWL648laBAYLhpEWaV7SYIhjZ98eHoyZj0e
hCmsiADLbrNbTUhFsiOYMC493QqY7bI34PWuMzScJIAIzKZoh4jg9AN0VDtMQMfZPmDioUK8VLPl
f3ri1Nj9pdQAo9jP2afeGKk5YJ3/5lK4XE/9iTF0w9EJe+w4RnxrF/+/dZHduOzjq7gplsql9nCw
Lxhiy6HOejFP7w9lWGe/dZmlHY+9RBvhMS7r8Q3CnMc41szO+J1BMyHOOzqacjWOtBONVs81jDxM
mAax9gwgt67Z/hCGzDz6aZzP5l6tQlksDURvckH8Fo9BxsP4GNJxY5bA6xfIJXqQ0PqccuksuXoC
PCw/DE0LOoRdYpFx8uX1RCNfQQCwbRVvINuYK8g/UtOB6F8hhBW6fNGxa/BVqsvMx9tmwh+aV88S
6bZ432SKgM4wwgNvWj37nSFFQfBwL5PgyUdTF2ApNIfU/ZfY2ecX5jSFaz4jZlmS2mka9YI8s6V9
H0cuwdG9IfbCJxUjKRwRVCOF9U0X1vvcEhXZ+33Ef3+41DpNpH+7Xqna6kzkzmaao5nQvIf+LzNg
55DAhrcNJ96o1Tg2vMsfJvXpYDVeB8N2PwGBA/aLLfMA7XCw4c0/gJj3oFTSF/funeOrAYf2vdEt
tL9vTwGqvzL3qmrYi8HSfUPTReYDunI7UrTjqgbCUssFvXEjzsog/Px4bpa1zCha1YPvPw2Zw9S7
/0kmt3dO3lx35iNdfrBNSn7qC8TYd+++Vo1XP6q7QBRtRBJNgtfafsQrxZYgr8IvUzgovolRJLHA
qUGqq/oCUJSzBdjHDJ+htg1DNZ7qkJSWiNUDbz7AkTZLBpPeVcsZ23rUQdFdCFC6AN8ywXYNbxrj
iaIA0kg143annj4XP/A//xhdt/X4+lKejJFY2U+udjurgsEbYwX6M8HQKvkrDadLQpjRVCWx0tyY
ceb+SAex1Uv/VouQDf5yNYelS6go2MnmfWfXVUb9wOpAdWWQ61OUFhRsDCcSdwpLynGl7e33cEdT
hZijHrSA5j5BIYqLQbT4apSfTT8vE58QBAKqeDvO6p5zkrw77TPFHM2pGOIaabK3QFSKq/cwVJEU
fbNsJvNh/mVuxjZi7GQ510lica0DkMdTFx7WNtQreHohHluuUiMUT86IWCAaPSJfFonENDTICckb
T56Cffs6eXK7+1ty9yQdfEa+F8IxI7jG1MiQRtiGVc2DPisPrGOLg7eTIQTH7rOiFUfQDBIquq7r
TtirQ6xo/uN/j/Ab96Y2wwqu84cmBPWhHdcwPPBo/yioPyRLBZH4+Gva9uJs2/Aa6K4579mPN+n4
4l0FD0IrurNavROF9uy7AMm05epo7Y6Mf6nrOaFuWhGC1X1YkHvKq0BTJ9n6zHVn2ooAXgnLHDsm
gOGgcg4UyzJcCYFZs85dKiAaxYP2P2JFx9lxWbOEgW8y3RP6Zo03NepMWb3vU+X+Cr6BmyW+Jg27
/WSKCRHMsA5ojWGVvLvUpxdqnVHbcFajlX+eQyykW3PaQ3/3Vwa23XJkX+LRvzzuwrU3tjntUx7+
7PW6JUtvGerFXyCt1JJ0PY3C/FA9nJZve7xnnWVYEu4/lSSpi3Xu/cJiLXvgq8uUuqELqMhllwOb
P5AQ1eJwi8Ic5XDAtpLdI0imS8uxSBxT9M7zoZ4hmTQc4kNV6vnoBRqnVS1/fRVLYRm4BiyRwNOE
JKaNz8Os02/Ol9NJgJM3M8TuAL169arShUA1UHtDZ191EKimarTJZycwaQvKtkWeJErEiJHfySV9
ExWTkZYh5GAVvIDvEt4hsnWwUfS+lnVYgQwfEC/uEsM3O0br0ZxmRYgDj6mwHH3+45sm8daTU8mj
soBQ0dXTwcJo7UdXMWMRDFhOGl5TDZRM0+ZpQvMbbWTEHdO+kPVltmQ/HgUkiYo3tDZIITaSl8iP
TLEwR8tnNQSog2gCJetSIv7MprQSEzi68pRgcEn/2t+4RdcWtHpaGwaFmfltO6Gwmcj+BfxSNNOt
aTUpwuQswJL/sHA608SX7MshPMh46DBrXm3vsocj/pKWmsf8+7cT2q9JQq3Z5rIMCZ7Wqq13TR7q
zfpDJ1oV9dNVGSlGZf7mtSo4ltr9gUlcGZJW93jmOcpqN9xRop1if65xG8e8YRBURNAmdEumL96V
oj5sgxmrx9vgiOoYQ81IjgqGnGvSgM4+zA24RpY/Rq8Y5shOvloWN6zh6Mi/IuWza2VXAOlrQJV7
Fjv8U/PIX9TfCdBEpq33D0XgwF5OOqifvQ5TAeMGlzZKwUeVWI/k2vUkO3QKaBgRE1WxJICFUtgM
2dl6pg5TQr2LwQc1bi9ti2mwgRYGe+Rym2A9kT/oRNwGhmi+2TrDp7lXFeQoqZQmsiFarU2sYZf7
gcx+7br5o184BSVTK59G9eHyxKp/EARIJ7ovbYrZ8UmOl47elZ1Nfmjz0UB3gOp3+cF/hztm2Z9W
JaPZhrRjd1ZdlhJoNtQ2iwwWQve1y4HZi5YUqWHO8yuwn6dU7GDr0FKfU86cPpGn9BHN3IhCKmLJ
UwI9u9y6kC9Kr5iEw9y54F1QxyOW2EZcqTnFOmMz1G9oHbph1sg0R3NtT6gqbCXCRDkFmhDZtEiR
adx0xEbiErUoYNfYNsO+nHS0KGNgXGIn+Y5B+TaZvEnWWEWBNTg9vWDdt28OQMGMW7LxJgM5xLjY
SWWyRr4e6ojA4rkFPW9pzcWMnMsTb7tvzxtvxlG4skpIcgZbrtr2gI69BKzvwRWETFwsdhy92D5R
SXklFmINkqZ3xGZcQ+Xh6kyzNBYnPXZRE1WCNc5rzyV3BNQ91d8F3MjF7ndeKZJOt1z1WP2yApU8
QUBuf3dxewdjzSvv1/BqTBX2LGC7J6wJCcBQ7E3O6Fry7pszLGr9PkrEucgmf8H/gjbkU9sYngmh
soH/Q+phL+au7jzowTmWR33dbFXWJTJletUDnSEutbZv37UexGKoshos3I4PZ+p9ieTkUQfvomHi
C0yS3yZ5WutoRMCZXWLbMW/8EbHserGB9hpqTzWxABCQD1fkzS0GdOIrmwB6ITkh4V4IYAPyZocM
DY2G3aOQ9C+CvL8gqOJu/CojSmmZxyxYUTEEfOqbgKd4/RnsNARX9q5vPFmNq1Zw+IaOntCnMPwE
4KBWRvRqQJNtwMDQ+FaUK+4cAj/GN4XIlnxlqGZOKVxlysbzAQA5U7o5jNce1d8+EF4Pt1fa4TP4
7srB/FR64Ktf4zaE/vlk+rKsewLxNMafTgssr6h8VfZLvlnIQDWvln1/t9QMa/gieFtyAbvj+Zq5
cxcc8eI+Rh7ApTs9fjbnB/xNwyNo55OPopErsJqSl/gvObI7Vq+8iw/gVGTQkpVidPogoe7of0qh
2n4ANrh30jonpLP1Q/MbT2qJaSAZctcKUYfyUHcMyC38Tfv4v1Kn7QyHhO+PzamhrItl/90SsGLQ
Ejrfb87s6X5MtVmtAaoriJ9u0hCf58pFga24PhL9ueW+SN0Qm2j5/NIminFlB1AK/oQK6o/kdgLr
otgKWSci4BYvJg/FkFGUBlBADS4T4EHPGBwKG1WzcJHwTPDh475zGNWA/KhZu3wjmnixA5K0IdbS
4tBK3AXFBOcRXtA3Cwj0IphmJ2guO6kT5Lyq5YX4YPJRRxRqQmLJ20+6sUL4p26LS9XZnxlXl2bQ
DX7nmUxxQb00GcQf7DDkbyxzLUp+XB2VnnXDvv2qsJY8z94S+cvGWuvR2IpImQ/7XI9h+tD1CXyg
jXqw+iUXc6j31ohRNZz1GfUJH7i3jh8Ybij92r2MreUyp64iBWvKCAGm5XWHbl4QCcP//0oblDgj
xaHh4mdtal2UCz6O8FD52sVYgB7XM1EDC62XyBZAEO3xBxR7axOgfWQAgIPphkGbXog1g4Nuc8zC
cXdkuB6kjF2vhzn3nhPcpjxiV0KFC2v7+HFqHKnmdccwnRYMd1wIc8wQcLOT0Oe0k5ofEx+WoTwl
rDy8WEzMLJ7rWEzYdg0px0teblKdmL0204Rydq0SZuWpSgZpqrW8hjqKYRyfcEfFmN7OaMJ1rViO
ihSOoyEtQORoZMSU0RNNvBcHCT6isrVW44CReE7PoRvSrn065vZ1AzcHMyzY0fhXlnlKFc2jCJ7W
X0Mv/Ejowezon18b5V2stadYvUsZpq8o5Qo/7kpcpOQZzMadpz2is1mE6p6rtwuqP66jJz//LuaC
g44MB61we4bivA7pw9ROeEclguW94zkn9x1jNNDijlViOJ2ijBhKrWOrSBY7n3EZ3buqqUPKdcYV
Syjs96UNBFYKz/RV+Ilvp7HAzp199lbuFpJvmaHMTaX8MeJDBs7TYcswtJj4mdWMrDiVwnKIaJQQ
d/qzB+SCjkG99e+/iOU5Vk15kTi2nkUWPKmogXMosNNFEheZFaDyz+/2305asdy0tyDflvMaK3FS
iiEsy0ienh0Wb8RQw5fnYThjM3q4q6jWf+hoyjS2WDiINLYJExNLPXHp8vEgj3xLmecckTs+G6oP
KPlCA5Jh4z/SFQzdCC+/khWNaISqU/kbymzXq+q2q5WkrB95mnuxdBobXqP+jq4WMbJoOzhG/pJW
bLX0kzbYjLChi/IvZw4sLH6TgC0HQwMHEd/EepjSxtVAYJpzEqJB9rvu8msDUMzrNTIivo8f2z/W
ULHuhCZ9iIJYQ9s1ViqIW0boyQH12GKqXMDGIjdUTPjdlvZFKF1VLERSNYaKM9CGICtfh7f4oBka
O+lDMEy6NKe/M4jNBn4VWw7q46igg/LKrl6VS9nXLK325YAMwNj75ytAJ8AMbv13m1fzaThin+Mb
tQ9oS1OOp92v1W1Alq4TI2RpsztcnxyOYeSmKrR/m2yUtmovml4/ORV7PcnrqBrUw6+bmioq6k7D
CN1l/z7P1oIPF6hAGmHYEPzOEvKwo5Fn2HlEWbRpMCTXBjKF+gtq3qvghKSYJcQnk318DjSCYFWa
G8NganXetMB7jrhg/D7vuEW29XnrTD45QURhHbXlXQvY4pzzgWhNrsd443pMd1G7ZFkX93+0RUsr
ZJs67SoeBMTOlndANd3fShazr2Ng2DLdKoOU+PkbPOEdYi49GHcVcZ9OVNloZZkoQTT4ZMLbIpXg
7PajP+VbYfFOaGkXM8oNukSzYbcEoCZiStJofX8wwApThLxXD3fq7QgFoUY4PqZqkSkjIbzN96Hu
+ag/JgXpiwl28qlCdwQlZeen3fEvTbDQyFqeE6fQns6NuBGIEs+LphoiVNDrxZASoc/AKGRNGA2k
4Hvoj4s2xqt5kSTUMtn2uC+SM7cWJ7KKL8JHsW61oAHYJvAp5APHzQmndB9nSsI7QZUnhPVli+jr
VufjF2hZrr8bNyqo/8YJS5q9JdPdxyQ1SaB3LvKrF0PBT3Msgyd5XYK8ChUjmjgIhd/FmNM66BTC
OYHaqk8TdrbdqEm89Zd1sDSyivUBz+PbXJ0NBXTejhgLBfFEyEFHpfAK2TnbKkL7CxW8KMtaToEP
dk01ngJstayFUuiNuNdDhfRg5qUwkVtgeq+PKxJN70FPYawpST+DjT6X8IKl8iy6RSC+Jkg8tRo8
oIwuTHe4YoD3Zg62IWzGrT751xsUOik5QVpY1+CLwWX7j/L7Y5WUeQzws45s7r7n26pJOFipztvc
i12KHMP1nDEBw6jZ1pA+a0x1nx+ytUcqFIC74/BKxLm/CSOLGyfayIFteUHIdFIwpxp5zysLBfiI
96HzKgZtDAskFfrE+sxDtRhMl/iHRDNs7LEPi0RmyMfCe5s34158JUBB6drswmYkH6hq4LjS5Wk6
xa1GPrbL6+BxsDm7YVP4QQt0rpPE48keNzj9en9MOECXdWr6bfLri3GTmMfTJ419zkzRNSUYGEvn
nOFvFXjgj/tSZj8sRqzTflgp5ogUC2i5l0ogc0X8wrYjcV4BtG5x6OJtPSKXRiHQyWhOkTSzp/9h
0Axidb9sbMtK5DND0RDk6rpaOyt3O7Bz8lsVT3VGzbm+2xTHbQgzBA4Csf/HyB284mqxsTLD6R4Q
vwlN7pe47Txo2bXRbngQbrvAyOVM2zH4gAaOZC023cizxObnjoaIX0692zo6MHMqRhVAjj9gb3+b
kDrRkdH5UEzunshVv9ZF/YAJhYPaZ1On3ZyxNBvylNxR4GuXHvB5/nZHEhGkS+kElJInVg/7OkWW
5qP2jgDruptlH68XLHNJeLJ+HLK6mnx2/dZrrLjdfmADq4nH2VFXvE3Ao8Uk/09jYNKUMvNl46Be
qb4TluIdLa16IACHz5ClGgWyC+aj1IvQJKd7kcKi1k2bMj6atZTFbB4hsdJRbC5omFlHpvENB7f+
idycZPxNK/807lhT6GwE6GlL9sB0D2lPDoIjTGsOVTKjDunJWuPHRABaulOWPERcQbBiM4tDEJR7
Cb7yOOcDuDbSzsyc10CrtmzFjVqtgsNROMHOZTCWZcSCZXkIhA5hwUuamLPuGuPHykH51EQb39gN
4LMH1u6d4GFsNF2/qT4fmjwLinqnAnTvqi2ALKd91tG28k6DcblHGIqVP2AmWaCYxzVjd2BlaMR5
evK2zRNH+Li7OXFdarsCK+X+vDsxmHWbdhO3B/ClwN20wAKvJSG8Y0I/1XQWq+bsRIwNUmX0jWpT
ZlEBADIiWFfrUqdkl9H2rtTo9Y4fzHBaLcu7HRitUXZcDEFcNL+JrwxOAOiHmWG0TzJ89F6/zqA3
I6Prn82kqfEDg8F19OHQKgwGjb9CfgUuz+Ay3S5TvP2ua1HCKBm+Q3r28Y2ra8XZ8ENXo8YWeZ1h
kkrazyvx0vsz+l9brtYox+4FutGuSXRyrg9DDQa7l5KTBiBYg5TPmHsSyF20QhKSVPV5SJvB6Ag6
KmrMGOPwzujpk6lxbBRdFvYBwJnGl/XyNWvSIQyxB+OHag38BqjCrL/pqzQaFEe5g7n39EzwXAY+
uDpnoz8a/InnaEqwalTVCtTVcjZZ/YSKqah+mVxkiGFL3HjHHltx0/jAJbIJcEvRQR1rOqnfZl1x
fW3sI3ctWn59Po1vHV43lXLHGZAaIdeHFhuOWvA3wgQav6rItoluekoeQIlcsfU1DbmbLhR78UMV
AOrq5pv4l+tIRXlghDNnsPgGls2SdPw19uJkdXjQGoJ1xprmQglxjD6EEZT+2HvQm/aFs3XLNgL5
0daMr4dIXNZC3PENzITdvp7LGvYJCz3/UYQZZuT3F2KUSe2Wm7M37FXLxFPhIrkoQJA6fcagJ5Z7
xY9/5hsuxEmzPJAwUnWkCp+dFu+jiuYTKt/CuMCx4tAF10c931DyvGZtlUZFS+IvwI3GNfQC3nU1
aRaforLigrNnw4kfw4pGtO0/1y4nRS+JsrzLyCX3Pk0R+Vxt893VKa9wZSOm1Ry8XD+WtKMv1c3l
f21Nd0Bm40+yKS+m8RdlNXAU2Z7NDML4yUNSNM7WoyKS0ppas/NCAi1M3wlQm5B0YkZk0eYr6/Uu
g5NYcRDhl6kwe7cB8WXpwArlqcGT1cJgSvUCHPg1Xa33ZXW8Xv1ka956x1GeKZL/V4siu8WWG4XS
GAF7rWFtHVzSZHy+ojS02IDyN77vB9kDWNoi1VgXCj8Wf/gyRlnDjnW7/nXPtyrDO+frmKmbIlmn
bUcMdRep58L4mlz/s9pk6KH4f55ijHS9TluldU1mGRLa+SmuVkSrwnjpgKDS/kbqC0MIJPk9aJKN
0LtZsrEcBhKD2k2my1hZB9l4q/7qdz5alP7yj8eB7f7nQoz7lsdnVBZ9MucZK21Ey2ER0/qG9P4A
Wv03JUGkLLnO1Ittcc8dY6WWu7KLPFlPTmmUUL7YED98KMj0Y+L4lD0lpiFKCdHyWNULzWKox4Nw
sRT3Erz5ZfTt1+/HBHXGo9TE0jEMdXEBWsizqqBc90OXA5MsDPOFUfGqY7LEijKNLsKj4+xwDHXp
HkPdQlth9QKP6iPMRpKuMoC1TwgmaQGDboy+ZkcseeTwqjYf4PeEqAunKRjCb+N5B3SXMUF4Cv01
TtaflUUNrA18kCR04mXqHWyfD6lep837I3fiFHKNkeerNc+KVTFuW7n12NNSCdk7gCgTHQcnD9rM
JZ4i/IaGOMa1vcEL1/bwfxsENVE/bOlBcgxaLdgLR/LN4oeiIOD0aWV9GW7WCvz/iSiCaYbDapHJ
pJtRq5FU5AEvZC9Fxc3VBsizGKcABxAxtZx/uuDipkAe+8IufC6+xcTl9GQCGEUB3V3QfndxUwah
fCMQl/Y/PvQAUZ8dmcVQIbP91EOTisOYHOvmiod0VtKaEgmOjmldzg93zpyHDmpmC6flJJ+CdXkb
BB6VF9APIX8eRxRtopuNcmMRGfhOFbQhFCBV2DpwNkIKB00hYz8P6DiI5DKST91O7w5HsGkK+8rM
wY9OaeZJWZqV6LXBBiyuOVaxgZOHpcXAG/hvwiwr9XP7xx/9pvdKpXk67diwGLbMO9SfahJvv7k8
eZeQI2xr/xr4NE7MTJ7swepbDzGcnDKEGLlcRftTIyZHjM9sZSbFI05oSLw5x7fSepCBmA0yKCqS
BxIu4J7xjgyIG8KD87wFtU/IeFZg+eY5hZJaInOC/emYFzyAU1TLd2NTZocGwwj0vjRCJPff3Rjm
XEnG90KD/0pZsUKliPjNSQCAzq6f4hgwogYdU4LcrbAwrJTRFDv2Dniv6TubCdf2YRWQaScJUEpD
Kv40AxMUo/1D9hoRinuVSvG2XB8Skwykhtm5rAXYP4EKsOH2vLavwxX3JbQNlpXenqq14d9JT4Qk
FJ/K81vymENaDZPaVkPsV0khAfXfC28YuJb9DpSjiAzbgfP2U1IANo2aQ8bpgFjbHzuPcOM+GIVx
z2sv24EFHvEIaemdh/o7eRm58VRl83m6ocEBbW7jfzq2VL7RR1mhDgsfG9tBkl1B1qPwLc1v/a3T
HOSLqAmonlro3N5M4Vzt1Y22u6HVmeAnZvYogeV8TVxlyAnpNleRAj8YgWcyCaSnELKP/ynSjYx/
CITE6qttdt3NxlHC3j6fRki6Yi0jlH8dec69ibd9gLf78uruuLcrEL+g9Yce80gyuocZ5YqNgfVh
HzaNDUfJWrirGPWQ1le6743XkYjkLAzjEmfCCElZ0zujxD4SYQcxMiF5vHDvIp2aW7MAJ5lE3rGH
1Qmw1fU85Z+eXJF3uOS9FanGXGVLEchhVels5G5FZdtAe7DEQ20ekSGZiBgqpBM938cCvgPbeYp5
QAKoN95UEwoQu8xwQM+LsPwcT3NmqLtp2jhhl/B3bowiDKHko1eE2vCF8gmLleq53YZ/MqqbFBoA
Glux4uT5dcMAMVusYDIibuUDnYdCQ3VS/c6TWicP6xto6SwmGkLayeElNRO+s6osWm+1jQs9ci2T
ELm2pS3Z0xdzJd7d99ZZFBbOznVgEEU9YxQCPCWNjABXli8TxDzcMsOWzUknfQxLHwHnRhiwmRJC
gop8gLIKP5hbhNF05GPnP4WVxMTyq3rC8zHGWLbEPXLc9mssP/fIr+hySN8t4ww+suOvR84GRLhi
v/DSFG3eWCpZtNmgzxDv7teA5uLKMSvm92JiA24lc0AdbVCxEu1PkPMaJzPbM3f4rTVt23p43HTP
KG+vIH/Lt+0MwnrbY8WJHerBOkb59Xv9z3N7b7XTClULVnaQHwpHa5F+/jYeYySkAd7JIKDKKbEb
inRF5KWUKjXpG3vhWvQ5lDh0LAbsyauLh9cljlYdgJqXXF91KT1lrZfM7yKpExtIyWAj7Jn9Rdvq
JCSoFNi97vOgNGjaSdwUYnQQjw1aDuk6hg5F71gnvjig+hYd5IfdVzIELsv1+h4yzoA8PYr3Ptu4
y4mZjfyzFL/v75Rl+Qb0/wM3rrm/c6wswMnbsumFqTgixh3x3SfixNm8pHztmV45aCvsDK8Jl2pa
HW1XckbaL6Tp7ktxCeKE6I/6q24OvX1P9TYn2qgvyGYsxFPcjzsKyoDVN+fVCLp1Rq8qyq0TYITw
ObrrXCEx77w6TixKU2h3qQusF8ShDCsNDJnswBTc+TtMPuWF1H3KiPtYnfUkEeiARjSY8zC9UVTk
08qTxFaZnLRoimwp2DTUptvJ6kfS2f0vwUwk8CySKEofJbcOOn7greBn0/eBq+sDN9Qbj6xoq4fo
/E4/askOArauIpxwaHXesJlHFC/jwODVcsPT+pZugbhBJudHf6V4kiPZnNpnO1WaT3e0cTUMAuW0
Ge1Xt+nTbY5aX7tZuk1ywLw6TkbL4CV/4bxXNG2m1bQHkm1Hr9ohdLvHvpTVBV5CVvKO408KJtyk
ythHBdxvHOqUYkaAU0G+Qiy/eI6GBRunIiCO1RzOqYlNb1CDghJmqBxs/i0aZ/jeKCxyQdsK26pC
4CYewFfEjzbsynWN7nlD+O17uX3XMcdWGWFYi/DVaeKKgALbwqYVEQeX2mPvZx1i5uqDCUL9GM/S
hQVtFpgvOaMpgvlnMl9tpNWK1yB2dC+FkcbsDh0T3NvmayGyvehfnbHDJFEL0kMlWszny16bWSyO
GzxibjTiRD4PKQxhbCG21NQJz+DirTtHg2JS4wYm9dSlVobrmXdghhZTudIzFqL7bJvtmNeUaVLF
mKPlgq4ePX6gfVCxBT/cyXGjgrABWNVykiiPa5Bosne8y9zsOLy1x+CcOv50BJM5GA+VRcZdkNgt
si8whKefOT2cu9OyCVLbjQiQBbW5HYJrj/KUKeJNyA+MIfElF2xKW1JZPQ2N6CCUWeWL1aT0cnz0
eenxoPxYDsz15DGMaEgK7wBXx/5bxKlWRwT9CHzeejyh2u4rbg+5ToiCxZnTvBzSkj2DnfUmE5fK
EmiZek0N4FiZsRA+dC9hU2U6Dm1w35jl73WwCIwNOLLUn6/ldySk2Ht9OjnqP9NMQaxnOiEdLdC8
2Fj/Wmq3qpwmXWBE9Pppyja5+gi1njqKokqeX8DqEZeo1vKvDo1Xy/ewYIoxV3kuPEZFMXWIMdVY
KfSLGCp6Ar4xkcHXGQTOV5wgDwCXBTHzu5Se9Gb6Vtcr9RXj8dnub0Kv+Fd9Cj1JEWm2CCawzDA1
qVO30idXfhmKkdZKsIUYHo903eqn49dAopPz5RfKVod1Siv3A/aWpJM34KegtBqXh6qLDCp5fgXh
3A32PXB1eEz1vvzeAdOScu39UMHNGGJQhKm58TKk8Kz1Vvr2+0zUfJ+7B3zRAyyh/lXirSehE4Gz
3l/02qRKDJyqHjwr6B2JpNRoLb29IKa/CY9q1UjP+Li4IuyIqvAgK65Zzx0KXpv7+7iGHFMXQIJu
YZRmxFsm3pRE8NC8EmYgaRkCJjkkiW4Ue9U9EarlguDZd264yBLB0S3x1s/XLtJwJ1QqLjV+QZQH
5IPHT8pbbV2OFbNFT8xXfhH+QRe1PR1G1IltlH9XnM6H3x0UyJgAtW4xBPPI42FJHPKmM/3WBTrr
cedGGvOvZQmoyrweCaJvBTeXT4OzAwBixTEoed71lD1pztozRT4pvkCkziYW+jAIPliyx5+G4Pw3
9D19e9jYRve2b04HOy4OfOpE+T/9kVtJHUR4AXLNDhq67mrLVotKMb/I/p5e/k3xRTgP7Gx1vGv+
3ol/HphUxRHfRHQk1uKiSL1d4Homrb7VAMupgVsyuxvnTCiFfTLCkBq37rv61f+FCy54GbXVK4Tp
2dZ5QwI2EVxkkgCrpF7nQklAlrT0GtSuKahPQciWTVF45RlsAAnwRq3BIOEc76vliylL0wTEAB2I
XIH9gtFKIXNV7C9iqtXjreDPjrw20lpRgTtcJ7nozdorIU4UPfpMdxWxaWUbgeyX0QxDDyPfo7g0
+fLilkImNElyuq7uOH9Rcab80tdGKfwYy0WcW4x4yIwKhxGWH1VMWMNUQZmXcnjP6xNZyL0xCVKE
ew9rsKUiqjfy9FF/OCTrO4eQXxCmyFmqVD4gTCJzqPPcYHGWWfAcRztVpUQCMr7mcc7ISMg970D6
H884UJMAHz07KGtKyA1b4AxnHDYVfixtLqWrytltH/YpWEMoY1/Pq1rEYdlbXwOxOFU4TS+bUwxx
lOVBlG4DZhn3MlsT13eOduDQ2EF8DXqyn8ZHhPlcdqeblb2fZUTVr38pqXzQL8AU+Tm5oT/O+tfX
+1t6aij/rMW3l+pJEkwrw3sZhe+h4p9Dm4k1zrs9F+q1sYZq667QN1hlBjA/wdTZ+Aevo+9SEyDa
z1mk+sc/02S3Y+12hBBzeoWXztNqCAaye+MkDRMubD5PYmSgNfnDHUIEsxwEkEVn3+oOp/o0b2/T
Mc7ezpHzpPmajFX+z5c9/CrJNVa1So5E72FLjX44bCWX4Ppc2MSbGCBbwuNQc2mQ3OZXDbsUtmMz
sbtIRt4zYLJCNeKksdpHLHQ5l3PGVmi2PaG3elE5/RJM99eibsd81/vM87BbQcg+WUCjWcZgXFGW
Qv7nR+4RkWjd8Rz5dluJlc+99UQBKH1kW7mDPXrm5CadXafAfBaHY4BZzrYXePCM6uTbNrz+c1KP
P0CDNizptpCNWt3iqlQJOwwp3hpfT1ZSc5WMuT8INo7mic8n6uK8e1bo4qb5alNyCBnwYTVN6JC9
AZLqo4V9rrPJUHbvaqp46sFolrEcdOM+0BjbqH7CJopYMfQB7eQ8SPoQVW/n2K35c5QDUOxTkVIj
G7smzOBdoojQLeH4D9ktyBs737DcyfEMK8SF0WBhwOP2JVwxQRKpxJ3ce+2uTLUBm0QIQXvg9oN0
VkU6R0QTVGqA1aH0syfx09FfypdwYdYfucc8SkYmeBXva+bATKf9A60oPFPJnPWM9+LB0JxTAxdq
Wf9mwh3p+IDXRkpPpjj6Hpje9+VeRuIg5IV5j0mUlw9fqNGfCCK0OpC2xmagQtMbQWk+6gW6qtqG
aFeQjk350AExzl2T0Q86iF2wt2PvXj/qsrlHAqIQsN8zXNxQggGQ8R39fAJqv7lpXva25ZxStH/O
fcJ4/ZVAD/QJVQe5NodPMo/rB3hFyoqliBxeXd66ULJ/l0IpavYUxLaHwzWIFj6GxBLZgQTCr7rV
OXkE6Vq2nwFJ+qSJbBmrbHfbHfT5Fzq0yy2yHO80HzzFL4MGxnVESaCYwTSJg1vaq4Kik1L6RBNd
dCx5tcYf8zzQLYebpa39RIbAe/3BuVsDU4Sw1iikGgKyuRBmtpjQfejdBr9rJ4+ZT2UVpOWULTVK
jqRRv8GcEHTPuU808/sC8hUtKYPEZfRR2SaP5WtVaW7slcGiV3yG8Y2TxLZ6mowejGtYPqAM9b4r
2NGgnBGLlfhprwe56Tx/qS0ijvHNptC+FXBkwHFV+mBCyCIsNDDj26/IcGBZxeXWYNQPwJqCA9JC
7f09TQdmPvfnvK1WAF6Ose4ldWETWtsX0IFFO6mOt9Feuw4+rsG8TvLno/MAGWUTalIkGqjZOYog
jfBX6MeORZjBftVVWiiDNa/ZdJfMH+MVLQ/GrlsPePiVY8fg1sGNZ3m7EeCkrFjYaVW79uR1Ock5
4Me4mGcZJhgDOx+e1mpMMbQ6EmSuy6uwzbHIj2eUTPSBbtgIwItRztdkhe2hlj0kIZd/BgrCVv5v
7Yt4KgtIrxTvh2erbyWSArTtQAI6+xOwszH3GiiCQgu21+ii5L0RxyIweOlblbWYPsORe6wYqrgn
KGe5h0Aqwsmjpd8KkgjHgvrM/2vwe5iQGmaFmqF9p4p4X9LjMmc+wBbzdVs2mmwwNVBbQuqW7wvl
QFvrasUUkq5UFwptZDf1WzZu8LXy3hG7522UN1WG0lgTjf2nMHA3S04Sg7heex8gNjunnM4q85sD
tiyZBe0kjL/fyKlXtIxJZzqvamlYXgvYaBwX7fJHvvbmYuDEYz2kheaWgH/VrS3t7Z7ihkMXSit7
HwjeFIsCcZWvDfYfpK9Zyvrj4lj4eTPAZB7Ik3shKEFO0NWk1xcjFJV05UesPl5OgQQAkekI+JMO
3M8aeFSn/rUmhNh7Kj/EmovsgJGpz2C9rP+bPyU/rAiBigHwwAT2ZKkWF33ruoK0LEfwUUHu5lZV
oYlAXPUucY/63PzLtbWEhf48XrZQUrrIAzRLxh0hSFN4xkr2LTbD8EzdV7QnEJL+rkiY749LFozJ
Xo+QjpErSM3LZkqV1iUedsfjLQHvfg1BbrfNvUgeK/Ok703Lv+s32tPPtNvLV1ZeCNb8Fq/xRWBn
exBu7T5ZJ3nzvvHtbzocKUKVN93QM3Few8EUCHnmIztsH732KyN3YCH/n717nczpyrSyNc0d1oEI
3QYrO0Du0rJXg4Febg4FXJ/7KKVWrRDMV+L4tp2wWPndcPqcpZrAxFNrCYFhjoqvS4rC8Pd9NAOF
VrW3h9PijFBPhZxpweMtmH+TunvuGLBcT9PGR27tYUsFxJ+3zuT9y3qWdHVY+yaw9/c6I546brbv
qLfP36Ti45xRM0WDcAmwCsJPEVkSs6iPxrchZNVmcBS1gkIXOrLnkpehNn2shhpRFzyyOB1VdW/G
kXB8U2BtMQF98QrWKL2MG3betExUqM3EiLPxa2g6N9oedbz7sFfSX7EfpWEAzAeSBAwJFLoCuNhm
W5FRpWTaW8M4/dzYXopCCeEYTQ1zf+K3hWhSWn+NHGraRx3CWjeM/7vD8Op8e25UsnxyKCQ60gYp
4+RwFGpvd1e6T8eMFvCM39neReyet+EAvbppUBUFvSHjg1JcJk09iMduW+n5u26JZAxb5X0Fqi5s
8DNfwuV/DR4CqsNV/3vZyqNI0k/VhTvM5glktt2nsj/cH5HnJySII5Qnm+U/5v/LwruQwOdun9un
SoHyqBZsJ63GND/c64tp6tyCkTRhJ6JGbMdu5PIPOvH/pFWOpXR2PwTr2LiUiFeLC+9VLC6Cou4H
OsWIsysZ/GDDwPGAUtSYqNsG4ZzDKlzL6J2O9Gpblm7VG6MqTb54IHBdWrhqfe4C5jhcyKEILthg
ZeLlRN2zXZ943gugLT23G2+t9Hd4UL0flBye4KbDb6v3m+reVrip6XtHmzgyVI50X0irJE6TXRPJ
K+xNL32IQQDI2qPP+a52qNiUzC73cumYmcZX6dKBy2l6s9dJFl0Z6Rn4AvAm6Dd16QvSsb7tY3vH
P0UIQ1lm3v+hVZL8DSMw2etp8CfD/q5lElCx6H3VXGAtUKm7UWBq/0TysPHzj67chYsfx1ABeKX7
710DntoXtnF1tI0lr2RznCVOlxHTeHW4tKeVAsLXCSeKguj2exkplCfVL7cUSDt9O4DgYYdCqUyF
pnoXZmYQu5Vw9rwhbxqCGAjAgDf19pnfDSbIyJxJEupYFfgho2P0uqUNibNmXG5gWTktDZ37JeKZ
HUdAX8gCbeV/iWoNEmlNRbkqJIrlO2uzFtOO0L+3+lUOI+oH44hDzFsaXZ/nbERDY97kwSaUYC9E
CQcomdRbK7qXTTDRorQlQs9MM8UZYsucnz1zVfIGInH94Ts/xbwmf/3qneA7Z9W5Xq8KLa0TEaDZ
mz7Ht9EJCmDwT49U2VBIHvNYISwSZ4N4MPkhGt01n0Kf/5ow8OOu6OJQUvD7s6bLrJsuPvJMpVCQ
L5lgk0gdu6cv/a4KNS9mdKDX0NQLrVgRV8c0tHXznr6gWFWf0XzfEH6LA602uOhv5ayznugh12/9
UYfbxffZNZ6W1l1cGFtitLn62tRptW8FIgWPvEox9NLDV8El1YBAQHkpDgayHQyZNkhJb/8yxG1U
OZ9AsUzdRUZ1uxVI8vXzCY8ewutkk/JK6fvK8vwTNFBLJ3GGGhe5BXOFt0mdICPH1r0+fQd0VLWd
dPgqYOhXbQVIhXkoZsn/JQICCVLkK8ul3ei22lQwZCNT8vbUcXxEuJvapoCuMpAOQ5SnETinuev+
qyYAFvdN9eZ8JGOIGFPD8GylXuN6Ugg8whKWuEVtRTzvX6C5ILZet4IT6apQllFz1b7pbphplAJB
EA61SZzvUUl/BN4fpr+PRpi07bZOUs7PS/5hk7xdedRxLLm/P2qsL/+evqgVJJx+C1cMkhh+IIym
l3C6GwkWuvzUdmPgDQxresBOK62k01ybgLDjN8BGv2XhWjxuSYFhilctyP6KGIHYr8gG9aKpwWhe
fzAtIA1Le+911sdDTaAq3kw8bbi5Wp4I/DB4YMGunvAcnZRVYiVdpORWh0f08uGjRHYTk7J/pCwl
kq5WItgeyon0gYE6nrWd8LM3fqWapOAygrOaCFUtiFMDXs3n4Hxff3QMhEhJagny0/n7Yp0LmviO
VkOn3UAtVlfeWtGnxLb6DFUe/jhPKXZFMdFzFVVlgCpfaP2cB68IyPtyOT5paYtRJYHEVb15y538
HzFAXJs+z1BP+6SAEUfcjBnf3lRizLvzaz4fOGitLPV4+2kD1MevmpcrZya9vqJ/5wyLZyhh1AdQ
0r5dvbc3tjCKnZlxAV93NTFWlB7FV3Kg7nXVedkFL4dKHzmZcZt7u4Nr1YRqxkK5lAimAViTNj+l
7VS5XcIybnL663/N8utFM1RtpwiOq6n9wwRDw97dLr70f7xUFE8aZIYAUxoHf0gngnf7m2+TlFCG
RoAa+vEze7VzH/FAhFP0bulY3S/zsS4CDPo/4B7hC1aQ8yuiAt/k6SoQNVhL2L4sQrZ7U9I5a/8x
YcUqVqQ0dhyBRKnNGnpVnQvelmyMskYMhrfeT63jhf+Qrv/l7fYcHOsdUU8HgxpBZjoRxU2Ibs1k
5Cn8Dt9CNjlNZZg+8VGFc8b/kZWh1LVj5zLzdvDv2v4AmMXLTxr1ZSUzza1fIq042VX76vpZC36B
5QZ+rQZ0ManqSW8gkUclWJrdoPn2L4HlWTynF7LdHAC7JriZdLjXqY4TBVte0qJv/npEutDwL3SD
DCHpOVcCi5brZF/RXCGb+/qNAx9lJN08hyEg1XcjbXePCXk0Os9ihJoPPeuY+eWeIZrLBSsF9TNe
jsu8s+fwK7dNIpG58uBj5Ym7zKX4LR8hcRvuyU5RDTaDdQp2bWokz0ia4IpkcwKX5GUXwWeqna+T
k40VXrkterJdFCidnZ/ZiQ28n9fLpTQmLYMGn2pFmwbco6vsgfjLvxK/eyOA17moF7CIzo7xplPz
yH4+ssQDdZlk/0jkOuh2xJ56wGTj0s4mJLc47QoSPgnQJJZqtreesJqhVEAKFGVHbuOVqBYe6MpV
g5dOBGyTOWBGnE0nbNVeZ5g+Q2HN76Mx6e40pX3lpT+QtmqhACOr9RaI2VIv9FSbsTfSktcYUrcc
JffaUwylqmRG9XJfFS1khA2FuP1jRoL0BqHPDW9I1mM8ik5mLbwSt9lSXgugKfRF1boJO5dakHKA
4ZZ7y5xxSRctYaHN9duWv0UPISVg8GndAMeQ4tluppGv7wW232OhkpYvKKP2Nt5H1pjKLTLov7nj
na+V3PhtXY80WQs49z+hkzIxYj8MJdbKIbwwxJlhootTethPJBimxoclhpJQO3p3gjvixfupxWbI
znPhCnu+HkNBTkycYcC8fP2KyiHo6QLx4LfBKqoGRAb1p5F8Xk9WoqjMOAsFiNm4JVmn5ZFzBsFj
P9kHiIerw/cqmSMUZFi19/vCnJSt7mNY6OKJmRTILoDEvojvxqwa+FEpMV1c1hFo93/k+QChlllf
W8NjuHDlpj4to95nH9glrPAPXqFGnTUEptOaaDDaD8yvUt0vkffEmiWahy6CPmzVJ+q5hnFWh/gn
QiTTekIheylfkzA9+yiBq2/VEf1Dxbzt78HXU3nhRq09VAZfcyj6b2jT5mT0k+EuOv3eWLRiviiQ
nmoPzhLfHcYPE3j6RpvsYk0jK+iStN7Bf8sUjASSK779+tcml3jQHhRVWXy0cstw93dJaUyhfcRQ
8UJan2b6ZZPwm/POgfq7WdFN6/771GSC+5w084SARIhXWpFzFFz/8c6bW3hURFcsYmC3hQP+JTdf
fjfS1NEUQYIUY1hbok/5jaxu3xR3Ih3xCXtCutuS8h08ZbEslXcSZURGvR/LBpQw6qQljfJioBlL
ZeRmr5uYt80qCjmNiw9xUIYSNXKymRyESx4Y9F3GJrR+438OoyTDbqZ4JHR6zM9Eh6PLZYuAv//d
ew5MGLUSP1Gl32i1B/WUS21waj3UqqP4urKCb99LudzFqDd9o9OxDd35oFUxzk48CUamMCzRAnbg
3eLygiINgLoUdO4PVLwxEeXrIMKc5uoo6WymtXhWKPKatCbEHwJ8lU5bWc7iSDkTKTCLy3mKbe4w
ZhOOXIwN2zID988QR2ZxzjJpTaXTMVsOD0TZY5sCdue7OC9wDErUlyQZmE+Uagkyy8WsIcJy1CI2
DfbS6NdnqHmEDc+0KsySwQloog55vHIAq+uvKrrtzXuK6Jibau7Bqy1Po2eq69Jsg6iHXnB3ciMy
pLZmbDE4g6KFTfNy5D37uCTF7xskGm5gjp5xqSbx3zixH/DWskjY9FUudP3EytnSsdSYwhKy3drv
H7RsjDaO2Ntm4B/O38zKyKftaS+RXm9rsA3WjTKeJ+MyAHWlS3UYI4SJ/LtoT8t8C/JUwWtlFwQa
PPY6il9bZXs8Aw5L1GYM1f0kqhgLKrjq+rYIVu8xxaa4qtKVgV8e7WJgMYA0EV/f7xO5kEirbUhX
9E6OpQV1D1nsuVMQAnquDXlhUHfMoHAMm2io+O++GFESciHGoJPwlRNsyYn+7uTj53mTMwHmC+Cl
1my3+68ybatlJ9xPjLByQnJn+DKhQ8pwqml/gLOb+AkzxEW69azMbm2LcbjGotaC/5rPAAxMH2Gq
qNlCPoWmZ97NmkSOjBPCkVLs75SByhVjmCsowGmHaIbYTQz9RMPUjZjFZ0x3zVgJ1OcPs7YpGWhS
kCo3/JdHzzqc7yg7YhhXC6kKi+siPAIDNg7SLr02IlCjriSQLLjYHbAtOeYgj/I2vk4eXCZvhTzL
sRTdTsMn9U19gcnP6W0ldzC3P3KVqOx7UcHY671tOMZxJPZvBGQIoH8thQeHNT3Ux8WCSOMWIOC6
Jf27sMRyMimN8eiRlIAzqtNLksDBH0YeP49iUeCDNnmdtRgSqbChZvhbULsJbOmePd3qUqXHHGYI
ZeZrEfMLYqA4Q74FB2/YC8oBp3CPAPHn2BoCJnjioAI6onGReITzC6wvgEssfuQ0yQBXrUUQRKin
qSWWHegOvQK5VZpTLIVEvHv6HKGfzGO8XzzwCE1Ud1m/VluD34P/3bpgUMbbKVZkDTuXxmFzSEGd
myFVtqtZ6iES2Nm4rw/LnCANvfQWxh4/SMpjlSGw8IZ55BCrXH63ebar2BCH+2Uz6wZfrkJklv/u
uXGjkfkL+tO5xChBpYIZcOnlDyFlkbunVr670wi718oqr8XCB2sMfpzoSuMXXbsONYyX+iI30MIz
FHPCfWQJ/j8vStOphqgRRMUJbjoGDC6sktZrDXDIl3bNY69TlouPdzvnqt6VCNsjXuhsWiw844po
4gEeQ72LnKbV2I5CN5JRVaQ/9iMZqeF+V2F57kDj43/kys2HDPLlfF4VNe4EBeTnjlEZ/YMpqtEM
0PS8BjHbbFi23SLfgUz4X69XPfLDNVpN+UEY6nTXr4jg8083egx5myHzVAHNDdgd4l3U68A20D69
EU2UxEAsgoSZRgnr1Wn/ihBVu5Yp0bfpASTirhVxP0jMfBHA140mOGxfb+q/eVIRLJgh4Pk9i+/z
yvF4asksHgqdjB2hp4hnYQQY31dVyFl4cg5rVGX+X8BZYO/VLnTTJtEcB+EGILkI7jv7uyfnQlqK
LV9hHQuziOnOj+KO4qPdjCfPhDd5JnNzM9WLiM8MWmWjPzsPANG1PJD7wgbo0gA81AhQKPoh8vxH
1dj4DairdIpPzCz90i4zarzLLa4Fq58XBe3cxr8UpNMsU+KRjyxpKaKNYqMnEliti/vHx2Z6WogA
Z1kIXqUkrDF+lsvXBpTyZhRs1+Bwo6EXNLgH1y6znMCySbUOW0q/uDHzLVeFABuiknJY7urAkrT2
xfJnht37bVbKe5ZVqmQuyNQ9crxgN0eUoLaJxabx3oF2OFrcU92OD2TCwx3sZIOaQP4riuZT8KQJ
zG2jN22RrheBl/TOVQCV/ezdy4s8ecSrVJpQsWmw+vGx0Ek9t/uyHKqA2QtYJK2DBj7RGGm5A7xy
E76BAGUwAv6+f+AzB0qipuTk4jzcOfGCHlZb5Uq143PsuFb0z1bLTM7BBObnPk+fTJ7o79Qgidcw
cnCKgbl2UCCPUQ7HyalgusX3+AaktueLdKubXLWTvJk9Y5OVQhIG5ELGBAb31rKoSRdCgY341rYb
ysbH9d//MX2QvcymSMleRG3icqWqAlubBZdvW7drDgUzjGSHDNGSfZMyU6eS8RalhVV7FL8y3RvN
SwRtWlabX9BiKS+GpPOu6k+6abE8RWpu6LDgPJ7VFO4rKM+rhfW1DpOm93DqDJA/DvwyUHWEsdwB
bE6eSMMfEOXOhY5otf4uSb08WcFdCpN4Sm+ohJlHkkqs9C+WTHQXqoQUYjLYNrufeHQg/EE52p18
dcrx0rrIswRUJuOIrtvvRTH0Kmx9635hg7wiz7+dfCOyIGMXwcr5sWPM2h7V1OIhneVldgLCMLoM
RX4ubAjePU6XaK203TBcrVzmh+4m0x6ClCFyMevyksyjlvKxi2NiurisdHa5uonLaMCchrSnTRfS
8Pyl16ACzW/YpKUFJvyAZM/391hObwA3U7UVeKR20bVQg7JZEGijBvat+7ly1O7OV3IOJTcZWmjK
eTdFofzZ7eYgb2cJ5ZElKA8GSqWIaQjVK2pQbHj0j1WV4O6JXqETbhyWJnSQBwVBu4YZiOh1ryVn
kl9wsCdQX31ghD5GmZ9FZzAUYYwHq9tybYHwG1b7VnWNKaT74LIJdcJ9EhDx6mVX/8fJyA+c+6sA
UTFk8AlHaksuHPInUE6/MIQCiOYW2uqkkTt9xt5dVav32x8JIe1W+hbyMi2tgxRD2EHFGMP7gWye
ByeOcuB2+xyq2veGU49PUHqmHyF2/f+sFIeP9grgYJ4AArT8wpXuhQI9fTa3pzucMwXXoxPpGQlY
/pXAQKePWP5G7DVyrQeZrEgTn59B/Gja+BOA2iECvVZrV8XEiJr/HwdYj7Aucu1fkrmKHmc28Ysh
L5k/RrJGpN8gDaAUc8ChuY5jP+1MqRmOAGgohXNn6EWP5KGdzUGBtAzCKTPqUguNsGPA4O5GBgFn
3dY+/5NBC5Lz8syZ8hn33jDqL2uP9Fx10Hsnhzs0xQlkytpy7lfV5QRzJBvZRTIUgrPa8PAjCnsi
SyOdC1ZTAwLoN9RRfAUwjz/zOsdxEvar+0/PuHja6ta5HcPzb/EwrR0d2DT0Rh9TCOy3EBkKnuC/
zAoeaTNWUr5NO+vetIWlV8THVw8WijWL37SXigkNIq4aNHhACrOoQmLMG2R+qgo83kfqSMadPfZR
JTwMw47Kjcz4Tqqo5liwwx8xQ2rmyvL96sifmYaak3GaI8+ger5PXZAI51xLu3DTe99T8kb6isSG
DOZqA+53gKYRzswqhw80b0ONWuWmkKLpRCLQ0WTE4+0clF/dC/CafKC1xxvXgA2UeQ5wGxNz89ji
y8zB7DEnDbDee+1tZlpUDp15kx8U+eBDVvH9a8M2yuvosyaZbo+6u3dABmW0UX6XWETYROoupUOC
WwRgqM6GoY6w8Lv1Ki7FSkytSUDhY+EINBdDS1AFIlodX5wdHePGt6MSEoJrXJfTnrj8TrJsREdj
Zi8xNanp/GHsJeqnz5sffYYA2k/OpGdI3NZ+WUGB4saTMky3siWc49F475jxJsbXGKUbmcbrztMP
EtYEiXqXTGHlyIQsIT0kjRo8emma24uaKdtJm9RRJ55GyHFU6ZLZ+rNefAJwZmdZQqAAyrsSNYWY
1TV77kWGXYHeUoUm+RfeiFmG8MXHtrfmfwqAjpmlE8LHGvk8NLQbdVJHel0uOp5bQBcZa8cWJrP5
HhNjcRCAyDRHVy3BSdaDXNaykyNzu1kutDBs48BvF60Y75IiDmElVplKdYymfg5dB+CqQXiR9Z3D
1bvlj6muxOrdZAzGxv9ParCuupSbuSmMG7F5v0zKfgKeZx/SQGMQadXZsYY0O6o1VUj1CK52FhL3
DWoY88UAroEE9NgFGGpVuA5ALA5NnD7oMmtzcWYemr5jjiEflbYYItxxkfDtN5uFjOY2ssN9gUYV
LI04raekh8lFDdSydM6Y6fqSnUO7eYKAmdhcOIY15IlFFoBh0KUQAh/VeBt+eDxLM/8gnVTkntQR
ujo/xpt7ccXBiaoghQnZz/lp2V4wW1XwUAerFyyZIT6vdxdO6f6trOt2mc+wzW3LpXzdZ2HCaFZY
ncZwhxX2HaVSQUUPRRDxy6GNGt/s4hR98/umk0acfKEVel2lgIgMONTeoJ3+n8WexI5mx0dcvf69
2FsSqcyP+U9VMw+K7d2bnMHJ504hgyqraka5TXrt4KSuMNsykItI0QIMDccHKze2b12Ze40s8JBR
ZFKI9ezq6bYWVFAfrEdg71/LlGYbp5OlCFow9NU4fFd+lKYXOMDOt5+voq1B0pnwzwB9vKnerqxz
C+TC+eMhdWXu2LiebX4JX009+pfKRF+lkwaGGh+chwb8EpEf2Ch0dxlyuG2ZhMeXCAT+CvFgNHZ5
Izs1cMaSjSLW8cnD76p9SIfyD6U3+9bVgRqGxXGfRPv2oWLUoJgWDfpeZod2N84tmJDdnP+fZtlK
i3SKFZGpzXjYEqJqjJegSRnnmgOPJk3W2hE69Iwjy44IUuF3zN+Is6vi7KDMZuJv9537hmgIGcME
9ZwNQ535tVU9yk1AXFk2x352TgEBNezrXZMFnFGeWGFKKux+oNAftYsUg/m/3//u6Ekum5xQT2z6
UP891W6Ven6ealHM5/noDErA7Q2zkEEpRsMJpyOCLTEkDqgbIHL+gVnuNWZByhYiLgvU8YeKy7Sk
s2YKNXVynHnzx7t3KulfIKfoJD0olQxJtQ0QkAb61moNTq2eMckE4Hpw0y2OXTdAGRMdWgaVTXzu
2wHCOghfQg4hgLth1l8WgWXF4cw2Bk1QhYc25sFXPUMsFBwpsC1lY12LU1l972uCa/hoh6MUfJoS
kmflKeu50leMteVR6+QJ0tvQYFZSOwDGGnoXSwURCWicRImU4Ci0vonLvwgPdwOYaCDsYFo0PoFQ
cRlG1YauyAVSNGA5heCjBXUgUDZ+6WZgI2PvH4hhelZRqkSgiiFjf4mtf5wc8pcgwsKlHODuRGLP
HwzykcxvEeMhOifC3CRPQmPDHnGz+vHGXcIVxHbVdlBenGCZxW8Y/Uiqd7H7RLNfLtKK1ZIU7VXR
qKEMMjgoCc+mLL4+BF0dqt90yUM62ptJGunaj1NCFTP9sXRG/8sgaNEwBVR9QcGLBkof+oBb5dEA
XaeZ8hUZn2wlCtMU/uxNeHDepGOQavp6TdKgGwhcd995LhCO7Mg1+97/MCgGCRY5R+Tr5BUKdkOh
QKDOJBOdScVaw71fHwDB7E6Ido35ZiEKxazfKonFIVPZ6G66+z4SAAsFMZBsSf1XCx+6LNJ+OVnD
hVUwOvAAJzEOz2uoPYOeEiqSgayB4F/QG+y4BKM6vbSy5y7LPCTuXlXXkfsBFyDDcWHddoMopITe
2vlwbFrUmuA27u6I43HtvIbZ8wk6QpWDeqzytY6k2IvLnQx+JNdPLosShhPdU+k1DKnm7t3xJ1PN
nzV2l2Iat9wrSQ8vHQypyapKXEoEvXHtf9kkbUu3adn44O2Iqw5+Heit6/QdbpbJqRPkHKXqre6X
UnN52T+U1Tll3jmja5Flxwiuf796I4ekd2UlNGVoSHH7JtbanI6SoUKrkAuMxFgORJB+Rf9JNuBi
ZWVUjRxzESypbqq3W2TOuPtyRxt38G8Wzk9d/bOCuOecLcAym36afe+XjCwhx9U2tejacl2wx7gQ
dSvLmuexjGkwrdl90aoS+uUmF7e1rBJFa5CXxN+hpRSOcWbrCvzATavUb+1AwJqwn+lPTOD5/iMB
WqL7ewzpH+i7s3wzQu4LSspnqY0PPjCakW9UE5ll0sSTybqfICaSGVIAXvBGvmGy1/ydUlE5X05T
PpbBRu3Luj2qZPTXnuKOR0ihA2xcjVQu4nn3QFVPW56x0de8N1yHSmzG0ZJnZkHaihpBNUZLgVhT
PPqKWUz+CbJHhIXIc8n11LvM1yOkJ4m+VyfM81pexjWNIoVTuq1Aztgq74VUecmYd/Vc5HpICOhJ
QiXISycTraKtqSWuELPlnWuJ9tAxZvMjHZLJP8mQt69ro0dbV63fJKWegZaJI+AE/4eNheKyyamW
hl1y1id+2izHoL6KnUI0uCOELwIvICZsmwbT/Exa8LAVjhKTN6/gbOtE7bRcS02CldDoPD+dEpoy
1H49BtGe2JsRm6yWaWejrHy1/zc6LNdSbLJ7jy2V6GuX4cN+geF9IeKzplKiHGovpKkhQ4RqwzZ8
g2jPM/UUO/wL3Rqa8DRMlM2oYpmfEXzo3gM/BIVgaOcblcZ2iYikbIDfZOJmwUHW8X1yFckpt0r/
Bn5tJaKoNW6o/ifkSloiuxl0fIxgL8d4LXchtsvLWIv2sM4PkMTGfO+GzL2W9XKS/r2RCxO3HDOi
8KfW1ghTpdNuC1PEXaJM4f6ktvkxZci2OmNEVtVBBGTgmPNlcw8v1BXqUEZmkkxjGbFKv39nIZMQ
/kulXxOnBdA4g6NqJ+76y2Ad147ewGtqG2dcG2QipY297e0vN4FntWz0lUj6GuFt5JCXGRBStBPa
yF9ndEe1aIuDNrqi3HGU/IPTUCcZ0bc8p6H1t9mapBL8VWqn0ayhgbRvQ6xH48WA7qJILY2HPjos
J6klu2oewP3Sd/HhXSDGiuAtXpxaVi8jvPHjqyo7sPiddhwYQKNEPT4SxHRjgLhjTcTgwebrD5sN
HGzPt7+QDh17bpvL/Slq8VHKURmpXkrMSVnkyBbl/0vh5ck2H/NvidllZxx9GhGUMV69E2rM10tS
aqWH5hfVpK5Cht9Wusn4W/SBS65LH6KoGRvwTk0tTv3mXJYrvdwm8QVvKNWpswPpGHy5UMK5D157
YkAsOshS98tEASiPRTHkr5PQEJ/rPA2dx2gScIFX2PZwLOGuVK5V31+v2BRhnFlNG8ZMCr/ciLIN
S+9dLt90ipx4n/IM8TqpMs0F7GORmnrzV33yRhrJYrK2Ug4QZa5h9ZXbiCfAeac9MrwQlxv1dwnU
Uk12PKEjeaYxdd2OGB6Dijw3CKAwUZvOvixE24Tp8cVtqD197/Iu/qPPCuPyjrQDo08RoboImvnr
8mil2jZY/mhwL3E3N66RURBVUkW0YpXc4L826Rv+HVUn9b6xJ8PRhwkpIXol5BtyaSBdyaLD8gdu
o6ypF1Cd60/lV16dFAv7DzBFLSnhVQQqUi1uqw+9P+0Q19Kl722/qyhCj//Xu+lg1H/SIRSz3NWX
p6/JQNUMYCLjizYWMWhdY5Hg9mZi95elyma3RY3QsCYXjlxVp74PWzUhB2NX+7ZNBzCLV/VNl1Fs
PhnghtOCb+Iu6c+q6KjS7pk7Qczy4XHMKcvpsbU/4epSDknupcYupuX2ouNFGY8lvVPNyM0xxsXy
krioJzQ6/1KPZBXaoLnmzZvC7IXlthHCDkWfK6i46lq/tTMT93JW1kJyRMkcKoQQjUtENWlMt1IB
EwVu2KCEA3Ot1lnqZoeAgbZGrnXvNMOsZWVUtMqGjuJhFY1E82JBuK3VlnCfQbnmtfyof9xVKJu/
10RGpe4hqGlbSIwSUtsMtsXNYkB1mnFspMw0WJrTYJDNONBG1kXLgrJY4NRfhWgM/fDYSNHiKGca
mSS9WmMM2Qp54zz17Ak9afz+138SU+dEMp1gyfiT/PNskWyV3ezvGaYD0Q4bbhOslplMAYmSHYjT
U0+1sEn0FszEEkSacSsrTX5hjHEKCmxQfNqDUqzMfM61ylp43Fwu2IFBDZ1PWIhB4tNUxWFv6XEh
T0VqYQyEFHeK7QOBpTZD/0EasZiyF9Xr0d2BFyejXfBP3En5p0HWAVc9/RoGugJ2Gwx8QHCHosyK
tvcCwFJMRY4CI+8aZPd9dnKuA/cweRV63BzduPOjSgfQYP+1AVB9SWbPRUhv9nC2cV7nrIZgRh2I
NnkFb36G2puHzaVQdCwNtWSoCjFrJirUSRtkKYdO3DappiHiCxpkl94bq3NfUipwQLpLPvZE6AD1
DIGjuvN3m+aTVKpyfC+Hx2BObPAy44R2cuFK2xnzmdOBMO991HBPPCrX8rQ5s98yRp51Fi0KFpfN
J6rmnsRKPU3RToDbfHVZZGUrZ071PbimJYfIxMVyt/h8Nz0X7rDaRa1qjrp6VcXpu34rJqjPEdX5
ORku7f1jLsLTxvhG+1whN5rKHLBMtq50U7CmmSPBDKzUsx1mEo7MO9wStC4fBkQ29judr1HbBHTs
Ycdb+EAAQGfP8+ScX0hsUCTuDy++y8NDvTIAL0LzMCWF+cl6xwltKhlkzYkW8ItveAi4na51l3YG
PLcQ4W4s4cQ+IC0TJ17HQ88yKKJ0v0t+03F4f9aGJonWs7Caz8OIe31GXtaahc4Srwz/gWOjMZjH
YB/gk9EnoDk0dZWOm+jzU3NPNVyCeK8n7Nb/8vWzygkHLkL0JEQx5juLwAKJZZ1H3YmEbSGWS8Lg
6na8Fg2T+XK8XTlhJUwx7qYh7qePkg955L4iNKf86/pcGQhhFhdiWjnP9lGVei0LBt7K3Dini5Wk
T2XvIm9vGQYswK1I6htJ1wUbLGSWC17Y/B+8Fol27hbz2xLSBmOms4Q/OcQ7nb4BOn1Pugjpdxhs
ZftHh9vIpMOw/d256AVECoYzwOQbN0NlYSSbZ2UoKdKn2Ijjz9I1m/YenxKtbkozIwyq/W7A0AxS
rdOAJWmMLEW4rb5IEKjLrbtwLfghpr7RL181/QJgeN23YBrrvifAx3ffCvX3iZ0M2bL9EYDR2+Ne
b3riP0VmJCgQJsUjF3LcV9wPy4pgNARgrLaZuPLoG3CaYNJ1BVmv6t8GatRD8i5M/5tfG4Qq2Vep
0Tu9/1NXP3m4QbvPXf9Kp4o203EYAzGPh3dIV8x1jekKtM33izwVZrYHq9b36mEGHz4KLQCB+kpk
xVUyy3RywwvsVd4kfcE39c5zevYWrslJ9N+lHmei7O1FIclwsyX+Z1mRxKaklkE18h5Yp5SJXu4l
c5vM1rUmesRb1jn/KRbYnU7UdR7GDH660plRdxcO71ckaRjftR329IGxwUuORZqeVWNtMulKnfbF
5KQuXQpF5PzoPm0w4j+fifvs5yAiOfKweRVj05d7zrFjNJu/NZ/6WW+c1+YB6CxevGvhgh3doZZk
rwDvt6SSATLFDoXLqwCxvLRyb95G7Xg5yDkrLz6HgBJVAlooGw9na4/LxRP8GgrVq0SU/Wf8Ypqu
oL/2ww6DqMnqnpMiUaTKYj6YgT6IC9O+xuyJlfYb2T0g1I3LNw2n8xogyOL3lVVrUbpEUWFO5X2D
LelzvOvJoH9yRrogiRYdwGXQ4v2UrTEPW7JaiiMGwMrU2ygCqj8ojpMKLitJ+8ONdzO5/VC+ETxW
VU4cwQMtIlnxmfo9ZnJAJkkUkspWIcDzdu55s+GScCLFRMdf93W8KpmYsp9izS2uoCh8O8xcbhe5
/VIAG9e6hTy4HRLBNNY409ONqHxoSfbxfAQgVQiYxa0EI7SxoYtPdCy0fEIyfNe17vx/4PMkadYU
VOEtU6OFSwE0NWFoQThOhFs8AHR6j0KHY7Icbguu4hoIa/TiTgnl7/KYOKOkegWARJ612GvL2C86
Sems0RKPEqHiLRGevM34oFiDvWCfovpzaxrZ5e/LsEeF1GtCd4q0PB1yY+0UUaeiP5k6r0UdpQnX
TTOi3CjsRyhOYzlbguE+mL63fa8smrSkl7434t6ZYWjXnJ6HuKr0zoBn/uGtwVsR+sCbVL4mIgQ/
fzwzFTBhunmm1zzXzrRFSRFNDhxANbETjYynGJBP8XZH/O0Wo4NZ+oFFHnDL5XpbVNImNrXhX3Iv
Jnv+/cEvwxJP/FILzSE1txv4Y8vVJYKYrCvd0wY9QX97uA6IEd5cqzckIdUDrSBAtzOsNjONICP+
AvKbC+WM8iQMdH1qiVhlB0cDvwJT9OY4f7iL4jO1UmMq3dTObjS95egjRXEnX/lYfsi1KhyVD/Fh
U9O1jG3Ktj4I9rDb936JUoFaNkLWlLj8Ft9k4b+M/JVZdJC1dBt5PHzCAyRdgB5YI9C6IEgJb6DZ
OE8ewQaaxPLpS5Sxl40tUYdtLh3a4i805eJMbq7LgpByZeh5kmPbEVUWxI7mprrg6qpuUeR5JhAN
qB8JdMrbF6qi9WWqCXd3hRIn4xFaCpQ9myFF7kyWb9o/ZsOWLqeaox7jHdyT8qVRtF20nLaPEV8+
Wl0kEmdgAJPuVkc0fpRLZMk+qMwXusFNBRHVbO7JDuozKX8LIN4fzYzgsr/GqTeH5Jzk9Z9tz9h7
e7DcVeeXZjEMbfUlKN4RqFqac/iR9aroHfmkqz7JWVVqf6xDo6VMdseepVGLUOC4CV9knM6+gTVf
HauhApfFi+AnllP0O3ax6SYhHHB3xeOD4o2V8GboiYIopo7cKboZGgVtM9s5puacxuBgTfkpyOk5
bEMstG8WcCkgcx6hvUmlHypVWuk9yN0WVYCKnvmGQhpDBr2QgZ12J8P/Kn1KkJ7Qu09U9NL4J7LU
knfnRG2lspfydhvrtK2/oy/qrQad0R8p/Eivdl9GD95Mm3ScEU7W2uvNYRdkz55KYyC4KFx2WM9g
IFInc0Qi8dAaIgbDOcEyUxSgEwEMOB/hgXp7p9GlGaFoNCHjuUCavCxVK77mKyzHgHpJkirAnHim
RQLOFt1TpUcc59/+lvIgPnBILJVGQmggKD7XscSVcRNK2+5qj8zy4cJkqEJqByh08Z95Zh3Uo1+p
kvce91kNbHJ3OEw8fANACfTICJNlSwR9mCHSKgY7CIhz9O6KOIojvmPP07vobUMNTQYNpeO9SnMy
vwLVGWYfJKACQjGdFS+CS5RMRlTNJXrO7pO+w/ZvFIoIHBs3Q1V5sgTL8mprCSrFCluiPg+KvCBU
T55C2h0YLmmS07i9etE397dQNvTHWVYFj90+QFd/ODbcrivBeyqEgAItHgl4lN+TkpvTSRTkTQ7a
bfb7/8KtMy/f5cwzg5wAwfJAgP7TADCN/044ggp8WxR5UpuNP3fMuGqApezwQZrWliz6c5MJa7T/
YspFIwJMnsQXCed27Apd8u1qw92BHtN8p1EUlvl7wWQrhV1AR/BWhYZl06WoWiP6e4aTuM5ADGO6
Jtj1df5+fgpBYsGOFhGcUVaadckE5fd1rwbV96xrCxa21S6bNJtfsN94Pv5BsiBwWb9Ew+JkhL4F
rDZhf+1g61SVsnES+eCofN6C5DYwewfU8vSGRbVUwhu0WdU8T+M9VxWpVN3LpJqDqTVPtnAheCuQ
RaZwUWf8m1uRO7ISH/tbVnjBZyu/2SJJsOQNx4Neyyl0pZhKKA2feeC+Bd5aseXtZH1FVH5FCjqK
aWaNZ7aH1MJagUFnVO/hmDvH/MwMr0Gd4Aw6ezLCKLfOCTKJtEIMng3TUhkG1njSDSFM8IpKGHw2
BVTkqWhmA3jvNURY1pUeXNa2CT/RFlGu67ke1a5QzEt6pGuVhgnOWqrgkZcJJzd/MLOKmWgBFE+Q
u6+mCHip50Hzfmouw21m4ucOuUM85FjjVJ8Ir5BjdjZnC3245QxhcRVRQORrYoPMm3F32GKYF4TP
tIDfxCUJcgb5y7UoqY0/HsDlsoW4YrDo7smWkVkP6IvSoqJoAQpojNsPGQWblQas3qB85TuodAJT
ve75XqLHi4IQoSDMYZ6MnW9w0Vvc6LPcTBfPxW5rVkJw07FMqXEdEpVfv5CTsS2qm3B/qO73cgln
Cwewx6aCPgkmR/I0pG2IuvELsVO/GUDyiQe+hi8RVn67aVPR0X5X32Y+mdQ3u1GP35rvjwyMm+Hj
JH2eIaURA2lEGh0+XXds43zTG7IIQGw2tMLHcVAwBF0HhJ5u7f/ky+KIfoVl967JadFq8oT2623i
2OPGpR2Ot4kgVrS0dYT7VH5To9JjOLWg1AdmSP+M7kJUFqulCcGORslQmcdjeCcVmEsy1uOTphW6
t0hlDsjId+RMn636MibYGOoRYXZ5T5Viq34atAtlxzx17ADIhYhIy0PXOp1D3LSIXjD3IOQgZXs6
SGwN/zp3xplmMzKZmw1R5btM2b1W9aP/rSEQAx5RUi0fJH5BrtnpGpHfrRhyP7Ub9865ahGZ8AY6
ULRZaatdFxC1wp+oACWPDK442mZ3R9iuafEys3o5NaqWkFdt9v2keZcFTZ8DF4pGLpm9hjRBiIrC
OTZ0tG0crJ6BmilxLvpIFFOX4FoFjzV+bTZHbv9XcT+8vsEqPurS7ev4HsvXCoHJl6FKcSTn1u0S
f3T8pOEXEPblyYrFwhhpPtOP1mndaNFKeCYw5EfbuDxqe5XEaxrAi2y/D//S0Q71cnqXpJgQXJ9Q
M8d+YHaG2FAIl24w9oK0vBL124ntisetd9ErdrCYFuAICYQe+ozIBPjoePj+dA1n2BnYOrkjnU0h
3MsxjPd2zAIMvOj1mVlJ1NJJgukQ1CyvEBEgUb4SaAmri5jgX4tWsgyIewpXOxn6kAVpR68iGlCX
u33183CS7spL2Ns7wOVr2nnu/BCGvpkobY5KZgQeQPMdRjlFzfAfNqpqVwDPwS0hYPLCQzLtE3SY
3InNeZTbM62TGfvjd6NuwRLqTsJGyMFZR0LKich+ojxdDG1u66vEgJvgSjDoFJ1i0F4tMaXndBEx
h/mPj1d2AvzHqjbRQgGKS3BZGP3BMi3cE+x1ZA6SjlklIgVN/mB+ODv5/uvmbfSuYPsHayLAZ/pb
tg5YNtfRX22K7wndS9FZpcZrDjk4RnbGnLzFXt6Z245HVZ312tbyL77vxSLHO5x2y+zy5fC60FZT
POk+MexVYyIvw8WRohkU6k7H3XdIXjdWvywlT6TsG7YHN4CZCDMfWUN/iTJyZIl1ORXwpM4tXlpE
7qviR0b8tCg0Aw6Cbku0ccOpCtiVSOTeVsvCtdOZyfraUW5EnTox7zIy+zC31nGOHO15YMi24rIb
rMIo+FRcl09grVNZHlrlZXZhd8rm7cRJ4QArDrZ3r6pi/zxQDV6vQSr7puMP63xXAzpk7NVELr3x
2ZFoB803R/M3XMWYCzd5e4KlIO8ol+7VvbzTB3FFACFPkeiySCNG9jkC1MCnvGB3JOf2PBl+Feo3
hwaBd9eMVIFI57vNBDeW26RVQrklTePJJkUuapoQKsG2bty3dP2mWVARrooPyyPuzbb+UdZy0eoe
2GQi03WBnnWrgBnHZeG8Br7bZNTb7N9qNHx+Tj102yMdc5U8d8fp3GXfERMPWs3t2Sc8dfCdeP86
JSMXTopAApHgqbE808anlFS5qe40HvCglxQNKVhi6wCtPpwVokJh7oNxoGakUC6fZXLDnkSK/KG9
eZlsydXHIwfySBnzwKhgOFt/PMcVzGiJA8yEuZivfwLMXuYpy1IFBCXxly2g147kgGOPm4WXNihk
ir4PbtrQuqT3CDIaeHqWM5vMa50e5zhfUJMXK+joKXCHJEMdSNFxLul7ZAughRmX/0KhUNwa9dEt
0kGumg/4rjWJUnhFvjN7pdlh26j0ut4Fejn9L/BP6C1sW8vu45/UG4GyrLoWtlp5N7ua/3psp0AE
RMdxYlibAa2kVnZFUefTbQRUWUdWfqmnCx8O55tW8ZiUa7ulz1955WpCa2D4Zb4pmhTneqW+OXta
drpFSUk6xZBgGLuhFm8cI7rzrehDrgY4yTwegVb9g7xgal1XHZU6onE2ium/DikemA96BvjQ11xs
/Qs4H22gJEaSnu6Q9oebWQCzSbpNM1B2Q5kgNaxH0fhPlnPPAPWOQEdP9zv3AazfhvFyjNoKtab2
bGWjalzrAGDBCBANWeMaBVz4hrXwZCnrLqygGM1PWgkh03EaPTqrY+AuLdeUNNlxvjdH2g3eQedV
7HQNhlL3JyYkrjSYPQ6BsYDVU8V9ui4inYo7fQZ3rLK0kljd0WDiYKMmjXXbdXClDkiO5NQltm08
+zRAhqZmF00Xtj3AAClVhTrW+lkyoLQRJInWomAv8q3/4SFwSqlxtFJo5jXc/1WOUuD5MsbabSm9
IDsfdPUYJ8zcWlRRXpWQZqL/GSl4qEotygmv0ILlDh8kfDcAySmMWchktOD34UyCtpFjqqCtTRb4
plv8hx5T9Vbx1bNk0fKzKPaFmSwPYXztrZpJheRDt2bmSJeYl1BFUz7H6giQ0grsUzHV05tbBZoM
NlGbzxOL0ZUg1lrVbiCZ2/TkOnvs0h2xR7JotFL2hoWTmweHEYhDFvSqwUJunDnCbkiPKbbV+FqL
XHgMvNiTLQeuF6ddOsjXnvL8gojTuyQVtEWt8szPnrWk++p2BPMr+my5rdq5AMNYMzJoun51D4A9
joKZN67RoQfaBpzJz6ntAeROlQRDHAZXP2KyQShLJ4RBsb/Uipd7ZUGczEJrCujwLxI2hjIwMFme
jNAi6/YYkrrrtg+xIcGYRZHD5w6DUviSLVthynOl2VqecVOr9SW75xV37bAf9LiEpqs/ALdsPaUJ
h6W2xD1fw3FTJ+MWPEptC3IQ1poLrCOb+gYZgIHtccz68eE5xun2o5M5p4gxOtU0dJ5xYxttGEPu
Mj0euCsftz/3b6sgQ0av5YBMHzQfityXUtuw3qUiysEf/6vPy29SE2NeLaF569w/X6Xs3+mI9FA0
WKyhtvOyJUrV6GCOde57Tm8674hG9TWdT79DNSxXANZlupmrrc8Gp1QxcRvpxzwUQplbXsDs2SgZ
+rIPhMwjEVXfsSRcpcOqpUm6ZZl/+e8zmc5Uug0EkV9tfArMybV8KJFbHTOmAXqv9LFRO0oEuBAc
0vFzRdu5BeLMpNbqCAquAX84pC3tSMQFxwpinIb1NUBk1DhlTdX6gFQ06XAEcJcmov/NA6xZS3Kr
3nLBzfNSmy0i2bHsvuQqUVoHC5T6Lo9mbKOtCVJg0sPyCcDSao+45wgL4sGpic5GSRBoPI51/8Ge
xaDHUUCsJq8zZVgKMD15GAXwOa8rf35goR/YRuLDMOzmVM/R/9lykyuj2Ye0GF966r7WXfPfFiDI
wejVIA9JA/f9aLuUTnau/7ZMl1mYyQzx/INSb164WwxPBEFWHBLa5DbqCKKNfl6z6WjGjLCRyYlF
FKz8P5oDzgVx5kC10LjwCZ+QoTExGbvwoiI+t/p//QQNc0uTEvcimqQjE6jRnb7XmXyvsHz0VAmE
jzXBDavD85h7rWiTQwq2PxTZ0ocMVQCZuOpu8z1CUp9Od85cfPGMLo9EJqftUmJaPfTCUkm/NPXJ
d0ayRb7mNimZX/Avq8HRZ8FgOUOr1M6y/cTf+IWUZqMHTEN8gDAKDJqnakRvDDlSiK1IcrneA2nI
j5LIt4L1z8MgxgsxFYNhL/0gQXYYb7iynX2D4Y+aAG+H4VJsaWIVPCFAlXTGfhehYiiXV1ZS+1+j
OsnDEDNSPNCvKO2JlKzN/C0aKS72J2fdOG7W70+WsBuuvzgT5q6ZWlvPi6qmv9rlpB1BvYbyYavr
IXc4bKAQ6zZTtA5eQKvWAFczFMP2bX3fjxHCmsEx8IDbOBgFEEBm5IZiRXJD46NRdcefAHpT8zW9
K8p2OnDZGqspwR5cCbnCoWkj6pT2o/7PtaIotMdmmwukhnI1GR0W9XUKB+62ayNxK2fjKFeRuyTP
Z/N+x2vVjYLc/h21zMeiPHnRZlfY/E7iE9+0dvU5vhboPxqzvfMp5KPADneP2tcJVCyESO0SxiPF
o/Vk0ujFiTkofC4CULij3J2qyhYWxd4f6xcLS8OTASav4j0u1Cnz9qNcqU35EGodjMDphiCFz+HU
9pOMfkKhKl4weuycJROzvf9KcGQnnoZR39+dMaseG61+uaXzIRl0YJVCMZrh3av1DV+pD2W0gsz0
LJNFDPGrzvzsn6wSGnJHoxyNjbI9H5Wff2gDvf3Ha094LqRKUZKYuTRdO8wkyK5WFYICTjSz6AwD
bLWjld23LKFdRatfIcZieozD35HAFWRMqNx5dKhUIQRw/EurQWN6HP4taFobjxLc7s5pkwI19PB5
ROxQX8U/qjEC09Yc3iYzB7msTF5sMpER/wsD/j5FZAIJngt3Sw0kDyYsKAMdL/4OpQlM5iDRifn4
BJFyQxqW18CoBKSnq/yCXGJWs7zy3pi7MAi8+fWRECZxYWolEPM/e7sOqnDVXIJ+qWf3bE7Ux+kw
9Z2vIIt5F8J4KzgylS0X3GHQBrSIYiocDgdxZ5vMHjQWRHRd5nGaQ0M3cUTKWfVK/9JdmbS2kJqY
s0L5VN3EuEiKE4ipbTC6ccEW42HwuCHWOzTqNXLiNaIZJchiGdJjOw9s0RUNKOswEKEoBKo948wl
utvX9e//cJ0ArVWOm0qiepReMbVeiu/VBGnouFXm5Yt2353FkI+iY8ulJ7EAexvuv+MmZWLjbxMU
99k9mr9+dadztFdsokCb8fV0ftu48wQUOD/Sn90+nV7X5a9SU3FYXuJcx8dVCBOX0T2IPjF+rKqh
6CphfryyGPf078xaSaHpGJMZEyFGtwE+sXKK/pexIoCjdeEW8zFPAM7kYXnXN4h4B2+xlHsr8nKD
jn1EDAxiIgI95SMJV05hHXtSKNmNXN98Qk6ff4dM32xKtdjmX28Y2tpgM0H930g7ZpnucOKXV1rs
5CHx+GGz3GsEgrGp4uvNGE2e8gzzFkXEtquOaIpP8gotOqgZtzSZX8ZZfjanBPzf1RYYIeoiU0MH
De32D75kh5g1xjt0iBPF2yUml9FErcDnJgE/uHyD/Eh/fjZqzNGdCknuBbxV60Wi23ZqbufGlMen
EdaYe9PNLVSAydoSZPOn3MsGL6GEAOgTQQN+CrJjF2VT7LM7IbDC5ToX4yGr7BHlLXcrdysEVq5x
RxjLMzAtMIxMuCMC/umr/dYSwWEGkZFUtaOIFY/gMZur0VTmWh05vRsn6TZcFAA88tBLYiz9o14O
t2vutu1BIkdpMdFXFshcTetJu6oWnOKVGuEhwdJa84dASjeaYI/5gS/sxuSGZ5AbZX/hLMAZ7EAO
88W7BXwl5RY0eZsjdOl8uWqB3bVQDUq3k0de651EWloQlA4PwQGyqepfojyw7pXJp0qFkKaUjPVD
YLqyZRsqweBv50X4DKVnaS3woSjjFGHEjwlDpRIz8mveFmcGzWqQ9BkcJPpNR/TAg18Q0ZuwN3k/
J9wEOVNy389vgMiffs8wKTU0nY7JJDSrzI+8CWqd618jIaOS5uV1Zdqq+I47Q2rOb8IZM68gxPuW
7Jzic6Mfq/VZm1CEIzpmVJlwcUtL5zy0/lhyhyF03CRuHspPTcBr2YuK6lSlLpWXlaHG6GbiCPBO
8wdPvEINzv9uYXWuyWdqvmy7ybi90ZcRBjXd0mUiq+Lu6babHT64tU0ZFn7pG6j42FGivQ6zvjcz
PhPq320hZ6IxRUnNenrOxuZYm8aaVH7WJgkVcL9IVXsuzcOX4CUEPsxlWGFuLsaY8dGX6lhRlEpj
K/+KIS5eVR+frfqQClBb9abAJRJjbPZTNOi4AqcijpTm81tQm6CRN/O5RAIf/XEXfKbEli/LCqWd
2VbxtDuEe6ZQln6KB7slUXwsEsBEZUHYt+1UUotF7SugrRaJ3hRNxVKS0oyrH6wLOIdApOyEZbmR
ayfbmnXiQCqWaDFOWrSQE5AG6rtg/mZ3wxPbfS9B+F5qsStcxAQjCYGIKBmcJOUd2YJUWZpMiw6g
CxeAO8eNVsWMsf/Tfoxbt59xlUF0ofSP5qQhwm924hcbMkZFyOv4z3aO/CJElUPJwiTcEAy1TBK1
6iTtPQdEC5cQ21tToD4kVk8f7ZuN9O2h/iPhozJBK1H72QFVTdqreBjvRe7QWMYVti8iJpuZ/Bpp
RLeUnNnP68sZMNx2w1/+TpgFexGgu6Ml3sMEKtOBcAHkSU+D+d2pkxnh4lp43K4a7QmPDRs0bXNb
OC+tboKKeXKyVzZfW6wT5vtRHTFj42LbbtIZR+bFDITkEOFXTcrnMKjM3hkUWkCwTW+031jfgHNA
mmSC0AaLRA+cV3TxKddorx24HvvPBgoANAev0YDk+bu8Qo0Xots/rbB+CdgzIB6xNZ2dYDTbbf+h
eVweYEvCb74+Te8JHSdks+GbkTJyH49sKn9VDLqFj08RFKX6VpmOrUtTbxB3nfGIJFAWWqEBKwzQ
JOJmk/bs2Ve4hwORoSXR9sESwqiQv+lCP5nvlf06bXu3Flvk3sEAu5QNVeLXiagA+R8W/dA+R1a4
n24cXT+76wuaBFCTGxp2F7NP3rd8e8r7mwgAT/Vinq3h6G1+A9ZywqKJMCf+zO+TtCgSRG4E8ESR
HHvrWuWaoCUgr2LaK4f8zwlKbrqRzP2SdccBr5npXirb5ClXiTnkeJBetx33FD6j7cDFStnMu/sd
c9vDYBK26rDvFwyJnkhbGZ9S0F2j6Ii8arBC14l05znAKdgkaP2uAtzW+wa3ETlCvBkIkrNfJgL1
Xa8LuYntc1ouy9zwntXqq/nSLbiWHPfRSELHBeiFU1O6hlNMuuas06p23cQO0UsnKf+SIINXEycN
Fal4dOTN2mOmaGYvZqzO4GlkdJSStG++m/fVa2t1enGrNVx+5ffKUK0WTqfOOBvbbo0V7KK7vPd9
MK4WMvSiTDzBbkQoPQT+4r3eDqxBnbtswNc1fUtqh9HbehYWKPTQB+acgtTLWkJ/OITTcFxcK0IX
E7m2sx24QL0FijEZlHLzdur7RVnz4gKlVT05wlsjmo/mBzWFdjt737++iQS72nl7RxDQMFXpNGVH
OX2o7jnuAopjN5bvnep2JlFHJPdqVjDsxjCyQWLtoy27q89PaFbyk1ujqe64zke90hGHXjObgPDP
HIo+78VXwiBLEqQCq0PHm1oqqQuTqAuHjXAQPQ/+EGSIZOxGMETtswedXvqVjdslNpUjfEFCTu07
L6NimjqJzwLoOvu0480pe8RPvgGh2mFlJkNSzQbPbveiihGDYxeeOT/C1dN7joTfEh8a1brg8x7J
XDQvICHUe8pFqM3eQxx5/k70QvQb6LkyuA26C+iBL2tYDyS+V9xqmCQRxNleRRLat4PPtGDa7hpF
uqtqNJsOQvFUJY4E3ou5deGcF7DClg/fg/hMfd3PDn1FmyG6jTi6P/0Si+pNOvt3cbuMG+nwOUwW
ezCjzwjLGAnREqlRKyCDa2xjlJZuy6TkSe4wJaZJ+Yvdf0pFPzyzwTyDHVoSsQd1+nyZpbMvOhKK
Sj2ZviHVvsixPyJQLWSw2lB09eJZ+GI8CZNhsKtryrSU0sF/EIW2yc3FHYivdGZIv7ZazjeSay5h
8QFhSHG+JTe7v2qwd51sgRtjrJ5xP2+I7Tw3QZaAdOF+cfEy6xiz/kDmE/gXnQAXKdiSgK1jc2Lz
FLAjg4W732eT+i84kl5ahx9MyDUrSYUVDu3zOsrmCL4XmSxp5/WJk0LfCTobKvPYGyTx61l4IIJg
hH8MZkOm3wIRLYW6+ne2cthkC6lEgnYpqHGybC579G1KbZCRWxKCS/lPIgw9ru16bnC/CHuPirnx
sXCpU12XQxmDAtHQo/RQiC+zIbatg5cN0Mg/mjdTA6TBNKGsHcfU4soThfxpD/d8RGpDJKHeT7qw
MGlh7fibGegQw6WYNZYM5URMnW7Mj2HzcKISadxS33U++9NvwXz0+USbZB7DikUCLeLyYZSYnbzJ
6B0M5DBFwIT0yhVVK6+5AMNfaJXfQvwS8jtvHJbCKL3koZISp5WqBfU2yPAUVk3Ccv7dU4dJYRkz
JgXnO0Xw3BqCbSdEOE42sit8aR1DJMywp4wUAZ5FMfNTn6Uyxll4rfuQNj4AhE8aDybwWpuUylCd
vNkA2HpMzKIc4QQUo2hwUrvTWC4HLcAjMyRcYs2iqAD6l2rhgRtmeR0OomNqe3TtYdsbwHJGj+Ia
zaSvbm4IFAXb8bkppAl0gBrWWZ/Oeps0C3BUccuo2MTZxGlzYAIRWd1IFf24z+nPalkxqRCKdf8j
QOmqtRMWwt5dcwTLDha+HdV4LuYEmNgLgL4NMV4Mzp6CkSeRMx7KG9UguNU0zZ6+CQdIaERwGaWM
nU5ILT++hEni1yqjDWqwtEyanRkOZbMdiPn+lAFQ6614XUzHhdP6pksXZo7oj1mq2wFk+7moFAyS
22v0h6i3uvajQyLwBnLgCRDanaSB5v6RnE0k6hBZUaPcJSTevm3p4Mh01HvpTD/nZZGb6H/TthGm
OazdCMXZF29x+zzeN6ZedUFkkWzdaNPqLaopKKh8/dW2FdOwfvD/QmcKhlhzfKvBBFkE5AzU6/s8
mpfa1LekQH0LsTmnEtqTfnqNAP8wFa1sgkcNHCTcQrpBzCvwTTPCxxuBwFyGcuqf5UpjPhPaCP0a
HAsdpp0rxMHhHgmWtnpJivY6IKwTm/nrRUP/2UArTq7hv/9KRAdqsM6Bls3cmU5bN5nYEnzxw3Ra
xhZWpxmnUe6hMptU8uZKtm1VIN5EW97QXLf1+wH7yOVpX7AbtKa8MimBWfc3zrvSe9LnxdXFHYIw
lJsWr/TUjvUs+6I0bAEQL3ncEU+2HUeB6bProM+X0eIqn7l1swzBsyMLbrhJHvzPixKFWOp0+vd9
I8mQF8VkSqHvPpd4Wvx/epCBS8vaRZw0rG5oKzO7XSNR8Cuh9+umwVhoFHM0VlUegaYUXb8y0L4u
UrIzoyBaz8A7E26p3nthSji/0B2+Grv/oN9pPVC3n6ZhTJkcwUcgl0wKle57wdzjqZQUJ+eXwIu6
6VfZeZNe7EB/l8ikwbc1J9fet1Zgl+HSK1uhCOpc8OndSINPrOwrbLWRP9TATZPjQ9v/re4D2f2W
uhbSy53+36g2r6PehRxsW7co8w47oDAeNOr3HmcIxb2Rsg+dh2ZdP6SKpRpRCI22XqAN4LCBRJUg
XjXgVHUoAv6vSwBp7i26NbY5c7MlaDi47UCa30utRUKpzsxoCpLcza5J14e0x5pHDnVkv3r64iF5
BSkjW0TdEJIF/F/nykkjb4Jc+RZfUrjFaocjABG3X7cAckhrlDeFPuPmEl1G+4wKqkDrVibv88A0
qPzyk1whwQEOy4T2DhVcF0s1p4SxLaHHJ0U6xlYqmEev7y/t2hfaJO0rgXf2aYPs4BymOrNxcV/S
Xsh+pQTI7PtW1GhOQp2RbqDb6oazayz8RoFrjOt+FVM7DcyTbC6fXFVqT4KY9ZkILzfBS27xprPC
O5jxftDZvn3tljms+fbJhlu7fVZwONbthdF7J9HDvKZw0DocHbFWpupDGE6XE55l1TTbIbZTbiVV
Ne86fKb3cibQFvWBxr+CRJoGIonL+i8tvdHQ0wWSznlekjOZVm79PlgeFgxII5ySTGZp6ibcBm6O
EoBEhlAxbi0VORtLhExKSw0djzcmmiyUfHOL8NWEU4mlv3G+n4fd76mv/XCvyMFyAuPpLeKaGDf/
mdlefZH+UKDzywgfJibdUo25E77BmdLOpAp7XPVS0fRIaFdQNi458qpVPzqlvcxQzCse/0ekk8mO
Vn0k2/W5M8p8HeKEaKKonypKZX3sbf3kfXc+0qVY9ZLkib57SYK8xVUX72URnc7Aiif5gHFruVMn
N8AqI5r+qzkD2ugNTZDV0/RU9YWDqxhp+0sl2NenXtPuuNBYHI6YcsG7ZCJVqAXPuJVrasvj51lh
MVZ9vcg5JE4NfOd4q6pjID7wMstcKTCeFdYl5Dfro3wUw4uV6hQGdD+bhV0j8KA3izFQZvc3lgvL
gQD5CSmlHgw1M3rh3MblcPMTpDMQ09HwdoRY4lC5uJqWl0C2VnCq0dy1uWJ1pboC6mWOc58iHhxp
7dLf5j+R16bDRqXY6n1+1aaYS4NJ41Q6BBkV23wGMf6m08eWG7REp//l1Jf/bJTfsGN1N3pYEiNC
BrTQjTR6Thu7x7Ns9JbxqopriQP/NvgVgElB704Qt0vtDj5ySINu7PfPXr8s6btzOgenDi5np4dI
W71i4hmG8PZV/XLnae26znHhGIOg5Xgvp4Pcaa1HOXR2FdajBZZ78RylledPRbOaDloa/R2RxQYN
Itr46pUEE74gkm8gYnFXHFbIg2K3TOXhpkc4x/XTmppXqFdP6eh2BqWm/rUXl8FEqZTvWFCD73sT
VC7/MJaKkjstfTWW04hTcdbTzP7JONs2q9cVFqF2jzsrGOQ2pXj36y88xbgkz1YUeShIpbNI/OaB
O61QdxdnX87YgazDjuexpR8dmKPIAubkOa4Y1r6VPXktXL2dyNK6OsYtN+6BtaTpzylZ3+lQbBuZ
CGREDf2xjQeioInDzNX19vo5CXljzmwjpKcIwigIKnc3x2wSODeJJMjMVRj9cR6c3pCBromtWTmR
Dy4CqggAR5g5ibjjsZjtA/QVMJN5QdQ2Y6GgZf8CFoD4lavb+ByghU20FrpET5Nj35k+g9DoV0b8
ETH+VxwX85/kYYRJivIAPEefez8Og2SOO9CbuOjXWEOh4mQDY/+KrRCw2jpYswqHe8H6bVu0ibAp
wdSbuqTMzbb5zSUxqBn+hdqo30apGj+wfzWL5lFcPMFLpA0IczRtd1YhD5nddVGwi/vPGUvCM3xJ
oHQty6gb4WE3vuVvSDjmYzEvLGxR+di87mHNszX5HN5qFN1TVjLebHvJ/HTWVXpG+qeZzLCdy6CK
YAnxIB/uvkvJHWZj6m6/Eb+r+aq5IW+0vBrow4HFPTjrgfVCvYN927H9xKRloJl4iuIqgYBYgBfs
fOZJTRjxRflxaLWusPflEjimUZyKgoAuJ0DC5QMTv2DqpJlTDnuPhsriEf1uuC9uazfmPksgxVWC
AL1abu2uHNpcwhUfFozoIM0/Ssn5lbv0gSZ6c9utnW7XwkliLNzzX1GuMtv7s8c6Z2H1iyqOASrQ
nmnxw6I2XLL6B//1mCfY/FTop97DwHAJFO5dpPXgxUUVdQKMq42JF3qC9TcCkhjVDGcvuDxwbEUQ
1ueZTER1PMXGEBzNYH/8rqDkUB7VI7a/5KF9aaC5kcoU8eUiiAMFqZz+VQ80q2qvcNuBts9sgXoc
KnfZNSwVeEyZAV1wYuDSmVjez46hx4/HCFUD7icVN0a4Okocm+X01Jj2VRgEUCxhS0StOlIoLtCM
eaqyeS818pOgq6RtbpcHDLtVnvt6Hpa8Q52/RaQjBt4c3TUCMT7VzIO0ZpWbCf1lpzLIY930SlhE
VjqKe48U8WMSblOxmawIOfwYoDJitIvZC+295Wz9pTI8xuD5k9TS7TZBHNTjA+UYYt4/a/JexLvj
LHH9IxQ1EbeLC3DRsjNAOtB/CJuiBoPfF3oByEx7L7cCRVUAfJNRrcKqhuoT0MvP3rgI+NuasCpu
goXhBUVmWgYFVD3R1Pm07gmGyNTsJrWHiL4zgqiVCceu3FFEzZxvIOR+EWLP3o2elQAlUeC8Vuuc
S3nZRq0Y/u+M6cPjFnHfHNbna+j4EFr9CWgRTN3f9RbB9xJH7ph77EubDW3V7Zl8hcf+bGQc7a9d
EBdo63rZoktinfS17eBANY7L4VKd8Hqfz60XYZcx6lTlQrhq82e3I5b8JYVra2rbFBTCuWlrHIEk
HDm8q2S8n8mzIqnFTaqTYvJLG05ly9l+MEzZX47dqcUqTgUrt8vhNpgJCfdhhN718mmJTKqB8/P1
oRYTINlyYUfgpPfIDisAMeX774failIdmcWPajmzRgS7bY9JwG3eBanJCo1vno1LXSH9MNlgpSg2
mLNGr1x9x4Ru+pPX7qHIDDBjdDNyaZwaFiec+lgzdCCoQlxTpmslsG7ik7bQNp85bNRgm400Fwme
+8BT77R5fMkM82w0kXdd9pGh7U5bpDiAHrhZIUxvyCwc852YqWOdrYKlYo+/W57+/P0i9KpHySEG
URrfEOMBEYgT2Cc66siVR6X8WlP3KbKrL+hyzh+XiXEIRDIDVGnOZvHAsglf/ErSURH/u4/gSGEL
3PNXwZnE7nIdXThwShRqHHH8B3RQOK/SvAHV4pEXarZAwnyC8x03Tbp5pH4pOnOEF9dgwAmDz8Nc
WstgJcNcZHH0S/V3WMOrybMMG5ArBFcgDWe0ThLHM1vRuDG6WdKjwXTuDrdOrIXVXxTCi/oRU4F4
JKczpGdJrhojVyZX5we7MbGdL7f+hHBEUfGtNO6l6yWNWj3AGQZQ+Fv66WZNaqz2Q4Vpp1IXLE/0
mxPqsdikxqazRPViu7gSttK+CoT+83hXsAIam92sHVTt++YPlh8RrhN4VMGvRGckosLxJl8TzDgj
uFaRYHNYFDJBSYlbzF80kRcXqpJsumNOJgrZn7b56+N1R++Zhdc4ld0dGcJUYWzY8ryf0XoS5zcY
w0u9KTX6F3zGc/6O05B3oHtBzdZErB1rD13+bWJJqhV3g5nDI0leRheno9gyR1sYh5KxjGArniKb
phM3N3ENhA6rO1WhWOktPGY7BMXzTZEHTyxPiysPJNeM44fXU7YkdZd9wFAqk+aomRWoYE48aRn4
XoiJW4lKvWOabDU0g0QgOAjMb2Nf1+Cpi5QSSGYrtSZYN5CkTesbKOifDmTKXL8W98BwWm6abQUm
t0eXGuNTNH9y7qIyAFHkn7xcEz53/Dx/x7gmYS7UPoyNEBwCplFQUjfQVrFncy12g5JB+6GpOoyk
GeHVBwvHb8k4Axq3J3i7vDk/+0Ti4HFgr4m3nvjIEWVvOobNvMNnOyhU+KxCxLGSclsAbGdqHc0P
yzDBgL7/0G0rz+8OQckzBL8+5Ntp4ZHNeSsIOIYxroxeVeA3Ir39WvU2rvmsY6rfl3GKJ+3Mr94K
ICGFpGJAg3/QINJQRaz8c4vPfNzXObkS/xQxB3MMW/XHA5NMiQXyflS17hhJL8D88Ze/h6ZhT7fZ
9ZcnhtyCiuKctLF8f7kc6iyHzTS6FtsqZayIMW30hJ2apVm3Yz2mDYND9nSPXJm4Sm0mNZMo4Fxa
qSRlD5HAtaBucNgugkqmJKlXvlGHinamnGH3fVfDxRL4gGYmxTZTPPtPbBb99D483BffKRQ8WXVS
BhD5ZCwflJD+WK8OZEAiMBsdW1+UQECnCvxZAy6tFw39hAdvgyC/d0Bz2xTzTJx4O1v9xmzTI/or
pHMcb94oQJIBPktDBrEmFgcV871J5n60qGCGLo6EgNlntZlpD9J5MxX56ZwS8W0JuGFBGeJ4KJGX
6EWXqMnxecxi2TthG7AFA7Mg/WOAMYiN+ZdqX7MwVT/RTch0i7c7P9i8ZCI6X39443kTI6kCfrnC
kbUBAgP9umCGJgV6J0ec7cBJX3w0NM70wEcNXF/Hhd83Q+HnLyVfLR3pIxBBOWzBi4GSBx0zVaDI
qkZ6bLQ1O7C4Mt75tFo7x+WRYa7ib760pFXvFTGNpUyOw3deOBOINrtF1+PZpZRsLZAP43EVQTnc
tGB2nnkQNpxHG4mg20FzKVDZoO41S03+zczfLFp2Nzpkla8YJoBdWSJ7c/v9NsholqTzAIhRnDdm
xibCecHz+bnMJUvWMn7PkXRECXEGkLo7Gu7DMgDgi5yfiOWI+H2IYrcKJXqwlE6FnUYlw67Df/x0
yzwyQWgObPvCCvh2Cnz8mSxJnV/SzJhWnR/dbR7m68/anvudaaJH6VtHSY9/arheKCvmD5Sc1XAU
XzkGs9X8dxyhglGcBP1LPcG9R6MNlmjcOZhBP/eALdy+f/+bzyth8Es0qEjx8nbYLdXzcUtQr02y
A+2PFC8xbAIDz15c/ht/EVu+6m1Ui5MqOyKQ1j99epUORE9GhMSD90odAOjS0LEDP1ajWuxxRHUY
5+AqidSIFjCQdNnDZ+IG8EJpUUmIbOighvDTgBmGbnuy17gSNGki8sAkbQkbNjYqCs2dgZuSzAJP
drKyUIUi/VgUtCJgAw8J04fnGq/KhMznuH76qTzPSVM/kLgbDi8I6vOfrYqZ3iSH427WMQ0EyyB6
7AikSs7+V9HUpLyTYAynDLpbatLudpG9QQNSEO2qRkgPcl36Y7wWLU46Y1GXSP2uNljuEFtRSXPr
n7tItkd33BSxVhge8f52OLLdSftsITQEoxNlm42XTXeJ9fz7Dm/JqkwGsbAOX/M/IrpfNQVF05hH
iyiFPAHhMnE8je7tnnJkCdxI6GpXW4WrSzdOX0WUX6VJ80lw4sOfbZCjFG/2NhsaalmT9JTrfLpO
pPVGaVkQ6apGC4UknMitpGOIc6f4a8YQy0O2Us9VAd6A9FgU18RIUA/AHyFgM1qfFZ5vF4a4sj1H
ooK6djzCM4PgwGx2GFjWPJhEXuZ8t1+KNtekxcGcoAXzTpjNakVUzSDwYDwXHirQY2awAIj3aiA0
RzAkCCCeTpVfJL+mf1mHMbX61KJdB9jCjQElnTxg7VYqBuPAt/R00nZ+EaXFHAZNDM8jUkS+DIlH
6uARcc4tLFthvKxCD4oUtTpUdj1BvHzv52l8IXqWS50eooFcxJN8NLGKrqgPEF3DJ6vgiS24PKtU
bP1dgReTO+4XsF/guFobDmfRyiPycEm4WegYjg4TOAki76jPCBNUsuGR88SNWOsZTEK2hAa11+3O
kZW4lLmO5jWHnOYByQY8FYsSYRw+wk4NKg7B4njise8+LC3ru+FN/b27ZzWZJxSnKTy/pCwX2iE7
zkzQ5hap8RGsddvwU3fRSSzlQuZsSk/CCntVFwbTBWjkWC+lEKyuQrd+YvBwvBnMCC7yKyEa5qOu
P2f8NwKer9v4dOK4BZlLwnXGYVZXjnLm2UjGl8n1vlTSq9E/5txudOKp+aOuEaK8kxhn/XoDga0q
27JVH1kbBZhqQWGUXFCaCxUHz4BFOxAR7CqbkA+iNrWKk0xuoLg1wXDJ97N02L7wJkAIDD7u8mKO
kIgyxTVVaKqPzwFiya2DcHXL9kCfr7FrYFm4SCB8xfgyQm+pT1RhJHmUOUQw0GEGMw3QsJmokNs3
CStxMmUDdHP6stZalBNsAvYSkQNjjuPB6PaBgHdWU9ySeCuSgCeR8Nrtfx1gsJhM/6upJNZsprTa
Ffb064i/kzlxURfY21/ioaYRPWoejMj+rtGdiX6fmpzgC1LQ9lm1OBfTu5tcBA5v8paO4agMr+vg
ByEl5aD3OjBoEXxbDqsRa0tyFsBJI7kVY1dUCE/2BL9asILmp3SPZuE178N849qqFrd/rRJEdskU
jZMavBVkfBTn99cKr9oWiOcxD5J/K/EuEKL4Clmgn3AAE0F7ql/R4HifStQptnj07FVE0FSFHzJl
dtOkuT1xbOZmBNRhr3JFK+KKxjT8CJyt48ZAlnICpoS02rnBswbyj6aWVzJ1oYvCmx5qgHUkH2co
qhurxKDT4I1GJMkLaXX5OvVc9Blee5oJ4BY8FJPEOX66yXBLwPLTtu0fvuineUB9ZGNE9xaI0riV
8uVZrUCwX8axLoTaIK+RRylQXbIwu+Twjb/tWRkVBinzqn4xw7kUG1RmavSlxq2pvV8qM0UfjgS+
nt0M2XLJkEcGOJyc6gvDU18dlH2pYCIoUL7ZyFJccy3KMMt/XsNSzM56UAbi8IDigTI5zkscgH8l
XUVLJAqHOA/AMpig30kFjnIlCLbY0QbOuZpXsumrXtz/0mJCnkU0TbMORpVRZpToryQ148lnvDzx
lyUFfMMuOWCbAw1aHedbC8s7SNI1Kd+rfOv4q6EAnAAZ4LZQ4WXcXcDtDx8QAsr75EXvDcNVaysW
mFxFkvbV7Ys2M3c2IjTGRpHdijbDy6iWIzJLrYDf0L6/WIU2Vv3WBNXbqFXcwsdJ+0yNL0947rvu
ipE9kaOyFEfNnfTDDdTxR+qr/F7gnFBqQzW0dL7ansvMXrRuNT+oEfa3937t1KAPcVeMXKkXWxqx
G40U2CfUfqWKbHeTAmVCBT5g1vbZrCmr10F4EX4kE168Y/FvVEhU1YIgbrEH59HAFtpaN66OWtvp
4krGcuqfFK05rqouKmYbOMxck1Xa3kr+2hUNaMULq7T3m2tMj09oQR8EYMV0U1y4G8eFwr3jpkN/
2yAFPrLC6O0bsKL0aq9R3KUtqMrWYpNZiPDWWzawxy18n0HePqtuyIKAD2NTLfYQ4zr5Vqlb5zEl
jveYM4GLC7phYJ4+y5b6kFJJgzBT2DZWM1RFumYs3YWVj8BU6CTSySZiiKr0D3PYUO8DjWq/bvtz
VBDShKLH7w6sRrN4fmnpvqjdAByIpdZV6oLnpolwF4evooOdIVaUn8v0f/48V4EL36ZnL/PhpQdk
5P8BGw6XLn4s810a8q/g+aQU/Qd9HPKZ5QfcXkiYY02WXmsD4NnSpkr1To/ylmKiOrvIpOuqD2fF
+d17ZHy6oo6gUyt8xZl6STM+oBl7LxhM2SlNhdBLn5jK2FmnN4ECQCeocV0gQLLa8Au5ahwXC4nz
kLQJb6DrjnfMEmxy8Aj6hiO2m9q4x3PZJTiW8Q+HTpuY1quSW5Drw1xhfsuWtU6PTOGFTcMng6DT
Ff9WLIKOvMn8z/RPOvQAlnBSoq38aRLNJoyzscUADCU14cH6EYDLbZzb9gCCLXgITgSexdheFcRw
/h9BQfuLhY23aWiti734JLdvG44LRhato9iGr8eHVo1QjSpus3hi6xUNV7g2Tmkm7T5OQIaNcn+H
9DXsp59cdgz94fh7jlAhqpe+MUZ/FrYVKP+c9qhdrRmYGAMIuY3iIpgpKddSPSUnVUprUeYuqSJd
1QoL9ZVTyEu0h30+7lHp16gpT4TqKYVqawf+R4fWlZ4TQoA+GTGXuICgv4HbXNmcf14uNByhbjzY
nGCNXAbiVEWxu8qAsN/og8jI380FC1heZhR0+N0abzvLLM9tP3sj164/VR/5IUCE1i+VtdxqREWK
IzH4qpVdflNjlne3Nlod7x5dfBB99qCMS+zRPFLB2I+lzkBiKLfOeUDxLWKpyza2VtnhO6/bNyjb
vV8LuOHVdNd8OYyBXvWrmKJZ7mOPWCVXnxI6t/L+5DnmoHzzL7IOv0PSD9957WBcZWhfcRfiAUkJ
x6S6+9ZgQB+rVssI9WMCZHlfdEjt2VlMo0trDsMya56R1BO2lLQ64dLL961OGlEAJclWGKuDbA2W
KSWGYlbzGR5DjYvPYAKK9sOwBQnxZBOvhM5tia2EyRp4qc0YiYzAY9Tb+R551Qi5GDcbUriHM2OH
6t8VD7sbrjFD23/IekhLx6a+JFa+JGIqbdVJNt6Kr6nccX/vtqssiBg6eiks1xBR53Z5Tr4DxukZ
wt7VE6TdWGypqYspeAjGCe3w2Oh5QIWrMzJ3K/zyaT5/kYRDqxXv7iGmp/lEYtLF+DB/v/ie+yz2
GbJasAkBntlZu21E4twfoLcazCk1GVyGUeNiM0zPTVSnm0jhwDVLtqg7Pxl8+YYWZ1rAbILau6bc
pSkcALazyPIeDn3URim9kHapn8bR4qJCpEcOlTclDgTDuFJZ3GNLffPyg2ThOla+sytmYWCqb+/h
aQrsAetFGEOsgRA6f5ZMfQQp7UouWAf9JPwoSoSnQAsHejHpQyPEHoVUG/EvYvU4HC6vHS3XN7bX
wzZRtbdcsbRUMHzYRGSFjAWTcsPAkx9yA8pLZqqnJptB1q2b7OSaP4UoiyXj5S2ao15mDvUFL9Bs
Tn3Gf6aj7xNvAjbM9lPjgahpxFHRWGFiIZDYfdv7JmFiE1kjWQow0CwAq+Zwmi6FR2mj44EFDnod
KkNJqfGDxYoRg7IbGFvSr+1JfZ3xrVOiYU1XnuFYa6X880qL7GgC+WM8872pi+G/1bzo0H/2CdNG
dwOpsGpyoGJafJPpIndmjcEobblp+ZNABRMhzwmJSvb3q4v/elVmEkiFuDlKRClf4VRj3OhVDY8X
dMxPGFcRLAJZV7cTjpI3S6uMwP15mr9rbwkVQk5cYFBmYND/LL8/MckABs2wPpMiUKwLL0S0CrO2
x7DKR1qR/nmHKUuBRU/G+r8Wd7pc0nz4YIvld16zpbMlprJboqoxD8q81cPJrchO9QJaphiKwRDT
4eAkM2N+utFNqOfrXwBwevD7sFI5UO6F9JkkyogNHzs/KwEZ47ABq2Pol7cq23omSAcgKtNrrcKD
dsRkjU4/DZ3TinsUenOeOMAOMUu5OEPJ95OufIqkSLL+wc+JPSDJS2jkzQU3I0+C2T7JmE4aCkB9
pDp8v3PBnNFTNEwW7eDv+anLEZJVJIrwQJbk7AFJuqInyjFNVNy4UBHfCtg7ej5QEB/98vfV+mfk
libioXDlSKwc+L9anQeqx/P225MADPeLBvxHOQHeUDzgnmuuAZmyDzqHO7kjivtm1v4pBzqgV4nY
Dt5N1qeQNQXdOR93y79DYoO34sLA1L7jVh9w2ddu5D5ECohyPi1B2J5QQV7FUX3JJ9tg6qbWIX+Y
Zy+iiNnaRHaOQZwJFJ7ec431A0YSWR4ApU2C1HZ1Q3HjxpbPJ2Oj6m0UsUua15Xe/2JkoMgLy88A
p2kamD+9SwXU3ah22FWCsZQniAAPPG10+n9LztOmzTYGgszCS7NIiiaYxXbiRJLHlz1JCsjiez0r
NjWH5sLhfwiY/C7RJWh57rb4RrTd5YJ16/CGyzpKwABFdzzxEkIcAQQc8tzWorbs+hiBEjXDEZLt
FpYqdr+/P6K6Yj21tM7ZhV1glX7uYKLO8W3VjSFNHUJxHB/YSvi4q5lUhMPN5EOQ4ISfowogJPYB
UubxKBOeoXwRo0P+LQeWsDQp9bNTXP2Cp/gCjXwka7y1iocYhIdU2yxNxudlfmPQdOYXhXCG0XCa
3fgbyOpyFZMkFMPuH0iuV+OvCawkqTs2tlfEoJSNe8bBKdLGEdGJyy07QU2YDwHQ+gktue3a3pvC
XTN6c9gr3Yq2PJ9v6ikB9yN1WL3LKALwptRApB9k28zlXTVVP19Ch2ObMKw7EfdTwaPuGsbz7Ooz
Gv1cd8WoWotpu8yAVx2ofQA9vi4tk9u10z7aUg6b61jlo+psOpcgf4uakeONUgRS4zmL+cRvWJ0D
9afH9kdFhwf8xJ/3xppxkgOcms/MGiSSHIOXhfdaqNgfPK4HCizKlucsEopO4K2rVqvff2AUA2DF
Gl2j5iYHjR6xnGSqLQKXwLqzx2NCoC+SIQQ4ht5weaVhiXTb0j/GmHvifLr3yOhrEIyr+F/udMJ0
4xTM/j1Y3+wkpXZjB+iH6ezemFM3rIHZZO/2OjGTTY+zzD3Z21DwfXKe62wN5vEhdGXOBryvCQjJ
K1zrBtAeHmqyGfVJpLa/bVVk7GQqwsvRRXnFPPGNAnBtPpNpbQ00KI2WDtIXLn7PjRIoeIaIXRpb
4u9RYFL7zbE+4cXGF0h1paNHS9YcCbJezEdg8/KscRv5x0hdD80yRIa3FQLIZ8PnXpMt040uF6an
Jyvw/2WWrQMNpvxThBNJGUstfd+qYDZuZZplw/ShZjgj9cVsTeZG/0S7LjgahfMtaKbHBD1YvS1E
kRhKPHlWQG+neqEdteDApVx0tideqeoIZqcDw7chgV4+9ZDUz8x8E3/YnNqC9ODWu8w7zyET+3b6
PXK28+Z0CFlxeOAs7Lx/Nj7tefAD7RBNENDVW36zlhu1FMMB9EiLCfjLm0LlELzLGH4I0fv+7Bkv
KcCbZqR91sZGZ+xyDjZiNFJmoBVkbpV29/Tv3jDoL0ESPYqdtxQbnEMC1fhkmN+nOsR4ug4ng5QZ
n6sV9439l46ktYYm4lBcLHOVZzrhBWY0nFsNGpQYsdkZre00ThHPET7xvEpEBGu83MlHe13u+dW3
qF/t6mUKJLGXFBNlUZyyCt/64kNpU6UOxtwvvk25HPdF6qBXTTqCfuppOZP8TN1karuWIPJ7daUX
kr3UFbsBv73xswIvwj6AU6awyrYCzMFJ1SorhU+IvzI/9zIs50dUd9/SzX1DSL9L/rYLQHVLlqvU
bN+tBeFapbDTVkYK6gLwYCnbhKuDr7y2j0h3N2AWsZI0EMNDUmR5MOk9rTxNHUnhChygRJ/jtxTW
pr7zTacOF1Oi0jLBE3s0LwlQXc4P+TzVlSr1WAASjwlVER6suSXf/4vRHOZMYoc9YFSQrXl5oGmt
pahkQI2goOA245a/gvOFofp/NMu04ZZE81w5s/j0cfsv/c057B9LakeVsWMTTURT5UJLUHZ+3gZw
ZxfJ1ZbAwIo35oTH8bUmPITmk4pc0+J13Xgq6OzNGfQFKKg7sIOPz/iPjtDvMCmojHzyJ+UIQbBR
9eT/Pgw9NEKfjL31s1Jjtr/a12EtkxXY5Lz9g1ma+9uEiVosEAkIQu+KJJK+HihHNdHouJo8Ccu0
sjEqvxAYJpaMyq7I1tYpULQTpM46f7IkpuXI5Rr1tVmMDPBj8rnHTQUoqbR5ZaAKuqI8TMcWp5hK
ZpqtjeJIpEASqRtYyK4NFtd9AW7/4zB4KBDVd+GOg5IrGedMdzGhG1BzXBppb09JfEbgPh2WgIFX
L7OcUMPufpNUtU2/FXXiHuqfvbWE4frW1CAmjDTe9Z4MsCLa6WAyrvqRzXYj+j6YL/Pp88QRaFH3
07asy3aUltJJauNYDdK0xoa/TIxnzpxEGzPjwPLllxrnAb7fCv0pCd0BSh1ZXLE62KwZyoGCfUeN
GK36gdh4rzdRg2wtB0YFa1r5hBh99YyWSmDnmp0MG4YKxqJxDv12b8C/uH3tEB1TGhyABKp3a/un
iLfHO7cVzA/rFGFSAXWeC9b1T7T6Gq+mAqNcicUmzeO9vbs38xnTyVNojq8pG++e4d/a0PmOz13h
YPHIPOPDEvvbzxA/WZdCwLMBw3oZ7QTxe6tgLkxof+ryWppfATyzyqQ5WG5YWk0Pl71D7BVthKPQ
9S+UiyDCOTI2bQMXanYJksc9dBxBTuo9HMRcWk6j+rrLuYN31iOO/yKZRYPmRKyz+DcpO9hxn3dW
Z/OVQwdLIfnZBo1pWJnE/sHbPTfMNi9yfMG2VN7+uACPNMYDqr7XsBUkMhfEJ8wX7k+sSbc8DzbX
pRVz/PPv7Fqspif9Nf7dYk0sJLL4adcZAGPcBv9G99MqEo/YjMfm9DicCcxl7VmKSc07K56/MRzK
np9xENcXt1IjvdZ93yyC0mdGeKcqJHNwvbaf+f43EmkoywS0LeHMl8TEFSuUcH8WkVnxxoNa9ON/
048ysSUInQ7Khf4EEBdke9zQjQod0IfHL8d0CQsrLTw6Tt4mMLU/KVKGKvhPM5gu3XRwIGJ0fpTc
aYFDVTdbfMSOQoBEMwBZye0FEN1PP+mRpazLt5X/L4RoZumisG21GFuiE/ubCORhyZpMnvMK0lcD
h7iwfVOJ6yqhbMq2+Fy0VvRMmf22Z+JqaRzbD+frMjjylLKo958NKewDExxgkHIwu4FoO8DQnhzk
y45V/o5BB+ktWcWA6a9VUhBt3SfenjIX9lktvyN+EqqR4LvJCW+xz7EFMjAlbbAyiNrVIdTRC5Zc
KzCVkT3tbC8LhF12exsv5KyQrm1jKJU0VngHpA2g6i+LEDagXF9IaFUALCUAdEAeM91YmZojy2TG
eNG3beg/IQHKaT6kXxCCpPhoyl/EccBiLvZ81OdNVWbiWvT+h/QC7r01BNtuGihxfeEZ3MGk6NyK
+f8oK55gY3KaRKHLkdF84/HuJnPgU98LjQoQfAPw/vxyD8vgHSivDMVSY0AkmgWSlIZRchPZKEEi
vLkVxtb4kSuK7QwuK26mSjRehv4KGBTysS4yfkTTcUvfxTh2td2N4kaio8zc+ITGTejbEsWO2xcc
SRjRIeGa6Gzn05nmTnICfAxN5d4hfspAtbRe4FNFQqhTPSIWHoB+xFPd3uN8jbNqFftULCaktn03
yS45Op6M46exzc9XsDP9JM7uQaVYP63m5er1YzA5w4Pg+MlgoBACCrmcJDE2mJn8nOaNjigGtEUD
QM8pxICQI2yj3/PSBA90+XHqnzIoeyiH5AlARBGSqvwA0zbNr3Y5FXs0FwnF6nkeyhhP+kPhtAyw
to7ZQNM3UIKLPEBijACs22cvF0l0QVy4MK3tCDcEqvJfXbgKjN91/e6AKzvxmT3Pd7M6dyUM57tk
EebL5TnN7U35nAYOcWukXMsT5vdAYO5enLAwZGWSeqILcHoIkANTbjYFWEMRBx/qkwrY93VRdwn8
fub2TFqEDTKEZanlzMajJHgyYw1UAPXkeh1cpfOLQk+sRDgn1X45IdCu62XpIhYEMtaXSUjHOxkA
TVhweO+IoP1FzLJGRpeqAbyzClgAr3kT4gaXwbIrZiw7HJ0AjJjhQzvh0jm+fVJSSLLk6sz52YeW
WKOlXDCde8atmGPKKzvfyzkceCPu02OGq4wFBcF5BXFoD6w+LXIwFuwbhfHGiZgCIUwC0Fn9389d
USoT8T59owl8uDjNJQ2BVGdJs9cyBdQVON2dXo4EkI1D1SM0bCIBBZyciQenCuAa2jTOjqcXNeVR
ZluLC1yBSjC6FpT7jLKRMInJnqkk7xOHNdDvrkthSh2Ut0prsr0I0VaOqFPGXNBIe1XNugjjhJ/r
prfobchEbWc9uv8BKM4v/IROsEl7g3AhzfPxKpj3AJxw3xwgSo23SYNKFID0qy4f2/0o3Ykni001
DSgw279sZWPjYjTsGCx2+tch53YLNg9sRnpy7U7+nt2cZqkIvgxtczKbEAJPcMODCw9CILTfgo/B
u/cpokyvGyJaH7jsa7fPe4Y6A6LnlDBlCcddmwQ/wwEzlCk5N1rsGf82Gyz3idSE+v5wNpDsAdiN
XBJo4wTYOH8ta63Lku9FV+RBo/AiCdvRyVwaILhRnJskV/V6Z9DutLijsKY+/sdl3lIqKSlwabuC
3AHuwTZIkQ9mxHcQ6hdqYh4S+teK5AuHU4fyh60wwy7TSqxUKamNWkSkZsBRcM4+Zoj6I158X96J
au01axxaBcDwi7tEcONw3bkGMA6rPL4ZvjsXj50ckDP/yVdSz1aqdKIKyEjbQ/LuACxH2MqB3qQX
t6mDU92ozaOudoG0xN8c9Lrz1z9EfbTQc5Kq3Es++g9z8/o7L6hZygbwPEAzw31ZjGhk6nJ6bmzc
ejvMPjMbB87Sml2Kcdh0xY3fb8MZ6APXz937wjsU050KiW8qSzLw4mcsOnJSGKGLc6MLkt5tTKb5
W5CD4i4FfkY03XljNmkMCferGmU/pkZ66dGc2ywIiImRwLkg0R0WLjfpVSvQvy5LpQ6rd7UdZvoL
2oRsA9EDVLDWOCjtCFIVDzFg5e09MKc2xCopEpfC1YmPM859g8cIltgGoXbmvb9LgP8NHyzT7Nyh
6b/U/KKNXrHXbSiD5rSGsm2CIQ2/VgquFJ9V4BG9p6RyPPRxR5h6i3LlDe2TcPNMh5dsc/QJr3f6
2gztFhbNTVrHUefew8ej/ZuAKIgyDdTQN8iSS0X2l6k3u7nzKftLVG4Q/Kyp9sGx2z6qxC+FwEJs
lscrcqDHAuHaKiscrGpIaalX8JhIngPjZSNScAUiaoT6+emUoEPnkFcaGsSg4P528lr2WU0IM8nf
uAhRxZnIZvrN9z2pOYtlH8JKDCL+u1z9IMxzg4r0hXd5a5AJGPzyOgb+576pMA7DwZv44G2l6M/9
qcif5khNbfxFS5kv41hqfDflwJiaW4Vrg3wJLR9yqyqLwryiUp42nDqVo6f6uzl9nnXFPakJwxlX
gVfv73uCFqeXnn+mZY01oV8HKskBV7c3mmhXMDSPnHx5PL5TuNiHcolKBKTW2oRtIF7uklEin4A+
Hxb9KYbwzN8WTr4QrCO64B+YkbIfLinE87Kz2m8EiWYOoGbh0A9RGBrMx1k7qLyET7FSMC5a8xx+
EXNOUK29z9stJ6EhEnNK2EnrUtfw3OU3/qJQi8ukFt56dHTZvPrc4pqEc1ms2yOuBX4nWsPkYm/f
4fCYPv/d7G34XEFudkqVlIKhUKsKUn2dg5huNpJCjXlQYz4ejg9maewF1k3gAVZLGkf4oK82lLnY
cJFwcwMEv3dtcxKiMKNnp8SJ9E0QD6FdVrHjH9+s5TGpKf2E1B4al0zmu4xgjvQoY3V4SyILeoiC
VGYjW3K1l6O/dPdpSQjEryfI4RarwbdIVfNdWFqmwM0JxjUEg+g6WqYtumH/xuj+sVHowkzmJzIH
rpM+TbRedCA3UuCInAnUTSWnwoQOeqGdwW3srgM322Y1LK3YC1AbzwqMHSS/E9hZjKE3J8wWt8ic
MlRCgMpo0jbVaJXFm9z7QRGfDLCSlyYiSNw9754/iUec5lSpIWp/C7EkybBw7saRcCBAFj821U1p
LohiRxVgwKN71oClIrL4wU8oE8GGRK9E2xDLiv7KpYvr0q4lHD8bWUZyBKOJjs8goUfLcAY2EX4y
6GPKg/Rzih833dxLefP/4sWK1uu8pfH4E6e+M4MzBPVGpw+wTDtdUjVW/nieqCoMA53gCcenD1vR
quiidrXK76h5a3zpfVFo7oV5RaMSXcCieGhbP8kfidbWiiGaniPrSMgCc+ffd1yRkDUVQxLrnEUc
Pa6qOQ8KeG28oBUdL5FnYDvlTsKnVrGBqxJY9vBqPFBAvhJaWNMNo8vhQsESqigutA/6iiKk322M
6LXY4u71ruBO+VwH/JVXWb0yMN9OcE8zWYR8b4tPqaqCEKphOQu09EUxrFoNyWVasm4Vm6mG3Jkg
dZ0tGyVUlKub+3DqWn0hpmkwnfug+ix7bAyeExW/OgJZwYWmbyBy4rwkx8KoJaqleCjUP+m8e/f4
rtG0C0dxFy+r9D3CjG/RDMOKIGaYpolXEDCt48+J4bA3plHWOItgOTyAU6RqAjhMR+pp0pQwxCO4
OTrpL5b3XTQgL5e+Vwq2MEWn9diGf3V6nXn724I7RsXa6ciklCF4772gbsKyl83MjJSr+liaBnTs
F+0S3Zvv6r4fwImUs2TucPlyGXEw3oNH0fmo8LwVg4P4Jga5XTK/Rrb1VoQ7aX/xiTx8h/07h6ao
3CMYfJKBjG+54XAA97SMY2Xu6jm8wIIPhZPBG8ZH403kKNeOXxhTHYvENKC+iMx4MOYLUHI/cG1E
7pXjqu7PXJMeZ7egyBq96AyjEBo5ZCQX3Qrpba8OgpFrYaQZlUqb1GxA7UTIsMjzFf9HFyqyabAp
GpOmgHoVmfrJmoxlHk5OiP+mwiS4PHTukN29SxHYG5JgkCHjz5D608aP7KuaCMCkwiQEHqioLsrG
gwHTmHd3OZloasSosph93Y36NDrQVlk97c5LrfeddWnCHCl7rfSleVuTWVpSAMqSENRXRsQX8ozK
XGHIfsUGJWt8f/Tbqi/guFFxLypwTz7ktYMN99YG9YfDUvztc9vB2bQgTjuxvKt553OiSPIKdaBa
Ovx+Y3ZT+xEDbm2lsKl5Jg0l1S4QJWkjyC1rR/4Z6yytKbJDDVMRxmZQtXGPrh46IOaokWg283B2
IMto/4WNxbMQ8BK5hz+kECYPfSWZEepC0sosYtEElrl6aME3/rH1e+/UYhWAsRPgGY8EKGtbv9Lc
55o4dzGSvP5aZhtB8fAsAziaWxgUVPUC354kPa2zgu3Bi1730ymSCP0Jm+sk/FcDbHRPWmzMRT4D
qdRMaRP+qpxZnN2Ez5AY/9YtDWNFYsqTA5yDljRFl7+nQiHgz9RdVScyAYjONfoLsKpwPXPeyeYK
SxxSK6W032iFd0dq4NSMBCaZ5g4pq/xFvIJiYPdL03sSu6/huwTbvNischoNTqxsa4LC8DvYzYsQ
b58ZEpZIbkofQM1vFXyUCgMO8FOrIf0EkSYg62IVJKK9267AajIgUW0Jc3agFBOyGEMQCDaUT1d5
KF+DLQUn2ZN6hVE3B6lFi/U4Y0+HP6aLgVXGzPUu7RDlV+XO0QJG4wKWfrGZ96ODbh2Ya3yYX6x1
VYoWjcLLmPrnVSPOgWmNikUfxZVV7T+Et+5AuMp/4HExsoXazsi+0t1WypgD/DVMzZR/axpcO5kO
HhJBFfcquc1Vd4G5DAfUFEHLZdT+bhpAybYzz3iyZOb4uZZy2ZmGFwpHNkxTPNlYnu+AU8gBlgwh
XBUdYVKZyuCVUtA2YEy6j+2DIYJf9KLtqNyP7IlnxjZzQDVCjdGW1oCqseISigCtlHecH44Pf44e
Fx1SBWqKTqnzI5dpEC9WOygT7rb8A2X+yPdCcaUWcbetcmYz+QPrQNBwdIDpk2pd8zfioUjL98DN
X/37vL7tAnjEGqzpllTliwrFaxOy8sYYY0R55CdrDC/+8tW+7rp78jIm1tTi2xZLMcPKW6dfQTBv
AFDLiyCGTeq+hU9ZZzigCGzmWmewa6hVsTaN5aK0Sn+W/QzZoQfLj4QW9x+B7QSUQji/HSvq0DQN
thIrpqgX3gTn10lNC6J0i5v6z8s1Ifd0e6iUHIQNtkGbVcGUY4w3WXwJCa8RSn7pCNIOpVppxlzi
MI2n1XlIckZYijW30rSBiRS4mBmZRDuvZmriMozBsW2qkSCrj1diIRaJIt1N7stNSIeS1g6OtqjH
5+rj0pBPJUN7Rlk8zr1dyJPyKDjQ8ZrPa1GTz/uwlSX+aMqQvQr3WKNc6XU5uGwgF7RybKcLWl8W
O76unDn96QBGa5trIvVWLJKFMdFSwkTkTWQzlq0z62u+UtVYX4g0juIPxBY+cDbktFh3WyXwwcD6
4dFR2CIDeE4JRq7Jra43WT2nparqx3nqVHEZkqiiiS6P7beQUUwwunn9o77YEYWrwBbJG/mnHmgc
+9YGCiexnXnQokSXOD7caEBRM/h01+oVIKfGvdPxoRNxsGJO5f9fAD/qybQaXC5qHtxVHiDVFp3k
+SGJvazPcGovL6LVZVIrC3Kpke9XyRuL4/c7erR10evSd3GofyjEq9UrpbymbBdLDTeZuEYufV91
AZU/BTMP7jdfMMcWEPg0jrI+s1pwVBgRRvik5dTOCIQCefKuyhrMGdJTVNm6KDE/wxOqpVrZnYSS
nhMg68xWnSxAPU7xcgjxh9qI4Qt6IW/FbGSd6Hc/K656exf1VvOKGm5ZjP3O59YSeOKClMhHlaEq
SIFvJTuJUgWpNvWXck3ZI5EcTqK186PjtmyTCUfpm4SKEvRm+f8+p04mr1d/dNg9+Rpxgcab6N5n
u1zlVTKkKupJNaHYB83gsY4T25BSsECy5I1CFJW82EpP3r5noPk5cK7D2mUfOra422spF47Xps8j
bCNJ7l/gP6nvAgnlb6GnUFsKSabluk475SI6qVLiKUWHrOAyDc6MH0QgX0hsXuNVAimYXb+JUn7v
dqdEL51zKfAk9eMw32dnQs6yBkP/lxAYsKJXN1Y4AEgMeR86JvxAR9JpVrRtQEsb7X33gfDZaIG0
TdF2sWukUjFzkPK4E+L6ix//a4kI08Ed+FFpVt4cvMvMT9dJVwKcf1ydjaQ9HrmXL69OJtMV/pop
0eeXxe8ZfFtwO8sRV190cDqDmIZBQvfJ3puaNk0mHAA6683/sJ+sw5qDSrNNjZSOeqH6Ro5I1bMo
JVoeAsf6+mAzcoXKKpouG1cY7erApu2aAj0ZKRPIRJxeaC+qS/aLWO52QCR01mZX8ZI8v6LK5icw
3CUwTMQusturjyqASvTylr0ta92X4C+QIF+14aUTNClTj4DcLZrfuhAqjEgmlz3FC7dn66cEAu4e
ECTlShGjwb6dMUJpdZ8us0W+u8lHw4PT1B5zBQKbEDzHR1Hnvqqt0D6vWU/3KKwy076s6JUKAF9/
P8vJFTVhJ443yRqf9NmvlJiGcw0qne8HmCSW3935fLChUsYhdtyCTNWaaRxbvj36wadtqqp9MPUg
WKzd3FL9zFIvuF5jKYAzIHkE/ujKNq5Muwjev+QF21wL+189DT4ObNhS0SjgWUn5qu3XYencGCM/
+HBJUDUagpgKbfK/UIe5rPtGKcJ5rzrI5SSFESoNwep9I4NLiyCoxS2BeJYYtyelYn13oSkbeGyw
UexQJ/4xkSjvkhr2cBBsuwRiYQqQdkjUdTxxeyB0Wpqzh57Xe8TC7DuZ8y2dI++jXT9qNO6QzUmy
4v8LSRkTx05Z+BHVos8LmY8X+hqpEO4dDHoTEoUodoY7SRY1wAdiMglS43ecYMm+oFTrvIuyz8t6
UCQF+dJzfULrehDhV0/EjjHN20Y7EtsU6a3D8BWPuueNkJY2iZ51i9gQTVNLjkifsKQbQvhiksCE
krv1YSuJ6lOPvBh7R1kgKfS2AJpvE8bMrso9jYr1AOFVrSZu4Auyg7GDcLduyVpXlGQuuyeGibN9
QsNyqUmmkE2fRY3UDf8zowjfO5fRCwt2kDW5VkBdtyoMDAQE9dWeYhSbvMSmziWJoGIZ/fmxc65b
mAXTl3sQ8Hjb7379ai+8DYJmTKWqHWsQadKZzSHN8aPdQkmmhNAgw5cr+kNAI1UtwxAuzr9ZOEvB
5lzrD/6Pz+GVz41YopbZ5Rg6oTbd9lsIGf11eSCMmKZDNU272+mZXzPCqYmhTHUp+X0GXPb+rOC8
VTHwODvVDI4AAm1hgFN/Pq8rOhUJ6OHMMNQ7r00jmaR3fZTBH4/VlG/wLW0Uz1/F5jVL2RinkltX
dsZow3zr/k2hcr4FOVND5/KkpmUBW5FKMzSbDw9aeKRZoLQ0XWX3TiXMYzjxHEgltAoaSEt9xnJl
QavHeQaLNl2L5HbuEq569wzyxMS6+3EbuDbEDrcOOFDGKQPYm6WhwljjYXy+kFZxlf/XAvOHuGz6
M5y/bl9UuBeL1tUhZ+8fmtC7ngdNCRbya9a5kWtB8Uq8tgPu2SM1qpj2EDh1W7oY0QqCj3ClnWPJ
OcARJ5e8AMX4Z91dlALgUDAoAOMgzh2HqK277U3UoP3iz0TLB9JatEZJDAd/WJORehMwWd6NPFm1
yA/dbC5ESIqVOW0uA4bFwJyUnFCorQK/7eYf/wu2iezCm+i10Zce/hok48Wk7ejLGsKqO5kT1zgz
7zyHu5fiT3gQwcAGGkClE3SPFwPDmrbG817MIqXTEfSV3hotop10gLvlftT3eUQJM7RJOtdu1IZ6
6EiOq3IeYzKIbF7AsvAATZFGFStCimCjIVHNZvmBD5z7szBsawuSKQijXi/YNeuZHKQgAV5CQTA4
VCCISjL3hc6WxVFUcyczw8TUUlJiP0ZM0FNq6PZFyIyyH+sTGH5l2hmLTJlg8X6xCaYiLfok3flA
agNjQU05VBwY280Lafn9PWFAOPeDncGaF0l1jEYvSF4CxRBEeWOe3khMgpZwbuOV/mhLSkjr+uVq
9pwhSAknZ6WynRSpQfsyPt8DNlbGJ8bHe8XKqA46aZZk+N6dZPPyM6J4rQ4FFxcFZ1FIcWWa8kOC
CzeFxYV5GuZGbpJLGG2BZskFzTk/9BKcQcqf9Xlc3lEaG4khfSyptaAObNoqNYT+IVQTrpjPdBqr
Rzl0M5dRBhfEIQN6+jcvGczBFU3NWbAmt4C77jrAeBV0dqr9ky4bRGq6UwGhZPxeOT/N584X3m4x
W+PUtE4o/LE0crEfzH10Uol8/aIDxGLeT8vlyvN20Ev5LTxZ+LSJDM6xcx9b1wl47/l70le/bQCi
EpCWv3s1SZTcQ7NMjlzrEU04fQ7mmLJ2OrtHk7j8lfqQzqZwptBwRFIcZjczDIEFXZkfNDbWOxz9
O82musEdEynQgUMKThu+sY4Wx/9TAgDvwKIF8Qo0lZpE60Gdao+rLWQUd75N7rWNZXGuEeP9bPW5
GTUE05Ut5gP6ZPWCx2YVVokCsucvpxrMFfNq2uviqANlktq5FDyqYo2GapGhin3Al8BMtYsvkr2w
OMtdAyZnsiksa8rI6pENAQfcfmZG2xAA4nzk3PcazwSlOfUhI5oWW2bz4+rzhsi0vRsTGVbpV3r+
NrsrKqhaLcBOe6p3aJADr1NT6zSqDfwfGPxCK8//vaOpk6hiy1i/u+W67hOg6/i0UURmTwdH2vvq
3c8FA6x0S3Pi2fJ0m3SC3TlWp2o8KogQG4Bh1cp6ohhtQ3gx3gU6EIRemW7UOZa/2sZfAKkGUjeU
BSVb6wb2lx3N1ddNb1gnB4yre/HWfOOLlkblEjETkTsi4qt4T1Z4dJ4cBgU7SV1tyfxOm+vkG1YP
SZvpxqYrJcb0B+tGqHinMGmjemdqF7BhOcHE8Ry+lqVLhMnujgxrjZxQSG2Kh6wkallN9JeA1WsP
AFyhhHPgS7lD0TbwliIzd1wKSrMqZcGzUKqCnrkzzlCwOI5GGdroGtWfpDepCuzkPEsa0Sq5NyE9
42UfK/4c9+6Dw2IO2zdIyZwK17baaw0KGCyRtUYpPPkIEsGWnhYs8QqKWPiyINNd7mrNx/bEV4Rl
/p4g3URMCE+AyiYUF8wZt3TpS9bqM6+Els55gAfumZRS13MFAKi6T35aDf109GF0W2nfSKkxe6GJ
foG2Nu1OsP27pRTqnBEHtCLlisiBDo5hz7wMMS0alzgD2Fr5YG7bNHhVVYMr+cR5pfnUq937SBwQ
MxUlihkK/F7n6imyQKNuj1d4iQMknQvrShvqHGUu6mcCgGlMAx/KCnkU4J1fvDZc6pJCRorvv5NR
vyhUb5Z8qnbghIHhCTc+D26iQpoSzP2gFBhpVBbS1A5lDIuFHjFKGNuha9ShJDMg7z75zpfhANDB
mn8jP2IMjvcnrQezlRT14ppAKgdewp2K5JUQYCndVFBMxW4NSB2S4A3TKHMKmJJquicAILQ0wygL
XuuDuH4M//qGITK7qL8xv8vLbEbY8kVX4sjkMMm+PjCsblXzxWTkDxnXihpYkHHhSSeaRJxYaVnM
GPxM2bguhFYmZCdFA/Yllzg5OYhOEHShUQIY3+jonXwubjzOYlgLed68umSFr72nr6rM4MQUHin0
dlP2iMahaX6VCGb4hUEZHkKe3wu6GCKXLGzUEz7SeFHz1pgzp14Q6wVEI+RjwAPIuHIg0QQg4p+1
Gn9Q2qLt6A5F/EPLyL3HlVAjI4ZBWhEqxr/gTzF6Biye1eNWsGgP9OOEe4s77AdiAPAENed0vzvw
QdEvXHFM+DpTkfmqtp+Fz0t8jknXjBRWD/zv/0KKjnC5OcKpUY0AXMd4WE8Spqg3YJhggisZbaKd
YKaN8ZqvkI7efsjiuIxOjnCb8G5mRzGMojZ/hXhDWr5eP+U+d45orFdykSuSUYURyH1p/xJzwy5O
V6R1c9Gw6UPPpR5gxc85kSkuHkdJu85q00C32ctwGsEpylMVO6tv5FtuIPDSTE99Ul6eyrMjyFf0
bQsTfKRzaKVQ1p825tQQbDw62/HdZ5JOFRfo9PYm4AxQAw0bdlWKK5n/WFTvhPjDi9PoHFGdc8mh
YkjbUJhWX5wcQaeGB6tQvprfTEdmtIb23zG+d3+otwN3u7Uvi4KwJXgRirxEXPeWBSRDgA+atxtC
86OToDgiZfib6XpF0aS8+OVMta7JVZFP8yrnhR7YRaJcCjlr15jut9EUVLr18wYzm7MYuh7QnvDz
PG+oluakKuuQ7O7sVeFwZJVdTqLOz+kVMOK2bIctI3IYikNix9ZEz6kAwJwg9YBOTB0z93pvagT/
Q0ZZScAtaABykODtj/GfVe8AL1zo0VxNHZlVidAJT05c1i8J2WT0+zyRdS6oc5NEjxwh7okEcBkz
RRfM6BqL2PJeXkwA2K8rpttY0TD/qnkOoVxdK/BFilqNANiyJiuGQYm3igEWszKPI8h5Kpc9r6vr
5cauUMqOYUpi4/QgrmMxx6nmNMM6HIwIqdjzPqNK/S+muzFj9jSEQdBoU4NHtzyMJp4oYIFzeuLO
/nsv1Qq/DVL9ADgnLjbgkkVQXLwLktWtaaqNe9XNxPdhXFxpcb2xLKqxmd+nTAE9rxr4HC42dgv3
Nv7T7ik5WzlEJBJjml0IqoN7GGfs1CJgnWb8dwHZCMKmUVxyYkbJMsBwWTC+g1EC9TJHnbvhTWcH
HCKJ7Pq9QzVI5bYaL4UujErVOrnmtzRu2/cTQcbTnOLFwjYZVBvw1fx+X5kwUOsHm6AquUyAvT9O
TmSXoNNMdTWRNPj2ld81c2QL3IX6nfqcbpyMR5nyu3gtAKjD7Z2xYIRSMRjxVkvKvPIE9TKLrACa
ZPCAWOsJ/3WUTPMEKcmXc5RAaM9sJq3Nls473mHU23zD1mRmqHIgA2ExVlvCveyH7iI467n8ymTh
dqVszR3hhZKSrd7XWnFBReLjN3U0Tz8znocxG0X87yAjwG5xDAv2HSeWySFy6Z3jJfLFDVNwLL8m
H3FxRdXiVa0WMbMC0TTcud0sOEB65RYoi/JtZKKQIvq7akquEwIZ/LudxPG7b9dZqd3+pZU/hxRv
/+jGQQBPYuQ+ZPkO2tOHxNy0vBaMkpMBaZsCiA2m7W6IeoLHWq7VNTGStjND+Do9zI2extlfKwvR
x6v8KRrwjSXnP7WYdFWZ2IvzueQXEYwnEndvncpKeTr9SdVPec/dXuH7i9QqUXc4ynwij80jDCH8
x7WY2LAD8k2QyJia5i1MXeYUXaDinblQytasYDm7kQZGoXAeytiPC9E5MCB1K57s165vEzlmnq9q
WtR1eu3b7rkMPhM9koIIbXsoCSLuoD/XEj3ytVjEZNHqwJfPi9JgYL2aFbjYjMhbttjo9yrkNvxq
46epuU5AMN0ZblP6vowAMnc9IkBZJfoG6jmUV7i67cWxLQH6QTugSu2hJaXYnN7hH+5uw1k7u8TU
purc+FcnmlWWYzIc+yJtOSFgasxee/knWqcg69zhst1l/Vd4h/LUOrSiGI2oYrOXljq1ZUAGI/UQ
k4GDsADr0l+IMmWq2jFftnsKk8ktzW1JUIakTo31ALA4Gc+YTXG0k1KJdeqgxMBNI71HxTAfrVMP
xAQ5ChmP49e4caa3ecoS/TyBgWQuyS4ybMOepo2BIwe1CY8ojXUQ/lDRjUNDsPGfYjUzm0EhHDlo
JTCX64TVibj5GyZfj8EAEEUlUccEos5TETx2cO6PUFZcAZdsq6G5TvvMHfi7tbbm1Y7LzxIBcdNx
1Atl9g1tOaB7JqPvIfEXbeEybg9gCf582wcB0w2dmLj9q336yyu8I9+79FKOdq0Uif9pVRejUnhg
n0xMI1ZYBCsN5Ssl/PY9zhGQbvOIROFgPuegdgjYQPUhvDibJanGpVZYjY3Hs9qWR6FQZYMydjSt
ckwUmPiWqv7k13odxZT4RPLILFYz+0CnrCycDGrYOgM6XPQ4ByHEpOW9Mn9QgW3DsCOPyWdjKHJU
iG73umXVvbSqQ5oapQA129iXvGLf2LYhbr3JpgQhZ369t0q6x29fWM33QXObqDIZfOlKlECkUgoh
kDcvGc2C2qlzY8xsDVs9CkbYR+TTlS28kivDQjyubJFOxDXVuXn40U/BsJxblkJqfc6foYVdlyKO
DFpfO4ZLCzajlunWyJ2Aatt7Ynv95LzhbJSGE38Q2X/Re+W/GyNjIQk+VxeD2kWmPuBEnvym1r3o
LfXpP1y+b0aHJOPqnyDNjzUF7Oha2TSRmhpv8cfYZH1+NOsERB5ds8Q0rAhv1JbZhDaRLqWuSQOT
q6kL1YdBbRO+3/OPFHqZs9nHjGPXJ0t/daY+3qMDcQ0JDzyvXNRflmd08H1CR9H4js7UQ50YKfHG
bVK3mg5Hwtk+a3BKoyZHhBSHNBpGFIvoYh4TUiaXvfu601LH8n/eU10wg03Kt2Sda+v6YxTjd3NJ
BtIdYstE2EmfIiTLGHke6Pw8ItMYC3cBLC4YHM/AysZnYJJhB8GnNNGgHuSWC+TEgEXyO01rPckb
oETSC7a2hWkd4OMarBupn8P3MY9vDlsuoaKAW2hLGNJmTRgg5x2RzlFPCvJrDIzBuzITCsbzflyn
S4L9gmCL1PnayqULER6I9Ew1q47Jx9oaoYBDbh4IJdoF4y9JDO1dEPNZ0/qoKgdTNc3PyydqZ4cQ
A6hS8HumYmtDrCEwB//AWFyIgS48en0jCBEC4oYy7W8TKoPnY/OBIN/ybeIZS9L+tcSefAJdCp/W
AXWCSuFGS8vqPKFGXPI8rYAS3Ucwj9OQeSwAje92NN2ZvVxxCeqTxY+LA9EkYEltDB3bugoCPOCi
nkxDWrnfxzl9WRae38tmxp6XGNMkud1vsWzmR0SLRSpr2BuJD1q+k8fb5rXAJ/LP6PyuSO/SDXZz
zOyUgrVUPYwi7mj6j5URyyXxhzQr+lw3VfQWmAor7Sj1eyfmmBvau9y0YqrY/c7hn0frGzU1Mgz+
a7oPDtmn6/L17+VPs2tWSuCZq1YSRyR4eNtFF/BpVEXtMVzMzTp+5GCPKjAOgBJZeyQnRnetjsc/
3tAZq331ou1OGO6fl+LLNnOZebWPUeGtjkJfa/MDQrX0b20yD0m1koHHX8sodzLo0q0W0sZC62c3
t2TmgVaNh3OZDNoxGNiOfB3YGGOim1UX1OP0hi5k/sNmuARftTgESIZYfYbNFwk9l7bEc/Gug781
tCBJzUsewC4h1hLH2qwrUZRLKqbtJ0LDtPSQuojlLXeks+Z15naG/mcWvRCefV5xJ9xWxWILP2a5
n/lyMW6hcTB9XrUWkbVCekBokq6uGSZ7GW+fzNxOlbYoXw2GNqUYXEnpWLE7j6BmJgMqgiMPF45l
8iKUso13B3hdaWUNg0TMAbL/WqBbt06aRFV7g8y0PCcFCYgWz8OgjstRTH4dOeakQogpiMYBlUu9
PEUxmxrlDq8RcmCxDL1CTfljP+1JXG4k4VtWJiut9V9cema32GW7DHO/twF5QHqtm50reBDoeG6P
CC6bZNXHxbK0E/iHR7hN1AFhWIbuZsFxHb0N3/OvfKTymVhI+BLN+bHvHkQxW6goBtfz5RIOm+F4
VERrysuXYRnimywp9WlsrHIAhlNKCtAQhBzHQLqJPfRHkmf64wVRxYMe1rA/fVYsroC2aeLG7OHG
5oMS5DLxxxiJN/MRIEjPH1Fd2LVCuD0ktMXN8tuxBmPFvhIJTSoNPZ4P00Q/Z+zWgazOr72HCWCD
Tz3PljU3xPGY7OHcOv6uS2mHBioVpmEbn9vVaeE3Szi+gpBjH7wdcsJyW8ySOO8DgOm/nMMeMKqh
VK5jwFV4fsrkIUwHBXp7BW2sjY5zhYuxueStmf3NoveMKBOQdtk5ru4t1OLekLwTvFTM9LpKnU3P
HxSfBjVlTYEtQLcFvfqOF/WSb3VvQnoYZxoKejjWydXYpDUDa34SJjg3L0dO5XaAcqZXhWFvURcx
hWNqth61ylmVw46c2+IdnY3RrQDV98MBN/nhDE2oONpCh3xOh+mhhrIfElsn46pVja+bIWUGj6gJ
OhLWo8QUJjuJ6pQwalaVNICHyzT8hPpx7S1a6UQYZVDZTh+I1T7tqn2zsMGnQuNjWtH1c0cCI3+Y
YoEAEcwLMgDCi9jcSPpztrNNq30xFobBcSi+Y4F3VdRdrlszrto/4LanITwDB35sILFxGMaWqyDC
UnUdi2xNDotzWP0KnyqSzdZRb3PTxiPNoK4HRIiDgtcSNkXTfa8nQ1zO3miLyaOdBpQSo6rKojA3
wfGt4cjhJFI4qGPjQOmvUrvisGtri2JjtiXAYnpvf4b5lIPeqQ4voA+lQhsGSf8s4+n9TuIBVJTF
aw8xp/MZij47cE+mUy6WevQzddZcTMJSWxli3z0yZ/+09GWJQk6CqqnNo1ekJjAyvZtg/zqi7aAs
niWqzcXITDKq6Z96/bX+fran/rvc5a7+FGfNNW/+aPDt/b4Uklcgatlke3N9QVQZdOkBwTUrgjk5
kNRLUIfjwS6ObFtP+CuMAZ+63QtIjfzoUJickTUZR7bJGBx6Mphb6qT4GNpfswo6Og71alD6EIxW
vaqgwHyyB0FrttR6gV7nAafR0Ol3cBPrXxijI7rNQRWF/pod485lB+wvIz42FDr29orGQ+w8xUSh
P8Ylzqp6MXViNr0aSo+Gd+mdOy50mdq+9Smd3/8r1tII2bTIA/B7aBRNb7D8CkZg0Li9SQwnr9qc
Zh6vP/7ADiUGgfWSkgspps4eTRa/Z7Mvtk784Tju6DTGUcPh9CmDUbfkahNHU5pcNt/276UBq7wd
uyAqYcs4ytajVU4trrtqzCoKz6uGqlx021SrHwci8ZRrcTJe3r7Pu1wTwySkTif/07oRtGHndSzt
pgCnvF++H4SpxPn8Tedq4ks4ybnbJjRaoxj6K6sNHhlSqwgGPUb1jym/7mXY4WtNGnvya6nAiC8a
XOF40BE4sajeDFbJWkuHw92yA+XneZXLzPMd60+rVrgbfoZGBThjR+S5tv60qquz4rCi0SS7DMDs
63j8bwA1QuWWSn6Yq2duANutCyouB/hRU/X1AcLx1ytHH3qbS/30Sb4nQSKeeFkzOiuNNlaB8+aC
znGrODN0A4KHUjRWJF+h4e9Vf/Oc1mU6GIB59G/T5NFQhKTG+ljLqHymoml1xaod5ZfCGh4k3CXg
ViuFg0GSa9HHxMkos8IQC3AiHdBvkSAr7DAjs+vt3k2IIMljFe7UO4zeKU+AWlt62U6WnQU0AmsD
cBxJFwqVOw+761jsNxGFAtAAQ+LMMf/paSs2SKQlbOXkCtu04twABpw3fRG4XawvWnAmHsOiLzLE
5yee4XEWs3KEjTo7y8zMADOmhWSo871NtqVDjw5dJ9d15XalBu/k5slvyK8jkloKdc1IO3+uR87P
+Lmv+VfYgpv3285h1vPbkLB42uBiW0d6THGJ3bnEuO8cckhJJXClf9RrFj/F7+V7ACR8jk59dufq
/7NIyehRg5LUb7GN336Mhe2RW7G3JO3WZtWGSgK62iQjedF265F2LR/hGEXxPJ7OYwEXvPpI/nSe
XKELcRAW7bI6YnrDaecG9SyHQ0g6xjr+/plp53/1llNRvLu+maMxZIsvstRZdW1yJw6O86bnpBDX
02R110rpKoRFp9jEsSnQNomQIpLzWXO/fmaWFh74TuSoDWTkl6x0wJwoSf1rbwPvVBDsO/EKiG1D
RWJAaW9nKt8dOgND6/rjVbsVD0OsrzlztDqBneJl4mTeSEgUJwRSPn8E45eQtwpl641hTH3+2BPd
NBJjxNouQKJ7p6vvQmAebcVCHoBcBKMDtfmyYuddR3J5KFXaEWSPwh+Y3PczGHdoVA7iv4bGRJ2L
CEkZf/V7avaQ2e1mon3P8hC9BIjfVyeDfb6l9anHV2WHHvaMI06efeT1cpXvIL5r9DOpc9BLEqtr
bkqGIGbR1godkuS52FgyhvZVDN9pNLJisM9AYdqOy+s1/oQzSkPERWySsJVAJmc1brcoiN889LUf
DsYOfxuGez+OtZIyrdtqGW4m6qoIru0sFmFuy+axWnZNQKdIFPHijyR2I+6WlCItmVVjG4/La6+k
2xi2YdMOqfv5LU1tr1R1yF6fYD3BW+x0+n5Kp2I5PTBBoM0jWyIk/yRjJLpe2w8L+fKGw44QCMDm
SsvJqfVzStM7YrLz0IqZRrYX5N6Zg9V/UJLWdjhZu2Bihm5iaKZk/p6arMBJ8/AOyNIj1lIgQ+ol
Wqrq/dbYdeCrSKp7etRhx6WWRQLJesNYVkRCWw9B4M04xaVL5gE6myaVa5qXHlP3Zn7XlrQLcAip
uRJelEEdXpDvCyN+3VJjwU1GCz58CLZlSQ8ZNodS8ncg8iMmci+O7/AF0MAwsSUr3UICBAiJIO9y
GoDISE4BDBmFBSg4sdcWIwNDC5ofxSPsa/lZ+LWSsrQBQqI+I36q3VcPlH7RTj7tuPXcugDiXnQV
MIq8ciqishJml/iH+YWNm+3Y0WwdHUrFPZssw5rOgC+E7N41Wbm/TepZayEz9DJIammgORj1LlQh
ilSZV8XoQPv2c6wKk9ukTu8Y2kZeUspMx6Qd5ifgSWyJIh9wnU+C3lgl3IbLtEygcQuU9jZVokU6
+BCCjKV/AuPBEbAZC8B9zizlkTNJjtmpMc4GhXxks7pdgiin/Ikk71uTOUMyf1aI86Q26+qUdXGZ
T1lHlotJDEuV3vSb1i2XKAAevMWm9SOW09a3e3qwwEZb7fwmTRH9FHWi/p8AVPZCTYCuUup0c13j
ugowgDKGk+cK4qhpKGKmSSWmyWwJx161jHyJWlKmwEukjI+/GMKR7R6SnTc6ZaiVC5PmfeEB32tw
fu1+/oC5W5RP5FuH7wqRmyZmktwO5RctfI89R60BwUWnI/U10Ku2nRBJ4kb2BvMe4EctePG01RNd
ulAVLMynCfK66Z0iEddyCTMQMgbP508wjjSj3RWcuS9tCjK3X9XOQ0OU7viDpdEsQizUTUhqKpqB
KtndVkm/TmqU7kNuUHptO7PD0f0TSkHV4NrEIMqP15BBfwLsS1r7UOi0Y6TTPVSt0W4flwo1IR2e
RblFAvDlaNyROhOfhsoUmbsf2NqyIz+XhaeQLTBW1Stobmd6pN07bRJJyQ6doGQk1SmxsSfHyRNy
CbkBPAVRLoBvRTa7QBNm6UA/h3CQAUtA8nUuH6vxpZxdW3O5gwL9qbVPf31VtpE2XdK12d8lqmcY
Wde1YXE32ybu71uf7zB4C/rVM4DL/UOeuWFdgJ4Cvr35eYeGxQEufUEXcipVFs9ck5VqkT8l069I
LQgBuPeGs4XlH6MtftsIL9WKnC6LD40sHvkhRsruQ5fC3V6bUF88u4fMU09FyTs4H54kqu4F/0xT
aCOH6r++/iVn4u+AI36z3CJl5d07ZBMefGaIUFIG3kCwQ8IYM8XJugYmFXhr+fk9jx9IU8h6ivPb
euhXTenIlYxvLGZN2dd7jjKyYtYiTQmv/G1WHvpfrWzuN9OyyjOpyWYSNZIxJ7LAytFhve7sYfJH
ENBLtnoBNMHiuRcZo6/k/4j/IiiYbxOuXMklsVvgQPqUd7xew6K2bMzSd/9fuh+ibiBTLjmnwGNP
6UBCq5elX+BcM/pK6rOnqE13IUFBq0UhstJBFI6YG+ri+bZk3YLK1k5ohM2N2zd26cu+2bYIvkE0
FmV11k/fSQS3jibQ3+c2+eoH1zBSLSn8vGgHvFmQvHKw6vkyAfFMgPdKGoUctdZvsCkgCEKEHZYx
2sYLeJE418Z5HPr0ROA/f/0FIMRsN4pUotTkUX2WztK7fg9pAsc+g6qKmEDTvInBLu37alhgdQkN
HE+xeZGU5fsXQ6K3045iyTAVW69TlV4vdp+7b6A4wDw6/69Jlw/YYXG4YYUTy22d6dPeovNKTi1m
iIyiksGjOqq7qWyuiQGIBDmRaB90oRAPmYFOo7/QDPiezkH6od4vMZlt4mGE3wW/c7y35eyKQKC+
FaNKprq/hOyWSM3AHI+KgxgZ9d4YYDUPb8uSXdvACgpOiaevsDpCKunbQ0UhG9byettd0ef1gmGi
63fk0074TKa+zxgBA3QcWiSLAxhGLSsLTlzEaCJoN3Ut6daOe2KGhFSRXgDnZt5rsIpfXrqtkPb7
knmfN6PZAxawNY/AyxDxf+hRyS/L9mhGCR5sa/vH4Y0Y/MGWJU7zQNpKLXiFzENvAhSWsJKqgPCl
Jr3BFVMwm1C2yZ7m3l7pfVZFkqTFEJFs6kmBTlNZy0WxYgdqTuG/u87+pfo4xzMCTJtd6yIPcEb6
/BdSBZkPYM8QE2vM42uYoSPlxXWXGaQiZa/weAu2OajdBstuTvBWZBkReqiwSNFQNR3O+e7IH+Xk
aUj6vYmFVfAyH+7NAf8msj4Ok0QePiYmYB6upbgPjhuzlXiO4piIqhg14/ViDj2noMhUOBsIbS6w
DzyG91v32EVreZSSt0Ki8a2jhWU02pStrgX5Nnk8HwAxOiGlwiR59mKwaGP5bhiZtYiJhL4L/qOa
cEF7rRgjvS5Z5N67qEbOyeQ5yVemXxVVORuMB7Nqd5QO8OFM0OU2cgFCtO5quqto61QUWpKZZKCV
RB5qu0EXLAV1KfMrYJE0Z/s2cDPVxByXCwiHIEHPLO5MDdGvF3OwXhTZY8wjYjT7pEZJU/YUyV/y
xCpSudHSzZGWGLI+bq9/Wv07Ed0GQ+arhJdjeKR1wsF+TSgZGarR9Gsgb/+ndekEMBt3lKfvqVx8
r8bx8+SoIRgKZru64+NcB5Gy6j8Wf264IT9WdRgQUZsDQv1ONVY/JtPMH434tCmIgv3Zp+qUbese
vo3+jazCZK2u3sDghMhkoXmSQnnJNDxxvVtoLp9lopy+7A/SGwPw//xc+/k3EaD34aCxt3tGUFuL
YjRy6oo6/Vcy40pgiwipkEAkyOMJi9/lUqIn+JniuMyqg3GRXJIKoxSd6xJc2qcXlA9I8UsTrD0p
nvHr3ZcESb2qQJkLzgegM1asczrlpOZoPmsHqBAWDSPziEVciTJwvS3Shq/wv4eUZzi3Xd20USx8
Nk5hfV3dlj8onKrSaWTfXf3Kt60oYWaYUPzYscLbNCfrFsVFcwC0SxKJxrcr2RoJIl6cMtZZF1Gj
2a18Becjlg2PgJNfb0vFHkA8otzOpzuXhKxkceQDugS/qaO5nfA+mrs7bpPyLJ+3IgDj4UHRYO+R
SC1fMvz045taJzen3JIdxOrdSbQLIXeeZntnG2Pzuw3S3chQtIkfmtgf7e8FYxgC2T0LXKelD4Ey
CbvIwc/72qqgrqdESCZRQTP0mOpTheH9YRMBhtjNW7irm1eR9E73eYrJ+2TemcxSecZs67VVkGDX
GpHOww0w9PVYsdG/E228aN43NO19irB7Lfn4yfhV/FPGOc/grtioxowTLrKKp6umdBtAShfGmBlk
2/W4zuVM+hvu5D3GGFIBnsT8SUmZ29JbewG36wldXxoeWa/MbJa1jXfnzBAsCmT1nx/VQttSjpew
fDB+E7AgIZMFHWmr/f0rpZYGuPAwS2JQsCYKtCF3qxe9ITV3W6Z3/+VmxutKz/5gbQn3BZoF/Q1I
XBsojEev313qo7uyrFai4QRMXodnwdWX2YZG3tcyMGBJScQySqL1cqK9IifRIv3NSH8KePZ9XIjt
BJRr1l1UM4G/6gbhzvI941ynGF7XBTv4bc5DdA6QeWXt/oeUO8UGm9zemXyLAO/dYMDtWUIMxOUp
6bC+1VyF5QdVKTPN5FEP/9oPOic3qay/T43LCDiJym8JrHwPHoA0qHzHxNOdp6J24EeLhXGZ3gEW
n+b+cLV8F2wx4XRE5KeEuoyBki9MC3ds3deA23dIzbP3UBviW+AxiKAyXi0oNBnijNDLMFvS1934
h8rsDM2avdZPkl6Jo62UvG0DU34YfmQUyWyK0a3BzqzQizJLScg3xrBA4b4hEdLia/MzJUjUyRxQ
cqtE1xsaRq2oN2aJnew4cAmuOeCCve6v3cpgvMYYyrKFXFiIHFowKeRQEOeWPoiut+/8kaAiBUe4
qhViVQnM+fm59AcWBD0lxncsyuqChlzlHrZfTzCnIxmJAc3Afctw8glJumTLyNoLoyh+rswl9x0m
2mkiheNu557YDCVIft/x0L6y/FKqXYKRJC3pmc1b2hSHuZt6by9ZlOWgtCKbTqYGwvI2I/nilcOV
0w6AMoMkt93i2AqhygYmiGQpGbaPMbxXKkb/Sw6DUn8w++THpBMTiYqnCQHdg/amjwgfiW8yIRi8
jcutMmHBbwbk0bfCOKaLByZtFqnkZ2rx2n4mtY9YCmkHS//AfQq6p8iFSbi/most6rbC0bPepTzD
UoEGbkr4ia5p1tEInav3oBH7/aJRxML0trV3uuKsCjfPbgkkZRo3AMErNbmlHlwNVXjxOrCN3ts5
QY3ac0wCeiwULlCR08f/Rq7s2OUi/rkEfT8rcfmz9btVIjfUwDSKLYRZ65iFYK3MvZkTna7ayi90
Z3FXMqMPPChaEBPunhautbH+YgSBpnYSn+SdJhN8G+jHUGfCH9WQwv1/oJsX49Rc4imjP6JE4K8V
A+Nj4ZQC2eZXlMr5GHv6IrXkIgaDH1x+HvxpQIqFbUXIr1NRtgNvzbs5OQTvGFu2Dfz3Git5fOSY
+CLgzqPyD+VcSPJm4vltjfvnVy5f6Vvmj8yyAELcxyo8gQ6A02t44xensOuvrdoqBxdeHlISZAbZ
wLliF9OWtPASZJYhX23p15Bdwr0CRMl38GGyFvzWqWk7qJbRI5FMlD4YDy9dx6CMwJJHGgis2aDJ
AJl8efL2OQgVQ38WhuknY6UwpnxK1tYfMpAryaBomkTih9yukRNb1wStrl98nDW4IqGO4Pe2xAO5
AERE2Ccex7UXtgeUfzTgxaTuxvRlpvYfrJR7MtpS3JQ0boCh0zuph/bn7js1/6bgH3Av47G3UtcI
dHDblNNyoQ9iMjjDQvFrU8oKQaiZZ4HEHNqjULHfDo5Ij3cjTZlxnMS+VGF0FnU9mn8B4qm3Ld8m
95Uyz3mmYP349pMIfb03Q5KXgnFJs9sceCUzg/McLS4zeYMUMVvBu78CkR/t+6fkVn7WDYZsxmhY
mKYUJgkWNkGENBvDUk0dkN75bcHfHLnAXTGB0kKSvyajPCnhEEEVWngp2xOUZf0qork5cCAr+JzQ
/a7z/S8itz46pciVQ/LFUBeE8stlhwSE6grgd+a4+A2E6zjKQ3qhTcsUpSR/Vvh+d8XtHcJgSwVW
qv3GPrjZ9Um7giMhvSlpLQs6sGrhBRLahhv8tlGMk8a/aLNstLA9GVQAkdXljcUnkaVEb1Jw5+b4
bdYne3w+BKOw9NUfqHqf6XLJHQrlTWIl6dGx1dAAxCROqa21uSe76BlFZ+YmTyLPXh891alzcRWR
ubZ/fwRHxXouMiOQ0T6NKFt/npYIH4rYbRD8iJdyripew3WWnjAq+7x7PxyWiGjhBIVhgNyQiWA/
HJnphBS0qKe8Nu0TTmBYUeY2F2q1znMl0CAkamsotwkI7svhpjEUbXzWo6WbzKe7fPgnCrYHEz9G
OfeZr2X8swgbW7IvbM9N+qtEWgKcGj2m//CGQWKzlj5ufgzUCTERJUh2pfI/Nf8d64hyy9lmdQHA
bTY78gL4cjr2gw8Hj+wGpkAsS5IYgbRCe63PcSqE6AuWI8Zjsx2+zJHa6LCOUoLCui4GbAqv83Xu
Rsq2ATB7JG3Cd1oyheh9P2diKq0fSl/flrN+Iz0xxC4frXnqExIVvAJZ0xv8ZjuZmAW+cY9DoEhQ
Gtzmfch1z6Kid6j/qYz20mwPmjzIWVHvjV0UeJIvesngL5+wFhuXGHun13ajyr5ltFXc2YhosBZS
8dNXv9yjnb8e9Bdyfc4i8eOKdJJV368eWC3T+TLq6flJqngF9iIh1FGX4d5JTyBBposfXE/oRThS
Uk2qcp0RBep14so1jEJ0SRTGCEc3xlRzbvtclrGCL02QExeIIxSf84GAN7HYp6knNMkviMeXVykg
XVvia1mQiXqQVfVk45yKavOaDMaRonWiaj8Xejqav88wKtm4VEpkuLiQ+mgN3/OpEr/8hyJXRbZ3
Jii3fr8thdlOdjs6O3B6bEBkN+VRDtQ59QX0I6+8zMxOWcKsB/zAiZ4aYP8dj9fTiHkj3Cfcbujt
bDeWLz3Cw+YDZ1gan0lPaVz5PdIfR4GrThWLrUUiKKebGvVM/LkicpxasYsOgQx3Q1aSz7QqjkMh
uKxyEoDOtKqjqIQRHyMUlHSbcmaSZYHUBJljzN9GDWBdta1r2sB6csldQWhX8/75SizccaiamPa9
VzBRl5R1YCMjmJlRRKLys6DZlPVmCgWZ1OJ439mH/3sCb2wFgfOVskZBDPbVsdQyvDt5VY5h3HHN
qt7VrhI4hX/Zwv+Tqg8peZmPnYjUUZX4/AlsN2htKOuh1ts//jDq/cVx+JKjw8S6uM70c2C4S18Z
PoXaiaGQr2IOLTA7KF0wpoBGtqHi4VoLO4f1Ca9nxKqlN18de0NqyqrE4KykAhNMB0AAnUGxdgfC
rlIw9SAgz1mDrkz3JjyY5l5uEiG39XZBbrReDa+9GyNtYmpW6MSgS5MnjNdblgAK9RtAtc16qqvD
UYuVAP5Sgvom9NO4ytxaX8Eu8dc5Ehy8BaKIE3ZreYzpZ3v3XaoNPTXyqg7r2pJ7TcUjapIHmNlQ
140KANUOUdAZp5ohFDY7yAERvEoda0K+tOzq2SxFwfxj5UVic9yOEDzUiVM2IoMBZwS6QPjdeDi2
bhs0tY+2Q4kQYfwslWcDwD9gCSCXSYR2+A7tpLa0+Z100ISHWTHTtkAqvMRfNp2iR6ia01ADtznE
X9hHvhM+mO3nCz7RVJ0JlZQdyxZ1WauWv7MY1f76MfGgZ0os0OQLmZF0xdjMWAEvfJBSxPXDaeDd
YQwuzxNC0LpazFBFEtw80gRmxR8uyxVKow9fX/8Y1L1hF82GtyHOmngJOWyZ8D7BTNJfUkaJh/ON
wK4QhnOFn9jzkACb/RBb3K0QiKbswHVaq6WQLhK/LeL4UNDCozeb0K0u/kViGXjSvDuvaEr9lLSp
8XQWpgVP5s50UbRpShpAfBCqFSoHxd4zmwxTe7S6UGKEZbjk5rujd/gzvYik4f75MrMfD/xJbt+T
7L7QqvOzx+aDaBuIRdWCVRpH42pwl4m0h0ykBvziSdSNj73ZJn3oAAG45CvqxQDJh6FoOXrF6/6/
5pIyZ+Z62NJc2HlbcDFEh5HNcTbMdVBuPJJDGvNPbjpDcjQ/tVP3YSLcxh4YqqqMc3WHktm6EfMU
UFOXfdVvtKT/+EZ7/zmICxQOzwqQhfRv2FVhO6gpT2B7t58AV1nQqJ5s7djSO393UO+kj/NfpCdQ
cwSlurQsR25qDxoNYzSFyMbLnXs3MY+33G+GkO755FBM/nCbAsUbWjENHNyOI/ZcceSjO0yKpopA
CGgEGP1S7FG765yIb1rZM43Elog7QNk10K8TAkNj0fUKP3WFDMOYHxl9/1+u7Z6BCRL7iANCxolg
3dnMHNh7D2ige2e2GVydGMIYkX5ZRzapI4DfGoSFsbG6MO9so9Ac3kIxscLDtDcY+dvfKVijzyxL
SwijkVZ9lxRixnkktpMAFmtwHyRS6vwW/n+a+mQhEHH6k9Ni0Ur7W0mJ0O99OHL0gBjmM4WZVv+4
I1tvow7LoJJBKyul/7lQjZXunnFlhmF7C8xVnag1fndAfrbkhVbvR9Ejqi3j3DooDpWEKAJ9nDvl
1NT06aYuWNoScdYujwoH8XkgXcVzddhyy3wGLPuqOAKCX3ZAeh6xh2Z8Y1ShW7ZEQ+jLNFnBySKS
FFWDc3uaQJ9XVxZCe+v8L9KtCPh6ZdkfJHNaPZ7y/0qnEBOpyP3lxJl8DH+F/21aYTJULoH/g0uG
9qsDFKBFDYU2OPhqoyroAeR3k2ot0IYH/ICWbi8NP2tYmmUdldZQdRLQtxaFA8nVEL0dGVUKaCGW
xF/ueJe+uMuYvapsphdoVjAGRnmSF4zpBGN/bl4MklNEQZBMGBECOywaytadZB5KAfgv8ExO7FGM
VxD7mVYxf0D2D9uTHKOYKpXgMXnGW+XtDHXsmNXEWp9n57XJPFw7mcNZnyuoRQU/7ECtioqHFNHH
rNKHqMsWIfdoa4x+3JVnuyatmRxcwCB/TAC2yZmxw0EFJ51UkGWwW4yJP59eepeAZEwZvNXp1F6f
5Qjqxpqlcxnkbr/9Lm1mndP7Q8Q1t9zUsZqkP9JkJjhlqZAyDDZbN2GVTL3gszw6koI1pxSaNVHG
I/Py8FalPX4janENDP6Sg/vI+FQ0GruIIFC9BvWiJi7utEQQDAL42z05d+xTXbZ4vEJBf1HMNL5A
Ce73qZfLItIDlfehUnuQPyFkufnRX2dzEkMZh2JjEdiqh0DmPdheg+VDrFhLoN4SfHjFulnGHal9
fVf6M9kW3VwhwDRW10ockLmCNUTt6B9/j75j6TMaaIqgz6XtXTlF2oC5XJmKxhdvLhJbuXjkD2uX
cd7wVRyhyESh87Uj5fpxl5e1rsn4Xkee8eMlIhP10AIEFi5SH/+sG/0IGAk9KMHztfaUJJiWcHhV
rI1oQCrLOlZnc+EAc8GOSALRk3T3coinpmvvOTPDCe0oNlKpXhYN8WQGhsADf+HWWgT+b+DI/if7
3xHzAgLtTxGAJ0duZy8ikZR94VgxnTlxbVr8zMYnEhVzxf4P+ZPnVNhpjsQ+45YfytH7vYHIBVus
HJKgAl0EpRdlej2kL8ly5B/SyYq1ZhEbqr3O/4eMcfVP8MMqPhjfFCfRRJoi5HXcsDRWglkBQDkG
ryK3SnpY+wik1yYCsJgWAUzUCWCzUWPAHI6L0jSVwDtJiyFMqdg3KEIZE/Hz3NvVw++BtRb76ji3
yKbGyVLP3SwEsJRn1D06XRY1C5wRbe2r1hOcRfSRF1bx5E3NFAa6MurG76oDauGDCN2jZgNzeQk4
Aqh9DElwnuVBlyXpp88+tCMTpgsbjYKD78LCtP0swwYk6QYLisbMi2QHXf3qVE2XRksxHZ2fcX5I
I8jFImQkEJMzZPLmTJs3uO3X5s1TLTmTcVam4WdoIxq0/qaw+w6KVqRtBWzUWizEoqAXub83SGLs
d0Uz8LfP4f0kExZQygdEgt2/AQ4nQx0Esih+f6ZT7oN2YwI/mhZgrUyqws04BVUbnoTFrlsffJr9
vQeu2/y6Sw8d0lrJUa/rQhVmVu0OWsr4bJ9K9WL/ybnV7ZSvJ0xRTei+FLKjEmWhVd0sZb6MfRms
abYtop5RD0N1X8TwrjEnIqNVHUlHUZPnPNRSvFtwl3aLN9U3R1E5IiyyLpT0NkaO5i2Vhq68enwJ
Qg22qQcy1CY3uGY8VAaUpH2y8GeWker7lNjmP5yGacSROmyEXUcz1uri8N76xwz7sL1BIk2IKnZa
9hbCkihtFKBKKpwJyYiOV0MRmy95jSkO3w/KA6/amy0cI7Ma1H+ie2vR0PMqgC3qoHRnJ2iK1Izd
knp1rAOh1Pj9dQtTT4Cj97uStX3k6uSffxHr5fqh2myhdrUuM4ix970B/HoQj10/Ld5RWk07Dp/2
944oMD425Doi4RSXg/WEP89KGqmeHpKG8VdmcwAgjwCkFMke/ybbJxSTby9En+PXIAg5BUShAP/S
ri8vTFtX0O4rEnVG4FUiES8dUonSNIcNNipj1gnjgM1CXtuCZkf4R/eMg2P5mAC4yyRfZHY45mqV
OJhKR0Z5SknDl0aONeOk+gfB7fSyXkHxBqK8iDcs7zskvopIcQqRiOGIPEHX+O8dKkl/RqR/35xt
t5VUPdEYZKLDf2cdkialE4fL5B2dqa3XSEL7wAEXqgIP8hNgd+KpDa7A1duvFqpWAbG/5vPPnxh0
Z+N1K7chh3UoS7Kr/lnmZXAzMH9b7Iva7JZBMXp9Y1xARQQYcd0XqakweSHmZ3XdhRt8gp2FTfEy
5lv9icxHQVQ53soaFhmCCLqPiSNvVHVqTcNg+SdGPvXZ03twQdmAMKYrGjPuWIbnxsZz8FqDNGC4
pGhc8Pm6htq/AxbHNOBdVAhU0uTMjHJXjCIDVvisIj5QJLY0OwCIOb20+h2k+ZVuf6gnWk8KkSMK
efXxzmlohblXGGeQ0fIK5pY3FRI1kQjOazLbuYuAbJh1o32nRrMDYKLaqXfun4H6HBf77bQ1Se0Z
+aO4AbjchzoirPRutae3Mx7jZ2dyHYYg8nf6mPNrOcH7BwlF+J/fBvmfRto9gxZNOzk4hO/+fNjs
i9TKIYbsu39THMNpIW6g1RkDkgEL/JUumRI7nvs/je/oBLPccLFCfQ9EM6KmPD8jpgX9gUO8cnb6
4UnIiMNotBXhLNsdefP1n52xyeewrKikwJExipiwyHBby2u4W9oV7J4qPJlz71n5e/7TElnA7CzW
YeNZgQj2vMPBhksZorjGJ1Lz5cq0wzbTLE0yD5ecP75kgaDuV8CU4TbxTaiMva6salZYgNnMtGAy
lgcYDqgQFdERrCn9F9ji8rHR6s/r8yliJt5ggHsCGzQVAX7rxGhjZ9Q4MkhGcX1zcity4TYyu1Fa
XUPCiYqr+e4kIpk+9df3yT4O9Ns8pt2ixsayHIuAxTm/Uwt3xsrxvpmjYHO/HCpAZojqwT7uFUyP
C0CioL9qyqlbt0901L0zBqbgpkC+9tpYTcQmbrpNUW2rSTxr7+pV1yb1RWDaMJ1PcvfhLYbft14W
TdWI0ysARSXdyJFyATMT6omBAjgMw08r/GAS993HcEIBBHUL5PON8SGJ6P7nek3Gmsl9dAXVJQJx
gvUahDBCmmyIwPDqJV/WlMF0em5Hmz4Id5Q5uWkKKYHF0CCc7FKkCYoPWxjmDiVTj0zT3/YkIRAB
rj5YW8fQkYEGBKfqQIBU5H8t5YoPiBFGgvWW8NxXlCq/ZKYupb1J1YvdMYweHfk/1KXAAw3Niu1h
4DYtcJ6CIbNY4bpMol3sxF8HOhISmHTGDGnrSD64hkh4D5ZuKg3SizH3uuPvCVCuHiJXnRpMOb/q
dU/QnDFa/15huqZmBFDsFlo3zWaSHk8CtNheMYaj/UYIIRCST9S5CBE2wJepebTMydjLjAmnlDoF
063VK8RBYPLiAgJcW0/smtqFRmEg8zKLYQreQbugcZ5kqGNIsf2pWhYc1wRn8upTW4GlI2G6BGxK
I0uOEsp/BtBUnev5caKSqvW8zmSry/esCjCPmCb4kJ7PpKmEnfSZiUiwWynd60gPh+Vw/x8nxSwT
ymv8nQuN/kcR281Y31+SUdXkzKxOyIyswQ9+aOn2eAHIvcsc5xQ6zy9IsOrYEeucH0tWxGqNLRWn
pZrNe4KQ9ahe1Iv8GcBPZYUK/EL5TKkDoEYCcilhFbq+K5uzFedoA1BsyzeWgY1NzzqC9XmSlq0T
XfQSfocg8RG3EN2c+xLCMvIUz7uFtKp0pmZI7erq4HCxlvVMqUESbY04Sy7FvdF+bXx1rxeKjX19
u/D2FpGXHNLeh8dbNkEet87PPcozzSV8OZuNXf8qEb4N8axjhbVVcZG57q8RWZ4pITOdCUrQL7k8
0X7OByfjJQ6a5QOysbE2x8l+3ZbTxHvd2IQT5cGJ4lw/S9pub5nQtgrt3/JrwA2I1ahBo6pITqgy
khkFCwaFXDkGqv9rJEYVmL00F6sFYi9+iwe3YxSDhsQysVaCl9FRKbNWf+qfnExfh4wqPra35KNy
I0i+4JwDqNXCiJ8XFzdzDiIVE/m378tjAsQM0hAR6JdCQ/EI2Ysx3cZOpPY8BMQ860kB8Uxst6Xv
Jo5VbFdPneUsVltczxJPhKHVxg2sim7b8/2wmMXwIk5IJE06wGm3yQSqaBfOYlP4Zk7f05EqFNGd
PWw3/pUXN/DBCoi+RqQ1Zrk/nq8eJiNzNIYkbvkclXzGqCQcuW3ub4dS6bHgssOd7bXJeFCDgg6R
ap3v/PvkpjX9RZS6X/KTC3y50NMoOPjt925so8iA6zPbQywHlHA5a9iuh6UsU8p/TKJKx2IgdJMF
ez6ZWjigP8wfXyInRHeqiNb9EHH1AEbJqi5zmzVouA2NxPnNmvOgAD5nadMro59UoS8tdU7MzL28
ylnZOrqxYYN1sa1Gxkq+Ez/mkX4qseXwHES4Es8zMPDdmYBmSJeWV9dxheULUCYGrWVuz+yD/8ox
0A0+nIlKCk/ryb+TaNZ0twEwBvH6zAyiUhOu6Fq2xf5PvW4baDjUJbZOTsXhrDWJAQJQifd0JsbL
FskwXDUrUMOFWmSlmCxrdb2sjU9YDL9RBfmbov6/ddvaxqF5z0WkeAo8fHHpZNj51L4ItKY+ibP7
p6aOaxo0PfYy54+//dn6g1zcz9NMWTTKf1dYlFHrjx2XOC/J9IVKiMxWTb3yVRdiTvqQbH4jnLMG
nNEoduej5yI7MAydH5/tQ1tytvXbDOOXSha0c4rtW2mds/rr56fESfyJvxUYGj9gCCEeJ3HQQt1K
h412cEuWl143xbYSAM3NLAJGSYLR0UrQExOAU/UEEBh/lsGY/5anbg6qjqJ/7X0DhIb2Dv/9iT04
R4uWpJgMzzLoBE1PC6eok//7ok8QszO+plUfH20DitVel7itiGQVTqAFQlsSFMFEU9dehVen1FOH
+Ctf1EJNYRjO3TtrGOi/3200M7TfKF2SDAnsXCo7kDrQKQrFiJGTHPRB3Emhrddy+m0f+nx0h5mk
uJWAhl/sKZkYIfZckW+aWBDaDKxumFW4eQXVxuVnFKnhfe86GZQLJQAz2lufqsi6YkPcY+8tij3b
jDLtZbT/Ccv7Jr+3XNBusH0BW3llSkJ9tH3v2gIco39GGHggs+qgGc0zqLHsoIUOlOm04N4vdK2V
dugCW6LBrZGrJxYUn8UbmrcmTu7NV7oM9zCt4fqpifcn16dm3XGxy7H2WpEdhY1htPa/rQnCHXUP
hgfUklIaZ2PJIcGfcgqtPYkxgc20EsdcGCepIGwR5qFnw6q7jBhDUcLC6SiOIRdwT/9t/7gdV83+
SOVP4SUGzfSaCKewi+1B/YT8AcLsHBeZFE0gv7Zq+qn6QaknltNK1/T+tOy0PIAddF/QwpUQQQRk
qdKjuISvNqRJVQWMaijDNhn7IjPu3b1EUink8AKKji2eK/YSnylklZjLtMe3gjDuexqb90fesC+I
xOnpEf15krOJYgE31YMrXjCglW14ETIzxRYrIn8/ciAywIjCkEZBxZjEKlgFB6WYcWq4hkwhJcVT
lM/AehuAqr5cUVQeQ+A+QybjH2WFxhomd0QuzMJRAKZlRhIvheblIDltYTpsO8Xvtg3bzS4LqoGI
/YWvXJzns2qLxcvv1nO/Vz+AjPT4O+D2ZkpwfriN2QegBixLKO5r0ZqQJ05JhOcpn1WM/gplAO5h
q9zhGK9FQ+23e07R3m5yhqUwHZ/ltfZh7hEXhcv/ncXHwf7I4JytQYLE16dDrt6gEg7Pg0+R1mrV
D4w3tyHwtAnIbqAsBq8561dVwA1pXoh83ZH22mYrebBmXlLwDbWGLvqTqL9Q7IFNcxgGA61iyTRB
hTjyc/fbUoa1FWRnOE/Ho9viU9x0r0a8iQxfJ3pVjP30aTH8rrY6GrFoHGZLB/fTZ0I/no9Six6R
tmWrFRRGY9+/NSURd6QJIyU4QHWVqQctUGT6STcb5JUKZ+XHxR5aEZeWkKqVoP231sjQTzs/p8Dq
qNxLsBqAd4mA4x816ut8B0z2QIyTdzosL1lgmoTqhAWjEYxdhAquU4pxgmqYCjsmTz0g+AnDnhUg
yEP7w8GV1q7B+osddrH/mGqot5ODiiKYVdsBiZr12npLk3myJpd+6ruAWCrxARhuARav3473CLMS
kITtdtScoXhy59Nw4oHsDCNcio4fcepgyaLndKxH8v7XUU1XG05/EXQgTverm8LuSxzAJajzE+19
R8LFAuiz7vr+wsl2bqSWztHv6G+q6ygpKPWZtJCIvZSGQl7lNSK8LMWako8dICwEY+VslkNc9N84
MCmArCB79Mw0NrOtYfZ/vdTqXgIgS3NJiL/WyuLQ5zSnUTP38XvlCwTtHH1lRWXU5r4UduTjkiSi
hF/ymwSUZFCayB9A/9AewzsHZakZU0HaFIksnktbQ8yR+ePGnd/HI5PIgtv5A6WOjW7HMUmWNSiB
MKdiNzJ5VIpbn0RR0ogMNlLPXhOmcv3/MVibW62ANcRYwcjhhP2jS5Ize53CIbQZd7UgQfz8/1Xq
jIk6IIKHYDUloYFgR0ykEKT1/PQF/2Jyz0jZygzqIUXJOA99Ph5DwR3CqlntHhquf8Kb3ea4vfy9
HhJXaA6T5nRXyE7CWG0NkjSzxbWiwkiwNIJ4Ndd3zO6glsdPOip3KXEdb0BxjPAqFf7Ccz7eLXih
eGZdqGPaXEqmqz+UsHS6PuIoffOLbm5zsYc1enewVzE46+YNxwFtTDMSQ1jWapdM2h3H9wTLtrDV
k/2ypsLoGzpU6fAiC6Ff8frf9Wg1z8HuWIgMf0w8lSWXYYKa8H/oOm+8v1utQaczPKhWIKHp9D+6
9JxPC8cdn+3wvbkTvA0EkYVdqMQgcv49emBUl3aDoTC2mMpYHdaoQayNoVaKjzMGYPtJslqhAmSJ
gdAotw3D70mqMO2FkFf3VrEhamx+15aZPFH+oJU9UbQRzR6DZSJUlF/XM9UHO2oosraLAhZqi4kZ
nlxRcQj5auP0mWRB6nIXw75fFOllYLJ9w9A46aLWAQNoH8N/5eMvFRU5fGcdl7Zi+tyeA7JKWyKv
5Jqr4goWm3HAbwJabvjRX+9xZJ+LRSgA5CeWQuKnWFQ38jjyoECdJbuFibwBaO0C0CMKBU6Dn4am
uwXCTVQgpwmEnUixCR/p/dvT/oSDVG1tNwXZcBDgxZenijNRsZdwT6u/izUtQ643ZE7c/dCxHH+l
L5m0sA8LQhYychJHZErJcLD3SHPoALs9bPbn+I8jAKYkszOFuTRvAbrU+mcwhGfdAn0K293xW1Ix
LeF9Wb83Id9GnBzGa/rJlHWAcqXrAKgoDXf0eWdknmYRuPUIHaZnJnwstjdIDchdB/ZZRUM8LUop
hh0sG4Bhsb6c5WJmqleVS2OcjVWDYKNYV8DhBGoeCMwRGO5oXMBWjFIRaOghTboko6UX+bQFS/Kd
MV3hEFDs4Anbx9rSQf9nIJAiREDdNKru85YReTavj+y15m2s9EdvCvx1Wxg0dllJx9gq4JgIck8A
5EiFpSu52ZqdhAtCHAbiJC6JxDbpf0X/7x3B2Vjr8RwQM6825izr9t7z4BXszdkNQl4wlucV95ix
aodd0d/TIxceuTVa9VOxU6NsRbhWxQJ919Vk1jUo7z+yU3KPLpY1VcxoLDnyAFEkc3zrO9uiIyb6
+vY3KwgZUu/zXpFKlaquo4unPlST4f6x/zOtcjoJzByBE6tatYNswhZVWitsRepIOWilJZBW2wLk
Jbjf306C0cvcyRbKvBbElTXoQBdx+/DSmr5eKrIHo99PfAKO1yfBzoAfNDadam9dfD3JyG/8v9u6
8YYRwJlEsPYcyJzAEzzRhYaCWq/VVljMLKloOrFQUK1bvl1DLiGTFbWdpm68vkBAOD15YN+qcTlR
iarrghk3ods2/fdtezuoiNT1Ym0rug8r5203oYwhZMOUErdFotzySSBMPWCEU3uyggoYh0GqSTbz
9BxuYiqZqHsQLB9MnFXA9mjoDcuv96wtP5tLj2GPnbDn6d/XmeS2ZNhGA8q1rxmZZ94zqDFjblE0
njCU4Iytu5y8w/IrU10amL7V2xG1ORGlunXIws11AKps7KyOR7qO6s4FvFk6DMHbD1IAje2YYxXb
bsYQoIok7dnD/3qLgTeg334KuDNLH0FqFzbc+AfRoLMdPipEHLzwya6yt4JuerWMgJHsDXZfJBFo
RWoY0GGeBTjAuSlx5w/JUP7hb5tVP85Nnrmv4nbBXjy2D39ilG8ceS3rX1H62NX8pQuV4TCmXx33
sOb4YU/1XP8Sxl0ezqDNDR5HCSDYHMjzDBajgCALlxCxf4l1BNvl+OltmsT6n7B8Ksw9RQDxjsDF
Sf3VpjRekdhZ2ACcLUQkdW8adPw/gXXPus982I4FHycCt8RkEsdFAic50bgNLSUZfbhpwri83TZr
VugtzTfuim6CnSCqnKbyD9tHOOE6fTloYoNnapN3yCEwhCdWTAWOJ0Tygjrl80bCTrrirDeXR7yi
9xDV4tr65nF5fe6JdNBL9d1KN36F3rs713OJJtVK5ksJymk4Q93Op755DLdjQapgRSqzvfEpiWKr
9bsQ1d6udLu6bO1IJ76ixdaYxG6cMHP9UFu88HajR6zH1Ja9+s2GMlT2Xf33+OiwqAnIyuIuZt42
3+vbgJ7xuuHoINzjyw7ETstowBvDQZVPOj/gnsCaq2/JQfC7+g/bSGlj3sjqienRGdiAuOQcdo0V
CMBXEVIcE1uEpWqfKkj4UqbAz8axJlCPqKoIwu1YDrEEjzYm5RnHA4s6A7X50pfG2idiFHH6FArY
j8IUIIC5v71MJAAHIRPkPRGKnLdGuX9PTaymrKdM1Q+91lJ3Y5plx05L0o7mwHqy5awfQyOjpv9h
BnvjSpZT/V2NwgQTjYDpIyZCyM8Q5xWdiyVpMxLNa/WOX22EUeOEyf3pCSgqMgDlVqbGwtQ4fpeH
WsmXYeHJhN8KYhzxzUQ5gynn9QP7gtH4A2n3/rNV/HGoJoOMnNxDEk/cikxnlJRvOvKGI2umWTSX
1JECtArQcO/E/+p3NwE00GLcosu9Ek/HEMnqSNZtZyjznxm2x4hVi6x9VOjyiW+6myg4Mf92c7IZ
vSf9UHRTeKahGyZVCO8E3CVDF4AwOEFo/cUd4JhgUeJcgM0+VdB7zcdiN9S/HaUmUhBJ0blSfy/F
bcb5JdOIXfdnjIK/J3/DTh8Is92wfJ9rBQBn8VH/b7/jF0Tl/PBs7jcohrjdNJzUD8dXiysaXW5n
WJJqU6rH0AsvTSOXffwJ9RV2lLyJf81+U/4BsCqYM3jsP8uHAQdMLTAXnV6Nf2ng1ap8zhILoOiW
3ZcZT4BvU0BIzAA0hxdgP7GrJ/JcqNL2HGG/PzBJvtEDq9Rf/bnv7T9pNi5zFoz5JKQDry+BzRdU
yuAgkNxY5MdKbREg+OY/4I+2qep3DeN2SJC+Wc2tymZ/ItBnCJaaD0gfbIEksFBS25WdZfrKwoDo
8AShpOx4sJQHIoyzllCHZyR+CVOvJNTlPMSAtUpAbW6RKDIEyYNjc9fhLc61GFjvOJhQ+AkvqiCd
dN5Jc5fAfXp8e3OUMe96QzcFfxFUHeYhfDjhEeEdFW9/k93a7xAyKcI+//TSljplJ/b2mBqqKDmL
AIUVCIKKZoqz6xjPR/dOSGLz+5YvmI6zweoPOk5e2Gq3PzWEUm1WJYzhLb2sLPm5N2tr8+CsH1gh
YUj8j4czOc++T0uvioIqWTHacHC0i2YWtrK1e3JRLzjkRpRi5xdRb76CNxyZIXH5nOFOq1LLnvgt
1T0kVW5W8taSDoXqQQ9ZFGHocZkwkRCtBxR/2Uz04AQSbgqVwmhGt+h3fhUgz5By5O0+h87O6qEl
a+usCyLN5EmBjzbrGsZ4P8Pl5D28AeN1R9XH59hYV2aKi5+w3r/O3NmmL5dcBF2E65/xdBNV66b+
p14jdKqgl1c1xvW/Ca2/9hnbwp2oDIGOiH+XyLkcjfO3EnJTpaeeUpEnf7oq4lGlPXvldeeqE3y8
U6itwGT2Ixdqojy0AmwmoW8HTG81Vs/NaK5Of4jb3CpAx6BsFAIqaCtCTuErCc2SvywEs3NPehTV
JIRSg0Ftu4aHGleGfYBUWJEycovEOwZuexdR1CtICrxuBkwDRUHSt0mX3bYSvmBpTVXGW3f+zy1j
tqf88Q6dLwehaF0CfpE27IfCVhOi6+AOxtGKmpDZt4mQlY1cDkKi4voDqXAoJP1jB/ci+MmBEx4g
gteSMMl9MnUbBbOwTEHaye95xdqaMPp9w3JiuRUZlk+dFMRwCF9CS8uO5AcxMYV0YePJdKsxEqai
4Gb51+wTJIuQPDDq55J7INt/DDCHkxhCUwjQN2t1E1F5iVF/K55V0fHg8z5YILiQApLva6Ck7bAY
gza1VXqnVgq9qyicqu0tLV2tzKE+E79l58OXB/AC04G+gD8pdeYWURjnio1TJaCOS8zxPp+m8ohN
dNXOIeYzWF2oSAwr+jJbhzqWso/oFsa4MJ33v2KO1h2ybyDui9SgekY2sio9yCpNVSTHHqmqbLXn
wrEvbSMmPzDd5Ut3VFZ45JEzqwfrW2hoWO1l90dIIcJOZ0L/YhEardfJViGFklkd+xzjgENinpZS
rlBIYvSlQtpD7PEt9In+r2QIccnSogvrdM8joQ/hEiELhPnp3CTV9fmtxCzCo7I1N4RSIZUHQuBc
rQn44zG5OyUFRGbOFdGFoNiH/7MGGT0xl24arJBojhX2PaFSKbk0kmjFjWmh+3T81j//A1I8i0SE
cVRtB7lWDt4PMyMhALTts/hNoqYymVq9EKvnkZLioGMO2tGPlrVDsEaAfwf32PzMotibmxDpzFAF
Kqzpjxr2HyXYPfXYPOrVbL1gM7h7Wgkx32t0WSvIJPyyhwtcKN1AntbcgiR0nXgtMH2AWUfJmtLT
oz39LhqNmWrBDjYnjflAucG6eSZrob0PwliTc5Uv8BvCO1M/V30S2+qdLDkvMDmL4cq92P8jQIeS
LnamTvZ5s1WTQAq+YsxUhw3lTqnD0HaMeu6R44cBakWQLN98boAdIqMYQifCR49zTXocGdurJ+zj
nLdwh/oMKr2kWJ+KOhQSkBVZ+AxjYJBZvOwnn5ZbvukjPO4NIh0m2z1X6xmZKKapD+VXzMJ4ve0R
EGwUHhrBuSS4aHQvYPncBYmSOBoMX0IzFnRdMxEsW8Q3EV8k2J8gukWoZL2XqK7DUemDYD/TIOqY
wxQyNwaPzFP41JMrg3INIk50aaR9S/fbKCQMhGP2efGPGsCqSJRvPwP2jMFfirHZEx0Nue6w/bbC
P9/Nny9wRPnaJJLPbxPKwOoix6CXQcvJj8bLbGHKysADERK1rfFHzw+wq9dpKnFSQ+PGzIxFP6uy
rijzaaTQVk0XWrKq1q0TA6F2gWhN9k5tvIKtUjjAVf3iyptRE6ch1Hj01ttFNVjWdioezIyBaVyI
GZ3eB+9Tv3aW3Mu+7Vz1462RznQ+dy2TibgDVdTgsfUm/+WiPLJ9p6VKfphmdVmhP6+GieluleG5
paB5/9/DYrl860vMore2BzoE+snEr75cmBlKnOv5wqWnLnh28UZGBpitwQ5XqA0TM2lO+R0Ofs4I
6/LzNfIsuSvoyuitzHHaINsna6l9sqyUI6yVRFg6h8wPcEm/tAyLizGkcrXsWrymUMKiUeGMKxx5
BlWOZOyHFzB5TrF9J0asyeo6GDhtM6rz4bobcKibnwxwXohJ0CgPXgSKhKpxtaljxXyf8HXXyH1P
n9jJF75S+m5S+aiN2hQbk2+o9ugb3Ws1pIf1tXUZIBHoA8ebhYgL+MiPkWSMytWweqvvG8l5JcZa
uUXcvnZRQGLYk4qQQNU9egUPtgXkZG+UNiLm/rJL5bh9DOYkE+IUPydPkMND/QQ8yXwtiXN2uefX
EM6b6qPzEgR5yqaAAGliiz5ECs1FB/mcro1RT3EcSxv4RJGXXZuB/Ku8tx2gPXBw8Le7enfs8FyQ
2DHibAyEpCM3/9grns9v5OsIbrnhuY9emxqLsIqHX2NF1lOKIzL7ZA6qTJacQTfYutu7oHjJp8yd
iuLUM0C33r41MepVPpSv4JNjMcYa9TqlMH1fHCO4kWywtITPiL7AkMncJjyKv/FJNlSc6MK9hv1v
MGgkvHkxGjE8iPdcuTid0JHttvXSNMHvobXyOJ7SkVBtThOhq9vSHTKVVF5tksK68S9Pzej56Pai
RrEwxcBdKjUJt/Z3LrRfoWPmlpCo2VXwZ0RHz4VlNdZrqXdpzzk70fEuMrd8QeH2AizX6Yo6SKET
IHynHdK/vXCb89Hwb6qSNw/rDvJKnJ11K3W2VVdJRu/NW1vg4DRdiVvuwwEz5jLsS5gbazXTOHdI
An3uy39SU1Mt/Rr8w1L8KmmQqKFUDTBHv7wPtPMdbNAjOYX5WBh2+h1BxswrtjpY+7wivMrJm5Kh
YKh/l3F3AE/Cqw1D7GUek+jO54ydRsfDTB3/FYW+UhDYUGJBTbc9PVxvLb+J2WEUom0XEwYoEG82
KsvKTU8R3su8FzQGkgTgp9IIpk2Bq9gP9YdmbcWo2PmYoQIiRy2zBwxiRKnYuVZkMPMLzKA0iK7q
u7zEkayyveWx48IwQU2Agu+e/BUqZ2n8q+7//1BlLx/dwxvBaAQp5UTWnAeLZFW2MW3uBHS9UpBn
sjZj8Da9mJXxqo2YdojU4mMbHrW53ue94tK7qjvAXFZ1yOPNrP70aVl9uJqEHlX4O5i4WMt5idH3
ftpg0yvuTLvoP+4aywDY7/gq62OW3zEILoUrulieD9bOKSX7XJUZ4iZNKFn7AEdZQLHM8MpqWwOk
NssiNhSk3+eH8d0K8zOQj24GFLQvUVj/7pNH5pP3RtQy8fdYpGUYyZhfKGY3g9Sre4LCCoZKggOk
fmEGI6dmO16n3gEMVGE+BSsrMT6NlZikdaQlHOFTK7z1Z7Ubx7s5S1aqaAmThujrrWeKdghW47aa
0co9Hu3Udw10VsRrZGJOM2OSU3AMwC9j/gVVn9CdsA8zOO97JcOcwfqoT4J2ra70KWLtSofxB6d1
E9hsIjloAVvUs2qbzfnpiUCfDJgdy2A/1IFCGuPhN1068EqI9mUvR+n2baQSw2hnqcSiIVUCQtny
oHj2cYAQsDVJy3L1zL6tiwZgdWmH/oE08azYI6OydSttcGWlpSfayLPXNYo1+0RopjHENntACTwq
HK7FxWRVMoFc4hbmAh5DEKuotmHp6oYnjGCbXX9izIy91pr3mwN/rcfkeMdroyep5dUWP5k5kjkT
Q/S/g6sBZFo/CHdb4HrAzhX88J/AS0O4C91BWiZ7iNED3U7HRhZqTghLno6OVL2no7QJlEckkqJs
Su6z9WDflrf3ngbD2sdNde9SInGABQPZITT5ruO3GkMEcW72kaj/EMPhZVClMM5ZBxYESoBuVK+K
2HrD3tu349Idn+zRKLMofG38Tq9bt6pwNoAfLjXcSwwQH+5ORQb+y1S3L0H4XHcdJcJJjCjD6r6F
21NMukcr94n4+d+75X+ozmbyUgt6oDJGK4ldK4KjTXR8ZkmCDOUBIEURawJF10YOqijtAQC+FcDJ
BMC8LZjrmhhgRLs7FFQv4GO10NFNXJrch8XP8CFn0m0moALfHqaGGJo3jHVI7Pk3JX+NOPFlAZNp
bEjgV3c64spS+hMhP4OFq2sDH7wlbtApQnsxHtX/p7YmOchmkM6oC2MKvZ/NACxvl4re+r2F4g//
W76ZqmXgXV5d1352CXKvQ5ZGJO4FAuQIK1b+5D1JnZNQXgDhT8B/K9hwYHiwjRgLZ6JXf2FWj4kv
Shggk4uOoNdguZOBQN74wNJEkGkyQSh28BJklw3TUuMPfX9ukkCPK/+3CFrPSai0ojHlBjEO6Lu0
kRUj0StEyNySKZcXLciSWI+u4W62hhmvIXRMkfRWVPDCs0HY9Z9+m8aBD9E1fhFDnZ/OH2pnBsDO
bmrRWN6+VZ3Rbas+M22tmV1lV7k7spxs5rk0o+OTYO1NUSvukc3rwdUVURIlIzmgwvIt8qAB+1jm
shmQg3H73RGzGxDiAOsc9/7aEqMvPI3jAlDX1PgPTdhlUlub4ZZZdqgQByZoKSa8UaNyu66FTNMK
UjEzVmTDeNlDHe3U/EwARFDlY/OWtGmzp2uMwuuZe7YHFArHgxfvpr2LKKqJQuK1GHT5PPX1/55x
sYS1xOT1bvDOxFivYhJFyXS5D6ByczBPXaKP7QriRw0KfkNUDNbltmy+djAnsq2Zk41BdRrnK72X
zCWURrhBRx0CZHuATaJ3jBatwfp9+5Ao1usSSS+3mQQ8TE6C+mWk+fF7oydx4fYDIpeOmFkxLimi
FK3FBlUUnDEdkO40LjJAXQ4cqW3dmZUHgCE6SEnQg4JA1htIAh3kG7EdGNMJQRZdTXS7YElYQEeZ
XteVnetRVjjItfJkRoCsI83DMjtV+S6VOaQs42t1cOqI72WfK0mksgE9ZCwWdNgTf/3whyC59J1b
OsZLU1c+NhAOjbUfLxXv/g/5sDKyS/faOQtuo/qCFO0qDPycwbldy5dTnCKlD5KzmA2kUwvWDwEl
kYkML/FuqTvQ8lcghfSgA1Zr+JhIhSJsIG+tIUNpmHRCMVd2CV6jlBYXjKtjGgEXeMmsBL22rN+T
FmArr7LwTkXulKPKzfmcqQkgbjPh/qxQ8I1qmuvg17NDttikhsaH49MimOcJHUPB8mjCsy+YqRHD
69OtGf8CPiWRhL7BlND23+qaIvrYCoqDjwpfGmFRJl3VcWcGsTkSFbSH9O5SxsZj674iUtjcXLAy
hRCixn54MHUH+5ZL62ke+u0Mxbf5asifW4qZ9Kk909kEQaDVQGDfPh6QboFqHI6/THDKrtecpAlj
GP+6mbyuXraG+xgurJDG6DV3xlcda8ULk0HL7g7zu3gtIxh9CvDWm+iVyT9nkSyjlpMs6pW1kCfE
neU022BxOUtxzvM4SBXxN8Hyv3aOWF+li9BNSHTCHDQtr/5oYkXKj+gRIppKxYNIDw5y4qld/+hD
IvQXiasJ1Q3lqWNBHnVGirWq/a+7+MLa5zRF/OMlfmB5icKiYghAR+C29BfZpWfF+lgjgLgnpVKz
bTM/i9lizAm2RoG8zyQ138lo65fEAuotPgKw6+dUMHXSiS7V1X8RCIPBs+5hZg+BOHvie3f2ggNa
Xb9YQIXZGTORKXPqp+IDIULJZzLFjT21VOzllgYHWCCfrZDKI+YAWUKs+J3sy65vf5juHo17VP9l
N5dTYTizFwsArsEO95Scd2mSHAOajgSFPPjwKwbiH9UiPAx1UWK/mYifa+EOfmP1j8J67W0tPHHa
hLVRAQ7fUDj1arUdZnHJf7UuCriyQ5D1QYpKPV+3z4RQYhO9az3bp7tOl6ipmI31wSQHWWajQE26
TzeuXFoAk5tjPWF45NJUeQWaDCeFWF4v9hyIcGX8LGJ3gPakPNhLok7qNjHa81vQx6zZT8UtrV2R
peMhYkL4IMamvkydwkbyJNeHr/Eg8kX6uc3SL+8cu0ct+AOIehzJpyRVDcyQ+lDTYr3RxXcL74xp
dvLIh6QZtIQOTzYKzWtZAQsEtz1WveixFP4HAuLk0Ay6cZRdYI27Js4Jql82oQyCCNGQ+I1hDTso
J4+H3ZMhtfjUt9LYnlX0ZWUDeYxoKeq75VTRYED6FfWq1Dg26QKmddJN/mMdCYAhP5CiLWMOzBM5
jBPvQMVqNDeH57fNXVaw3KS38+kZAO6LGstxxHgZmCFECj360a4VI4w6HdEwvcyKcZI/HbuhPqwc
mLwPBo6qRgV90CC2DtpB8sb0XJ2bMqk0WUzgCKQqf2f40fucigkrJ7f0l6xiKqp51OXMhTNPKJWH
C3njTbSqNrSGkrn+gzut/QDq6sYLFyjOxwmDkifEtgvrDTerAtDqERWGvQd+Dk3JtQEdWGa+dvr3
D0m6DiPdkJu5DwNTMRiOxaCafpl2NTTPbBoWHu4XMnob4yzg19KwchLE4IGu1IGFZnHPsXUL2wtp
X7SQDY2grUkSkgzJ3q3zWgorZSSrxdPhazMz64Xwlgnwtb30CZUc+uqGRMs/LeQeC5v0Q3uWGaXi
HhOwM1aQEZIJhbE3YUXo+5VelSdw9UXxgcY+k/tIjO9SvWsqZ5lwlK+2KHbBMXFYVzuZxU9b1Hzp
ngVjec97guZIouMUCN0Ire0QjO5uTEtbHO9XL9lNJtL8VmPbMMiFsYQU1eJzMY+HzNjbte+iXTBY
X79+hYiHvzj9F6+idJSIIlBzQvR3SY4i1jrC5/2fInzT2Ck1IoLUmVxqBvYlpnj4OxDPFt+C044M
Smrx7iZujyLiz0HPXlnTsOX41IAqnVsedX8gaZ6gvKN5Tm/9wB7BQMYcp5QtmV3PaBwcZ683W2SK
/Kz9OMRLFLnlKIm2yEQ1akEy61K8jCVZwgICvPr7kwU8fhs6Da7dI7Ysluohp3nyv7ID2KNzHpCi
QA8DG3P3VjsRGFBmZHejJjOwSpZMwP90yAhRp9Xib36gfctenChiCtGoOh3jVflL9OSaR0TraR7V
L1gbHQhl0nBrnNUTf3gSFi0av88gCZtLkw/COe35wjdrZigeilmSJIxXH497SRyoF3smODxwFUAA
zdHxK/H7Cj/L3eHEopwihGz4BfQYvOJ5A94/FLM84Y1jxF98lnbpHYEWy/kshU+u+u/j3ci6HZIc
GOHNpqxOfHVozyFvI+cfU7xZVeO7Bh3FcBEGj93aoruE9Bqr8LNeNN4BgQVi9YOelbueYq4J0jYR
kYRGsxSC/d1WFVc8lE6mNFmc4rHgmsQ+4xf2aRbLcwScmYdWSdPzN6PlVNfCSmHtC1LP7YKtFiJI
h4UQlyXhTRIRMPBH4D9B6V27SbHWAYcEIhbswTIBSxvP8hRDEEQS948i6Kqmpl1UySVWd2HSLXHv
zI+tGJP1HpNi8plVEARAu+jyF5TAn+pNtxUz2RgpR6WgM7HMfMFUweLZHslmUOSqPehcR4wV0ouj
Y8Tk8r1HI3E9Lak7ua6zntES7q3GkE6usz6I2slHkEUrAiOrVvC7K1uwa7JTdq14aOX06ehWhU1G
ODy9ZBgLBioqirqr0La0ZWE3anVotmwBspfjye3MnPMBFe+d35W1z+jClBLUBUpuYEEb2qElJmUy
9mjSxLjymu4Lsu0rsIvnu4bJoIU909vH6XAMSzLWy+Y4cEgtEX/35vixkL5U45aQL3m0vJ9sSnxK
8BE97g0M5behNOevxJqqvXbxThp0VgKfH12V2aCHkwGycjxsNatBg1Y9Ql9nzOC9pzEZaJ4sg3jj
e0aya0kVsOXxsQFer2po3jTWAwM4/CyzXsP8EdR1Wa5/DtchsrCJWI8XHT52Ru+a1uHGMubTy+63
WanE/bjsUFPX16LwwvLX8KepEoZTw6oPCgRR+LGe2hoogr5ozd+Xdx6q7kQRmrhJrSfZHOdjpCVh
7+AQ4zJuP/UtpwJ4PkneGRKAZtsPmv1SvRSH+CnZaEcVh7SorfHcdCp91tyzpJXOFK/dSB5jEG3g
aI/QoVcDXVEbTlnxiOmWOfEv+o7SfSLSmbZjRRBXmPvulV3iZ1HS7UpMHmLXUS4DRpmDZe2eAErY
nMsZkGUk1zXxaOxo0Y40Ai8Ni91z3h4+Lb4aYpnnjtXN8OaMH8jM6LJNemh0ZRUCgLlr69vsR67X
O0YjHCjJPO0Bvpa1iGFMak2aZUoitG6mkw11wJfP0MDpA1VN0OGMTcvwpLowRXU6Cg5XVr+2kgKs
oa9+4WlxueOTsJEJOrqawg8/CArzFoA51vpzEowsFwTaMLnbOmqC0hN7Qz4A3JyllYPEZu6ReCD2
33vSy5zO5CRZC8qYzDmgyGhsUw1YuaKRZD14+s2WR58MoD5q8u1nLDu+irk5faoVtcNV7Zcc9z8v
8AB35obKv5MsTzIETMmVqir1hseANDyTX5GY1vqxJIRHDy8xCTOdl9Lj2YF/rOpOa+qmeNJHX5au
LJ2gyScMFzb855C4poTQPxk35g0h8jmXc3lJMWdQq4IeqgDemZnanquH8NlkNuXUReL5QB/Fwq+I
2YPGsOhUk+8WpNB+6WfWy6EMk2M7TkeRrJqk/mF/tOzDrxMyADe86HoFMRgFiPFYAktsCDtSnVi/
1iFBkfnUlPfNkIdONLRGdMALXMtji9sj3cSVFgy924F27jVXNpCpKZg2kpQ1IxrtFFo+nH4mCcqA
7w7Y6MB71G0M9ccBvVx8VBvZETn1b/WRLVXU2pkvhbgprSy8AbJYzI5shC9aB/luPI7y07tQp8hP
zjaSvFreLPgdEoXSlT6Op0xdX6bxXutmj8VzoUL/gSQnXJsCU48feja+8/DGVGfU1UXPEp2Xzg24
wTweLmdt6+QjCHQtV+GxjMj6CzRLZmxUZirQMNBRig+Ku53EfpXFOC61eKAgR8lfrry2AGHCuLTq
13CP6+1m5LtcTcY7Z4P+xbydqh4S9YSEAzuXNDVsdxzeI49BfPwjZIDdHVzmBaU3Iw7gJoxfwzy9
a5KC9P3dNqsJPmn72GXSqQ0u5OCdy8oB/m1zpKRSVgbX6h4LEiVAWtoCkVZOg2qEs9JbYhjrcGxt
trbc5uWTNH0uKXYTaAqUefziBlk5CAjlTZljQAnKyYElReFV37wkodjRgsgQxrj4sjSugfE8EGnq
Qv8tIcBpeg2lGV9TMl33K98b2mF8SI3y3ZiilBZlPv/ajqTxbpbExjjddKgOARLCu7fo4ay0k1QT
Spua8McQr7Vwqppg/OmAwfbCbJpJDrtqsPjGgr358FOagP1CTsTnwZI1x1EkkWkOmEQH4JQkCEEG
X8pkpyZkSDTvQchysnxuCuKRy1TldflIP22r6TFsMAi/YOHwLtsz/nboKELcLsE3VKiJ+zDhydDI
WNQLuuxp2+D8bkhNsTIr07fwh8zpRbfO6jq8sudIUqFUUbdaszEaxC3yOARqXEgGqEADBjHPR0Cw
QDul9e3b+bXS8leZtJ++tD/No9wfJVZppZTUH0Nj2kKDRaWumma5xX/AliRb4eQmx3a3KUP5JXDD
ticwVitVbnMOmUL3wvnjUea9DU7jzvhGp4vg+JbmzHft3DKdQ94i7iF4ptOkdN7+LoIeKsYG2uZD
m5RJeixlkXrInbPKI5ALAzBeGzsAUz4t7J51lLrKWD3In8CWXugfSELiMmqPfRHXSfiC7BU1zwnD
Xa/IeysBZ4feBrkzXz7jxWNXolU+TnuWFw7ABqu1Jw0pTeRhw2LHKcSA9VFQFp8OFqWL+aR6Vb+6
i+AuB45j7YkGhwKScd9ZU19QEQXHBtcTkZux8r75nbkbUu2iPjLpPOCwJ3teBjFhF0mmOtpHxROG
5TLCoKFf1iEiSbmB9muG287jBfjqGtnxEkKVWXAaSRxTYmh/saE7jiHq0MKruMab2qyXLaLnZk0J
UvKSQl3/X2XEbPTBF4lADHRybG7EZLGTy369lmRgWnmXhyh4mpiFmpPNRi11kGN3vQxh+VSOEZKv
ZluyDc10sCqiE1iCYOPwB5kXwLIJpwQTMHv1goFXwIIfrstvQqwqnUkZZYjRG6OwfXJLSTkJvSn1
a5EleHbkQfAliwoEk9HfubHAobgQZQVCMUS+nSDz8hNsNbqE2Mg2KvBolN58I5WvCfFijZFForzq
b/TghnAhY2o6ZxDVGK6jRRZmRONcQnlVdVTXu3a3uUy1G3RiXTQnWoOqpmNiYJM8MAJAaXtjSqlA
Ka87/rpDpQGF/ufPJmj69IaldrGExquONq2xGbAXubdWFXdj2IaSomK1ZdDiagODoh/BPVZqli/l
xrq5a8fnVzxPgqxLqMY5dpMY6DUKhiDtaclA7whbQCByqbHxmxGfR3hr+i0HXv+tDjdrpPKomcAv
3m1/mIXjOE7yzGSScSlTsBip8p/Ga4S8Ine7lCxYYMNlmXwuPrQU8X4FXfSBSHVqhNAIDXiY0XNw
cGtruNpexAJTmmXbA/AJJKMbZOYldlpYX9jR4PnvkxHLBWxswV1F9uYsgMGfW05oxWcem7yLPvfz
5D/hzz8y/IeRNLAekUkFPHlwDzjmoisxaKzRs4pGkX5f4dKsnkQX5EPN9NDWFyc/Rb+5l7KQ+BPM
4JwsZA6dyXEtcCjnGcE6cO+clxyxttDYrw5mY9cUxlWi96sKk0oDPDluMH1VOzP0HhD9eYFBFS4h
0Ma+JBZPBCztvlxT2gYycsiUQUBn+yRt20yitOMupK03NTdkAUcqK+E0PsHiAT3XEISQeg+CpC1c
uAjvDqtj6qUEMZzrKyw1yLFpuh+SfDIfpcdI0lvxOVZHjrxh5+qAkvFzHhBQLonS1Phjdee0HmG5
/+G7xmduqjZlWGNbwy9xRivZbC4o3W+Wrzx8bBqRbeQJVmFjhlkaFDJOifoLgS8iCiGuNukEF4N3
wjAfI45NAnmc369dv8tL66icpvKmaiA1EZDahMd9QSIywAGg+u5BhXMj/LcHQ5EQcL9URoD9hrrV
IZcsFTtSGyyXgPkQLEmI3TGnCx4Fs2bimge2D/bXfx+zRN5lY1TqPpkwo/ju2YfDn82/xam0LuQd
qtWTPpnHQHBTHcHmZmU92BFeOFOG9JUty+2KS2eT/1N0Sfq4pih7uC+XbYo5sVmUVrsaQzRXarNW
8HlKK44MV4S5P0G6/jJeR6admHMe2ScSSXi26vpjKeOkAn6+vzhKKUY5k4iu3IqQ8N0h7tlHbavE
PgJ/vj7opWv01u84rQKUFhRqQiP7q2McofqyOIcnL9vRV+oSzpS9gkQ802M7l3hn95DtPFN4fHz5
2i5sCz+2WrhkN7RIR3n2wRB5uKAQBF0CxyyDBfRQ0af0QEWbBaReEuvaGL023cop+GLS4R+S1Ucl
nd5DsLCazFCRXXz/MZvY2tiOyDZLdtWZEYuzCRoYrc3ESsPhIv9RSQmR/Hf/05BzGzQiO2RYkKOr
9LkzRFG8HC4eMd3rB/sYOJcrMRE6ADy1mL6tcUo8pAdSyjYXta3Wj3eoV7B1Gk1jc6FnlGiKwt+c
K8Tb/NBwL4jDfOg5jCd+ZCIwSvSuHNahp7h5X1aLZU27zK+D5KWng5iLnPQw/D06s1dGEU96CNf1
bM4uXAMFIJn1urEwlPUUTlG/A4o1ZJF3Yjhc1E9VhYMrer0vyzwJTbG2P8Dm2X65n8n5Hs9scxZD
huc+msGPlJIEcA0cP3TogNj7YCYMU26O+hzhtwfNlM8LZlRjrfkvjKdQHmM06J7tX0cuWd+uan3i
vIJVj8ieA1d9CfRcT9ursc2Y9CbnA+rOOIAALiJLeAxZdBrrhzlvdUlQt9puq1jaepIW6Dit5h4c
OHBV5Rn5GrBt+CeInkxBdEhNDB6DwjxiGDmKdzLjI+CKYOmI/YXR3sL7Dmh9412w2TJFwl1KMK0A
wBGEyX3eYT/GBQvpjLxr1MR99y26N7Q3itvUCQuPbSmXt1ibHe1lQ6ovWBve1NwdiiSlEyGcjAga
hnhbko4PmTMJ+UjTtjAAgDHwSkDy1BFSgNSgRFpOuASb8+cZKI1F659LROUCFIzRXbFewm8o4RC7
yCft412KeaXz0LU57d1PYqCpnR8N/izeoqjUS+7LfIBs/goBctIJX+PnFPy7x8Tu7s9YYbINjSPX
Huf7/go9sRIWhXTIYW8hekfCnJmd6lkhgUXFpburrLsct+havFQkxvYTnC6c+l5zUbGvAUR9xZqM
rYW6R4Alh+CMehIr8L3/hFECrOdGQCSUtyrV/r0VNaEQ/sFSQY9fS1gPrhOAIlcW4AB5nhZ+Mzn+
+2Hy99Jf7TFCIa7e4As226jEyEjwKJ4lljkshoGuCK11POUoP83Zi7lK3jX8UUr1gkRlFlHdF0f2
CXEVc82UsKcVhwZOUbj9EzfVZ6egTyNokfwngF0/Uh5MRoAz0+6qlAEkWX6gb8u6ccjuRO0g+jen
W28numuAVsZQ9JkRij9rvBtBs8iwkziN4xXRRMOiOnFoiyGUgY0xMpN1CNUd0u3syJ3sy6V2ygOt
ZoGCdcbLjVsa7rdX2VQdyNVTYrrUdviQ/alwyXKMxNi+7FrJ08yZPKAWi3DptNZEDUUpKU4basaA
2iwgUZyFPEy4BHHqK492lEA/HLQHQS8p1mv14seQjXoZLdyhVOpsO/2ZK9HH64dxGd4PH/LDNPTd
Z3eDhc/Xwu558NOZzjLnjeOL6DvqRB5Eagi7wAXa1sSoRw91+nh2sJJxPYDQbAoFxczp9DWSSGu5
qofJvM+hFFh++COLJt6t/0l1g0uPzyGMYC4q72mWODST0i9PdC+YSUTl+lRW4sCPN8//p/PqY1al
TnrSDrjOAcCHcjo7yfBVB59c0NQaWysxtmQwtS9PD3qN6GJLd6xrDPqkDHXAxPECEQ4/Fe7DP1Mw
NbEVsDkdZ6ewCrHuA9x7BvBN1SMJwZfr1wnjfcCnvGQZNL6WTDKJQMcuPUTLtIEVHVPQlNeVMcMz
4trq7JQdo7RHwJm4dt1QEhjTiPcXvaCc6ZhJ7MszOFGeXERiBbF4SA2EGKBD9c/mzbeAtCB4BibQ
M6rx1bnRRIlbKwt5nHuekgpJb031DlE0KrNOtI0IjB1rBE1jh5aJEDTjTOZNljYoze7//SIL4DQ/
CWl4fXHyqKCCM0IDrC0vNbxrBBNQSdZjo1EXYkPBlLarQxbrWAR83mqZYMtRXaTOd3VtJ4ctDide
DqPrbidT2p78cwIfNh61QPrl9KyewLrdksydl0myvJDRCbkqeesodPR2oiKwc9065V+SG52484w7
bKSa19dE3gH2VxpUOSpJffC4FOGiVWcgepoBv5khrrsm1jzoEl9z/AfDhKXrBwwaS6M1v5uBpDVf
pha9ncZPBpkL9UN0tquXQ706j/XjhOT3fApKpHdeU78XCO93+GuQMCda3lYL3bhvbFsJsZxnsrbS
WBvSL33jqWksMhj5HU6I3tWZxXzHP/gZmrIETxqveQgtLdbZCvLb5gbnelqlLA1S6VCLLmuncH2d
HKraxaBEhAW+6nwRXkTa+5l9jLYst3nYSl21a40wUC7zwWFq6LyzrS8y7HbpKj6hqpZSEi+h9uMU
pcxmZkOS5aWwmVyc5r9tX9ZVXsgvmrlbwhH1i5QUkMqBebERQ+lvbWTvbbGBRc6/9b6/XpAkB3B5
a0kwaaR5fr2riCN6xrB6ld72EeyINL3aLPvDDFsyDsFBGHmHKgFUQDs41aWhJvRiI5jbUvHTF2cH
GehKNemx83hAnQvv9hbDBXgexUj6vBhrGvtlLCWktLqhj/rJ9cX9a8tW3Bd6Zin99PUcwDhU8c9q
+M6a2inr5pkbpmd6O3fdIhajLVm9r4ffyt1O3dQ0YlUPIs+0kj0YXXGaVG19v8094LxMro/SNhXC
8ycqx19hQUEMfS9SGUmraih6aL7unKP3KkqNnHhLvKGJIm1QvYLwuB6+aC+ic1NG3I0VpJAA530X
IKD3FltMzEwOxV0ctJMG24i2KDR0T01VRQwJk+kfL3vvnv1Tx29ujfYu6Gs2uC4/7Do/cu7EgJLB
HMsFNxp5H84c2N+DAYlgQAWwz74axdUgXW+eHt9IfKU+XGxQXmx5Or5Mqv/f7482DvCGpzU6uYx7
oBjx59wWeaZ/27BjemSUNOergQqUOjlxvy3S0BPR2zId8b6G6ckGIOkvBy6yWJIv2PEHWKTARjS6
td+Z+SNAX6VR5rWA4UCtMNw3QiYnxOyVbotUyT1peqBNPbvQQDwIXsNw7k9xQn/EfwjuRnWCgO2j
ZUd3O7SYn7gpuzBUk42Vne5ZMOsA0uh2En9Ugwjx2gFhQ1qIj9fFEeP75ZJUM77zvAsihnIlD29t
I9kyPf3X6aNrx9ZtkbfR0+SNqAopGwVVvU32GCL0xD+dcU+KywUCvwulibcgqVvPAV4TpjOrfub8
d/q70qXe+3mZOeW2sW5Am9DPfO4TPUvchJz6+KL6V7Su5BYSRJsPeiqw1D3HJ2ek91SBXl65/KH6
gurD+pJr3zBx6p5dZy9f2f7koU7Rn9z42755Lc753uhrSYUbYxfJahlQSaNLaL+MafbrAh98eXda
YnfXo315ruL1g0Uzf1dljkJQpsH4e5HupFSevy+vJh1I9bvoMLLdSzyNnU3PTF1Rz10Ua2U8OEqX
c8LMLcHWCJXnL+iylK+cc8C6M2xpAyLCzwS1vULvHlnO0IX2Ae8RdHljQOhn20sKSy5RmwGwaHAM
G2lNgjH0j1YkAeJgImj1T9PljSPtoa4AveYhJL1nGEO/dh4fGDwA2CvX6zFsdAbEsPMVM9Sh9VHC
aui7Oz6HMfiBD3nKeQ53TiqLQnK97oYmnR9D1NtQhlEzEiLpUD1KKZAP+XaAIZsmkaZ5BQgRIH8b
+LAhjos/Nwf5j/YRUKVJNUw2REjXOjqeDY6QFRGeEE0KrTgwV+4xjzPuIpPDFccUGr+6YW6w3Fcl
molrcgzIy0owqS0pB7x6tXYf2vMYmv4TCL88qDFiyE/SFb5nVE3XQaGOMFDcyYu2uqO6nr0HMM9n
GeDMB0IoqESzlPJJb7YA5QNEdju8qPCR0qVcwBBKSyrUKwLhci9v75WL+CmwwxlTuh7mG2zJcqVO
rUkeDVNLjeL5Wu/7RRwUFz7jGrQ8wyri11ci78KMC07A/KxM97Wo1lh+M9JOzI7S1nSNwv6rv/D6
Q/pSYn2CIdu+bJIOM8NHf/tsbWX+L3wGX9Zs5R5hePOD8093rgEdlmJhQ3NYTY+57Z1c58fmExUX
N5zNJf+Nr1gefVuyBGWEvuK7O26XsKPcAMmODM3bcYzQAfK8b8IOKteHO1kryd/hKJRg5xy7h4YA
vha6bwLWx6kC0HGG1mXoBT7IoH1BVj4GD+T5OSormDgQj3Xu+EA37nM+SqL1rXBsH4I9vGjZ9Paq
O1rCDuoCyDsHvHdXY9wbKLw6qk0xSrrMEIIOsZhGcCVNnKEYzdteKna+tPMQU13hx0mrItdxEXUU
OOKVhISADsPZ430RiTxPH0aPKUD40COCrOQ29UNU27HztmHqhTWeQjNX1qFn86e8L1BqBMXEellw
Uk7wb83vx+7u1qSd5MDyRnSjE0t3DdMQG0O696srQ1xQxQpOyfjgXnYuwTKJ2uLPwLMUWlo6EGbg
EK/WbfXlK5MlcccUP83d/EEIiws1B6pelY2hOa0/b6QpAl4FJht7Z/W6ZkzCiw8+d79lJy7Og+Qp
aA3ZB2que5K429ecujECe/8KV93do7r9I0baV7ye8w6TCmSyWgeL3MpO8r4XXI6dSJlbiPISA+e5
0llIp5qtmAlXOLU/3BKiPlp0GaL/B4RUDxDaIlIWkQgEUAv45+XPLiO/X68qe5jXo42ijgM0FLOX
VRNcVKCwF6PVwqWLd6Hu/fOxwp37w7jY9mDnRN4HeGPzkwd6KI0MUFcvMs+xluFXVYbzerci+omu
ZuWIac57EZAB5npxZCar2JxwAuV4GItmlBYiUtCZQsWrccEvFphgPhHOCRAPOkNJSWgeoEmhvqje
bhgMK8CDt+ZTo3+Wexexpt9ByiNEkW5UmR2XX8qt+vYZY63OeuN/6fnRDygRj8YTQafjCI8grncN
RlRzDdJ5TuoZANAkb86zcDnU2YPY95yqgEPtXpZmRulsjsYMpNFmKvLvjgxXC92ZNrVHKDnuwT+B
5SZn4osMZkIxhWMrY9AJSxyt1OhXriofszdxwMOXpxeOi5l399UnVcTEa8BofIAsWJstVYuFYY1t
3kiM8kLXgWINkHs+rAa52HDstUg+bCmAyN9KJ8TDqkJ9xTAJC5sbGuc/BXVrd3F9Z9jtwWHfqoUW
g+hYL7Na+BdzwHQVjVtVPZ+ox1SpsXRq+aryWzITZcAI6OmXagCUnLDLbzem8QUK0oXdaf2yyays
r8f5gNxCYvssFuKO4MK//3+sajKXSABnQZ7JcdEZ3rC1R9CoTj+L84XQ2OPA1x8kTP+AnKVr9+KE
XAE28hdmoKJMIuZKicGbSGAj2W6v+QAyz1J1+LykQxtG0wj2tDbtOixZExaPYsBuDd6XYiWLy5T3
GvTt/19qJA12cS71aGpxDHvuephxoNDqYf0QsldKQnBRJNfZf6BycDgDBNFYMVtljcVAcD6rel3N
rLql0OjaZARNnZXTQ/yL4d6zwQXjNKN6V5czk8gOtLTmHnObQn0GY610SNRvphJdCdXuiK4SFPia
lecDNK2Zh+cEnQFlvqxTGyTL8MV7Ao1nR54QxKhYTgG0sIZ0onEMFusY0uFucriqiXyATIXbJmtg
hijfdtD5BgPPlLTqj8thmJIu2ni0lVSRVBkG0I/sDLLV6lpZq55HyZIO/DlUGopsdy5aLkynH/6V
uutBrEONii5KQG4gcFh8hUe3gvlAHDHQZrI3nxzPuIIEQ5AdRrERBCrmaPf4g38Z47uOCKhBFCWM
UgqAMNFNcMFjU1UdEvUw5RzcvYA1kt260g4ZY2O8X2TLIB6EcSMsVopPcNttJKBCeV0HK8fJwZGY
ufPogvtd+iQaGUPRlUhRaYpzB+GUr+heVV/061oauwYvjoigu+ljUiaR6vMi/kSshrnTLBL8mNUj
FM0ySkaUM/OLVtPLvKksvl9O/xKSzTTPaljbPzMmbM54L8c4J2KslqWOhgRnEw7CRaAz0MsDipll
yJvrccdW/OK71MxpSe+ohiZhbTMC80knxDY3athC3wVVxpXxUejTf5VemOec5ao5kZuZxZEk6lsV
Qa/geHmqsHVCLeM3o3Tsp/9dtMhzPDhthm5McWU03CC86diIEzF3OF0AkTKf2XxYWUhgHkduHo/i
OcbEw2LQCZCC90/LMO2xAYYY9k2VVU87cjcka+QYzWiEyrL8doQJ2PfOnIUoKS/fRi7hahDLj+QB
ExfoNuv7OKeWyu02gB7KnRkKP6+IlfjeDgGiZxxc1QfpDwKygPuAA1GubiqTOI9PydASOhE0oHwy
CO+PmzMl7KmSIMLydCoPX65+ZkolttGwahm39HG76iohJppC11h3lj85FsNnWx0FTVaKJx7xeP4t
qWZIS7/bErTw9TNSL45FK15kHvOLGTCnFzFWkjVDiQd72Gw/7zNzfCJiKbeEGZDj8YXA5vslI3gn
YFY7A5DKn5V4+3JlwBcx6ipGKvOzgrNnrYT4soTqAXHS90xZRht+mmky/RdSqkmPV0QlCwL1AyKX
YNiFmiyTRKr4T6iWCQpIY4mwpnoT4Xo/euKrTFaTh2XXNJ0yLuHAzkhwcK/4TfMJ6LYSlyHQL5R2
FeexpQqpsdsYv+QCV80pd1Ven7fOwONQxpKpVRwQa2+ve0bSVEnBQ6QclGSN30L0Ad1yKmRqvJQh
kNRmMDoU56d2jl4AoUoGnIPXjZVU1BuQzP5fTwPi4pq0EDzW+LDm7Ev+8R6bVIYF8CgAisAil8y6
UkeggMXubeyOnazJo+NRGFY20AJQex6kZ6lbwhN7TCFh0CC0PK6V8Q2fbrbeXw8k9CUwHgU8KQnu
PKcXm75GOy62NZR9fpADP/uRlTFeW/gS8MBlMR8GM3ZRGqLjIdgV5ucge+Q1yH03Cva2zNWizkWO
9kN6RWduYN+VgCOpPTya+Yz/ubUzuxRqkve2I41cmdkDI6fwx8uAOhBvGfY4T3mnxcwa/cAN6OXp
KsTHMzKrQYSjs/QZ5gRK1tnqc3/FWlCiOlIYk22ARE2fYAULX7ujly3/fJwYcIE7O7Ro/FN69Sm9
0feWAAPVjh5NId89GtWuhwzKFn02hHL8i+iBbHuNlT9J+0P++XMEJxyfBZRKpG0nZ8dor1KnI8BN
wIOkrNh9WznI1zuFng+IYQVPZjr0UlX9014PqoEfGnmXCeaX29SR4a4U1xckenEnU/BsWIfqMiaO
NUtKvYJ/7v64kVI9cOwTEFmLlV9Sg4oeWW54QWyOkeZ7Bec1ZSiMS07n1dBEIlEewOPSvnJPIJ2A
+PdRhrWqZNLriTtpD7KRH7E5YHXi9IPAq7jiYPzQq6rDdYK19Y9/zU7wcfiIJXihBfVjKGxQzN/T
uQIkirYWBRWBQ2PW60rTijGGZ5X3pqBBDv6k5W7hvAg/+j9d2OiqwUef6j3LNtSGiqXhR+K9kCre
dBhAf4qE5z9/l+1gaOpk9u33CAQSthNbhp3fW6dKVK+w6UeMYatqslRgfx48BrXznjWZinW3Y7a3
sI2ZgXtW2UegLKK57ZnZDLIOLJX51qRcAjfUuzOlEdo3iA6N+4R1hURNofiQqlhYPXhfnAhp2dxk
1k211oP7bOT0thnt5tBnQbvZJxf8AFdo59KLbH/P2aZBBMT6qNUr6qMmxVZMUA3wpx+0TsutEb0x
6dYyP6ukFSdv5BerdtRiCc+6iUVzdEIs145yGbGb6rD8CZmRwWrJ3mYFIsmYfpOzYmdtr8Mg894E
VM3JEQQSJX/THvHn9bvxSujT0qHN5poSl4R6FxHu9mJ/+hLTSdRkzKo6eOPNw0Q7K6dXvaZzUawo
R6VHcIfzNLd4sLJbTvWGOPzpTv+hTNneOLjk/yP3bVn5TOjzXsaiLD+x4mIBzFFadnAK7JwCY5WB
PWSDhHTUjLLEqQbyVMTkIiNCLc7xm7qPJJc3D14nfEhq6QPyOERGQRIij/Y8igyConFQyQycpK20
WOWP4iCdMHDUxnzGXhERK8JFHD2MzLxrtr/mNbZwjW86NaLMXs14jcTrqDub6H8JMbKOSxg4ik4H
jR1pXCZ2WUVFR1YIc/HD6cKmJBYnaTbeMGLbpawbs8vVPASRlsJjEdZcialrGtmbJo2djlGJfpHh
NAEongbjwxWPlbT/pXepoJieY0TFHflo/x++qgIVKShTWVTwO4O0jURfSvnzxpJ2utmUGE1ItRPD
ahzwxgCRVCEEC4tTk/vXZ6kG4pomcu79FXMGK95jVAeqIgCRNMylpcJsGjpqyjL+gzNazhQZGMQD
cIJsUQTtK1L0GrMKyp+9JoOh8RkbMBGp2gYbzqcbGLkL+75xCH5HBss3Us/HKjRWDbQsfPYh2EId
xBn+C76EiO8VITpdj5QNBeRR/jYxe8QxOrQT4VpyI0sQbdgUomfE3Vhav958bBa6sSz4iko4T53K
C9WTpioHQdXji/5whGdOIzROUd/fWF1ArMfa762goMwlV+gsdnHWMbBaVkIcz68w2pqeBdA/2Uz3
UZwdOoRzsZINoBNujMWdS3/pL6WXx/3ErqjyaQql+lufdRhU+v4HqwyKDnZEjy8du9vBcxgqIiqn
4+rSbokmxInFZ7BBryRFTk2GPZ1XqLe2LOYGfXSB5lDBsxvc4uRhkuFsjOP37uoMTykVQRgSYSFS
jhasoHY/EZ28ISiWApy5pXhpLB5TZG4+pnoX2aRBeBLmZoTYfRAOiOt8HTpeSohccaQIHv7155cu
WVXTq8XsDM6KJZH/EBzJfV5RWr3+Jyq1XPEkn8K8sqOAdUuVktR76PpqU5U8F2L4Wu5t8tZzjOKc
XY6wCdvuR856LqTYS7uNUbsulQST/5M+2DiogwB62qgd701HlsBDGUx5Uu5hUTvg3be6K8MpQvAd
sQSOJVTmz8qpeth/e5V1HdAJfnO2vtRGzxvxkZmz/OfTkEOOsMeM9i7PLDucHKij4CnyXptm8r33
HIYBY6XYG+j2R23CUsj96lbdCinVeNZ+cteUTeK3ScUVFr/zoWVgDR/kcABV/9qAk/DNDzrqE/4G
W0lDGrUremJr0ru9s+GaldZDAlrnCZ8jn0jpw5rZTus+2Hd01Wv91iJbE+yTbtyuhOM6TJZQxOHz
JF8y27hi+iBnficXrZngvWAwJqx9OikFoEogMEAG9QBsQ5iLdPe+14A7gzP8P/cxbPnSrUVSiNid
HptgJptJ9AgYAOOun3d7/H3AWYcoylqFIPi/ZDW39SXAquMVGztCYuBOAZWHlGBfds4izSNCVcCY
sZzm411Yygaak8+3ZTIMgdzeCNv8qGs/pc59lwQvzoP6dY3aOPsJ8lQt+KBREixr6rheWyTl1rmi
Yl5Eg0ZlrHdWYYWzVSdnkAvEBl+hckU+mZDsEPX9W/gWSXwHioNbdhXshKN50rOWXwfxHf3//71G
ov6fwsLBry8mXyhvkVEjQa2chxvXEdsk6wI6AmkUWrzVlcFtTRllPcBxyW0YiusFLCnEC6mz0PkP
sI2G9XaN7FAdZmRKvhuA/944+iYljHuPok3wEIQ170bW2mmUzPoOEYy7MaCyI1aetD2tunH7oJA3
42jT6PUY+71tV0oxI20EZ7Z1ORfln627673y2zQuDHntdZw0x9hrl4VdsL1XVyyzfPRLZBhSXs5q
2D21h5omiOlPpZ2jrVJSDQERL/qmtS3jbdN/LK7vDxcsGlrkaZ1Y95S7EZbjF4L4m2TVN00CmCs6
0/UZd/F19iy29fKoteRvkKdvatd1RGa7C3FAcUjlO8oiJaomN02hCbvv/bWGZQq4n+LHL5+9NQKN
You3VrFN4cFMQd4A1oZlBfnkKP3smqSpGmtyeo6EF0ogRlLqJqzX+FeY/AhN9tDwn2YVKg0PUkyT
H/JzETk7AQCZvMOGxYEX/EyWpfK4uoE27CzsYVYWw4hR+K6cWEA0DpfNZxy0u/vF1p4oHMH5QbcP
wHXVT/vkYb/7ZN4wmOixZMwodVCVmGr4aU4grXISXDez8+PBWhNy1UJd+FKCOto3yv2XVZKqB2hV
sBoMTk16+/qVrjvdWl50hi1Lt6zd5f09ynTj5Vh88BM/Si3leVYXoG9vFexjnrTLmoxJHMt48EV8
BJIEkb2lwWFmmZjAKGmiCWhM/8RntRJtfP4mfINpN7zjcK4ElEoWDPirh1R5hUWPX+wTQw7zgvV9
qNp/pHykqNlQQDtuuEQPbVvlla1TIYzQ9DeEadMVQnOpCxy8+yRNaoY3Y15T1p0WdiMsuB/dVw8M
7DzIge1/TajK2EFu9xKZYvNSCDsToUKFWhQJdw8tdm/+IHeTwlJukTpYukzAl9QeOxQVE6b10d4P
M+q6MHKPOme0XMFxOvM1uzmr4Q2m7358TklulDR1TMegmWAs3kYpSObi7/qwix1l/j2PFuy8/cRu
BjnGYOxUntnEsRnTpZummPSESv0dU73T3rZ1xLt9hzwSA82xRBv0xFPAGe0CSMYcI2mbvzSVlaUR
AYal5yv9Ucsf3PS5Dfu6AsvgfxFhvkPQMjc5qtlZS9u66CJwBIr74W9RmaOr6wmFow7z6n0ZKRls
MOMM161sE1nsDza0Yp0k4g74DpPOAztZy9VH1dMA4eISo+y8PBhu+U1T/SkxXAjk1Pp1IJ/wUu6Z
sJFuP7/pBy2DfM/TEdHN0j34dPOA5DA55bbLDA5fvXxCvTQbnVqNn3BtWX6KuSfv/XyG0LhLYwGC
jJl9LdvjutRxeHaf/ueFa9RsmCQia1rMDhx3StmrdvpFC27ZNe+D/GinM90uC1TXbnHuPfUSJMae
PQUfxAWeNR4jxJezGmqNXfge3PVUqU+ms2/CQT0vJz09v3yb/jghlcu+FQBhVA/Xrrx/bVw3MACr
XuTo5VPqgWbEUtKxO7xgmZzIdrbD1IPAjK/Z3I4jvIxrUnyeLbAM9EnHFoBVRlx+lEUZ+eGY4Qki
Qz4QqxW1UUMhGDDIBFMmYcwDIKFv6B0kJfDbXbSXnl71FG6tmKi4hpF/WqC2tpJmLFF1mpVrjgbd
qVkfFp8hr4yeYj1FiokDuida1lxtXsqiwPKOKYuWTg73xzGkuwASGMEvYyhXV5OJIIADXqb9WCcg
wDIDHl+bHOHqIOZRXisrb+/u+ppiZJhgirnx0lyF5pe73tpsZ+zDBZo8UqE4GAgkaUxVOz8mYq4e
78rwpARsn9QTot1Zw/9IxgZuJ9uGs3yncvzqiXKsOzHb9BmnxgxiuPCW0bVeKugdJK09aBKRvuom
7HbX79FlR5UdaF3KLUsNlCYerD+iMYh9wk4RsBYEIvi4fNMmITf36quuc+9kNFyZuASXi5E6GTyx
IS+zwNt8Es3er3LESE3fIpxhVHAKZyGsRlcBmVZyTLEz7RcIaYSJsPeXpfuCfG5BdemkcOkkOTb2
gnggVTZtuuXoLpmBWgMHybZhBNyWvWrkaFZ4UwQbLGVMnyh1RuIcMjeWG/27qeZU0j8UiesbSfbq
MPIFsFTP7ZOnvyKSoTuvQz6e9hxE0kJmzlIsjC4GSoqw10/maV5wqDA/fCp7ZYPX3OVJB452EFWa
+9Sxet5SoSN44eGXmyroOgd7Lr/9YGx8MWAqmAhESB4Q0k3+Bb1NDLmocx6Ux2KAT5eqSGNw0qmf
nqwJWXspMYU6OYJjCxl5V5GI4lPYGCEV0whyfTmc46tfCpnpwrKIn4Yk0Ov0moxMyKLvlDICBK8u
1LcgqKamHq3hgQr+w7nf45Fnze8xkFC1vE0B5mYyh1QzUU0VhKyET2wVanWK9Yw46S5HDq6DuDTZ
jEI7dK3T3GDCxVj0XS92IjYd3jzcadwa/hJk0ANExyONyjoLwBfZPkMxiJEbUlAmDQgz3bMNuT69
qJh+FkYkGmhlpERDorAcgHNfxGXvg8D2WO4M9vRHlWlTTyPbGa5RGkV2fTxCH+9o/8LsNEVAJ+Fv
v5Z7RANx7nlgVhwu7cK1mjW12n+b2jBACL2D0A+q31ZLs1V0SzPe5GX08S+RG2H4MEWjhgGO0QXV
OHTfAarb3uD0JEJb/1UgYWQb6Q3JVqeFt9f6HKqb0DEuIb5HgdiboEpz7mFqBgSYKBiHlI+9UH/7
Bjtl3/LdGbV9NjT53ljEeEQkcC98Qsza/mKV9JgtpJwLVThs1jmYGJFNCo0ciUM/dBbPgV0Lm8uy
KuPDq12U4F/eQc/35letBb1WaNBP49iChv5Axl8PuJ5SQ/rTUo0tUfcdYys8HJZJoDn7M43nks9q
BK3WGWomVtw3bkTi5QCrZU45vJJiSA6nBki6NpAs5VDmvNIMsfoiem0ZbaGmseD0779L8Ua8C0rL
VNB0tEWj7tRWhwkiA4Pvd/97y7V/BjSZoPgYqNaAteLCynt0RU/jGJee9bze6SJe8bg756DKugUR
SiOKyUfalN5P3aJ2eME8FEUaYas/Hlk0UHPiU0X2vSM6pNy7yPIDzUg3Lh1odNyPkZ/rQVkF2M/K
BEcdHcwep/h4VqNTfpHfnRzEC9W0EfEQGu4H7KS0ByDAkdslqNA2QLHl5u50KKMEYwLWIz5svK/L
7xjlhEN1B6oELAzIwMghTsaS+nGOCFh1CaHkUh0lure94c3w3CevrhAJurZAVamz+o7auP4rpkgB
8sL4CsK2ocB4weKYLezjopHSaKsuHrot/AcOYeAuUQ+dVnF1jVnoq5M8MTZ+ECyxJMTwrAuiD+rm
OK2ZuUgS4CEd7GkiV9DlCaJirAKsnkRL/7MmqHGfugGYw5M2XZ2xBgeCEmNJ1wL8/6MFomoM7iQ0
FKRJnvaAYMM8dTjytCVvv7R8ZLFj1BccWTwjqlepka+6JOnRPFkrvUIcQzTJFWFDh+VGy8axHDpj
Ht4kxo/LURdJWe1ROseBsZXK9+TQ3OQenhbSRfRQBmrNV0QRRZLa33eSG59PJFMQkyiCvzfDpHeV
OSo90OomqtjO/+noqLrD8j5d9MWc56Dja9NvkdgOJ0WGDMOI5udo8/jhm4YDYhs4RCzjeAtLOcgo
YwON7Q61C0ScxU3L3b76pM8eI+ZCperGcsUAmyycJSPoh3WR2rofimO3/MPw2yBaOw7FNFqhcDMz
Zi3FG1ks9WHY06OwfevlRLO9/syLsbhjL5L4Z/DI23OOEX3+zOqptvmGY6gnzofZwAJKTO7aWL6b
T4RKTbnHm17vyRC8ZLN05blPzJjndrdvNcIc0Lj2Tbu2Z5It9A9Bhg2NvvOXl1V+v78B6YwKp+uI
bICzz4ULaseKizeHq0Vgkmad37llFfhqlIyTVCd9OzEfXbVMrSblAs7d3h8g4WidanSXKcxYOTea
QBzhkI1lBzGmvTS/PPF/RQ545NYXINnxY+cchvsWKnKDVnRbfom906xEo5maKNhQsTB8xK2ulu5E
a26i59RZWbGd2Abl86LOvauMGTdCErfVGp6GoCcrEa0BKbutOnfzSLv4yvuCcHdwLREJlir6h9O8
XvnCloVXa2yQrDga040LTGQpRsrPXWGVbcb9dLEK2VWFWDwekrIFsT4oSbV0WhjlUPFpP7uohoz9
O2CLU8Cj8g52K49xlvvkC5RPXlVRcw2fUqNl+kH9oT5vuCMIRq2lcEER0NxDXHDGW0JPPw3EPXDX
j7HwGJ5lznWws8fhJv0fd/6ql/P5Af2B7/jwInhhc+6u0zNs9Rcx8qX+xZyr1yOC0E01jjCGL8Oo
thceFcBw7m+Mm+zijgUvlr77hl8GUKsgO5b4qAfEQMJSUnXLqNOiSACTRyj0akQOzJJaissG996Z
fz6ouzuRfwyX9Cjfg3iv2hl70yAc++WPiqxyxMVx3m00yraPYHjfrcIY7YIDqU2HdzGPQ5qxhh+9
xpzRffoIh17Hx+5FSFPG/PWIQA6bfnGUmobif4C6wEWwk1wRbsd2fNTSDhNhOlA4DC0DH9tXdnC2
bFqh+Kfe7y2lveRIErYv/ch/3g6Yja2Hhd+16UfguZ2B0sErrAz/w3+TjcqpPXQ04NZjSWx0tTl+
vaw5Asgz/I7mJsyRTtpwi2rUN74CttT4POscoMPym8VxdSxhJJLmWLL+TwmUCLIA4KeasrhdWOr+
ZGZezwF3JhoscXiZu7OsZ0KP54fWExl/O4ZCStzjXbfMRxiIE/iA9ybOrBpmiLnwUtJKK/xrlTMh
/pCgPkX2Ea2r2TjAs4eqhTWUUij+U/prB9KVwngxXOFvjVxaz+qo/Q8yttEbC9r3YBoy/TsQNdsm
NJ8/PZnvjQCz3lN/gQmPaCu8T1hPPwmkKPkg6oTNP2qUOjuWI+huY8TnCXoVjRq0AVqul+ldzpBy
U4XBU1HfF5pF0pQW+vzbfbeOeu4sTXgc6aF2lA5VuVIXQhJrSZ29NDP4Xnfe11mhaWd3YMKkX1iK
78kKdabKz0/44XDbGMYMTTgQBCOvY8qCZPSRpAUJwEOEg7Q2feTh47MLHhQbE1kQD43larON/psP
WzB/hPIJtGXc+lXpxV3zJTF1iK9XThoyD5WDrl+PVQMpEkAy/kN+bqeS+ZxJkgnB4pbNJv4jGCtl
n9vQiN2yi2KzbP2VQ/+D4DVqBpnmdtbH4VGxEAo7KwKSZBTeam6gEZ2AGyeV/jI8a0/5aIGcwiTY
cX+kjcMPhSwMqQfWO9QB8eqC6FZJQGxqMQNANj8cSLQ91VsLUTVYzJPMX9kYSq08hwn+nSFV4fwC
f0p+O2biXjZ6+HK5Tt1cD8dt7/CcLNKjJos2stYJ9rkhzLCtW3G8WZn3d2PNUjuBbkpdyXrsKRb5
Zd/FHW2LmeSTIZNZg0LXfRWHquw4BbaSzvKG8bc0XYCVL31wyGQm9YSqhWp4dDtjRpK9Qa/r4XJ4
3waZ38xD2auW0feGwSTvVFZRWduuTGBMu3uHcia/EMPy39yURrcUYKH4+Ikttm6ShCroWpNleB8q
kvwEQrmPl0nYhlxIgzAGnyKz8HdCIuqsoa71ukNHni15YlFiN5e0aSyT1qIMCZj/a5Up7Je42di/
JpsI8Jv3c7RdXtPWPLHbJuPK8gEeci0rZZlTmFgzKqcVlHosahIP8SEaKmyibeaWcCf4BWyVcO/k
Jy4ea9Clf7rWc1qkdzmGatV+xtaoMmocHzqwmmV9qatWqGfRq/nRGMKMnIHNFJZSyeiXt47zsqEO
GUjU/sj6XEH53tuKqpT0BZbptp8+FUNgH7365tTKCgMOGxsIbwyQDUP2r2eldq/rbJImuwTyfDYV
z+kyUlyh8hsuZbqFSVaJ5uxnffX5bINl32JJkL4QxFS/0HwZdCmq6XgLCVJRnVx18Da3MMeIfjoA
8QNRalSQ2wRhtS/7MNDob17BvkNr0RbM9+wzHfyjkbiCHHcT5iL351Kf7chf30H7iRWSlsquEIFK
gYI/DR5hf2CI8RwNc2sjede1rWx4ieteguugdcJL8QN4DCaCFA42PLLzUxkQ7rj2ZIi+tvZh4ZCR
cjBVDADyk8XUXpL+xG3H+eezvtKWcXTVMtl1Ye5xmBc9ODWDIaODZin4maBZKSdXUnc5hFkx5oG3
Fftt/ulOFT2zIuJiijQTmjJ6lgczG1O7SaeDtN5woZ4KVc1wZLWkB/sl+UVSi1sqINpa6kCC76h9
Ij8wF/pCUJVJ1kCag6avjgr1FCsyiRNPSb4DaMDdmlR7pnLx76jSwezFxK4qz9PzpfiU25HloTQ6
ZyyiTkRUrK/ZuolwzY5qVitQHPxTz1U0CLdsbmO53ODPYgzixkGsiU0TnK0KfhVtirlOycrmy9Mm
J9immwTEv32du2p2UBAf0YVmP4+PZwOnbsmYvV4B5CD9fPMiILKIw7LbVYS9OE4IzIAvgxtJ9/Qc
Ahh6+eVQH/kthjnUBUBGIDrD7peFsZNzq9WC3GbJ46cAtNSbBGm0IjLxlUhuHOJJPjIKp0gIK5+k
rwGBAUpuXMXKNWCdDnKpCFloaR3EKm0A+3i4cIpg72kpmiZ4r6VDN8vdiB1XCgAubMsn0ZSHCRA4
DR544LAWliYSDLIJCOT1t35llUoDdfLxqCxKC1c97R0iSK7EqLfyYDcUZmS8Wt5ApmAOWSUVFeCg
gqO/QwNUWowqLKjPoOpMNvqN20dX54O/8uY4WmSg/TGJsRiMR92LRpC5RXikmLIc7klko6jFvWf4
O1/rxBByzJc7NDJDZh19ih8Eiqr7qKaXefdULky+n8EgVxS8B8YGlU9EoGiMLgce97p/WaF2+Mav
LK0hYKLDKgLeKrkj9GIYoBFOSA252IoFl+JkX8FDvYSA+pxe7rZHaK9bqTpenDJC/9fVyOjPvgvT
JbbLFasqJl5smOEX4GKMqFyceDnzmygl6oavnMxVgfjJxGaQHYo7BpJWoGNzn3kIfrj0zL8CVaQq
NRQMCd/hmYYtWIMD2VY74AEQhYyy8zkqLi0oIpoZFtzYg7wbfd3SDNkll+osT5j9RjYMfIBScFL+
AyShtneZJSDDLdkWZhcRNnJWo32HstM4QeGZki4DnqUWAOSZUzeH7JEHHC2NgOpYc5SGrWdFdX7K
0lP1pI8WvGaKeiSubALQAN10oXBGghdn8hKJQmSurAFS1IN581hxjVMaFwvvMwhI3DS54RkLIhiJ
I0kjCBSC1SyBfR2EHIyL/8SYYff2/7gRYF7/8pBzpFXh1bqz5U32J1WMsF9ibpHqL1bzcmvX9ZMb
a7uY3RLkryIhhBEu0KsSYa1GOZmeOlwxw0W8d/v/5jJ4ht4bq/Bf3yMvOABug2Hi9ZXePTxXOEvm
koQQFHAHDokbO8kd8IwMyIS5/F6qgtiq7mVSlgRi8TnovsepDjWsoS7R1a+/TuRyRh27VWWOveVx
0c0ThYx1AICY9GmfEMSUFu7xSdvW7E3t9zjjxUHoUr+zm8vLQo63qE+76OHjplmXkc3m202xSzcE
s5+G2H3j7r7cS/ti9QO0sB5/w9WtboRKZ0OFEbzd31zj3RlXq65vaChErFwx3JwMG00ZHlFenob3
hmfV47oY3Y1UYLRuWsiH0t74Kyl4OBMUF8+YKnDZ3432rUFQRiOMTemGqKAZ9R3xwPrqvhCrBF0u
f/qTcfPgDZDRvGwOBbywgD6TmKJrsAEXp2pg7UybHcQm7cyD6fb0ADI5xvvFiHbvBlrkFzn8uYcY
46q5hmgNvDuR7cZuPjDku5sSQKI7P/RxCy/+8+/lDmPpxYOgVXrzZ9yzy5tGNRN7uzgsCktkQ37W
zHm76i9NF6/pNQXoU+qEB8vdnYRjRi17ISDcVwVVFVNsnCthF4/lmxOe+hUJKH2bkZi2qpWRgcwh
XHeRKwhTAP67OFPcAOtg1GwKUWsI7ms/hofJTItPavxjHTzDySYeU0kKR+lyzsoa+T7bDks7N5NA
ah94sQl7q629EruzqEqjVrxPsX1+jmXZQCOn1HnF7ufA7u3xpXkePsJby2JrJbyJoKqr1kyoB125
0NeeBS52qKBarA39ta6yyipTka81HK1cimVq7lnytAvRbm8vKHcgW6qWlHcVf4jzv3bOZxngBNNd
8bsTI5CDypnVaGb8XiGk5k93oGo2GI1il5zTGn5lOSU1b4REVsC1IPrSlQpSF1PvavLWzmV47SCl
VRBfgfDAyagPVg/aKoO3sDa/70pIo9IB1X/nFrExR9jRCk8h2OA9pVVr6VXAVoMmRkIIGUKWNNT0
BLQDnqggJKnTb0w5N5Q5gEWnIowFouMnP20hXETrx60eTO6QQsoTm1C7kWdtntRZ8LIZSeTzDtId
dZiqNtEP5Ov9BxhRrug76VB3YPXADJ/GJG5x6CZuWeH62Q3ttYr22x5FLoNpR2BXOOMi0WlkCx+f
6yM0gWoGIj6J18FWfQ+a80XkE//UTSPbV5OfozcEUzNCNs9c8Oz8JLsWL6uTx7KztwwKUr7YNqph
AU+yW8b07Ms7uguuuJ6ONvbKu3MGjz3hZ/GVnm/7ZAP80Y65wg6AWf+6FK8KnJ2kPiXRFudNPa0/
BY7BtDNo+3jpocSnMHas1wbsSPHauph9StWqD2pwK5ZvQ3nkEAD4s5mWIVertY3s0xIM1o6FtTlG
ZQsGHk/LJJ1wFgUrF4Hmi3orjU0rhbZvBNezlRjNNsGUT0mkRros3IImBWavZz4pxLhak43ji7KB
Xc516bKedTkmVVQOiOkEffXAo7GtlKMRQBUp0UCy2c9D/wIGpaCfJU9zvCRmpNFbvyUiniIM3iPZ
/RiCpyc/2v7h53vVcZRfqzQNTk/3JTtmaiQiq0SJq6y6gjmeNqu9UwCPK2B+ob1Ckt4QV0Q1YTgD
skHbriM3fK/6pg6nKE8VhAcTrZ/EbSgH7KKtLPSfIXs7T88sBNEQ7krMnqAEM5ka9t1GgV5QhTKD
aDFh/1MK8oNFhemunpO/r8TkeY2XAcutBwCA77QnfyqNfAX2R3+HwQ0uuP7zjpJdi5hzK6MwOeJO
D4lU39liZXPwEx7t+WBJjNOcuinTozamRKAqpkAFwmX+8jj7g0m9SE0r8SQZk9TRn6HTjfLhHL37
xXusGifTlC91OhjIwLJwYrlaEtHHvh2O53mi9AOrZ6D2r8luI0dX1S/mMtp3XXl7ZkBthoXBb7ji
RNPaqZkCfQQIIzBoTZPBZMx8zvFwlenfZ3XobmTc/W87dvY/affBjRUJ4W+HZD8DzROW8Hh8nCMZ
5bilk0ElIPB2bZNFQqoQxQEjJq8p7/S4oZoOGPW26kZZYVShpXd9Uhxd4+xm3iZa0Cd1PPAgD9MZ
ID2XyFuv4eqsVAe25U9zE9rcM8OEsqFjtHfO3oCfk9DvZud5n2VMlq6M/JcI4Rfy94af7HdnAXjy
fNVfoy3yZI8hJtAkTCaguvBaUyIOZ1MXzfUDCjClHjMczEtbQdaEteoiQMPesehd7B7kFG2kazSW
YqtvbP0PF83BltyAX8ZKSbnde46K7IF2XmCe18E8qsQAFcqrlixXA9cR5MPneetCwK0PtllMb5c2
KD5KEeJJr64oWZ9qzDEA1N3TgVmIhoH13VxWElRMZU+bL6ZiWkVWpoesVCByEdjXXvt63UdDpqgI
fKPrnuxSlnfZc9Wv/Jn9QiR7muDW85PQNGXdgdwsMKIA5lhvNz3i3jUxsT2A8we3CcZXAqrCSU2L
UBJcgzlyTy5KQ75T7nRNsudjj/EljB2inOI50wvz0kFwpaAShK48Chedap6yi9pi9XMoDwfSV+Fe
lBC3BoRbJbVMLchZfUbbr6XDLt3lgjLORXgzcDbxYEulk11EfSxHOredl/RnPR3M5vDN7WjIbocH
V02jVrKfqPm35KdmEZy4Tpe2OypKltgX8uKF27LJ0hUS1nfVBmh2fFbLc+xM5YMROemu/IpI3aag
uzcJgj5yFICahdO/U5puaAxFS+zIErnWHfJWZK6EOl81UiMLclu5mdJidv1awc8SL6C9rDH7KeRH
EvgCGrkv4+9qThkFyXoBZ/4xIAC5CkxwaA269QdLehsLrhzT0tFJtuGx7adbvEyMJ4v6akT225BR
BOa7LsS7AhYMlCaeuBYijnVQIidXjkMgiOiJdJOIYlpO0FC1Bz2giHb9rJ/orlE75cqHzgFaHaIm
rbOOF4JRNTf/b9PDUpXhC5xJ4wOrF0hpVI9UjaTKgeKzCjvz677NF0d29l9Algz5C+oQxSVJjy0Z
QrqVeRo2GJqKDW10ox20A8UHgwLwx+IsKd4CsFxkaMsr5vgx/bAR/FnQAuTGUbYZYIBnZxiAgJ4l
7cNCF9KDth9rOyeXAOGNY+wmw+V4An0AU/YZvlJLi/+bdfZ8L8Xw0A4kjBYQ9USGuZp3SBCGjl1D
G88+2Ttx0Sj784oa3BqsTOoZ/ERmEeL+1pVzT3JLaagYClEOyfavef9zHADUhcCT6Nn4tx0qQ4Gz
9vosaapJ7htcfEtXJsGrDI1i+CX3Fs1EShgj6fzVz2S6/eiKfHSSR+NLP5k5J2MM4lm5O5ZrpZ+K
XYNpyUbNp14EWvxNfesDSnQK8kKPWSg5PxrBgirXskDiH4fna5bWCP9d77DgDjHHDceS7NFq34Xo
096k+2uS2Yo/lTbKGil5yaCt8waW/Lx556BGJDDlZ13Ki9x4wcxRO3dtC1TX93qVX1GERRlLD7Gi
EjUQJnlDLM1dJEy2wzASpwvl5CdG6XTQsNCPdxwxljQhF79vspV2Y29CERHWc/j1H6qRMMBpP679
kLdon1RInjM+Pl8KuH7NmAU0qxOmr1gs8o2tsXrh69zpWmyl/DEgN6xK1Joo+klqVhtxhOF7Cz3a
zxKxRGFp34Td6vQymDr6XvI7VCAzgtXWJegBrVsQ+tfml6101mIlSQ7mZ6mOQbMcfqPNe0+iwaCn
qz9vZjaQdTC+kN8e/TsOlt1T3ON6dfpQAtLKQs06t6DDKk2cQytDxJ5FGKf2eaR83RjGuE/PJt/Z
cKyZyXvkFFasEiTT2VZHa12HAaD5TRdPYFO8BXQzyfWZdCDISQGvd4QKmK2jvenzvKMdllAn3KIX
vl1tAz5OwT9yFe5LIE5mFijhQsgtLJSp7CPo+IZlFoy8ulv1OT2C9XBE89dNIOvoSIHtaJgnYOn7
lFI7y7xi99/F/XpXsJInJLzqVBPY0i0UeEiODTGzP3xmbd92I+Difm10Tm11UGmhoFsA+H+ff9k0
R5u/rAb1DmE+w8+rP03t7ZOBmn1mhIY1AVnaKPn2j1UmqXN43E5WgxodfY3pKbO4xkWyayZHmd/G
AEnB+aKD0gYPGMYhGHcZXQgSPJ66/ZbDbv0dz9HYC9sb+rPh+s6/gji4li8ejwDB1ecao6cnYcIc
niuOU2rgfmqowPIXaEmcyP8OOKOyjvhr/DMWQtLdrXxAyauHZg2ECb7tSl/XIqPQlHjGBY+0eI9j
u8HFH5LgA7PEr4ZQLwG3VqclvNEsNJg0YQ6YA+K9L5mkf8KX1OIwy1mfhf6MubazNiyA3E7CjNgZ
6M+5Rv3/+7iMn7tsx3xvHneWbKjoMhODsiDdFooRy4G+0Si8/3Uejz1vjhZIs+dvGieQ0EkiW14U
TA/NqUyfkolsKXbb15fs1pRdtS025p+8Jdc5f8mGTRHwbEpr3Wp4jk3WgdKFNQ7Lqv5MkLCHnqQ3
DfgQcUyujZXubsWoUyQ6LZUX12S1Hy9jvkKXEf11vuYHO6bgDwCXEQdzey1R6QKoI94SA792CggS
F1vDMrgaAkeCbFtD5L/dmkf/Ele8SzNlmGA6ez2lmwEXZHj49t8CGq6z7FSTznjCHmI+zig+xTiN
NDPK2fM36BA1yYCJGjHXpCTtscVkvL5ZhnBaC4xBZewejV/hh94HDKfsHLiC1821WVAfLcCraCyQ
ZPRq13R85Ow4+mz9CIwJiMqM7QuhdAcvVUjCChQLPrQj9XwSAmcd1H8UilfpD+VcJhAkN4UCzSqx
lwL4N+FJx7B/duzJTHO8JgfdbrKEqXgkxlz8XR089gf05Ua72Oc8tzFVE4ifKietSoaJ1pMQo6+T
/CBmx3/4r9+ZwyYRHAX9BysaL7n5tmzEoClIui0uOftu2ZcKK6buZfhG0rj5Tvt1pHOq0z3WyQs9
katxLr2m/XFDZvEYlif6djscMToLDE8NPlhoHiJtulcq0WvWrCLbVG/hl3ItvzQ7r7X7RfhCrDnq
zGpbbXOfPDImUYavh1SNd8xkr3K0n5T7ioaTTwIfxNHyVhljLAgxkq6heDdHMMfzd/495u7Hyj09
eObgaQgYdqXtWAnv2WHYy7rF4W2Si4P+g5hsHLnDoNDvmxW/x9ZOhXEAlWTJzXZGTWMy3zq6aZJO
aPevzUWA20VF2nH6+OQ/CaiNZBDQiX2m0L6EN6X1znP0cZPSaCnVv8OETYRrwqkQ7hbXI6lceDkZ
c/26ILAnDaDDsbKI433pxtbxYe9FMQC7rk87HIOtaWk8mj+wRr4/UtIUyPt+SQjklTi6r/3dGiJY
PVQah6imfcZ+gzY3LeVPBSFhcFRYzou5qqu9kkQuTLO3mRX5kB2LsvTjwQD9kHTnS+LV4+U0WrwT
qNbRUtCZRWkCMYASWTLhVnhvymEsRJ2t4CfpYUpQ6WnnpdzsQoABIts5sBWCHLFCGm1UwpRL2ynb
kBU6pUOYy5Uvm6VuKQEB3xldM5HtFNy5dJZxHSMOu57ssruYWwSGR29dQvqgCIJRinTj+p9CAKV3
1qYftydYp0ceLsKTSNfhQuQ1BV9NZZyRjbjoVx/eTRpiCSfB44eJe0A9loFHmbH0aiaU4K/bgLuh
QMe/rMj5HqZU0nUKCPCbT0hyfRDXQ32pLBnfGlEDa69atzvbiRE3RjW3tgdEflDg1TQfeRHqO/NA
ryXqduPmGgFS3UAoTJJ8V8FaexjjeSVQV5K+YKFhKtULwrCBg/XrFubLpskQKn8n246vW5H2+QsS
E/2OIcK8W310JFuQVdzfe7g2OUk+gAlZY096y5lj99DRbWaqCCfLYb2KHWH6HHTv+ew+cVFNWfNU
YzdnHNMrhfC0dT4D9eLe7/3xzfiOzboqt0IUC23e4KRUwqbqfXNE/McFMkJEXiyvGKe18umCeChy
VaKqx3GKEEF6WIEUDnZ5Ij2Kp4x+iuccUfKg0Skbf90b2iIA00sH59whzWIAF6ni4rZYNEpQx2A4
CbPizu0g9TazJ7nfeSKmBQ89rK5IBVCdIsioakL1/MXUkSdR+I51CBy8G0HJuqzKI6vOWcUJQ5ee
K+9Qj79C3NVSVqWjIqgH+CL8c9sIX+L3NLEDyQ1eCecDmHdcGmWB/XUb1RMT2N1K9E92zWWFCWLG
Y93QrvX5BZzfvuEVhJdz1fJbbkMG0TA3y0B2wsNBwiIJpUvB350gPl++Zw8/JVNs1QX26w7xqyW/
l3BiYLebfRAL4MaAVkKhRu+HaHx/Oc/G+7iKRLTPCE7pIeT+3eklrlEKhyYj81I3cWhZjiGtdfqX
1DPzMgLUp2KCVmkXp1QCsVWiKNK8Oc2qg00W7PTO6xTg6QDYGG3EMDSSk8AWo59ts8rAuPVv/2R7
A7HVl5eJF/999AidravW1+rMvrx28gBId8CrWATgTbP9LI/3u+R2GBX6p4yjyXqhNUpUAVUBXYP3
3xxG+4b3Mf3FKJId3c6cFv5EB2H2JL6jWnBHdL7WKqiMTUFd8sAFiuDy2fPSaKQQRa1iytAc/k2z
XhblpZqkvPCKEqPNMlFQr4FRtiVifNbzFqZFNlxZA+buVmmlbN2NB0FqSvsHcj6ZBQSmEBkWb9an
4vukGLvqysmXhj0ZjnBmS0RrX/d5e6KNC6nnws3A/Y9c/b8/aneWapwzzrWGj2G+nWzO4Otm7jkl
czRZin02OLLhPDrzIL6T10Bb92xtwtXMGHwyeSm7Q5UcAAQitPUH7KSdUBQGtptv8/hkM+j2eQe+
NLLnofroyNehQcss7FkIzlk1yCuBErnML68XXJTyTnqsyUC9/I2ma0XvDI9TqWKEwPTaaTVLdQLh
mlWdhp864aY15d0ghuR7Us9nfSQsdPqYuYeWIxMs69c3NLFcNHnVGikQtj0NRWnXoaahCI8GYs6P
Rt3d+uOkgakGsNXDDY755usXHkt7cLFPYLjlcEBgbU+xiKusxsRCeMxNLD7cdysZ3C7MbVD39oOo
s7i6ftE5U19nkEpdJGOd8WuNghSAYfLV5/w8JeHG+G4s0Ed6stLKMjGo274frrArZVBV8myprq50
Ji/vDqUWK1wj95LKuWTmHeIYNWQeXrLX3M6bof8rWqRCv6S974FLJj5SuB2dypT9tpJws+MZP/Hn
sHNPXFlqQWgbrTHkwZo0u4UG22wcLNMLTy2zUtHIMxtcYJEh/+6E9FsY8Dsx1yFWx40AO7L4nPBn
z+c35jJGkNkkMEtlW2Db3vhhRTHtPTrmmXcAXlVdRXvR60oIWK4n+LM7Q6lIo04vkPdhbnla3+wn
qwWg0aaH1HsN1+4Sb6J6yarQ5YMDvr/V7ONKyEPZy2rA0embVeEFNASTIjS1MYVMzpQ0Vyg2LeeK
WNSB0RGgVBaLUgVyq7ANNtHbzTmbX8oqlfF1CSiekKwmereXULZn8o7wfMjQIjQsjp1hq/vQge0H
7aAUtuhsYPk9iP/pg6LMuI5pF8YiS03SVGzF/Uw64t/2qToWHA/zroBAvddKiDq1Jmny/Fueh9Sn
C2DKOH5n9DoWppzccIT8HJbrYOnKMP9Tk8Yqv7Xw2AhfklAPaI3sRY5PAkYeoHAquRt1hHQXBqou
HA8YuUKDYbR9dfz7ppsHhLgYGUBNFK8ltg2fJxfosjzzJv/2mv8O+kCBzxxajG592LzBk5D9PM1t
9jJYfKlv1KX7KAmCqbvuhqUtsHMnK8aXs9V0GsbAgyEMk7mTnsuR5bhriYjRVLm/5XuQjpaRFiZj
ebG+o7cwnlYl85n4CjOWBc8ah+e2eNJptuDou/bt/YJftIpqZymJF5aGv8bHOoW/ffVGbjDfjMjx
cE0+oCvmaTDzxhVkPLr2kXhzCY1IHbUHHSHsBrpUEAA1E4Ooy60QA6oF4SPhlhuL5yobAqRZLyar
RS2D4XfMtkYb9+t2JjtRVU+otPlr+WGZyPN+KxFEAvpFCrTD9lfnMS5DLmuqCsiDjSOXkG3pIHrf
9OeVDVZGvJ8cbEnI6B5KufRrxGBVIGMzY2jjpIKIXca0nvTBjC7DfAzlQhB6v02Lzq42gfimIFAb
fe5fX0gv0TsA5jMYcj5w+2sWYIA7MhG6th+Ly2fWNiPSVR5P/JPVf4F/aZl0e6Wj/pt+vtNvK2SW
5t5inuxzlMfAoiPfyqMMLdI27NECipC2ElQ8OLjVwVVkNOpavlhMvNSnS2kXtyh047UvG/S2P6WD
OFrMlW/Aj4dyC6IcxnsyoZn8GTvUpSBxrzq1UrUY4Q6LSNO3Qh1hatRm2zKVwsmyGTO7UUk3B0lD
u3lJxBYB6UF9FymzAU0YOWXLWL9Wsl7xjkd2PHC08c0yRaODJheXF91CcFSNSQpWnOFCBsvjgsxh
YLt0MMgM+nN2pV+ggdGK+MRpMpjb4uGJ/9MLTP2AytF6JvkmE37tR7++zI2JhSIvb7miqHITefCN
55o/iiOn/iTUMx3epyDsz+z/QZqGvK6N5GFU6Kn7HrfWMGO6vyyE9TwxPMHzHeuHtMPA9yA5TsqH
O1XnusGWsiRijzPTxSZ1WKkHT4JwCnPw1R38E6CpigP5uzlFXf4k6VQDsEN4coPMojGlNG4W55oU
KVeS2T4IVea1J9sGgJ1ejgjU66dWx7dEko7AJIx+3DD2/PBuCHUsBYYmwVK5+EaZyytQVzxcU4mR
YRkWRNl0fmCHRfuMWflLXDHI2bkh3fBdC1CHgPnDlZhxbnKle24YstEuuKsk4u0XwN5fglDg7Bxz
wVJVWzZX3b43UemMEneOZPlX8VZq5juDtG1X0RX2wtTav0bdw1almpJGkTVNQBB/xJoeSuwWYz7w
Pfr6AhNX++zCTWOhmVdynuT8872QcsGFtyBQa8MOHYE5HS2la1TBSVfPCl6Om5c8lcz/LgWqxiFP
CFXAbtBHE92911OfToeo3Jx9/dAldq23ql5CuAvq85mqjQphaCi6zFPvvpgvWo0/koTbIbbMWEJk
FrOaEa8yzbePntmEyXPkv7AqXNKbSSfiCPZ+Px4iw70OysuPENTfCtaFQje/h3fSqBCcgvubxedg
VMxwyovglyRvJrTdpNJ0mokzREXJE7s2aYSPjthDmdGV32NiBP/hhjDH00k9Se4C3vB4vbpFgtYK
IasimIROXvpIDLfv38rOjajnJ5O6Wy1CTMA7TGOi+b7DA/pHthmvH03FcM8HDNOgDhqBlxkZhW5+
voHGOp+BtvjsJxBw+LH7vzkEsuBAiUaWbfr2q3zPkQwcOFRsg0jmpkCJgBdpZC04GQXlAnsgcvXj
sI6IRYZe7GLezOEMnRejcVUST5AEoQZa9bT0W/FH9UaZUBRFLOc3uVSEXPzGWzGX7xkS0ipB+s3W
2br9NMDrzZQAfDpTd6x1JuTWo8l4e0BDc9bx+WS02PCdzmKKgE7DS8A3qclMJikK99GF2E3qUKzX
09M1IlRnAQ+yCUiNuujEvBPT+06N4gisyKLS0PIfU3ZGOZv2SMztRu2lLX2gP2C5y54aEPELjwTl
Wh3phMX2ToayEob605EIA5cPofLpFN4K0xbocHXtiqMp/e94S/4imFH8FeY4U03UTiHanTF4D8S+
ix9C/4Usx72HV8P/Uwe3KBzG0EhayC5KAQlvYiYGjmtYMwqYCTr+Ez4vrgp0YSzDfjsBpm0EJKSS
2TqggzU53vI1g2nhrWw8S3uqf/Bra5eCe8pcua62rnWjmciST+UlWRur+QlzrAOElw7qhkqNUY0Z
Mq3vjyzKv859fylR4APRCbCkceezg/kY5+xfvUtoTscASDUiuEW6LPF328cOPapQYzDUYgimxcTB
5o2cyHUFRW7MjR/Zd8/Fi5I0kzekxSOfyjhpcDru3TnxIX2GrSlEzUgoZ8VN7j6KghXsDrhFxqgh
oYrgJOmS1NWTj/3reaTbsjFGl8E5DLIyWfiLyEwuiDioT7IRLW9KmLc5cJeUHgJq0oKZ7YfW2qgP
rU3zN52YkyC+aB0hIQvo6v5Y0VTPHhERGmmlqfJToDNmO1luFVSsXjivUwfYFf740P8cStvMypjN
n5RF0ShCTM2n3Ctwf0GLDflKlp3LD8F/zAEuggMM+44v33pjTTm47lmgeJcucXiUCNhYkL2mF9k/
r4YdWnr/DqwugrhbwOREHOhi6IdJ+k4o5dDHzoAeCw57/hlzp6WiCqVZYNaEGxW2qim23IQngqLY
Nsu4EOgQrizhUpeJHqRHohOoG8BooH1mebtn3jpiTuHTKeXedIzbMkhU4RV9DixN+RyqitW/z0Jl
XRfN9EwL/gymPgd3IcwdQ+shZbc5Fqi7a4RiF4cvWyn3GXE07Xy7/bkajV461nCINhLYmR16JqDK
JegM5LFJetN37ZHGm8yxKW1YZZ4XEtNOl3dqARY2ra1dIWm/07hBdTk+nyUINmQEKn5ZNxsUC2ze
0XTRldD04rNVFCbmepFf8m3yMvNiHT3TKGFCWO9wTB3N3NBBwyQOaDQRUUSUHcDCysj6XFxI1xS6
Yw4QJTXjOP/3D8wGjMPO8S1L89s5WDk5ct2vuPJMr4Fdti/wzd12ovnqwjucZvJId7A86/rI29Wp
nINvACDIuixo3a0k49NkRHx9i/pHxk8RYuOMU3dW0sZtX2FWr4YLRXKjtIakpjUelR+6Kum5xovq
U4tnBTdCdOqimq4v4+NrPgkpimge4YEG75bk0PymYs/it5fL0qWGRlFaX8ncajofo3nnNmmyMD7V
ZFHSq7ookSJmE4r1TPp+I8/2+4I9N+UX1VYdPphlCwkOSQHUioDTyfUwyoZ8NmZfMUxcZVa1OSl5
und7ZnktoLQNLy/FLof7MKGzMSMF5PLtWAjkcN4LCwm31tcndmv91jenq4EYdrmYU1T2oe+3abnL
lgdkMNhmxVNYnMgUY7dWqo3j2AHI1zoqesI3hAQfItSye9SkrAQlpI+Gs3cGHJ+PRVyOkZk36PP4
9fDvKF0CGNIilPJiWvrm7vr0sIMdO1l1/lMQc6alOM98FAEl977u4CzUONaPgB08TfRrrF4tRSla
nFCcdc99e8OS+Sd+UfDt63yr+5vt7RtQ2aEWrtwVjKDvtAvAb9BomPX99QzJ+tjmQCkZYFYc7QDD
pZ1c/pIa5heeaqx+fUPoiSCsEWJRy0As7WFifjq/9TPYcveBY0lfUP7gT6ghFik4Z75vT9mV3y8i
Wml7nGtM5gFWhlje7xAacvMz+4ZAaev6nMWJ6Bn+Vu+HLwHr4buEm6mHBSeQGwGKuSI3tQciyfye
8qWeV5E+UCvSj9JMszLelGe82vc45IHp548wKJuzgXDQFAt7drX1B83ScPxCfrtYBOiSSu/ZmzP7
qAOO3m3dSgp3loGnyTlzwIdXJHo3OCgDa6V3GorDWBIaOraiFp9PX7qj5P3eRAEX6SwqhFzx7p9s
rvTloOCdzD6F/JUF7hs3ap6cU9YcnsBam/cC4gYYQidXj15HZFC4Kahs9oQ+h9uScmqTNe3MTzMJ
ANptxWDOOp+yBiBRs1kub2D8ree93gAxR/nHj5ehwFSUq1VYS6jmKQz7a7eqoilP514ecBrb5VSH
JPVYuH7zDXTHslryQOSjrd7N+puj/b9IoitTU4ZFbuV3HqjbkEIYQ7HcFEMXrf1sQVLc/GYMI/lO
k57pMlRnnlgA6xAb+JShgMvRIPmNvj7Uh3cPDtQTg1hxVYyZX6mrwSyivjpf7ZErtJIE3CyO+SzL
9oR+2umJ7LDWZWb6vnkTS5W+pcSfF+qtVAjehzIAgKl+3Bmid4KvR9sGhOfZj+BMmEI46cRLOmPv
TrA+ugbQjo5nWtPJzHMpIpfb1W1vQTFEJgOKrIOTwVI3nRTsUg15yt+/UK+TQBVH01uwEoLIMPRq
eMjxysfX8YnfSSaoFRwR2tCjYC4bNnZNZus1mQVyo1pMe396AhfEZmoU7BmU6EZVXgt4tgqDIXF7
fHWbQJ5nTaP6jgDHRaIW/0Pu3CRjTKEqwgyU4JOzLdCdHc32sNMAX0kklu84gk2RtHsbo7pVYC+Z
335z1OUfDcJScbhwWkx0hFujCGAeQiZlhKlK7BLe2esvgd1voamJkad2Dqw35ri0zd06lUvA/UL3
v2jH7cIm1uMZmVHu6PAqMhsOxphT29etVz1b2GWkJkfuG1daJbfJDWQC3YMJVSLQ+8ihBYa1yilL
xXPNC3tDzEbZV/G0qLI59nSp43ydJPMfnWkStfg1B3YFPvBlGzRMPJg1UzSr4eLuyV5uglWp5GYQ
SGKQW00DPEM0Tf+RQ8cVoU69POZ7MbTvH8Tou5fDt9IGudGUSua0s4Hq9hOx0wCcoyXXvyGM+3iX
taLnp/3vFuxjvW3XBnTxB5gTUGOjGNa/q370dyg4YC4YYKzUp50F/+DHlp+DlDUsyR9opDhpKCiz
XatkEnov6v6qdamy42zWzgNnMK+IVBSD7YtJSV3odUyVKC0ZDGeU4a9QRZs6qYpfBX12IV2YAEJC
WzOTSs5jN9qZU9tR1nWSWhSY4JMVfNf8Up8cICKyBDc4q1IzApYymkfAFIIBIAL2OTQXsWK+yrJQ
1/q6Aq0+ThEl2IBk8T917cUkii8NSSo6c6rjqkKNLCF2aLEjGW3LVCYFHgCLWO38oMIMudQoincg
M4hNDEPEYAevL1cy3OofRHuy0DfQASqvgx8wkZeMoj01gslQeQzStiq+BjYf5u2ePbMIjP2Hndfw
sSRNnBqSLgIL58fa3H2eJcyUZHCAGMehEY2lSmWu0Ln4cLCaS8XPe9F3orNp5wElH9oSSO16xFNn
EJFpyCTV1he4Jq/8ulHDvGXXn5pdW5ydkPiWMBZeO/btv60mjTXyBKpUfYLFqdGinUz74rJL9u/e
hiRw6V8SedDxAUZWdn1wk2V0b/l8DmqbZK+yhJIMWl2RbN9cKOCTWa3zUEGcz5lf6uAk9ItwkLe6
dXKHyYp9i+eMxums8VI//SlAbWt1M4d2ld/q2iQPLDuW2EpzMqdf7I7Pf7ufOOoDqoKLsL8BWTM5
1hr2mfjH7sNhCJUfsCU3OupKQRWQ/1R4RMxp5CdvELjMWbf4ctPGkEKwXVpVtVsn24DxLgRbj3MB
k/PDsgM/hNdez6WE4hzALdFwN8Q/o3ENFTN4dqC9Dry5SYQlq9r3rTowEOl3sApSM67Owz/Q0cjN
XWWjYJQFoVVxdBkXRRzJyDZaqbbiilYdSgx0XgdEFNTtWKh+MZtW/b70/KZSF3MbW9B+t6xlIhJ8
qXHLilozconknsv8PjHt3ZQkb83UXxdoP7Zr3vkMZDAKBImABwnXaXabG1HVxCQic4/6VqV1QjU1
R7G8NitDdAuFh91a8LaPbi0J3yTzACz+BlxzziI9NM51JWoGuASf4mHZWTFnuMDBv0J7L1eD5Fsh
G5a7CmisCL07n70Yz0kzugEPVK8X5UXtEKUajodo5hPmuApvC/qiyydRCeBOGz5rTYqkDlbGKa1B
l4MhKz/RmBO8YkrYQ3IWELtwPX8S/sX78FctldObvuH1YnzoSf99HeqUdySAKdAzvc8qHmKy3wSa
SfQXxyMCJfqlwKmQQ1yYoNlAOOzbLsVLrxhTJz0YfEIJdQt9+5PHOnWTInw6AqVouvhGy3rMjAWJ
6vABl7iJl68x6g65FkSx6uOVefIxuSIIC9Br9JIg+ko8lB8utknK4JtydU4qHN56X6utLRDobUvT
ppbgb0OSdTqrMBLePNUseuRlLWXbCBbsyjgSQJciSDQxU/ShRI0Rpd2Z33CJ1wSwJPl4rCFPtVso
AF7UbpLkX5A692cZEjm/aOY2xk1IanGI92YMIfWjQZKXQK/8zWuZRja1Qo8dZ5pw+dy2jf4lfc5A
vhcLvf6/SLxVKDPn8sK2zM0/PBtmmA2yYkxxrUiIk4tsVmoFZodv1rq7RbKZ9q5Qx5TtQlfp67zf
O6Vi0CusHp03wmL0ZLgUqvr4GlAwcy378f6s818XGUKNWMe7Ue9lvP8x2f7d8x9iwpDZP2F7Rl1a
ygKA+Q6Xnb3DKV6uODdCbyROn/D1Fsvf0EP6m1tSkHQfY7ppFpBcpTxw4lo4zElR2GaoMXWcolDk
buJ4knbWxQj9oiA9ZN1nqaJEwA6W3KOkR6qlubU2j/j6ju+lIdpw4VtOH6WkUBepTYyy6I0vHh0e
IhkHSXx/KBFS7p/4GvjhLBLk9cIFijpgn7NFy+mPnrTxxZy+VnIpCmVxy5UDFHt7jYbkC0oNJne4
RrFxLiwpFbaOGscEt/4aOOTXdemCz1Q/PAMSg0bZZpwRBIF1Kb4pqpL1ngD2ZLpn4gdc1PbzWAIJ
TWRAjHu7S1PT1GXtx+GJwa1ENxrBjsf4uM8iqmjeeyalvB84F+/FjBfXeauT4GvyVtC0bq8JTGRe
wFqbvoHrRl/f5e8imGS5CSKxVDEpUPlirCgaT0vRqRvknb/ra0I/ONSDwSl65TyUf4RPZ5lvXiq+
841rhgwhyn0BGC1wE7Gxai/Zlzyp5cwyHD/AI+MQI5ju+QZgtOpZfrH/AApPPKL69rAXTw6QeyEs
kGUA4GINgP+H50XEg8goBKgWbaW1lX7Ag1MeznoRRHniIXB6U5Q5+05IHCgzJkMcSr71OGDSWXAW
izBc7LHx53ePGzBx2Ylb6JXpAMi79CvswuPs4q84AvbWPPDeFU/NqEBIWzq6hrMWchHgSTsG/Ixl
NqtMV2d7IZAj/DcbGuUoPupS/nIymdTMZZiz/kUOIHR34dbY34ZF5/qJXrKH+ZYHtRE5P/2gARzA
C8t2OQDSsjxk/HBwT6/S+AN44ug67VHm4rg9euone7M06X+MZ+Fg/TzuWHdfQfzpXDIsF5xzaPdD
3sago8rHu7kFM94ZL7YQaBrkdCgiCpFT+3HGd4Ibeggw0gibenbR+mv0sPOT2O3ScpPwhrVNVjg8
cPwKHtY9zUv6wj25ok82+i72hAvqUOT+rYbtscB1XR5IE0mpJIFqAVetLJKxPDI8IFED156Zhq2R
ICehAKg4luNrXYx/HQBym6EGneGk7IzhqZ4rdhlW8hmZ5wfNKmwhImc55L66yKL7304Rz6/Ourn5
280mkafjZFcd55a+Kow+jrV6Avy6Sv/C6IZk5XgmHyCnsaXwjFMSLk15W4oMO5d7VCiSIlgdJMY6
zLfsTgVDb25iigjAY8GfFvIkxbyvqJukqbXOUOCaAL81K+othki1E0QZ3LuwdMyLZpFsEgNXernG
q8d2nv27RcuxC2cU29f/qq0duhbgVs2W16Oo4vtH5hwU1vMnNS//0tLHKsdpR5hLA+m2UIk6jjCW
3cRFlB21GKvpe4uieMJGZCZLEjbYizYOqYjUOHgfPVc0COpw86Kudj7b4gDz/9ugFGHvkO00xEau
eWW7SlgNPPRS2XnT6CayGfBMPN2vSCC53fqCmoZUQJjfWaNS6hmsJa/fxM8Zu/D7wL2P6e19ehm4
SRZ49afV67B2ZtT/H2eNNC1uLR8ym2xR5xfNeOvak9XnPEi2hSdWHJ8TWiUwrdwrJyaR/1tM5/kU
WJgU8bNswk3roGkmQB04vNX4XilK7wqS4volPRZFJAd8tvM9kiidP3d0WxjNCEn35K/Srk8GTUGZ
ve0S+1nXN1oM6jfNZRTj6ZRixisqpntzua7FF5m2wpOynbczKS/TsF8NZjsRreB064fzmd6YRY/A
ETk4ZwpZh2oCV0efmd8g8TFlKkBGQZ8BgIpsdQsZDUfJllru940GTb1W5pYshs+CDaEpU0ZrGOmu
arGNzzB/KJDX1O4H9npBjPQWeX5pGT9iIeYow70poH0LFjPjqoU9oPvX46wRRhNbldtZ9FMvzu5k
puL+m32++RYq7yBYvofg6y80+QEE3DCYBDfkk2kWBvicbpL5qzMW0Z0kV+rtmzpOaaKNGVnOQZKc
o386zWntoR+7DQsn2GW9NDnds3u4HotfytOUVoQ+Bn6dx/siP/wbg/R+dzJFgiZ+WagJTwnVU/pd
WFuWXOcHRS1ykDf1EYZkd8rDXKqR69VAb43QWX6oCxo5cxp2keYi8L13BPxKYsOeXUMvDscB1iZg
5H6ZSX1/oQZgkoD5wPleeWi/aEgDXOMXv9wmANyR69L3KvOLTtiH2d7PyJIY9AMWVFp3I//GpG7x
t7q128/IPxm3SJR2B+eE9Tw36OEYCuHYDZaRNK+aYeb0CBkmuUl36/m+WsnOysK5P8B8aHfgg/aV
Nf6Gi8VsWhKYyAClxzz32cHOyxc4GJArqW+lxTqgAIeEYeAjqbfdYdk0qhPVsaHeSKf043gGEWD+
JjCaoTO+d5ryCX/SiHW+e48Ymcz21xfjsjAvkHAIyPGH/PcnIqdoCd++8tOjxwn0PF3i9dE7qk0z
CT28E73MBRvjQCygp0IWGE0Zzv/n99Y65iRtz0tgZ+bifT9V9U/7YWelGmZQ7dssBb2e/mOavHh+
QswKtkHasoJe3k7iPtjvkUQ2UlAOeCRaxzFsC8h80Z/nlu88tHXaow3ecnFUXd3cHNX2Dj8BgvN5
gTMwpOpe0oCCWA51dHFeo17pzZCJ4p/D931pp3pnyL8oTTIbz1IEExdbkRhw4spDEBEruhIMmyY1
g+cf78xqCjDcENoeo+tqOkkQkG6QnxgO9FkstyrLB3R0wPeAlqxsEasMk69aXLg3IUTmTTYExn2v
qR/irBXX1ODwgbuGnSSxdsouPOAl+0SN2PBKL1Xl+K9tZxln3TpmD9aNQFk0Rpf1Id38+1U3kZ+2
QStNope6O/vL5hWvmxFBw9NbCrQDq+TXMv9Odr4C3rilVG6Yug07CVE1DIGUkY8Zo+rEMUCHDBLR
s9DLmiZNHAnN47tBoxAvlKHHDNJE7cpaKTUT3eUelX8Vetq92kJGC6rr2nLUhfkAGSu4c2HWcl5n
igyw47ebdqxdvU3kP75NtTu0cVSlp2fi1Frl7jiYSDa25bixnVi19+xyntfuqU1n5rUZSYpCuo2E
0+e6Y3n3W+6QaJAZOU4TjfFBkK8fVS+Hm4EX/IBwMpmTscmfHkbGAv99aUmOTFK594i+ccTDNpjy
E8pybUPUwYXYu8nLmZzW9+plfWZpB15KhkfXsVRDyhx3OUDGIoKwGhWvv9OvD394oY+UZ6eEDZCv
pkUXK8g1oR/RjUQvFO6xv+hDjmZYjESlzXuBLaqI1U6pyNpAVic+z5F1qtXhMVp4OkZ0H7Kh5NHt
3NiHlBA4qw0LRp57yemYhMBvQymU7AMSsrF25dJ7c9FI8iaHNAIUxn7Rza3bFo/OsEMACbxwaKyi
cxwuMT8JcQ2pUMcQZc69P3F3ls7ZXrUv6T9e+MhptaTY4EuUp6H7LTAaV+9iBLsRkVh6l+XBi9Up
hnYqad3uV2g/gGIVu0vQyXqiGxhUjTKU9ZcGZWzvjZrIR0Rm1I/6ULPZYdiXP+L75jsAFYcsFCwI
WHNlyEZ6wh3wRgcYBWzD4rUUz82i+OpJ4XE0A9yx9gCHPEsy6gO0c0REHPQBPx+7LR3DMTCgiA+a
O0AzyLJcamTo85v+WjPVrxPVBBsuRiRlPpC7ybzuPyWQT7fddlKICnEdvmd8AyidOQIerjHikNwm
IAcqXwLYhAPr0enxrOzA7LKGI6pqRgwtVk6nUVlsdci/ZBuWMkElNni9LoXJrKzbEUw6VNT8UGQa
KZhE7ycAq/t10cxk8GgEOLinvT4vXKB1fg7Z4dxRJywZsTpw8Y19lwE67b5TeFf0a4WtMQyjqUOH
egPoM09VA5O1fAfsOO0pcyLuA/v2DHX9IB1zhSQ2lZt3Tf/rrmz3alziocvleg7EpkOtdoen3Us5
ZaPUAGQxhwyeMaUg+ci6VCXPGeVCFs+KKaTnt6nXCuxL5iOG/hHHpkvU0rsHjHBTYtXEL1Gxxd4A
z18TeaCoopEn70EMULm5e16Et+OpbMs5WjXfX1YPFnskXubUlqfLHI7bzImYUVt2GD9yNtcvgorl
ZeMYfugFoNgOj7bTK2ChfqDqoyPt0e5KZje2FN1XHigwzSgqV5r9vrQNsdeuQiaWK2s5ohdeU7WM
r2fTAA7oX8VbtJKdNYjHo639UGd+z/78QFnAeZIOt/dmmPYMkGPMX4ve+guMXD6h/U9WILaZpXB4
FYByZi836x/imNbQ0o/ybekwh/iwl7QKc06zhX/ld2jW+4xBxbheUzHMwjf62K9jhEks6PUEM7nw
nQiqYgKNUOSUPUnmd1gTBNOxtsGQKmvO/o2O7wBNb6PV5up+eos1o2hdOSAjAaAyGB1v1CjDQGYf
6UUD5WRkY8wi4Xoqw9oF8YmDnPsipJ+04ZO7y54dr5qrKmAuouorzhCUPLflcjkWNK95bcPEGgOj
WSw+D+q34IZpdeKkX0Q8/KZ0eyvgSGoVVRl+qdlXMZJcuI8izwYHZCI7CQXIhHC6s0Czn+ewzJAI
5W1OQ8Z79fpuf8NR05UCebhDn8Unb7W0aeW4Ca7snlV6hLGXujLC0UzM8BAAJc6h3Q3V38HvC0+C
q/OZU5rHxaLbq9GUVbAWWxV/q3m1PRaMWHrVumO2HDYj8L+cCr+aC6GO0zLpoDdaZ2TWAZu9WbHz
CbbRdevKfEcV59Nnrj955Kpkfn18CFFL5IYbOp00t2XkMnSxy1G6PPNkJB7qOVp+NXgdRwVOUbCm
4odF29QKu2J4cC4SFMJa2YzdtGwf43IaFPNI5TuvKNEC8Dd0LvBezxO38RNycCduRTT+JUyaNhLf
Qh53py3DtX+XtRghqIzlYPIvmoqGq2hGWPEGMDNrAjG3oKman3g1QdPnzo7zUMxsEYp5I9NHyjGl
wl4TEmH3mo2deoCpbEFmjb4mC8ipphNIEITRX5yzs3HI0fYYOK0bfuo2dWFgVj5sOOsyWP+lrhNR
gcCFXAuk/d+dTuOK+8vlCh3Sa9k+tpT7zWn55+GfsYFdAXhZmLdA8Mm6UVHMaD3XQyWWpWnHOTeZ
sTOOW5OKRlGtSc+QPBjs0hjl881x8fsZkBfhzoPB9uqMI4xRq5dp0IVHa9u9HXRhDHeWXOeyVSq4
MxOVoUka4BikvgWBp9NSK2AE9DnTbtYZ/nvowqHPV25OO9l5zSEovlDz9Z5H+Z76v5euBu+cSqSC
9ny6vlVV2C/yPNrBbZkZ46sEpaSjpqWn2+tFlZX+LMSkhXdCOGNPT6h02l/9hP+0IuaPryTJ7JfC
06+f7ftLCBwZBSqSc14gQfPDR/GdNZxIRMW/Lxxx6Eu+5AjhMpFhTp9Ue1DIQXNvnmItTAEtus5r
HfohYZYzaNwUbyTqVk4PCU5XZguudmeDGn0b2EM/Fl2zG0/aAs5qwNJ9PljIT/1YmZslNTWlsgFk
djFCKdi1lfEBgL6vDjmeklEgapgT4xX04Z0g200YVvxfpKnKgggrQp5eJ40flhejoRwvHlHB+7ef
dP+wSfd6CycDP4VqoQ2yuzj39VlOGXx1xMe+kZObULJsKQUP1aAUABYWDaumbiZQXHHsyjRDqyPB
VvORVzcLC/EMtjibXn5yusNKd3xiyXGQs/i1c9eTWCZBDPCG1vibzhR7MLde+D774cDP91DIKgMn
SzNr+AiWDnWmgtVUlAoxydohMqnZXmstgSeqP232kwP42ni/P3XP0ltGrdn28caJxx1S4nipu5tv
m4+tySuag99Qmbt7DBQ+cUXKEtoU2z6pD5FjNjWHjVbpbvK7vEX+rsY4/Fsj9yFZhJhi5mAzviF0
tl4l5KuBRB3H9iZFtqx6ttdR6ro5aIheAEFSJkG2UkrCRl0fC8F+ghJCX2guL3mHftg+CvnSCkNJ
KDimmp6OPoicQJg+258QjyxCh3YzvqrW6vfAhuw5cvbfkCEGVodG/TW/IxJQZ0TpOSJyyMgzzXAN
cgECdIRwEojeHEuzd2MvJdNQqra9N1ToLpNIzVZ6y9mpfV8+UKpMiUgne0PYIlzl9fT2AckStRUU
8nFJxWQWNJEAl9es0trWNAVkSkdEHwYBiGAxy8mVTUuGWpqiATRmWJX+msB8bu7aXNUdX4bZnAMS
n5ctbuOwfOL7o02LJAuaE6wqZNtmWX42dwnjVrJ730QvZOE3mQGNgFFSNNOsttOLH9xN23HQT/sJ
LoUk+Dpa5ZErMFycYZToEeKUHRyifoh6W6XnNbki5GxN83dZamPi1XEwNAapJQCg70s/oMUBy4qz
RfDJA0nY+Vuso6GNpECwz6Sw2T5e5/uw8TuwtrXBkMN0o2CidWjcSLtN1MScW/VWUgcggwvrcXAy
nW27bVuLjnC5FoS8UetB7VBfwzAFRMxW3NIgr90CGLXKbrkK6tL0qpDUpH/V9JdxabaQrC99pepy
lkl++LdFKtC/WLN0rMXTJPEChsjETigmPbYTjUrl8a+JDrzWJxMGAXIzsr+luUYtxh+iXyao+Yfn
RpLreZ/9YLivP6pn9MpviDK1tlZl0D6fbHJqnEW7RXIWmhrgf8d0Pdo2W4kPXwrSIuIPLHYL32PS
ssSMgCGyDOw9DE8xf75bf6KFS5JOm7Oq1nd6kG5q775lnoT1G1W84MbFcCHmfI2Iv6zeGkqNHQ1c
A4XVaUhR7CuHSpv6LOe4ZpkxS7p+TiRc5pFQV4R8PuWv0kDo3mHYOthb3X42IpL9HIG4glpTW9r2
gBiFxZpXD8yPAaZeoH57OoFxmyfRjHfuooPyTDd2+fwNBzF4F6TTPhoAGUxcPyY/HaMM7tgI9mGa
qwVz99eg+FelBBXu/SAKlpIn1o9sRk1U5S0T59EDnJwwZajACo0bVUMIDVSoAU+Bod/d001T61E6
lGY4R05USKBllzhB9UViiJMVu903pMaUnz1S0h8+ztmZY2AOoaI8POwTcW4UoTSqzy2Ap61ZMFH6
CJY+BLCAswzSDwRJKKtfwSTTxHsnOfZb1lsCC98xhGZXNRHqQEAG3lsYY/YpgZ+5Sp+UBQ28YzR/
ozKzfQyRJ2ZAtlwmSVQ7w7CO5PCOYHYbytbV/kgQS87jEnVj3K7Zxai/Vx7t+K81Fj1l5WwqOxbO
fuBWrj36y9RRzxJso/CsuAVMGpPN2r63bzOZ6SbcvBNsXe1ZZsKS2a9nMjkoUHhK5aX3OgsWFsQa
djdYntn73mYAWrPTjzc8dhwaw3+QZh6xn6I16imheQ5UC72JMyn/V7McZsqIFJ/my6ltYrtsPQjF
5Aix15zyR9Qz+6Av1m5txWNcmIlyst0Wj9fOLKbUiUYeNNqv33fPQPCuX6GgOrPnkR+wqjHquReb
igwFeNpenidPmPkjaqK7HqM+xBrgilhKfWNVFL3bFFOhkHiTjjzyfG+qk+bL5sjonmpLcAex3p9A
xJRDQpG/qIpp4/ge7qHC2+kqFYZKDlUArFv/pwCREKi6DIgsh2EQTcrFf1dRVZ9ROjG7otYc2hzu
QZwi6B7hjSwJiRtuNWGMKK+ggVdq5GJS2UmUkgLnTD7xV7rCChsOwLbULQMRz/noLwe4fuiArG/x
FWeNF5tEJEUDIElqsrvi19NKQ16Ib8tBhl68b4bLtTp/4Iv308j0yrSlsMvFMB+iICPU75AfKbqh
md8+j/fKCn9hhQ3CeZ8OpF7y6oQNei5DaTfCHwOeYhBqteIbMQa9NV+r5PzxOKHPq9BNZcJDdU3V
V+tmeLpybNVKHMYDTq802SC5x6UxFVRKuKDsIuAp91Wtv7FQHIFBwmiCRbkQlbJF0/n2T9Eaag2j
5jAMpNEa1I4cxPK5/tnTKOUsgs1n5k1c38VHb9AtFKfFS9SP7PQWBy977LtGatVWTsF12wfBC1hp
3VYxLtMv6t7fsUZHnH3EuYvw/PbM2WpfKTv3aarVxY1KNkL/Frl+XKQ7Y3DXSqHKpyH6l5Usj9lJ
HpVx76BUkF/raZ6HRymj5L63onvKSUA3PA/pngwS+CBGC3YE04MEIgQvrDgZkF9Pw+MI8DBTIpza
3IVEpzqWA1iDPV0+XS5+Zbj4s5AfOBsnKjvHiUctvlh7+qgXeXiLygVhbNW4P467Jpuc4L1iJC+v
+LlTkDJPpmsL2OoBEI6cVmN/Hw0OcrzGuZy2WiYjHGs0EtqKsTaGI0FX/Fmjxr+mE0c6iQBaaaeE
tH4ToRrQ5Gq4Wyd1JS3+Zj9cEFo2U7kLA2RXbU8R/352AFChGDQKh5fWrF4Jlz/qvCHe68NwgiD+
OeUSleH386OGaxT3lf9WWZn2MhIiwDwmJQoDFI9EFy42VopUvBwyuUlNtHnQmm0a3At/k3NUvZVs
WzZPOeHncgxNNSZMjZxwX3c4cmg1tgGB7v1tvTV/mv+iNaJfmeAHP8xvLqZCG+Ki+Pcl1Rw5T7XE
wE7lpSrI5RvERI3pjfo904+XjpEuR0W8vAmXSgq4AKpGuouyZXXPBPJw9WXnATNhzn6mPhE/SGnZ
Wyaz1o0zpEy7usW3nZOZVnvBzaNpUk4HPmGeGyTVixtEI2lgWmiCrWtr7sKbrKGUapS0QYK71rPd
uG89i5qpQ6xG3p8TIsCdvi8XjdpG4wTTYrKZ0FD12nSiY3wMcbNjBS/lGyPjRuJ3Djm168ccuTcW
4URzrk9RZQ3rd8I6FAGzafx+r4b33UqCnXtP4fTr5BuL219ZKje8RbUcfvI2FrtumzWF+06EF6UL
90KM/x/7uEMli64aOHLh0QcPDiwiHS65hMC93od4Ku7Uhnt8mR5gBKYeHdyKsM2T/ogSLTBRlwn8
6Vri9Cbm1ifzpsknikHp3FcloMIHsNeRUMQOqJtTqS6qrBYvn6SOKiCQHj6mtT3QToPu1LrjAZRC
IhMBVaKSbKhrnTsmPOALrQk4KCg4kHr4elDF1zCWC0fi7dtuFhz2Uu68XwKe3Tn7OjxtK0KZFI+F
neH5EiTgZGqHLEpxdQBmUpvWMbCHNsbdv4HMKnxNH/6faVNn8utTTuh2gl5ztAWZL7HEWHJ6KZ+L
3ng4aKDhtSIgIzuDRZ1vvxWNgUR2gtb31zmEAkFw+wJfpVBNulscaPcWQBk/8CV5EyH1FShnpM+q
tCdgy4XAcEI4CJc8IWh+x1qd0CN0gVTn+Gq90k0uwSC88PvZJscgk+3aBo62oxS/v7mpmH63cui7
cSfGPvR2lUnot62dvUcb/9kWuXJSHv3v6QY8SLM40OSjzx/qy/zQUNOSo+lSEobRBUZaKRl61Q2n
UKRpQXiQICWSDUOeHxYr9Ir54wqarfC9Yp1fPKfvcLSp+nARDxyXbiP/DIxsG8mj/iv+YdCYy9VX
ev3HwwpwSmOirAalk27SILGsdydW/Sm/N9euTCSz2j0mQpagCdLvYnAEl1W+1NbdHJF5nbBTeFGk
5w5uorSr0bQFwq8ia2ThrmoeDd7u3o0ILMgPoMuAWXt6GkPEVvRPX/GXd0y7w41jDfw+40O4oNMp
lf6Uiu+3iLWjAwycIDC6vGMzUFKkmD5yYDJ/JAn7v5yrIGDDZwZ9zsSWd2B7SLlZXFz6prddSeZh
YVgujGAZuJs7uH0KasulurnVP59NjiPvQ2XE+HTLZx86fNJNozcRs1thZemllFhDkP7h/HJPXzuG
pDY2PVNuQ/yYr5pBgXLpToyaRXNU03BBfCs4px1BJfmd9WtBva4rkSJ8yupgiU9qIPLHXafwuFJZ
CbTxTWeoX/kF/n4LIGs/5BFMxoggyELdEpLT4mogWDOpy26lHCrJbWaqEcGdomCR6zy3v7JVzpxO
LHmvKRhxAfJTk/631X++q9Q3TjrB/9jSay4UZZFejiCnz66kfwU5E2iAGQ4JnrcVkF8BkzSK0tO6
7LKiNSYmQq7/1fyQ4A28VzzKOVq6aSyMqC2JGx6gKf/Hu/Xl1OcHyiN9u3b4NjuOvZbB2m9FqvLZ
UfFoDKKTHR7+qE2FqP7juACuuYhDyAQtCisob9DryFzZmFTMKRJAG2xuLBZEXDqZLfcAIOLevUxs
BVIBgXyWqC6FkqQg+gFxMtyl9YzASc5iRPBX2ZubTzv8HSg94BKdD85UN3feUDu5XTKe9FXxLCzl
L+ewTZAE8WYu9w3zkT49Vpe1qUlVm0A8Nbl/p4tA3nnBKW+qqtJbaI9lK4zL7BJuWsfKC12EFkav
a2F/eQHpf1yVQxdViuhO5CGu8RZKFAURxfATE8OyoPyGCR9W2+OuURufQaV+yRRnxwICwxLmOhIT
Rs/iydQ+PC9ZEvezC6LCxDrlvk9mfCYK0nmD3bb9DNYRt0hpow+cbk6mnYPeb3pGfGGwZ2djVs6q
XbUZml1DLsvaCyF6W2caRhtCSWamGR7l/6Me19a6d24ddFrD2g9cPnGBDResW/KgaxHVTYJlHkRX
pxzPDcjAo8kCdV5XwJ0/cxns9FNguPi898ti81FlCkp/iSiMti+GHpInU+HcF0YGi70+ibP6YFLw
L9oiDKWfewyq3wrP9nuCDqJv/u58ItEiUjuNtrqMWKCCVaLHqwGAkpt1uqpy3yUbpk2xTRHGq1A/
XHoDJwOrwb3eVLRodDHJYIoNUyb+rOE5YNyX07YcSOvhvWDBIL/4cTMUgdY8bimO+ktYHzqagt/0
MS0j2fmdoE6+2cYBiK+yISTgmMUVLfYVN7GcGdgbssljRkJBIc10Hzz6qBcYD+lRcRztAJEjyniM
pw/eqSlYHMQdKmMuBVgMnqHAWfhHc8ae/5LIzA3XSNWnNAZZgar3JP7+nhwR+2zAS/KIVRrRUE6w
m8E5bjRoq4XR6jiCUm4JfVnWGaq4i+tV3mqrQ/7LX2MfYZuYrmtlJLZGAYJPyM85KmpzkxhXcNqQ
jJ3x4znm+CylZbuoUDCx//q79rDHXm20FxH05leqyGJAfwEpp7rtN7ecZKO1fNb1q6fntoEwRrmn
KmTEu8oMXjHjx2MNBUCJPicSpoUxFvAkBu02QntOU+GCiiwGWMHsc4BIPzF9eQkTffBImwulRyrL
NmYbj7KgS2RbQso6CzJO/E1JZzacU6oibQ/mVKHvDoeQ7kV9JHmJarvmXgnGkBaEQHwh9k1Zzqhr
Bkb6DetIvNiZekgM+TCDdMypps2TUFoH38s5C3Zhk4RZQnzN80vYi9jefqSVOpBRqKggMM7LPgq/
xlQoxH+9gLF1IC3YehdyE6j10kY7IY0zFMcO1UrpX8sBpr9SP81hcbcn3BXIi+EEX/IhzGLPP/Gk
GEYy0jfZvsfwRkU2aTmep+N5o/yAp879z2DTkyID/MHu1bcla52NnnBDltIc8ns0BLGgzopa5TF7
7+sIgHoYBaP5zBNrl0qfmbZrQAcfAyNgcYHmVguZpjno4Id8mkfP3T7koqv1AQcce7jl0lQS5mqq
CmIwLzZ212QraeoApD8pBSMciT+U5M6HGpnc13HEWMACA6RGmTGO3fsg9AVHnLhSa6ZwxYiseETZ
+4RDU5wgOtFoOvljUIi6pfH7h4MKXIyVdu40Ky2+VbkeCQrCPMBpsuigSDdXujz3NdwP7ukRkgSc
YKwWZbsQ2MDeZeWf5XhX/LrDYeF3LLSeUo14oaNwrrA5vAX6S34jFMvvZJFNOgyN2yV8p0jajkcv
KBGudxtCYsmd8dny/Wra8xnEbs1UGc4wIi0ylqgtQxt/YDduqhoM79Y6rFQrVukNizbDcLJjIj7k
+1PXiplxPbZDk9P9KGoCXfIS0O1JXWwYayLoxtkt4bncaSZiSNr/LADj/VihJOMjUuFJS3aJPjJe
xNqt0uZxfcw1HpiqztMfG4s7ilOZ6fGZdn19YiuPuHOVNltr1UlrV8k5R3YEYVURBuxaSwWnaHfP
8ZAOy77/O7q1oINuZpXTGUQIPD9pq7RjjqbQPncadwORODcY7a4FjdKCZ5+nmDR93jrByaJAKfNy
/Bhzmg6sMeiuJiI9IvoH7j+TQ1G4AfeAnklo1TVNU3aKhjnlvEpLhPeYjAjElSL2IHq+Nim0Q1Ft
bCP+FU/hICsNUNJ9FuT3Vq2Ar9QA/DO+Jd4DA1v1pyGlyhshQc8JwRL3gLLKzXVyGDIIGS1ljYmP
x1BLuBWOiRApMdy181UXKXZJaf0rG+AsQ51avddfznp30OvlsEqe0Nc5ish18NfBGT8B3DD3x16K
oKV3vYawvnihrrPh1i92NcePEZ9sm4lxY4NxNqEXQykZnwUQcTj6OSctPGt4IKmtJWE5zzGBEOhJ
mbj3pODTDIHTVohyvg43wnT5PGwH/U6RQG2fqq1v4fFitFGxJOOjjWSpsBq4/oX+saRRqFqiuneo
Nyp+2v+FnNYvtRdbB6kZ9l7MmB3UmdfWK28lv5u88HB+zLmDU68rdisnfvkfByIupUalB/mQHkD1
KVwQ4Me2qk/zcgu4mT5HUVHbeBhmAaE/JYL+uTglnWjaDNshLCB6/V5tQN/CfTMkA3YVEqkACXRE
Lay3d8ioHIzeSGEB/CYyv1CZhFH6rwdfE2uY8c+Iz81ogjmNMmZEDFwEKTTM0UWekTLuFHRxx1IE
30riqoroibKZ73mNz6sj6XRA4w98OgId/A+ElG0dJ3GJ+jv+rkA2xBrBgHnxClx/jUcTHKkEc8K1
0j4cv++A0oyh3HMaGhn/NcAmsAXi1ThPYoM2xE7ElfcxU6Sd+0jvcdx2Bh7c5ma4ZmPU/y71t+X5
8FR9RroC9rg8wLxaGVBYUizQNvLeRd5SWQk5B84SSohExud0PNdYRSMxwrG35+jeRZh3Axi+CUwL
3OQWVvLy6BfTgfq9yM06NIJ6Dfr0CeuUt8Ilg5aEW/2hXThwNqTLL4TutHD+CzSIDWi2ExOUVsqO
T3wNw/RVZGo2p/eGpYrWGYKiC0rOr6kaa2N97q+FdAPStIqix75outByh5pGQnr9SPgsq/GZmx7P
Kn5O/ZYVPeqN9IvLTnPE2+ueii9lWxL8L18qWs14Se5G+SHSdJG9NDEp2pBUSMT/ZQBfCv0scmDZ
544QnBspc0xtYcdbCtpkc2+WxKZ1FCIC2g/ALGKTo0GJx2wHApjsGmsh/ELU/bXTwe+mgV+eyTMe
Q4+xqFk/TkYrnpK4oWgYCgtLL/vSI5N2ghPY3Rp5q0n7Rjl/6TsZjgrUQ4JAX6dyt02fePi+dz68
jDdhUL7O19HaRgZVrYt8LS+L6FBib5J+WsMCo7FlzoRcepnFosKlPWuv2otseNCjAkbc/80W0NTf
ZBrwHVqL7Zrht092t/OV2LMc2oioydRh0p/whv/TaewRP9BuTuK1Ju+/EFAfqlnVYgrhxtdve3r5
haLI2xx0nDD85P9wYIRmOri7Kj8EZOkX8HTe3NPfrqX1kE29zQ3F5/8CsyLhdW1r9eBW1VwCWr1P
d1p6W7fNLXEgrjz/813utmPlEbdRdbh8yZ60x8FE4Q5FJzh+H8RWsz64LNp7dN8Q7ruFpUqHCj4V
8Fu/rhlBQJVDOd6hcF36ZhWfxdMI0e0Djp1VmWkIO670L4epV1LL4FK/xnd8mlyqA+Z5PYRgjzMx
+ZzLIpEwHLT7trhwUXLEZki2oiph118Yf1n0E87qcRm8mtt19LBaVWUC/ebnuQvK3/8gRAJeSRis
1K+aZ4SpXWgKG4tUEh4TnTYAZ7HmXP9uCa1jYPosQB99oZ5PrSMtHJNsQPpP/flWNWnibyYbJxW/
bHfqkqgy3FXD6o/QDIqHHVm2wUQR01JfpBrsiCBq7XVPcnwbOcqsNZM6QcmODM+yBJPEBKEzDYzz
7x9C2fXO8Rs/8uZODbP5LAev3Du1hbl38ifwaXtDLdBZ51hRwGezhWR6Wa2LR5+TszgjtU2SgYOI
avER9AOMptmYYsNRjsgfxA7PLRmn1OU/480Durskb8faAT4mk7nH9s/wxS+ARnyIpZyaMN5tOxwQ
dSZw9T3VTYyQwjPeHO+pzWoqAIp7gDNefW0UzP26Hhv4ax7fk6nKPB5PMn62GQYPG+jJrdriU+PR
GmXduDAjwLDgaVX6kqsROXp5RlDxsWYRpVMRrtkW28pLWonx3lBF4+QdWqAvw5sM6fGN+y4izcT2
22HnwtjzAMUBj1OYR7sbaL4Z2DSWx1GDbiqZVk376XtaBrIXPwIn++2BBPATkkSTinuwqqAVFzhT
nnjqt8LrQmovsrp3DhIXVk/v/rpkl1vJsyuAMCFocY34oWsNgVEqtM17Rn9DYKS+hh2FVMT4i9Di
5lipIM6a1NoHyxrkxaB9L0QivvfttSPI2mJrnts+7pmopxiOF4IjPzNxMnBB2fe/WlaOUISFCQ8M
Mlsu3hLnT5X7F7gdvbo3D87OeW+JvvMFmxIjhU7XbbiWlDQR7XsZ/xHxxddljUwPPyLoXDuwlh7m
eLKcOXwLbx1FvqWCI1UYST3RVRLhu7yLM56UCjvyIefrpN2OJN0tMphb8vz/bB9bFvgGpXtUiV32
RQIlA7YqVzCwAWH9gYw8A6x0XaCs8G0bGv6cLfcxcqDCafiXhGLD0ZU18UF9JZoTsca2nV0HYt3D
oS/HI8BgWc3DM9COIaeet30XX+c46nbtfvY1P41w/q/w+JBgXQBLnQwfvuyEHBkAqs83fnMM44DA
S/Zq3qYdBqkr8qVwmPcezx9WF16E2xFapdj5fn+WkfL1OepA3NE22loXFRYXo4GvtyihVn4ivNln
+H4oQOnFb7SevnS9gvYvIxlisJxeuvgXQ0Y9bicCsD2UeSTOFAKFG2Yxc+y6ttt2/c87N1L1T3aD
y1RuukK7zv/HoABqDE7v0sKo47FGMxW/sopBJk/YK30KFVgx8aKjAm5NMkwGCx5YZnayqm0swCj4
f5CzMiYBVlqz64/mK9H1ESEKQ5DWgLEopzYI8lN21iurU5hWJxzP5ouwBZTeTJ4SUwfTeGSG2DPi
YCfLjHTEDmAZU2TUW/tMnvNxytv0DbaX3Wmq49ngrwrWht/W40ZkPz1jKude96i4LM4ejloO0PHX
K8jKu8LUdjTshNXGD5uFtctXeaHDn+P9thiVdDMh8YCqSPwhnnfxLz7SyCEocFLdGVdjZAxBcNcr
8ImgMYVczfHGuIIMNX0t6YXdYDrJzYQ+qBj1b0ANUFqoccQocm/dLIUl5Np3bQT7dWXyi9hP8NDz
L21tV/5rIYrnZoc/xfHFoZtAq1Um/xcd7aD91d+/ZCn+x6usqhkKHO9JsTp0v983JPuI9yfrel7u
DWbYft0T2G6nOXxOXskTwiTOp39H+4XUnBFOIgSAvukd4M304FnTIKHVeN8rYXHq8y1l6M/nxPXT
BraunvKiJDfWs1Tsn0b+1DIUcmP6QXcaBvDCHzCz7uJ3hWXqZZCBN+ZB/ISrPirXutfqy+eAbfLe
qmez60qq8zOtzPFjzvUoBYKsDseVkGm3kHDCLktARmpU1yw6v9Er/eakPQ6otbEs69BerZuAPTIm
DG0TSr0UHb/RTM6E9Ny/zTPAS+JLbYayTpVu2O5hmSiqlNUb3KO9OrZP2AqfV6Uw5biIiPkIKl3s
7+EdWDl8qsz5v7cBsS3/6qkopGK1HJhah0eQzBPqZB4e/iN5CTKCglHxkizVz7O1DW9LGCW7fBCi
BGJPkbatRrjh0xKIzms4W6eLisHTjMez7ibKISUNKU4ptXCtehoqHJKbCkIXgMM/EXA/cqGSzRSf
XOCqOYH9ozzMZbNMG/osfCJhn/eJb+nAGBPdoiSE9RQJlR9rxntdhwq68RT0Cyi3reLCrbeRblG+
eku4LsX0wGsoBwsEoaKaVFnvgHQpwfFsB9C8rn5Ps+OOADIhweyMX8yaf1yJbV52ByiyX2g69RMr
DQkKf0W6Dy3MUvS+MWHn3tqS596fOoJvGf2SI8xSvqpxDI2FZ96R+dFEOJ39aLtQhVSuoXfYESJl
rX5KOlTaG8WjyHw21/Q7fVeeWT5yFRbZsW7T6muwaX7s50caSF6+H1XKvL3nhcRIs9bgaFsFbz59
7dUJWIAVhfJeqswPWNNbCqNkzBOpoxV4nmJ4aJ/lXRu7I6x4TIsccqVe5eI8yW1MCHqUbXitrRpS
Srcccyj+NI/S50h3yT7aC4Mw/JcnhYaSmdkdHvgZu+acrohpqpA1Ofcm5YNhSv6Bz5aY0K4JPMQW
XlT4oiuwYqem4I/fmChnhIr81NIsNnIQYQfk0GU43lLXBqMZkbIE0NHYpbYmbY0oR5W706Nh3jXk
Ns7hcnyuwhKWLuNN9GTwf6tX0wQ9fUamFukNcSkq7U6mnIjfBUulCl5m6lJJv0SIzvoZPzuBnl8N
cvp7rN/5w5zFxqVrLkDMvvvIOmgVXjrEh9oXJG+3soPsQJxY3EBwXqrFMpAcBGASNcOu8GvfTk+S
0ndJ/+gpcwQ+Glgv0hUmgT6/k1fjRn+PAHHI1Kvn+GwUrTVBv9z/KMVQ8yF0W1PEIXpYCXSjRUL1
els5w5rbEa2a5dJ60M/PV4l1NCeRfUBWFLsQbnjPK97AeUHxPewX7aRcCL+OwX/6jItnkw7cqXw1
7ameBXMsUNKXO/FLdEmmOTlilmaIuRUhL0G1MEYT2nJeW4aha8aYdDPEnPfvNCdpJB5tmF2zMlom
UGiy3kOxAo9jsPUnfmVkANCkQlFU1PSJtkHc+2XXyXhHd2mWIrCAytlaB0Fho6WwH8d+a8OjyMYx
sYXitUJ0pg4ZzpFub/Fhzxy3BzpGhCiv+H+SceYzkiHeVA+ViNgUULTb4nR1T9TbDuwU5NX1Nljs
4YgeEEZA+Q7+nh41hVJOVHknk+ZB8fHUMeIqggdjQ69N2IOCVGf7rq6cptITtLjeSNzgLaGXdy8v
Ujvln2EzViXj7FxBCYvESEwJCnrUHL5F05fmJ9MhHdfNxWJoJewf+jwzNAXuZdsJDt+3/ywR1zkx
vpypGjLnu72gVIfkld3R3YPEhA0q1ScPUtk6+Dh9tRRaXtNlRlOAFor06uZaebnna/PIJZsWDZvm
4/MYCX60eo+d7gPH6p7EKSSLehbEtEPGTMb4xf7efpsbnhCxWw1l5CTUp73iq/P4DAyAlYPW5Iat
VveQHKYJufqVm1uiG76SWCi65pYVpJ9cmn4iLLflWEqh5umgW+il4AuI+2h/59aZZcamIhoTF7Ty
DK2+KIGYljyQG4uPqy67kaHeccgYoztNUr/xzo4zpN9wZOx8SW99bQrPJz7HaNVWBZ+gs4uQu6BH
1HPlz9pYv9/Oa+uWfznI7+cWuMAC7rcQla9oIlkUThKs2Pb0lAmyzkLxXwzuJE8lMAq8ey0Yqfi8
QIvMvAKVLQR7g3oFeUJ19pkwardDplfyuhEltHSh4m5tZl8+JAAbLxBGBapWVMpLbe8NUgOCHWd7
9uSc+Y0QDxOq26AKigt8nPENxkDWzdcsKm62xzKTqERAFRmyin+28nPQ4AMhwCCXj5v+I6sNZstK
qiH3s8X4ZbvHkz+KXD7kx9n6ZKUvOEFV4+SZftDC6Z7OH1E6+cTypPAqIWmVqE98GxaiiLxDpTqI
mgofCJaXrIrg6Z2Td57iCW7mUdyzBolXoyWGlAFtojANisGRKJLt4GCypgEAGMXFZhsPr3HNVARH
wp7ofSsWMWS6+88eF/mYn8sUTY+3MVER4Bd7ewjaQikLIeCz0ypB1F4y6VjCoLkbHzvySOnt+/3Y
fHO1xucRHhKqciH3fYzgpSddTBHMhvMOQ8gdXCzgtviHNeyphE9ZhDNc4/uBZQ7Z7awCd+dhhaOl
BIV2t8cbh1cgM1CqxPBv8Z4QPy3ziXtVyCu5FRyMFG5xo5LspRMHczrYE+knum8G82AlJpbrDeam
Y1JyVE04gLl0FEU/pE1kWmWw+9zZ4xJeotJpg6YZ30ZkADGl1e30AMU0T8mG9Cv3Dbb0dYNmIIgV
WdykMFPFJk9QVA/D+1e8gN7DhVnPRPg5LL/L3U+wHmbNsBrsbHdd83kdA7fNkdLVNjdoZgWhgrCM
If1XL2sYhMKqw9ZGlsR8W5jPd+Ug2wtkshMIJoiL8be3Th2Tu2ahX+rtfQvhaofz4xHoMN5CrYhI
9DOH7EuJ6A86YOM34+MqgSibHfD4RL5lqj/545Y04FNIKNmsvRORahkH+Hz17vE2+2JL+GH6Hxze
HllvLfK/+3w2UoEFHjhqyG5nDP98rSjrcmYjXtcEWSMG2JMvzBd4Af/a9leDuEyv+GiI1g1vWJsR
8wXm4Du0ykWn3kRp7qhM5i3yadKgima1CctcEJJHQQ2KhSxF4iYk6+EVyWY950Mko3tULGhs0Ws8
TglT+PShtvf9GbSRmTFiAcyD5kt/sE0tOLGYzxs9HF30F5XieogihJ9xz2GqpgoG8xJBIKO1TFqu
vbvgiN+HEN3q5VrA1r5pwCdd0DM6PDMqp1/chMEr+y+w7m+GroWyUvXzgLcBsIVNdtSLKU7aPp1f
676aYchVDthC/ZU+p5GAjbIQvKBLBDV7u7LtSHbixH61553bwl1b99mZLBBVk4qjyaKoKqeQIKz+
b/14G3bv0YC6EFdDydPFeYjEjrHGivt7gtoMtFwOgdasfAHzDRRzt4UfggwPLy6j57vjKPumNECg
7XaIyXBoRxn4G1/NVM69Sd++vibf85V191UphJp6jP4iObqe7/a97l50wqcd+5YDWEl4LkShdPoe
tl9daZyRyCLK/HfN//lFjsaQLJsF6ogZ6AUhltp9jfaICx4HptNYwSKJjcN5NNVSFCH7tnOxpn+q
y2UaZbuQbFTNJpNR0Mjeat/eTzxCh00wUqdUZoUjRjlwHQ7tzIock3Qw8DyQLUyVyxix8neQfiB1
me4fNhvujzxlKyUaGI98/JYGyYNIxkTql3C4QX3Yd99At+d/Sq21JfZzjgRuOnqDkjlfevKnZStV
G3SeK5qfCy7M8HMo0V6xLZ+ZZzvLN1637zMHUfs03iElHPKoWhjKNaoQzBefFdtIeKr5Lw3DCC2i
NpcX761UaJokHj/nbLZDCxgCle5GWEnoI20V9WUts4uBFVD/WVjsKOwMI/tMJfLRHGWq4oaFicQO
oDWST/3UjkuJvIVK36DNNyGzMINI/0iidU42H1T6pv5RRvocHEE1Tqhld2w88mnkJfvFooDmVedw
2lON65sURfb01m+g6y7lfOYp8SOzxZQ+pvpNkisOl2X+n/rnkPesE8s4wTGkCbntUKh0B9JRkd4K
x/g1LLMMHsXQJwNIoNmyK/kJsbLD8NzD9gAz9/SCk3cFvoHBfq02bZ3Io1SXFph0tBAraaKEbu+L
esw7JnCJqT0vAL5+935oqOXKGcq7q5nK7fOBF2Dt6zdfYePNGFmUWVyrIKkJxRjAlTtnBj/W8Bks
Hg+VSvv7Olis+X9r2kcuyWJ0Q1g8czi2BgMhrp0mtwdHWU2tGebVql5TXBssbIwC0pblZq61ebo3
nrKfwUowEoprvjEuv6VLjwPI7eQv75EAzZLBu4SEWdEg2FzH6dAdv4v6+lIG9MCePW2vErn0lJfH
WgdUoW4IDqUcnK+IhyU0Gak5Mu6TmEkf8cq8CpCaHshVYrLCR4a0DaogspVBGjXq6XvBQLIcjChX
Zji0W3g2USgN2ukXTsOJAPQYhUfWfm3mNNgduFV+F/mz8tnQGt6WG1J6mnn340gOz5O8jqYQMhTz
CJu9TUOdDyhoe/WRKj7lOOk4tPfR14c9WgRc81BXf/Njxqd7RyN75Le3wHJw9/P4PZwBB12820B1
HPRM9/Acssyb3RzedBDbmGlRm2kTIJ8+LKJg6UZrd0N/SBe1F8BLkZf/bOjgveupdn3aQMDu6Ls2
My/PIqTjbnQqW4LO8k8Un+JPltKM32LXO+fVvUKQhIMUnHMvplhPz998I9NslLuF6+pzpNACbR0l
VVvUTkDa3H1vwsehqo4QztfHH+zSmY2MN4WSNySLiRvaFPy2ZvL+TZxD+qzdeWurevu/s3gnCjdZ
IxQzUY7ACJ93/98kI2v5QsZFfjq1KyG6/mzyE5976Ky3GWdV6djhfdabDj0sN1KHfik4wC8regAV
95deSVIXyQFD3axFbNRwUgdNYIfy59q84kCaznyX9d8KFFKtD9/FB79H3aC5t14o60gT8+ZQ8QVz
STNqIJ2+qfBXxYvigANGzt9vYh0QodefsTPaD+OATmKH+u9t7x6JKnDRzcCT4MxTDi4Y3sABbJe5
EuFKk2enY3AFG821qx2s/OTz9OkCsYhISd2pTSlQQri4ez1PqX0SJ5o/P38CJNdjNVT9/4MYgCwU
3ELlHnJH8k//yCX2Bpjt9ds3D3fzALLPHvAKgxWLAV2FakbmHevjZTDqG4t9Pjge7Mu05+e82aI9
tzfckhmBVDl0uHktyIxe1eReS+WmydP0BxEWONz+cgpAHRiTp+UnCAaYyfEeL2T1M8koLMC/ooBf
ybaG4iKyCDVDdlc27zgSDnxxO2DUy7nlQ2bX97pNj5JMH0vmHyqRSr++p67R3rS6my4VVjMgB7gr
4cqKPtMr/sEOrEjQ7fc7b1Kgt03OY69i3rrxfe7yASJAY4WtQlvqCk3xHEeRk2Crugj0l9dq/jAt
UgAWpEyHKtljg1Brfl94+0n07OATnJ1jDM+IUl6sl6L9jlwwX5qSqw6ylERdIi6pwoyXw34/ltJC
u+79077dl7K+LjMtFbjyc/l7HicK2PeZPt3nFciELK8BK0vfpEzom9w6FhT0RNsjRprs1uH4AVw3
qrkYOTuBXpr30xvJiDV0euBqltGl2zXda2WBfbQEbZo8RfyeAZ3VCMxHPI8+gPVqLw4O7lBHFgtJ
erzM/127yk6iMDgEkQb7hIWhg9pMSJoKJs1fZ7XhvpGCwSpCH0W0N9KoDi8vd16OoGmyw0ju+raC
tA2EIkNUVm7mV6seEkpL5uzHCqEEStt9/2ZMFc01ou6nUrsYnZQXbVkz1Neh0UWeGq5KW6qv9Ovr
hp/5ZbKam1bsuHt8ikNcYDjOzNedAoDl44rCxEL0mouA0lFrSso0xOEnETxmzPki9+xuieuAMpr9
E367iI/FcCF4IXyPeUbi3O9IOPfEa6Zs4X4gDSTeINBfNOwh4dwe35x8nR9pw/NDZib1udsp20oC
7V2pIzb6dQALJfqth3UTocxZvnY6iCN14EzwBVEqU9fDnXfiZtd1vI3nJj93liFrfIuXLwWeOx4n
xZjQGSpGI6lxBWt2mYcMiXWkHI40vTq6fKIU2GYJorDSVvFIgPG3bro74TfTaGxjw+LXQhcE85IN
u2ZgtPeG9Ry90GXdcvm1WH9QgVcNF+y4r2J+3HHENTHt3TLgGn7X6fLO/7lpsTelL99tH6rfDDiI
RzaaiFdE+sIj4DRtzyWGMtYf6+p9/nEJaf2ALMkp6iTKxAFTCl/K8zxY9vYv5g7OmP/6ddk1r1v1
OrFwhPOvBbfPx9W0JWEUEx9IENkmI6xULHFVTieripkUV1CqBNHRbwp5szaUh9PsDW9lBJRsLpLx
t29k2fNGeEyYMkq4PbvRFtSOXrxV94bfLFJlILa5dlsZ5EoqUI2D1gOwM4xRZRCn+LCVILXl6x7x
mF05cefB8H9zaeYgzoyFYXdAlLoWG5wFdg1pOtcAdR0QZfGmTVju/MeKl8bPtOvwO9sg9EWTMyW7
SnMV/hcsgRai4y4BtNBf2Nocvm1k7SMam4MYXgKmyIlSAJZUzRZy85NmrbQ3k2A1bFllVSnA37uP
srzGC80hXzQN5AydJCuEN+TRiRTaSuf7GfOoJKu0k1pCedLNlROE0cC9f4amoNXmrMe5HwPvFrIO
fSlwjfcfc919oGDPVtsxKj1UMyivtWqYbyDqiWuqJB7sE8Z59CxHHnsh1EsNno2R43sL3i0TX75E
bgNNxkR3OAVxGb8/Dc5lepHwXa+93BNF0tKQy38V9qWXuUnpfzrDLn4YAIoQIoGEzCU25mS6Zl4X
c1Efv2ldOFBBbEp2abvYha7rwZJFXRJdIVcCka9MfA4YTqvLqOYAJUFYh80ZlCy8y78ClkcPaSx6
11QW7JDoUyWyjbMLdfIjZtyMPUyxaJTkM2WLXc+LcbeyZYhznToeukGw8MD9bOHh9ZueeU2hzvMR
wN0U0bYc+COKNOJIFIDAsVEyeMgmcRl25ey81LEeT49pS5b+LmN/VqaKchtkbxBuZzE8ntByz7lo
SMLSJudbdNB0TE/aDAOiEQZv3MV1zGCo5Ex06APfOZMog5oOwOkaQMlf3gT/W5iCuY/kST99Ginr
jCTHmFw8NJYq34wokqurl2HX8Jf2wosheA25O/q4wsSksiRtJJFKOFR/EakjU+sWDI13/st5zM/4
JYdiKxE4jl2w0LJPstO2JU/dd+9ZqMv92ytwD5WDtKBpcneJj3gyrovwKVO/vXz+fQ4sXPvzw3Iv
RQg3jGOxkM4uZPmH8Qxu6xVwrV7pXg/VH0qMXbz3AzaBVEJQJjiYIwXtbH46AnNCwiSEIr3j6Mfi
UDA/muzJMjWtqj0pMVM3cNEBq1+ispCnv+dMRWrHEqHeSY4NkQWLnOcij1QFEuocE00YTsiLqzoL
epvs2XP6tsHlu/Typj8XjljdoQSPenqWtH1WQt0DJDsJXhmt0KhaH63RAfkFLSFiiQ4i9codxfUS
6PFjAOGml4olK23UXprbXkNnHvgTMMsBSzApHLmdOygN/tVLX5Qgt3YIEzoOuZPro5ZjgnjCINnV
VnF5DeaMICSru42kt+tkouDdtIQ1yjVmC2uJBcIu09//JzU6d3lkSDaDQzYxEPakvj/0TuP9kL50
t4JPXHJSm7j7a2NiMypykzV/aPZGQmLwOOWI5l/rhxoy4Mx1ngXutac6tUfllNNukThAsZeul9vn
C1HuQ6mHo2IlGIhcEzWM/QY2dUkV2cqV26jx9NihVW1p7dKNjimVY1i141hd2UX1xdt2H49URtGg
xb7dsRtpCNKl6Ja8IS90VGngjdOyTqnHTLE044Nw2FJ9PUuHWHjm6sjI2QgA3hSYgAisOVaBBni+
XFVav6EB7CMGHNn3V6GnTt52SSyliOjzz4FK9tiy85N4zjvqr8OtW1nZVcYGEUZWxJp3SQnC4xrR
DqMD3eLWYjU0NZMXqD6qsTN0T052vd6WwOx000RqYgVX6TEd0uvKB+O8awiNJlXD6Gc8erbH3r4f
wBZkCgEU45C0TUG4RP4baYCG/5kVwmChDq4JGRQ3pn7LfQiM/O5gC7YOSzMAZm8mg7HHU4JmusIZ
vkPrQwGSiwaBJlIzkHGXUyZ/Hq0MES1JjqLjBUZ8mY3WhfzgMqsQwbVeOmoMWH3cwa+gf0AKkHvR
fojee4PzkaB7HHxkGkAgsZpX3Obtx+rMvTQX5lSx712r0xtfOdMIMGYSQ3FIrgj0u7WMT+tXE3yb
dIsiWSSexCJCZkKKsFHdKumjBLNnCiVoU9w1YJyiRhc1BBpE8WpmahJBB0Frt0CsJxJeqsS6PO9a
2YtDWWr0iykWQhbEywnArzI0tTv1v7V/te8DdleOowQY56j5leEuWHdqU0pauMpcWHibshqS1lAc
y5KLkXxUqRK9Ec/wx1EWpyHJ0QDqGQLe1v/dF+jOh+d35UspBrxhsdql2KAhsXIngV6nwMcRPIpX
/s/bJU/RvR+6XY3brnmdcnnd9LEEOzJcoGDv92L3e6roNWrg+UHM+1BUcN6zFBiNTLiZnfT32BHV
twIxQ110ioB3Qp4kK9NxGKtpRIy1u17Z9ZvM3StOqNr6OC+NCYWVcYgPjUjYlvhgzZzJJxsdDVdP
urZOEH3xAKh5+zTyyNiskGXroM3KcKd8KR/Bvegrvtv40v7sRolMFKptAdc1pig9dQnccHNQAlfd
uZRo+3Ufn5l+5tVB3Cn5P00IXffuZNNZZWPhPR9ZUjA2l7joMLCxYmvyQolocqryeq1L3bfTPIRU
6L+LfKnnFzAhRmXhIHX3+TjMiQ94sbHvlqe5SdVF4rAzq5GxLfTo788/5IWhIryYY2qqAOajQrG5
98QGUeHu5m60hOdBsbn43Wqp4XAZWGszGyRBRWMU/vPIGeSwU2Ceq2bclbLBNbkUGyZsssgNZvut
LY16cjvJJp3xl3ZQZheVxRLkorB5ZNY2WOZYdkpW45sHjv/vSVlAcE1rN33INu380SRNWCFBIyfi
YC645TLFE8iBPcmr5FMiYvYliHiru921uX0aFHbnfFwunRbFsbzZ7q9SJiAe9/4FFkOVN80g5g3S
IHqSE7KJR2cnX3PaGMAg2maJAtVQOiqy524mQeCYvELhZSMpRIezqLmt9JU8zZCSF2wvhQvzU0dQ
DP4VC1I9XcbagKeEcGx95k93Le8TyD29OQYX0bSY98dEVTV1qrNd0s/Ao0WX2Rh6xX15v79PuZJI
WJ1Pxblit4WaVotpiu6rTbdpDw2DgTWmPH+FmxNC3XrR5FTKV9CCq/O7MQe5shaxO6E2fwSkf4wG
AXsIHRPdTB+14b3nTQfpCbo/jRtWcgK2jwMqGnV6Z/5PK/gB7B7cVd7CkSfHwUj+VM85Y4i3+jPp
wqexaTv0xjO+fGl/xdqR/m83HMRMhNB1kUIla19nXOjRfd6t32o3iJsnQQgwBTkkGVOpDpHeY9Fl
mEKeaGlTorGdcezxHL6nocw7eFkrfJn9aeS+Rq1i3CBlbjp7WBXCx3EoOCtxNgd4YAM4wq6iammt
NMJzvbbKXIECkdr1mIpvrzwT+MBQKV1mZbxl7xHHV9Ltpk6OjD+TD/9Ad3Xc0j0qseNlJhfgSTYJ
GH3J9fLogIP8ZlSvzGNpuMrdofZgFKyYT9NgSfBpMmMLUhiuOETfxAxATEPAOvN3KKOkKgRxYhaq
1ht9hdrsnPxhyHgqWsteKuT9oTes8e4liNVsWgTk9yBBpFIsemxkvzyWCR6CQnxA1Y60AF/FtAG7
nfiMv34Gh6d2rJYj1ynDLIdmWZR6652CztWF7vi85HbFOOZ4OKJyejsUaLOftJJsS7VL5GLfxiQX
jGgW1Zh7G34y0Wr5Cf1h8aJVFe2o9CyuyeJjyBCgo2DloaXmGRMWMnux72yTPz66vNHDK75xZoiH
IywcVcF2PRec0qqT+SYIX++zJAv5wboPKJZf5BY1hwrl/vvDejfOeYmGcRAG3Pl8Q3HZuCpV9DLA
rK7XL/4qHVToIM7obShLvJIQscEjBUfPq62yoBIHLEyuHjcgJIj7txFfPOfLKZWMoqC8lDyeXK88
SiOglgaRueHt2X84t4FdQk9li4uSW+HanDZ68ij3r2XS1nMGMdvkeaObiYhGb4izZWpWaOuL5MQb
wLGF5L7ZM41E9kmJnsV9C062BeK0CFx3zhqjU3ycAyTfcsKT3rJQke1RrVoe7PeDGEoS1hrjo5pn
p0H6T8IHBvg5hHEx5wwrhjzknAbM8zBWVtU8MMGkEI4aLHJ7kwt2fEiagTWPMfwdAFgsBUjOrPlm
VynLjPPZT8696IvioxIbtyCNbefzYtuix4NInWZs/ZpthSCpdmnjyy4npYOr9DnC8mZUYA26NmBZ
a0pAZcPr4OPZ3yV/5fU8yxDwWqe1F8KPRGHzLLVGieRl1WJV5lGAztCMTFXqqrR+2r0pwDK6+qn4
ptxKbBss5thqBu8lDtOrBCBJdLMZGHOqyCtJkj4IDsX3RKLR+wdQ9cIjrgPzbjkM5coWVOhUz2hV
iFhVQMHwo3AYuX8ltg/sF+V9KCv/zLEbN8/rS3b/g825xKoxQxi00VvQ3ng7Oztwu7oU1jLYJ+6+
qtsO6OAoAkl5DGC//S2Y8Jzxoip/XVDD9A8sbfcKsR4Ghxpqlz8x2z3iMsRR6S5DBOty6rHH9a0r
yAQXU+htwIKIpBVOXLqq4o1mJRwoYNa6pLTWtpBszl8a7r9ccKKlg2UqVoXNfQgl2vEnTQW25YJV
14kPzuKCeELWaZ2ffjn9rC6/HzOQs0EAPnCwACi8I9IxLCgmDJWvuEmMioL5bXW0PqhS3IvurvvA
ZQKzcRgq5sIAjFpAuhErnT0Ka2gEIkyTcMgDnV5j8Ecl8JDp31veuXXsPYnJr1TeXs5yQ5jUAzcf
1BvHEV83sQWqwYEheADeOLVJOYTgVSwvwn2bRQHLpxB1wuNtY+D7C7e/6Qj32/yMoQ4xPrpFLU53
y0sfXNDCIAnYS5RYcyLYXvgdFATCZHbqBCU13wnj/aJgJGxLd6Wa8aeJcwdf1wkfFZQPmNulMPDF
dQaiEGTSQsNXrHb59INw62C5dDAII6kZ/13cEKuuWOKq0XtoRIpCDwtnUC5hsnszlOcPupsJIYhk
CG/9KEwjb0wVwvMawrRtAgQshe/LXwiXm61EjPTfy7PYoy9v2+NcWbGz+D2898B6hZVrjR+iUZuA
07Nfa2BFz0i02rcsY8VhXipySOTbEqytaC1vYtj5R8mypM/WOT7EDJ/6rBpMHvjGjTkw8L911Ln7
iu3F9HjQ9rrm8lqq7WhcSqCKssVONmmQFfiJlVS/2RjtNUSJySmazUsaeHetSKGkIhyclvR8uKYa
vNPNbwhKg65XnL/61o01jyNW4uYJj8aK/40FRYsxxxqN5pQ7wZ0lXmHmdMwrK7oaUCrtAmNtApr+
g+1OgGylGy41xw2cHs/LGE6BlVQOm0ZUYUAzEMAngEB2lYIFr9Nz8Fl/LQK/3dimF75TnabkFEOS
9XJRFqPsVr/zCMYv6Io6RSyi9iZRgLDGCb9cgPtsVgtD3iwFGaoPcGbOZoryNP2xH2xCkaUlbWxx
PVVybRbG11sdXGwjGFE0Xb/BkxitqvqvoMDaAGdWLXdCvLtB7jnTH3b5Wk4VIP6Ao/Mgc9pHSTvj
x2ibVeIGSX1F7X9w4keaN8tacbzmd6ZgOvhpDos7O8SzzWmQ0hWNzw50+85XYpxE6ZmdRe5mGKgL
GaiIb5xsXxjy5IRU0dE75U4USvGU1cNdhNLSvH1qdxOkuY72ihce63+0HoN7pEKH2xjzc9sEGqNH
7NUe2njKAYT9tNKdozwiOQBU1XfcH9bVOzGAxPQuSAUFo2wBKBu5Q9sTxI0tRF7AAoi7Z5Jjz/73
GIu2YYPW21xJL/9chVJTLZOF3auWKeT4hcsoKmEV3+n3/SsKqpaucuE2EKLCybX0aUylrD3wtj9f
9ebVc9VUQlwCiu9MzMA7JCpcA5mjScWK7ZJvMPMvkggi36vBclR4oIgqnFy3d/oIIRPKXJjILNMS
V8CbiI8zJ62Ikf79jjtDKDmheqpk4xD+3W0KSTSmGgUB5wVnwmTQs7ipGL1YiCG7zE/+qGHMIZ2f
GB34g94Fa5HEv6cPNnFKw4Cagc9wCxKPcaoIUl8CJ5f5DNTR8WYCz5IROZHLBcbUsV4vOsNYml+b
8RKT7BaoD3pM7qA24OyK+c68nnfRo+mOkx2KGYE6Ni+JtDPIxOPpzqcXfW3fWsYLSdBFuEe91OeC
ICWy/dnc8I6uYijf8etd9VLMMArnz/LD7/btGq7/58gfz7TPd3eeo4V9bzeKkEwUrWjca0ozqI2Q
T4GC1iokMHR1mFI6TIWdu8PwyWLvLa/hlXrJZNDyl31eemtnWzYjoqDJ1ogm1VEJ7zUgOuPLt2GX
qQa9tQkuCZ9CNpbckvs4ZheIPi32e0pqifZ+Hwk4b4lHjX4eBcoL0E0d7YkF/GhizyOLfHUsMu93
S60E7oqCYW+zE1epJrhHf57/LKAI/WitUDE5iXVvSbmTY59mc7Q4YZYE8UiEBCI4ojywcsa0jkJ5
hKPjbr28ZqVzooWC6s328MUWn+A9lO8KKygSYMUhpQPEV/NAsuknnODDeOoue9+RQRY8sZ+GQz81
49gGZLbrEabahOnF2mpv8qoPp1omxyjwgHeGb/c3X0HKYb8+4IIWyV8I0EhT8kbiqHVrUxCeIoBc
fBhnp98IkSXXMQQ/MPcy2kS6ezCO2A1/cLAmgfD8eBlZab4g0sOgRxd/JnSfngQHa5i9V7vB7i8Z
p+SY/wDQ9a0XKynkJmHtStJAr3uI3PZw9kJU6mWHRYbR4TJT0hTnU063CPLidcgUyl/WwXhCCfJN
Y7GKjhzheKZL2CEpKMfbvuHSrcEenCY+LLlBFtoAcm8WFHSZ3SKb7Je4YTlmApcchyhEiZPNWWSn
guiACG3AXolGyfLmvhRmx/HYBsXTm9lnoLIMRY4qoSHKJO65oaTfjZLGC3VpaByTxMpz41V7I9QY
8uqFL40ayE3syiv+JbcqQsvr1raqjf+N5bPzgATgMivSdagv/jripBrfdQSZKpsJBs/HPAA5d4y3
XNMCvqZzTPw8lKKKNqa7U0P1OMgSh4GWdqXx3g1t/uBHHo3ELf+IpvJlMU4/gXUoUeUkUnNFCOcd
tMAeNFdLbbHa6a9A7GE4LBdjJX1k+/FcQmGuDmnpx5jIsioUknrDgaYiWN01r6hPUpYk+VRNfBNY
Zd8qFs/L+9DtQPjoxXzwj8zAqArwpmhIW7uXuMlk8HmqGcJrWbL/Fz7dsiFp0a+QNR6IfTWAteVa
qTNz3/JHQ0NQ0Xo9xIQE0aYPOUESZqNpaceZfztnWVC5olen3Pxs2Zw1f3e3V7gAiPUGJMkc9U23
8xuf+rTCl+FOWNi7UmNJD+K6n4Dp3KWS4DbYtOJSsEfcNTih5zjJFD2E2Cx3gM+0gSzQEpa1Aasl
NWtfI7xO53CvlcM5YHIwP8H0ZtV5JoK5zmIeFbPcftzrgbfewbepxgY6zk6kWKMnMr4a/BAn03lL
obFBm4pVBuLpoMxiAZqkhFU4AN42hPmr9C1xSGERDgjNtAXKGrVKW5VhQb5t6+hOIkTwpqKr7MUe
ltx2NTPUTyl7vKyd2UQYGiThbHLi3gYLkCsf/br2ZXuFS+3Y1c3mKz4fsMEjfvSFiddHs97dEyRt
R1SvmBHIWac5hocBOcH0TYmo1DM4UYJ7aWegNOft6h2RwZqQETPy5O0T2wdFBOo2kmQA6LvTpxIq
HgZkZLME0L/PPiBjIi1c9ix29BC9wG6FztnaGBG32xLybRHd2fSHWO5plfwKbYFd8OyYoR7L7b+s
TeimRq02GNTk3etAEmpNwH6wMH18cPMMA4jEJN8Dx+LqjpvwwF9h1mVGxkljEev0a4NYPW1wTOt/
OYn+SgCKQ8uf4VyxGYt2X5LX8M4eXmFjH7uwv3CaFdPA2jehfy2eK3EtUT2blnOXCzQJrjHeusEO
8IK5GYuWAfmnWdap9GIAOkY0yB00fpX6nkmp41kQf5VQDukaHgK8Bnq61oFayP0DPcxIf33/2MjJ
kJ28rlLwIdsLgZOGhChqdFpU0Sk7erJsPRYoMsjIFtF5BmqnjCxEOLyLTMSJiA4CGvrQyG3xegWK
SJU2m05afOstOxLvSZJjaI/AlsU2WE72NsSUkbjov+wGz18unmBeLWPLimWxhUsuxPKAmB47y2Xj
w8RNC/t9eVedY4VCKSG9QTqf+HfA7MrQMVuarr3eqCbEe93rdhBdq0XgYgw2p8nsaGgs2YGaUSkt
vcB9gN0/E1hpO9nxuiRKuCfcUlo5p1BKuxVE7+dyX6db1oS/JZG/sOBlALw9buTRORi97JeW+lMR
cOtFBlqhl5ChWe/gR4obzh/Nlkg33Yq3GfbNO/iVL4uQiarBgBqzb0l2q8u9docaVqIh016Lx5ho
KSwOBLlIb39RmvLRaCqq5gqbfk3MWtQJ5dPMa1Svc6A9o73TqwxQa2KoHFk4/AOH30ze5u0mk4c5
G1S53VekugOuM1gQ7hHDzhc7HlY6CAie7vS6xK5VBOMmhPJhXcJsP36BrGkJzqXbFLzY8tkEMOBz
WWqHQDxmyGshdH/RcYlVrHBwUkmHTLqqLZrNVNcLm/T9B3ifiVGLwBoO9OpDvJjccyPNmMzYUXp4
htKJW5xM/KlOTyy8v34+Wt6wV9Y2uApPtswKnE51qm01r/etpk3Jh8QdIG/g1bUnSMqRZ8iD5ptg
R/8ua/pZrHIuFTA0KuYC0jsJNyS15AiaqiUs2NBUsXPHlJuP+XLdDFJ2z6A04AFdNn9f1DLeGn7X
reTHmGv7w/XjpZO9fy2QCCXCk/i+rzDRWa7ONqpkI2HLrNEA2vt0SkSLsmNxE7AFxLhclPYjvWyt
wIeiRAZaoS/BZPluqTUqT35TTOMOUXwjvXp+xBKWZOs4arM5ty5cvXsmw09VEbC3mlCMjbHyNd2C
cOvBePkElJ6UVLkvppl1rXVMJfr2ejoUxw9/qJkevxdsnmCCsbn7sqnHTCQ3o/t877chP+1rGp0m
X2O8avJa9Cag3TVRkBgF+M7VLrjVdVflavu0aBjzwE73QhBPQ67NO9VKVBnICC25+un00uh9IS+q
bNd1BV35WjiWh3mcaAJ+iPWaTYdfLZkLmMFTJuCyTh2vJFGalAvReNBffiUgOvKW5cx5LB3IGiHT
bXLFLsi14XNf7B5Rk0ZLyOO+ADUY85Sna7k3dHfEVzk5Pz3SUbhxm3dd/mgh3RY7lGhAZvbzSQjW
JrIDgR/jFKoGZf/k38YdYAVIpY7lwiwXoqe0UKkjPbGnpMHlv4+hsA3MT3MeYvjWUUYrXpd3yNxE
cLPu15XVNeVnrEUoji+NBdWhEuiAA//m2Jdbrd5/KlBys7gR0nxlWjdhUzF5rxRuETQWnLgY3j3J
Q4S+dB3SLM8UpyWYkOG774BYRJ8V08+jCDZk33md2tGxRmAji+243Sek9zsS9d1zBPNhUKqCpNEV
f5BgN7agIBvu5XVOnvG6U40tPu5OAqsgHqFUD66h+mC8+dZUzoGmj4epPbBmgHbPIZVG1Ydn9zDg
6wiGZzPlJBzVTh5gsfv9un8s6Xm9RzNI+iRFUtQAQinSPyr0u0XaS/0E4Wx5ZB6/XK36Jj0Zky/i
fb4Fqz/2LSSB59nQ3YAWM1t5EyFN3PSSrluRqetgH6aBNo/XykHxSdeuIkPFKm0lo0WkN6As4UcW
fJkiAxwmgKnDO4h8c8BP88iPon7/zy/q3H3ciNyKi5RjRHVGPCNvvF0wt9jHHSa8lYTBJQodkzo/
NqbejVRngKj8TCd40cZrlK0zWEyRYrquuSXezxAecTNtALUZ5HRfgY+0sUcDnotqvzOf/mCxgTBc
eZUHNbym38Al+UZHB7LoItQfInef8zPzDyYVqB8M8Tj/TFQ+Qdy/Uwcbkf516G//rg0kB1i0Pmct
eFa+WZEQYOP1fIPhlmUSZ1MSpucrOE1oRntj0XMvbggjO+Opub+lzzramP14RqEOt+qV16QUqWIx
cfEnj/bX8UV+WKWqx37xhNQ0lZDzEk/NKgwh2GQghF6m31/qewc+cBBuARREFmOpM0/X87ksX729
EouXb157Lg+G2siWRzMVcT8QIBVl2spFs2OhSUwOoZXl+FakWPukRk9IGTIO3FcKdt2L803EIAln
4FX8roZXGCabE5jmwGn6lhj6T2D1cZ9zj/2Q/cg4jSGnmMlhOcaBhxpIRNFm2iH6s8gxclQjDj8U
27smE7rPUxTFaE0mD69Qm12sNT7nqJoq51U839RQp7gVAsYD/eZy5NStARhhcFl0ZZVWtWBIBOOp
ftBEsVBJrTGr+7tV1H4dtWhDL8r9kGczr+yAzGb8kpbKPZuAmu/T9KJ3Fla3SMJCmIvQoscNyva3
v//9EmLeLqVnY0yj8NOCB9dvMfMqsV2k12hhbRMH3NaRn1Ao511Mf9Jc7B4/tHntA7HX+xklCK2W
7GVZHIb17Ow1hLThKuEZDnQd1MU8bxJ/uhPEzr1eFCZeWGvA/+HQ1Wz7IKybBBg2hvS6IGN8bosK
w0HwWBSuBrFBG/T441UbX2Hb52Vgzz2g7a1KBdwyIb58GmeI54wNBJqqPKWp2apfrsJa3SrXq77R
56OldRfcKmjTVlb2UfnpqMFngwQxLhIqdsG/74QhIdY8i2JEU2as6FnCk9I0p9pl/vy5JJVWGqkE
65h9baM78KM14IKNkJhBuP+tRoOgmbsh5OO2eFH1CQNeU5x8KlbvFTbjsNLSsXZfouMsJY2AQ2pw
ABIjKkM6CzEZS66b+rrRMQbSX0tCSVi+V25GDR8Zz234MCvLbaEJEQbb5jzWWnKb0gz453CtGG1z
Qc7KlexQ14+bT3Su5XbD2yN+j78JIR+aqNeKwW6ilU5/b60OVAqxgHa3YVw4QCOp+i+L6yh8GcxA
mBdPFvkdJTVOexYN5qhnl6LY3HYenGZ3vvaoteSfAhS0ojMU0YOlHV3OppAJrkVnMto0kiOUy9uE
LWNy8q1qQFy69ixmIjSz7uzL5R2R94wcX7eh9HFcqnxgRcEKBFXp4yoaaZ3m3rwSuOPwgBcr4TrA
E4r+dBC+/aJpfCzVBDdLwFIfpZ7zfKpt9yVa0Pg2hr79xM5DlyRPZnX+JtYhnamYSZcSACybB0Jl
gYRDuAby3UyGd459YT/5NcXx/3MtjwYibxjq78kqoxxf1CrRZ6i9Gh6144d152d7HTOHV/5BYQGL
swWcvn3I20eVw4ihdSlmwfrUuXaOteDxCA8nDcOfq0Vbmh3F4kZXNow3UxEu37Tn5T8/XOUIpzrN
/j96apRIrCkA8qEyC9VwJ4hd1SHLImXAtR8cQCS+i3CFPcpBgwdxgOjZSQCygEjpnUNgiYwNwV40
F8pxJLQcOxQKFkyRHH6KdZ9RcE79ALmvUqOSCiK77NIiGleiir2RSEh50917bNAJwqu0n64MCl5e
vioe0HFDqoJh7WGE6d4hfLowUtVIt9ozTxb1HDt5od957yWaQkQ5DjSulYeHGIYBc8gi77jMucDH
DZCbcrDX1jDJwP/BXqTaXM2ugW4G8kjq57oTlWInZrWGtzOkIOLxenuoN6rCdB+NLvknb1O8HelA
qFLTfqWzgbzcFut+4kIlomXwmZsXH91v/VYy2biDTDSDFWg0zyYSWya7TJnIzwrlvWKJW1uizJsq
gMVgtm7n1LiuerNqGRqbu8qztL0wfSdAyaI7wulkneOOva5/O0aDv7fmroWf0VSg9kb4Crd1rByr
kD3kJKuRjd5HnybAoGKIOgGmrHixzDjS8Kpltkq1dxwWWwyEz8YZpNE/61wIJAG36fK5mT+pMiGD
bf5+9AWg4AB6WuahGBLO1Fi9AOlDWOmzrEQyt/0mXmMRCQFHO1MRSDuPaJjmNNDr4egoC77yNoBP
I2UPKS2mwvcLJuzh+KoFVU2SQBigTQ6Sq5W6oZ0hhNYrz1ZsV8J45UjYWmIiasUdMc/zlXhz7VBQ
wmIc8SZN2NhqAH76JaBbfv6oJkJ9DzLElM8+NMILDgLHKLchwflUYKYUtZ8dUVM4CReXLcPg+H5C
QQOVRX5fO+ipYUANfaGSAOIeHkelidsS3ePI0Ybbwc1XfN+H8JuW4tV7rWP0Fxi1W8qWXArnaGvi
sDdFWhGVRiazU15JxGm+tyjlcsMyID7looOufz3ubhvo0PEFNgYIUxlDDTauxoe7GwMGxG9QcqAu
DjJANyFoNaflsW0ys+OfOR6lS+vCb4+8nqri7n1hAaP2vNnGj/uxs41eofjDpGOsCrQDlu+h5t5o
naBwUaU5GZ5zkB9WA7LLj+tFvirWBQLnCfT+rgvj4tH2Q2LUh/37feLBir5SBWgksWkVTyaJbLHv
I90nfzJTWGFNEOXQwvcjKtd3lrd0z0Lmlk3B8uvYV2KRAmt26zVwuDt4fbl/qZZfD96TeBi9WFm1
GarqqdLLmQQxiWACkJbx2EUlYTxT0uOiJ7uzHRilk4YkYFIHiVumzL0oeBPuyR0fdhKv964nSidH
scZlE1hD2u2UPaoBZY++oF6pjX5fjut94gRmcu+iushwqddfTKPFD3t9R6b/DIsbLZb9iNSL/OIm
TIGXsrkmaqnwrlNzP1xW/cLXzkbCpYJBFzG9zaZan0VQHY486GazkL/ro5/qMZ3ZjgPSlsPwRcaf
ZurRQImu4MaH+O3bzEs8MDKXMzF5aB9EoWhUwQgnL12fXDQf9M30avHbTHkZuaPxT/r0nlBhB6fz
gQA1VlvlXQAfGZvL2SKhYa7FX5qADnAB2iGVKMJefkXEYATJG1oiEXMebAAd6Bt7JWo/seJC6wLr
2jLrvEnpiKjARj0/Uqkg2lWyqxeW7UpNxaVUjRo1lik2ONyLnaHYwPWy5sCNEpQMvYTYFOPRBne5
jzmgODLY8EajBVQQdiRThAnSq9+FYBCnv/OGaBBTkAk3gHFLZvSXNMYh3naojnU/amppRYNgo0Xj
9r+SfUKyvegoFSDkqwUniQKCCND/OHCyg+xUwS9fOGA7vt0VoF+mXXhee+iWATEFIhafjemJslSf
E+fttyOFygzazZg/yPj76p711M5ZxrN3OSg3fA95nPRz4hPz8N1U77a21yfGhTzn/zpKgh/f6ikA
bQRG5G/zytLM279WnSDQrfP2jSPGZ93ykNbLcPAiBsTKNara+GXECfro5/TLXb9ITxgr4l16IzjD
W71tn9Y1NYmkdj/w8n+wwGtQ1VjnfUYgN1W+8L6KSP/9UDK6RaeX5jrfZukX+H60hJ9DtDYkDJSq
4ZZ0N0Y0sZwKwptekHCldx35IncoOK9DbdizXvuug+AtMqryWNNuz5hhHGU+wdN8J5m6QJncF4uy
JyrZ9XJkEhNST48Zq5NIfIIP6yODCMrOKQ10AGBSs9mlXa8eqe1hsRPvEmf20rAg/wfg26lXmV9s
K13lxgIZICyVaacL0DVTDvGYXkbVbb9ZsvXu3qUX9Zeq69VMV0FxXBmcPgHeTgwjxMVDtuyPuZBI
lem7IZnKFioV57oejrrfhWClcCWZaakBMve5C+833uCW+EAESbZvkHqjTLEtg9LQ5wW4F9bTDvPl
0vFEOYVOe+kIx3F74quVM/S6IdTG0NwzdbfDeEimS5zzJM3kM/Hvj6RrU2gTt4ZXX+ZN9zIHnhCm
BsHlRzM0OfOgjH9wHE1ycMoRT80b+dm1gfhH4ce6vjhsiD6xxFUIkjgs8hskBzcl98f0EuEFisZa
J7Bs1CNeUsh8uWisedgA17YfCiOVAXHUf/NM65Iv/UIln09SGTk7X+ymt5gdJdkVDS5dePCXjtmW
4D+AXpBASvW7Z1svhx6TW2ok+jvagWGu1jyuvtnkVDmVgjDC9EEbGix12WBGb8E9IxqXFxdMHcsT
5l7OM0IN5UXVhoeo8Jpx2QQOc0tPtrYFV/KGIiFMmyq+myldB4Mi9t79PlcCurt9fP3QcE5LBt5F
/Q/iHn0GKtBDexLXu4eHiB88KQZCVOjGO57VIW93gmCzNb3uHjYyvxxLijobTRW2GL++lUMs1fok
P1Ui5GtIvzpBvxL4nsIYrob53rs8lDaulcBPLCpboxWnqyaBbsTYJUk7a3eDjGCK2lt38y8VMe3W
iUdWkmu7mMcAyLo2pOVt8FE3fdSgVCmseySYgLBHEkb3lasxFkW31GY028Blow7HD3Vo8hjlDhtv
DBl+5gPahZbGz0u17nw5ieB9z0SX8zb4tVFSyr2JY9jeOvOnF6d67WdE3yVByVQJr4aG7mVvqahG
6yG5KWvdSV4jQD34WdNzjiKdRJN/JoIHfZVP9ZqjsuNpetYouRxa2QpzWMMR4yLB86J9tnOB83CK
HdlxjREQuHJ7YDciu7vwFciliC9fJXjWKSW4KEzCDLpg5PTq+8cLY2DeWFN2a94UzgLklKCX11AO
bKVrhKwxDYNFiRgSZIopDTwczJ1C6V2fJjFWXwWJ7Fjv+hDk2alhhm/ZNaPbVde55uO00XyDY7Hn
b6FB1khW6nOyO+meuxXpLA+DoY1VbW4K/wjo4hp3ncuuudJP71YkL2YdX05AIWZmd5mKK486ziya
OMwb3+yeQwCvQKynUatQtyFBj3u6iMmPgw6l7+nYL3nNAjt1+XdgV43osm5qgat3HPEF8bdPFJll
PlNydT4kEObpBHTBXi/SsZqWXiaF4bTHFKhtqbJmDARw99sZMsCVlKjmM8reXrIKH99K4UoI9fg4
H3BOC1swjqpqLqGmP6fBsULIS6JAoOrkPx+jmlYPcYl7vglyGXQkuZL1Ny+rpHo+WCLLx0ju/QCT
cCbX4B1eaMyZn8NcDcL7dqxjIuHY+xTI+tPWV/HY6aBiYiE2M28udPQqS4CiJPr1jPBx8HZwo8rn
alNBokzquYw2eS9biY6ndB2fOEV8XTos48TL6HeMYL7TcxsGe4ssWPA+07nw2ag24gfHjCzrJ4ib
NC+qSML+IP0WjQFdG14xfqBrnlTCutkQmPos6O/Vg9Yb8McRi4F5v56BqZ9mo3tLDyaCKjMTeA6p
//r0CcwNjsvqc6GP72gU4BXs8GIa2JAJclIgUAM4aM3zYJxu5j2RIoWevGuXRp28qcCPS7Xj+AV+
+layYqVEDw6JZwjjF7oBw52Rdl4ZqFAs0lxT/b+eRLk0792Zqm43+5ig/1hnqUCqDB4hgma7duWR
eMd4UwGkVDxHUGO5TW9pAxs0Cshifz5HZxeQpGfvyE9qsn5QqwCkCytL521Z4K2Jy/k+MYgfnd78
8MrBiox52q2rdgd+aBzWNiw4v4wD3iAP3hUPi1+onHlWhh/bHft75i0eN7cYbPwgSKACUDXp5etB
pnwMpcalETElCe5zBZ4VPYSX0rpWk2GzhT7QAtS478gWXqoxqMEY0XvrS3UbELOZzXPmDdMeNKsx
2Kv42RKBPNz2s5AsLPNmNU+nKoNtXc01TR9JmyJVs4BQjFWqitzxyOYVTMXr9Inv9s27TnlJ94J8
DpubtZjSICv84MB50DWygendozeRhU08i4IL+knFNjsnGQtFZDEIl6klHWpXPJ6VKx2WFVUP11rC
jgNnxBv8QFySlL0F6vm8Qkf1wkVfEblCgx/mkBNRg08nQVl9zQyJ4Yk3AN4zVyXX7Hq3HmIaXnV5
DEjbp844clqCWbs1zwnf2CaOIMDcMKwsfUp2ZxFQBCT/1tyE9kbtlhpmhdVwOPrzXqLtYvzNweQn
7pU5zXWOC+6z1HW/QPx8Vhv5njgh2zpSe+FXtwsD7QVPu4Tnk9gtJHsQnjwWq5y4muRiSyPuapcG
MG8bFJ8t/r+l+b+eDyDOYf3niXYBYoiW+sqWyVNbAXOkQi8jsQqJZWynm9ZHIoNGq8BJYq7C6FrF
m6lIC4C//YFOx4n/ZeDBgyYvjwy9PZrXkgkG4vluEyEPCfVnq+jtPkQyxJ+lrUSGUs2x+r1Qspk/
ybmgTsq6rODIhxhIiTd1un2K95CUxBmqe2vUfsJkw3CBrT0yeju0M3a40zxzETKkgx+naR23oO6Z
CDSekzVKDB9Ym+UZQQMeq0kn+a9kaQQsuH97csVuma2REV1jKP8VXjIb/ULWynqWTH57GEse9tij
noL0nVegJYzKdszyVaH5SSPatiM7PY04/nU11+NZF5j4GrGJKRIfYrdOj8oQHYxFFEHoU/bKZLcz
xzawLvJKRqMOdRdr1SjySV3xeaJUBfpUgLzfARngXmaKYt2hxJ9p3nRv3cfVCUge5fnH9ZwNfqSB
tt6R/rKjeymmNeynCBRz+Q2PEdGTPOSJD3wyyOuesr1hgA0AEKOKKP9/d9s6jt0lvrOlMyVh6QTa
BhrqWCFXWGQZqHS3yuUro81VBMyphAiGfo7KWRdh94WzjjH7ea/ldxM1ujid2WG+E/Qe1BQzgI8U
SykeNr6q88lbIr/mpy3WG5RXWUxbCOAz18W5Zzqc+kl+8nxvJhsCWnw/9EpEEvp68L8Z5j5txZ7r
ZeLr1y/MlD+yACMR7Nb9fX9jdV1jwBwXMSNAJLbqdovap4AB1nsiUmLXNkAWCPUr76gex4jC5b14
g/kVmscAbHvME/Fpa10zuo08hQx3Bc2n9IleYqskkl1jQdhstbivm1NTTHNqOdV8OqJg8xZR2dCb
z2iKzrDt0s4rt5yaio6tJzb5ifxG48y5v2n5UT6Fx7bYe/Jifq+GZuF25u0Obkc8/1IEpoDJsBqi
IgCM3APj+meaq/HdvYtz7kh/fz/L2oPImpx4B+jqtTFupkWZIIJ2rEU1R6yK1Pu7sJVHWq+WtCXH
FcgzAUvVS3E3Q1dGdwTim/9xNgmqT+mLVSfttUMb0kFYiUx3+GHCCpo8JT9PlsBwjc85SKbujkLI
68ChlHWaWEwSvfJ74QbNGv3tppTblPe6ZrSM6RtGyfHmXf6GKLX9D73S04H2YcHX8+2MR3XYwCuV
xLftXgbpxTQov7AhgsuOCRjN+cBKy3VDDfHR8robG6ocRWk5c8/B/7SkUWHjdof1koGmSq4PzsIR
+vaoe82NqUPIrCwmGYULK7d19Ehm79XtasX3ycG9s1TCNlIA4EutLt8dKFsfvKPF6+77QUWxSMjk
/a03mQ4MRZLqdeQFUaVoHpm2Hgu4JiNC41Ry+0mN3waIZ4QOpM8QFyZ3dW6IjK2fH5DoFvchS0rQ
ov4KtvKlVvx+50VBTqAzU4TaOeixLFU6Jy+YCN0uGcLhR9CAcrnQ3b1/ywWuiQEHyPnH/npH5quz
qBMKY4bfQFoh+y+XTWBoFNtpaUndZwdRPQILNnsGw4/vFMLjceL6HDclZjkqLomCnzsraiUmT9a4
5+q4M34Ljskc55AHaO4EA+rUtXKdEWtj8qG+6knRelhEOGsS4jgb4fG5MaZtbaYLuCGmhit7dH4K
0LybkXrU1dPoF7O/r422KqmiTuoU+BJpXEZHcFJ9EgQQS1z34PS72TWLFDd46GvRMBqffzYNIXa4
4sczWr7kPj4z377qzw6DmeR5sJMm5Cp6x6bG8H22BgU2yfESUH/wCaYdAo34Hbc+hG6DoS2reJ6D
YPaOJQs+0dN/YKNd+VU/903Ou1W9KTcGpDayGk2bVzbj60i41Bvhj62cOu0nAl9kLuGUJP5karQL
JEEzoer3DViY25qV3Q+MsrAyi5GRTVxIbLivMFNtAdxLsWrhtvcO0VNOUi9UZxBX3yI7R7RSm+B0
/KXE1geuyUYy8jEYV+0KgfJhOG6h7TY0T9fqTKvOxAWabTb3tL3o3RTbaBLm1Se8iByBaUpsIVpP
zm/JKnZXSionES9q1vDklJXA+/OYognCbGk8Zb0IY0v4tc2Ccm7XGiKTOzOOGkdtwQfDLnHrpwVm
245G+7wn3qUiuzwcaee8Pc6njsUsdE9TxbkUoEAphVv5mt08Im1aDeBlAJEQhzj7iCaEAV8A6wNi
1t+onm5xUkdpEC1MdAct9lohKX8mk4tUnL0TJuqfSWsZ0nVjt1daZGv6iOt8Khzwh+x2z8n6Qnuu
Tp/F/ZwFX2sWHKj03CxqAVJJHwPXwGWCkdjyVaXRmlGlIWCuxVUkCLd0JJbD7usve1B6hi/Hq9ih
PNpUY+pqx7JKl7YT1fnhb9IPz5fBt8JwHAGeqKuEk3BxMVXrn6DLRYd5CuRRitG5Y88yegtsp/48
esegl+Nfl3hd18RTQIvxZNenDnIZOPXFJRcSSCkB1zbERkEz/tBhGip9h05UQX+06mJlLBXwUHDK
X4J12VX+zF7qCxEfO2BxtWCxGLkkDmWWFfp69Ln39cO82gEbHXKRZ1t9cw/gcGX81U2ciXA5nU+p
E7kEkXuC8/JYhnjuX/yj4pwMlNlZPAxXwmx6psRNlFpP7s2Fzx8kAP/PzYK6WQc7fyG1i7uuORY4
opOxjDWk6lWcoAQlVKwdaK0RYdr/efBKwk/pZJJrPWlm7kkEBaOyi/xFMyQfkZJslqTjqvx4Atsh
TaleDg71R65OfCQBCra85kducS9jI/mcfPj+4kBm6+AkSTTL6M5lJaTp8J742N9gQWxHSL0Hzi+B
fU9EaESbNXQTEaCil92UJoAyl1mXRGxVT1I8palGpRYuYYOusMogBu2gPqa+wMkJdRDwHI5mLgHf
Cw+RZuUjxiMmSOJfCKqh7YX6oyiXx9HLK63czccRwplFfVM91UjEE5EwzzHCyGureXSNznwlXsWS
AosU0nwpeVeS6pNczkuUqfNAh6b5pwWVALzhkVH1hZm5diOy471amGV57NWJqpNfXzuI6nOqjBde
QDhc3CNzjvD14tEAUsKGXbzGC5Ps/quNsY1ngWty4jz1DfNwbO4b5ltEXlIdGtxQBQY9GRoRy/0S
CcT4aKeVfhqcjoR3ciR4oANRCsano25bJWi55Pwq0thnSXkoH/cxREwF5Mp4nhXy4ZcSNASOeeUa
Tp822chS1j5+dNN4b/Zrb7y5DAdo/vJ/mtivnIKIytntCoqhf0M1SzBO9KnRtcqDTxhT2IJcfi4x
jgM3PHIvKGtSlaQH8aSGBnL9AYdzCHQnpOvDhZgi817lbTLlxkfiyVQvje02+fMyz8ZSt+4mWsgL
NpAQ6AWmIySM47qL4EMW+lW8gImDaFJtQ37I3apHegpvKLTJfN/cBKz8PA+tO9i/Nx1rvjFgnJWs
1HcRl5RFGf7uIeZj6IwwfkvQwiAWxnOaP9Ltq11ZRLPg1NyBu7u8fIEYI0Icb+ucUbcb7SLr1igP
jwdfFvc0B96ciP+ORs/W4Y96kfc357hHfcSQRJHIvSz7ZdcUFf0+JFQ/vSiZlLupbOfSwS7cAWnG
1EwxY5PQ0hkZqUX00jsXRefZ0nHiTnVHmYgVH8A3upN34owd8iCNUUQE27i4p+fIygrLTibclOEF
l4nS2KMh0iDBidR3qxutnBN5T05uIAHKYkugtvlre8RDt/CkkCn+SXyfKQg1LZBj6K6ub8hZs9jM
eObJS8/IJyvVRSP3Xosgfa/jCiqk6PfkTjpQjI2hBvchLmk023lWGQ7Nqw8y57OyRcEHsSgJ6RyL
KkRx+7GprSYWOHDCwcYn8PwtYULseiv+kJT8a80V9soUitpc903mQtKCCfQK8xj5n5qm18HMU1hi
2hewmYrcOK/wgO8wpft3Z2cuhtC558dzwdJmp4oUR4fW5B1bOQVffBNg4csWyztcRAJypQFBDd8y
2plmDk9ePaLgYIY+Q4bdGt8WrdXiNklzbmT4L1SrHn/KlMMOITUAKO5zFKP5W/x6WFNiVDnpRibo
X9u1RVr0v1pCmHxHRKyMk7GvDrcsRc3EoM52Dj6qy6RUW7gs5Iyauoc2bYTcgC95j3mc2mFY7MpF
Mbsfv3fgS+ccTFPTt/pso6uejsqBtLNxDtyfdat+9o1jerGcMW9/aLjzydxdc8+0mQDW9n1lMuzq
7gcy9N7T3fFcu+U0r9OpsVcEVl0dDjz9Rm3BrdXggucpSJZRDjnWhBxzGDGdtxZ+nvZFYXMwfuOI
H8DRmM6FnYGy5SDD3U8gRSY2z/rZ67xh2Jh7Jtc6i7qF9kyXTcRls+mQdwI76lnAO5gkcJ0bSL72
UMfrck/ALX6HrZrV01RtV29NBQAYPqGiAkk1LmhqOngRw/fIFL4R1gAFgf3GCfDGQh5VSX+UvxLp
4pC/RA1hlbheskOQWn8P9stfBahYHwPANkvbVla994vXtqhmgGoNT19kLK83DDG4Q01p9bdr9Puy
BI3CyYo0kBzWolnr8ancxt0prdNEmpMu+hIRVHjP3byA74POIHgn6qb1aLu/3D61IaGqL/0veKwR
bjuGraGJ1mxznCkrJSBi98crGTXEbHQJ0b/TorFQREYsUaINvwMxrIXFUR2qvOBV8gTeN8MFhHiG
H+CHis43wxB+39xuhQdm9+XA8YH2PVD7qhk1ZzQsFi2DD9pXZC6QNmCDZV51lbMZe0V1rk0+B6Mv
7kCkgkWVBM9mpb0CcHjKxczFJKXORepYrc6FN2lcpjAZyKE6fkhD8gE8qd1hLRLdc5xhcvwQdWUq
kyDCbDrIqNflLKXyAf7V4pLWT46j/HKcjecNq4erXD0aU/6jizt3xrYYVpkvOT+heVLzcxwxkNpV
iq6VX0J+FoMQ9fsDKMwEpIhq1hxwOY0++c0eYU+sA1fkUc4yE2xvSpg44jF24DKRMCmKWhHOT7sd
JPSmNtoxkwppk8T3ZqlUuZPt3IapHnR3CN1dXTK8mvMB61SUu1EksPEKIpSJXwspDsYIM5z31add
j07rFe61/13vP6ARNiOaZz1lVBcXKcil9OiOGcZqLQQWBgHpbPI0aIK+76E0TLgXXRqXoInJ6vSR
5Co6vmto5qdGSbM8UFzBixSpFHds8JE4LkCQ+P4QkOaRPik8GmgOafrGBpdxLYGH4Q4DcFHASiuQ
KzRLZPfwHC3MOpU0cZ06flmKzeIbxu8OuPw9BZwi2CM54XdkzFx/KJZfi+Zu8/ifkwqJXh9X4vpa
Xqf4wDoCfSS6JPdJMF+KezyN2s3XRdzcZFiyV2OKJPKa/7heVBqKebE9+oWfkWkOHE0RYtA10FtE
TJSL0zps08VL5FiBwXNwCLWFbskgxSqN6B1edbFWnQXfD4RiR8LL7RWUWDJ0jppAZ6MpHOAMf2po
xxEP3r7shIQE/XkfWlonY0dYimQLTWmEtE34kA419WFwEaJbKZNPl3NgewqXYQsc2GCv+cxeFtVj
VYHKOYmf3OCDXAGCst2zjDr8FswEX3JvncotIJRtUjycRsd0KX1BBTFSuC3vEgMECRC1inxErtWs
gmJclcECdYWW2qc5spsWMfojzDwf7iLlvjmtx6dwJb0CKglWqPFerCbwtQ01W6JGE2u5CprHbagg
Bg+mJDSpX80JoV1E9vnTMdjg7W+jgSKwDSmZf7QbtN5hIV3C2uyVKQoT5cg0h6T2ne5zq8Ju9ZQe
eKvIZqQh1i8zDs0+ZywPoszVJ6CeB3gnqTkvWXK0YkO8JIIrVT7m5iwIyqfiYgFj+PUkwZqtBZD6
G70VHDTYNvLSpARwKr6UDI6+ZQ5dhggreak0brW5gPzFkQ+Q+AqkQb9DrOc1IK58r4T2Od6LOv1h
eD3TGsKQJNUBUo3f3CliFAkmW2+HceknvS5ykdN5wjrQGR0RrNm2dyIpU3sj0L71NkN7U6tqvhJz
QuWqK07QjG7dUohSvAk54TRLaE1Ull0lt/Spe1nHwVg5oCtx2SOb+p3Q4RL4Ofgfz9U4MQuwGdUa
nNUvjqimmV513GnRVRsefTtIdR/sqRPtyudUcm2FD+kbGpezzKFh7J0/pShefcVteqaRU9ZEp4dC
SRkNG/posREW5R/RqW03eyY/51L4JzB5v+bwEec1cROu4D21FNYyDgBJ79uF9fAHtGxgJISs5U5R
GRGKn9DryTHNcUGq4JEECHSefJiAQqLdOn6D5ECgkeyaQYnfASkqhzTS8wVJLl2MfQisGft9lgxR
ckP6GjG92Mbw954UoOppIWm37gUvSSfVwv4fuoMBdy/jOn4W+CD11rh+p6gefLg6+q4QUdf/334m
uYLn8CMHpL6nLYEGiGoJ/Y3DUBdpGbR5HCl61yACFIDJneBd/PhVOUdyVspI315munhMOp3W6gr8
BP2zf0RWDL48XV1pXLXqLuWuvY7ZlmpK6Jsuqd3xukPhsoeqLSxumRNWPB/OhqPrVPU+va5Bmxyn
LUNgtg9apgpXtEU4C0rAvTQAIAfKsFGnzxkClS2Kod9KhNvupNJlB/Dl6euILAe/zX4LvcI1W4kP
joFIpF1KDI+xUkYykeuxyBL0ddf6p3nq+FiV62p0S+WVLXsEOawH8l7nGIGizwEsX0bwPT7jgs4g
EjBlc75RaV6lfQGGaq1dWxfTx7rOJDYl1rEtduhKjRhruR8K+6d7L7YvdbqUJcBnC3I3oGNGxGUC
XFoAut0q2etTbhIZ5bhYxA1Io0TlTTBiwN8/sPnzQCdLm+AqjagMmRtUsDGcTU03osKT0wlAM2CR
sKjm51ea7CvEFucB1CG1AAQFbEwZ5AEFAaKJkU3t+OYPCZYFuI8HRU7MXsXysV28H5Yyf21UjILW
tQgMDM1rR91bof+BnRx8qFXhpKQAJNysysRvK+cwqWZTwn8fU/NybFWxvitivJpZ7t41aUS53q/1
a3D2J8lMINfCw9TJl3RZYAQ9LBxJlMFmW1hjtwoYORjNc4AMAn6jib4qrvyeqOhqzY4srx2HHG8e
5Kc4E4Yic4fawHNSskJ292/fxQxDofHOf9fOaenRrGqB1KRDpjKj+yAhm5YmeE0i6S8V4qHCYTeR
K2nOjrCX1qmtCCYuPoSKaKTD/e+6HqonkAXtHEqrDUubSIwS/dX42eExojyvW9tZE/rGObJztnTi
wd5bFIForVirult+06jhG2LyxtgcKfUI34hj55Mvto6g9oBbZMFivTrBUJzUcq89ikoug2IwdnmT
M6ENt7MrLNstqjrAYRFg2KBZGgmZIDknTdZVHm1fyP4XoDxasEH/k+7L2F4qiAX3dJUK0SlKisiQ
eE1eHL42oUShMQfu5GcnpWdFCW381aVNN56LBrCYTtz+koimkAl/X/tUxBaXEK9bZRDatxjXn9bG
G1nIuLViSPpTvmvURi/+QEuXDhkNzjbFOqC9EN73fikjE3SEHOfhG1oA9Z8AFQkllab0iIC96LhB
l6980Q3k7YnIdlLMkCG9/A93KKjiL/ZiXKilyUWtrpBFlA0E6uNYptOwdCQIwEGwzptF03w6gr2S
djOmVDWDc/JYyX9/VCNx90u+214v4l1en9OxgpE0Nxf4ZGhBTeNP+P25ioTP1k8FqYqSCLm+eDJP
Ual2gvgJu3Uyxy4DJ+ijCz2LMQvZoglauKJceZUCopbFNO2M1WzlphfSV2tpHbqy0fCwzVTVAoR2
nwHvJ6ZFqhiyi5fxCYO994BnZ2yancC/xE6ovjx5ZJ5ULthjw20wScvUZZxTMoVqvkWuIZEJRHiD
cjSIccO6r0KauMUvqIrKYuSGRNUiIG0/RE5c9ZTz4LSQzwxsn0fAKytb7DKrTJhu3z2jbzQKAsSx
G8G4DcLlMl3mFRmybRdNLW8pEiqEkXS5sHAKB6PHXO1s65Hs+IjiWFfStONwz7z/M60t8s2xiw2B
LXdqr+2znEqi4EB4gO/Nsqj7twJiQyu5hLm5lngIwzRtwgtYNFpLEACwFaMD13YDpyG43NzX1A2B
eIMtL6YMTXo+hAe+AtsP9vGPYiTyK+1Oj7sKL4cmtrxce2yCAaBadXFRX4Zpj1d1gmQA81Yt+yd2
PlN7yE6bv4ZkTQ7CdALSXdHNo0BOP+4am7N88ANxsH+aPklMSAgs2OJshiuh1aGbKb9pkh8n/lWW
/ZgFvcQn741N5HZQcAijcJCulZ+rrpUZq3hRaT18vHqY0c0P5WBMaWbMbWm8CcmE3bu/QBT/jdbC
VuFcid9lDxAimbBJpntAHJhXiueGruWWfxMkJ61TRdr3l4VmcwbKe9bdQjCOJDbC7A8+PbQstsph
IPOEDHK5aFlzRO85F6E1CylbFfs01aC2bHKNPjd1XCHVC7p3zEupMcoB6QNfajHf3mqCHj76KbqF
N1PJkZNk7DmuoVBbp4IpgIIJwNFDDQ0PRfhIwchjGvzKw/0qD0kY/AVTBl2jEVBbu2Pa7JZMMVns
/s0OrFZ3wtBfP1i1BsHaKWj95Shivx2CJDG7C1aojIqnzZR/B2e78BQqvieIEwl05RiGhH0yDfmz
mfHRovIOJL0JL/aa4vghIbhqoo1bJIbQfsz6Hlu0rfY/vgZ98vwgMcqxSZGpi7OJPKRB6ATGQkxS
eRs0VU5V1C+2YzpCrWLf454D0P/02kPl86n8qlRzL0S9/JHADJT3LwlFIwLVHNavhGwYjqFv55H9
YkJtXDHA1gjEtYkYse8GNsSf7dZFhUWNjsbAFbyWBN69AARuRv2d1wFIo+3Rd8zSrt9nzUd8XaCC
wE7hDwm5G2Um9W1YUfiYjqRIObMe0RnGScEDQE5sSCiPHk3UUZ05Q/b2ERXqql1N9SyhvjxBgZ/i
0CCuQqGA8rGjx4T35lURGFg1cf7oR9aXTL1wgDYkCKBebbB7E4zB6U1szFKDcMQcrk0OkTVrbJAa
dsvxwE66u0GG0h1kjLO5ixd7B8o890qc537avG1xnJiNy6kTHLZMKlogZ0Lp/eVSKU/ihdXNws73
/PB+Z51exDwDPGsRRpNWYM4ihe6iY2PBhrWTepUXHCJCLfIqnC5x3Ni5Q4pVdpnI1tyqJ+jLFCxg
TumzBAZYVe0TtXNMLcsXhaCEgBto47H/BZsCMFC+ACYzaIC182ZeS33nmATJmSbo9+skHP9E3TL8
5wgeFW9l+S7m+cVFYU7jfOYK72U5tsFNHAYTKXc1kVkSWE7GcTyoRnWzb4q5N9RHmaPs1V8w+89l
6AuIgTTZc91Dy6UVzro+7b14VbUXmpl45kvPCtfj6I/f3O3aeM1e+FyJAPHk09CY6EE0s7ulOsHx
o6Lzc7c/TPoKlkBbIxHY4eiZJE6lprwjc8Z2ivZYdysZRuopol9LAP9sk3KXu7bIc9eVSkkYvfjv
FEXKRgoGGHK7+yuVkgkwuqCflyrAuQDkAKs6AYt1IiQlw0/McBh0wP6qGxoICHhe/Xzp34vnd8mw
e7cIfb5c6GzGl0t+k7MfQIz8QGVsWtoB578cePeFX+tm+5L7b9XxSQzIcsjT0Mctox2/AL8XRcW9
9zcIqA6OtSKDNI13qGmXCfgrLEqtGFPUw6KDAtBeh5O6utJnzr0/bTJVyZrvMamO1ZBifLm3JN3+
GVMLc7nGmJlyITCTNbTfQNF79JqBnTG4e49CZIGr+CLj3gEF7nPHaHlOPJFCfSYJZvCuBUYlI1zY
AXbUPtcuyBGCSCdA7jziFh2+xF7BZpU/uRJIrVeI+yw78l74o/45H0M6sSiCMdziyT7wLiCuqo+1
H3v783aluFD2YreWT2YannDBGm4ACgUTpJkR+a17j+DpX+lJEsDzImp074f7lv1Fpx9n2BQ5/+6v
UuoYazfD2vbp+MLH6CXM6c9zyrCJig/Xf+Bvy5IkppZzo2Xu6yYcbVNE3vlBPY0qMEvzY2lszElP
J/Lxv0nB5CJ9mKpgc1vBFByYWb1HDZuTo+gNtFT/Ke3Wy2jRmWAdpV69o1VHXoy0wN25JFT/FnAR
QyDeYltQ15lFUwK1qR7Cn5czQMpzA1DxxHB+nnRs03Q9sB6LoQ6NA+83V0UTk8evAjlKGcWRH9OU
Yp8U4KcL1mm81uWBJ/K/6947OminHjyPfdSLTt9upRIbGQ7okP+EsU3rKky8CK0RmLXRofLVHQd6
gAkXoDm/gJHjGIPBjxsTLFqmAcZ1INfinqqmYpXvVbsrQryLNIk9HZD1Tf00+sXLbHnFHsSbG/EA
etCMnf5JFc2mxIZA+jXWxfEuPu0sxJCaSiskD+Qh+j5p1cTj3LQKIMcHSB/XoBstX3uiYVO7Zo5U
mTVkgQQMZomZsq1h3mNAfVQoxDf2PpSPn1Qo+ZmeSGvgys1g1x/Q07iggwJayXkk0iAoj5/VYMwX
WPzjx+XFdTqexhovvHo7Ek/1ghR0bF/Jf5s9pN+1fP7yXP44nw2TpnmsvA8x5FmXfkxkUH6VljwI
ndvge1axJkofRwUwFY7kz0yqY2dTeJ56zrm7kl+R0UY8rbvarw5TSh4P5JmxpXU0nm7yqkwPkNg2
20PUk1oAzTT+qD6FdC8YcF2tjwOZ8qtwy0GZFxFDPa1m96mBrc1IVkLIcqNzmBHLqTaEZioY1BY0
ngFl6Uz/bKxA0o5a9Rh1lzS6rSWAXe6iG7gaM1Elbdd1mLCCyc40ERm4E8f864BXDsr+kSCQjWEj
KFUGq+AgDarUC10xKEAsijqEaTmBw2blnBGbfQupBfsFU1wYS5kHlDtW+YQA4/xcjU0MUcPwg6pG
qGf+OpTg40vofp0HAal5WxBwcqoWdZyFQVB80seuhAAw+gtZo4ArWYU6Gg33DGQjXVByO4SHlPKv
JnQDeEu+UpgV6TrBOdFz9teXZ0aVdLzGZSwuSjU0lhPNFZBZ0p1mvVEJpxmAwbh/qVyGLW1gdBpI
cHiJqH4EZU1EcScXZPUmmw4V+nhmaaq0bakNuUnHpTHjuH8PcAZy/KZZDucWxVocKLwgUn6Ng/5J
5HpLoee41tu7waune9IopPtKciR/y8DZMagXzhc0BLJLQwHrkd2aR7xvqAwgWYRZLhQukstjzS5K
Zocz2NjuByD+Vk/xQk2kjfY6xYdbAFgYtnWECqdfJGn3XmlJbaj+8up+wa1/DUsOaNb62s4mvQ4b
rRp7s8E+hta3p5574ELY37YgFE9yL5m1QrT5MuLWgzY3JJRA1l8rBcMIgKOpELvYcXbB2xfRB9vx
W/jrKlt7GPhtSoiq7lD6vhqW/QFl5aJYOG9llOsMVACwBfhCiWG4FjcmUE++oGqLIrsbDTJ0UIjF
CXlDTPmAeeM7AZ2KgDok51RtJ1eOHFFZT3iTkaDCrmoxY7MQn/XvGaa7nAOj+F7u3k4HRN4xYVsn
2GNoFYDW3/u8nOhChYAY2Nt3NI1hsnMs9HCUqOUuNDi8yI+ktKzd1rYvbpOd4wCf1Dg3mhO2ijrS
0RwrcYbHD+PLaHfdgxF6UIjBk1VBbO21nw2PS+0WimYuyuagIvvQlx7NU1seTM8tQUTJCAj7ssjH
xIJXJRLrrrPqM0ZA6vKzzNHLKMLBsPE5SovEa/EU4b/h7TashzkrK53lCesWmxTAra9UGQAaCAuu
KENdXIdlgNtcLZ4p/NAD/6HhS4rAhoO+AGoWA2of8Rehe5+IC+WE6QG8eaooeZ4gCSbxYH5A5Ska
AsUCaw/TdTZv/DiDqRMOeM3QCpe57NF4DlqZemyfvyf99R3aFrBblGw+SxempZAltw9gSzj8izaO
YGXXPwBSuYk0auRQ0HnXiDRfbQUhzk/n7eqeew6GI9ZGvjh6agmNzyA5kqgIC1KHU2zHIzQPrn1K
JPrOUVFiOzDZUUIhPhNWlYsSeKmdH0zB9svoBQ8wwmszx3cYTVdClcy60qxNVoqe7DY8VkScKwMY
+VvwlstLXgSoYDMvZVBvyFIJksJBozmLijbrXmqAO2CoInsgYPB4jwuWlTYHcObF9DQahOIrwhPK
OQZFOHRakHkZIxYCbClFN/V8OfNOAtKm7e/uY36dorfyD5h5SY/foLcHGEcbeJrw0oY6lH6UOK/4
GF4Kid+dqvxg0lphKmM/dO4s3s+mNZREa8t9Osf+O780YKkZNqZ3Se/HOSriU63EGCAkAuKyhBIy
02pmNMG+TTpCGb4rxvuD9/lhCVZ1VgLXY6BvtvRfTXCOY6wD9UVRCHEgWqrV9hKfp/i2UnLeFEWI
CuR6OaaWZT/M04v1o/uRGPnmCnlH5hfhrPfLJOdE+WuHa4irlH+UFNJMluzcu0fIDvUY2ji/K5Fl
0bQ0n59skJ3l94NKNbIyEwH7x7OWJg93K3Y796n1MYI1zCT/+8VwBs2LQuE0QHyTiTob2tvXvhAU
9y34SXaFlI3vusqcozIAZd28Jc61mDqb2yK54Dya6IkPl61f4G4Rsi3PTTioH7XsPZ9l3OzewCB4
TC6oLRTrs0ijEx+v53itfSAMOjy4vebsumJ9owTHzKSanAghBiOvP/FOQp391lJyBa/gxYn4WPpn
NFY3iC+Vd5P5ZfKNSBlRxGjp2ecwyefLh9FIOPA0rSZLNV+lKoNeyJaX/F/7CYxI9lhIdNC0MdVQ
u6uHmO2YKwAi28n9CFw5q5nt++1gK61BKGfrrke4BjYi+yStGTgIBRU+cjR8iGEEPSDBXqDVPrOO
yNo4wXJu1AM+NLZwyNd2hly34dVWOSFPitfWDXg6/1UdDWZ1eF7SuCMde+6HoEyBBEb7khW1FfTh
1Crj1d4IophDAPSmb30fwPLmfwaDHbgLkjEVNHLdU2qhaL4f59G+db1lcNz3cV8/YW7SDKUn7eQJ
l578QRM53/I/W1mldP69SZlBHZlSDAcruCYU0LwNTkKzjVdIqxgb+scvreDHkRG0t6yb319xb2xE
nbQIfzQ1QB79cK7XyQ/CNpECx4su9cD4yGZgYsIB/SCo6fmQqOSNxzKSeIL8gWZU9RqUQktx4ooT
3B0Mk1dnYxg9xXGa2FvVSEoOSrMWNDWIlQ4Y/8xDIhQsz8QWpTdf9dXcddEvndks11753smZlP92
M8M2rdrHtxR0Kk7806RV12JlvY8usePF3riczqpx/cAo8k55PpP3q1pYAJ5+MBQYgEqm0d66PuYz
iKPIbSGU3VGbEOvrUd9wqOhDIa0Pkdnr54RJPiSY/2C8dY/IrpgajO144xGMgD9rHcm4EIJ5j6/Q
0QkFc/xkZ332Sd3tp18KmGZ6f7x++C3TQHMT3Y9e3xbnbbYZ3VGDRDV+mOFYCOUmtSeNhGspyHUn
CroZlWTVC/rlwt9kR5TsFIofpsn1AZ7Zjn0ZsJpXqzpRtrfG9z4iBbLDKmkK4KvwI0nycd9O0Y9V
F836rkVifCUgEgcIdBae3UvPkc4FBEZQCTcAKUR7KOMwunELX9NCIlPv9JqFkMLYt95nTljXlSeD
ERd+mvK7Kx9AORzS76ZB2tXWZynGVlNzIeHOzbueXqUJ24K+rvbQgkR2xCXOM2pJA2ojg409AkZs
aO5InssuKtJcB30XxwnxW0VhBvnUMSfhaF1WPvYiroXofWts/igdv1+HVsRJR5oevjipu7R2V9K0
F8WSL/ocniWNOKsRX/QVn6PbXKmjPPXBIlFfKlSi/m2hcmeRR+iLGAPOWAK0h5HYb5QrvYmmkisL
j4vuhNMmi2s1tj0AbaA1li1dP+INnj7DlopEhbk7u9QPd92L9+rjuJxrEG1FkHjZEWBe5WzZ1JwS
scuYR5DbTcaVukwXBkppA71hcJ3dXJdiYSAmoFWNJdYqTPwAZnRJH0a7Xjdb+fvWnXdcdFunDhY+
SkO18QNP98pTfsUTp//UTQJL97Unbt/WtW9yxdE/dpNWxzqBF/1c61FScTymz4SeeBiyCw5OihSG
UXwX1KfwCUGTPIFpKX3rtBfobrVsB0OiU/uuqmdLy9iZZkODlf9H7QoCbDHvgL9kcgpRbXOovT1J
F2+xssYVprXafJlA8UZt3HR+KKUSAq4nuZx/olr4cRHIbIkDpUWqkbK2mtoRAOBCqHhNlCMbg4up
q0Gs5zQ4jebBPeplSJR4ff9gYyG696VQh/06IJEQ477ODkDVDDNi8f2C7hgKRKx6LCrakhqoEbYi
cp9EH/SKiM+56qyTxMxtbn75SuqVcB9oIx7C5HuP/607EtYvCpdKZHLbJtmISN2LXUyXj5mwmat9
BtRKUfIyVCRVKfRl0LKRWOcUMZiG5GNzhc7xvlYLy290FxULipmqWtN9ib82EJRg4fjAviV4vSIH
IQF3dLXNtzYoPBHIY/lGYFZ8QNy42R5ry7TA9NzkGBQ6/CWKdTCIOCSiieOtWjXVWnBi3WyO+D9J
h1h5jxO5GD2dA03ZejVPJEvxBB8AQNqKxtFsFbmDleJ+d4YXirfqbsW4upmTsBohVplF+7aqrAc8
k676LwYkLoVYFGMcWtEocuAbKjZjmZ+LRohj/hj7R/q2ItE1BCmd5v25kFyMkWkZAfWwqTJznECS
ttnIcfoOiskjgobZGwjOiPS7esXqBUCb4/ABw1uDflm45ofbO/yScnqaBvkhz+Pq9g915I/LuXVq
TDLs+5PkM9MajGWwpNkwamOFjjBTOz3OPn/ER3wAQgu0WgVkqESDwFzsxrNkjl3nRrTUlvQ7E1lM
YCTAehz/ZM8nGpVu8EVPEpjWhZTaw6efM+pfytTp/jMmhX27LRWSHfEdyKNalA04w9fgk4EpoRFJ
0NNlZknEcY/pBN6Ny5jUWfbbKlDk/f82B9pFTpfLFiQollcpZtotcxQnBNHt1MWiEAP/T7SIsWky
NvxoIaWkHPYxOki5cbey4tF4DhgKAOpmVYT5WgTxY4Hd3RSAB98e2kWXU836TvIqpn+cl86ZApxp
gceBX9LC8+wx+SUN4wADiCyjmjTGi64qM6eQqUVazKy0F+IBdEww1FEMYzRF2756+z5B2CwU8lqJ
zk4J4WssA1hFggfhg3Kn+itIkzK2hjomh/dULgvLQgQWIRMSRadxr5pJwLPL7+NLe+Y5ukjVtLTf
6Sanwkn6L3d/kLWPj7LlDMLi71zY0/sub5QHi91zfS908Ro1E6SsKa6NpQkOHWB2K/6wEyiSa/6e
5VVAIETkI44BRbyo8FSOPSAucoGseN6JeGk6N6R9Df80B37pNuzSotZoXPuXva4NoLWEmlVpAN9a
ex+D2YORmoESQFkrxmhtyNGfkBsHj5s35zyiYUTo59+WrJNj0zn42MXoTetvfpCBLPAzhGGzsENx
WpHqd8PuLWBlooEMT8t954MXCzJ8Ix75y43Nzghwjeg3dpZW2rl9pu8v+zK9zqqJrW/rLCvpOXbq
EympdKVfkftPFD0aMZlNZZnu5lmreE7t2Ql0XfME0HKcUgbUfgFRzA40lWjgS2W0bBtgEg/1K88h
aTlJ8eWtZZtUj/53i0mFff6IhhzFJ/FDZUUFrsIsKJR4/YeEiLTNUr4Rwjs/qnPzPBG+HYHn6lGw
0fVedYP/VkJnSVGel3ySEpn9HK0HjBVXkiqRehh3+nVQ/68nfhxSHIThEMHbMnFyBgGE2Z+svGvB
HJ7A5hdxP9Z8rWyLNSijDlI64VZSFsmXNcR13LVqwoGtCsOXHjJVQ69BRW9vQisDsWhmvrvL68cv
OOfhVGdW1goe0C1T2NVfE2Zsw4EbnGcJD/k7ficO+NaztXlKXeShv3AkLA/FzU5lp7W5U4U3BbG4
mZ9QM1Tnq7G0y5C2AneftijS8HkHDlyRyDFAsZZHisPaM4hkMQg3ZQW3uHT3XvYhhkTEmPntzFVw
Kvmv6saG2OORkUS1B0LpXKEboZOc/6/20mNkC9VUa2VTF1bjULGOJWm/55kJ/x6Ob6klARqxwufK
OS57SGTLpeTbkMVtNk2dsBEmWdoMyoqexs0NQSyej+bh4qkl9OrTIAJDBis5RZ304CZ0BV3z42M+
DCrMWGurB8DWZUj4kjPW9GnCN/ghvURq1rhAEhX1DFnyyC6mL0duYq2fiL45btvXDSfgzzmk+xg2
8UphoD2mjGuVelgf/aAt4S6EODBFL02BVW4t5tYqGVwpVeX1wC0D0U62aH9hSFqx1xp+pso+ojuS
N8x0XZ1CIaXtj6R8ZBCjn3kLifjllcEQ+n1QjqiChn2u9qu46uno7hX8H4ICWZjhMEIghfMe7RAw
OhItphqZ3q0lEcnwivkBf/79H+k908LTvZDDkujsdbLdwbmTiySNF+PPpQgUgsA+74FgJd93ADGw
ECpRMYx3bR3vUVzwDBy85eZB42L7BLGBBE0WuHtDR3Qj/ngSolO9YiZM5GID0seczVmfm7qTqeAy
PH5tfaOwTxZG3G3XIGbs2xgUMSJjGYBk9At4K6PaAIxuU1TU0R1YVM5N9peC46STRzgLcYcPo4b0
oqOVbCA3EdrKUoNDwIjVJlnPF/svgzyLM14JU4skE/pnIphjynaN0IZXRDkMyuooF8G2WkanN741
HtstfJct1WULAawcLSSMhlYRmBLtOPXYYwnRkWMY+Fqmg6kRXvOV2IDhDIwiFu7feb7QRymaAk7T
tflhahX/AsINbs7qBZIjSgghkjtmLGtUY6qVJrYkS10q1tqttIec6p1E3jl6ZHSfO+RCSjwOwGR9
Dp2vUkYcBgJ7OY9iyRqtAH8udekVf6F812Rn2er05oT46h5ibTFuaRYygC8WX1TXqC1kH2GBCRf7
mdK2KdIHml9Vo7Zb0/S6WJ0KTak66fvRMUbImYuQZcoz2f74HyFhpjdvnv2RUd+HKc8wVot/AFFs
uyLRJN8xencodXhZRCU6J/aZsdqxTYpK4mucX6H337kRlJL3uzxcHZEJNh23jqKObBFbjtIPU4Du
r46PUl/jcuKUWoddnP9JsHUazbdq2LNYv0t1Xv/dq47w7qnp/ZPJJnlBkEdgj/jV72HK4lRLb63l
+UEdHweFgqR0tKVSyLvDS0oYOKgxtRNDB8vd7mCZiQTAX9rrsthDqGlzcWmwiIjwYFHWYTQBCxJl
e0aPmUdyvzul/my41r8zCu7Qx+TvDuw97G7fFfgx5a3M4/LbOjNd8XSGOysrG09hySpcVjkgwj10
dGpXYMyblv5KMSNSKD1AkQBaOjnzITcTnlWILuD4ATDZnrgPvgxPZYEBgakki/a9JCD2HU0fqRVA
4Kw9vDPLp4PqpA51u/joaDXgLv5cr88LTrZCzf+FW4xdprRWKHqfs80xOyScLMcQmbW2OJkkZDQc
44mh+5LTueFCXP112v55S4AagKu8W4/8P5CJrFBAvuHRByBQ/H+U/YNduulF3gX6k9eB5+hO2sJD
1vQOg2X4QMUK0Ry033PwgBbercnTzfg2w3ZA+kxPlFFH0ozGrMETLEQi+XqvfvdyWcjX0Ofh/mYz
uFiUa+4K3/4Pj1mP1wzEs38f4yIiiUyPJ2Ial2TPWvSVKmi/Pm89z0geJdBpoVyFM3myShDlzKHh
CRm3tc0ogiD9dR1hDzJx6MSuR4YdGxE7BIEy8DsfBHUDHgj4fah0/b2YHiVWVDbQfpiPvk7fa7wY
6a+Iw7XAGv9TVP8p/9ocBX01U/5+iHkesQVXrf8stURBDPnPWGnN1UEvNNl7/Mjm13FmKlmrh0Fm
DqdAmTEFfA01qf14oLkqAXCPgoBq4C4rarJONza9XaG4qSBofzsN8IRoLZONLAhWcHCQmB8cI+nq
BEMqA+2UHfJkTIXpUTBn7DclNaoYo7B3SiQ8Uj6lQrT9RG5+NTb4Q32aeTQzWbgPqM6Su7YyTZMT
PTOTDoePJRRMyGFpGHNNWMn1oaLCrFLMERANNsa7Va5zcsPwBBxvDHf0tNqnnW4dRL7C8XK4aMwH
10SqWZEgN0AxKiaUVnncRaTXqPQ5cN10LYOfLrPYojFiOLutoBOlOEvf4QTC+PPG3GWX+c5EZwQP
HnpefxL19DJCOFVtpDieJE3B6bHG3feNz8OVW9kZac3bVMVpxIFdZOQlsOrjxH3BywvF903ir3gq
XwSohE0Qq5oV3xGcq+5zVCHKhkG6fRCxNgCe6s7MlXyHChZUkRnflU8tUrWxeQ0AhqFV0eo5AfM5
V3q/NlsQJqwEpEPfITsLax4FtyuZUFdeReZsExo+J4i7GNdZO4X7S+h1LZ+6hSCwhxwYX6gHviSV
DXM28eU38qEqwutMQleUQaOq+eSpilfzBJF93qHy/Rf+3u/OVXeegid/1STUK1mDwwCasEuyDepY
2p0k2n/foBox13lhG4jlFTNxskcJaW1+l/dLkzt37FRhg9oneq4pRfs4dmhKXKPGP/kcdZLCWKJz
CTuelsM9tSj8hrXbnnJ6aH4pG4U80rsy1PiCZEXwBcZXySMD3KSfQ8uxZrTdurymygdFXIiP64ZD
Ga/xTSpUJumr/KS/EaSNAgrPs7WsXgZHmIJlMVeLIIaQhUmfKcfNK0ENp0+3quJApriEcSziNX2q
Ch2Qw76+MaqYIyLoM9w+z4ccc+7i+VMixVb4TnUxNN1HtpfK0/28S1JukxEQvkzQuch+BVuoFs2n
Ye834OkPCWTX9jO24PBYcdZtjYOCs1ib3XoZwVNdn4fHKrJqnqg+woW+K9+JJB9iVafkxrA0UH+B
PqxbVnPXLL/QqV+YE5g8qXmPqze0Ho7gI0/YtK3OETtBrrbFoZl2wwhGn+e0ZXy8TJAw/Camaypu
kfoDmwH0SpZw+JZTMBCmEehZpAhZBilKLx1HYRs3P76yJCGkLMq8GT+gcfKyjBWg8ZUqA7mRiN1F
7YJ6uMyFYoKwAmwI/Jt6zg327pTL/W4oz/twTBFwpPsVcAGhruIy+rAwAdKGqxsAz/nyAWCBGdgg
rRKBONLjY572w3blWljOwY8pI2DGfKO/++whTK7qtD0zUB6h/x0AueUs2UbO6WuZ3d9KjnfiOhA/
x+nLYLAVa5ZHS10Ef8NjT5PQdqjJaiF8tlAaKfe5quonCtE05J8qbxtwb/Sn3DeTZKwCq2FZqaLI
2u+si1xtqE6CaEy73N8uWEYkw/E6E0mY0VBMJSEahUvYJBm1T0zwQ9z2We+nu/VvbagQoPwxxE9+
gFY1R30BVcHSAfqawA3WbnBHb3p4sxkB4P9QOKLWtLG35YnRlp5qVN3hQNQj/pZm+pRpnDS57q4Z
gW95r9O08n5FxgqH7yR136Sm2zvod+t++B1RRt4JO/U9CLh1iu7a0D7M71dR52CT5sKcxR4MZYg1
1vl358eIHOnHUauWx5QaLojURhmm42vrealUDs4ULjJSw4E80TZJV7ftqlOq2e+7RgLYBAoHqFPU
Z4SqSJeVaUqpjopKGZIN1wU8aHBKJFkVgkmEVPsWkMJX+cJaZnrM5e+j/tq1InB95cQTyn55LM/y
uPtOPwDelwUBJsT+RkzcFJssN09BGxAC9ZWgnU5j7qbOm/yoP7geCFYCm+vpQ/+LMDGyttAvhQAo
eCIO0xVO6VNQuLbuZwV2eRzD7/GqGdzXNq+kdV//mNJ0sxCXRx1AAMo2ZiewMrygAbHFqywyo49N
yzhKgI/UbhUPKS9sqW+fBLD4d6r4rGMWPxSRaMFVXldIKtDk4xzi2T2uK/PPWLk4QVUULmDDxyMK
WsC5gGy7YLIyRqt3bTh2ZmER11HL+CPCCak6iuPaIa9vHZLuHEm4cz+QDhIRFn7vOnww0cGoqZO8
nfD3t8VrOSapCkPdL+gEv1fx9pVMki8S6XDxYWXIXx/ouRsrTAoA6YstBjHmxGE62q1GnuJ1B7N8
f5e/RHOAjZSWxiq5QUkyg7gBPXUUys4JH8Xx5KTaAfI7UOYmVb7kGWuu3Dc1pT5yc+vouxhaK3Wc
JhpKOewIfh/q8e6sCCgk6zKBZxeR6rAYJzMVgN1YEKpcKHq3fqF3+7PiQrqOTaWvPtbmZ+VxKacO
vf69nhXEioAqDpcUzXsIz6IZd+kGdshucLvvPK2bqxKPsXyjDrX/95+O+BDxxPsE3of4//oXe1L8
/1TmO2m50qsGPtgDEUdJca5MW82vOJaN/xjGWZ9SKpjqr4RNd/WdA/VydWfGH7tG45UuQf0wHW+O
7q3RJ/bgviqn1kwOLMh2EsUAVw1+3m83o3RV1rs/vowMPzl1S0ReIU/vuA5efNTRbclc3cq0/YTy
BMh/zoXjXG5Os+GLraWBqb7/NqLRqKC4Qvgep4CFMDmXfVRpeSSXKH0Br+7DvJIzkXhejF3yboXA
P2zrP4fePIyo/TzmYTGNI+ESctMUSElnAXTU7d1ZYv8L7TvOxSErHSCNFHgw8yEQYkxuJcpvgmG8
cYUcb9+XPIC8Nm1rgNVTD9UlDclj8an+uq4gfdcUG6vBzTc3D1/kxNWe42S9dXeS5nLoX+/M8uLw
PXh22u1fTQPffKO7xUtkI0uTde3ZmCBVd+pmt+a6kwl9T2esTL78ET7hJkR1kiDhzQ6BBmMx/Xaz
sIBQpH+1uo4PlzstC5aVacx4ivyF1JKZPEypaJNCXIwp9DwZlmwSdAMOnUNQhYKlgOFkGex3uIbC
B0tQEnYb8p/ssjy6NCipp5QxW5nu5OsR6bJsJf/FQkNmyCsUec4Qd9BR2ZK2maKGF4IF0dbVFLAe
jJ6KnM86jhI/7uz2OWKjdkEkxfy9UdEbL9SQ6k92BYsB+lJJ2xKdLyrNmDolGDrPioHzXgfAe8k7
P18+PkXEToPcZ3IT2aUQAFuws57bsBrOLrGns9ldcW5E7FjVnGlZbiigf0Ms08Lh5ceKQAI+7wsQ
s7UIF2Pe+/YmWRSxkB02sx2vTwGWTMI+ZTvxX+LZdrQgCpG0xFquqekt8xPNEb7ZOPblw3ByjuQN
AItzQ1Vpqcn2U7Qro0rE6KFSEirRFF+5Le3w5FqdGXDXrIRKPSfiWfmYr+neZfP4Rl8ZlFrQImwK
+fR8K4YXAMtGyr+v6WquV0MbT3TQ63c3WvB9a4AAkzQoMvMO6/sIip4etwpQRlsedMUC0K3I+HQl
J2JuKpDZlP2YP0djQscLBh5T3TJjcsB3diMcZL4cmdF18I7TTk0+ue7wbTqbBZTedEg68WGjoDpO
rsS6G2X/KkDyxhVpqEM0NMrdaUiuFSju0tnWOHn7RFU5Jrv7I975fl28syAby3pJt15jM65IBb1U
9Wf7XwTPr7fCG0c+cihSTqkNgT3PyLlPf3JEMCXd7A/HRHzuPwYEQv9+fBrw4X8lfsRgyWP6ErTk
ExtT8QQfMRrdzD/C0tKudP97X6VpUkp36v1+1froNmuK3ccIq4JcSw5IfFxIru8gjTg7unNAFcTn
bW4zay+lqZyne55la81fQr4uiYnSm/JsKRY09NKjEuXH0LfKfxZPRUZYJF96d9uvSBjzNPW6gww3
wXxt3JGG2ZNLVs6Lx0KYYznGJO2ga2+XQlNTdYsNkVIZyEk50MS+Azv7ZJunZuQSt64pIf3vZ0em
wf8sr4cZowEifZKAOYcbBg4BNI7fdFxMGHkIP58YOIU9PxQN1BwK2zCTmc750uRASFySTWO2A7hh
f5EJdIoBQkd275xSfS+TljAhGDUtnBPtQfvPILNsMSzAvQgyp5n/EExIgpmszyWUjvZbMVrFEHmH
xkZZJxbkAtFCf1WfjRRnkWmeK+k3oBbuToSfBCPbdItncHmjK82SsxggwNc3veZNXuL3zj7tQfHV
tKQBah3Hj4KQouDspwHomhzdOruCaSxlKSO/D7AW73BPd8863oTTk5Oru9hC4LB6WdwQA5w4qjY0
Ctea8DZYAUk3NQKD2WKreq30Uj5nWSbZaHcWmFR9adcNvolM01++nBAxVnZI05w0FYJiV77ZzDyY
Nqi2gJBWv/g6BPbZe1BPix5Rqxu9W//9jUNYYBuJoDIyZWW13FSOXdyJqRGxacwAFFidQ/0WLRd4
aysPglbnAiyNBUdT4wdTn+atrN7in4fJdb718h4ZedvaI419aPbV/DU7FBwQErtpyvwyMlh9cfNY
YqS4tJH+CGFaPbbddhUi+vps0kSkYSBbNo4egF8YPcP/D7Rb9l+qGdOlZBieRNRe8b1yZF56yZsk
72Qrg8cwjmgmGNGClUh41Y7LT4E0M1KgKUAb+yIkFStHwiYuJqGyqSqJ0xZhlK2VTc2B8wMY/McE
rUHUEVKpJuM/nhc1EUSgZl0VJDnHqEPnVT4eYuiCK/8fImS6C99vlX2AqtFXKij9kE3ZM2DR4up2
CvPnU/swfog1lha9oa+APtU7cX+dV5Qn3QirZLY1i0W1TVLbOMZwFbOFjF9RLjVeBPUiE9fZoOp5
ewJS7nhqhswnRoCVytCyn1Se+JQHn8yBCyYn/M1OYKX/BYTy4Jb7dImKBJWU9+L7M++wII5FcLIk
7TA2EzRhE5g0LOegjokC/cXvuc01ZTh+S7hHjIg6HMhEx3Rs21bJ25/Pti2SNFcfR6rxU1CwBKJV
uz8/IEFko5t+Z3iuKFU3Zb6bk8gMs28ol7u9HODJIzFVGvMc/QDmtbLNf1YHcOaPDaUsvi0LTUua
63xBiUYbcgDbRGH9mIP4bAhvylTdoPcaCrFB+iJb8il9MV75h3jTMLqT1kfOamBQe5aQRq/fev5N
WdyeTqlx0mhn07qOrthvxGYipKFtnXDBjhncPLbmnm+m7UN5P3xaLWTAsZvp14r30ro/JZ8E/sE+
O3N27QnlWnrknVZas75IeT23Gvc6pT0yxVCPRLxJO+7cDTyblfj7wfaEnpnHr2YtQ6aSwZzUZM1+
aQe0zczhDG11gFHRYD0VGs2PiI44HTgQw4gwgNzOPfUgMK3jDWuRbpbGMEQolq2H+UFC5wp+LpKs
y1cfzCg4+nHn8nb5jDBEZhuw1U0cOSPyiHLO2l1NDCHlEIE8hPQ1N/6AQosIqeTwMnIXkI4TbNhG
easkxDJpiW6UlU+/tXCiUENMt9Q2UpZl+qeBHgMDH//gdz6Pv8/YEwkhr/8+0EgwexF2trFJZZZr
/h08Ebdkh6FEwj9i3omC7+NFPMu8cAdEm5MrOWGMWvWMgjX5rg0NrGzN5aeTjHBbYU2vA2S0Gaz2
J2VP0ZmdgrO5EX6loYyoHIfz4FHSusZRBVKtIhD3rGA9Uf6sW8RH9OZyvCx5emc59PJOfChJAN+H
1Wec6YbP4BIPWuhCsll+oi+SCRYBk26T/BJ/JdNMBiXHRPli48JU/h9hdxGs8opA9GOusNf5+kaG
0zETVjCW79gFTare2KE2QHbPwCPQLJ1pUxlWMGvGZtlrTWbOckysaPQtWyUO5ggcLQmaGM1XdUnP
kLIkDOMHr6i8X3rBw+zkpdxTWBgbB6EPN0gMgKbH1N9GoRuftEkDeBFpjoyweyh3dNAYT+Kl3bmH
tsmeKlcRu5J5n8GdsNY4W3X4eJfCjYtiGV+CAvTgMpW/9J+bnw22cJOeq6GGj4iIQaho1lSYY0Nv
uo1Vv2A4WEdvOPHaczxZxpSWWSOUTS6rmHcL8qX4ZcfXs4CZw4ids2w0pBQDzcdwOotaKR0qKcEJ
RQpwOCbxwdNOjIWHBgRbgsBel3oXJM/2TPxS7IITHUbVxjViJ6E++Z7T2hQuMFJo4q9h3nwrDbtJ
AfCT8okBGdX0DB/h2H5H5wrw6oiqRTh8UnYnQi0pxqOU9MvSmitzO9VaOrgcPiZ4KkTentYGM9gV
xH78aiPLu4btLrZfeyYvfRMkRmvzvUMCqP7eETm5y0R9m/prPnhGgd8Jyr5Ipd7G2AZUB/AAyg/m
dxSOtYXZ4N1f/aZJ2Doy5hJiRUYlzCVQCaEytzos3pwHhgf0MxsxzgT2liySepjN+cVuV1EQHOG2
ePitTHKmvjiA8ZhnzCAkpk1EU1zPCK5aqF74P/8HyCa4yE+qCQyLIOsn92q0DtJcs7hLUKtvuPWk
G8+lXmPTaJfTv/fNEE3p6CPHiO+VzYe+P+1JYU7B+H1GMANcv4Nozi08z0yNv2bIh439Mp5zzmBI
A5lygCksg1Bi9sOk4+NyBPu5c1Yx+N0ExhvfCDtfOytwWlH0qfIi1StUwWC+NtivALdagLY56Rd4
HjDglk8/z7398VRP/p8W42rmtyVYZhA+c5YPhCmtNbQ700kZMTfy8Ka1dnktIBpsEi1Dlb0bVu2U
XQT/PbKRImaJVBGEgixvvD6h4K8vaP5ZAKCTPcfI095e0GHAo0OdELOeLDuMTXX1DYC7on2bfVoa
vI7NNE42MQS6i9U5gnmVMS6TtbcuYl3Zi2Ljby0mLSNj8Fxy3nVMHbHuc3M03sqVqa38ZCf+3w55
Aenc07NQBZhpYQ1fQy1/HC7DdTe0Tp+TTteFleFQem0NJ7zDOdtRuOsme0otWNdC3CNVrc+EOqG4
KunGY/tyqGsaULa+L9Q0BQTudbx1HRt9L2SX4LO8pLXoitL/HmEbXSoBhjNaSprHmuLMIJz3N1AI
Uf3o60ovtW5Qmydnj+VlzZns+y7l8OQ9L1VOLJ9BEHWbBHsl4rg0nTG+0LCBXlQjFeh0Zw0i8G50
uPquIuBlyeaFaJpQctzZRbzBUYHiKiqYoAm4mdmSWsusjtnby2//FCRFBpyeB7y31HikzncUWrhx
uVHcRBLM6MwXTGexgLmdVkp+DeDJowRcb9WIxqeeICCH/1i1iTIi0Z/4nELXc9rrsV30IdRrqfKI
TAsfQedYZVMq5biO4OSB80+5vK2HQyfvBYzfAQkRl7Bgk96Jb+3RvRnXBt1DYYjCrXmaGQyiLGfp
DTBwjPLjvZf8RW33dexFZ8BDFynlYt8bMnBIMY6XolkBTcRnCrtscGfMN5ZdF5TgB7MtLebXvvV+
r+qE8iXi7fhiNh2lHZLVAUpmzkVszTUK9C4XVXrQZGGFIoyD5pHgGQifmVY7xYG2Mwv7UEFPAUmW
SvvoLlwDBlX+qkmzs76H5WFerafcwzLrMYrQHDo2AU2NHzfCofRcX3j/xfZIlTCvFu3OS+BOoLyn
tVPRzuw+TC19PdIm/4m7tDVCww8BJBMdTgcjVz4+LaQoo2OL5+voku0ouAI0VMFFEuk0SDTp/eUZ
eNU0JFtabe06yq42SqQMcPOMHFHaovvFwUMfXeGgrJ5zhByxPkOB7uGh5JnYXF62x92Ppyn6H0kB
yF+sWm+9VhC9bdn4qTB9RVihMXXghdsAQRoFJd0/AyPBuTHloIhD8ZZVcxFk6MceU4soI1f5dbwB
lTu1dgOafh0PIsz/lk7NGFAJqEe5UvI4wyAX+wDREku+ugVjgDf7EhbJgKO9cBJfsF1jjz3GIMtI
9OHxwPgwWnxHg4PgkYFe2CXFAw7jRx3Dr/ZPyn0CUeSFX1702Mx4R2bivIZjyi6R7PSu5sYa8AU6
Yuf6sWhcyJ6wWoNCj2dyQ32vVj12TdqgUA1YVdZXtMFMKfCFgXZYbszur+m0efs3ICFcaFjdoJvy
kdOsfU+Wanu2nk6VhN+lCXkNWC9hCsOqTeO3Xrzkc13ns1vZkoyaXsoHOGfpO74DD0eqCXUpaxSn
8MAqOofxSSW8/Wd2GIGTtC6ALGq7cYkLAVxAl7lLLK+QbliISggCB4xBBZ6gO/f/FU4aoMsFIPQP
LnB6v7XQG9UdHDZ+G4D7kdW826Fk0qXtWEUnmptLZGuHxFfjakgR2JJgxg8yuH1OQ2ZSpmTnL9DA
aFliv+dyjcDMcJXCILIpSH4Y2dd9LBdeviRBGautjovpXj5UsfqWUq9Ul2+3kzwaY2YOsjBRrUA/
svHCEwq+aHzM0IPsFMyvbDcQc74DjdBX6iso9alM0RDe2qg9khK9Ph18VtZb1I5f8PxfFKu3OGcI
3K6KQj4yPh1tVa+fqLZLU20aVKpIXrHvf1GCvAwH6Ne/StP0hv520Dx1K238t5PZWgducf5ZVOIN
V3WAsnZSRPiuW8d4ovlR92I+aVWT2x38fYq0oFrbOHDG0nMyvPMevsWaGmD9c34oM5eXXzf57N7z
mABczFb8UaD0KGGNULK7uHc4S0+DA0I992SbdMIasgNv3fNNSTYSJZd44/RU3xXXKUx0WUkkk+uj
A/ixDhmcn2jSWTi9uD3p5u1/W5EsQU0KVuw2/peHbuHxbF0kFchjU4tBlGQOHx4HQk8GQd5K+3Aw
kW/AzMvaXL0uwUgXpGtkB8djcQztftjxuuf0xXwrWIKdZvE64LKcFcs6392f24wYXCvhvCt0fipz
s7JdH35dknuS0nFWwoDZVQUbfj3Wutwjui25d7oOpYgst7x9fJunLgHm005omdMl3e2sRQc13MUc
OSUJB0tyUdX6Zt5NbTeM482Hwjjp2bN/sK/B6YIQxmyrzeA7MnGPwa583uqutJiQE4bv/oX05JWP
BuejY/EVkcTUVbB5g/dLVKRQ56MUFnvioSWRF46tIIXmiXa9Vw6IAJ5AitZT33oqtk8eNy1Ry9aA
ksREdhKnxsgIeEm7wbs1wKJOMYiOoVNJpy12G+tzu28+MBFJpat56PyP2FfOAQT/UFPGtOUZ3qTP
KGbJuJ9LvUr6fFo/egU+/Fy7gHW9A5qzPhxI+14jPkXiHdTwxnGCb6qrcxgTMFvU7ZihmKse0geV
YtSJEeE20tqYxcEhuexipyEn+9lftJHvuLCFaYlowKk72X42Nr1hK7O27pEtSsfWUBgxRp7CNR52
O5HZDDtnhATzKqkM0BzUbeHJuqi8cSZFjMyFFb+meolOxuj1+1HTrRLQArEdgoddjhTXdR918AsG
GHC2+m9Lh7nuOZfH29Yl2aM9yGVQZDELU8fNjUUb2GA5or63niiiH3zTpuFcA8TC5P2C3110PGAM
1LCxGIzAlLn1/8PuN30WkOnSMbrpScvySSlXQjYouBhpD6bgGA1STnFPSKDkjK1F7Qvh0B3lYbX7
Ubn5yGZjIuqN0nLERpuHkg3ZZ+CEBanT+PZxCU+yhnCxfbBe3Hr42aF2+f931GctUy0cJCBscGbg
zQOTRaJ9AkNaQy8Dq/1pqc6pTH8aAxxtJ5MVIqAwbo6L9WbEro8YbOOkZrnGxLF6whN5YDDvvhGd
Onr443IAmEzeVxLOMMl992ekJHYRTTFGjqRgsdpLRzl+R80Ykat0PnOc0IddzO6bob39kQ9bVqX5
NE8Nn3tMlRiLdQZUGyuDvpwBzBFG1o7sMB8UyQs7vs+TylovIShSl3Goh8Fqu1yrxd6UdI8oa+XL
OssdN8nz3b8U0faLobbk0sCZm7x3yaQJumFUObjL2gxfxAuxB4hO/GHUVVhGPJzf3pXbYCiacwuW
uftSelIsj9SgYS9CqAtgwLDSjSDkhePwnDn4NBNx/8aiz/MThDitHEJo9HSFeXtO+952s2bH3vqK
GxrlDSd6pfesHfPji/aIAy6VfEt86MovgZOMGB+19mWCSGNVLPWA5mt5jmRz2/2SHEHNwCfCh0R8
qk/LJav5tUW4G5R3wLc1lNaCmUOsC7uQ4OhFO4jiIcqPdHLB2R/LTVnRU7by4M6u9FBsl71NKcJJ
xv4T/SjfyxEfyIKnqwZ1pwPtkvkKOY9yND9P3iqoJW9Xa2i6h9cWvWnXCDjRIJIknl7SWWpCmPwb
WHuUibs720qIBsw+KFiHbDCoBc7CTMlufJqW3rEdPG06KvsRMs13CJOyjMYUHVc3Jwu2UYbKQfHD
q0TQ2etrNLrYalxWz5jrXIU1xv1KS/c5OEhR6HnHYR4abpbsydREQadReau+qhjKHtjcezleCOQ8
ldbFyzf0WyAP8TQ/tlosmM/MNBpeUpTrKCNrdd44D/pJwuWEmEXpx05+eWwZtXoqVtGFz5sn26Gn
/adLl1R6aYkHwWsqZCD3dJ2pZQeuIa77w21Oc4EK8mGsDEz9+6MBWwjcZAqZnPOmAR98pUdJfagF
0ikGfBw7/1TTJDYXzrNYiH3YcoPKWI5AxUXUtWTylMns74F6IEhIx/mgfIaDRsUsEySpq4KJPL+t
fuLoWENh8apBNgoV9KltVqf473pyMVxadxvkNVM0Z5Qg/W2G13QNOflHIWqTSxx3IY/ecpy0yCQv
sw6X8A3h49rPNsfNuXBB5cRZ7huzYeWE+lmshMeJHDGOVGs5afQpj1S4ABLY3VexK82164IGUSHJ
0v2KYh6oDeqQvpb3xkSEWBVL4/A43idEPFsNRVCe8Bqu8LMJj+i2fJEPfL6V+eH5xzYjfP1ZsaWX
hHf32tYHccV1ANfxTTYioGg5CqoEdtYD6VJvahocf3RSteLKZdUxh/YI0gLXm9MtfEbe8Uiq0eK2
/2PfdhI+mqQG2o+Jw+eahGftz7xCrNwn7HmVQZv8Sf5EYmE4n3hk6vwyXGqkII55ma0TvMqTjwyC
5hQ/oyvN+58SNtjMQS08kGKzl3CBwN8Ll7qY1wdrerbieEPc4je/Mwa9zv2LweWdqgu2HS2XHldz
rJSbtZC82k/2mNpqVwRzoVoy+Wz8GKZ5+0GA2MGQwyDzu9SyJKF454uEs6Pq1unS5WBrZN6jxPP3
VMhZqn57HgeVcxjulMF/vysL/80p/h8CsC+itGk1lK9A2LNDNmkiYOilVEEE9e/hJe1a81iG+njA
uIBdQyGpAx5pk+StDpU66tUQ2fUsuVHQN/la04yeOh8+9KJXnH/tE4FBVa55Bz6mLQV7f96Ohw8l
wU+qF6VALIqDN6atXo5HTPx3fofBBRUVE8AGMK0SDa2EYzq5GK7Ifl5ehRNKSTnvxPytbT6DeYRj
KT79Exh22lZSVrFGbvVGQvNJ22AfrQK92xB45mOU5Smk2Zi1s/jHw7ZIIv+mW/Gsf55S3ZKZ/t6n
3TDwsaTcaa/RJV23rznIdJIQIHshFBJ8i4U2lDBEPIzWWvYMraD7Nl0b5TD6Lx3dxTbMEF2ig+ls
wzUNDBBsV2FazofjfmawvqUdrOe+l+u8q1vJVlPrAjj69Rhw3xhwoF+Lsp/C9tQuJuXbNXQ3wwjx
T6bBQWnYJP3id2tnDlUPcPmK3oIQcbdC91Y2pze2cCZBetvC7BdflmKAlVJUPSTq53Noe2oKgO0f
3inhnGaGkafHVNEc1FCvztTJGfASS/JzGDp4vmxOyLTs10VgLUoQ9FEBILP2ogv6Ivt61ynG6fpv
1zh8e/mPROYwtgfhhofiXpnI7b/O63e4NxprFTmd8OMmTvY5yanNOFEMt/6DMOa7mfHMu24nxVZQ
hvLTKc69mwlmSFM+f29ptSSVn/Vs8OnJbC0pfLVI2ihJf7uDl89ugiSE2GVdWN0hP4aMkXl0pO8J
GpROJ83Tn/KuhLcpIswotcZmkyp3D9B6rx4Qa7h2GUK8rCZwCAHjckn/pZIhVSRuFEQZKWh1FIaP
uR8av4wM757jA+6NL/kV5gYU4H2CcHtdWw4aqdEDB9AYEstO2IItF4qaqonIFzdoh6jqOyvj3Ono
aoFtHIWzkMNntWVNtihmzMuCGvuqhYtEBSK/CTurhlGy7Qsk5znxD8OO/ECpUnrF1wWBUXgeDaik
Ixj4IykdE6+AD0S2pny4xPWst+tBOiKboqsFtDDaIOCTG5tZZdVGvDNQtslCOWdBptGNhyLMFZIp
9MNTshJUe3Fmz/PMIj3rRlfYyDPt5fjBf8MQwfU7vkZZYmpqdJzfrpyCtl4V21SGRkmd2Fq4vs8N
QqwTir3i2lyS6DbuTgR0I3585Lo7MzvTbzZ0GpVenbwuFs7caLfCVX/oOvxyx1NCJeP0XnKpWQKr
/s/u84uUgfQmXBDPr1MtBzvc+86C4mG8zRDr2h2S1mhxZyqTIhCnLaLP+ArzDOiHh/2xRBfFc0S8
yJkYv2PSJiQ918sar/PJ/D2/SSeAmeUxmw0RzLnBvedhgfsVQQIIQU0nnltvNRj5ee3UG4mBMZHO
GLbfW6/VUsNkzHabnzJz85Q03gPGPePbAtTkZm77uz2SosNFFmhQDpJ/NECeCb7A4Xwt/iKpAezc
OsUA/YeyeXttWTeA+s3Mhjz6u1Hikebvzqy7NP6Y7caYfTWtVXA8OZHLnekAnEcaH0sss0huVx4H
7Bf/zudCfVyl6M/p5stLdqBrItqvD3P39DXrSx60i2fXPvhlBd91SBjEFjFrrApEdN5EE/1nmeTB
WMzWcGPHAHizIHRg2SzW6qQIGn4UmvqA6IFydtVzw/+ZZOrfzST9IGaB19uE5ywY+MRkl+AbdiE6
TCnfwRRijesPSzFv/WcSY++bAsl7S5agfi0P4A2COaPOYdLMTqOmgG2GrfHmRIrEwHRT68LcRzA6
0aWtUfoQrBo1dZkVCBCSr3au5jnUhT2dm9vIQVUK9CHs0E05fQFJGNloyVZE4pMG+cP67k5Q9Gq/
YasDhScDcuObIatMVsfNpkPNBmdhQxQ6g4qdyx5f+7r5eiPms9sCQkeYiZ8c8K943xoahYj+VRyE
6Om3pSxZVexFR42G9a1e3RouPZEOX++z7wF79v1wY0xqmS1hi1w4hzgfWGj0QtVh/+j8/R/4Ajnc
R6OYt5onmTiiqICUdbUy3EOe8zrNNdAsg2VBjk0wpERmMPTWU+Ky4FiEGIUQn+D1cJB9HG+FWYHJ
W5cpQ9XT7+IB1VtRg2XPhJlyHHpiBc60SKcuYuM9IsDe117Q4hHmmlos1WKyuBFEzbODt9arjw48
XOJ/7ixB5N0PqIHloLNcTCY16RN/D2+yJ4rw0nsNk2Ht0fFAWgeva/2TFA4rYrzhhFmzmFOXsfX8
8NpVBfhn/ylF/1ohf2r8MW6qWs/e0rxVZDpRP6pPeKcMzBBlj2JeAwpdM7dwERhnc06gwGNRWjwa
sgy5nRjUyGjw63CdPF/ZwY5vbmI41h3fTh/ucsmZc3nWTO/+wwHQLvFMeOitLWxRWwGbl4VJWSZ6
YNR1UVv3iAUtVrSXj9AS/ajV/JsUldYhpNdf+pMh4oh3KJkwWKuDVaXFNdicSAbbzaC3bqI+mZOp
UzsPgDKiJtn+WvR5iqEjM3pnIYL0Lnyx8OHfWPYTgkjkV1wuxYvP4s4/cF8YiGf40Gjp4KKKYc+p
OcwkzaVxd8wqV2bZCUh9VPt5afTg0nh8M0+NcxSnD7o4JCKcLys2FxF016ZVFbWW8AMu/poHsZ0+
ijgvSN3W7qAyLl+7tMAzNqovGfahCubd1KFjX0+d6l2KQUiNhh6frMUxUeJ+GwSO7pRInnfiPKmT
v45qcnoLj/RBAmAhMs5D9xpfgQfZiaTxoqKcG1fkfk5NiyF3CQWvKGYGtXDIG3kcZyRUatXZB60q
+EI64Cu76gXdiXNwnz8sfm8DFLB7zQ9Njvwbr+ucdY+MSy4+ZzOZIlJfAZUtCi+IKc0mtFXcBOyn
N4e8tw2xA3+9VjlL9LY2j4Y1aI5RuED8e7bUtkTdFj1BriXt1gVUMSJEKObrrpd5aO7sHCpkd1Xy
0vk7vpBE8I3pvhw68Q03f8ES8tOcLJa4XT+BhmKfGapy6172spY/2YgACT8++TmIOyBHo1ryntks
tPFYgeEewsDo9VbP3FiJeuU38Qe8JlP02a3S16T4XvRT/f1lsrxlJgAz9Pgyf6mSoW7P3SnpbPbG
6OFA1vj4EDif8WF9Fgy344d3EF6ujki+gYVo+pgirlJu6WgJLU62mfaSo0ep3y4mh+pTRpHcoKCI
/4PMH1OicwHFwcOIgs3etrBwhH3lenOIBPhlkkzysSBJFQao1qVonnekPHlUpKe3SOGVXgETvJ3s
NnLn2qKO+TwY6PX88Q35UMDkaBZWCNrq4Aa/HJHM1FsJc8z1FpkXCnAnAX57fKlGEfuQwm1IqoGB
q+HUNMShiMySTkTCEjMYY4wfvVUtJsD00SaF/2fwb9wRjMi6OOL9KYDzHoJTE4C0YjFsw0A2T9/6
cAw9hZS8wK628XUAfVZJ2cnSvDH85/gYSZwRCuEW0GZ6wJUjqdhM+SEyk12iCkG+dExRRiwN/tds
oDdivQi+zm4pIaO6LBSCJkW0617pYBsLO6zk2KD/czqyAVHJGPh9H7rG2bO5o2mDPyRDXllvk6td
PIZlAvcvgRyGNnYRSrQa5Auh/WJ/hnHj3H2nxQmdxkDmZJfX3RFRupPEtStAavQc28KxmqGkNLM7
vP9dFGZa6aEvtRQmwnl2CpqbNKfZmEUi4MfIJOOpPk+tUOpH9joI6gGMYG0xfkaetthA3ZfwRIHU
zIfRNhXzneAfcFKLw+hqlvyRyvmE6t46hiSz35EZvs9VWttMc8uzUU2zpAbvK6hAJfOwKrv1+QjR
m1/ek9ZOuajRTcka0gb1fhYg6sRIyXV6ZU8KO3oNsd73lFo7TR6kgd6UXmgOV0dEDdBgDocKes2o
dr9k+DjWB7et/qbR0fxMtRZLT7pR6R8vv+p3by9qXG20qdW+BmxDypnVda0OkNeHK07Qunf4OHTM
3f1mNXm+XqK8XvPsd+NklgI/U6hXmI2JnRr7YTLIqrj3MtH1LnanameAuTnMx+mxWcQhe3/1c6RF
ZZv3oVHBBo85nQ9A/tGazQnDaYiqfHKev+N10Obft7/lfOnMssiH5Qhp5RUmAeEnWq8liMaeLs+9
Z8AAU5bAUGFMMQLTUDRA/hB2MFOXF53zZZ8v3QXOwe9m/95Ru8lZY57cjZSsRN12DbYV//zI/3nO
GBZzWl+8dLhp7DW5HVFA9vGZqG6Kc8MnU1uYtH4f/hSxQrlKkrw2o0b9IwgExhO+xISQj5x6s58N
y3v5z8scZ95zUYJxF/LX7xDnPjl+wU+Yifq/QPRY5YTqprOQCIH3fzKHIO/F/jd6JBUaAvD/gr43
OzrVigeACIW1wOSbaGCDYLCk6Eam1GTkih73Sm9KUTgrf9x/qkx/Qa5QtTgW9F81axpW1ifnEapm
ebijlxROMpmz+1MI4q0bBFjfSt2o3D28VJmiGltEuDMBoNLq3hexTNJty2vm/W5oRfu+4XU0d5cQ
0S44Bn0dpijJ2Brz77ysFd8rULQHaTfRadOaVIoLEI2CPAeqXx+8SG9nzUHU5Kd9ppoF8kwn6vYN
ga41iSInJ4BjaU0WYDE0HXmltYIFIGtp0D0a6LcQcJdlPuHJeqVfJNqW00y6QmfsPlwWifg223sX
PA4WeTYuUOyWMor3daZspsQu23exyjOQuuiTDjs/7LWL1/V9Tsy2bQ5UU3DC568oyINxSkBVkyGh
1HrrlfPE9oF6rc6JIao0BhuRcUQm01B9cGpqirq1yRmOKxXNLkt51a07WLRSaMjuVZ8FS0ILJNjc
TrCwE4tDiFYgLXXa0skJe3xE7udHvU8bsxL6cxdk1AT7ILCfxMbbGsFzywvb8bY01UlDtphK0MNW
4z4qQXX21IiqCwmzIsOjYBiiL+uPD4qfsRk4SR+asTDYLY40eGJOQeUPe3sK7GwUYeRz8TMedM6U
9MJl/IOS7INHLKQivGi7R5T1BST6YpS67+tznuf44+7mIJPP85n0pMqzoNZJXGdCLQZY6JtvdPmh
wn2hmDbNB6BJGQVt5RfIt9TkuYQ6XBDk/VktfguwA8CnXjnp2y3of4oxbaY7reKSS0d1MFHjfOQq
DhAsLcQ2fm82XChluwLPixHCX5u1ANhyvWFRITDiP33upo6LIU1OiAuPFvueHoy8pOEuI8iNi+rE
htbzRGKH0ilGvGkyPTwcaa7YkikdboaQnEHyr8msXt+SBJ46z7AJXLNqy8jqeGUU1JZj2k7A+JgU
cm1+nQSbg6vbqpfJN8FpjDHq9/Sp+TJ6rw3WE8WJGFhH5Voa81B6J5sMyfrU/P5Mr869VIer00sV
63fGFVqcDcy0uKWaDsi47XBuorLDD+RkwISnxfQkq9VJmcglsEjC1l0CRbAxAgV7kOrxBnu1A6TL
cJ++JIXQyh0uQuXrrkgz3X3yQ/4bpa0wDE8bx/IReAq+2MNlKVJbkF3+cKcpCuWNRkLB4Yg0UFvJ
Av4dMdhYZySIw+GkLHjNmyZVP6E6mP/ryf+smA5fUugJJfqxyykU67dAwBZGKlkmL8LV0azxB+pJ
/dSNRuiS3jC8vVYG7FxZToLpwF6DWLGUXX+eLzDsmhAPiqWj1ryJ4kkjkrSlwvGMB1VI763jqPW+
xUC0B5xJg+aMBytNeWK5iai4QGhPUo47uqXPvAnTPpde/GSbvWGk5DhB2n1poW9JBQDKXe9wH775
1zsABNgPNRRf7zXeV5/jMc64hIZzyCGXOwoJah/KWCI8Kj85hV5BxKz4cAJR8JjHotMGFiArGVC4
bMVKBprWsbj0vnWCB0Rd/nZJEE6H8DDFiuoPGDqqxxIJCsg+aKwpAQlr1NYr6X0ElraemHpIrxH2
mM8OwLhoGjHp5v9Jld8nDN7H8ijRJnCILvviLV52ObzcWBkZpLNtAm2Cx8q+zbjES/1DX7A7oIoV
jKw2AXFcx2dbrvd9nrNoA/ekS9HuT+D4xSwH81nSuhrjpdNQy6B0BmpJ5gGZRvMTum/73UN5UZSM
CJ+EFUT3uNSIZ7imhgu0QVs3R72Rzb+titmee2XL9cKjHDuOb5NUrWcXwvSr+EPA2ejOa2reG1G3
QdiHOEGiGUIflC+vLxDqSH1m8HNVS5T0GT7VvnuTsmSSnEICA/wpVzQwVL6PoUXtSk5wltlnOucy
H1n+fgFORSpihLs3vco9xkinRtPKjgt2QsIGrEQui6Nj2bK9kTnGCved6EdHRHh0jQeSCgD4GQ2P
VZCUl/yu0vxV+Yz7n/4xF8Mt93dfJajLZiUetjvmCuw+GddkaXSxFmxZYyoqpYTV8Z+J9kulrJ10
EF8UuOxRoV0cXxvXy5tch+RHVgkE5ltZe3FB5cRE6vBGdEIf0xNMZugNlfqUM8XPTFrOUl1YE8tJ
/Y10IG+XTcQVfLZO6BuByE8+Z0RJGavcahPc7Zqd5oaVrYhqo8Hsd0yK8NVVzyiGKpOVNT+Rr99z
ImwYiqQDuu3HLCofaiZKA9DCqWEu2J+EZZ86gwkZUsk1lEt/zoP3OyN1UnHgMIbQ+lseTze1lAWo
2QY+zn/83OQZG4ro8bPo3IBflZYyJ+My9pXB3eygd3CxzvYZynU4eSbf+/JRaeICKPFxwn8L0cxV
u0mRiXqKrqTvfJnnC90MHmRAvToRTzQilZA86FrjZaBgN/ul8sc+ZC402TsLqkeUg3ieTpm5O+zQ
9tmjWH9Te+TWyjvn/UnmyeHlAyx3PmLNzjiFhzettVjIP8kPppvk5NFZsMnC4BQvaQ2NS8Kbr522
oRhPoHbk7TfEicmvk3FLcXuXirk7MfPhjm4yWB0f3l86Sh2GVCTC/RqdNB+hEKeq5p0EsVBxMA47
OW3ulgq+KJFu9k35MRTOeHvoxCpGC5d6YoDLmc2KpI3vRmLk9fEaWoufl74KYwnmhPEQTNXZUTE6
vEyMkIuJsAtSD4CHFbwx0nrWgxlQZPXmAypcJrfOYpwvzoGgGsez/3afzbmdki/WrnjenfPg7WOX
fhILo9AVa6dOGwGiWxdzseg0bR2xyWl8yMCWQoqTpO24Xqbf9kPhvIoWLEtq3yHrYtckQvRVsK2i
p0idLaZgJRarmX2uRuF8NPk+2qb6QS4DQMo76EQjRJoVbn47sHJjefSaEOkFAEdMr4o1P7jwztT4
XgTLuO4TDhC54SMR/mb0+5RFNGBE0rlVvW2XV40+Zugg7iYjT47ScGvMHAg5z1yK2ztuRSf1FQgl
5uJ4s6CRHD5fdmY4iYYE236HgA9Nujk3BA2BTagYWoqylqXNxIfXMRXzpuJ4c28fCL7HIGOzQS79
QMx5Izcs1oTN0Jgjc/VbXTKf8j9vGQAGJW33z59j7EPz69s6agvjCWRH5629NVDQMdCfxvuZAdQQ
NJG7ZbGD6PLkXHtl3XBQ2AdNpwnHXC3PqflOLYzILacYMPAcxJNixUpmFn/phETw/OT8AeCL3jhN
U2xPBzgG4jB2AKu6kGeTcLjhUJLjVoW3NqhBHj0nUR79tfC49U1AA6HEHQDVEfIK5RK5LKjqE2FH
TDr8c165D5eggX6qRP7lI9xUU2YrIq8V2JLjhEwKfBgqb2NLSQVxksE1fGUGeSkNN5I6CDIHMA8v
NY5KX81YJHLttfcT/4oJ9+kYdsyGUnmJIqILRtpMPZnlUPUFHfn6qDUtMJoRFmwgUi2vvg74YNGy
eZwN6+zIlyorWTPZbTFk2473KKK/sgVq5GLMwS6rXfQ36/+bBvwxjkkjBSxw/XF1qetcXBL2lrJv
l5LWIAvy2yADO1SJw/iKeHeHwFocBl3TA5vipV72hOh7VNtuwjprpcnBieO4WPf49+LmF2eFCaDA
io0HL1lUJ3YvHLJhVSo9nYMfOpWSmqD6CUAh0Hp4AB7sfwLDO/092OHLnbAmtSB23IJvAhqGgGzU
qtkA/pUWTGUZ0iv/bEVhqu/CuFMrnzUniNQ8YVbzDOkeC5BqekrbxfdO6pvx5moeEBxic82aS3M9
5GCswdq6LWz7VCQXFhRo4nn1ot+gC9sGSxEZGrZoXolHzgIWxSjyDWoCvivm9rY8vEKcrxd2nE+H
b8W9FjGG97KsukqfE96zDGu9Y4RwH/xmY3Z8iT0ZVZdZvH1FSM3dkRNHxpSNay7t4EL6j/B9fDIy
L/x1233hXjE2X0x8c6mn2MHYXjdITho8/KIvUz1rj+lFEKeBjP29illrb0up32zRhWc55TOuzLDl
LLUxoUZtWnqufYLk07HAdyhY5y3QQ//rL8yi6iXL4Rwd9tKS77HQMeqezs5loPTbyJ3ow6LxhtTZ
CVpePIPR+vZnTn9ek2elmYT1lWTxUevf5lVnKWe5gWgueO4FcQmeNc4QwLq/pS1dhWr7qXaMnL1d
GaDV1CGsyXWHwBwZXgTffEQ8cqGP8EByL9u8qIMWplbAYU7Nmill9VFRYtAMLrxOPOSaYFRI51QX
3sJAQn0AiomNCzMZaYUP86f2/rX+46i0tzqg46HyE3loOb+jqz3yTHHrkR0NiUVP4pNiSCC4Q80f
Pa/NC1B3TSmc+FohyOVtBjtt50V2Npxj7/hNd36Hs3l8if/x9sQjLdFl39IzFX/YHbYnvm6LU4Fi
0CKgnRNd8H18qDWDylMLCMT1D6wcWNyK7Xq2TYb73gk+BD5WAQIiIomepQGrxuCOuR6JaaVyWMQN
4IPjs5i58a8VVVoBdSnnQzwbdzkcLBd9MaIc5lIMkSskArzriIOC3b2sGF8+L33oESosHb/tE1Dt
PAgr5as3lMlRzzUx+UWncOT7dAtrg2mAlSu5d1QfGZGsN9l2Vlg8zOFHwaL6+x38WkODh7XNVkUD
USmfxbKLDy0/XCt8DmY7B3iEln+UgwCpr9XEqX1xZeRO5Tkrr3L7yYY8dyVUJxPA3zJzIWXMdC/8
KGbWoXqQlg5oyfxPCDnsVlmMihjRUrlebeYvmF6JtQ7FXW+Q3DS6Xs66w9GUDYBXmajGtGvcNRtQ
a3swdWOG3xBNuQpSdPFS6Hg8NPr+reJImAGVlAB8Z4cIKNxXsICgkOnEdXvebUltvFSqgE/jkD7O
gDmyQjirw8DQM+fPuTZdbFBIub5xI9eeh7Hwtka2uonf6GnPcz97qknJny8/FW0YLiA4Ym8hn9Jm
fzk1V6sRT5k0Jg1FJe96p9vxSlm0KVqP8xhA2A2YXN7x23imfp9iMLg6K5RvRHB2zPHn5J+FBgh6
jTEtkC5WBTubJcXqJpw/6uXXd31slYR9UTkLhc5vRUGJLKP0ZFOpwT3MfXA3VuVyNeg5+gMgtz/S
odk4iTAwWE3tH1nlRqmtEUB+EDDe4nCxB1kMHp2gIGLCNdZGEkzLnRBprDNGin8zk0vwYQ91ACN9
6gKVbKs8AWH2qWASMWxOKrEUhRrH/EPk586oq2o/UfZgFsr6eJtNmjERNN+gW/Du5L5fiRH/wrBP
UQog8e++4tgWrQ0dWozUU4J5pQMzbqDrM+W43X62TuKIRSaiWiQI0ZrKBgjkGLNuWsXUu4GRyNGM
8nzyXfTivw5KdTtLnTyw/mCSyQ8dt0adviBtTwGJE8nDQ8Sq0hQU466H3oIYUysqgDiFUTGaswzO
JLTGWFBcztSVJNONk/RF8W0QJ9BXP7yjSQmTL3mx5fQbNJ0rUoBad3/x6xMDEiDdQ3P85nkO33sd
Lr74P+Y/kAq0RIsA+psefAxpKUJyND6ukqSH9RkdeH9k5w3g9700KUaki9/2WiNXPYeg7+ymQJVQ
tKydG24Fg2yLxDYc+jTd89tuVnptZcuIjUmgFyTozJHiyExy6cXLzUumDpB0ENYwt0AGGVgseWSN
yaBZz9pGZhyompg3AYVjvKCxRKJcYOIJQ7sifaoUWy42XnYdtGNsU7z6Ck9awCkjLrnDiOOWqGqz
UFjHjKk3lK8Pd8wqBEXM8KtsZGnWNuX23i0xj1qLRxuxQTVxawcvN72GbloqD/saDtNoBQxi3wg2
6CvLZ+lVRMOjmFRF+tKFKRIhDQhFQ2GYVrysoAp0Qzph00owYcsmXIEqVOHVeHcqrHBsegqOUASg
GZBPADk2DYqzqfDM7AachOTmW88zLUJg7CtXaoNpRSus6A0ACBD+9mRmwrn127S0HJTy/Chr0BIQ
EVMNiaBFtK2/UF0Ytfq6xcnC6UiCPZWuIefEg2YbAYnaW/7Gqwd2OXbgXQRmx7NsOwOYDEQyYHpn
4gHPoyTGUaL8g5ejG4BD6x4hl5OtPj+P5MsPaec6zn8kL3YLg+b48lxvlLSjSwtyaubSOHG2koNu
/BuUiPTcGbz0FN3+fpBMTI0ZA0kvx5JkcVZ1UUG4XloenfQtjaQFeHb+lCj1Ag7JxZcUqFBEl31c
HrezByaCPtmvnYGjqKkd21MgKpsf7SjsDLjUZrIa9xuLRcShbgqvg2srO4Br7tcJ0A7aW7y5jff2
e67f4n1UW9937gnos6OCbEERkm6UXJWBt6aiC5OfteTN2biJ+6CYAbtdL+tCDIErxWqKRoywDC2v
A8jsSqed7X7DtYKQd7PKu/WB9+5CtuCPuddrhVRzaO0Je8sASL5MM15IGqEqvgtSyN369g9+p9cg
ORHufUvrDxOlApwCi6ItdDADAwU4303M+su0ae1baouiABrcHdrf7uvVkVzjkrcE5mDJsAADBOH2
TwQku+CZ7ujwOC+DPVItvtFfu5xrzrITn5OsliwoQMvPX7F3zm9SiD/D8EY79YehxHd6RNr5wxed
e8N5nsl9DcL/TwWZ6VBhSREvOzkkgIO4kNK/qIKGg0QPgxWiy+Q1ArTG9Odp46b7H4TqY5MBVR08
XvuZW0/ylnpiyIC5kK+jbtbfP6qq1WQAg1+GmYogu/HkUdzd7XYP99SUZ6Pw4u5scDzw1JdArEUj
V7dzgdRJ4iTAU2bI0IEwEVDjjQVLiw9yFU+hcQ6y2lc/JYSsv1GqZj23vUei7r1hlosahWdvugXK
tAqZzyAVgLHzxX4uPdeitETbd5AROmZf8AjMMiqkzCt0ZvKi1Oc+A/dXsFQsheBmXsFeFSpR/qMI
wYoNaEbFvGAyufZlJrk8PWOzFk5a5I/k3CTIwIDj9fkCYxRNk/n6RL/pqoE3L2n67OdQxbT7cguv
2PxxhaqE44E+dXM9qurE35BCSLp4MA5ngdZ4P9akdaG4a3tbPkV0KQHR7+puIdu8XM03S6REYQsD
fWhqEOlv/P6qZJYj4+H2/WLHrHJS+zw97wxlc8OXbozi6qfkc8iq1GxC23Gl+UEFGR5ChdDb85kw
aWh/V4540qXGLp72uOJimW90A/hVjWRWeFBI5zezRYGNR+nHV4QLDyrx9DgVJt/Y+AUztprDS/Gc
1ZFQt5Plbn4GE/MYKkhYWYPsg07qJ7aGMGqiYNowP5lzDYVmhFPP6K0or4LeMTLlZwuXrIW6e7mV
VzK4RWzjC1EwoYaGFAXjGzTvnT4sjSEV/UrEUq1wg/ph+UK3k9slZLY+AdHd2fQG/mzYUeSq8jV7
WHjsfupa/LQUkauHZ/T1SPUIxPmK+0HgKxjhQimmJKsxxO3OpXNY566+YnItzoAVTknTQJfjRHIU
WO+hQuXlIxmCd5BV4SqgressgbB69o5v42tPM0ienCQ82KNSSFxoDc/Qybeu7e6B9gKMhxEJT9iB
A44c3PbCJxla1XjTf2EVwoYvKcMKgwmXH6tpopnvpc4zNXjdhpftkyZV92RRmoFITJcYLvMKP7CL
0JESRHRlJGOgwR/orVNt9Q+I/iAOlORB8XyV1wtPNMEwJnGZsneFaPsNUPOctL+jnzFOcbgmw4nc
oUXpormwb+nUG0OEWjgXCwoBDOgfWuJwb9ebRYdbtvbdjPR3LsE9nqHKkLYBNRBsIqLC5oyilN2H
HZlRSelygd5n018CpEzqAUubUmrBg4JChWPUrjK+Nmy1YpUtfv/ekVZnfF0FX4Z6zEtPA/a2Xh33
HiQhCAeHFArwlfg6Y0eyClhP09xmb4KFl0GWW1kS02kCSpKe695TQxWP4RBICtZyuIF6IMg2UNgv
Iqyv4L3vVyjN6deGFSKpfpbadzIEXDW/+Gww5uY/7E8s3nb20AjDa2l716syMawtjiy7wgKjEjWM
yvzPXAdzScuNSc2TJl5TqwpjXykLu/oSU8EzaO7wdZXF5XmXJHTkA9kFVfDBWJc11bzeTTu9Q+Md
bXA9BYvvA7JVcEQM9JHPhQZtQlF2ENNwsBb+WHAwidB3TA6VQr9Xwj9QEHqbkKE2nHZjt8V8z0ya
T3SgsS/QSHClZPpZdXW2oSjNBxFZ2Tvd60/BkFnL87kS1+MO8MJuM4QK32OPhsSwkJ4v8AWXxF0v
sClEZwcqXD1wbix7Io5wjbLRpJopJgTZFNi7Hxhm2wtT2GOfyBBK7p78WlCj/JO61Ty8VnIs2kYp
gni3pMxFeisuNiTH+2t11EZ2WUZ+g5Smu1NVyNpLaP0PUICWCuPZZYs/9qYA+Iy4WCH/vl8rGB0i
bJpXRx+rTr3rNrAZvvbxz5Gsh6yVZ6OEwLBkRg8eNwdq5CV5EoAGhKRQ9JFpBHJS2g1YIQTuw/Zl
n0ifQ6Rep3u6PTDf4j2qlDuLEOATaDRrtgIAsibrc0HoRAUBWvcoXKKfKxdJSBHC4pgstRTcf01+
q3sM3fiKKtfEhCD8ogPyWlc7OYxOuJOBQMbE1ABHw0vWPPpMYhxzkde0hTL+G/4aBXuuf7Q+I/8b
i8QVPtZDqV2Ubd4Z5guPbTXlKNB/wzBueg5R2p25eTvv8BYPuqtbWmfltwFLwt2w8MUtflkiEOhg
Dj59I9KAtrcQ9d71y9fcgcfMtpvLzHvP6nGPuG6Umvx406PScENbGpgZ3dn+vfyCLo5Ioikz5O8h
TYS/ycnE3BBsoQpD7p4/v7botSPydFCnECr6VeFzIWluE1icyStEUdOyRnMVgZNtYJGeIUqLyly8
2aNL+XgjK1HX6//TnNCAr6mPy3GXjc16l+L7JtKgkQKxC8MeoWCTIEXYttCo+VIlOQmzvw9/M964
jaqQwqMHnhWu1SEEk/tsR7++B6ASj5hNoUipXNiMwaABYQRdiiXQacfkeptV5mI0qIqygLg7Rfsz
uk2kpMLpvY9KXrE57YM1qvWwKnSvmghVb0WWneePdfMmmUxLSiOc5FMpBmeC7kX5zpktPUi6MED8
Te7Mc5LJUS6YVR4QJ8PpW9Olm0v3LogG4vMcmMUlnqIV5wZp+5Mpsbch6bWvfsZcrVJYtxvTTw9k
3vm8MaT1K8NgnoMfskrjWdxoQpgUrHmFVSi7RWoBQAwKMDMalfXMFaRwB7DII5aWwaF5OUg0dZVx
9d96mK7d2wAWyuMKeSZoPXF8HEkgMs6nq2ywdzmslo0xHrsVzKZF9DWQXJiS7q4K2gX+MhIa+liO
8xl3zkI9hP4QVcpERuYfRicnYqzTxjCl5HSy3eyhIhpzxLuuPKnXUS8nLD1otIcAHBw3Q54/y5u6
QNkPUo1dPC71LCQsckyZ5+24xkwWztqOE6IWQV3uG0JoGhd6gx7MoBucYXpl427lNuBFvwYYJE5T
sLgzi1Ylw2ZMYzqTvH4lfX4mdT5JGR3/7412QImzhlAxG2fNEkAcfVZWleBVlg3y9ActP1EPrfRv
Bm/ABKyLtM1kv4icK+Eved3047UUOSVXvmZwhS2puAvz7beFsrB8h0+C0FoOV2CpoYAZG7ze7RfU
Q/b/HHkQaa9X+px7yF/l+TxsPs6RxC8iVMBZk+nGLdVytOG/f0qVXskeqgbWmW0p7q47X/uQaIoS
JorMaC/0NPGutyV8clumRh7uDbk/egObg2oRECaorF4hXRH3onyxep51Sg2Mp9faY2ncnN2a+WN9
JiFWbqODA+8+/tytKm3W9LCgPtT5OVQACVxa1jrKZ+DM6VZu6JbfvUTndzmvsKbM1DgOQj0mYTpZ
MHAsX2WP4Esn0mHXHFfi1YeHtg4oqOyZ32CVCB9f9RKTTk/Zvc64p8EuHmFMFsnFnKGtFNfUzBzD
3v2QI2zu4ZTtXQozgwbgA5DzUdAqfMiC+NQuJqSz7E66+Z1oezX6bNUUQqpC7fBbebOaVe9hIXSU
RabQQrW+2MJUfgpR2NNdiysKRmMUgf3rCczbT6jGhB1UpV6iTUOStsb0826qOqvJU+beSKl0vv58
cODtC6rqesBnNaa3FgG1Iq9lQ3+j9kMrTNskpKve9qQ3TSNyMbmNuGi2XkryO7jLSNi2TFi3+rmq
yjDrsJ0QXDGQwmGPlLprZ9z2+22UTK0RtQwUIqf1BmjZ6WbgTGMS+WOmWjGdD2LTnSeNlJi3lb5b
jfwmImv3mOQZjAxW+eIFMt47VDVTbv4nnX1SA5zyGFb4lpz8uFWIogbghgVij5pc3HmPwwlpZIcj
Op0IULzn6CwOqIkEMvKixjNk2b4NJ2gs6q/TQkzBmeqR+bjdQ4kEeuo0pzftjuYZbOtx8GFgHuVm
ibLgrhdeSx+NYmuv2/Oq48zNjf8PEUWBxRYzXCNROw+w1DTO1NXqQIh9YCl6RQJDpWjCQOSxv2tF
BN1ddqZAtsD1dHYV7HUwgh+MrrBIih0XWkmUkdqcZ+JHr8szGsaxw3x2M8i1n2A2U2gPpM+eXz8T
SvRBx3RIQ6ZMASeTIMoet37bZagwrRBZmX3ioRzGxK4FNjJe+LzAkAM+u0iT1bn4pwprvNVfKiyw
iKB0B0nWAfbBv/KiJWdMimBrUwhZSVxQIE31Aynm5KB3LHzMcG5vS8F0I4aG+HtwOgR3QBZ4C7yC
U5xCT6M+Ih2urcGNdwVPSOBc5dMRdb+rqKUXQOQ0q+FLyesxOza5IhYXw4RqpwBk0PinaLui0PNR
5UimojDNSvzC+zegzr5wSjW0MHv1LnK28TQADceyaZ3WGIixYmWJQvTP2wAkjnauJECxQMzqM6aT
6Hp3j//nehDvvxueQG0+WEVFDe+pH+h5oYVgXh1Pm5b0c1VAjm8UeAJ2Ye6m5K1LjIvV4cMqt1Fq
8XLWeOTFGfOL/pFYya35P7G4IavdPVuXZPPv12AmB95Hod+Dx7Gt5zkkj/g6mMLtFGo4i0+dyioF
5pMV8ZUJKjz6lJORr+WTlMKgDbgt92ijUc38nMviCqROuwan7HR7QhJVWlVcXGBDIgserMn+6y4C
EjKIJsqVt2IqEAw0CFEXBulsA5tTV4fS6PlXPBjLI50a0OFnpayB46yYDYdR4v0ntc9mGgym6dM9
6HZKtSiTc6698zAQsCrSNC0E/PKgtnCcLOE4P6TQcRzSRvTVPyP12jMG+staHn4qq0NuTC9O7172
vRNqXW45+c2HMsOMeZbqZqmCndxBz0M3zLBje7l9VCQBCa7pAg2R4CPaLt9HQwEAB3O5f5b2Eidz
/qQLppzMi2aOO0NQlHHxdO/CDpabm16YzA9fMfFJypq6G/hRKeQh+Wisx8wQv2ycbTge9CCDg1qk
RFWG7PlxQw9Njs84pylSus5Er0ipyRf+mNmv12yraM+Ah1PgFifvY533LdJN0JCWJY3G8uxMdP/Z
jEvzc0l1VcZbfrp6YdcpKMn3olTAkx/8HhEtW78vFs6mdDqMHHefsR6ClVB/GbkW+e7LyMmllA8O
XY2lKWlR0XE30M3rYYoQ5FZv5lH83Uh13L1eWxKCLvUs1zCq0x4yXuBZqaSiuWouSAyo3pEK7DmT
dAZo8vCa3EhDIS4QsxGlUJh8vdnHWMqjBEyBLCQUrFVCUAc/3KYyeZwOo873pqRh9Jdk+gmDk+v6
CY8aFz0W67GEq5+HvIFIALgiscn1qSmFBKvQBEtkIDgQrsTryDSIfEo/U6TZZD4/Mfd/mXU6YuRm
yR1rdmKol7CSutkSqzrt37uHdryryMEy2C31QINBHa8xQ7m6q9hDDV2LlxXlcUGht2Z8xkL/vOW+
swnqRAWG0z2HIaDJ5wFJ+KQN452fVQfBlOshBzgJGuqCZLFVzRYHKlS6nLmFM+l1I4cfvCgT+6Up
K54o1WZ98iHVIGMAY0GqxfY9ezq5aoRpDSHaTlSJSvaDC58Ajr+Ta4GiatAYES24L+Zk9MI4EugQ
N0FtAOU2k6easJWnGmsj1Aa5upfFkpIcSrEc8D/PuyWWOvV0gR1JQUxQsLRxm9P7a73MQqbm15PC
D/QvCSECe++kvpTg0KT7zo7S2e1KLrtkvtvktPnjSfUqORz1VHn86p9v+mGFihc7QTPMGAKjk2yu
3x6zzZX8YWQNS8XFEMm4sF1oQ6duDpylYz8OJz3PasAzSbbZ3mKSTC0qDAcyHyaSxFwrrzS5k3Hh
R0zmvqdL/ISDvq+xhGji1gGdtZGiFKPTjwtMzJANoFN1UPuC4/ykGHuMCmaObe2hTc4eRP5Tt/iL
JnphvYSziU55tuRv8DYnvA4yM9AtVO7iiUw+fg0jsOhvpDzgpJ87/SWMkfVwsn3z804a2wH9eaUO
qgizTj2n6rOcUqxU9rZkgnMNBC7sAPg7l+zjt8WbnJ3n9FOBMqGRMeToOmAj9jXEJpWnvdaWqrKL
cTcQ6B9MmCft5S631sCxVP5WtTXCY4p5VhtDThXV6qJVu6xxzkftLhGtRdnwzo6wgA2kYLdmomGi
3d4HhSTE5YQuE7nWeUHwGu0kt1Z7Ir0cf6knGRZAaHqC+xeLdd8fdQr3VKJDzSUeqEs6fa8NO6Ld
FCaztD7qkmWadmY8YeY3fhHzRm7kB2GJx+uK974mvmh034Wi+k+etfVuQ1u3srZdrtMntjiyvYUb
GC1Tid90fZlLzjNN/ro1/6506Mj60jZpUX+l0zKU9cI/KlURGgNQir/bAa8MNugAVO0APPL9W795
IbaCk1Sm1s0UG7ZUWZ+J7U/h+vFJFTbNNhvvoXZnEPuOrqhZigqqtbFAPuUNXOm8k1Cx/X8c5c0Q
d1ltCGDm/B7xtnrmt4brY+S+5+bQhu35Nt899UJFK7jh9zBbUkV0Q5gsiwsYgzJYvj7+xkspnTE1
Af2d1PVyoyoiro0NZRXhDpP620vNictR36R8mQPrGJXqw72vL5LCAoFoH++ogcasC5uM95fVRdGu
QcH/5lyILZJ8MOmJUpmOUSN6UaTYT4B14qp5/mYxv60soSsowm2oHNzsj/CC2Tdnqg2pElggTJ8x
zUKtNtn6JBrNjfY2xqY48HvM3tbH0GIiUIZ+uSjE4pz4SLWpuJfDohEVkPkm7nFKrkSZZmoJHyFG
q12BmPH6I2bqqwoV25OeYFNjzejrXsdi1BXUCyFZ94X2WSMr1IeCg33oNwXP0+TNrp6CuWJ8fvOt
Ehb6DviRZxSy9t+n2n/iOQZLpIbG0rDmKSz9Oh0U3robksH7DpcFHZBRRM+DsEVi73coH2jl6AO3
CHcFRx0vAoERaKYqwbkjh/vKsqoGNlL6G+z2dJoH1vSyTJGHsgb9jsCIQstlAbhpIVhkzg7Kp3xo
RQnrD0SAJZ/rEmcxG68A3mxnLMPeGGBCVdMRwu9RXwB6RHgYwyQk6C+/WUPiXGIaWeOtkO99zlnS
3sLJTIjKA640A3YV6Oke/1dA5Uaq7dSb+qUdwrN2vhWo5mcaususnen5TLxNk9K6u/mp9kF+0QtS
NlQaa5uBgVVgfoeluxUwTWQ6A2SYEpUJA9gF499fIqsmaacUHBg2MsFJagAQ/+mWBBY8t0wdnaLY
ljG5x/r3Qh27UTWn5ShmtqQwU+H7p9fLqhIS0BHjtwhQvLYccXBankTrFMJ/MEfq8ForCcrU1mti
xqmvp8UqDZGKSll9WbUbzBaJWciO8qTwwhbHF68qaaAeQP8O//EaTe6RGbET83yTvCdXpnOaMzZa
o+jzBAalGPXRIEnuqmuv/gF0+J8sg5p8eE9QytL3SO8FpMOL4cn+C0hQeM1KxHbnE67wH3O5cvkN
Lc7ac+bYJcYDLNpBZxBF6XYp+CYpkptifHViG7Y8FFmHJTq1QMxCDg4RKFVF2hKk3ftapvbgKmKn
KVCFMsZshBcFu9cb5RAT+7Ers69h0FwI3oIOdGPscBUjmFj6BxuyIhdtsswgLsLodhkfxSEALdOJ
BH5T22e5c8Trmgqp1D4ZyVq6bsou4cDgk0Py8T1OHcczgz2UAzuZKpLTbGen5yrP5mW48Tq/dKZH
bC/vQ98tIpZYc35UZyMgzPRchzkp1lGIzpxowW8YtAzXh270uBgmOLc0lpTHTT8ySzae5pFvEnIm
rwgrdJw/zrHKseU7sNS4nXJC6zN4qckfIX3YU11gzVluIOieP+42gL4W4lwKqmdzQByeuno19qla
+CPR0McTIBBF6n4AWoqs+O5xfztm7dLbWUmIzbfpJh/C+FSFslz2IhN0Vcfc5aLa20bDyYjuR3WS
DzeiiPgeUebdfawFxrQSXJ/JitYp4sGTf3e2X7EAuJLT5kCFRan5yRc4XlnD5QAyuGh0bNYeBHJ/
/FWl3j5bLXztZZo2lgH8CPbkXo+LovShXSpo82VDRsl3jJHmtyEUm4HLPt/JM/H0SrkXdA+NoHX8
qX508s+6qaHXtF8Di8jTjH5Ph8IH4ptkRA/TGdgkZNYJo0FRsEjN0Oa9IelyPKNU4XQUDKyeroR8
cEhaoaPAjY4FltWmRSqWKONUwUQV1T1fg+vy7Qi801xDX+Xi5tD4zd0AK7qR0zupx6hMVfezTiIU
uncwS4KHIditlzz7t3ZN/ma5dtWSsRN/4OBesoLlsR8VnUsHFJTWhEDbHvM1N7pohYu0nRPd9pfA
ziU+/kg2HDaqgB+Y4YhEexsmgAneJf4Y3YPfUVK1Y+JLGBfMbNetaRdk/wuLr2gGTv2a7x4SOaHJ
4x1CMYltvnDZK3HNJetOCGCdSCK4MrX1QlBqu+QXzz39exVsc4jqCywpEGEmFSOUPN5/ZUXKddyI
LrJGlGZMD4XYkXyCR7q+gq3ZZpvNJoI3TEmqmFjdwIMlwgYwY2BB73R2/9WWbfTwiXE2og9BMY5Q
aV6RvWWWVlfZbbglS6Z9KYF+cSMcA5BrO150OmNOxcp74G2XktUlisvzTYcCAobdjkjxQf6sQ/dS
HBrX2QuPXibnzySP4FEV4DK7rR1HG2UUkh2BVEd3kGVlI2C/fxYTG519BV4Vw4T7r2xb1kY0wNOh
ODgKF+SjPgi/QtK/QT9eTKabO3Waj1BluVdNEwjjXGNNNQM0oH0s9zJJZIytFWok6TQP4bl5tjOK
7a7poRXfGDJvDqvy0ZEpH4RJEdw0zp9NG8nBLDIL1id6xCuXBCx1xQyCLfTNbDw/92WMqkAVULNm
CZ81+5NhXEzY0b42qlCav04WgdFuZnBm2hZYqSZkQWwj9Wy3Dt+HXfrqSh0wD8smSBwA8UyxRqiB
7x8wrZwliXvsqGhNze8fjNzCcuSXzoXokPbwy9zmBbiZXMRC39aj1kB5Ck6IX0TKqUG8Ax35XTn5
/U6m9Bmvco5Wr6L2+TZpKnav1Ie92aJmZE/DJkfFW+T+EH19t/3I/Ke1x96/cCPDU7JtoFidALaL
6gdDh+9S4SCLMx7QsaB/uMofKSIeLA0Zjeary9erAJdFvi78ChgJrj39A0FzCWYrXxy5+KUpDJQl
pbt3+GSh0qxNt3YuTs8BRuPtk+cxKiMODD18MTuWxKfnDffHyF/XuWn+ZNLTCz3BdLwN1w96spD5
d0ozDLr9B+tXlf00SytJuwG9GrKqSzb7Oqq6cOg/Vec1y9teZGX4laRl0Xw1R4QNjPSy3KZyUZDD
0LnxWyHXKzdmwqJ0GgHdH+9utfT3FOWvqJzAjqUyddAs4r99oONseMh+ubQrKAK5uFg5cX6iZBnj
xVpSVjsy3pAGZH0jTKvyRtJUqwlBNc/6o0ZMB4dORmN8fr5i3QHIIEVAmmM9uyPSmfeCKz7/4Opq
maEZBfKScNb7Et25Kpdgob14AKxAAIzV2gDg2PY1Vi5JB9LbAMs26PBAwaOuwa6qNk0+uZF5d8aF
D+Tj98U4qSypi3lAek2yCsrsX4cY/yVb2fHIszqGCwpdU7EPK7JP1WFLgxEOUKvJ3ZRYoXaAut3B
BwXElb/3/cdU+NsOhVETZYSzMlwL4YNtO4tUrHbEcVzCsq079nQWhi563WqRcHEUKdWE079q/2xb
0AFHGD7V3IxBSbwnNs7ykb4JYdaEzVUnQwo0KoqBV5KIzrSIvWRbaLyF04ZenRpMPDgx6+QlOOop
Oa/4quwUHNyQeQEMB7zG/59bPhtW85RnSrkyPlceZUch3qjWIfRQREHng3lGqrEE3gOiDCVnfPe5
PLTpCs/tEtWICSMae0KDhmKYmmfQVLEDiU4FlSA4U3qooPZwebCr+AF/K1XHluQhBb3rfoYn56Lo
tgr9DTUfFzm9kY4QgAaJ0eyR6hEqq8FoiLNiMmgA0t2ozfhRzpx+F3J1uUuJ/duZcitfikQLzYJ3
sTgbuwcTPsp/OgWx8abLLu4MrvdatUMchfDONVs9QePK4YH6Z8irdvpHAlGR0AE6ECNtBocdemvR
HmA0sPet1V0khyyzX+Ragf4X+BcrJwuwngsPscQPo6nmN6MUdagWKq+95mJkY0A+j+2qS93FLNPZ
XCT36GPpves05cA0HPM2ZuRIUvHsnQjR3VxNjnWVX/q6XbsGxYWGfFk8ldVgLxhEOTwcdtI5DRvA
1U5NJVEQ1gKnQpmrV2eGAk7FA2jsJ3fare3SW0fPnOvXihIX1bHCFvxGs3EEiN+PBd4mSV+gRjxH
zrWTuWjcQ1ZZEJAozqormMd5bPgMo/0nOdOvbI2f/mwHwB81qP5vWZ/FELFu8pgsPS68q+DkcDQc
14Rllvm2sUa/yvfWfObt5sKDpQqh4Z4Gc4F4KRjbqOkv1w/eS48+CVAzwJeWaUNq4Q/VkLUvVi4c
7O1iND0eJ37FhJMZ8XNm5i4sHQN/5vQK7hIdfN9tZhjtHgjr2czD1/kBYH0MqcHH+aCWVacnvKv4
6Rqu3dfLy/IA8y9xb/3JW6lCTHRbT8qOo0VlO6HwP6tPoReajc+cNCq+RAEToxINfyGf8JEpNahB
OvizEXIxJJwXCniIaE19ZRnO74hGmMqanqi/NGp01WU56k3GwMvzYYJBLAFHti+uDgm6Flh989C4
qYolzZ+03L5o2kb+UizsKZGPhSsCGDVFCQplvVJD+EwcLKNVBprgfT36vH6HZhp5Kv5dDAp7PhSq
sSd6MhePbdRGY54vSCWv14VsMc+ozn3aiDpJNQwhTTmI/D0wKcB2bg1YwC5zJbMuQtGfv2zm7+Um
E/ZzcnHpstoUy5Zpl0KMZEFFjTMk77QzaH6Glecrd717Bq3YYBL2FhKEaeWbcLv2TvDDXsh36NMU
oxf9ZkDfT/GJxNFUOwWGUt0/tA7DCfRBdFXZG+7j9CaMHqp5Z6Eh58A4nAdKl+AzDCfnyZxscKLd
o2dmcVsM+6asajwLwbpIX9vA4BteWzDGrOxcNLGlMiYSZHaSp5Wyabi86qIj7b8mhmWvUZbEwt3p
6kjdEta1+KtpZWqczUUrNHksVpLXLEW+EVX2TiktA9uboad8KIYq3DCA5lQFlD2qhLJmO57WDvrB
v6sR3XAbh9EAgRakyfFp5LS6hoSdm/uE+Odo9ZYEZ3oyRW/i7JJO3+IXrujkJT7iuIb7XqhWqg+M
Qw8MuzGveB1ynE9bMHm4fsfHI61EzcHY6hgbuFJIQ7DPPBZeZPRo3wRTlZIz+eXIA0vyZTNzytWn
fc9iSBdHwh5CYoLjzqpERkxN5SoJ3M7BK1ZFWqfM2M4MoDdcyQc+TXyVUPL5
`protect end_protected
| gpl-3.0 | d6d2f999a8527e23981289b889d74a57 | 0.955203 | 1.830485 | false | false | false | false |
makestuff/spi-talk | templates/ssa/vhdl/top_level.vhdl | 1 | 4,871 | --
-- Copyright (C) 2009-2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
sysClk_in : in std_logic; -- 50MHz system clock
-- USB interface -----------------------------------------------------------------------------
serClk_in : in std_logic; -- serial clock (async to sysClk_in)
serData_in : in std_logic; -- serial data in
serData_out : out std_logic -- serial data out
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- SPI signals
signal spiCS : std_logic_vector(NUM_DEVS-1 downto 0);
signal spiClk : std_logic;
signal spiMOSI : std_logic;
signal spiMISO : std_logic;
-- Component from the Altera library to give application access to the config flash.
component altserial_flash_loader
generic (
enable_quad_spi_support : natural;
enable_shared_access : string;
enhanced_mode : natural;
intended_device_family : string;
lpm_type : string
);
port (
data0out : out std_logic;
noe : in std_logic;
scein : in std_logic;
asmi_access_granted : in std_logic;
asmi_access_request : out std_logic;
dclkin : in std_logic;
sdoin : in std_logic
);
end component;
begin
-- CommFPGA module
comm_fpga_ss : entity work.comm_fpga_ss
port map(
clk_in => sysClk_in,
reset_in => '0',
-- USB interface
serClk_in => serClk_in,
serData_in => serData_in,
serData_out => serData_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => sysClk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk,
spiData_out => spiMOSI,
spiData_in => spiMISO,
spiCS_out => spiCS
);
-- Allow application access to config flash
spi_access : altserial_flash_loader
generic map (
enable_quad_spi_support => 0,
enable_shared_access => "ON",
enhanced_mode => 1,
intended_device_family => "Cyclone II",
lpm_type => "altserial_flash_loader"
)
port map (
asmi_access_granted => '0',
asmi_access_request => open,
noe => '0',
scein => spiCS(0),
dclkin => spiClk,
sdoin => spiMOSI,
data0out => spiMISO
);
end architecture;
| gpl-3.0 | 498d53760a0ca9f66b125312cd6f2de4 | 0.588996 | 3.5374 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_sitofp_4_no_dsp_32.vhd | 5 | 12,399 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_sitofp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_sitofp_4_no_dsp_32;
ARCHITECTURE ANN_ap_sitofp_4_no_dsp_32_arch OF ANN_ap_sitofp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_sitofp_4_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_sitofp_4_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_sitofp_4_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=1,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=0,C_B_WIDTH=32,C_B_FRACTION_WIDTH=0,C_C_WIDTH=32,C_C_FRACTION_WIDTH=0,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_sitofp_4_no_dsp_32_arch;
| gpl-3.0 | bad44a5a537d2054bf0a29e64c43556c | 0.647875 | 3.008006 | false | false | false | false |
airlog/vhdl-rc4 | src/rc4_initer.vhd | 1 | 3,668 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity rc4_initer is
generic (
width: integer := 8
);
port (
CLK: in std_logic;
GO: in std_logic;
KEYLEN: in std_logic_vector((width - 1) downto 0);
MEMINPUT: in std_logic_vector((width - 1) downto 0);
KEYINPUT: in std_logic_vector((width - 1) downto 0);
KEYINDEX: out std_logic_vector((width - 1) downto 0);
MEMCTRL: out std_logic;
MEMINDEX: out std_logic_vector((width - 1) downto 0);
MEMOUTPUT: out std_logic_vector((width - 1) downto 0);
DONE: out std_logic
);
end rc4_initer;
architecture Behavioral of rc4_initer is
constant permlength : integer := 256;
begin
process (clk)
type rc4_initer_state is (IDLE, INIT, SHUFFLE);
subtype rc4int is integer range 0 to 255;
variable state : rc4_initer_state := IDLE;
variable clk_ctr, ctr : integer := 0;
variable i, j, si, sj, k, tmp : rc4int := 0;
variable keylength : integer := 0;
begin
if rising_edge(clk) then
keylength := conv_integer(unsigned(keylen));
case state is
when IDLE =>
if go = '1' then
clk_ctr := 0;
ctr := 0;
done <= '0';
i := 0;
j := 0;
si := 0;
sj := 0;
state := INIT;
else
done <= '1';
state := IDLE;
end if;
when INIT =>
if ctr >= permlength then
clk_ctr := 0;
ctr := 0;
state := SHUFFLE;
else
if clk_ctr mod 2 = 0 then
-- nie rob nic (podtrzymaj ostatnia komende)
else
memctrl <= '1';
memindex <= conv_std_logic_vector(ctr, width);
memoutput <= conv_std_logic_vector(ctr, width);
ctr := ctr + 1;
end if;
clk_ctr := clk_ctr + 1;
end if;
when SHUFFLE =>
if i >= permlength then
clk_ctr := 0;
ctr := 0;
i := 0;
j := 0;
si := 0;
sj := 0;
memctrl <= '0';
done <= '1';
state := IDLE;
else
case clk_ctr is
when 0 =>
si := 0;
sj := 0;
k := 0;
memctrl <= '0';
memindex <= conv_std_logic_vector(i, width);
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 1 =>
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 2 =>
si := conv_integer(unsigned(meminput));
tmp := i mod keylength;
keyindex <= conv_std_logic_vector(tmp, width);
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 3 =>
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 4 =>
k := conv_integer(unsigned(keyinput));
j := (j + si + k) mod 256;
memctrl <= '0';
memindex <= conv_std_logic_vector(j, width);
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 5 =>
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 6 =>
sj := conv_integer(unsigned(meminput));
memoutput <= conv_std_logic_vector(si, width);
memctrl <= '1';
clk_ctr := clk_ctr + 1;
state := SHUFFLE;
when 7 =>
memindex <= conv_std_logic_vector(i, width);
memoutput <= conv_std_logic_vector(sj, width);
memctrl <= '1';
clk_ctr := 0;
i := i + 1;
state := SHUFFLE;
when others =>
memindex <= "11111111";
memoutput <= "11111111";
memctrl <= '0';
state := SHUFFLE;
end case;
end if;
end case;
end if;
end process;
end Behavioral;
| mit | 1b5cb93f39b874875937a9c95c6f4ced | 0.487459 | 3.226033 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kn_kalman_add.vhd | 2 | 290,784 | -- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: kn_kalman_add.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" DIRECTION="ADD" OPTIMIZE="SPEED" PIPELINE=14 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 clock dataa datab result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_altfp_add_sub 2012:01:25:21:13:53:SJ cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altbarrel_shift_h0e IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_add_altbarrel_shift_h0e;
ARCHITECTURE RTL OF kn_kalman_add_altbarrel_shift_h0e IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w681w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w677w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w702w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w698w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w724w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w720w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w746w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w742w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w768w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w764w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w673w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w694w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w716w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w738w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w760w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w684w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w705w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w727w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w749w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w679w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w700w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w722w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w744w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w766w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range759w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) AND wire_lbarrel_shift_w679w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) AND wire_lbarrel_shift_w676w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) AND wire_lbarrel_shift_w700w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) AND wire_lbarrel_shift_w697w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) AND wire_lbarrel_shift_w722w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) AND wire_lbarrel_shift_w719w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) AND wire_lbarrel_shift_w744w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) AND wire_lbarrel_shift_w741w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) AND wire_lbarrel_shift_w766w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) AND wire_lbarrel_shift_w763w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w681w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w677w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w702w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w698w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w724w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w720w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w746w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w742w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w768w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w764w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w680w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w701w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w723w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w745w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w767w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w673w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w694w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w716w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w738w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w760w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w677w678w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w698w699w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w720w721w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w742w743w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w764w765w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w684w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w681w682w683w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w673w674w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w705w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w702w703w704w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w694w695w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w727w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w724w725w726w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w716w717w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w749w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w746w747w748w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w738w739w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w771w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w768w769w770w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w760w761w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w771w & wire_lbarrel_shift_w749w & wire_lbarrel_shift_w727w & wire_lbarrel_shift_w705w & wire_lbarrel_shift_w684w);
wire_lbarrel_shift_w676w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w679w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w697w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w700w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w719w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w722w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w741w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w744w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w763w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w766w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range759w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range759w;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altbarrel_shift_h0e
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 REGISTER_OUTPUT="NO" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 11.1SP2 cbx_altbarrel_shift 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources = reg 29
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altbarrel_shift_n3g IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END kn_kalman_add_altbarrel_shift_n3g;
ARCHITECTURE RTL OF kn_kalman_add_altbarrel_shift_n3g IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sel_pipec3r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sel_pipec4r1d : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w796w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w792w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w817w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w813w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w839w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w835w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w861w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w857w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range780w795w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range802w816w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range823w838w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range847w860w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w879w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range783w788w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range804w809w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range826w831w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range849w853w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range868w872w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w799w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w791w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w794w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w812w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w815w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w834w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w837w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w856w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w859w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w878w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range780w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range802w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range823w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range843w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range865w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range778w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range801w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range821w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range783w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range804w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range826w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range868w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_smux_w_range830w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) AND wire_rbarrel_shift_w794w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) AND wire_rbarrel_shift_w791w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) AND wire_rbarrel_shift_w815w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) AND wire_rbarrel_shift_w812w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w839w(0) AND wire_rbarrel_shift_w837w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w835w(0) AND wire_rbarrel_shift_w834w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w861w(0) AND wire_rbarrel_shift_w859w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w857w(0) AND wire_rbarrel_shift_w856w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w880w(0) AND wire_rbarrel_shift_w878w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w876w(0) AND wire_rbarrel_shift_w875w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) AND wire_rbarrel_shift_w_sbit_w_range778w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) AND wire_rbarrel_shift_w_sbit_w_range801w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range826w831w(0) AND wire_rbarrel_shift_w_sbit_w_range821w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range849w853w(0) AND wire_rbarrel_shift_w_sbit_w_range843w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range868w872w(0) AND wire_rbarrel_shift_w_sbit_w_range865w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range783w796w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w792w(0) <= wire_rbarrel_shift_w_sel_w_range783w(0) AND wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w817w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w813w(0) <= wire_rbarrel_shift_w_sel_w_range804w(0) AND wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w839w(0) <= wire_rbarrel_shift_w_sel_w_range826w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range823w838w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w835w(0) <= wire_rbarrel_shift_w_sel_w_range826w(0) AND wire_rbarrel_shift_w_dir_w_range823w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w861w(0) <= wire_rbarrel_shift_w_sel_w_range849w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range847w860w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w857w(0) <= wire_rbarrel_shift_w_sel_w_range849w(0) AND wire_rbarrel_shift_w_dir_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w880w(0) <= wire_rbarrel_shift_w_sel_w_range868w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w879w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w876w(0) <= wire_rbarrel_shift_w_sel_w_range868w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range780w795w(0) <= NOT wire_rbarrel_shift_w_dir_w_range780w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range802w816w(0) <= NOT wire_rbarrel_shift_w_dir_w_range802w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range823w838w(0) <= NOT wire_rbarrel_shift_w_dir_w_range823w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range847w860w(0) <= NOT wire_rbarrel_shift_w_dir_w_range847w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w879w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range783w788w(0) <= NOT wire_rbarrel_shift_w_sel_w_range783w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range804w809w(0) <= NOT wire_rbarrel_shift_w_sel_w_range804w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range826w831w(0) <= NOT wire_rbarrel_shift_w_sel_w_range826w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range849w853w(0) <= NOT wire_rbarrel_shift_w_sel_w_range849w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range868w872w(0) <= NOT wire_rbarrel_shift_w_sel_w_range868w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w796w797w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w792w793w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w817w818w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w813w814w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w839w840w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w835w836w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w861w862w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w857w858w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w880w881w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w876w877w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w799w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range783w796w797w798w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range783w788w789w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w820w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range804w817w818w819w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range804w809w810w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w842w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range826w839w840w841w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range826w831w832w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w864w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range849w861w862w863w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range849w853w854w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w883w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range868w880w881w882w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range868w872w873w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 3) & dir_pipe(0) & dir_w(1 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 78) & sbit_piper1d & smux_w(51 DOWNTO 0) & data);
sel_w <= ( sel_pipec4r1d & sel_pipec3r1d & distance(2 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w883w & wire_rbarrel_shift_w864w & wire_rbarrel_shift_w842w & wire_rbarrel_shift_w820w & wire_rbarrel_shift_w799w);
wire_rbarrel_shift_w791w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w794w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w812w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w815w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w834w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w837w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w856w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w859w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w875w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w878w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range780w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range802w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range823w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range847w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range843w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range865w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range778w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range801w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range821w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range783w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range804w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range826w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range849w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range868w(0) <= sel_w(4);
wire_rbarrel_shift_w_smux_w_range830w <= smux_w(77 DOWNTO 52);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(2));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_rbarrel_shift_w_smux_w_range830w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec3r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec3r1d <= distance(3);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sel_pipec4r1d <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sel_pipec4r1d <= distance(4);
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altbarrel_shift_n3g
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_3e8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --kn_kalman_add_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_6e8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero919w920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero919w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero921w922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero919w & wire_altpriority_encoder14_w_lg_w_lg_zero921w922w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero919w920w(0) <= wire_altpriority_encoder14_w_lg_zero919w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero921w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero919w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero921w922w(0) <= wire_altpriority_encoder14_w_lg_zero921w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero919w920w(0);
altpriority_encoder14 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_be8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero909w910w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero909w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero911w912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero909w & wire_altpriority_encoder12_w_lg_w_lg_zero911w912w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero909w910w(i) <= wire_altpriority_encoder12_w_lg_zero909w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero911w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero909w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero911w912w(i) <= wire_altpriority_encoder12_w_lg_zero911w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero909w910w(i);
END GENERATE loop52;
altpriority_encoder12 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_3v7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --kn_kalman_add_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_6v7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero944w945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero944w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero946w947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero944w & wire_altpriority_encoder18_w_lg_w_lg_zero946w947w);
altpriority_encoder17 : kn_kalman_add_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero944w945w(0) <= wire_altpriority_encoder18_w_lg_zero944w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero946w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero944w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero946w947w(0) <= wire_altpriority_encoder18_w_lg_zero946w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero944w945w(0);
altpriority_encoder18 : kn_kalman_add_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_bv7;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero935w936w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero935w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero937w938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero935w & wire_altpriority_encoder16_w_lg_w_lg_zero937w938w);
altpriority_encoder15 : kn_kalman_add_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero935w936w(i) <= wire_altpriority_encoder16_w_lg_zero935w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero937w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero935w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero937w938w(i) <= wire_altpriority_encoder16_w_lg_zero937w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero935w936w(i);
END GENERATE loop55;
altpriority_encoder16 : kn_kalman_add_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_uv8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_uv8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_uv8 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero900w901w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero900w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero902w903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero900w & wire_altpriority_encoder10_w_lg_w_lg_zero902w903w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero900w901w(i) <= wire_altpriority_encoder10_w_lg_zero900w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero902w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero900w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero902w903w(i) <= wire_altpriority_encoder10_w_lg_zero902w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero900w901w(i);
END GENERATE loop58;
altpriority_encoder10 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : kn_kalman_add_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --kn_kalman_add_altpriority_encoder_uv8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ue9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_ue9;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ue9 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero956w957w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero956w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero958w959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero956w & wire_altpriority_encoder20_w_lg_w_lg_zero958w959w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero956w957w(i) <= wire_altpriority_encoder20_w_lg_zero956w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero958w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero956w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero958w959w(i) <= wire_altpriority_encoder20_w_lg_zero958w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero956w957w(i);
END GENERATE loop61;
altpriority_encoder20 : kn_kalman_add_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_ue9
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ou8 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_ou8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ou8 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero890w891w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero890w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_uv8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_ue9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= pipeline_q_dffe;
tmp_q_wire <= ( wire_altpriority_encoder8_w_lg_zero890w & wire_altpriority_encoder8_w_lg_w_lg_zero892w893w);
altpriority_encoder7 : kn_kalman_add_altpriority_encoder_uv8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero890w891w(i) <= wire_altpriority_encoder8_w_lg_zero890w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero892w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero890w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero890w891w(i);
END GENERATE loop64;
altpriority_encoder8 : kn_kalman_add_altpriority_encoder_ue9
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= tmp_q_wire;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altpriority_encoder_ou8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=1 WIDTH=32 WIDTHAD=5 aclr clk_en clock data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_nh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1006w1008w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1006w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1006w1008w(0) <= NOT wire_altpriority_encoder27_w_data_range1006w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1006w1008w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1006w(0) <= data(0);
END RTL; --kn_kalman_add_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_qh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero1000w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero1000w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero1000w1001w(0) <= wire_altpriority_encoder27_w_lg_zero1000w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0);
altpriority_encoder27 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_vh8;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero990w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero990w991w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero990w991w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero990w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero988w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero990w991w(i) <= wire_altpriority_encoder25_w_lg_zero990w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i);
END GENERATE loop67;
altpriority_encoder25 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_ii9 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END kn_kalman_add_altpriority_encoder_ii9;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_ii9 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero980w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero980w981w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT kn_kalman_add_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero980w981w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero980w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero978w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero980w981w(i) <= wire_altpriority_encoder23_w_lg_zero980w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i);
END GENERATE loop70;
altpriority_encoder23 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --kn_kalman_add_altpriority_encoder_ii9
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" PIPELINE=0 WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 11.1SP2 cbx_altpriority_encoder 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_n28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1040w1042w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1040w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1040w1042w(0) <= NOT wire_altpriority_encoder34_w_data_range1040w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1040w1042w);
wire_altpriority_encoder34_w_data_range1040w(0) <= data(0);
END RTL; --kn_kalman_add_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_q28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1035w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w);
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1035w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1035w1036w(0) <= wire_altpriority_encoder33_w_lg_zero1035w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0);
altpriority_encoder33 : kn_kalman_add_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : kn_kalman_add_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --kn_kalman_add_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_v28;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1026w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1026w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1024w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1026w1027w(i) <= wire_altpriority_encoder31_w_lg_zero1026w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i);
END GENERATE loop73;
altpriority_encoder31 : kn_kalman_add_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : kn_kalman_add_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --kn_kalman_add_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_i39 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_i39;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_i39 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1017w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1017w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1015w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1017w1018w(i) <= wire_altpriority_encoder29_w_lg_zero1017w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i);
END GENERATE loop76;
altpriority_encoder29 : kn_kalman_add_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : kn_kalman_add_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --kn_kalman_add_altpriority_encoder_i39
--synthesis_resources = reg 5
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altpriority_encoder_cna IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END kn_kalman_add_altpriority_encoder_cna;
ARCHITECTURE RTL OF kn_kalman_add_altpriority_encoder_cna IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero966w967w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero966w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero968w969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL pipeline_q_dffe : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL tmp_q_wire : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT kn_kalman_add_altpriority_encoder_ii9
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_i39
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
loop77 : FOR i IN 0 TO 4 GENERATE
wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w(i) <= NOT tmp_q_wire(i);
END GENERATE loop77;
q <= (NOT pipeline_q_dffe);
tmp_q_wire <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero968w969w);
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero966w967w(i) <= wire_altpriority_encoder21_w_lg_zero966w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop78;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero968w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop79;
wire_altpriority_encoder21_w_lg_zero966w(0) <= NOT wire_altpriority_encoder21_zero;
loop80 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero968w969w(i) <= wire_altpriority_encoder21_w_lg_zero968w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero966w967w(i);
END GENERATE loop80;
altpriority_encoder21 : kn_kalman_add_altpriority_encoder_ii9
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : kn_kalman_add_altpriority_encoder_i39
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN pipeline_q_dffe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN pipeline_q_dffe <= wire_trailing_zeros_cnt_w_lg_tmp_q_wire974w;
END IF;
END IF;
END PROCESS;
END RTL; --kn_kalman_add_altpriority_encoder_cna
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 716
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add_altfp_add_sub_12j IS
PORT
(
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_add_altfp_add_sub_12j;
ARCHITECTURE RTL OF kn_kalman_add_altfp_add_sub_12j IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL add_sub_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_dataa_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe12 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe13 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_exp_dffe14 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe12 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_man_dffe14 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL aligned_datab_sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL both_inputs_are_infinite_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_adj_dffe23 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_amb_mux_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_intermediate_res_dffe41 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe23 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe25 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe27 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_dataa_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_infinite_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_datab_nan_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe23 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe27 : STD_LOGIC_VECTOR(27 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_not_zero_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_rounding_add_sub_result_reg : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_smaller_dffe13 : STD_LOGIC_VECTOR(23 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe13 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL rshift_distance_dffe14 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe41 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe25 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe23 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe27 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w276w277w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w280w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w276w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL aclr : STD_LOGIC;
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL clk_en : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range275w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range283w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range290w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range291w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT kn_kalman_add_altbarrel_shift_h0e
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altbarrel_shift_n3g
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_ou8
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT kn_kalman_add_altpriority_encoder_cna
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop81 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w279w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w276w277w(i) <= wire_w_lg_exp_amb_mux_w276w(0) AND wire_w_exp_amb_w_range275w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop89;
loop90 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop90;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop91 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop93;
loop94 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop94;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop95 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop95;
loop96 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop96;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo337w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop97 : FOR i IN 0 TO 4 GENERATE
wire_w293w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) AND wire_w_exp_diff_abs_w_range291w(i);
END GENERATE loop97;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop98 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w280w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w274w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range273w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop111;
loop112 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop112;
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop113 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w(i) <= wire_w_exp_diff_abs_exceed_max_w_range290w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop113;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop114 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop116;
loop117 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop117;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w276w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w292w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range290w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop118 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop120;
loop121 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop121;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w(0) <= wire_w_exp_diff_abs_exceed_max_w_range283w(0) OR wire_w_exp_diff_abs_w_range285w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w(0) <= wire_w_exp_diff_abs_exceed_max_w_range287w(0) OR wire_w_exp_diff_abs_w_range288w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
aclr <= '0';
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25;
add_sub_w2 <= (NOT (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo));
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25;
clk_en <= '1';
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range287w289w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range283w286w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w276w277w OR wire_w_lg_exp_amb_mux_w274w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo337w338w(0) OR (input_datab_infinite_dffe15_wo AND aligned_datab_sign_dffe15_wo));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= man_res_rounding_add_sub_result_reg;
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w280w OR wire_w_lg_w_lg_exp_amb_mux_w276w279w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range290w294w OR wire_w293w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range275w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range273w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range283w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range287w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range290w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range291w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range285w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range288w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : kn_kalman_add_altbarrel_shift_h0e
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : kn_kalman_add_altbarrel_shift_n3g
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : kn_kalman_add_altpriority_encoder_ou8
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : kn_kalman_add_altpriority_encoder_cna
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN add_sub_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN add_sub_dffe25 <= add_sub_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe12 <= aligned_dataa_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe13 <= aligned_dataa_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_exp_dffe14 <= aligned_dataa_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe12 <= aligned_dataa_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe13 <= aligned_dataa_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_man_dffe14 <= aligned_dataa_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe12 <= aligned_dataa_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe13 <= aligned_dataa_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_dataa_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_dataa_sign_dffe14 <= aligned_dataa_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe12 <= aligned_datab_exp_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe13 <= aligned_datab_exp_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_exp_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_exp_dffe14 <= aligned_datab_exp_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe12 <= aligned_datab_man_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe13 <= aligned_datab_man_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_man_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_man_dffe14 <= aligned_datab_man_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe12 <= aligned_datab_sign_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe13 <= aligned_datab_sign_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN aligned_datab_sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN aligned_datab_sign_dffe14 <= aligned_datab_sign_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe25 <= both_inputs_are_infinite_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe25 <= dataa_sign_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe41 <= denormal_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe23 <= exp_adj_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe13 <= exp_amb_mux_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_amb_mux_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_amb_mux_dffe14 <= exp_amb_mux_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_intermediate_res_dffe41 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_intermediate_res_dffe41 <= exp_intermediate_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe23 <= exp_res_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe25 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe25 <= exp_res_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe27 <= exp_res_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe23 <= infinite_output_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe25 <= infinite_output_sign_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe27 <= infinite_output_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe41 <= infinite_output_sign_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe41 <= infinite_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe23 <= infinity_magnitude_sub_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe27 <= infinity_magnitude_sub_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe41 <= infinity_magnitude_sub_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe12 <= input_dataa_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe13 <= input_dataa_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_infinite_dffe14 <= input_dataa_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_dataa_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_dataa_nan_dffe12 <= input_dataa_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe12 <= input_datab_infinite_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe13 <= input_datab_infinite_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_infinite_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_infinite_dffe14 <= input_datab_infinite_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_datab_nan_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_datab_nan_dffe12 <= input_datab_nan_dffe12_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe23 <= input_is_infinite_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe25 <= input_is_infinite_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe27 <= input_is_infinite_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe41 <= input_is_infinite_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe13 <= input_is_nan_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe14 <= input_is_nan_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe23 <= input_is_nan_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe25 <= input_is_nan_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe27 <= input_is_nan_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe41 <= input_is_nan_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe23 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe23 <= man_add_sub_res_mag_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe27 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe27 <= man_add_sub_res_mag_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe23 <= man_add_sub_res_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe27 <= man_add_sub_res_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe41 <= man_res_is_not_zero_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_not_zero_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_not_zero_dffe23 <= man_res_not_zero_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_rounding_add_sub_result_reg <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_rounding_add_sub_result_reg <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_smaller_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_smaller_dffe13 <= man_smaller_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe23 <= round_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe13 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe13 <= rshift_distance_dffe13_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rshift_distance_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rshift_distance_dffe14 <= rshift_distance_dffe14_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe41 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe41 <= sign_res_dffe41_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe23 <= sticky_bit_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe25 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe25 <= sticky_bit_dffe25_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe27 <= sticky_bit_dffe27_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe23 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe23 <= zero_man_sign_dffe23_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe27 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe27 <= zero_man_sign_dffe27_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop122;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop123;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop124;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop125;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop126;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop127 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop127;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop128;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop129;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop130 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop130;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --kn_kalman_add_altfp_add_sub_12j
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY kn_kalman_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END kn_kalman_add;
ARCHITECTURE RTL OF kn_kalman_add IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT kn_kalman_add_altfp_add_sub_12j
PORT (
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
kn_kalman_add_altfp_add_sub_12j_component : kn_kalman_add_altfp_add_sub_12j
PORT MAP (
clock => clock,
dataa => dataa,
datab => datab,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "14"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL kn_kalman_add_inst.vhd TRUE
-- Retrieval info: LIB_FILE: lpm
| mit | b0f49145285ac5ae1f7af487c063d07b | 0.683105 | 2.509376 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_fpext_32ns_64_1.vhd | 1 | 1,932 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fpext_32ns_64_1 is
generic (
ID : integer := 4;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 64
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fpext_32ns_64_1 is
--------------------- Component ---------------------
component ANN_ap_fpext_0_no_dsp_32 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fpext_0_no_dsp_32_u : component ANN_ap_fpext_0_no_dsp_32
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
| gpl-3.0 | b18a4403417ae8e5d4bb97ab0e3ae418 | 0.488095 | 3.638418 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd | 24 | 10,812 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
qQi3Y4JwXl7Wn1bhw/jkWXomzcSGtpscU8oJ2LP5BaQ4u6xazRA/mCI7R7F7nM8pFppzcZaDXNDE
awD47nPbZg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XEx6ZQwv4Vw0EbtXfrnFwRRFXeTMxOSVFFjSp4WS2rNJPGaN9nwYF1MaeUImPm4WplW12OharfDq
Bd4u1MUCQQngaNAVq+qRFAvic1cEd9UAgV4uPUwUSymN6YFqFEFkBe61gVOGTL52kYCmFP5vOloO
dikNZ7RmkwcL7Ou/YYw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UywbMvtnenvwrN54J6TLUnt5D0ugRYGbxGf5WbHCK4A1QpEpAfm4/GMahChLWJyd4co3Sz7iyKnH
pF9fGrDxABF6+XgD+gYwW23LAy4Oeb9L0L1aN751j4eBb+SD/nc7Bvs8/PkG8AEiUh9nBX5X8YRG
y6Rb3Rd/oLAqNh8W+hPkvGvBFD04EpmUO8rwABNMEgzx5Xy8UXIXF2/AM7g88q21LLpqxJfNMKwc
6gETTRFn2W/DccvMkQI7J7x9xQ6JV6mIj8jQumxc8qNgDnzszgiyVxNRBCbBRnwlMks8aj9jaN+c
Q9ZuNT/eHVXIa0PtrhWx3BPMD5whsOfdpvUEtw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
IBlJOJ+ArISdfMfaRPeRQ6J3iITR2w063jCi0nfoo8xkZyikCIgC9XnNEXDlcFlFoTYVTWN/pOxk
4QfAUNIYHfGqxHDX5K+igT3JRGAbHW05TeT9Sz1Tz76BTL6nuYHgWbYb3HeB+sQkWjFalZjk90K9
XOlFLMcGKo/KZGkFFlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
UEgDruV4ZmeVXnBh8PLE5PuwbRj5lmOC7K+F+X4e7otBgmXMWFiIeN9GvRB5AtCI3/1G6zC73gYH
FO1FlbS2tVmG3nSzVkxcIbEL+1KFosqyivHaeWvPOnefymg/10sYhtvZO5E9oVciuYijzF2w37f1
+4YL/FQqMk/yNEOV2k/YRjnqc95iWqQ5vwJ7EAAYrnHnFINWKUvk3N1gH1DwIaBkwK3QG8wkmtAX
tNp4c+AqLhfwpZ56BFnB83iDMJP8wmqSaW72Ckgh0dX309k5OA2Zw6uWUoRzYaEgJQgRL7ARYuPh
p4NJLaGXoIG5duhfCAO8zu+TZ49OCwwXulwm7w==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Dzk2duxGRZEP8sfvf9eFwJMWv7R8u0eFXVvb80PbacYDJR7yK9uh327PG+jja/aceEUlDK9iE6LC
gHnAhFB+s2L7gbIN5CB2gJ0O/y7NGTy9/CsMTLlUlECbh3egIAKJ4XZKfIxn7KP1Sb+n2k7aQe6H
FXUgDSit0mOXHhQbzQUUynd81PYcQDMSRTrNLn6L7GsMV/N4KrCegZhOpHfzOVEhHkkMpIWSGBt4
0gsZSXY4FhbaybuBSsYhSiZIPMLy3FxEgJQeZbHMHTyJaibx6UrTayI4VnRP4BA2lHpY4yqhwdrI
qYhnt3+HhAvJgqexSmEUJ4YIMZSxSGHLYZZeHg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5872)
`protect data_block
tW2/X7vSNTSNWTm7mZMxJdbdpKlStwr1I2qOFJ5Ka5TPzAVTCBLrYL4wfzEsW2WiYzahzut11iu7
5bkkJT+XY+nnYDeLNaq9oZiKa46GbDQij9eBRfPL4WutrsGLOo3fvXshpE7s1cbaUjni1PDq4wTh
EL9JQf19Q/tfUTIS8l2q1O3vfHO7sJmfhdqmHl5Ktimz7VNjbz0rvZ0uRl7uilTFub2TEM3GRc3t
TMRCiEOxxRqThe2a/cipcAUKtFv86RhNvsViCgkdnfM6o106htfeD0j5NVgDahXmjWbUdjtrsbwN
YcVuy++v85Qz68E2AepsHg7f66vVNbL9/SP2KMfSqE9doHIhDKbDuAbWNcDI2VTZLUYOmJ5Kw2FZ
d0/JLJDBOaokoqSI/DvDiIGhFRiDl9+6XMZAgGdte8G20M9Ps147hkc92w2z+yFvg4U2jnSgbJqa
ZYmykyqv7agwv+czqNxVQZNfu43fgyaSYzQ6w8nZQSG4nR3fn+n0l3QiM49Zm3fpQrGVHx/Qnj/o
M9aWaHGtNPFQtvMkQNas7JoGWH5BQdt+AaCsqkzwUEvVBPrMBH9CH02yNe9P4K/RNDZxKJr/RKOV
Tv9k6pR947oH8Gr2d2IohTh+TvADSbtOYLaynJWRI8AvI1zXGI5dhE7Bw/9a6t2RilvNyhVvifpT
wOwEXl5vEBTnNR/aZTzoebQxh+DylXdXEFEIx7vauRyWlaqw3lKTZ+AJUxfu7+JY+12iBie0TbIV
TbGcYlPmwlW6CdESmqPhpY4fn1asS6Y6Z8p276/LDQRhBO1ou7XUwTdFt4eJnRYGA6OEYk8hYE0d
/7uRv9iH2WfgiOLjEoLfZULxKDaTrD+yyYjxmlmy4RJZXZ+N1yx7HKT3PYQebQ4LJ49CzIHIFhEm
vw3JXv/e9BoYvNFyOyW37841mVjZ5kmhMgSN7qxfD4yxDZIjbZvja1l5gPjf2cksl0f6MNmJUQMm
Npb4QspTvctQM3Xs0RReGW8rsGx87jdkIZtyyMtrBh8eHYizh+XHOSShcmjZHI3QhhXUu9mUAt9P
NKyadBOAsnhGz8wmcsTXdQJLhb9I/m5eZHrZWn3O+rkZ1dWfTPZMvAPcqsZ/TK3UPBtlE2slkuJa
LMw0829WNWRTfc+DQbnqoMc0HZaXi8HvWlPy17QBDxyHDy77ldoKQ6NqUyjtzx1QjshPz86DCpOp
F7shN2NVyl4ZxfLfwqfuhvKjx1PhHOuP0OShsQHF4lxChiecG31o1IajAytfNo59/ophgMucatc7
3U+HM+arslNmzOF+cLdT4xVKZnja7dmacQVTJxb+QQ+V3RchUpF8rRNxWnT7BzgyBKWKG031xiCW
vRy4T9/URmISo8gRJBUKfg0hwpWMeTneh23Jc1K1rNv3n4BM4Tn8LIGWl89/MTHpc2NTS3F+mH/h
gyXNYdFnO2zHCkGNV7kE/m6EtJ7FE3p2TfOE13ru++DKSStPiYEXE9ZjCeYQ/tUNzPAv9plO2NeB
gjpIUuasbCXp+u9w4aF+yNZh2XZ5myOdGjLcmFXgkOUO7pg7cGafAMkjhc6N9WJymPsQDF+O67k4
XYC9f41zr0ZeBAOkoHb53CDEAvhlwO6Iy3GArzY/P0QA6QJW639o2eRJefKiQj1KE1/VMoEVmAxV
6s0K3d0gcVCbuzZ787mNPNCqga+WVjvPcpXQtxTbDz0/FcmygGIe+CnlJfA2yyg66O9rEfRvh9B2
dNafVldov+knrH3S2tr+Wosc0wNZ4zkTpEJjSCKSLUG/bBR181QOEmeuVc1zf36hGPYjkIFcuvQ5
PBThUx8XIKXTp+NpQ0QDr+k9CuuBu0Yd81j8xgeA1iFttygeOX66Xlrc712S7f0kqBaHDS+s9xyC
4vo0nfQhWmGchTFEfTAouehpfP5B139UtAA6KP4bRxHTT1OY2Ea9UiZzp/P/nn4r4DuZQyGQec7D
HX6maHIJjDcqo8WHES7PJFp4VDmj993iZEG7WV/oWFKwlx/zXCquUIq5zs3YGg7yilvtPOu3iWJC
/luNGDe/2DfDz+wg8U1veMIVxxB6XOEHlbUF1d5KbR/nW5bpuwUm4gZZ4FBVf/LlZA+FLXnz24Ht
btgYnVzanXTje+kI9DPtbo5SMb/Yj/a86ZX8lNPd8NlD5JTGfJVF1Drz2xT9VVwc53CmuDBa8/oq
tmhFOPSgdBCGA6dJ7FpC1/lOPDrvsqQFlhmVId+9nI82su1VULN5ShNRxcJ4e5rtAq9Klc1hRa7t
7DLJLE1mYFT2vOWEtJs0GPbvv+xFPmLe5LgQJ8IPAhQnPUFRJiQ3V6V65+ynkk0g61N7kA4juK9J
BoL/UgzJacoH4VQ7NwPN5QtLP10i1jjwjyMdRCcTEC+vYbPHjKCuY0ReXBplVQrHfugz+XxK7Aa5
WqwRinPKKz5kfac/AXqvVc920JbOk0PtolAduXFB8PLvoCkysjPXVlbd8GB2vye88GnnjL/Rgxj7
BRJyBjoxq7ADd/t1+hJf63m0nvnzlcLBOQsJl0LroOL0w3IZ5B686FlLCwnvUgQggWy4C1yLTjbF
djm44zxEyXb2PlEo5Pc9uPHd9vggLOS6+BHSaDTgfWDvcwy8aR7LAOLR51affr5GAIuuK8ukNsrz
Z+O4Sc5Gi1WFQ7wcdTq6VaTyccFNguYk/2kkFsgO5BfJCuf8IQFGAijoQQE6V4Czy2FR4dYmSxCI
nnR8LKYk/jKvcaNL+OQHsyWgmftYGvKeKGQIAyVNbo6k6jC+6/qRfhm9BYIYrEZBAOA4bWaNkYCB
zau4xGVKDC4MdR9K695wiLa49antO2UuTQyArAieV7uAG63lpGZ8/BnRhOpu1QSoxmKll6gbTtxV
tcp+1AK6btonR4zTinHNnh4n8Wsrd8C7HADR1+jr3QNWDWxEjEDNxDh7JcKH625h/dHDkdfpgGCN
gjXtJ3PQN4fWnRgX8RXYeoF6fEHGtpfP7zsWHdSqx7IYvPHRLE/kzWYS1DdPj3DVOkPuRrXWk3yc
0xOWx77YXV1NX5bgGol50tV35AA6BGDsp+hmigsuYp1GQBazPbeZBvq6aKd/NlAAN4aigeiKQ8hk
jUsXPyP7ReERwP3dU79+bPyWAxPOITt8ID2j8s6witX2TIam01RttDgW8C/0hdQn1kTWN9JH+5yS
fr82DzHAxoEMqicCcDByJywl8+MM6U6HsQXwQZS62S2fvEMA1cZ1jnNjb73P9zP5ozEEKlwIViav
rw/3OEJPBwQtiH7Y5OzqCu5sRcw5LrdI/PqC7Zbu6hClcF7G6BIivy3S7JLdvZESOz07EIYmtdHd
Gq5aTZcLoJDIJQweutlvw7t55cthv3hEOFPwC/Q4AVZTPfhvsBCnChyfTr81BhT5P0RO4qv3Wtwd
ZjmPqYd8ySxElussVSO+P5BVPO3Mz7Q59/Y50ePAJkPakOd9qR5bmVGOKconjMYsD5hVfyIYkmu/
m9xjPUEN0qGzgE5bHpag7cHV3N1yRR2UN4VDSl9Gd1VbpT+hEHzCbWd6Gk/m3BPHOYqW8krSn9Wx
4bZmV7v51c715VCHCRu0t8866ApmIwFTJLbKyiINqKJgq39ZhZIPN5awtwpZ1YEEtaqUg9seeboC
fQpIHD/vXMUp/qi3TEFGTrItnJEwahEv+PKAeTlHuL/S5ibCxMP8vL5F3Dljy0kI5odFDgIjJZqe
x9y41RnFluPgWqZHJU2HdL9M6VLUc15NIKEjFXBhac5bbsomP8YcD+hBQseXvPr7gaLI3IYh+GSh
YHUhCZMw1daobXLGIHhYznaf3x78Xkp9wAltmQgI4TxYBVzenjssbn30S+cEYZZbgZ2dmqwF8uZp
n9IDIIvWY7arh0DWHVh19nfVVIkpaDHoOT89G0jkzbVLEUDibcypPfJICXESIG7hoiXOxyQd5kzf
Wt7UzSxbV+sqyaBvtJWKyePJFDIV6ycfhN3DdzdyBUeG/z2H3Sd+jmC23Ftqp/qUMpoinctKcxDy
rYzSUAjFLR7C438nxw5/zkDv6WLnl/1IsnRPA7NhKYZhdbTC5JMFy71aJgmOtyc3Vew3RjCLdUIL
BdEjV06WE7p3z83+2WtrJjwQ1xwYCDxMAmQbvrunqWDJrucStxDQC8FEjNYTtn/IMR1CEL8XB9os
2GjZAOlhgLXOG1wMl0ezNmCOKPDwaUvRVHhLxy+LSpA1YdpJDSWQBUcPNvJWItHGpkIT1HBGDmSe
TpemSP1uAF6kHJmzPornufCSO76cAA2myPK0iwbazNhh3na5l2Kw/tUWrQgaPIyODYeC4sOF9v/+
qPXAof8cdUcX5uzpqeaw0w7xN3gf7PYyD/a3Ce/Z/zbVx/xpyCtmbXJwnFy72816pXdN7EgTPAo6
ziRdKUefSJWrYbkzAnTM5NdFtPC323OgdWz/Sn+bzBePwe/fWJmkGYl7KGHXCyi051HZl3kZcX0m
gtN7impQpOhdV4UqAtHAw6jatSmf77tPkdGfMPoodclpvOGAelju43kxPdpV4J55qzDDiBtPhU/R
pMnwbhEGDcxqWaTdNDMj6MLferdIpqMtX25biYIVS+r2XlbV4I1C+HrPM7E16jtMtFPQTiiE4J94
gLzZRk4f8tMrPUJffJTnxdROtLp5fZDBOTKAXO4qiRYny14MhgTzTRn7Sli0WSlabDCTYfs78IEt
UP46WZQhO5+BYaPgqbGssAAGag2ndG335AcXwAHjLWIGs6FtjWCwPw8GnrjjWVxDpKROCWKgzkFI
dYn1tyAFANDnaD69BGE5i57r/IMwkrSDOUkEpfclqIIV3xCULa5OPzBi4G4dyhraDF4dWPkWVUU1
MxhCrRKZxRSV4mwW9PrfnQU6D36g1mmbmihWDXtsFwXcUqHkxPGvwa49ww4LdxIVaWKtVUM8G1c0
2SiohVcwrIj3UQekyLv6jLTHObwmfuPU//jesduS9iBVAAt89gzrwY8RuND1TtEZXLXaZj/cVIoW
zqBozMJUELWjy5MkaOyk92i2ChuWcMICGV26H/YOyQjJnoEvZsBQdpw5aen0gBUG0AzPlEgJDChv
KHCc/LyNFrqn/zbDnOE0fFKKIgfcXlNahX1NvEXlPWVTPEjKu+Ak42krBFVzbL4qlYSO/62gHpv+
u0wh/a5F6XZsR6diYZt92Kut5+OzxsjUW3VrL462Qt4z3RHjtFvF1mfxNagQBSCfnPKf+1gtCG6Z
xG9bHNkc+NRry3KVp7Ykv8xzBzCTvDeAKHcYmxj6D5UCb1fV4L0uS+gRQOhN23oPe+/wYVzhsWG1
YpMnLA5dVwktLGZywArletpW/86R+DTta48WOzpC5J7fTwflWGpSSydi3hqbrKk2t2BFiSoHuz1K
+Uc9Noz5Hlo7ziO99BuJowVS2lpvLvg3BqMS8PVyT2xH/MHfXB93iVSdsE8SsrIU3PWzpDp2CC1s
Gpq6t0xrOSC12kQ3SjXVWXQK3qqWfNL8IUqtwFFMAhKZTcJQv5dQ7dkR49vxCeQ+9KmhXkxJXYiZ
c+3QXHMFvT4ReUu5aFsPPL4/EB5km9li9fybffsdo7WTaGdem/Z0H/SwkvAGpzWT23vcdLlOAU5Q
E4JkWpjf18UZZG8/CfitgMM+QdHFYFPdtg5VLKIPCsuVT+oRrZ15kUY62JGlYr0vUzcQG/8VwJlP
EJtPPFQqWy0dujfPIC3m4Lrq+LbkMSIg0ub2oxQvK1nDtId2pSyt5gyKgHkOmiI8QcKgeNUHxWIT
BNata3sAEYnC97QRiEBPw6DCQG+QyKldL6JLX+sOcwgW7N0oiNL2PArqwY/JnqeQ3GE767BgKLjg
c6ooEwHSXSnwg4IOhtIzL+HGmbeGCD4mFTlBsMGR44GylKXwwhDkqdcA2rbPaqC4T6gt4U2Uv5Fe
37aSDf7nmpHTv+EfMsprO+7g7xN15Ldzzt/l7uPEVISMIz5ajSZwLWQp9DzX4M8AXBydbSMT3w1h
2+NAcYSFLeY+ALpkbOkFIeZCr5PFL46Hy7nzuuJGoyHU7dn+CpMf1MRqNqcOVXT33R2Cs/x64MIu
xHOAIwHrLd1EoE5C6lXqKDZtNFeELeTUsHh9qQN5kbpM6F3Z42A5kHu5iwhQSIYlHHywXecDE/70
Birt/+PhIe0E3tuoM15+KmwiNZBd8cO4nTV5sH79Zjymk5KdGew1BdAoqqAGGIips7r0xeTSaVoS
VEtDOev7nQ9RWdKrWVQ41SMDcMGkgefs8hNfc4td5TCxbIIG/QI1qj/XmO4sODCy8gBNNvcM1AoF
VJtNnZYQyaO1SBE76wrxNnI3SpbkgW8egFWyFA6i+obeeKYvKJuhu4btjtSZm9Y2VbI4TBbOP0V/
vRZuT3qQJpS3Dau6+95NFXOfLyNOZpXHWKk+xjX4u2+R7bAkPm1o71JmKukQz7muLYJsbZZFadie
hLMscshTeE3f2gvjx705PEAo7dF7N/izVfzenagXOJVY5Vo2NkuLwdg1uutY3OtUrj2TfAFhoYXG
nPnyEfWjI8V8coj0EWpT1JZw2ZOfznV5Ys/nuUTZ+7UESVBqE4zJOW2xPcuwFCemd5EktnXWE8Jo
CYr6RnJsHvjubEBRNABaDBKciH9t9B1+0RfZAExCP7aKIOoIzYedNGRdcyRNFbNYNgnCszlfSoqX
uNk0aE29wnKpXlO9SccHlsas8C9OW++s3LmX1ML6Bd/tzDJSBth++TDQBCpQXmXY5amymPjyKt36
Wcy5ruQW2bOkCVpvKHsdNPerJvytV8sO0O6S+Ycqhx7NYln0W6XWMC5UKaHHTR53dflvoDt24Mxv
8rQ1NUkAfV2ZfdhorMqa1xjBkitsHzCq1EpZLV9gtERI7H/sCIWBxbak0hGYed66+zACanFm0fZr
ISyFDVJ3mImjQnFlS1M7ebQALxFL/TL11xRFb+zib2+x+6lXBxbZZD8O547NIgxEqY9sQvm/TNhp
3yk4aEA1T7GpteJ0sJVRR4bt2tfDq9/VX5UZ+CZXezfrWs4S0epp6B5dZdCZaPE8S2qNslCmHQCs
3KJOfjM0x6meWx6W+25DdsFbFrDauis4yeliFMIUWAlbGgb0uo/jHTX89ferjP3SdbOJVK3CGFdw
KCTBC8xhwoDY5POA0LIioTRCc9ndNvponAoOipQIQQZEg723JFR+T2Ik0Av+mDO2I+d4kuWzywb2
gk2bLUw0VlSsBM7Sz0q94jqsSU+3VL/pORBaCNswLzWgspcnPEaK4+JktBgqtYBv47q0+uK3QAGF
lbi/q41uz4GUV5OrRVFU07ANF0zgFrLaZ7UNSkYwoXJosGSsewaj9kNOi3jZc98NLxW46t1INhLp
OE0zHwQnGFBqs2a7a7nUrkOJOcMMLOLKXh8mpK/yE9H78Ia4So2OKxmtjI7I1uqgiY/mlZ5zGlcU
wtY2GUW/kh+SyMYKqEblK1ab9vCyZupiwBrZfVpdiNwRkCU+Ek2ykf3/OrEQDLwLpGeFcuACiXEx
USTa7xbbkYtBUP63m/jKmaf2UUOE2Y6aerrwdifxOsQpW1E+FTbj0pE+1dgt29qhA+tc/66nM/jy
oSU1NhTq/gokjzxIAK1RB6NCxQnX6jdrQ2dGq0ASEEKh6Jl8GRjijmGDw4iZDRXfyJYHfGmaoQ/s
OpbSATBF11gABSUp5hhSzxRaOTUqV+0Ti4V1TWK1//KKYua9vnXJCWGK950p9uLaWhmiCM9Gw5zr
WMF096gmV1RIRiQOFxseuzQkVqB2oYa7YJdp8FGKQENvZpLSsJ09plDqEXW5HtKu58kfsHnowR/+
hA==
`protect end_protected
| gpl-3.0 | ffc6bf590751f35f51bbb2c3eab4a125 | 0.922494 | 1.935553 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/hdl/design_SWandHW_standalone_v2.vhd | 2 | 98,911 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Fri Sep 02 01:29:52 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SWandHW_standalone_v2.bd
--Design : design_SWandHW_standalone_v2
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_L3FSAT is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_L3FSAT;
architecture STRUCTURE of m00_couplers_imp_L3FSAT is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1HPF2ZR is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1HPF2ZR;
architecture STRUCTURE of m01_couplers_imp_1HPF2ZR is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_165G178 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_165G178;
architecture STRUCTURE of s00_couplers_imp_165G178 is
component design_SWandHW_standalone_v2_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_SWandHW_standalone_v2_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_SWandHW_standalone_v2_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone_v2_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_SWandHW_standalone_v2_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_SWandHW_standalone_v2_processing_system7_0_axi_periph_0 is
component design_SWandHW_standalone_v2_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component design_SWandHW_standalone_v2_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_processing_system7_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_processing_system7_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_processing_system7_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_processing_system7_0_axi_periph_WREADY <= M01_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_L3FSAT
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1HPF2ZR
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m01_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m01_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_165G178
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component design_SWandHW_standalone_v2_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(5 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(5 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(5 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(5 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone_v2 is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
btns_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_SWandHW_standalone_v2 : entity is "design_SWandHW_standalone_v2,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_SWandHW_standalone_v2,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=10,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=4,maxHierDepth=0,da_axi4_cnt=2,da_board_cnt=1,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_SWandHW_standalone_v2 : entity is "design_SWandHW_standalone_v2.hwdef";
end design_SWandHW_standalone_v2;
architecture STRUCTURE of design_SWandHW_standalone_v2 is
component design_SWandHW_standalone_v2_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_SWandHW_standalone_v2_processing_system7_0_0;
component design_SWandHW_standalone_v2_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SWandHW_standalone_v2_axi_gpio_0_0;
component design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0;
component design_SWandHW_standalone_v2_ANN_0_0 is
port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC
);
end component design_SWandHW_standalone_v2_ANN_0_0;
signal ANN_0_interrupt : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_gpio_0_GPIO_TRI_I(3 downto 0) <= btns_4bits_tri_i(3 downto 0);
ANN_0: component design_SWandHW_standalone_v2_ANN_0_0
port map (
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_processing_system7_0_100M_peripheral_aresetn(0),
interrupt => ANN_0_interrupt,
s_axi_AXILiteS_ARADDR(6 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(6 downto 0),
s_axi_AXILiteS_ARREADY => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_AXILiteS_ARVALID => processing_system7_0_axi_periph_M01_AXI_ARVALID,
s_axi_AXILiteS_AWADDR(6 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(6 downto 0),
s_axi_AXILiteS_AWREADY => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_AXILiteS_AWVALID => processing_system7_0_axi_periph_M01_AXI_AWVALID,
s_axi_AXILiteS_BREADY => processing_system7_0_axi_periph_M01_AXI_BREADY,
s_axi_AXILiteS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_AXILiteS_BVALID => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_AXILiteS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_AXILiteS_RREADY => processing_system7_0_axi_periph_M01_AXI_RREADY,
s_axi_AXILiteS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_AXILiteS_RVALID => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_AXILiteS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_AXILiteS_WREADY => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_AXILiteS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_AXILiteS_WVALID => processing_system7_0_axi_periph_M01_AXI_WVALID
);
axi_gpio_0: component design_SWandHW_standalone_v2_axi_gpio_0_0
port map (
gpio_io_i(3 downto 0) => axi_gpio_0_GPIO_TRI_I(3 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
processing_system7_0: component design_SWandHW_standalone_v2_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => ANN_0_interrupt,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_SWandHW_standalone_v2_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_SWandHW_standalone_v2_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
| gpl-3.0 | 4ee12650c6a5bc3d6904762b0db12213 | 0.685202 | 2.828938 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_mux_4to1_sel2_32_1.vhd | 3 | 1,622 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity feedforward_mux_4to1_sel2_32_1 is
generic (
ID :integer := 0;
NUM_STAGE :integer := 1;
din1_WIDTH :integer := 32;
din2_WIDTH :integer := 32;
din3_WIDTH :integer := 32;
din4_WIDTH :integer := 32;
din5_WIDTH :integer := 32;
dout_WIDTH :integer := 32);
port (
din1 :in std_logic_vector(31 downto 0);
din2 :in std_logic_vector(31 downto 0);
din3 :in std_logic_vector(31 downto 0);
din4 :in std_logic_vector(31 downto 0);
din5 :in std_logic_vector(1 downto 0);
dout :out std_logic_vector(31 downto 0));
end entity;
architecture rtl of feedforward_mux_4to1_sel2_32_1 is
-- puts internal signals
signal sel : std_logic_vector(1 downto 0);
-- level 1 signals
signal mux_1_0 : std_logic_vector(31 downto 0);
signal mux_1_1 : std_logic_vector(31 downto 0);
-- level 2 signals
signal mux_2_0 : std_logic_vector(31 downto 0);
begin
sel <= din5;
-- Generate level 1 logic
mux_1_0 <= din1 when sel(0) = '0' else din2;
mux_1_1 <= din3 when sel(0) = '0' else din4;
-- Generate level 2 logic
mux_2_0 <= mux_1_0 when sel(1) = '0' else mux_1_1;
-- output logic
dout <= mux_2_0;
end architecture;
| gpl-3.0 | 85b106ae747510a4d7aa3e140d987dff | 0.562885 | 3.174168 | false | false | false | false |
hoglet67/AtomVGAWing | src/DCM_A.vhd | 1 | 2,523 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.4
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM_A.vhd
-- /___/ /\ Timestamp : 03/01/2013 20:52:34
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/dmb/papilio/projects/VGATest/ipcore_dir/DCM_A.xaw -st DCM_A.vhd
--Design Name: DCM_A
--Device: xc3s500e-5vq100
--
-- Module DCM_A
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.06 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.45 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM_A is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_A;
architecture BEHAVIORAL of DCM_A is
signal CLKFX_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 18,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IN,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>open,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| gpl-3.0 | b39b9fe5d22d6571e6cf992b2644313e | 0.467697 | 3.754464 | false | false | false | false |
makestuff/spi-talk | templates/eppa/vhdl/top_level.vhdl | 1 | 5,826 | --
-- Copyright (C) 2009-2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
sysClk_in : in std_logic; -- 50MHz system clock
-- EPP interface -----------------------------------------------------------------------------
eppData_io : inout std_logic_vector(7 downto 0); -- bidirectional 8-bit data bus
eppAddrStb_in : in std_logic; -- active-low asynchronous address strobe
eppDataStb_in : in std_logic; -- active-low asynchronous data strobe
eppWrite_in : in std_logic; -- read='1'; write='0'
eppWait_out : out std_logic -- active-low asynchronous wait signal
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- SPI signals
signal spiCS : std_logic_vector(NUM_DEVS-1 downto 0);
signal spiClk : std_logic;
signal spiMOSI : std_logic;
signal spiMISO : std_logic;
--signal sendData : std_logic_vector(3 downto 0);
--signal recvData : std_logic_vector(3 downto 0);
-- Component from the Altera library to give application access to the config flash.
component altserial_flash_loader
generic (
enable_quad_spi_support : natural;
enable_shared_access : string;
enhanced_mode : natural;
intended_device_family : string;
lpm_type : string
);
port (
dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
data0out : out std_logic;
--data_in : in std_logic_vector(3 downto 0);
--data_oe : in std_logic_vector(3 downto 0);
--data_out : out std_logic_vector(3 downto 0);
asmi_access_request : out std_logic;
asmi_access_granted : in std_logic;
noe : in std_logic
);
end component;
begin
-- CommFPGA module
comm_fpga_epp : entity work.comm_fpga_epp
port map(
clk_in => sysClk_in,
reset_in => '0',
reset_out => open,
-- EPP interface
eppData_io => eppData_io,
eppAddrStb_in => eppAddrStb_in,
eppDataStb_in => eppDataStb_in,
eppWrite_in => eppWrite_in,
eppWait_out => eppWait_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => sysClk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk,
spiData_out => spiMOSI,
spiData_in => spiMISO,
spiCS_out => spiCS
);
-- Allow application access to config flash
spi_access : altserial_flash_loader
generic map (
enable_quad_spi_support => 0,
enable_shared_access => "ON",
enhanced_mode => 1,
intended_device_family => "Cyclone II",
lpm_type => "altserial_flash_loader"
)
port map (
dclkin => spiClk,
scein => spiCS(0),
sdoin => spiMOSI,
data0out => spiMISO,
--data_in => sendData,
--data_oe => "1101", -- drive D3, D2 & D0
--data_out => recvData,
asmi_access_request => open, -- ignore requests
asmi_access_granted => '0', -- application always has control
noe => '0' -- always drive
);
--sendData <= "111" & spiMOSI;
--spiMISO <= recvData(1);
end architecture;
| gpl-3.0 | d985ee3321184eb762c5efa5e2d0ec61 | 0.579815 | 3.565483 | false | false | false | false |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/sim_tbs/ANN.autotb.vhd | 1 | 43,549 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity apatb_ANN_top is
generic (
AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns;
AUTOTB_TVIN_P_mode : STRING := "./c.ANN.autotvin_P_mode.dat";
AUTOTB_TVIN_P_index1 : STRING := "./c.ANN.autotvin_P_index1.dat";
AUTOTB_TVIN_P_index2 : STRING := "./c.ANN.autotvin_P_index2.dat";
AUTOTB_TVIN_P_intIn_index3 : STRING := "./c.ANN.autotvin_P_intIn_index3.dat";
AUTOTB_TVIN_P_floatIn : STRING := "./c.ANN.autotvin_P_floatIn.dat";
AUTOTB_TVIN_P_mode_out_wrapc : STRING := "./rtl.ANN.autotvin_P_mode.dat";
AUTOTB_TVIN_P_index1_out_wrapc : STRING := "./rtl.ANN.autotvin_P_index1.dat";
AUTOTB_TVIN_P_index2_out_wrapc : STRING := "./rtl.ANN.autotvin_P_index2.dat";
AUTOTB_TVIN_P_intIn_index3_out_wrapc : STRING := "./rtl.ANN.autotvin_P_intIn_index3.dat";
AUTOTB_TVIN_P_floatIn_out_wrapc : STRING := "./rtl.ANN.autotvin_P_floatIn.dat";
AUTOTB_TVOUT_ap_return : STRING := "./c.ANN.autotvout_ap_return.dat";
AUTOTB_TVOUT_ap_return_out_wrapc : STRING := "./impl_rtl.ANN.autotvout_ap_return.dat";
AUTOTB_LAT_RESULT_FILE : STRING := "ANN.result.lat.rb";
AUTOTB_PER_RESULT_TRANS_FILE : STRING := "ANN.performance.result.transaction.xml";
LENGTH_P_mode : INTEGER := 1;
LENGTH_P_index1 : INTEGER := 1;
LENGTH_P_index2 : INTEGER := 1;
LENGTH_P_intIn_index3 : INTEGER := 1;
LENGTH_P_floatIn : INTEGER := 1;
LENGTH_ap_return : INTEGER := 1;
AUTOTB_TRANSACTION_NUM : INTEGER := 265
);
end apatb_ANN_top;
architecture behav of apatb_ANN_top is
signal AESL_clock : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal start : STD_LOGIC := '0';
signal ce : STD_LOGIC;
signal continue : STD_LOGIC := '0';
signal AESL_reset : STD_LOGIC := '0';
signal AESL_start : STD_LOGIC := '0';
signal AESL_ce : STD_LOGIC := '0';
signal AESL_continue : STD_LOGIC := '0';
signal AESL_ready : STD_LOGIC := '0';
signal AESL_idle : STD_LOGIC := '0';
signal AESL_done : STD_LOGIC := '0';
signal AESL_done_delay : STD_LOGIC := '0';
signal AESL_done_delay2 : STD_LOGIC := '0';
signal AESL_ready_delay : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
signal ready_wire : STD_LOGIC := '0';
signal AXILiteS_AWADDR: STD_LOGIC_VECTOR (6 DOWNTO 0);
signal AXILiteS_AWVALID: STD_LOGIC;
signal AXILiteS_AWREADY: STD_LOGIC;
signal AXILiteS_WVALID: STD_LOGIC;
signal AXILiteS_WREADY: STD_LOGIC;
signal AXILiteS_WDATA: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal AXILiteS_WSTRB: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal AXILiteS_ARADDR: STD_LOGIC_VECTOR (6 DOWNTO 0);
signal AXILiteS_ARVALID: STD_LOGIC;
signal AXILiteS_ARREADY: STD_LOGIC;
signal AXILiteS_RVALID: STD_LOGIC;
signal AXILiteS_RREADY: STD_LOGIC;
signal AXILiteS_RDATA: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal AXILiteS_RRESP: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal AXILiteS_BVALID: STD_LOGIC;
signal AXILiteS_BREADY: STD_LOGIC;
signal AXILiteS_BRESP: STD_LOGIC_VECTOR (1 DOWNTO 0);
signal ap_clk : STD_LOGIC;
signal ap_rst_n : STD_LOGIC;
signal interrupt : STD_LOGIC;
signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal ready_initial : STD_LOGIC;
signal ready_initial_n : STD_LOGIC;
signal ready_last_n : STD_LOGIC;
signal ready_delay_last_n : STD_LOGIC;
signal done_delay_last_n : STD_LOGIC;
signal interface_done : STD_LOGIC := '0';
-- Subtype for random state number, to prevent confusing it with true integers
-- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines
subtype T_RANDINT is integer range 1 to integer'high;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
shared variable AESL_mLatCnterIn : latency_record;
shared variable AESL_mLatCnterOut : latency_record;
shared variable AESL_mLatCnterIn_addr : INTEGER;
shared variable AESL_mLatCnterOut_addr : INTEGER;
shared variable AESL_clk_counter : INTEGER;
signal reported_stuck : STD_LOGIC := '0';
shared variable reported_stuck_cnt : INTEGER := 0;
component ANN is
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
interrupt : OUT STD_LOGIC);
end component;
-- The signal of port P_mode
shared variable AESL_REG_P_mode : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port P_index1
shared variable AESL_REG_P_index1 : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port P_index2
shared variable AESL_REG_P_index2 : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port P_intIn_index3
shared variable AESL_REG_P_intIn_index3 : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
-- The signal of port P_floatIn
shared variable AESL_REG_P_floatIn : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal AESL_slave_output_done : STD_LOGIC;
signal AESL_slave_start : STD_LOGIC;
signal AESL_slave_write_start_in : STD_LOGIC;
signal AESL_slave_write_start_finish : STD_LOGIC;
signal AESL_slave_ready : STD_LOGIC;
signal slave_start_status : STD_LOGIC := '0';
signal start_rise : STD_LOGIC := '0';
signal ready_rise : STD_LOGIC := '0';
signal slave_done_status : STD_LOGIC := '0';
signal AXILiteS_read_data_finish : STD_LOGIC;
signal AXILiteS_write_data_finish : STD_LOGIC;
component AESL_AXI_SLAVE_AXILiteS is
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_AWADDR : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_AWVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_AWREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_WVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_WREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_WDATA : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_WSTRB : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_ARADDR : OUT STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_ARVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_ARREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_RVALID : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_RREADY : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_RDATA : IN STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_RRESP : IN STD_LOGIC_VECTOR;
TRAN_s_axi_AXILiteS_BVALID : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_BREADY : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_BRESP : IN STD_LOGIC_VECTOR;
TRAN_AXILiteS_read_data_finish : OUT STD_LOGIC;
TRAN_AXILiteS_write_data_finish : OUT STD_LOGIC;
TRAN_AXILiteS_ready_out : OUT STD_LOGIC;
TRAN_AXILiteS_ready_in : IN STD_LOGIC;
TRAN_AXILiteS_done_out : OUT STD_LOGIC;
TRAN_AXILiteS_idle_out : OUT STD_LOGIC;
TRAN_AXILiteS_write_start_in : IN STD_LOGIC;
TRAN_AXILiteS_write_start_finish : OUT STD_LOGIC;
TRAN_AXILiteS_transaction_done_in : IN STD_LOGIC;
TRAN_AXILiteS_interrupt : IN STD_LOGIC;
TRAN_AXILiteS_start_in : IN STD_LOGIC
);
end component;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_str_dec2int (RHS : STRING) return INTEGER is
variable ret : integer;
variable idx : integer := 1;
begin
ret := 0;
while true loop
case RHS(idx) is
when '0' => ret := ret * 10 + 0;
when '1' => ret := ret * 10 + 1;
when '2' => ret := ret * 10 + 2;
when '3' => ret := ret * 10 + 3;
when '4' => ret := ret * 10 + 4;
when '5' => ret := ret * 10 + 5;
when '6' => ret := ret * 10 + 6;
when '7' => ret := ret * 10 + 7;
when '8' => ret := ret * 10 + 8;
when '9' => ret := ret * 10 + 9;
when ' ' => return ret;
when others => report "Wrong dec char " & RHS(idx); return ret;
end case;
idx := idx + 1;
end loop;
return ret;
end esl_str_dec2int;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
-- purpose: initialise the random state variable based on an integer seed
function init_rand(seed : integer) return T_RANDINT is
variable result : T_RANDINT;
begin
-- If the seed is smaller than the minimum value of the random state variable, use the minimum value
if seed < T_RANDINT'low then
result := T_RANDINT'low;
-- If the seed is larger than the maximum value of the random state variable, use the maximum value
elsif seed > T_RANDINT'high then
result := T_RANDINT'high;
-- If the seed is within the range of the random state variable, just use the seed
else
result := seed;
end if;
-- Return the result
return result;
end init_rand;
-- purpose: generate a random integer between min and max limits
procedure rand_int(variable rand : inout T_RANDINT;
constant minval : in integer;
constant maxval : in integer;
variable result : out integer
) is
variable k, q : integer;
variable real_rand : real;
variable res : integer;
begin
-- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE
-- Based on an example from Numerical Recipes in C, 2nd Edition, page 279
k := rand/127773;
q := 16807*(rand-k*127773)-2836*k;
if q < 0 then
q := q + 2147483647;
end if;
rand := init_rand(q);
-- Convert this integer to a real number in the range 0 to 1
real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low);
-- Convert this real number to an integer in the range minval to maxval
-- The +1 and -0.5 are to get equal probability of minval and maxval as other values
res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval;
-- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this
if res < minval then
res := minval;
elsif res > maxval then
res := maxval;
end if;
-- assign output
result := res;
end rand_int;
function esl_equal_std_lv (lv1 : STD_LOGIC_VECTOR; lv2 : STD_LOGIC_VECTOR) return BOOLEAN is
variable len : INTEGER;
variable i : INTEGER;
begin
if (lv1'length > lv2'length) then
len := lv2'length;
for i in lv1'length - 1 downto lv2'length loop
if(lv1(i) = '1') then
return false;
end if;
end loop;
else
len := lv1'length;
for i in lv2'length - 1 downto lv1'length loop
if(lv2(i) = '1') then
return false;
end if;
end loop;
end if;
for i in len - 1 downto 0 loop
if (lv1(i) = '1' and lv2(i) /= '1') or (lv1(i) = '0' and lv2(i) /= '0') then
return false;
end if;
end loop;
return true;
end function;
procedure post_check (file fp1 : TEXT; file fp2 : TEXT) is
variable token_line1 : LINE;
variable token_line2 : LINE;
variable token1 : STRING(1 to 200);
variable token2 : STRING(1 to 200);
variable golden : STD_LOGIC_VECTOR(199 downto 0);
variable result : STD_LOGIC_VECTOR(199 downto 0);
variable l1 : INTEGER;
variable l2 : INTEGER;
begin
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
if(token1(1 to 13) /= "[[[runtime]]]" or token2(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
while(token1(1 to 14) /= "[[[/runtime]]]" and token2(1 to 14) /= "[[[/runtime]]]") loop
if(token1(1 to 15) /= "[[transaction]]" and token2(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1); -- Skip transaction number
esl_read_token(fp2, token_line2, token2); -- Skip transaction number
esl_read_token(fp1, token_line1, token1, l1);
esl_read_token(fp2, token_line2, token2, l2);
while(token1(1 to 16) /= "[[/transaction]]" and token2(1 to 16) /= "[[/transaction]]") loop
golden := esl_str2lv_hex(token1, 200 );
result := esl_str2lv_hex(token2, 200 );
if(esl_equal_std_lv(golden, result) = false) then
report token1(1 to l1) & " (expected) vs. " & token2(1 to l2) & " (actual) - mismatch";
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
end loop;
esl_read_token(fp1, token_line1, token1);
esl_read_token(fp2, token_line2, token2);
end loop;
end procedure post_check;
begin
AESL_inst_ANN : ANN port map (
s_axi_AXILiteS_AWADDR => AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID => AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY => AXILiteS_AWREADY,
s_axi_AXILiteS_WVALID => AXILiteS_WVALID,
s_axi_AXILiteS_WREADY => AXILiteS_WREADY,
s_axi_AXILiteS_WDATA => AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB => AXILiteS_WSTRB,
s_axi_AXILiteS_ARADDR => AXILiteS_ARADDR,
s_axi_AXILiteS_ARVALID => AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY => AXILiteS_ARREADY,
s_axi_AXILiteS_RVALID => AXILiteS_RVALID,
s_axi_AXILiteS_RREADY => AXILiteS_RREADY,
s_axi_AXILiteS_RDATA => AXILiteS_RDATA,
s_axi_AXILiteS_RRESP => AXILiteS_RRESP,
s_axi_AXILiteS_BVALID => AXILiteS_BVALID,
s_axi_AXILiteS_BREADY => AXILiteS_BREADY,
s_axi_AXILiteS_BRESP => AXILiteS_BRESP,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt
);
-- Assignment for control signal
ap_clk <= AESL_clock;
ap_rst_n <= AESL_reset;
AESL_reset <= rst;
AESL_start <= start;
AESL_ce <= ce;
AESL_continue <= continue;
AESL_slave_write_start_in <= slave_start_status and AXILiteS_write_data_finish;
AESL_slave_start <= AESL_slave_write_start_finish;
AESL_done <= slave_done_status and AXILiteS_read_data_finish;
slave_start_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
slave_start_status <= '1';
else
if (AESL_start = '1' ) then
start_rise <= '1';
end if;
if (start_rise = '1' and AESL_done = '1' ) then
slave_start_status <= '1';
end if;
if (AESL_slave_write_start_in = '1') then
slave_start_status <= '0';
start_rise <= '0';
end if;
end if;
end if;
end process;
slave_ready_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_slave_ready <= '0';
ready_rise <= '0';
else
if (AESL_ready = '1' ) then
ready_rise <= '1';
end if;
if (ready_rise = '1' and AESL_done_delay = '1' ) then
AESL_slave_ready <= '1';
end if;
if (AESL_slave_ready = '1') then
AESL_slave_ready <= '0';
ready_rise <= '0';
end if;
end if;
end if;
end process;
slave_done_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if (AESL_done = '1') then
slave_done_status <= '0';
elsif (AESL_slave_output_done = '1' ) then
slave_done_status <= '1';
end if;
end if;
end process;
AESL_axi_slave_inst_AXILiteS : AESL_AXI_SLAVE_AXILiteS port map (
clk => AESL_clock,
reset => AESL_reset,
TRAN_s_axi_AXILiteS_AWADDR => AXILiteS_AWADDR,
TRAN_s_axi_AXILiteS_AWVALID => AXILiteS_AWVALID,
TRAN_s_axi_AXILiteS_AWREADY => AXILiteS_AWREADY,
TRAN_s_axi_AXILiteS_WVALID => AXILiteS_WVALID,
TRAN_s_axi_AXILiteS_WREADY => AXILiteS_WREADY,
TRAN_s_axi_AXILiteS_WDATA => AXILiteS_WDATA,
TRAN_s_axi_AXILiteS_WSTRB => AXILiteS_WSTRB,
TRAN_s_axi_AXILiteS_ARADDR => AXILiteS_ARADDR,
TRAN_s_axi_AXILiteS_ARVALID => AXILiteS_ARVALID,
TRAN_s_axi_AXILiteS_ARREADY => AXILiteS_ARREADY,
TRAN_s_axi_AXILiteS_RVALID => AXILiteS_RVALID,
TRAN_s_axi_AXILiteS_RREADY => AXILiteS_RREADY,
TRAN_s_axi_AXILiteS_RDATA => AXILiteS_RDATA,
TRAN_s_axi_AXILiteS_RRESP => AXILiteS_RRESP,
TRAN_s_axi_AXILiteS_BVALID => AXILiteS_BVALID,
TRAN_s_axi_AXILiteS_BREADY => AXILiteS_BREADY,
TRAN_s_axi_AXILiteS_BRESP => AXILiteS_BRESP,
TRAN_AXILiteS_read_data_finish => AXILiteS_read_data_finish,
TRAN_AXILiteS_write_data_finish => AXILiteS_write_data_finish,
TRAN_AXILiteS_ready_out => AESL_ready,
TRAN_AXILiteS_ready_in => AESL_slave_ready,
TRAN_AXILiteS_done_out => AESL_slave_output_done,
TRAN_AXILiteS_idle_out => AESL_idle,
TRAN_AXILiteS_write_start_in => AESL_slave_write_start_in,
TRAN_AXILiteS_write_start_finish => AESL_slave_write_start_finish,
TRAN_AXILiteS_transaction_done_in => AESL_done_delay,
TRAN_AXILiteS_interrupt => interrupt,
TRAN_AXILiteS_start_in => AESL_slave_start
);
-- Write "[[[runtime]]]" and "[[[/runtime]]]" for output transactor
write_output_transactor_ap_return_runtime_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
begin
file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[runtime]]]"));
writeline(fp, token_line);
file_close(fp);
while done_cnt /= AUTOTB_TRANSACTION_NUM loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line, string'("[[[/runtime]]]"));
writeline(fp, token_line);
file_close(fp);
wait;
end process;
generate_ready_cnt_proc : process(ready_initial, AESL_clock)
begin
if(AESL_clock'event and AESL_clock = '0') then
if(ready_initial = '1') then
ready_cnt <= conv_std_logic_vector(1, 32);
end if;
elsif(AESL_clock'event and AESL_clock = '1') then
if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_ready = '1') then
ready_cnt <= ready_cnt + 1;
end if;
end if;
end if;
end process;
generate_done_cnt_proc : process(AESL_reset, AESL_clock)
begin
if(AESL_reset = '0') then
done_cnt <= (others => '0');
elsif(AESL_clock'event and AESL_clock = '1') then
if(done_cnt /= AUTOTB_TRANSACTION_NUM) then
if(AESL_done = '1') then
done_cnt <= done_cnt + 1;
end if;
end if;
end if;
end process;
generate_sim_done_proc : process
file fp1 : TEXT;
file fp2 : TEXT;
variable fstatus1 : FILE_OPEN_STATUS;
variable fstatus2 : FILE_OPEN_STATUS;
begin
while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
wait until AESL_clock'event and AESL_clock = '1';
file_open(fstatus1, fp1, "./rtl.ANN.autotvout_ap_return.dat", READ_MODE);
file_open(fstatus2, fp2, "./impl_rtl.ANN.autotvout_ap_return.dat", READ_MODE);
if(fstatus1 /= OPEN_OK) then
assert false report string'("Open file rtl.ANN.autotvout_ap_return.dat failed!!!") severity note;
elsif(fstatus2 /= OPEN_OK) then
assert false report string'("Open file impl_rtl.ANN.autotvout_ap_return.dat failed!!!") severity note;
else
report string'("Comparing rtl.ANN.autotvout_ap_return.dat with impl_rtl.ANN.autotvout_ap_return.dat");
post_check(fp1, fp2);
end if;
file_close(fp1);
file_close(fp2);
report "Simulation Passed.";
assert false report "simulation done!" severity note;
assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure;
wait;
end process;
gen_clock_proc : process
begin
AESL_clock <= '0';
while(true) loop
wait for AUTOTB_CLOCK_PERIOD_DIV2;
AESL_clock <= not AESL_clock;
end loop;
wait;
end process;
gen_reset_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
rst <= '0';
wait for 100 ns;
for i in 1 to 3 loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
rst <= '1';
wait;
end process;
gen_start_proc : process
variable rand : T_RANDINT := init_rand(0);
variable rint : INTEGER;
begin
start <= '0';
ce <= '1';
wait until AESL_reset = '1';
wait until (AESL_clock'event and AESL_clock = '1');
start <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop
wait until (AESL_clock'event and AESL_clock = '1');
if(AESL_ready = '1') then
start <= '0';
start <= '1';
end if;
end loop;
start <= '0';
wait;
end process;
gen_continue_proc : process(AESL_done)
begin
continue <= AESL_done;
end process;
gen_AESL_ready_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_ready_delay <= '0';
else
AESL_ready_delay <= AESL_ready;
end if;
end if;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until AESL_start = '1';
ready_initial <= '1';
wait until AESL_clock'event and AESL_clock = '1';
ready_initial <= '0';
wait;
end process;
ready_last_n_proc : process
begin
ready_last_n <= '1';
while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until AESL_clock'event and AESL_clock = '1';
end loop;
ready_last_n <= '0';
wait;
end process;
gen_ready_delay_n_last_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
ready_delay_last_n <= '0';
else
ready_delay_last_n <= ready_last_n;
end if;
end if;
end process;
ready <= (ready_initial or AESL_ready_delay);
ready_wire <= ready_initial or AESL_ready_delay;
done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1';
gen_done_delay_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_done_delay <= '0';
AESL_done_delay2 <= '0';
else
AESL_done_delay <= AESL_done and done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end if;
end if;
end process;
gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay)
begin
if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_ready_delay;
elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then
interface_done <= AESL_done_delay;
else
interface_done <= '0';
end if;
end process;
gen_clock_counter_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '0') then
if(AESL_reset = '0') then
AESL_clk_counter := 0;
else
AESL_clk_counter := AESL_clk_counter + 1;
end if;
end if;
end process;
gen_mLatcnterout_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_mLatCnterOut_addr := 0;
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ;
reported_stuck_cnt := 0;
else
if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter;
AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1;
reported_stuck <= '0';
end if;
end if;
end if;
end process;
gen_mLatcnterin_proc : process(AESL_clock)
begin
if (AESL_clock'event and AESL_clock = '1') then
if(AESL_reset = '0') then
AESL_mLatCnterIn_addr := 0;
else
if (AESL_slave_write_start_finish = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1) then
AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter;
AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1;
end if;
end if;
end if;
end process;
gen_performance_check_proc : process
variable transaction_counter : INTEGER;
variable i : INTEGER;
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable latthistime : INTEGER;
variable lattotal : INTEGER;
variable latmax : INTEGER;
variable latmin : INTEGER;
variable thrthistime : INTEGER;
variable thrtotal : INTEGER;
variable thrmax : INTEGER;
variable thrmin : INTEGER;
variable lataver : INTEGER;
variable thraver : INTEGER;
type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER;
variable lat_array : latency_record;
variable thr_array : latency_record;
begin
i := 0;
lattotal := 0;
latmax := 0;
latmin := 16#7fffffff#;
lataver := 0;
thrtotal := 0;
thrmax := 0;
thrmin := 16#7fffffff#;
thraver := 0;
wait until (AESL_clock'event and AESL_clock = '1');
wait until (AESL_reset = '1');
while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop
wait until (AESL_clock'event and AESL_clock = '1');
end loop;
wait for 0.001 ns;
for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop
latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i);
lat_array(i) := latthistime;
if (latthistime > latmax) then
latmax := latthistime;
end if;
if (latthistime < latmin) then
latmin := latthistime;
end if;
lattotal := lattotal + latthistime;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrthistime := latthistime;
else
thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i);
end if;
thr_array(i) := thrthistime;
if (thrthistime > thrmax) then
thrmax := thrthistime;
end if;
if (thrthistime < thrmin) then
thrmin := thrthistime;
end if;
thrtotal := thrtotal + thrthistime;
end loop;
lataver := lattotal / AUTOTB_TRANSACTION_NUM;
thraver := thrtotal / AUTOTB_TRANSACTION_NUM;
file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE);
if (fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
if (AUTOTB_TRANSACTION_NUM = 1) then
thrmax := 0;
thrmin := 0;
thraver := 0;
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"');
writeline(fp, token_line);
else
write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(latmax) & '"');
writeline(fp, token_line);
write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(latmin) & '"');
writeline(fp, token_line);
write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(lataver) & '"');
writeline(fp, token_line);
end if;
file_close(fp);
file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note;
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
write(token_line,string'(" latency interval"));
writeline(fp, token_line);
if (AUTOTB_TRANSACTION_NUM = 1) then
i := 0;
thr_array(i) := 0;
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
else
for i in 0 to AESL_mLatCnterOut_addr - 1 loop
write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) );
writeline(fp, token_line);
end loop;
end if;
file_close(fp);
wait;
end process;
end behav;
| gpl-3.0 | 8e35c918eb4cbd520ec1961ffad129d0 | 0.534157 | 3.598793 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd | 24 | 157,786 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
GK+B9PZwAQG0AijumSfbCugpYhcwULsoxpdEe41kJbdOvZ5J1nq4AhWPTePhNLqLZyBbfYmxsIZl
Kzz7NcppbA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Kc9rX2vH3RY42aoriR6ztPTcqZ3ndb7iB1z0rAP/XXc76vu66p6pBS+TY6fgUWjogz4K8V3rQcVk
QhbKnNsq4R85/qIZX/owqI2Xbd/dA/PL7WzHovQfQ2Zbv/FYpOTcbk1GlvA4SP0qUPoC9F172fdR
bmnSOlCifs0w7zFrmVw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
TLARkr6nHml2Oi3n5stw/PPzVB7LbOYkShwuslqxUidwZ+zXMopRNQY5lJiwJLSjHJiRYifmHfrw
1j3pLKHylIJVGwwneKNlQUIEC+wFjTqZ0yAuiOyhJf38AZ+gdgxm2CaJ3fBX7x4vceudOD/tftHy
+O8IILkavSBr/DqYddVCvBGT+au3etiWBzsr8SSEyNG/lJTbDK4JA7vFUA0c+/p8kmR1k7gzgea1
LBaUKnLUiV7JGUwFE/NhXwyQOUCGmglBA06YamX7h1THcGtlLA93Az177ZMGd/ySK/UhnBMGCitu
M+aRnd+ejseJlC/TV/RRTDxx24ieJfkWvHUodw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SOZcfpI9WzYyQTjPteLe53BWFPZc+91kF34keudF0ftzI9AfaU+XvWb6i7/0j9NFuqQKcqrO1mrT
mCJW4XBC6rtaSHo+f93/clBlPzNqgtx36jyVhhwaXJBq8NOhuHgbnb/nCxFVsG94fWluz1T9COXk
viw/Cwn+UZigS75GXwg=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
iag7/uHCfg3dlMRP5oC7s3rpNUzCn0pv+HfRxcgf8SAWmyxvCg2B8CDf9KiNCUewbeMkGKMGe3Tb
R2WV4d/gItKUaNAw4Uf8kShbJmd79axzwnLiskEgzh0j+CUBLA5R5vsCRJG7/bkZDHI/qNavjSAk
CR5yrk9pYg56DPafPJ95uuMckKWjlrj6IWIGVOdp3dHDL4emrILmp4AK+cXS950aFNNLCWzyQKzN
+FlCVg2/0I3FhHgIx3xQ2Dnq1sUKOUKp1ixFXKZ4q4xJYeJTLNIPGu46A8oV/Dt+xgcCjQmID8pi
iLxuw3lWUwdrRNfmEI5YFE1fjCSObi+pLLVLXg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Wo8k9qSNHjnAGR/g/m5L/ddkyNUQ73ZTe5OnVIGlwWehud2ibAyKEn5YmcrbfNYu0YZa7A4HM99Y
Og5OjbEZe16RUiTwAS5/DcFT42yfxzDUFjxNKukT82hs335OEyhTsOjtOrzqBjTumgUGgBJmZRgr
mZ1oABh53+odWx0V2EYwQoXALntoYWhr1xxtglpek43rHi8oau5sK4Tms6Gyqfj7c9WpsIKE37YK
EHC5D7h7fTHJhmXpQyTEwa/W46hwUcSV/ADv1d297c2FRqOHwlURm8vTbqNcrI70Qst5/7vqf2JM
KHfcXGDQ/S5SfZ67IKYlYTnNR7zkgEIdy8goYA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 114672)
`protect data_block
+p6IiOq494xySVwAEUme1GpicgVWFs89D5IanJw/OkkVwMV1NbryRNBWot2FFyqeqxLNnGFA4AWu
AU2xDfDvTiXA0hq3ryDXrOqXfjLuxMfeiA9GUc85VQ/zNgRAFQoTR6PGDDq+rLVcCDXil3NseL9i
p5jnALSn+dJHRhysloOD6RLtRO54zlUWAHE3wZvxQ7TLQRk4QEx+4nq3gpj+1yhXsywZomn7Ia/k
FpOo/nn66pTJ1F3xuRknW7LPd2ejbZiy+80pd6zIfAkAqZ5o2JbJ2DY3CmYFIIGtLQK2vnCoriGB
dt4fkeMnIOGu5hV2xVx6q2qjLfX8Biazi55MfB8VFsRGwg0zJ6/s9RYMmESGBvsP18xmtMX5/IEz
45pL5C4+mdp+FG+y3ubozEsyhHJDYfXpwwKIEg4zybXxJWwRCNFxomYkdUqmw7TkBP5Yrohhk+jH
WA8/zoYb2bHC3mE77ejM8rTYal9HNMToZa9qsMYF6mSraRYjSnkYVwoYFlLDh7wTBQSafsql7mBD
5Cw2DCy3XQzokSdw+yRaLRdrL20oE83HJyXpns2zQAteH3ExY6aHvcCQpQRadTDxBPqadwy57wrL
XsTXXH6HE2XUWqnBRy6NCAQM8a9YpVfwytZODn7zCkvYjaEq4hAjcdkF0XvvhJfIPxdGrmP7OXwa
EdBfyqqivYwf52KW8C4IqEhtoFLcdzEptOEx3Eny0U6NElM5Y4jdUNotdwSgkCU1t3xAIkVggDW1
HXA+XA+jdW8ufTCCFCVKtFrdr38TNu1cXwSODRyc1BMl5YhFdpXCyfeidLEA4uDt+FcLzI1ILMsQ
yWPKzKZNzgZt0lbObs0vLkn5xcgSOLkFb+ZemSY9lAiICs97jFI9fbMF8CYBFr4FkUOssuxgyaf2
ZSjnyNw1WF9l/gtTxspz1vO+m0cWHX1Te8TcHIVmM2Pxt7/I4FR9+ij4O1J2KU6/XPdZQdDOKLZ4
lf7GOdflI0DA+UK0ONwV3XF4JAA9iGy+A4t0R1c8VpBrfQSZIO7cLSgguFclq5KlwsrolXWnG5Md
M0RJD3iYQgfdveFx29CLhfaB+LCJYGYmpxvwFMM6Ltw9kecrKpQ8nxfXD8kJ+BZ6QNrUZdYqLtzt
W5Fatdge3riDKkq3RGEKthrsHRlS9dCMQkPx4dDXFRrPFIzuTSj11qIyLAhgws+47oNjjwJ2V7dU
SYiZ9090zHk/5mwaJH/mmJ6pjy/Ebmaitn493AjQsOFYqt7LRjTakRDeH+80GU9QzK2Q5q7hFhmy
HmwIo9L/QMSqNKqqJhb9iJnSt793PHsn65VCvwDGLxLr4yIZXRdbDUnWYWu8lzeOe1FZszQFTseo
8/UD35VkyJGwYNhTqvazOHtidoHu1Uxj/z+oOa79XTDg29Ez3A4flhZtoWR8Xigv215F0YUSkfTe
lt3WuzVShqpBMvgZqKbI4GEvlYEa4f1N8hRgA8d4Sf5yOl25Kfa5yr61p4o92J+jCPNgSMeHAa7X
HEr5EQjqwEfLZSSty09HeiNKrkZQn+8DO85q5vdYXZ2PjWSXCyeo73UME4l1LCyOFkDPwGvX092K
IBlyxF77zeYdLUenRd0M6Uw/WXY3iioYxxWLzlu3N1493V6lZgYpR4cju2H53PSRjHxxIx9/kF0/
SPyl00EqQU1v50LG9jGPlhnRgrYIM7jMPB6gpxtuHDaMr3YfmIdFWgO4AU5JMYMCFWqltHxBbjpH
w7GiH60UkPmAzK1/NhQjxYfJKBKUVDezLWifHTv7LD/QmMPsLuLPp81i371WPkBEGDSuAAdMmssv
xAQ1dn+OifJbxbw4r8CQ6Kfj5hl+CPN6571eYg8yuzsEcqm2ZJEz/z2dC5OIbGGPyh377ppgB+KJ
YsUGWOOCOMlP6efNOdZNuwqRn6k+dAtnTsCn1ChPJdDWlDTcK8TV/I+jbjZ5QHpw1PoMqUXZdy7m
zYpmNbQsMn+ZW3Mczd6d4onIDLJ/4SIR3FY61x7wUi5pr5m1LDIj7j+d8CnZzMOEi5fYqKdn2JCg
fiGG300wfAE/W/gVXKERiBvAIcotA+Jf5g7HV158RoPrJQczLuvBbgm5/L09wxFLA6VZGLfBUFdq
8xk9lKNtkf0aJzg5U1i/mlO9YCKPg6bsqE2jxNWy+9wJyp2YnPBq9FTTU5dNSXzcam3DswYDE49z
uUtvizeZcJ4rJomxjRQUW14lm2mYrlV7ltbkELtvUbjBU+jFgJDh9oNB1BfeJ6ysriXH+x37Nf/m
P78suE+a+hZqPeU13D+YUA4ilr7G0Ra7xcqlp3Uav+rbzMcyPhGNH7nlUiKxKJviqwpcdX9BOVJ9
NJQOHG94WGbr1f12kbi+HEIT4yuDV4KARvKQ+MtjLrjIcxyitYROFgomB+Gw1POPg82FwjSTjwt4
95yT2dIUVzyO/h0/S7AiR+OvhT0MD237OfkFnhKbDU3IiCKgv/12Ak8hp8YGUJVoeDz87T2flJ7u
cO4Qrdi/ghkn1gjTrEKwTM+2DxV+lHI/BXPpExoEf7Cnfkay0+o5TMUkxFQH4dZYiKMM3nUpMkeR
35OT9znj7QUX+iYoas6NoNlFR7aOr5A3haG/2nsY7ZuujUKD8lvUKw08JJ2MjbLCDnRs754bweFV
UcV0f7b57EDFvgs05FFJox/oE4SAbTifJ97LcvrHzCcFjRX/Lv6JaJs+tgjiY+5fBuUOPFnTAH8Z
FiQdGd2mg5wakhyIDDz2cNmxBxZbXTaAA8MQ2OApEjusfN3Hz/vsxM3S4rntr+V5ffKOrBU2yla3
x/DQ2FNgZFRXUchpQdq9kY0LYjPii4WdUBU/QPC2Kfakhgvn/5eJmOwGHLkTeVlBwB0KUmoDHjun
lXWSWiFEtJz0kZDG54SSWNP9IHHzqrvNzo6eeE+T8kwKzxNM7z98ksK9yx4t772p8fJGmu3tfJxy
Z2UXIORDUuyLzzbpAgEDMhFMUsCzP26Yh5M9ly5EJlKFgvEq7qty5pnlA+r3eO+NxC8FC5Xwx3Sw
VvIXeMHJLik30yrU+m9sxhO+3CF13SjmGoIp6luw2Ynvipsob8EX/TDtzx8ebDFB/dhheL1OvR9I
UOn81nv+yhnrNg/P0yWXD4b9HGb3F+et+Jq8dRZCvqxICnOa4R+poMH9gVkTohE03c/yzF4dbHcL
/MNqm5j7EgXZtwWDi0ZICzZJ1dCckzq35UjhPvmEaPTt2KvYRrs5R8zeddX/CN81PfZQHyCPQ6ch
Xl5ygE7/RLR9tp92UpbLJAPgQIc0qoV4ph2DvJsgZcDdDsw8xrifYVG0yHFG4DL2cAA8ulQC5kdY
2WCdaSdRvTMvfR3wAzSgHH6nycvRyNyikz21aZ7cOqzLG/b0HfIvDPiSodqwN9JvsXIDem27keFW
oi+a38ADF6InPtueG4zHlGODc6gYOt5wMsu0vZvfTs30hlF6VlQsLsx92qy6wh3PUQvN3u55nDWL
HTaQ+rxTuMwHblFqoNp0jX4dCkA/jqSSKVfDlAMKY9EeMzyCBykbL8Nx3A348fhg0gd/Iva6TSzX
0RMXExSAuwZLwjrYlb6UEAJqKGFfL7N3j4sHlEFB5HSuG86Jh2h1GAOjmE3fv7eHT/G+qgUiavUB
wO9yxGuL3YwjyfXX968F30RRTTFcPCiDrsXly9DhRTdP3kfMjJTikHXNtTOL3jJGE8Q5eE/2aWsh
oKFdWMO55NhiHxiHUv+QfYy74tldIINpw6nuxHqSZlmJrf7sk0gh5Mdj/b1Hm8aoS+1iUwz5wF3E
aPgJpd8AIbcEot35Ig6168NHQIc+FpcePMfzpaSnc+RTMi2gVI0vh6BIdOrOJwlvNlp99WgC1Uw0
pR4enqdsfjgK0Arf+6NRMTDw1q2P6dJOTZ4Dbh10JAyVOAibv3msx3e/lDuz9o7kKncPw6up69K0
qHHizSO7TJg2X1SfZY3JmJCEzxr23HjaczN0bl4yhBQpi//VH0nO8gX61wvEIdYMqRMgOeZnb3BO
xtqwXp5L9pEzcjibg9nllWotpAVqTMbju49jAHMOVcTFyNXlYusV5jC9ICExSBx8fk57+oTVOuhY
5sCZ+kx+CMIQsmRcOfqEzopKFGH9Dbki+AjPPeX35VX9fzKtB8S2/jXeDYWESug0UunpJTG23Z3S
t+EVJv1fzHY/tK0YRv8kOtxKybSNjPGzf/qhW5dwRkxXBIax9MbcHGe5ryXdPeynn1GBIIK5VlRL
SKwwbxFu0VRWeW/vMgq/2gLogkNiYXCaPjV9rMdvlYAYc/12Jq45GJUqBJzZfQEsRqjggTzcvKeP
eiudACR3/z+D/5Ay4f/3+LqzOKUTObJVF4fikmSAbIXj2eONa+ZZE4VDc7qU4or2MA3HtSv/+8dx
x2M/aXA3Vd2OWwknDtG4N1CtaJrJVUtHYQnevlc9nLxDBTb+pR2rMG1bvdi07u/pC05vxhynp9yU
V0X+bVF1PlZo8SKJNVBky2JLdkHvscKjylAXUVMf7gmE69Sr289jJrf8YXcIeSyi0U/ur66Cp95q
UzH4keTjPJNcpnjV/0/5zgk9hg11rIyhTF7ot+ggm2WjFeP732Fxp0lIh6lCa0p9Lf/A7b995I9A
GQj/pEtX+5vztIfthIWMQGTlzu7GvRLLRDlX8tfPE+5WTBMGc7IlBIEHDv1i979OYqPv6cViCddH
qeMegIwRavPXaVt0Hakb6t5M7PSr+bhlMYUMuS3UrecVD/7CUOirYcAzEo8k4u2HNcYOJo7c+Xsq
QFYXlUVXBETgzLLSC2pB9wLgzONXwXmIs1Nmr+6YME1S28JpUn80ftFhItTi4bVSX58WtK5Sv6a/
ebdH7zIBT1A/vEKr0bexjwl39keID8AY9trZRZG0qyQcJeNJxM22gGM+shJjO95rgCMmNQ6XveY6
8uzzD9yXh5G96IvZCg6yW9j+UwGTYWHtmoCShniRYIjDHx/tbcglykW0qMqLOivoKJPezTfZrV4X
UzQaJCmy3EO9k/NC28Ggc5jhKnzwpI9TbAEvAHi+WsRA94isU7OylYT8n8WuHEtwA3DpMIQs0rkb
NOWztgvFr+61INSLC2Xsv82K8qtLmyYqLnWXS+XbYPnNr9BwG/b9Ge+2BN8m8Hn53hPB71S854g6
3iyI7egb8YEqf6SUO905XY2u2EBbe/HXeZkoZWQRmKyrIE7V90/NHIAfkYUZkbcEtFxHNHzSIn/X
QsFvP3ByHr21AnxilABKJ5kBdP8WayAPp9caRxfTmImgpfQiwlrhpYqZOWmQMzPUQNKTUE2xMpzj
Dx9rHJIaW1++AuX+clrzhPKCscRjFCm8p+yAvxs1rZWCO1n6CCxYfaL2k75gY+tsjQh/9+jgf72P
L8ngBknoTPs9dFOK99vtpTWOjwcHZ+vJcprhwFpX3zPxC2fT3M70z3US7ppOv4VUCVC2+JlQ/E0r
B7zaB5A0TyFTyJAGjlUMSGIetlcyOxdJTRuodO/UOcEJ2zqdi4UJNvs3t4J8DYz5HaOVji3T2v8d
KttP5Re5oLPrD7rzKRRobyMpwaMUd66u02h219oLTJoORfWIflT7DEfhyiKeHLzTIAkvuQ9KWPqM
RKKmJoMpzPapxIX9VwI+iP9NzZ3rOoIs6GK7V3a/zCh5eTWcA2fFG/YRU0vD022zeB4HM+CP4lsD
vFdN8CLIbDxaKtxt9vqS97ZN/CyKRlGKOpTRdNajV3voIc2exgl1GsVhwnGwxkwrNR43iEN8j51X
9P6NT9qg7n177HfJsmOEpUlpCp892ps0+PfZV7speF4fTZxcAb8513nTY0KiQ1pgWbPuggHBOELr
koEWBj2fkrE6ybOlIEiuo47UA2qQmajhmYjSjM2VsQ4CDHyK+ZvFrdNM9XvJ/1KFcrV5Lg8dvKak
fSaPEVVyVLEt6N81cMhnd7Ho5vl2UdTc3Kqj7+3g4ysVoGVApGlJbWKbJYjSsWtgW2draTtHma9J
CvquAAU8c8AY5MmhSitGuwa7BWwpr0PTj30OKjjaqvfuBeTi5UkFTJU7VVYgXlOJR9OBoQi6gqg6
/Rh79qqW/wJ5uGSfcRLu/gk7mUc660XTXLzJ9U6zXWejOPoLM0eAu2V/CSmxasgx6fI4S9PwOcqG
qISt0L4RI8ImI38/Mq705nymHxGU+85EjtI1pZa8HiTmZ2poKnAtr4h+rOi6AI896XLBslBU6rBK
T8GEj24iv3zdwXv1K9L6JczBcG5GpNcgcBXZCMbfQEixmHafE10iyQ2iurUEP9I5i7xUBXvUF7ZI
bRAXftc6NdSb26WGRapXVRyQDCMAkxLxOoBnb/cL18qiTZ9WwFDK6AN4we/dJrhrbhEos490ZccU
jmrOQy+VS2hkymj93FAE6OLWpeFMbI4VMSmvb4RhvCBgIYF1JRm1QvbMiqlpYZPNFYNElecYIvpK
bnt88snO72Vvh6FSptN/oVScKj1ohawzK/uXbsRUyWb//72K3SQ/puDPmaLiBPE9RpvD2mqdlYo1
ggERP17KCMxIb9G2j7J/xvXSSA1p7vy8+CpRHT3+4/i4d8uCs7dodNFKH+2V63ED0HhiiSwCa5CR
UY6zMnjZWiC/T/V3jVgSORaVM47FIqEIKGuC4FIwNfE9bi3Y9eE0BAG6y7xeLpG8ZKLPwBrDz4nE
5Qv+6TNwpXVrhNxk2ZGba6UQQ+rNERt3Ab8D/HPsc930WcGom7cUyiyuThczdzE8xCk1vSw/KMCM
yiVjjJsdtwm7h+tQTnV7/c6BZ9jhaW9tcLUhItg4n/kOctqtwbMeZfZvB8MpXvqO1gET4/BiAscF
FsVYBozpFIdDud8QSfAeDVXPVIASP4Sp7vKovcGx+IzAIt9s0rqxoP0Fz3lSZ/uWzjmEBVNcgK25
/y7O5QveQFwsbLXSMEVh62aNpNl43Uh1CRew5saqJZSryylsV5J+RazgfFGEW4cYujMdVIf6K3hC
pz0DItgseRd3jhGsAqIJgsH6mOUsxdOI0DpJ3ODhAcB9bK2Oqa5YcYmsL0aGaA5TsM15GaPkHtnR
0Uh/D1QHgKA936FzolWJeZFwOyTrDxzJTxCeoXb4k0SJm0+MtGjUxJrrCjs0uS+SZnkCKvIifh+C
Th4hYJQoFco2bA7g8KNkC/6eOZjWfcHR/D6+QMgvoULScJOo/0rLmYMb+MfXjsk7UvzYH0meOm3n
PtaBp1X/OZEosSg2VShrePoyVf6UrXJOBsOBYAKW/uO7tp9yE7VKaquFJPUmF+JaP+MMwGw+SdnH
cLCEuM35es4/kTmQZULY6eLK5sy614dt6obA/EPfwwVr/OeQTtfn4m+PGHIrV517WUktv2F+1yY9
jDWqCfBNFbxuChbx/O0JqrNsAnwNoqJvxZg0XkaaPW7t+AvAM6oF13gF/NwizQcZf0st2dyu0m4f
kagLN1+3KDHUwO+z7QXZ9/ZnuiWBrIYMI+kV+DXOCepQ5gAVXJ4+N1xW17ZEM7ZehUn+nArbmx8l
e3C7z4hs6VLjwZg8cQ+JWJG9oYjoYz21lQ/IxviYZT0aWhK77Ov6z6uvsH2/HrCkF9vlQVzNBBVi
/Qr5ZZi/DgntNZqp4375V850zhey0d4eoH/nCMq5h0iprIuOtl6zPti1Kh2i7zndCS/OfmVgSDM+
ukXk86dRI2NNtBXg2I9ajZOr8Zpr+4c9TjdoDBw4sT5XCbKIOHw1Bjke1jJm52YCJUH4+nGbBo6F
8SszGKzPnZokmNE78dtX5Tyl4osEGxnUQutk0yhgPRGHKEiavFI3bef7DxDofJTHNrrk76C8D6Oy
Xq1pwuj1eqJHpT5WGovIByieDbcr+ik3k9M3eWsZ1CT9TWisXHSZAVa8G2eUkoBYZIN3RAHIAoYS
MsQEO14leWhRMj3JVsHlrBav2CoBZpqJfunmjSYYGdEg3Mu7NutVaUD5jKOjVoOKg8U7mqX5nyqo
odLu5gs9dn8aElV9TPXXBhMtoVdWm46NXEI60VqxETrBd6aVdXucDjacgt732Lelim5fpA9oudQK
qZGDc4hKv+9ue4agedtfFymsDgOuwlaU0W7mONfwsoqZQh1JI5Z8be/iTfLQdoaW6sVkQuYSQTEu
k9DrbbW4N+Jv64ZB+olTwLFgbkMYcmD7XNmCKYOqRYdrEZTzm4NwSpKqsh2oTcO+l9GZOExxPWn7
QOJgGUOrht2J79sdLbqNYiCH74olf/AFgaJEJLLfM5ps/WBjPLKFoKVdpLBpQ6BJrQsGXXrSixXh
Futaf5no9tJPwQlHnuhuNFdp8j4JzWS5LaGxiWpmcAVO4mcTnNpWNSUReV8iH1WJqHjZQeA72IpG
8BoDEnd+uSOoiVCN5yH0NevRNLlYIDNLr57merCXgP5WL5NofvqgCaKxqewcZXMDeITZdcmOpa9x
eECRLRx5G4oa2UqvrX3drlR8qIDayvIOSwr76voJFbnbq6xlrev5C+7z6FRWo6BOzhaXlcN7I9EL
QRrXZbbayRX6VIMl1NsOr7u/hwq8u5Y9+WMT4e5B3fTyxBDNQT/siRLBgr20gr2WLJcGYAasD7wv
sxacIZAaljmR1nBWwOzpAVXslgzmH9Snjx0b77RDlbJY1Ch3qjRons6BAGZ5LjWbvVrZqTvcxSY8
CwKIk+0UYSX7uay8hyPedPovaxPMO1M/q9j/cMiECbPRSDMTmdhXXctQtZacYu1dbZPqO8Z+uhXH
crmTYXjgkwJjHn5IAaBVyPwUqn5p4YK2tEFy+CWCyPzxCXuNypjZOqvnJ0bu0CFriUJvlln9EUwq
pEVdofoqgdAyMDJPRYXqV4173uVSxjORAtVJfJc6TOWQiSq2W2E01jAt70zsPwSpv+f197hFcgdY
GrHj1juZ4q20xUQ5JT+ewx3AltrGoFOmSgs/DAZb5QhMgEsqhd4LtRXBBWqQp0842fNb6Umv3c1B
h2aEWKNln+JquDo3Bs1AzdySo02az+1uZNPs+OwU4N7REtNxAQ3L+dwHTnYDT/UcdvfxJljYmb7W
pZkXoOEKEb6eQUTfuOsbBiFdM0pK60bq08d/mZ5aujfjhqWulNVCd/ZowcwolzlbsqhYc8Q5Rpps
u1GE1ZsQJPyDGJK1QN2fzeSGmqseheFl7/IIQOQymI0dXKWib/2x0KxtolamRsvT4AzVHTvng9Ik
IIlYfrkoz120tvK5zcUHOamqqy5yTi8GePKK0F7aMNIoktGJNp7s8UlSke/ZaqaaAmKMkdcZPxbA
UvBTcVXR4hLHSWPGBjjgJIWIbEUYQY7HMtfa6yev25WrGZr/7ADHO3dOiX133dM7Hi7Gi62pE2af
cqOGjjJTpY7nihllS3nX0WBay4k6r5zKhYHSrAcOEErdUjCg9yr1FbthslM4apqaF5GcX7+LxF2g
ShC2K/i8RxjF0yq8knvdnGlYWT5yBsEW6LMjLFRng3cIhx798P2+T31xpHuHlvK/4rV4x9yk3AnQ
gvd0xf4LxpzTi0EPlu07uYPGmbeU5byUHs5HCs2qM3IdYemP8/l2Nf9Cu8JndWGF1hRvz4Yu3gOj
QoyjO1q/H0OZhIy9ykzqabiY3WuWw0hxuw1VNxtTQky1527vdio71jAM4hc9NOS2u1OF70CbvFMZ
g3XBo71jdoi6K7PhbMReCU03viFBqEtCwCCU018CQhB44Z4DAJpVX7/NTKDGU9YFVCDm+R43BLVf
bRo7pmAuOEDDf0shPUyp3XsmIRMEtCtxNljk8ibFDopCm2NbUkcq/kLchy8wJJ6sDh1irwogfZI5
HktXMBLdxzJDsJXtpql0xoTmHOTmv+830YX4DAh9ri4aInJcyGa9rmdyP5t5+b55vvEdbjzNkaXC
xWL6PaiygATg8egkCwvNORzkMXgHJuW9C453NDnyoSdM7OdqG3fVLHcRlhyqQsgdD4kqnvnbLpuJ
LyWpI7e/gbGJDqVbc2Kaui50iXWJZyHvoraNYt76qrhqEFRlAN5rOQP4MyT21Kyp7U28VratiA0V
U7xWalH7Yjj6OLRWMVZ1QJMbN5117YFmIsldsikUvNCLXYGst8u5Y/7VJmxqzFk0pPQyCVai8Oa2
uWIEjmtr/KINxJ9ooUE9GFwpysQE9ezoLehwmuNjJ6gmqZh+axc02C5TWPurEZKOpyA8g9063Qoj
3QW80eaN4L+uP7r56BypV10H0bssvlYIJn4NNPq33YYJfvYb/BxbnkBGJzJVNdbFu3FJZsOxMZi1
4iP+T+T3cSXtxV3ZpbkQjWFyAbNWCkWamr0rAdpR+wBs5/02E/JOVKsFQuXuXwRzFEnvzYF1wIgg
Cw9fikA6N4PKO0OpGeFB/+qLp89fVcfXT+tkkPIdJp+2w+2Ud7Z55OWEhQRbVMHHF9k2HRuYko1F
ixga1im6Mtukb2zjVPM1PAKKmea9BvKr+lEdccV256KB8QYyJ5P43YWEcXwc/XNnEjUaieJ1UeZl
cz9L62TK3spFiCCsyxE6/IkuKypLNS373iNmraRn/A9WZcgnMapT3wj18w53ewgm/SQ88YtkkdlN
7S/CeOeR/B/3Im8xvMvdNv/ZNWeOCQK3InV93Ad4Cpa2Sl1SgHBBw3lxVQCilRG63u4WyoH43KZw
nI4oHJDEXTADKmmON7lFrmQ76sHMz+dkhx5zW6qGSw77zF7ElPP/0e53Q50+emOwxchIg61OaBSI
eWe+gK2CVe+aR/niISHcJWpEFJ4RfCPLAUcgdd04MhlLfZh/PjhSQUgLOIFPh6hSC2Lgia1bhVNJ
K4i9ti0OAkMVJ5ZsQuWIe/P1v7PAguw/iQTIFR89SAwrPofIexR+MfF7j9UrRpR5QRxMvW9pgI1Q
VmX0pU6PSJJ8XSk3iaEIr/L81klEB24VVk5n+ox6Fx7MQx80wabRbnnOm4a3kjecJpTOdF2xtAXI
ynpJGjzH7PjY8d6g8AITo3q0fkHBJbxbn72hN+ymNU8aMjp5XpmFadegv4YP2RccZ2O5Re1ZloIS
zqpzAEQgYST+zS5E9v0y34XPNpBYyXnu6c7dugKPuo02A6ulHkcCkrwfLxCv5nk+JStgQJTCqDVx
yWz0yQqNEbjvVZcnkVbgieGj0MB1tvnheXybxcFKiRsYXooIMAGVRCW1kqByf9Q/7ND/L8P/drEI
f5GgC5D646HCpHzdAJcdxsudm81vO2lySm0jC+kvRgO2MMBHI/I7SAJBozpPD3HZnIrNnX+AxlTf
hDHck1c5n1rzhxfYiKEC8bw8aVzw2ryaBI/OYA4dlm5NulLEcR1jOlDNGFJfDKYE4c02PEPNABoN
EHTdKfpXkUn/I7R3WRjL4d6Ax5d/OGshs59o4yoPjT9yzT4Cy9KR+AKsg/jpy0rlnLM2tUEfSqBR
s2a8QLpFw+PzOgolfD6vX9caMLW0K5+5RDZTRzR9xQxIVjtoL0e+RdvCXnYvYiNvbzOoHvc2N613
9d3cpooLnR1Mr4pKs+NADZ1zMpNvXyq5LLOJcXtxqIUAFCVGWW8oHTrP/Md4AhZJYfHNzeydlyir
cAof2W3LI7peugp5vv9yetf650pdhr6VTcCHwMT566T718JUxW1XPSJlJEGtND8nUZMaLAVg8CZt
CEmm68rzI3buHw8t6pjiImlAbaMFFhbGzCFG5s2Hm6iSwtAkR1eJjoGdtByuiHKwV5J5vIUN1N8K
x544p7CloJiffYF7iT1RyS2+mNmnQyBsjY4xw/bDhk8air2DGk318QdRHoMvNyXlY19SxOoIpf2g
e8PIMjA0A7KzdIO8/t0JITZCq5XlI6RVjpS5nSEI5BDCUHjKRra0BRhe7GhS4v/BuVSEfIgPb4OS
EGrWu8CL0DU8ac0VVva/etIsa+GKHLONR1kU6cjNd8pLs+3M+LpFjKXpz6CGx68p+yPkXguwZfMD
dqAdCuJgBDp2RGXw5lR1bDn3yGyMDgiKjU0UqUR0jv4CXbYiOhKgdPXL1oAEBNHM0btMjxHcKfgT
NU7FXN5BHFK7rvQUhgqFTq6Gv+NIy1s0OytElJzfV4Qh9r6YtiMZMwlFuimByWSRquormEVufGy+
p4RmkFTNJ/JuwATSUQYlq80sJuKkzLOPJziI88ZcP4Z3E4CRTpIFZjPhCEW0MNWeaBiK3+ts0jPI
aKcOvnY6lQjZrzcQT5nYq6zNgTJCHXUJZ1CLhlwIMTTns3wkyYmj1J7Gq1gP7gsxFPa5yssRXSf9
x8AaSB8OAL7qAkEIwuC2fuYdgYM2WIhH+mo0/BJ+pn0iEh/HzWma1xCVvK9MmTr1JgoZvGjM98t/
RbtTpPESXuTTmFtgfC8I4wQwmQY/IEDAPsZyiY6q7ILfI7401g0bFinmxjFLUlH7H1sFzZA5WMhM
WZFnmQsIsjkk7CCYTPAkqO7BT1EBw/i49oilD0cLAqIVl9f+pio72oW+8FndoGjx/fWhh2D5QTb0
Gb8DQGXDXehOtjXOTmhWMC63a5v324G7yNgZLcfA4dZJh1XE64mbYLlBtYfA3FQq9e5jLZ6+qLkA
EFb2mdrGq9FDYG/fSf5+qbm4AYuIUBDQjSlPaGMTaycEQeJ6oEv1trYMbjOCcEd2pQCw62OIiLCs
DH5LAO1cw6mn1VGO3K7PIbrcay+p+G2KRPxDTaHeDeshU1rUhy73y/Ixp3NyR7XznnoYL6rX8Dkx
1ifX+HysZ8JfyRZtQ1ML1Hq8gZam5CjYQQ3S4lmIH5wjiKM72s6OD2STrsA/UuBonJsh6KSewJ8f
gbA3QA/LVNcWX+pNEJl/LfFlULGQcHsozEW2sYFStlylCQZ2c405UZcqeHQyKMfmVQAkXw3LN8EV
BAT8i54O76ex83Op/yfPmQ6YIPJFWHvNOOfqKp4xzKQDAQafRUTh22NQK3GLN7+dsAwhAiW8NsgZ
G5vZSEon2XALGX2Oflgxmx7cyuAge3OwGgPExU4fL6wrw4xEL2i3XvQBUb14QfnkldOsh+5fqRry
qDmwWySAu5cmDnRsjR0pPu22Xc2dQtR6rcrBVE2X0neVHo0lG/1d3JeNXfSTr8y48xOpmEwxu0bm
QlZrb3CbCRPmJL5kXvvJ86VhpX6O8oKettv947TMguBK6z/jL9m9KsdksHrWlFjUMo5DvKnv3dkY
H/a3y6DBe8gRhCOrvldj20sphkirlKeSpdwPcYsP9Z9uyPlpZdNOKla4bv0JTPGRWNHod9zzUq3G
b7wkFvJhC3fpYc8n3C1uMiTNM1HZEcvN7fLjxUwYNWhEWblkczi73q0DJslnCrbasc8VvIWH98pu
9GcFHioboS2ems5K0JMkS4j8wRsxycSYEI/LaqGPXA9xNu8X9aEdRxlTkTZfEsOE7hew1qGhtcWz
xSKnc8kio2u/B5q4AJNfTPqxNgim8vYkagN8jsFYKOxFVDYB6JPuzakJiexnbhPrd+qdL0Ko5+rr
W5HT/nurMLxkQxUzkoR5nEHUHkuQbSyZP3cIWbROp2fLnoG1dSOaGvlAR+OO3ptkQMkDuN70Ql3H
kkcc6ln+apy95E7T1HSjyPTQlmqlbcqeNt17Im+yiRNCodLgYkuH9J4mMPOFu4rr9nILHOtnijDX
58rfzd0x1Ad2U5bvR5K3RdwlRxlZUy1VfRnT3MdTK9qxv0XT8yXfe/60TVIzxt+9dDlaUUoxQlMw
eHyLPzFJizXiSDMw21Zg5l2kx/yHRobDv3Aq/qKJtsAyaetS/NRE7jJlZ/rkIzhZeiItiXl84RbT
t6sxozTgvWITtPCnRNHQGYdlelsEmPThsFQvu6blrE8t78U4zdWYNsmCOUrv4OkwGojyBomtb58+
HR4EYg0pbZ30RVYB6zWLg8hdjrirGd8gOgI0i/0ZHCuG/GokcsxCtZk/+yMUscwt5JHUD3WT0MPd
a3a3Y7CwDGQDVE0UcXmTGJFL3YvgeI0YwiBJcqovMZLS30UFVjz3ThzIWscrGDvbHbelWGghRgxF
JbDR1qxCImRCKKfXXZhie4zmSdZwJh6c4n1TjaZJ7CPiY9vKyehk1AxAkRTW38z6wKbCxD+GGKsw
+oq7ajlwd+YxgaexEGVfV9sQfPIKmrBGp+esN4kGetSSzUswgi3PpsLNFdiUeXck+nqfQspkTUqA
gdgv8nP6fyivHDwKhRVbQy2N/GfE1F5KrBFFnYFE9k9OrxfpZJyhfnnM/avJ2x1oct9UU0sNySO9
bwEG6Cq7dErZve5AYTRq+5jaQdKxmR/couqA6SMjomd2OLmupsEBeOo+6l3WVg0xMPD/TuHXdLXc
fafH/c3DeXpaVKDtz4CUIQ5fZs12rM/S+C3uNCCT5o8E2Rxv3yJqvgSq+Lxa5XPRV+cX9WeQLDD/
xo6YouoTjeIyGcuigE2ZWpQXiK71zJ+mIYfykJcIOkAlQV02yfoewSe0OnjzRxPN90piLStXH9e3
7drbGe0HriHusvwaVdIUSuK8Y04watn4zZUIuS7hgRfJl3fUt6m7Yv6mQiUwKmhmFWKamJKkEPSc
GFa0Za9ljBJrPx6kB2MxPHW/H47iKML6KJG9gpeH2Ng5y9rMKWnTyRqYajFTjIGprWDNpUhPps1L
gMbchH9q46gYBboVLCB5ZNS4MQo8qbW6r9w3tSBUh6sofu9MoAUpgza/iGsRkDSc3wE07n59jDV6
A4pRWqSGOXbUAGGrTGFObY5SEGLGqwMp0lkdJF+sq5sTq/Kjf43LLMvLoVDqCzY5rSp5AZkI22E6
sQtZ7861JwDRi8zL6gstYAehSej7yHfn1iPG2jJaWcPWeT6H68tQbmn9GfhRExnthz2v6Jt8bXZZ
XdXabpJQ/XcGT3oS9IuuQ2tt6WICA+m5KWz0TZ4gwFSN+lcZI9mCdzI0rsXdjxgEcdkRJ64YCWNO
SrPAsG8JqfZ6qwpNrGIa2x9NjpfuekJp26oyRbH737CbTEtXlTfScb63/IRn5LgLfWexFS9ZIcmB
jqU/FWydZl4z6jL+nzyQvQKkar3thZNlAUnyD67Xe5VouA/nD+vP//LlFmyzMdYF8f+fNQGIy5h4
NcpbIYmoCOCv5IW/Ylnu7Jb8zX2/zrBvMkOv6QnaMNRRxJ4LREg4DOZZV2b9kcFuy1iOLdzAERR5
MXfffobto0yPiDiUcZ/zzUJ9+DkLVcd4g2PKHeFRreD+kGRs7R3Tiu6wIo5KRvg2ySgpT/9OPewd
mPxSXCDGt+95htpAndK4NaVVJBVvia6b61G1aV1BouljRfb/KdLCJgU9ljhtN7ug2P8YLYyXn8Y1
Y/k/fweNqzjNbghi87AewxFJ7IZ6CyamyjfAB15I/K7qainzktz4m9IMcXRU6VeInwKeJiLhqsVO
bD/ZYTB0IJjtXInbFcg2GYQHpcwkBKH96z3w2iWkVllf/quOJbxS7yfCO8WM/Agc8e7cjkTHxHL+
A/pGbmPM7+ryNzyD2HwNX9IBIv90e5lkXmJDA168l/deXQWB3wogF5py5qPb0hrCs4G6nK431moa
Pwu6XLzuMrC0oz906o8TF4CgP9zO/3PZ0mMSUJH7hB+kukrWVViq0cyvruL/nCnml0whsM09rcRb
RieGcYiVE5gs7qh0zj2MPdbudfGGUqaWzZ4Xpah1xx/XsAwytPeDtQKlQK2m/S3/3s8MKdJrF9so
TxkQ1Qxw0wuS3sv+T5hyQPl2NsBz922Gjm105Z0LW7qFApKqVdayuHpMdFcm2RdbbddE5K5/Ut0b
tjpApOwy5qZmXc5QN/SmJSttT2SzCnAEp5l/6jlkywQxKmGETPQRGGaC0QJeekbCAp0AYvpdfRqj
ud11aKhNOTP3+Chw8K9ZhGxuFF2gUDVS6VGrA5uFKfVc7H+1nonJk8CC3xkhnpWJwnOCI/s5DpC5
gipR/8TmqjcxK3NKvl6UbcnFenqoNgobKKqwYiaDVG26GanxTcnQ4yxVw1erQeE3I7ZyIiWj69rZ
QU/JqDp1MPycB31Bub+gqnz9TwrsvJvKjSZcASsyGdRaWqRvF9Q0Pz4leMdgJ8Bxlpc+sInPq85z
ZBClM6faLKDf0SB4Lbpg6ZjYtP/Dmc4q4nkYp0FHKvkWuGhqNOsZ0NPdyrB5XVoNLsjsBriOyD3n
E7J5eUsklTEbf8070/qNyGX7TU/kc/EWr3YJXCxHgRMAKrcvy9teeRiX+LCoMaszSiA0Rn/zppCk
xk/WP/gHpK3FQJnu1tq4Ka+wKlNNQN2az2XVWMh5bt4muNBxJ7gNPK9CEdzkja/p9DpwUR/s6URn
tdAeIODZjZdXkMbCFXN/cLEUJWAT4FDBTKVJz/KazrfsG4XZ8aWSJVvDCZKhP8LDivhE1cWjes/z
wOfnruFPbUT9UvGQoRG93hkouFaV2O6jhRFtmMrugSKRE7I6mMHYy74ei/06Lv9VVspFjLYS7pFA
YbPxjoVUBhpUxzGDdL49T1ZaS+5vK57Lw7g8aiKSbKF1RJDOefxXrxsESCj5PGX4t3JrQZqavmrD
W4iDEHujWnhaDADDvAfUK5nUqIxGLexRyfi99lOWw5RpB/FYVX7UvPghUHkJ8j6jFUzi1fvE6X4q
gqmDOnU1S12GpjvofUjKArrXHVYZJDTt3gVuRHHWbREyxVDjZfy2UKhimdz1OMcTkxt++lO31fH1
QFeBn7Zw34Vv/3rQbx9Hx5p+3771xwB7Kwyz/Vrwh4o/iX2sXNfZ+50O7AKOYc5YCO24GVGWl+gZ
KPNHp+DTHvz4aF3NhKVXrjX1ugYyWDIVG+yp8CzV8IXHXoXZ3BQMUNNToPzefgzojMmMfskJkS49
csXrzd6+yz+kczb8Mo5U0Af5v2D9ZK3qphG61sfFPFmH1x7holeQDf83qqdcCNUXVrThQBbr/py7
qficlJavhg8I1O7TthYe/0NkRVelp1vxzFQ9VsPjmb7xkwBN/qKzaSTG3kvtTiH73IcgEE54kB4k
jiwXiB02UNQnJa/MxkkhNfETE4IIviO8Jm6zbRPESUFTV0IVU4Ea323tnsWwFEmymUI5f3jaD73L
wt8imHjUFR7GCQsD0tdDhnzsh+eppWujIO3gOY3KiF0NLWTyoTQYwwvMTnxZQkz6yFRCrc4H5mMQ
MDSlciCZZgz73muaSUg1D4zwizYrTZPSRQ+CbKeGwdnedxdEbAhvplVHUytUUbnAnftPCNaqyBZr
m+PzbYgPQLTjYjDtMLkUKsTDAsj9wHHNGSE5TQoYcvt37mZ9ircFmVmTF3efLoQo3bX3e7ke5PX1
SzAH4gzNZpxgU+8V25SWaSeFW6evd1ZH//NFUHyGHuxW/YkW/x1zfo7lOVC88YKgmZiX8OER4V9p
05J8hfLbV2pr6yeZjqGKPFnGlSaktX0h9p/U4VL4+b16sC+CL3YBbpSPE9+V1JHSEjm5CONTgJVz
uZw3YfradGMipVBoZx5/mCr/BRiIaIrV1h5o11Fl6298srTpyqH4TUM7elVyMF0P+YTo7r401H19
8d72/vdRA1DW3lgTkpF11QdNcT0W8t/B2ATwOyxtTeKYM2Yvvp8j+j0RdH7em1ELHVX2asjRu+3t
IpRC4B2kKGxGhrUZW0V562EowGKPCK0B40x9vu0NtHMkjiPuqqdLjvEM7TGx/HMUYmB+kfF2GDKi
JKBx6LTFQcEk+xIUsZs+schI+sl2Ogog8Gd5vlgMEKQaGcV7QpXC6dLUolIp/8FnU1GKrvmau6mn
v4wX+Y5uMQsZzlgZPWEDQgcbWr3odfJZ8Q5KToI98nsDp04XaFv48ARTEFjJ4q2avgquLwbJ+iVu
59RGk74mPSEm8y9HoCNwQEs6Tyl9OIwzVr6s60imeSaEy8nGRlQSpvGJ9gTrhBHvvAtCWhCO+J9A
b2haFdR3qAo0q94cNL6/bsHucH0OTd26Uw6x099oSfyMhsjoNcS1Os5yl4X9bAc6Nmwt3RoYa1Nw
LTg03rczmHMmRPBekeWqS0o55y8gbaCRI32yq/HSQn/7U+UUbIBEmYty9pup99iG2EDRkJIdG/UG
T+UhNyQrZupTjax+3uj5gSGNlSk33agtqYUzW1Xyi3gByKhqpn6eQ9v9cYK3it9/Zn4YANHgKHjQ
xl2J9zDE0jV4Gbw+rX6FD5cpRuZM/BBmrhuSaT1QYhY4O0iIfKies5LgPpivxSreOT3UtXfC1T6h
fl4wNOXqUufL/LZdosvpntOd/JP/aQ14gw12vV5wZc9Y5ViGwnxqmDJuoI1XK5FZ/MYnMjpSqjB5
9P6edwa8oYpg6moWsAm/PJ7em+UlWqqksbPmBemwMRLo6q123Ff33381bPEkx7yGFCmTauIr+OU0
ri97I+a05B6Xi2sdjXqEG+VFdf4vhk4Sjkg77rpjdpQx+6DWsf1V8wTFMczwwWlllLXEcBeirPBk
wSbtjPbzFlhvY1lXGc2B2GE7hXbgOaTU2XasF1kl0+u2Fa2Ne0nnWGoDbo/LYDx52Cyz2vyliTcr
K18hJmpWVTNYxz9y4PDydSpfu6D0fkiocnCcqAfro3qLJm49nzKe/EWIwCGkvLJ+h0DvJUpPu7yp
6NtFHLju6FzWOQgfp4nkVyGvMnNl1dyh4XwM277PKR0CvmRFiz8N8MfOGv6qdI4T1CCW4hoL62Eu
tcxPKuUNx0uyjMpo/MKlRJIwkeninO1ZXAFeT0KSuxayria7hlBbxTPi7FOBpeawv7rtXGkPRYEQ
+oVyXHKAxqwBIRplvn1f/tCLDxF4UZRXr8BrdhsEQB+oiA1lAU3HhyCeLphjvHwjNJq/d6KzLAnb
E0syj9oyx4wTWR30upCVXH0M0XAs/a62v0Fx9FjAbQ8WtK0pZTiqpmFx0juDcLfDWn34r7xyDN6S
Iv41SdFZ9ZgeUzM9yK+McKt24vtBoliGNyc1lx3F4FhDtQ7pVnCunF4l3SdaCTCSu8qWss7r9KSq
9jI+cHeVVh0iOZYpEHywwHvj44WntWAoHDiJ/eR4d1jK7Q9FNW3drmEESB5nX0KkCz7sa9uCw7bX
ZUj3BH6/HeoN5Um7dt6B5e+3/26SXkynX2ex4bNIQPAPzpZ5cHwlMlob7lV50vlbwEyVYjbU7q+2
xjjiTeAghYisZQFv3tPuO4f+zEQ1KOdvPY23iYnyaftgKUD+oATds3uEif137d4vE2M+gaK59Nj6
sUA9d7XCvOqvYPuIFoRoOVq5AABGfAQe3yIdcdXjpshjihS/qQk7qRAtHkw1flqwDVpRLsS5gFt2
YN1YfhGp5laW2gzBcVEQDjpd4yW3J9aYhd5tRJi3Jc3u0Kh0S+/OagVsILl1G8GEDatLBr3t/yOH
A0lEIaS3Yaxog1EPiU/CuRq9SWnGUj7h5c/aIyo0uXpnSq+aC7QZEo4QETKdvUse5Z2LJ6kt6dtJ
39UAGQjy56L0UrZ4KuU8+ibkG1fOBGcEhK/NPnJylxy8PbSczgsfXZYYRk0PKtwC9TGseUGzmkHG
SZld2841ff7rbUrqeJzEVjfK1nYiAkkoqW4rHqIRp77p/QUfaG7eqm8r7+sHzKPuNPusJlAgTapF
SxaStvvBEqvEyOcm+CF1Wv9Q7/RVhKOt3dOnw1eC07pVDmsGWUSKnPsAnT4F809RlGfc2ZM3ZA2+
4J+y3+/j+63ERxKG2UwTSXZ5PeKXumpL5i2lgtx2dSLVbMATWzKsPAlYnDBBKtns4YYwyRJjOQrn
MjeaK5Yleqbf1iMWtTfogN7BOOm7ePaLQqq9qsG301L8QxivGFAN5Sn8pQgFfeiNbZ+mXBZEmTrN
migq11z/IQyX9VmUgSsNbHVjBWv46zrISsvO6/0wVVSnDTlOvSggKKdPWStxe/juH6Y+PSkaHAvD
FY+BGx38PAABUz12asmV/N03B4HLT930/LDsqScOhpdkv5hPDg0D1Qu3x4ZTccxR7NQCa6bKlGmR
kzCTNN8BNWHB/WOE2TC16MPFN2+bGZT3WZcioCAEYgqWsrGeQCw7socLxf1vNkEQSTJtDJ0Mj+73
la5maiiViV6hpqGm9tPGoWFxbaBaIiGlrG0DS/GAHQB4Zn6rYrxkTnwma5IlTKUaEUQkVx1+z8YG
oNRpuzK62HwXc7jOR5aCYc0wOIVuICnsXKeY81FxDjRjmAXMKuPMQyaK+GYroJbe6zfMRJqEmsE4
V/xQgAn73j93DmykEfVKGM4aUmMiWnLkTlOb5rHhj6rbrPZJsOVyKqjVM7X+R/9/scxSVjoiPT8/
kjP5FKp7lIekwBPa2GXdYdAjHJaHTZZQ40S3bl8CeDUXBNPjGow7n0LWY6UnxLNLZ7d51MeH6zHl
/9eClstRgC3hjA+fIOVE37SWMHJ30nhs3EXFfB/k/IxMGyB/N0W0KSicRmWffe6QZ5FPKmE6J0nA
36ZgHC6SBzuWkHroaGocz/7LhNvBe3bt2zbDYp4PHAyLUax8MjGjdFZHCgHoV4orvQboGkhNfwt9
gVujDsP8d3KZx7I0srPFAFJ9LWJwrORSCOjjSsVe5LuxDRGrLXjE0z/i0PEw3k3nmn8Sj/jEvCUj
CSCbwuJxOz6tLP1a4NxrgtHKu71KmwCPY0VST+6dR+1/t7fSH0PWIKKWLtNEFcYIKbfsRfJh5zaS
NE02d2txxuRGk7KmSHniaP5pJMgHs2bb/+Ba++zktX/56B4XkSEABg9oYHxcEesQMXFdQR5yVtjk
DM1gwt7GtmCd/SuNUK85w5YH08K51NORSw+bwpX+8PO4H1utQRxaQ9JN1bZcqKtVvn8PwSVohmJb
SbFu6Wa22t4d00LVcP7GEqd9Dh5e44fanxipOW4rnE9jvo+308O2rC2w1kumxGPKOURA2qlhOmOu
m/tBeC1EbM4remnKqrKBx5A1/PyhYXPyRmBUs6IraAop4BEqsvNLKOSXWaMbfm523XHd5hDeHRpL
MLr34xG22v3JxtfjTvN8FlL6ViLWgsZu5XL8/h5xeo8qCVUIg0NXbtAKogD6CPLeM4mkecngxfgC
6JkNw54wplaEu5YcFXDupTCFK8GOTmV1GB126oNRYgN5vhR6Q1FJJaSXF69QyR/g85yX1RLqjQrw
D0MTmVjkhKSEJeC76FlKdgyt01lBHFrLS67PRwMYOpOa3J8Bv50xwlOKDLbiSoB3Z2PtNgrXBr6M
+8wsjyQGysiTpfBKPsiKKaHykBZkGHJYcrq0PjxfckQ5+4FtdLjhtxTgL1iK/HrK7PGMtVMnLxsF
bdn4/xqNvZ6QPjj6kVyaqe5KGPaBl/JRXAmrAYMX5Hcuy4pBbc4z69NWmMZvODgWv8Vvq5c8dT/0
9YsSiw8jVjd1/tHS9DJgaR5nsGqBfPPIz7nnVu9QPOEL9LoIspIFGUnNMANl26upNcww5cwClGlw
h3dJtXX1Zq5UzpN2NB53Z3s2YKKqaQZV9n/y2niQDS7+jWjTe4fJtSbEZJNGicIt41IzIWgri+kC
YhmdtFvKC/fEbbOziLwx/VREIigJv6LgRP5o4qAo8R3HvxBgGHY6AQVtWnAY6ZUvXdGVDI8ZeN+9
bm6I5RYdr+5/2PNv/EUlaLP4FUv/jd1eNj4t165y4aTRGoY9NLnAPFtDzoRjNeUoA7mv36kn3NTB
YDBW6oa37+FUiM+yoLkZgjTBx+8Y09tloUnH/F9AqZKuYmPXsT0QAav+xisQLLZ0jI1B1ufJx9fT
dy8yfiFWHcvs2sVmAo9eghkwsotARwMqFlPlr5AN7qE/b2yfJk+Vc0HjQ5LYTm1hitOuOOOhrnMN
i//mI/wpMYGb+60yPSDlKMGw5bV417bT+cPP8Ugosw/5ubCVE7veKJ++s74hHbCx26MdPtC1ZX6H
wgTYJdFZbJ0fKipPEt/0lyXOtJh2V3l2uQY95aOAieKFNzsfwKKvwUCeJjGBY39lE+yoGJuOT9Jc
1CLVJ6ieWO3B1wQ4utqFpvndfwGbwta4RZfR+/JLqPdug1mnuxREoviB8pflAuNWj4HsG6ITNkBz
zBTxBX2fEUpEoMygmRUZtcCFl87ncqmYLxwE85wEtppOJsrp8F/IW9TJ9WbuLNhlVCk1yTFbsWj7
Y5YJbLqTEpZuRK3mStO9H0e3gCfJYygQL2PFOHL7adQQjOtM2o8wR06gx7PGF2AqFQfS3jmXreeU
ei+CnUA5QOWrwrphZP+95Jc5zj51NqQ/R50Bv20/vpBgcadxyLaW0uLyWBR/Jt/rRsImiBPbaw9m
wGThCRr8AobNU2ReJaCsCeB+nn2IMzg2i7Ge3xB1EeX3CPtsTGtdezDkqQQqFqPUsKaubUtOonMl
LjB1M41+dtgcqRW8U4u8RpaiwD4584hxxKWoZLxjMrpjSdYN2y5Fn026kqEGNrJ7pQG719qL20D1
im1HJa/qyt4dw7a7N9M0YrHszWlA/8i07EzkQoU1/aDWPpd3mbLiZBI5803xrq8VxLFoD2WPItWX
kVCGeUSdfDKmKQIRYaiI+EP+aVTUseFf/2hGiSRtS37nVxD7ZDegDkbMRbGTJx8jIRdua9AwR4C6
Ve6TIwBrwqYlxckqTXa81JNsjWRoAmpd6Uzs13KVLrC2mftBqfxnSaX+zHsxoCoMBFDuYdUxg562
K+43tf9fBYW4qNBRaz/J3J+yplaaFeg7Fnjbg+GjDiGeTK3nk8cyjxvjIzsRx3bMoicQdWib1SoP
7sHT9SseCJbmoF2fqdzYhwuAZuYOKytjNwm6ch8cgPil6ROnlm02kKPBtH2FwP5cP9mGIxkpf9qU
JxA9120+2F8s3gUM8niUJacIxuE43ZDjbEvpfE0x4u2Eq+Su5MTc5676TzZhyeI1bV/bgzsSivuC
H8kHWW/rlnXFSTUz8Pt36QqHLv/vsi+jk2Ss/vCAugU8i4fxZLHB3wJMIAUZOaSycKt7P7uvLL5H
fnzkrBbayZVRtr6i0U2iF6Rl6VkFC2kjRaeWiGI2R7mUunmxzxYIwyzLegJdX25f56L2HUF1Yv93
Mt8gVM3490qUnS7vm9zQizIKRdTEt7ywB4Ka/Ei/xylqp8gYAWJwiebbzsGPNBpSOYVVQL9WVq8L
0t+iJaIaSxO53sB17tVwGvC/kioo3FD4ExIdK8crZM7LZXxvK3nhg4zNByfzX6yeaGlWIW5XK2y/
HmkH/DSEZrjyqwa8toXRnUYOb2aZxDNLNNM6+hZmi25ZnR/SUigzsaGN/ArNXYerDY9bi/sUBwqh
XrLorkI6I1xCjr+SV6FnQRm6RQFBEKhsn2emzhxEFAq4s3LlYKZNUU/YKUzTM3SS9Tu3LRo1Zuc8
+n1SW/qoAZwPpeez4v1mv1lWCKHW78ux78Ou8loqi30khVr0aza8nFNMmuzR/X49r9ITiMJoHBz1
B62MO3KFuZbzSDA+qbTa5k0FUR39+zUKqPXr/DYE0kP27ISIUqCV8eI+s4QwUL9N8tNpxNFJyj97
fwSXqrnkAbGOuJtbeOECIpgFF8TqY0mk+bfu/uXwggxU8bMyzPUf8Av0SmyCElkGF2kEvuSLEG8u
TpL5t2ooyRPhTTBg1uV7ADoFRyHLQ+wc8ePQsZByZ/HUY6VEiHHHzS4amvalt34xgQq2/tIUz+3S
KBcc5UvcOlW/2wJgTj2WYP0TzxvRKT2lWSCqHRJMpN8itGgSTP9hNLzzqI4+XhmKD8dpsNlpDXg4
HDTkwxnZsELFHkMKhcyg4DyGlXr/phI2tD5n5IL/z8OFqUvw2LgjDHJKpGJiNsHgfh6jkOVTPB/j
5vkjMFPqdcrAwZIySGnnQKANUYQM7wH8XMVtLJ7Nc6PF/hXcY64j85TzYEgzaMrXRnfL7O4DbGes
YzzfnvP8o+2OEbot3wNsTk5Z321N2Zew9q/tDfDswvgp/ZvC+hzK9FHA2SG3YGXUP/JuJ1QsFsSc
13KggnMVEDiqbWu2RqA1VyCzNUqfC8rdBrFm4WZe+RPI657C6m+ZKF57IIaIQxmSazUXqYQp5J0n
GrOQF501GWCuJowJx4hg49wx9plb4zB+fpE7sdWqr17RJLwdURlXZzsuI0NOVsJ+QmZwF76qbZpj
TJV9G94VfO13S2IikVuSWH6nVmEKVF7/mL8gD4z6SxtpWMqSh5RthpM5fJ5vUg3RrBVYVNRlNm9R
Zxe9G34BFf6wnif30IatVHwgp4D+AAh4DfUDyGEbhicbQ2eKOdepZ0OjsIfkrwD4R4/lZNfApjD1
CKx3NZXCdeJzZVlyYL2jOPU9YrwjE7sB8YmennsQZQ/xQoyvQkF36ShlTjFNKPhM3n/1vDo5b2Oq
C3TTGrXdDqzc11GJGTtj4Kh9AjvL/dSNq+kgcJ0jQWaH18H23g8JEuR7tWhveaGs7VxWlzuCe+IH
wqUUlu2dkg62rndVyEmEDo+rebiht6WKPo9BdRk1RSNDQ4g9VK4ui6+p7SLswSAfpEfhUOkz+tzn
oOhrPx+sVjXMSXSFRnjkLsiUAmCG000WFvMyBtv2jsBvdD58GxqliYKfEx6A3+eQra3CNpqZZHkd
rgrOFxvroj7xgnYFbfB3fMY3HF+WQql6JLZHITmuu1R+lRPEgfJ1zZE72YNOgR+4A51vobOiz08T
2qUU+jXYnFIQ7idcrojgrR4jg2O9UdhZFlKhiahQVUn73BhQTbbvuFkeBzCwKBOzo3Or9a2uEAqG
RbdZQ5Jyutm37j5YLgcjMv/wiBFv3VXxVbzCbjvcZE6kq+xqqnaqjLPosvsTwRPlLCb3/Ma1rJcP
T4VWvH79kvd7NIcjA7DriBNcp4PfNBrhxWQebJ7vheVE2Mcq+e8S7qK7ic4je+64O44Sd+B4x1Ep
EZ8A0MKSOn1Who2sZ1avRk+SiaLi/Z7PLm4tbpInY0Neo9RhD4E/cSj+f48oMZBocNTTNj35f9YV
uoPcDcYg5LGniweHMvZ+DDOcox9EJID4aFfO3mnDLQ5taBREwMcfsSLPPi/nXaFs3e5MW8ILd8dO
6BtJGacM0yJcl3oynB5b/d+TD9NMcdDnWK40IS88lqLf/W3sKHSHxWRoXPemh92cKgkdduk3wwoI
G/sMCAddv6+hvYkrnJ38MZotHUKA3s3l3ZRC4kkIw7I9wHjvY6HWgXRdbZzQlXX9KmKDNPUbYydZ
LAhpRgeX9x5Ej8wd7yyT6q7odblXplA4eQXXwECmYxnghkWSX+bTtrzN1/FH/LgZh6R9hL7cYJhQ
KJ04PYNV+Tw2LX6R/xqdwCdknKR3pXPxt1rqR2hH9mOLuDtcdrlYS/rDdpJVp7Ysv31QAu36BeDI
idnh7mfjc9eOlZw+iBJxKTwTmFk8WFselzsE8ln4/q7seJj5MB/RAOViN+IatninNKHtRfywJzJo
ZSaL7I83JJOdJCw8vqjLwcpVCibLz03N3nhup4HWqcvToG4SuuARnZqnF6VRQvlO6deqW9iRbUha
XFuiXVnkI2FSH2ZJsAX9IbhQVJUC1xWm5Atc6rNWYjrv+A/Uitwdlr7vz7u2gC0TsM6UpkYorMFt
kYCQikkmrChoLFXf55M3K3EAb6txcHk6ExSIoyOdFhSSI+HqnBTFPGix/l6dYaqf7HIN55ihbKSe
66moaNrT3yB9jxzEMuLfTZexxOXmjU4LCn2V/fmkNSGfP5nBKO4th9DpaiD+9vFPFBzL1JtV1K9T
FCZg6CfR1TcEhc9XwxxQjSJH+vixPH7FDmFLrEuVYcoeUH6572Qid24id5a9oVcKdYecM2+gIX4w
fjhzsFmj5kR2X9YwLdYscqB7RTTFZSDn5isFJ09glc/1qha+IGj99X6NDRZP6lkPq+9/M38i9Nhn
PYAR+9fuvTclPXk/yWIkHN9XTycP354Ubj0DNy4ReoOmpHyMAFZSnprMUKB2HqHsF7Gi8bt0FYcl
BT9wj6nQy3oWVL/yBwSoXlgg0ff2fgD+IjXmW2xAj4guDhtX7U58LWzal7mR76xdTTM/6Uw1KeuI
0Fgf0vd7/opRNCB95lFirXaxFOpfNv1FsLiamt/VcMsTPaX1Sgxq6tRs83s95RdEqgh6VAtWGyYA
fGe/+D8ojmKaLmLvDUOTu3XkF/U8Gd1O4vMQpYjROemB1XrcC01PHyJVPAA3Y7yF39pWuo58mjaN
gvzjCkgZBJoipOvW6hiBiNDbSxJJLqowmiKIdgj65uVNhJk2fj30JG84XxnYKolV/gVkYb7F2wK/
LwqzxEfDAY06u2DGkyGvE3kIMzpWSz5kG3IEMsmI8Y9f1xqjZjiCTGXeaipqj/ji0ebLa0DpQ7b0
hyxCfwF/CZcAh/UOpF7qdPW68N/tNOcjeULLh5OeXVk+kYlIqczenG4fuXe76MR3ixf7gUcKoKP7
Ta6AC0Vqf5LdjH6F+Q5eB7j4y6Sn0QovydMe6Zv+yQW84bSGkDZrS1c3F703MqYsd060x7W0X8io
DEnIeWLHG5yDMMUXz7Mhk+SsTLYNOfs5ctuIyUNZD8QC2IayxDfgPMlToLtrlvNbSbEr4cmxgtcQ
QYET0fXgq+nRk7IBGHj+4jnly7shGihGyQvwFdtYWW1fhV632XuZZoKH+hhs2giLcVq+76AcNCdy
mj9xsIzUrjM7dB3DzHOCKTFLSlwMmYD1Avb6y59i6f/Jz+j5W4bLNtUDZyjBniwQkcsy4dxYTcJe
J9Y5vo6mF4M1rgLDPJkL6XKaFPEnlXu6WuIOvDu8nhL1palmC/4LfNOz5tDEL9NgYpZj+Qs43zvH
ST/VFSqtdg3mmyTaqZlISOaoTprRPIAUVPjJSpeODphc6bh7UsVHD6lRHH4zYHPD3TackV5Sr8nL
dwjbAvH5yTeKEtul5DiDgyLRIQHpyLUndPfUHbbhRH0fbzHZN11g2DzXjxQYte1VdGw4nQ82qp2z
tP8JSK8InRnnjvRRnaUK21F9Z1vZ4yKMZDLoZ6i7YLRmLBdRl7C1sVdlcjUfu1whYps9KhECk0VX
5b119BBx8GmxbBwI/gLuh6PwK45yJHLykCJfuzcnHcoUaFlFv31OLucTxemvq/bznQ5TDp4IhRLb
4zF1eDbUW2Bh4d5tUAp63BTTwHg8S8QfFy5yrc3Y7qaoC5lNiFjN9oDSjLtjRbnhDYTcjyOmv10g
UdF2saimeGDSWXzy33+VMuCe/jcCDW+ogMkxhqac1S9cEY4/5BTfOTNwfZUMmuY9iq49MimkceU3
/3M9BaunFboF2dINEhwtx6syJ1F9+7DdDqzM8FIgNd3FuEOy8JdN/DNQqyvuSxfNfOQgwxbeDGPr
B8wIcAZzhlk60cxqXaNuddXMf5I+3kHRvd+FMNMY+SoFJ5sn1708Yo+FJZJeln2ifTZ0HQG7eUIQ
LqAT0EH881/z5gsObhgvhEeJ3jLLA58BzABgVs8VYw5ZLws/sJ7HIsuO7jhc/BYv5gzqLoZSe3WD
iDAABKx7ND4uMkzK+O4ff/hJE9ZlhfRJeS4Hcl+xT9Ly9NWzNwN0xY8RMd9uJTGlqTuAr9yQjpX/
EKtSAONSxwlNtlBXNdbz1cSt5eo2uGO2W46BlQu57qjUo5s/RPj7VXpHsH98OUghVfh5boyBBvJp
2ROyD77HLsPJV6/mbl+8IhKn4hCZgdN53OrKTFrUM/Ge2ifznrazJ4+ZG2uU4LH4o5iADfbfc9k0
NUnP2uJWmhzAEnSoQeDO5EklqEU4nBtOr3Zw+OBpiiY0PQsOyG1i0FLMO4KFG7AjmP7TYkJtpDrv
XD0whEb4PiMwtuqGHBnU3ib3Mzqfmm5SDB8640Pewo+EL6jBXP8IkcOZRCCnKlMF9k1lEInlZKvW
0HXi1fNjJ0NZjh2oLX+xI4nm4rRvZVxmnDMn6SVN6rnXLV0m2kMKMLJ0cxAboM5IqWJ0GZiDjaRM
x/p15bufn++VRaJoMz9QgKErVkpUGo6c0HDoof3ifnJs+/l0+qjFkX/EZFmhsvdzNYPHidVpl8ko
71R9BEOReiT/sBKcA3wiepBcBLbhuwGPp3geOnHeNLjtbb2cXdkAC0Gc0ICsPmOh7UrtQCgs9QmJ
ps0O7fFQheJmhkGGlScdNI/AKuQxilpD+65OA6+3W66Hkiav7p9aJ+CtM+EBss2GarhagMeJ4gth
NXdaRy/gEvJltUqloKdQZULLxHx08F5hhh7J9H5dUkWvMGEen2mOkjaq4IyzWl1TY4KEg9CdWlgf
pdfAyOi59ZLVOJImFy81f9ofqqSGCnatr+j8gRW/K2SVHOkMktvGsAn/87UE0pmuqV2FQzvfyNHS
iLg4xD42DkLQjNVEwU1/y4Ujzyfvsd3a/gW4FehGWnBSDsbtSMIT6i6TtdFAXMQyE57RBlJrU9nz
ZcWOTUrsWzCZHPBuz4c6ElW18rIRViDNZ2dgR+3mz5Zt4VRTEvzE7PytoS54B2UqPYNd0aak4+vX
CW37cP+/7MKJM0eOHDNXlbiYB+6fAfvO0w86qhEoTm0YIH+uJp+Z0NdlNPomeLLZbmSTUPtiqI32
rEUjEGbFfKLslQdJxBJwdTVEwpuc6vSMaaI1SL+C6zxVYATjlnbrXbGrCoJ7wke2i4LUmHAlEvDQ
mA3E3oGhbRGERSCved6yYzTpVq9lUQHidFH5WsiQReABK23Y6TIHZ33NP6LzWpT8+0t4XgEc+iXD
IN88F8zyGAJYAeZYC/C2iRBMiBFRhVVLvqW0OpegOzZwFy3Ruy0FfgJgiLOtIkN4ndVQRP33lYXS
6aIyuSrYOGYqPY1vfcwrTzPLuZZFB1IyijBM9tTsRjaHu9GifA3H7vb80/Z5CnWTUjpLw2MWSdbp
LITrqOKxvcXVLUbqlxHo0l26vUj4fRaSHxDRpBvBhDTQ70coXRHQNLOHR7NV48bu3lIoCR9h+Fpj
K3CDxXIyvaiemkELl46jgilA7vT1IbseI7oKa0ON32SHLB84q4OrmnWPMnsawgVIqbtLwSfbqM/1
tqQFXflTESMUAC4T0WXeGCON8wh2UbduQ2SeZqcQRAh2JenM6g4E5l240gnqZN0jefuH1gAO1iFF
hF2mV1k5UAnuTx+XHrflrsMCxp2Sh54QHowDKHwbUiUixpoopTrLN/pTHfLYzOmx7XDQ1Af4hjc/
MfWlAo5yjqzsCx/Dn55dEGzHjru5eeTsqEkAuyDTNXlPPg5LZ2djyf5EwDJdRkhWqQTjdM3TuJX/
TRN0XXzOlmt3qsmxmM7e44C9FLe0wyM9Zb9qPcnZSdGxr9Uroqep2SGtWJqWBhP2KAk5n+J2eDbr
xXgsHTL8b6NRleoCgbq2BDiMzR1RL5t461ZYtX4prAdGQO/HcPqUZvLnDfZB81LFDTVo7Es9MLG7
enK9AZOiy1+DJ0TeE3mwpF3zW3wu17RI1DZ/j0f3XPftw45mq/af8OzyUbZDKOzauoqvCaASZjlA
lZ9PMGBJaaXdKFUiw7OcTLYvKHPC4vW08lMXDwdlqXjilrbrLAje2NLl2qlyVm8t4M4Giftj/y/M
VXQ2EclzUKxJ5ZMshD9hbHzZib02IdpCSCfXK4ANhn2f4Gmkooa49la/KsHmBklHONXh2AlaKQCO
0D9KSBILw9Ek4jFQwK+lBBOvRCylvyaskpwTcK5WL7LvUxntVVT2LXoCYjeeANsnW2PkVlu+R5nn
HqT2/hI8Ok4Vey+SNldm8Rg/D2hTFNREvPl+YIsVo87VWtMebifKFaX4/Pnmm9fvPUhMiYwhYr36
/WiyyqYNgeOYK0W0P8FKGA10GAHD7+sIpvvfaNZZFpH2CrPo2nGV5YXwFuHri7C1aTdiOyus9tVG
r1l0o4KP6MNJGplQ0gCI7Qy+u9Yn+BDGmi24VdDU5uS1tmS1837HtBbzAjLyiAOYt9/j+WHE5wTm
krWiw1DElFBA7W7EwfBLKlbfY93hatSfkt38w5R9/BOTOotiGhXGJNcXiilz0HlSFpw91JdKHPz3
BDzUwAM99EwRkFQvQmHcm72OL94Q/qfN13zTL3FsfQx+BbOroyKLf9E3NwiWiUN1dMmdkWhSrdGO
Uk0ewgc+Z+rjXrURfm5maNVm4oSlXu4zIhHYVlF8LXyOFD0nHy08fibrcg8ZoB073cRiBkJinxuk
jkK7/aO6QEizj4KJApz1Pplwq+PZ57adXl4zwG8jkCq8QC11gzy8U25+7RB5a7M9n1tG8w0VaPFY
9ExZbGAtlJ+VHihfoueQZQGWQqgR2wcQMa4WzVFMw9b4kx8bYC8mLkq2i1tOecx5zX2obSZpmEt0
qh0tFkM/qx40fNlIRO7gl/a87fr8nZpws0qcdbB1ZU2TfJg66s2mW43hexP/J6IUHf4tI9I8inO0
WqOxQsH+K+xgPw+dSdbr+1HT6aG4X96eHjfLl2tJ/mJogXbpapK8RwK0LrzzI5UODrtHcSq27zFI
K6K3JvGxaQCExCLxmWck5aw2jXREADYXrXPjwVGQoRDPzCTxt6n/LZdGvMW/9GFdpE0NeQ6EA5R0
k4X+jcqBdGWu6yVKGeF8/+4bDgxp4pZj6kwvH2UCLBacPLUMX45wNDH2vydSGsoF8hvg0wfaattN
ahY8xXGokK89huJPnB4FIfCa3eMsGDhMDHijhBNrUL5mRqVJ3yuVAdlcM2iXQE5Kufaqr9Qyw47M
+SJax7fCsiLz7uL0qYofBmbvOTfp16rOdigDMlO6Y2dylamYNIE6heRL5fpENfIWjme/4iN/g3Of
J7h3VgX0FLnNOF+fZ335pP6YLqPLWomvfq2av2dbLiQ6GPtVDpUd5UV54RXQLnSDtqyswzbHI0cx
hq2eaQLIpCDuob4HVCmOU3+tWu1l6wAo5DKuoky+5KNzRez3S3Ro0vF2RTkpF/q9Dc2iMO1sCzqH
TXM2sw+8vdG4WppYWROEiVQzHyNgkL7BqB4/0RRH+yoKFlmaQ7+tnKf4LQY5dqtHm7KoKGo6p+vr
xwvfA/4GDqJoJbeurXwdlSFBOquh704b1RbrN49Vmi0LODos2rtuKDfQoiYB/LWWzodpG1UieRVp
LpTzfqkt6j98P6wlySNcDQTj2xaH6ak3VQeiVVc2rGFW61YoifaSW270CyesSc29OQIvC9hqrH4E
E8CBpDxdK/yC968iriYaVBTUG3/JMy3M20/5Fzh073uVrsI55YEEigfX9tYB3VT3IxYjRmuhk1eA
Py9AGaHin+8qoc+MNqpb7hP7UD5/WL2tycSRIz0KFuyFsoZ7KKq3yQpMM373OG6a/t4DdabOLtOv
6KO9ICrvu3Dz98Sd68+DunY9eORB1/fGmNfuaIeLdGcco9dylftgx4R/g5p2VGglbY6oYj3rjT9n
gCW/BW/tvbPdaAAc3WERPlyBB12g4EgYRraAjGNvTZRtB8dDJwI4bPa+GR351i7sMiToAtrBUADR
rRICYK3UlCHAuw3XBG26cLUFQpUvT07hxJiW+Ps0vYE+BT1RQNK/101+uo6n/vZQ2CmveqYP7O8X
LrYbq4OHS62qkURsIOiY9Z3w/g8CTU21caSKhAIgaMCL2UGG41bYCNRJRDH2MjN9eqKF/6UwBv2B
EtLsPYKgmxJmHrj+jKVrDzzcAH5ZEkN91qSLf5TMcZiC4lUPAqJxhn5L3usF6uDsyGx+srq3A8HS
WVLaFfA3kD12CP8VEZIIUqelCtr/sfUSrv177jzq7/c8VZ0VP3VQqWsv+Zmz9Qe2YEbpQEmqEme+
LUHg2vOrOV8kf6e6o0mr1ZydKXseAnZYE91HRVIJEOVzxXUpHnyFDlKLvUMLqx5QPoaZeHgZhArh
/EAI7C5pnhKbKQyspPNZ5P+J2xAgQWihAmrmUBpFzXoDAy7B9jWZ52u3kciRvRlr7tnblsgQpgjq
FWsOebyzOPrlSfFjKyDtibctNZi27ZDyRiiaZxwihd7kKUGzK0Dh92tbgoznqgTNcz+z/WL7hvNv
4df0GtxnE444efxAisPEhVGD73cO8mh3xMxHupGVctR3UuIMXe7Ri4uC1CdM2jEvbbyf7xZsJmmR
o0fohh3zaEOTOSHlIxgMn9H9b1TM/mEHRrnBKEu4/K6EVGJ17xzp+uKrFvECa0gdA2O/GLJWIcBX
L8RJXX2l1B8n3t3cs658PiNt3Mu2VHytMT8XGQHavJeitD9HcbDDpfVk2QpWYukVmhnJVJPTcLiv
6bpys+p/oKAHuCE1qHMiVYd0dFOklD3EtKEao3CsgaaiQ2mPDDLFTrcxZwwT0B6ppZw8u8U9JOuN
xyDLyxKuV3vPtp+sgPg44kAvSk7fW61miFBmjzMSE2ImPT9XuupVzOPAjaOZS7lcPzrYdflu4OX0
nyt3A22DdLoe+8TUME7+Qnkn2cJu5++t5wh31oYGE37nK1w8qvtbatI8UsI3xHn3SzgNhHaOaUxN
Wyhk9dGFncIUudNNFaaabaQOhphsW7F5GQb4T/5tUNWywx76zeXcSRKDUvN1iJir56wZW9yZ4WVd
R5eFWp+o0iF49rAzn7f9JTM9ZXmOL0LEPvv4P6zVpSLssx/5PmvFZSuA85BOmo4zU9bfZ/KLzrYI
/Gya8Faixn6Y5Zj7hPtMwPc9+C2BRcXIONREAjaoiIu5DIFQhN6lTe0+I2CON6lymhQQBoh4KteE
3+bdgFfRIPeAnca0UgVBBfRU1MrXOGsRxTTkN5Sr1hsjh3Y603rUpKOLdGxw7AKuA8AHFNrvL5oD
Ixqy/7Il5uRcRHu4oGaVG5wkxJTAk2QXpnHVyt1iA20y174pnOKQr/A8bI/+NEMifTdpHn6Webtf
vBAxXCcFmJclMe9UI0479jH8wnVhoeMA/DvcM+66A653bxoCZjkxP7ilLtEeWr0Ew6PJzNJgxdbn
WmBPiEh07CL1mgFl0hI1s0bjDJWohiMWEUWhUgfA5jYE6egyy6v5gryu8RLPYjVu/I+sgFFFTSXP
AM+CUgiUDlHPm6Ja/8ZujPljds/2R5HX4uHzkUuB8sEDrsmLb83hICyU4V2iKPzVYln1bengguwx
6W0xzYMJPwxZrvnT3Xh1StmYTHHkHeQtbTDZ5PfrB2HXtJsruTWXLuKrOk1T1NbR0mdGgwCRKo2V
xN2ITjryF5ingJ0ma9N5HbZ0vEnSa6cykjV1Bfpr43QipOsLy4xbzORvXikemfCVwEbHV+rvZYet
zPqX7pOj+E7oPl822SVqdjeU5Y96f0Id8Ah88S+jv5L+WeRLRqkrJpTLwA6679uCQ9iUaHI9FpOq
XGIaVYmew9k3Q7C8OUGDRxnW28smHE/5R9EUO2uHDH4R0cBjIFpE3fpipoJBRukbAgvGLt8lZTyy
3mZ4TCK6AcyZPIwz2/pauV809vowHXgd42N2Zxv9ndpVIB4seYMrS8ZHvPqsNXBNqu5eTuWoPmxp
8McVpc2j8CCl0Da5OPvO87j+HCGkn6UHpEliZ2btp23q4mq5UocHXvq2eRBlpZRQe4xnmDxpCTiF
o5cn46FEv/LK229fxynb0+kwmV1jAHS3GSVRskPxCUScPrqHD+t02CCj5J2UHrwNwYi4AzWHOg0g
883uYxlur9PhR/oNBn6HP3wSA8yD2F2fUm6aVXxpwKbwFo3fE2FSHj/QhC42HF0aPnKXoMl1gGUu
RsrUNmIn/FdbhKUceOOX/0r9C8YkYhoApPglItDxed6CS6kE2kgGNrwGtRktKJEVV4bFEwdA8KJT
tOIwO2c5IyTgETTc9z8WcxIMPZKxCvndwj+1i7Df/eob/dxo+t1/d83bjAGhhMtQhOsnK8bIWq0c
AzGLeWnBH0PJ1fNuAjG3lFyH77tWqZT6S5yXw0DXMpsAVbK94X8MHuOaCO1VGcOSQ1WZ1zaEBs2i
vmKSJSNsQvuYSvV3Gfk9AKTsVzZcybkM5uE9BgnqJ8r+Bp/JT4b7I7oHKXoIqFmYWf52BC1wugZo
sY72q8UPPXNoU8eoxBJAS6D+AKJzBJe5tH2X69xAlob3e2ay/Oil5Jy9HzIQFwAbOn5SPeCYsXBc
GM0JBU40VuErDB7Sy10UWAp3ZI8+RlOWHZpJe1t7pCi9BFFq03WUND8o3Q4omcgVPlxt+7DpR/9t
Q/RgARbB04h60Od2r39LmXvNUvRil+6oE7p5JxJ/BQnGxeKYgmjwsSOY6bcPA4TnkBnfUcMMMeYr
DBPEtPjX0iZ0lg0T8cO6W+Rc/OBqvzPFvgYmgq6xPZ4zEKHpJafuw2o2RABuS7eltOkgXnRuBxkD
KspP5SBY+KdeQ+yQuV1T7WxFKoBNtQsDTyB7u7GB3t4NJuDGCgf0I3HsD/1ZnEvh+hTZx5I9tLkN
bBVgsrdlrHoUP4Mq+TqtEiSnXOJTcjjW6oOmYe6Kxkb2KDdluAEfV+90XSwGgU3dO4scjSNRwMVU
G6dtynNwbQuySnRfJolvigj+yQmzxDmv/qynlsnJBSfHSFOE0uOVUwLm5wxpaFV8wtokh7T7Xz2G
3AOc3tT5gvPLjcZ0S7Zq2ZLFPAWxoQCzaa5T/IKbJFvSorUHyRkx8h0AjHRGsV+Zb/Qmv7hb4zXt
/X0FE2x14QiOnX0s1g9HG5DXee9gdpkSSWNDnAcrG3mra6HRPXyoHEwOq5yvHynn9KDMRe0G0SRq
F+aBc1gWfeWZrsqqhZjxvvnkYge6+srRd/Q8VGJSY+ZoXSqq8G8QkW5AUQPLvH9HFcFkI1H3VDK/
DOzccl3iqTFuhXt8+pCFZoFA35P96ld7lukyMJmTM59JDgsPIkn4OrlDexe+lgjlFX1TSMYk2Gp/
UL5eFF6GW7xpFPCMr0VeBHC65MBrjaIngJG5Q6XGgsJ+VbIWCzUGQ/8dQV1Erqf0TYN5Qzsf3ac9
LwgDZBqkGUQbuRxe8RckEhOXiWeztEPGG+Bchv0yAdndMK0Ws8x8TB6c030i5h36c3/k5ufPCfuA
mxqyl+1PzFPJVj10C8EEGUVV0HN9SzFVPNzVVOl5A0zKMBUbfF427/W6ppWGBxVT+Ts6/vTmPXEk
HiWt5s4azYx3a0zS4nJpafTKJP/w0QUww9EHJkP2z9xImNqMfaQ3ErwDAlaSMPIwLhIRVo/Ei8Xt
2NRgDGTiSiKyAi0MEAf2eQR5UxpslWXTZEXzJNG8gZQB9bkulX9jWeeKeqEOgDYnl/DcWQ9xssXe
/rClRxDdD9UvZhPTu8fAuSs4KVV8g5YBhsE7QuoKq8kD+jQ5hk4aAfzLg+akxlhyhH0lgwLkz7gu
cytLaOHQXp8F0UWNd0w9vzTZ1oU0YbDZteAuAzgMZqn8wlfQcAeJap2WLLZ8Gx+1uygItz3wfXyt
YxR5dUSPWE2P0M6puHt9qAxzBy1DTvZdPu8B2FhKzvUvfXL5p34/WX3i9Gsi8OXUD2N44oMUk79Z
oHVWyYIXkJZYn1IBfEU5krFojx5cfWo9GHM9xpgfYPZhVzEp+yYoVS2/8D59HnJGpe91UcISSQJW
8rGfH6GgJDhvYfe+mQK5qOnZ76zTJtndXnFcXD+P9xZqGmDjQyxwR99Dvuy0WOZ8DX+p23dDEFcN
gdUGvMmIgAmSzO5MEuT0f6cQktgupiUWdlKo3o8YjWrwSV+bxrS4a6quaKLwvQT1LGYh8Q4Y4lek
5tQWiKiZeaiMSEMQnSS+HaePp7WV3KlrH8f9jBLKI5XR88t6h96YCvDlU2JxMylCWbJOBKklk5L2
yK0vvLQLL3nWFyhEhIA2qj8WaCLm5kokxiq41nSuRM2L8OCDsvR2HYdU46LrDYNvZIPYw6zICqx1
nwyePlz3I74nl1verBJ028eWEyBG03noT3NI20ChdprdFq39ZjVvIY3Fj+doBgDghl7EXU6rZznu
nAht/n+uo08on/7vDMsybFF77cgNtcBVomJz1CZO7j9bOP2Q59nOuybFyFbWKFSD51iyMeuDQcP/
ss7cP5ATr9PbXvU+w+/5uIe1JL8w6yqHmFrdrTYr3JWHGvDRDVRHQ//xb6A7F2RDfydzxfffaxDE
mKxAYxaORtyR6KzUyQBGv7OQmFssTrXPJRPiZ+ZWFLMoWW6fdPggyzUz/ulP3XUrye70XQQafMXG
6XJeylq9c4hW4VRSjFHsl31X+OLX28u9iJhF6kQ6C5wxh606WziNMNqaDRCg/04gO2LYPBvnCH2w
kGqpPvIvt1IitVKfgrUE1UFLh3l/WOIScik1fpDAdqrl+PhpdIf8GCCEamfU/Pzautju5RcKNS1M
Ebh3lSBYXj4Lt4hORw3AhrDZ8IDP+jGF7W/9kh5yMmCsZ+dyRcMY1Kae4Qs3+S6SN+ON5+MWznh/
luasldonrzw2IUMJno89S79519dzKzmKTx1jnb+f53yToASdKuAa0KxXVPnaLn+UdByNNMMBW0J5
9H1+1FhcPz0eEcEz2tVZy772r77TMlnAubxpqdOOxAeVjNPHmrGPtpECDO6aA6TsfnRY+6BAAyXx
9mFezY1R2e1ZDNDxxNlRpgPwzk9YWFquuZE2ICTVVTtFx7FQqhKeZ1SITp7a1iwfNoQ/aVFVd66M
gkPiwsQo5tfdaO6wOiteBLQSbsr7ndks8hEp9AUYugDEbiedNSvMm1UslaNzFLaq4HLc0sJX30MR
HZ5rE6JCl2/WzjoU+Mw/y5B4/mEj75Baqr1eVp+WbT9OpQC8Tm5hRgHl+NREhxIgIzJ+Vz0BFUQj
l6GNwKdDeOJ+iROg2/tVH9z4csR5y7wK+tJ6LaDwPH/JKl5MixkqI4teC3JI8fZnIguHsQqJhph3
b1uDMbKrjRpE740odcid0LbfMGcsDgPLCUBTOeoUe1XlCEYD6K48jRHxOqVr/Zolg8me0ZW/5uS9
DMxo7ie7qPpVFyjBqvlzJOEV9LeDuv4r7fvSTv9MtViMcOErdIouceUhjwxEUEBKfbB4R0OMY7zO
1tqgbKJVQ02wADdMkrKOjj4QPVnq2KbP1Sj+uM0QfMveI2t3roG2U5GTORXVxSGQQ4a1zdj/1CqW
FlpeN/wK9ikV+1b4J7FsEpT/Lu8ibn1RpkXPpTvOU4TAyaIYWY8H6AOWhrCHhAaBo+0txYGgN8AU
IbOEF6EcDvpizgrHWG+FpXbUqZlKUBXHCpll8FTsQ/yD7Dlbn5VzkkUlOmZlBifhvYPN7psEMmq8
xYgkavz1+lRjlOw+bRoepI8oInmQ0+ozKAwSzkuyu173H0D9/fTe9vX75YTZEh2sa9EAfuj36PUL
8zP+E5lRUs9Rlo1GayWHcQHggNLTa/37YlH+WypaG1sExpuA/Mut+6GBsSrUlCmrkz34KUhtdUEK
Z9TDPgn4IGdaEDxXwzc9tXeM4BuGQyAKCZVKG0DkKpa8o6Dwo1CfcsCoiUDZ/VemD6KivJ33aGcy
X9LmNRIOtjGao1fLxnyQhur0kJzw8ldqYqN068WzIOhfsPYKjICYhLoFSf1D8FRkkdm4Ajyf/l38
7KC2Tkv6TvgqCz4DH29TEX/MjujO4cpTJifCsOtEAVxlVJnpAbZHlYjkkf2W/EQJPRD3vbx+P706
sbZOGBGUNciYuXAb55lvtdkllDZQoYHfoOQZJ1/mQEjoLeSBDMBd7EmpRKNFHrhKAHC5zxmjszo+
8Ufhcu484veN32fUpfQhAcX/4ocvRIjwM8cKMM7udrVLYSdJrmxg3S+SC/JpdEq+5pkkonyS4DQw
utQdFAqOV5l7RzMDkSo3kWF4oRZZD7ReTf9V4GK+dIgOq94k2yUbBo43cfixKjKow+FCZTDA7J66
6MwkE6ZNaKyGmDxTQKtXa05wOto3R4nAkmsEE+w5qVAUYYzp2n+Ka1xSTCa6BwEAMWQBf86uKgn5
UK4q1r2iXeUrjKn1Ss6FLQoIaxBslqWUpu4NYYgnjl8lWyIeVpLBPFDWfoutlUcP3UnJxamcLdUP
5HMyhm9g2lQfHaAfbhMLGOOwfXRNtRr0O1YcOqS4PkR35scHH9Ctzra2tnGEA1j013TLTpi6LBQQ
n/V7NPGXQPKbPj+14+D519obMSqxz3NRmUlklRgZMIQG9xwBuk0+xPCdlFetkNnLUvDhDr6qYaEa
W/544Bkog4LnjqtaCpyw0QIJf7sx7eYXOHsqbazny9nM551Brqtxz8m9wxRSxhYg7l48Nuic4Q7Y
uXUzJDijlYrVbuZQ/jbEmDxX/NsGFmcFz4pGfRSgcmr+X7YKnfT21HjxTJ20YE7lFoclrWV+xObE
1NO92Vu7D9xWQUL+F1+h6mZP8YjhsdTTwxSOBQS/ptvxymxhLP845w5xIHkXwLqIu3u7yHyg4+dz
Gvxl7qUpGS7hve6IFR8MATgAPJ3xyKwml2QWPPaPr+99PvlF6ky4zeyYC1sM0BS02srAvXRyK9y5
e/vuzY3vBqs6lYT2UWOaf2u5xAqAIdYOiN+6YTgWlk/lyWDw7Mqr+TPLFQ7wiMquoJBmWA8ygjUf
lNF5wMJ4+WD4SULLX1LkGd7F62IEC4Mo+84qtMVLzabOyjhWZvgmoFnARLkiB/xPPYov1B6oI+UO
lKKUjTN8K/cSCbPEBcGY0EFSJ7kPmYbZWAoz17H4IABwRZQEHvvDDxwnqERqfPjBWZAZofUNM1hS
mIfQRY6A4L1AGzLNxnuKrxRmYgA4t5Sdf7vYAXteXoEDmGGI7FLdbRaZTn4PuJOxNL5YIRL/ZC64
oujGHgbQkbuVcKHeGq6Lbz7t8PoLLpb0vPTusW4y2RuFUdJrCaAjpvFxoW4GTSMB5nuiEwDiXouy
JX4xLi6FeUdkOMb3Y2dwWCPFlTvuNkBDYa+xcjCza7S6ssz+2mdkJAnX+YKJ1N3ToYmXTFTN08pW
yopz2YkSMb0C5ypR+PxIBijWMvZrFRF2DcJl5gxpYEQwN24TZ11ny77XUE/fRq6lz27wMtHPS385
FvGdwDqei81IUxeGNM2Vzx9USO51XNule3npOclS5q7SKLx242xhCH30DEVEQ/4QA73x90ffmyEP
n9CHfIPVO1k3ye0N+PWxuS/qyw24QwF+QaO+id2qsaHeZJjE12CowmnlzKQkydOV+164suXm4uwc
A8GBQ9cY1ICrpAFP+6KNqE0GtlGhwkclp9qp7VSsG6VWALxMlzUE3N0He3B9XMPsVDahW8/WbNUf
MOLaYNid5EVPFT+xBwfqV+VVuyUFrqCKSFoAJDccJNORxDIib8vADF5sDY/Cg7TdoNQ2jOvCSRNy
9tOorX016QZqAb8PNvC445sWUlt0PXXOT/J5SV2ga7V9hdKM+pVEiX8DHcwz+orBiCYRgtCHcNZx
ay2HIEurPdGYMofFA7pepWxBD7L8Otm53EsFcRL7Vhe7F9iOOhIWMTyUXxV+LccJBdKOpsURBT20
hcEMCsDX+Lgebo0wClaCPJ8xQPgVE2RGDnAtusbr6MxOPVe9y+22UuTC/zYYU8r4uLTETqQZf4WG
JeCeiMu99vx1Mf8yaDMr9PoLSoKKRmeUv7+BIwA/6xEvZbGr9FLdjxu1PgDAFMFVk2lFX0ULRMj4
hdDLUpuWfKfzovPkhfg68ZD92NNKH9gKezt3/RZw5ITyGkDBdeaymXRk6qruzQ/R03uUetlOYB/2
iXUHj4ymqNqw1AnO9vt4I1/Z1EGjW24eyekOWREhEsRp6xlEpWr+snfZOAp4w0Y7aIXqp9ZrP3xB
jVXA7YoN8k4ohqN+HjW9uRYYtKrTWBNnQ0JPHt7Yp/oqhadqUoELpg8ypGvkJ60Pz5sZ29VAZP+P
WvbylECA+tNdhduMCCDiFvs9V3pDOUElSf32VDvXxbKCkd0b2Z5NGglyqrvfCls2ehwR7F8PZRwm
I7ODuwMZ0FScvg/E1BxpJRpQZDJFmOA7FgtO5AiAJxmLzvODuO6hPrh9wU0q4vTl4hcmSo3vIMpp
l0Uq9JEMMlQrkQvuGKJsdNtTK5mH1XtiCuuAMqi/Ra0RspWiDnAkSz8+JwMrQ9obHd7dAhIUyCkq
QmDJjFMJ+vDYCfy8jQAZgF57iZNHF8CmkT53Pa3Ri2HLjf9wKKsgEPdcFc8Q/jPoFZ0/pVhOEJi+
REDJ6t/mLbUE3obRS7YGaLc1QJ0Sf0pvClddVjS8LD/+aQq7kc3hmWD6JUd+m9BVATUp2ngGZRBV
mhHBJDOBVheDQIaOVIhZ2wpySVrbVEBeNw/foPNIcNZsLMdf+MUNJV3n4jmLptuqKctndv8WZsKf
cMEeG80d4blNsyTi9hGKtGkScRGT1x08jTIDBravuWFgAIxc5vtrzqPjbt0dQMEY7G8/XTJde91p
7enI7PjqR9So0nqgq0DnnDyD+Zwc3JW89V9doh4jYMLKhW37H4V07ct5bCKbGB0FhgMdvD2iOQ4v
wiqrgIaQAtTSq/Jg0ZlnuX7n2iR5HTOFx8Dbuiblbz8esOYtoNr/TPWB5YLJYBg6doIgxF1Q9AI1
NIKR8cV86yPBeZL64DKk2AvwOtr/jZw37/Vj6LhCzi7Zcx/z4E+q7mFnzAzMRvnoop3etpwxSZ/+
DiDAujLPj5S1lhj3dKs06XGmlI2LVZELbCa5VmPNY0LLqiP2TffIUQtcerAQMzrGe9I2x5sQii6X
lnrQWG2hpzNHyKKTerZW+Qg3qEdFt+AiiA1YC1Dtt6vLMevNNOKZO8najJ3m9fLkMVKgHYFFqGyQ
RyindNVUM6O5ggp95Aqj6FdQqj9V7h9JNktTEpxv6iWIyAFRUbS3QP2rcHk8QzVaS3bg9E1a1rAa
c36kYu065JFwExP8YmWTEokxCiLlVCdO9TL5A0ES4cMbZT5zVU0GNoBiRmzO3XdsLXlVusLnpeRz
/LobBxD+cYVHtrejQ76YUUKk1B9eSGDNndXGFYre13xeTEI4NooYZehIo971bS1rUwcau6XSAyZ/
ecEAdg+RFzYD6Qg2plDaibbSS+cVlgPjdME0iT1hFY67XPe4YgTRxtYG5FRYvgwSYQYF1OTbPvxF
lDczE5kSgE/QTaZu3jEpiz7fUgd/DBGKx+MiQ+76qP9WcPHUzZDQ1ApuZeQ2LmMZbQGg3PSQt9Sy
ZlVcTS+SORSZdyhnUAoxl9Pdi+15YQu7BWM06eTFfJqVO1lF6FbYCU1uysHrGmhhCDTSMbalZfcK
/s7SrUbcJbBrBqCYv2ufdUV2XJto0xLRcBXpvYr/j4tssh1rvtnUMf577nou3M5XB+AW+8Xsx2Dx
diIiZQet2gVHq6hGhDjSx+WTZDi9SSh6daRPecaTDpG3NhLtQBTkq4xvipyr4zsBtTaqSgg6S22j
4SJjKbPHvfeIiJFnMtqDlbOIejNpqqAtXVkjXJ8FZx3j4rnQgNkJQ5bPc7QpROpR+aQBwNsOym6j
K+7lI8pA8MNmNMI4NcURWaq4fqK+vu8F0KDblzWA/CLWoeEaxgtuWwSnolapPK+g4rV8/pDV2IYq
FaqIj+DXs2hoso2RMca8zdiIllEBolefr+G9WpKCtdNdx+8eiGpQm4Jfg6o9KILTD9wA79pmbarZ
iZ3f0r+lixuqe7Gsjxev70tuR4+g1M/dp21Ims2QtazqM1Sx3IJ2DakegIKPf/l1LY36be8v+sz+
8y7VuRfavE1vSUGSff46KKCwr/K4WEiUv85fUIgv0mCUdDWnyQRYIca98OAKsX0nANF1DtGkF6OA
FeIenQLWRnmqkQWjzGtQfgiP82B9vD/QZhHO6eE6XiusYC4mYAKs/c31zs/UycR6pT1WMLSSgo2+
3AMEx9uwMOuTFac8fAqGumjppr3GWn+1iojunvlpJ/CpjXD7xsWx4rlq6Dp6eDWCD6qk/e6JYb6B
MN/2kTsho2OFkRRhY7ZcZFY2/HbfvT14x3Baxi82bYWwzDxtJTBI2q5hIOJrqC0/jd/2JOXRHg1o
h2yS3u+2Rn7/Ln+Cx7h/XTPNohh2Nwok8y0hHr/eICZkxKwl5opfYOwKaqSYS3dWS25BTq8A1KI9
n4FE8cF9udM03ZbXlwxC4rmBWZ7RV2a9+i75oy2nvByror8hjp87ckChYFu3PxNDwGqoco0pr38f
JhyQnV1IqXYFZb0Y/3T/EpvF8aZ0wxw7bQHfdlsCXEGYHvrselDB04/WlveFYKxpphNrz/YLN+1X
EC7U2e6mCjsd0TTJX3NIr4PKLMJwi7sPCcBHnmDth14Ix3Hosd3LBArYZY3T2jXcqZduEugeBqhn
HalJeXuhJZo4bHqA5fRicyu8CxKzqFhPKQTCE7j2TQrWjOnMbarQWAkLpe21wfCONKDPg0+BtQd1
84Xj3UhJRqcYvsy69f7U1N3YrjQofMsn704qZLD2hJ3RjkM942V78m5yx8HTPqrlHojttBvMD0vq
b8Yg+MCa2R7bqOZ7QHPUNnRZpFEWzNYK9S40AmLln/Co/RU+TB0By1h3uM76uW5Yz1aSPn2Miejg
L2e6+q2j84J9zpZ361DGDU8kybYrmFvujkuncQE73PE4NBFGVARemqAVeJb05c5gblfh6EVWdPzf
ZOxKdf+qMuMcOUR+unhgihofauyItSwGwdMhYtgZmIZipUbbTmRAu9/LApvwpv4ucSvCbHTGPsvn
i3ePvEbnz2bEZx+F9ES3gUDmaowJ7EafSviBs0uvm+/nNvtlZ+IZSrp8LImC7AceeMvH+dg1yxKk
WG4+kwNw9AxZKYeiZIA9JDQv76PpXQV31/cCtpIuix+JvTqHWQdLlud2pBh69/PQ+dcywQ/rSYs1
9F2oO2WbRkqzgbr98+BCteKBPndRtrBS+YIPA34iVhl5RpcylHH/W9HR6IJan0tBp/0AE2pi3MfO
W5oAoX6Yd0r2fw5mutnNH849SXwwCuyDjIbpYGgKYz5KBHFhxch1H2hmdB80YDH3G6uOHSsyzuPO
66mfBNKKJ5j27gyzwSkChJSCEqDUvXn+NUKJWHCpK+fqbBomsmmgbNCVaZdVXpTXkDPnX+ysXSKb
IeYYRIn3j+PwT1ETzBT0w0nK21gq5zU37Gth5INePapGfuh32P6sdg1JGCCiWGtomiaktJJkqbNd
Sy48+SVNoAKXF1gL3BY5qGrXmktLjm+QnCFYVspgwUWUVASoSI+Kh4jUtbOLCTtSXC+ZsyaFcIP6
qKXW3pUwvo/s/GFrvVsk4gGYWv1vAJkYu3rSjOqc6HQBqvBEXdiDACR6kFooK3kbbbclDije24Lf
IEpu7O0cHoYU/GCi8k6llt3vHKMZ/qb6Ky1q9d2OFddByfm7qOQJjwCD0GgDqR5ULPi3B7zADnjm
XTpWFnRH/d/Bk9VJG3TiD9g3ZNPl/JDKc1BmtuHkHRcMUCqAwOCww9tpWD0BbecRnp6JGEsM3ByL
OLgECbBjFGaibh1ObRCDXv17+W0tSABFGe2TwhbDnyUiYCnKZkGhAR6mUhbsBXMAwBdPI46pWu20
adMEgezEHt79VP21UNG56qkoEl4+rOgaUWuFhNtyEzNZx1+kc0D9jo1SzicXQ6W0KtfFgjuaqL8M
76LZOS1SJL/izAtF07YobPD0NhR0auLAMAntQOO+WkmkM/Ral0CJb235TonQVckIAJQoZUSnm+Mb
OEY8aaVMzEdu0Lm0janCbniFBjVHIEdp4gcNdEQlfVVkrxuTSKqDkFVy5BMGCs0iZGncNiEthHXK
mFxQ+Tsyy0KqtLG6I/6Tt0MygC5nCBLUjrkU3D9VknZDf2/+rtAw77FsS40WvhdPP20jATdAo9YQ
xVioYbYttIU8u8r/bQoOt+IEurt6d3g7NVypeJmR6MgbcBsJeljy+FHz8R1Xho0m9LubUnqf9awc
ci2Oblnrd22fRR6gIz3hoovQ+40Ra2aMGaA6LZPv2VId+9qveBK3QJfr9PruBKn73PkjsP/oxZvk
v4FIiCCD02ThgHSMVSEqdhnbpVBILWRscmoyTrXSrao4NmWBcM2g27r1IWHHWWU8VldWbtSjF2bM
yjuN2sL8pMQJnrne0HdRp4xCHqJKuvdHAHH/5FjUPnneulxxjnQTFXVTesf7z7wX3SJEaRSOc0On
GQ+GWaGzJobLTGQi54mM/ZdGnTnaD5XnR45E1H9kcGk3G9PohUd8g8zGw7hL2V1SRr8l4q9Yk1Ix
1TXSpWKNRvVvrFk3Pl0llW6FWl2kc8Vx2h2AYqa80jdLI9bGyquPiQoDnoeAniwNgpLtVbmPKeLe
xMDxr+QWnpDgfJ6XNs9j/6QC6kxaYcZaa3oatytGUtjVLPAsrO39qUgETGbPXHSBxsA2u4T5GLvM
2Os+eLuoWbIEESDAFOZog/tYrNcJk38Y+pSb3HmkrIQhPpPmHWpK/B7FHnty/Txxhr3+GlfjskRQ
yu23MMWg0FO8knrmdLfWOpg5C9bWGLKtmxzWSu8VxzQ9dHmqfuBTnDdT2y7hwCsJ6Rw3CpzqjaYg
styhyR/WSh/SW0dGBKWyZYj5DjxpsIvJDBlgFpwJR1vuEjmoFoUFwz0S9Gc5s7zqDyGf9UC0wRkC
mcKuLhpIcrTcHv+v6aoM7Uj7UlH6ZOOFzepiHexe4lKad/7p5cA5eURU6OzbnTRj7jxnYZTp5x64
AT6RwG7/aZ4ozAxZNe5r+7jczlFBeuKJ2se0DYq0GjT7FaRNaRW/vsyq4x//xpUvi757W7H2QYnn
wi0K2rSYkNxbnjlb84Of4cnblCioEgcU60hMPhOIlKubR0XZ/76gpyJ2uHsOchROeWtH7oCJgud2
TCkwFL1nWeapdp9CCGG+oEdwJT2OtdV1Q1pZUYjlGHiGIyf5TFKz9ljXnf1k6CZq/xgRM+0WItSe
9+qlaHkaN1QdtQqrCZwTVBf8Wt6sFZhp120rFq3MVGPu0McaC7oIfr0Y3RR76t+uVzGYBJl1vyn2
B+eRYNopAAZJX2FCfKRuTt2nd5XD433tCjbdoqpIkMtERYPlL7ogw0Q5trzyLOia+R6rOz8ZNynW
TzcAk5TP8AsN/jORSR94RJMnCpVsPXcFwDlfZjZHyMDH98Aih65vo3lWnNiuXLl2Ld+3AyYmQwnd
3SPc9+qDDPWEKe5lhOKgkRpL6FGF7adES3GjRMLsqbKK6UpTwcYFb6bNICwREG30ejgonWh9X3Kv
bEGXTJM2yTFcQInf3Ds9OLLS5w3ABpTWG3bq18ocEj8QtUws8GpTBvT5+oVhMzNqZXAOZms0yQly
5IuiSQCFNxKGGwJhjHpgRFHhaROjSzwgkrUqCnzennh6M5blrKWrGp+9CjaFqbsDGRgwYltv+w8T
BERlTesafIbUSbdcUNsFmeQawBlh/AbgBNzQPproj9bVF5q5w7UgkW8gL9e4Mnig4ZKiNAIq4YdG
A/lj3M53PF0ORE4+SlDT8A98z7W267ncT+FqKxHMZUaTsNc55+1f+3OJjHusGzKBrA9TNj7xJsLf
8GWaClhSFFgiGRT3obHRFO45XOzoSg03VCpvJhdL1ULzUQhhmOudg4H9ebCpfy3DWcucxXT8XlQF
Vro/0XstHjAllAUDJ/rO4J1/dSiL0lBzbglK8jZUNuNDOVmZGxDs/pJ1JQFmHs4c0IWO1mOvBm3g
A/A93qqAaG3Ng5DXXHoR+po0O+/vR1WL1a/JCaVetYAUjb3/l8gCB9cEPWO9dLxTpE32X5wbw2LG
r2qkCprdILMUIZcx2P3/lN7PuQxGngMb+ez8YFkMUUy8UR6ApjprOiKslo7SIA3Fvu96GbPk5Fg7
QNjlKhFKe3RLDdue3KWI4J7hwgaqcQOiR+INb3p/SAaREoReBKNzvRsGRgTNZeM98DhHgNu4JJXT
4kfRfPLf9ArsusXAMU/KlR2qD6WkrBgswMOwynQh2Bw5H+ckMIPLMnwKuFSLz7ElM9hGZSAUFks0
6P+3KlH2qjN4PQOg1+IbCkbu346Ns5lYTyfu2OdXl2J9j1wtzCseNMlC9FMP2fRuIgEZk3XqTnAu
wWlgq7Cv/qU7s0eyFRgM8rtaj5ysjbuBQVkOwJ0jxdqWFwkn6Du1YXMYKhyZJwlEUKF27ZsC08sg
UMeT5e3dtFsEf3F1fy4PWc2nCGTx+qMn2A70wi1UT3aqiF6e4eNcATyAWeva4tN6+wNjSdIl/QsH
8shZY80rvYOIejQKdpPxDJxKBZCznQKi8dxhCa9wvtMh24wmvnvS9FJwjP22JYfiB1DUbeM1GHDp
7vYzRNhSbyORJtUUkBnJZeSATuj84Zg2KK8t2132gkTMhwuMtyJewFOfhYoKyYjO9/T7DZmzAc/0
f+5mvH6ma0JHNBlXAMcb+fgguG20gBzmHx9JUzsgbgu8CfSPVV2/8u24drWC3/jNnZ2U8B4P4CZr
xgJ6Bc1JetQQfWrzA82pfDYuA6G7jeDOPK+Y4xjeoHrnT4uuKbblueH8ZnlUh+8ypR7TiKc/9qmS
BN4dZwueH6gIMlSs2LB4cXasGryMoJ9kGuEmf7oLBL5+p5wTkfT0PLocJJNWkwlAA2gM+OVhdQpA
bgy3MtNgx3W4x+7gO0d6uHphrLAkjT/ymHM674bV/OSysMqgO166AwKcB3cvo8ZGqKIag2487Qj1
Vuo9laUe+ppWcxt2HL9WJT6KQL8wRMdilyNUFJX7nDSimhMqmbTzvN1hiyjjkDBl0Hwg8CN/FN9a
95hDC7/EB81Ut5IOvrNhADhH3MurLmXyzz4dZ9MY5o90EiXGEPIg37YEAmdMo8fjF4uDgv3Uuav1
v/ijg+uW045rsxhd1RpLTKLwI+f7x4QtJmu80R6hSFHaO51p2/yMm6pKLhFeuyw6SFow2LmD7aI3
DxSmuHkp4ulcpq2gTDKgQXlyFdhY0/q7id9oGt+A/MYCPqY1Wyo+6iWv4+VlCfFl++iWsVFRsoy1
KUJibppbohTZ6MjwIvhSYNOHwlxaE4RbQNuneNDrQLG6LSWDm/MW1Wh2NoOs+lZ1X67WfNUXjW12
RVIlxxNDWNkyQsAPpFCwMIeT506guPh2s0nkr9Pt7PubhNqUE5zsfWCACYjWhzdw9gdjZf6hRHjW
EzSSdFeTzcyliAwBHrhW8gg+zsW4ttcQywwaKaLpkRGfTkI2u71vn+6zWPX0gj/5Z4X2fT0QMlIi
v4wncWP0BXvg5TkralJsXMtAn2SvzTQOhEvZDMb4/6ftLo0/811BnzEhtP3ejOUxHD6LlfJJol+y
qLrTt/TSl7bY+c8lUiIz2VW0vRcyeDZN3TXZWlBgnDThUMXX6AVNENEDguHLGyckE2R+BICDRvUw
UG0nVuT4VmJ00/UH9TBcA63bYuevcaiy1abX4vYtRU3/UG2yE1rZCpLKp07UKwLIqR766gCcs2Od
AvUcQDt6mLWUxtLslQP84nWFoKnCDKPKAAxO7geDT1DjZ1vL+f3xnNo/JIr8T9L3cJWU4Hlgr5rS
cLEDPiIBb+M0x9u0gEN6vNr0jHQHKrw6lynBzTB94cueNkSkvcoAVntya7N/ds31gBLQdZh1T1CS
zIEbO/8Tw+mAXB43oUYZWXlrhLChyBO+c9cj7CBJ8vOfQwEszMiPM6qc+3SYKf/eVaYZOCAKlLhe
6qQuBvo+FLxbVsdmj0Y9MLLGMQaRo3USJ0yS8wHOZiIAW9v7tvpBv5BYJzlBlhC0Xh90Ie/T6y1U
Ge5tdJfpGhrcvaOx/VD6B1vfGhPMQjHM4ZYh7gR4kl/nEyO08yjRsRcWUx+1UzRg9EwJ487VIet5
y0Z1Gkl6uQCLYVDOI1VT+Nr725Le9qVtA9udTHRPf6vU9MpQPJfnc3dlAgS/UUIQTNrYdGus1ZYc
ldM5x7rODF49WznImm8YniNTkKzhvzLTlrzi6UUv0V9Nkk4CsOSnH2r3i6wJfupf16sB1Drq56kD
PjbOzhjF5vrZLv6xxr35RQ1Soi5WNwWrd+LeioCcOH/Gcmmry9Zyg0/Tfrt97RlEPXru9Gv9uv2b
6ElZevxsfmMJBOp7ogc3qYXAsROodAOo0BRMyDxAbEM4XGwFHW3EQ0c+ybuRYx7nBlBmQQOxbbmD
uIxG/tp2YjUgQlGCL4XMenB5Bsyb4Xtwjw5R3HIwNqPYLLrQHW5yhfqXp46zrLGN/3mZAPh4q6yO
9uSij4UdUQkZ0Wub2SZycp/4hpkBVgql1TEZTt9DVc+r+0H994TocK0vmz7SN+3luIftJsGRSSDr
zDD5RJrIFPVHRyAAFW+diTmI+xz2OriuuMCeUGkkGNlKAzdDIzCaXT72+qvpzJ+e8tzTYjBOrXQ+
THTzKpO7Tj7L8NWz8foky4VsYok9ixh2W3X4ci4vSTn6oQoi+le/mTyjz37stZ6tF+hiXbBnpTf2
sWKXI9ogdvkKo+Sxt2f68J7FW/D+g6OJMU+A2sCKe238F4J+qj+ZP9nIQ5vDQk/9vyeGK6PjJtgv
+5iNr3+c38rqgq+5QZ7UpJz6YaLGPjVYF71y1VFNRvemG4VWRnNFOETZ5OPkxhCiYQkvcSzVBZUI
DEonEyYA2GFtzstpGNsBrbT5vJMS2B+kVJkZYvC+ozy4V/sZ8KouJ0MOaVHipWF5iGeT0LTkG3Co
HMEEHlizjTqLNReJLpgq+LLc/vqIlJpgzP6gUnu2puJdeOjbsV99U/+25+6IQciMnX/mQr62vqlc
8dXvwdQjD/NzGUMfeFeeW8qLIF2cyB2/vxXgb1kE/ItoPGPNw38pIB9RLQSP5tOlzhw8bgoIAt6X
Aj4AMlh6TwvG7Eh7UlDeKDknuoDZp7wQBexc9fiW0heRgEG4SrxfpuA5waVV07LPz9QYz1K9Pa4c
hkNCfx7DoleUfFPz+OytKr0Ne7SQi1C9ii/9dHoUrAvwbf4p3qATvALIvIM+iN0CsZv5zUnSUvTc
go6ewj6knlHskPoT28qc9wp+BrMzE7gCCiMu/3d+3qB0oqG6QusU2Gu5iX/nEK3ian/LoT6OZm6D
KII6poGQUVAleWdtLetogMvdYMSoyFiLnP5QzAwdyYfbME1PN06sNDDTqakl2ThnDx1dT82bCt0y
5Q3ERXENVW7xFR4QSOtkJcvkiNkvvhOnlnBGh+eOWx2OJihScxVEVxo9xKjs2qg/noYvK6iQ2HQ+
XVMi/t0Ytt3EW2UeNpL6+nhc5ytO5ObB3Irj8XS9DCq5d7GMZTkqOQWF2uG6ApFuFxuuENQPRlPy
BWuU9iCaph91meVoc5l/offbhjJCJXPPdLej4r/RYQ6akVcUXgJjm6cxBaOhSEsmEa5/WKSp/dLL
Kze7UzKZ9DRK7+2kZWa9qA6+5JCHSs+pVqe4vYAJ+GbZTJmn++3K7y8e+yevHJov0Q+iVa6WEU0N
XwK7EWdt0QWMiEWzht2c5+r9VHZfc686hhrJpneELNOtThGfwweQ1lXL7diWcT2EUj+AE1gBksO0
GVOv2lcCkbcqgJEuU0RjCUQDEVq4f7hv7OrPSY8gUc0DonPRbg2H8yIRZcXeDijwpYHYBi1DGMbK
p/K2MTO/td+B5ETpZSg1LA54oSABxBrXK8vU1wczHLxl61dG5dasKEZMEQgndQGbRANtSqA2ywjm
VuC1SL/qqnRYC92PDtxjLXcRD/XNcKqHz4cdaAtDS/L5TsgSiiRx1oAKQgFOs2QW+qW/OXhlwh3y
LXi7Uq5wizaq5iVHr88Ya0ysmJ5mA7uyM+zcjj1udXdF7B+kpdDY7mZ34R2D+jKncELIDYIIc3xK
MioD0wjrFDPQO/h0qcHj6fgicbV7RReaTXpepmWdHttDDsOZp6m68ZsL3jubZ1z3iOgaMkPRKMhE
ooN0EdqPJqWRyOu28+F2ADiBkgCrzxGfU7uQ/Y4qAZcY6peRkgwuIiiaD886YwzOfuzViPXKdERv
eXRA2oyKXNjeLXUVy0yqwNUh3hTN0wBHu3sr1HhGPkXE+4wu+SN0C9ZvsB/HRpJQX4VbvQbsvEwP
eoMCvV+pj7aqR3333dJMOV5u9+/j79HSz5gXvzI9tDpDsmBU1sNzYh5mHzIp5LGZ5PzwzXVWvw+w
1BB4NzfLJJ6EYjdxsdtqnlSFyRs1m6YJbafDXWBOKVmWd+SKdxqCkaVVxBPQaTCjoPhPzSQyNx0s
Px1Pe9RE0mbcQ5Zkxft42M5g3a6xrn+hbClBjlwoTWkZZ45rBXwlHYw8Xn8/oWyF0GjVvIytHRZX
/zKyuVRfB8OYIizpclIYtWQi6KM5dIcJtXQzF5LLeNuDOn42fKrcXkmjUMUJW1iVSckIOGK+NUGA
Oy7kVTqi64yp1z5ZgNjmq3nFlfbpyUeN6bBFoaExqnu+Em02IGKWAZj6lukreXxQrsLTVIajUVIn
ZkekFeoyvF7X/AJilJ+70LiuT6f3pwUeI5TJ+1od50sxUjfR+SqQz/5zzniPcNm7LWbxanSyWYKA
Cml31svrHbVXQInWL2wArgWGERzkd8AEmijKtgCUpt4UF8oedroe6OUgrng57SeE3885hQGfo82i
UZJtgnRBMa1izLZS2WuHteUeX2oxDd0H5rOlJvsJDEiJycbnNTphI4eVEEpafzePpF0/RxijHaS3
9Gm3uam7IXQ73Hyc24EapDO27X8h8Gu3af0UNsbiNw9EkNV4voKy+J9oPBLJNKzvMhMO/AxOwRL7
sR/M+v1G0Py+ggmiYiOQ+n8OOUDsnZFWEtoyi4ciRwctbCnEAorD01kJ3axpO0y0YQlZZ3J6MFOj
YOQrmifB1emaJs/3J7jzsYd7Kxr8FlTPKQ4fxzhvFD+mXPT4J8Akya6KbaI/v4ZwrwuJc1S5quGG
kjoaU6hyD1AOuawiQy29u1uth6XKJRez/EnWCUqg53s/22haKwPEhvW8qgb8XvBpbdqyygRWKL9v
UWdB4LsaiUo3wxJfGGTZCtTKKZZOeersZQoyBTGC2pcOu40cDVY7JNoAlnIEL4AjjDUJB+LjRo1I
Z5uXpcopbptkWK0maEVOlZXYd+T9BY15g0I2zyj0j++tTvfNIW6/byOBqPfnkaG25f+LAgoE4k1C
6wVe7tZGNI29jsgw98wqZu8r61d4Go96fFTB+8rxBZ1lqSIh3EIb7jablFWQOqwuGE1a7h6uro+t
TnhkybgFbj0jWSesYHdObSqxOi75BMhO7HPCAvyxgOkwPs4jngxHH3M8eICny6zw+LLlr6G0Yi2I
A2ptnP/5s/paRq6lsPFRDza4xjs8w50u1A4VKCO997Pep4boDa+krHjm2RK7gX7/h1czggnEsWGV
pejoVOOK4sYhfBvOuga4Z/ihHTYnK3ZR/l+z4CWdXyLwzFb6UNIVMGL19yuu7SEY5fJsHLNuGazN
AvYE1Tsj7B4T763TiisaifK8ET5uONhfY8v9dVLz5sXW7cf/rCSucY8e8UfyKDimNNOWOy8zJbaD
zh2+9WauvTbMAsXoEIEzkocpyuL8YCDBO6NCke0BmaeJqbT+0Znb+oQKdEyISrNdm/oSlq3AB735
iyBUAvgBCkve2kzd5mUfwJPMunOa6u5Zd6lD/XqYI+FmF3LdmfMuNGdO/eTwhjvf2iuEYsG+guMR
idgIm/aPdX5OZlrpURDxQQ3EW2+DBQbj9l321m2BTvOIYxdpZj7j43fntHpamzNFETtynzFpbq5e
PcSXfrJ4beYTb9q1XGSD+kSy6fl9GPBtPGpTBqlsUgZlTxYyfMrBK86fDw3iJClfy5mevAvzCco2
4VcAkvTLsukJ4mlqsufHhbwM8boPQJJwT1VAt9ogTyzRzbLk6mtLPVjCwvxBgIgJ7d5g2ZNzI2mT
LtnLmDOWH0ODai2DJ3xYxFGNM4NQegkUesXDT6ou/K+zRUS8MfbrF8//VMD4bcnErTJ4Um3wl5FS
5khUbTAHhKBrA+5DXRbZdqmrKPJFk71nNfRuU/SrWYXhRKtvG0wxkwVgZzV9JzT8h50MsHwZ7J6E
JQVOoH1TWAxRo7QhXlWjRBZ+2OwsL0QK2jaz2N8GzP5D6GPj1jrv37CpcDRyTMxCuuhIWpI8ugQm
IeuckdaSZ+YhjPSSh+rxuU9iNSenKNcHbkiptOzBD5q0oQSAkIGeuX698dHSXwFW8/JSJZBA5r3w
dnkFpeV24aJd34ejBouM1AXtKe77dT71XB8M0oHw8QZ55FXYv0SHeFlz2Gu+toLC9A6OFJK1HFvz
0KYygQo5HlQeiXpWc8+fVOAsoyS/8HsRTKRzHWJ7XDOuvRGc3U2hGqLBzTWIMXd/yRMev/WJt0Yl
MyGUe7wUdt9RiOyhPgUOVB6WynC/43dO2Jq5oI2HCukewleM2KGY3VDVmurHCb0KMoc8/GUf/6u2
fbPCz0jzpbt3nM86t4ynBRi9KLHk/rmLS+BEL/mfhvbe2LKQS5ZfTSOgHXo0OAOURm5+rHm6+lGz
6FGckNV2+vIlNrRnF0q19WxHjjwABonGA39gs10a2ubpEJldr2SWb2DuuFJXp17I6JhYswfWrW2O
GBYQm51FesSWvRHoDCLesPibSShi5CrD6Fpx7kZ38pVhAxLYLBwNNY/a7H8nUhpFZoMf/Bqny66t
KwLrzgwJrgZs0q2N8uvTN+NpzUktUCIYun+KrRaqSj2gk8Swpoem+q/3wNhltfM4ZCadZ0D+YYvs
BqdNrtlX2G0w7uflD9FjmT1jLgd9X0OJWJr/8L453SWJMQlJT3NSsWuegN+OcXYT0KB4lvZWJV+G
c1ExCsk2kBi3m+ArNjKS5LNKihx+SdfD6pUJzOoP9NWYq/kDJrCOv2Z+yIckOYI2wPJZtTHBl9Se
rCecPwycVW0Koxo8Fj3U7bUJeqw9G32ku4ym0WHuxZ2CbQWOp6gDUQdGvHjpi+iTVRPoQCyFyY2P
phhYG2Kg4g4Th52FaiWx2tWXT9bC5RQXdyNUKLc8IfQ8ryU8zz4+B0oeGmzt9xqdSeIAuuWCM/Iw
dhnFl/ncLHEf5hyHHY1S92xFV6m2LmERIcfGWsdNYZX9D9o3SNnG12JnNpjBGA0vePY+BsfTIli7
gk/jJ6Gwc4lygZ4lVOTtKyjYTBonR7Nx2mRQrLZoT1TiEeJ2s7C+20SKRu1W9W62CJUV6XhsGfrg
TGpI9UEfriRx/Wi+a2AzxHtCE0cksbXfmWWuc3P/xF4tpgoLBCLlVm+9iIl9iAqExczlDNZzqvEc
WJGGnq8ieUV2K0sShig1xwBdsFnM8d/FIasatAiw7Ic7N4uKzT3VGAVbuB23Emi43hbvF0G8DH3O
4yOaeD3eFgeB/cbzjQB4w+WqCFf5gpUQZ2PKxfEbUs3xaCIgShwJgo1GuaNHi1KDRYclzdP8JqTI
D284hGBSriBkgBHbl1kstpS8TnYNyEZacs6gU2ZyPf2ciEMQki0KxLSJICqOJQkIuq7L0mqbqfeT
b6PEr3NTr08MbtBhMKYtMosoSEDN2vebrUjxyhH/ITRPC7/9Zmz7eNOxzYlNE6wEL/TcLchTDewZ
/dUGKw95kG0jPG/MqZclpWrKCZjPvfyLhwO7noIZkBbcV5hwsC3ZqqZPdiEFUEKmxwx0NFRFqEu8
syirbIW8NevXveI9kQ+Qxg6YCNDJkWyW3ikeujrH5depyBmWBr9/VXBXRCUygx0EmEg0iOSOUmA6
NWVBjGmjEUbbZjsKN21dtkQke9EGx4W1qkyoxtDQns/0q/732dHBJpvQSx42FEtC1SQ+SDXkVgkn
XMr075IcmX6DVKKpH3g52+GIUIIn1gPmO1H6POATumnjSNM3uCIuRpvntvulDUyyFTS38JZYMgx3
J6vLf7DwBB1dTUFJgFxdz3wMTxSFGqp9HwOx0nce61kcZrAsOIwF8yYU57fp8bev3q0EehXehc0g
PR4wgGIYp1Z2shfj8/G/eaaMHCefBjXffc++As6ve6ZUqWJJPO7ZfdYaYXhXTyzw1BJquoz51G8g
h9nc2yYJlMq/v833Cp0lKhfemg1LPrs4VhXI3+Bf7XKdx0jzrapILHlneWlPs1bmu2+psusmImZm
j0D0UTwq4QQhlbN0a8hller8HKdQycT3I/aXEHuz1w2RTSYl6IpPtTExnJ+3zH6pUYmv8irViwJb
yGNayP9GCvUGnfjxh2SbKRXYjoJUbroHzlxLMllGhIjcVOhZPxTdkOOR1as/iGS8LKUOIhp/DUCo
smzf7E0UXQWOjS8VwTqx/4n/GGP1IG1JGZWuTrcumFMbFDHMzDx7g2IfYID7+mNBFtDSC1QNYna5
By1LdcuGvMernoA7jQsnN2QTCaHAdeZqvXb5zbYrdMvjINxkn+vjZaAU43mU/s6p6dDdAbupG8Tq
3pA8mQl0WSsG7DVjSR2Z4QlreWC1kkHMDDQHVcU80A2+YZIuYvM1bVl9u4cdotpaRo9NzIaFhz8V
t7vhbU+6CfLspBVjbgInMMqH4MI6cLz0Z+/bqKHY958qiOvxGi1mwut0YDsV9zQLR4EI8aTrM7Yt
abTHeJqdhi4Arc8SWXQ2gMye8rOhyd4yAqwjtjcVoUoTHKaxyrbe2IxKwOFuG+zgC/szbn1odNvb
2GNYBzysxYR0ASEh/AEAoqB2UwNSL2rkUjWiDsHfSugUtcWdzOy2U1HUE62GISs50YZ2YCP2bcga
I1dViUjlTViDJA5Syu3x9JtrLJVj6ZBf6TEMknHeYxUbEqsm3EsRp9KMpNSZOZcexFPCNEUsFd3j
TPELpwAlQjNbUXktA4QZ4WFM+ZQnZvjWkVl6oU8Nv0cty2uEDhDQHNXq5grDTZY/6AqStsrhyYDX
j9gXOSE6c0PJ00TmglMvkwIE7WW69bEQJOE0R5zVWeoKDjG1tgJXNKs8q9ZLbbA3Wk1d94Q1dP1G
sEQsUa3/HwZgkQi4wP+lTIBFeggw1SrG/b/oXRfkmgF3AoUE5CwSWTFQPNz8EvK6052iVfq/DAIc
QsXT7XOGk40eNxEZGrtBawke9ZLH6+9kvf6DlZBFMt49ABkj+Wtbw6ZBiywRUVD6fxZBAJCA9Zhm
8i9FIQpoKopxfw6hB7/seXoWg5sxE2cyS6VBsJv4oP1mbe77WCxBDVx/qudIs2GEkw13Vgiu1+L1
XYqYrT9mp/1Idvm3XUE18LkTUP2Bfv3Kwz+qULKJQON39nSLPsY8OrIEaVu6FrbrP3FRY58wa2WJ
AoVqxIqx0Xzi8zlJR39s7nKFdffqbzOl2o8FkVu6/m84YkfBq1ifYyUDb1PPfySdMnwFKskW1GZM
/HTjYqZzer00DrxTg5VcSeT2k6R5ilxfX1IWa0hZhj7D+VDxrX/DjBDgcD9K7a3zVtPR3/dasml2
d5gALsqYdHo6uXjk4b22MXmhMploRdM1QGuHgGBo1LNiEVZhyhrFBxrld3R5Pb7MhAwB9DtwkdCx
VsfYch8cmZVbGTxYSLlR+VDfg0xPzGIhzITjX8o5qduZIYfbcfx4AFi8vgMi74BARfJyRiDKN4Vf
eWZA0hm5kxddseJq2JpJo+MmUiS/W8wLLImXxoMgC6MYXAUeu220q3AyZgvS2++FWvFvVMOMHZTa
4pkAAO2dF4G4EgO4r5zszSCfWgdcK5yTfIydIHfN31ufXkxedJo/XWgbXo7Hf6OCSAatU8N1XA+Q
+RK8KlnG1uQX3SBNe4+9Txhx9rvPyJurmGg8ySK4y3TrA3X+MXqEZFnh1hmGUYejEkwGPrIGDePF
kerfCgs08iXgVLVsrYlE0CFqe0Vw4lTcSa4VBI1xxVITsoXzYNslSoYhH7cv5Is0MOmVvKrRcdg3
A3v4BWwWidD9lL0IikuZVCRxEdYPSfFKArb2Q5Kw9A2nc6j1jXzX7Bym0q5y2wayyYST1uJNqo2n
5Jkk86+Utb/7qqagrkbET7nk63vVRo686YiFWLgEGQ1Wzwnw4EkGWMukZKUCA0ItTfLBFsMNP13o
lFRo0qAJPULWAiuXBAFGkY54uHCOC7U/QYLk7lwGcmOJpqrNwJc5MjP4qTCL7lzTzb2ebJ70liFw
Mf4mYwbnbQ2cx1i6J5NfN7IjUbjCRiWEbvv+fiXoXxjC6NEnoR+KXtjfGnYp1kODSX17La70UviA
w/PryVo35HnG+W+g1xWVT0M/AQpQnrQCNzPyt1ss7MXvaa3f/yHmr71dgOESS2C4xtbq9GquU1/v
BL2ZAN7sQvlVfGiPhk+ZdZzL+1+u03DCShpaMp9ArheZcSXpra8rGeg6e3BysYZxvLJ2BJ4QM48q
hN1KSlTVmw2BA7u/BAbF+mP1WINovgBqOYEfezrYcbdl/YIeDFbI9Q4s9cOUfhIhUTqK6VyEZZss
dQvOeOcnbT/eJbDx0iKvltEreuWLqoIN169LiyqFfQ53Pyu9vn8wqLwUpYyvMR7U/R6pFYVBkIOn
nh4DTfkWNSW+C763cWkZRJfQl0fMITqyYcPlMlQ+ARp7zN0XSTPPNHRoFcmlHyqntWreCEFmjagz
7NlkE4F6R9Dhpjs8jiG2bxT15EnOvnyaSVFpyzuxd7qdy0jdNs16XQtsV/kRoyR4UhKwY4zu8vww
V/tKEm8bO/nArf4pEGpG+QcoaSZg+r30MZ5Dx91vtPcMkt7aI1z6BtquA+/o1Ared8PWMH6R8EAb
3lI2wcoys7LpnyDSLMHsKM2JLlmaagGyCg3O8oFeZ4BRRb1g7BwRGMrecXPVUKq8znJE0hFK5vxQ
Lj/Zj2gn2xu+bMSEWHGtmnda05Sp8oUpL2J+kPJhamT18Rxmztw6F5PwF02t6jzKLVyLg0sFTkIz
n4wQlWWle2V6eN3DWkcGKdwp9xMasxAqxsLvr7Te5DDbHI1WthFX1nzmzqpQLfZZlmvwyiMx1RJ9
1X2Qe+8HjD3av74G6HmOJ0U1QarBcaSmLK3d+kpJJ8ma0yBPZ24IA37SwX91fAKDmURvy5hz0fJW
dLasmaC36zN1ELLNxgv65h06OVu8r4ln+DLIENKFTOE5RIjZRbkTe/lMDBabPaXckdxZ5wznyHme
CLIE42MHhHpb48zWQw3Cup9KCVdITFOpleJ84rq8gKq+CfcoeTZ2/bVHqbbFZFn2vd8vOVe0KxBg
B7FmvpDZ5VAQRAkBXHPVfm+wyq8u6fSFH/pJwyP50NdkI/99hTKVuw7mYDdAmod8FFTmWOXLhVy8
1TcT+eunaFEUdDOzSBZ1R9Hr+6lSmGYSrlgynkqSLKI/0ISSkmcGZHnzb7o0gkUcwZwzyNW7FpNr
RWepRjP6Tp1Z/8yInfQSUcAB17LQ++BlBRjRjKQzM+aNOvqnWsdd/1RsLOZmATPK3iQLXvL2RAia
DNRGcAB6NH4iycbvLtRMvMzLYRBX7T8N6r+La0Rk2DOEyLP3vl8XXlobKnG2A7Xx25n8XcKpk9vX
prCjrX/XZ6alWceczzSofcWYW1Up1Hrtq058C/TN6PXqTCtsoDhUZkIcMoV3yB6WNK2FD2dXwt6A
oX3HNahNnEGej2ZncYPlKVnsL4dteI49rrpoTEM8cRLmuzANOMqkl5DQqZUpKf1egREcCLJ8Y8y5
23KelDo/J5AE/2rW5+7ifC+L0yq5aB0jBHueeKj08KpCaegP8JgS2NxJIBgGB4cQ29FFR4iqShR2
IFxVo37wg6KSAu0h+d6m4wSCLTLm4UkFdBDXYsBzJenYd/T4+4yuqyzaqa0bUoB6LCJihEnvOG8A
JxHsAk6KpxpYcEryniB6Q8fb6wUynvVc1YFC/wS9qw24JKzXklFGU+NpBivlKDnY+zofdOO3lOxP
2HdM2b20QzMrFsf9ox5VBVg1IziM/HvdfVDsKanmPDvMz4j1JOOWbAwRkNwslDDoRhvlIW9GF4gD
5tMPUrIdYXRDSKdoOpbfCnlahnpxvafDXCWEFr6tBCGrGxXnrH9x9uHsmuJt3Bd35YRaXmHPazvA
hlwv0q2ZV1S6LAlAnS+TiJjlbyOB0wJC8rYk/lhRnMqmahTJdVIgjf8hOI9jlbwERwQG5s9BdjFj
QQLe1LwY52xekJF8VmSZ6AHA950erxtS7JFe6ygIMi+2s1Ri0nZNoeqdTq5Xg6/AhBPpLkmvYrnC
V6bS1i5NklwJrDguPG6cZmpgFZUz/0mYhRcdLzFGo/Civ9Qlei38tvrN8oxdKpAgkShp6evXir/8
FZwkjmLnkOi1PXr/ZDatZYnoVA1uwQSsS2Muc1AenBTV37ec20OwDlTDx2nzWXckWQNV25kFulIX
SqyZeX1/YCSot2jDTVuCsFvIrWgM64yPuCIIs88qOhLgnxqSPp68BVCYY8VKLRWmtwTRjy+X5myM
GuW1lvkQqP8Ulx48/OlCJ9e7Ih6an8gZ6KHKT5S80DJVE59lCasuCx88FuLv17ODw66SrIg66QD+
Kad4nXNoXUem+zrTDefCFkjpM//YXSpd2fIgh9eXEeJfiVfuEDcP3TfivPoV74TBC6Qg9mXvJLNv
tEdJQfbT3pKHnv1udJ17+1WhtgRoTg9/coTqtdzrncoJIJ6eS6GJcbWBQzBfW7RkvHMi7i5DMbHh
4d71ShIr6Z3roBMCdh5aX0F3oXbfi4oZDeKkBbh3i/FPlHLROFrLpFXoafLIKKCWJrMT2pRyYj2R
ebjUMS21zIDjkZiPKGnGUnvgdmWsk9pIQVxsIaWc4PvRw8ahQfSx/sZTaltOgHvOIZW3+umvhV8j
OhFNm/BT6yJTf7sTFItGssd1VIdCWzsqz+c4lWoGMS/PHP4v08rqYZeAuMHHVmkkfSA1qs+7Nn+d
+diperEJrHphCMLGl3G32sWnaaHawSSdrOACYffVKRB2xfpG9TbHVsnVCGD46eKIAkhoPKs3ihcp
NpsuvfYyfbkkV/hSJcVGDF/DfyxMaGMCM1DBiqYNuBLX4ncz7UxRjBM+vGE7jsFA5iKcbxoICVkV
ps0Is2DkgRW1H/o3uGMAE69+tc/PkMNTXDLKP3s4G8OD79a5JExAcrEHeOYaTfuGO8B+jUZNOvdB
b6BqkklflDjmFkqskgR1ut7RJrn7CS0nMPeMrrttKylsZAhl433AupGgt1dFhi51jZrlUDNF0Uef
eKQcq15j64UaW/PIn6PZ9jFkiy7TuxA4PmmTIP/Ky8mG9gwu+hNxLfxiNNN2cjXxB3/cSgSKWtpR
k3Wvu9fWTltwUxGhCIT82rqy2Mu9Dwc16yEJDuMhQ9hBZm5NTj0hh5mnyO5iEVUggH2Wewj5mD82
eSSK/0kqtXQF+HUHoz/3b0yI2bYG34cNlTfZlUVQ31WrD/+0B6QJSdlpOTgtPOmzHfdtMUJiI2kx
3gbUfHD/9kTmXpF1f5sfkwJT2u8MVSlceXYGqO3FmKElDu9Sgx2vcNHATvnt7O7xDDtgDwXFkGL0
A5xC9Z1/g9teDaqvIOSf6Rvzucz15pBWy8AldkFF6eEYw746ASoaKmX65RMkipBaplivRZBtKaGm
wav1gZybrdlRxqLKpkZRwXYT91HLjnP4C3gYe4NEgSgMN9xSBp29NxmmFzdAx15OtZhUvd9X3ZBq
hRUtkYLRKvcueuHfDtWY0yW2yIBd383w+ZTRfCAKlAD4sXEGvBsVNx6+Jg395rwHYj0+jeSxOXze
mWndtBQmT9s1ObK1co0el8UrxcRzjdhwDUMEor2omJvjobgpJQnBYfVUXtjgWkmvRuYJkvpeyRsK
NVIybc70e4lzrhHsg2lisT9/lMyU4dSblI/x0eYXyNLPEvXEPlpARZwOT7XFfhQDhkcTcCqEQqJR
HvJDuVPX4m3ABUx332TVey/dY8VBdJJOccGdTBv+89cgugDrIePOoRYQu7XkI2fyDhnuj4jFzxqz
CIdHSbF6H3DFBOliW0MYe00IUEHbMMPwL++M5YCkkuyQQCWFLS59NTIyW/Auai18NzVP4tvpA6rr
bkTDKTQTCmnia4+ingbX6z2zOpG70v400GvystZgor24Z5be9E3twQ3j2d8L3iIwRR6ha6zWjC0I
kFB4eGTmLSW1oThlDtYDaH2m6uvGbCXBZUIqyPsJqCCf69PBG+Hg/dVwFKRNLKEascV8FpU10WvT
W0pKzw3v4C7sd+UUECGZCBP/kISWJGUaihOQUZVeqI6KeS5WbpuG3V1YBgz8Y2vG5LKaMdj63ph/
vIhhRU+Nh9pxqLZ0JBckdmuy4Lbt0SOFSTJlAXpd0tosRN9NdckD6RcoURnDXArrsHv7+S1q/stx
TRLJknXikmZhCIfqjrGpHKs2Er2ElwaH7NFEJ83/p3F6S2G3Zo80WSmKHPN70/Vi9K07eutguqwJ
URWNdXiA+0t0vpArogI44rAKqAgkcXYICW80Hid4yzfHSh3VyWZtqyjoz805pJxrU1cGytkn87F2
Qijnh//4tvElCfru9tpHdKEyBkWenJcfLY+i6BP6oneOlF+chDXvJQr1aaprxvcpbiljSUgwGKhw
B2oclKQ+wVszOr8KoqvGnvhArRXtmCJKg2e7uiw9d4jMvwD0sF95Nwq4Dy87ZsiS93/5RkXNtTLq
2nnVepRRrMhIi7uWLaDmcx21Dvie8Bg3QgXCCZkLTKrE+Wf4MIuSQ7Gc6dEVsHFUc2CuGcfCeJiJ
eNxD4T5huBZBkx4woOCYDNUWvz6gsQrQvXkhJjsdvGYPoAEd/Ww5oB6lE4oyJ2ZzTL1pJKwojkx4
lvENS6pt8vdbjFaFhC5kYGEmFI4gPoe8pJcWzSPjDt5VrhjrLvMQZ2F0sFwSvK2b2kjiBHe7GWtS
FUB2BN81ktjrzGw9vaguUtH7HCOrFMr4JSuU+WLNCPyex1hpIgmRO42NcKnpFyQcUOXrKBvnjok/
3BqrtnUshFkzLc84yTp+r55TFQDjeY9AxofZ9YEWamQb5gX4L4AUkH50VT88mmV+ZFevncyZ9LqT
QElMqMA1+8ld6+0LFQtFCPIKziMKEjIKk+2gJSuNlRnHb7+usGw7qGfB+cslQBfsBp4q4tg/fiWD
WbUP7EHvzyMtf41Y6DqoTLjskG5pgJtiyQVKVAkQ3qBgWF1PjuKqjuO276f4iljOlpL74RCHOTnV
PDsaTI68TFbcWZUvR6Wv+baeIGoIOgEf9RDgkG/+PptVafAjOvtDU7Fx7ijOQKbL3Z5S8F57DdHO
pxp6Rtk9tU7SiJAQADickRxdTnpB0UN2pOGU97w21zbyrLs7HQ0bDwEbDk9oQAT6fu0akXBlTVPu
jjXuIFtQqXA9gk7UmKEch2dbSqGEnMRrpAWq/V24Zaz9BJC3KsIPI7DR5XFSKmp3k9rcdFtJAJHP
D/gkvtUosbxuKhkkxT5/QlhX03qiySLNk2ey8+QuADyCSrKD/G91xZeqiYbZKve3Z13aw/oscD+d
JAKZ4gAgRyIq7ONIUCPlN7JiOQMlIrNNPvO3wB3hxHLqMSPmP5GVVZnO2NMRQVQH4sLeEVwr200e
tTdz2lv1TzUg5QHHtx0yEpbPkMqNGQbrlwZh2Obe33aZ7G39mjYZzUOzI8T83VRGeum62IUouuXq
e5Ej2aeEdFd9qIYbtN0wCTHWr8OW3ALn5eeFE0lmy9O7JCu7cUDUFUouzXCBSUjoFL+ZYEP67F+m
5MNNizMUpAOIrhBiIs4hN/gBknC5tGTZhEHqiL0fp+v7Sc1XNEWaU6R1VOhyUusmJJOwBiSnoMKD
DOrSAYD3HbqIpmLjRpnmRRmEDDwnuFJ/nvKCPXEx+68/0bUkwe6AQj3VFWtXJt0zujmSyhXeCU29
y845AFU1+LUAprTK1P7zX75/Ux9jOjzwxFtjTaMWnx23NEz8Barvk51VF05MozQ/K/8DP+J+GrkX
VbANN6VJQs9QsOwY5b9HfVqXztEFQ8sdaPhcFcpKfQI3OD53H83UDyeY3rdKj9a+H3AFgDu/dhpI
LRl+oSxo5V/bMWeWBu1qXIUfN4+hEzXuYDjmWq8Jn10KJ2SnpYXu9Kg8bObrcGEEFAAoAkBCYPOB
8xcBCbHXz1uGV7wms/ZwbpJvZVzfA00DiC1W9ufVc7oboAXXNUWVVvIX9dt//peItzlgfjgXN82b
OOfMIhX/xFK0e6gs4O4OCtWxDwSK7I47UwZf9qzaspNzISsGouYMpKkPYELKA67vEhLpIvaB9pk7
gp+zc5KcusLhDRqrOcLr8mqP6Gm6aDEvoiMa8NlNh9W3nJlZeDrRzJ3VYROv2xThJ4yW/JF/j+ZB
kKHIIWRwDylT/2Jk93rakEJZ8tuSfKaaix3tY6r8aff6gZQwdBej8rDkkWijCb0GXqYQJVEwdcFs
bHXYrIL14niS6JlmDPMkVmr2vRfSpAUwbm1PbjG7ieonwswFiLpfiW8qeA3vOJ5CNrdxqGNXkJLR
EbyCfp5jv7+lD+1c832V5xD+sIV/d41zra+j4cU3zrZ77iRTmigBSMgqwKUTyc2vNFzEAz5fiKx7
Gzzq9wtRApGBHq85uxfDtb7jcY0Om/bnLtECoaxB8oU6o/IR6lonvX3ry6nzdhPZ1NVb1219Wkw+
4sEpTSVk+qngk1OXrqjLXRNa8HRYOl/2Jj8bdbObt9IicibuIQsSPktfGMvxWklxBZGH4tHXztAJ
OOJVkVDq35pGkFUnrH4uqgW7mscT4Audrd3L8dMgdRLzgysWxV1njo18ZoE+6a860dWcv65SfqoU
g4njuDYvQ3fYgLCMjbNo59+z82CiOy2Y/DvrLjYXP9FEU2bYlTmRRB16Zgw8PzhKJtB6NDKEqi+8
D6kktDJKoOGylwTnhPbAfjsplHkPeC5CJ7v3J/gZHevuZGpMP1+l8QUfynjltZA6Iy1/6ahLrt7t
7GrS0+Oj6wwfBuo0O33HYOOrrItb19ObDquDp4kiy3Mr8sxc6qUaKJR1bB1yuQVptWkN0eA7ul6S
SQrSWrtYbo34T1BxV1mrMq3BBqu6Mde9OavY2q+FF+Kk/jLXGzKFIzB2jbCnZIXJn05BMfhhxL10
s5QAn3GJWGfw732aQHh2+m1K9m8WHFoE0MwBj+fP0WG/RbMv6/7xx26SAbfeaNQgfPRjsUPtcmFo
HdEuFG9mM91hZNHjjKnr7y7Wp2F8vJeP8UEbF+EOZb7RxZP3RGDEHhfnhfhAqxIjszET1cQKK8+K
ChJTpEc3rBveDqn2L5KOHxSRZ2ePRwqTn/WLNvWzLIx5POY6wJnJrMx66eLF+hbnd6X4sqkw+akk
as6y9Lj6RG2AmZgU9LAoKCi+TWjxxm/h9pOUk+RfIA/ZtSdzhzG9aQnoS1klyTx9qhbf39ms1DhC
zuLwvjCCvrOrFJWvLCUqf6/pdOU//XhV51AMX0UfbBolOWCeVT4vVqfjUmYaezkBxqSPrX3XGOQ1
MKJPaQLOkcJfd4/pV2VR4Boi74O9dweHzkMZCvxbDPUXME6cINGeTrmxGfC2+pHax5COiXC9DQGo
czQDTBmEg2boz2OY4Jz1RWLrj74m7LjeJGytx8mi//nSGC+OebTISmQDRfNLMaGSqRGrWIv7sl83
AFoHTZAR2gJZteoEN0Z2Eq4VMu4u3dGWqB3saFkl4IhA04JE5k16AWWcdh37yU+6o8tJXoaVPJJd
n1cABkfuzsCqq66V6InIRpwCY2Y8M4QMAnU9+UOG6wCMcrrgczVU1EOusEnDqIq9Yt9Gf4Szgx6z
iuUjLyGfuVwfwa6OseeIjnJBGUDamxFXPKvGaWfgoDDhQdHvyyjk0Z2Fk9SIrUfYXEfs00yqCBAB
Y2fp6PBUCZnqjwZhNGaLKjFRX6gapDi2zLS/FbIa4nY0x6Bnj/Sz7DNskOBRCJRdAxnmGBVxJWl4
OtC/4JRLusMnxnCY27XC6piyjiqPLw4emncfWNwpO2C4uw9FHZoWNhDK7YvEDSrPKPhEpGh1JFMj
EAKsZX9xknoZYJ60vCKJm9MVo9KT+XPCe7KTmhON9tBq5pt6f0SL11422qvYRIZJegn0Y+TcwpTn
O6oQnodEcpdMguMhNcSsFT5Ql/bl4cggwO9w+18Xy3DrWgkt6gKKZBUwIaeXaTnKGB5JGj3X+31g
2e1i0NMfcqSSlLOPfIwR9b1o2owGTpWbB8ZtW3Qj1MuVSJ3FOVu1CPeeZoHIs00Y1IYNT8oySk8t
Yw1Vb7THpt/q+M8M9FVnCd65B424r3LF0tJ55xoWxQkJ9iETjk+ReaMScLi4aWvYfRuYCeOiy6uh
uSvUIN3lhP6luaSrvLs+fU/tBRPiqn62n9gVg72zvoXvgdQbl+1r0ncMKm4R00OIVbkQypPI2r4o
k3JGKnePgCnNgvzkYx77sDmQ6ugSXjxApRdb+bNVBnzCmNixSNGCsrrOJF8QR6HlXhOYakRsf365
DNaN2aYr0MlMrZsKRUc0GQtlvKRTkPoig7/zlIAIYz7y294WzSvEPpomc9701xnxcW7IjNYuTSvN
4FjeMjq8ErFq6Xz+rvaC1H3C0VnnKY8Ojk+1drwpZhg4/jgMV3h4Z239F9Xp9Ee0srDGn73fFc2H
6BAwDCthjg/7/My9kHXXjywkpTLFoCxodCBxcifI+UqHHTSJqCFI/ae8Mfi6C/EBMMY8DFpURkft
/mBQhfag2ivPkULw+/Htw3MREp2juTMAv37usxJUHAyHcGeYY2hkDp61gQ2PGr0/Ox6NPQ8NxlLu
EOX/ISrE8Oz8oRj8dZoWt7gCznHV6Ms/AZCokVkKKQiDMmoZhUV0InAesqnD6HKOCgNTxxXEQN7o
Ga97sSbWkI5YbBE2yf0ctsblqGoGkvBJuGHk4n/JXrS8+X4ctwkF68ROa+d36GyyeSfrYCshsZHC
bqCV3FFXM+sczwvCdfm2KGrZ5RrvirYkjj4kZOww9fRGoMcpCxCsoKxkvkfeZAIRG7vMaebrTBng
sVQgWcdQea+fwE+apJS7l5vS1MEwlmRcKVl33ZAUkESGD01zeFA8ofPTzx9XiThpeg1hVNH9v5so
opmH/zfrwkl4PnI2f0SLbjE8OxUHQfA5R4FElHbcKjTicqbuejuDg9SNsjNMYTyKHiVTk9WeegGx
sR1AxXB4nA5pPAVlH919jbAiWmLgKP5w11ZAuQdxEGCansAffUFO0BQZxX/TrDXLSD0dhC6wUS3y
zF0Au0S2WpRrnMim/kq27j1ZKOvnoQZ2guVuqO0Mzx/Av9CQrkGV0/gMlSPzaEgg4iWpifieNfsb
wA4BlM1vxNmOxyZrKaAqztaCrww0VRtYGnD7hMqS6n5nc/LBHoc4ccmHgTMG/EXyN9f/OJYua5BP
vXIAGzT55X5xSjc7W1XnSXHe42ww5w9a4i7ACumRo4tiMWHCYdeaRHbTgdI3iykizU1HKuHq4vN6
+edDw+YRVNRRbbGwjLmRrYrCeBzExO2DSuVenO28n6oDH0PRPeRD++dU2mI2/BceivwSzpyIKLeB
53tDTPfCirIQwehZtMZoiBZdqODOmYuAm93CD20MHrrjBqw6bLidi5KwrTVRi80PDItJtetJKoQo
d/CeRkLBp3crk3YMRHDyZOjcmM23klxhPbOVvYCEOXKMH/0YdejXlo/lhoAT/F++VseuKG2OS077
iwknuNKYAUNK2GPRVi1YUp/2ZNDN2NuqUa2mls+5sBtc2eAcK7P6BmZ4WSGjdwyFgbVwwchoU2b7
E5311+62tLGfTVWQVEHBDqIIPLvYjJWid2Dyw9w+oj0YmF0vVxlI5MeuWLdXoSUFlCqPOhWHdwOg
17pVWqf50oUmAsN+38rItQY6/spzGZXYFSlCTId2QpwvjNL/ybNh1isqTNs4EAWZZT4v63ZOifLp
yfKPs1VkX4HrtoRUvF/BwIe7mNqOb/otY0D8SZQWg2PLS1N1f4dH28rIAgN5J4E1cpeh9uhpihuZ
m+rtC0aEsS8vlbxtjTyZKRUfLgsa8yrW4sbpCMIf7B8WQGOafBHiokspwN5XslixXt9uI/tELL19
/NOOk6ut6nUjzelIdUtDYu+mW6yP+UQE9fanMvOec9OsleFH0uFuyqkuAiA9C2f5xD/1qJWBUs9V
bXob4i8GYa05C3Bl1StOXWR+jXmIMuvbh/hLCOet81+RrngFEKewYIWNSYm1PNR6cQKBfNArOZt7
qxVXs4j6zYGZLTDCqBHv0ZbnQw3imoQXXuZKBJsvVHGoCUZIPeHTE3W5ovKyWSu5uMfNwGLJ0uHb
1eqtNcZDNqml2VEYgZOeDfDMjiUXGi+ix2P0EOxPOtmmCgj8b8EzSNDrErrsmcXP8DtLGn3nMeRc
PiudM7xJouenIsJJ9yNv8zN1GtW4keAWleyO+2y9o5ELk7zaAkGUeFKY18mpMQP26wkUqhHDpuil
O/X/pWoqcJGgJv8/+D+57x/6ljvVkCHThR8q6u1YG/CzsXqMoONQBEO3iKfWG+57abjTbWjoxmm4
g7YxPRVFsLUpS6OM7IdXijwiQPGItfKHqAiCH8yRbLzmx+bbJXOpc+foEL85egLSFzmhzkxy2lUD
0ZKd8mX9hsTbq78mRosQOBexoehEOUi6hr/ijrBCb95V5TaREeolGNWG1KgsL/LNWzV8VH7Sk+vi
vAQPDn1iPawV/lRUvEokeN3RfbYeoQNLlg4BjziivOOz2kT/fUrnCEryQiKkN+8S1clMVkp1Eq8Q
az0eC3HGS85UGfHhCg5wj/bEtHcG9KLxSwflf0EDwZhjNNKGKPYfoG16swI7nPTp8TJT4QP0lkLn
xg6FyRUmHh1wbi5Jz8i/1zQ3XQkxFwvtNePatu9Xd84kTa9pQIKb4pRxGym+EnFyXqOMM5n2VAFg
6Uj36KZIC9ainb9ZkiyTxYIu7xvy3pacUDObxpF8ZoBOTFendXpCU/bWlHXpgXxLjof/IhCX+Xhp
1PwcPlRnuv0FrE9kJ6KZrIRWOQE5go+pJe2jSBUTGfPn2Yi07VTntQaJhr+64HK78cJQdkW8+e/t
bFmxRh/2CRtT3Dd/QIv0azLYk5th7TX8sbs8LnfHG2UZPCYl8uISOqxkJsCvfO6nNpN3ybra12Fn
y+sseJ4By6e6WFv3Uk89a63rjS/I64ESnMiOQDRTrtRKVcV/2kABBGUKJpv7EhrOKkgRXcakBoOy
Db4y0VuDuuZ0n8ilg8f6vHU7YZaKJ1/zPcorFTxvK1ZDFHAI1V6OhQOXtl8msQ2hzkmKfzEf9SKQ
+qbHgiKdH668QJ8jOs87YzTW13hBCZC9OfvtYVpcYAAPv5UOEnqc62GqHnLSmA15yr67W+eSPuD4
izOep+Koge1UL9DbInX86e7pNXKxfnsOgW2NwP48Cl7X+IpXUny119ciCr77Xps7w5aVoIvn6X0S
dGZe1nCm49Mf1RhtNOl9EKqodNYPa7rABZiFHeZdkJnNWTKYfS2nc8VXQsgnCL97rRtlV4EA6fjl
psuYjKsUIgA0XrMOZduJEKrmAIyvEkLarILJO3zPdsSN37ZkqxqPNuXKMjVEf7j/AzfVRg4pbc45
Oe/5d/rp9FHAvBnmddw9XQzTb+2wKGQterLGphsd39GfsEmTYlbmvBIVXeHomw2GyNk9rzQszTm8
sy12QQGbgSZhERt/LXJ4d6wB8M8Y+UjpRlzeU1+QOEnxyyFD997r3RJ8KKQmqFfEOkJZNRo6i/ic
zoTUt1jXic0jLxsVypgQORGVi/XUOcIsVD4ijfy7ikprsM1fNXsi13m6hrAoSZRrmWw6dLk2A0Ui
Ed30JzfjCxWhPo72kVacFQFFAQzBtW4TbMsUeQ4QnWa+s/2Br79Q7OUhiaXmSrTgfjc0s4M+2LyZ
a43aToiSljYeW0EFF2jc/cPgenNwVjeq1apEO5BiMRAUt/P3BqdI5ArGs/g7VszHpu+PdI28ZOp+
/hddFCU4AavFf6zWwQjtSZJXggXCmZp24H982CN0FTRL+9YnaHDEBXfFW4b+/rKZvGsEvBZLmx55
MVxpEkV2nntlSt2jHLdb3V19TLEFSkgk8OtOHpMaLM2+/9rUfWUoDyEzDUzMwVS9MvAF8IU691Xc
7U+CVrJZBCxFTXvOQGxTAHInv/L8jm0Kd4PCv6QFSrFrc1aS64N2nYGqMgiG5fiN2aJShROJejpY
/csf6UAM8N3ApZrBIIOa/BIEtJG+otqs1HN30qF7fKIfJNj5z6tWNDr/klJtr2Y6oAiqB7y/NtAv
ktZKmwqMXFWhFxYsj1UzQnufvRt4L80x9L9SzWQUXVXSuFet6l6GSShhJ0yBSJ3fNjte/fiFFGlD
raLdWX+rJVcw1g3XsRTllShGxOJkNmHeyzcF35oIzj1igPMsMEjuNjJ2ki0fvNy+X/G9qFIs9vCT
zbR6F4PEFEoQV1kv3qrdD5Gq2XX/2xf/9JUPIWx22TsYRJfnzz9yZpzMJp4Th1mHmSaWxTS2FUjY
jqrBIeasOH7yduhT606jXklORRiyADoKj/pX4Q6k5sQwwqgyGppBCVUiEzZCnp+DXiOh9Mi+Cv/T
4m2FA0ILvJan//4KbZuZlkUlVdjP6ufJ2ymfRgcll8Oa2WaVx13QVRcnSgf8GpXMqUWJKoQG05ad
fVGWDv/3UkDtnATx3kkG9ZZ+dyAr5SNjrUpmyT7Ajg6swMXCWJpXXESZhwbyRBhDzSVdwaThxkeb
rBQPVNl4MeiOHGG+Kcxjnj/ZajLhlXG/U10st10oF7Nq6CjQZ/TXMeTQBSqNX8D3mpe5Fx4u3fl6
6BWWeg0/BP+Dbmwi9qCpcplgaoG1d7UXd6/9Bbmv4wE6OHFBdmiX5Zn7tbou/I+NDiSYHvY0vkVU
HFIb/qj6BdHc+cpxA2N/MJodqSPY2SYr+aIBUDIVu5jxUxXJP3yFzVWW3xfw+4RNXArP/hOWlgn5
mCnoGszxtBGfCY5/MES2ANqcyY2t3qK+QVOUPgq6Y3tPSexB954MOzWfsgnDANBGMNuJsBKJg6h7
NbNB9EM9uzQAstOkXQqUJdJ7fUtFTZqz0jdgPLPWmDDzrRxQf2L+jA+hpbRKSfSlcHlp2qMzjJmn
WDfVeqMgsvEqeZLOrF05h0Bf8GUWddOS7/8Yck3T2NULU7ZKyuiHtsaSfOpfBy5qekcVUL+K+ka/
0UwOBLdk5QU1wqUxgcZHlWwIMG8SJ3kOQSANYBDnteLq5dzwyO1JUuq6zyST6X4EdwBJsyvMDUtT
CIzO+82Qg9TQaSfxSIoroAHN3iB2aJco/voArYcSAYRJhYPa34KweAGMqdH7y7+PC10cxEm6bStI
6uIER0nelMzNcP5X9T71CMiOInw1um5+s9Szcl2u89zvjUwTmLARLZUeamA72PwCOA3bmg4wq+nG
2FpGaxJzo8d83IPiay19eLZ24NgDAXqLyEdjAEwNicMHfilFVpUxOCMFFErVBcwxAgw69/FwLN+E
uuKH8+pWy3hhUvmVxWGynShJDZiOR2e4zeEmKsIY+ZZ/9Yc6nWN153OU/T538/Cjz6J0nGo5mMC8
ob8LBiRe88M13FORMy+/v2ZdL/9ylevRjKQeqv2XrHqVZ8JTmNqo1kYAp1qr7oTTp54i/llwJPuX
tZeyVvWlKdEy+IVYIcAMtqIQmTOrvIdIX0U7dl5FiOZUUrrAjzybxMLkcwllBeiiAIuoRhV9lIDk
luRUkywXumsyAGzR+TN3HuGRt2JlV2EeTUu2LQrVylc6awcXICxYwFXc0DB3Fcs7OqejzFr+oRBA
uyFdzxNXo4pE/vF2IYqLAi5UjLOkWbix++ufqKz0A6DAMRnlPxIQva+3C5T8szCTRBd7chopAaES
gcznoXTkTh8MSWIpmz4U3TTRlN0W0GDLAg40n+/zvr0KFRFEmPwRcRraP6j6izXXvlZp/qFwbLqD
YQNzTKbthm8FrHld/3GgePUdigVWalSOWTRbpN/W3Dog37cvVEIqMEI97BpvI8mri1j2TXpqBvIP
HUln6310OaKKgV/tmL29GBzAARUTym1/GPpOlRvY2Eq8OTuNM6q5VDCZjR83GRqJzrASEcGygMeq
zTmpDmLdf5BfBHKeHUhUm5iZHslgzOIyvc2b7xeyuyC6MnLFIHNHSp7Vqkr4aZHEmBS69eFuKwL5
25iYK2ZwfRzEM9pNwhNkJmT+i+h4fIwkFrs1ODVhCm1O+37H2hLMDx0nrnlQlHGMd031xtiSyCky
Bf3DkMdpIGgwPmUtEM2C8vM5TZcazIiMsCCjcojgKKKDKzZ/w1wiCb5K2MC9KW8PtQdnIUgsZnq+
FyEMRIO6gfPPYFijGJxwTN//c+ENn23/74yofPdGyBmuj5HwPJgogmCaiR9z162s0fo1PMMH7Ltp
Q4Kcf92BDElodlACVciOPqYy3OjtrTutBmArJ/cfIFn8sDSPPer9w3AkyB8FrJLBpufJkaCmUdL8
UCuj0mDI0e06Hk3DxHA78L/G3auMxMS7hv/SHgZNf0TMqMyv9TQZGV5JAKNH9aZmZhBiGaBvuFQx
GZdQQBGpgDDqRQqOEUVD1aM5bCxQ5ITMSDCB8CKM/hyLquV8KkrAGsoyiChuestYQRlDxpN5EjXy
rq1F1XCSIaviyRd7xZScL1cForwijJUF20Fc5IVQDPccTJLgImBNtNSpG1OJsFS8h1BhgVwjM7yT
8941jZosXXO/BqYtf4lTFYnY/JF+81fy3dSnF0qA4WtiriF2mV97VkH9SaCbL32SDWkBlM6F/LwY
XLcXz3ZTA1hv7VY/kHnONh/6Cqzi+XhTfWmanD0xequj/daahEY3k6G59isDLyAP9xSqvxpRi1dv
pCbsweaFYA1mM7G2lhbQceAn6NDrbuU/qy4iY/J6Lda6B48qC+0vqYas9MTlCRDwa3ClzNcn5H24
hj/HCxxuug6sgeA9LLWF24DRUnYR77bbWW4i+8JbMVJ8w3GCJ8jWtiBl/vy3D65pq6NQZd8Wes9H
SuY9ljATNq/rYwXE2NuO/2K+HzbT55cruq6w3VPjwdDrjg58oYP/7IsxEnDwHVM1LLBxO1JCEzJK
cj6vytzcsmMBM3WQ5k31qtNi3na5afRaF7R7pcrMzWWl51dbuK/YPpzW8EmaNzNG74DmgAKL87OY
3c9bAhWgQuW51bY5eGokFn5oIwgbyTqOMosEebkBRGVqKwf7Bx3HnQERezeCS+MLTTSGodGsjYOs
DNNs3G0wRrYOymDQa6KTOCx5LbfTfG1lmaSP5EKI16cpWE0ajIhtOyKrpCR8x7oQ4A6R3R6nMsaI
kSGbTPLEA/GfCjJpykuWaXjFyL+EK5yn1PV/iVBvA8HAd0VrnRvOT6X9QG4DH6vsG1kdPbIZOdzX
bo/lUZj3fS5FVtrQPYbZIRHn2typTXMzMy6S92ujJyERtfncrWoYXa92nTDRCURbhwi1COyWJJTw
akLY/Nvls/WQa6zQ4KvAp6DSXItGLPmLS2WmJ/bnAsZ6QwCHwe5Wpar5D7vZw28ZL418N9pVDDQy
uYf4Eqc+WACeIyoQEv0hnW1SV4zCJ257UnAYQG4sWiquy/R470snf+2Vzj9YcC234DT+rmSe3nUO
jPk+b+vh5DbU6/xfy4CEscKxXDLhdfKvjP3MEwxspcx56iY2EOLAF/vz1C9ebmuYNa7PiTfPFKLb
3t7FH1kYhtX79ukEaEG6ep1EB6qWR22jKvYEWK02K226zA+EIQmrIpqMIr1kXSMMKBFVYFAMeB7O
a8z4h5FcnGHZsei3XX1Na5uf7gbfKoEAQg9p4ioe2JUTeMkYjco+7yh7zGieyeWAHOUUvRZJ+voH
JLyM3X9saQ68fUsop/dRD7jWnnJ9h0AphFJ/+9fGZzx46ggK2q2JOtSJeK9cSRFVFznfu8fHdbO/
Cy+uP8pekQkm3PtyY03ubSoRSy/7X9OCv0SWWPy22fMh1QAkCjiK4ltXrTQ9CZiq6QJ1mY/kJUTi
cZKNr0pPXZ3MV3uRRAGS/lztfJsLltRlJE0/YP2G5Alg/8cB/Q51l6of6BGBqqhjACqd7kfjAC1m
e4AZ4jwiHbRYzamwfYnzbknBe3nsQxNvpdLa7IHnCw7ByAuaTCXks6BxxQlqr/4s711elQCSgWGr
8uvb4OmPt/ElsHYpybPM4xT5bM78yg9+hsTPwfTEdws7EZvhprmqgkofHnS7CNtztQ6+GYUHG2le
yfI77lW73hPMqHug00uvfuBvNHkgdnQK3hZgLt3njUvZUPvfdf5uOZ7fCi8phhdCx39Y+b60HaZS
wyjuZYoDiOH5A2AIEtavzGQSxKvIZqllxExXhWqbLOxjjXkvANZwLjC+Pw5JPNrC6Eskv/yLqDXi
xh4TrHV5CSbhocFNCu0OU+TuKZkIpcYbS7biktAyNzvv97lAtyepYcs7b0LMwpuwY02ld9oo6zlx
5KJlJEmcZAd2XtxNX4SbIOGUIts5jLAE12uOUTabcz0TxaPidZUtUed0G5vhaiTJ3wkvZbFi+TG9
W9UdgZ7d/uiFUW68e/gr9RXcpwMuBMSSFbeWR/UnPIhiCqGVHsr3BWo+dR6EAwlPU2dh6aiztdfz
36MR/0mPfeCuw1AIht+JlJHLrZ0NcgDj7Sy9LJtCGSKnHAFLOw5iHKTVE118rNQPBGL2CcT3RbYz
qc7DHqXCdXfRH3UVv1wfAhM0Yo9pu1VE+5Nrz80KNQR5PX/Vy80lEvwNkQVlnpDT7JrsCoIY8sNP
SQAKXsgeujaLFhtadk4GHmmtWyGDDtyNiNhgW5uS6AbwTg9fljNIvT/h/Nf2i4tDJk/M31oW5e6R
3yPyyz3vGXPoDWfZlvHz5g8QwXF0H2o2BQeXI8BRIG41YnSImsLDux6Isicr03e8wAVzkhM32pzX
MQWZ5WWqHZCXtGp3AJv1mleimHDHAEuj9ER7KpRVDf0MXxPcgD+E2hCgR98VpWa5pQahJd1wTSd0
8kpq5wyjLQKMdiPxx6asbJlE+ykuvuOBBIw8UzMTS/xmuf8aYH5DyINW3FL1a0LbRzzMJGaArUu2
1NHyBOGEaICBa5fp/cWtl5nqa7JsKO1n33IBufs77AOQKFahaJJMPLgS7aQD9QsLGKNeObRHRvwl
m9qz/M03AXIO+pn1JI5I1s5p6EELgEpgEFujVKHaTrglUv2RBkY5ZjNV861LGigkyoWWuMZWAEbK
TGM+m1IufBUvsRHTZSIJq2ELUtzdLAYG9fMgg6I305qncFS+fhGQEHJtR35xxTmKmctfBPQMN5mD
r3OaU0JLaBUy07Ghd1+rveneToeviYunnW7XlyvpcDDMa3kAByeyKZv3ZadUApSynXBHOY27ckFi
24e+dDvohVEqVIMo6fpDW/DH94A3DxcLPx5+wtnGM/sm+OdfICqQ3LR1IAf5u9h5PywjtLEPPtso
8ziePLRdwB7BH0oy2eJMKRS7G1aiccGgLAABXpOhy4T4GNu/9K+2JsI/zdsggO/FvmlWFRka7EuD
jar+6YmLmll5Z392vwoE72LJieZERGFHE81qof6w4lSHuQrgUYMnL0HFM8Ki3YAp3tc3PC56XKaG
j/YkOGgY2qHLP/CAxoeZ0EnNj2wawlzvlESk/UksDHAnd6LDFPD+XVG9kqHdOnPu7K3kJpb28t32
Gc4HqmBMeNYaXb0AonCVmL+Luqj9lWa8uyOTfnZGEoCUkq4jN6svccBFSIXaRUI5MtWOY1xTIL7U
D2AD/inxidyqYkhIW53zv5d5kH5ySXP/4IijvZCCTwjGkYSOV1SAMlhvn9hKyof2DI7yl2MYEPQZ
V7g5IxoHzWlhJvvXIh48zet/MGO/ahjADCgXqMjCQiAZ6owpnoRynL2Df9ybJoA09JvwNersE6+Y
w5Sn/CQVokN0G/uV/dU5wuZYmbCQeuQbRluLqtTxGVfgzt9k/ZbmxH+GrUaivi1q1LnU4Aeljw3h
3d4JbJPxFTjs+LMqxMpuDnkeuq2g3tk+7pyjdoLEfxhT3BnRpQgaYvyyK8VEkXQyjIQ9Vck0m0WQ
w0YucjgBKAt4Cz6HrRW1da3IikYcKCDoxP/1CWPA9SRQeBvOmYL6QksrWJtu7afS21RUsVKZSoi3
IC9cS7rUHwmvVZa8+MU4m8df6yNyZnaFfBIxpLEftHBNuN6LnYDrHfZcf4KeVoZDODUrQT0w6sUy
XXM0eTveONh90pcqmspf4RaUsl9Tel2EAo9tErZbpQIn26pjc+No+M5WfEPRnkUudbiP5MFyaLNL
s7LwzlmKuvPYSObbu7koz6t6GKx3dAyTcJ0UnlSfCTK77k2NUElT6F1vlXs+8xHcIG/irts+Hg3g
zoYzu9fCGoOghERLnaYxvyJk7LGdZjmp6eIvX3GehLI5OiIVkvQ6Iea8BFN6+yS8xpFgCO0Z+KCR
cnMaDBvCVavtt0vqjS8RaGl3+hjk/ZpVHnXaDHK7/AIOfDemrkX6OEVhGliIqWCnehROonV5orga
Wav7XDhivbAvLJaBVwDTM+i+QG+9A3fX6jbKBqUC5m5/tlFhgqOGqgRfrJDW/xZHU3JfcwRFZLjU
pSGlRNJ44BkBsYXzMZNkMh5Hj3bIY3BZws41mG8eiufN3BksPC545l58wBqLLsmtHgQ6MB/1QIyW
MZVrbYKVP3bDsYSop+eFkijc+tHkDMu73Rz3APm3fGjEh4F4zp3SCtf+UQqVemTt87PabzVHF+w7
dAOdvY44b4HjKp/GQBll64MS2vFAxXJAL0Yrxd0hm6P4jF2WSVWPkqVh5zuoIdDNvudb4zyvP3Xk
Btpb9RUrIIwkobkP/iGpfkTaxzjj+O4iWvscBqwx7aDBPrhS72fDIIaFNDiAPjobklNPjTTNsZUj
Ba0FYCUYZUxRZ3AWofZRrF4FjOPC2/0BtHxzD3CEqVzn84f+iTW5F/XLWAEkrpivGOYfBoOQa4ha
lwllscgGenTNnUHVIVYGtEgHUu8OWMSm6CeG7wKacnk37ibT7qdQGJQHQxuA5CpuifLue2cZSDWn
gHf2IZW5svGjFZfcFgPA2+oqIUAvIeLuUJfJMj2ayIG8nFr9bKYkQmp0LkcRNHsPYafFzfCGHp0h
hBDRwE8Q4OYo7j+38zYe9/+fSwcOYPZm5/834ogKfCpme2vT4Ru3LE4ubcSUiAZEPUSSEsVVyNqs
p4+AH8ibxumGTBeBaa0DA3CSKwxWMCF7+o8cIZQt1ktfjlEA4a5HiJRccdTW1+3wemtm0EfEC/YG
e+0iC2pocg9lcBAG7ASjt6YgjUt797siiCU+sxRg5shRm7+3ahPBuwzpgI4PEbhrbYLssCyqJUQl
HyNon5AMu0mnQNfnHWNF6BE92ARr/QBdW/I3bIklSxmO7+aBFOAWRnoATXudcC1wuaTz1zRJfzVe
uqgr7F6FO16fhsPqeB1QhEQJttISCgk84PosQp5LrdBAUSKgu3CNdPqY2d3R9l+q8oLTD84Zz0/b
IMp//Nxrv5D3LECFO2ezw9CZXwrJgs13ddl3M/oLUnxl0LZAPeXJITFlU6Hk5Tf7xANYHtPZ//+S
4AYI0mxJvk8FdUSLqkf5jEp92XD107gfdVmvewTONXGbhGjQmy01Ebzlkys0NL4mQRXDj3MIJSeK
ojevyPHMvCAFbPVsSZ5FU9B7jDv18xWykzowOn063+D7vlVh2xXPiGkQIKp90W3hxEZxrsiVEzw2
Xyb/HqDkYSIGkTQkeNpWL7ToFg/zglIuAVywDJT14aZ74hlV0shlCle9tEUFA+YgdU7eeW/XU25f
TeW53qdf0g7Aut9AUwOsxtzn5ky/EFNGCJmhxAAylnPCSNR7JqEnI9gAF18j/lwsEvUT7FMMSO+8
prDD+sMwxQdR6LfzqwPtJtRQKWQQZpxXcf/+ylhQmRKchoJ6Z+tpCnxoqToXpI1zeD5c6tgRxX+f
91DzM0Ay1wwExK7QpxSxCJ/OgFkwsj1ZYqnJkqhhP2w07kvlblObSU0P4Fo8z7rh1308619Lvkp3
G2RP88+79p2kFBj1T5OZOxxdAW1MBYIZn1nbIqO+LX/mWD0rot+iGgobLgRfsSmTUbIgJjK6aiWy
i1rmUXQBjdvM9jtko64VzVHjXOatkW9zyGeXHls+4b2DoqCJ5usTo+IoHlQ05OzHijE/9LDvNURA
ov59o6FjhThgQBfkMhDu8TQVO2WZfrpvkrP4+Z40KnAMbCxjUSrKljIYe2vbOwNYOvQKcEJz8GwW
7EohoECnIQKnaNCuIG6ZHTjLr/3FHsh/VeukQUBvnCiqty82+mt53rzps9gmjKFekEsR8BOQOWki
efueIl10JA88Roag43XQnJ2SnYRtCkpJjm7k6ux5ZkvXeOyg662NdwtQBlPP+ADmwMAl22gjPIVu
zgbhwsJS+2mh7kWwmoWUZ9/89HQxPymitmut6vfxEsYi+cEXysQiNH3huTdhyjm1ds3RuIGkvM4P
QLbpMqoKJwTKJzqYmJhnBuEMCj5i0oj2TAO5Nxxp6q9yRBsHrq+KHfnXmZdaa7f242T1oazmcNDX
H3QlchUvxAEMyXgSpkBIQzf41kPOleACPjU8ahYMqxX7lPrlJV0bdmYOeXSPxcjrMjlgrjD9jY44
e4IlkK3/wEd5LgEOZpo1tew171RvzSWTBMBbMhpjn35f7PiR3xIXPf3vbTMQuT8fGMHzqD+0m8lO
ANLUK6P/cP3hApjQ0Y2wIU0FU5AfBN3LL3F7osfoATzEZIrM8uPfNPyAc2xXtYXSuu/I1GKq8jpC
trtYANbrOGrLz1V4gQSsTs/PkBfnWEt+SMZ3YZ6LsI/pKGchsZqDkBt11ilE6+aoQ0Bpyk/uX157
v2eGB8sSWRvMZ5Ag7NE7eAEfw7swxKRZKU5CACjNINc3fUD8kR5hK5bSbTIbqd57t8n/upT4yaco
jThrpQyFG3Fni9bLIDnXAkB7aTJDG2DRAruTYrUMkKV0ndREv8QugD+2zffZmf16o0AFKOQtjGAk
W2PHLIoUsCsQQaKk07CtZhVI8RJ/tlZMmgUN01/obNBqMjCQ9LGyk5T/efxsW7fZyo68W80yPCXI
pcSrRdZD4/7JEW/RuvBhPfdJZqI3DfBq3q6Rmen3GEwX6vePm9XubVKRRU3TXsZM41nfpcbEF2kJ
g+wkKY2nA3FBBr6U2VP7Gi9m6S0JxlSPoUDSSI3Jl/RdKd/wmOoZTzgPjuxiL2/xcbaXLMZmh6aO
aTbS7HKxjl+hlv3N4rI91BeyLtDFFPuU735aVUbZo7c0wyJJvKuFCu4B6XxiFlBfQvJ+ZRElwTRi
A9jhOQhr/NxF9C+0XrtbSIlTXhOj6ckX5jJ72dKMbKWP/jrJN5hiGbk+bGFscu2qMJWGtd7JWXWR
0d5b85aKmgcuo5PpgzQiD+x2S+549QNVGL1Ckc9S4s7xek1NT3//RCb7ngihO1RcH6CbDPdt2vPK
JKFrOmU4HqGhdW/2kHUT5HmlWZQ5sFZ9Cr4Ot9zV8AZGnH6CU9jg3t6X3yxMQzRITt7NZ2/b+5qY
G9FBYuXG/NI/76NjpR5lg/3HYFmzmNyH+YQgR2zoNa0UM/S5oDFnYQP3GDE45oJPd4sERj7tDac/
vu6F6wVks4GCrp5M6N/j1m0YAyARwA3stXZfdvFMDRAQW9c0H/lWFUmuC1RvopPjH9hpsRIcnigR
AgLYkBnRE+Lyx8fOZG6iHMxRdBnx2zAClvGB3gEe/IAkbJZxcHMPKESo72fKzJsdkudFVXd8zCZl
DNtIDJUt/A0l3i0rBb1X44BrUwcG4oBlX/pWazfXYMVkgJFTazeArKIx87Uq46UJ6y1lTJziw+PL
oiSGumlSDFqelCS7dax4NTajpKOZN0YcK1UoFbnlGD5Z9jFsK5k0ljOsxb+MvalV11ptJoYPm2kO
Jir68PzIl3KTeN5FbNyd3BnTUdlJAdTnKTi0T9+zEeCYuQU3RDB2aTFPkfaNh8IoUl+NIa2IcZLo
J7MYbssBLILh9eKGIhFdHPJUj64U8FUotuMNc669Fqg0QojCuse1ku3rwGgiJkiu+7ZbjKu7XIzr
Ww8xozptsBUUjfpBFN5GeLXLLtfFCtRgvRh3mIhyUmz+0QVC+0IIsI0acuvSvG37TiCfhGtqPnKT
bW5f8q3IBLrd6JPMaq2zoyjdOzbJMhxiaql0DCYoVqrkIHzIYUo9+wPY50G9IeocXCymg4uBlyFL
CCnoopTP5o8iGHlHtWnxHs/8K4rle4WUPrtF+J/sBhjqGjmCq6gYy9XAne8Gc0NKG1kQqgt2zL7p
xcvl2fZcpFWjwIlG4x4czasMUbf3kfRw00yh9KYu63PlQcDxUkrNeMCCf2HLiv5CdBfeqpvaFuFv
8neJuZ7Fv0kXv2qsIc1Enz0lIVdWVMJUdM+WJqz4T/++XrVnxgR+W1OI1FKMb4Xo9XcPNnFTpNPr
Ae5/BvYPPpsiCYed7jk1rzWFXaTtcvbEmpiPahQ/nK9e3N5UsQUvwq75iGzexsoxZVvWRQrIzQLH
U9CfElsMbA0FSZ+IOwL6wf7srn8iNUNro+nI/a0ia/5OGbpW89qZQQ7vOiy/4ev6tDhkl7k94jl5
QqQQqZsWEJMwqLXUA4M5FWPzKlt2n2LWDWP3JEMg9BcZffiKyD4G8OmsfjQjdvZzb7d6AbG4imdJ
GQNDC+kK1aX3ryWX2qgqchzwiCfGz4ws14Jn3iRPQUorUWiea6MIFRmYiTJRyPBX2FxlJAIvK8IR
C6J/BBkqyceRwMGbCmgK4LDRZ2CDG4R0+Cs1r9FqjdZaCQTp8A1QI/OBYnimvmxLgyfrBzwq9Zju
4hu62ZoGpc4c4QdxS+FHcBfRKgtmyi0pI5guYnMLnOvLFFt7WLvoCFRUA/1xh1L/zPB9C4pfQcym
jfjfP0JoOZKrmnTnuwPrDgFaVW239FpvQz/h8fQAi9UkSzWXCiVmipPlc1s05n1XVwd+2OqsqRuN
ubZfKFzZQ+FOb+XYpd5GRdlS9QZ2x8D9fUoKLnOP4/0VIKrl7JKQfHt75rzbNFhqO8uc5agGjZXo
L8EMESHwuLKExpcexLUdR71Hr+P14LKDnOBWZOLLnJh/ibgR936h311mVi13vDOA9JdMGXA/Fw2z
OWJBeEhecr1C3otxJD45OCQNWPvWoeeGV2IRQp3b9/t/iHMR7qvBIxqtSYP8KfoNerduH6O5v13x
L9OBY/x0bihk2mwCy9rdmwvM6a66dfUB4tybM13RfbL1xmb7hmpnEOvdQpjKfM5qRviJ2L3oCcZS
NraeIXg2XOdDhzIDQeyrFzUmzXPtuYN1jPSj8b8ZVJeahLM8fiiRxMuVtfDQmlBP5pKPkXUG3thq
8Fp/44i6Hu9z1Htg1Panf2R2U35aNpdh/WsXqnwtEAdHirNJVTT75PWAOnwwvglG8XZjy7mXvJzC
PASLhPu26kHKYw3PIcQlLm1f/v3RQSUfB44Zy5AEsR+Ahz/9wewv2Nl+a2wRmTWcfnrLhn+ALAb4
OzC3qHipr31RaMpntWEQSUAO2+Ff3w5mizoX4dVCV1LlYyQ8y1GRoneOqnhDBCzRAW4RBI3v0iW9
qpBq0gm0Nqo0+xkIZXgNKtH06dbTsiublAqNFIhQ/DjaN8QuRF51OzFvB9E+UQXnY+mvTKu02zD/
zWAHJtym7xrYMw4uQupyWrDFSY9Bui+F0xmYajikYsDkJL7KXKpKE6gFzT33MASrtYCVVl0WvkET
9jscfLTpv8+pMCxl1flfG6JDaSuDmjoeP7xXW3G2gZQDp2atamQ18aaLvF3kKLkm+8eA/ZziLruA
7s/ju+KLSv456Hy8/dv/rWo8DRzq072hmYaf9qp6f+dVTQPg5JKyMCMNXqB0kts9YfZcoPQ/CQp6
plMcor9ZmaK4jA60IQEMQUmddmxSLO/FSBxZM21+ElVBJpTJONRcK9gY0JAPVloWsQKwMsR7Tlpg
tthtAfq9n9tHjUYMBokbSnhocRY/m94PWChpsLQkSy1z0KZpxWILtQBveSRkF1vE7cZweSX+Xw5x
bgg50XsQXskpafDzr+9hV5qBtHqAwdV2lwzEnc0jGmDiiC+k5DP73XC2+vn4L4vv5aavQBtKSL7P
Y9cr8ZIeht0sVJ+UvZctd3nzrJZgi1xcZbb+YdALrMWe+UiivaBc/5aTeObuR2VNt6IODpM/SDDq
D22J0SxNo3hYngRcefD5bS7INEJw76KIxBDW+af+4/Nml4qCs9ikVj/4tL/UQUxpXIDVIW3I4dsf
lkCmTdYbyVbyN1uWoKcqNMHxNpRIxAFAiE9IWkstouupU2TUmWipIwr19SzMpIgcWB5tWtJHqvoZ
xQw8xYlJkakx4LiNnHWBytLwnwlJPpPGRzyyDymVGeeSFXLejT3KcxcLdg9dxq8zzvFkoSrh0mh8
E6jdVUHDz2VsZ/qM4OYHJXBNB2nnxjpvFhWXTFjIHHiwZwozlgEdVGwBF8Udvcl62IXUx67JdeXZ
pox5DyerYhL7TETAaPRpxSeaA+WjnUGPeGkfaW9Gzkc0yRaLk78eHfPo0veKD6bKeZmht/tbPweK
jePdlQdZzHzeqGDroVN0X83kbGhT8FfUL9S631Fk1e3+qDrClCGCb8EHvR9DL2RHtFmEYIpaRWas
Bw7GjncTUTDs7/7U5SiACPJPlf6kPj8XFEmTs/xS8zLugkkyxlhED0ElNMYT1YyBYUyW2aCm5P7g
EY9VAQ05DB/uichfsgnDdNAJ4vMCT2b5+Iy0tS2bA2dNbzK9dtVPdPEKLg7osptEWS9kO4WbQ+T2
08d54ABe+3HYi6I6eFAzZ/OXoTzXCca+T1bb2APDasZ5SswKv8OWSFt2hwUcX1XZCpVQvjSnvfnE
PKeY6IHkHz8WNenJ5flYTxhApasq5qLUa+Bm1Ne89nt1aS3PQQ02MqQ1OSWO6PNf3kUYintPnB7z
r6vK1BrFWBP2PIfb7KBksYgmJJJVwvxbVtQnGJnMGU65NofAvTmjbYZGG3VhOuxg5dMvv2WatinG
MvaamoiQ+Ra0LxbcFpJ+H/BpPoQSO8zMo9keymTxpibftbz8yGdo4DQAEVO1KgNEf44NXnhtCc2U
jjOUxZi/20cGwLsnju6vMiOpuKvNwiJTa8oDNAVAc609lVOcC9SQu3eByY+zHd5SeD8vJtfhk+dj
zBdTlys0oKuWxDcX5ytyF+uhR0UyRnSJVF2UPPoFHZcBys7fST6j/xcXOvD5JWykKgETRLV0TZuL
15hz2hx65sQuZLVu9XI8/ctJSvnzP9EI9XtFJyJAXXYdxGXhibgVnZJN6OxmjhPghDn3JefmOLqC
tV76+amVu0IqccWtF4ONMl44JYFe7hWFz7Oabam9G6d5mqbq6d6cOVzJ5iF68rtg6oNvtveiglba
rRUlJlT3uCgzozaF3hRfPo8M+EjYylJg/O9TN6UHG4UiU5Y7YD3rTBs1pm0J1pC7Tbjz6oUVPQkN
tHzBB7EcoLp586ZJfPQ9aWVo6YME63l1W1t8Oy3r8c8kpB9RUVJ1RHTsbfcBhfTMlnAMs0ucphTx
IG5w4SjsA7FSbjgApfzjzIfvwk8s9nwJlQnsgXpCTNkqD2GB4vwmQuNZjC1ccTe4gmuI4W/XhK6M
769sub2Cn5gQJWkw/9ZLNooO1taeJC7slBSLeQVeDOahoZBNPCC36EDO86NCrAG59tA22hZfAtSR
ep6Mo6gaGf/+d5SdFvpBJQD7znFvYrfC9lujp7G/e0f1O4bfglWafNcKQitw7egFamfWVijp62qG
zqcZS1jtY5KR1iWUzjPJktL8HU1B3SdGcbvqhJZgbgwtp0XY0EC9Tht4VPNFjZPyX3fef+Xfr1ge
uM5jHLc8ZzW/nceo9bR6R1ruZeN+1O8JUZ6Kf3jImQHnwhbVOsgfOLKjVmmDY3zSjlIM7/cdIhz/
0QDewFUwXBQ7RevDfIWPJdAj49Rvp2fJN5ZEWFU1bHOxNlvWirRHP+BuAea3sTp8o5/b/d5YIRhV
c+s00Df1d0mgpWvydnh5IjDVhZLEfw3CHkM3lKO8xQJFmLK/cskE4X+fA3rh1GXewhjfkvUnkN7Y
M9dCgIFgVKD2poySXHcvAVcyDT7yjcXzlaPQLAKZNyatSNVyysg/lyJKwKAmuLj9yvovnh51foTd
9YU9cIwbJMLImFeUrnvXtsIM66Z0XhA7FzqZzKVDwk6keAnZ7XzUCDt5AuN8tSWxMxuF+xv4Ztdi
ouc6XSqxgt+C4NSzbVV8zvoQbXuW/tOKXmBFSa0AIedx6EBwl1pFwrioUtvRvFSHkr4UzGK4TCWM
kMe+W0bmqKmRDIICgPMmWNbADJBxyu8wHml7slc3I0tRiSvW9nalZLQJu94eohrlyXMEwYOp/++7
s/wEt9vOTv08qkR2Hx/bJdhYvkJFArOHDSpJEiqB9WNMts4QFJrcSI2jThTQpoxMPdu/LXDm6/4u
Bzcw487JjfKsaFpfB4rVENbdU1ABGw3L4QJJRZtuWk+PSGbGiTwlsi+G5l5Ibsmu1J55A1zakRIR
I1Q9p47PhuCOeznJK0KxryZHxYxAh+vMe2VO8MbOYdvhCZ2dYmfTVNsNkIr8BchsgC5hkc05CUF5
ejWDJaCDseMOTuv4chT05IrUGb2EUxwzMTcCk4TJ+W2J+LTicm96btzB6J1XssfwYQlLEOOXcphT
kbL8RyuDVKrajy3rHFTOfA980zclvM2j4wFUO2uaEMPiPtT48xRZjP0clauaY09lvEMN845Yy54r
FTQWWKa0emQqeATtjN2y6UB5mv/xMHmjGnLl6GjArp9ehRaAxXaTgk/35WAC5YHGGKZRKwMoK8v5
yBBxn9P9/OwaLptIwaNxacfcG4+GDR37mVebEXxHhvIfYuLDD4dnsGszDC1xjBi1WpTmGmt+A9Fv
m9q2fsw3u4RqJ4vGkKi8TjjtGEmYq6b1n3q3rPzPciN3AWnkLTl9oZCtr8Y8eVN2u1LGJkJMavLB
nCfG4EOMP6lGy7c7ECTDwYAxf2efzEg7ZE6Ce09hl5CeCcEJ0xFSBBoq3jHvgt6b5BD42sk3fSq4
Z8Nr/pbEij7ExhC2YnH/FLjrvSjH6xJRcZxkZTe86jpGcnsozjhFjtmd96Mi3PdifqPJSmn11EpG
Q0VVdnuYR6BsXVDAdU3l8idB8qAAg6f8y0tr1W8YCsmOALfh5Lio31Ff05+VmALgh/+mVZ6gsNfN
y+/EL29XJ2dynz0wRHXt4mKl5M1RIEPNMtYCKdJXoU3nASwppWPkbv7j3SKmH1Sy9Y4jkE1TfT3t
NTUL7X+jmFobz4iX2EtPsbUEy4Iz84XGSRGEQ4iC3GG+2DO4XdF/NoJc3ZrEcsmAoOUnbZ2CvW4v
QomtXoLkKaCCaiKAdlx8DrXJWSjmFjnyy2YUfd8iT7p/Judwl1D42xdDM/Fu7EBfmwuYTHJCuUeR
I6JJ/JXb9lE/+ScQuWXZZF1miJErVlo9kqxNJmsmXKDGhFRn6xisbrlGLTFHTqr1Hy0KrbTi5x1d
NObd7LRztnriVOfsAFo8CP0VNcHxDwEOWF3rMpW402mTAoRbDsMKpBTjfCaqDpBdNI9gzuic8eVK
BBj6DUwNsLDttRdOJvM4mYRgpXWAiArl0Tj/HLpS3HAM9YTHTaaBTxW9KGCoqOLf+enuc2Tvd2o/
puGmJjS6Iata919QNNl9U9sBNY/UH9tqWH9w8UrMItsNamdBLgQW3h+/tlLBV3TPdcxy1O+xN/AS
bsJj1Jv52LG9VfFK9UuZMKwXbCbC2bcMDI05/B1y7HcO3YRiarVDKdUvCuYcN5aKkvp+joA6ajCi
PhxFg9PJli962GPmbl7IGaOBYSLdxGBtBFfAFRHV5Kd061AlQhTz/XVvf7jR2BctH+jn5yYVO6vd
1ojVnISjl3GTLraiAoahklv0T7XjFWIFbfHWoiTC7wKQOXX4TeeaKlx47Z2pUhi0+OFlqTYrk50r
dN4kHfwLSPFewWKBCfZGfmlKci3hGusnl5cNOG16PC0MvMbuoOHxiEpVA6NId3wwfPumD+8l9yiZ
7YHRKRh+y5NsRPCxIGYXoMpO+IB9SUVl5VH/eYNuRwBw0u6trGCrXJIuMJlMiZAPVLtnDNGlStZ7
uC+iVXhwqEaIlCGsXr+59wJNfdD8gEUtijfG+BBSxT5/EdMQV6hI92HXs/6IUj5BW3vdMwvMhgeT
/2AuFtEgGtFCksGp9zqc1KW5RB2Wam2ZN151GDO+FC1AvdFTja9JzYFUeJOvUKzK0Rs7vKLuMiRh
SlFVasTN0EBLNK2k4hccgHd+8PQuWWeH12x3WleNooC8xFJTzqA+ya8faIQZUb++nI91flxvI7CU
51cAbLZCCv86UYGis2rnuKkDoBGjFe0iMhx8bpD+UpFp8DmjoK0qltzRzB2yo/6uE1W+D68YkZQH
1lJWSjYMWVBgFhzOK/n6idrrWGmk+zkkMOIMG6h0cAziq4weHOTpgh0Gxg5RB8cps/KecfBWgWHo
Z/GqkY2k26XNytV23xSQD4CcWj9st06S/pKF/o8P9dzrahTMWgsOUj19YJesqtXCWrgwXkZGWn1z
LIDQy/Xrqb3tw5pupTHfSE3bPMwlPbU4E5v5JYb+bZbj6rDajPMxBN/oIg1YH1u96YD+Zm5oGzqd
YSD656AxD2qPQFTHk/5pz9bmIWyDoSSptTWcwkO/f4/EJFMHZMkR8pcckxOJy12U/BQsxHzuVXLP
rxiXDYV4t7r64baK/od6iivETfAeX0uTa+VzDSC6mjzjz+IkdxL7A9wJ0719SV8EJ3k8X1OexOA0
nqIDWVeZ6KEbOZlarbxt3PmMDapi/4OrSNDK4XLETZADUo+7DtIt8z6tku3llpapU77w+NkCdrN6
eWSLNqoOK9rFfscFtrBn9/JiN2mwZKrkRJ2UlI2kssIQAMI0D+jbl5sbRXcl8k4US5ml/3A+cpMX
4yZxK3tzf4yRhvXsM9leGbQj3GtZqv91cJUgML0lp9PvTnAps1gHSgzxBDRrCI3Y+chOD1/llE5u
CQmermvM9FAOT+ZDmayHh44LS9Z1XZX/Fi5hxAm9ts0EP2Yrs86xepgpRNMx0lgUs++EqxRV7rxy
8OWyEktA6Bw6cHRe1Mc57SCJorZ0LT5DS2tId7KFAwjFKyW7/0CIyB/KMBW17XTod0chN8AbNcnF
LOvS12WjU3lpIXINByV3mnxnl7NXItOZSX4FBtG7tTZ/qN6u4stRPTynMjIEWKrREz9YHrbfqGN2
Cc7k9GKkKh1IOl54OLHO6EMWDk3IO3xCip//SoVcE8wIlNvbClamxCBAgdoYKRIoa/2yDEEC298f
Fu3/uMgFuC5lcu89BIILbOIMhIHqfsdeNffZaHjTr02yZjV0QybnFBUYxVqvgx1ZB/57wzOXI0qf
LbUigKdbQX0Y5S/lUU9I16yL61IpwKl9JTUhidnzYjyPZ0H4EeMrrFC2Ee1xk1XTDc6oyrluhMKq
8wgUArgaWyv18V2+E2q/IO2NDbo5OuQXs4XqfRTHDDdyuTrTtu43CUWmUx7Dz8oGWtsXJT2zSowi
uuVBaYs5YL+et31s5RSzg2OPuoru5yuHKYtQ6hO5qh7SxBjVgRt5OF0VDtVwfWMNSj68fUXSITxj
b66/0DlRankAx69n3OyMIHZ2ult6SwLZYOeDjWS41IMGsEYqy5T4PCL0abTNOQDXhFAQFGTnwVoo
T30SbVwyIaaN1bLy5ayeMWviaftBG8gqvnzkNLWqOV7J8Ht+rj49WJQ4y5b9FCZpH3USMWj7DelX
QWaHfb6+PMVUYBRkfKPyMxnl5qQeJdH7nwBpx1G6i8/SAZPNZ3nuO6KsZFmbIr7QSxPiPs+bR9IP
BTywglqZn78cmG5B++PVigGCozWy4Pl4rNQJhV8tC7usJf3bekglPW23xRxVo3k5ZvPEiEzB+zVu
6T03EGipYK4ngeBWdivXfWd8eAJawaS91TDwE9YNkGGButu6WxMAhvS/av/0KSmytEKOCG6R+4VK
tUfpKe6i1YS5k8Ft+0H6dee8wuenzdvaFfy1UrAslUCJ6LrZVdabygHi4ii/QUYfv0UJJSGLmWEn
VQfNqOXLa5sxPCXnSfj0hCopR6PVjeky7qEvzOw2j4kXH5g797RHdY5RDq7mm/IyzJgkFRVOWcHB
6yetTlZsnxcZ2QkfTe8dF3CQboMpJcnm6yAPwP2W2LkctHpF3RXOjr0Ny4x5yQZ8npmmcPTFmTwu
N7Em5U0uHsIqQAkklFkjFJ55GEg6DBAjq+jHVhxR0R8zlNoSd3cFXinjB26dhtcm/GbqBuH0cBA/
7T/OVOt0w7K75fwZT2MZk7gXdGefN69yPRX6ftbr8Mb/Wp/dMj/CmtfAeSjfr65Ato11bNgOf5fg
fKEjlAcgojNWWaCEKcK/JShhMeMp3CiTmtIVW5rpl5jNef3zC6SOPWp0MgrhuZBcl84eBoITx0Fe
hXY41Uv/wKS9O4LboAUDjPiVBlIZYizNNx7hzJ+JBK/el/ThvH0vKeNdBldpIgaL8OsbCH7ZzqQ9
zqgSuiVRQHxfDXaK1Of9i0eqrxheJwQnvSU3FcABjLLmUsz7/9uILsLp4Q4b0tNc2fm7NEkA2/Fw
HsHs1BKAcbaj0PB8sf2wUn5GW90WNDbiQOiLUpJEpkpmhyebm+w/K9gDiDpL/Q3IIIyXj33Lq3ob
iF5arFERpvIcYs4pP3OrKdAjkTak2t5bxSo0SbQXOTnMDV3SEp5W8heewNmR4MSYj2h9HbsS70s5
Fv4aD5hNOJXcYfQQ921lem56NBzkOrEim74j6dzkYSeLyKVNFkUevlDV0Ym3mSEqI3GOg/HuY1wZ
Too1xZ9p2bLHw4JNtkL+MKLhv/UCv/GOHSjelBFlTLVBxoEf43YmlZtQCKrxWGqvjHf2XyXmig3P
X7tfCRSflmvhnFmIQLjERrRuuqyMz9szDqICEW5Uv/u9GEBO71lBOvj/Nmqd+ImbBnOgsLLs4Dz2
h7RxIN2Ab1vZvw562WA4TYY3Q3J1PV3GjzLCaGCVllpkBEI7Y7FvrGV+y6Y987eAFxQi4BC1R4KO
VUlA4dOELv7BAwJ2Qbv1MLcIuughNT1hegYu6UypVR31tV0ZuI6Vmc7ywWtQ+1j3HzfbSDKcrnsF
tKfM+F5iDwKYDs2bVDYXWasYFPp49Zdgbw/T3xWN7CuNVZ6UUhNPKH79RwE01+Fg2nkyMISUIRRo
QCgZVfxs/YFs7vGrq7JAkgaM9d6NVDb7TXmracrSFGL1/kdyYzH4uF8CiEZHb6XRW52fnhG/ZS+a
BxYTFZNjmKSRhC27wKYMZ+ezdrHxJ1rNlRsvXz0WReZfVKgldYJl8ovEATPyoX6G2byesZij7YSH
VJ5TcKhgE5Fqq66Yub1nHLZuwjOZF0+0s0kA5YUwqYpceWXVlMTcAZTQuTIjzojTYY+FvHbpTfL3
E9zNLHFJrHcEsyF6cfXoSFO1otwv5XZinKQSeTmDcchSVjmN6axbLenmoz2UJnI6YZ99mjBjLYZZ
+/IO5akvmYBVE7dtaJC5JaKIJn6DMrcDQZTqk5O+4E6z9BjqoiRsoOsMQ45qGxoqmMuSpKdNyob1
rOkys9EAkWIQ3rSx35t0GwaNa0K2Ni81zcWxsHwbEgUNM4wHc+1+PKDSLfSIH8hbUyMNw0akiCFa
ZxPsd3UlhpD4SBwDME+8Cv8VrLjtLhYRr171LCdIk6EDng+6jTS+behr9CM3QjzN7xe8E66d9ep1
wcAG3G++KOwmxTmiKoRRPGXEPqAhpLIcI7RCFXej+il1pRxpPVOUQ68utzsqwvJXHarYmIsqqM1d
oPQDhmSZuKBhEtJVvIsxMb9x9oH1pFRbVoOsOco5Gog0eXwXmSlny6QxA1mBGZrgSWjfIfNmRslr
x8ISv+ovZirTnQQ10r08OiZgv+tV6+9oFTQpxcDYDC57Jp8rA0bOkiWPGjJOVhi9de1nZ/++T/mk
ihZpH0mfW3NBxxqPTbD5dvcJhNGgOZ7Yj79e27NGeeXBf4lM/cJNjEJbObJ2Rk8QUiPEhk1ZqhAx
D80U9uVs5qzwo7c2Dv7mSsEqhykMekDB531sptstwbITWbSvj+p2FiJq13Ay8hsMroZoe6c1lcFO
rDPsIAAzZG055iW2Pkq+MNR8FXFaT+SBQS7LJDDTdZRxKUfnRE7TEetWlVwW6v7P4tYP3cSQDtG/
jv7nSdXR6TwIsXawU14Y0PpI1Ei1ZEoY7Zzm4FnrPL3wMuNqZ4+0Nu5nCTmhYcTHldiu7GDGabvr
X0dXbwNSLMXcNx5TGt+SZm18ygu/YhCe9KdLwpfWLL8HAA4PGFeCLlybC+9+bizjl9nEWhvfhcu8
FfakIk80mqwmIZeUhOfcpQeUFuYEl9bqj/qOHU7YEol+y3y3aaYUZv1iQ3Rbp+fC0Me2b87G4NiG
lxLcr/3E1yUfOoBiMq/cdKfJJVqH62b+8a47Txn5F89TgAJYOaV6bvVveQiDhaeqdqs0KT/HTBIs
VY6ZvSSMirAm8gQe6uFtNHfJMckMJ8f55hIZ/Vr33fqryG19Z6FyHEMAjzlBqWSqWXiYW9xKAN2S
p1mY89IKOSUsj5yk4NffQNKm5HTxEaUyE4XcFZzSKQE1p9fF9YJlF8R87k8+FCdBq6Jz8tjGcudD
olhkBi7OITmdJ4N0afs8bMddJJhqiytUpuLml7adPobr50l6sMpWr9NSwYLIDQfFH2gb5wSqH8A2
GzioQTEl9fngALpOWTOdQ67fG/NFS2zR5gtk9VHTtia9X+gSYaIjbWo/DrAqzZ4ij87A7+aiCmtJ
QzwU5tWDYL2qwhzouN7qkGqt7pmik2607wnYghmgwDtXkIBcpEapRwBak8IVADuJQYR6vLmhy9KY
dtOJPPctu6B8LRiP53WRlkLlhLgVyszxwnskR0JZ1bQCKYNybKFScBDQpYqkAXrWjqDNFOpNt1AY
1Wvqv8ZG3puP+LEvc0JukNp/hofrUOm+M2pQpa3A/h7JwmX/bEs7ZCx6LUVjiBI91fbm1ZtvpKyu
jR4xB8DaaLdSHKy1s3Lfgxlcmy+gyZjJLPckpLqi/a4QK3i87sSnOh6g9MocRtl61fJEIm6pZkyT
92zD0ZJtOPvSb98/7GOAKIVnlysgKtszyS+cHTvx/orM7+h51rcRV0xbeU3rHhyJfX7TJ/KiSIvn
Z0QJURE7Bf5s+ZIaLfRYEdqKrx1Dbwzq4e5VZO0rdPap65f5R5ZJpwH6d5Dfe1jL5t6cw3M3XVTM
6Ed7j0b8WudLO4v0qEOczPdjKmTXIakzHgzbkABCdXku6oMNt9yTCnOSGviCjMtoP1V1JZhdzDX7
MvOWo8DFI6Z92cjF2ttgFyI3Vd5TRv2FB/F2bgQaYOPzpcFQA1jKfcgJEOc/TET+VLw2yg71adQ+
6q1Xtc4f+GBV4yMcXzZ8Fpze0CH4OFJ7PuPIoL62pUEaoJM7YkL5N/8uxX7sDBnCU105085NCpzq
NHzcA/mWp83Lkydlr3jvnxgM5OQ067k6LzqJH8G+Mg4pkDmqI6jfXkMIhG5XumikOfj+RnRbjoQq
aIuboidoqkvm8ykVPqAg3drnyyXY+mwq7NYqtTQ906lgY9e4ANYZxpD0YBbsxUx1dNmWQKDYrBps
dhI7oDGZQe98620izflB5iGDKShVrssr2mKuVITy6Z5JdxLVhEUWrcP4HA6H0IxgqqUrqfh103X4
ic+E8VQeW22qUVkbBum8mVZluRoZcN5bgIwrsQuu5ixqw7dgh88EBTKctZot65vIwXHg5KX5xWYc
SHLS/vjWM4ThVbnX6zvoYSzByCf6Ga5m3C5dWmBLnlsKZo8rO/BDyD0UIo4i6Wig1GmApvu88YZF
QT5c4507sqa4lc4ObbSU3JGDzF7jUZwZbtrKW8tzFoXQp2B7DpK4JXFzZHDPRMS9rF1iKVO9uvOj
R9NyrZHM2GYE0GHd00jBo1EK601WpqpytRSbsX7dJbTAYf0vA5ZTzH1vk2MCJXuJsQ/QWzyADLR3
bwxWJPlhB1YSV0oGSZv/RFh+iyJ9EbJj+iILc5wo7b2J0T0ef3LLaUTklFNwP+qnvn7Fq/QoV1kV
AO4wZqKnn0nslnnDQjKzHWyyNG79d/pe/9zBvRbYQdmJnsVfnqOu/62k+kYG/0u1ph+WGzrKbVUJ
iz/l+265+DC+MroW0Enk8uPP6MiTPInT5pvtfd+3hbvm5/omRiwglbiOXHvjETyNZwn4L3ccoopK
eZblNE3ovJ+kcLzjWYaQdlnfBzyYV57WIpm6U0kb1pZs4smfTlzKhXwAPtYG9URFEjxUfmV+90zE
hIucXPfnc5kYif5I/WlKBkb9gwnAR2f6ft/OabyJpiFiPoGX72ziZcdRaHJKl+y8kBmYvnkpnYtt
k2hvAJNacTl61ahm0vgcMqBn44TnuJThTM5PeuixOKJrfIOc11otFWFQbklvsqILJqbe+IuQF3Fo
yqyjdKwECHLccgDst3tDFjG/84SOJuz0otqq2c1Oyd39SiK4CoZuqq5kQy8LUSRrqtzCjxh+2iVk
uQBrglvZTTAxiy7YFhD27BnY9RVdKXDp23XoPbE6u7Fv/Ia0M+3h4AtdIQSyBF7dFAop0UIhmhT4
CXxMZg/xIg4c4dnLE2tJE33EKVObbE1IncNZrQxLhhtNxcCaB6sG6orooH3rRAwuU/2FxFzxo5R/
NJ0RmfYREnmdM2RyYQVSPgh4OdcSVfWCLZo3r6P9MPIFIdnmZe8WDn1Evxu8eAsZ5/kkZf/W/4eT
gGCixzyeli44B1n3nL0h5b1N5yiHfReZ86KCF/4676cZwh0JVIVEgAor7F+19UGqViubd99uN6VL
wOmgku5J1QrfDHfvAO4ZfUV7LFHQbBSy7n3UZaWwvTC+n0y1hHarFUwlXAoeIYr74Xh3DV4MDV59
+k9GuGqLaXQlMYgFynVRcRGGHDLAYlUHGBfDxp11LEzNcOaSUSlv8zt4ARjJ4WSUzMWx9+tDJWoG
cF8IiY5dumJbM3CWD7izjDLdEnY3Q8AqCW61qONrR+jG1XTwpuAhIne5xCp9jzCiYlbK2xnBUESJ
4WFVhb6cP5mNCOGvAlBrG/YpWDz7u99aJDgDtIP3wDp/z0vavFKz4k1zEzThBfM5x7HpoN6iKTOT
ZJmRBBQTYwsxrxXbnwsr92caaXNgej5+/DBJ2kAY954iB1tub4dQIqnPWBVF18Q+7UACAw3dGHnZ
sOJRoL7PYtBdWCvlTMP9c8TjDii0XayIgcIr/iAy3nvDuPpRt+molNx4DCI+Do5SA/5qkt5Y2ZgC
HmBXq+WA6Ns7qimU5UWgBsdIwHzcgz1dMFOEYyMP3wiOuin8A+5hZc1p/QuPMDcE7C46nTS+/gPG
Mar1DIVoEj2C4xJgwOD+xSIDn2DxIL/3oofpGFTNOfqq0n/zSeQlScI3a2iZ8luLBuRafMzNbYwq
5dJ45K3Qnk7NkHdcDLLBHiw+nEhHvHPKig+LSfObPorLuk3KsWsBefghqHXd6ScKPLshF6MXZVsg
k4LbnwFB61pjIZG0CHJd4w33iVhFdFd/TfHYsTqA1sfuyYkJaLv6g/YjfbHDMq/V2B5aiO4d9a10
ulhVs9CDxYdNb8JyXnwos8l9/7kWnMnxY/0HN1AjOFojVdNujWSkRD3iMYJaiu3z5IoCv00vjBZW
SJys1hyOF+v1FpSopiQQnElnXPsUqZN08ggc+bLAKr92FK0Ixrp1qzCcC4y+6rR68+yw8hMhSthi
EIjPA711sUefOVzpHA789UnMMluSzIVo26qeiaS7qUdFiz9DEZL8qk2hPRTu9d1ysoUc+58fDtIc
jQCzAaldsxRMb26eKcjUG40TbtS4nDrYVG7q8QQF7zYv0y8I/y/cjBKIc7IJxy3znRxuiDaGPlr4
7SC/xTf/8GBf5jdUm4YceHo2QR7f0ZvgoBqbkCNAyRqYW5zpnJVP4JGekITqNMS/TQcBrC8TO2UJ
yycT3oyQLx4PyYVCWVpBfWZacgRsIwSCbESxiehkM9XDVannshQuL4cZuLQxCIPz+kvyDTfHnx+x
6DxyXEb3CpZwjLKVzuWgj0qjiX4qo6+1sNFHFo6gMhmFjKKH5Fux0Bg76Yv4+ZGbv7nf7+DbHZJo
JyQ+2JDCmkDZwb5M6aoH08SjOGDMqmESbOIwLRiH+AUy23TwykGDE/fcHwuyiKo7GQJvO8vYwiwW
f4oU4W1XcqsOhuEaJ8unuZQr1xldi4PnsIa4OWrBevNjF3UyNgYvun/XXWnEyzQxv0KCKZzi2/Fo
pahvJ5+bBC/trHlroXKNLiSB/m18dTQa0VBsAN8j0qLbqHMkEoRCVZALVg+hBkcD8qZQhzF/aCYt
EBFOWUinQL7K/bqGPK0GbqqnBE2cHic8QkKSjcuWqbFGSXJM4R1+KKhSYHxjj1gUlfcbWf0Yl95e
qzCIAVqE5JPwrQZvWEFqZR9TN2EGdoa4tH9fqmnol4cAkT/ZeByv0+kgKR/W04NUgVCWjx21IB7S
C7fLaE5MjqYMaxUIe8gyhQgi66GJsBgjLhG3Cv+iE5D5r315z1jeCVS2x4zvY2Zbm4daGaozblv2
4osWRRWRLQ0/1Jsy1UD3V2uAPDwB0pkwzd744GGQhp1N+CURV/bvy3S0hOeXQzcRgNlL/g7kFGgh
rHh0N6kSKD7p74yHK4/8D4cLSAZWpPmjJhwuuzrjAsjQ07BOGYbiMiuA2TZk3bmDa/3mwd4R7f6I
1CDi8JsZv5EsOU1h29tJ1Mmig9K5wQKyJo4e9wIyNxFrGf27JQ5hkfPa8KWrxZnk8auvXipptl+U
Qm3dkHbKU54ZduLJIeGN2gLY47DR8jBmV14t7KuhQ2PT9+UYf4g/AWnrP+aH7q3rePiKvsz8dx/T
t7eAq1J3nvuIExxY0yVbkyup9a/g5juXo8isryOTPaldZwTFwLPjSoIXiowVnlOB2l7lsgb7eqzs
rQvfxoKFrlimauk3ZpOFtNP87GFZWHh+NbURIl6TPIv26UPQfE2plYgeSTj4W8kK1lRPlo39yDao
z2dmXKv1d83j8TFqMFiNPMeFcEVxZb24mKJ6S3+cTxHiX+45mGNjvr2z1ryTguyu2xgSAXxXoRoI
oPvqA6U5sEICDbwnC3FjCxUDVRKyhLsydmtYh2Wnd7bRAs6ermU6hMsWCDF42/n47k3d1nfMe9DY
+tB5SEgNCaEyL8j65DMp5azYubw5xv759eaCdEwhMQvO8Y6LAli9n/dDI2uklHJlizOlsn3dmpeI
cys1JBfD1TxyLkgsQwl2c3lKUsyLLc7UhBVVaOZJMhW/LzufY1SQsFECm3emELYAYPIYls6C2sd8
K2C/egZXvSUpvkCg56Ud3NcrtfaD8IIn477blwZwPAQTQuSYhQCCqyX5vhEi2xIoBapjKR2X0xu4
OAw4ACPtLRe9hOoudqf1MjDjSFQ073EgPKvDc37WJUrETh0PaxdzHhwUceByfU0wQlVlDj8wLbqF
WwXdC3+aBZ6SGrjny6O2fuE/GtFZNaeOgixrLHy+gORMeSwfLXfpag/v5z3HyzUXINJUniq1MuUT
xChEpJwTugHqf33E0g/4danCdz+vFW4EMNy5FbLp7U7S7BTVn3VGDhP5+yDj2UAS/l2OzRYAvNMX
JbVPUyomKW0gMDLdU5YXVYw1zpZxzmuvOU52gYDrDrr6LywKtLq8OM2c+0KPmTyDzcE3QL28Wnc+
lNpkDW8YYekG3CF9RyeBSyGyq6bIhEkqdL97VE0nY8VZOMy8ZrfzD/xKco3HXMtyJlw0ohbsAK6A
bHMg7Q4ps6T/uDEg8bnv7lQzEslWpGAFMPC8fw9pFTxy/bygt7scHHx5r+1LV/TbezAXprLoZNlq
qmq93hG/umIz1q+mjfDYv5Wu+q5ebQVoeP9GP9S+yKQYfUd/pE8fZL+3CfV4ifveFlRPEL1QDdoQ
DPc7q6HA9uhHBwlrlWpk/+xJTmL9wVKmdr6dZ+F6DxSmlAQjPYBjraFYIH95XjnaKvG7tCgHSYEu
tbBCRJrthsryIbhYLLOe8HIHtLzbaovopUTjjWnJKW49Xd0hdQx9DaTCObYl7mCEUAQlFWfdB3VR
8Fxw2qzcDs0cEyZyHRNK7r/SDA+Y4ncCvEXfpVq/Oe8WHNGjg2sdLZQTHZDIQGdDrgU7alhTwSTF
m11eCJUZK6O0znPGdywIK6QfyXMNbLk4En9cXLECLoD6Ri7WtToOmffbojUwat+NTZBA87HNHuEZ
JPHza9/my+D08FMtZbLWDX60KmIRVxPySb1sxNIMmKrVG+JBfkGa2wKWXk6LjuFErX8Vv8DqGbiB
RyBUDnLYuYHIrUHqlMoGbH7cIcPof6/BD3GucAq3gqfwIwiHfdhO/PeffgG+VzOw67Gu3S51lDos
VHyIsIZP2vjAvrg4DtpL2OXs08tW3z/41ultJrUjS93H4MOmXXwEY+KKR9Shlo5X81RiiPnVdYr/
tp4Ev3pN4DWUoEUTqjsX2dopRVUP6rK/0D0k6mGK+qalSnEyRvrNSQLJQK/X1bVRruvmlSBoSnhb
2/gpaEXDxlkm77yLMiqBVFss/ctKwJ85uYTysq9gL9SGfA5E2HgeAvU0UyO3rLZ3bLMruNPghMnm
HSXG6Y0u1Cpy1YWKaF+J31JHfA5xbdCn/udjAfkqGKL2ZaWaYr4hlYLDg4plb+PmSzM1y70H/wbJ
WP/9WLHBUCaVDx0XG/OIK2LkvDJ57QJj/4dLbMUu6LLC/yNWAeINYSH9rY8VUfex1aijziixkNV2
WhmbugsK2FIJGYupCd1RcAH+QcnFKjdCYQkC1f5iA6oKDKukM6eqRrDweCCqRRtBzvJVzoPe7TKU
UgzZmRniC4oqEp/0Qhocs0UMHAAWvdQbLt7GzW6cfUtlo2fDmLZKce9TeAhqBY1UOkfvSc07ibdL
Y/btHAG/8bq7bBNw0C2ipwZEqvr8oc1P1BjEuxorm3U8SqyqnEiWOzMrd64Ffgsx+s854cyWg5tO
dka0EYM7f/pXUOgCa/LSvbmcAYXa9PQFrqayh7HYLnNEBeDFS+N4lWKZMc8mQan3MbiAV55Le98M
rYePyyudK/1ks8znbmOuKBV6lz5CAjil+H6VLydwdAC2JnVfJiELZzZ5+ZHge5E46xryzf4xMtvI
rl3YQRPJqu8+fSKjI1NDxSJo3bT+04QOhX4zwMtoYYimtrPMiegoLGHICpqZxlEW+o6rK+y24Qow
hc8ECxdvjhFJz8B01I2NVsGU7NIth6dd5de9SDCX/L2MKlz+E4jNBhbquTi/rF5KqjPVQGPekvrD
yJZooeUmWexUQAR0U0Wui/rGE4w0CpXazTi1q9y21x68yiI2ndXgGuW4ti0XAuG9bi2KYBqpzRyy
jMiHb48lLnQRtX5C74nVlYNZCnJbo6dsCWJHLbpu7aJh0MxJf6XcLjFD6nd7LU6Aus2ttARAWe/X
CA+fOBfx0GIO99dsKs5Jurs5j89OgVHx8sBbbtv6K1HL06YEdry7oBP/74yQ3xd5IiDpYosDGcUm
RHytdkZw8MH+v8mI+FvVo5Rmp3o4t/991fb0kog9L3gZQAG4nYN3FG4ZEpvwFYX1ZyfXIssnBxJU
0qTCFK1m1mh57+IrSVjTfKvraF+5mzivyKJhtg57OZp7v51Q8O2+bth3Mb0n4BH0VC9bl80GSa4s
LnQk4YlC8ezlQFEmxMM8s7KXhogQm81wdGmHotklLitKIGAuN0Y+3Eu14cRhEOUK4FB7y2+0GK7+
Ou8ulzpQGoL/uxfKDgAotB5tZOnIxSikJdVOYz1HZnKFaYMhcUZGBqMhi0DQEww6fIgZjSxI8f6n
ZvmhCqr5j2L6sR22KXLemQnC6wIxyheaENK5MxOjyl0iIT+pLIecSdfTWNAqEHtQSo4YrxHKMtnF
foGYrGhF/MqnZ3YHkn58nvcZoo/xZ0qDV3xxVSYi4Fush++Mq5JByIypT6M/PyNl/NMYTUlkzkYT
9mWeBHbezHvkIL2RQXBeXrS6mcyH97qCZUDrc9/pNb7UqL8RD7Ydee1DmLS7YifiQXMS6sHXp9ah
sHfmpGjv23pzp4KvVrBGwMAjpgP5aXJxSinkPlQWR0d0EQFU1p5I4loSCO1EHcQve/R+xA3haM1Y
Qva7Squ06c9LCi/aRfTAAaayQkG5dyQyLmwFmvtsMAPQPsq9hOcPC71tKhEuBqH+PVysAwet3QcM
n8qLEDuVoCgk8btFTlAX5BsHnGu4JWCR+IMHpi7RWVqaPU11phEh4cT797RBiVidJU7FuvLC2XnQ
2FrC+3NaPjCvniNqbCNA9gobl4yz1X3XYEzeROANpplNeEXup2gpHp62zHxVG6BuKaPB35fCmcT2
ZWM8C+PoO2Ov3fWSxRqHIrSjQc603IhI3tTKnNoWUdY/G2QkwvbI/1rPiM5U6loW0L/2o+1dWS3H
DVrv9Cbiq0QcbYJ1Rq8ilUAP6J/M2t03N/7sJMl7I+f3hUtT/eufn0u/GANvTKRKqMBi5rnkZ6K8
gKyMoHHt9QLz9Mw89EGTclrhwtJHV5UbZ27qE5j3shHwsnTtsh1SgXrhmRlMLoU7z8lOKw13vUXt
7oVaJfrLB+oYhpPckKEvFJqVR4pmWlX2c5U+j7NQwIwucZdgbVxm5jsYc2mXrAa6FvkpqDCZwd7l
sTSIWlkBK/bDl2iU/jgnCvm21ENaczFgfGQp4r4flqpDxFf2eB0w1dPsLOLvzDkDY+xXaZfcT+Rm
oBeHg/KgyPN7GFZYdeA80FEseJrmufY+lNiWNbY26A/gIcaXehaTbEOD4urkbC2FhLCoCvggxi84
+Kr/f1rTYSfRxE1lnHZvHhmXIXRED9PsJeaoJr8irYZCfyxDDGpGL5IYTMuzStGgfhBsfhtAqkkg
WkhD/VveWjN1hyCu1TEGgOTGknyY3RjfZMxl2PTAdm1mRphhXTYBCafUz3ffinK8LZvTr8M0zJCY
Z7AHYlflxrrxrcINO9N3xgX5Pxh1mLMdm+sKWCBvINi4eTftJO7TO5kLDyV1KqXTb2o7wTE+E/Mg
UUSpTRu/sGlq4vSXWjzUFxaHDr7h8/Owy9YqOjlGtTAQULqYmY9nclum6a6n7xTKZSMDo+NAECHm
zLCSfGJcSDw2P+DY7oQ3JCWXLP33Vbu3R0+ziWAhXHrBoqnKNJXyYVdirC8PXj11NIb47Zso1oPM
WCy8I/UAu/xYn/Enc+KZ9xmKlbXr1h7XAW6OQMaWnZxS9B6UQdJYMmH4UgY/v94twA93Bi1Ma0xp
sbvF6TU5nBksPjKJqrXpMn93gB3di2KYx0qYmzFDjBhHgyzEpMIWlWgTToyfg94hLffui80k4Fyd
DTnFQM4FnmJnh7tm7LE4h5tfBvsHlauD6yvfvjHZDY1Ai+DcfScouVqv7j22hrRiEVxbHGMqdtLc
CnsDHy4LxNZ9tncCJ+LicjnUgCaNPN2B+uKx7kV8zfeGY2xmp8kfm2pAza7x5w/WKVxf8XrnGnZi
mGQ+mKCw7g901A1k876ZHg/aPcE27lb9DE8i4C7958WfXMzg1Bz+Gw+UCXoShXlzRhEO+++Prxil
gdF4xFEulks/RKjdV5UaNgOxgbMRn+xHN+tgjgjLNof2/QK9sedgrL+w+yGr4N/6AnMiFE565C5V
HGCzswZ256aawSWYJJnnctYeb30vKunGarKhin3ElIjVoFeopapywtjW/rfRSh7D3SmD7wsSt3hB
So2AhgzX7dhdT3NFyOmkMwbs6Rf0I+yZlqvqH7EXANb0k9Z71vHZsUO7IK/Ir8OIduFjUcJgFa70
arv2zvtdF//4h3pULkZa0iFF2EpyimaN1vQLVJcCXOUfq+yvT+PVQvpJU/UCGzxqeeyXm+fhJr7I
Yrignmmut1+894OJLbzY/0JcuU5BqE11+N9FRqpNnYozVqNRvwS9Es2CAkaMTajF8H+cOLA6BWvY
7zgvZgAtfCS3+hfkQv9VqGGT+Ygk89I4pTS2tSeuYgeY+Nu2RUYW+4Xwss7WeeWSIDHoRNRed7qQ
CNd7I+J+WA5988IWBXftxNztOliQUeSItwJ54GZvMvf8IomnEWnLzjudt5GfYs7iB/WVhnsHnEEC
sPAWadmbBJwbUl+sBGkEvH7qGw+8tH5CFRzxhYlDjzJOyXJZxfu5SwrZ62FnUjSsg9ZA4gQuqNmK
c+SOOMRjJ7jdXPPvtYLCry7nm9RfW7J6zO6LkC4nb10N3gtDvx5OrYjqS/CfeuvVXX7a80Er0YPB
yvNR2RcIiGlKiviUwueZ/n4v0vwa6Z02ts/kP5mJi0IOyg+H/trF1su5UAbVYdctX4UCVxaYYBm/
RUhpUFHADAktBpM+rqUDcnJe8YQopCIwAeNNSMalga5jWpiXYPwPJyRx0/AVgnso46I8i/AwTLb+
dUH3obnxIs9cP1RQF5e9vob+fKGv6llLZB6KS8sxTU/rGvw7yeKqGSSe01G85bc2UergtrxaNqH9
oE7ffMd2T6Ga0SvvqQjbc38VWdw4eLl2EZwEHTuILIzjw1dWsZyhcSY8lCUmYHAv8CZHtUvFH2ML
CRfjQF0fg7Vae8NhfExTfHLcxG0T7N3yfPii+FaOBLF4qDU7mmuzjH4s806j5Q3YULXnkoNzjInL
ItLJi254WqXfTcYUwSKUME6urGpOMht/r189XlCbdL8/ScGO8El2vlaAvd/R7bjNsLX+PnrCOBLQ
ezQgKEGNFSsQqOYmnCMwNX7L+gPxFl5ho9TlSPwVSwwQzzUbJiQUGDpmlddJyyRSubtb5r04VDdT
DrYQbHUcS0szyOHL+q1eGS3n1lKpqT2um6UqlKpsdiPyeg3huZ405DN7jd2+9HFjbgC7jdwAabCQ
6Yj8ihbMG/qcJ0vw/bNJAKcvtVvmj+dr+OEi2SbRZpa65RWPq6rkZFAbhylMKPxfLBkITICUWhA1
rSHe+oOc8twVxX4uRHxPo7vi0sATxf+qCSTox2gSM/hzPXlNwAcqhEX696x5ll651FMiz9N5KFt/
yOCvPwR4c+Ig4WfOAZHsK40zmth+Z8m9838VkeBPMRQWsxtZVJc9wKatV2xVjP2Op+AIurYSU1Xi
SZBokuOlGuKgxPIjWv47cyvejeX8piUsPYywwZ2Xyxbl1PNffo/+Lfv3Y7Afv9McZ89NcbeN4H1o
wzFlOUe2qApsQ4rg5YmD7eHT3hZPOOpC20xwTHzJvrBhSbV7j0w4IjHr+bsgmi3hhnBhdylQzOIY
xPozdFaiCvvnNH+6+YI3jC6x5RctK2KTI35eSVy2vYuJTCubE433SYbM2bwRnCj9as/qDstg/Kiw
g7szCkjW3OJFh1FxJAGqEFVVuEzajtd2TlVO/RdoGEJgNuEsiW94hhvZmeqBUvYpkJsuuMzFtmhY
SEMnzEz6YsihJWojUEuGY/XQpjvFo1pa3qnQnnHSNr/6ZoWrDGi2DZJd1sjiaEedAfgZpmK+h4fh
rCmkjRg5QIT0IL9KS7dvsZ7MzQglVNgMpFejPOso8XE49k/X2FVMR8+YLN+b0uDeNkBrIbTcGSvG
dG/IsQwrqgHDXWgVr00p6Vzb6g0pJn27kbCnR4+24hH+bc3HjuGo5c/Qh2m0Wmo3drb6xXtGV7wC
t+dpg1Cavd07AOXeai7iPho6ewSy78V0B1oWVVDq1WbKwYrG+t9tKBZf3v2v4tvl495ybG/sxv4F
ohtq05YzeSzcEPQCQiP+VCw3gbVfo0VIUOSgiFfKAeT+VIiXzAHjiDXWO8gnRx82+gLSKQRAzZAC
03swrwNMsBj2zeRuMZOG3Uc6VE+7FXbGFlNMdoHHBUMo/NNFrHqpbAaOz4BLma2Clm0AjEwW/iw+
y7W9JUhFMq+tVw4pAHNHXj2oQvwVxyvg/vvhp6aaT6tPPQ29q7IUttlGXk3pjztB8V23fDYjxlAH
9tpCqTOSYMO18uly2mrvJn5UCqr9HiFcL0h4bVVhcwQ85rVcpZOhTPYGAEVTXPxTE0YBKLz3iPHz
Y3zVHKkQYYv2i6Q5jhs8/5/KwAGgwfBRwq3lIwj0rmnyWiIt9Ocx09lDCzIvklRFmdaVLoUVvES4
0W8ecK1XN9BYheDsfJkWR+CfaH7uJcEc2xVT3+nvpDILP2DZwACkkJjld99HmFAU7P4eS+hIXNNF
kBMvKc5G3IvY2Ed8tHLMxUom2uQARN9NvE2DAJbzXmbiBI/6XW9i/AtZP+YEz1/XSH1X3WQp4tPs
4JzmjYemEipW/K56T5mGzN0Mcu4AqqkHvpX9es4aF0mVEPqWiAFC/YareNohIzRoxjTCTFXgqwVX
a9M96b8erXUuAkJ3+NN5C2tPm4u6ToAk/vel4XgQAei1V6qFwGmhONZy2LtHG5mJ9sKt5lq/LeHf
muoe4meMablrh0Yz8zcxODbdxRvXtFP31eCymSc3f112EHMy9p6CWQxwlgf+QgQgukH4F+SqbVWw
+evYrs0Uwz6stgPDurwKbYejEySkmkBAi6QL3RzJIWrhUSDIBbJVAgRGQl1DcMr9r+ehUVX2KsAL
jpZcNE72yDL7Y0h65mBD6YQHcUApMUfI2+cMpq6EmOxACKTmets7gD+53U4561BpYXC2zQ/Jl+o9
bT4QEf4ItDhu94xj74a+GcG9JbElpuCCDa0tIpsvpbU+tbNSK/r81PxOp1p6jwSiBNN/daNvsb+9
iYW4x9erkW/F3kcMokXszXj875a600e9GlvAnxQWntukAtY9V9gc5uoKAio/mUE1676+R0t8Yzi5
MU/mIfdUSEQ6ooOX203rdrH60aDzMwkq+9iWBxp8jlrwE/tJuxixPqemhH+tfyQXBq20FWCRN1iM
YD6awo6u8rzssFMAmoMr01fv+DUhBCLJHGxkXZv/RUgooGKhIWfcCeGMIfoVyen+BBu/5qCIy7gc
ld/VmakcCmKrBsNxHaFLUHjtmUSn6DGxzwd+SqT3NYjgTJfWFZyQvaWIYGZPahTKDY8pfn13hR52
0NSY+UoECiBDdDOmrhGE6DvFukzdz9dZbXVh5VFfxomvlRnOqfuNpvNKODY+u1jFRCrKG4MZ/Mh6
Hu0elz0MHnjRiT4osFbsM6NROnZEsntLInwntd0pCjcslyKgf7pKXFjWg48Dgu46bQJlAHjN6kZS
sxtkG5BwMvjbV13VTRprOeh6lQaLxjQ5+wGcffODOKtgFM1NtgStr+FKfzgHDFrwVIqVFexrjhPn
cLLgZ3jwehNZhVa2hGfvRd2mKxc2DVDeU/XNJuaRBmjx6yJebys5jIbtyHbeZSs/geFM+RxdwW6I
WMw4KoYj00MBkycX7VJic47sv/8WYyCNn3ivVNhz4ry9YBEajY9fAjWRFYzgmw2kCGQBGonYhp+O
/JIN0QbTlinF3gE/9WjPa3xTK9KViBODTVvuD5BMdPjz3njUlRhpGjMUs9XcB1r+s5ee1z4ECEEM
mwYgUcqDzfpZEu3PimmLuafqA9Z6cvCCNJ+ZXEw5tHx0HSnOq8ubg/QNxJgr5+gKQZbNOsqnPzL4
2kTZSz1BsVLFT3wDOSeno2oJ5+oaHNIyOcBuqFXu8L710uVxyLyBce3MwXd7xJ46ewm25fv/y+o5
OhDB9sNapBFxDphnSN8K3PYpt/d0MLwmbn1q9+tCvSKNkFKL45dnadybGcfID4/89OdTQ2eT8XQZ
C2uyfvXitb5GdW/miXG0/ZUzuVCAiCF84A1EMw4/tx/pxx87S82oPR4QdVwARrn44E/9lpySM6IZ
fBlfPSzBMf5c27xmvbRHw9fxlvik5+Q/UQx2GPUIHRJ+PYGpRalg+sw3J0N4IIVbCPDIfRRYoUOn
sopzrP1dBJMOUEXe5ySHgY5QNTioC5jbQKYB2WgX5ZSj4kiqLMIhFrYrhAjLvmX0OpP79F2ZMPxC
FY1YkUzB8/GVKfDvPRFXequfyXi0ZX9J8THI6/32zaDXqDZAf3vfjiEeiv0MboOlAq5ZzGRtvn1+
GOHieVpkHJ/ZL2M4bOJY3emRPbm+LeIxIiCN/PJ0MCO5Uqp/M2jukOMXTfBxa0LVT2kFS+zErR0u
3Kt2TOJMAxMSTX1pHWRtMm8OfI7nckxAYpbkISyiknqTxVg2EUpwsCPZUVsGDaTS3L+9+ym2BocF
4pjHLDPJzqZMlEZNT0d+YuqoIHWGQlC9f3I+P0ovSXhRQpUk27P7rLrob0yfBr5awoGMjMq1T+QK
LpVddnzLhZqTMa4rPrhfHtYC/gAq47CcwCnXxKW56ZxJeWlctOyeZ+1jKzmV7OGiBzYMbosB58wd
lRSTMg+PK4/y0UdevQx01NlRDIhPAl8jiAz+jfW8J7JjGvlHkryAWX3oE7+id8lsZMBUsjPwGuwN
FS+dJWv8iqhB97JZln+lA2+kBN/xNjyz9G0u4XfcAazhnhLONX/1V04592yHWSmNBrkCZ2JWSOtF
lH59d796TXYMWvu2CcFpNgwGDO0wBkbzfbt5pW73192Sr4+dnNAhleW3rouzbjcgMUAuQYwtkQsQ
xV4S5BYRukGN6aMP9XCbsu683UyN5bVh/PAL/G0Ra7CYfQX4/0thRqr2n6BZPNRHW6MHmmOgxZ+/
aI8TyThEResMXWTstT/vAN0D5zEDOinxcwPZ5viLiClbSj5huWeuqzBtak8MrByHDnNTJjnelPS7
XDFEmpxr5xFtooJzZThSPSYOEqP7vjoKP6xdgluPV+D0nI1vV6sjz9E6UizvjAI0TAXHxek6FKiv
xIPV5NkwfmPrZsYdEgFcYalALNPfmNcD6zfhEWsB6QqX427OqrMsIgiugJzUlefTjtJ9/f/SR3Qj
AbAfW129fhb9T+E/3eRC153Ev2Di18ujE3703yVa94auADPo5w0VB+5JfDcarM+VqZyYPqwjQq4n
Pepg/bDY1Z0uDgRmpg3dCxX/ID0LjKG7G+CjfnQDwGCVWbm6Ljd5lSawOmSOloaVTEFnBSnS/l6+
VkyUuWGN9YJ3eN9lHtoUw4EG3AYVx0mSfKN0C0HZEzXEvIeTrs2qQPFa7XZVutByplcluKWk4ogr
jdOab3Sj19MkxsYT/p/WUHJPyhAUsP5HIQFQz7mDm4HgA+2JdXph1ld69hJwR34nHhvRUIeV0fhb
C8RO3P9ytMqTOL80anvd2aLJxrbbXkNynlKC55G/c0Kwio/F8+yXieyRp74y7/zTOItJWpUlhICN
azuivNtvnGnhJo241vdWCHouSBKZlObKlBdvC3u66SaFZvr9rlerPO7Ap2yimMiy+1zTJW3ZtgJ9
XS3YqYIIvVbz8/0XjL1Id99PaBnVIT/SiokH3sK1WxppRlQgb7GsrE7f2eR5DnYEOnDFZZkIhcyP
aJ7WYzXHwC1nLQiS5rayXRb/zj3Bf+Qw4N09C0FrBRWFq+DaSivpZDaXMK7blm3YSTm9bjyhU8cb
Gndusse1+jvpo07Lv3GaNu19bR90ZjxKvePMbAsq3h4POKIaXum03gUx7VRcQR3S3HUjXXLSPeth
YpggH9H/iYW/hFLRIzQSf/dk2cDnCcnP9dr7KQYjwZlTjtHT5Ne0zYzo2xdMYW14bate4YA06UVx
FXFfIQw1+rT+84nqe9bO8SCNWe+j0NiAuH/F4j6jin1tXr4j9YLcKwAnrDtBG+CsDYrWs0LQbIwH
zOrhs3wniSogjHG82sT1wBcAMlHtwTdFagyyqCfPg2DMqFt7U7ctiP+zBtjWAwnR4QbejwuZzlCZ
LNL/KKOHqr9S+/eY8YZ2eqJitCVpa26LKQfLWFUFKl6GxsQ0eLk1hoExuJ16Ul4hAnIa83fveFlT
kS1lFQS5Sl0hqCRctGjRCUDwViKdPfLyolk16sUFZKbEUyj6CkPD7vHNepNmrVV1Fv/fuAY8c4fS
4pKpZfCA6wXDCeymQh9Exs/SipELkYOBzBluRQd5R2/srtj817mmT5Z1QxD9p4c9IekMdd3PdriA
7ix7lwI02J+xTkJ2oJnEk152GUEu+zqyut3m9i7bfRl8e47uVLe+8p5d00y4ZDgg5jQDttvU2MQE
nvY1yPMr+vUBse8hYgUeG4EEFVKCep3aLZaHgJqcLV2GkSUfL8mUr/p1B0+IWUUw0VRM4RkVbx6m
K6O73LulFgoCifzT0iIgtZSP/9HEyhtqfO1vaY2k5XUDQ6dwhmtqKEJ973tiNi2SK6HdgvN58u6j
66xAgF8NETnDW3uQXJryBmh0EnykKbu7TdwiCcK/E3TTmhu3q8q9wsX/n9ZegPRqwni1gakuULz7
WSthMRhZhKd9w0EwBco+KB2pRTwBHSM/nX7sQJLrukKelaagXvM6VNsahd175sZZQSO3fEx3aA1x
zY1w989ETOMCfy8/5Z2b/1TOZC5Unv0937UXmx7S43bq8p2zCBv0Nn1keQHG1RIGoQGE99RIelEk
uvqkSKD+Qk7o+PGdqUCIbX/iXvr+UijG+ib0n07j91on3dinDigxG+NeX1Q1Pub9XenlFwr7FiMi
JQGBu2EUo2idblcTn8ALn8eK7HJbznFVq02sE7oJsAdvgBexvZsYQmKk3nAraU4og74hQjoaD5kP
hh1uxVGQlcJuTtfO7Qsfuy2MqYQJLhz9piTVAUUcNvXclFkmcm0zf9wwI5Qo01rzFaScrPnJBaP9
WtFcpHgo2ndR1IfM5YIZmAgvJchUDgk04RogZbfqH/KcpmZ9Ah2RiK4nAPAqzk+droGXNnInqqgR
Rsfylt5jkgecfGuItfiWj/FJvx4Xjvk+rzDK2J4Xk41wSjH7JF6+EWAkcHvOnSSw6EAdl+ZJQGMY
EnLjMp8GclgWHoU8SqATCtYZ42ErAIpansd77dkMX2rvoly08AWuSC2Kk8Yfj77sH6G8VqaUkuR8
CE5599Mtr7fx26GEdsq7cLh4J44x3BtGPZVFu70OtToerWd0qqsB+i2XFhCEMGlaXS+w0GdgxQAB
6YM+Hc14uJk/E+zkXVi+DYdGQyCvvHMlXObrJ73+f8dee/ECZjUxa0fVYEcIqEtuDNiOTnJiehG3
zMipRgVHIctCIQf2etFQqW5/h5yFkad5fy9c7/s7sRCUEHk8Cxt9kjEkGBUV9f64McDAIc/XZ12L
5LejTbQhyO3KO+2FqgfkbIxjySIZDzDg8dX4i4Tw65p37PrmDpB3IWzORVJ0YuMD43XtpuRMXAFq
hs7BIvc3O1HnXduRtSwlFzBEI+AlkgZ7nagoTLw+2x0USopdbfuEXI6LAWXmOjUmggpdbqTrIGzD
NouSbo6hytuZGz2JMkVQ1PqLXWkIjNAMjjU5PMC7cmKNiUIqZe0DckzPywxsz/mdSsCEniryO5ex
yGrpXw4OKiico0nqZVH8aIJfdNudrdeMtjSJvSM0q6iHoKg/+3RO8rL/nNfrLMmgROe4+6YITo4b
xSHTqWF5fg3Z5b4ZdO3EqEp3frnACN9F3nKM0y2VDDiT+RYRXAjcDHIXUn9inw/ZBPH4WTQYavNY
abNtYMek4PTctDIWz6Pb/sdaK1UsGu//p5RzidivxkAA6Ml7TaWfu9qiHe0dwn/AIoj/26Uan0cB
ks3p8MeVjKdY1EYjsDyw3XPWBVYyj6X2IprPatH4yHwRgpwfEHNx+GHMXPAV34sJtN6g5WoPeqfX
lvn7w/LB6W8pXH9r3khXGNi36l2Cg4EfUGUgs/FwYcKfzccKWkOJvq5Dy5w7EYChhi06TMYkGa3j
waajyaceu9DSh4uC1pYYRjJUZHiOT6YaP+i11LcCGCuMS8g2lozVtj+LFd7XFsfMesrcGfo9HpZg
H3iUKVtVJuYBZV0grhaW+l8KRCoxmSzjzEklIMjuFpzS7CUmoqB5KvvcSRyIOsgZC2vFIN3MaaBm
/4ceD35dQsD+dYTHhonak0K8ai6KExfxqrLh4Ge/zSKkRHsQkT44EJGC25SCOjq93hs3w/qpJOV6
Zm5I/943AvFlBIgY13e46PKRqnBVjpAaGq4mI8odgMGrSkRbxO6SJ9spFG46HB+T/ja2hwcP38Yf
y23PJIotPXkUOLxnnCJBhzMmSYKZ+5Rl6Tte1UKXEy0HbAuI7SM2LVikQcO7Y0b11K2uEzJGvfcn
MlZM9ZE5tGmgFK8Nk+Oo7teN03Dn2JHwXmTXSy5JsOgWbUVRRHyktuT25jnBisE8OLs/rg5bfjGm
oGfIEkaWd753tne+FKa89bSmRAuEruxnS0sY4lfxoJqZzWPOkomWVCpsZlQF7sn9GJv2tdb8Kdl3
KLgs9p7VWFfLTzGbef+RVmWxkfRY+d5w3hpf8uSpAWlvR+BGha0ERVWvII6QGu8/0EBfhxmZCwts
psh1gVq8KOQguUMasifH6k2KZ2/dPuG2wnDWHGJ+IBUwlHBpfzO7xnz2N7IddbqhuYdxBRJjEhB/
sGj9sfRl67bRc3g8KIffLrKXcFf4ONAwoU2ZWAggegowNhLZedvmTlkMX4F4bnp+Rc2Ft40apONb
TTGQ0iypK7S9aRKn40OL5P/ZiFDrT0QV8wzhb3F9GeXK4vKCpFt+QZn4rhuExetG2KzzI0dkWiL2
Mf1segWS+1USBAmcs/hKAxo0XnI7TtBvAlD8lmvo9ablJk7z5nQYWUVmI/FclA3syrSTEVXPWTWz
VG+c0zRW+oSn40w2oPjGf2ZixzH3DrCUWagBORu5AIirm755TqEpjBbh+8GG1+ddd74VY8NL9z3Q
TNXHpZOIFDyt+S0AKMwsrTwqY29cz9N5lQsts8KbFTRj4Anhi3/UO/lSgRvVaOEkTEVqFuMZgtEf
BeJCbi0jlz4xiJGvdtt9eFcQORLk05xPGps8Ub6v3JE+ee8p8PZlOPnxOBElJqWeP2YCLHQf/CzJ
GlAy/Ws9Yb4ylD+8h5CF9AZORXxOYQX8B29YolZSbeRpanE3x0X5R10rKEPUB52c7V/pi9e+qr9Y
9e+la8WVQ86c5cEtpvVovg+5YTOk3cyCYBMjfsSO1S47D7L6DowfDAXRaRtQGzKHOSIyVHnXAP20
fxAmQFqtb3UCwMZdyYY0eL7l2GTHSX9Dr3kaX3NWAawzLjYLTfcGrBy2E4ml8KnRN0k2OXU+nuR6
yAoQ4qerZKc+fE6r8U7KHnVJ91k5HGgI5y00qlMGgDEdUqjrspJltlpx4slj9vHaEFZwb85hbpno
ABvPQw2H+0MbmLtETZaG5xvjXcJs1mH6vAY8KxlF7ZQCl8/ksFFqzm/sg5Jvg+8GqoXuPqAD8s60
06kOnQpfmYyElvUq9KH3woSn2EVdTvcUaXu0PR4p1DO9VS2/q0aEQT2uKCKnYs5UYwTk6a08LJP1
czX7c09l7L8obu7kkbo325LPiW/+nvujBiGrfOirm0PMEMdeDxDzy7X/+K09SRKdq0mt9G9Ji8/B
9OvlthSVKIVDS8Ldko8zSV06MnvIIKKEbgnsz8mcRwCsL5j49COghROaHE/7qRDVhe2eX6oll5Wl
gwZtZUgyQqzYXCPBMGsJyhv0rOJNovqAvMVeHCEUkRxZn6y5BzqQorJqXMZoWmXBhDQhvl4QdZ2m
WOmgSz9N6pOtMWoE6VJyHxBRK65ieHOPK4X+NBMYxIGhf/DMfAx6BxnS1FBJULtc5oDn2rcsZs/T
tJEV98xsg6w5fU9Yl/EIdXMD8wDCeL09ilg4wPayscVfzMy+xF0GZCBYxG11F/MA1CBlRX0r9qBF
MGRVpzWJEMM9qI8CSihBt7XTs5qJIZ2NuG7/1xR9vkKrCNZ/tOr34E4bNhI1sn9XIrG/L0TP8tl9
gVZT4SMcjQKkUqVmFjvGrp7oWPz9UIE0rktNh7VJ63Fi09q4imwCgloKPM+BBIveW3Ne9heNBUt4
+j//blHX9+jVLDvu6l+gNxcFFiOIoNjiCAb3NqNsuc3O54Ewg87t0pKhxyA5uT8EInUimKxzvxEz
GHzDqTjH6d9v9efL7MQjwNdEaRM0dJVYirfb4t7qMHcXFGnI4+FmxU0B8lbLIO2WnYJfIIrarCRJ
g7KA4930xS2Z/fUGwN+qeuMHzZca6kWnJulT8/npmqBWXNauyw7BLFb2NbZbJJgAH8sOy9eUx7Xq
eJ3xPwx8r9BMWcyP35EOd9S5+GbdR4UWW5+uemjEbiWuF4q+c+H3ZewWTqW4M990Pe9o9LSABBsu
cQo8bo1aW1MBXD2C28kf9Kfmelj6bZ1ZZ1i3TzgLI2mC6QzJbwdTYuMZ5Yt0v7u/uwGkOJgCeum6
b2dghiFaK0Zn8q618+cA4mQC11BuFA/SwFlQj78G5tZEPnDtuq0ZcbIbr1YpSD6baDZ+zvGc1781
pkeoYwD6iCqVFChsqsrrnR71sUVKPRF1XMGGkSLTQmndlggREsoUyiSVskny6f95HJTUzkNnMWdg
wH6TdQhRHK6lCEWxGDMSAh/ZH4Z7PMy5y73LX6Pfj/AZ/XqIzrIDQrhWbuuRFtQPzVPFp3jyCYEE
A+D2vpXwGltIt9+qkw1areGuKznyLoV81ux9CE3lHBVhkUFqIqi4eQKpY+51BscP+vZ1EkvZMS+a
Z0/cnL3C//3wkDdwkCKnjeexP0m4q9N3sZzxi5lNit66bzOLk+0LROfWeKJjpi9VgxHxgnG+QrLR
jkr0znvTWrqb5qZpHVrX+glJhZe0/wEaELpqGRTNA5erPV7c30WEhn+W+QAG0d5FBFPqbuLkRzaU
aVDL2yjsoYzSSCiMeMW2wH+pI0j9WhNijwNZY6es5WDUiAL3pGap9gf+o3fr/GEN3p+caTYkEwe0
XnamxYJPo1zYJCEqpiUID8RfiyXDBMs3BZoVyArtagnQ3EZNQKBH8/S4y7BTV+361uUQLI3ha2lb
Si/E6zyrNrvYvOUKheIgVxBQ+FYZ3DJPvKqhtma8bTZvRNnRRBs6aWxD8e2jZHuJtaDeWQrYyGtc
u3BDc5yf4LsoeIpcKH4nlnKyyh9O7NmLpSkRetA2cBGavR2dSg7Iy7panWCLzeYmOYu3sQe02i4c
BqMWCuc0ijK3PdlGo9VAaOxlkjQ8BZCSgq/krGtoVv5GwheN9sWXjACWnvtfUkSQ7gkfRQGcncto
5b9HYYPkZJQV/fH7j7QawMp5A0C/fq4L4KjRFU71YPislWGarQnWK2tzcMqvlVxCBEqeXpsEnVLb
Q2V7uvAoX/XdZJ08u1ueOu237wOc8FmQPcK249z7YgLmoJAeg42PAqIlDX3vkkXfDwgM8dhkYpjc
pRNdwmu3JgWITP7pGk2aBrd4al+Vq+lTarbtGwAR22N/gL6ZiRYD/Xe6xHV4C3iPDuwr35OcXC5i
lRgfhqq5aNldzMR9rA+NEyRMvdElQ/pjTTbYMGYw4jJ7Z6V+o/ui16wB7pkGlxUpgHgGk3YCpfNz
MhN/XRAG7zpvTvkq5zd5dSBSxv38MsEH6Kt7S6ukemGwZZ0BfqF0TJmXB+m2YdCkHXo9h0ogo7bb
SBWp3RrAuFZKJbOTJ2xCsPfmgaI67fXVpjJMjMOIAh390qucR6szC72tFSnCqLIjTXprLWtDy/0A
5qsxA+gx2A83O+EA8PgVH1xcTSbvYb8+uM1GNmUOteXcP9YxceEZPXTkfHTiKSbdyINlOKBGkMAC
R6t4lT1zhdnRoCJClzV+ZCmSKokFeqaUdDnxZlsjdNM8PZ6cBuzeHI8Vp+y4fkHBpjX5EvpU028O
eHDocZ5xD6Lk8LYV7acL9Z8+665vOGWFvIen6PBIooP4CbuCNgpTdDw9YNUfkUhx6xIkzipQDD1L
LaKgwasdO96YyjfdjZ5oWOUJIADDkGn12dOoRge9qRxcsmYtlh8KunYmix3IbZpqKa6TR6kNlBuF
vLaPKLQ2NvQC4ghJlz+KrNdhFhvCYE+4YeUU9kK7yVYJ4A5oTcgEvRQmmhxDi/USoDmcYjFO9F8g
FXIx5mQ0zDFN96t3FCU17JPo91Vwcc1vtbclctT58VDrJvWdv3NK/qutfZotJEqbWE7AsQiy4GV/
EgHtz2QURw8EtLEa4et2s98UhU+C+ycGokUrimTOPnV7VzlksIbYdbqYkYpX6JZtdpTPypvCzSMf
Hyn4fOS86Mt7yfME18hhFB3Khs6srj5wy+cR4ob6t32Ek5irizOIZs7auKkR5WKHBrC55VtYs+D2
TfA7R7284atsH7QPVBs1JCLcMlIRWlL2L0Z2904WqbBz7/VEDermSAwHOUWFmgKH3lrc4JGcCLqb
NS/D8yiD+UpP5fpB3MyeKXtAUHM3ZH5MuzxK481choxLhX1urK/6sF7BzR9zvYYT+fQoF/VBzzIH
orGEhajKQDiHT2BwZLZIE2ltJqmy+7ecl9p8HcS74X//5T0rcGmYwvAfkt2l6ZcQ9XIwzzRjLos2
Y1omyH/8QmhOcYdL2tfJRHSE6Niv4Ymj1Groxt817VLitiGlbvi1t8GdVTO14R5xEpRskUQOH+Zt
K5FqBUiXtsqZU63PxQnub26YSW0cYZFLLfJpAprZw8EK9A8gc5gxB2iR0XfS16utXvMuIjYTQKpn
wCw04t6W6DD3uLQAhQQ0HJotKFfHFja0YYVQ8g4y9xY8aLFNidd8sk8lF5VWrFh8pHA4Y4OKRVrY
to/V8XYaZvyr414Wu5LiiZSzh9Qc4wxKe7kNv7h5JOVoW2q2T4xyddod5XeHjSy2W8iay5rSRPh8
L8zAec+bR/b8IW49CbEAN1AnZfiyiBu/S3Yme7n9N8L3ssENnvckXt/EWREaoSg1Jt/LhtduZa3B
djx+1HfuXck8EdTmNA6+f+ynksYvJthKE2/kFzWs8crhzZmn4XIcorASC0T5LfXGlXlhqFFI0l7v
zXx+bbVHA/TTREVebTzDmsFjA81Sg6I786JfPTPmm9YAnJsxC9jWnnY9dupxHqiDnlk3SSCz7U9R
uHW8MN/3XvULZkZ/QFxysYbHUWIOOloJ/HAcpnSAsYTFWu7KMEcdMICyzHEUG4egnIo0qFZZ1pEl
D3GeRqV5fegTyARnbeubLaK0eXMR0MConKQwTL1k1AWs/nmiRH6PSqS2+Q7IlbyHpeTha92hGTIf
t0enazXB2Dl8MYfx+GU6Ylo7XA9HfwW6xxmBnNYrXPqow5dCXoq6V6tpBOCUvOAvYHhZnEBFjXez
YfVDx7CaSVozQhclhoXOMFXDYZFP3+6yu35fBA952Eh2l2Hegon2vqFq2PbKzZlRjbbOnUs1ZFdN
MXOkhyJeVBULTAGmP/5mh31N/tmkvP9JoH9ioq9epjlhDKy+e/ZRx4CUoSX5LEuS+8uJ/V9CPi1Y
wx+vbufu4bjX/TLnxfgH3GI28GgTdjgMo6nxngORNMRiaykAIuj1yL81v6Psez+tHZxZWrJiDL4b
S9zcdQcb/2jGum6o1KY+PyBr38nJdqZnningx8fJvZKnuR4hum5SADDAApPWDX/glRkOA8GPaLzS
9TiU71gSLBW7vLAucm9mZeXsirPX7TsMouaHTXEPzm42S52gJAPdBtUmDGI8QVTLr/54zChVkUWP
mI9bV+HxbR5u1rvFZv6NdU4kcy3W3KL5tWziPF2ac3OnHbFKBNFA3uDAG85jFYUABIvlOJV4B6i4
8AQJWhqo9xD3QPaqP7U/dNg/ZVfbh7pvcg4nUfsaw5Lu/yvomrwQvd7ldko+7mk8CwGdW6/uKP9r
nFa7CtXSR61ErC2zlFKGbh1zRax5EQEUXJzHyUGwxTmldl227W3a2uDvc+vaUr8KRGgiSpeF0tr8
1vMypTzBFFjAzFrQi5EnYtg7vZns7lcueIEzr1lJ1kbxETYHduaDP6YeLmeZS+TBznCEz8vpPNAC
yBwshIk/DyLlRUeE3/lS1nYOBqP9kwag0BH9i+G8WFdj3BkP62kIriu2lq/qG82ZDURqMvDyXcG6
StzLWX0aWmGTvVGdmaJA0IuJOnYeEBZx9iuMzTtZ2QJOtN7OfRwM6icURyDR39V7Qs7yJROPj5xW
qgH+bElsO6buVcH3M1LsNSJD6hLlEOzxD7z9ffcpa/VGIh0NMqW2QAAyCZ99H6GG3vxHlZoZdNXE
12pEkjj9NVGAoc6c84vHgVbZ7Qj9aUk73924B0jjrkwnUr/SfVQmSIs2f/GlU28QgFcyAfV0WDQY
HqOKu7lN+4KrCrY87sRjcYQBeeXOFoZymggLi7IgWDbnLitiVYbNTllLFzmbwpzv7Nn2Flov2K7Q
Y13pqWZxXlbi8p0g1a/QowW8QLlWmLHCczsbJ72Tb+ieaKzycAFx03FWAkxRv/QM4YRRAEGbBhdu
ArPyd4nRR310TK6BN/937bt9kk5dZnsEIV8U4YvUQigQRrPNzmmIipxD7V/hvp4CWsmIzgX5r19C
y8dd+ladK9YVBp70Z/h9aQ/goF9DXVTmTZe/wabwc3KzzEswX9cL2JwPVCcOIiRb4PvDjYbWcbot
KTgBMTQeAwMvR18sjQgtCwR5ETY7hByg9+tJrE/JhNxsFCIncgjcLA9L54f9O59+Q7DI+h1umi6n
E4ZkO415yWeb4Qe8Gt8TM547NwcjJzfFzYIcI4OGADvCQ1uyK9X7CDaBdIEGY1BDKuBFmEO1E6gj
VA31fvIq49pN5UV9KgvRabcalBMwqvMdOzWn9xysMUQltJunnmOuXlSW2ofmNdntxBOmzWIPoaD6
aQEUJq8Kw7v54mkKNgu1ISgIxu7dQUFZRJ9U7NE7SigOb4uK9aCYcCeBsdjsK9cKuJ1NUaaFho4W
9GfQk6culDqsuwLiG776LJlehjKcXLRgv2Iuwock1bG6cEGB38FbmzytrlpibtXh8ZkahQ91NzoX
KRiFA5otb+7DtmbGOmj9HvekmbnO2hPAux7rbivXCC3Rjjmtt/Oj9sU0/ESBDkVUpi2IBZAo2q8l
CfTOgpj5kPVOBzhueOiroZAUKqaxS9XMP7bGusIDzFdoiVlSBzm/x7W21u7KyQEST3JPY8k+qfMS
1MEfAajy6Sv9J/ET1bnN9fnsNUkHK1+4uHnbpzBv7cqDwubrCpxa2lzoBFaYcqB2811/7mc/XLpZ
Il25sDdKQaMBWc8HlDo0n3yYyyqo/ThhyjwKHgUj1iqis3XvRkBPMGVtUn4JrQZfTVTpaCNXLLat
5ExM0Rtb7/imvNsgQfcMz4VMBrAMmi0jYkJ1jo+2F5ZieutHF9leBV1jUptbW0ZkJaURrjWfbSzN
E+XUU/elcWEC/Ulx6sbcbFS0VXE9cIm40BAyH6qkKw30EfTXAyW0GMukrEBwnYwFxkihVc9s7/Uf
J4IL5ryGhFf8NtE48RBxs3DOYCAE1I7y0q26GH9ZehcCoknsNuu/kbkVE61/5AGxTcAwrEwKiYco
m1PXbmiSFhRw5sG/Kgc2XQvOUsA/ZnZNWL2xZ/Tzr6pi+hh//+QCvgq8q5lXpi1W2WTZTV94GkNc
7InjyhNxllw/WC5PFXi1IZvcvOFGJjokfl6uqOqQY542wlT0/bbcnmBBtAzfPW9s2QKARny2tSk3
Uw+zkD+7ro7oTYoeeRymApGKziJ4NCQYgm9CZ8JaZr1k428hoTlcvsuUfcayP2GxVe7kVeB5CruL
2V+JreoUuUaNrriDg8HbUjkpiA+9+OXVomHrcizXdUflXhqCtRcVGL9pmVLBlL28Zhjnia1Z51tk
1P44hlkLpGJ/bQoTIs58k5FyX36nWQ1xSqiNpTjvV+IwWBIP8RCy1TDAoSwFQx1ZmWvPgTGSwlT6
hjnrStCXTPZBBH58AuubwKeV9uq/fjIzVXz6xrx1xBPjYcnZO9CBjE8d++6JWMpEyxYLwxSsY6Xk
1k4xqQFnsGg4qOS6CBX1T3y5iPgybZVzQPw8Ip2u/1dJxvMrbLt7ixCq2kWgOS9Kupx8S83YjHwl
7MK61+lO6uEJUY1Ef+m+jjL7+87bdqPBARdfi+ht4EZcLsPX80u5M1/Zsq1LIYQRDCmL6C+23itY
107Z+auleDomEgPYIZKC0zDG1sh+EzgR82DLD1CDtRibM/NJSOSWoMDweauGOFNoNovO8lAUucRB
MKkdT4wREbrsDyFq6PKBsYdeeXqBFWhC/gILJWOfNMgc0r1l1v65AOllZkT8w5Cakg4k19AjBStK
lLjygFyhJenY5b9TxGIBBKHy2V1GSJCKnNSsmoFb+SWyj+AwQC2rjczEyb4P/T8y/cGOvRx+O7jX
yvhV085/fjvA4ogvy+RrVPA2VKzDluAtn1xBjaiZ3VPkvH8Sx9iknlp0EqJK3kezjPL63nstiunE
3SgB8oIPzMvcWGxrL99d2F/eu/lOK0Rc4FV5IAqdntSXvIOu6rO8Vj0CyuL4/oBUJOgRgpaMReKo
LeFN+wItWZaGNPCqr/MY8/q/QIuuz2eoxEYKkfS3237AQf+5WV3+/Jlc0pXCCBCpJD5f1+N1f9TS
RoUWJHsR/5S9BhBWTzD67jPsUKvzb59MwyhMPubKIWKR9Dhvp1ay4rj63qNmvoFr61UTs7Ywh1Fj
hz2JL7hqHqNBQjd9a/8wriGDkBSasR/ah17rDIOvLhiiJyzosoyp7dzgoXlQ4s4OymcZqok2as+r
e1rntaXf+ZREwA2c3d612+KqzjYjylHkZvzEpbcLdBFhKhRPkNWQ3Sql6lIFIWguMGP/4Q+K94zW
WI9GekMpDtBkNni4aMv2CYr2f2iyGa88WPTKdQvdlzQ9VP3At6nu3sTJeCboVLzVhcLX0huPq823
gDHTWOYt/361rsL2VjDW3YjRoo2ilc1sM9fCKryS3NSvgklh6xiGd+eJq0rNtrUjMxDBVMurqZnU
IuZtqfns3jq/fTjOcmihev7H0IaClcbSp/45CuvvnEJ+x0Ub2qVByaFOLol9HF2CPDJXLOHHc6Cw
8605ozsV6TtydhWLu8Y3ywr1jVIMHHUYSgingMnfvCR3zSJPWwUOFs1ZNljJ5S/yGiGoFku3mWgp
KyyU0KyBOCPSfyjHTbqVVulL04MUnprRch7s8YRzw6S/vtMyGHn6ZP67T8l0vb3Q54LaPfzifkN3
/LPMnysSMGFu+SBQek0JQ8Mfq3Ynfz1xSt0a8tLKvj07syYMiqlJB03h6aRR23an9LH4gnuTiRTT
Vl0/cZCM9TQ0zAm7LQPaL2gR8Mynlv5udzidptzq5wufFh1m2JHFXsABfvojRq7HrRhrbZlAb+uZ
JtBIGsrsRGsbbtastRKuMT6eLYngRcwC3yAX/F1iM9mW+OmJW4D0iGaO+OXTVFtQzBZG7DCBxsVy
4zvOUexU29y2UgFlE3rxaDhv0GGrk9Rn99dz0HSTsWjkZ7/jHNn/jQ5b1TNpGvAV9S8Y2/x0sfPC
QDKkCIh0XaAvLoQIajFp3ZfnMliyXW5HdLzzWfk7KDk/yXEQyuIKgOMaKWqN89KgvTKw89douBb0
5dvkX6hqBjs7flsonVg9nu573XdmmrlQkkGy4AjEN4YzQ2pXn7U7AtCwlW7ZxBHvHqeD/wiB5Kl5
uvTOSyWwYrNmAC31KSszEGZGr0mLbk8GuyBY0Q2b3uHtUZa3+xrY3u+hg2feygrxRMa9mKfeMgob
gpBdAo9sEfOKb2GLeVwSWJ5/Ttrv+901yk2EGtnIsfT+n1shz1RqrfCRpukhc+JHKBXmlXlXzPzH
wz+9BpEgE+xR06e4/Aqc7lpIOuy8H/INkMUsoZfTPBfDLn0M4HG5EG0vNpsOx+yfxVijX9PhAkKw
AIRDLqFKJt4CaMj3/hG6ODGmsjcDqWlR0rqZ7i3L2m8h0AsmoFCAjUQhdtHYjjs8rHE0Iqg01S3K
NiUgbDXfKHZGt7FCVMMqjn2c+XRU92HjWlBqMNaKwuK42BzbKVJ8waw9EmlxKC85pDj31VnSw5l9
4/KomaIeH3o6AaDM2zr5ktJAKULF3JHd88S6pbjBE7LOENBQXZqlqTnlTXy1OxO6MGyWqmNTxdog
3ZnuG8shPSc83IxkhsTeIPEG3J7UXUsjkP53fcC2bg+mVADi08XVigdJ4VLiPDvq2/qN3AIJd7fv
dUPVfR3hI3diEPonhl81v4Ty+WwIeEhR/Y5qj0yg7ecU0kKDoUQbPG+nJMhnlg2dmbSFSK9+gqKi
eFI0dZwD9ZBi4wZ6aqNXOIYBAt4uqbw6ynNPl56jzfLQUNa/0KDQe12LgCy0QAh2kAsH4GMltnTn
1dk1KLsf4t6tA5icYYaol43r8w08z7oyvOreT4kviRFb+G8zSqx1xkRLvPhkZUCm7CAq2+HGVOES
KXLXU9yXF4OW/V+FNwii3ApiaKtZhBQkwu5d2Wm3QUA/tEuDc00XD6vGdr7T7+rvh1Rfh6Z4zFMe
z1jp9os/SYAJwvJAWYDOAXjth1J0ssIJJqxh6uKFeS4hHPoXZ4LvAXcxiTiSoJvJjOSCe2kDPkxm
ORSRMSNFNcUV6yceNAHlYASgw05lyY90QBWu0m3dOCe8kI+YaUT0dg4lWiaBEfegOJIcX9ADURDd
gikvgC7d+aDkBZrb1uDiTMfMv6RQCaCiGa7U4NN80e8w8T+zw8OoLlbCtTLLzdh7lJSYaCBBdh92
UQPdFhYa9F6rTfIcDTefd8x5nDzudrhsV/m9Mfql1PFF4p/7EYE1LbOT2h7byUrACNSBK5zFZ0is
TZmBxMO6hQYTL+OrI0TO2iNHVgowDsfEf3COot2e3BSefx5rKlPce/KXUfqqY9VL5iKi940g7jFY
dcQRMbOTYJ6U2uL8Vc3Vfd2VDz7fSKBYqYyT8R6zSD3KgRYCEPY+RZX1wHP5dl5sXZeqwKTyyEtq
knVuSZ2zqNw/9Ejmgj0X1ffkdlz07H0vBC7GJlGuAyUbeQC6e3GmTb0v28FMimEt5G0AO9PMbFdA
OGWAzEpps2LYgSjcDKrqGV48oXEmmqGaxfLJNaCinOMaOidVJhU1N6tiA+dV8oUe+lw87Cwm8l4/
m4DZrG/v9JJ6u6np+C7JPntNDpn12KTdqSuXVdpZCUlINwFZYg5yfQaO2bBJY0LZmSpsB/xiDwg7
b1Id0TD/VTSBNVwLnaLDvs6WcStxyVNw04fAtJSywIDKL8bLsSpeS4fAIFF+b+iK5jzggp8C49Qf
CBIaKbwdCGDX/QK8k0L4o3MBY/p0xN/IBSPReslWH71yZfmrzT+lhZlYWtk5iHnY5Z4bNx2LObTK
NRG8vwYYxva7VxQxdrG5YFnApxsslloO2cjkP6A3KmbAk5LGYcHYJYSaYRE3JKzN5U8HT0+qyDoY
1ABkZZMEj8xnbIkGGaBvMj86YVfhqQ9zhEWBS919jI4q+SdfQyV905revwFHIzOAT7f3UQYxAoo0
LAnKgUdhpg7l+yIkrQ+YJcaod9qKaCq70XGLGP07uH5xtm6hdExwUBdyRa/NmJAb4/QzyzXavw+5
LWVTeSLZqljDkKW8OtcxRvYgPREAbD1j7jy/Laoo8/wfTNvGDFi+Ep6dTbt9Qa4rVoz4yODQZ1NT
cLtdUZhlALOEUmXP9di40Xue7kNf8fgitu0ir1B6cG6hSwJZVz+7xwLXk9rcDNKbDm5twQAH8dG8
9q9GCWewLhxWkjoHXsvm/yjdnMdnrpFIGQNYksN/oP93vQkgFqmJWf3/1WEs50hbZwAzC19LJNTd
gTWDkha5xPN2EOJ+n6oMmxWw1++vtNaZEBuyR2k9S8Ww2fcWC9Vpdl8jzwHu/iD3ssshNAhNAz/B
iYFXvd7WeEGcNtTnef+YqAy1soJ+q8DHKLvYQhajQ1EaZpev4v9JEnww/iRiGrMomEluMTna7Vbp
tk0A/+r+8Pv49+IMzkAUKDBYpWwzqiHcl2jboUD6lowd9AsJ88S9WY8zNfEKwc+DxERqXfj1TQ68
qoDQN3g8k1jvlk45YKRXU/nusOGGv/f1/lh7rXs3SdROAg/oDuEcOgsrAiDM5c5/q6Nij10uAvOL
PuhM+ShqAOS27R4nQcF91VoSSD7Gg4+nDMdKcVbYMM3D2I5RXF0Ky6TmC+K32MRL0IVvVVZ1kQ9A
61RLc1jTIYi7igdGwDVZzbAoNmYvSPJwn9LWCPT1DFv07Hhv7MSMiUbxE+mDyLMnCdFaO3GzaIGV
2mTpd/rWIG1pRZ0OTKbQNHMYxIHqa4pb8Ggmi95hMdZK6mhYYDPkiU5X4dRsgHHJEsCSI3OLsUBD
qRJvHAvEUse/rBntxTza8ZtLjVnrl71L/JX9fQfeENWyl+vu9oHIsD4HED+EfBmYmYIpNd3S2mle
OcVIvDwIWyeD2/VivuhCyfHaQ8FCb1B6I2IAlCbKCL+RL4IPPy9drI2dzaB7SrZrTnOU79lQfNXC
oekn9cXn2hR19zOvG7szUdlYMp6/3whN0QCJPCTM2oFcaaH+AqcVbs1DTnx1WPOzJ5cIXM7Lf7ic
rWEA2jJIa7m0HRCaRpC4KEB+GYd5vzMkyQxVFS/oHcTRAX/qdqzQAI5fxYXF5r4LxPgF4gcf3ooN
OosYxPAmVbpwQmUmhcTpR/sJElMrD0oZxQmgxhGofZ2R4TLsdgiPOfk35OBtUMw5KFoEK/hbnZnc
eeH9/cjCEBYoUj8pPqdYMK/rxwfLdqbNkf0jE0ZE270S8+7egFSBPNPe80VAuARF0WzMzsr64y5D
yQmOcKEp+Ytn/CsMAyRZ9GfBK+MMeDpKgEBNdhMUTlH3dPwJfjSk0Hw92SFhdTbURyEYeEJIBf88
Uwv1D6zVzmJwRtyQiVAiFc4Fg+1YzJ+FDscsMrzYzyA3Pxw5oTc2waKOSwLLqf58gSMfULRgkBZm
LD0hgDz38pliMq3NDllKx8srTxlwgWDftpyrETDNxiAR5YZLJ1ojwBnZWCqeI7F6KZS1v7gqGwAU
vPtdKiLt7R4iC416Q6ICfm0mK3OO74LwI95DwIEZUmwiKoaoREyaYf2s3e3jIuAc+nE2SYfykf8N
IGGd9kkMwxMKCLscAlZX0m4rQU2eFDIe8Axp8PLxOQ7pozgPs2zztyMdWL7ZRfHoMbqFM6qiyBx0
MQUXeRR1U0/f0uUhWF50V0+yipq/6/KbpgBePExz60cunPd2Q//ZQqOrC1JdKZ5IFLPA/Wejem5/
eeUrqlBfBke/WdqGn1zdI4yKwGhxN8BUtOEqbKtME+KwvnEkhkVteH48LroNsPDrsgvdYpKnuMq6
w7DOb8VwHg7Gf61bDS9rJNOACWMxXHFtKdoyVCQKy9sBpLxYH9+Zvq5RmGcT2MBFJYoNoNSLGwIp
RKO7VaBc46FE80rXpaYfhpr1dlSyMHFZR3az19wOG87gBaUHfYR2qMXEjWEvX45lQZwfxXB2xnkS
nz5xwaDVuEJL8SwbIWuenDIjidiQYxoLWqhVuye6xAMCsTK+weUTCDkGVuGw7Wenf6FVtEEtGxAX
2MziiBmUtfcJc85shfwDDiO2FOzyG2uR6YQIrh1mtktml/Oo/RTncmrUofJe+TzjKOtCGLCpqYsx
hahAEryv7485mcwcu3fVv4O8eyxt6Pg0uLJJjRs8CII10gR581l7M0KElCXYbuCQM+wOHe3UbUuE
JSzOH9EsG8Lx97HGUo6j4nUj9H1+P4zRQi0fPkoaaO4elSlBAhWNgXIg1YS2KB6U50hQg48/Hv3K
efnPLEKoP59YTjh35zAc/rE6Kll6Hnaas4dzjUT5uDzT5+azVuXe6bKBqBhI9IJIsEysxzqx/Kv4
8JY3bO6ZImp9ZCBlCo9sF0boXXYSuuUWiyNhIvaP2F5pyX8NNo/WxFSmPITRyfIueRspmzpKl2T0
p+JE2qIiYNhsjn4hWT6p0UUjxQ95oBmR5e5uEcrUHV8Xw1s9obvDD6Sa6cdHULdRRsZV4vAbGFmd
qV8zIrkSPxQI6cAykVv6rVFQCQH4JicamwYezM2tcakZtuw5lSF7dEp3svsXC8dRx5ZSlZf9K56s
d30xcJCa9z2Wzye38X8RTpWtCGMlFQXwckQEQBKabye+sbA6jnOtTqgpqfVSnPZbE1IY8DtwCvt8
gxObdKr7m4kkOan5OefCN4g57xhw/dweoxEeB/apeay2lXlu+q9KN7FaMC3oPuwxCqxoExch+9oY
Fo4tC+Ysms5FBC92psCRFrmRtxv9mTxL/wsZFwzTqPkisByDdy7LfK+XgIriEmBQpuDA84HujPV5
/YBBsKn+eNt4lE59FDrZ/KDrXYVGIz4oufC9IQvQENRJM/JqrTIICB6bjPbqb4jaqx9YqX0OBgCD
kuyqeQdUcOmTu/mQjVYt5x2dXk6ZOnFt1XZe0yn+MAkdIIB1kifVI49Aon0SZFaD9d/omLBIHptw
Ifovk0msT1WlNIEL3jwrNK4m0sgv2DCB6D/cN3hO7ZxD7EDD66g3hcmBYyJz/ebZHi4uSOYaVmnv
E4AP7DYfn5JszRQ6vtQ2Gl0jXn8RWS3nEwVeu+KYWJWw9f6v6zng7JIsqpDfgVVcvUeyB6xnyNm8
pL8qRyS20fMsym1EzrY1m92/faPoa0ZuBwSU7nnv1qfyuXwU9E/u/QTPNtB/+83U6KdL3vE76n7L
SjgKlg0YhxGwpGGL38L4puzoARtJ01i+78LXxm62ed2Kj2eB2/9MevZQECliGojrS7S8HfOmL6QU
wqAdvPrJxgw7bjqAetVWswBRgRZiwu+OgoiW4w1uHtvMlpZn9UvMZdTO7EsnQ61tFhATnBsYkfuY
1QVDCdvSYXsoOMtnZZfy5LWjGkcCicOtFQ91jOvEZT80C7d/WZzvR7L1FcCchZVI3SnWonfZHe4j
G2eIRVOYkeg69LathTzq6ZbOvmXoNc5JO/5l4xhD+0eFhTEvA4rBoUQwAaRZ9Av/G7FOE6ESG9Oh
zejab+Pl0hbzKVOU9ld793hX1BIC1DiibJ/H+n4Nk1+MHSJRGYx5nfEp8Npb+aCA0qw6mjvtAOx0
qzvlms+cH47SaglBq+OOl83uLDCkUO7D1lDrb9n3ld9QAUBVl1G51R1gt9OK4irOBb2joRSC8onn
UXdpb5BYDfWwb1Wx//KgxyapGONq+b3idmDRNQ1lMJkLi0/7C+qOU5rT1dP+vs/B5toE2XGE7Fwi
vPtrwk5nHLBSQ06glszfBvVk3Q1qS+g7+1ZICIy3+qbXOJBalexgEIuawg71Y4tbc09mowN21Gqm
88+BrDvE+TOofuH/ZTnQiBCW8mH7Aur1+La0asjLgsZZ9ktgnxnXX9ldguBzHnjnBsTwNhsOpD+o
A6X1Ql0O3s1U+lXCmCU+z6qKUz0VMNPj2l4MrQRFiNGzPr4WdNaT9SWWhAMQOo5Eq+JZZd5RjPCc
Hm30p6ptFvnejsuJ5Erfgv5B7rxv9jXVU9TQhFOil9OIuZuK6+bxgvnsn1sUPGIh+EV8KkzYWFBW
8khVYL3Z3aXI+qyFba1QwbxhwLXxPv8i8YuZkCNdo/HvWADQJsQJtlLRdJ27dERQPJDHmhofY0d4
O7D4NkEh7nEAXzvdGVLQTmgf3pPVNb4pFCEcDMk/IyBTJRalM4FkKkHsSNccE4M3O0ISxogHz3bC
uLXjAmxBuXdm2ZY2iT+QGxmbso6+JwNiai7K0cr3UUwa7S98+Vefs+BpaF5gbqrCL86VLJ+Y6HcD
XrKNTKfiTWLDjV76JYkpSyvJGKLt/6gM6TvXhEwbVShpEmQNZHz0eKqGynCYBMaHIo/6iRb8SX/r
jhahxW35IdNUuyDJujZ+LCEn87nM34YDiDBCnFxLX2eWP295hhArEEanmQyOQP3qOyrqJg2gATEt
HhsWmSfK4P/Vq2I8SooDMIxIPa5TPHPR03cvilyuzpt0gg5qtSX32o9WjxbteDotaR7h44/t8kQr
tQ4PMLfwUhlRlfc3o8u++9lMYCsSH63X18xRNu4NyDy78owFoMH9Nv72sip2smry2Ter9HAXB5rz
qBYKfRN526YF10GAlceCLYOKSvbx968jrFNTn98K4gnohHBQ5dyk3+1hhVdiY+CJura8BKWd2d3M
WSpbrIpe21EkPqTnfl70eW8jBsUDynPxaZ2NrnJk42sKmpeyDSTRkLAFWwhUvxn2bu7xIxNCfpUP
boSj+yVqom7WmX6ChZFE46ZrqGx2slfBfFxL8MONtxIIF7OG6zAHLcZsTndkRHJjlQC1EFUVjLSE
wFyX/nWxs2z1/aWA3Fvj7XoXjVEDtZXLHD4YVVFQrrOWfw+eO+kRCX6hdSPWn/+7er7qwNPWR3Ct
Sw+F0t8RxkoaS+arqNIR0LbZUXtax19uMCn+lXcRBlp7iC/zgGFD8IfLtD/8YkKhZtWMxOZofrsK
FO7cz8iwJyu7kNKTtG0Gi7PlyXaEN37+aGRz1hs+c88Ny79+erZ0BsD58alIpg6qlRkaqMRQh6Z9
/bdVBn0XGR364EXo853CPy78OGU2iEJvBF8VdEO+LzQeleNdVkRuavj1sEyjqGMT7I15QI/B1O2O
OGyedqYyHmdd3jzb0WNAqxOhWEZ3Z+HtI6aBhAc0pHwY+9fDj5I6xkao2Y8jysbBZgJqZgSlpF7G
v8Ry53qxqYGU2IjB51+Y31bdsHttWLZuNSBGDJuGfhC/ZudkYxFS+2xc5BF1y4p+jIS7f/AHwBsW
MRoJynJSRce/4MQIR54sg3YLJlkTs7gYE7dXmAE1JsWNfLJ9X+6KDs1vq1FXL10cB80Dbe5A7j4B
cYzfFzr8rZTt50kIhoVPZhcScDW+zuYoS5mXY/XQHY5FNckNHHR5z5Xz7qGSS6H2QKbdCrQbb8BQ
w9xf0sZXm1yjvA5lu/uMMkJLt1dS9VuQ2n+Nj7KXTYQK9dUKj6Rl6HAZByTKtKORiddessCZKCK2
b0Mp2LKJATstBJFm33H/3FfF59qCWnn02lhyy7GbC4BLDqEZMynvfjVFG7cFzBio3m9VGprQdqZk
mQ1uinK2DRBpVTpgIwh3Mua1Nhu+zwrIAlqhXV11JPxMRti37/cgh2kKbLldJlchctN8YDay6ZKO
QAp9JEjDnOLDL8VWzjreKIqulJMGMXC1rB++GcINwvpX97xHCxZ5LXW9Ix3+UokkricpUkaZ+/W1
beS4tZpzIDasyUrOe97LOx4rLsWCIBWti7tbC+k/m6OljiyndzB5iXOjTGb7R0jX341CRhKhOKCT
+Sf8Gxo/gbQmTXbP0xCjZgmB9+CGY17+jxOrw3B9vGQ3ginkdOAcAkA0/OYPc7eH4i5XNbQFpbJf
LiohtlUAhhNXpzR3uG5yuxAgQn7YztS+2AcjcQT0QaVNd0X7IFKhWOL6yT81Trf0DASYV0kN4X7M
YznZli604MDmsvLbR7eoxt+uUW0zir+YOQQw1eG9Uug454cu210b3MZC7eByHQECze2UHly/RxNy
d109D1FCmYwY8HCBpJEudZg4k4EPbKiZZ/d/dybqDnmRUVJB901DuJ9ibSB74o66SgT16XFgL5jw
tH13Kx2GiIw4PlkPuTsjUwsaMohHtiJfoNgrAb7U50C9ajl6jYx7arG0d6/OwggL5bBhUXAkDyam
oCRifCwWVmw0LXoU4FhlMkKZsWxkVVNy/xNC6yV3zCO+HcE4npNJIQ8OGfAB4DS+5kmtuseWck/x
IYt3jXyl/0XO265FWjvqoeg77FCXA1I6OjakIMwANDBAEG9h5eF2lLpzgqfgK2ZCXZawHXBFsmq5
Q+ndtsTEyB5PsXotBcegxPCrtN42d2P3NAwS9+1kET7IFl9mxNumErJnSTi/FYB8VbWbrbOPAKVk
5rgHNtYlLKEJcg4vH2eobi17F2winDRpNltNJOfKIkk2vUQDxelD0OdXxwNntk1SsBo0hzDrYhTL
F00K9dW4ynLf8uqkhPLyFJ1Q+O1Zuai3Oda6PszMthksLvmrAf1CDtfBn2kDGooBt+KIx9+qJrS7
fMHzTCAFGKRnPUlK3KHMav7IBG4Mci+vyepj+dIutwznVPKgGzRW1KcXzkjcUNvCgC//zu5KcEKy
Fub6trz2zISdoJ3/f1Tar+nXEzADnF9V8aVfRVeWf7MkUK2li3hUFrdcE96AOrcgLfLPZf26Kl43
WxQJpV+5k/U8YZdRLM05mrE9+1/VPSXUP2oyoy8BfiNmFKhc+J+fy4InK2/zn0LHzPrEbV1z5RkZ
bFVhmkpjsYu1HqGZ/cpM6sqnxZquLCQRrGuD30nVS2jlfrCXMOtV7a++5HIZx0L/2kFrfO0tvPh+
gFRMjoBxf88KKt0I48hn0+/wZno7WAg4aWcvRM1r0ri2JqG/zR5cvJjd5/4n3W1zeZeNo1ZQwDTb
Tv5zza6TTQ3I8aVvwDI87a5obq1+wmFRmrQaC9aEDVmqE0h3SO8mHGQGBlbO8/mlMIIz9mT5F0VV
DhXbffYE4+iIulLsT0brUn0B7II8i/Y6AiWmwLtKXJsh02iVdUPiBPTE/fDIDEL3g9R2+X8Rlfzu
B+c3K+TNRkxUMlbS/KiKUuCcXpJJ7JYygn01qyXuJPOKLBai2RewS+Et0Z0Nqct97i1YAbrm1pcD
eFu7bgPupdiGq6ypW4eHgz15CtWRe9OLmNCy1ZUM404U0YT8/jDo63Gie40uF7MNrqzi3xjq4XVD
VpC2Hr7lcuuU481SSRdRmX2VAvav5QbQ06O9fbnLWd4DWQUDxV/9CqNUx49GVvvv09711cICvpaa
SOVhWTgeJsPAPX8m8CC4M6zAPlFEA4DTzUGIOoaY+H5g/q9Igosefqezq2zXHBrQw0Yt2n85Lq5L
YOmDdaltVH/vGc0R4jtfwaZHfMicZARVS/z9sLcX6VSZT9Ttwm+HmmjBJf6boIjrgfTbcATCoOny
QEgVdazs1zKYNZG6+9q35E0OcsF/mO0MQgb7YvkLwdExL5oEjDXpoMpJ+hm6ORh6xeHkq1epZwMU
UPHie6VZNVx+zbZyHzjuu4siOuXm/ooI2PFcG0aPfX4yXNbqbrpgu1X8+7hG5RfISz+rJxk/iFod
Mo+kgfGxrzwlSr8SvIOdKg5yb5giZtJAhPWMc96sEouz+kIo7q2DgDeUorHG5ix9Q2jK4DwuV/HQ
VViC0xTcDigqbVsl+ZBG3S962XXGmxjODhmqwvKIRSSp2mwUSm8yV0kYve5zh3MWYd1H/XZ46t68
Fh9LlCk1c3lLjGKgbUxiqdnZ9ZwwYhDEgUCSOP8TUuLtn7JWT0TjvCrAI4yXhXGFvctpSx84l3FV
524i/e/3KnOKQa3sz9RT2XzoI01o3IgiByXzeL4tsCk0uJjVt3xuDYPtpZl16oVMhp8N9PT2bmdj
Hc6H3ijG+pF9XKcCBpGoYndrH4g33QbubG7DCM7lWfPVPdHwMhYC0cyquXCqPztPdFcV5ELXt9Et
z+o+A/RIj0JDmo7D8hpGnbhQ09I3lxGjHVqWy3xBVvG/KAQhd78m6K36Ad5NtCqKTiXkyTmlFm4g
z4USmxf5dZGd5EvoEY+9oBh8PKMcGipqfjqIRXkiGPcw8Zj+QW6kK1svLLFeVUHvAI+9cPr7AKn3
E5Ef6uSCA76TtKH56KpZWwacTBoRkIIDyBM4OyXW0jTkHwiTKDJYpRK4jm5wmpdTrGlK5HfOHFEz
aq0sy54zs5b5iEIJ1MtZGnPTa3Wa+BTco8RvLJEQrc6w99QefmtWCtL8PFEkIPysy3TJas4AR/j7
J76TqD7g1Ujqpi80gHHmM3hC6L0ElwJhvmAwrkCQCxcBCkK3qLfTgMp92WZwgI7OIAveipUHbR9Z
iaQ8TjU1lOS5Eu6eWmbl4DHocLj76j6tmODCNfhVo6ra7B/8o3G4d1u88qdo5dAMFW9tUpgBchX/
b5Uq4Irbjxo/GGJPyHsBngfUwYvp1PU06mKPgS5DqzX3liguIZf1CULX4uJHYoW/vlRlSVNQT9VM
7gH6rPr0EXDH0ZEjEb+WvcHxchKU3XMM6/yKU1GPgxT4XH//MaQ4lEkA3UEVRIvK4u8D8HDB7bWx
/B5gY4RXYsvZ9A1rgd6mkEHJlVOcEpRXVw6lqFO4cPHTngcMYUiw6Wa+MM8PlebAYmGb+NL4nakz
LDnNLqHr/C3e5hdFOnLRH4ab3e6X6gRZuf/akpmCWJk54d4f9VK79Cip4EJW5FjX83VnGxxDOODk
FYPkcaavbUegbXWlTKKKeDsu2S4qWEIWRhfn1b78t7vfgLEx26iu2Zlw9L5SuM5G2mIdXR+VduqO
4WG8EZ47C4TizUWyBW3nAc8/EYFqUOFhQeddeJ39bPo1SdUt/KFPsmfTg/xky39Fuc8fFKi/9/4j
0obZqn5SnHPfxlPFaIBp6q3qRVXxw5jmf/Fsc8atFdBJ8Bkst+3Sj8uikk+dQyOIXnTSxxVj4Mih
8ngpmPd0mNLXl6Ys2bQUzvBjL5Kyd8E+3Utrchd50bVlpAEAtLN9gblZeEgEWdkzjthIBi736IeR
qMZLsGH+PVjvAatW/sCbF1iwr0REtyDCdqxDiumLIlRsJ45HQKT2XZ9vLChbl1CIhjUvTUlYChRl
SQgcDsEMjxk8EY17XrUQwbC5r6bwJuh/HhVD0NVK6T2OD3MqNdA+KJG2HDA4Klwt8GBvyeYPrOlq
ry7A/35doiuZl2UriHYj5+Zd5ceydqqGHhVk95KGy6kiEqaxaTw/c4WNj9xv6I7sGpX92P5/hx9y
Y9pEaOCcHlhjI9BqoqqaJ4GK1tq0NCYZfMQXUR934P6iAIt/zQzC0U9N1enKScsGR1wTMc40O6xd
dKPW2/ciDT8f6tTSvmo4UH2Ah+PJ3E83b7zX0UHLH22T8xb5wVAhOfxnfYYQWrNRzIjKB5MkQZFu
8zDfl/w3ZwGDDo3cJM441unWXG0dyh63mYeBsWJkMGMs5iBgwuNq3KdCsl6OPmdt4WqfWVtv2A1K
SsHpSk7ZFsXBEweMelQ06+HgQjgO09pI4jVNusBJvxMu6oKR5ckTlshbv37RtYm/verLGElppcr6
ydNnNaN8+SpDJJ22tgn6C7xlxeqwgpBAG23LzO1EwQqEz8oynSbPpO1jHwX49n1wI279XhXgtsY+
MjpN4YP0GgoLiYl3sb3HH7uOxzmpQBB4NxX36X1jGh0QD4ZDEpcmsC6QaK9c1BT93sbC2SX/iew7
XkCNnzO9gR3C3LOOA8XmHRaNF0LHRkUs8rxfO3S+YNnd7wXOX938JKDwmZUh4yVrB0Muh1SeGwcF
l/KslxtREl/9QOHa4AGWHlU2kSp/HOQn7KcpwpNXFNsTHTiGGR/Pjhy2u0IoGVQUp/djS7/at27V
YKJDMHhPhvaGk5jQet2RSBQ4SkIkZyMwAx5rNKaWaC3arcpwSxZpIyRVyg8RFMWv5KEoFqu4rHW8
lBo9Ao7Cts4vpnbmAia9Odyv9exWfcj12FV700+ANlTiUj/v8Lkpu8DG534Yn3HpaiIBY+PnZx2C
8aIOSkpKAXlMT1gyheahDLkO2VQCRNcw9EBmN1WYMZk1YunIBxYLiGyCd6sZn7Hlg7ZLY3Y+4CRT
pCUX0VEb+6isVeeNQazev2eWWCvOXHKtEfN2USJpYqQ2hinDjdfoxyitqkGKQT1YNryyeqjY1MWB
X1XfUxl/HpKnZhXp+AikwiecK8mAlnNNIBrS8zkIMrKn39RGK66tdBcSTWKWb587jmzBZ+Gjosp2
jJdpNsIkmRIzo0VjzuCPp5GtbeqYEV2RPndOXMty2SDdtAak6QGSxwlFJbvwNDdwsmI8h+O/88Ui
gpCMtpJO79OeUYPUqChldwHuRLRihXvsbCEDIGKyZnZLvT3lsl98Mkke2YWiXueuqKeHwqjpCqdA
xuEipfvW2MFlUGPHRnShZ5q4+kGxz0FfuYIImb5zKgOKiviZaJOwQDmQiMI+j1Bn3AhmU1tb0i3r
tQNM+5wreRabixLSVaLJuTat1ZoE00VZjc3I6eCl4/PBQNQfBqsFgGvbAbI3Vc6ty4jlUNTGw+0L
4iKHR5Ma5Con0G6j4fr4zpYxY7ksurbPs2MsQXzIsWHyxDDQoBIuK47IM4V6AyuGphwZ2bipDHo2
aH9FYXOn2vx6NLm/mQRgXvIbuyX6YqgL6DHYv4keWdwjlqWYVzDNIyDynXK9qmxisUgAXFr8wZwE
yMAd3qE4vLaKfg1TGlxB1wJYUS4rNSwKjzNQWocZCYnPX3niTrHavC8XEmty8YPXGuG4X0EUl+RK
JvTqXIqbiX+noikwsApyFAWraoqlDIqZXC+r24VlQDL96unxRD3ohBcwhEsFjZoFVgNDO3umunFd
fBRxE8Mr1PaA3rpJVLT+jIFQHAZhLd4jhNSl+/Qm4sHbYJfN/bI/1W/3Y7AUBLd+uny1mN8GJDas
mXqTFzxSWc74KK2SU8E0SSTTtu/e6XDYqd618VCMUUl7UdHOVrCR9nI+Ed8SurfHrfTPSac9odHJ
OPt54wLBPOGEDSctmkeRwrDl1s9lsWvmKhQznL81eNEmcFYhvJCxOk1JIYvsShT0K73oXO6hqrM7
lhg19xJubn1D3ymeLGg1d0XDIWSOEMebP1c8tGx47v3lfZJlyDIaot1k4JmPDEmawZ8RuoUHgiyo
eeG2HpPj1dfwjSAmI+265qrv4hh0gyP1eWcG+XcVEdYqPPccP5kxkxKTNi/TLktpnx3ve6ju3EzF
oaK/MzjmqeZG/m+yyRjF3PYeUC0GRZZ5mYfbOtSJnngAAyOABgWWKkPPwARzwwOfRBXk5azTNKzy
ftyHAr6CXf4/MmhWoCbz59pBFt2T+eocI+qQTXpzZXd1h6m00xZOmtcVJ61VQGhKSpmUdVK6gpZG
O+FGoCurqIUo9fuxssin5dbXl9PAwzHQ/qVuXo023HSqK/Aa1pSBKIRNi7GzTdZ+v0GLAO+9mxmi
TonHG0Ytvxm3T6DIQmlxP0Q6E6cC+61kDbXrBtEgqtiUAjVJoxxwZjKXd5GY+yHjT+rp22NQxLFC
T3yFU2V2AWN6DtieAxyQs01uimE2uJzrGga0QaHAH4xCZ/gPJ1CXeAXhTyEbWDA6ddusjdZ7KBuk
V64Wpn5z22ZIPkt/JkZh8U1itcsK76DzYK8OQvj+Asx+hqqYTiPYHyBh9G7carfVP0Pd2EvmczQf
Sp7MQxph8/qUiSqp0FZz3UZWc8HgLCiYB8zTj0yxYMjzABYn0WCv9idXPmih2xh6BP/miJgYmX14
8RhFl3N8IYwv2fedL4R3wkR8k9n7ciZdiHD6UpqxyitOl6nt4i9b8slHFfhP5pXWr4Jfo6C0L2Nb
sdWDiOpM1wCs7XpGvZ8+52eDIs1pajcbdVclzvpVxPY0aYkvFRFxytO4AK6adQzdG3LSqUFxv08R
HG0iuMP/6n57mauQgevNNJQt3B30mxCEdkGC/9Q+FJ0wi8Bg9bkOoCpEA/OWKlWLfQgFL6XU2p9o
oRnjkFnV448XMnL/pBXtGNKDa0Z+mPKUOazTo6CdIwu8skcXq6EOe6KY7qYk6uuCMGg1tRfmdyyz
PRaL9XFJZHrYVxstvxZzGUcPcbFl1UqHlWuxaTAQAFhwJUMUaOyGCIU4TqCA6ksx02HEcQ2nakKn
1GoKex0AE1nnch+XyO1jjeZUvmhfXZigX67my+8IZylpkBwZhV3xF29HQGaGKkiT8j0CtB5fk0Qc
29cA8+9uPZp+AivyAGc9ixIRJeqwXsrVWwkT9qWBe8AB8FlEejXTKP58LGkwh0IFYjqFGdhVkpZ4
qh0tG9OFyA6Q9XSscCAl1LZVDn6TQAOm+wbeTkm7adPlFVk+0kl4SFiUpP4W21IDQs7bZxlToiRa
1ssLR7G62tnrC/os2LZLKdXUPluc0OP8tWhj1ioH2+cjv/cTu6ez4UBpT5nxc7dh7xxZKhVt4m3q
aHlZIQiJ0wsd9VajOlAvQmZHWTHAACUmmdUN6PLZtGVX0jIwHdu+a9QNahdu0NpExdoJf0YvFMC3
fkmPzykx6VSsQCrylcYgtatR45hwALSCSzabRMcNSLSzR7ND1XI5dgFGzxHpW9FvY1j/Rv+zwETb
xhbg/mRpF5PrOpXnB/aJzJsjGv5dId/Mdwvlg7AV5O04LN0dPgy0PekNUEKdSa2gcz52yUlzz6ri
EzobLM8ytkRqBl+CgT5ab6guGJIQkgD6mVDmwjgvvufRoSt/ICSrV7OWxLmZdlIc9Gm0NZCEBf8+
84Ohav0+OD/B8WNai1IAu1WX8niPnU3ewZyjjyUuIB4jBz0J7V5VzJnDyiZSRbtHrU2eM6MP9H7Q
IPLkWlHZjSiS3Jcouv0a9K8Q3JTBy/jXA3XmIjiTAszN5BBRL2rWHPUL1HVxJ0f09je6xmC+k1O4
qivfJznKGsxWMGiBsgUkzNA7ACnavN1RU0u8zYrRSUToCoHjFD8zm1d3ZnrgCjEsMShbGysaekH4
u/TlPuZzl5Wv+mauOkz3U3+E7a8raHeDgmvDnYNtj5OGFJri5xlBSxUXhf9QWRJcJTjRxdgGacSO
AIlbkMkPotWDCom6QRB5g5tukwF97BQ5eyWDBPsh9DclB6nfCZa09xB1tsLeCnkJIUhttHChsOI0
0UOGsxjzBkiDDOEEedOmAQ2uDVe1UrCay1ej9Bfydjh/wCH6/5+gX5kVyoh+m8ho9L27XKDmWtFa
z3xuHJdVa+yzngRYURIguU0hH3keoBmTCAcUC2MgtRQe1JGUBhuYPWXCNEjQpsL3JMak6tTx9Kz1
Bj0cKiARER5pL0mFFq8u7Pe+SQF7H0J4xZixXmUzcfiJhiivZ3eLbW3IWMKU2pe4LuSmuBd1f8BM
s3+R4oEWBaFLDS7ev5QkZlpWC7tFNE0xtXgNoSwvAIFN/erRLfLZRA3QCSWO0yxLuJIaOu1Giwf7
ZdrYwtC7hicW2KfTYZTaH6kvBxv0HzUhugKqsbHXnkDxQcO4UiCByh9xElTRxdrbd0PlY4rmlc1x
qOaFdhRaY+cZr0sUqCJn0Ap6Sl0xzrL6VfK5jvFoVVHGNWZn8/shZXxrh8I5Ok6FphxbBD77zwuA
2mSwkLcmCBvX7DPnyMDgj+lnqE+AILsj4N/psKjGGwJhMi3wiNmJq036Gv9d2T3VfOMax1LWGgDJ
eQKKrgODR+NyEtGTf28Uigm+hemlFe4uM0ai2CJH7bjwPcbUWJrIT9QPNd7J/bm5dSjxHfNu5s9n
IQWRxofD9rYZwgtrNRSAsxCqinHPbMuIDFjR9d5R4Dr2aqHeByPOW/VF4et9H4NCsveaBSajn4vo
65FTlcGvYCIRxTWKNAoLHfBQrZ/TZiJsRN0zdwx8fOcO8HaziycpjrY9xzwLacfc8SIAN7znz2Th
isOqjOm54Rlyt17iQxB6wvW8x+iFUG8oMB4D6JlZhIgqto2FARdsgBwwAMJIQXIHThpChdXKbOXV
zLsPrX9pXkwxwknRkx3gKPLllHW4mJqjwMo/FkbTjZtw8VG0llyx3kZNwACij46goOrAL/u/e7AA
gHSVhJuaJHF27VopStofYkoMLyjBkXFYMJhxa5piUDYUX8mV67arBjf0yc3Q5BU9dAcUTvkshAEy
zsJaIR6sVXUqsafF00G+/A2qVj+xxTI1HPFIAxIuYQwMd8SSq6eNJaNDUpInZW5hWejHZ4yl7hrJ
Mt1h2n6XYWEq02535yjgJLkVizTGlT2WE3lqZJ6XnuerPp3SmLRvMcn861Hh961HBTdWENHmJ31Q
GsgsHAyGmuat4pfdBEWRHLJXQc2l60AxkWt1Re7GNF8wZJFoUjkkLP2TxPJ2yyqN3dbQjDLZeRI7
J8oQ88EgMNcgK4H4Vrf+IFmu+raW6j+oZjAAf74mz6aMSIUfihxOAkKLFHaJutViuRSqSULxvTiL
wtquavfNV7lcp4bMZmxobXsxZpKCVg0ojHMaljj6EHwZ41uXUubQWlJQ/AGgiTHksLun/qNgMJ/3
eryNfNedvAR2UGFDiCWLzzdI7IefBGXh/9shVHIUYjOujiqeBgmIQuICm0zJeXENfyP8oAHILlvE
DRQDeRuvhPxlS6gm7DOg9ifLLrDgmxrbc7xJhyQeQ+yglkEqvPZUYlZl+yqUsVkWlhH4KsjVP8oJ
Ugxq1InZKpaQgeaHvA3pMKNQY60rzBP77+jq5mhTHuCcQoFqF5Sz+a0BLcsqEc3UJ5TPxVnasAY1
paPDu6GoUeW1g1o3K+POJ6P4u03LEAyOgZx9CiThauEZKCMGNWW3Y6XLtpLOghbpxAaIqtjmyItV
Nz9kyUDn19M01mQL1g/OhAIj8QDcbz7EML8cI1jGY1ad53yoepFqK2+ph1SQpgPj6IS9XK9pqS7G
mIoJFWTpBPMPviD0+4YdQgghD3eQrUtu3tacG9OavKPAKFmsF2itdqmG48xemAlkffNv/z4NA5G+
UzGvfUl8Mbd4D11784T5ZkVI8iKvQvCQ0ynzkEKnpNQMPPuOkblJLylLbnRBomKf/AbRMcVE77wM
pzIrdjnTMTLYRCTYkRW7QmE0hwXix3f5nsQzaHUL4RgOSZqDZFjoAtiletQQXmjJzPYIMiSPfBWx
iH9cQ+uUafUVuQDb4cZxeqn2z1h822JAHqNO+YLu9vsOB0KmyfBgWbnY+0vA/bn2VGdwwVdzRn0c
8cFBFXfsc9Z93YoVLyqkKITt8DKIZnAPeSxsddqM9skGUYus8SOCwJ3n1qpk/6CrScOmGGhYeaJ+
MpD+FB0iaLqsh5iMZKAkAkfeTtW6bxweWnKwez/OVlWi1jQejE2EUupX22ZMyApmySzb0ly4Og7I
EK8cUaFO2SQoGQPdIpPk0WYLkEYyMIBkTnXIiWWgHBj3WtQfHHNcPMR8B5IXESsL0oGf1bsXBF8q
adGb671Yp3ueVSc0Y1W9wnK1T4/0t2a8hHANK03MN2lf7C8zg9/JdbaiSN4X7aPqQ1CWqFu/+ES0
WXTVaWkLGEVXWP/oSgX3EMoKmMurOc9sOJelkkaqP7t9hPtJAbaH1gqy5QR4pq9cm6tb8Sh8G2eI
7LI8QzBan1+BMImExfYc+fL/M6gf9BWZSoY/qGU96kGJf9TkjDSWa3wM+1mZXcsVdnlxcfHssfFE
KLiP/g0ZiSKJVvtb2tpWslU1k7IOmZhFff+tcg8RJ8hF92d5063ahC2wc0jr9E4yJCWrHaQ32du8
0VVObIBpsMoFxkgBKYXyFuGOJcl1zP+eksNfJbcCD8Coi/1JEQ+jLkvNKEy9x5ERMwwy1/x2efni
YKIXHa/JJgDNtqy813syYJrEd/8y9D5n6P5w0UYsqgIytkbWSih+CxvrOZzUPW9zK2X6oSaWa5fq
4HscBlYoeslDU5K+pIUEVybVdV7Z6wFc5sLuVgrNVzAgWf1pt4EhSPdnwRemZYsFQ8oWPGXbOqDf
YwXv9+ANDRhUVtUrD1E4idvUp0LFXkuGFTcH92Iz7xiXF0wnDHmfYhi9uNYzANqBgiLZHJYqbonm
E6RdXHHSX85RexRLzgNZ4p/k/oGku8Cojm3d7qS5uZr9oT32zRIVg8bRJDsBZawG2aWmc4aK5wgA
c2HX5pca+mYcAb8fQ9PAhW0jYVTUZ+xp6PnlrEHoIr0EXjr75s2aBSSXTLBIX+cdYdjOpWA/7Rxc
cfV5PjbO1zBmTF98z57CcjOzc2AIW+emO/6DJMOIUDmdWrK18q0L4vxwAGvmiXV76hMayVfGG6Fp
I9+DPb5FXemTEWMNfqoPi3xWDT8yeDEO8//OXZVjoe774XXTJf6eDqonapuYxvQhmWW0ZKRkc2t1
h3bHQWdZJzyPBKWoBdvR2SmJ8kHTkRcoCFQN69wrF5ePZROb+GO6dbHmZ41x66xcbiYNcQGEFS4Q
xV0ClSqyJxPqj7WEmI1zo7RfswHqU9RDcCFjffEEifpxiGfBW0N+WCoJI0//2NPM5G6344Hhf6S/
XhIiusn7dL3W+R+Med2hO/S1Kfb8ciRSE/YR8OGkHtSpquP85+ZmYdixqv0KlX/TdNZQDeTftK44
sNrvYS+lb8G+yRwLFYTOXjU8B40WWqpd7hzibkyc6i+iuKG1cmyz8PeYakt56jyddYxjd59a+wGT
JM1m/J5Pef3nQ1OgBBLkdB1ZvjsxQA+UhsDDNAnrBQ9JRCs8xNRzG+P+gKD6DXOpFmPd8hoFsQMC
DHeAroWNUpbSPwkInwMgeRwe2RqwSQ9AnpudxRZ4kh4NVDCw3doVsvehP69BNz5olaLSZsi8rEq2
fq4WBiWGHJEcZgO7g4LdxdU6Kfa9sIvUrMkeMcVd69zuLnM7p7sXzwN2VBn5JY+mPgPLAGEIBaJV
t+DyF4Gv/f/ZVIyUOyvYdU38SzQGvjg7XbHnZPFHO/2ZWCz1r9e9F6iD7ND9sLhaarIZRAFzKaa0
wUfijYiWV/jefYm7lrWeZ7UbFV9XnQDWT2S7X7oqRlwg5ZHkhHS1qOmKDzGWQsqgbUuUtBNY32qA
nBXM8mpo7rilGZvSi1Hct1LMFZOMRkRUH/jtLGSrsOl9Gd4VFv0RxQ3al3WMvpRYQnYnsPQQwIJt
GCouK9jHAoQS+66SPngkYxjbBl5+qDHPOMb0mY+LSV8Qx+2/aPkySvLFcwfUmBFzE9Af40bxw211
Ok1Nabjfvni1S4bb9TkjuaR2N4uDiuxJpqNfnLzof7jd6gCoTibQwZxZbD2w0u+cPeIof5jjhWnz
TI0K09trMaz1xYMuSONwEIbaZr2SYuxtz4GVCFEZmc31/Aeq3ykgqmLgx5Od3j28kYlLUtne4vvw
FachdVGgFSaQrZcqh7TpW8yq8sqvHFJghKxa9lMWtI9BukGYB0wyd2Ln73D2dyIXlreujzHa3WwA
0Ia0vbzLuUZQoquR4ZF1JnLiOuvzeaCRhBc4NVFyEHMvh9PvC1vS8dT11SpuLlKJ4es5P8R0Xo3g
55u2iAXimL0wuHUAccuE4z3/JMClJjunDa3RxAwjED+nEGtV8JvtbN70RixfjFDC/AY2lkYpLvCo
rGnNsXZgXvjnIF/1p/EpdSS7bDY4kDNlH+TtCEby4ZmZWxyurrtEdA5vcscJYA92Uq/rHhNiFQaa
il16Sg8AF0rRFMVNPJX1YIgPt4f3qgD60VKHQPwn9wyB2wyRjUdMX8M4/q+Ip+snqswMxp/ujtmU
a+xMvYX/5KmNxVXMwEN3dofOmKjCFfFrkYZQpLFrI4W3IQ2VcJS1dg6+cKG5gfgtd2lXWeBsRRt9
xu0uWSGkZd64gqutLj0I3X2WzwiXSHBJrBTifXQ25Vg05vxL7P9VtKXotDnvpWJWiZZZI3prjWpP
9bgd7IwMnE1t2/P0b2JoDdSrV6FsXzMWCH/KL49zK8Es+m4u6h+oBh9DDcONd8Lq6x697mZtz5+I
uqK+8BJCZ697wpAT3ndwM4Yl4xEtM7J7YhzVIK44aoT5Tjzh390Vv01JTjKppClNR6pZbk/Kmsef
RWVprzdkqULlRQqy/nIjiywVas8GsOcSLHkOeQESMc2pBzRTSDW5kd//sy2vgHaN/jM4bNZQ/HF5
95UVkSsMdEV9piwACq8SRRqS2D8IcTuKZKK3FFCvIeax/ArDlf2Um9A/o/pfD94f9rd0+3DbAiHn
wbR5otlk0jnpSvsXJPxneY9VWH6wDc6LnZFRvMZJMQ0yjlHUKH0NszRu0+Auzupu+3k7zGIOdtvq
e3ScTEL6uldfeb9/vqQRfMfRTN54wDzi6tSKpPS9AMiBJihtP8Eco2mGAhx6nhq8lqQnex9FG6SI
ELVhwyIejL4BrOgEuVlb/KVV9gfiFC9gAEA8aHeWFKeVPUyC45sfCHkVMAIpqjPA8bjzqx2E2na+
5hPGSHjfhjJtu1gsP9LIC+aZmRTlxGbl+ux4fFs6/disUKysK1KO9ttX7/hBSFUobScsgdgPILhh
3wKhlonWuMNxyI5kvpVJdV3k6U8Se0s75wd1RLRDLlXHEXSFZWvWPVvxZYyW6aKJ+v0RENBr8KXv
cXilxlZWvSWpCTvZ3PKKU+w5AhE3iE4NWH0jI5aHkU3n2A0+h+XYNKpRcUEmai3z+vG07Kor5h3d
ecoURoSgPRluwXOI8L3wuCsg8808dwM8XBzIFjRHh6zs/u/g++/L1hdsmUnCV636ZDpyb6o+EOPO
HUKOAqkQrN3sTmgC73jmmuCG0ukZkjezWkeEBThLCUyPBecxOEYpIFEz7RtlNhdFrbZLkEPUaToq
lgIY17h2SYP+c6o2BsGD/CEJAzqGJbFBz2JJWB6VSo3yYoLymldRRKqcsgfeOce7Td6hxxwXxXOP
/FjwYCTQ/XEq68LB31tSs7/vM72qsIroDFzVlbCC7KoL0Nazb8+yJ3u9U3+QJQyz8RyYJApam0d1
rYOwcis8yL2HRip+ByPwtG0NnAi9RH9ND+QBccyvZVsUN9a7NGRWm/3pDdLbm/Be9EOoDz5tru+p
GyOCL1KCCIoKPDvQ3U3xZm7jX6w5wKIpM7gIpC4/VkZKOvh1Y5x9g9caiXMe76p1XZYsPDO4e0pW
3CBRYww+2WC07bQSjsWfqTRgMUMWa9SeL3ngHE02/01MVhOPyiZOQboN3LcLy8kjF1Tcl6JpDfxs
1S0hJlft+VeuNyaBDk5nJ5achk0Ke7/lhdPYq8q0hRvkOOqzgMaWdXpF8q8tp8ImCdkYIltEPpga
8GeC8TdGh8Nq1y1yrarT52h2XlWvuLf+rVAu5KnYeNo/Tdm1yZVqIwnPSJcdkig3aOgxSZAdfLk4
xkxd9A+G1BxE52g2M2mZsb+BRjwrxryZyoj1yR82MKZZc4G7XlwGs/ZO/vSzb2SjGG8+KiX+29R3
RxZWYP2UBlRFI9oMCQ1/fOk7QkKlfjR8VtuoRVwMGpAL39Z0QgECD9cKVmNm2P5AqTct2i5c952o
Jz/kBw2a78sQ8ek5U6RU7aXtRFAC1wYSOGKH43TO723RmhFEdAOvPvZiNiL5KuWVx37JYx1ikkLu
nCivUxsEjXLWOfS3pan4rhHT96xp8gKwPkX2psLL4wVU9vJr1X5LGFaMbB/JjiZ6lKJOG/zISEUR
UarqEOPblAU2NN90lXhUVfbDRDghpgnzSVbe9XaXL11/be5iLLm5IdxvVDyc7Q4kP8JcWSV3cbtb
4Z8/E/Bmiead8uY3I6ZbuRGbQdkoh0GHQUF4Oxz5MIMv5IU7xqmon7SnVzIs5+z5Ut4rgBOPp+5r
yxTEPRRQ3lml/BTwjQNMsiKFsoNpS4xMA1XgEq/CgpWJzU+EBLmpic9asN3HH+7qiu3CETp0lJcg
AIhGNW76PfGjXfa/z2DZorN30cMu0+nPnI9Fw/VS8AUoLgORCIO9OMcpmqlkd2bwBsIsGANPEZYJ
CwqcalOdCAKPBOVq1fLJIe/tn6F0vL7QNC/YMZXJY9FICcmcw6kbzkfL/Zj3YLaP7QE2a0Bjh8bl
KkKvE+T6/cKVpjDC7U+pZBhlUBr2IxWTVXkPk3XWw93k3oEjvas4gYIVuW5Z3Pqc+Wid9/OxfQ/H
vqRMTmI+blWLXSyZfkWZV1oYOF+JaRTEcEcSfQs0q8B6tllN7e24p/WOj8k2K50zUGDySgT6i+6W
fV3r/uRry5uZ1hn9RSXO5hv9/V+OaENhzlDrOagYoFkBRUMp3Fg/fH0JESA70nazj4ImcuSkpyh2
JxsZ+KiPiKCPEQBlsO7B3HiXjenG2QLlcrf/VMANP2ysaKO2hTvrlutQF+1gtlPo59rgLbygQmke
ZqCK+R4BqfVdY2eI9nP5EVTIFFaKVqLCF9WR1Um1AIeN5RdoOj+6Le5C8LJ30p+VCnWZAMnppakB
JxBiMQW/1G0PSD4xIJPWOjWWw0e5eO1uxFK864NRrT9enJOhhs5hbK7/fnEeVar4ic8i8pE4APJQ
wx5hH9pGXOSVjM/ROpIn6BkJB54w/Tb8x1Ty+wedd8Omw7ncfm+5t9i+4XMCgGX8GraXLUNRZtYG
SswVotCBL5qIXFrUjzILRHQwfAIqpZm5yzv6Q0d+es+TOUl3KeNqttEiOXmFwq/PMYmdB5s9pePN
SJ+6TtDEhj8aMh4t0HpyhNW39Y2BZw/UTSl+NR1WjAYBFIHfIPqt+D5DC0yu8YuXzQjt1Xdcmuje
NWd9CFxnFd5cxHqMlrSMWhAL+eqA+x3IjfGGK7J+pZtPmIcgu/ZRkF4qyIt+3ZJNEzwyH6l0mS1a
ie5vYUMideZRS9tEWN9bsyPY7aKRFAG9Zl6/lZsvXasf2XHCNOgJflmGx2nA/OnX6jScx84cZKoP
EImlQWfcc4VYjVIOUBGyKLGM+zyywd8p6ZoRvc+F8ame2eCFEUbWbKLiiS79JvqFYbJEFnE0UEJB
vgQUkswpM33jzNafhDDExElSkFqc2/gOvEo3qp8EHn8bbZBRpl+qJZJlnAA5WE/+GhUfEjMzr7P4
UA1azgTVF8W2Z/sE50zKV31qLQRzpXh6sL8CRExOiwE0QhMYADpamPUGozPo5Av4fkbxJqlo6eS5
l15IzdYka2yLx0uc79Kwj47SuxPLieDEbHq2i8w6Cg+ScN1YPxwIoZdh/Eec9vFdp8PbUuLfhjAn
OgQUG9jMToZBRTmUTys0ppbyoH8rexX/ZQmjSzOzuiT37mGSIvwA2iJhJ+CpBzAmS7qYg7ZeArk7
/LvcfvI2FiYnhUjTipgChmbNWJITZZ0RB9dQYFKf2GroUBiTI0o6R0P0ZXPqeTtCJVCkPBw5jTky
e8zxmyRiw0g/xBjCmz9QsoLusF2zJgDJbtPH62DZN5WznKKt/ECdpxnyRjJ+C1vB1oIBUJcwRIpW
k/2I4gQ4P1bcd4lAPEH09BhceMw3eqlkYPN1dMaOOGDbn3xsxApLyC0hBH38uZ8holRkH2hn6lj5
bw89+cCRwsRLcRVN85znqyxnP35kQFExdD0hH4xtwY1870Weih7n0nFK7lG9IpFzKzC6pw0Z8br2
ugpEdA/v9sFr4/MG0Ptb3WUBpR/MMvtkp6MCotqnjTgpCTxt2KenaEncfbsHL48W+WZfYwhp/vqs
6coHXflvIp2KjcOzUaBTUbku+UQPdrfOnVjhXt27YWmx42Tw/uWz2XZ4up3C3naczEp2X/8ZDpl1
w8+BBCOvUcjo3bh51r3Rm2qO8G3eHfGSPE9RmfgK1OhgSrkdjgOqHQvhXJ07E1+B3mN7eZNSnKHb
5N4unQiLAOTeGcYV4ET+op3xUy8roOVNcfB1Rr8VWhh52JgEHZnP/qm8iIxG8EUZax/WqD2BLNYb
x/bduTI5vkP3J7AQ4JDCPI5fPRbujzkGHQEr9zFrUx/3ImDfvm2Y06ls1VK9nxV++UY200cH4Pa6
yolgGH1C9C8jMosHiWei3n53BjnMcPs3sTgSer1KkuyVzQ+XX5gSRzGMyxqF6gne2akNCqXaC2j9
KV6aOjjIcwjwnh6d49USGmhHZWLjIF4CcKFwONg4+J94ROk3at2ieh5o/TPSbO/gz9B4YwBkITy/
lsbHiYxalGM9/c3mH6oMyBYuSevKWvUQNUge6VpQ+bARcwXWKORRXNbMfLmqa3F/T8hkUT9OhgRZ
WH7qzjprgLtcPVyXmAONMC7GEfamfdLh2MOfEYia45lmlCfByy4HLuUvxEu0+bqcOqDOPQaM1IXc
uWVpPmMTrcDwJL2Onhc8l9V5z7BVpd6voD3KMHZ2f1Gu+jLZlQwjTb3+TbvOVv2XEwY1bayuSMrW
EQWRdJJJ5Tt6xkguf03183eiAmtkunkm0XDQNopLaTBZlAv/adZ+bku/2zKYVBEpQvNGf8Hn2w2S
tVK5g2zjvGYA6Ze/PzrfHjNFhb0t4BnNrriL8eZvJL4ij381gWOXhsdkRtJE4JIg7Yz/ML12f1P5
I/7Cixk9DSi+AJry5exN37jclqU6nqE7r0FXX7wgY96YbqV0kqw5ic6zP2/jv5yXtZe2bFBF3cRJ
ho60itLpRRFpi5y+TssZ42Wkx1xK3Ttyb8O0VS+rOZexa75BVXPFqmkkAHarLEv+pb2Jz/K7DxWA
2taGNCbIQ638QflaWv3MrTNBJQRNwoiuloSsN9Yg2tQsrD/qtgxcp6Yusvz9EbSZSphCBdn9S+NP
zHjkKWUb9w1+5M72dCz+PFtdRyjcReejBSwVltcoSexcpr0czgq/WjUYQAysrxQ486+knYV8wAIK
6fSEJKA9jjZkrWIYtnED6eDFlr9pDvcOPEXyVWA4iddpW0HjT2IrCRB/lpy0z+dmoI0JVTW2CklW
zKsHOmo3cpSYO7dLEfXAKbtz+bAJMCwkID8mIEq3k94kphJFaO9mwWHMKcxETCiWDxyJddbsXv1y
32V1xbOzbSFHEzMWGEqEDJbXI8YJR6ysizxs5SLuEs8ZV0Vnkdcq/xYjUbh7ezNu7KhIliipHcfU
HYTqSmDDInTXZ+UDX5JTIHuh5/6GEtqv20OQISW+tNv9Z4b9en1jfOipEXFXyDlBDnCSwYIwq+wk
0rjPqofldBE4M6h9151JgIb5Q05jghSe6sPtksRKyQbOw9BF1jR6U2GuTVdlUk3BEsXSbN3eu+ly
ocO25CoqlHCA5Fs8Dqm+3SMC/bmgy96ruCwandhV+9Q8+DjFHvxj6TNV9rg108V5eVXw8fG2+D3o
85ai5z8C+U2kr344cOtijr5jdAuZx71GJ5CTqQfpurmKmyHPURbkZt2rGPB3JCwmHR+m0/aL/yYV
6zOzinpTncW+Gqct4npR4uziKoKGXRBewxnmAb1ZzlYqdU66aMd4JiZqOI9I1oRS+0ANT5ZhJ4II
6JKGzEKxEVbueNuCfS39eUTr8HF8oFLcFhZDH1tu76ghHlyfUYRS5TVSLzm74TWFhx4PygN2GG0f
Z85V1a6CNHD5K4HKVEy/Ukm0UIQMdy6tRWRDoPjO1qJHu/ob/iA6m0tT3W72lwLHldpYoQYtzQOD
LVT1DWLCLqi2IyXDKZT7GgXSdvPwKGoWbXzWy/0OdXZ5z+vSD4xsWPdgq3SA8Z6vYsXXraFTq/QG
NjKaIWEJs3O67L+gFyDfYH8EIwCb5Q1Z+yjGkKoFVkwIkRMXJz6VcXj7p/V6/CnuMp3wzClM/t+2
tpUHrRvdFOJ1dkuc6d1yGJMsBx3yeIQv+nu4OaPKDyWrY45afArSXkylnn1P/RLrPix5PUmFy6Ot
oVp/QYkfL4/oFkIrltw/YU4V2+TOLB6gPw8tUHSV1CSI5Id7Iy5EO7f6L8XufleaKANf400CBKSo
RHkhhqzsLccRIzd+eSzUJuE8zNcr6zpdt8tWqcQXh87v19qi/mktim2/2JEbu3iswAI1yijc7ej0
yFyee5PPJXeZScqArYd5bCV5fa2Ij5eR+GK4d5iKBO6IFOIEVie8V7kdJkd13pAiI7A8pF368uPm
oAIN6tJYQawq2Zx3SY0IqctTtQsT9hU2M2kTPb9MqiB15DyVco0JHQJDYNso9fK6/1pEvH8R/kM2
mHwVTRwXDuIVIxR0DntvOU3da6An8lY6tmv4mxNMPo2PLsU+YvTVREVhqAMtC/5ornsJ8bHG5NwD
a/pYbBlx6bRrRU5b3Ribf2CF4N4fCmxYCWsoK+H+GE1ga7Hrukw6ICtj56qY8Irw1b/CFDTnPcfK
dFUHD4p6d0zHkNV5iFmkzNARu17THRqmXCFkSSx3OBVa61db+kUoSkW80EDXbR9+w7Xw6WxBXmTI
ggyjjaB06pUG1t/mc6k9lQr/9tHW17V2Y0Aus5HTUfKv6rCFIQG9St+m6oGurmxmvc9pMHc5oqBj
egMTWNt5SmVNj7Fi7MOMe+ABXicuGzl3RLRacaR1jDpj7CG+Miaz6pbSmJsxoMQ2oYllRLJBG3Dq
KhwKWShsXCtIirhrgOf3cUNaSHGaZh63qls98bdxYeNKtgPWYn7voeR19KvRiVpKPJ5s5+vDECuf
tcTk5j1WUMDqk11m5KGhal3rcqNEG5zdMLAiSeAA2kbJyeRxApyarJukUdgXjvAatjO7ogtSdk3Y
2C3KyfZU1onwvHvFIr4OPeCnc/gx6VvuaqD1VCRFFCHNKiQYsrOxlLUz8BA+LlzQj54oH/TMSALE
2eB/0q8w6yuQV6CNm7E22MqnIDhDw1zLqFTDLqtqZbmhVpziefwI0IrDUnsczEXUYTzsusuG5jTg
b9jlQFIudAHEbcW5fLBex0ZlcYO1A82LLdTBHEbPU7fGgq5RNc/tWRE/H04QwKpxkEA8hChuqw6W
4Acd86WTdwFl+LQHZK7A0Lacja+FUHG/MwrlR3wrjT9teTC5CIE208IPsohNfh+oWH/cNKg9wzsO
JNe7VGYZkAah4STr9RgJ/IYP7EPQhU8bLyDUXBLYIeWbO0+k79aDUCD//eUsbnbR/7Zb2QyomBK7
2ojzfbgQWhIWYUX8KcP6OFU8qOhoFEVoUcX6WfFVvAY5iJh3kDPbzeef8zNpK2WNcIzaqQA/Lgb8
c6s6JS52gXxOFsFeO3nCEsoY1GPd6pPjJKmz/ZflOqzTNJXY7rtChvZoSMJfFjY125rxAlVJIX/8
DkMAC/YY7kX7nc5aHsEjvSksf54BUtbk66GDFR4nwTT/XGWcnzyAEgqFsLHdHnP9Gf6aSmnTy7XW
fOnIhnqi4PLMyxT7tUTqAX2/Yl+RAE+jjin3t7F5qQr9cW1FPpXGpQwUP51c91ACJVtMFr4UW0BN
MIB30nEQYW/RS991+vXWMxyFJ6VSbTCdnfmoYxUMdFu6F1EF0JQhIEmpMgdP2T+m4/nWbUit6Wii
t6GOGEb7q7YeeJWLBQZJQ+8Y3XuKYmdCIWeBl08MfIzQmjK5OV3Cjdu2MrVL5kOlgu9SPrNr3oyx
eNGcMAmiWBAdJnk4eOmQYiMMzo6jSYtomIk0iBmj1xkCm0Sv1BRf36f60rB+vFhHbvVQ4R1pU53d
DoSgC3s5x0doB9Ip3F6mHTsvDo2+9GA50TxTToOCrRmYDDSrZFI+Q6iMf25mvdlo+cHTUS4Wtekz
AKkec22eoINuo//rG+1QIv0KtE0g7pssGS5kIAdPZgxhunjFo5WROMJBN6L7xgdSnZwZdBafLtYT
7Ss8/hsyiZ5oeBqIFS24HD1yU0lKRb3C5n1ABdL1dlrjD6mHAlHWaffhRltr36ArcXQud1qQ+Wxp
0Te7rnmbTyAn2Nx/O/5B3g6AL1zjWx0dhgy7i+wYPJ/FElfgN0Xj+ILl+ndbGi2RK/x43g5P57dY
6jtFlly5okRKnUk5LcSPpxUdD8UzS5WvL/Dep5TgmM8ryZ4vKyhGou3Ogmt5LL99/mbHnR176brl
yCKeFu9+VWPTNdwcU23wdn5KlV2NlAGW6SNk6QzYQoWj9XLwddS7VBZbmTL4ifgio5c9kiuJKzvR
AKKhcPxvo5NWwRlU+yW7BLYlBDwiT6TtEji/dhQ+FmuZFKcY8/9tQsqiBu61XOwJmKha9inuHC8O
ruMHtXkWHWte1zgs1AQAUSXKgUrQnjG46QyFBus8ByppVKAKBjn8FAtXG0cbOy+rGCapfIi/oU7M
DCDybhqrn7VIM7ybpT/LgUlg+KHYKvHMMS+bsmjI9BPHOwySB0h4+tZV2HTbPLGX1KHFRrmLMhYh
Ts5s8pt5dziKa5HO7BdhwTO/xxnb9VDov7sXic0xzUx2Jab7HRDRwvL4N3xkLDEjJilITf4mnv/D
H0ho2YTv7wOwthnIZz+BUxgiT7B6zNuwSevH2XrRDChIMvZhB+UE/XQeeCEWzvRtpXGe1NCX+NkZ
GtVdlg8DeRIu9L9tLEHzgrN5WIXdPB7Z0HbqdX8xLHMnKtUQ58ePjIpf2bpGZGuJhlr+3ZXZy66j
ztKduy5sD0oTZ2r+F4QRfTMs6n8TTJ8ZvrABscWzNA2U2Iu6GKRpt5LSnVw/hak+e2pQpIIv0Bh5
uvjGcKslwl2BNyw2OkmRCRG1/rlBuOhocB1HvujvqIxFdS+QFXEZIYCRNaDkxmUJWs+l7qy/fk04
Ibn0elKoQhE+UF8OGYUfUibsRy2G5CEyHFm6Nx1XRcEpyOQ5RSe+W9jWwtWuRVUrhRw1+zOS5Mji
UDoT5ZYdxKxz4XriReLlY0r5YsAgznmypMaaQLWVSJuI/A9F16zUThbZ37rkQ/BCK7bJ/3hwvmBL
gX+ZLpQ3sF3Nyhb5oU9K5DfbcNvOIiIyhbLNi4hsUJuuDsbd526Atl6rdsif97b16qAiUpPqObtj
P9iSIhBYl++iYi4m46BdKwB3qWnSuw4vv8eHYXPnYtZt1ifNIGRHnJZ1b2XKnbSh48jDUO3+8dMU
VZMP9063hBc1rtgG0aLpc8rg6G7G2gAC4929+hqc6EIzrfw45TRAGw35nYTYjxXH3uB7RBOOocen
wggxx8GTv1RUUGIOZfl1wUH4Ngby5Jmb2DhpnEMuWJ+D/TenrATAYBRhMoYyK1WZ420IRilN4Gaz
vHVt6xYe6ty6n2bXn3lhWRcUS2egx9hdYmEVGNzdRRbUXgVoxYFXZF8I8+r23g+vmk4vwKDsDpan
jBbIB0xvMJwT0+4MZ+sjVEDKI8lwsIUy2ahkEuojRrywfobvicdvXEXExbOdpU8ur8JGe5TF3qYq
lzFZNzh+FSbJx9Qt8eD5neMMbQKjyEUmUOS1qY9OnYPTQi93kMMq8f1iq9mKVX95CZJo5GevRp6k
8qbwjAbPc3tu7WCbqzfjyiFbok0g7qiKpdY66McSLPY0SCC9Ir1/CLojfxrDdEG0nn/ZuR+JEfcq
/+9QzXpu8tzI5FpJMyr+L3OjFPgDUIhS6T0n60nFmyJoGSEX0xspHHZCH1OTGnIlAH+Ar2e2Jws/
wDMPxZrriY2nBKjLdqzhmrkFzrcAAtvFdUaOc25C1Cc1xpktV8sl6UnrEYsZhuqcqKiHflggIgNR
BSr3EsrvQ1h8BxeLnkv3PWls0nbTsLsBUxaYidCvBVofeGTWLYahBObztg5x6mlL9oJwBCzXK+8F
ayMnlp9ort9sxVfRHJoPYS2Vz64KGWNUeSb+xfdnvyjps3ehuzDC0M6EzFK//gS0IWuNw5FRA2DM
FPnBMDgS4hEoTcon74+ZCRkXe138lr8Mgwb+TUJ8rd528wMMSI4ucyBe1fGODY3TZsn0VdF2vH7h
7MZRqt/qnf0y97kMXvDmHBYppG1ar8FCfv8RFkDymqywLe8/54HaDbw/h1nLaSSEugUc4qay3x6n
7qOETr7m612nJC5usmureF7KOEgJMIGdLYytw4QjOrfIcAF67J83CdJc+RL/7v0uysrPQwtPGjLx
IRyw7ozfFR02ILjZpZ2bjpE+LOO3a2gLAekSHvIBSfNZyoHtCdnF58UIjh9qnTjWo10eshhsdG5u
bKzb5lJ2rPuDWOacaWZSvhdIx32BIRdJOYahVC7r0kErmVtzKuh9vn5XFs13DG/46ZL7Qtzl6zPe
m0Xp9Dv2eX4/gs1aUyDgBtG5yUUyU4+We11Uk8K8fsojYMJjKL3ltQ5dc4bt7jxr0TZrbIXjary4
vLbJLwwCMay5luZ865Y+AxU4wryCJVhEyBAHH7GFFV3x94RSleS8vsfuMCVX7+fvXArwnR9FIrbm
IiR1i9F0C1AY6C/d+kbMxoDzGqRTbZ17sof1A0G6BdQGooTC5vh+ZSmDjSyJjhKDtnBIHlQgFSYu
LOLtPs8zB4boFm32MXbEC5wSoho0ooPLLDJ9v/rOKlcbWQKsq7xrKjHI+Njj4q2UvcVh2cV/XuqT
OA3aMi7G6FFDeYkBowoKtnIt1JI2+i7ruwJyX6Bxx/JFY5aN12L3YT8q73pQ/AH+1N9SN6V/3Ywm
+luCf88CVqlC6jzE2ilSpfavD5MrtiFIdchczKKYNMaz5divjb4snATEaXkAjt9dstl9d0beGAQ4
VDAdCo1a5coTZgjUVhXrvcrABVZ1093bWpGx3PcA1GXXWPjxit56Ix6ilw4TpzNMxgfAOvzcVGo4
C0tDEJMz40jJOggdtmGa1GuI6JOMJHEX4XHUqjxksaHGxa/Hsh6MJn9PIc4FfhoVtXhVFMSmzH3c
ksvR2F7WG62g1qP33u1W5aikjRb4/9CWN0Y8lYFgAO/o55s2X0Nc8s34zzYWv5TqZGtn9i86PXuQ
dgKgRAtPmCRrFK2//poNP65rWndC2rzGZNRvLzXX2j4kVwdxeIQZDvzpJrKUTckbpAr3RVjUYxcP
usuRCMQhprZ9MoiwrDlP6a3Y8NWCcxI6fZD0qoCy6jGAnnqE1KpNS1v/Zqg7cKIkxplD6MOciJ38
GJanGxs5ZLZEw42yx2gRIi9nE3uL+kiGB8XGkZd/moSaD2BPTC6yWAqcTPxA87eWalv6O86XVu3d
8NTsuOT8v7mjONb3rCeUA7bd8q3s0Hgw9Ir04zzQsA6cbu6yCSk4mtQcr0PfrbKxJx2xLksNXven
pl/rEDimJuegCZlfODFQqCUa61ZYNYih9vj9p1/Y/kuOBcNOjgPwD85uxdm2NGFV++O1+fWvisDA
8bU80PRMO2eV2paGzgl2eJDulc9AQaKRGM2azDewNd8ETWtv6s7Or53z07EzWwlyw9haD+9NAfvR
aithLe36vS7EAbVz4MotVSYT6OwJYSIJIz7qILZOuunKiPF0TjsIjaw3U0Z1PQiUQ3gdmEWARSDD
vwR5extiH0s5Nl6hTyaPWONa6D2Y17YrGlz1VUWShP8M6R7JJvSVeKfXyMHNH7eXIoClZWNasvET
xcbI6TF1WmVSco5icfpZ0I/u4uppjAALaR3wQzEtiXKFcLcZJXPhQTvF7tFl1GJy7E1ig1Oe7BqR
Bu1iYregX2EDTdE/zfiDp3uoxm900qcsTWkr2PaGK/xnKWSKX1TUeYO/llXGohbjVXgjsSdPZgdb
Au+nZE2HUozrPYA0FdmZpoo4/lYyZzwx6FlhX6iY/vfd6GPSnz+hEhPG9dDqYh4rco31nG1epDIY
34UvRDoeRYwVPwwF1uHzC9GiU0ih3uOuYrur9NUxtf72CekDnmnsQ54Cly9ULn5j2qi6AnZjdN8Q
318RRKvbIQTwofkHChR2tB8qZy6RhnUzUg3fz4t2iI4EmRwqaEZquJE+KOBeatQm5SzVONZO2QOA
MNYSFBRSJStkOUgx4riZ2MIGuvLYckKwdM31qBqfVLPhEvR1Gwkbj2AEhW6zCaq+kj8dX3BLJq3W
V+0nbkhTO78Lkxoe7fYG8884SwoMSJv3Nq68WLyQ8qaptIQkMNJjuUmeAzacpu/kPOLHa7qPpXCU
eKSBOnc0jtAvfZ8hF5l7SniFY9IqNlQWsNG7u8OJbtMU4iCmHq4xg1S37KvlqJtN2auH/ccqLG13
358Ubag26HalmTt+fcQWDQpr/CT/+oMC0EObicm0FABiiVQedfzsH24qdhVHSPRAzr42hv26EcfE
3qZ1AoJx9tQYN3nGXDuwJhDt7maLZsVWORe5c/FSQQLPb7SxRF5u06lY68yO84sRh763phOh/Hed
WIcued9LiKLmcEY1JuRcdJ+fXFzFf74Wz6tBNfBLm/0SnxRGb2OGXk8KSmO8/giBWO5B0xIi0i4u
qcNXJ7YnjQP0s+2v8nxWZUKFYu5Nersm3GKUO96UkyrC7jG3dojWdw+Q3ngiqAcjEyHVjOQSNR01
WojZpnMXz0h6hRO9H4xt+SSA5+xQvF+qxzU9++SoOeVLQxoaDWY28ykfCxDZw81DlzGlp9kTBC/e
nu3O34E4beyMWzyxi6ZeWDsaq4yucZ6BfUdIDzovqTMnG/wCLcVAruTtC3eCy/yBtCvNkBCAPccC
FvCFSXzUALUL3chyqPC+XbSibpEHQIAtqlehhyopePcE4rUBwRnQwtGArepO7R655CFJ0d/RpNJ8
RdgPCGzERn01HevZCdPLiwI5iVDrDkiB1kSlGAakIrIw0onKe0ABGAehFdRSuGBxq2u67xwYjgQK
aXoDhQwJNDVhujEPsPoCugcffUBQB8dCPBiWRYmCaMtJgEUO4mKtOTmGSaGwFyb3WCxd0dWR7joJ
Vcor/yVgbmKpPITJ8R+3YlbdWJa0Vu1+duD0lSgKYrb9DZ/j7y80Mi7PZaAgutxSsvJdV2Dzo0wM
cHt8WfW+ARZQEvdArDsUzPgWD22e8qVxPUSQchVQnlLGO3Un7CD74jWEztn8VZv1b5d0PRN7NLDC
feiIehM+8Crx9S7E5QbiC++8PUKaTQWUTezqZGKB0A/JK/Ot/wSd/eDALzy2b7KT+QoQiABvp6Hj
HrOvnp5R5Z33q5IHbOdGHNBr40vXUpmzwxjPOaMHf6LZ9X4Xn7xuwIQC4uQ7u3FB3Tafd/17fctD
w468bMLp4faNE+gUyUW5d58lKB98RJPHEJcvhFJIYtBq9hfjn+NsWs6+kOqemU1MW8qrezRHmet0
pNXZCLBDjWK16Bj489yALG/B6EMmJWRvblsANakqx8PbCi2Pwh8NMZaBzl/A+6wQWDvpJ6uBY8IT
n5Z65EN4D/rE509AGzwL9LYEi1yg8E8WfFdOlL+cz7JniDBDepZsU+eUSV+9tP1vzKk6RSDVc1ol
EFN2Nl8Smx88yq7WqCjwm7BYLIxnbw7tcVomETIzl1e37ArtjsPrZl+vqPzWCGY5D7XvzspsiOl0
148/RHtJs60cv42XBQ5Zlc94YXQR7DN9TiOOVRCWp6lEUFWEuvbqJuKnjR5XkgOg7ZIB2qecIJ1v
zMFPXVplMR/Hvk2SNf0ulhdmI0wEBAyRi3EBS6s167Zf2uSuOHm9RwbCIJJwnySHaHa/GCWTZC94
du0vySQg79/bjRMS2kFZzK0YGYwkk1aRidwFNqqVng8qcSR1sdHxBzY9EILYpw/yeDkwMVanpuCV
5umCgHU3WPlkVSGHHED6zyXhqvAVaIn8eHyTC2i0s/clNmUVT8JXpwVJhFV1h9+JIT5Xub2lg7SY
88T5sdxojJzuoFFUSPS4Noh3uhabXpsSn01zWl//Behm9fLnwIDIdAXUpsn40Lqevml04ZGqEkvE
XHBxf4/ybXFtUe8fUeXyn3ozl9vehxe1G9BbQ8m1OAEHGJ/DCg4dQ6zQbi9crv5+gIkU7bK7Nm5X
gW2MO5wRvCv6SOT8EQgkSnGvBnA/kbEFMX5LmBjmGLYoCqwkoKnGfBLk4AY2LMCu7ZZyp/aZLhNn
CB96FsZyWRbElQEnV0tMEvH8pd2CLa3tUHqnz9O3QE8N7HQfhCEJ38aFfqZZtkGnPC+ids6THv0d
MGwHwwDPOya3zjEDqToaPm+abeE283btVdf5Jcxhijm5UVlRIf66LSAGLwY52WY6EeOYwWt/ftEK
auJ8df9yuASvtYuQ22p4nIyfMAWcBNXbwyOFTZEvLJb/xboDfClY37JKh2XkPPZ2leJKT0FMyLqM
8+LCanuwJbsEfqE+LGswH1AP4K8RW/7vafl4hKA2ekhTBf0c8+qLLgAFVh0kOcQizhPKlFK+dMWT
8WySDfTRgEAViHx6DQPJAvvhOi1DuyclF5rXQ8YL5SwEEnoq2maLbuF5EstYTdI/jt8e5ctR0T8z
zLzIOYpYZYenZfzOKRQ4mMVz8WazPze9WIUv15z7KhLY4J43AbiSfhIkeGVogzFzslgy2ICGSRzK
qvVowHl7vUtjYfbGKL2p4kntJtFmsu2oPlpn4D2W9flor2t03ZtskyxfSTFbJrKHLosW6sj6q0KA
pI/E2xJCOmnJHV4YCGXEpz7YAeRDX04dXhikaBjD7bVUa7JZhI3oYrpWGvfr1X0SUNgg8NcVgz0X
AgAtttRj1qcXimQnEqju410lGD/zVZt1Ws1/9CV82qHtDxM/oJkWbeHdKu7NbApZQHtof/YW8zNX
nVDY2sbjFWAzRRdr10YF3Htaru9nAXPc+6VAU1qxYgGfai3ZQSuDqPFndS1HgJjkJxSdswZFtCLN
puRslscPcfTr/YcxeQOaeMlH8uGnMgxjTcAT5qeNp4BcEkEPbgi2QgUvIPaSiiANM6l9lRENmeJK
4Up5yUczL/svMnaPQn9KRlW0QK+Z4NqYDvKcwRhKRwUp/K9cDF0bALtz1LIeejFcbk5JelQVGpNP
UM2XI0JZpOhieS6qP0aJIn6Eiq0MYXZ+tf+JNptVXmvWSFj9f9FD6Zc+HONOi3CPMBy88itd6bZK
l3Fkne3GOarBsgK1Fsoa0TL7Spj8CimxD2CfNYPlUQDJMpPwNKoCCLKGEm3AvH1PX7XQPnccU2E3
f53VIUuJJEhMiy3PNQSJz5MIuGmkYTBSnQJGxPbr/xN8S0xFti3C6oIu7bE6RAnpA/4179398QKe
CZsqA8AiWvKkni8ab+8ZCamUpVKu10PqxnhV+XeLrhnWgSLa+7j90RtqSx05WeBkSS+21WF4gioe
7yvTxmQwDc0CbO9baYybXPhbUDBoNobWc97pqfm8dhRjq6KrJg35gplak4rxnqAjshf3u101MwUx
xnpEiDOHo7qe1H5ggEanrK4heuuu/oCAlnJXrzAg4oM9TfyPHbs2PD/to0nNXNxcR+9YnsrHjc3i
aF70gRuzA5XyiQJifQ4xChlU+1RYxVe4D/OSla/W/6+SzKovghA9T/MBFlqdwOo8SCgrqY9n+BOB
6BmZ5Eq9dVOvo+p/HJIXVzb7ohHZmzGGlFQDw56bVvNcrPWzHeFOTlqMGvFCJWUQeI9Meswc+LF8
li5bR45aEfZp0A67E9YV2jfV2/dWOeQPBwxO2a/L986k+dNQiVdckweZ/xjth+BKeK7bHlGKICos
0pgchlgp35kZeBpLCMRfTnK84351yOer08Fyeb2qnZ+IQ8CyhClQXJUonNu0Tz3lu1jVG16TN3Aa
Xi0HuKKiGa/v+2V84J1MtDhBFe+U+zL9eNa4A5K7FqveL33500wc6CuhIZspezlBbuo437tHvQFk
hCYMa9lfLkm7XTM8uyjLjVnf8O7auD98bFRFm6J7f6YGBcCYPRozp8oYaHxm3Q3CwapFH2hiRO77
1QHCFmXfyXoT5IPNtQjt5M8dzMB8fooYDvQ5T1vbq/nt+y5sQZn/qePXyTdbKf8/3Lmd+CBjKr64
yUgxlGsQCt6T/gBd4UfbWAKWJ+ZPExOB5raN00Dh+d/tSPY60GiCO7bsFQEslP/fGw+sICtTad2P
/6w8oWXx1efDWTPbMuBV78DML0zQupyvAE/PDVz3dyU7kEtEPZ4/pck2zzLr76DL17sMt/qa+1qB
nqkNssygN57ZTbjmVyoRb7mUgeamCga58y/urSMf7ZAjDX8Ne/zsGw5ALgOz64XRBy/RnjvGqHIJ
sCqTIeUOvdgVBIyzRh+6DoVovmFvFaFl5ju005mda/45VA0MNw3ydjEngIyztR2c2b1R+LguiL1l
94cfe7zmKIekd7B6mFXLfTwjUVbJ8TigfOVySFepbmB8JbRLojFSErAa2R9q+I8P+zOpuTUfKtxK
2nEkMbahIGI12uw+oFryccyRN7Yvuf7xQt/wxhGkVUkdDcVj8E70PGGpZwlueuvJdb/VP6roa00r
MeghzlQ0UR0S7yddPAb5NbkqbppnC+DLJPGV+LeGS90XXgb8phEv5PywAC/75aw3vlMZgDdO5X6X
c5AIWyms2ZYyn7rSUy69uM00b1yUZBQzhgCl6LJIxSdk2NWCbjh1lsQdwc0I6EEsRZcma+35Or28
UGeGapGiubh6THjWu4vzMc2Dzu3IKhw8IAKG5Aa15tx41sBnzpVY2t8IF2RggFy/BU6putmCOCmK
q0OuBznL+iX1WACU50+wNVKyCDeLb9SPodxZyK1I5AnUL8KFuJahQfJY2ZnLMVE99FkbFeV+99to
1uWLu02z1KKcxfuNRgahExJLgi8QXeoKzcgnXd5X8OYJwUm4+7WGDyfJkKU+dIrL9do2M3Yf72XG
sxoC4Dw2khsbQ9oSUbspNsUydWxQU5mfazPvVFKW/S4vNuUhKUyOz9jwHYVeanhNRlUFZkKTv+Dy
gRRlAxCwjTNCuiHgxI0rEIkZZFoNvE6XK3AcbI/tQUYeqGIFC8i0yGwIeWHwdb42TU+xo9y7bilt
cc42oNdC3KBxKzktk58VQa+F0//7hNnbX3Liwh+4ncX8Y2AFsYMqILbIBl2Ku5iJrICVYR1EqhHR
yvFz/5/61Ko3X2NXk01OrhcESRUQYSpz9btTNCfPoSiesMJT6vjJ1BDfGeYL7tiF8kbokq3dmI/w
d3AI9t7aHftuIvsy3cR9IAK/9ftnfPc3bntuCvdjAwbeWPF915qSdEMqpjU54Ve+vEV0HRPF4Vmo
gNx9Wu+Ilnhp3R7nW4Y5SC65JoTfUmOVO5cS7CzFWOmVTz+sFkSFURqZLB5PFgX4iqpAS634JnKR
D6Bh8Jy3pkCboj/AmVbGEFypVi3JVZ/HaiSimQt2KcI/Nzpq1Vc3qd+Mvo0EqqQb4sSfkyqj8FGS
hn8b6h+D+312PvEfwX7SwnCfzcpM02+NlzUJQijH36ZCumZKb1yRnOzQOJ4UdKuCWETB9aizdZSV
Duk2TqrtbhJReorEgks9yxrFotpF3rWXweVTFhIC61UnrXp9p7/jgneh6bhddBq96kqVbD8y/qAG
e5pivrXoKBOE6W5rqViJ1MgMogbBY8ZdpwzeIG5Oob0gv9IJm3ioC9c2yUu6bVKwd/yH+gLdz4zt
jHYDKpUBCW/UcUGBF4QybqW8k2y7PtDRLbojBHC2UbHzQ1d8U7nRoBtg+rIAA4VoHmsrzZdnhPzX
djAfuAYNWuBXaWKoYko4TU8DNOrJ4RwoehTIBQLiZiNS0Nfl8B9ZzldJfnkG3yh4et3WZ1GQNFGJ
PaqiWY+gE1MLUdGnu41gKdO6XZc++BgbhdvTsXaG6BpQDjguWN/5tw7PrQiF0SNz2iidlT+/kmi7
x6NY3aK1idIVwaGfWz+ALzVsVV8dyrBbHU1fJm1NEcjpBJuIGLBl43uH/3/ZtQDRenwBRLbZ8cBh
Fw2R8mMkch8xDNr5x1JwdCLg28TGCo9KssUfldS7yZkUuczlRnm6LEXzUFkV1Bv96117BcpXXuHa
PdDgfsehbTuYHUfTejyIbPa19qm+XahTogCo4VM0GR/PBIEb2uwn2KP5TABlK6POfYnE6wChd2/n
A9b8hdCc3t7afcs2Glpu4sx9aBkxM1FGEJoQdyLxejvQAh8z7D7FEQENlQqoQ2AOz8vpvpKdFTMP
tXDb80geuwRfnkR5vNuAQwqUDqQfM3J4mp6i5qP8D99QPd5D/jjuTCRSvGisOHrDeXC5xkTHmLsT
f1kWhkaId8r1YSccfXjoWPOn08ZZsWTU45S/7g1yAXwF3rze+QjYFkjbyyxEsZJ2LVcXj+hpCCv5
WLgMwAqhYdtfF/ihUThNCc7SU00V+qa5Xw4CqGVXmsXER1RVsgBpbHyinMPjT6tqVhp7De7MNnmb
37DIFEhThG5F8ETT4iUtx+JnfIkn3k+a/HJ1GmScsy+KwB+LTQ/wBkIoxGFP
`protect end_protected
| gpl-3.0 | 27b5362cdfce1c72bbf39f11b3104809 | 0.953583 | 1.830294 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_fdiv_14_no_dsp_32.vhd | 4 | 12,779 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fdiv_14_no_dsp_32;
ARCHITECTURE feedforward_ap_fdiv_14_no_dsp_32_arch OF feedforward_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fdiv_14_no_dsp_32_arch;
| gpl-3.0 | d04e1847b0ddb15c38196946e4bf6e6e | 0.651929 | 3.021755 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SW_standalone/ip/design_SW_standalone_rst_processing_system7_0_100M_0/synth/design_SW_standalone_rst_processing_system7_0_100M_0.vhd | 1 | 6,968 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY design_SW_standalone_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_SW_standalone_rst_processing_system7_0_100M_0;
ARCHITECTURE design_SW_standalone_rst_processing_system7_0_100M_0_arch OF design_SW_standalone_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SW_standalone_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "design_SW_standalone_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SW_standalone_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "design_SW_standalone_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_SW_standalone_rst_processing_system7_0_100M_0_arch;
| gpl-3.0 | fdba0f4e92500789f5e2df67ec4ac8df | 0.720867 | 3.454636 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/synthesis/Top.vhd | 1 | 63,190 | -- Version: v11.4 SP1 11.4.1.17
library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;
entity vga_controller is
port( vga_controller_0_row_0 : out std_logic_vector(9 downto 1);
vga_controller_0_column_0 : out std_logic_vector(9 downto 0);
h_sync_c : out std_logic;
CLKGEN_0_GLA : in std_logic;
AND2_0_Y : in std_logic;
vga_controller_0_disp_ena : out std_logic;
v_sync_c : out std_logic;
AND2_0_Y_0 : in std_logic
);
end vga_controller;
architecture DEF_ARCH of vga_controller is
component NOR3C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component XOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR2B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR2A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN1C0
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
CLR : in std_logic := 'U';
Q : out std_logic
);
end component;
component DFN1E0C0
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
CLR : in std_logic := 'U';
E : in std_logic := 'U';
Q : out std_logic
);
end component;
component AND2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component AND3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AX1E
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OA1A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN1E1C0
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
CLR : in std_logic := 'U';
E : in std_logic := 'U';
Q : out std_logic
);
end component;
component NOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component DFN1P0
port( D : in std_logic := 'U';
CLK : in std_logic := 'U';
PRE : in std_logic := 'U';
Q : out std_logic
);
end component;
component XA1C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR3B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component GND
port( Y : out std_logic
);
end component;
component OA1C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component XNOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component OA1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component MX2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
S : in std_logic := 'U';
Y : out std_logic
);
end component;
component AO1C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component VCC
port( Y : out std_logic
);
end component;
component OAI1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR3A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR3C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR3A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AO1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AOI1B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AO1D
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR2A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR2B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR3B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component AO1A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
signal N_76_0, N_69, N_70, N_131, N_9, \h_count[1]_net_1\,
\h_count[0]_net_1\, N_7, \h_count[3]_net_1\,
\DWACT_FINC_E[0]\, N_2, \h_count[8]_net_1\,
\DWACT_FINC_E[4]\, N_9_0, \v_count[1]_net_1\,
\v_count[0]_net_1\, N_7_0, \v_count[3]_net_1\,
\DWACT_FINC_E_0[0]\, N_2_0, \v_count[8]_net_1\,
\DWACT_FINC_E_0[4]\, un17_v_count_1, \v_count_4[4]\,
\v_count_4[9]\, un20_v_countlt4, un20_v_countlt8_1,
\v_count_4[6]\, \v_count_4[5]\, un20_v_countlt8_0,
\v_count_4[7]\, \v_count_4[8]\, un16_h_count_0_2,
un16_h_count_0_a3_0_1, un16_h_count_0_a3_0_0,
un16_h_count_0_1, I_20_0, I_23_0, N_23, h_count_n7_i_0,
\h_count[7]_net_1\, \h_count[5]_net_1\,
\h_count[6]_net_1\, I_17_0, I_14_0,
un19_h_countlt3_i_a3_1, un19_h_countlt3_i_a3_0, I_12_0,
h_count_n1_i_0, h_count_n2_i_0, \h_count[2]_net_1\, I_7_0,
I_9_0, I_5_0, un2_v_countlto8_2, \v_count[7]_net_1\,
\v_count[4]_net_1\, un2_v_countlto8_1, \v_count[5]_net_1\,
\v_count[6]_net_1\, N_28, N_77, N_36, N_38, N_72, N_83,
N_40, N_73, N_84, N_86, N_127, \h_count[9]_net_1\,
h_count_n8, N_126, N_85, h_count_n9, N_128, N_129, N_34,
N_81, N_32, N_50, N_30, un2_v_countlt9, un2_v_countlto3,
\v_sync_RNO\, un16_v_countlt9, \h_sync_RNO\, N_21,
un20_v_countlto8, N_76, N_129_1, \h_count[4]_net_1\, N_26,
\h_count_3[8]\, \v_count_3[5]\, \v_count[9]_net_1\, I_14,
\v_count_3[0]\, \v_count_3[1]\, I_5, \v_count_3[2]\, I_7,
\v_count_4[0]\, \v_count_4[1]\, \v_count_4[2]\,
\v_count[2]_net_1\, \v_count_3[8]\, \v_count_3[6]\,
\v_count_3[4]\, I_23, I_17, I_12, N_5, un22_v_count,
N_132, N_4, N_8, N_12, N_19, \h_count_3[5]\,
\h_count_3[6]\, \h_count_3[4]\, N_17, I_26_0,
\v_count_3[9]\, I_26, un16_v_countlt4, \v_count_4[3]\,
\v_count_3[7]\, \v_count_3[3]\, I_20, I_9, N_10,
\DWACT_FINC_E[2]\, \DWACT_FINC_E[3]\, N_3, N_4_0, N_5_0,
\DWACT_FINC_E[1]\, N_6, N_8_0, \DWACT_FINC_E_0[2]\,
\DWACT_FINC_E_0[3]\, N_3_0, N_4_1, N_5_1,
\DWACT_FINC_E_0[1]\, N_6_0, N_8_1, \GND\, \VCC\
: std_logic;
begin
\v_count_RNIVC822[2]\ : NOR3C
port map(A => un2_v_countlto3, B => un2_v_countlto8_1, C
=> un2_v_countlto8_2, Y => un2_v_countlt9);
un4_v_count_I_17 : XOR2
port map(A => N_5_0, B => \v_count[6]_net_1\, Y => I_17);
\h_count_RNIH4V7[7]\ : NOR2B
port map(A => N_70, B => N_131, Y => N_77);
\h_count_RNIIUQV[7]\ : NOR2A
port map(A => I_26_0, B => N_76, Y => N_21);
\column_RNO[1]\ : NOR2A
port map(A => I_23_0, B => N_76, Y => \h_count_3[8]\);
\h_count[8]\ : DFN1C0
port map(D => h_count_n8, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y, Q => \h_count[8]_net_1\);
\column[0]\ : DFN1E0C0
port map(D => N_21, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y_0,
E => N_132, Q => vga_controller_0_column_0(0));
un4_v_count_I_25 : NOR2B
port map(A => \v_count[8]_net_1\, B => \DWACT_FINC_E_0[4]\,
Y => N_2_0);
un4_v_count_I_23 : XOR2
port map(A => N_3, B => \v_count[8]_net_1\, Y => I_23);
un5_h_count_I_15 : AND2
port map(A => \h_count[3]_net_1\, B => \h_count[4]_net_1\,
Y => \DWACT_FINC_E_0[1]\);
un5_h_count_I_13 : AND3
port map(A => \DWACT_FINC_E[0]\, B => \h_count[3]_net_1\, C
=> \h_count[4]_net_1\, Y => N_6_0);
\h_count_RNO[8]\ : OR3
port map(A => N_126, B => N_86, C => N_85, Y => h_count_n8);
\h_count_RNO_0[2]\ : AX1E
port map(A => \h_count[0]_net_1\, B => \h_count[1]_net_1\,
C => \h_count[2]_net_1\, Y => h_count_n2_i_0);
\v_count_RNIJEG44[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_14, Y => \v_count_3[5]\);
un4_v_count_I_15 : AND2
port map(A => \v_count[3]_net_1\, B => \v_count[4]_net_1\,
Y => \DWACT_FINC_E[1]\);
\h_count_RNIT463[9]\ : NOR2B
port map(A => \h_count[9]_net_1\, B => \h_count[8]_net_1\,
Y => N_131);
un4_v_count_I_13 : AND3
port map(A => \DWACT_FINC_E_0[0]\, B => \v_count[3]_net_1\,
C => \v_count[4]_net_1\, Y => N_6);
\row_1[4]\ : DFN1E1C0
port map(D => \v_count_4[5]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(4));
\column_RNO[9]\ : NOR2
port map(A => \h_count[0]_net_1\, B => N_76, Y => N_4);
un5_h_count_I_7 : XOR2
port map(A => N_9, B => \h_count[2]_net_1\, Y => I_7_0);
un5_h_count_I_26 : XOR2
port map(A => N_2, B => \h_count[9]_net_1\, Y => I_26_0);
un5_h_count_I_6 : NOR2B
port map(A => \h_count[1]_net_1\, B => \h_count[0]_net_1\,
Y => N_9);
\h_count_RNO_0[8]\ : NOR2
port map(A => N_73, B => \h_count[8]_net_1\, Y => N_126);
\v_count[7]\ : DFN1E1C0
port map(D => \v_count_3[7]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[7]_net_1\);
\v_count[3]\ : DFN1E1C0
port map(D => \v_count_3[3]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[3]_net_1\);
\h_count[3]\ : DFN1C0
port map(D => N_32, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> \h_count[3]_net_1\);
h_sync : DFN1P0
port map(D => \h_sync_RNO\, CLK => CLKGEN_0_GLA, PRE =>
AND2_0_Y, Q => h_sync_c);
\column_RNO[2]\ : NOR2A
port map(A => I_20_0, B => N_76, Y => N_17);
\v_count_RNI5N4BB[7]\ : NOR2B
port map(A => \v_count_4[7]\, B => \v_count_4[8]\, Y =>
un20_v_countlt8_0);
\h_count_RNO[3]\ : XA1C
port map(A => N_50, B => \h_count[3]_net_1\, C => N_77, Y
=> N_32);
\h_count[4]\ : DFN1C0
port map(D => N_34, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> \h_count[4]_net_1\);
un5_h_count_I_21 : AND2
port map(A => \h_count[6]_net_1\, B => \h_count[7]_net_1\,
Y => \DWACT_FINC_E_0[3]\);
\row_1[8]\ : DFN1E1C0
port map(D => \v_count_4[1]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(8));
\h_count_RNO_0[9]\ : NOR3B
port map(A => \h_count[9]_net_1\, B => N_69, C => N_70, Y
=> N_127);
disp_ena_RNO : NOR2A
port map(A => un22_v_count, B => N_132, Y => N_5);
\v_count_RNIJRTI[5]\ : NOR2
port map(A => \v_count[5]_net_1\, B => \v_count[6]_net_1\,
Y => un2_v_countlto8_1);
un5_h_count_I_18 : AND3
port map(A => \h_count[3]_net_1\, B => \h_count[4]_net_1\,
C => \h_count[5]_net_1\, Y => \DWACT_FINC_E_0[2]\);
un4_v_count_I_5 : XOR2
port map(A => \v_count[0]_net_1\, B => \v_count[1]_net_1\,
Y => I_5);
h_sync_RNO_6 : NOR3
port map(A => I_14_0, B => I_17_0, C => I_12_0, Y => N_23);
un5_h_count_I_19 : AND3
port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\,
C => \h_count[6]_net_1\, Y => N_4_1);
un4_v_count_I_18 : AND3
port map(A => \v_count[3]_net_1\, B => \v_count[4]_net_1\,
C => \v_count[5]_net_1\, Y => \DWACT_FINC_E[2]\);
GND_i : GND
port map(Y => \GND\);
un4_v_count_I_19 : AND3
port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\,
C => \v_count[6]_net_1\, Y => N_4_0);
\h_count_RNO_1[8]\ : NOR3B
port map(A => \h_count[8]_net_1\, B => N_69, C => N_70, Y
=> N_86);
un4_v_count_I_8 : AND3
port map(A => \v_count[0]_net_1\, B => \v_count[1]_net_1\,
C => \v_count[2]_net_1\, Y => N_8_0);
un5_h_count_I_8 : AND3
port map(A => \h_count[0]_net_1\, B => \h_count[1]_net_1\,
C => \h_count[2]_net_1\, Y => N_8_1);
\h_count_RNO_0[7]\ : OA1C
port map(A => \h_count[6]_net_1\, B => N_69, C =>
\h_count[7]_net_1\, Y => N_84);
\v_count_RNITCVD4[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_17, Y => \v_count_3[6]\);
\h_count_RNO_0[1]\ : XNOR2
port map(A => \h_count[0]_net_1\, B => \h_count[1]_net_1\,
Y => h_count_n1_i_0);
v_sync_RNO_3 : OA1
port map(A => \v_count_4[1]\, B => \v_count_4[0]\, C =>
\v_count_4[2]\, Y => un20_v_countlt4);
\v_count_RNIGQB75[6]\ : MX2
port map(A => \v_count[6]_net_1\, B => \v_count_3[6]\, S
=> N_76, Y => \v_count_4[6]\);
\h_count_RNI9FTF[7]\ : OA1A
port map(A => N_69, B => N_70, C => N_131, Y => N_76_0);
un4_v_count_I_26 : XOR2
port map(A => N_2_0, B => \v_count[9]_net_1\, Y => I_26);
\h_count_RNI9FTF_0[7]\ : OA1A
port map(A => N_69, B => N_70, C => N_131, Y => N_76);
un5_h_count_I_16 : AND3
port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[1]\,
C => \h_count[5]_net_1\, Y => N_5_1);
un4_v_count_I_7 : XOR2
port map(A => N_9_0, B => \v_count[2]_net_1\, Y => I_7);
\row_1[6]\ : DFN1E1C0
port map(D => \v_count_4[3]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(6));
v_sync_RNO_0 : AO1C
port map(A => \v_count_4[4]\, B => un16_v_countlt4, C =>
un20_v_countlto8, Y => un16_v_countlt9);
un4_v_count_I_16 : AND3
port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[1]\,
C => \v_count[5]_net_1\, Y => N_5_0);
un5_h_count_I_24 : AND3
port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\,
C => \DWACT_FINC_E_0[3]\, Y => \DWACT_FINC_E[4]\);
v_sync_RNO_1 : OR3
port map(A => \v_count_4[4]\, B => \v_count_4[9]\, C =>
un20_v_countlt4, Y => un17_v_count_1);
VCC_i : VCC
port map(Y => \VCC\);
\h_count[5]\ : DFN1C0
port map(D => N_36, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> \h_count[5]_net_1\);
\v_count_RNIQCDGL[5]\ : NOR2B
port map(A => un20_v_countlt8_1, B => un20_v_countlt8_0, Y
=> un20_v_countlto8);
v_sync_RNO_2 : OAI1
port map(A => \v_count_4[1]\, B => \v_count_4[2]\, C =>
\v_count_4[3]\, Y => un16_v_countlt4);
\h_count_RNO_2[8]\ : NOR2B
port map(A => N_129_1, B => N_73, Y => N_85);
\h_count_RNO[7]\ : NOR3A
port map(A => N_73, B => N_84, C => h_count_n7_i_0, Y =>
N_40);
\v_count_RNI381O3[1]\ : MX2
port map(A => \v_count[1]_net_1\, B => \v_count_3[1]\, S
=> N_76_0, Y => \v_count_4[1]\);
\h_count_RNO_0[4]\ : OA1C
port map(A => \h_count[3]_net_1\, B => N_50, C =>
\h_count[4]_net_1\, Y => N_81);
\row_1[7]\ : DFN1E1C0
port map(D => \v_count_4[2]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(7));
\v_count_RNIAH1R3[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_12, Y => \v_count_3[4]\);
\v_count[9]\ : DFN1E1C0
port map(D => \v_count_3[9]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[9]_net_1\);
\h_count[0]\ : DFN1C0
port map(D => N_26, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> \h_count[0]_net_1\);
\column[4]\ : DFN1E0C0
port map(D => \h_count_3[5]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y, E => N_132, Q => vga_controller_0_column_0(4));
un4_v_count_I_21 : AND2
port map(A => \v_count[6]_net_1\, B => \v_count[7]_net_1\,
Y => \DWACT_FINC_E[3]\);
un5_h_count_I_11 : NOR2B
port map(A => \h_count[3]_net_1\, B => \DWACT_FINC_E[0]\, Y
=> N_7);
\v_count_RNIRSDK4[4]\ : MX2
port map(A => \v_count[4]_net_1\, B => \v_count_3[4]\, S
=> N_76_0, Y => \v_count_4[4]\);
un5_h_count_I_20 : XOR2
port map(A => N_4_1, B => \h_count[7]_net_1\, Y => I_20_0);
\h_count_RNI5GO4[2]\ : OR3C
port map(A => \h_count[0]_net_1\, B => \h_count[1]_net_1\,
C => \h_count[2]_net_1\, Y => N_50);
\h_count_RNO[5]\ : XA1C
port map(A => N_69, B => \h_count[5]_net_1\, C => N_131, Y
=> N_36);
\column_RNO[6]\ : NOR2A
port map(A => I_9_0, B => N_76, Y => N_12);
\h_count_RNO[1]\ : NOR2
port map(A => h_count_n1_i_0, B => N_77, Y => N_28);
\h_count[2]\ : DFN1C0
port map(D => N_30, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> \h_count[2]_net_1\);
\h_count[7]\ : DFN1C0
port map(D => N_40, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> \h_count[7]_net_1\);
un4_v_count_I_11 : NOR2B
port map(A => \v_count[3]_net_1\, B => \DWACT_FINC_E_0[0]\,
Y => N_7_0);
\column_RNO[4]\ : NOR2A
port map(A => I_14_0, B => N_76, Y => \h_count_3[5]\);
v_sync : DFN1P0
port map(D => \v_sync_RNO\, CLK => CLKGEN_0_GLA, PRE =>
AND2_0_Y, Q => v_sync_c);
\v_count_RNIG66L2[0]\ : OA1C
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> \v_count[0]_net_1\, Y => \v_count_3[0]\);
h_sync_RNO_3 : OR3A
port map(A => I_20_0, B => I_23_0, C => N_23, Y =>
un16_h_count_0_1);
\column_RNO[8]\ : NOR2A
port map(A => I_5_0, B => N_76, Y => N_8);
un5_h_count_I_22 : AND3
port map(A => \DWACT_FINC_E[0]\, B => \DWACT_FINC_E_0[2]\,
C => \DWACT_FINC_E_0[3]\, Y => N_3_0);
h_sync_RNO_0 : AO1
port map(A => un16_h_count_0_a3_0_1, B =>
un16_h_count_0_a3_0_0, C => un16_h_count_0_1, Y =>
un16_h_count_0_2);
\column[3]\ : DFN1E0C0
port map(D => \h_count_3[6]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y, E => N_132, Q => vga_controller_0_column_0(3));
un4_v_count_I_9 : XOR2
port map(A => N_8_0, B => \v_count[3]_net_1\, Y => I_9);
h_sync_RNO_1 : NOR2B
port map(A => I_17_0, B => I_14_0, Y =>
un16_h_count_0_a3_0_1);
\column[9]\ : DFN1E0C0
port map(D => N_4, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, E
=> N_132, Q => vga_controller_0_column_0(9));
\v_count_RNIA3G14[2]\ : MX2
port map(A => \v_count[2]_net_1\, B => \v_count_3[2]\, S
=> N_76_0, Y => \v_count_4[2]\);
\h_count_RNO[4]\ : NOR3A
port map(A => N_69, B => N_81, C => N_77, Y => N_34);
h_sync_RNO_2 : AOI1B
port map(A => un19_h_countlt3_i_a3_1, B =>
un19_h_countlt3_i_a3_0, C => I_12_0, Y =>
un16_h_count_0_a3_0_0);
\v_count[2]\ : DFN1E1C0
port map(D => \v_count_3[2]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[2]_net_1\);
\h_count_RNO_1[7]\ : AO1D
port map(A => \h_count[7]_net_1\, B => \h_count[5]_net_1\,
C => N_131, Y => h_count_n7_i_0);
\h_count_RNO[9]\ : OR3
port map(A => N_127, B => N_128, C => N_129, Y =>
h_count_n9);
un5_h_count_I_9 : XOR2
port map(A => N_8_1, B => \h_count[3]_net_1\, Y => I_9_0);
disp_ena : DFN1C0
port map(D => N_5, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> vga_controller_0_disp_ena);
un4_v_count_I_24 : AND3
port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\,
C => \DWACT_FINC_E[3]\, Y => \DWACT_FINC_E_0[4]\);
\column[1]\ : DFN1E0C0
port map(D => \h_count_3[8]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_132, Q => vga_controller_0_column_0(1));
un5_h_count_I_14 : XOR2
port map(A => N_6_0, B => \h_count[5]_net_1\, Y => I_14_0);
\h_count_RNIT463_0[9]\ : NOR2A
port map(A => \h_count[8]_net_1\, B => \h_count[9]_net_1\,
Y => N_129_1);
\h_count_RNICANC[7]\ : OR2A
port map(A => \h_count[7]_net_1\, B => N_72, Y => N_73);
un4_v_count_I_14 : XOR2
port map(A => N_6, B => \v_count[5]_net_1\, Y => I_14);
\row_1[2]\ : DFN1E1C0
port map(D => \v_count_4[7]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(2));
\v_count_RNIDLTI[2]\ : OR2B
port map(A => \v_count[3]_net_1\, B => \v_count[2]_net_1\,
Y => un2_v_countlto3);
\v_count[8]\ : DFN1E1C0
port map(D => \v_count_3[8]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[8]_net_1\);
\v_count_RNI9S9Q5[8]\ : MX2
port map(A => \v_count[8]_net_1\, B => \v_count_3[8]\, S
=> N_76, Y => \v_count_4[8]\);
\h_count_RNIF94B[6]\ : OR3B
port map(A => \h_count[5]_net_1\, B => \h_count[6]_net_1\,
C => N_69, Y => N_72);
\v_count_RNI1ECA5[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_26, Y => \v_count_3[9]\);
un4_v_count_I_20 : XOR2
port map(A => N_4_0, B => \v_count[7]_net_1\, Y => I_20);
un5_h_count_I_10 : AND3
port map(A => \h_count[0]_net_1\, B => \h_count[1]_net_1\,
C => \h_count[2]_net_1\, Y => \DWACT_FINC_E[0]\);
un4_v_count_I_10 : AND3
port map(A => \v_count[0]_net_1\, B => \v_count[1]_net_1\,
C => \v_count[2]_net_1\, Y => \DWACT_FINC_E_0[0]\);
un24_h_count_i_o3 : OR2
port map(A => I_23_0, B => I_20_0, Y => N_19);
\row_1[9]\ : DFN1E1C0
port map(D => \v_count_4[0]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(9));
\column_RNO[3]\ : NOR2A
port map(A => I_17_0, B => N_76, Y => \h_count_3[6]\);
\column_RNO[5]\ : NOR2A
port map(A => I_12_0, B => N_76, Y => \h_count_3[4]\);
un5_h_count_I_5 : XOR2
port map(A => \h_count[0]_net_1\, B => \h_count[1]_net_1\,
Y => I_5_0);
h_sync_RNO : OR2A
port map(A => N_21, B => un16_h_count_0_2, Y =>
\h_sync_RNO\);
\h_count_RNIKVO4[7]\ : OR3
port map(A => \h_count[5]_net_1\, B => \h_count[7]_net_1\,
C => \h_count[6]_net_1\, Y => N_70);
un4_v_count_I_22 : AND3
port map(A => \DWACT_FINC_E_0[0]\, B => \DWACT_FINC_E[2]\,
C => \DWACT_FINC_E[3]\, Y => N_3);
\row_1[1]\ : DFN1E1C0
port map(D => \v_count_4[8]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(1));
un5_h_count_I_12 : XOR2
port map(A => N_7, B => \h_count[4]_net_1\, Y => I_12_0);
\v_count[5]\ : DFN1E1C0
port map(D => \v_count_3[5]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[5]_net_1\);
\h_count_RNO[6]\ : NOR3A
port map(A => N_72, B => N_83, C => N_131, Y => N_38);
\v_count_RNIRP383[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_7, Y => \v_count_3[2]\);
un4_v_count_I_12 : XOR2
port map(A => N_7_0, B => \v_count[4]_net_1\, Y => I_12);
un5_h_count_I_25 : NOR2B
port map(A => \h_count[8]_net_1\, B => \DWACT_FINC_E[4]\, Y
=> N_2);
\v_count_RNILVKU2[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_5, Y => \v_count_3[1]\);
\v_count_RNI8CEN4[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_20, Y => \v_count_3[7]\);
un5_h_count_I_23 : XOR2
port map(A => N_3_0, B => \h_count[8]_net_1\, Y => I_23_0);
\row_1[5]\ : DFN1E1C0
port map(D => \v_count_4[4]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(5));
\v_count_RNIIVUA4[3]\ : MX2
port map(A => \v_count[3]_net_1\, B => \v_count_3[3]\, S
=> N_76_0, Y => \v_count_4[3]\);
\v_count[4]\ : DFN1E1C0
port map(D => \v_count_3[4]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[4]_net_1\);
\column[6]\ : DFN1E0C0
port map(D => N_12, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, E
=> N_132, Q => vga_controller_0_column_0(6));
\h_count_RNI8LSQ1[7]\ : NOR2B
port map(A => N_19, B => N_21, Y => N_132);
\column_RNO[7]\ : NOR2A
port map(A => I_7_0, B => N_76, Y => N_10);
\column[2]\ : DFN1E0C0
port map(D => N_17, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, E
=> N_132, Q => vga_controller_0_column_0(2));
\v_count_RNILL85A[5]\ : NOR2B
port map(A => \v_count_4[6]\, B => \v_count_4[5]\, Y =>
un20_v_countlt8_1);
\v_count_RNI5RST4[5]\ : MX2
port map(A => \v_count[5]_net_1\, B => \v_count_3[5]\, S
=> N_76, Y => \v_count_4[5]\);
\v_count_RNISQQG5[7]\ : MX2
port map(A => \v_count[7]_net_1\, B => \v_count_3[7]\, S
=> N_76, Y => \v_count_4[7]\);
\h_count_RNO_1[9]\ : NOR2A
port map(A => \h_count[9]_net_1\, B => \h_count[8]_net_1\,
Y => N_128);
\column[8]\ : DFN1E0C0
port map(D => N_8, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, E
=> N_132, Q => vga_controller_0_column_0(8));
\v_count_RNI2LIH3[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_9, Y => \v_count_3[3]\);
\column[5]\ : DFN1E0C0
port map(D => \h_count_3[4]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y, E => N_132, Q => vga_controller_0_column_0(5));
\v_count_RNIHB6KR[9]\ : NOR2
port map(A => un20_v_countlto8, B => \v_count_4[9]\, Y =>
un22_v_count);
\h_count_RNO_0[6]\ : OA1C
port map(A => \h_count[5]_net_1\, B => N_69, C =>
\h_count[6]_net_1\, Y => N_83);
v_sync_RNO : AO1A
port map(A => \v_count_4[9]\, B => un16_v_countlt9, C =>
un17_v_count_1, Y => \v_sync_RNO\);
\v_count_RNINUO36[9]\ : MX2
port map(A => \v_count[9]_net_1\, B => \v_count_3[9]\, S
=> N_76, Y => \v_count_4[9]\);
\h_count[1]\ : DFN1C0
port map(D => N_28, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> \h_count[1]_net_1\);
\v_count[1]\ : DFN1E1C0
port map(D => \v_count_3[1]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[1]_net_1\);
\v_count_RNITDIE3[0]\ : MX2
port map(A => \v_count[0]_net_1\, B => \v_count_3[0]\, S
=> N_76_0, Y => \v_count_4[0]\);
\v_count_RNIVRCS[7]\ : NOR3
port map(A => \v_count[8]_net_1\, B => \v_count[7]_net_1\,
C => \v_count[4]_net_1\, Y => un2_v_countlto8_2);
\h_count_RNO_2[9]\ : NOR2A
port map(A => N_129_1, B => N_73, Y => N_129);
\v_count_RNIKCT05[9]\ : OA1A
port map(A => \v_count[9]_net_1\, B => un2_v_countlt9, C
=> I_23, Y => \v_count_3[8]\);
\row_1[3]\ : DFN1E1C0
port map(D => \v_count_4[6]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => un22_v_count, Q =>
vga_controller_0_row_0(3));
\v_count[6]\ : DFN1E1C0
port map(D => \v_count_3[6]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[6]_net_1\);
h_sync_RNO_4 : NOR2
port map(A => I_7_0, B => I_9_0, Y =>
un19_h_countlt3_i_a3_1);
h_sync_RNO_5 : NOR2A
port map(A => \h_count[0]_net_1\, B => I_5_0, Y =>
un19_h_countlt3_i_a3_0);
un4_v_count_I_6 : NOR2B
port map(A => \v_count[1]_net_1\, B => \v_count[0]_net_1\,
Y => N_9_0);
\h_count[6]\ : DFN1C0
port map(D => N_38, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, Q
=> \h_count[6]_net_1\);
\h_count_RNO[0]\ : NOR2
port map(A => \h_count[0]_net_1\, B => N_77, Y => N_26);
\h_count_RNO[2]\ : NOR2
port map(A => h_count_n2_i_0, B => N_77, Y => N_30);
\h_count[9]\ : DFN1C0
port map(D => h_count_n9, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y, Q => \h_count[9]_net_1\);
\column[7]\ : DFN1E0C0
port map(D => N_10, CLK => CLKGEN_0_GLA, CLR => AND2_0_Y, E
=> N_132, Q => vga_controller_0_column_0(7));
\h_count_RNIOAU7[4]\ : OR3B
port map(A => \h_count[3]_net_1\, B => \h_count[4]_net_1\,
C => N_50, Y => N_69);
un5_h_count_I_17 : XOR2
port map(A => N_5_1, B => \h_count[6]_net_1\, Y => I_17_0);
\v_count[0]\ : DFN1E1C0
port map(D => \v_count_3[0]\, CLK => CLKGEN_0_GLA, CLR =>
AND2_0_Y_0, E => N_76_0, Q => \v_count[0]_net_1\);
end DEF_ARCH;
library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;
entity CLKGEN is
port( CLKGEN_0_GLA : out std_logic;
CLKGEN_0_LOCK : out std_logic;
CLKA_c : in std_logic
);
end CLKGEN;
architecture DEF_ARCH of CLKGEN is
component PLL
generic (VCOFREQUENCY:real := 0.0);
port( CLKA : in std_logic := 'U';
EXTFB : in std_logic := 'U';
POWERDOWN : in std_logic := 'U';
GLA : out std_logic;
LOCK : out std_logic;
GLB : out std_logic;
YB : out std_logic;
GLC : out std_logic;
YC : out std_logic;
OADIV0 : in std_logic := 'U';
OADIV1 : in std_logic := 'U';
OADIV2 : in std_logic := 'U';
OADIV3 : in std_logic := 'U';
OADIV4 : in std_logic := 'U';
OAMUX0 : in std_logic := 'U';
OAMUX1 : in std_logic := 'U';
OAMUX2 : in std_logic := 'U';
DLYGLA0 : in std_logic := 'U';
DLYGLA1 : in std_logic := 'U';
DLYGLA2 : in std_logic := 'U';
DLYGLA3 : in std_logic := 'U';
DLYGLA4 : in std_logic := 'U';
OBDIV0 : in std_logic := 'U';
OBDIV1 : in std_logic := 'U';
OBDIV2 : in std_logic := 'U';
OBDIV3 : in std_logic := 'U';
OBDIV4 : in std_logic := 'U';
OBMUX0 : in std_logic := 'U';
OBMUX1 : in std_logic := 'U';
OBMUX2 : in std_logic := 'U';
DLYYB0 : in std_logic := 'U';
DLYYB1 : in std_logic := 'U';
DLYYB2 : in std_logic := 'U';
DLYYB3 : in std_logic := 'U';
DLYYB4 : in std_logic := 'U';
DLYGLB0 : in std_logic := 'U';
DLYGLB1 : in std_logic := 'U';
DLYGLB2 : in std_logic := 'U';
DLYGLB3 : in std_logic := 'U';
DLYGLB4 : in std_logic := 'U';
OCDIV0 : in std_logic := 'U';
OCDIV1 : in std_logic := 'U';
OCDIV2 : in std_logic := 'U';
OCDIV3 : in std_logic := 'U';
OCDIV4 : in std_logic := 'U';
OCMUX0 : in std_logic := 'U';
OCMUX1 : in std_logic := 'U';
OCMUX2 : in std_logic := 'U';
DLYYC0 : in std_logic := 'U';
DLYYC1 : in std_logic := 'U';
DLYYC2 : in std_logic := 'U';
DLYYC3 : in std_logic := 'U';
DLYYC4 : in std_logic := 'U';
DLYGLC0 : in std_logic := 'U';
DLYGLC1 : in std_logic := 'U';
DLYGLC2 : in std_logic := 'U';
DLYGLC3 : in std_logic := 'U';
DLYGLC4 : in std_logic := 'U';
FINDIV0 : in std_logic := 'U';
FINDIV1 : in std_logic := 'U';
FINDIV2 : in std_logic := 'U';
FINDIV3 : in std_logic := 'U';
FINDIV4 : in std_logic := 'U';
FINDIV5 : in std_logic := 'U';
FINDIV6 : in std_logic := 'U';
FBDIV0 : in std_logic := 'U';
FBDIV1 : in std_logic := 'U';
FBDIV2 : in std_logic := 'U';
FBDIV3 : in std_logic := 'U';
FBDIV4 : in std_logic := 'U';
FBDIV5 : in std_logic := 'U';
FBDIV6 : in std_logic := 'U';
FBDLY0 : in std_logic := 'U';
FBDLY1 : in std_logic := 'U';
FBDLY2 : in std_logic := 'U';
FBDLY3 : in std_logic := 'U';
FBDLY4 : in std_logic := 'U';
FBSEL0 : in std_logic := 'U';
FBSEL1 : in std_logic := 'U';
XDLYSEL : in std_logic := 'U';
VCOSEL0 : in std_logic := 'U';
VCOSEL1 : in std_logic := 'U';
VCOSEL2 : in std_logic := 'U'
);
end component;
component VCC
port( Y : out std_logic
);
end component;
component GND
port( Y : out std_logic
);
end component;
signal Core_GLB, Core_GLC, Core_YB, Core_YC, CLKGEN_GND,
CLKGEN_VCC : std_logic;
begin
Core : PLL
generic map(VCOFREQUENCY => 75.556)
port map(CLKA => CLKA_c, EXTFB => CLKGEN_GND, POWERDOWN =>
CLKGEN_VCC, GLA => CLKGEN_0_GLA, LOCK => CLKGEN_0_LOCK,
GLB => Core_GLB, YB => Core_YB, GLC => Core_GLC, YC =>
Core_YC, OADIV0 => CLKGEN_GND, OADIV1 => CLKGEN_VCC,
OADIV2 => CLKGEN_GND, OADIV3 => CLKGEN_GND, OADIV4 =>
CLKGEN_GND, OAMUX0 => CLKGEN_GND, OAMUX1 => CLKGEN_GND,
OAMUX2 => CLKGEN_VCC, DLYGLA0 => CLKGEN_GND, DLYGLA1 =>
CLKGEN_GND, DLYGLA2 => CLKGEN_GND, DLYGLA3 => CLKGEN_GND,
DLYGLA4 => CLKGEN_GND, OBDIV0 => CLKGEN_GND, OBDIV1 =>
CLKGEN_GND, OBDIV2 => CLKGEN_GND, OBDIV3 => CLKGEN_GND,
OBDIV4 => CLKGEN_GND, OBMUX0 => CLKGEN_GND, OBMUX1 =>
CLKGEN_GND, OBMUX2 => CLKGEN_GND, DLYYB0 => CLKGEN_GND,
DLYYB1 => CLKGEN_GND, DLYYB2 => CLKGEN_GND, DLYYB3 =>
CLKGEN_GND, DLYYB4 => CLKGEN_GND, DLYGLB0 => CLKGEN_GND,
DLYGLB1 => CLKGEN_GND, DLYGLB2 => CLKGEN_GND, DLYGLB3 =>
CLKGEN_GND, DLYGLB4 => CLKGEN_GND, OCDIV0 => CLKGEN_GND,
OCDIV1 => CLKGEN_GND, OCDIV2 => CLKGEN_GND, OCDIV3 =>
CLKGEN_GND, OCDIV4 => CLKGEN_GND, OCMUX0 => CLKGEN_GND,
OCMUX1 => CLKGEN_GND, OCMUX2 => CLKGEN_GND, DLYYC0 =>
CLKGEN_GND, DLYYC1 => CLKGEN_GND, DLYYC2 => CLKGEN_GND,
DLYYC3 => CLKGEN_GND, DLYYC4 => CLKGEN_GND, DLYGLC0 =>
CLKGEN_GND, DLYGLC1 => CLKGEN_GND, DLYGLC2 => CLKGEN_GND,
DLYGLC3 => CLKGEN_GND, DLYGLC4 => CLKGEN_GND, FINDIV0 =>
CLKGEN_GND, FINDIV1 => CLKGEN_GND, FINDIV2 => CLKGEN_GND,
FINDIV3 => CLKGEN_VCC, FINDIV4 => CLKGEN_GND, FINDIV5 =>
CLKGEN_GND, FINDIV6 => CLKGEN_GND, FBDIV0 => CLKGEN_VCC,
FBDIV1 => CLKGEN_GND, FBDIV2 => CLKGEN_GND, FBDIV3 =>
CLKGEN_GND, FBDIV4 => CLKGEN_GND, FBDIV5 => CLKGEN_VCC,
FBDIV6 => CLKGEN_GND, FBDLY0 => CLKGEN_GND, FBDLY1 =>
CLKGEN_GND, FBDLY2 => CLKGEN_GND, FBDLY3 => CLKGEN_GND,
FBDLY4 => CLKGEN_GND, FBSEL0 => CLKGEN_VCC, FBSEL1 =>
CLKGEN_GND, XDLYSEL => CLKGEN_GND, VCOSEL0 => CLKGEN_GND,
VCOSEL1 => CLKGEN_GND, VCOSEL2 => CLKGEN_VCC);
VCC_i : VCC
port map(Y => CLKGEN_VCC);
GND_i : GND
port map(Y => CLKGEN_GND);
end DEF_ARCH;
library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;
entity hw_image_generator is
port( vga_controller_0_row_0 : in std_logic_vector(9 downto 1);
vga_controller_0_column_0 : in std_logic_vector(9 downto 0);
vga_controller_0_disp_ena : in std_logic;
red_c : out std_logic;
BUTTON_1_c : in std_logic;
green_c : out std_logic;
blue_c : out std_logic
);
end hw_image_generator;
architecture DEF_ARCH of hw_image_generator is
component AO1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AOI1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR3C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OA1C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component MX2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
S : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR2B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component VCC
port( Y : out std_logic
);
end component;
component XOR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component OR2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component OA1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component OAI1
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR3A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AO1C
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR3B
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component GND
port( Y : out std_logic
);
end component;
component AXOI7
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component AO1A
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
component NOR3
port( A : in std_logic := 'U';
B : in std_logic := 'U';
C : in std_logic := 'U';
Y : out std_logic
);
end component;
signal \un45_disp_enalto7_0\, \un45_disp_enalto9_0\,
\un28_disp_ena_0\, un25_disp_ena, \un24_disp_ena_0\,
un27_disp_ena, \un38_disp_ena_0\, un39_disp_enalt8,
un37_disp_enalt8, \un48_disp_ena_0\, un29_disp_ena,
\un58_disp_ena_0\, un23_disp_enalt8, \un1_disp_ena_0\,
\un10_disp_ena\, \un18_disp_ena\, \un38_disp_ena\,
\un18_disp_ena_1\, un15_disp_enalt8, \un18_disp_ena_0\,
un17_disp_enalt8, un13_disp_enalt9, \un1_disp_ena_1_1\,
\un1_disp_ena_1_0\, \un2_disp_ena\, \un4_disp_ena\,
\un1_disp_ena_2_1\, \un58_disp_ena\, \un1_disp_ena_2_0\,
\un4_disp_ena_3\, \un4_disp_ena_1\, \un4_disp_ena_2\,
\un4_disp_ena_1_0\, \blue_8_sqmuxa_4\, \blue_8_sqmuxa_1\,
\un48_disp_ena\, \blue_8_sqmuxa_0\, \un2_disp_ena_4\,
\un2_disp_ena_0\, \un45_disp_enalto5\, \un2_disp_ena_3\,
\un2_disp_ena_2\, \un44_disp_ena_0\, un43_disp_enalt8,
\blue_8_sqmuxa\, un19_disp_ena, un45_disp_ena,
un27_disp_enalt8, un37_disp_enalto4, un27_disp_enalto6_2,
un37_disp_enalto2, un45_disp_enalt7, \un37_disp_enalto7\,
\un15_disp_enalto7\, \un25_disp_enalt6\,
un45_disp_enalto2, un15_disp_enalto4, \un1_disp_ena_3\,
\un1_disp_ena_4\, \un1_disp_ena_7\, un25_disp_enalt8,
un25_disp_enalto6, un29_disp_enalt7, un17_disp_enalto5,
\un17_disp_enalt5\, un39_disp_enalt6, un13_disp_enalt7,
\GND\, \VCC\ : std_logic;
begin
un25_disp_enalto9 : AO1
port map(A => un25_disp_enalt8, B =>
vga_controller_0_column_0(1), C =>
vga_controller_0_column_0(0), Y => un25_disp_ena);
un23_disp_enalto6 : AOI1
port map(A => un15_disp_enalto4, B =>
vga_controller_0_column_0(4), C =>
vga_controller_0_column_0(3), Y => un23_disp_enalt8);
un18_disp_ena : NOR3C
port map(A => \un18_disp_ena_0\, B => un19_disp_ena, C =>
\un18_disp_ena_1\, Y => \un18_disp_ena\);
un39_disp_enalto7 : OA1C
port map(A => un27_disp_enalto6_2, B => un39_disp_enalt6, C
=> vga_controller_0_row_0(2), Y => un39_disp_enalt8);
un58_disp_ena : NOR3C
port map(A => un45_disp_ena, B => \un44_disp_ena_0\, C =>
\un58_disp_ena_0\, Y => \un58_disp_ena\);
un15_disp_enalt7 : OR3
port map(A => vga_controller_0_column_0(3), B =>
vga_controller_0_column_0(4), C =>
vga_controller_0_column_0(2), Y => \un15_disp_enalto7\);
un29_disp_enalto5 : NOR2
port map(A => un17_disp_enalto5, B =>
vga_controller_0_row_0(6), Y => un29_disp_enalt7);
un44_disp_ena_0 : OA1C
port map(A => vga_controller_0_column_0(1), B =>
un43_disp_enalt8, C => vga_controller_0_column_0(0), Y
=> \un44_disp_ena_0\);
un15_disp_enalto7 : AO1
port map(A => un45_disp_enalto2, B => un15_disp_enalto4, C
=> \un15_disp_enalto7\, Y => un15_disp_enalt8);
un15_disp_enalt2 : OR3
port map(A => vga_controller_0_column_0(9), B =>
vga_controller_0_column_0(8), C =>
vga_controller_0_column_0(7), Y => un45_disp_enalto2);
blue : MX2
port map(A => \un1_disp_ena_4\, B => BUTTON_1_c, S =>
\blue_8_sqmuxa\, Y => blue_c);
un4_disp_ena_1 : NOR2B
port map(A => vga_controller_0_row_0(3), B =>
vga_controller_0_row_0(2), Y => \un4_disp_ena_1\);
un27_disp_enalt6_2 : NOR2B
port map(A => vga_controller_0_row_0(3), B =>
vga_controller_0_row_0(4), Y => un27_disp_enalto6_2);
red : MX2
port map(A => \un1_disp_ena_7\, B => BUTTON_1_c, S =>
\blue_8_sqmuxa\, Y => red_c);
un48_disp_ena_0 : NOR2B
port map(A => un27_disp_ena, B => un29_disp_ena, Y =>
\un48_disp_ena_0\);
un25_disp_enalto7 : AO1
port map(A => \un25_disp_enalt6\, B => un25_disp_enalto6, C
=> vga_controller_0_column_0(2), Y => un25_disp_enalt8);
VCC_i : VCC
port map(Y => \VCC\);
un1_disp_ena_1_0 : XOR2
port map(A => \un2_disp_ena\, B => \un4_disp_ena\, Y =>
\un1_disp_ena_1_0\);
un25_disp_enalto4 : AO1
port map(A => un45_disp_enalto2, B =>
vga_controller_0_column_0(6), C =>
vga_controller_0_column_0(5), Y => \un25_disp_enalt6\);
un10_disp_ena : OR2
port map(A => \un4_disp_ena\, B => \un2_disp_ena\, Y =>
\un10_disp_ena\);
un45_disp_enalt5 : OR2
port map(A => vga_controller_0_column_0(5), B =>
vga_controller_0_column_0(4), Y => \un45_disp_enalto5\);
un1_disp_ena_3 : OA1
port map(A => \un48_disp_ena\, B => \un1_disp_ena_0\, C =>
vga_controller_0_disp_ena, Y => \un1_disp_ena_3\);
un2_disp_ena_3 : NOR2B
port map(A => vga_controller_0_column_0(3), B =>
vga_controller_0_column_0(1), Y => \un2_disp_ena_3\);
un43_disp_enalto7 : NOR2
port map(A => \un15_disp_enalto7\, B => un15_disp_enalto4,
Y => un43_disp_enalt8);
un27_disp_enalto6 : NOR3C
port map(A => un37_disp_enalto4, B => un27_disp_enalto6_2,
C => un37_disp_enalto2, Y => un27_disp_enalt8);
un1_disp_ena_4 : OA1
port map(A => \un1_disp_ena_1_0\, B => \un1_disp_ena_1_1\,
C => vga_controller_0_disp_ena, Y => \un1_disp_ena_4\);
un2_disp_ena_2 : NOR2
port map(A => vga_controller_0_column_0(2), B =>
vga_controller_0_column_0(0), Y => \un2_disp_ena_2\);
un17_disp_enalt2 : OR3
port map(A => vga_controller_0_row_0(8), B =>
vga_controller_0_row_0(9), C => vga_controller_0_row_0(7),
Y => un37_disp_enalto2);
un13_disp_enalto6 : OAI1
port map(A => vga_controller_0_column_0(6), B =>
vga_controller_0_column_0(5), C => un25_disp_enalto6, Y
=> un13_disp_enalt7);
un2_disp_ena_4 : NOR3A
port map(A => \un2_disp_ena_0\, B => \un45_disp_enalto5\, C
=> vga_controller_0_column_0(6), Y => \un2_disp_ena_4\);
un13_disp_enalto8 : AO1C
port map(A => vga_controller_0_column_0(2), B =>
un13_disp_enalt7, C => vga_controller_0_column_0(1), Y
=> un13_disp_enalt9);
un18_disp_ena_1 : NOR3B
port map(A => vga_controller_0_column_0(1), B =>
un15_disp_enalt8, C => vga_controller_0_column_0(0), Y
=> \un18_disp_ena_1\);
green : MX2
port map(A => \un1_disp_ena_3\, B => BUTTON_1_c, S =>
\blue_8_sqmuxa\, Y => green_c);
un27_disp_enalt6_1 : NOR2B
port map(A => vga_controller_0_row_0(5), B =>
vga_controller_0_row_0(6), Y => un37_disp_enalto4);
un17_disp_enalto3 : NOR2B
port map(A => un37_disp_enalto2, B =>
vga_controller_0_row_0(6), Y => \un17_disp_enalt5\);
un1_disp_ena_7 : OA1
port map(A => \un1_disp_ena_2_0\, B => \un1_disp_ena_2_1\,
C => vga_controller_0_disp_ena, Y => \un1_disp_ena_7\);
blue_8_sqmuxa_4 : NOR3A
port map(A => \blue_8_sqmuxa_1\, B => \un10_disp_ena\, C
=> \un38_disp_ena\, Y => \blue_8_sqmuxa_4\);
un45_disp_enalto5 : AO1
port map(A => un45_disp_enalto2, B =>
vga_controller_0_column_0(6), C => \un45_disp_enalto5\, Y
=> un45_disp_enalt7);
un38_disp_ena : NOR3C
port map(A => un25_disp_ena, B => \un24_disp_ena_0\, C =>
\un38_disp_ena_0\, Y => \un38_disp_ena\);
un45_disp_enalto9_0 : OR2
port map(A => vga_controller_0_column_0(1), B =>
vga_controller_0_column_0(0), Y => \un45_disp_enalto9_0\);
un17_disp_enalt5 : OR2
port map(A => vga_controller_0_row_0(4), B =>
vga_controller_0_row_0(5), Y => un17_disp_enalto5);
un18_disp_ena_0 : OA1
port map(A => vga_controller_0_row_0(1), B =>
un17_disp_enalt8, C => un13_disp_enalt9, Y =>
\un18_disp_ena_0\);
GND_i : GND
port map(Y => \GND\);
un45_disp_enalto7_0 : NOR2B
port map(A => vga_controller_0_column_0(3), B =>
vga_controller_0_column_0(2), Y => \un45_disp_enalto7_0\);
un2_disp_ena : NOR3C
port map(A => \un2_disp_ena_3\, B => \un2_disp_ena_2\, C
=> \un2_disp_ena_4\, Y => \un2_disp_ena\);
un1_disp_ena_2_0 : AXOI7
port map(A => \un18_disp_ena\, B => \un2_disp_ena\, C =>
\un4_disp_ena\, Y => \un1_disp_ena_2_0\);
blue_8_sqmuxa_0 : AOI1
port map(A => \un28_disp_ena_0\, B => un29_disp_ena, C =>
\un18_disp_ena\, Y => \blue_8_sqmuxa_0\);
un1_disp_ena_1_1 : AO1
port map(A => \un28_disp_ena_0\, B => un29_disp_ena, C =>
\un38_disp_ena\, Y => \un1_disp_ena_1_1\);
un24_disp_ena_0 : OA1C
port map(A => vga_controller_0_column_0(2), B =>
un23_disp_enalt8, C => vga_controller_0_column_0(0), Y
=> \un24_disp_ena_0\);
un28_disp_ena_0 : NOR3C
port map(A => un25_disp_ena, B => \un24_disp_ena_0\, C =>
un27_disp_ena, Y => \un28_disp_ena_0\);
un25_disp_enalt6 : NOR2B
port map(A => vga_controller_0_column_0(4), B =>
vga_controller_0_column_0(3), Y => un25_disp_enalto6);
un15_disp_enalt4 : NOR2B
port map(A => vga_controller_0_column_0(5), B =>
vga_controller_0_column_0(6), Y => un15_disp_enalto4);
un27_disp_enalto8 : OR2
port map(A => un27_disp_enalt8, B =>
vga_controller_0_row_0(2), Y => un27_disp_ena);
un4_disp_ena : NOR3C
port map(A => \un4_disp_ena_2\, B => \un4_disp_ena_1_0\, C
=> \un4_disp_ena_3\, Y => \un4_disp_ena\);
un37_disp_enalt7 : OR3
port map(A => vga_controller_0_row_0(4), B =>
vga_controller_0_row_0(3), C => vga_controller_0_row_0(2),
Y => \un37_disp_enalto7\);
blue_8_sqmuxa_1 : NOR2
port map(A => \un48_disp_ena\, B => \un58_disp_ena\, Y =>
\blue_8_sqmuxa_1\);
un4_disp_ena_3 : NOR3B
port map(A => \un4_disp_ena_1\, B =>
vga_controller_0_row_0(5), C => vga_controller_0_row_0(1),
Y => \un4_disp_ena_3\);
un45_disp_enalto9 : AO1
port map(A => \un45_disp_enalto7_0\, B => un45_disp_enalt7,
C => \un45_disp_enalto9_0\, Y => un45_disp_ena);
un19_disp_enalto8 : OAI1
port map(A => un37_disp_enalto4, B => \un37_disp_enalto7\,
C => vga_controller_0_row_0(1), Y => un19_disp_ena);
un4_disp_ena_2 : NOR3A
port map(A => vga_controller_0_row_0(4), B =>
vga_controller_0_row_0(8), C => vga_controller_0_row_0(9),
Y => \un4_disp_ena_2\);
un48_disp_ena : NOR3C
port map(A => un45_disp_ena, B => \un44_disp_ena_0\, C =>
\un48_disp_ena_0\, Y => \un48_disp_ena\);
un1_disp_ena_0 : AO1A
port map(A => \un10_disp_ena\, B => \un18_disp_ena\, C =>
\un38_disp_ena\, Y => \un1_disp_ena_0\);
un17_disp_enalto7 : OA1
port map(A => un17_disp_enalto5, B => \un17_disp_enalt5\, C
=> \un4_disp_ena_1\, Y => un17_disp_enalt8);
un2_disp_ena_0 : NOR3
port map(A => vga_controller_0_column_0(9), B =>
vga_controller_0_column_0(8), C =>
vga_controller_0_column_0(7), Y => \un2_disp_ena_0\);
un37_disp_enalto7 : AO1
port map(A => un37_disp_enalto4, B => un37_disp_enalto2, C
=> \un37_disp_enalto7\, Y => un37_disp_enalt8);
blue_8_sqmuxa : NOR3C
port map(A => \blue_8_sqmuxa_0\, B =>
vga_controller_0_disp_ena, C => \blue_8_sqmuxa_4\, Y =>
\blue_8_sqmuxa\);
un38_disp_ena_0 : NOR3C
port map(A => un39_disp_enalt8, B =>
vga_controller_0_row_0(1), C => un37_disp_enalt8, Y =>
\un38_disp_ena_0\);
un58_disp_ena_0 : NOR3C
port map(A => vga_controller_0_row_0(1), B =>
un37_disp_enalt8, C => un39_disp_enalt8, Y =>
\un58_disp_ena_0\);
un39_disp_enalto4 : NOR2
port map(A => vga_controller_0_row_0(5), B =>
vga_controller_0_row_0(6), Y => un39_disp_enalt6);
un1_disp_ena_2_1 : AO1
port map(A => \un28_disp_ena_0\, B => un29_disp_ena, C =>
\un58_disp_ena\, Y => \un1_disp_ena_2_1\);
un29_disp_enalto8 : OA1C
port map(A => \un4_disp_ena_1\, B => un29_disp_enalt7, C
=> vga_controller_0_row_0(1), Y => un29_disp_ena);
un4_disp_ena_1_0 : NOR2
port map(A => vga_controller_0_row_0(7), B =>
vga_controller_0_row_0(6), Y => \un4_disp_ena_1_0\);
end DEF_ARCH;
library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;
entity Top is
port( BUTTON_1 : in std_logic;
CLKA : in std_logic;
NSYSRESET : in std_logic;
PAD : in std_logic;
blue : out std_logic;
green : out std_logic;
h_sync : out std_logic;
red : out std_logic;
v_sync : out std_logic
);
end Top;
architecture DEF_ARCH of Top is
component AND2
port( A : in std_logic := 'U';
B : in std_logic := 'U';
Y : out std_logic
);
end component;
component INBUF
port( PAD : in std_logic := 'U';
Y : out std_logic
);
end component;
component OUTBUF
port( D : in std_logic := 'U';
PAD : out std_logic
);
end component;
component INBUF_FF
port( PAD : in std_logic := 'U';
Y : out std_logic
);
end component;
component vga_controller
port( vga_controller_0_row_0 : out std_logic_vector(9 downto 1);
vga_controller_0_column_0 : out std_logic_vector(9 downto 0);
h_sync_c : out std_logic;
CLKGEN_0_GLA : in std_logic := 'U';
AND2_0_Y : in std_logic := 'U';
vga_controller_0_disp_ena : out std_logic;
v_sync_c : out std_logic;
AND2_0_Y_0 : in std_logic := 'U'
);
end component;
component CLKGEN
port( CLKGEN_0_GLA : out std_logic;
CLKGEN_0_LOCK : out std_logic;
CLKA_c : in std_logic := 'U'
);
end component;
component VCC
port( Y : out std_logic
);
end component;
component hw_image_generator
port( vga_controller_0_row_0 : in std_logic_vector(9 downto 1) := (others => 'U');
vga_controller_0_column_0 : in std_logic_vector(9 downto 0) := (others => 'U');
vga_controller_0_disp_ena : in std_logic := 'U';
red_c : out std_logic;
BUTTON_1_c : in std_logic := 'U';
green_c : out std_logic;
blue_c : out std_logic
);
end component;
component GND
port( Y : out std_logic
);
end component;
attribute syn_noprune : boolean;
attribute syn_noprune of INBUF_FF: component is true;
signal CLKGEN_0_LOCK, AND2_0_Y, CLKGEN_0_GLA,
vga_controller_0_disp_ena, \vga_controller_0_column_0[9]\,
\vga_controller_0_column_0[8]\,
\vga_controller_0_column_0[7]\,
\vga_controller_0_column_0[6]\,
\vga_controller_0_column_0[5]\,
\vga_controller_0_column_0[4]\,
\vga_controller_0_column_0[3]\,
\vga_controller_0_column_0[2]\,
\vga_controller_0_column_0[1]\,
\vga_controller_0_column_0[0]\,
\vga_controller_0_row_0[9]\, \vga_controller_0_row_0[8]\,
\vga_controller_0_row_0[7]\, \vga_controller_0_row_0[6]\,
\vga_controller_0_row_0[5]\, \vga_controller_0_row_0[4]\,
\vga_controller_0_row_0[3]\, \vga_controller_0_row_0[2]\,
\vga_controller_0_row_0[1]\, \INBUF_FF_0\, \VCC\, \GND\,
BUTTON_1_c, CLKA_c, NSYSRESET_c, blue_c, green_c,
h_sync_c, red_c, v_sync_c, AND2_0_Y_0 : std_logic;
for all : vga_controller
Use entity work.vga_controller(DEF_ARCH);
for all : CLKGEN
Use entity work.CLKGEN(DEF_ARCH);
for all : hw_image_generator
Use entity work.hw_image_generator(DEF_ARCH);
begin
AND2_0_0 : AND2
port map(A => NSYSRESET_c, B => CLKGEN_0_LOCK, Y =>
AND2_0_Y_0);
NSYSRESET_pad : INBUF
port map(PAD => NSYSRESET, Y => NSYSRESET_c);
blue_pad : OUTBUF
port map(D => blue_c, PAD => blue);
INBUF_FF_0 : INBUF_FF
port map(PAD => PAD, Y => \INBUF_FF_0\);
vga_controller_0 : vga_controller
port map(vga_controller_0_row_0(9) =>
\vga_controller_0_row_0[9]\, vga_controller_0_row_0(8)
=> \vga_controller_0_row_0[8]\,
vga_controller_0_row_0(7) => \vga_controller_0_row_0[7]\,
vga_controller_0_row_0(6) => \vga_controller_0_row_0[6]\,
vga_controller_0_row_0(5) => \vga_controller_0_row_0[5]\,
vga_controller_0_row_0(4) => \vga_controller_0_row_0[4]\,
vga_controller_0_row_0(3) => \vga_controller_0_row_0[3]\,
vga_controller_0_row_0(2) => \vga_controller_0_row_0[2]\,
vga_controller_0_row_0(1) => \vga_controller_0_row_0[1]\,
vga_controller_0_column_0(9) =>
\vga_controller_0_column_0[9]\,
vga_controller_0_column_0(8) =>
\vga_controller_0_column_0[8]\,
vga_controller_0_column_0(7) =>
\vga_controller_0_column_0[7]\,
vga_controller_0_column_0(6) =>
\vga_controller_0_column_0[6]\,
vga_controller_0_column_0(5) =>
\vga_controller_0_column_0[5]\,
vga_controller_0_column_0(4) =>
\vga_controller_0_column_0[4]\,
vga_controller_0_column_0(3) =>
\vga_controller_0_column_0[3]\,
vga_controller_0_column_0(2) =>
\vga_controller_0_column_0[2]\,
vga_controller_0_column_0(1) =>
\vga_controller_0_column_0[1]\,
vga_controller_0_column_0(0) =>
\vga_controller_0_column_0[0]\, h_sync_c => h_sync_c,
CLKGEN_0_GLA => CLKGEN_0_GLA, AND2_0_Y => AND2_0_Y,
vga_controller_0_disp_ena => vga_controller_0_disp_ena,
v_sync_c => v_sync_c, AND2_0_Y_0 => AND2_0_Y_0);
CLKGEN_0 : CLKGEN
port map(CLKGEN_0_GLA => CLKGEN_0_GLA, CLKGEN_0_LOCK =>
CLKGEN_0_LOCK, CLKA_c => CLKA_c);
BUTTON_1_pad : INBUF
port map(PAD => BUTTON_1, Y => BUTTON_1_c);
green_pad : OUTBUF
port map(D => green_c, PAD => green);
VCC_i : VCC
port map(Y => \VCC\);
hw_image_generator_0 : hw_image_generator
port map(vga_controller_0_row_0(9) =>
\vga_controller_0_row_0[9]\, vga_controller_0_row_0(8)
=> \vga_controller_0_row_0[8]\,
vga_controller_0_row_0(7) => \vga_controller_0_row_0[7]\,
vga_controller_0_row_0(6) => \vga_controller_0_row_0[6]\,
vga_controller_0_row_0(5) => \vga_controller_0_row_0[5]\,
vga_controller_0_row_0(4) => \vga_controller_0_row_0[4]\,
vga_controller_0_row_0(3) => \vga_controller_0_row_0[3]\,
vga_controller_0_row_0(2) => \vga_controller_0_row_0[2]\,
vga_controller_0_row_0(1) => \vga_controller_0_row_0[1]\,
vga_controller_0_column_0(9) =>
\vga_controller_0_column_0[9]\,
vga_controller_0_column_0(8) =>
\vga_controller_0_column_0[8]\,
vga_controller_0_column_0(7) =>
\vga_controller_0_column_0[7]\,
vga_controller_0_column_0(6) =>
\vga_controller_0_column_0[6]\,
vga_controller_0_column_0(5) =>
\vga_controller_0_column_0[5]\,
vga_controller_0_column_0(4) =>
\vga_controller_0_column_0[4]\,
vga_controller_0_column_0(3) =>
\vga_controller_0_column_0[3]\,
vga_controller_0_column_0(2) =>
\vga_controller_0_column_0[2]\,
vga_controller_0_column_0(1) =>
\vga_controller_0_column_0[1]\,
vga_controller_0_column_0(0) =>
\vga_controller_0_column_0[0]\, vga_controller_0_disp_ena
=> vga_controller_0_disp_ena, red_c => red_c, BUTTON_1_c
=> BUTTON_1_c, green_c => green_c, blue_c => blue_c);
CLKA_pad : INBUF
port map(PAD => CLKA, Y => CLKA_c);
h_sync_pad : OUTBUF
port map(D => h_sync_c, PAD => h_sync);
AND2_0 : AND2
port map(A => NSYSRESET_c, B => CLKGEN_0_LOCK, Y =>
AND2_0_Y);
GND_i : GND
port map(Y => \GND\);
v_sync_pad : OUTBUF
port map(D => v_sync_c, PAD => v_sync);
red_pad : OUTBUF
port map(D => red_c, PAD => red);
end DEF_ARCH;
| gpl-2.0 | 0c5de67ffddc8595a1266821bfca3286 | 0.473793 | 2.650365 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_fmul_2_max_dsp_32.vhd | 4 | 12,777 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fmul_2_max_dsp_32;
ARCHITECTURE feedforward_ap_fmul_2_max_dsp_32_arch OF feedforward_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fmul_2_max_dsp_32_arch;
| gpl-3.0 | 82f7ca04d35bf362f76b0845f72e24f4 | 0.651874 | 3.021282 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/stimulus/last.vhd | 1 | 2,039 | --------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: last.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::IGLOO> <Die::AGLN250V2Z> <Package::100 VQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity last is
end last;
architecture behavioral of last is
constant SYSCLK_PERIOD : time := 50 ns;
signal SYSCLK : std_logic := '0';
signal NSYSRESET : std_logic := '0';
component Top
-- ports
port(
-- Inputs
CLKA : in std_logic;
PAD : in std_logic;
NSYSRESET : in std_logic;
BUTTON_1 : in std_logic;
-- Outputs
v_sync : out std_logic;
h_sync : out std_logic;
blue : out std_logic;
red : out std_logic;
green : out std_logic
-- Inouts
);
end component;
begin
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 10 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- 10MHz Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
-- Instantiate Unit Under Test: Top
Top_0 : Top
-- port map
port map(
-- Inputs
CLKA => SYSCLK,
PAD => '0',
NSYSRESET => NSYSRESET,
BUTTON_1 => '1',
-- Outputs
v_sync => open,
h_sync => open,
blue => open,
red => open,
green => open
-- Inouts
);
end behavioral;
| gpl-2.0 | ada86200810f4074cdfab6b356f9cc37 | 0.43796 | 4.422993 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_fptrunc_64ns_32_1.vhd | 4 | 1,982 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_fptrunc_64ns_32_1 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
dout_WIDTH : integer := 32
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_fptrunc_64ns_32_1 is
--------------------- Component ---------------------
component feedforward_ap_fptrunc_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_fptrunc_0_no_dsp_64_u : component feedforward_ap_fptrunc_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
| gpl-3.0 | 6e80a46c49ae4d6656afcce455bb139a | 0.501009 | 3.73258 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SWandHW_standalone/hdl/design_SWandHW_standalone.vhd | 1 | 349,801 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Thu Sep 01 14:49:08 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SWandHW_standalone.bd
--Design : design_SWandHW_standalone
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1MVOGV6 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_1MVOGV6;
architecture STRUCTURE of m00_couplers_imp_1MVOGV6 is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_3Z6JOL is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_3Z6JOL;
architecture STRUCTURE of m00_couplers_imp_3Z6JOL is
component design_SWandHW_standalone_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_SWandHW_standalone_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal auto_pc_to_m00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_m00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_m00_couplers_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_m00_couplers_WLAST : STD_LOGIC;
signal auto_pc_to_m00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_m00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal m00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal m00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal m00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal m00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_m00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_m00_couplers_ARCACHE(3 downto 0);
M_AXI_arid(2 downto 0) <= auto_pc_to_m00_couplers_ARID(2 downto 0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_m00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_m00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_m00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_m00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_m00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= auto_pc_to_m00_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= auto_pc_to_m00_couplers_AWCACHE(3 downto 0);
M_AXI_awid(2 downto 0) <= auto_pc_to_m00_couplers_AWID(2 downto 0);
M_AXI_awlen(3 downto 0) <= auto_pc_to_m00_couplers_AWLEN(3 downto 0);
M_AXI_awlock(1 downto 0) <= auto_pc_to_m00_couplers_AWLOCK(1 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awqos(3 downto 0) <= auto_pc_to_m00_couplers_AWQOS(3 downto 0);
M_AXI_awsize(2 downto 0) <= auto_pc_to_m00_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= auto_pc_to_m00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_m00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wid(2 downto 0) <= auto_pc_to_m00_couplers_WID(2 downto 0);
M_AXI_wlast <= auto_pc_to_m00_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= auto_pc_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_m00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= m00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= m00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(2 downto 0) <= m00_couplers_to_auto_pc_BID(2 downto 0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(2 downto 0) <= m00_couplers_to_auto_pc_RID(2 downto 0);
S_AXI_rlast <= m00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= m00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= m00_couplers_to_auto_pc_WREADY;
auto_pc_to_m00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_m00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_m00_couplers_BID(5 downto 0) <= M_AXI_bid(5 downto 0);
auto_pc_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_m00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_m00_couplers_RID(5 downto 0) <= M_AXI_rid(5 downto 0);
auto_pc_to_m00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_m00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_m00_couplers_WREADY <= M_AXI_wready;
m00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
m00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
m00_couplers_to_auto_pc_ARID(2 downto 0) <= S_AXI_arid(2 downto 0);
m00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
m00_couplers_to_auto_pc_ARLOCK(0) <= S_AXI_arlock(0);
m00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
m00_couplers_to_auto_pc_ARREGION(3 downto 0) <= S_AXI_arregion(3 downto 0);
m00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
m00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
m00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
m00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
m00_couplers_to_auto_pc_AWID(2 downto 0) <= S_AXI_awid(2 downto 0);
m00_couplers_to_auto_pc_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
m00_couplers_to_auto_pc_AWLOCK(0) <= S_AXI_awlock(0);
m00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
m00_couplers_to_auto_pc_AWREGION(3 downto 0) <= S_AXI_awregion(3 downto 0);
m00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
m00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
m00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
m00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
m00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
m00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_SWandHW_standalone_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(2 downto 0) => auto_pc_to_m00_couplers_ARID(2 downto 0),
m_axi_arlen(3 downto 0) => auto_pc_to_m00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_m00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_m00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_m00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => auto_pc_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => auto_pc_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(2 downto 0) => auto_pc_to_m00_couplers_AWID(2 downto 0),
m_axi_awlen(3 downto 0) => auto_pc_to_m00_couplers_AWLEN(3 downto 0),
m_axi_awlock(1 downto 0) => auto_pc_to_m00_couplers_AWLOCK(1 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => auto_pc_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready => auto_pc_to_m00_couplers_AWREADY,
m_axi_awsize(2 downto 0) => auto_pc_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid => auto_pc_to_m00_couplers_AWVALID,
m_axi_bid(2 downto 0) => auto_pc_to_m00_couplers_BID(2 downto 0),
m_axi_bready => auto_pc_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(2 downto 0) => auto_pc_to_m00_couplers_RID(2 downto 0),
m_axi_rlast => auto_pc_to_m00_couplers_RLAST,
m_axi_rready => auto_pc_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_m00_couplers_WDATA(31 downto 0),
m_axi_wid(2 downto 0) => auto_pc_to_m00_couplers_WID(2 downto 0),
m_axi_wlast => auto_pc_to_m00_couplers_WLAST,
m_axi_wready => auto_pc_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_m00_couplers_WVALID,
s_axi_araddr(31 downto 0) => m00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => m00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => m00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(2 downto 0) => m00_couplers_to_auto_pc_ARID(2 downto 0),
s_axi_arlen(7 downto 0) => m00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => m00_couplers_to_auto_pc_ARLOCK(0),
s_axi_arprot(2 downto 0) => m00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => m00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => m00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => m00_couplers_to_auto_pc_ARREGION(3 downto 0),
s_axi_arsize(2 downto 0) => m00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => m00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => m00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => m00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => m00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(2 downto 0) => m00_couplers_to_auto_pc_AWID(2 downto 0),
s_axi_awlen(7 downto 0) => m00_couplers_to_auto_pc_AWLEN(7 downto 0),
s_axi_awlock(0) => m00_couplers_to_auto_pc_AWLOCK(0),
s_axi_awprot(2 downto 0) => m00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => m00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => m00_couplers_to_auto_pc_AWREADY,
s_axi_awregion(3 downto 0) => m00_couplers_to_auto_pc_AWREGION(3 downto 0),
s_axi_awsize(2 downto 0) => m00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => m00_couplers_to_auto_pc_AWVALID,
s_axi_bid(2 downto 0) => m00_couplers_to_auto_pc_BID(2 downto 0),
s_axi_bready => m00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(2 downto 0) => m00_couplers_to_auto_pc_RID(2 downto 0),
s_axi_rlast => m00_couplers_to_auto_pc_RLAST,
s_axi_rready => m00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wlast => m00_couplers_to_auto_pc_WLAST,
s_axi_wready => m00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_7OD9KA is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_7OD9KA;
architecture STRUCTURE of m01_couplers_imp_7OD9KA is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1432F1V is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_1432F1V;
architecture STRUCTURE of m02_couplers_imp_1432F1V is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_QLWQRF is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_QLWQRF;
architecture STRUCTURE of m03_couplers_imp_QLWQRF is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_PPSTKW is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_PPSTKW;
architecture STRUCTURE of m04_couplers_imp_PPSTKW is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_14U9M2W is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_14U9M2W;
architecture STRUCTURE of m05_couplers_imp_14U9M2W is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m06_couplers_imp_6WKA35 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wvalid : in STD_LOGIC
);
end m06_couplers_imp_6WKA35;
architecture STRUCTURE of m06_couplers_imp_6WKA35 is
signal m06_couplers_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_ARREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_ARVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_AWREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_AWVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_BVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_RREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_m06_couplers_RVALID : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_m06_couplers_WREADY : STD_LOGIC;
signal m06_couplers_to_m06_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m06_couplers_to_m06_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m06_couplers_to_m06_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m06_couplers_to_m06_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m06_couplers_to_m06_couplers_AWVALID;
M_AXI_bready <= m06_couplers_to_m06_couplers_BREADY;
M_AXI_rready <= m06_couplers_to_m06_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m06_couplers_to_m06_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m06_couplers_to_m06_couplers_WVALID;
S_AXI_arready <= m06_couplers_to_m06_couplers_ARREADY;
S_AXI_awready <= m06_couplers_to_m06_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m06_couplers_to_m06_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m06_couplers_to_m06_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m06_couplers_to_m06_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m06_couplers_to_m06_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m06_couplers_to_m06_couplers_RVALID;
S_AXI_wready <= m06_couplers_to_m06_couplers_WREADY;
m06_couplers_to_m06_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m06_couplers_to_m06_couplers_ARREADY <= M_AXI_arready;
m06_couplers_to_m06_couplers_ARVALID <= S_AXI_arvalid;
m06_couplers_to_m06_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m06_couplers_to_m06_couplers_AWREADY <= M_AXI_awready;
m06_couplers_to_m06_couplers_AWVALID <= S_AXI_awvalid;
m06_couplers_to_m06_couplers_BREADY <= S_AXI_bready;
m06_couplers_to_m06_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m06_couplers_to_m06_couplers_BVALID <= M_AXI_bvalid;
m06_couplers_to_m06_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m06_couplers_to_m06_couplers_RREADY <= S_AXI_rready;
m06_couplers_to_m06_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m06_couplers_to_m06_couplers_RVALID <= M_AXI_rvalid;
m06_couplers_to_m06_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m06_couplers_to_m06_couplers_WREADY <= M_AXI_wready;
m06_couplers_to_m06_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_14GRHI is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end s00_couplers_imp_14GRHI;
architecture STRUCTURE of s00_couplers_imp_14GRHI is
signal s00_couplers_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= s00_couplers_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s00_couplers_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s00_couplers_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s00_couplers_to_s00_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s00_couplers_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s00_couplers_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid(0) <= s00_couplers_to_s00_couplers_ARVALID(0);
M_AXI_rready(0) <= s00_couplers_to_s00_couplers_RREADY(0);
S_AXI_arready(0) <= s00_couplers_to_s00_couplers_ARREADY(0);
S_AXI_rdata(31 downto 0) <= s00_couplers_to_s00_couplers_RDATA(31 downto 0);
S_AXI_rlast(0) <= s00_couplers_to_s00_couplers_RLAST(0);
S_AXI_rresp(1 downto 0) <= s00_couplers_to_s00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= s00_couplers_to_s00_couplers_RVALID(0);
s00_couplers_to_s00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_s00_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_s00_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_s00_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_s00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_s00_couplers_ARREADY(0) <= M_AXI_arready(0);
s00_couplers_to_s00_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_s00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
s00_couplers_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s00_couplers_to_s00_couplers_RLAST(0) <= M_AXI_rlast(0);
s00_couplers_to_s00_couplers_RREADY(0) <= S_AXI_rready(0);
s00_couplers_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s00_couplers_to_s00_couplers_RVALID(0) <= M_AXI_rvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1PPRTY9 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1PPRTY9;
architecture STRUCTURE of s00_couplers_imp_1PPRTY9 is
component design_SWandHW_standalone_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_SWandHW_standalone_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_SWandHW_standalone_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s01_couplers_imp_1KHG2CU is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s01_couplers_imp_1KHG2CU;
architecture STRUCTURE of s01_couplers_imp_1KHG2CU is
signal s01_couplers_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_s01_couplers_AWVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_s01_couplers_BVALID : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_s01_couplers_WLAST : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WREADY : STD_LOGIC;
signal s01_couplers_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_s01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_awaddr(31 downto 0) <= s01_couplers_to_s01_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s01_couplers_to_s01_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s01_couplers_to_s01_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= s01_couplers_to_s01_couplers_AWLEN(7 downto 0);
M_AXI_awprot(2 downto 0) <= s01_couplers_to_s01_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= s01_couplers_to_s01_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= s01_couplers_to_s01_couplers_AWVALID;
M_AXI_bready <= s01_couplers_to_s01_couplers_BREADY;
M_AXI_wdata(31 downto 0) <= s01_couplers_to_s01_couplers_WDATA(31 downto 0);
M_AXI_wlast <= s01_couplers_to_s01_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= s01_couplers_to_s01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s01_couplers_to_s01_couplers_WVALID;
S_AXI_awready <= s01_couplers_to_s01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s01_couplers_to_s01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s01_couplers_to_s01_couplers_BVALID;
S_AXI_wready <= s01_couplers_to_s01_couplers_WREADY;
s01_couplers_to_s01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s01_couplers_to_s01_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s01_couplers_to_s01_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s01_couplers_to_s01_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s01_couplers_to_s01_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s01_couplers_to_s01_couplers_AWREADY <= M_AXI_awready;
s01_couplers_to_s01_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s01_couplers_to_s01_couplers_AWVALID <= S_AXI_awvalid;
s01_couplers_to_s01_couplers_BREADY <= S_AXI_bready;
s01_couplers_to_s01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s01_couplers_to_s01_couplers_BVALID <= M_AXI_bvalid;
s01_couplers_to_s01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s01_couplers_to_s01_couplers_WLAST <= S_AXI_wlast;
s01_couplers_to_s01_couplers_WREADY <= M_AXI_wready;
s01_couplers_to_s01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s01_couplers_to_s01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s02_couplers_imp_HTS99Z is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s02_couplers_imp_HTS99Z;
architecture STRUCTURE of s02_couplers_imp_HTS99Z is
signal s02_couplers_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_s02_couplers_ARREADY : STD_LOGIC;
signal s02_couplers_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_s02_couplers_ARVALID : STD_LOGIC;
signal s02_couplers_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_s02_couplers_RLAST : STD_LOGIC;
signal s02_couplers_to_s02_couplers_RREADY : STD_LOGIC;
signal s02_couplers_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_s02_couplers_RVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s02_couplers_to_s02_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s02_couplers_to_s02_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s02_couplers_to_s02_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s02_couplers_to_s02_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s02_couplers_to_s02_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s02_couplers_to_s02_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= s02_couplers_to_s02_couplers_ARVALID;
M_AXI_rready <= s02_couplers_to_s02_couplers_RREADY;
S_AXI_arready <= s02_couplers_to_s02_couplers_ARREADY;
S_AXI_rdata(31 downto 0) <= s02_couplers_to_s02_couplers_RDATA(31 downto 0);
S_AXI_rlast <= s02_couplers_to_s02_couplers_RLAST;
S_AXI_rresp(1 downto 0) <= s02_couplers_to_s02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s02_couplers_to_s02_couplers_RVALID;
s02_couplers_to_s02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s02_couplers_to_s02_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s02_couplers_to_s02_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s02_couplers_to_s02_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s02_couplers_to_s02_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s02_couplers_to_s02_couplers_ARREADY <= M_AXI_arready;
s02_couplers_to_s02_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s02_couplers_to_s02_couplers_ARVALID <= S_AXI_arvalid;
s02_couplers_to_s02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s02_couplers_to_s02_couplers_RLAST <= M_AXI_rlast;
s02_couplers_to_s02_couplers_RREADY <= S_AXI_rready;
s02_couplers_to_s02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s02_couplers_to_s02_couplers_RVALID <= M_AXI_rvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s03_couplers_imp_13X1ZY7 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wlast : out STD_LOGIC;
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s03_couplers_imp_13X1ZY7;
architecture STRUCTURE of s03_couplers_imp_13X1ZY7 is
signal s03_couplers_to_s03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_s03_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_s03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_s03_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s03_couplers_to_s03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_s03_couplers_AWREADY : STD_LOGIC;
signal s03_couplers_to_s03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_s03_couplers_AWVALID : STD_LOGIC;
signal s03_couplers_to_s03_couplers_BREADY : STD_LOGIC;
signal s03_couplers_to_s03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_s03_couplers_BVALID : STD_LOGIC;
signal s03_couplers_to_s03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_s03_couplers_WLAST : STD_LOGIC;
signal s03_couplers_to_s03_couplers_WREADY : STD_LOGIC;
signal s03_couplers_to_s03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_s03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_awaddr(31 downto 0) <= s03_couplers_to_s03_couplers_AWADDR(31 downto 0);
M_AXI_awburst(1 downto 0) <= s03_couplers_to_s03_couplers_AWBURST(1 downto 0);
M_AXI_awcache(3 downto 0) <= s03_couplers_to_s03_couplers_AWCACHE(3 downto 0);
M_AXI_awlen(7 downto 0) <= s03_couplers_to_s03_couplers_AWLEN(7 downto 0);
M_AXI_awprot(2 downto 0) <= s03_couplers_to_s03_couplers_AWPROT(2 downto 0);
M_AXI_awsize(2 downto 0) <= s03_couplers_to_s03_couplers_AWSIZE(2 downto 0);
M_AXI_awvalid <= s03_couplers_to_s03_couplers_AWVALID;
M_AXI_bready <= s03_couplers_to_s03_couplers_BREADY;
M_AXI_wdata(31 downto 0) <= s03_couplers_to_s03_couplers_WDATA(31 downto 0);
M_AXI_wlast <= s03_couplers_to_s03_couplers_WLAST;
M_AXI_wstrb(3 downto 0) <= s03_couplers_to_s03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= s03_couplers_to_s03_couplers_WVALID;
S_AXI_awready <= s03_couplers_to_s03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= s03_couplers_to_s03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= s03_couplers_to_s03_couplers_BVALID;
S_AXI_wready <= s03_couplers_to_s03_couplers_WREADY;
s03_couplers_to_s03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s03_couplers_to_s03_couplers_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s03_couplers_to_s03_couplers_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s03_couplers_to_s03_couplers_AWLEN(7 downto 0) <= S_AXI_awlen(7 downto 0);
s03_couplers_to_s03_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s03_couplers_to_s03_couplers_AWREADY <= M_AXI_awready;
s03_couplers_to_s03_couplers_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s03_couplers_to_s03_couplers_AWVALID <= S_AXI_awvalid;
s03_couplers_to_s03_couplers_BREADY <= S_AXI_bready;
s03_couplers_to_s03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
s03_couplers_to_s03_couplers_BVALID <= M_AXI_bvalid;
s03_couplers_to_s03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s03_couplers_to_s03_couplers_WLAST <= S_AXI_wlast;
s03_couplers_to_s03_couplers_WREADY <= M_AXI_wready;
s03_couplers_to_s03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s03_couplers_to_s03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s04_couplers_imp_130BMV8 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s04_couplers_imp_130BMV8;
architecture STRUCTURE of s04_couplers_imp_130BMV8 is
signal s04_couplers_to_s04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_s04_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_s04_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s04_couplers_to_s04_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s04_couplers_to_s04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_s04_couplers_ARREADY : STD_LOGIC;
signal s04_couplers_to_s04_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_s04_couplers_ARVALID : STD_LOGIC;
signal s04_couplers_to_s04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_s04_couplers_RLAST : STD_LOGIC;
signal s04_couplers_to_s04_couplers_RREADY : STD_LOGIC;
signal s04_couplers_to_s04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_s04_couplers_RVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= s04_couplers_to_s04_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= s04_couplers_to_s04_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= s04_couplers_to_s04_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(7 downto 0) <= s04_couplers_to_s04_couplers_ARLEN(7 downto 0);
M_AXI_arprot(2 downto 0) <= s04_couplers_to_s04_couplers_ARPROT(2 downto 0);
M_AXI_arsize(2 downto 0) <= s04_couplers_to_s04_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= s04_couplers_to_s04_couplers_ARVALID;
M_AXI_rready <= s04_couplers_to_s04_couplers_RREADY;
S_AXI_arready <= s04_couplers_to_s04_couplers_ARREADY;
S_AXI_rdata(31 downto 0) <= s04_couplers_to_s04_couplers_RDATA(31 downto 0);
S_AXI_rlast <= s04_couplers_to_s04_couplers_RLAST;
S_AXI_rresp(1 downto 0) <= s04_couplers_to_s04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= s04_couplers_to_s04_couplers_RVALID;
s04_couplers_to_s04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s04_couplers_to_s04_couplers_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s04_couplers_to_s04_couplers_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s04_couplers_to_s04_couplers_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s04_couplers_to_s04_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s04_couplers_to_s04_couplers_ARREADY <= M_AXI_arready;
s04_couplers_to_s04_couplers_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s04_couplers_to_s04_couplers_ARVALID <= S_AXI_arvalid;
s04_couplers_to_s04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
s04_couplers_to_s04_couplers_RLAST <= M_AXI_rlast;
s04_couplers_to_s04_couplers_RREADY <= S_AXI_rready;
s04_couplers_to_s04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
s04_couplers_to_s04_couplers_RVALID <= M_AXI_rvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone_axi_mem_intercon_1 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rid : in STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wid : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_wlast : out STD_LOGIC;
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S01_ACLK : in STD_LOGIC;
S01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awready : out STD_LOGIC;
S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S01_AXI_awvalid : in STD_LOGIC;
S01_AXI_bready : in STD_LOGIC;
S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S01_AXI_bvalid : out STD_LOGIC;
S01_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S01_AXI_wlast : in STD_LOGIC;
S01_AXI_wready : out STD_LOGIC;
S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S01_AXI_wvalid : in STD_LOGIC;
S02_ACLK : in STD_LOGIC;
S02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S02_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arready : out STD_LOGIC;
S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S02_AXI_arvalid : in STD_LOGIC;
S02_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S02_AXI_rlast : out STD_LOGIC;
S02_AXI_rready : in STD_LOGIC;
S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S02_AXI_rvalid : out STD_LOGIC;
S03_ACLK : in STD_LOGIC;
S03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awready : out STD_LOGIC;
S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S03_AXI_awvalid : in STD_LOGIC;
S03_AXI_bready : in STD_LOGIC;
S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S03_AXI_bvalid : out STD_LOGIC;
S03_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S03_AXI_wlast : in STD_LOGIC;
S03_AXI_wready : out STD_LOGIC;
S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S03_AXI_wvalid : in STD_LOGIC;
S04_ACLK : in STD_LOGIC;
S04_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S04_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S04_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S04_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S04_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arready : out STD_LOGIC;
S04_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S04_AXI_arvalid : in STD_LOGIC;
S04_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S04_AXI_rlast : out STD_LOGIC;
S04_AXI_rready : in STD_LOGIC;
S04_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S04_AXI_rvalid : out STD_LOGIC
);
end design_SWandHW_standalone_axi_mem_intercon_1;
architecture STRUCTURE of design_SWandHW_standalone_axi_mem_intercon_1 is
component design_SWandHW_standalone_xbar_2 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 159 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 39 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 159 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 159 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 39 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 14 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 159 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 4 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_SWandHW_standalone_xbar_2;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S01_ACLK_1 : STD_LOGIC;
signal S01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S02_ACLK_1 : STD_LOGIC;
signal S02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S03_ACLK_1 : STD_LOGIC;
signal S03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S04_ACLK_1 : STD_LOGIC;
signal S04_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s01_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s01_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s01_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s02_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s02_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s02_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s03_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s03_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s03_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s03_couplers_WVALID : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s04_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s04_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s04_couplers_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WLAST : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s01_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s01_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s01_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s01_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s01_couplers_to_xbar_BREADY : STD_LOGIC;
signal s01_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 3 downto 2 );
signal s01_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s01_couplers_to_xbar_WLAST : STD_LOGIC;
signal s01_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal s01_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s01_couplers_to_xbar_WVALID : STD_LOGIC;
signal s02_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s02_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s02_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s02_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s02_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s02_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s02_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal s02_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 2 to 2 );
signal s02_couplers_to_xbar_RREADY : STD_LOGIC;
signal s02_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 5 downto 4 );
signal s02_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal s03_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_xbar_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s03_couplers_to_xbar_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_xbar_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s03_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s03_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s03_couplers_to_xbar_BREADY : STD_LOGIC;
signal s03_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 7 downto 6 );
signal s03_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s03_couplers_to_xbar_WLAST : STD_LOGIC;
signal s03_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal s03_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s03_couplers_to_xbar_WVALID : STD_LOGIC;
signal s04_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s04_couplers_to_xbar_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s04_couplers_to_xbar_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s04_couplers_to_xbar_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s04_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal s04_couplers_to_xbar_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s04_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s04_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal s04_couplers_to_xbar_RLAST : STD_LOGIC_VECTOR ( 4 to 4 );
signal s04_couplers_to_xbar_RREADY : STD_LOGIC;
signal s04_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 9 downto 8 );
signal s04_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal xbar_to_m00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWREGION : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_RLAST : STD_LOGIC;
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xbar_s_axi_arready_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_xbar_s_axi_awready_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_xbar_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_xbar_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_xbar_s_axi_bvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_xbar_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 32 );
signal NLW_xbar_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_xbar_s_axi_rlast_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_xbar_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 );
signal NLW_xbar_s_axi_rvalid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
signal NLW_xbar_s_axi_wready_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0);
M00_AXI_arid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARID(2 downto 0);
M00_AXI_arlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0);
M00_AXI_awburst(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0);
M00_AXI_awcache(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0);
M00_AXI_awid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWID(2 downto 0);
M00_AXI_awlen(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0);
M00_AXI_awlock(1 downto 0) <= m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awqos(3 downto 0) <= m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0);
M00_AXI_awsize(2 downto 0) <= m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wid(2 downto 0) <= m00_couplers_to_axi_mem_intercon_WID(2 downto 0);
M00_AXI_wlast <= m00_couplers_to_axi_mem_intercon_WLAST;
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready(0) <= axi_mem_intercon_to_s00_couplers_ARREADY(0);
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rlast(0) <= axi_mem_intercon_to_s00_couplers_RLAST(0);
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid(0) <= axi_mem_intercon_to_s00_couplers_RVALID(0);
S01_ACLK_1 <= S01_ACLK;
S01_ARESETN_1(0) <= S01_ARESETN(0);
S01_AXI_awready <= axi_mem_intercon_to_s01_couplers_AWREADY;
S01_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0);
S01_AXI_bvalid <= axi_mem_intercon_to_s01_couplers_BVALID;
S01_AXI_wready <= axi_mem_intercon_to_s01_couplers_WREADY;
S02_ACLK_1 <= S02_ACLK;
S02_ARESETN_1(0) <= S02_ARESETN(0);
S02_AXI_arready <= axi_mem_intercon_to_s02_couplers_ARREADY;
S02_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0);
S02_AXI_rlast <= axi_mem_intercon_to_s02_couplers_RLAST;
S02_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0);
S02_AXI_rvalid <= axi_mem_intercon_to_s02_couplers_RVALID;
S03_ACLK_1 <= S03_ACLK;
S03_ARESETN_1(0) <= S03_ARESETN(0);
S03_AXI_awready <= axi_mem_intercon_to_s03_couplers_AWREADY;
S03_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s03_couplers_BRESP(1 downto 0);
S03_AXI_bvalid <= axi_mem_intercon_to_s03_couplers_BVALID;
S03_AXI_wready <= axi_mem_intercon_to_s03_couplers_WREADY;
S04_ACLK_1 <= S04_ACLK;
S04_ARESETN_1(0) <= S04_ARESETN(0);
S04_AXI_arready <= axi_mem_intercon_to_s04_couplers_ARREADY;
S04_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s04_couplers_RDATA(31 downto 0);
S04_AXI_rlast <= axi_mem_intercon_to_s04_couplers_RLAST;
S04_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s04_couplers_RRESP(1 downto 0);
S04_AXI_rvalid <= axi_mem_intercon_to_s04_couplers_RVALID;
axi_mem_intercon_ACLK_net <= ACLK;
axi_mem_intercon_ARESETN_net(0) <= ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID(0) <= S00_AXI_arvalid(0);
axi_mem_intercon_to_s00_couplers_RREADY(0) <= S00_AXI_rready(0);
axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0) <= S01_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0) <= S01_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0) <= S01_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0) <= S01_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0) <= S01_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0) <= S01_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s01_couplers_AWVALID <= S01_AXI_awvalid;
axi_mem_intercon_to_s01_couplers_BREADY <= S01_AXI_bready;
axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0) <= S01_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s01_couplers_WLAST <= S01_AXI_wlast;
axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0) <= S01_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s01_couplers_WVALID <= S01_AXI_wvalid;
axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0) <= S02_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0) <= S02_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0) <= S02_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0) <= S02_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0) <= S02_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0) <= S02_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s02_couplers_ARVALID <= S02_AXI_arvalid;
axi_mem_intercon_to_s02_couplers_RREADY <= S02_AXI_rready;
axi_mem_intercon_to_s03_couplers_AWADDR(31 downto 0) <= S03_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s03_couplers_AWBURST(1 downto 0) <= S03_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s03_couplers_AWCACHE(3 downto 0) <= S03_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s03_couplers_AWLEN(7 downto 0) <= S03_AXI_awlen(7 downto 0);
axi_mem_intercon_to_s03_couplers_AWPROT(2 downto 0) <= S03_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s03_couplers_AWSIZE(2 downto 0) <= S03_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s03_couplers_AWVALID <= S03_AXI_awvalid;
axi_mem_intercon_to_s03_couplers_BREADY <= S03_AXI_bready;
axi_mem_intercon_to_s03_couplers_WDATA(31 downto 0) <= S03_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s03_couplers_WLAST <= S03_AXI_wlast;
axi_mem_intercon_to_s03_couplers_WSTRB(3 downto 0) <= S03_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s03_couplers_WVALID <= S03_AXI_wvalid;
axi_mem_intercon_to_s04_couplers_ARADDR(31 downto 0) <= S04_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s04_couplers_ARBURST(1 downto 0) <= S04_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s04_couplers_ARCACHE(3 downto 0) <= S04_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s04_couplers_ARLEN(7 downto 0) <= S04_AXI_arlen(7 downto 0);
axi_mem_intercon_to_s04_couplers_ARPROT(2 downto 0) <= S04_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s04_couplers_ARSIZE(2 downto 0) <= S04_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s04_couplers_ARVALID <= S04_AXI_arvalid;
axi_mem_intercon_to_s04_couplers_RREADY <= S04_AXI_rready;
m00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_mem_intercon_BID(5 downto 0) <= M00_AXI_bid(5 downto 0);
m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_mem_intercon_RID(5 downto 0) <= M00_AXI_rid(5 downto 0);
m00_couplers_to_axi_mem_intercon_RLAST <= M00_AXI_rlast;
m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_3Z6JOL
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARCACHE(3 downto 0),
M_AXI_arid(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARID(2 downto 0),
M_AXI_arlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_ARQOS(3 downto 0),
M_AXI_arready => m00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_ARSIZE(2 downto 0),
M_AXI_arvalid => m00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(31 downto 0) => m00_couplers_to_axi_mem_intercon_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWCACHE(3 downto 0),
M_AXI_awid(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWID(2 downto 0),
M_AXI_awlen(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWLEN(3 downto 0),
M_AXI_awlock(1 downto 0) => m00_couplers_to_axi_mem_intercon_AWLOCK(1 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awqos(3 downto 0) => m00_couplers_to_axi_mem_intercon_AWQOS(3 downto 0),
M_AXI_awready => m00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awsize(2 downto 0) => m00_couplers_to_axi_mem_intercon_AWSIZE(2 downto 0),
M_AXI_awvalid => m00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bid(5 downto 0) => m00_couplers_to_axi_mem_intercon_BID(5 downto 0),
M_AXI_bready => m00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rid(5 downto 0) => m00_couplers_to_axi_mem_intercon_RID(5 downto 0),
M_AXI_rlast => m00_couplers_to_axi_mem_intercon_RLAST,
M_AXI_rready => m00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wid(2 downto 0) => m00_couplers_to_axi_mem_intercon_WID(2 downto 0),
M_AXI_wlast => m00_couplers_to_axi_mem_intercon_WLAST,
M_AXI_wready => m00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => axi_mem_intercon_ACLK_net,
S_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(2 downto 0) => xbar_to_m00_couplers_ARID(2 downto 0),
S_AXI_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
S_AXI_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
S_AXI_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(2 downto 0) => xbar_to_m00_couplers_AWID(2 downto 0),
S_AXI_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
S_AXI_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
S_AXI_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bid(2 downto 0) => xbar_to_m00_couplers_BID(2 downto 0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rid(2 downto 0) => xbar_to_m00_couplers_RID(2 downto 0),
S_AXI_rlast => xbar_to_m00_couplers_RLAST,
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wlast => xbar_to_m00_couplers_WLAST(0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
s00_couplers: entity work.s00_couplers_imp_14GRHI
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready(0) => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rlast(0) => s00_couplers_to_xbar_RLAST(0),
M_AXI_rready(0) => s00_couplers_to_xbar_RREADY(0),
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => axi_mem_intercon_to_s00_couplers_ARREADY(0),
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid(0) => axi_mem_intercon_to_s00_couplers_ARVALID(0),
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rlast(0) => axi_mem_intercon_to_s00_couplers_RLAST(0),
S_AXI_rready(0) => axi_mem_intercon_to_s00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => axi_mem_intercon_to_s00_couplers_RVALID(0)
);
s01_couplers: entity work.s01_couplers_imp_1KHG2CU
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s01_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s01_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s01_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awprot(2 downto 0) => s01_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s01_couplers_to_xbar_AWREADY(1),
M_AXI_awsize(2 downto 0) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s01_couplers_to_xbar_AWVALID,
M_AXI_bready => s01_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s01_couplers_to_xbar_BRESP(3 downto 2),
M_AXI_bvalid => s01_couplers_to_xbar_BVALID(1),
M_AXI_wdata(31 downto 0) => s01_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast => s01_couplers_to_xbar_WLAST,
M_AXI_wready => s01_couplers_to_xbar_WREADY(1),
M_AXI_wstrb(3 downto 0) => s01_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s01_couplers_to_xbar_WVALID,
S_ACLK => S01_ACLK_1,
S_ARESETN(0) => S01_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s01_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s01_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s01_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s01_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s01_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s01_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s01_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s01_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s01_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s01_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s01_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s01_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s01_couplers_WVALID
);
s02_couplers: entity work.s02_couplers_imp_HTS99Z
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s02_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s02_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s02_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s02_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s02_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s02_couplers_to_xbar_ARREADY(2),
M_AXI_arsize(2 downto 0) => s02_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s02_couplers_to_xbar_ARVALID,
M_AXI_rdata(31 downto 0) => s02_couplers_to_xbar_RDATA(95 downto 64),
M_AXI_rlast => s02_couplers_to_xbar_RLAST(2),
M_AXI_rready => s02_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s02_couplers_to_xbar_RRESP(5 downto 4),
M_AXI_rvalid => s02_couplers_to_xbar_RVALID(2),
S_ACLK => S02_ACLK_1,
S_ARESETN(0) => S02_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s02_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s02_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s02_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s02_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s02_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s02_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s02_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s02_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s02_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s02_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s02_couplers_RVALID
);
s03_couplers: entity work.s03_couplers_imp_13X1ZY7
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_awaddr(31 downto 0) => s03_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awburst(1 downto 0) => s03_couplers_to_xbar_AWBURST(1 downto 0),
M_AXI_awcache(3 downto 0) => s03_couplers_to_xbar_AWCACHE(3 downto 0),
M_AXI_awlen(7 downto 0) => s03_couplers_to_xbar_AWLEN(7 downto 0),
M_AXI_awprot(2 downto 0) => s03_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s03_couplers_to_xbar_AWREADY(3),
M_AXI_awsize(2 downto 0) => s03_couplers_to_xbar_AWSIZE(2 downto 0),
M_AXI_awvalid => s03_couplers_to_xbar_AWVALID,
M_AXI_bready => s03_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s03_couplers_to_xbar_BRESP(7 downto 6),
M_AXI_bvalid => s03_couplers_to_xbar_BVALID(3),
M_AXI_wdata(31 downto 0) => s03_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wlast => s03_couplers_to_xbar_WLAST,
M_AXI_wready => s03_couplers_to_xbar_WREADY(3),
M_AXI_wstrb(3 downto 0) => s03_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s03_couplers_to_xbar_WVALID,
S_ACLK => S03_ACLK_1,
S_ARESETN(0) => S03_ARESETN_1(0),
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s03_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s03_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s03_couplers_AWCACHE(3 downto 0),
S_AXI_awlen(7 downto 0) => axi_mem_intercon_to_s03_couplers_AWLEN(7 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s03_couplers_AWPROT(2 downto 0),
S_AXI_awready => axi_mem_intercon_to_s03_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s03_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s03_couplers_AWVALID,
S_AXI_bready => axi_mem_intercon_to_s03_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s03_couplers_BVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s03_couplers_WDATA(31 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s03_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s03_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s03_couplers_WVALID
);
s04_couplers: entity work.s04_couplers_imp_130BMV8
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s04_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s04_couplers_to_xbar_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s04_couplers_to_xbar_ARCACHE(3 downto 0),
M_AXI_arlen(7 downto 0) => s04_couplers_to_xbar_ARLEN(7 downto 0),
M_AXI_arprot(2 downto 0) => s04_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s04_couplers_to_xbar_ARREADY(4),
M_AXI_arsize(2 downto 0) => s04_couplers_to_xbar_ARSIZE(2 downto 0),
M_AXI_arvalid => s04_couplers_to_xbar_ARVALID,
M_AXI_rdata(31 downto 0) => s04_couplers_to_xbar_RDATA(159 downto 128),
M_AXI_rlast => s04_couplers_to_xbar_RLAST(4),
M_AXI_rready => s04_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s04_couplers_to_xbar_RRESP(9 downto 8),
M_AXI_rvalid => s04_couplers_to_xbar_RVALID(4),
S_ACLK => S04_ACLK_1,
S_ARESETN(0) => S04_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s04_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s04_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s04_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_mem_intercon_to_s04_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s04_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_mem_intercon_to_s04_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s04_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s04_couplers_ARVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s04_couplers_RDATA(31 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s04_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s04_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s04_couplers_RVALID
);
xbar: component design_SWandHW_standalone_xbar_2
port map (
aclk => axi_mem_intercon_ACLK_net,
aresetn => axi_mem_intercon_ARESETN_net(0),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => xbar_to_m00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => xbar_to_m00_couplers_ARCACHE(3 downto 0),
m_axi_arid(2 downto 0) => xbar_to_m00_couplers_ARID(2 downto 0),
m_axi_arlen(7 downto 0) => xbar_to_m00_couplers_ARLEN(7 downto 0),
m_axi_arlock(0) => xbar_to_m00_couplers_ARLOCK(0),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => xbar_to_m00_couplers_ARQOS(3 downto 0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arregion(3 downto 0) => xbar_to_m00_couplers_ARREGION(3 downto 0),
m_axi_arsize(2 downto 0) => xbar_to_m00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awburst(1 downto 0) => xbar_to_m00_couplers_AWBURST(1 downto 0),
m_axi_awcache(3 downto 0) => xbar_to_m00_couplers_AWCACHE(3 downto 0),
m_axi_awid(2 downto 0) => xbar_to_m00_couplers_AWID(2 downto 0),
m_axi_awlen(7 downto 0) => xbar_to_m00_couplers_AWLEN(7 downto 0),
m_axi_awlock(0) => xbar_to_m00_couplers_AWLOCK(0),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awqos(3 downto 0) => xbar_to_m00_couplers_AWQOS(3 downto 0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awregion(3 downto 0) => xbar_to_m00_couplers_AWREGION(3 downto 0),
m_axi_awsize(2 downto 0) => xbar_to_m00_couplers_AWSIZE(2 downto 0),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bid(2 downto 0) => xbar_to_m00_couplers_BID(2 downto 0),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rid(2 downto 0) => xbar_to_m00_couplers_RID(2 downto 0),
m_axi_rlast(0) => xbar_to_m00_couplers_RLAST,
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wlast(0) => xbar_to_m00_couplers_WLAST(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(159 downto 128) => s04_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(127 downto 96) => B"00000000000000000000000000000000",
s_axi_araddr(95 downto 64) => s02_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_araddr(63 downto 32) => B"00000000000000000000000000000000",
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arburst(9 downto 8) => s04_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(7 downto 6) => B"00",
s_axi_arburst(5 downto 4) => s02_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arburst(3 downto 2) => B"00",
s_axi_arburst(1 downto 0) => s00_couplers_to_xbar_ARBURST(1 downto 0),
s_axi_arcache(19 downto 16) => s04_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(15 downto 12) => B"0000",
s_axi_arcache(11 downto 8) => s02_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arcache(7 downto 4) => B"0000",
s_axi_arcache(3 downto 0) => s00_couplers_to_xbar_ARCACHE(3 downto 0),
s_axi_arid(14 downto 0) => B"000000000000000",
s_axi_arlen(39 downto 32) => s04_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(31 downto 24) => B"00000000",
s_axi_arlen(23 downto 16) => s02_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlen(15 downto 8) => B"00000000",
s_axi_arlen(7 downto 0) => s00_couplers_to_xbar_ARLEN(7 downto 0),
s_axi_arlock(4 downto 0) => B"00000",
s_axi_arprot(14 downto 12) => s04_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(11 downto 9) => B"000",
s_axi_arprot(8 downto 6) => s02_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arprot(5 downto 3) => B"000",
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arqos(19 downto 0) => B"00000000000000000000",
s_axi_arready(4) => s04_couplers_to_xbar_ARREADY(4),
s_axi_arready(3) => NLW_xbar_s_axi_arready_UNCONNECTED(3),
s_axi_arready(2) => s02_couplers_to_xbar_ARREADY(2),
s_axi_arready(1) => NLW_xbar_s_axi_arready_UNCONNECTED(1),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arsize(14 downto 12) => s04_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(11 downto 9) => B"000",
s_axi_arsize(8 downto 6) => s02_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arsize(5 downto 3) => B"000",
s_axi_arsize(2 downto 0) => s00_couplers_to_xbar_ARSIZE(2 downto 0),
s_axi_arvalid(4) => s04_couplers_to_xbar_ARVALID,
s_axi_arvalid(3) => '0',
s_axi_arvalid(2) => s02_couplers_to_xbar_ARVALID,
s_axi_arvalid(1) => '0',
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID(0),
s_axi_awaddr(159 downto 128) => B"00000000000000000000000000000000",
s_axi_awaddr(127 downto 96) => s03_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(95 downto 64) => B"00000000000000000000000000000000",
s_axi_awaddr(63 downto 32) => s01_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(9 downto 8) => B"00",
s_axi_awburst(7 downto 6) => s03_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(5 downto 4) => B"00",
s_axi_awburst(3 downto 2) => s01_couplers_to_xbar_AWBURST(1 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(19 downto 16) => B"0000",
s_axi_awcache(15 downto 12) => s03_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(11 downto 8) => B"0000",
s_axi_awcache(7 downto 4) => s01_couplers_to_xbar_AWCACHE(3 downto 0),
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(14 downto 0) => B"000000000000000",
s_axi_awlen(39 downto 32) => B"00000000",
s_axi_awlen(31 downto 24) => s03_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(23 downto 16) => B"00000000",
s_axi_awlen(15 downto 8) => s01_couplers_to_xbar_AWLEN(7 downto 0),
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awlock(4 downto 0) => B"00000",
s_axi_awprot(14 downto 12) => B"000",
s_axi_awprot(11 downto 9) => s03_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(8 downto 6) => B"000",
s_axi_awprot(5 downto 3) => s01_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awprot(2 downto 0) => B"000",
s_axi_awqos(19 downto 0) => B"00000000000000000000",
s_axi_awready(4) => NLW_xbar_s_axi_awready_UNCONNECTED(4),
s_axi_awready(3) => s03_couplers_to_xbar_AWREADY(3),
s_axi_awready(2) => NLW_xbar_s_axi_awready_UNCONNECTED(2),
s_axi_awready(1) => s01_couplers_to_xbar_AWREADY(1),
s_axi_awready(0) => NLW_xbar_s_axi_awready_UNCONNECTED(0),
s_axi_awsize(14 downto 12) => B"000",
s_axi_awsize(11 downto 9) => s03_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(8 downto 6) => B"000",
s_axi_awsize(5 downto 3) => s01_couplers_to_xbar_AWSIZE(2 downto 0),
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid(4) => '0',
s_axi_awvalid(3) => s03_couplers_to_xbar_AWVALID,
s_axi_awvalid(2) => '0',
s_axi_awvalid(1) => s01_couplers_to_xbar_AWVALID,
s_axi_awvalid(0) => '0',
s_axi_bid(14 downto 0) => NLW_xbar_s_axi_bid_UNCONNECTED(14 downto 0),
s_axi_bready(4) => '0',
s_axi_bready(3) => s03_couplers_to_xbar_BREADY,
s_axi_bready(2) => '1',
s_axi_bready(1) => s01_couplers_to_xbar_BREADY,
s_axi_bready(0) => '0',
s_axi_bresp(9 downto 8) => NLW_xbar_s_axi_bresp_UNCONNECTED(9 downto 8),
s_axi_bresp(7 downto 6) => s03_couplers_to_xbar_BRESP(7 downto 6),
s_axi_bresp(5 downto 4) => NLW_xbar_s_axi_bresp_UNCONNECTED(5 downto 4),
s_axi_bresp(3 downto 2) => s01_couplers_to_xbar_BRESP(3 downto 2),
s_axi_bresp(1 downto 0) => NLW_xbar_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid(4) => NLW_xbar_s_axi_bvalid_UNCONNECTED(4),
s_axi_bvalid(3) => s03_couplers_to_xbar_BVALID(3),
s_axi_bvalid(2) => NLW_xbar_s_axi_bvalid_UNCONNECTED(2),
s_axi_bvalid(1) => s01_couplers_to_xbar_BVALID(1),
s_axi_bvalid(0) => NLW_xbar_s_axi_bvalid_UNCONNECTED(0),
s_axi_rdata(159 downto 128) => s04_couplers_to_xbar_RDATA(159 downto 128),
s_axi_rdata(127 downto 96) => NLW_xbar_s_axi_rdata_UNCONNECTED(127 downto 96),
s_axi_rdata(95 downto 64) => s02_couplers_to_xbar_RDATA(95 downto 64),
s_axi_rdata(63 downto 32) => NLW_xbar_s_axi_rdata_UNCONNECTED(63 downto 32),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rid(14 downto 0) => NLW_xbar_s_axi_rid_UNCONNECTED(14 downto 0),
s_axi_rlast(4) => s04_couplers_to_xbar_RLAST(4),
s_axi_rlast(3) => NLW_xbar_s_axi_rlast_UNCONNECTED(3),
s_axi_rlast(2) => s02_couplers_to_xbar_RLAST(2),
s_axi_rlast(1) => NLW_xbar_s_axi_rlast_UNCONNECTED(1),
s_axi_rlast(0) => s00_couplers_to_xbar_RLAST(0),
s_axi_rready(4) => s04_couplers_to_xbar_RREADY,
s_axi_rready(3) => '0',
s_axi_rready(2) => s02_couplers_to_xbar_RREADY,
s_axi_rready(1) => '0',
s_axi_rready(0) => s00_couplers_to_xbar_RREADY(0),
s_axi_rresp(9 downto 8) => s04_couplers_to_xbar_RRESP(9 downto 8),
s_axi_rresp(7 downto 6) => NLW_xbar_s_axi_rresp_UNCONNECTED(7 downto 6),
s_axi_rresp(5 downto 4) => s02_couplers_to_xbar_RRESP(5 downto 4),
s_axi_rresp(3 downto 2) => NLW_xbar_s_axi_rresp_UNCONNECTED(3 downto 2),
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(4) => s04_couplers_to_xbar_RVALID(4),
s_axi_rvalid(3) => NLW_xbar_s_axi_rvalid_UNCONNECTED(3),
s_axi_rvalid(2) => s02_couplers_to_xbar_RVALID(2),
s_axi_rvalid(1) => NLW_xbar_s_axi_rvalid_UNCONNECTED(1),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(159 downto 128) => B"00000000000000000000000000000000",
s_axi_wdata(127 downto 96) => s03_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(95 downto 64) => B"00000000000000000000000000000000",
s_axi_wdata(63 downto 32) => s01_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast(4) => '0',
s_axi_wlast(3) => s03_couplers_to_xbar_WLAST,
s_axi_wlast(2) => '1',
s_axi_wlast(1) => s01_couplers_to_xbar_WLAST,
s_axi_wlast(0) => '1',
s_axi_wready(4) => NLW_xbar_s_axi_wready_UNCONNECTED(4),
s_axi_wready(3) => s03_couplers_to_xbar_WREADY(3),
s_axi_wready(2) => NLW_xbar_s_axi_wready_UNCONNECTED(2),
s_axi_wready(1) => s01_couplers_to_xbar_WREADY(1),
s_axi_wready(0) => NLW_xbar_s_axi_wready_UNCONNECTED(0),
s_axi_wstrb(19 downto 16) => B"0000",
s_axi_wstrb(15 downto 12) => s03_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(11 downto 8) => B"0000",
s_axi_wstrb(7 downto 4) => s01_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wstrb(3 downto 0) => B"1111",
s_axi_wvalid(4) => '0',
s_axi_wvalid(3) => s03_couplers_to_xbar_WVALID,
s_axi_wvalid(2) => '1',
s_axi_wvalid(1) => s01_couplers_to_xbar_WVALID,
s_axi_wvalid(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wvalid : out STD_LOGIC;
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wvalid : out STD_LOGIC;
M06_ACLK : in STD_LOGIC;
M06_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M06_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_arready : in STD_LOGIC;
M06_AXI_arvalid : out STD_LOGIC;
M06_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_awready : in STD_LOGIC;
M06_AXI_awvalid : out STD_LOGIC;
M06_AXI_bready : out STD_LOGIC;
M06_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_bvalid : in STD_LOGIC;
M06_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_rready : out STD_LOGIC;
M06_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M06_AXI_rvalid : in STD_LOGIC;
M06_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M06_AXI_wready : in STD_LOGIC;
M06_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_SWandHW_standalone_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_SWandHW_standalone_processing_system7_0_axi_periph_0 is
component design_SWandHW_standalone_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 27 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 20 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 223 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 13 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
end component design_SWandHW_standalone_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M06_ACLK_1 : STD_LOGIC;
signal M06_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m04_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m05_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m06_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m06_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m06_couplers_ARADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m06_couplers_ARVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_AWADDR : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m06_couplers_AWVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_BVALID : STD_LOGIC;
signal xbar_to_m06_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m06_couplers_RREADY : STD_LOGIC_VECTOR ( 6 to 6 );
signal xbar_to_m06_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m06_couplers_RVALID : STD_LOGIC;
signal xbar_to_m06_couplers_WDATA : STD_LOGIC_VECTOR ( 223 downto 192 );
signal xbar_to_m06_couplers_WREADY : STD_LOGIC;
signal xbar_to_m06_couplers_WVALID : STD_LOGIC_VECTOR ( 6 to 6 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 20 downto 0 );
signal NLW_xbar_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 27 downto 8 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_processing_system7_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_processing_system7_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_processing_system7_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1(0) <= M03_ARESETN(0);
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_processing_system7_0_axi_periph_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_processing_system7_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_processing_system7_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_processing_system7_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wvalid <= m03_couplers_to_processing_system7_0_axi_periph_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1(0) <= M04_ARESETN(0);
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_processing_system7_0_axi_periph_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_processing_system7_0_axi_periph_AWVALID;
M04_AXI_bready <= m04_couplers_to_processing_system7_0_axi_periph_BREADY;
M04_AXI_rready <= m04_couplers_to_processing_system7_0_axi_periph_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wvalid <= m04_couplers_to_processing_system7_0_axi_periph_WVALID;
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1(0) <= M05_ARESETN(0);
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_processing_system7_0_axi_periph_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_processing_system7_0_axi_periph_AWVALID;
M05_AXI_bready <= m05_couplers_to_processing_system7_0_axi_periph_BREADY;
M05_AXI_rready <= m05_couplers_to_processing_system7_0_axi_periph_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wvalid <= m05_couplers_to_processing_system7_0_axi_periph_WVALID;
M06_ACLK_1 <= M06_ACLK;
M06_ARESETN_1(0) <= M06_ARESETN(0);
M06_AXI_araddr(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M06_AXI_arvalid <= m06_couplers_to_processing_system7_0_axi_periph_ARVALID;
M06_AXI_awaddr(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M06_AXI_awvalid <= m06_couplers_to_processing_system7_0_axi_periph_AWVALID;
M06_AXI_bready <= m06_couplers_to_processing_system7_0_axi_periph_BREADY;
M06_AXI_rready <= m06_couplers_to_processing_system7_0_axi_periph_RREADY;
M06_AXI_wdata(31 downto 0) <= m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M06_AXI_wvalid <= m06_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_processing_system7_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_processing_system7_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
m03_couplers_to_processing_system7_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_processing_system7_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_processing_system7_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_processing_system7_0_axi_periph_WREADY <= M03_AXI_wready;
m04_couplers_to_processing_system7_0_axi_periph_ARREADY <= M04_AXI_arready;
m04_couplers_to_processing_system7_0_axi_periph_AWREADY <= M04_AXI_awready;
m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_BVALID <= M04_AXI_bvalid;
m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_processing_system7_0_axi_periph_RVALID <= M04_AXI_rvalid;
m04_couplers_to_processing_system7_0_axi_periph_WREADY <= M04_AXI_wready;
m05_couplers_to_processing_system7_0_axi_periph_ARREADY <= M05_AXI_arready;
m05_couplers_to_processing_system7_0_axi_periph_AWREADY <= M05_AXI_awready;
m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_BVALID <= M05_AXI_bvalid;
m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_processing_system7_0_axi_periph_RVALID <= M05_AXI_rvalid;
m05_couplers_to_processing_system7_0_axi_periph_WREADY <= M05_AXI_wready;
m06_couplers_to_processing_system7_0_axi_periph_ARREADY <= M06_AXI_arready;
m06_couplers_to_processing_system7_0_axi_periph_AWREADY <= M06_AXI_awready;
m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M06_AXI_bresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_BVALID <= M06_AXI_bvalid;
m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M06_AXI_rdata(31 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M06_AXI_rresp(1 downto 0);
m06_couplers_to_processing_system7_0_axi_periph_RVALID <= M06_AXI_rvalid;
m06_couplers_to_processing_system7_0_axi_periph_WREADY <= M06_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_1MVOGV6
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_7OD9KA
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m01_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m01_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1432F1V
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_QLWQRF
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN(0) => M03_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m03_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_PPSTKW
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN(0) => M04_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m04_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m04_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m04_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m04_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_14U9M2W
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN(0) => M05_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m05_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m05_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m05_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m05_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
m06_couplers: entity work.m06_couplers_imp_6WKA35
port map (
M_ACLK => M06_ACLK_1,
M_ARESETN(0) => M06_ARESETN_1(0),
M_AXI_araddr(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m06_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m06_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m06_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m06_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m06_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m06_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m06_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m06_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m06_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m06_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wvalid => m06_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m06_couplers_ARADDR(223 downto 192),
S_AXI_arready => xbar_to_m06_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m06_couplers_ARVALID(6),
S_AXI_awaddr(31 downto 0) => xbar_to_m06_couplers_AWADDR(223 downto 192),
S_AXI_awready => xbar_to_m06_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m06_couplers_AWVALID(6),
S_AXI_bready => xbar_to_m06_couplers_BREADY(6),
S_AXI_bresp(1 downto 0) => xbar_to_m06_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m06_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m06_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m06_couplers_RREADY(6),
S_AXI_rresp(1 downto 0) => xbar_to_m06_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m06_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m06_couplers_WDATA(223 downto 192),
S_AXI_wready => xbar_to_m06_couplers_WREADY,
S_AXI_wvalid => xbar_to_m06_couplers_WVALID(6)
);
s00_couplers: entity work.s00_couplers_imp_1PPRTY9
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component design_SWandHW_standalone_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(223 downto 192) => xbar_to_m06_couplers_ARADDR(223 downto 192),
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(20 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(20 downto 0),
m_axi_arready(6) => xbar_to_m06_couplers_ARREADY,
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(6) => xbar_to_m06_couplers_ARVALID(6),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(223 downto 192) => xbar_to_m06_couplers_AWADDR(223 downto 192),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(20 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(20 downto 0),
m_axi_awready(6) => xbar_to_m06_couplers_AWREADY,
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(6) => xbar_to_m06_couplers_AWVALID(6),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(6) => xbar_to_m06_couplers_BREADY(6),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(13 downto 12) => xbar_to_m06_couplers_BRESP(1 downto 0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(6) => xbar_to_m06_couplers_BVALID,
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(223 downto 192) => xbar_to_m06_couplers_RDATA(31 downto 0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(6) => xbar_to_m06_couplers_RREADY(6),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(13 downto 12) => xbar_to_m06_couplers_RRESP(1 downto 0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(6) => xbar_to_m06_couplers_RVALID,
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(223 downto 192) => xbar_to_m06_couplers_WDATA(223 downto 192),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(6) => xbar_to_m06_couplers_WREADY,
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(27 downto 8) => NLW_xbar_m_axi_wstrb_UNCONNECTED(27 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(6) => xbar_to_m06_couplers_WVALID(6),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SWandHW_standalone is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_SWandHW_standalone : entity is "design_SWandHW_standalone,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_SWandHW_standalone,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=32,numReposBlks=16,numNonXlnxBlks=1,numHierBlks=16,maxHierDepth=0,da_axi4_cnt=14,da_axi4_s2mm_cnt=7,da_board_cnt=1,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_SWandHW_standalone : entity is "design_SWandHW_standalone.hwdef";
end design_SWandHW_standalone;
architecture STRUCTURE of design_SWandHW_standalone is
component design_SWandHW_standalone_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 5 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_SWandHW_standalone_processing_system7_0_0;
component design_SWandHW_standalone_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SWandHW_standalone_axi_gpio_0_0;
component design_SWandHW_standalone_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_SWandHW_standalone_rst_processing_system7_0_100M_0;
component design_SWandHW_standalone_feedforward_0_0 is
port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC;
interrupt : out STD_LOGIC;
P_config_TVALID : in STD_LOGIC;
P_config_TREADY : out STD_LOGIC;
P_config_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
P_WandB_TVALID : in STD_LOGIC;
P_WandB_TREADY : out STD_LOGIC;
P_WandB_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
P_uOut_TVALID : out STD_LOGIC;
P_uOut_TREADY : in STD_LOGIC;
P_uOut_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
P_netIn_TVALID : in STD_LOGIC;
P_netIn_TREADY : out STD_LOGIC;
P_netIn_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
P_netOut_TVALID : out STD_LOGIC;
P_netOut_TREADY : in STD_LOGIC;
P_netOut_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_feedforward_0_0;
component design_SWandHW_standalone_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
In3 : in STD_LOGIC_VECTOR ( 0 to 0 );
In4 : in STD_LOGIC_VECTOR ( 0 to 0 );
In5 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component design_SWandHW_standalone_xlconcat_0_0;
component design_SWandHW_standalone_axi_dma_1 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_1;
component design_SWandHW_standalone_axi_dma_1_1 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_1_1;
component design_SWandHW_standalone_axi_dma_2_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_2_0;
component design_SWandHW_standalone_axi_dma_3_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_s2mm_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_s2mm_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_s2mm_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_awvalid : out STD_LOGIC;
m_axi_s2mm_awready : in STD_LOGIC;
m_axi_s2mm_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_s2mm_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_s2mm_wlast : out STD_LOGIC;
m_axi_s2mm_wvalid : out STD_LOGIC;
m_axi_s2mm_wready : in STD_LOGIC;
m_axi_s2mm_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_s2mm_bvalid : in STD_LOGIC;
m_axi_s2mm_bready : out STD_LOGIC;
s2mm_prmry_reset_out_n : out STD_LOGIC;
s_axis_s2mm_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_s2mm_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_s2mm_tvalid : in STD_LOGIC;
s_axis_s2mm_tready : out STD_LOGIC;
s_axis_s2mm_tlast : in STD_LOGIC;
s2mm_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_3_0;
component design_SWandHW_standalone_axi_dma_4_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
mm2s_prmry_reset_out_n : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component design_SWandHW_standalone_axi_dma_4_0;
component design_SWandHW_standalone_axis_data_fifo_0_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
axis_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_axis_data_fifo_0_0;
component design_SWandHW_standalone_axis_data_fifo_1_0 is
port (
s_axis_aresetn : in STD_LOGIC;
s_axis_aclk : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_tlast : in STD_LOGIC;
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tlast : out STD_LOGIC;
axis_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component design_SWandHW_standalone_axis_data_fifo_1_0;
signal axi_dma_1_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_1_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_1_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_1_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_1_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_1_s2mm_introut : STD_LOGIC;
signal axi_dma_2_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_2_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_2_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_2_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_2_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_2_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_2_mm2s_introut : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWREADY : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_3_M_AXI_S2MM_AWVALID : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_BREADY : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_3_M_AXI_S2MM_BVALID : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_3_M_AXI_S2MM_WLAST : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_WREADY : STD_LOGIC;
signal axi_dma_3_M_AXI_S2MM_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_3_M_AXI_S2MM_WVALID : STD_LOGIC;
signal axi_dma_3_s2mm_introut : STD_LOGIC;
signal axi_dma_4_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_4_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_4_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_4_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_4_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_4_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_4_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_dma_4_mm2s_introut : STD_LOGIC;
signal axi_dma_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_dma_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_dma_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_dma_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_dma_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_M_AXI_MM2S_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_dma_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_dma_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_dma_M_AXI_MM2S_RLAST : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_dma_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_dma_M_AXI_MM2S_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_dma_mm2s_introut : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO_TRI_T : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RID : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_mem_intercon_M00_AXI_RLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WID : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_WLAST : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_data_fifo_0_M_AXIS_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_data_fifo_0_M_AXIS_TLAST : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_0_M_AXIS_TVALID : STD_LOGIC;
signal axis_data_fifo_1_M_AXIS_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axis_data_fifo_1_M_AXIS_TKEEP : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axis_data_fifo_1_M_AXIS_TLAST : STD_LOGIC;
signal axis_data_fifo_1_M_AXIS_TREADY : STD_LOGIC;
signal axis_data_fifo_1_M_AXIS_TVALID : STD_LOGIC;
signal feedforward_0_P_netOut_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal feedforward_0_P_netOut_TREADY : STD_LOGIC;
signal feedforward_0_P_netOut_TVALID : STD_LOGIC;
signal feedforward_0_P_uOut_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal feedforward_0_P_uOut_TREADY : STD_LOGIC;
signal feedforward_0_P_uOut_TVALID : STD_LOGIC;
signal feedforward_0_interrupt : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M05_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M06_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M06_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_axi_dma_m_axis_mm2s_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_m_axis_mm2s_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_2_m_axis_mm2s_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_2_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_2_m_axis_mm2s_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axi_dma_3_s2mm_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_4_m_axis_mm2s_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_4_mm2s_prmry_reset_out_n_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dma_4_m_axis_mm2s_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_axis_data_fifo_0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_1_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_1_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axis_data_fifo_1_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_gpio_0_GPIO_TRI_I(3 downto 0) <= leds_4bits_tri_i(3 downto 0);
leds_4bits_tri_o(3 downto 0) <= axi_gpio_0_GPIO_TRI_O(3 downto 0);
leds_4bits_tri_t(3 downto 0) <= axi_gpio_0_GPIO_TRI_T(3 downto 0);
axi_dma: component design_SWandHW_standalone_axi_dma_1
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_M_AXI_MM2S_ARREADY(0),
m_axi_mm2s_arsize(2 downto 0) => axi_dma_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_M_AXI_MM2S_RLAST(0),
m_axi_mm2s_rready => axi_dma_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_M_AXI_MM2S_RVALID(0),
m_axis_mm2s_tdata(31 downto 0) => axi_dma_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => NLW_axi_dma_m_axis_mm2s_tkeep_UNCONNECTED(3 downto 0),
m_axis_mm2s_tlast => NLW_axi_dma_m_axis_mm2s_tlast_UNCONNECTED,
m_axis_mm2s_tready => axi_dma_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID
);
axi_dma_1: component design_SWandHW_standalone_axi_dma_1_1
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_1_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_1_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_1_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_1_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
s2mm_introut => axi_dma_1_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_1_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID,
s_axis_s2mm_tdata(31 downto 0) => axis_data_fifo_1_M_AXIS_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => axis_data_fifo_1_M_AXIS_TKEEP(3 downto 0),
s_axis_s2mm_tlast => axis_data_fifo_1_M_AXIS_TLAST,
s_axis_s2mm_tready => axis_data_fifo_1_M_AXIS_TREADY,
s_axis_s2mm_tvalid => axis_data_fifo_1_M_AXIS_TVALID
);
axi_dma_2: component design_SWandHW_standalone_axi_dma_2_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_2_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_2_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_2_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_2_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_2_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_2_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_2_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_2_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_2_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_2_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_2_M_AXI_MM2S_RVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_2_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => NLW_axi_dma_2_m_axis_mm2s_tkeep_UNCONNECTED(3 downto 0),
m_axis_mm2s_tlast => NLW_axi_dma_2_m_axis_mm2s_tlast_UNCONNECTED,
m_axis_mm2s_tready => axi_dma_2_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_2_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_2_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_2_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID
);
axi_dma_3: component design_SWandHW_standalone_axi_dma_3_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_s2mm_aclk => processing_system7_0_FCLK_CLK0,
m_axi_s2mm_awaddr(31 downto 0) => axi_dma_3_M_AXI_S2MM_AWADDR(31 downto 0),
m_axi_s2mm_awburst(1 downto 0) => axi_dma_3_M_AXI_S2MM_AWBURST(1 downto 0),
m_axi_s2mm_awcache(3 downto 0) => axi_dma_3_M_AXI_S2MM_AWCACHE(3 downto 0),
m_axi_s2mm_awlen(7 downto 0) => axi_dma_3_M_AXI_S2MM_AWLEN(7 downto 0),
m_axi_s2mm_awprot(2 downto 0) => axi_dma_3_M_AXI_S2MM_AWPROT(2 downto 0),
m_axi_s2mm_awready => axi_dma_3_M_AXI_S2MM_AWREADY,
m_axi_s2mm_awsize(2 downto 0) => axi_dma_3_M_AXI_S2MM_AWSIZE(2 downto 0),
m_axi_s2mm_awvalid => axi_dma_3_M_AXI_S2MM_AWVALID,
m_axi_s2mm_bready => axi_dma_3_M_AXI_S2MM_BREADY,
m_axi_s2mm_bresp(1 downto 0) => axi_dma_3_M_AXI_S2MM_BRESP(1 downto 0),
m_axi_s2mm_bvalid => axi_dma_3_M_AXI_S2MM_BVALID,
m_axi_s2mm_wdata(31 downto 0) => axi_dma_3_M_AXI_S2MM_WDATA(31 downto 0),
m_axi_s2mm_wlast => axi_dma_3_M_AXI_S2MM_WLAST,
m_axi_s2mm_wready => axi_dma_3_M_AXI_S2MM_WREADY,
m_axi_s2mm_wstrb(3 downto 0) => axi_dma_3_M_AXI_S2MM_WSTRB(3 downto 0),
m_axi_s2mm_wvalid => axi_dma_3_M_AXI_S2MM_WVALID,
s2mm_introut => axi_dma_3_s2mm_introut,
s2mm_prmry_reset_out_n => NLW_axi_dma_3_s2mm_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M05_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M05_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID,
s_axis_s2mm_tdata(31 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(31 downto 0),
s_axis_s2mm_tkeep(3 downto 0) => axis_data_fifo_0_M_AXIS_TKEEP(3 downto 0),
s_axis_s2mm_tlast => axis_data_fifo_0_M_AXIS_TLAST,
s_axis_s2mm_tready => axis_data_fifo_0_M_AXIS_TREADY,
s_axis_s2mm_tvalid => axis_data_fifo_0_M_AXIS_TVALID
);
axi_dma_4: component design_SWandHW_standalone_axi_dma_4_0
port map (
axi_resetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_dma_4_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_dma_4_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_dma_4_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_dma_4_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_dma_4_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_dma_4_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_dma_4_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_dma_4_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(31 downto 0) => axi_dma_4_M_AXI_MM2S_RDATA(31 downto 0),
m_axi_mm2s_rlast => axi_dma_4_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_dma_4_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_dma_4_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_dma_4_M_AXI_MM2S_RVALID,
m_axis_mm2s_tdata(31 downto 0) => axi_dma_4_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => NLW_axi_dma_4_m_axis_mm2s_tkeep_UNCONNECTED(3 downto 0),
m_axis_mm2s_tlast => NLW_axi_dma_4_m_axis_mm2s_tlast_UNCONNECTED,
m_axis_mm2s_tready => axi_dma_4_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tvalid => axi_dma_4_M_AXIS_MM2S_TVALID,
mm2s_introut => axi_dma_4_mm2s_introut,
mm2s_prmry_reset_out_n => NLW_axi_dma_4_mm2s_prmry_reset_out_n_UNCONNECTED,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(9 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(9 downto 0),
s_axi_lite_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
s_axi_lite_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID,
s_axi_lite_awaddr(9 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(9 downto 0),
s_axi_lite_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
s_axi_lite_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID,
s_axi_lite_bready => processing_system7_0_axi_periph_M06_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
s_axi_lite_rready => processing_system7_0_axi_periph_M06_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
s_axi_lite_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
s_axi_lite_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID
);
axi_gpio_0: component design_SWandHW_standalone_axi_gpio_0_0
port map (
gpio_io_i(3 downto 0) => axi_gpio_0_GPIO_TRI_I(3 downto 0),
gpio_io_o(3 downto 0) => axi_gpio_0_GPIO_TRI_O(3 downto 0),
gpio_io_t(3 downto 0) => axi_gpio_0_GPIO_TRI_T(3 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_mem_intercon: entity work.design_SWandHW_standalone_axi_mem_intercon_1
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arid(2 downto 0) => axi_mem_intercon_M00_AXI_ARID(2 downto 0),
M00_AXI_arlen(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awburst(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
M00_AXI_awcache(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
M00_AXI_awid(2 downto 0) => axi_mem_intercon_M00_AXI_AWID(2 downto 0),
M00_AXI_awlen(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
M00_AXI_awlock(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awqos(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awsize(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bid(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rid(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
M00_AXI_rlast => axi_mem_intercon_M00_AXI_RLAST,
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wid(2 downto 0) => axi_mem_intercon_M00_AXI_WID(2 downto 0),
M00_AXI_wlast => axi_mem_intercon_M00_AXI_WLAST,
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_dma_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_dma_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_dma_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_dma_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_dma_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready(0) => axi_dma_M_AXI_MM2S_ARREADY(0),
S00_AXI_arsize(2 downto 0) => axi_dma_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid(0) => axi_dma_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(31 downto 0) => axi_dma_M_AXI_MM2S_RDATA(31 downto 0),
S00_AXI_rlast(0) => axi_dma_M_AXI_MM2S_RLAST(0),
S00_AXI_rready(0) => axi_dma_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_dma_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid(0) => axi_dma_M_AXI_MM2S_RVALID(0),
S01_ACLK => processing_system7_0_FCLK_CLK0,
S01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S01_AXI_awaddr(31 downto 0) => axi_dma_1_M_AXI_S2MM_AWADDR(31 downto 0),
S01_AXI_awburst(1 downto 0) => axi_dma_1_M_AXI_S2MM_AWBURST(1 downto 0),
S01_AXI_awcache(3 downto 0) => axi_dma_1_M_AXI_S2MM_AWCACHE(3 downto 0),
S01_AXI_awlen(7 downto 0) => axi_dma_1_M_AXI_S2MM_AWLEN(7 downto 0),
S01_AXI_awprot(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWPROT(2 downto 0),
S01_AXI_awready => axi_dma_1_M_AXI_S2MM_AWREADY,
S01_AXI_awsize(2 downto 0) => axi_dma_1_M_AXI_S2MM_AWSIZE(2 downto 0),
S01_AXI_awvalid => axi_dma_1_M_AXI_S2MM_AWVALID,
S01_AXI_bready => axi_dma_1_M_AXI_S2MM_BREADY,
S01_AXI_bresp(1 downto 0) => axi_dma_1_M_AXI_S2MM_BRESP(1 downto 0),
S01_AXI_bvalid => axi_dma_1_M_AXI_S2MM_BVALID,
S01_AXI_wdata(31 downto 0) => axi_dma_1_M_AXI_S2MM_WDATA(31 downto 0),
S01_AXI_wlast => axi_dma_1_M_AXI_S2MM_WLAST,
S01_AXI_wready => axi_dma_1_M_AXI_S2MM_WREADY,
S01_AXI_wstrb(3 downto 0) => axi_dma_1_M_AXI_S2MM_WSTRB(3 downto 0),
S01_AXI_wvalid => axi_dma_1_M_AXI_S2MM_WVALID,
S02_ACLK => processing_system7_0_FCLK_CLK0,
S02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S02_AXI_araddr(31 downto 0) => axi_dma_2_M_AXI_MM2S_ARADDR(31 downto 0),
S02_AXI_arburst(1 downto 0) => axi_dma_2_M_AXI_MM2S_ARBURST(1 downto 0),
S02_AXI_arcache(3 downto 0) => axi_dma_2_M_AXI_MM2S_ARCACHE(3 downto 0),
S02_AXI_arlen(7 downto 0) => axi_dma_2_M_AXI_MM2S_ARLEN(7 downto 0),
S02_AXI_arprot(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARPROT(2 downto 0),
S02_AXI_arready => axi_dma_2_M_AXI_MM2S_ARREADY,
S02_AXI_arsize(2 downto 0) => axi_dma_2_M_AXI_MM2S_ARSIZE(2 downto 0),
S02_AXI_arvalid => axi_dma_2_M_AXI_MM2S_ARVALID,
S02_AXI_rdata(31 downto 0) => axi_dma_2_M_AXI_MM2S_RDATA(31 downto 0),
S02_AXI_rlast => axi_dma_2_M_AXI_MM2S_RLAST,
S02_AXI_rready => axi_dma_2_M_AXI_MM2S_RREADY,
S02_AXI_rresp(1 downto 0) => axi_dma_2_M_AXI_MM2S_RRESP(1 downto 0),
S02_AXI_rvalid => axi_dma_2_M_AXI_MM2S_RVALID,
S03_ACLK => processing_system7_0_FCLK_CLK0,
S03_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S03_AXI_awaddr(31 downto 0) => axi_dma_3_M_AXI_S2MM_AWADDR(31 downto 0),
S03_AXI_awburst(1 downto 0) => axi_dma_3_M_AXI_S2MM_AWBURST(1 downto 0),
S03_AXI_awcache(3 downto 0) => axi_dma_3_M_AXI_S2MM_AWCACHE(3 downto 0),
S03_AXI_awlen(7 downto 0) => axi_dma_3_M_AXI_S2MM_AWLEN(7 downto 0),
S03_AXI_awprot(2 downto 0) => axi_dma_3_M_AXI_S2MM_AWPROT(2 downto 0),
S03_AXI_awready => axi_dma_3_M_AXI_S2MM_AWREADY,
S03_AXI_awsize(2 downto 0) => axi_dma_3_M_AXI_S2MM_AWSIZE(2 downto 0),
S03_AXI_awvalid => axi_dma_3_M_AXI_S2MM_AWVALID,
S03_AXI_bready => axi_dma_3_M_AXI_S2MM_BREADY,
S03_AXI_bresp(1 downto 0) => axi_dma_3_M_AXI_S2MM_BRESP(1 downto 0),
S03_AXI_bvalid => axi_dma_3_M_AXI_S2MM_BVALID,
S03_AXI_wdata(31 downto 0) => axi_dma_3_M_AXI_S2MM_WDATA(31 downto 0),
S03_AXI_wlast => axi_dma_3_M_AXI_S2MM_WLAST,
S03_AXI_wready => axi_dma_3_M_AXI_S2MM_WREADY,
S03_AXI_wstrb(3 downto 0) => axi_dma_3_M_AXI_S2MM_WSTRB(3 downto 0),
S03_AXI_wvalid => axi_dma_3_M_AXI_S2MM_WVALID,
S04_ACLK => processing_system7_0_FCLK_CLK0,
S04_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S04_AXI_araddr(31 downto 0) => axi_dma_4_M_AXI_MM2S_ARADDR(31 downto 0),
S04_AXI_arburst(1 downto 0) => axi_dma_4_M_AXI_MM2S_ARBURST(1 downto 0),
S04_AXI_arcache(3 downto 0) => axi_dma_4_M_AXI_MM2S_ARCACHE(3 downto 0),
S04_AXI_arlen(7 downto 0) => axi_dma_4_M_AXI_MM2S_ARLEN(7 downto 0),
S04_AXI_arprot(2 downto 0) => axi_dma_4_M_AXI_MM2S_ARPROT(2 downto 0),
S04_AXI_arready => axi_dma_4_M_AXI_MM2S_ARREADY,
S04_AXI_arsize(2 downto 0) => axi_dma_4_M_AXI_MM2S_ARSIZE(2 downto 0),
S04_AXI_arvalid => axi_dma_4_M_AXI_MM2S_ARVALID,
S04_AXI_rdata(31 downto 0) => axi_dma_4_M_AXI_MM2S_RDATA(31 downto 0),
S04_AXI_rlast => axi_dma_4_M_AXI_MM2S_RLAST,
S04_AXI_rready => axi_dma_4_M_AXI_MM2S_RREADY,
S04_AXI_rresp(1 downto 0) => axi_dma_4_M_AXI_MM2S_RRESP(1 downto 0),
S04_AXI_rvalid => axi_dma_4_M_AXI_MM2S_RVALID
);
axis_data_fifo_0: component design_SWandHW_standalone_axis_data_fifo_0_0
port map (
axis_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_data_count_UNCONNECTED(31 downto 0),
axis_rd_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_axis_data_fifo_0_axis_wr_data_count_UNCONNECTED(31 downto 0),
m_axis_tdata(31 downto 0) => axis_data_fifo_0_M_AXIS_TDATA(31 downto 0),
m_axis_tkeep(3 downto 0) => axis_data_fifo_0_M_AXIS_TKEEP(3 downto 0),
m_axis_tlast => axis_data_fifo_0_M_AXIS_TLAST,
m_axis_tready => axis_data_fifo_0_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_0_M_AXIS_TVALID,
s_axis_aclk => processing_system7_0_FCLK_CLK0,
s_axis_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axis_tdata(31 downto 0) => feedforward_0_P_uOut_TDATA(31 downto 0),
s_axis_tkeep(3 downto 0) => B"1111",
s_axis_tlast => '1',
s_axis_tready => feedforward_0_P_uOut_TREADY,
s_axis_tvalid => feedforward_0_P_uOut_TVALID
);
axis_data_fifo_1: component design_SWandHW_standalone_axis_data_fifo_1_0
port map (
axis_data_count(31 downto 0) => NLW_axis_data_fifo_1_axis_data_count_UNCONNECTED(31 downto 0),
axis_rd_data_count(31 downto 0) => NLW_axis_data_fifo_1_axis_rd_data_count_UNCONNECTED(31 downto 0),
axis_wr_data_count(31 downto 0) => NLW_axis_data_fifo_1_axis_wr_data_count_UNCONNECTED(31 downto 0),
m_axis_tdata(31 downto 0) => axis_data_fifo_1_M_AXIS_TDATA(31 downto 0),
m_axis_tkeep(3 downto 0) => axis_data_fifo_1_M_AXIS_TKEEP(3 downto 0),
m_axis_tlast => axis_data_fifo_1_M_AXIS_TLAST,
m_axis_tready => axis_data_fifo_1_M_AXIS_TREADY,
m_axis_tvalid => axis_data_fifo_1_M_AXIS_TVALID,
s_axis_aclk => processing_system7_0_FCLK_CLK0,
s_axis_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axis_tdata(31 downto 0) => feedforward_0_P_netOut_TDATA(31 downto 0),
s_axis_tkeep(3 downto 0) => B"1111",
s_axis_tlast => '1',
s_axis_tready => feedforward_0_P_netOut_TREADY,
s_axis_tvalid => feedforward_0_P_netOut_TVALID
);
feedforward_0: component design_SWandHW_standalone_feedforward_0_0
port map (
P_WandB_TDATA(31 downto 0) => axi_dma_4_M_AXIS_MM2S_TDATA(31 downto 0),
P_WandB_TREADY => axi_dma_4_M_AXIS_MM2S_TREADY,
P_WandB_TVALID => axi_dma_4_M_AXIS_MM2S_TVALID,
P_config_TDATA(31 downto 0) => axi_dma_2_M_AXIS_MM2S_TDATA(31 downto 0),
P_config_TREADY => axi_dma_2_M_AXIS_MM2S_TREADY,
P_config_TVALID => axi_dma_2_M_AXIS_MM2S_TVALID,
P_netIn_TDATA(31 downto 0) => axi_dma_M_AXIS_MM2S_TDATA(31 downto 0),
P_netIn_TREADY => axi_dma_M_AXIS_MM2S_TREADY,
P_netIn_TVALID => axi_dma_M_AXIS_MM2S_TVALID,
P_netOut_TDATA(31 downto 0) => feedforward_0_P_netOut_TDATA(31 downto 0),
P_netOut_TREADY => feedforward_0_P_netOut_TREADY,
P_netOut_TVALID => feedforward_0_P_netOut_TVALID,
P_uOut_TDATA(31 downto 0) => feedforward_0_P_uOut_TDATA(31 downto 0),
P_uOut_TREADY => feedforward_0_P_uOut_TREADY,
P_uOut_TVALID => feedforward_0_P_uOut_TVALID,
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_processing_system7_0_100M_peripheral_aresetn(0),
interrupt => feedforward_0_interrupt,
s_axi_AXILiteS_ARADDR(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(4 downto 0),
s_axi_AXILiteS_ARREADY => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_AXILiteS_ARVALID => processing_system7_0_axi_periph_M01_AXI_ARVALID,
s_axi_AXILiteS_AWADDR(4 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(4 downto 0),
s_axi_AXILiteS_AWREADY => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_AXILiteS_AWVALID => processing_system7_0_axi_periph_M01_AXI_AWVALID,
s_axi_AXILiteS_BREADY => processing_system7_0_axi_periph_M01_AXI_BREADY,
s_axi_AXILiteS_BRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_AXILiteS_BVALID => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_AXILiteS_RDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_AXILiteS_RREADY => processing_system7_0_axi_periph_M01_AXI_RREADY,
s_axi_AXILiteS_RRESP(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_AXILiteS_RVALID => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_AXILiteS_WDATA(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_AXILiteS_WREADY => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_AXILiteS_WSTRB(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_AXILiteS_WVALID => processing_system7_0_axi_periph_M01_AXI_WVALID
);
processing_system7_0: component design_SWandHW_standalone_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(5 downto 0) => xlconcat_0_dout(5 downto 0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_mem_intercon_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 3) => B"000",
S_AXI_HP0_ARID(2 downto 0) => axi_mem_intercon_M00_AXI_ARID(2 downto 0),
S_AXI_HP0_ARLEN(3 downto 0) => axi_mem_intercon_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_mem_intercon_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_mem_intercon_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_mem_intercon_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => axi_mem_intercon_M00_AXI_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => axi_mem_intercon_M00_AXI_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 3) => B"000",
S_AXI_HP0_AWID(2 downto 0) => axi_mem_intercon_M00_AXI_AWID(2 downto 0),
S_AXI_HP0_AWLEN(3 downto 0) => axi_mem_intercon_M00_AXI_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => axi_mem_intercon_M00_AXI_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => axi_mem_intercon_M00_AXI_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => axi_mem_intercon_M00_AXI_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => axi_mem_intercon_M00_AXI_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => axi_mem_intercon_M00_AXI_AWVALID,
S_AXI_HP0_BID(5 downto 0) => axi_mem_intercon_M00_AXI_BID(5 downto 0),
S_AXI_HP0_BREADY => axi_mem_intercon_M00_AXI_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
S_AXI_HP0_BVALID => axi_mem_intercon_M00_AXI_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => axi_mem_intercon_M00_AXI_RID(5 downto 0),
S_AXI_HP0_RLAST => axi_mem_intercon_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_mem_intercon_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_mem_intercon_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
S_AXI_HP0_WID(5 downto 3) => B"000",
S_AXI_HP0_WID(2 downto 0) => axi_mem_intercon_M00_AXI_WID(2 downto 0),
S_AXI_HP0_WLAST => axi_mem_intercon_M00_AXI_WLAST,
S_AXI_HP0_WREADY => axi_mem_intercon_M00_AXI_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
S_AXI_HP0_WVALID => axi_mem_intercon_M00_AXI_WVALID,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_SWandHW_standalone_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready => processing_system7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => processing_system7_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready => processing_system7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => processing_system7_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => processing_system7_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => processing_system7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => processing_system7_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => processing_system7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => processing_system7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wvalid => processing_system7_0_axi_periph_M03_AXI_WVALID,
M04_ACLK => processing_system7_0_FCLK_CLK0,
M04_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => processing_system7_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid => processing_system7_0_axi_periph_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => processing_system7_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid => processing_system7_0_axi_periph_M04_AXI_AWVALID,
M04_AXI_bready => processing_system7_0_axi_periph_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => processing_system7_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => processing_system7_0_axi_periph_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => processing_system7_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => processing_system7_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wvalid => processing_system7_0_axi_periph_M04_AXI_WVALID,
M05_ACLK => processing_system7_0_FCLK_CLK0,
M05_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M05_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => processing_system7_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid => processing_system7_0_axi_periph_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => processing_system7_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid => processing_system7_0_axi_periph_M05_AXI_AWVALID,
M05_AXI_bready => processing_system7_0_axi_periph_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => processing_system7_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => processing_system7_0_axi_periph_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => processing_system7_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => processing_system7_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wvalid => processing_system7_0_axi_periph_M05_AXI_WVALID,
M06_ACLK => processing_system7_0_FCLK_CLK0,
M06_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M06_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_ARADDR(31 downto 0),
M06_AXI_arready => processing_system7_0_axi_periph_M06_AXI_ARREADY,
M06_AXI_arvalid => processing_system7_0_axi_periph_M06_AXI_ARVALID,
M06_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_AWADDR(31 downto 0),
M06_AXI_awready => processing_system7_0_axi_periph_M06_AXI_AWREADY,
M06_AXI_awvalid => processing_system7_0_axi_periph_M06_AXI_AWVALID,
M06_AXI_bready => processing_system7_0_axi_periph_M06_AXI_BREADY,
M06_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_BRESP(1 downto 0),
M06_AXI_bvalid => processing_system7_0_axi_periph_M06_AXI_BVALID,
M06_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_RDATA(31 downto 0),
M06_AXI_rready => processing_system7_0_axi_periph_M06_AXI_RREADY,
M06_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M06_AXI_RRESP(1 downto 0),
M06_AXI_rvalid => processing_system7_0_axi_periph_M06_AXI_RVALID,
M06_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M06_AXI_WDATA(31 downto 0),
M06_AXI_wready => processing_system7_0_axi_periph_M06_AXI_WREADY,
M06_AXI_wvalid => processing_system7_0_axi_periph_M06_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_SWandHW_standalone_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
xlconcat_0: component design_SWandHW_standalone_xlconcat_0_0
port map (
In0(0) => feedforward_0_interrupt,
In1(0) => axi_dma_mm2s_introut,
In2(0) => axi_dma_1_s2mm_introut,
In3(0) => axi_dma_2_mm2s_introut,
In4(0) => axi_dma_3_s2mm_introut,
In5(0) => axi_dma_4_mm2s_introut,
dout(5 downto 0) => xlconcat_0_dout(5 downto 0)
);
end STRUCTURE;
| gpl-3.0 | 06948d286ff8ed70ab88334845d08ac7 | 0.682359 | 2.799393 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/TEST_hls_example_1_0/hdl/vhdl/example_AXILiteS_s_axi.vhd | 1 | 12,381 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity example_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
mode :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity example_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of mode
-- bit 31~0 - mode[31:0] (Read/Write)
-- 0x14 : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of example_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_MODE_DATA_0 : INTEGER := 16#10#;
constant ADDR_MODE_CTRL : INTEGER := 16#14#;
constant ADDR_BITS : INTEGER := 5;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_mode : UNSIGNED(31 downto 0);
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_MODE_DATA_0 =>
rdata_data <= RESIZE(int_mode(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
mode <= STD_LOGIC_VECTOR(int_mode);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_MODE_DATA_0) then
int_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_mode(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 | ba58942b0f6e70fa745574b243404446 | 0.451983 | 3.824838 | false | false | false | false |
minijackson/school-vhdl | E2/TP1/labigclock.vhd | 1 | 2,603 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bigClock is
port (
minuteUnits : out std_logic_vector(3 downto 0);
minuteTenths : out std_logic_vector(3 downto 0);
hoursUnits : out std_logic_vector(3 downto 0);
hoursTenths : out std_logic_vector(3 downto 0);
ctr : out std_logic_vector(42 downto 7);
clk : in std_logic;
reset : in std_logic
);
end bigClock;
architecture bigClockArch of bigClock is
signal mu_eq9, mt_eq5, m_eq59, mhu_eq959, hu_eq3, hu_eq9, ht_eq2, mh_eq2359, generalEnable, muEnable, mtEnable, htEnable, huEnable, mtRazs: std_logic;
signal mUnits, mTenths, hUnits, hTenths : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(42 downto 7); -- Yeah!
begin
process (clk, reset) is
begin
if reset = '1' then counter <= (others => '0');
elsif rising_edge(clk) then
if unsigned(counter) >= 499 then
counter <= (others => '0');
else counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process;
ctr <= counter;
minuteUnits <= mUnits;
minuteTenths <= mTenths;
hoursUnits <= hUnits;
hoursTenths <= hTenths;
generalEnable <= '1' when unsigned(counter) >= 499 else '0';
minuteUnitsComponent : entity work.clockCounter port map (
enable => muEnable,
razs => mh_eq2359,
equalMax => mu_eq9,
clk => clk,
reset => reset,
dataOut => mUnits
);
minuteTenthsComponent : entity work.clockCounter
generic map (
max => 5
)
port map (
enable => mtEnable,
razs => mtRazs,
equalMax => mt_eq5,
clk => clk,
reset => reset,
dataOut => mTenths
);
hoursUnitsComponent : entity work.clockCounter port map (
enable => huEnable,
razs => mh_eq2359,
equalMax => hu_eq9,
clk => clk,
reset => reset,
dataOut => hUnits
);
hoursTenthsComponent : entity work.clockCounter port map (
enable => htEnable,
razs => mh_eq2359,
clk => clk,
reset => reset,
dataOut => hTenths
);
m_eq59 <= mt_eq5 and mu_eq9;
mhu_eq959 <= m_eq59 and hu_eq9;
hu_eq3 <= '1' when hUnits = "0011" else '0';
ht_eq2 <= '1' when hTenths = "0010" else '0';
mh_eq2359 <= ht_eq2 and hu_eq3 and m_eq59;
muEnable <= generalEnable;
mtEnable <= generalEnable and mu_eq9;
huEnable <= generalEnable and m_eq59;
htEnable <= generalEnable and mhu_eq959;
mtRazs <= m_eq59 or mh_eq2359;
end bigClockArch;
| mit | bdbf58bcc5169d21aed37caed8bd1119 | 0.597772 | 2.981672 | false | false | false | false |
yahniukov/AES-128_VHDL | Design Sources/MixColumns_module.vhd | 1 | 5,121 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity MixColumns_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
start : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC);
end MixColumns_module;
architecture RTL of MixColumns_module is
-----------------------------
----------- TYPES -----------
-----------------------------
TYPE matrix_index is array (15 downto 0) of std_logic_vector(7 downto 0);
TYPE shift_index is array (15 downto 0) of std_logic_vector(8 downto 0);
-----------------------------
---------- SIGNALS ----------
-----------------------------
SIGNAL shiftby_2, shiftby_3, xored : shift_index;
SIGNAL matrix, matrix_out, multby_2, multby_3 : matrix_index;
BEGIN
-- Initialize and Reset process
reset_n_init_process : process(reset)
begin
if(rising_edge(reset)) then
for i in 15 downto 0 loop
shiftby_2(15-i) <= (others => '0');
shiftby_3(15-i) <= (others => '0');
xored(15-i) <= (others => '0');
matrix(15-i) <= (others => '0');
matrix_out(15-i) <= (others => '0');
multby_2(15-i) <= (others => '0');
multby_3(15-i) <= (others => '0');
end loop;
end if;
end process reset_n_init_process;
--first take the input and map it to a 4X4 matrix
input_to_matrix:PROCESS(start)
BEGIN
if(rising_edge(start) and clock = '1') then
FOR i IN 15 DOWNTO 0 LOOP
matrix(15-i) <= data_in(8*i+7 downto 8*i);
END LOOP;
end if;
END PROCESS input_to_matrix;
-- Notice that the multiplied matrix element are 1,2, 3 see above matrix
--then it will be easier if we multiply all the matrix by 2, then by 3, and
--then choose what is needed
-- first multiply by 2
multiply_matrix_by2:PROCESS(matrix, shiftby_2)
BEGIN
if(clock = '1') then
FOR i IN 15 downto 0 LOOP
shiftby_2(i) <= matrix(i) & '0';
IF (shiftby_2(i)(8)='1') THEN -- for values exceeding 7 bit field, XOR it with the irreducible vector given in the spec
multby_2(i) <= shiftby_2(i)(7 downto 0) XOR "00011011";
ELSE
multby_2(i) <= shiftby_2(i)(7 downto 0);
END IF;
END LOOP;
end if;
END PROCESS multiply_matrix_by2;
--multiply by 3
multiply_matrix_by3:PROCESS(matrix, shiftby_3, xored)
BEGIN
if(clock = '1') then
FOR i IN 15 downto 0 LOOP
shiftby_3(i) <= matrix(i) & '0'; -- 2*value
xored(i) <= shiftby_3(i) XOR '0' & matrix(i); --3*value = 2*value XOR value
IF (xored(i)(8)='1') THEN
multby_3(i) <= xored(i)(7 downto 0) XOR "00011011"; -- for values exceeding 7 bit field, XOR it with the irreducible vector given in the spec
ELSE
multby_3(i) <= xored(i)(7 downto 0);
END IF;
END LOOP;
end if;
END PROCESS multiply_matrix_by3;
-- 4X4 matrix multiplication & mix column
--row one
matrix_out(0) <= multby_2(0) XOR multby_3(1) XOR matrix(2) XOR matrix(3);
matrix_out(4) <= multby_2(4) XOR multby_3(5) XOR matrix(6) XOR matrix(7);
matrix_out(8) <= multby_2(8) XOR multby_3(9) XOR matrix(10) XOR matrix(11);
matrix_out(12) <= multby_2(12) XOR multby_3(13) XOR matrix(14) XOR matrix(15);
--row two
matrix_out(1) <= matrix(0) XOR multby_2(1) XOR multby_3(2) XOR matrix(3);
matrix_out(5) <= matrix(4) XOR multby_2(5) XOR multby_3(6) XOR matrix(7);
matrix_out(9) <= matrix(8) XOR multby_2(9) XOR multby_3(10) XOR matrix(11);
matrix_out(13) <= matrix(12) XOR multby_2(13) XOR multby_3(14) XOR matrix(15);
--row three
matrix_out(2) <= matrix(0) XOR matrix(1) XOR multby_2(2) XOR multby_3(3);
matrix_out(6) <= matrix(4) XOR matrix(5) XOR multby_2(6) XOR multby_3(7);
matrix_out(10) <= matrix(8) XOR matrix(9) XOR multby_2(10) XOR multby_3(11);
matrix_out(14) <= matrix(12) XOR matrix(13) XOR multby_2(14) XOR multby_3(15);
--row four
matrix_out(3) <= multby_3(0) XOR matrix(1) XOR matrix(2) XOR multby_2(3);
matrix_out(7) <= multby_3(4) XOR matrix(5) XOR matrix(6) XOR multby_2(7);
matrix_out(11) <= multby_3(8) XOR matrix(9) XOR matrix(10) XOR multby_2(11);
matrix_out(15) <= multby_3(12) XOR matrix(13) XOR matrix(14) XOR multby_2(15);
--mapping back to a vector
matrix_to_vector:PROCESS(matrix_out)
BEGIN
if(clock = '1') then
FOR i IN 15 downto 0 LOOP
data_out(8*i+7 downto 8*i) <= matrix_out(15-i);
END LOOP;
finish <= '1';
end if;
END PROCESS matrix_to_vector;
end RTL;
| mit | dbce441548cc0c858792bcd0b697af51 | 0.54091 | 3.325325 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/TEST_hls_example_1_0/hdl/vhdl/example_fadd_32ns_32ns_32_5_full_dsp.vhd | 1 | 3,360 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity example_fadd_32ns_32ns_32_5_full_dsp is
generic (
ID : integer := 0;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of example_fadd_32ns_32ns_32_5_full_dsp is
--------------------- Component ---------------------
component example_ap_fadd_3_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
example_ap_fadd_3_full_dsp_32_u : component example_ap_fadd_3_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 26e6e3a75fe0ea847500709be6a1d3de | 0.4875 | 3.496358 | false | false | false | false |
makestuff/spi-talk | templates/ss/vhdl/top_level.vhdl | 1 | 3,699 | --
-- Copyright (C) 2009-2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
sysClk_in : in std_logic; -- system clock
-- USB interface -----------------------------------------------------------------------------
serClk_in : in std_logic; -- serial clock (async to sysClk_in)
serData_in : in std_logic; -- serial data in
serData_out : out std_logic; -- serial data out
-- Peripheral interface ----------------------------------------------------------------------
spiClk_out : out std_logic;
spiData_out : out std_logic;
spiData_in : in std_logic;
spiCS_out : out std_logic_vector(NUM_DEVS-1 downto 0)
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
begin
-- CommFPGA module
comm_fpga_ss : entity work.comm_fpga_ss
port map(
clk_in => sysClk_in,
reset_in => '0',
-- USB interface
serClk_in => serClk_in,
serData_in => serData_in,
serData_out => serData_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => sysClk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk_out,
spiData_out => spiData_out,
spiData_in => spiData_in,
spiCS_out => spiCS_out
);
end architecture;
| gpl-3.0 | 10c11543504e019fc811b7450b4e85e6 | 0.591782 | 3.587779 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/hdl/sync.vhd | 1 | 9,593 | --------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: sync.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::IGLOO> <Die::AGLN250V2Z> <Package::100 VQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my.all;
--h_pulse : INTEGER := 96; --horiztonal sync pulse width in pixels
--h_bp : INTEGER := 48; --horiztonal back porch width in pixels
--h_pixels : INTEGER := 640; --horiztonal display width in pixels
--h_fp : INTEGER := 16; --horiztonal front porch width in pixels
--v_pulse : INTEGER := 2; --vertical sync pulse width in rows
--v_bp : INTEGER := 33; --vertical back porch width in rows
--v_pixels : INTEGER := 480; --vertical display width in rows
--v_fp : INTEGER := 10 --vertical front porch width in rows
ENTITY SYNC IS
GENERIC(
h_pulse : INTEGER := 112; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 248; --horiztonal back porch width in pixels
h_pixels : INTEGER := 1280; --horiztonal display width in pixels
h_fp : INTEGER := 48; --horiztonal front porch width in pixels
v_pulse : INTEGER := 3; --vertical sync pulse width in rows
v_bp : INTEGER := 38; --vertical back porch width in rows
v_pixels : INTEGER := 1024; --vertical display width in rows
v_fp : INTEGER := 1 --vertical front porch width in rows
);
PORT(
SYSRESET, CLK: IN STD_LOGIC;
HSYNC,VSYNC: OUT STD_LOGIC;
R,G,B : OUT STD_LOGIC;
KEYS: IN STD_LOGIC_VECTOR(3 downto 0);
S: IN STD_LOGIC_VECTOR(1 downto 0)
);
END SYNC;
ARCHITECTURE MAIN OF SYNC IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
SIGNAL RGB: STD_LOGIC; -- RGB iekshejais signals
SIGNAL DRAW1,DRAW2: STD_LOGIC; -- Papildus signali DRAW indikatora, kas nosaka, vai vajag krasot pikseli vai ne.
SIGNAL SQ_X1,SQ_Y1: INTEGER RANGE 0 TO h_period := 600; -- Papildus signali pozicijas referencei. Pirmais kvadrats saksies 600:600 koord.
SIGNAL SQ_X2,SQ_Y2: INTEGER RANGE 0 TO h_period := 500; -- Otrais kvadrats saksies 500:500 pikselu koord.
SIGNAL HPOS: INTEGER RANGE 0 TO h_period :=0; -- Pashreizeejaa horizontala poziicija ekraanaa
SIGNAL VPOS: INTEGER RANGE 0 TO v_period :=0; -- Pashreizeejaa vertikala pozicija ekrana
BEGIN
SQ(HPOS,VPOS,SQ_X1,SQ_Y1,RGB,DRAW1); -- Tiek izsauktas proceduras kvadrata zimeshanai (no my.vhd). Tiek zimeti divi kvadrati.
SQ(HPOS,VPOS,SQ_X2,SQ_Y2,RGB,DRAW2);
PROCESS(CLK, SYSRESET)
BEGIN
IF(SYSRESET='0') THEN
HPOS <= 0;
VPOS <= 0;
R <= '0';
G <= '0';
B <= '0';
ELSIF(rising_edge(CLK))THEN
IF(DRAW1='1')THEN
IF(S(0)='1')THEN -- Ja pirma poga (pirmais kvadrats izvelets) nospiesta, zimet to sarkanu. Citadak - baltu.
R<= '1';
G<= '0';
B<= '0';
ELSE
R<= '1';
G<= '1';
B<= '1';
END IF;
END IF;
IF(DRAW2='1')THEN -- Ja otra poga (otrais kvadrats izvelets) nospiesta, zimet to sarkanu. Citadak - baltu.
IF(S(1)='1')THEN
R<= '1';
G<= '0';
B<= '0';
ELSE
R<= '1';
G<= '1';
B<= '1';
END IF;
END IF;
IF(DRAW1='0' AND DRAW2='0')THEN -- Ja nekas netiek zimets, tad izvadit ekranu melna krasa.
R<= '0';
G<= '0';
B<= '0';
END IF;
---------------------------------------------------------------------------------
-- Katru CLK ciklu, tiek palielinala HPOS vertiba par 1, un, --
-- kad sasniegtas linijas beigas, atstata HPOS uz 0, un pelielina VPOS par 1! --
-- Rezultata ekrans tiek skenets liniju pec linijas. --
---------------------------------------------------------------------------------
IF(HPOS < h_period)THEN
HPOS<=HPOS+1;
ELSE
HPOS<=0;
IF(VPOS < v_period)THEN
VPOS<=VPOS+1;
ELSE
VPOS<=0;
---------------------------------------------------------------------------------
-- Katraa kadraa (kad palielinas VPOS), var atjaunot kvadrata --
-- zimeshanas poziciju, atkariba no papildus 4 pogu vertibas. --
-- Tiek palielinats vai samazinats par 5 pikseliem. --
-- Pec tam VPOS tiek atiestatits uz '0'un tiek zimets jauns kadrs! --
---------------------------------------------------------------------------------
IF(S(0)='1')THEN
IF(KEYS(0)='0')THEN
SQ_X1<=SQ_X1+5;
END IF;
IF(KEYS(1)='0')THEN
SQ_X1<=SQ_X1-5;
END IF;
IF(KEYS(2)='0')THEN
SQ_Y1<=SQ_Y1+5;
END IF;
IF(KEYS(3)='0')THEN
SQ_Y1<=SQ_Y1-5;
END IF;
END IF;
IF(S(1)='1')THEN
IF(KEYS(0)='0')THEN
SQ_X2<=SQ_X2+5;
END IF;
IF(KEYS(1)='0')THEN
SQ_X2<=SQ_X2-5;
END IF;
IF(KEYS(2)='0')THEN
SQ_Y2<=SQ_Y2+5;
END IF;
IF(KEYS(3)='0')THEN
SQ_Y2<=SQ_Y2-5;
END IF;
END IF;
END IF;
END IF;
----------------------------------------------------------------------------
-- Sinhronizacija. Horizontalajam sinhronizacijas signalam (HSYNC) ir --
-- jabut '0' starp FP(front pouch) un BP(back pouch) + SYNC. --
-- Tatad, ja HPOS > 48 (FP beigas) UN HPOS < 160 (48 FP + 112 SYNC pulss) --
-- , tad HSYNC == '0'. Ja nee, tad HSYNC == '1' --
----------------------------------------------------------------------------
IF(HPOS > h_fp AND HPOS < h_fp+h_pulse)THEN
HSYNC<='0';
ELSE
HSYNC<='1';
END IF;
----------------------------------------------------------------------------
-- Sinhronizacija. Vertikala sinhronizacijas signalam (VSYNC) ir --
-- jabut '0' starp FP(front pouch) un BP(back pouch). --
-- Tatad, ja VPOS > 0 UN VPOS < 4 --
-- , tad VSYNC == '0'. Ja nee, tad V SYNC == '1' --
----------------------------------------------------------------------------
IF(VPOS > 0 AND VPOS < v_pulse)THEN
VSYNC<='0';
ELSE
VSYNC<='1';
END IF;
----------------------------------------------------------------------------
-- No FP sakuma lidz BP beigam RGB signalam ir jabut '0' limeni. --
-- Tatad HPOS ir jabut starp 0 un FP+SYNC+BP un VPOS tapat. --
----------------------------------------------------------------------------
IF((HPOS > 0 AND HPOS < h_pulse + h_bp + h_fp)OR(VPOS>0 AND VPOS < v_pulse + v_bp + v_fp))THEN
R<= '0';
G<= '0';
B<= '0';
END IF;
END IF;
END PROCESS;
END MAIN; | gpl-2.0 | 1f919e6fca5ae687e483dc7d7fd62f4f | 0.359533 | 4.472261 | false | false | false | false |
brotatos/Whack-A-Mole | src/WhackAMole.vhd | 1 | 3,320 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity WhackAMole is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
DISP_EN : out STD_LOGIC_VECTOR (3 downto 0);
LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0));
end WhackAMole;
architecture Behavioral of WhackAMole is
component clk_div2 is
Port ( clk : in std_logic;
sclk : out std_logic);
end component;
component countdown_clk_div is
Port ( clk : in std_logic;
sclk : out std_logic);
end component;
component Countdown is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TIME_LEFT : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component sseg_dec is
Port ( ALU_VAL : in std_logic_vector(7 downto 0);
SIGN : in std_logic;
VALID : in std_logic;
CLK : in std_logic;
DISP_EN : out std_logic_vector(3 downto 0);
SEGMENTS : out std_logic_vector(7 downto 0));
end component;
component ScoreKeeper is
Port ( LEDS : in STD_LOGIC_VECTOR(7 downto 0);
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TIME_LEFT : in STD_LOGIC_VECTOR (7 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
SCORE : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component SetLED is
Port ( RAND_INT : in STD_LOGIC_VECTOR (2 downto 0);
LEDS : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component RandomNumberGenerator is
generic ( width : integer := 3 );
Port (
clk : in std_logic;
random_num : out std_logic_vector (width-1 downto 0)
);
end component;
signal randNum : std_logic_vector(2 downto 0);
signal clock_to_use, countdown_clock : std_logic;
signal led_s, the_score, the_time_left : std_logic_vector(7 downto 0);
begin
slow_clk : clk_div2
port map ( clk => CLK,
sclk => clock_to_use
);
countdownClock : countdown_clk_div
port map ( clk => CLK,
sclk => countdown_clock
);
rand : RandomNumberGenerator
port map ( clk => clock_to_use,
random_num => randNum
);
daLED : SetLED
port map ( RAND_INT => randNum,
LEDS => led_s
);
counter : Countdown
port map ( CLK => countdown_clock,
RESET => RESET,
TIME_LEFT => the_time_left
);
score : ScoreKeeper
port map ( LEDS => led_s,
RESET => RESET,
CLK => clock_to_use,
TIME_LEFT => the_time_left,
SWITCHES => SWITCHES,
SCORE => the_score
);
egg : sseg_dec
port map ( ALU_VAL => the_score,
SIGN => '0',
VALID => '1',
CLK => CLK,
DISP_EN => DISP_EN,
SEGMENTS => SEGMENTS
);
LEDS <= led_s;
end Behavioral;
| mit | a87a8f58b5ffd641a3660d6c24997361 | 0.498795 | 3.961814 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_2/hdl/vhdl/feedforward_p_uOut.vhd | 2 | 4,111 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_p_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 64;
awidth : integer := 8;
mem_size : integer := 140
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_p_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_p_uOut is
generic (
DataWidth : INTEGER := 64;
AddressRange : INTEGER := 140;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_p_uOut is
component feedforward_p_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
| gpl-3.0 | f59600615eda2153e44faad3791d7608 | 0.544393 | 3.516681 | false | false | false | false |
brotatos/Whack-A-Mole | src/Countdown.vhd | 1 | 729 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Countdown is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
TIME_LEFT : out STD_LOGIC_VECTOR (7 downto 0));
end Countdown;
architecture Behavioral of Countdown is
signal time_tmp : STD_LOGIC_VECTOR(7 downto 0) := "00011110";
begin
countdown: process (CLK, RESET, time_tmp)
begin
if (time_tmp > "00000000") then
if (rising_edge(CLK)) then
time_tmp <= time_tmp - 1;
end if;
end if;
if (RESET = '1') then
time_tmp <= "00011110";
end if;
end process countdown;
TIME_LEFT <= time_tmp;
end Behavioral;
| mit | 6a8f9615d51dc397476d23591d0fd710 | 0.595336 | 3.406542 | false | false | false | false |
yahniukov/AES-128_VHDL | Design Sources/ShiftRows_module.vhd | 1 | 2,547 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ShiftRows_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
start : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC);
end ShiftRows_module;
architecture RTL of ShiftRows_module is
-----------------------------
----------- TYPES -----------
-----------------------------
TYPE matrix_index IS array (15 downto 0) OF std_logic_vector(7 downto 0);
-----------------------------
---------- SIGNALS ----------
-----------------------------
SIGNAL matrix1, matrix2 : matrix_index;
begin
-- Initialize and Reset process
reset_n_init_process : process(reset)
begin
if(rising_edge(reset)) then
for i in 15 downto 0 loop
matrix1(15-i) <= (others => '0');
matrix2(15-i) <= (others => '0');
end loop;
end if;
end process reset_n_init_process;
-- map the 128 bit input to matrix1 so we can shift it.
vector_to_matrix1: PROCESS(start)
BEGIN
if(rising_edge(start) and clock = '1') then
FOR i IN 15 downto 0 LOOP
matrix1(15-i) <= data_in(8*i+7 downto 8*i);
END LOOP;
end if;
END PROCESS vector_to_matrix1;
-- matrix2 is actually matrix1 shifted as shown in the above example.
-- combinatorial logic
-- first column
matrix2(0) <= matrix1(0);
matrix2(1) <= matrix1(5);
matrix2(2) <= matrix1(10);
matrix2(3) <= matrix1(15);
-- second column
matrix2(4) <= matrix1(4);
matrix2(5) <= matrix1(9);
matrix2(6) <= matrix1(14);
matrix2(7) <= matrix1(3);
-- third column
matrix2(8) <= matrix1(8);
matrix2(9) <= matrix1(13);
matrix2(10) <= matrix1(2);
matrix2(11) <= matrix1(7);
-- forth column
matrix2(12) <= matrix1(12);
matrix2(13) <= matrix1(1);
matrix2(14) <= matrix1(6);
matrix2(15) <= matrix1(11);
--map matrix2 back to 128 bit vector
matrix2_to_vector: PROCESS(matrix2)
BEGIN
if(clock = '1') then
FOR i IN 15 downto 0 LOOP
data_out(8*i+7 DOWNTO 8*i) <= matrix2(15-i);
END LOOP;
finish <= '1';
end if;
END PROCESS matrix2_to_vector;
end RTL;
| mit | f6f98fe06ec9ef8fd22008052fe86fb1 | 0.518257 | 3.532594 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/stimulus/testb_0.vhd | 1 | 2,117 | --------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: testb_0.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::IGLOO> <Die::AGLN250V2Z> <Package::100 VQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity testb_0 is
end testb_0;
architecture behavioral of testb_0 is
constant SYSCLK_PERIOD : time := 50 ns;
signal SYSCLK : std_logic := '0';
signal NSYSRESET : std_logic := '0';
component Top
-- ports
port(
-- Inputs
CLKA : in std_logic;
PAD : in std_logic;
NSYSRESET : in std_logic;
button_1 : in std_logic;
button_0 : in std_logic;
-- Outputs
h_sync : out std_logic;
v_sync : out std_logic;
red : out std_logic;
green : out std_logic;
blue : out std_logic
-- Inouts
);
end component;
begin
process
variable vhdl_initial : BOOLEAN := TRUE;
begin
if ( vhdl_initial ) then
-- Assert Reset
NSYSRESET <= '0';
wait for ( SYSCLK_PERIOD * 10 );
NSYSRESET <= '1';
wait;
end if;
end process;
-- 10MHz Clock Driver
SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2.0 );
-- Instantiate Unit Under Test: Top
Top_0 : Top
-- port map
port map(
-- Inputs
CLKA => SYSCLK,
PAD => '0',
NSYSRESET => NSYSRESET,
button_1 => '1',
button_0 => '1',
-- Outputs
h_sync => open,
v_sync => open,
red => open,
green => open,
blue => open
-- Inouts
);
end behavioral;
| gpl-2.0 | 1cebc3b568198a005cd3e67991a18bf1 | 0.437411 | 4.347023 | false | true | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axi_dma_4_0/synth/design_SWandHW_standalone_axi_dma_4_0.vhd | 1 | 21,724 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_SWandHW_standalone_axi_dma_4_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_SWandHW_standalone_axi_dma_4_0;
ARCHITECTURE design_SWandHW_standalone_axi_dma_4_0_arch OF design_SWandHW_standalone_axi_dma_4_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_dma_4_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_dma_4_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_dma_4_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_4_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_dma_4_0_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_4_0,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=256,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=1,C_INCLUDE_S2MM=0,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 256,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_S2MM => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_SWandHW_standalone_axi_dma_4_0_arch;
| gpl-3.0 | dea901393c09d24f4e96eb95658a731b | 0.67193 | 2.800567 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_TEST/ipshared/xilinx.com/fifo_generator_v13_0/hdl/fifo_generator_v13_0.vhd | 4 | 91,022 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
EIJPO9OSDMvMNdOLRjwQaF6UWoBQGuoL9zzQDGu35ZPwlaCEsuX2/bXZpi1PYJWx1fIV4fCHJ2uv
SGI9TaOoYQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
jR96W/xy6IU1CwVZ4OWs9uQHbt8MxEY6OnhSFsNtb0hYTN1DbC1Q7k1rAopY5R85kliEBsNMYuT4
cKz3DR/nTb0Q1MQjXvFgtNYTIJn+x3l/oYgzda29/A8PpsBi6sz8KIglPS1mIVYa6RurRv4LkYKw
EaTHjYSLD9yqzkfqJaQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
l+dRl/KQgn5YC8NdqXiuF3uROWLYUXnJ8JxZFU5L4rAPmX7kzGUXJZnRPvSDiahmvJuv8ANZs5gh
xs5LoEmDF0CFompV5QwULgbR2Q6qtwhrEPfg6MLWV0rRtc667uYFE9KTsFf9JZKKO4/H6DzzAdIP
WLVbf01tBroj4IeWcXlkzK/313rQETBKihcoZIo95c6hdiOI/cthsmWnNjsjRy0+PSU4464xZnC5
TEcE7sJSPGR/fWSbLVlBZxn3OEvlbOzvjiNR8+/H97sx/ei8Vj94gc3yWS1QgQO+AcvptL0n+FEy
JyLr8oQ6zAVfPaFj40vg/JebO/peHp+yKYPY5w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
KHbON44TPSwtGlB38csZ+aUEMwCA8EA+f07XdNfbRNzHCWdzgmAoOb7uBfu7KxgTm9Dt8IjH0z68
A8EQUItPb1xEcce3WQRQmtBL+94WCLdFalg3R9madXc+OvDU9lJ30/cmMgJzC7ZqYcKNxsY+MltP
9DTs2k9PQ9HK8xPytpE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
wBWhADcN+GmDp1YCpVhIm6ehHfqFBS6YvXzYJFLy6Hbtd4ICJ88jM6iQIHo3AmpIauawmkob48i5
njLAuUbhiO3pjbjswXm9m5ULq7P4Zl16GePbc8+NzBZSqwO0mIMB8wKnwW++E2Rn+Nns6sn6MC2x
zonzzsSzqRzajp9fUDbbOq2tS/NGomoy1+X36PLd7Cy5AliI6CDkRHdS0IOLAwKKtEXzMUbjOg7H
Dtr1NedDgP/xgl72/c9xLklOb+LA3hVkJJO16GJEccChdA/9ulSyPIsSQmXX2bub6jXFEifZQ/8t
ihBzhm2r0HZ75QWpj/gbGRQxM/9gTCkKkqLwzg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WEJsl//nwwFukI7AawNtPva4Okhp5BPPbpvcOrHU2WhmmE+kpe4aQOMO547NxOMlZwGZ/nioOZpi
LrmS2pTou7semtJjuwLmE1hUNq1JnXEjxFJO4V4nyJ54enCYSCvNZDfgVzETNMWgvh00LJlZjybK
m78e6vo4JdsWwhR2Egwd030HGF+WhpCBmJqVrWwK5tEGZIr/dG0JtSC4lyLT4TI0WhfArNiIuILg
4hItSA/a2fFSiFfuPJXYSodzb/CpnIKOqjTcK004JEGCZJcglHRpZxK5ieOzXEV5LQE3Ouc6ACbl
rwBw6NkW9ODG4U4PpNFnPhbwmmQLP3dpSXp4+A==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 65248)
`protect data_block
bMfPX2R1tFs2k3nA+qlwsKoJziUZOwPs6DjXY9eXJxQc0uYM+CDAUpiUG6V+TMR2PH6ijTgCb6B7
pMdc5/pDtb2YVPqF9LhiTeT7x8zKqx0AuDMtUiYsaO9reuGcYhltSdOUxhRM5Oa7MwfI24R38I//
xvI73Y3knWzqvIm5U/S6lmzGiJZ6Jayeft38z0veeVMMJ63DPaqQtRaAqtYndrlmC6GSEc+hpdWc
2LC+hPSyC9dNUhKrbD5rxhyPaV5j8Todz1U/YupkRZ/4sxll4oDltMJjulXYkQS4qlLD5Y74KeI/
ABPQ1HgNly4+UW+GGXYxhFKF0JjzhFjoodO6TPOtOreYPGM6S+20QB0QlEAgzkYVXBO0ut/p50mt
Soy1FdD+oWDUvuSo0ldL8nqzLHHF8ZWo51wy5fPFh/gCbikqdhNqEOz+q0zjRqujbTUVoo2zgpBu
fZdR/eNYvw5ZLSUermVZY4myZxExq6hJh1rTTD+v8qT3vGXvwSiBgHbzEodsJNmfbptg1iMHSMf4
5AVJsOVrAlzpV9ZzmB4d64+JXONVZSg+Mc6jkSQRreA9NE9fraY29GpEvB9vIJoMXt7M5kPdkYIC
g3kMJA8Qd4vk9h98brUi3YS8mKx5ppPHxBCp6MatCsGORfc6tNYCHs7pOHq/ONSWkXEuDf6pLBd2
jgo//BwPE2WNOA7lrRQSKDJzOe2Iz7bfi5I4t4sOAluvG3zf7NRKvATgEFJGds4W1xJux7RQV+j5
kiLdcaKvSv1euLeJU7kpYaXDgMXVOLLRb9G8pHU/W6W2tnxMq8liGloYiHoHT18Fuy4AVM/nPh7g
+Z7dKIzBlU/w5SF+nzonQdFoQ6PFPuCm05sp9gxWNBQe4voN3YJPkSiAwKGxgJ8F2dWQWx6Io+b+
G8Q8hw7TIqDDwQYDFfYMTrbMuIc4V+zZFgmhRz9Wr+U+K536IDEcgd3dIQekZqxaG93XZdlK7Ubm
wlYMFlaLtk4YZ26f3Uw9Sn/o8tNQCOz1DC1fIA1ei7WgdjluHUTNUdKAXF3VXLQlZBcESr8EIeXq
7MzmtRoC8bqlAcXD5/px7KHtk+F+aU0DlM7yJUxKMKMXJBu7gooEIiLUx9tvU5NEP8dDPV9y13qA
Uz4LhTBFu6psVylxPp6B0ZdYEl8XJiBjInjIN+NGRl5rdkSGss7daIp2gybxPtRJorNvsGcMrtWx
Y2+T4Wymb9qlOAJR4DcWIIP0XqJCyAr+rNxxo+gZSfDlf/d7SfggUEAPA9ErxIRdnm4tRBBOdokr
3YyY5dGZeI3BPKflcu2PQ7BmfUOAY1tvB+2EDGCtnFsYi08Jm/2ZDlkjPlNxVml7MCtzPgn4qs7W
3mAuklTGH0AFQV+sD0f7pSAzX64xLlNk0tJRAwesIN4qzdK7SZIuPcSDBc3JUrPQ0myuXeGwoUC0
jjK2Sw2TR9bz/LaJMuvzeOtePSaLA69mw0bYI8UmqKe5ccbAiHt6dHhHog44yNv+BdP8HLpA98VA
BYzlDdYSL0LUlKXIij46M3uVTRdjCjXQZbOE+FFsIMl3Y5lLOvJdY1yBrQvKH3vlggMRtV0kor1A
nxZM9JzIYYp1y356Y6dFQMTnxbd643HeiIbbryF2DV61BQCimLAvxm8gDPSpInBy9um/CvCAONwe
fJetvjoTXBqedbkhw8g7PvmeZTttuQtFGI0CSmRZOcEkCNJcrtFSblgv7DG3zSUE9BO9vglORrcK
vNa6Zh86ssFR+tpT6p3J4C1t3uT/m9/CzGSdk8sZLcWH23KFRx/FHzmM0ZhHrWy4xPu3IOn0bbvG
b5uIPFMidWrto3kmtc4QvJsCvL9NYDRE/Pe2ss2W66H7VLSKqH8EtUWt9pUDNC09MPHkLxwdSODF
zjgwJpeaT1sZ6VTY1Tcb9YXq4xCl8MINYYyLgfJbhQln3z1Np12cAsFKvB+9mremDgzhbB2EkFxE
okW5fT/lFGwlVTY2E/es9WOw8wYrg7I5xFF8rQ1UicizFHZTrhSWYsRN6lKy8nhaw2emO2BOxnDz
olnwmFv5rb1gVHrDRRudJLO+IL0u4thKQSct2uDlupFz0JlGUsPPP3fZkiGAfMfeJy7J1G4jFpzY
BhAq0o211wlBF3cx9tM52o1XEkq8WjoMlbytpNAqjShJkfCKkAz6G3w4GVb49MPxWvIUgJM+Tar2
8yfCwXuCnin/ttlO+ydXnBrEv1EHka/Gl8ef3RPexlSFHmblncbdMirNikab+1S0Neb9fOOAqmUC
ec0U7VcwfL53PjH8UP2Eig2SgiLvUTno+i+MFg5SyjPUeuA8Qitze5k6PHJkXz5Pxu5hvStnrHwF
MjUpTpcOtkPT/0f/24H0Z1HF6sAppaykgRG6ZsbRXQ2041MAz4DFpp7axClWQe0SoCr7l6SgpOkk
t6vsHmO0lZAGTCMC8rNxo2eYwhT+9pbTRckdv9n/wsWtd5wSK4XrL/1McYSIZiWhLESACchVMmz4
dt1CBaYxkY6ISscLfGJUyJ6YFJee43nikI3MkEjhfDSiSiCtsvvp5t2Jyk22KVcP6bIGOXORtbYr
3NSLeHSZhZIogfUoaHEF4IfaWwLNFIUxzwUWyeQzZjSyCY921ssOKv5507Lod9CgiRVX5QCvwnOI
+Dg9GBzcQAWwRaWncBtAWtiztVWj2QjTADDrWhxUf+4kcpDfXWgTii0NKu+bX9TD9gPAwRH8W939
YS/McWr8rrpm5aJxx6J1tONIQ4NUAeOpGWZCi+lyvT7Pt9iV97Bs79mDEfn646KURgMukaADTxz3
nxpvpYt9WtFrXRgff6jL/sNEDSCgTBJzcqcuJCK152kdSZk86PozDboTZGheOfxR7jr3znxGVPNp
YzE4uubi1ENOYQOLVCx+TJjtUh3hA+T8iDJSvlmE8Nlqn7H7IrGnidyyriwVETRRTJKwtcGBZ8zu
3ywaDVk/EroSbExUk3JJyNcyO9ZQdw6GJUlycn8ynIjfN5TiOCrGMjpUPhlXlaBBUHU4MHwHFjlk
0AYsVc9VXDl0nkGnIDdD741rs/0w0Slbngey4F4coj44NvQay3qydaipA+SW8vL/b0AmItcjGGge
m42N3OUldtvQAXEy7KVKKbmN0QoJSK6S3qDd7U2YZtINxL/GHuWDQ9z8+f3evgaNU85iUb2FYVLq
1YA8XhEUepC8k8UKQVhbqandv2aMUloTbhsc+L9mZjStK4VQtaQ+ALdy3uHaSmlXyd4lh07mC8L8
I2SWPicAaUARfq6d4xSj4HE8HjyI5Kya/H+dUjkmzpHqzYHBjZXuKOnXtV6lSIuGk6vtwFvrCZF/
IjZkhwIcjUlgLzmyKxsvoqcRMctkBvcWNs6zm1hmSUPFytGo86Re1g483QwGCwfaCC8rHUgjKCfS
FCs/IkDqHXRBu8SVrbyvOUp/ye3NIKRjcFsV6B+gm/Tq2OtSsfGoXxJmJisMjwqNniIeEe6uss7S
nG3ulwK1n20FeoTqhs15wcElIlF1oIk/3eVJcL5aWJaZpQeh0Ld1BVr3a9FXz1sNmba0FWdDiyth
RRtqwSz3kMPgv1OAuRmkmpZpmIgHbbt5POI4+7L1kCNkTcBFdxwWny8KBLssZA7nuwD+XGIa4Vxc
AlawJS0kE/K5jIBoT551iF/HP5TQdXO28ErEWVTWFAUOfo9BfROl1CZ2SDW0G4aGqodrkh8te5fo
zNKjJNlCgR7OUwccQfaj1AbjxmLgtLQyok48nXQY6cPkiuZB9OvnW38bG6NSayVzJEeQhQO36pe9
kJm+Mwjz3fBjpudbffbJPdeBeh60WixOW6uawcfwSOm8tbP5gbgRmr6m/J8EuGyps+SxArdLBGuV
2BiMpwYRlrBBbwICM+i3GmCvxynj2usU1EQjA0uwfxEdeALtFsEkct4xkCxBBP1fX25UephbI3LZ
cP1IUGWEIbjWcEvFcJEBp59ddTuHWQbhbjJ4bth9fYuLrH81HN1RUjTZzoscBH6Y3hqbOsNG956b
r098iY0+vkftkKxeY/Cwg60ORC7uYupCy5meUMM1XKvbEOZB8gjgQmKCHndXF2HU/Xrom3dNeKaY
v/cpCRQi9AKegqscxwxsPKNg9OBugwmbjD90XVB61V9o+H96J3Cao7+AVG82egOh5i3TmRuxP/QK
UjDaF5LyP0Hjv6+wp1qAKSghUa0pvIxZc+J7/i1QnMaWq5bYYjdUP/ZT//VHYqOHJW/1gH4AdaxL
hd0ojcGxGqx1e89UX3/VgAy0g9Bo0b8FdVlofjJT0r41C39eOAecL528AgakP87lQWTnUAbg9T8b
SGEAeI/npZgdP9q7ZpvFlAzdvA6UsnzmBTZ++GDE1Msm8MEyAORgpuJYrv1dhPdtufqGVKp492sY
arcmeC5Mx4TzN3WcuQINL/VNLjlxUlv8JiMBuafJSb7Vp5L8k6YNa37BFC8y7UVXNade4b7zbHAS
5aTGiercV3gRBV83suee8RZ3tyu1Zdtvdw/j4M3byfpKExWSPbPnidwmn7ms0hagOUZ8+AFMbJsc
LVxaqFz1PHHyRm2kcUK+wTL/ySWfiSmmI80IeMRK7Cku5F1MJrl/ZfL6uw3TBeh8HPLkrfdYx5m/
YHForQFzn8ulI4NDhDJJ34z5Wjiy7storWYQcRopPp0D2TrXvRww6+sC4X2IkkVLa2Qw5fIOLFvf
hCHd85S5yks0qwCyZODBahxq4mlzKX6le9W67nKzQQbBeXWD6wiItSpgdyMiGDJCiVvbhAlk0phU
yJb9sj40zc1GgLidG5lpQMgjGXUVBDEmPseSLhr7JhokPB0kTgYSjOP6W28oyaVaGqarYOAElb/T
E2QGUQRxYDNgbFAiOvcUYTzKFnTTyUaEZLvmzVoQObvA7OUsbvVaMCMH8XdU0IEd/8V1tBAmg8zS
TEmKQbEz7DBwa06mGfZ/s+mVIxTfcWhM6Ggnxo5GiYNHmDcqeBmYLWDVM/U+7m9GYZJjpYZ1jyRy
rBK0D8jC2ytwCGBHU/dgR9MTpUuDxZudw24HuZnSQNQiVW/wWN0FpX4RPCAxuO97gB6D4m63eHlr
CTVMeb8wWzMsReF0O9m+JWT13nVsNjsPCnuJVb2Ojdkv5plRyvAZLxcXczax2xF5Kh/Eanjr7bSF
COt2wz70XDfVDRf7M1s3vPdmA24hKbZUkMH/D6vAXnXZhpAVrGHoDxbpR/WV6MYgWjT6z0z8PeOh
tMhR7m3o7g82bzzHYjqvYUxiuCJOfs8xjvKzbs3sQghr3pnk+mhCQUrbDoUhMIRy5qRbdi49Rnbx
yhIQYs8qAINT7MGmbiQxGPxPp23gSwCcm+fk4ReKEtaNv6claWYyt/rr2D3gYiV3mVqI+LSPm93q
m/yNP85ndmKy405Tbr6aYQHYLUYn5c+W52gnL2XUMj8kH9F69yY7XCtlv6Csd3BBPq3Uy+1ut+Wc
apdmkNP6VkHkWVBE8kVejWiWtweItwNVpcu+jIqeFF2smirBbA4VSmDckSlQ17mcuhDgFunKkvFN
6NKHRpbKWPglRfJGc4ft1v979QykG2q4cQRZxeBcvzDYR4QM4LsxE08ZRMTp6EmHhVYFKoHUQtWW
cmur57hYu4WquBy468dIBxAwvw/Ookdtc4V/E94OKb7tJmiYRLGgsBIXNJ2r1DhAEogjEeAQLM2R
tCOVJfnJ1i9rIiiVUVRpfUnAvs8opKDGo38YavMMA702FmITfilH4vByLJ4Zox6ob2bMQJynVGI2
/GGRejRNU0XNPY+bXCfn7ij2K4NjjYEjAe42BPkYoWyiKOwWoUi9cAbxjr8idJVjZ95agRS+76pI
+ZyiEfcUjV3h3yRkDrn1veTt8AzyUIyl3Gqb7QK8XHao8CS90HH6hL0T98g7fKmlH/InNUybiJpw
BEpWjoEPBQ4WoYQiPFDqDbnERrdaiwiu01ojRMeY3UaEsEodQZAGk9ppHFoAJnGQbyIX3/wsFnU5
PpO/M1omFbdB/DWR+SjV1R93QAkZGgvlco95o26gSteWQ4BzSOqr0RxSCxSrEIfH55Jw2o3OPw7O
uIDu4mbOTUviIutktHlBAHjk3FKafaQjkQ+3/r3oQAvkLsY4EDxigOFlbr/5gvBOc7EqFCVhkltI
ZMlFi2v5ikhDoUFRXZfMHdm/3fFg6xFZFyKOSTo/yFJ6y/1KP8/MLjPzajejHSyqMIbNZdJpSh2O
uZBGxi3dXNDVvjJ/hyC/DWOgsovokCZPhM+V4mEG1x6XpiqnfsldlMkFX75VAwW7+Em40U1eku1c
UREDwXzWo7JHE5dQDXVEJNHNVNMD9dgrsZypRDwCLhqcKFzCsyt0pFh4Di5uqALeimOEKITogdQA
C3G34UsPUKsDPIkxGQHoasN+3W3GRad9xcr738E3wy+FTf8rb0XVM1iLK2YsB4estsWsmykk9cNn
oILQG3Z1+3xhrdc9OZF85s65uykbsLzf6epeadBAQqhqT5DJ4JPd/LbXEvHNUlbi9+w+xJhlB5R7
fxDXXL6wD/jaSAI1YavGMPVEjCD13GDp9TPT8y8RI12icLvkuGSeNAVNj+3ehDkEARQ4rp03evJj
9FBBPx/W2WwE8NZiv6jxaG7xUO6dvFzFrV3jlm1H2ZxCSB43h2C9rDwNUzatSsRatdiYSrLpy3Xb
UK5ybaXaBsQploGFA3i2i09i4BxZZcvm70ATizIHsAWzFTn1h3Jd6CuTX02GWHcpMMlRqapRKU8j
60nXEcHIP4Tt73w/pDxCSEpsKwRRq0MQwueo+1dstQg03J1RAMk3BTZeBO96QE2ZFWRkKXMif+CR
JYIDbDKFr3t5zrRVsqI1ZsgEwhO0YszjmsjPyL69QOClFySMuhl0XoqYt7IuwsJ5iFhW9Tl6kv6e
3f94l3/G1icTjX/AviqV53WcTy9Ve7zCIoF39i+P626vmHEehZ0hGrD6RFSdZFDhcJd3Mu5onRwJ
AL+P/UoijCquDz1w3n0YvtG7wX2uRjuRI4bYrrBja/ZzORXXEFObILPT4rrXd1usE1Ekpd234mfE
Cc4leTzfltcxZyy62IPrFXi1ebo0CCC9kuCrlkEMivgborHSC6gTGo+mFRybIMJ6dWgSy82JBmvy
pJ7SNBbrX4cM7Cr0NMxMFVbO1D4hAUwgKwkmZmdQhP/lJX9oc8Y+ctsEiT3hROeOItT8a0oPg8Jw
mmBIMtWddqNWXusIA5FCTZ0tldBgw17vovcel5F6wY8PrtC+AD/rAF5KKAQgrET6eL88n3WneLzf
BOBAcjEKGK79RwBzBvZubKIt/ft8pvApjY2SnG87yvd9mkvbJslyqE81eE3s6xzSorzFflxUtSL7
5bK9ctPUJoKBJ8SFmSrjNRwSKrDkxDkrYoBaNs3b+BLP/0j6MgRblIWo3aYcIdJu3pZJpi0s0OBC
a96rQgzlFiXt31SlCzMEDgWsJMrWO4P6/hnZr1XGxkMgvxGdToDkMhGiehaWFM6sOaHEGYYCiSw8
nwl01zlDGeTyaEvILVARww+dNqPcAqJBj/yaiUHy9Oey1PNrXGlp0SzSIxw/c7AiBtxQca3cLhQK
3pT2DfN0sVvI23BO2hd00ycYyOxBscqZK+Vv+pNR81nj26Xpf5aqYSkBJEqDjszngz24plP8aFsC
9EgW3Y2uSiA4T8X66chzhrLwYelAJxvpyQBLNGTby1msJBKZLW+Qq4jUivyvsBRgOz50iMMQ1ssx
Gu8/opJIxkyKXkvCjHWoFQof5fbVzXEazqZkH/YUm8uNMVP3NYiRB+fE+TjVaQOnuOpTNxmDuTOg
KJCMeFUFgawZ10U48uAysQbA1uqhPLiiJYfPk5VJa7wgdc0dq/p6SLXKb5pze57J/inldqErmHi3
jwHa8ZDSL0cus8eGvc164On3EPs5c2c9RwDChHKwUAlfHqhOdUvY2bmROaHd5Ye9vGCuXwHaKvJ8
WnnYfXVzbto/Fapx1jNz7VtClKDX4xOo3yUXr8ZjGxogEBMn+Dr3XXNjCVEoRET0VUReyLatf7Ig
N9oVFCAtAyMIyeebX8vePps8WN2dNFlUUOQAa2GPdf65+nD2q56oTtzDpnqea7m+/bCFjOnYjyWI
OJi3s/aWNjYYx8YwNxuL6i9UMRqBkyLYs9iLlp+fnUgHsMiOxvsznTiM9fMj1qB6EmN9kuZEjxsh
3ZxhJsmtSEx957uzYjvTJRL4LHbjWNAGBMfcvdlZn2jP1R5285kFRba8cyxjeu2ahFMZ52He1ZS1
Bhf8riyIO+qUXiHZzcsFpRbHTqyGgjP17VsLlS4lWiSY4Ebmv73s3Q1ofXsnrr3UkRVdHQDn0fEE
cgFdtIJBn5iHecAkGoi53IMj/2PXxQtCUnfd4Bsy5MMtkIr0M9ylWyqpqfvfoZCUdaLrntJIQDLI
0e5fiFn2zncS5kct49/EXCH7K88JMKH/JYgOsY8NRpDjpbiC+wLERBUqRJgmlG8gav4QxILqMjF2
GUMjshEveLrx91Q4WWLIu+takLTWxVfX0R9d9KJZjSt0cAcAqyEVBgeXNDdnMriIfd60wObGnjk4
F2XtwkU5TS6afCB/wK2iYUcVdq3v16jgBuS4PyBDP51I/clvD/Z2I7uNBagt3IdkNAYum+kxiaw8
EMSz0k5PF3qBxp/x+kgE/BhYlF+1af25FIjVe1Kvw8FEdDFX7gEj9JuGO1RKaD0FlTNGv/I8BAJn
Ctu/zvwEow3x/odqv6t12NNnOlhctQfvaRvnBJ71os+jK9DBXXU7QhZqx5tBPh694TsQPh8k0w+q
HhcHq+3gtU7wcSUg8gNQOe3KddLLeygu2+dvuzP/DSKjxOTxR07CetqYONUg4CQjjpJOBd7xiFDD
yeZ1atvXsaJDTC0RmRGEjf22r07VNpveCyOezrFLOpmsbSMy5QrdWlC+5bq+9sOi8TZSSinFBHXE
ed5vZZodPK+v+S1BNS4BHEBnaBJSUiDqjYrAmf/XlNHN79QFOOVy4ZOZfqr6WHu32pN/WxKwpVq8
aXoxvy1O+Y5NSdSlwztjD5VB+89uCXZL4X4ZsgdG2PFhZ/9FHIQoXzyzQBcKH/acMjlHYunptigb
nHWVS+gLeVuJ7/EfWjOtLGcQA4qzWnUAlDOXLfcNDlvs0Falr1zRLOW16vBGwLEk/35CAZ9bA8XK
3Rkk05n8RfxMUq2GU45cMN4pyC0kR5GDfWutQxnY/xPZyNphaRAroLcQ0UrSxrnPmeaTAqSn4Ohb
bXHjtY9+ClDKIw3Gj99NIzGqC6dHjz7wT856sQuaK7s6mdKyNJfb9ZConypalDlh4hciYKtRQaU7
tHs2HJE5vbobgv10kv7Sk63NWPOCGNx9D2IOccFtAk9xsWpjbI00XUNTndqTRVwhZPEviXVHoVb6
iexxWF6yUlMoFNvMueYYpog5WPY7OpT9ay7aJa+DDeQo/DgiTlhIy/0oiHEkhMc7SP3pj97w6RYs
4+Pw0ayoPkWLmv66LnkFGxIBDsodcGrVcslDrsxmB1rzrdXZ2cy7duoalHRAm+lRslb0+losbIWq
Rq/MYamn7Qn3/b8sZL7u/pxLCh1kJ2Sfax2WLsYE1m+YIb960EWPQPDb9lNQRVumTdaN9vrWLacd
Wg18JR3vdBUQkd59XjcNRu68UUgEHTQ76H7TRiE48NwT8Fz8JnR/SAlxy6+Xfk39Pj2qKxW1ZNOF
dDZb8WWa/t0+UH5+Zofc3433q7fL0lOFnAMAQQ7uk6M5AgtQYOavZlrWU7QDLyPfpjHoKDjl+X+n
JYFJk/D+vRnUxL4wNLRAn8o7lhjEXXbgtVTkdPca9zJ/yL6aRMDDBe2b5Jf8qXPGmNcQgBCeC6Tl
Nje4qvRD/lhdIP/OPYVuZmJ+z9zoFUobqkps0nJtBF7XccmMrEMpfDX4Hx/TxnKWTM9dJ10y7Kyg
DptFyhQT1Xy6feO+ddr2bgjpeZQlB5n0+XrR4xCszWlIPbCQh7F+FbzTyKcW2xhbV3+UsvEKJjX8
7b6NHhcoWdai5i9VlQUuUFhRfX6a1deFWAUgBxarTKSrqG2mGGcXMGDNLfIW8ftsp+OqqM4W6I61
VqtHNpy6qsXgrBXaNdZHsvHXtBOonicSnKjroDFW+bpRo4mCwXPksJN1uJ781aVHXZkkgunQ5TNC
OnoGoLOVcfoIof9ymmMHokCkODsxlUf7fvVCAIRu0LOv1oHrvNezS8qtJJZ8335/SRjCb8IKRunY
modrNMoKUpODTLQ7zBVmoL7L/2Bdom8O1VpJaplIy+5kmjtJykIdMsxSyJZ1n5lP243qbGX+Jpri
fmXzOkt9/M1GpJlm3rpU940q0HadLmUBv/TLWuewriCq3D+W3i0oZOx2CtX3/5N6+PkpSPfeB1/e
o784uZGwlGB+YdbiJAAW27Vwa+ZgbAfMPHHR/90BumsczPEow2J37h4mcCh9omMVVYKb4kUurTF7
gf3Pe1lzu+vI/BWGL9bEY1KKzBnl2Z+FlFVv7qZIl84xkTM3dSSYuh2uAzVhwOoFk3EAozG8F49X
NsrabMa1U0mMSzKbk44NT8QDrziv1rhhq7sRVknHztKmWkRLTlT9RVw1eFcQzVyIhF7A+rhU6k2j
NRGg/3dZcZc0MUdItOq1ycsJP6whNt8birvCBGSRKLymH4EyT/kWyXjCSgGuYlXBeWVZ/72nIU94
PfK4H3EBIFu4MrPbyByJUQ+LF5erBNG8Hw43854fzKzYk20lIKXyDf7BaEjLILjVU4d1yrqeaURm
p3A2e+Q9pNaLR0oSgDyP1gSSTpVYkWXiKXkZfkWr40hbyt/e6osbxNxou1B7LQ0PNWPhAkdPVcff
vZaT13XGKjdcUgTqWp55i87L409v7lLw+gADaiT9RRyu+XGlPNbQQN0hKPycVbrjxvR28wUqmLZ5
jRnmL6jJBuFU85PEDrZE6ANXw6ZChHabhprHbFK4YxU4mIU8fxqwcpiJrvjvmyriOt8alefdHE/9
v7QiDe81jpleuFCwyuXTHedLZRwCmHzzkeUWBeRbVm78BzSWawAJSuylznTUeQMKFAkgAMyLBhFQ
yP+MiVhi+b04a3rBCedJyTg5cbM6tWiOcZB8Mp1TJ6eKiCLiBvAX8Sahl0+Qvo1TQmGBJqMgGDMC
cLXUeI32U0fL/ON4AwAlLYPCwgEv+bQiMgOlcJs8+MOBJYkdIh7pBi9ZCLgFhtGUIJDyfAr0PzlW
pJIi3wSpxY9E22IsSoe4Pueq+mFNObaPuRlEUSFRD001f4AZicltW1yHIfc0TA6oiBKbjALtoP0v
+H5S+YLrifz43yH4/q3jb3u/jaVSl8piCGnwtkkA/lftj51btfG/OrWfW5aO2n7mmaswyoe8KIR0
T71sCe6lZt/vu77N0COoEpJXs4pIH/kgi5Do50eBWfO4i5aLFcddlmzBxjyO76yUDVvCAdJwPpEN
zHy94P6F0xnOaM55eNhM31WznG/CbTXfzaMDWTb4PZg6AxvB5/MlDro2FggmoV3bEEfHOlm0AZcf
pwiIDc/FhMZUq8VQyha8F7YN4Z7+qrcnpr5I3zWb90q6cAntlVXgflUxZMAnzmTC0oW4o0GDMqzB
FDk6toKSFUDJsvCC4PouBbHugJEnn0E23kxBP46854KX35y7VVXtrXD7N4omwrSCcxSufZV+W2F6
pl4geX04978B1L37S7lfNKet3Q3ed+9QmqST6b4JvERxiJk6dPOasfvfUVV8sM31nuyGfNBzbPi5
D3PID7yPhUNCnrPPwRaKpV6e6CDmkZEiXqCTojVQcC/7jx1pa8Awvmt3NVVsdfa7eNHd5lj1lL9V
r0GfHsDiiw68aYt54uWpK/mUFpHiAtd3eLkjSpycKxmaVYLkLN3ba8HVVu0qpeWd4DxS7w/+46pf
URZaOsDDXI4ZNCoq4U6Kf9zA+wDpHZOzQwbx5kEk+AubcSDr0Ii7OcZHWh8dRztNZhoPwxByl77z
CT7CeYjzPfCBMO4RLQvjC9fxNaoQn/KnrpxeQ+BJvfImcAr6cVYlkSWgsu8Q/aSfXTGcNQGsZ1bD
UIn22+nsXk9j8ZGm12Z5G3YYCVpTovppWCZ848K1jRHaUtyYnqL5efwHwqTt3RP7jFdTKLW0vnVm
Jq4WmpPWc9jVPqjIPi4PZyce7kFoJKO+SrckG5w6VumbiLd+XE+TJpRcDS7p+SSbNbGTaIfjvmQo
DXRt8/4+JH22kHmvT69e4buhe0986K7dlGiVOpIb+9pqXqlOzhVbJCwUhiQVu208opLy5+EGh3nc
sx77LY3bbK7zuX4eo6X4S3+yijRAjIxH1EuFIBOwP4xhppCF2ZJvwkJ4Oi9/+HxsvjsaczgP936/
cBuQ7qB9SBzAGHGga77lFIHX0BGXpulfI4kL3SmDw0EWB+D4jSGiXukEDspzsnYHPY6vrz7jTb2s
SFBq9306t5JFuB6i7aNpfhLPJjBtFNk8K6/5hdfBkDwMMXy/js6WUtP06Nk8zmrT+bKXwbK9R1V4
umbNnWqQd4GMNUc08R+WOYLwYgoimGnjj08yP3kijFvX7/mUBgEgIToNwjFQsgCWzs0NDw+Tm20G
cn9RG9ZxSRiNYmYhn638hLgsP+uh25oPpgNE+E/76jMOmtYQBC4pdb3N12/9vzzfKoED5Cs8SLs9
OSq154Cb0MZP9pxA4VuCzd66a3oiZwTebJZzgHx3pCV4NohrG+avJPtqzUjTeci48cuRUBjeR3xT
wbCrUgG4rjtgPvJwBGBPrGYisfXczivMwi/3PU9oYVPShjxclyq0OiOFuicmv/LvfgIM2dLeD4d3
2pij+N8fUto7rq6SWZ2H/poM5DIuchBxwqE3aV/2bwE1fx4ndiXxy2SlWsnNIQPKw8TeRJnNxJ8V
D4mbLNYE1CH+Jm24fUnzrM3+7sOV+pND2E4O9AQg7p/UDz5nTudaXovyGNYasUJsz9+TrrNP1Fdx
paH5Vh4hoJotVqYYUNPHRLS2JEyMHvgx2RwKjcIGWdWIq0otSwQQ5rbOVR1twkBhxceSzzybKgUr
p9YWhWXjGrc/umqIEMkIyTuTdiYWt/F0WnTlI5Dcfd0WwE8DTksQMrdI/j4PAUn1TVfgVz0KdQA8
TMR22XQZ5q64nQORriqjNh2vA+y2db2wD3E5klN4o4Qk6HrP6l6nq7e7twraCVEYr6v4VWOOJwwI
tF15D9Se8Hk1cTwmodLOgZb89S2juD5keDXnzG2V6/T5Og7oXsZioxwwA9u7Ex982IB1Qe41ijyN
GlzYv/V+qBfdo6rUlnLBPFDGrTq4lQwsXPJEstjD83gfZG97toLqs3X5xuH4093KKJu97DVGm3TM
vX5S5uKeb0h0Zp934dElllYVUs5CvF7ZXzWktb4ZSY+RMNSHXPOkUuoSbPgj508J6Sc5d0JSGxmx
UEGP791Esyt+L/RqpOnwWmg31fEn2zWJ7NNtZHjYQCqXoqx8JNrsN1XknRfFOCeC5IoIhP4tbuBy
RFbULvHaJWZzFvLVJFFRuyzjhCWhByVakFz9uOI8A1LyMTQvNPtaRg3nmxljanyAcXoiKDFssVBT
xwfsw8Z3ZPYo0YkV4WplAYwhE0rgaAbizoDVqWFFF3lT8rfV0iMAUBK65Ry7+DMQMCqA9hUssvjA
AlPwaFEnJ6ot3KWKyYvyiWi+dkfJqIumAnPdF6UUAUtISEdX6OSHdfmSU+32k4DV3BDn5HP6AIhy
jxLFis9KOBqlBJVRiowHxaeoaZ6ugzsRtevisu4uFsU43ayo8IGqFI4QsZ+IIZoikGvm1B/qgLW9
kC3eA07Mw2JJIlZayJduy7JMPMfPecZSFUqbYaYJ2IOMGhUD/OnwxcbPeaewtO8i9uLqWZsC4Z+Z
aOW37wbEMAGZFKMN8kKXrqTg+lFMd3yCMqKENXZ1agXsO93PZcAdP1M6MOwgmmhpexGBn6wSOwir
4HBFaGO/17+XJmtdTbC0xqeBPTnaep633ZpDDyNc0EkWJSIrm/uZk61jOWjeRGAp2lMCuCG+gH/c
s1qxWvdv7BCa9xyk522f5nPYjWb6QuRtJlWrG9vJKB/lfbz1n9N2gU24XrieIa3KeEYaOcimJQky
unmkSX7wimk15QJysLEukRYV5PwQbh/kxLqCBvom/CT56OEcluiGyv7A7blT/kttq/apRsnjrkZX
rWoBRtyuIrGo6t+X7X3oY9sGoxPaGZj4k59fdIwgCgxUI9mhp++brNNswG1uaPjXsplN0yDoDQhu
tUkV4+1iQeBQhPwG4e59iRF4ViOoXh3kOw6fs0dSktM2Vr+M9uMh4ZTSV7/mN1Au1drCU/5jpOXK
dxDGLNFI0YjHRqIXTsT0nbmAsn9xzvPVfs64SGsmKW/SCqefO9q9NyQMawm94fvjtueYNr7NCFHl
d37QzfA7HcIpK/SBI9BtwQuKTxgjbCbT0/bt0uBhRK9AMUb/OxR2ovM1UOPaYWrdqVPzzW+LD0BT
sTxaqK/UfkN2O/DgGXitnHqwVArXjIEWpMsjTbFFyEonzqmrrDdXBnxGVc83GL2vJSEM40GvqcxK
hN5NO2aFbu7Tiv5DwEbQQxpMBcGI56/UrAQQh6I2RMWeEBoofWMP4+51ojuo+vmDQZHTvXM0rQCG
igNrDIRJD7+oJtqP3JZjZ/yIDVY2EFPlZ8S2MJXwl3jKW4uyKG0pgy11J9JiOWKX6XikNpEO302A
f90DyhEW5EcLlP8D6L5CRMyvDj6HGDFEQxsr5QCJXpSMCZOYUn338KPVENhaLux3mzybxeEtpvCZ
s/7LQKogXd8jaZIz7+Pg77L9K9sDUw5QAu79/zIR5IQV1V31Gh26RMcfZ0xbXDRSwi/80EbBK1jW
rX5QzqYHR0zlqL24RCMaH6E/fXllmgo4lB1235tOyNg/akQdRyTYb7P0AslJGYb2YX1imFNKEzLp
Ek9ehcZskpBduXyXOb7IJ62osZGZDZimoDRj54+Xbc9SupEOFq/LZriEsKZ9aU4PQIglkOYhg+08
jiXXyiicCzFzZgAfxFmJVW5LirsdPFIBzMZyrwL7N3oqM4OC0bASchbO6vmflIUIR6zOeOztC7Tq
RHafvPuplT5TUQPmfgxWbm8q1sNf7JGtiXDrytyU+wBth/YdFEFHL79ie7NhXUySWcYiyU9/Vo58
97zAINZtU0lCyZGvVar0a2uiAkmuZda/jfpWTGEHopdEC1LrH1AI5Ydo46RWH+Zz16OZVTdx6QT/
r/GsnacD+89dyUAW/AnmXaQBmnrR4dP8GPfjB9+7ZMyCMeP/9ANQLLi412P3gogQ10OUYbxZLsiJ
HgjNNQryXNNKOoS2ePzWYuvmtxgp1bt/AjS57Ksufqm1kHmI78T1XeVLhKRBauFQjxrThMDnVeeX
k80rXNSzQBAiEoiyE20elyTB/uxj0p4OMHj38YVsRautM+Eld+MmWA3Jg1l7laIJFsdauL+/4uej
vjC7cOyc57VfFChf9wSz9oXPY6YleUwdLwsezouD5WDLeJ8LatQTy6kT0FxPYinjcd4t1MeVdhmg
mKgZWPSywIpwsumrjtY/lp4um83jZA54zJlE5j1Su1LIP1LJmRza/Ba2kLqx+IAjX6qtIcAYxw1Z
FcTmjIEoQ4tSNXgVdAuPX1QqJB4cHGwf8TqwjzYWqZB0zNNqrV2P+Ku03viyaGdEJxbemwQ+2lbf
9atGbCA7I4kVz22gkPqee3G4+7wX6jL7AMHOvXT4hi8rkbGPMjd6c9PWLK9rNdsvF5NsSBfp73Sk
n+zPF6O5cub5+ev+mqGuGQ+tt1h81yrmiIq3maR8AhdGO3SEK+oyVfqkWNgOhc9GOuTbU6DDBEk6
wxJDxVZOqO2rbWc+1JVGy8Q9NDhRhLX0Gpjm4GtKtIE14zxGaF4cW8e4pLohtqP6NevXFyoPU9ex
2OKKdfVMBUG0U6i5RFup1PHd+g6VuhOePWAt84yfacO1NcH/NpM+LPw+VUrQGdewHdJqud7oLseP
y5KgCam4MAI65dTYG8r9kfte7KqhImVtDY8XgytMZIf1Huu49y9LvqS3M3O6is/dhLbF7nF6J8yU
IC+kDWX7kE+PUyjTTGyR+ZwLRx4/MDNRKAuU/4ZqtuWwQuopNitIdSQIyzna4iiLsNnVkkH3J8A/
PGtIyhjYeB7ps221SK2+ZzxcATu80ovUbrACLn5bJCZddP6HxVkhCoOeQt0bvES56GFzHJ8FM9LV
pZSnc8XEAdtzb0MyFk4shXzMbTGDyuoXfj3KrcIPcUbiR7GhSSpPTT09Imiu5l/BMyMCBvgPwLi1
giWV5RSMQFEkkBtFxOeneFSnV9760DVV1V2d45+AyJCyzFf1HnkKghuZzTgkg3fRwYzoaX5R3JkC
h0ASCMCgWAIVni2hfMf2ikyMmbYOm/ra85J8R7JPy8PCv9rH9xfoOYpK9I6ERwUzts58cDe3JXtK
qTcD7aWi92c/KYcabzsBgZf3wRi2VdxcQk41F4mrVjYbV+TpeglyPUD9FR6iudyezHf0x8zo+fX8
XsQuWnvcMeRw3GS21eMZ+RNEQ9aTBY3uzfJokrnrMtYdpzHOHcve9oUSAsepBIC+UYQdWUH0CPmP
ML7lyJD4fNWbGpvPBV7SNeypiuHwpUQiwYSe6Re2pHw9NDfbzEeS5fFfc5hu+cvq/Snd3abFJSsw
FQqbUUN1FbGa2YoL8w7iB4JQpBVSdJL8RGJxJIV2qcM6AJ45WwjR5VwRMU7V0phchLXd0K0O0jGT
nA8M81FSuxT5rLd3vbNHAR26G5GuIiZmY1eod7iIwegMPYjYAcLkubU/vsP5mrMrslI+e2MAtpGw
5eXmboDq5ffj85kIcQVvtZ9zNYeJ9vaGBoygXStkw7PgVgYg31DJ28F/0lzQ3b2uRlXIzDwg22Cx
b7MEZDDvRqAWFc7TQ1Uu+vVaLeUin3UcJNFJdTQ8J1Xy1xCu71A4Mu64o62MJjPgf9kbduWOt82H
3vgLtPk75TBmSDbnKKU/GdmytWfxA8hIq1uU/PTV6OU4yvseH/jnVGdYEuE/hfSr/dbq2Wy37+Ak
yK2wDIscD7uCBD8CUsLEIR0kgBjCNUEJRaGkbCWhzsBwSlb/dY5sWMz3CEvlyH8wJ82CT9v5bhmL
0+mFvjDEIzVlWsXSwt0Qch99AOo9tPa8dH+jvwuHv3feczXi0Zp71u2omH/NOd0CUy0gJAxk9eff
4WqVBmhoVDeywdhT4YmvN6f5JWVR7H2zonWSmr1rxM2x8dDd5oqCMeDURiJb8wB6PIo2oAJx9SIs
dn7rL5vnd0qynzLZVLhyn1J9221EJvHRdasuwwwajo634ffnt646JHn2x7vmqX4/gyj3uoKmYq7T
XMhUJUyFtHl9ydp+nx2ITOJCtK2Zcx7ZVKiwxfAtomZs2IEJRYjcMdA2f/RO1DT+eWddOaCB6d5p
9uAyJEHely8LIniTqUVVWszSMeGkrOz4ZgPjQrbG9vviH42xfINb16z0E2xJ8T9yIbM7iEpV4okL
yiys210vx39GDAu4UtYWEp/h7Rydwyk7R/3GYhWs39uuMFuC9yI+rCBw5okPelWXiHM3/EZWaE/1
1HG2OpCTrHJh/QBRIlJMHItcV4Lo/CzpeDHG4KnVthdWyayKb67pZ1lIqASHBffqdRw9LfsxOPXn
iICW21iK/SkDnmBgQCmvyda6rEekFkLidT2i34kH8MVGS1P9QIYY1M0wS1ig54z752VTuEr4Bxcb
LmseG5Be/Dv/EtDOKngVxmLfHqflGzKwazBEroIqgPFefdTHDg5EuPznCPzn9BTqnb+7i6WLJD2t
c2J2MHgfzPxglwx9B00EcrcsmW2Zm27LTJhfkVwqK0eUqqfGifKWuKX6vC0fsSD1V/vuurifEA86
p7vIYR7TqQruufeHQjsoCxd9FdkE95fkx6IRzuDD18ULkHQugEPLWl0Rkw+oVHsePx57LWFQOrbP
oTBCt4T3QMUUx/QPP9AE8q0gWmYzJgDzaLeRXfdh0rFrAWi/K+60cXhGTc6JbHJ4saTncQ4PbU23
J3AM6kZZ3d2DYeouYHUgTwyGr4gYi3cQhhiCp6r8oHB5ZgvXExWRqOGR2gGH4YV6EiY+I8314X99
hXpPaWNzQNoGnUBVGeIsCX6VFujG28etGTDhvZwfLW4t6FgRIlUomyMqJBGzri1eYFH4tRMIqBX3
pDSINvfJRRerJW5pgn3wNY2uilosggothsq/oTl0CH9ZaHdJCRvHbq9EUqNfK0nwhFDtWV3fAIHV
r5AVRuCrEJlLE7TrKK2XaEwLxQ5Qd+T9yvGPWkGjVfRaPsg55BhH0iez9+lL6oQlW3kq5+6+ha5o
RWqDWs6+m7EMbAOtenJ6GgTXktJiRNt8RTwrocP1RsqxeoSOGc4pjB2KXen0btG85ZGI0rEL0d5t
f/7JLCVPmBT3p6C2GRPDGzRDklW664CcvWzmgXP8alAT5/yCRHshjRXCRxelhiAVgYzqq/CY5rHa
AsdiqJSVI1EGwr79NxX44NstalS0bb8LsCoYBxDRh8v5QbbgUKSqXXrR2Fx/ltTwR6+kBBopGmZC
gjKplt/xEKdhtOBYrm1yWh03rM3y9uAO/CvRnP+cSc9Uh3wbK2JbLnygzkwwZU04e+zd/lMO4Cuq
FUx67ye2t5800VVpBtHU6DYx3mXrb5N0aXGEt8jtQdW1/9ylbvGKewfUNttTRqZz09eR/ZM7TS50
ESOLKXg+msNF51GY4wCZnUW783WFNktnv38clpfEZPeMp2EIuNu1RuhaAvCfJy/z4zKPDt8QENWl
Zkddk/4Ll7bm7ExPuviRRWrcssiqh5CQaAywotQDk1qhJjzKxUfaXZd8IiKpgVuTDtU/QoNlgkDQ
wOCDhRNulMZ4sAJF92GIqe7Kt6tC+yMkoCUbwv4JHZJ4nUKPXaFrmQYb89ApJS1OoVz3sTh9XEKW
JNIkPEz1qzeLBlSacs4zYtgML4ABUB3dIlz130dWGxFGaAllqcDpf8ub3L0Lj4LoL0u9TqRP214n
IvmFGdsClhZ8QlOF55q8E+PvZ7NaeWcHBLaGVqBt8KgRrHAg4Wh7eBq63V0PvCw2idasFs/eHmQO
+tFc/ia+psGjhMr1NL9/dRwK0dp2anuHW7D+gX+w1K6mJYGpVamvw7iF2nBE0kZ7N4a+7xu+/Wav
jENN9xBMMZzhdfP2ab7wUmA7aLAvgVdBZ8LD8sW/dPQv/Y7SxO0ygGZd/A1MYIG9nqa9ICGH6YVz
me13caG5yGLS4aOeFZsLK5jsJ8v4GUfrZ3kiI9ArbgdmJLN7eA36vt6gcyA02ykY61pHcePFz0t6
RHh4HHVUbhuDEjfEKHnU1IdF6rumS80xmgQktxayVotbm6eHceyHP0KXTLSPKkJYCmOsjYoep45R
QQrZUHXKMwKCp1lPffJ7Ue0O4bM6JhZGbFwNx31W886b4KpqBlor6gV0nPgjvie87NpBtWjIih47
49+rSYykNipEX6evtILL8sFwQjykDa5H+64VM8ZemxN8R/LfNNd/mTH1U85D2Fs4Q8KCG5qP33ls
BdB3hg6gwlb9B61SDzygJGD264iYCXCjHiJqliGIHc7VYO9vTAIPBdfrm1CXwnGcfRm+EXj288ik
Z4L3pak9g1VwGpOOnZRd28p0TWdp5DqHKBZKj+1/wcWl1gfhCe8KkmoLKqJwjSWtH3qdsyvXkBHV
HlYKYSi+hTu/fgioclNnZtOBUdUzf0IhmGJgPvq+GvxppygIcsjXWiFafto63kVME92z78sZf7CD
SOXy31RRsTlZnO+ECIBqv3YS7jGjd92AJkW+v3NZq5vXN1IBP5jhqRWd0M2zSE4GISrqn9+NEI+R
0KJ376MFQUghfDk8XgqXfFvDdl9gHDjfchwAzIcNOAbT2DgFJ1hHxiUrU0lR+yC158U2wMO8ywPF
nUXeyt2kZlQnesCMgM8t3fI1ONT/Gt8J3k/QFDL3PaqWeMluWxx2HOnui5P/MTaSmMzBiAdDdZrb
CNNVFAPHoAimjfONkgC8MfuQyV+WmAqhraM+tgVH9H2kbnl7UW7cTNC21x7fyG+PEypDQZRCkNnb
AGl9vgm+lUgpm/I6m3cs/q6gcqsEd9W/Ba8A2xcU3HH1H7uTejM2q7qEoxHzbdhGGRiVYpKcIOJd
MPQtm1/3nyl4CIewdaRa423NkDJDD9tuUDhprUzOf2JBh+ZTodT3qMgouPx/9sdBNC4qpuhoCxAN
RSJ20uyhp3YbalSDA8agO7pBVjwuQkqYBcTTHpNQps2ZD270R+D6gV8nIETKnXFoJevbpe6rEUwM
JJAs0g8l0PeVODRn/x6l9d1ZZivW9uQ5SHExD/kwCAI1kusNpktdXcrkN5NdpNQiaLHam8cWXZEz
Lk/ilJNQYQoIBzTjlZEmcukyiCdUoayk5BxGYJsxoA1JdFihVtCQylgGgJghwXWfZGA0V5G4XWzU
WuGKLty6Yn+BbQPuD6Q5Q/elIB9LUIXacz9sNMrEksI1saDjmYYHxi42uPEByh9ICalj8J1QqSS9
p2sLiPU58cspetdzR0resNMymdqgm5q2+KSbb52hKEYVcI3YAjLk3FUDJOvE8G6m3yn6TrdwOYR7
/MyraRbX3R9MTOP6rwxVEXi9DQFkWKNzeCLvQmJsvdi8AIeAHXPHrQxDvfqEuMPW7Oh2m+5FNxyD
/aiPgK/4ncieMO+x35hEcqZqglFT4dS9eT2B6HN1Dw9KARhhffhMyEusYaZn/zwruwfWmQVRX0Nf
IytBB0cEWF1UUwyMbYuMcsKvyf+Ri9O7mIUClJnOxZFEXfvHwkZ64fjy2KZwlG2wpVkBpkFugR8+
kB+WRwmuPeKcPJABQdynWLYsvualDDzk/AykdLesHxe5Q7XpECtv7JScYnLYM7oHGjTgnhCiUge8
RYwAzrn4yQCF5yx9gT03ir57lS7h+J3qt+aSllTEhp48UoTafQ1yyJOPUnlMls3dxUnjBSTozG09
l8hgcOZ39+xS/wc2GvFKx+nzJkcCPcxHwn3OQpH3GKFKhQ4CAuZPxNQUSiRUENov0FUh5gphwTfM
SB7r6JCXLnHIbjZ7rh6zy3CEMiVj3H6Wv7QaVAQfQVUacbma+4kD+Yj4p4J9ccwi9pul6CN1Tkz+
mya0KqJzZ46MViQTeqpvQCpd3E0hfg6awSVkFw2s0mFjsRAw0A7asIK8+7mUVns9oRlBqhcHo0sZ
BSyIHxRhDw7IxLE40n5qxiL/9KW1P40Z+Glu2794peo7O0Vvit59Rwd0kaS1CDBD/YabNYcIaZnu
GL95BLaWBdghhZz/cLSJnjLz4n7Y2ZJPgy/+/qXDIavaD+F6MckPJZhrO92Vz74Q04N5HQeDUfRh
hMSsS6sIw4vClGZgDSTdkVGGfh5Hk7eWpqTFj2P0beSi047su3U21/02jyY7q1Bo+PGBX16Lefmh
XTHb7xz9ygUUxvllxJn0tRGf9cqBFXCFkbkGrnAVuU0aeqzYyTBKk1Sg+aNTfTYG/rAR4wWh3cgF
kIQ/HxZneQPzdneNBlpv2MylFHvYY9S9FGu5JVHRxs848kV0Gb1HZv7Ofq8C/miwM3j3CeP9S35N
/TViOA2AR9Dn+5JALGQoKyZQDtpDFSfkOnottm+gIJpgUIltUid0/L8Xd+B9LSucCP4adaRwbOvp
E+SnhlnPXwoZcJSAIw5hmXwR8TrLwltyhMpXPboDLjr9mHkaTJVLtssNt+YDOHJCNgFdTWtNWD5X
UvXiJ17rNHYpSYGfICaCKnhDbJSsq7qhzOeoseueFhkh/h9PorhRQZqZiaxvOuQFalYRQ8Nl2kGN
k5exXrJESeTjhsWoENqHQgCYnZgBE9iOxDNWpLyoVr7WB+y7kBGOS95bAU6PoaMpXfVhOyjDR4pM
6Qv9bK+QUxV6+mDPmqn4H0jD7oV4imrkbZ8A0aj+dINWvmX2JJhNV5TMV3rnGrRorUcRkP7jV4Oe
RBLNV+BdwaC6WV1chqYu92dgOJmn0TSzy+0Jeg22xwdtWKH+XIkjin5w3uiXioNrbgzCWNCAkCRO
KoUJdKK+ETZt9sc0X8QO0U0wyt57N2KDE7Oh/mBjSzwRt4x3/pYDNPIZXHE7uDjZWUDzJWKunnFT
5t7R3hJC8malgBGj183S52NJbK/poacZwZREnxKOXBigEegi+yzr+b14ScaFkojWyVISpnt972Fr
ac6Me1sZH7Tt7mfK32FVwCaLrc3mJ+oyNDAUUfMkkSgSDj8kNbJRbL9G1tGbYg0cVRPoonWJAdFz
g7A8rUrywqAIVMykJW6J45IcCS0HW0PJzRenOvCPbwMowOS9HmgO0PCTOQokat5AZL0DBX1eCvLb
tjjDU0mWHELSEO2NO9r0nIu3wH2slXdWEmZC+rBcSqy7i5OKZNUyYi+oPYBbAEK5hl2azA52nyVP
hv6XAvC7W6Tlpge8tYxG6jlB1+WpFyJaw6svQcf68sa7gzT8eG7pgVbC6D+7Ev6fXdo5vVWiBhDO
JyGCNrF7VlM5PFY/L8RwvngCOdk/nElkN9XoFc3RqQgIf456ycTik2stfGexK30q3GYhD6Wol4Fj
4RsFVDNsU15ZKXXhzwGcF3z6dKMFuuIaOB/hTpzCA+Errlfcg9tDjEzmalXvQxJEpvth3KpSj24c
oZU5f5coGnh+IXgC2fYc5El5RFi5ZTAeGPjIUGZyVVCAAPDw+vyR3Y4Skfian+EAXifrtrYwDVTj
qnwQyUihOjr2RIGQ5Evwchq7y2I9ZFdBr4dxtOMobJZLisra5o13IGNUIo9sL9tNqq3UpVVPOTR1
rQHZnQBVrD+0/8yFrEXiAiFV6ZamMUknR9wseO7tLMHVaBpBPXhoCnAyzkyzeVwtB+dliG1FjUUn
pZhRVlre7vbTDOfQ2bhOaSXQjnuLItCtbrcgwi7J1286bKVxAeYX1zC/QQDf0UdjNj/CNCUtQg9q
VjDi2G+7MEfkKLOWAKq/L8IOUl8ebWOH5tsd8g4+Gsc8x20iw2NpTltkg0gmWftOXY9cPDOjMGhe
CW7NNKawl1W8ppmn/ojvhtVaVDapOCOjYBG3c8YC2LhGU//uSV5iuOUxRXwcdv3QDjrFQ2u4P8v6
rrpXfiLw+HZfLg7qHyxZfZusHpZqnK62Byy7ra92Zd8MHcLz6WU/5Um8S3gkcHkMn5v75sUNSD8m
JuEgUSmEldkVRjlLAcqbol0chCjivzgnYgxqnZXZdPxLqqq5YEHoWvftbbdlHPgEFr167Igi0FYN
8z3rFco4RAXYoZia6tsqBCBckE+DYGcPZ70t65jgEFKTyJK/M4UnKKRGo9UQxwoWsbHYhvf6EdrX
i/Pn808mshtXecVy9YI/AqqEnMGCqzUH3IjMleX4U6s9znI3cpscYszGmaWDLWJUQ3vQ/qXOb1g0
dlwt29gwt//VL0ZbpD6pqki1egdwMcW8y3ZO97vHXI1rqP2+SASNCkITuHQ3Cc4M3VPWtg3Z/Wiz
Cn8ccqLMMFbIO1IO5dVT4N8BxTAkgJyLX3UWowPO3Qbg3EDbIsrN6Acwd5bCQHZvEfVzsh/P6CU2
EG0tbYiET9nOi0hWudV4Jt3FWHie8eInucJLbnAIG5RESG+fdwq0gSlLievs8O2FlapZEV4tppVT
vf2dW5Q3zsh8eP8V3qArMp2UbxY2C1DRSHeiix6hr/zwChzi6bpr7gxBXVPxBmeeqdo6Yfq+f7vO
n63enKPHxsX5rZakACexRvr8s3XFgJ22k3n5fIAN58t7LONASjXoS9zMxz8xMVoZ70BeGl6qsNLD
7b5s+enq0UJuymXG3EVJ76rxDiISbY7WSxdz/lC5EoGsWHGXigOp9nofiesP58YZX8QTpB6n4XtJ
KyZ71drqH/xnCFnbZKEyh7BLZroNV9Xd43o0oiFIfJCk+YZPpwyqNd6RuuZD3hKkBQPu252y97Zd
P1qzVp3GcH0gsqD61kNziI5ULVnd9L8EBDGIJvgTXrEasoXDULEmNy2AYt0M2KIYTnGF5WxD1Df4
0cNG/HaSskEWowbsZkE/Ok/5vjMuY2rnWo8qi6P0yHWZsItXfZHOmftIpkhFKeMq5Fo9Kdbf6SS7
wI/j5m1/n3kgiikfDltQFA+722IsWYli22O0W7PFydVjSJv1h2VsyWjhPL/awuhdzVEeM/bstKSU
ex91bpgU+g2ncOiEWDsEWwJ6nAQrlUMJqv2FYa5KXYI6MGgJ5mr/SmH/TfjAdpeSrN7vJI/YvbJ3
GaiKLRSDooB/Hv/4IIOP11M+pfy+Pii5ijucrDWh6f2iX6pUbWpZMuJeRSbXX8RMP7ugwswk93Gf
4sHorfyfTsxkjX0LzLmlTsVaB4/tlKibobLulPjsMURzAzN1lZ3tnY9oirJuT+ObwYq1tds3pv3C
0xju7PHFURI3goLEghXyyPCNOGWXHH740dlkTexTtgujmgTQ0QEIsXhkALvU+rH7k2a2CkQUodJM
oKlK6fhF75ZVK6LssNG2nd4o6pBLMxZg/hjyOTjnvp6KWsRSXAnuDmGO1VmCepMA1lTfuq95QkSo
CYQqEM+EMbPw674LHGvF9PZLWnhdZ2E1daiV+vqzvg3mF3H47gnduFR0K5l5GgBKJPMVNTRj/p0S
kQo33Y9JeI62Yze9kOblnBG6h6k5Koqau5xdHVMsdIeWmtyX2Rd+OxpszRw3S6YTccukmVdbUEyW
qyzvDTGPvmxnAxhXmT+R7Zpa60THNLkVlgHXxBxdIPIYa6Z5wWEAbEMzYxixHFCCcc5XfgkRBTC0
pX9+rSpShUNPIn5retkee314Xudl36WWUOstZqZWfjkMIkpCxRzF38PyP08A9d3lZrFOfLvBSIrr
+O3v2Wt77+U8LtUGDuI40QLoQAgJEDLNA5Srxp8N85pIrDPzZwYf5tMOgV58wXi4cVABSFZbbaif
YcCW9K+mJalkcCYrPJog/vKvQEtQdOSHNeiptiturnAY13RatZmx13np9+jKh110zT13+dBD8uFG
WprObW4DtudlYm3W9skuINaOujRHIqf5+fti8u/g4sbKIoRRcvASCkZiNitd6r0VtSxvlHp+jC4f
0HM1m1DaDMwHuph5opQe06qUJUc4o9POYw4bmtfh3iDy1Vb15nDz3megEWXExx/3OgSeRPFF4fEP
YN/CEneYjZc+ait/yNzx518RR9q2nZai5hU11smL6IF9NzcikgOVki7F95n/zsFEJ+zXpLwx9Rj2
rgE4zdxe4NDeEsD3C2IMOBw6bK6hmIpBOi7u52kNuNkw/U1hlyRv+F3XinytJ2OjTzgP4wOp7nqi
8fOamv4FOo27tpLomTLw4AMJ7Pg/fMJp2LR8odjNwfDW3zpj+HnGp2Eo+MyII0Z5sYOZPib6AQ6s
I7bNTZp9Sp4EZfFbLI/66cVqPkl68Ko3fNq2HTcHbdDQhzVaNvPK2ynbMPUlAkRuMacGcQq6LQlk
WI2HuGTY2ykpJj0qo08yVMI03OkZRvpTo0EOYxthwGQKa2CfkWGEwJBTUsVUXRuN0X8UpVcGJJyc
1L6E1Jj7GPqqfa2lwOiQPTSNebdE1cdlISGVKyZ25nKkNP02x0zX5FpjUuTCn1M1dUEZt4QjwTAB
4k9ZwkdkhZ2oHCxVlGmPgKIDhbIVMOEYivwk4eb+JPsevpjXD+50ZQ5MxwUCooyb+qI2mhouPrxG
AAEW9aYzaNe6G1ArUs3YU21Q3+bVPTJhl/YUeie0/BayedE99p/yS+Uxso1Z4BWVVxzQ1/lt4v+D
Xs6Y87gVvphf3Usl6r1fol4HJ7yFqtHsKJmfh3pvjDGCZg6+d0uUNroj095jQVL4kA5TAcTN81jU
bcGNMrNfik0wTPXYIX/b3pM/sXxZvWyqJ61qKUs6cF0oqtbD0lG4l/AZIfEoMNl+2Zuw2TSp+Q4C
xuKvJArN+tmX7ZeRC6F8azM7O8VaJrlVL6wPkjGwqWnQkyQFzONT1GvCpmFsnjHK4h1uYOAsCqKR
69hhNDlipHc5RxvcuxVeyPPkCMLOCOv0ogRP0cX+ZLLvCJTJu1gh32tiz2smvdAKB/4TCfQFvlzc
28MCCoCbORCznu3XMrgwlJORiqBzCkoQuNFy9iT3WMciONCfUHiNF4JYYK34JhYxEbA7Wqb9Vzsg
HQiPwadczMD7sfVFp+GGaEjScA9ys5uxlxMBQcRmbQJ544Ap40ADk51UBWcZfqLoQT6W3RBxfRtH
yU6YPvZk69nRWL8YtuCnLl7V38qmFVUVYlWAtekiXkDKW9ksGnN1n3FLWMatSK9HAxRGNAaK3+0h
kLCY1PW/gFxG7X3OXJBKyypo324OFn5WWt9BVz4aczNocpWtGHSEVcM5221kclAujZiEVNAZG/YU
Vs0N+DrzeNLwRVqEc5p5d5wk8MPHD4Wx8KyZ6WfuQAfvMjjVTAXpSDYr6N3LP9QM6WwbeWFK4Z/q
R2/bXzzMjjbcULpEo0ITXI0Y0GMFpRm4uWWaakzusiRyDK4+pkEUMsLL3THbZ4qccODRCdViRyox
h8f82KQjdEIY+LKUlirQXQuZ/BYte6AXozZV8UKct9ApEztHCRKR8jlW8Kw8dgJq5vVMbL05vifT
r6HIOVxI01adczELDmGfr7Qf5hamxMmi/c0Te5UWwAt5fCqMqsxUsrsn3ig7bXmnoeguf37OtCw1
GTv83sf9Xv9xEFOqmMzbY2C02xIMrc45aD06APG3Lj5xPF8cM2wHeM/r7dv1BWPiMWjwFX92Jme6
BzDz/irLxm5VzJ6kz5o38dFyRsn+21wfQ1BdI8+12uNQ+cyRwU2Vu+qw0/+x7bgdLKzHcyrLjAOk
/GWA6x+j8ANdnKUW4JsdT1xFQ2i/uJ6u1xlv12cexfwmfUiLkq+Ua7jmrXjIaMmY5tRXassSEeJA
WjJhIuZLo4z22GxToIU9C3NWZlP+ZMQ5tu7mH6o5/upqpLaWxcDqojsf6/JlAkr3dtg4VPHQ4Adv
6xUzalz0DPNmPkuv8HCXDMJFtV5RUTjDh75dBB5sa+4Q8eme6YyEgAo1FW1fARLfnckQFV86rAy0
UFxp1UjEIKd0dQ5gPAA6byZ1HJER3Q6z65SYJITft7+V0Fw2QwVEOBu6nzz04DAjCRMUPIrLmKj/
efAX9N02D/M+pGT5h+/Q+XULT4SweMwcToak/pq48g7jv/6A3eLpZ67FvD5zmgpmj5bZXY2IrXRM
yiuIzQ7PtPD+Hm5Jw/fejV3Yydx0CW4INPttz5Dv0RsONCmSb1weD0JNb/8KfkaAByR/abcy/LjI
B8Bn/h9lRJjRivrxxGmUBC+G1EeSkERydlPjG/GzVjDzrKKWQQIVxgvPZ2k04DJSvh1ZEdpHJZSO
FQaQJRZeotGdDxyd9Dm/8nrFugCYuEhIAv0yA2fnYTbepxWYRjFERXWAGPvZLQ+oNuJmOLrIC2kp
QMcvjrMZOaPQBR9THKQey37Lm801Chlz2Q/2MK9AKYVaq3IVIz8BAVU/jEZXXSpIXLWocHn8mAYt
sCz8QPMEDf0/q/19a+PoYL5TvprM6QZ8oOgercAWubb4cmqwCPsx7ZnvP4o8jBssJaQadDzR7KbI
KaNX+MznU6G0gklu1n+QzxNSxJdcOAx7NiR74blfegBEukVjrEt8guoWY1WjJU/UfUvYnqMHsZB2
Cdqy522FG71EFHF969GU0iH5SndLmzZwipoXNWf7AN9k2chLUrKB6+biByon47gW9KBAP6ZbwkgT
v4tjhtxUmbrk53nmBOMrlr+nnAI3WTffKdlS6uB3gsF5HzIzpgi14FZ97QDcaLYC7S2CrSTWX57q
1bYjkL45AAFoouqzyvA4aLcaxKxzWuQe6a+wsSWxsh+L9GXK7/FyPXyf1YAUYB1+iBSJcM8rRasX
RXt38rzFREu011pDXN/fiwalAFXDx1b7mjeGIaRnzubmMQzvbLjURXViGVd89LyNy9jtUND0yT/Q
TFAqggFacCvZmD8goNBxiLfSzlnDEoJYgvo94u8OdmeB++PBJqsfGGM7e47BcrmPnQ5qii2U7g6Q
tZcZGZ3H6IEbxcPnTXfuvanPvcxSg1eGini5rfpvYLAD6Je80RSzVRrOaAZYAcVes/GLuPxQ28DH
jgJg0q487KWnuOrYkzQg1TOEs3zTPXBDJr93tmjAC5Y1xMptokpi16lbX8cWnQ5g2egcgXiIeeW5
RLzyEAp68Rq05b3c3Fqi05+JHpGC7z85ztC+qJnU6AlQ3GAFDsiAz3XPykjl5v5TnKXUTiadzBzE
fSI2iRCa3Hdjfhmw2DpNskBaCXEN0B+In7JnOs2RC7wVcqhXrpVjcwlVvl7uzIUV9cTokD7y8YWS
UqVN7NGXau5qMK8lQBakcMEcTk8MdaVNnJ2KK8pZmRx29rcv7+PZrN1QS2rB9YFrsG9kHYRaKxGV
FENB2rpv9ZINkJagtQ5J13R7pd/5CV3KlITeWA4UdepXIHKM3CtY7r9tOL5w91CxbLPrZLMXk7xP
cBBphj0bBJuleoh623DPscO7GkM4W8chCD6gPQdsVNurEBxwVJ3tJmgWQdAWe0J8PDPPuKkkAJ2C
2SAgAXYnI0YO4LD7wRRZGsCcBv4c09Mkxgxv03rpH8tV+ilA2qZUAw1ZoC4XjpepfDan8m8yWXcz
kO/XC5fCrJsY2shVaOrQquN8f6UTh9wGCDh72X3mzL7EFEqxzjgbzxoymdpCr0LQpxrY4vvAVtWW
fJ1G2fdRiiXgopUH67UVlmJsFR82idpycLyMfJ7dDDFeTETfsVuMEEm2mO3EF3cUc7cWXEFgmexv
8xZLGdFbpFiYYwqePusMTGsjxxFjehHN34P2Ahnf1VYXoU3ED9zTlwxJkXQxw4MVwwIkDCk9Qsw2
TJraiUjz08RJNL4SFXCcSA3gBPjkTRYGxdwYei9fcuhxiX/F0M5KJ7kWVrLXsEqTY7FKsE2yGE9l
SvXU74zmPRfZzhIdrHQs0q4TWTqVfUzmsWXVI9r6eqmpBPAdzD6HCrpA8hcJE8vZ51j4I44fFPTt
zpaGYdnMUE3mBm56iDTXUF1716S2klX2+NemiWtYXR6/sTAEocWkF65VbjeeBXlmZP76955UKgHu
7EJEIi8vGMogVUaJMtcakj45LJn4Jp73wxYDGIHqV2lpsgJdawZZ6OzX1TyUoeruE8d6xwNIBQ5n
tRpLOdarv2aYUvmPb7nEOHMHP5wF1c35hB1w05ObAa+vGJaqJWDyQylejGrAgD/OdvLQ8m0W7tXa
KmErp9jo1O2e/7fdT7g/o049woYDL3Sh97Qs1s6V97mTXhMxF87qBwlddI4LHyEl2/cWmYnvxDnD
tI6r3ho31/bLY7+sT5jCQuCjYpsHeXPUHQmKw4gUFLosS2i19AD8q/YKUBp9czV+D7uthEVcDAGS
0Cqoa2TCH3saqNHBKx2sxdDfSAH5/xNk5d67LTstUP+YnO/hW/paS7+qsSoKFWiKqsgFvPRJCD02
ZmdefEuWbdTCLV9GSU99iMBQl9ZARqhrKznYkCkU+NBSKCnxAfyQGnFpcC6Yq1JIVDwu5kt1oysC
Yat0gfXSftf3Fc09sctrd85pSDrPiyBVwqis7vKvlM1Ej25HkWP3Kdu1Kh3V1n4tcNmrSs0MuJ6f
Hznlrk0VntSg8951n+vPr89vpDTqJh2EoMvRZAifwtPtQhx7gqguJ8oHN/0D8BqJbv+byJtSveXW
r9XvcuKcR5Yu5tGJ4g+irmHpxS5OebdicB0ih3eHOQNBtbGkJ/kq1q+BObLrgAp7OM3/RET38xdR
17mJ6/6mQD/CNLxQUXL1L32K0zwq7WtR811I5eW2myaqMex16TWnSNkoBQy2fpQiEcoSjE6uO45m
/pVqVSFl/QyxBUcYpzO86EBXkph1LRstZL0FuBhyVKmnSImx5cmpuNETm16Zg98Sv1ULsbkM0eIA
Xds8eqffuElnWNr4/smjSpE/1Q0JkxUVLpBPFYSwKwi45VK9jnAABXzwkOn7DJnSU8ZAX327OwPp
7ZuTgqA3iljAYD2RfMISOL1moomzfl6cfvszL+lLehVNLxD2/Mvc/2fBCV2fVHxVr+TEeK6KheWK
ZvfiF7af+aX8F/PiTIW+WqD8PS8f9Nx9HNsVmOJrVvpUy6tH7C6Os3YdcX0EWxzsroxfH0QyQS0D
9NGkNpMNtQGxoAFrsSd83mOXHLYOqGE4oa8dI2ba07Yt3zZAZfGv7IguAEVP3VWameXAFj3MCS9m
V/7SqacYD902cNZFsRIuMIr4yPTGE+0zPT6yfWFPaeiYge3fqmxZJYg5C7TERFixV2UJjObnvtyZ
JxLFFgiKIMeamNptE4hiP3ZrQZtDWxbPbcywS0Jo9D5y9ZsUcCaoXk8QXQF1jDlywbNyGxNjoAam
v8FKbjFVXlQovYHiaNxKo/r7XDgIQlrx6b3TiCmEFOaZjynClXwzbNXKZtmcLg50LghLAHl0B7sh
CfUDxH7qwEQeICfPso8uneAD9M9fcYuKfzpwpXwgTGmD69wWli1QuTAeUYMr+ISe2E5NVzhx0Px/
XxC/PufBotPqCL4JN6Mg8QpUvnIfrL9rMKkEhx9MGzofglhzVVykChVkC4/aUgkFM8+CV8L8m4dp
+e4zn1SgsxTSykcrpP1bm4KgDN7FsbvNCDdgQOuqYvDcv2bP/uDk5Zwid5U1jkCcAIAEgHXyNsqc
7YXmx4uanNPs7NxilT8yuffks6Z90hgyzH3IjEZWrtMC/cLsybEzZzgUgvzbR9UyBxgXWN5LPlhu
nRLVn8EzdklN3WHQovo+7ay3PZRRazdVx2LiFdHMNdFPCQqZuFPz1isykQ/rY6WjclPhf6k7+9Xq
0kgOPyRTEDKW9kSkW2yvKw93m9+kDwFSQPTYIel5E0kyx56wKV8CncGwAXt8AFoGQA37FAW/1Sra
WUhSQUi8oauqtQxcWCXIEdJz++iebqfXB+HWk8c9t1C8ces5XUxJbP02SmmcxxzLcDiDUZ+FRQwb
eKWAQIHeEC/1Ga1SSKg6BX5YJSjPcH7+UQdlohsz4tt8L7a55x6BjbehcS45jFWReoQjQYFR8tf6
0otoV7FpQLQsLJvbk0bJgdgmoEbeb4oplzi2OGindZsmaWwbI96iBKakguK9gwJ5c21G6Gar2d11
5spoEAWH6WHITs/a2gpy2unP2xH+8HkMahwJV/VBG4OaKU6vJq6kE7Q6Izrp76fPqyrmAg0flc/H
W72QfOeCi7kZFCY33XWxbn58sxtiYpgExR84pg78or7DVU3HtUyEWoRVkg0HpCSluDpQCB1PoBSr
HDloQfX6WlZfgoun5R7kOY8eZKopRFl/oSG+UFcfuLvyTjxeq9SZEOnVV0E3jlDPc6mICxn77DEr
YhhtSqMehHIy2zNYDH443g46YHDqk5IuUgSouGI7hKAYQ2O1UdczdZAQ1OL79FJuJmm6TwMX8rXE
KpTrij5NhoW0e1bYDUrndKWMX2iZ4Cg1MoSs8r30CPC+fqt4aEXGM/tNYTLoHoK5xwGKXhlCZB95
xD7FAU6URPcF+Y0NpMM46t5a7JupS6eFEtFfOdB/dsE0kxmdGFGKzYInExwX0/tO/I3w6OapWzCV
HEQodZbhDzLRSgOo43Sr70NmVD5FFzjxPL8NSImvsPIvMcBA4huuMtTRRDWM2fqLQE73pO0defYk
q7mRsKTpEZTI9xhICAbv3xivYaFLDqHR21SsI0JEEzm0S9ksgCjlf4o37jhHHbR6h/9cE1XdanD+
eOYS/Vq/GbUhVJUstWtUjGJTsCEYlhvVBnVdISOvMY6ouwDyDkSQxLnfEBfdrJ/mJp/eUA14fXy5
ZY7G/FkYIx9oqPPnx0xUfbZoh5QpvrIox1kXMSg1rmIZJ6gVyotO3JhTH6g02xPCpat6EhWGw2WL
YzwvkTf4vIkwdlXTwusan7dulZaNkpwtw3tvZ4YNqzwTmNwGbo38brCZwEGvCR0uP/lxZ9meI8/k
rnki4Z0LdAfhT3E6b+G7x8+gxFkybzGaTzSYyQ0vW/WH97SvyNQxH9vvvhob9Z0f7THqIWp4TOL0
082T/6f/Js7IpA0Akv7qtokEbOtH2NI4A4fNyB9LRr8HJy2yCMxRdG9c2h3GBnWtiviaKc9oJSqG
4RcQtjbwJAc+oykbCyV+nZl/vGqmqNrLaqP7r2ldCPhaedA6f6OjGCrhPGZEhR2s9Ko7aiLP5M3P
MRhhdW8j16/U+3JXtHIOiNwt+bkz2ssTqN8ijT7w3vsVtlIw50hjtyOTQkp8WRPJ6oK0gW0AWr+e
F3pf7gXbbC4BpCO7nJABSqPqoy6Cp9nkUY0JSMnI7Zv8Kln1638XjVpd0h/rKn+Iivu7ZZjsLqAX
QB9urba3EpU6AODe0WV27+kQ1rosLTcBR9fO5pz9gcIhvUWZ/QD6i5l91Qi9r2D9nn0DzHmyi1jp
jNwIVwHBKhoMIVakkar+VZOsJPGs8aL7Wbiq2hiTpwIgC8uDULwlUDs+cxhCRCyKQgNSUqxZBlgl
XCEvHVAwJSB9bjd139gYdyUKXH1QZ404ojXbhiIsDm0X1t7DClA7XN/+rS3WLpF1I7UhmsFrTLIl
Mw3XpSCsm+wFBQV0mkfacOGA+wFZ1lITw2aOe4dWMyt2K7PF7cuUPLtvYHYR8+oLo2VgLZZ8pDD4
Ybwj8GQIsgr9JMJ4bpnR5mEwtF+jruam10c7ZZsagp8D8auAruj3+pTThlXDNy310zIJE2gU8Cz1
exVxo541npmav56cHLX0gjG+6TkqZXoEoyaiDc4W1vhMkPFcZHIoVl0HFfojLo5aQhRTbP9xiv44
hkO1nR6/w1DAORp7jJyVRsZBIebzXysru1sikSCPDBSIvBiOMd94zEDwCjPo3lyQuoUo3L6tL348
6Y9N5IQDs+cv8vgnq6FBSRse0jonsb46YwT9WQGfp+0pzQAlvJFhsPxWsIU0wGhSD+8L8G2meAlk
hyzW9UFUw6fIp5aR/aKepiyLZgp+92YGK1sL7Ftp7ZVGdrAjZEWsDUBvO3Jgdt/PHFIA3jtrwYpt
tYk18a0XyHmfZ5bWL0eeSfT2T+lAB0wG60srtNGCvPKHykgTjegKEzHU6FLXeEFmh1D5E4Jf22b7
OzWTXy9m/Dg+Kmx3zBo2VhIjP4SEUVWWLqgi4Q9mkeYONB4nlsH+dLiL+gn6eeJvlY77R3ElEhf1
7NWKvRnP7ESo0hrg40sFU3DS4yYZcmLmRHIRGjkSF5v0QtXyB61iXQ+m0yr6OBvdWJ9w/b2FgKJp
NLtHXBSWLgAyoelLuMqUxE8jf76MsYTurHEnTIXReIwVHR23OMhjiS+VdCOTahLITgI2hdlBEipr
TD7IBfepEMWiaXdLjYzjmmlMBSZTOc/I7wIQx5llNo1lqBBsMutR59pnURTcQY118f2KVEg4UHCz
z4xids0iW50LT5jL7LTDbIi/+ZNWa8xNFCm1lpuQslxQPOolC3KzFrVrXwfF6B6W+WLGr45DQLUf
RXh8S0cTX+1XNz6rsj20EXLe4XP2ACBcm5Xu5plquLNb0GIdPKl4jRSagZzTDkNTKpsGeOp1A/6N
yYHDSofNiVd94Oklh23NFXoVzBpJgwO+CS/lbuzUiDFCW/7WOiGcq9O+4mmOesv/qyuYjUJyvLux
3h0xPz08hQ89XTVxUbKvJOX0EGCS6D7I6LZu9EhzZOYLQfqEinDuG7YfMXGP1hn0wn/ASc8H2FY5
H0SSDExd/Y1fBmox5mY8YG8m0Nn2M3aZ3/ZcKPXwk9TmmmDg768adiB/54PXxjH6oVG2gzbvct36
4u+/tl8ULNBZHz2roDwgkRD46+qy9riMlblu3EOsJqAuwEhy2wxGXjLRTcjA6zThuQoStDfswyxL
9CKL3DMxUdU9ZH+rBSDd9xHMCwFUzCqLf/RsPKrnRPNcOYeig6kDAQAy506sDmvV01tigKlZVOwS
4c0c4rEibhrHMQf9HXP7uWt6xWgyuIRvV7xCwu2RLphVPfy51YVWp40dTM0w6v16X+yur7fBr/eh
zlsT2EVlxCkQN/AokMr+kVrNNk6A3yMkFK2yTsdBVhn2WGtQnVxTRqXysOYA7M6Tgq9FMA3fiF0v
V+MDawVoUZsDS1PJ9F8Xlr4ET+KuvooOVmUK6xcftXN5bVLWrT/QmfZFvOOyiEgOGi71GUCqYAP0
mrLxNGKl6fQtkyECVbaUJY8k0gjadJ3oN+Q+qAoYatmQXUMZ2qiaQ+F9xqN8oLkiUcM32L4a+0Lu
8pFIE//nFr6+zOHAohWsL/FA06UTIAj0chiW5qNrEZ9+Lo/DKqKQg7QhQ0CdhPP7QsxFFjLMDbFv
MTcBn+N14lXdrVwiyENSieqvIZJRKrFCjTnl8IzPbgZBSfceAoWN716XZpx+2mceeZ4bYM1FHPFV
27UmqZYyCmYWP+CmvAyE4AFv5aKjtTotGZmqDh0RN4sqU07duMFtbPlXAF5KZoCmF+tTXML4JCXP
rpnqTCWFv80CJPmVzTNjyVXtq9Setzz7dDzsq3y+cNT0oVsHzeLAQPwQaVx7pjb2pcy2iigTF6MZ
wCHY6/N2HfLPe/TuursRe1dTXxW8qnUMpOA9bN8a4afQEVaYqp38woHjwRVSFSKbbDpxGHFPH1Nk
RTM1gxxsE83+MXBds3fd6xovTdzBKq75uxjr/wwn3gclSTVm5ZpgJ/JHfwlvC3hKP8Sjsck7kZxd
BLPoM12kbrQx79wZ3C10vzAA5Hrs1YsoGoVwlVilcgj3wIQC1+p74G+Fk1GVxcsLAL2kTgIj8rzy
UnKoe1TML4cTlKAbRgzBIa3cVckS02OVpDHuKbNegFtmNXbBxpM14eI4u4PczwgDT5xjZefo7hMg
othaVzU9MAAxQ87ktxhxWVaJlX4TJ24hhtlwC/VzmQfltmTXaIaIwhSz7391WWGd0Ksxs7FsuWy7
IM5hKnUEYlk+2xNuIzk72Z4dLSM9GloLRXK7vpvuvLhwo1H2NKou62OMy4yiY2YCrDTGyjZHgQiC
O0ucaCOUG/yE0LfgTrBobqFH4RBgtqZKevVtnArJhlmrRNK8qU0DGmrljzFwPF8HIjib6zLH6ZiG
Wl0ck0jfXbapfxVSJiOkfHFlNumV4Lz8uBMbJLHMV0zGbKBInV0Do/53lGgvNCKL0AAFjItqsmO0
eNC1TFOAC7er11+Z1cn1KXoB5nK6q91BL9vajUE8W5x1JvtjUq+mPPvu+24aswCOTSEFLpYTdFOA
irZxCprP5PwvCLTFnO+En1g7MECtVXhx7xBSL9PwO1fOXFsEw/S5ZhY1/KPXaIDJy447YLQHI7/a
x86iM9ZLsK8bovEwql1TJ7LGyKbXqrzH9cdPTm8TGHs7m2XW2JJIFD2dZteJLIAaOpVgs3SPT6X+
9CUip3bxJ49nj54QlWuMrmVTv6GAeBJiBoU7LG8Eb7vD182ReFN7P6GAeYw+DyqfZcgUn6GCyMUg
WF/Bv1heGPQWfMyNzn9hu/IfYPqf7Ai7lnUfEiZKN+Zdx1vQxEFDNQO47LxY/3i8OG4BHyhuJQ9Y
f5FtUVsCp1zXGSkxuUA72AAoMnh1Qw7fBV0AC0fNlMGUEUBbCST73mURCfvO8TmlQ2/sIdVCPNfl
MiBhTccGsw9LzqU48WTfm5MFucivGeTWBSTht2mkcksyoRbaCr02F6BeGkhncCJWY8i1c2XdSZVq
ELsWaOR2EmGiVOCQSgw3YLFMSXf+4M06Hj5FytV2DS6WVs8E7YtJpC0Qy/Ec/mG+eB/s7n52N2fX
XeWJ2VEiRNIHzAXBa5zNM2xLLuGgQ6/augkG5rv0DGj+HDax6XHZuAdLN+S9lLDfVKe1UDTP3i4u
bgHHn4dfCzQl1GKlLS0B9yyatHw+U5wodU6RmrkBdtX6HvZT/bR9V6D/UDGczLSRpzT7yZEFB1/H
50OjsdbZBnRGjyoyNMECd+FMj+eR9fkvEzqe7nB9QxLTWr7O/1n5yUTk44ITHZBRd+/vG1S6my0W
Y3pkoiZLPYkxFCZPp70xH6ZI33ER8I/fJ5/nZK4OxWvVphkOFMMnJPnly+qL6LdumqnyPCzjBhjN
9Nq47nFssPhhJai+IvLdM4d5x3tL8JyO7cjlHv5HUne2ZdDTKb1IWTu/k0fNxEgpLBgHF5zeUUkB
snv1hCUlvbOjaootmx8RmX6DjhPGQgCtKmDBnv4sOZSjaulAuycRK+kNiqh47NvBZjMXTW9FCLcw
x0InFKAgF644cmk302yP3C124AYDc7jkyZKRuvOMmk8BNy5g7nJ124HvDGeWVgSPYAh7MkR+RIey
vStsedjBsd3QkycqQEM9hxmOTNK3KjVDyqSuhlUghqcwxOgWQ7e878I/KTLW2IW0E6j60nwNeeZP
7AZiL9UYti7wFyTr08lyJq41DcuiQ7U5EkSmn6fHRV3JqdNp8+Y1E6+5isTYfdMgof6yg4S4vfXi
0yMGKKlfBJh97jaO4uv410sUDweEEVmsjR2Kdp7ACXnKEc5w+Du9fw/sRvPzvZACVq4yEKoqsi/2
eXjRsSJLCQICF64TpD/wAsAhc++yHNm+XHRP9bWSFP+Di2eBp6cZRParuYhoVPxuIjvLlgBuA+Mn
IPb/cZ9MdwmOBW5msyja7BScUrbBiBhOALavquFyeLHJ+HLtjwZQ1tkQn54Ag1/zhtY3BcObwBIv
8LqI6FkXwQvBvjHi6DJ/Js8TDPbW/HBoHPjTD9p5fOxhmiw1ZlHFlsUA2u9N37z/Dl7tzBmwEtRg
K9xE93FWndQRs791iFwQBJlxmFbX13oGFIvx497iQ8hjZovym0Y1XM5GcfiG8e9ltmklTieFVBdr
dB1cETELG83tmaFrhkac3i8Tm32hao4ySB1+mJKJ87a474M+a6beAyBmM0TUXntqVAfJOrMpIjwR
y44YqmFoBC15iDuHrQS1B0HTA0RZK+mszGEeS08cEd+csijMMGT4iOm4jPKuwAjcajZ2QgAwD8kN
4v323m9F8IbFyfNhqAvfHyq3ApYMtrMVPlpDumHCPbcNy0pzG8EfiIA5IivRGoAniJaxytJ7rsHz
pezsitc+OWGH4L+hE2SkE00FIx6NKUomkF4Nd+fuFkKOlcKQC4K3jAOwupeWxjLNhFC2PMazSWsb
Cm3/UifW06gMD4izfajJamfMtNLpf4E1M2dKnVDoeyX7Yruoo4T8y8vfgd/5mBUHGHJZvtS71j94
otFZumI+PiLkjuEbNPnVmoNFBLDrUOqZy386SwBh3ktfbNWT4XOstk0rujOQWkRWUUwmXItRZKEI
aeX3xn6KM96fDGytzyVpsdmrj328kVixS+j2SWfzBjSfVNkqEbZ1JSK3FuvKo0/TbEHuckOqaAfO
6H2/gd48NwBz1DXQ1ZkeGvQygEd9hE9NSHm7uUdEKv0EAWjyYvOtjoh1gyI/2uOCTLLuY8JP7NY7
JCMIT8wb5kMqUSy2ntsLo/7Pt667HUvcfBWZsQLOa2O8pHlCEdWYXDL3YrP0h7ONdkII+nwdnoSZ
Vyoza7W3v4b8ZbDZ1/oWZEgcu3jLx1qbuLhInYIcLLx8Bp4S2iMEKr4E2gue1DUNZKdLH9fri8hR
8KjuEo22OTjGc8BCyYmANLIxiHlOMFsQzMDxEAX7Je2Cz4apLVgIyUbEej31Vc6TFCfZ/o1a0b0D
9pvnkuSknH8vsqjaoDHXmaYJS39BZ2IoNg37t67FR6CT/f5fvNiIYip9anPIUawCMF3/MJNqSLPG
lAh4CE8UnVvhYCIMfqIo4twfqrp4tmH8Ki+qf65W57+t+VTjmcqYlMq4/kjZOt4S+UecCbxQoRd9
CO99lvnBCpuICugxWxNos5qso7TbYhEO0OByWOGwDesgvJlM+k4IEePak4RxVHlcu6pGKIuvC89M
iSYj8X3CtKOAxOD7cE2kHvsn+nA5BxWhIYNuHixvf/uvA7vToIEjRqRe9pu83/oG7RjbwobPuWrP
HSZkKr3FOM/ArWPTqnRXvVH+Fw0ylm5Py019y+byOeg2MzPs3Ajmto5kYyuh45Yk0dSaG7Q5Q6/C
vIXPej5TmYaJar26K2/ixKTVI2WI53ILyri8ULjsQrskRoIckENX4NT/iqH1HyHZGUp7lie4OhKr
XqFcxPx5R/dJGbyFPMtWY8kNvokUVpHxD7aJKYwCxbse1yH/xhmZ4L5SLx1eXDfYRPeDS383pw0J
+n+U25Tc6cyUETestbM6OYkGKKzp8yPMkcoJemf04vH9Zw45PgdP0JwzzpYT0vlMON9KAN+Qqsfl
DGsCc558YshsxhNUExDVgtx32JZxGeazRDPgMQnwj6F0MeeWg1c3QTwNOvJj4+GDsaXYE/a0dEvy
Axr1UBv6Uy9UtJ/DYSM005yCrSbdkNwo7Tso08HuhNJt/+hZ+nQBFrDftHSzx2QfUKNinlFNYM7s
0b8aaWQlItKU7alXnktg9Qr5Vk2QAHMMRLUo2ULcDakFquet6oL8zkX0sY6qXw/XQWmwm2attUYV
S8bxTnHU0ot2Kb32Irxvk3n+EWBWiJhUudVSdVnHxzKcgvK0JEBZhVl0e29cJR8E/7a2xv5IOkNX
yzpG2VOhL/OUBkZK1y6bnqASQdYmkp0pPcjxE23yn4f39wQVrseiGbeE8KcjvabmC5sZmhAvk5W/
QBxm2c99dtjLXCTl7b4nYuO6HbnrfqR6lPmo5qD0SavZgsgCM5aIBRCymj+CQWRFXeS9msmtNgDF
bFhQztVHUEvQVo75Ht2Un0BZTT+5EKzJVLy3KHds8p/pmNUddWovJ3tV/aqjmpGyz9KcBqVu5hTy
Mnn6rzKrvtqCLYNThLRvee9vlWSrQoNyOY0EOMhMdLTMyJCEjt9Gte0sFmhfAWHdkI4XLHLMTtcF
OlKd04GCpibis6aqyl4PVI6z2RfurxxVa9mncaikioD0NsMBsayLauVEmlZ8xTGBm0mPdhNWcMi3
hTtDpkYw5QhvjdZU8MU9ew9oNud8l83ko7gNKFNEnEHHDTllNQF/BemhngR7u9+FBEzO+7i6OosX
q26/gM3++ERs+680ZVKVYBFNvGm2xZHUJWU52h/k9UMk03MBxPupRJa4QtpWjPZYgrsPLnrQsZfH
Cf+etoCgAvE0d72uSztt9R9iZ+cbP/N/dj8B6ckyJ/R4DVGxdAyIbs9vHJjXlLCzG5aTYiOCuC9d
fOTYbXtmsIeERh/uB6X8aB8Q2pvNtP9txGMCQTiuNeVkhW6N2ZnPfS7KYe84qDl/35bOR30cr/4t
u2bw/ou58rw8PuSL49QaJ+7zjWigNv8K2FaKoiHM8c+VWxsdCDbg7r1ulygW9Z/i+uZCfT39aJtz
m5U/j4r4PZE71MVNfJds5PKMyTxJrO0x1Gn0+4SpYN8p5bRkJavaR/dRWDv+x/4tG3A96kjEU2s9
1AWBbrp3jqJQMX/FfTL8nltbtCbgztoURDKdO9SkFNKXuOI7mb6U/FgoeE5r9nok+yNMErpMEYRF
gVWTG1+SlreKca+i8P+gNZ36OktlGj9RtNzeEyanyIA+xIdONSkND4qCttpbAkom+A8804u4CB0v
21BL6Px7uW9PftITNwPg5PG34z9IJnRzuNprSL+ww11QdOHcLsNCJADeH8OIme7VTkcd4LTOOz8Z
i5HsNd1WoaKVUc+9e8QzrZcJ7lwhdSw22l8EgoGdt2Qx9SS+KvJmukj/50qxG/j0zDYWOYE/U7F3
pA2b0/IYoaPkknCb3ZK7Fa2GHynxHigKY+od23Wd3l5KaicDvOQPJncDoVnMBv8eWQHKOi6ZMc0e
9m+I884rkSF+4GP0rxM7d86DtbNIM4NnsY3987ArYVWa8dROuXGks8sudYPXSe5hOtE49Sw5GXyl
KdzzolFNjVv9p6Mt0aR/YzLIx9esOF/esH/+wlhMHnJD1klyDtBWR29dpp/ipKoeIhIWgP6AsVTB
BCTHGLRhE2jpg/57jfSqcYNW4Ua+gyw8MS3uyI8U9Fyl14m1hJxKErExABVJt+U9IUTDN09sRhoA
vqJKqlAcC0B3bXF766tQzrC8PjJFAkOwkdaMzxYsylY2Qz75h3iGecxs2HYNbOkktIT3h5WkRdli
NSyBZp7pzTb0kmrGo70lJtNek4DOkQCvDZEqI8MWNHgsnB3a9Tuggz6XLhW2QAKV0nAs6PWmqKpr
tjHvtot5W+O9f/Fo3O0/qFi+YXpLUVCciSmXlSyUlyJim9kX9I+o6CI4Tty1dff/O3PjBSYfBcBB
tsRalhdwfa0G7Id7fGpvIxrdsoHzNW/iY0W/2XYm2BUO7iPte6a0BlAgUv7dy7PfXkTYGRy+8c8t
NljhNVv3wpcV+eWspXYiT8dFt41HBkLLOTrloXWSGTZvN9Dn0qhPxrQR7fZkYKnCN900Etw3xTjg
ll7EptACwDWmGi1/qcJnO+5oKE69ApmDHWQu8OJpr7Pyy9IZTbJWhvBKttqQ9t+L8kd+1s357kBC
KqzH7gI4JICM38G5Zcmce7ovMqR/oHx/BEurOxeIGB9GuSaLstkRld/aeaDle61TpdpOK61H0xRw
DpUIMx1shpeepKD6/9rRlkVoVyTHpPLHR8pGCLRpHv0Yh4NFNaPj2mRneQGk6byvK4B27w8D0NEy
Zg08EO+sc+ZlTdXFtFwweX/opZmWdKrut1nnBQhKbdRvLBLVO6uPO3JIDJpGuh1nmj+tODQ30Z9C
Do3pone+HWGMbM8O4KDDNuAc15U2agtqDXEhSqVmhWY51wBPrr9ELO4j+7wa3+8xhurjj65NqkJ/
Ost5kQlYqOPwXG0Z5U1zBg1LCk68EZeP3Ex4aRDL+4wQdmUYG+ppJGVMKJe1nMn+b6/7Vz45H2/K
qoq7kfqR1XMjO/d8sAiI/qYLTxgxc4w3Xli9A4WXIU4Jf3C1RN2nc6lFEke/N7rLKzayV/0VWEuo
Y/DgGsD9oZrY9JuHFMeG1AUTtwNDAyTXeFB9K7OQZS3P6wkqvPDKoPPmMRkjn/b2roTxEBK+26k9
3gbswGy5WGef/0M+K76Q0gjkH8J52jgts5CHksHwQ1waXjPxI+J2igb5Z+lKyWselqnXGh962zPA
hT4GnUEZuFOUUnwJoocRSOXCm10NJJuya86H8NRKjd9Byybd9i379xwjn5VshBofPj1zRCZuOnmE
nJFHdKuAYxJQX3+Gm7L2cCC9SRLRm1N/ApY3Cqjk4Zn+Cy2JOZ4YzyKwjetzuFmx5upiqSb6KkLK
kdLMvSvfECQy/UTx02NjWbmmRI6nwBAkwCWTMWKtHol5Tv7TloiiecjwTBkQ97H7/+mvM5q7lSRr
BSxjv9zVsHG8eHM7D4zJ7rIX00nPRMOxYAzvXlO+8DECyzElHxyKMkSDnuGMLxpW3QkDngC1E6Ea
1eoRbd+ZgjShZi9NVkH7Jig6SYOIW3J9jr3OzaKczCOCQvnEpCQxEdSfpsfTSCG+An9Wal9W1rv9
aloFlBHgmXkSmc4TYGXUY4DK7iQ6Ym3MlqZ7forPhJGv+NrHFAWJoB9B0+FJ48WjANHNUI4zVuK6
B5/t2iM4C6XCPSeWB5CbXAE2dIzGjJgzwj/UfrtKKeYtF0eZctptQ8IU/SbZ9uzpgM+gpJR1SrR5
B+phjjZkbO2sjWNpzUV81eyu3dRa1nxxR/HNGmRSwp1QOd97HCo0N5hbUgBFrGeVA3WypyhORenv
8bDeeF7Gnk1eLZqE+B5eek062DNfcqJf5lBa7TTqznEWT8R/QQjkPTrbdxokT3gzx7HflD2xnSIk
QHzRD0RPd6uA7Nedfm6OPD7syfZ019yNTZT/udrQNEUvl5EuyBYlMXTmI/q0tGpXl40am42YoFiF
gVkYXIH/ZWBQfdtnbVZVfCndykHweGgr6J2lB6hY6NwuOtdg3uObXVuaKAwMF6oB8Ps/NsxKXKqf
61KheeeWH/MPyur5IG7iSBUEFWvyb63Zxhpnvx5/AR2UiEtCt2k8FSxaNtkWDjLUM7rMeqGWONSA
GCNV9eWkdpqTeXlRa/pMw2qAHe+w6K/7tVjsOp7K6sKj8k8jbLrSDBRVULSlggHxJhhObLWq2JZi
wGfQMo7scGh8O4lFlmZIXxDXGcnmya32I56zGMoCAGu2sNKOyxYlIqbYYmq0gsL1Mc+A1nOMAQYO
J5sbuExJST3kY1uSRV1Hh+A/2RPHG3N2LtVTRKG2SgUsoZdMnE2EygZoHWdZAm6fIhyJcGXV8S51
I3LMn95FeXiqdHP9I4AV+s4pngavlKlijXh+sHxuL3sm7qWnRz0zZs5ogBhGvfNjsiJy6OC4UAAv
bgdJ98zfeqW8N2L74lGwa6hWrjeW0JhnpjWuwxUK799y4Ftc7VWAFjrpQB65yzt6NLpZj3kZmXAJ
p0icA9pzTJ3axGZ0juBJNBCyZCxlkVXnV11HHzhWl7WVn22Xn/6mZ6FyqDqCWggPxfIygqkK3SjH
hIBV/H4eqYJ/iLTYvHr3r+EKNBL1nR8QMMSXxnkaJUtK8iFzGYv7lfik6AYtqbHxwowgweLkiwkC
Ff3+Q3hE2ru0v8+cbIi1ON0o3WzqNYArRppjDGUVQXjDvD+9xVstA6pX7EPVHCmhBMQK+veYkma0
Y9UBD04gvXo1ylLTT1hkffzVOSIKCIhzGfGp5kf7sqx+uYicgo0vc+KIPK9loYQgwj9QbUjWA2BK
rIqQiZ0th+ua8/ip1osVUv+QVa8Liftaj+e2vjpOxJwSORv1QtjW5TBLlE+wpdmdL/WhLCUG6ZPm
QocbmweHUbwOg/rINmubQFBOOgRP/fKgqy9OejjpYEbCtW7ZiH2EtuGEPUF4Ds9xMPm5xe8pBW/F
Jeoasfdb3yIMCfhDrdZTIZORT6dvqQT3qTsnZS+9h8yVx5iwZEwEEw2GBOPiZQR2dJJTpYDazod2
gqmwPjQC1z4JBTpHeRXGj+Lq4BPJ+s4a8ZIN1l6HDyBwTSqKQmNMVQrjipr4UmcotvU2qIOwG1Oq
4bzFcTzxOXBOSRA9U74j7m+VQbAOy0UIAVUYjgQXLSKBCtduLJX1WLzbYxy9MMOICJflpqnThbBv
CtolTYULNoK71LVm5gFdyKJUGfZKPV2Fn+CzANK/unXxBfM2hWQERK39ybvQxakIxR0Bdso3xHOs
AXmgewXZQHrAeVkpPYdjauHuiCr9hIZafnbCCkp+SxMhTdOHmdKbbT6H/YUzLXpBC6rEfqYa8snl
QxZcXrjcH7bjxQylXPTo6Of3VOk3VN+xqqcKU8sheZt6vw/xXUPzj2OuaA7kggDX+2vttFm/AZ2X
jbs5NmgIWf9aO2hJVPhJlvN9nvzE3CY5VnYPSxUT7ove66ER7zzhUfXki2OKFZZESxioH0SWx+s2
Y66T8PMDdCIbCcjvQUKS+X5I3JS3fEnTXP3DhkGETOCWLmaR0CTMjpe6R5oVk5MX7lSFnhmH0ENp
31On1e8cDqCcjZ184mRzBD58LgPh+KyXPlgrinKOZgfWVI4YehOlxkdi96ploMZslIP962qMtJKV
6aOkplvWsBWgtPa8xTAziKWoJ+fMq/C9HUoXmJIbcShIyCXZx/JahZgETjtDKsoeRFs5ymT+LabE
IrxORaX6f3HrKtDXlS3tMO3DBEpnpZ5KJw8ElgEaNGtL891mhqn/zfBaenOl4fEKSi4nJXW3ZA8g
+OtfofR8yMNBH84EK81SnaCetX3ZsqDjRV7FYRuvwZaFrp5+1kOkIQiomnZOxAFPHMXZcyUh490Y
Wkt47T8uFXuJm1SDLI4WyRtATOFU6M9B9EQxUAbNHChsEwn/hvT3ZsrupKMjCYYbvlIKIVxbfDvd
lRyVym7ZQvDuZ3IdnsywZ/iY2mHlQEtTnf945FvG1O5m/ffErtRW+dFisy90dptaV0siIzRBKWSU
e+2Xw4kIQZgzzO7RIEXml4Rwb4HEF4gIhnEr+Dws598lP//m/LcEiYNTy6K/22fB6wR+pJ25EMFQ
NADZ8VkVZ5NInpLn8UdoctKPv48EUEojuJfyZOBr785NdRtgn6vXVONo/CLuuqMDmvS55UE32OMm
1GMzm9ZXdbHPWPGah9dx6BwrKuixTlTBpfNQaXsgnwCKjnjn6uX9ayysqRzlaJgWUKWQarg9Zzlm
sir29SxXI+IFj2ona6UeJHo2UiXULz04BtGFvJphByGxGcL7nRtPDLt+wqoAb4QI/IZDdaqnrqPg
yWf7ugnBRLOk6tn82diclFNCAHFk9uYciChLFTu5Rwq7FGCkiRT3RQyHzJJJLvsBE6uGHt0w73qE
fTBRfUfftxnH4DJx/9xbzhmBrwPJlTwrLPIYZ/wXHpkKnDY6Ok8yFTD+yN8foNeBnKK4p7+q/hwc
vEWGmpWOdEAuMQ/IqZ5laeDVLKOBkB2IGnrZY64BDABiOJSjFcf19B7OlpRxbyMwopnsIm78zgkX
FR6Tq5MMgc/5NjAv4VrFx0oRNtMDO7OmQjqx6sApyldLj/gmDJTTIT4o7APue14da79BbYl9VJbf
d2yWViTrAfgim+AJ7F9wT1Co9E7cRK76jztxQGccEHcQfhrzvt1hDMcF3iyeN7xDAfjOIpXTvffq
gMLo5xq2m1oEMVHDsD6dNwNW7y18ANKXnuc3uZDm40DfRICaAIlXf0Ru6HEkJvT7BUczmEL9CGvG
JcFDunBK/khmpTkN20BbniCTZYTAxRPOl3UyvBOi5ryrbOJ7Z1c8dO+mxjYAIQhzcT0TL/3/cvz5
o6CGNUPOlzDouhV8YuXCkBgoKkRIkd64vHY3ICSEfT7MLz2jdpUNsk776Fz2eBfS/S82kMfQhJV9
1k48pJeIRwi1wcgMZDbUx0noivl3TiI+yC0ea5C3yP7Jkkpw+71TnFcQZT9RUbAe5LL6Prgo6Yqr
Gv+v/vFVbpvCXAtAjk9LPKnzrojZPzVnUSLPUdlhRQ1oj7Q+DJu4qS5aKtHNnOPLoKsgeks7x9/h
xujyPyAGeYl7XTMzxCfDYtX7TXWBtaGc35H0Ba+Jnqplhlv5g+jrMjJHwuuAHvC5TvrSOsooW4Xs
A7AlEE3fBke/QmLKJUAx0D4rFG202SsC1Bp9faYR1ncSd6PJNal17+jGGBLMEv1VPx66vS08seJg
GChaz9K82gZxhvetoV8t8X1FGi8amK+xs4oEYSByaKz28RE3+9Jx0cjctkQ8UVgR2L8qEvUGu7Hu
7p44V5qnRb1kBs7ha+elPU04yK2aFpPVRSqIgAkCaId4MWxvBD9U9krALlLcNhvnk8MzhnMHedsQ
ywlUoyAYibB34JzzGPaclEzxtWxVfHVpuw9h7bT3d9rz7AbOzi0Hc3VWJf2mGIVvNDRWmIxfJhlp
6LKg/bAcArG3SLJen6VaIxFUwL7DXV6M6mS6LEiFfoQmoX1FpAFL9OszjEV1X29v2oTRds0PbXmN
S+NbdAABZnrjTn4+Pbn900zQNJJpQUyQKjcJoE0ydjvAEYPZ/ynQuiU1IHaMlzRoNLF29Qv70ORc
PZ9BsRFHAsLOJ56fAKQM8Xkj/XJmPkFPC/rCu/01RYavO//rgdwc61XihMTXzXgqjM7BZKzBcAgA
Htk1vNzXmh2lmTz5ZXdCiP8EiLdvG0QasRoU+Ijhx0ZIgxsIbsGFGyPVDHaocC/oX2oQjRyhznJt
SHg9bo52Jhx1UCl6dyc2fl/2KqJTTnohVKhJ5Byx5F2mszCfErIbbP9SKS4lOKCG0c6y/E+wcAke
6O+gsnfm6SnD/wyDEep0T2iZLh50hNV20bs4U8J+PCQKiXMIj52DrvVCA/4rHDgxzoVH+TqMTjPz
Wsv3/JzNLokh2+DE+5clAAyuOYhm7kkxgqyayv+xfycJL49wu3iugDBgUyD7ghsvrTFcBRgxiBPH
37kWzg1gpJvZqCA1wamtZeFMn6BCF3mWNOA9rCzsUoFyLaP29GLbGKx493aEKQk3S7FNB8t3ZWHm
vH6iF/wFFg7p53TbQfIM0C1oDC60PMa8RlBkwh5V5Jhkj1VDn0vNCTTsAb7V5cD44RJG0OFUZnBg
Gz2CvLkqxo08jfi9fHxqFrG4DogAXl7zyHXrUVS+mUsFJQTlPdoTQnUv/xjXLEswIpQ3tz975+R+
0y5Mv1t4188uXs62h5lOJ2Y6dsNvXRWxdUNpGcYbx3nP4Xhj3M4aSnsiyWkRwiQZGkQGet0GglTG
kxdAdp+1GJa597PpDuoYfyAKKXJorAHxAZLwZ8e1Jsv/d1x7OeUWFZGpLjVaHlw7WXZKAtQI6A4p
QP/AykyhKE6XFlajOiKmhJ4SaO9Pue6syIB42aeshDroPCSpM2c7Q5t/3oIg1pNxDWRkDPcmu/Sv
urnirkd/XLIk/8o3xevVu7fNSwwbQ6P/+0OvOvcURjZoknC5s6ZhPbG39xPB4f00O8sxPgvxesLV
KQWcKb/0keeUrdokQGP829ux00clWE62FH8d2HsenjvDGQIQIPkngin2O74upLQUk9BSyObpKPUM
hp1jntItx7L4gji2Mi+fIfxe7dKeJNg8lh/DoSH+hqPig+kFNgVc3ZvmxmChmLFn2LfnyowN0CMH
MFIA7c6iiXM39rTg0zFLNuQeX1Jfa82usdJZ04qKkPVCBstWVUDyGjcqh+VRb0zAx4xj5+bNQUSm
LEx9Hp3T3a5N3WzNhF5QQkfYb/ggH9DfyyGHy2hw/yuo39jW6ZdccMyhuHZ7OkrcbXYFBY1cZfh/
i9My+/UwJg2au+EPf7Cj3ntN2mN/81LXwOHaN5MJUBQhw+CPxZq58CWwZJs+GmuH4BIke7v+74r5
5p+axnHi2TMje9QPPow4d1G0ZxYbEoFQr8Az+lJ5BdjCYAMpe4dzlPp/jOIXk7tKa8UFo6I2ZceS
Fe+0J7KpgFBclnKBsn4TJ2UjCqtVrJ5jYp1ijWOlY4qRzlzXaab+3J/420hoDWROxoydxpYu5BO1
+JEpbXm98rwqEJzrKXTNwlEVUbrRXkrbrWGTS42biBMmTCnFzlcnL3b9iR8r8PSDmnUSSmpY0vM4
+mTYFBGH8BkjYVE96NTGhOg2CfX8rrOt/AySC8h54oLhAr9M/fIrvWkluNCQ+CPvEMDUg9Esnvis
vF2Iz7o0zptaj07yGY5eZcbhuFmCtbMgzj83oe3jTLK7t+hnRxfY46LmbtLYPsuUTFOTVhXlFeF8
Qr/rPH2WkBzrPB2zYpvIIAlq617ca7wMDwc1ZeebVl2FESoKqDw6/cBFSMIO8w4gxrK9ROkMVWaV
k+XkG+Ne8Blzx75BtS/GKV0o3LGwvKTogiobGOsMOdY8mjUzZ/XkHSTP3RSh0Cel1jpF9YnlG0hj
/C2/q5MDQJpNsUSWlBEL0pv+LPPnHurTbjmEdRLwZdjasUv0E+fwNtNnMJvibStq3i5qpmjqUIRG
w4UiKgShh1uhSdcHtkZiC+q3/hYxJJMF1GiiDHG/gOrdBLIuJyvjAoy1Q5ZbtbzIydc2VLiy4Zo3
q0KMfHjm4WPt9wSvdPNxDGEj6yl4N8CEkaYemC2QFQ2ZkaS5+RyiUNYvUHKvwik9R/DAng6GcvcY
wP7pHZXZiLaug9UHuGOra5lAYT1MR9Lu70lUMV/YB5MNtZkpkbHA9s5+e4VYJ5yGZUxWDILXLWKS
0QqEvQBR+Jv+52UlQXy1bXU/D+/RBVzxoVwI+ZNPTZ2ooJ/C8shKldk8uGJ78x5B8JpXeyUkFI81
jBzsW2ey8QmOEaqKTpBKw7nuS6plzgtUHpCTLqRhwWreDYb5Y9sOSyy0muyuuGkmg21v5lFPZzrM
Jmxm5wgX3GDmEa868wH2aLi2+h91p8j138necfy+vc5GMqQ+A3ajODr6y8X3hniovAWK5ivepUnO
lfNRYahURUGAIe+j/kZ67O7EUDuofLDO7XfmNcZunuurjtBIiKGo2RsbbuODUJsDo9rHnv0scQfb
m9+o/Gfl2rpdEe/9uS7/rb0NS8zrj02dM4NlZ1yQsJWpv5DP0mwYCxO16ma6eDDdEHOLhGJsP3g7
IuH6/8HY69qhDYTSR5dU4WnlXtCMDy3hUZk+EpCCuUTh8utwtptOKnObv/gPcDTUyEcX5x4oTQe6
4SfglVPlUk9lWhJ3j6P7M3q8rVqvvl5bKSF2u9ZqFT23+tyLkGwRiGjPizRjyenRBLWDK+ZFPv//
OJF8NIP3pUEvNmLWGtr65pUFxbnWdoP44n/4c22PhJ+u7tHbIS2wfuLTzAixZYd5oKrlFUFKkFZO
mdLzYQPEGwJitn1kGNfJpAx1Xs9hCnK2ZsZG+6wgE02gobG31O4wf43tHEQAkmnDhyu6mFqPhJNp
vCJ3iYWwTjqeH+NnGd1vI1KZ1uVhnb3EVR2/THzDDuQcYufCSimHh+WowVNwRJlWmzkleJzt++mj
5wpTKbsYYgHZGIwOemEoc2/+auCck79L0JydiYF4vE7lcbJMdxXceuIWjJ3BTPra1sUXkJEMqB5E
46Ox1BYYh02eFc/l4DXL4/swBqMdkimDAMb1jSg1/ErP1FNpRZrP7ky82lixEFS1Z0YsBVVzhq+N
Y95YMzYwNxwF3pkqbzdcdkpspUEwKSSedhcvv0ev8uCVbHIvDSyuRAAMMWYFIHeSFSRaRdMS6Fex
8fZLhNaoavWece0QoKJzXWK0E4fVlq3jOSRkr/bJYb296Fuehz89jXowtvFYV8loU/+zBPe3m7HO
XY+zlRcdQpDOVzUdtvTqhQZsrjCfPk7om9olqh9PbHGlNpGpGm50nx6L8d0EJciz6JBImHxbWj6T
OtXolWs1GZWDSHwIAXvUd5QcmQ0Z23x4iJAY8rV2JJilGtxHNitZZtNq+A3ltJEYwHk/dasscKrw
eP3a/ObYmzDzN9zV85AsGCgBVKt2Yka6ayRstMvRIDh6vM1hOq+1/yRIM3gQrXtAom4Yc5hcHPf2
Q6IhMu46a5z6R+ZyoE9VzYLjsSIG1Ef+j6GP0zu9aCGbV4igFPtF/YmEMofKXmYtEUtdFXvT5XrE
0QOH91j5jssPDb5TBmqh8cxX9Fr3kd9xYLk5yOPupYaAeEeOXyXT0q66bRjOS326UyIHA13iYbus
IeBLyCUorZTN9TzlRq7iEAQOq4zaNoaTmzscHjK32ClIKXF8l6TTb/uD7nTULzZfPZqFAXwxFrVk
5c+Q9iWtSqkF3ZXuYXVeSIX/KK/13JGh2uc59t3TtJRgZfSucYJ/SEC9NELmjp52eG3ZzE1mxyyC
XMXmSjLIpItY61fNGpVna45BPdqSYaQyTQCl6/4MRL3eKl6PkAk4l4sMx3giU7hgiYNTTIoTpoPu
hg8ldNtzgdKoR+52rvtD4al2+GLb1qlJnQVQamiXQll2GIFmfvnw5dAy5bSLe79dqj7xD9bTTvQi
gySztxfH6d+EybBz9pDqBQsVdiw7L9VeFixUyDHo4HxZ/G//6xgemYDm61ds9dE5IyTiKb5jDlgz
cUTv/6bFy4vqWjfTdXlLl9uHPcClLbndmW9X8ATROT896VcysBeRzhhFM6peq/uCp/X23mA5bIqG
2GWRKYFCQuJ+ln9koY5JORxgzgqaJDz44arV+vUDQOXT1mKejfmLfTusR93vCaevIr74XUzEuNRp
RCyUMngPspiIxhDi55x8PPbzUIsXDuUJZYA1tdsHCqMtW3ySsnxWsO8Z3tT/PKa+hmJN36eJf/7P
cV3KQyx/JOwpH1J2HtSVHU0pK6ytqSrJIUjXYuqqWAx+FVoE7e2ffODmyNzEyAgQTmtIXch60cIZ
y55R4JcJtRRwEUQDZTdcwBuJIEQAhX8uo7lok+LA4GVA4p2V7qPNHXXy9xNzwP5Ey8U2nzKlBAoY
8yKWgcgZcS/jdflrFqVSPdLQvLAH7Q/fgzWneZzvASmsRzjx0vfzKYT6Cr02QiQPuMpJuhX4vH5E
eFr2uAJLd0U7SZP5YMTrxKhtXW/NIAX8Vezr7GNwJQ8x5CJ4kjLd0EIZ368sm1vPyS5+WFAF0Tzm
PvxplZRU8ZD4vXdQUuiAk0+aCz6dnlIwFYgwHexnAfkkp56LXZG8fp0pKIDaPLTjDHt5oCqChl3P
BKSJiMKbUpbpXsStY7dnyBWwzMBHJAjovB2hXFi/1zykK+RWcrOqdKSPHiltGey+BaaI8v+co47Y
5yLUQtg1KUguWJx2MGR5Cuvg/SMl1dawXji6hNWnyASu/hA+JC1GSu3LnFi0xOsOMvqAqxgq3hOJ
H/4LWc96WEpqYVX90ZY4j1f7vbnt8kRLh0jffcMAltde4dFuL0at/qT5IrMzZV3IDf3Xw1WLNgG7
p1w+EEXUrVsba99FK2cmcjHQS7FW85uN2WMOror4IFDi1jfNf+dzIvj4wwhjeBhj+n3BIWZNnndn
itJ4SWY3rcfMKNayCKt1YnNwcbyjVQR6Wol2EarG6/HFNrRPoP1P4nOp0rbKx5lcVuxenWpw5Zw3
sD5vAPSdyYxjUit5Wc1FZhE0Im9Tifr4MUU3t4Eo1Zd6A9UDkh/93l5go1rgGHBChNEGnqC7uJWf
e8sNjJONDOzpUggIi9G5PYHY4a4rDlynp4g1CWRnsXyJn/Bv+FSbdD6ld4lJjrEnWyehDGupYCu0
iXQGMoIvjRECj9+oJoh5iVDlbz0HSsLyA+KDLOsWbL+MzspTyyjMA9kM+IsYGo6JU5EM9kA7ihCn
IewWuipVF0MAeOPnznWpUKdXREMP+WC8yL6D3dvJQRuPdrxVFumaE244haHyBOk7DtmKIPAR6d6M
aACg5WY51/09OQocQotPe6sjNMSRjlXJ3WS7bkiNAzBo9n8YW7+znJheXLYZXjGPeYru3AZzzPN4
MQr2gs4PFli5/PIw8dUKi5WHOTyIzpJ6c9hS6MASEv/7YDZHZ/MXf8yTWtgUG88RYdiRj2+wYqPx
1KmDO0lRRrPhuHVJq3lbuAr7IWrg8wZKoM0mDJhKdRSNpWSXovYmCFq15fN2sNUlD1TKXqi7L8bW
RXs6Yhc/FGNS2nhVWN+9s6QAtlkNLKBayYNq8pKBLcqy/xTPUgAW/y9j81u2rrskbmDNSve7obSX
v24/dZIR14CtaqMq0Awk7bKgD0xIAbw0VGIMKU8GoPxtfFCt+WNKgIQzCM2WGkUx9Y1jGQZvojWB
ZmdZb5XtSx7QtNfL80AfSWDB3tNjwdMlk1yLjPjufyFPKahVNzurwr1KS21kyKHX5dNdu2G8+u+e
XyS4B9Z9QfIc42AigQ6Ss+Q4+caeXBewqgF4qNdkajcqGIX4xPgMEh3oSl7cwTM65wVxlmauQXa4
kfzntxUICPOluTOWAD/5SlISUJMRFiBvvrYEUwoXtSM7iWAJza5n8cyHACGsFcQwhCHIUW9U7W6/
sY4hL1I7rlJk1aw5VnX6ZXXPTXd3VdJpHitN1nx+Br/YzIMNqgaoVmVMdd7rHw57Fy2ahJ3WKqPH
zWkrUCHK9+yJMa0c/aZeUF+AlWckFub2M7SIXOQPbPGgQ1CDEiJScyKBLUtnEi7F1YTg/Xf81iCa
znkU9zybyutUf8g70Tj5metgB6Ew0wHRRP4IiqoNy8LSMqu2FblJXCrh5R4pREmEYynXT4VWvlnF
sRsKrzqXTlviTJhS37AGh9vSyZ6Rhc8X++cFplNhOGpnoT2P7Ene4jri5Y7JPzV6e740y+diEvrA
Xq24XpHWcZP+P495oSn/wWv8VcN5wPhVnxra91On0+zkm+fgFk1hytegGhUbZbYiGIkiKc80EwUq
odsptxQ04+KPkr4TC4VgRUpZhpPWcdqmrBC0+d95vKNxkDksjPMhQJHwDkPeTkz6SUPKCbRxCowi
+KB7NywlcDsZzrILL3QtY5su4wGgbzEZwYy2d+uhMrelHlIlJ8QgxknR8m+HF7sKLBCRkMdJ5iBp
sIPlYsNxnukU4J7gL+JAFVhaUoL5VH07v1J1bXJeYBSUr/k1QDjil7i25bYjya6dNSUYXv4lmbJo
hWa8k4tEuNJrUEEwFfm9Z0lRYWIBjKVCE8104eGL8QfRUEDEgskJO7gUM8O9b8qxSm/buLKMCB3t
HFSqL9qyH95Fe+XJrQ/A+e22ZSry2wVurvIk8PURLujyL5dlqVc3Yz3XEXbA+Lswb7GYJmG6kyRX
t6y7wqbwgT5udPJVclff8dJAWenT7b6lhsOhP1H2Vn9E+e7WZJOS4nVMLbSpdQC+tDeA3YldYZO+
PYZB6Kup9Fi/ZqPvIzvMIE9fOa1S8MrezvCBpHTIJ132sp7eIpMPV2ZmrbR2E/LyCCqqN/q6Qw/7
aY7iHS6/0BMUPiG1cgUNdFW3/1yYt4AglY82p23NQAnp/fK0445mgscdoGrlP9uhCl+ySac3abxO
4t9FP5VsNgxDKRl3nrP+xJix/TRYoBKbZn7QlzGciontz/KpLxOOA1f1Q0PNDorJs3qNULTJZur+
yRYP/eJgZ+6dSmn3hLEbteEyqtz/J1APXulb6dPnZkrXFgWWNO6YS7Ymgt7i7ZgeH9X2hkJ4oJRm
Vi9ufWbv6URBSL2AU/yxgF1TEX6Xg18SHfJ6sgL8IESTxPeHdpOullu3VR9hD0GU+Z8JC+/VzF+m
zrAKksP4+sOVuQ1IwEP7D1Ea7SS7X/npKbi18jQxf8oI7IaIVZoTSnpnvpr4ob/WtopMEw5LqSuh
JRmoiJN43haR0NTKmbWJ+6Jd9n0WuLD/9+oEdv1CsTG8uNWbXySqMFTHZajVsvtSF6eHj2IVNaeL
/sF5g3KqHuouZUUoWPdz+uauoAMsnGVS+h0HhcydSyVMA4qGIPIzq+uWiCGMenJICPn6hhNcYPB+
Q89ocDpFWv9XGzDaY0FEUZpAfGEsw3SetnB0QHUeS2DcNNhUOqvJ8n6FpQB6cKFl6H4x7SLMr+gN
LNmkQJq2PlqJqUzT7mOvGz9xgCTUXFCZebSYQYPL4zhUN1hDC9udwRJ7yx60fU+Bir9he6SJELt4
IjXvqDT6NOCQ8uxuXGKrNh6OwLj/WgqcBrbk2J3hshWjnTKSX3x72k78wtO+34wEgKMvbl7aZYLR
Dubc57phc0eR+MpDSzdZ/txH9Yd6isSkFpA5+ySBCHqW6WgPsFYb8OuJM2f3cpRl0ldOAwwlEP+w
YHs5IFAAbczkXvdhATWpgL4wbEETPGMuqwTck33Eluc0Rv7rhPU9oWnjRfCXO75PqOtx0rnmRcpw
4vYKWhWqnV2jyd6wtlfla7bFRPceuoYOS1VasOQcxFI/Tf+IVZW3Aqi1wdAV3BqZjNAwvfqkyOe8
fFLCNWcoxcKS29bwPROruFnIRNbDpgNTlfyzEkPdgrA4hhODCZf2nQcWioe+sdwDliwY+q0H6nZF
lQdZQKEANBzRUMqFgHFh7sa4cofa6gh5gFq4qqcXAxTpS1oMfBKvETkf+RaTqCwaJcznSmgHcMad
atz23sQOpgYPtFRT3m/az/7B8gUcke8jEXLW4qNjeYYVxL2ycbxPmxFxRHC3WTwClxCVxObrVMx6
OciZCz+ioDLPZz0M7Whf9AwUyy2Hn6hpiADHwLjarWLiGDDzDGMl8XNJuTW/V/onTKiL5XPbzmx/
rwgefNK4f0ddEWI89vXKV8PhU5YqKD+ILJFeJvmI1OydUwFAfB75EzqknTep0GU5+uBAzbcZxiFM
kAiNCXqhbO8KdM2pHMBjqJAlsFcAcm0v2wXxNhbUOWjV2Iz25E2u5ctXM0S3EISjuPNlyMzjPNXJ
eqKzfJ/V7GGECxBvWOUj1xYNuxPLdLftyFh3kHeEzvyxqF1lvWBAOpJIMY/lFD6D9xoDUDaDxk04
89/7AfqtdPrEP8v7uEplSGUXqtZ9BKPM1u42QxtbQmIa97OInze9S2M23HWX+BT0XWp4x6qdhOaz
aEzwjSIZhnQCn8LFRe3STZ2pM3FquXdBzOZtJq5TsuKXnjbcUDtIL7ramDORt0LMkjXvpdIidmsV
1HMB1Tyr5wmMRJmJRedDmCg6S9r4i+8URBIFjRm+5EJmMP4KaJZxndZDbkPaFu6NgvOnv8EMMpU5
nwA48AIq+TJTYnmJYCBS1PmqjksEXlLo3hKZKUp5SKwAiKCFHNJaYVGda9CUYBjXe4Yzl6ZaSTuN
Y68MluUr2OCX9SYmKL5M3ZzKwxwm6tl30mQpGBYDdtMQNVQACJPxbmXdzh4lJuGhAPR5UkHizLlh
YhxWrjh3o/+7DsllUx6R4FCXX1p8APbil2AMeCUQUF6FJyLubwwY78ArL9INSEG6BmYlHDrR9+qG
p/aeBWBOC3dfQCyKtBbtPYueKlZlgUZwPPvVwL3w7cT58PvFKKGbyrhkkZF7+59mcskU/N7bAEzP
EuKKJwmWTkm6vfMqQtEOlnCSZ0HdyVhTJ9IENDkegvJTn0YE/S+NDZPnvnYOlpRUoJfpgYS6/Hjz
k/v3F2d7BH42+2XFC+VPKuGV4jdIgFR1gxju/N9LUYRGB7NdDTCDlxmzfdwrALuSRgiqRgr/CGUe
OWqJZzNdQ2a+jOxtmdH7IKHT99x7Qllg/zBf//CfV3g1lJfPgyfNbwKqbKO3xvgyTumuZjnWwsM8
7ZxJuK6WEw1Z2Pul50qB7kM220caYaY75zh37jPrLDcdm/WnYKl9oTLaGIypgpNJp+gxODKFOZXz
GjxJ6vVtDTvI4hCT9ecR+ChaUIMiv+MzHfR0DYLcsL/QnU/T0a5fV2kvTyhX5UpAEB1Xs7sU9prY
bSh+eQEutxEnLXLwNJoW2jcusL3576h/5rZO4L2LRlUE7r40t9qpCEz9S7ABHV5wzFahEAUyVw0f
GO4LTbDzMG8tmkYY0/3kGQbxPCWeQgG5DtyRBZzn3CARxWDuHmp08Ms5UUd9G1xoTSSmlMIr529v
Ap7aihy2ZiowVaPD/eJSHmq+fP6QnMYXil0uW7frqcVLIw4vkuUbjyaurmlpz80tpITq7DnXm79p
JN3uN/Bdg/SDWSLNk07nf9/oRaE6Ainbd4ynRn17LTsJsf8vQfI5sjO32uLxsgLCaFu94WfA0Tsw
2bndsGbZlOssQaFUvRmjaO5D2Q3s3P3Xtc0qQMlIr76+SL5j/dac67NE7f5Fto8qR2MUc3hvFYNv
+qfffHWL2PolILkx6JcXPw327LnOq/W4xFI+Tg2gy6JL3ZiARQ2gblEqr+vTMZdNAYI0mKmrsTOW
+XWph+Yjs3vLvf9GDttIJeB3iFo+ro63PLT6wTSxeO5Nfq3FcUxCdkYj34Ckd4C3jDxvw/Q/yhr9
881WiMgZRSRr7GhCdPixFVNRe54sNQz5zVNixPLA6ywj+iBuZSFwiYcR+D/lJ7RtHbVxqBHOrInV
1cvFTCWwur42ReWvBIn7JqlNG4uN3Zz1pPGxVOBQTaAwDlcXWq9QiB9MwO0SA1xBu5YxheFVzkCr
Pc/1J092Aw8DWTyx1814WOqVoGCOAvwm46GDvOtRgr7HCgt8qm/fE7W8lAcyJ+PeTmw2aq+CYo45
oeok3LDwnA5uH/kyRlFs1C4KjPHKss2fFnEvnOYsc8pi61B68Fk5ba2VZAcJBjXmjcFPaMHrl56X
s7d3Vf9HywFYTtk5Opprw5TH0tNJkpn5rAC33uWwCrFoWfgME5eiE0yVn4TMnuRjZOdLd6uk9sLM
YlXshiYiSKeZluM5e17BB4By1IAVdsiRRgEIjHPkGUBGugkB9De/kowffupUyCBK+wsL7YtN+Nb2
9hVaHeYnf7K2D7tp+z/TY2lMkcMJpP0jZr17x7/Pde1/5Rij0OFla8n6/vIr0PhXoip4JRZGuJT3
jzp7HhpTr3Ci4+TeR25sZsutOpPRtH/hNuUtIEHd027/3/olN+TbmCarOvG/fP4MDdE0uxXIXtMG
7ZcAW5wDEk8or/5zMEVyCJH+hOr0+LvoexFz/QSc8fbtPoqnv/wokyG4D1BXN+5gQi/CeWOh/HnJ
1AVcgAazv5LnUPesTJ42InxiYGU5xoWBebsTl1CMhUjTEikQfmt+MOGyWmQotLBGlXtPjHGiehD5
rQqvAhrnaRbsQesHeeLzAzwLdFgkkDLvuWAAa7AGHlvbtHUfgXCefydLlgtM7YPiRU6zKocicu+V
dbtiGHNm/fCHusjXWgLskMn6zIYCK48qo714YUVESNp6ono8mIt1GlCTrWGTQQj1e8q8SW/LVhEA
3rt5d/Fhws9WWZi5ej9mguxj3GzkZZOLTqN4UGRLwv/DzjSMwgbSOMOhZ6KkOQsvNrgZtNa/dpp3
+VjH8K0cME5+SXU8dR2xmj6WVwvWR/yxIGXbEmFLObrzM8tUtD8swQpD40rjcQXHkvagrrif8Pa9
6d8ARVUkGVWQWJrmhvc4WJHCZX79IG9vtVpHQ0UE8mLuo0QbNsLn0gcT6UE9Vl/VB6tRPk7cv4p4
ql/F09JGZ74sUM2Gp1xAV1XPotDEmFcbqrZIZxbFRRjtC10tW4YlxWDuM2XZ96dTacRFJLzcPqho
lf1ZlMdyHMe6Y09LOLJC9EGxoWCqZyq2Vd3gZRUSskh2r2/YU2UOBHThxcAajXzoFXB+iTi9zWjy
Bo61TXzd/o/R3bkel6jYNlUmKEsgNwnZu80LN8/GYaGEKbMDlpZ0IlaJVVHWsZHzI9kwhoAKd88T
Vw0R19Jw1LHdVaKs/OPLJ2UPmroWKiwcCTFoYXLeAiJ4tDvRCqfrZXkNdMRJ8iwOKbv8EwVyB7RQ
g0YsZ07uq7smtVxjL0OO4xvLQdig2WZWFKqJ3tjTCaMBGIjeEzzTQHj8Mp6DuHNBTlsHHBoy9/Q9
sxWDVcX7cfWAHEhMPJwUiihTkeBpY423PhVyQU09kvlyWjOJhrE52QdQ7JBu1PWEVNAJZmE0IuFy
dCI+EJcR3WT7MoCtKv7rPModFTOo38pybx7xgx9QoreYEOfhFCR7bfef/UxDLcKELHsvfNhScysh
hZogtBA1i4jNGyCwezM6Y/MURZb8rMRokeCzalGfCBeBluw1ox4VGfleRgmrtAKh4PzJ2+z5eq59
9dDCzWl6G1bljg8x17aYvJfZ8rOMHo5irQOyA8ZeouyTKw5yiYXv7VQNOGumEijwc7dNPaXVx1uM
zT7iXinqzBm5Fua7Sy+kpmqhxLNImdaiakuWi0y9i/3YlfQkPy71MZuMoxW77bQrYeWaLNZU+w5w
ot2/MlHo5rOP5rn8EXbNh54qFgROs1L37AsAmZ+nrp2BaJHfvx/PExwzcIIiYbiNo4OwaXYjYFaZ
0kFHA67zB+jro0pegW0ecSXky2e9ahKa5nPXjIQxWzSWibcuIKPaRl0ccdOI6opR9TBDPf7YaVSi
o2ubAS3yxHcjDsud85jQQTKj4fugNzzvDnaZ0GziJlVRZkmb37Q8PtAbnQEmA6ei402H3sQzdtdQ
w2GyFvfHIh9A8GPJ1L/4woXfcxVopNLFldYYLHggnVccy4AKfwF8xD2RfjCS8IyOFeIANWJxiiHI
H3xqsuMpXE4fkSjKSDPb7/jvbnR4CjxgC5IQDBnOqZ44Cc0nQuhDYrU7orMK2RlrtqlZv1+QuAln
JH6aI2IJKSpv0i6BvfcyTwsuCeW30pGn4inGeWiqKMJ6wUJaSkFNGPHljGXsquQMLOeeowRgOSxH
Qo3lGNDUzK3inY0eOTELTg4O3qTUphvjpUpRipwXcb18oOjN5a3ZSvuFaFtM3TIqPmYfbbNNXOVG
dqqwuaimCR6jeL/Ih9nxNuM3Cw+T18r+VcsXSGNOHW/xdor1CoWeOmXsjvtAt/XVQlgoFmlE6VWt
SUWa5quiavCkWPjQiv9guShqq1IB0Wla325++o8RZMjCkhmVUnDbn/WZ1WSD3I0+3VUPKTEWYMSd
2VJD4lbETc4Kpifga4h/dhJfrk9OCxX8jqImbFfXycK+1OwqSMqvbGR6LRqsCydCX4iVCUblhr7b
NG9Omww9Dtpf9FPeAu/Q7VriI1j35uzkTZ+wTT+T1ea/S6+TU6C97WxE75iii283qHhzuObPlgA9
b42QNTP4qr5D1lZxGN7/UrSiTioHyyD+UfU3TzhS2Li1xRlyN6D8/3eMCefWPMP/CdBue9lQi2o5
a2mI+uiNwVKXRf5T2I2Qm88YHCL1EFB68btpTVSCT8h1mSfMJvtp3UENrTZQbb+qaHaN6wjuDR4+
4cAXj1ZntjI2Wcx1xwx/PYbe/JzD3rg7mUI47BYD+G45xBgPVqI9B0qipGNVjQRSjHgnMhfGhz62
YP5kLXjwXHRNOITeQAfvLXwO/ZESfbgJvlAPwFWR3e+1Vrd5LIQQFXX6hU08a/9BxHf4qPPO0yxr
VH/Rp6BeLcJ00TJa7XcTbdB6qLXzGGPAjMRmzZfYkXRgeeLoUxdK33kWD7oFeNIuprgUT0j1pRfV
j//zDZOxJ4kcQ96KE6O0GCGPfTtDYuZ9amSvPbALsgLss55h8/WqOvJ0biYQeSg6Ea45fkTbTGWI
SzWX2jMJNCaDc3RoaTb4LzqCA7KsqraeeWQWtqoKvgp0uLiKXWVngjyK/jplX7hpjy8h2g2pT7pY
2zLexf2qtU6WOJZ/MTBwMqTYGj6YszH0O9zV9gtXjXochwHADhzHfMHWJEkNj/8tUhjYiZOtALoi
4dkaMlLB3iidxY0tPZML6rr4Py2b95EhyweGlY0Qp9S91TvdJLbCJ64PHyh0LYcCcjTLpZzcH42x
oAA2f2k2FM0YQcLFva7m0+RS9MsmeKzSJ/XF+HKOX2Zdhq5Yu6ToKIS2zlTVM0y3W64QllLBlU8m
BLcNj3e13SmTuRO14MRYV532gLXfainTDIv5jUFiS/ayUDk1DHXU26fO7B1PqT+fdjKEfnQK3VJe
vkRQHUldPiZ495djzmWXAnWtJXJ87uiAIt4GOMilwpGMFifh80gBDJzBUy4NzV9g1NRuR8JXgAj0
yWmDKzj5KGBTNFxfhTmEt+3rDlY+Tz9sA4cgH5CEESLeVyEkYvbspl4B4i0H8kG7MtlJWj5ubVQs
nE/lYu1oZnK5DmSk1AkEEIrEZN+7KDM6VcO/qM1Xis4h5Dp5OBtWiZ23fcfqr7VKIVWPqMyATPx6
0RgkxyHBzBLyHdtCruGuqcvS3iKLAWtEvHnADVWOYrtCUwNqcI3qR8JMhxTfRKwY/VYEd3MDMNO+
VNRyrjyaoL7NKIrT4zdica+oWMR9+2+m0Tz7uZAyZFwzQPve0j7jxzMfxRKrq1C5jAD8tSAL7ntm
sCBjtgLczoBsHzIJPjQocC2xK1FRo9d5wKJkwC/Z5qLlYE8QngTDcyuTJNFstisqTsIjfWQ3ytb8
Ne3BPm0R26syKP7/sdIlovrzo2h7D2ZNjPFEF6bXJCCld0UaTSo0lvb9vogOEPS1f9317sSkyCya
lfmkTmy9bPvGyFz9MmZTJAZg81DmGN97tNm7djM5f/+jmbvJRUwlRuWL5cQJq5BQ0JG1R7CrazuD
jvjXsZMLQLdjsytrh9U+tdVufB7M6PxXZTeoBse9eYCqThLTmGdUBrf+XAQf5BqcnVp849UWejYL
LcN8+ymzBwOXBVPRzmX+mE2Rf/bEpaZUr7PvM2M3xp9bcTTnEin3eBYpHFGSZs65aYOVMbMYa47d
J134N7AA9BDlgW+6AMmAGo4CmjjC3TGfME10R5BR1bP/CSNQCIyZZ0znjBqC8+6e5gMffqChBpA/
vzQWE0PpDlACcedOV2TOtLmiASUpuS9+ozgBDBIsu1UV9MiVtj/FV9xGbbqTm2Gc/saPEoIDpLab
td0iI+41PtHRRJWxUs1UrHsu8DLRgh0Ar/xDf9CT9Qe5T6asARTSVlXjg5rF8FiZhbvuBxzF17ES
RVA3oE5Ut3SSL8mTu5/hQGNgM3Y8i1OxxSvjB8ndQScyeXqU1s6RnJshcZSoMig15DA5tHuR9NsM
rFqY82KnGuf1OWVAtHVLlSuuG3edm5/CVb2b1G5fYbFTBjVUqvXnEqjjipu58u7U/g+g3bjyl0s1
4fGS1X5IbjbR1UvG75OtMC6vWCSxEEK3SPFSGu8Kexl/DS1Rk47J3+jeiT6jxVNcalU0BN75ycAX
xRqBp+xrtREgYXMwuEY5r1reHCo5BkZxjDAoCJ1wfQf9nQGZfT6dXK7ERf8X4nWBwbcwhGJ9A2WG
+FFf8RWy3/uvqSTBqrKU9Xqu+GG3GmFkOT52IxrTu/tsFk1d7ZFHXJgCpEVOhkDRuFLfMHaJ8TiK
QKWZVOgd9Q3YBWjuduCXB80+ENhpNpV4z5fJzL08BARLegJAOXTjPu6aDTVmuEWA9uWfYudK6Ktc
0GN2qoa5+rg48gWpRhpjWEkMwjAjzR801nTwFn0WLlV+pi0dLds54keaOKT/Bt7TM2c7UsHHZlhX
Wz5duOQ+XoPeU2knKcnvfVHDb8itDjb2cBD3FrRnJoKAKm+jvM5BtaOH3g9ijly4WyQSkfxYltST
ACDd7AQ/K4ZvCwtdqT+ahW7dCHtt+s8kgjbZE+oxQxr+RIDNwAJMyYY1ezwG7uiUM/SIXbGG/u37
ACOoJgYcQELMuhiJyEJ/TL45u58Oe2L2iXSUkmre2SLR5fwE7I92Rhxaip3x1SK4CBwQIxofCrFy
mE+ZEJvFSJBMp2mln0KngrjmC5RckBd8bqvXYm09zzJcfj/y7S0WxqX1VQv/elftxU/YN35KZFsN
3ZMYZLIN8KTFAXBcXio9lGt/2eo1EcFgJljiV2rb03yqC0p0dyWyCHZiSnGOUQdXhF4ESNDYIkDJ
eAAgo0NvYyxEK5UOoSZ5kU0Y+ALe9c6Q+dYLwMWksir/jc2EiiZ/5+LyzfHJ8UOSSsxZ25haMBGJ
HOCCTGKspn/8SiWrUHiTZf01vYMunObNULln1Hh7UEqDLsnRFOM6/aNaWyHZRfe4Y4i7iJwQjmso
nk8a+V93Ndi1zvINU8IV5zgXCnGap93HOdSpTjdinASTAasFqxtJ06EfVA1OsIagXDijxnDUQwQ6
uwbK/+RbwS9H/gT5gRq9I+csMdhIzNIj5Nr364x626+BUyH7fin6RzRB9X/sxtFbUHk2EmJwKb/f
85eESdV0HQ7p4g5ErE9JuX0XIeVXNI9RNkdhkHd99W7z9paXDdJGnzTK7t1Bk1iC8wrG6AVvnLUQ
vMerqgQ/SpCnbUzbC4G29zSf3L2gmwtRFc//+De1r6jYmbfMVotaoLgzGTI4x2QHv2s+Xnx5/hFB
tCGb30CW+hOxdZxwUDVSs2REZ1tg0VhYCMJkNHPuXVoZZUUnpWurV5DpWpoUWBJHG44jOatYR6d7
r99GtAB9dZq/GLUY/B7lM+7ctdOKJtA5JEJwtSGhvq9xvnkZMm1T8bhAiXbBglpJIZOr7cc8zrQ7
DrjpgJeEfoCyV0Pent5Yca+Hs++PfbkiDDObhE9HBY2V7sJ6mIRwooNh2Xlg+SRA3wyPkH1aoK9A
MIxA+86IOhv5Xw0YCNufwRn5f12MBk2NkFeRVj7C9Vrx/MkBDmmIi7p/R6QIVPLs61678eTGT+EW
grlK7CS2ugSEmPDtxoagFFBZWogDPAJYcfmM8Syrs+BcTC5BcT1LQ7yeNdhNNOOT+oQ7hSHYYc0E
80VQxDP5pl07J7C8k+fBL6SF4CHJVaIOMYq6L8OzOhAqptZ58t+zeP1XnC5NDx5Mds79HoThcaeR
oDREHk19TcKIF9VZHHuD3YQ6Mi73HjpEhErDtxUgx7qZhmeEhCCmHYUWiqiyShjCpDEFndeIgbHI
p6esl2dPSkiTlQRoAgkLR+CEllnrtpmw//SfSUUqezbJWHNrjatyqnT41OgudDqMocO0tjObe+EP
3JbP1p462c1+28Efm8cbkyb+tsV/LuZwztQSQnYJt6MuCRpG//hKFpvEQEtx3X6QgqIB708XlTmH
S6CWb/hcpdK1d+FZRwKrgelIOW5TJei/pfvgoVwG2VH1lQGwLMNPCxNKfHmYqpcZ/FjeHOl1HFbM
FVBosgMdq3be2ePUvajyphtPCy1a99Ic5LLR7lSptwkyogJLiaLjuGjNMJB5XGCv1ZAOz9eecA+C
b9kOH/50tO0G1H6YGJEuEb4Y5oTbodcLhPG2znwUq9f1c1L0nYu2o7mqWA/GH2QsLBNxmuNpxhTr
pQAariPCtLyXZh/o4+mYcKuRPyieRVYbEAyuhqzpbokulng9dwveXY0Y5SlhfpG4aMho4DSBTGZt
WeLNrwawcfYCgrJ8THBiStXbO1lAOKV72Ae2v190pKxb9fRJugTAO83TYOGbqodsctGGEoj74551
j8DN0YCr2o1YP4+gvm2iMmx7vYLyYfXzAE+01V4mg65mXaFlJ8pIU7zFNYIcFm6KpzsNxJRZlOlT
hyH5PMI/pboWF5taJP0OYPWqPPHimbcdBlanxHBsSS/a8kmZzh2TxD3QeEJt7ZgN/LIx3kqOjInP
EFU+Xt8nz7eZl5Lcnzg1zqgR/5UMEmeHws0g8oGa4Yu0J0+Hie9nH44RJ2H5HWbF5Q42G184o6oP
mrLWBjoUK4mB4jT27ckGLX6lrKuZPZUB9VdouVan9AK/0HA3no0ZiDgVrig804zC6K+gwZFA7RC+
RD7OVLmCyvCdCriMkSEYFmIfQbERApxGM2cvTVOjjW/CRAbtRwbwctLmiY83OYs8QiFqfwbz18b/
5xbeosl1DQd/W+S1krDAKTUxEfObj2UyzRFacn8ORHyNoy03CtJ/P5DlmrmMemLeXr69iCnZmQqu
wW+veIeA4C5W/3I3pYDxjOA9rFuLlxpXFY6C+dYjdY1uNfQaSKlGwBP+U9jwVNAHv4SZ37zg1iZt
v6DqhXSxKNcJRMFgr7tIBgfwaX157QGmyndr/c2VomWTMy0wSQLMy8u5E/lpKXd1JyjX8XAHBP3V
dPbi+v4Sc3WYc7UOgK2c4+8D6R6pLYFrKUWKyOR8pqOpHlSGPGBVRloPaoTiDa0ZGnXgl5b3dP1r
/vjutew96TsfWxo+5O72lYuMY8DTeAtXMBKyKAS2O1oclBJ9MOBS1ZQU5UUtyzPocr8e3dXOe2pl
EYEDDYSU3Z5hpo7M+kfZCWTypXhc6oNKO3ZqqZ2g8WoH1VF55g8VhpaYhd6tYXB+wZO3UMuY2WaK
xNhViDBaI9D1N5CAtMy2zxLQili2/VCDwd8lIr6UIAkhMia/XNCGS9iV75MK4SK+4w3I/huFp+HG
ZkHz3sLI62LvVPaX0YWggLoGCesgKXfCwegkFij2oUy36fRyF8hVPO84uLrKv+9KLb30Rj3p6oi8
oQY68BN9MG34YiHWmPHCGq2vkd7Z4TCUdRzEgTKL6RTzHfiMZ1tl2qvTWIbRSf8cR+k4FHAezr0s
wrkxQMzWLE80boIOOzDlvujI1eYtDHrqcAhA8tylmQJdyYm2QaHtaaYc2oPajErBxxGA2SF9zMmF
GnRqlreZMAYn01R7dI9EZt9uNK2TI6zvhNwF83J6KykLg9FM6qotRrXP1p3G/9yBJ/SHFBzLEJLN
NvNezDBbOmNcRUWLwE6Jp/esnyi2HFwiins8K7gZN/X9cNcDXkivYX4doUpgpQJMaFt/ZTkks2GI
h5yjHtOXv9XSUZ+OKAmpcR7NsymYW/LMOVhCEsxN0XjO3rr2rpvU6UrXABP2gGkOV2rmT24RUlnC
vEUyj9QyOVg4jFAXgxVLQP/ofJ+6Xc/6EVKCnGjW9ANJr5EUcGL8pDg5RQeYsoPOFmFfLYdjuVxb
cNIsurvHqLw2rKyYDNz5NGIcvGI/txtgEURG8XZLYZtaLitD99q5MsyAeY7P5MbKB6kYEtcQph1X
3GhsNOTicAtLqPf0DdqJ+6+mHPI8ge2m/Cw/rbdgaW1wFuquyXIAb/5Q7tWCREzF+2SIF6ayOqka
LmMsp8y3n4lshUyZoG1S5OzkoAUWpk8O7Bk8D6G04r8ByAY9gnTizRllUwdBNcfP625gCrfvS3bS
YQ/Zy7xVAv5t2ZZReLDgc+KfyNCErFFRYl3mw3yI0oOO7Hgn6UYC52b1zWEovB2f/3atrCmPgNAN
W0eQEziQFDX1J/rGJqvV8AJXwwB97EbwBaNCYha54B1PJFg9h9LeV1F29+JqEbtNQL1Dp7p0bDHT
e3iVhXmKXF0BA89Gx5kG/vwx5YqOobNqNY08GtkBhvwXpasgPPARlf7YjWLqCnj8wjGChP20LKuE
zqP8kbBMEs8Qeppb6j2nLQx17d4zgG+OZLPfEvpfi/+0HGThrxELv9SHQ1wm5A9tbd05K2bBU4cM
Pjs+ncIJKnhpsbLAazst890ANuAWNEIVXVCQlFDb3j+8iiPc4E0EeQ8rjLWFkDsjfSRLhiszBFsP
qjZLTWrntQ6A76rQmqYVMtbKhiguSjpTbTWnJoe/AY7KZIXcIz2+fHdnYIkb0jLmw/0Pkxzw19Yw
Q5XoNfxyxq38BMDYXqq0me0ASAPjlIA/XeLGBEobqotxCVh0tCcGPzHdFS1r2yFcR+Dpj1taC6oS
PykfTzYdAyuKq8PALJL1nKT1VpDMr0vTlnmu8ySNzEblOqbCYOQj+iewAn2lykrI72UbTklhDg4P
OEC8Wi5CBN8MYXg/y3yr478NeD67uDB06MQW8/sTHeV8l+vvt8giDcrULORiYxCjGwFPRir/44ia
I/4FRwzZHzrwmCzkgsuQveX9s/GECsDVe7IjOLiucxJprxquaDnYKy/nOE7hY9SR4bMD+RqrKjVi
1CIJ4o2B7Gp6fMJ3mAQopEImNBvfqWqIgrYyFJXILf302Lbrov4IcuxW/Lltz81zCrDZ6CHeN4Z2
BnZU59aHW3fzLHWt2f633dzYx8/0KBaNASbUhAHY4azRR9rVK4bNNOiJHCWXLF3m+Pp1toTeZ+SL
mNMaWVqQIecK3hMdZ6EXT+MMd+ec7ThHgfFiu/MwtJHUqPxqdU5N32ZfUq5xyqGHeTf9GoKmHOHp
V0cgrgCGsRlaAizFSD+XFvwYErvT3bXI4gqg17f/rgVAwJzXKxLkOSOrXGt9kAmMAFhUdwiI5w/9
p3FPEMr+C95eX+xeN6Ac1fvJ4kMPoSeCNTqSOQmOxGsS9cYTNFYAohrXoz+QqZtjHGE5AIjbp2qB
RoBjhJO+Hiyl3xl44HoK4M8suLVV8LinqCI1m9T5/8qCMJIO0R7Qq0tcMuLFb8QKUCXMAZNVpj3P
W9o83TZUtNaCnwcnS8TdrSOsSlNfQ3UI6anGufSnn/8wj+5ZhUfwMe/0bOvHG3M14U+8/X2G9Nhb
mkPAd36FhAvBxNq2+dSmbUfR1fhrY/VCQ1+TdI/51SM0LHkL/eo8NncBeZfZyCXBzwLXeyequJ0i
QYmI2xihm2A6yvcHKUGyoAhB9oRBGehSwMu3LEIcmJpNoz+J7tWfWG//VbKn0wDdFhL5t7OS0EOx
gNbU52LLRYJLdE6/GNS28DYStySWz/MrY4r5u4PPmW7nBBEujKItO+/vtdH1g0IP+Mfs38YIBS/1
6Vcd1LIUyLdh+kdtiK15hN6hXj1tX97OmgolUbrwyzFrZGTrzkeo6DCYY8zHsx/Svq1THhXgQmN3
rlF2XHDY4mezean1K4jwgrwHZiLbA7ihOCTJ3f6y6ZYSCreRilPHUL4SSD4SC8NMDMrFpAW/DEAk
gcKNIXC3T6kv6KE9eBghzhGsHWGOSWjPS7YzscO+3RD69zFgOBxmryh18HeHN0n2vprFMLV3MLVz
1LitCDhC2O7P92ei9R0g15R0jA9c/xV2RQe9kqT9mZmqyzOvOgeAwnsc+JA4EJsE9r5LRVHBSGj0
Gf8iOop8g31aXCWxP9sGo/+rAeQfSV3hjLBnvtemRUtdYT+R41AXUY+1D1MVttviWIh8U4TMaY49
YfPALtvhJWqk2Lb/1kC5WxrpvuQc3krKYwUUBKPrmXzrJxLDDwr4ADpeL53hqMKMui27QWivLvxq
oznJ4fzsFPvwFU682lTh5yO9508HBJmt0baAgaIv6X1RfH8KO2kPzSt5ncnM7Ucplk4SiSLepnRm
KQ4v7+VZfex1Aiz0xSv3SfFc5YTC3PCxqm4wEuzyOf++9wq2nAnKxno7l7nFlHZKJXtDNqI2tP9W
PF1vdUn9JeR1bOxEl2GLJaV4eZ74Y2WGjGAIgo+lHOFMVTyCZ/DcCI8Jk/PTTOTfc8qLxnRCqAPQ
5WQIukZGNZWMDMg6ICq3LOih/qIZ0FqCYrpp44LJ+O/1ybX7KbIM3benlk9zYyUebnizaX6aMbQM
glXW+8RPcAPSRs4a60GH+oJT+2Nrxf9aGCS5jqT+WTDfP8cKUSOZQKYC4QsBRZ8JnGORLhWQz5NJ
AJ4lq7Ui27PHUBDU0kJQ1NYn1Jmnblr+n13pFhj+LkX2803OFFs5/AQASNliv6i6VKZfTVVvCOGN
CacaN7N8QclYgjw0QgOusgdWNFU79GiPYWNU53qiUf0Q4bG1JtdF7GslA2C0DKGVyHfUBAU6E1Qb
9gcH+T4+4q2askiPidPauFEXrAE1LUc77d7HD5zeXjOa7976uwVJWobIq/HKCV3YbY3BoTovGx/Z
N+trKaQNdc6sWhUkvK244R+3FbgbA8onXKaPO9UHylQdD3qJ74x+14pUXIc9Eslb61tLoKOmxJ95
eNOOtpCv5RaK46UNT7rSUsP3ELBqBxWPVzndxe2adgJrdAkHpInQk1YRhE+y5LikIo+JftbpTSK3
+G/pBIGD/bwhYwPCyAPhkjcL8+DyJvrdQtXkadFuMLI87D+RLucoDwQyxNx20+M0OZsbhb1iHOOF
Jct9uYU9ecnu9Fodpgs+vzLu7svWc+j1Dp64SRmFBQfBt4QTKZMAgfPdl4Pa7Ikzxyslb4mMX8iK
hIxNexP6YJCkF1Jgz6edMmG7ZTATQu+5V6X6QHTbL0N4c2fyrf7TCthIXVlTFYSMnge7GHa2+DBS
gcq1w/ylg9KPHopRh7JFey9e4dpRv+eYTlpn+NItT0VGkRfrDRz8A2oSuUPgsI57/fkcGNVGCU4e
NOPycjYJpzRLLIBTPiX0QsiydNx8auuBp2BeMMjEuvxx++KjJpdTyvV4BMG8ml0Uq7I1CWHdr0OZ
yvOxJhYhpwchlOwZ8W2TFMPkqMtgLvYKGtznkAHIFedhd3NXeLSTTcfQ5eboXK0P5DKvMHdpXp71
JkGisinuDCM0AFvKTEaFjJs/Ya3grXGhAVu7myZiKU1IitGIqdWMw4r3pKFyvaDrMlpI4HzSCNwn
0l6EvA1i92cvLm/MawRvZNEN92gl/4dqotGeJefKOZzXWkaJbo9d/59yKckIbiJYD062y31Mkga0
M9lTL97Wq0uG0+ap7P1Dz+zmtL0KeqhiGS12qqKOeseK+DwI8KsrONZ9cUgS3LHPqJ/K05p+cVBO
TKSnnWDISkmX3RxJIX+tRNXuq+ifFtrCeBp5PVWgbtVbaKG53fXYqsdALZunV/kM5hb5tTdB2nzv
AT9HZ1w1zwkHbv/lgCW2mKuAfyyIbDue2jGQXO17KLVZHR2mu6ecbK3fiFPT2GVAcXzsw6D0kYcO
Uc5isYxfY73qsOL7Fx373TDPJNuhH4B+lNwzaxnJr2cPVbHiCCQ7pDqvuAUot7nh38Ke2JdySbE0
dLpfahHNaByNooe7kOgviYoj3K4bya658MAdma9rM88j7O41m1dG4/9iyMz9shCVZcmO5bLb3o3l
6YccsbTwGzZ9TpyhWu8Q4UvIDGWGr3KNSq2bz6sru31XQ/6TSYLccoD7Je99LKwaSs9p2p8A2Go8
pjqDk0f5uUnWBWTX4/W59zmxDNxjuztK1uhDRfIEAWoK+CRpkZkO3ldowSFS+quJ5UDmYONyohZe
PFlJymiUweLYYWe/W3iNmb2fNcxkqEfKgQoUEUwmO6wwHqRfO4hz5UsFxFDBZqc5YwbEtruU3zmp
OsRD5fzQo7MbmCxqPHaaIBln4P/HfE2u2rW5a+See5OrflF62WmEnXPfiF022Wo8YufsZPP2vkRA
VXVpT0ioQhvFpGYVbWSbaCoN70rWJ6rNF1PYk4FEUW0tP/SsaO8Ei/x3CGTepKXfT8o036PMzWWD
9amp9/KhywKu9Vil9ZmiYIQWG6/W6/9ILekvv3XZjsFRQui428kr3074zd2q+q+gBs5frcAgm2O+
xrh6MUY1+c5jqnbm1du7r87g4CtFCqGbZY0f3OPB6vOKnzXkuvPEQquy1q0rgGc9RTWsKbwoSLcz
9IvH+IOSs9SeMTAxgnxiLzXMthkjnvdVJtH8rrS3tbhmxwdkiDP+O/nc6na7MvzUizJZcHxQRe9A
dWDuq5MYTZ0L0rpdnJfXsJNCdGpQmKBJ7S8XBKsFYs7qPDCXDBDNebBD1K0SNS0nHZyPN9+Djlil
64Ql0yJDxWAqsMuFF3/S7gZhzrNzjj7wuSjkya4HDuc7MEYIXUjodS/So8A7GPMtpUA6Oh2V1Lto
jqGtg2LF4yqEyInp4NPHWmWMVpudIVuhi9GDyv3yQ586SYBODMM9r+HjkxZRw+Vw87k0+tOxIRJj
dLhVhw3+grsz+t1abwJaKXH9mF69oqFynvO8Cxml9WnwPDWokOvnuuUQpAvNEQgsdl5xbMw58EIU
PZjRKKlhrfaf599Vnuu7j0OCpcLdg5r5+UbxtDYhtOuo8sZLAg3h8HsiL0Y7O5bAOfIt8FTgUIpG
Jl2Zom091IlujDBQgHYykaa/UqxIPIATd9DfwyLglDSa5ZbfP2xcvrEXe8BejvWpEVmCWXmW4rvI
HiYhifZkPp8TYpPr8fpXjJu+VmkYsRsss3ldOWy7gPlwm8jXMAEqlwhcWWUQgRGTMHpDB59dVhCL
zC+/UXqv2iD4CWJH7SMv0S1NDZz8zyMBD6Y2bDSI9RM2FchWP+YIs+aan9IOTlhAbPYR6JKjoMYj
HqGaTDtbF6RVI2/8gfgdEo776euzF2NpVNOly8LAWJnAhhG9Qkex4x0byv+xkicfSBpSA946Msdn
PVdd5mfHxw7EZVP4QfFQVQ9SS5wf51LVtaQalv1scKTWmOZ7QnEIcFz+tUZ9dcOAwu2dzSPpQUVu
PVzIXoXL6FKjX3A+HtZZtaauUA+hBxOt+gblH77YITonj0dRqxnlAO96HVNXlMfnhyv/j3Wsohb6
OEf1tLV6KKkXmgNAd4Uy4qBoNqQ4PwPI7wYY9qoYFybmifclzpQRdF5r+3U8uIbQw+jFvCGB1glF
2c3i+lZm95Q3kHyGEUKhTk3YmQb4ygOu4cCtq8iedpOHB4WnjpGr8G/zhH5JZq4cV94Mu9B4TxFl
hJD1/uGm8K4uEIzXgL5N6pO54sl2Fu9iY+aencr6C2+AASTl7vF46aWp05S2WFLsG6Cu0AxU4ADa
23pDYknyxtxNnJ5vlUr4AzxGPdP653KH3LDqYlCC6ukFzj77ezEszdaI/x4ol27qBIxHt5s3m8W1
3v+DPauZJt8syjVtQt9KMZCgF3Bi+Es9YCd5FwC3z6z4gKsr5pa9fln1r1TMJBkSIKmloAx1rzWj
D5X7AeOMVY6nlU2uIOeTCwqr9yktskAS0azIJaKFW32w0AfFNOPch1cmRYeNAbyKkHzPwUQGYwXI
IuxLu7uArlBzPCbiVjvCh7JlNeBPDzja+Vi1MboVsUHbczyVCCt8zobs8GMF/4y8gGsWfx1aSKlP
BMSmO8xjG3Ue48Qv4mMUxfdLlj6m/jLIluQBB5KqAgNloDttLfA7BxtpEtK8x2vgi7WYzrZG6AvR
+maS6sCDouWcQsWpJgR6j67+9Td1xxLp52JLG96t/mQ5yi52qhYOPycyJNyJMRwTVxxkQPuy+b8F
bwWANVWanuX6tzoh47CiwqKKAOdXhwZNDrkkwGq7T+27Eq5byDg94dk4rVFM5AdkmLaTaQgtx4zW
+fHI06A2zK30pWIKndADWQvE+argCYYnCj4RwQ0Sb07UpkRw7WjGJ59h3gUdltVkiJ5ZxpamtjBH
0ykqBGCpZHV/Zre6WaK50FQExog7paYK4nVvTh3czSXfvhZDhAjvdQ+Otfz8Z7N/p+bard/ybE1K
7Pk4DKsbCLYrf2bVGCHsHumexTci27zPyJtJvk6IWy5hhMhit+b7ZEniAV6F2C47buOQKqh/KZCZ
Cplk5zRvv3y4QsKbKt+QEEAjK0FoxE4tFwLQTo9JCvKynEsCWG8mwN/fO/UzBt20gC9XkZty1yn0
lSb4VvNvJPVqrDP7qL5ad3I6lO3koC2Y+SBr3Akj26p0RFo36aECv8zXAJF84DKB2AQhON5zJFIf
6eo79CrVikPXoq9Jdpm6lYNQQm6hq8i4PlwHbptFKfTKvVu35GWWZnnLApaJhHso6jq9qzcvNUEP
QJgiTuw+sJpCA9KWWgI6t0zMLNe0gf/jvQp9r6IFlQCnekNi8Xy8kkELtj7qPel+faG/tS8cC/w2
gIwdC544bh5mwaIAuQr0lhKK8qE6cc02TYrgPBoCTeSeT5KB8HE63mdMFIPKAxKVrA2EPsTnDk66
YjiRdQpZxw0broCsgvwAtNaot/s5c790GW0reJv/Esl71lLLK70VuF8JV/622KoNOjsoKUUCbSg+
DrrUF8amuUw0g1tGE82sjGihmSqu6OZOu5Pjcpjc5VJCVWyZ/JGlLxy/8SEvoD7F1U0i/IiSzJwS
W6XaQ4O2IUzxoKZmEypQnCg8FhDqGlJIf3JEuDxLiT0+cVVoozeeoK5BPEEJZxNjk4f6jkYy1qAr
AqBoHBxcL68e7X+AzqggjO+CYkMpP6jTYzUWBs2D5dKFBYwGhaO63MsWj4KVEl3mCRgD6d7ViiyR
BQ6ziqeESb8pnkfJvxgRSkBLMmX410FqevPyxUDrF6HCTGZJocT+IBRWbniZk6O+Z6cJM5zsOwU8
lQ7w2l9Xd5vcOLxJ9WQtv2pgoJI2ZwbmPYf314W32QmuApexFCxMG5bXALSuM/H1tvX7vucGiEhW
zHR113P0BlibiK23RMR0dHcqnOL2OtXXOga8G1S27UtDzh4uQ5nC5sd1+Roexfg4jW/1W7SJ4yuc
RXbkyMOjFUkxjRm6pSHF1XdrnnY89SkHLWSskhWduD73Cvy+8lGumqYPr20DttKY4ypPQyRiwyNY
xJGXivdIoUlWtSS9rJFo5+gSyzwCkATLBk/a68ih+Xv1XU9nx/BfCc9mupQa2m2oTquWB8G+1hEN
KB0wqYG3XIyTfu691fq5tMqgyiaTLr8Pqpf82oaSNOJrrZqAi3o7zf1XStxiz1M4SZyKIix2uKHP
8QZohJ5jN+nf8DFN6uxIQK03AK+7UzgFnuke4Md/eoBjTfv+O5pQ/RwG0uiRjtaXd0eROt8hSyZr
0Fox2D7NJwWNIYudp2th6XmL1w60EBZ/NxUKWjymtQLb6kPYkUNCHDc1vHIzJey7rd4CuGP3jUem
mX0aJvgBaoGB2Xa989EJ6kq2JrHBSqKllyRl+IaXKIlOx5a2X3Zn94LHhx0jdGCygxS3K5PRnIJP
+zfDMpWZNz1MVGR3suNuJnxJ8tZQi6Kke9DPjwJp/n8iKr95UD2g3+o2yggx3hlxFdZ6aP16Dy3K
3D38IqH6Qitzn4VfTdj2MtiJcbKLI6OdrmRC87gvo+S4B1X28KmC5QXi8rdwO4tK+pwwp/Wnv2nJ
HS1o+xseGr1jL+vPpQWoUMZ6IFXnzez26ADp9w/kBWhuFIfPt2EXEvvH+ABzBuQkpqyQgwRqlTsq
vXSppbQMYq1vRqpjN1BqFaIVr3FFhU8Gmcu85R0lLyYoiAZOI+qqTgb8mTlu+Ick6U09IkJFpwJo
JiLpHyYZepZmNd0n+15T5XbsRHkEe1RFL9MXZ5FPHjiS/Ye6Pyei+/aQVm4eT5A0HfMbK71TzS8f
J4CXtW7P7b+rh2DCwdypXVLyvCGp9g7moHF0C49fCY0ge4vs1DgIH6JiACybS1d4YgDyEczp7n9s
JmXVMZ4GbqgkaWU6VKdCYMtn7p5BqLYIifgGEu5wALqhJv3owPTgFn9/urM+vIdgvxIEO+gUuWBu
ejquM9yAZy0hQ+yWhKSp3yauA/tJ7WyxVODawbBigjXf17Ifl+c5vVLOonjwDJzmoR5nLvNSHdmj
j490bWinKNThD/Qu3GZjkwJEWrqBNul+fw48UURY9sH33tSA29khOusesP1bjOjbxNMh4K9u9Agy
hEfoePn3Goi60C92OvBa/vbhAytFer14jlAfSN5geF8+dPjI2vMght3yZrE/+2CGVaRYnQ/9m2Aj
/Yu5+8v63rsfa+vtD9va7H7ZX19kh3yZbwBJVkIE3KuIFsX+yxdCXCnewLQTLY3ObmlvrQozoOhi
B1HU6pnB71Z9jBT5WrRBqELWA1fe57ZmT0G4sUsTs96PdEoVfhFmJ7D1MPk+AJHQw8ei2CG/VAzl
gLgHtk8qYMonsOeHaWQvcDwUFkJ7KAaAaaEz2FKzyQtwiZd8iJdud1VGvV2eMNwPqwjLJt8jvzmR
oNTnq9LU3xQVDHseuzlTTfFAIotLPLHmpk6Eff6KLT735Py6i9zjzxu0wQesYgNhAcj42y0FbmJL
Npd91W5XYB+4NBq3/fBssuubLlVBhv3ZzRWiq3QtjJSzvw2nFnic9SxjvYg+2H5daQ3+X+eyfbJA
pVma8Wbdva2QXqYscuh09UpUV67A5OixBZYQoCE/GlZ94AVcfybc1KQ2uP113DudANw/e3FqBMg5
HhOLGM4UvSAtD4Vqog6AdqWMrlxgv/Ebj3pCnbA9yqxYKTh0Qw0ihLtt3vpo+sn/Vlb7xrsd6a7Z
vQvojtCybVo1d4rqWqVAcuTnUb28VPxfSxs6SkT92Xix151Uj6+aYE6nk8o34NUE/sSvqaKL92B2
g516UNpNBSSGz3cDpMFVlX7LOQzFUW1YYp2l6+WHJb4sogkD61YrA3xcviBOwEjTPlgn5YjfvANz
DfPpkBLiBj8L0l/qZXBsx6rD33vrdw6jpRt3Z6iaYdN/r3UvNLmVgq2t5XtBYTgQc9cVwaF1uLli
iL01wnAkxb+jxQNNjZ2Plg6Kug3zp06H7slPn0+IFthdgLE6u/U19p4hQpDEYfubXXJb7p1zu7Uw
UyNtAoYzQWs7QdyrC+3M8xsRZb3IIj0sRopN48HCYdI4kXdYm9RUER2o+q1fPX8Zh+Z4xyuuGIuz
Mrw5zoLZUzhUnLOWo2wKHjldAN9r0kqrSoDCX4ICNSEWJkxYNpEfS1WJppy/COQqtb3m9vIzmc/i
78JDWhm1FAdDz4pAymth5WRdd8J7Gl09XEn7CyiI3fwDxTAKN/YVuPQyX7yBeVsl7sE7c/8SuQwo
tjgkVl1m9V/BoZ0wuFc/oAjFK+LVhKEtjZo58zquc44ICvz1Gy/qauZsZyNuXw7p7LLgF4MahyQT
FBJpgXLyrpHpxvV3I7oXzJUapAlzBRqXFaqHAhQ/G96P1oEivAirD6HW3jWVTvGOkrdcizgfLJf+
iAE53YhtfImoL9MfrGE456UAUomlV8dflzsP2I1Wb0BePX5DqewzmqL9aQ9Dts0zT6z/I3H/Rzq9
ILGhlOYv7EVxI64VD3+LxnWpOP2vyQk+0Md74JIBhgFf+sGce31lTbwME+RofN1Cf3WQlVMBcq6x
X4BoMvexKSlRIKSz8+1yc9yyfMiOT1MUH2UTEmz5v4y9LVMsr50MliABfFF76W8mN/X+xF0+adaI
yyG+3POD9E4v0N4HRhqDlZg5stpZqQOvfkQiJdB34SnolIFAF0pmrJzXD5XX0E3zPXjAEkewzCsZ
evy/Z85zlwkGhem8lQsbonp3HgRKIrI6qzW0QHdGVUEbxjc63quqcLAMKsDCTBjD5mUePwlym5WX
QWrDHHtl7lB9K8GeUOT48qHpTHxzb3gyHqGBagHYzJVY/HFALm05ozghXXCDrkPN4Cya3C4pQEsB
3Fz4GW+SD91CVWBVhaSJG816Qgr0dSnQaxsC6i9mBuhhpkpKbk2+fpWfL3mHfTrqgWE0VfxjJyOX
83trPTeB3+XQAW/1AmT93Pq8ESgwqopn44OvL+Pbeo2D+zCdvR8Ty1Qx08urAAGjUj/g/jKAH1u1
Nr22vOI9K3LZjIK8LqH5sZu7bxfX9W9UUfaxwagSTP44W4LzkAtOOvEK/enopTNAmXar44Q+WNge
J5Bn0OKNiSvnhb6SokW+FEXMKMrSA6Jn/pFYnP5vSg9csp6cA094lLpZIIJSx0r2HE5ioxUzL74p
Q07aUat/k9kP8wpOKBqyxiUwwTSD0f0dsbY3n5FG2G3eGrthS1kp5KDJvWgDMux6YL+n7qzMhoR/
nCluGjeVFZ3oBL1JaNQkBCCgBx/kZ/AE5LAPq7QwEp2n2BqxXtzE4A/GVbZlkTaexqthwyvJIYTj
+usc/ltIhGc/2eTLMWgkLVXwrZbWBCXEMPQ72VmelcxSACgfgP8wyI71cBxGdRvpR0snly/jzpIn
hLIZz5f8jTSV90rjlPtX/MuG6Z8GX12xVdrUHXae38s0v597dkE4Nbjfw08DvCD9sXXoPtQDWfa9
bX6dvjKl0sFDHytfrXVK2/9IDxKq9aqYr7SxehEHomi022v+4Q6utLT0a58HMrDZUXOO7HEqIJzO
8t1PGyduTvakfDZJoiHJ+G4lF4c5dQ10XvoH+chlV0lf6oyLDpyKN079zHS1b6/jOftio8CKLUd0
KBPYAWllSlv6aJH5qjkQ5wT56UaerSDGafFDYA+j7ijGR4TrQZkyKldBCx7gaQiJY/euNjTbJXCk
z+lSixdoMPYtEWANmAXXxskIERhrY4D0nhjsweG0nt57R5JWeY+ajWv3EfBrXPPCLIK7YT5/islE
pwpgLjmcfKXB+chYaSecocLzFd1GsZtinm622ENY+dSVQdJSEMON3zp9+PRVGnCheTI8c5WcmMJA
fomiRESUOyexdjxGBDCUV03crv0Tg4MnBCXcNBRxSC2mdVaM+Uw5hm/pj29/VQILWL+V1nFIkZ20
7cxMk4XfX3GdOhYqeGzOM/IJ5qQjXxkNNoAflrNcEgcZVeyAJ8zX9ArmaGrr/bZ75X15IEYwhlef
mcIL9Jfki8qVEMNYY1iYt7DZTDC7jqeJD9kOLvV6JS3w2F4sq6WfyggjzJ1ufDYTesQSC/3VDsJc
M0w+47pJx0JTHWtNRdy93OWSFxEwZDj4KKGiTdPkZsie40SKCSEyOOnBIsPGVC7fnNCBHNSA0qZM
porQiqsXLZN2JFVmwQ35CK+n7/1vdYMCtnXVKuwin32Wm2A/TX6u05LscMLfYaPCTSstB8uBQUED
ynRXpJvxDH973j1Dbgeqdncax6WCc/uaZ9W1aioFxYS+dLIMarkMweur9jT0beWkh2qrUt9/07e2
yVa1cD9ANAFXzbziGhl/i5dWthHzV86Jm9q932VuZL1pe/7nkvIC4oMmt8CfcUwJGA6PzhGEdSmg
iMKPMOYMgUJJbGLQBRQdLpDU3cnzzO/qlafL5QExxJLYwPz0ITpKbZShNHPqOZQF3yrnHJbi7ywy
SQF4VbKfpfGEcjo5TX/ef1jcrYOTAffEwZMT9EAxzQBf5NOVHQYpp6Fn1AhNQMf4EwZJtLKRyfjt
1KVv3goJsxKccQfWDExhNl2BnZfcSiSpbFyxZUJYyQrTAUgP72/Ra0DbH7Y/LRon4F4KRm4Qia4z
s5/u8NgU7ORZt0Mh4aZ36tKRF0+7gbe4FO9SWjNBFfIsfanVKFTdZ+r+uyOR+PcE6fcaN5lPezMj
HI9almeU+tRdf+yb+tCj7+1IhJloontW2TfY5Q1rN9ZMoHDLDdDMI3EUJyX9CrOAxxoyUnu3BmpM
+VIkvGByyjpCY2HNcTtnBndlvJ+0gKK3Q0Uvj5/X+deI551QlhGCw9IdqK7N0W9mJV/aYutuJPFo
G+alT6ON2vbnZB6Lh/pzisgHxd3QonzJSDm6e88HLl+nsbufV9M4h8DNFoBW4DwPVsKVCPKZ+vk/
DlbjqAVHAuYhGFcX3OoVjThQ/L4Exvf4iwThlHFAovLscdBFqzSx0de+g6ujML53ZOGaHKG0R2kn
+dYNh0sek8789XhMDI+1x/mGAyzsFH6Y+gvMoO41cXXDKQ8gRaW/jRQNCBzRT43xefjM56FwkT+r
Sq/eykl4HekEEZkG/ZNNpSb5Ichbm/+YPgHa3iwR9BgtSfIYbSw/ImE5BTIO1t/8NtaBNyiThOe4
XlhSssAqSqF822SwsRKl99RCiqfak9hXdKkn1S3WvA72nE8P1n9iv1dkto5SEyLeJCQaEY1i5Ms4
YePfsT4LZzZRgTWdrSZ78WsIgCoLH0EtruxCXTvJhS8W9GZztL2d9nwaF47hFrYb+IyNRN8whopH
LlmT0vBJk7qbqcnS2HY/ERLobsTnWKfm5GhtYGdR4bXTSZkhX07O3r7W53l+sm2YjYzvBJ30rJuR
vkeHPAGs/5FSrxUxWLWwT+Cn/w7NUKcMd3Yfx/bORkTDv4CiyzhKdWinwVg/4Jm0t6Z8BZuZ/ujD
+EJWqTcbHwY876aNVVOmVxSIxSNyULBRTe9P8lDqQvxRKbxTpBRu5AJtrCWEnXFrEki34tvUiPGF
d7zK8UAsFpC1HbIuwrwlFqnWpH2pkx9fULNJjBJPtFgsn3oyu5h64MLJKIDKgKnKVZOe09uJLaRH
WlPWAYsWm/xxQfz33j0Gu8Qmg/wpsy3+pKef5VyEAKJl7S6qxb2sDWUmqZkzaMlQwuIgY/iPDbmn
LgCIoEqHienKMj1eJXKjo9rh1RmgW8EsncBPenZxh85xfkpq2+Mwq+XoJ/Qubi/l6xpa9R6bSjrE
OYczrdr/66l9HOYj56voeZcKBItRwnOcL2wkxyYbymlkBbn4gsEMm8jVjHnudmTpe/+conzfyguk
/AvXmb28qmf9lWA+cS/bsCq8v8Q46Sy36A7QifLjp57rlvdI2cMUptHX4WQ6owQyY0BaLSirFc12
s8148t/I6RCK10CUipsyfunpMHVQM/nfAreZWnSPfnzhbUWAmT3nREqHDfpKE98ngZYWyYhuZAiX
oMN+9CxfCJ0DBmoqObJ3Q9/HdecIc1mUhs6IoY4uhE1JoNaaexkPgDNrIicvVqvc+aGDIE92pd6H
e1BcEdN5l4RQgN0s5LOUm2g3zkUArTa1wXw0b+7yCbfuQX7NvHwLqJM++tB8IGR+aN26F7abr/wR
9ZKcEwvRbrBYyoTkJsBZhPTU/tAq61xA7FrlA2hXE4DRigpuXuwKlMvhFeNntMqE7ZmWGkFSDofw
hOnrNZghZ4JvxjT5WCFM2vlfFAe0EdTaI++OJPuruHpXErmHBGvHNRxAYdbU8bjzvDm9vRE4XhLd
iqt+0hEt5u3jkYJYvsbQDFFmVYcxnm8t1oroxPE57zhKyiNv72/H9ENl+0MiJC6VZbs2bHa3sEDR
Xgd9JrOkcOuF1AjKdjpRDVU4NxChY+T1xt+1AYYg6o0bWDX7pTxZ9ISNtCDAPWb/i5a2Z7+tfyQc
/mnlv6kzfSqzPkqSmfHXnDirP6VM9F2oAPIAp3gX+qUgGvcgBOjQukzDoRYr/kdrYQV9d1n7B1Bu
6ORS9Ouz+uQAriDy0Fsbe07ptxmjwalRvStR7+l1jIAhha0LXYpxRlJSianbZYeFtucTWcGYASie
s/oK5g/kZzlWXb4te/STzrs1gXmQf0E/tmJB2bSHVqpm9IEt4MPT3PJcaU5D8X0C0zNfez6z59Di
ufc3JpLn3yVg8FPJlDuCatLpLPExp3sjT3NIgFKRkVQFh+B4d6AhR4VCWa9iOLQHdjEnY1SpDlsw
DAjMGx8GsMwy8xDOPDWAT6U4t7sBLFDSDTxBXjMAZ5DP8cYmUyBGB5X8vjNv9MpqP4iiHjAjF8Pc
leX97ujL3liWYSgorM7dyq5H+jKT1R7h3PI/kDIAfhjgzb2sRgYHs9JP6OQImzGjHKEQMvf0Q3fV
9Oo/W2BC262OLUhw3A3cC3pruc0fH+MJzy4oQlqQ23mWsTVzV8Clya6ChGtOA0HmZSor0qPkitr6
CdQjsuSOwv0DGhocIqBM8enz2sVV7zf2MJJ5X5R5iRWtTdjTwdQk37usIlQVl+412YFWmkkUZxaf
pdPxrvaQlFtWQ0fAFbxs6YHAQ47bEziXYbxPxh8gEhxWkRaaSIh+hSvl4V0pSm4lVsurs1XyZJZb
6342l/u9LVmS9VnBs18g8U56zOkK7Ol8KTHBQNhk0a5aGqqZxCTQjj/bxw9jqA1oGU+1kZ+IMjwi
2OaCmSORkQPxS6MieBNU5JeUzw5cUw0fBvXicsfjnfTiKHS3DPwQ4yIo4fzAK63/WRmXd8VkzQhv
+8xFrqTNwGxG207SHKmox+vaHPf1B47Lsoo56p2fcEDjMz/5utCBjFVuK67yXu2Fa5tpgfW83a/5
/g0OSNu3IwC38NqOEBOfsSg09x5kMHLMj5fh8gSg2l9hIVzDPYhLHL9ODFS/UQVwdlO6VhcAuA44
Vch4JfVMY/ZAiAlo4Pam3izGg5qUtfrdzHPhp9LUapPjGnKlX/8cEUetf+DWWaFAF83v/v0HXzvf
tL4vdgLXg+8DcbpsFyikN1TfenCz3MwHMJmsAhqjF3YHs+xTi8SvgewQdiYdAkZu/Rj7KjMDid4c
XTZhNUlQZCOY/vTs0YBFQLY/QZxOgG4RzsSBg2WCH1Vd/ft3Teby3DuzxxQkVYwvWiYllVd6rLo+
2h9HNnMyy2KDjs+Z/gKUexxfHvd3UNpW4kIAZ60XCxDF6emt5CLyDNr195qBHNUHiCPP1LyBr8G7
I8gypY59eu3VcbbkczfgnvLG1IsLjC3679HXr5QSuViNpzqOc+w4i6lLUtsIm5ao2M/Yr31q7BRa
kxT7XYbfmTdBBBR90ItNzIEsg3FNKD2MVyro/ArhEFBOUi8Ff7MrMgRVtu6RseXsuvpXwP9YtpqB
zCM+36eLZ+tzzpb8RNUdXdPqzVnGZeatHR8lpTkIdkiFYmNz8rj9N5P7sxdz/slPjyVeQAxPr+uW
yRWBjfAI92RiYMA0LZZtKYAIfQyUouNcH/mg5ICeXenoP+WgHVngde4FnIj9TApgmpd9XUvMPAda
TqA3UMqLNujsSFUXqJZALMe3Zu24svSJRu/18l2Pw/66RFPUSMkyzOmoG+FSqOLSJJcatKzO3fYp
/k8BZ0UWDtru66SP9VJLSzEJEa0MxpsBy/wTiC/rGR7enK8jEan7YvFKd9kcCNoDFdoCjA5TxOoh
kh3v42R7ZjItKYqP5UyGDvYgraUQf88bjJi+HKQdr3yzUo45hrePilMK1qgyF59vebyvZhrBtR3j
KoHXHLD+3fxccDZldLEe5wGa38j0ne4CkqWD31oEMP5UDuED2G0EeEyhkWQzCSXJGr9a+bwRKqVp
bBVFPJI7HnCsOmhKLk2z/AQujdoh8rQG5LUuKZPfGT/QiC3z+wxk3lRVmfS7cFTIlszYzt9hzXxm
xQD6zJcv5jXjE8qEfYIqqbVFJ/b6wHWcUj16NaIaKpPCfY+3JRSmdNdSHGY6GRYTRBWyWB/0M2nd
43uPr3YaCbPYRyToxuoYt8nL7bO3xZGNsVcrBshRqjSYGOhJMy0gDAxUfXQpnVqUVHEdBNwzlrKy
VvHkGi5IdNkCyk91HoC0m8ITkjwM8OcXsjIlrRJjX3AXguUACA+86x2HHsLnLPy4mAfC28C+fUT3
YkFifx3Rv6R08Wq18I9nYSk6UXsr51aLpPTvMsBs8GBdQlO34EDwyILcUGsaCUvTY/lj4hTSdXgU
4rZ2+Kw36Wmo5s12LazHFodQmZMq6XgB5HtQw3zzNaAmb0ExjSeUtaPLR33sXIsPGvqdopQrCaSE
qb5f5QRklCZDgkX0nZOjEtIjKKg628Ud33xdxiu58U5R2epEqeLFuDyq1gh6FTsAJo7k/2B9Rs0Q
1S1pOdM/fawxzF24OhLGX1fba84zDxUTjM45X9WZW6QSP8/dBuCi0WChe5qK2fPKoyCr8aEiY8rG
wsxs4aNeT3fl9VyZO8RnxSmCZdLnJKQj2h8cX9Xx/IGeChK2quh/66jGLRbMfVtnVjLWJ5eUgh66
xAYSgJ6Gl8W+iiCJxfMMvv7r7hjn417N7fXbaiZ+W0GhRSwbqCQq+xhgc+AxAymAiaf1MuOX2Hul
kcIau9hseb41mcME9IrmFu61woGxmYbJFh/MO+fDB3VNlXELPHx63pxEQMCmUibYDgaB5mj5obY4
NpM5+Qfnf0Z8Qj15baSnLSO7DTqYa6uI46gnzE6m6cWTQGL87jwOFbIwaTPNfHFn2zDsS6m0qH83
OyMMYpf2Hs7jqFFDm62vSfLjH8rGPaWGe82594Iz3o59Yd4FPBc4vpVo49wbj1tzmm33HLjayKfN
CUbpD/lWI3EKCl4/RdyefVwwB1Cme4pPgAfn/dG3gLDFyhZWM8YNjGuAt5m8jcJSEyHhuqDDrXs7
DmAqO5uFMgJvLnV1FA+U1colVuqlGip822l9+Y6ZKnENr4kiihljQ4QZCBA8KsEmOsD3R/5OhVFh
4Fkf6VItzapcPVqjc9uZ1q5ZgjpCEc7HhsY8t7yOAR5tHxK5tRXPm/R/cCWKSctzMJLI5uWkqt4t
e5k5z4m8zRPLcy81gV/FmQx2hSSlFmbeakUMbEbCX9pN6Z8zUci/3LWOvZ4o1Ps+x6MJa+ePmtup
ZY2j6QuilDet4st4MsgL1rs+YkbPtP+UAIhun+oNndIkQcp4O3Z20+GWVCo+RdByEhXFBS0cw8FQ
TJhEpYwEbPBE2XT0/goUj9PfsnSiBzT6BUSeJRVLMtSaa58tSyUriDfYPZ62gTsY665VfsepJ5Y+
thrsqjkFAPEpD5pEcXGDSjjiBVqfl8VUndbnluKc7+pxrdapHghNoknZZReA980DKasGXNC/+rp+
AhVRhMLjX0Sj0sX3Kkj9bEoHpEdmGJJw80wFOWaggSgyrYU+9uW7EJwiPiCkWwyFfDEpBkXLEwz8
dXUh0bDYaQ5AY2QwP/mhaOgbjdEyNoO0bz/JeELoEGDvLlKS75Xiw9E5MB5OYAUPJmjiopT2WRA9
6fC9vYBmBv0fHNsicZXC4VMfXz1+VqEGxdFiZFC/oNBRnIg6d1R9pI9vgIfbaU/NojOH/j8jvGGK
Q2asqgTVd9a3vnE2zmUN44c9YPz1PGMdIdVaaAHRJijHEVvnR4SVPbCkV8pFyW+JVkxtRhoyl4+a
AnltepuiVN+Aadu4cvqPTZipuZJkJoHq+d+e3JMkLVcTZIOfoFOGJnUojETzP9qaHJe8gPecHYW8
gEmPdCbi1vZZqbCYWbh+1Vb+m1evIjNx79tslIPHVWc9k4f51gZeJS3SrTajPw2+OiwVAtmuqoOz
mGOY3gjzh2fUxTTcgUSmSJt7qxbYT/VZ2U8ro2paqszBTmx6yBXnKFvaUV+XeM4PtmWLu4r5I8g6
b7kaJxtdln0Ym7OUataY8LBMkguTO0QWXgaRcSDM3oYYdc/r4UeGLbz1AfV+KsgJOAqELGV6aRCx
aGVKzhe9kKsAQP6gsHVfLNbkdB88T3+BHnx4KzPLF/tKeMwKLLFrFJkC2DHpHK8UXn5wSYgMgk9A
onXteNPyt6cpP+OGoUrgrhFf99pn0+xS17gxp4C3Qmpyfkn5xqiqdt1WHcwVOpg6bbJoaD1+1b9e
iKncHE8aKkucc+afAW7TQRGyRt1l9Fs68Y3gLKb4OF7kK8kaeoq9CcqVy0znnC/aUQDa/fth8x25
U+N3wAKl4CqfpXZLV0Jm+nn7xPELgbhHITyKUr79DKQ4jZ8NjTAj1B9pLoywNXgRaiJDZ0p9N6P+
XyuGCaab5kxIru5jZFNyvW79EpbTJQCXYX7kIdX062ZxZQVGt0G8ca0Lxj1TAbRvYDxrGeeIDo3F
z1YRGN3obuyCzf5Qzg/vTzjesGK2cftxdHxmCwd9mIke45ggajpiGdcvSOCcPZwBrQAVAm70yf0j
88oL5cvT4R3iv7UVLQR6fiZXV4jRWdKfc7KREe1OEeGs2nPtxqo8/E1VJgliiZ+o5oEbe1ulhvO9
wBx7DHyIlz6uXrzpbP/en1xvAZtPuGb/KjXTxBRUA4haDKppmVt7aO/MTzcqP2HxaoSN2e3Arlyb
UVJXxUPuo7m+nFV4SLajx+1BMBapeghaZfEW65k19PMW0dG9xabn05pL52ktwq4xZS1zC671VVmy
eElMAJz5PVXNvSni1QVmSn17Cate6pBUUUlDSiOMvWq5Yq3tCzhsspGmNk09fF8yulMDae5RGPy8
GkWOj0Qxua73irB+epQSnPvqx090X2898qk8xltxSwMkJgQL3uS7TzoucLV1k1Y+5oKql1CJWItm
6gNWszeIf9S4vOPep3v17eogmOYqV78ZP2Ppxg83JZbtkqFrZSXvU5yuv5bx1wX1dlzmp61w68Og
fDEuwuT1iAFzNopF7eetU8VvMAoA0vCzMNoLfWZKPeG1VVjWstbV7K0iTpwvJSilir/eCHh9Sdvk
kqyl9yrQR4zeIENmXU7WpXU/svOZQpma5f3njlu9bVpyfTtaKazY+F1wRLqL7YVv3zhgG35SMVTB
p7UF2J6ekfOYW6BaoM2n9qQEmsDaREgYv7dYDIeSML6rKDLClNne+tEmdXEAcjafSjawlx4y7nb7
Dh1SU75kerq2KKwQeX9D30OUHFf/nDDfIFZmOMUpSWfdYA7S0nTwX5ACtWjFZ3mGYT0WLM6Gsg3q
tiuaoNgWp94FfVsseWqjLpf57T0VGyaSciFlk/wveIUtht6hTCdN0JVPaQA9lBDu+H7F3KYoj+KL
9JBHIoz5dPiieVoOWicfv625xr1SaU63z0KvJdZ2zsGPa/Vl8MVO/UoC4QavXZi0hQFdE35xzi9H
Jc87y+F0ao4ypBTJY5UJ72ooHypZCKyUOF3hbZGp7bNEY7dVu8tuDrr7X21t74LDYLpPeDlGgxV3
zXh1DF1xzxu6KGsM3b0dtHyqUGTuG4q/hbE/v11UCClEAXOTsneNuPWUNgW/A5aSENtmoWMIIIu6
GqHnC0opKA4cT73zqClrh9lwf6iW75vLlY/1y85hDgSe5bD5NtDY+mCR8AUuzFb8DQvkkVxDDNAn
3N/HqjiWqsZRhFjeb/rUrQ9xH3Op0bwIZetZQzz9VRb2GgS6nN27+cXIuTUpX4SJTU5xcGQGwWhZ
Ao3WmNQQCQUcoy1JcneoXHU4rIGW8ahzrf+feTTRKh3C8Hfq6LgUkK00hE9GKLhp4+VeNBm+JTsg
7Zql5ghzR7XngxSn7DCYa8/5oqOQ9RKwpQKtDv41TUwwSwjQcUjCl7jezRLbZh5ofAtuS0Elcoyn
IZ+JvcavGLIHYJ8WTgUU2+FFr3dVcYT9+VjrN7iQCxYqC+aPERgDgAPWlpiIeBjyoZ3S3jKCXrKF
HiWAKxnQP1zSZIlN8TJLK6Kg+rTNOQkh/hlaBMYtJotHBLzkWJfzUgKrem2AVi5IFUTSoy28EAVZ
YakeY6D/2xUPUXPAveUxp4bl5qzLa+steUiKrNoQN77U4lC4eLDmYarsVODTBrysfP98JXINKjk7
wL4H7pUbvtK7y8WnF18J9oKbb8POsjTbRSO3HCw8pdVofi4HHJ01a5jJ+Gnbd0oEsWCMoXFCTc0j
o7kJYRu2AiJ8Thb74NZCLRcKKT5PopVplbiLL0XIwIS3AaKcR4xf/z+l7oefs+a7nrqkMBfLNU3/
yKwbCkgM1m5kcc6TjMqLQl2QWo2u6h7/vxukd23btY2Kn5RuCKKQH0/klA0ng7id9+pA9cYGCCsX
gNhhd1Is3FEwQGu4zSPPpQZbOOo3YrtK26JXamZk9WEL7te+tDcowQj+7Q+e75C+ViVX9HX0Ebp6
LwSsVNRxntSrOMAGp/A0SnCJFl1Q4NWvu3Uv9ASXGvbFOThDUWIjn/Cuk7drzkReRAvlRB/qZaSZ
Z5ibqkBINkajl2BpWlHEw6Nl136LNqIlf943x7812I20zYQF4PEwtJNWeu1ML+8NPaQgJcFmiFIE
g52GMdXw/71epZFa87KMDutulBSOxNRGsQTPqK6folGpRFqS/85/kx4oj/mNw2XC25zDY2fbYE2U
e6LqxPzve0rwTJapjwmjQ6HI2N65fllQPOt9TPl0WdjRFhxvrKnEOXkavB50cNF3Y74dWww3BD9S
2tapyG2pBiW7h2eAzizq6PXK9Bm2ypS+PBzhvz9qjESNnW4Xu+YuDoOlbmvzl3tvyNlUJ8TcjZUI
2vvOZgQPeAkJyCEU3rSHNR+xWOaphqp1YqcihlTzMJpAn1n46WqjyxqJASEo542TYDkJYK8EvcNT
eT8OO1z19EauZ35DNmUyq6JEeQRFMiO7pfmBEEtf7X8SuNUlsI0SgB9jbUiHy/Gh//RCd2SRJQGF
OB96QpH2OQpqmMUANj5prRHvzVy2QC65xEE9SgF2gmkPQTByJ8vgxzsFvWXD7TmY4hYH/BuFGm7W
J6uumKYZVUZqwOmJr68uD8ktzskbpkZ94s35dCo85pthy/OCq64OqC3fP9dziJUXbo+BnSMbHo46
mVC0bdBh2OD1qatVDooe/TJ51fWhUqQ4BP7TKOa6Kq9XZUa5c6BS0MF4gZFg4qkAg4rNdgbmcxXc
LQjj/MANcHVXb6Noyj21c/vdPwUMGyIPXmRqWcB8xdfFWphmJSIbS+1LpCyahCCC+81qStPtwX/e
b+4D6YW1QUNxYmR3792fLywRJ0F3A8eZByIp+WnZK+nab5hx6GsaHMM39RuVrxDAg/nFmSrjJ+i9
xCmJERgP/fE6hrrv8qMqPIIuOVXSL2Eq6Vvxbs3hrh/WVhhcdMZTLMF4pOc9dU393P60ZfFgO28e
+6FvlRUVWsUz2KCbgKMB1JeejAjjKWvzoHoWU0rzFnR05fnwwiyen2T4F+uMh9PABBdvC2rMosEi
EAbHh7pj6BLLH4Z3aXVG80PIIrVOfbK85bEWyQp6J5Oh1oHDMq75tOloYrYDG9K9u3euYio8tEQk
g0GUgjJisczQQbnuz3XKVUYBodEpCsgTr1JxGiB+LWSlk0VUs8uKsENt1Xp61FjTSGHe6aAhbHE6
0fmlIg14hx/BcW7XlN42hNs3Oi82T+wPNCWA3JDtFnplWHNM8xhQRf7ypy3Y1Np55OT5HO5b48zl
1D8FkdX+a8onsHOJpXBS6NvEuIVJdDkM2AulpcBvWJMeEd5vqq5KQNukinDmK68NRTE6K+XtUPFz
7saILWeEc6ytVw0knCfDsib7ywXgL04KN8ND5TyHyURpvxUvIAuNWvPVf1QcU/M8ShfzHB/4qSuL
Qte9V86HcmGAUnj1B1hQT9MuaqSXKV8MkWTiAXiInuOn9AWge6GW8tRTIJ5s2eosSAVmMcaYUMHA
oP+ulnwm6j7e7WSxfNXfwEjdpxgx9Mg/pJCSqLKa9Gt736GwM+CqpCMxnLTI5KNubyiJeKnq6mwC
D18kcLNoRsdw+LlRKjxB4RjzTCD8yyxYD1OmWGeyeIFypOOxeQR2zwBGH4DwznoCsYd1jO5ajDN3
MyQRfhDqYtiAnk1igwUTXmnrqKkc7VA6TI4PadTjyp3sYXpr3zzR0D8+RUfp7oPty31ULGia6IEl
lKF8hbfjSthWm849AvkOwbtWJglwwYGRSNY6mSh2+tJnUHK/pvjBH/Bd48rGIztYNiWJnsqozoUB
rI/V1ANxW4Jn3/CgnFOB4cE1i+XX0yJi75ONlHbH1TmyHl0bJyg8pl+3IFmFQob8T5lk9oQRI/R7
M+NZbRCyeC5jCFqrEeZ2Lmbee5GPLxSk5lgGSD1Nes1BihBRre0EOITS9HYj2qrL/NSYUlmVWOQ5
WgbFDEZjORKz1vK4uUlsnHYqcP8pbRptW1jpl2KvHwjrJMYCGtR95pjI2HavCXVPo8SmjF0mD++/
bxpZNDZUbLy+c4Pf6Kmj+NcHjm2BOSk0v4/AcQd8guhaj8sw86olJ0HJyMsxtBe36vUt5tnvbdn9
x3uOsfJGvM603BW2Yw1ZjXaZ4Wk+pWFYOb3tHwEO3Ft+Bo0uhMKNAUHs1WesHKGyxNes0Nvrr9WQ
QinTHiFVwHm7Jo99L8/pXNYTEqi4W2BqVt/Sji726bKZ8n4Spl660JWWVoUqk2oG+bfUbuTdVTx7
JVxOsabvYvC1SZSg+w5gpnlK8w/6icrtgZ8nkhpxtj56H1qFsVlv9sb2jrKpLPEMhMgnqrTN2TxZ
b6uS85Uj0/F+Qws05glqAbu9Ke7aFXZFOzj6chb0LiA92DYkVfkJ5dd40YIMMJ26gbG05trA2sQF
JEiIadPb7c3UiHhiPF8QgP3ISG2OJgtKm7w9Ip+q57EhJfCd/JOLrBfuONfkfTkZ6I6Fj48lxo+b
mszScTRWNM5JR2EIELa7EhnGw8W69kFoStGEKKupVT/HK8qyZF/qxn7aJJIDqFLlbcR8j5secDhF
X2KLxxvC5dV/EYuxuz3k1hN7mTHK1hCNj4EoIBGVHrRGMEAwnOu3lAPtLnlhecLnd7aVaSoSjXcL
nPkUbdkOYK3ha8KTI7W0AMi6FmqAgVfpzO1KLI+meHNOaTyieP93gQeNgEu13gILHGN1Ak4MUeNp
gQoMxWJ7nDPcQfhR78ObMSdgMw28Xk9pRyeFXjgpE/FrjJR+i5osbR0SaLImJ2Rkj5Ni5ZiNwQ3x
3PJ5wgarrm2wQdfAIEdx0ssAttvG9wE3AacWKnHIy1gXkAArpPRbwCPiIwJE4g5+E5KkS4c1irG6
41ZYNNFhNWwXw0+Qwf6xKIAkYuGCEVTuL6EI9Mykuypka0QD3P1YedtGdb7TNot8GiGOcjbJFdRx
KyQzJKJF78qgHIENCJxr02Qp34tM/qKhoDeR4jw2LXHHPzbHNpMWLISwlwqTlDOzm1D+Alrarbr8
2+vSptroF5ScYH2qkL0XQ9pzJM25NP0iuv+5UfzV8Gb0roAjqqozlA==
`protect end_protected
| gpl-3.0 | 899cd6093f3f85e21934aaabf2f76222 | 0.953 | 1.843745 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/hdl/vga_controller.vhd | 1 | 4,417 | ---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY vga_controller IS
GENERIC(
h_pulse : INTEGER := 96; --horiztonal sync pulse width in pixels
h_bp : INTEGER := 48; --horiztonal back porch width in pixels
h_pixels : INTEGER := 640; --horiztonal display width in pixels
h_fp : INTEGER := 16; --horiztonal front porch width in pixels
h_pol : STD_LOGIC := '0'; --horizontal sync pulse polarity (1 = positive, 0 = negative)
v_pulse : INTEGER := 2; --vertical sync pulse width in rows
v_bp : INTEGER := 33; --vertical back porch width in rows
v_pixels : INTEGER := 480; --vertical display width in rows
v_fp : INTEGER := 10; --vertical front porch width in rows
v_pol : STD_LOGIC := '0'); --vertical sync pulse polarity (1 = positive, 0 = negative)
PORT(
pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used
reset_n : IN STD_LOGIC; --active low asycnchronous reset
h_sync : OUT STD_LOGIC; --horiztonal sync pulse
v_sync : OUT STD_LOGIC; --vertical sync pulse
disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time)
row : OUT STD_LOGIC_VECTOR(0 TO 9); --row pixel coordinate
column : OUT STD_LOGIC_VECTOR(0 TO 9); --column pixel coordinate
n_blank : OUT STD_LOGIC; --direct blacking output to DAC
n_sync : OUT STD_LOGIC); --sync-on-green output to DAC
END vga_controller;
ARCHITECTURE behavior OF vga_controller IS
CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row
CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column
BEGIN
n_blank <= '1'; --no direct blanking
n_sync <= '0'; --no sync on green
PROCESS(pixel_clk, reset_n)
VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns)
VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows)
BEGIN
IF(reset_n = '0') THEN --reset asserted
h_count := 0; --reset horizontal counter
v_count := 0; --reset vertical counter
h_sync <= NOT h_pol; --deassert horizontal sync
v_sync <= NOT v_pol; --deassert vertical sync
disp_ena <= '0'; --disable display
column <= std_logic_vector(to_unsigned(0, column'length)); --reset column pixel coordinate
row <= std_logic_vector(to_unsigned(0, row'length)); --reset row pixel coordinate
ELSIF(rising_edge(pixel_clk)) THEN
--counters
IF(h_count < h_period - 1) THEN --horizontal counter (pixels)
h_count := h_count + 1;
ELSE
h_count := 0;
IF(v_count < v_period - 1) THEN --veritcal counter (rows)
v_count := v_count + 1;
ELSE
v_count := 0;
END IF;
END IF;
--horizontal sync signal
IF(h_count < h_pixels + h_fp OR h_count > h_pixels + h_fp + h_pulse) THEN
h_sync <= NOT h_pol; --deassert horiztonal sync pulse
ELSE
h_sync <= h_pol; --assert horiztonal sync pulse
END IF;
--vertical sync signal
IF(v_count < v_pixels + v_fp OR v_count > v_pixels + v_fp + v_pulse) THEN
v_sync <= NOT v_pol; --deassert vertical sync pulse
ELSE
v_sync <= v_pol; --assert vertical sync pulse
END IF;
--set pixel coordinates
IF(h_count < h_pixels) THEN --horiztonal display time
column <= std_logic_vector(to_unsigned(h_count, column'length)); -- set horisontal pixel coordinate
END IF;
IF(v_count < v_pixels) THEN --vertical display time
row <= std_logic_vector(to_unsigned(v_count, row'length)); --set vertical pixel coordinate
END IF;
--set display enable output
IF(h_count < h_pixels AND v_count < v_pixels) THEN --display time
disp_ena <= '1'; --enable display
ELSE --blanking time
disp_ena <= '0'; --disable display
END IF;
END IF;
END PROCESS;
END behavior;
| gpl-2.0 | 45a6f7f87d8de6e42c33b66f017941dd | 0.569391 | 3.662521 | false | false | false | false |
bonfireprocessor/bonfire-soc | obsolete/papro_lpc.vhd | 1 | 2,849 | ---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at Sat Feb 18 19:01:47 2017
--
-- Configuration:
-- Number of masters: 1
-- Number of slaves: 2
-- Master address width: 26
-- Slave address width: 8
-- Port size: 8
-- Port granularity: 8
-- Entity name: papro_lpc
-- Pipelined arbiter: no
-- Registered feedback: no
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e papro_lpc 1 2 26 8 8 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity papro_lpc is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(25 downto 0);
s0_dat_i: in std_logic_vector(7 downto 0);
s0_dat_o: out std_logic_vector(7 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(7 downto 0);
m0_dat_o: out std_logic_vector(7 downto 0);
m0_dat_i: in std_logic_vector(7 downto 0);
m1_cyc_o: out std_logic;
m1_stb_o: out std_logic;
m1_we_o: out std_logic;
m1_ack_i: in std_logic;
m1_adr_o: out std_logic_vector(7 downto 0);
m1_dat_o: out std_logic_vector(7 downto 0);
m1_dat_i: in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of papro_lpc is
signal select_slave: std_logic_vector(2 downto 0);
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal adr_mux: std_logic_vector(25 downto 0);
signal wdata_mux: std_logic_vector(7 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(7 downto 0);
begin
-- MASTER->SLAVE MUX
cyc_mux<=s0_cyc_i;
stb_mux<=s0_stb_i;
we_mux<=s0_we_i;
adr_mux<=s0_adr_i;
wdata_mux<=s0_dat_i;
-- MASTER->SLAVE DEMUX
select_slave<="001" when adr_mux(25 downto 8)="000000000000000000" else
"010" when adr_mux(25 downto 8)="000000000000000001" else
"100"; -- fallback slave
m0_cyc_o<=cyc_mux and select_slave(0);
m0_stb_o<=stb_mux and select_slave(0);
m0_we_o<=we_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
m1_cyc_o<=cyc_mux and select_slave(1);
m1_stb_o<=stb_mux and select_slave(1);
m1_we_o<=we_mux;
m1_adr_o<=adr_mux(m1_adr_o'range);
m1_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=(m0_ack_i and select_slave(0)) or
(m1_ack_i and select_slave(1)) or
(cyc_mux and stb_mux and select_slave(2)); -- fallback slave
rdata_mux_gen: for i in rdata_mux'range generate
rdata_mux(i)<=(m0_dat_i(i) and select_slave(0)) or
(m1_dat_i(i) and select_slave(1));
end generate;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux;
s0_dat_o<=rdata_mux;
end architecture;
| gpl-3.0 | 8ef75608f20286ace8e4881336f0f8cc | 0.622324 | 2.54375 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_sitofp_32ns_32_6.vhd | 6 | 2,642 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_sitofp_32ns_32_6 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 6;
din0_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_sitofp_32ns_32_6 is
--------------------- Component ---------------------
component ANN_ap_sitofp_4_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_sitofp_4_no_dsp_32_u : component ANN_ap_sitofp_4_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | e35706a93d602d281fae9ae154fa6b82 | 0.467827 | 3.715893 | false | false | false | false |
brotatos/Whack-A-Mole | src/ScoreKeeper.vhd | 1 | 1,496 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:40:40 12/03/2013
-- Design Name:
-- Module Name: ScoreKeeper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ScoreKeeper is
Port ( LEDS : in STD_LOGIC_VECTOR(7 downto 0);
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
TIME_LEFT : in STD_LOGIC_VECTOR (7 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
SCORE : out STD_LOGIC_VECTOR (7 downto 0));
end ScoreKeeper;
architecture Behavioral of ScoreKeeper is
signal score_tmp : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
count: process (LEDS, RESET, SWITCHES, CLK)
begin
if (rising_edge(CLK)) then
if (TIME_LEFT > "00000000") then
if (LEDS = SWITCHES) then
score_tmp <= score_tmp + 1;
end if;
SCORE <= TIME_LEFT;
else
SCORE <= score_tmp;
end if;
end if;
if (RESET = '1') then
score_tmp <= "00000000";
end if;
end process count;
end Behavioral;
| mit | 349074e2a198e8b49cb573cc5228cf30 | 0.505348 | 3.875648 | false | false | false | false |
hoglet67/AtomVGAWing | src/AtomVGAWing.vhd | 1 | 15,110 | library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity AtomVGAWing is
Port (
clock32 : in std_logic;
rst : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (1 downto 0);
hsync : out std_logic;
vsync : out std_logic;
clamp : out std_logic;
led : out std_logic_vector (4 downto 1);
test : out std_logic_vector (6 downto 1);
switch : in std_logic_vector (8 downto 1);
unused : in std_logic;
AL_P : in std_logic;
AL_N : in std_logic;
AH_P : in std_logic;
AH_N : in std_logic;
BL_P : in std_logic;
BL_N : in std_logic;
BH_P : in std_logic;
BH_N : in std_logic;
LUM_P : in std_logic;
LUM_N : in std_logic;
HS_N : in std_logic;
FS_N : in std_logic
);
end;
architecture Behavioral of AtomVGAWing is
constant atomClampStart : unsigned(10 downto 0) := to_unsigned(2048 - 59 * 4 - 110, 11);
constant atomClampEnd : unsigned(10 downto 0) := to_unsigned(2048 - 59 * 4 - 10, 11);
constant atomhInit : unsigned(10 downto 0) := to_unsigned(2048 - 370, 11);
constant atomvInit : unsigned(8 downto 0) := to_unsigned(512 - 39, 9);
constant atomhBorder : unsigned(10 downto 0) := to_unsigned(2048 - 16 + 3, 11);
constant atomvBorder : unsigned(8 downto 0) := to_unsigned(512 - 25, 11);
signal atomhCounter : unsigned(10 downto 0) := (others => '0');
signal atomvCounter : unsigned(8 downto 0) := (others => '0');
signal AL0: std_logic;
signal AL1: std_logic;
signal AL2: std_logic;
signal AL3: std_logic;
signal AL4: std_logic;
signal AL5: std_logic;
signal AH0: std_logic;
signal AH1: std_logic;
signal AH2: std_logic;
signal AH3: std_logic;
signal AH4: std_logic;
signal AH5: std_logic;
signal BL0: std_logic;
signal BL1: std_logic;
signal BL2: std_logic;
signal BL3: std_logic;
signal BL4: std_logic;
signal BL5: std_logic;
signal BH0: std_logic;
signal BH1: std_logic;
signal BH2: std_logic;
signal BH3: std_logic;
signal BH4: std_logic;
signal BH5: std_logic;
signal L0: std_logic;
signal L1: std_logic;
signal L2: std_logic;
signal L3: std_logic;
signal L4: std_logic;
signal L5: std_logic;
signal AL: std_logic;
signal AH: std_logic;
signal BL: std_logic;
signal BH: std_logic;
signal L: std_logic;
signal R: std_logic;
signal G1: std_logic;
signal G2: std_logic;
signal B: std_logic;
signal atomhSync0: std_logic := '0';
signal atomhSync1: std_logic := '0';
signal atomhSync2: std_logic := '0';
signal atomhSync3: std_logic := '0';
signal atomhSync4: std_logic := '0';
signal atomhSync5: std_logic := '0';
signal atomvSync0: std_logic := '0';
signal atomvSync1: std_logic := '0';
signal atomvSync2: std_logic := '0';
signal atomvSync3: std_logic := '0';
signal atomvSync4: std_logic := '0';
signal atomvSync5: std_logic := '0';
signal atomhSync: std_logic := '0';
signal atomvSync: std_logic := '0';
signal atomvSyncToggle: std_logic := '0';
signal atomhSyncToggle: std_logic := '0';
signal clock32out : std_logic;
signal pixelClock : std_logic;
signal atomClock : std_logic;
signal tmpClock : std_logic;
signal tmpVgaClock : std_logic;
signal lockeda1 : std_logic;
signal lockeda2 : std_logic;
signal lockedb1 : std_logic;
signal lockedb2 : std_logic;
signal ramWE : std_logic := '0';
signal ramAddrA : std_logic_vector (15 downto 0) := (others => '0');
signal ramAddrB : std_logic_vector (15 downto 0) := (others => '0');
signal ramDataIn : std_logic_vector (3 downto 0) := (others => '0');
signal ramDataOut : std_logic_vector (3 downto 0) := (others => '0');
signal border : std_logic_vector (3 downto 0) := (others => '0');
signal hCounter : unsigned(10 downto 0):= (others => '0');
signal vCounter : unsigned(9 downto 0) := (others => '0');
signal hCounter1 : unsigned(10 downto 0):= (others => '0');
signal vCounter1 : unsigned(9 downto 0) := (others => '0');
-- VGA Timing constants
constant hMaxCount : natural := 800;
constant hStartData : natural := 0;
constant hEndData : natural := 512;
constant hStartBlank : natural := 576;
constant hStartSync : natural := 592;
constant hEndSync : natural := 688;
constant hEndBlank : natural := 736;
constant vMaxCount : natural := 524;
constant vStartData : natural := 0;
constant vEndData : natural := 384;
constant vStartBlank : natural := 432;
constant vStartSync : natural := 444;
constant vEndSync : natural := 446;
constant vEndBlank : natural := 476;
begin
led(1) <= NOT lockeda1;
led(2) <= NOT lockeda2;
led(3) <= NOT lockedb1;
led(4) <= NOT lockedb2;
test(1) <= atomClock;
test(2) <= atomhSync;
test(3) <= unused;
test(4) <= rst;
test(5) <= atomhSyncToggle;
test(6) <= atomvSyncToggle;
BUFG_1 : BUFG port map (
O => clock32out,
I => clock32
);
Inst_DCM_A: entity work.DCM_A port map (
CLKIN_IN => clock32out,
CLKFX_OUT => tmpVgaClock,
LOCKED_OUT => lockeda1
);
Inst_DCM_A2: entity work.DCM_A2 port map (
CLKIN_IN => tmpVgaClock,
RST_IN => NOT lockeda1,
CLKFX_OUT => pixelClock,
LOCKED_OUT => lockeda2
);
Inst_DCM_B: entity work.DCM_B port map (
CLKIN_IN => clock32out,
CLKFX_OUT => tmpClock,
LOCKED_OUT => lockedb1
);
Inst_DCM_C: entity work.DCM_C port map (
CLKIN_IN => tmpClock,
RST_IN => NOT lockedb1,
CLKFX_OUT => atomClock,
LOCKED_OUT => lockedb2
);
Inst_VideoRam: entity work.VideoRam port map (
clka => atomClock,
wea => ramWE,
addra => ramAddrA,
dina => ramDataIn,
clkb => pixelClock,
addrb => ramAddrB,
doutb => ramDataOut
);
IBUFDS_1 : IBUFDS port map (
O => AL0, -- Buffer output
I => AL_P, -- Diff_p buffer input (connect directly to top-level port)
IB => AL_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_2 : IBUFDS port map (
O => AH0, -- Buffer output
I => AH_P, -- Diff_p buffer input (connect directly to top-level port)
IB => AH_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_3 : IBUFDS port map (
O => BL0, -- Buffer output
I => BL_P, -- Diff_p buffer input (connect directly to top-level port)
IB => BL_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_4 : IBUFDS port map (
O => BH0, -- Buffer output
I => BH_P, -- Diff_p buffer input (connect directly to top-level port)
IB => BH_N -- Diff_n buffer input (connect directly to top-level port)
);
IBUFDS_5 : IBUFDS port map (
O => L0, -- Buffer output
I => LUM_P, -- Diff_p buffer input (connect directly to top-level port)
IB => LUM_N -- Diff_n buffer input (connect directly to top-level port)
);
process(atomClock)
begin
if rising_edge(atomClock) then
AL1 <= AL0;
AH1 <= AH0;
BL1 <= BL0;
BH1 <= BH0;
AL2 <= AL1;
AH2 <= AH1;
BL2 <= BL1;
BH2 <= BH1;
AL3 <= AL2;
AH3 <= AH2;
BL3 <= BL2;
BH3 <= BH2;
AL4 <= (AL1 AND AL2) OR (AL1 AND AL3) OR (AL2 AND AL3);
AH4 <= (AH1 AND AH2) OR (AH1 AND AH3) OR (AH2 AND AH3);
BL4 <= (BL1 AND BL2) OR (BL1 AND BL3) OR (BL2 AND BL3);
BH4 <= (BH1 AND BH2) OR (BH1 AND BH3) OR (BH2 AND BH3);
if (atomhcounter(2 downto 0) = unsigned(switch(7 downto 5))) then
AL5 <= AL4;
AH5 <= AH4;
BL5 <= BL4;
BH5 <= BH4;
end if;
L1 <= L0;
L2 <= L1;
L3 <= L2;
L4 <= (L1 AND L2) OR (L1 AND L3) OR (L2 AND L3);
if (atomhcounter(1 downto 0) = unsigned(switch(4 downto 3))) then
L5 <= L4;
end if;
AL <= AL5;
AH <= AH5;
BL <= BL5;
BH <= BH5;
L <= L5;
-- AL AH BL BH L R G1 G2 B
--YELLOW 1.5 1.0 0 0 1 0 X 1 1 1 0
--RED 2.0 1.5 0 1 0 0 X 1 0 1 0
--MAGENTA 2.0 2.0 0 1 0 1 X 1 0 1 1
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
R <= (NOT AL AND NOT AH AND BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L) OR (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--YELLOW 1.5 1.0 0 0 1 0 X 1 1 1 0
--CYAN 1.0 1.5 1 0 0 0 X 0 1 1 1
--GREEN 1.0 1.0 1 0 1 0 1 0 1 1 0
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
G1 <= (NOT AL AND NOT AH AND BL AND NOT BH) OR (AL AND NOT AH AND NOT BL AND NOT BH) OR (AL AND NOT AH AND BL AND NOT BH AND L) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L) OR (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--ORANGE 2.0 1.0 0 1 1 0 1 1 1 0 0
G2 <= NOT (NOT AL AND AH AND BL AND NOT BH AND L);
-- AL AH BL BH L R G1 G2 B
--BLUE 1.5 2.0 0 0 0 1 X 0 0 1 1
--CYAN 1.0 1.5 1 0 0 0 X 0 1 1 1
--MAGENTA 2.0 2.0 0 1 0 1 X 1 0 1 1
--BUFF 1.5 1.5 0 0 0 0 1 1 1 1 1
B <= (NOT AL AND NOT AH AND NOT BL AND BH) OR (AL AND NOT AH AND NOT BL AND NOT BH) OR (NOT AL AND AH AND NOT BL AND BH) OR (NOT AL AND NOT AH AND NOT BL AND NOT BH AND L);
ramDataIn <= R & G1 & G2 & B;
-- generate a 1 clock hSync signal from the falling edge of sync
atomhSync0 <= HS_N;
atomhSync1 <= NOT atomhSync0;
atomhSync2 <= atomhSync1;
atomhSync3 <= atomhSync2;
atomhSync4 <= atomhSync3;
atomhSync5 <= atomhSync4;
atomvSync0 <= FS_N;
atomvSync1 <= NOT atomvSync0;
atomvSync2 <= atomvSync1;
atomvSync3 <= atomvSync2;
atomvSync4 <= atomvSync3;
atomvSync5 <= atomvSync4;
if atomhSync5 = '1' AND atomhSync4 = '1' AND atomhSync3 = '0' AND atomhSync2 = '0' then
atomhSync <= '1';
else
atomhSync <= '0';
end if;
if atomvSync5 = '1' AND atomvSync4 = '1' AND atomvSync3 = '0' AND atomvSync2 = '0' then
atomvSync <= '1';
else
atomvSync <= '0';
end if;
-- generate
if (atomvSync = '1') then
atomvCounter <= atomvInit;
atomvSyncToggle <= NOT atomvSyncToggle;
elsif (atomhSync = '1') then
atomvCounter <= atomvCounter+1;
end if;
if (atomhSync = '1') then
atomhCounter <= atomhInit;
atomhSyncToggle <= NOT atomhSyncToggle;
else
atomhCounter <= atomhCounter+1;
end if;
ramAddrA <= std_logic_vector(atomvCounter(7 downto 0)) & std_logic_vector(atomhcounter(9 downto 2));
if (atomhcounter(1 downto 0) = unsigned(switch(2 downto 1)) AND atomhCounter < 1024 AND atomvCounter < 192) then
ramWE <= '1';
else
ramWE <= '0';
end if;
if (atomhcounter >= atomClampStart AND atomhCounter < atomClampEnd) then
clamp <= '1';
else
clamp <= '0';
end if;
if (atomhCounter = atomhBorder AND (switch(8) = '1' OR atomvCounter = atomvBorder)) then
border <= ramDataIn;
end if;
end if;
end process;
ramAddrB <= std_logic_vector(vCounter(8 downto 1)) & std_logic_vector(hcounter(8 downto 1));
process(pixelClock)
begin
if rising_edge(pixelClock) then
hsync <= '0';
vsync <= '0';
hCounter1 <= hCounter;
vCounter1 <= vCounter;
if (hCounter1 >= hStartData AND hCounter1 < hEndData AND vCounter1 >= vStartData AND vCounter1 < vEndData) then
red <= ramDataOut(3) & ramDataOut(3) & ramDataOut(3);
green <= ramDataOut(2) & (ramDataOut(2) AND ramDataOut(1)) & (ramDataOut(2) AND ramDataOut(1));
blue <= ramDataOut(0) & ramDataOut(0);
elsif (hCounter1 >= hStartBlank AND hCounter1 < hEndBlank) OR (vCounter1 >= vStartBlank AND vCounter1 < vEndBlank) then
red <= "000";
green <= "000";
blue <= "00";
else
red <= border(3) & border(3) & border(3);
green <= border(2) & (border(2) AND border(1)) & (border(2) AND border(1));
blue <= border(0) & border(0);
end if;
-- Count the lines and rows
if hCounter = (hMaxCount - 1) then
hCounter <= (others => '0');
if (vCounter = vMaxCount - 1) then
vCounter <= (others => '0');
else
vCounter <= vCounter+1;
end if;
else
hCounter <= hCounter+1;
end if;
-- Are we in the hSync pulse?
if hCounter >= hStartSync and hCounter < hEndSync then
hSync <= '1'; -- Positive hSync pulse
end if;
-- Are we in the vSync pulse?
if vCounter >= vStartSync and vCounter < vEndSync then
vSync <= '1'; -- Positive vSync pulse
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 8e0e51211253aed5d48d02d463236cd3 | 0.505625 | 3.589074 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_dadd_64ns_64ns_64_5_full_dsp.vhd | 4 | 3,380 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity feedforward_dadd_64ns_64ns_64_5_full_dsp is
generic (
ID : integer := 6;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of feedforward_dadd_64ns_64ns_64_5_full_dsp is
--------------------- Component ---------------------
component feedforward_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
feedforward_ap_dadd_3_full_dsp_64_u : component feedforward_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 78bb85d47eac55387623a0c5e0e89f83 | 0.490533 | 3.51717 | false | false | false | false |
makestuff/spi-talk | templates/fx2s3an/vhdl/top_level.vhdl | 1 | 5,257 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 downto 0); -- select FIFO: "00" for EP2OUT, "10" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2OE_out : out std_logic; -- asserted (active-low) to tell FX2LP to drive bus
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic -- asserted (active-low) when a host read needs to be committed early
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Needed so that the comm_fpga_fx2 module can drive both fx2Read_out and fx2OE_out
signal fx2Read : std_logic;
-- Reset signal so host can delay startup
signal fx2Reset : std_logic;
-- SPI signals
signal spiCS : std_logic_vector(NUM_DEVS-1 downto 0);
signal spiClk : std_logic;
signal spiDataOut : std_logic;
signal spiDataIn : std_logic;
begin
-- CommFPGA module
fx2Read_out <= fx2Read;
fx2OE_out <= fx2Read;
fx2Addr_out(0) <= -- So fx2Addr_out(1)='0' selects EP2OUT, fx2Addr_out(1)='1' selects EP6IN
'0' when fx2Reset = '0'
else 'Z';
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => fx2Reset,
-- FX2LP interface
fx2FifoSel_out => fx2Addr_out(1),
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => fx2Clk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn,
spiCS_out => spiCS
);
spi_access: spi_access
generic map(
SIM_DEVICE => "3S200AN"
)
port map(
MISO => spiDataIn, -- 1-bit SPI output data
MOSI => spiDataOut, -- 1-bit SPI input data
CSB => spiCS(0), -- 1-bit SPI chip enable
CLK => spiClk -- 1-bit SPI clock input
);
end architecture;
| gpl-3.0 | 5ff9bc45da1d6d1a7a17c6586a351b6d | 0.607 | 3.316719 | false | false | false | false |
Rookfighter/aes-ss17 | tutorial/ledblinker.vhd | 1 | 1,002 | -- ledblinker.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- LED blinker with configurable frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LED blinking module
entity ledblinker is
port (clk: in std_logic; -- clock, rising edge
led: out std_logic); -- LED status, active high
end entity ledblinker;
architecture behavioral of ledblinker is
-- define length of counter
constant CNTLEN: natural := 24;
signal cnt: std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
signal led_int: std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if unsigned(cnt) = 12000000 then
cnt <= (others => '0');
led_int <= not led_int;
else
cnt <= std_logic_vector(unsigned(cnt) + 1);
end if;
end if;
end process;
led <= led_int;
end architecture behavioral;
| gpl-3.0 | 29788df3f6c14f7a07080d0288b2ae3c | 0.57485 | 3.929412 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_p_uOut.vhd | 4 | 4,111 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity feedforward_p_uOut_ram is
generic(
mem_type : string := "block";
dwidth : integer := 32;
awidth : integer := 8;
mem_size : integer := 140
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
d0 : in std_logic_vector(dwidth-1 downto 0);
we0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of feedforward_p_uOut_ram is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
shared variable ram : mem_array;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : variable is "block_ram";
attribute ram_style : string;
attribute ram_style of ram : variable is mem_type;
attribute EQUIVALENT_REGISTER_REMOVAL : string;
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
p_memory_access_0: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
if (we0 = '1') then
ram(CONV_INTEGER(addr0_tmp)) := d0;
end if;
q0 <= ram(CONV_INTEGER(addr0_tmp));
end if;
end if;
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
p_memory_access_1: process (clk)
begin
if (clk'event and clk = '1') then
if (ce1 = '1') then
q1 <= ram(CONV_INTEGER(addr1_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_p_uOut is
generic (
DataWidth : INTEGER := 32;
AddressRange : INTEGER := 140;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_p_uOut is
component feedforward_p_uOut_ram is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR;
we0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_p_uOut_ram_U : component feedforward_p_uOut_ram
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
d0 => d0,
we0 => we0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1);
end architecture;
| gpl-3.0 | cb6a077261ce505c83ec6c515400f89c | 0.544393 | 3.516681 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_mul_7ns_32s_39_3.vhd | 3 | 2,722 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward_mul_7ns_32s_39_3_Mul3S_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(7 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(39 - 1 downto 0));
end entity;
architecture behav of feedforward_mul_7ns_32s_39_3_Mul3S_1 is
signal tmp_product : std_logic_vector(39 - 1 downto 0);
signal a_i : std_logic_vector(7 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(39 - 1 downto 0);
signal a_reg0 : std_logic_vector(7 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(39 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' & a_reg0) * signed(b_reg0))), 39));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_mul_7ns_32s_39_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_mul_7ns_32s_39_3 is
component feedforward_mul_7ns_32s_39_3_Mul3S_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_mul_7ns_32s_39_3_Mul3S_1_U : component feedforward_mul_7ns_32s_39_3_Mul3S_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 | e58d0205173b7001c5277fc8e34d532a | 0.552535 | 3.240476 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_dadd_3_full_dsp_64.vhd | 6 | 12,700 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_dadd_3_full_dsp_64;
ARCHITECTURE ANN_ap_dadd_3_full_dsp_64_arch OF ANN_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "ANN_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "ANN_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_dadd_3_full_dsp_64_arch;
| gpl-3.0 | fec2dcdab8f56fc59bc0794eff485810 | 0.649764 | 3.003074 | false | false | false | false |
mjl152/usmt_uarch | smt_ram.vhd | 1 | 9,670 | -- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- SMT dual-port RAM
-- Michael Lancaster <[email protected]>
-- 4 October 2013
library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity smt_ram is
port
(
DATA0 : in std_logic_vector(7 downto 0);
DATA1 : in std_logic_vector(7 downto 0);
ADDR0 : in std_logic_vector(7 downto 0);
ADDR1 : in std_logic_vector(7 downto 0);
SET0 : in std_logic := '0';
SET1 : in std_logic := '0';
RAM_CLOCK : in std_logic;
OUT0 : out std_logic_vector(7 downto 0);
OUT1 : out std_logic_vector(7 downto 0);
OUT2 : out std_logic_vector(7 downto 0);
OUT3 : out std_logic_vector(7 downto 0);
OUT4 : out std_logic_vector(7 downto 0);
OUT5 : out std_logic_vector(7 downto 0);
OUT6 : out std_logic_vector(7 downto 0);
OUT7 : out std_logic_vector(7 downto 0);
OUTADDR0 : in std_logic_vector(7 downto 0);
OUTADDR1 : in std_logic_vector(7 downto 0)
);
type memory_t is array (255 downto 0) of std_logic_vector(7 downto 0);
function initialize_ram return memory_t is
variable mem_temp : memory_t;
begin
mem_temp := (others => (others => '0'));
mem_temp(0) := std_logic_vector(to_signed(6, 8));
mem_temp(1) := std_logic_vector(to_signed(68, 8));
-- fibonacci program thread 0
mem_temp(4) := std_logic_vector(to_signed(3, 8));
mem_temp(5) := std_logic_vector(to_signed(69, 8));
mem_temp(6) := std_logic_vector(to_signed(70, 8));
mem_temp(7) := std_logic_vector(to_signed(71, 8));
mem_temp(8) := std_logic_vector(to_signed(2, 8));
mem_temp(9) := std_logic_vector(to_signed(69, 8));
mem_temp(10) := std_logic_vector(to_signed(70, 8));
mem_temp(11) := std_logic_vector(to_signed(71, 8));
mem_temp(12) := std_logic_vector(to_signed(4, 8));
mem_temp(13) := std_logic_vector(to_signed(72, 8));
mem_temp(14) := std_logic_vector(to_signed(73, 8));
mem_temp(17) := std_logic_vector(to_signed(73, 8));
mem_temp(18) := std_logic_vector(to_signed(74, 8));
mem_temp(19) := std_logic_vector(to_signed(73, 8));
mem_temp(20) := std_logic_vector(to_signed(4, 8));
mem_temp(21) := std_logic_vector(to_signed(74, 8));
mem_temp(22) := std_logic_vector(to_signed(72, 8));
mem_temp(25) := std_logic_vector(to_signed(69, 8));
mem_temp(26) := std_logic_vector(to_signed(75, 8));
mem_temp(27) := std_logic_vector(to_signed(69, 8));
mem_temp(28) := std_logic_vector(to_signed(5, 8));
mem_temp(29) := std_logic_vector(to_signed(76, 8));
mem_temp(32) := std_logic_vector(to_signed(7, 8));
-- factorial program thread 0
-- mem_temp(4) := std_logic_vector(to_signed(4, 8));
-- mem_temp(5) := std_logic_vector(to_signed(77, 8));
-- mem_temp(6) := std_logic_vector(to_signed(78, 8));
-- mem_temp(8) := std_logic_vector(to_signed(3, 8));
-- mem_temp(9) := std_logic_vector(to_signed(78, 8));
-- mem_temp(10) := std_logic_vector(to_signed(79, 8));
-- mem_temp(11) := std_logic_vector(to_signed(76, 8));
-- mem_temp(12) := std_logic_vector(to_signed(7, 8));
-- mem_temp(16) := std_logic_vector(to_signed(2, 8));
-- mem_temp(17) := std_logic_vector(to_signed(78, 8));
-- mem_temp(18) := std_logic_vector(to_signed(79, 8));
-- mem_temp(19) := std_logic_vector(to_signed(76, 8));
-- mem_temp(20) := std_logic_vector(to_signed(7, 8));
-- mem_temp(25) := std_logic_vector(to_signed(78, 8));
-- mem_temp(26) := std_logic_vector(to_signed(80, 8));
-- mem_temp(27) := std_logic_vector(to_signed(78, 8));
--- mem_temp(28) := std_logic_vector(to_signed(1, 8));
-- mem_temp(29) := std_logic_vector(to_signed(77, 8));
-- mem_temp(30) := std_logic_vector(to_signed(78, 8));
-- mem_temp(31) := std_logic_vector(to_signed(77, 8));
-- mem_temp(32) := std_logic_vector(to_signed(5, 8));
-- mem_temp(33) := std_logic_vector(to_signed(81, 8));
-- factorial program thread 1
-- mem_temp(36) := std_logic_vector(to_signed(4, 8));
-- mem_temp(37) := std_logic_vector(to_signed(77, 8));
-- mem_temp(38) := std_logic_vector(to_signed(78, 8));
-- mem_temp(40) := std_logic_vector(to_signed(3, 8));
-- mem_temp(41) := std_logic_vector(to_signed(78, 8));
-- mem_temp(42) := std_logic_vector(to_signed(79, 8));
-- mem_temp(43) := std_logic_vector(to_signed(76, 8));
-- mem_temp(44) := std_logic_vector(to_signed(7, 8));
--mem_temp(48) := std_logic_vector(to_signed(2, 8));
-- mem_temp(49) := std_logic_vector(to_signed(78, 8));
-- mem_temp(50) := std_logic_vector(to_signed(80, 8));
-- mem_temp(51) := std_logic_vector(to_signed(76, 8));
-- mem_temp(52) := std_logic_vector(to_signed(7, 8));
-- mem_temp(53) := std_logic_vector(to_signed(76, 8));
-- mem_temp(57) := std_logic_vector(to_signed(78, 8));
--mem_temp(58) := std_logic_vector(to_signed(80, 8));
-- mem_temp(59) := std_logic_vector(to_signed(78, 8));
-- mem_temp(60) := std_logic_vector(to_signed(1, 8));
-- mem_temp(61) := std_logic_vector(to_signed(77, 8));
-- mem_temp(62) := std_logic_vector(to_signed(78, 8));
-- mem_temp(63) := std_logic_vector(to_signed(77, 8));
-- mem_temp(64) := std_logic_vector(to_signed(5, 8));
-- mem_temp(65) := std_logic_vector(to_signed(81, 8));
-- second Fibonacci thread
mem_temp(36) := std_logic_vector(to_signed(3, 8));
mem_temp(37) := std_logic_vector(to_signed(69, 8));
mem_temp(38) := std_logic_vector(to_signed(70, 8));
mem_temp(39) := std_logic_vector(to_signed(71, 8));
mem_temp(40) := std_logic_vector(to_signed(2, 8));
mem_temp(41) := std_logic_vector(to_signed(69, 8));
mem_temp(42) := std_logic_vector(to_signed(70, 8));
mem_temp(43) := std_logic_vector(to_signed(71, 8));
mem_temp(44) := std_logic_vector(to_signed(4, 8));
mem_temp(45) := std_logic_vector(to_signed(72, 8));
mem_temp(46) := std_logic_vector(to_signed(73, 8));
mem_temp(49) := std_logic_vector(to_signed(73, 8));
mem_temp(50) := std_logic_vector(to_signed(74, 8));
mem_temp(51) := std_logic_vector(to_signed(73, 8));
mem_temp(52) := std_logic_vector(to_signed(4, 8));
mem_temp(53) := std_logic_vector(to_signed(74, 8));
mem_temp(54) := std_logic_vector(to_signed(72, 8));
mem_temp(56) := std_logic_vector(to_signed(0, 8));
mem_temp(57) := std_logic_vector(to_signed(69, 8));
mem_temp(58) := std_logic_vector(to_signed(75, 8));
mem_temp(59) := std_logic_vector(to_signed(69, 8));
mem_temp(60) := std_logic_vector(to_signed(5, 8));
mem_temp(61) := std_logic_vector(to_signed(76, 8));
mem_temp(64) := std_logic_vector(to_signed(7, 8));
-- data section
mem_temp(68) := std_logic_vector(to_signed(34, 8));
mem_temp(70) := std_logic_vector(to_signed(10, 8)); -- n
mem_temp(71) := std_logic_vector(to_signed(32, 8));
mem_temp(73) := std_logic_vector(to_signed(1, 8));
mem_temp(75) := std_logic_vector(to_signed(1, 8));
mem_temp(76) := std_logic_vector(to_signed(4, 8));
mem_temp(78) := std_logic_vector(to_signed(10, 8)); -- N
mem_temp(80) := std_logic_vector(to_signed(-1, 8));
mem_temp(81) := std_logic_vector(to_signed(36, 8));
return mem_temp;
end initialize_ram;
end smt_ram;
architecture behavioural of smt_ram is
shared variable ram : memory_t := initialize_ram;
begin
-- Port 1
process(RAM_CLOCK)
begin
if(rising_edge(RAM_CLOCK)) then
if(SET0 = '1') then
ram(to_integer(unsigned(ADDR0))) := DATA0;
end if;
end if;
end process;
-- Port 3
process(RAM_CLOCK)
begin
if(rising_edge(RAM_CLOCK)) then
if(SET1 = '1') then
ram(to_integer(unsigned(ADDR1))) := DATA1;
end if;
end if;
end process;
-- Outputs
process(RAM_CLOCK)
begin
if (rising_edge(RAM_CLOCK)) then
OUT0 <= ram(to_integer(unsigned(OUTADDR0)));
OUT1 <= ram(to_integer(unsigned(ram(to_integer(unsigned(OUTADDR0)) + 1))));
OUT2 <= ram(to_integer(unsigned(ram(to_integer(unsigned(OUTADDR0)) + 2))));
OUT3 <= ram(to_integer(unsigned(ram(to_integer(unsigned(OUTADDR0)) + 3))));
OUT4 <= ram(to_integer(unsigned(OUTADDR1)));
OUT5 <= ram(to_integer(unsigned(ram(to_integer(unsigned(OUTADDR1)) + 1))));
OUT6 <= ram(to_integer(unsigned(ram(to_integer(unsigned(OUTADDR1)) + 2))));
OUT7 <= ram(to_integer(unsigned(ram(to_integer(unsigned(OUTADDR1)) + 3))));
end if;
end process;
end behavioural;
| mit | 6e9fc508174914dd62c78ade08c51a11 | 0.615408 | 2.713244 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_fptrunc_0_no_dsp_64.vhd | 4 | 12,253 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE feedforward_ap_fptrunc_0_no_dsp_64_arch OF feedforward_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fptrunc_0_no_dsp_64_arch;
| gpl-3.0 | 68d17a2ddbc40f769ad20a806eb3202d | 0.648902 | 3.025432 | false | false | false | false |
bonfireprocessor/bonfire-soc | uart/fifo.vhd | 1 | 3,755 | --+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | [email protected] |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
--| |___/\___/ \___/___\___/ \___/ | |--
--| | http://sowerbutts.com/ |--
--+-----------------------------------+-------------------------------------+--
--| FIFO implementation with high water mark. Could be improved; currently |--
--| it is impossible to use the last byte in the FIFO (because it cannot |--
--| distinguish completely-full from completely-empty) |--
--+-------------------------------------------------------------------------+--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fifo is
generic(
depth_log2 : integer := 10; -- 5 gives 32 bytes, implements without a BRAM.
hwm_space : integer := 5; -- minimum bytes free in buffer before we assert flow control signals
width : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
write_en : in std_logic;
write_ready : out std_logic; -- is there space to write?
read_en : in std_logic;
read_ready : out std_logic; -- is there data waiting to read?
data_in : in std_logic_vector(width-1 downto 0);
data_out : out std_logic_vector(width-1 downto 0);
high_water_mark : out std_logic;
-- Debug outputs
dbg_read_ptr : out std_logic_vector(depth_log2-1 downto 0);
dbg_write_ptr : out std_logic_vector(depth_log2-1 downto 0)
);
end fifo;
architecture behaviour of fifo is
type fifo_entry is array (natural range <>) of std_logic_vector(width-1 downto 0);
signal fifo_contents : fifo_entry(0 to (2 ** depth_log2) - 1); -- this is the FIFO buffer memory
signal read_ptr : unsigned(depth_log2-1 downto 0) := (others => '0');
signal write_ptr : unsigned(depth_log2-1 downto 0) := (others => '0');
signal full : std_logic;
signal empty : std_logic;
begin
dbg_read_ptr <= std_logic_vector(read_ptr);
dbg_write_ptr <= std_logic_vector(write_ptr);
is_empty: process(read_ptr, write_ptr)
begin
if read_ptr = write_ptr then
empty <= '1';
else
empty <= '0';
end if;
if read_ptr = (write_ptr+1) then
full <= '1';
else
full <= '0';
end if;
if (write_ptr - read_ptr) >= ((2 ** depth_log2) - 1 - hwm_space) then
high_water_mark <= '1';
else
high_water_mark <= '0';
end if;
end process;
fifo_update: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- reset
read_ptr <= to_unsigned(0, depth_log2);
write_ptr <= to_unsigned(0, depth_log2);
else
-- normal operation
if write_en = '1' and full = '0' then
fifo_contents(to_integer(write_ptr)) <= data_in;
write_ptr <= write_ptr + 1;
end if;
if read_en = '1' and empty = '0' then
read_ptr <= read_ptr + 1;
end if;
data_out <= fifo_contents(to_integer(read_ptr));
end if;
end if;
end process;
write_ready <= not full;
read_ready <= not empty;
end;
| gpl-3.0 | 6234ecb72f91687b640392b3790f2ff4 | 0.455925 | 3.919624 | false | false | false | false |
bonfireprocessor/bonfire-soc | papilio_pro_dram_toplevel.vhd | 1 | 16,898 | ----------------------------------------------------------------------------------
-- Module Name: papilio_pro_dram_toplevel - Behavioral
-- The Bonfire Processor Project, (c) 2016,2017 Thomas Hornschuh
-- Toplevel module for Papilio Pro with 8MB SDRAM
-- License: See LICENSE or LICENSE.txt File in git project root.
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity papilio_pro_dram_toplevel is
generic (
RamFileName : string; -- :="compiled_code/monitor.hex";
mode : string := "H"; -- only used when UseBRAMPrimitives is false
Swapbytes : boolean := true; -- SWAP Bytes in RAM word in low byte first order to use data2mem
FakeDRAM : boolean := false; -- Use Block RAM instead of DRAM
BurstSize : natural := 8;
CacheSizeWords : natural := 2048; -- 8KB Instruction Cache
EnableDCache : boolean := true;
DCacheSizeWords : natural := 2048;
MUL_ARCH: string := "spartandsp";
REG_RAM_STYLE : string := "block";
NUM_GPIO_A : natural := 8;
NUM_GPIO_C : natural := 8;
NUM_GPIO_B : natural := 4
);
port(
sysclk_32m : in std_logic;
I_RESET : in std_logic;
-- GPIOs:
-- 4x LEDs on Arcade Megawing
--leds : out std_logic_vector(3 downto 0);
-- UART0 signals:
uart0_txd : out std_logic;
uart0_rxd : in std_logic :='1';
-- UART1 signals:
uart1_txd : out std_logic;
uart1_rxd : in std_logic :='1';
-- SPI flash chip
flash_spi_cs : out std_logic;
flash_spi_clk : out std_logic;
flash_spi_mosi : out std_logic;
flash_spi_miso : in std_logic;
-- LED on Papilio Pro Board
led1 : out std_logic;
-- GPIO pads - assign with UCF File
WING_A : inout STD_LOGIC_VECTOR(NUM_GPIO_A-1 downto 0);
WING_B : inout STD_LOGIC_VECTOR(NUM_GPIO_B-1 downto 0);
WING_C : inout STD_LOGIC_VECTOR(NUM_GPIO_C-1 downto 0);
-- Software I2C
SCL : inout STD_LOGIC;
SDA : inout STD_LOGIC;
-- SDRAM signals
SDRAM_CLK : out STD_LOGIC;
SDRAM_CKE : out STD_LOGIC;
SDRAM_CS : out STD_LOGIC;
SDRAM_RAS : out STD_LOGIC;
SDRAM_CAS : out STD_LOGIC;
SDRAM_WE : out STD_LOGIC;
SDRAM_DQM : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_ADDR : out STD_LOGIC_VECTOR(12 downto 0);
SDRAM_BA : out STD_LOGIC_VECTOR( 1 downto 0);
SDRAM_DATA : inout STD_LOGIC_VECTOR(15 downto 0)
);
end papilio_pro_dram_toplevel;
architecture Behavioral of papilio_pro_dram_toplevel is
constant ram_adr_width : natural := 13;
constant ram_size : natural := 8192;
constant reset_adr : std_logic_vector(31 downto 0) :=X"0C000000";
signal clk32Mhz, -- buffered osc clock
clk, -- logical CPU clock
uart_clk : std_logic;
signal reset,res1,res2 : std_logic;
-- Instruction Bus Master from CPU
signal ibus_cyc_o: std_logic;
signal ibus_stb_o: std_logic;
signal ibus_cti_o: std_logic_vector(2 downto 0);
signal ibus_bte_o: std_logic_vector(1 downto 0);
signal ibus_ack_i: std_logic;
signal ibus_adr_o: std_logic_vector(29 downto 0);
signal ibus_dat_i: std_logic_vector(31 downto 0);
-- Data Bus Master from CPU
signal dbus_cyc_o : std_logic;
signal dbus_stb_o : std_logic;
signal dbus_we_o : std_logic;
signal dbus_sel_o : std_logic_vector(3 downto 0);
signal dbus_adr_o : std_logic_vector(31 downto 2);
signal dbus_dat_o : std_logic_vector(31 downto 0);
signal dbus_ack_i : std_logic;
signal dbus_dat_i : std_logic_vector(31 downto 0);
--signal dbus_cti_o: std_logic_vector(2 downto 0);
--signal dbus_bte_o: std_logic_vector(1 downto 0);
-- Slaves
constant slave_adr_high : natural := 25;
-- Common bus to DRAM controller
signal mem_cyc,mem_stb,mem_we,mem_ack : std_logic;
signal mem_sel : std_logic_vector(3 downto 0);
signal mem_dat_rd,mem_dat_wr : std_logic_vector(31 downto 0);
signal mem_adr : std_logic_vector(slave_adr_high downto 2);
signal mem_cti : std_logic_vector(2 downto 0);
-- Data bus to DRAM
signal dbmem_cyc,dbmem_stb,dbmem_we,dbmem_ack : std_logic;
signal dbmem_sel : std_logic_vector(3 downto 0);
signal dbmem_dat_rd,dbmem_dat_wr : std_logic_vector(31 downto 0);
signal dbmem_adr : std_logic_vector(slave_adr_high downto 2);
signal dbmem_cti : std_logic_vector(2 downto 0);
-- "CPU" Side of Data Cache
signal dcm_cyc,dcm_stb,dcm_we,dcm_ack : std_logic;
signal dcm_sel : std_logic_vector(3 downto 0);
signal dcm_dat_rd,dcm_dat_wr : std_logic_vector(31 downto 0);
signal dcm_adr : std_logic_vector(slave_adr_high downto 2);
signal dcm_cti : std_logic_vector(2 downto 0);
signal dcm_bte : std_logic_vector(1 downto 0);
--I/O Bus
signal io_cyc,io_stb,io_we,io_ack : std_logic;
signal io_sel : std_logic_vector(3 downto 0);
signal io_dat_rd,io_dat_wr : std_logic_vector(31 downto 0);
signal io_adr : std_logic_vector(slave_adr_high downto 2);
-- Interface to dual port Block RAM
-- Port A R/W, Byte Level Access, for Data
signal bram_dba_i : std_logic_vector(31 downto 0);
signal bram_dba_o : std_logic_vector(31 downto 0);
signal bram_adra_o : std_logic_vector(ram_adr_width-1 downto 0);
signal bram_ena_o : std_logic;
signal bram_wrena_o :std_logic_vector (3 downto 0);
-- Port B Read Only, Word level access, for Code
signal bram_dbb_i : std_logic_vector(31 downto 0);
signal bram_adrb_o : std_logic_vector(ram_adr_width-1 downto 0);
signal bram_enb_o : std_logic;
-- gpio ports
constant SPECIAL_GPIO : natural := 3; -- LED1 + SDA + SCL
constant TOTAL_GPIO : natural := NUM_GPIO_A + NUM_GPIO_B +
NUM_GPIO_C + SPECIAL_GPIO;
-- GPIO module will always be configured with all 32 Bits
signal gpio_t,gpio_o,gpio_i : std_logic_vector(31 downto 0);
signal irq_i : std_logic_vector(7 downto 0);
COMPONENT clkgen
PORT(
clkin : IN std_logic;
rstin : IN std_logic;
clkout : OUT std_logic;
clkout1 : OUT std_logic;
clkout2 : OUT std_logic;
clk32Mhz_out : OUT std_logic;
rstout : OUT std_logic
);
END COMPONENT;
signal clkgen_rst: std_logic;
begin
assert TOTAL_GPIO <= 32
report "Total number of gpio ports cannot exceed 32"
severity failure;
-- Assignment of IOBs for GPIO
-- LED will be the highest bit of the gpio core
led_pad: OBUF
port map(
I => gpio_o(31),
O => led1
);
scl_pad : IOBUF
port map(
I => gpio_o(30),
O => gpio_i(30),
T => gpio_t(30),
IO => SCL
);
sda_pad : IOBUF
port map(
I => gpio_o(29),
O => gpio_i(29),
T => gpio_t(29),
IO => SDA
);
wing_a_pads: for i in WING_A'range generate
pad : IOBUF
port map (
O => gpio_i(i), -- Buffer output
IO => WING_A(i), -- Buffer inout port (connect directly to top-level port)
I => gpio_o(i), -- Buffer input
T => gpio_t(i) -- 3-state enable input, high=input, low=output
);
end generate;
wing_b_pads: for i in WING_B'range generate
pad : IOBUF
port map (
O => gpio_i(i+WING_A'length), -- Buffer output
IO => WING_B(i), -- Buffer inout port (connect directly to top-level port)
I => gpio_o(i+WING_A'length), -- Buffer input
T => gpio_t(i+WING_A'length) -- 3-state enable input, high=input, low=output
);
end generate;
wing_c_pads: for i in WING_C'range generate
pad : IOBUF
port map (
O => gpio_i(i+WING_A'length+WING_B'length), -- Buffer output
IO => WING_C(i), -- Buffer inout port (connect directly to top-level port)
I => gpio_o(i+WING_A'length+WING_B'length), -- Buffer input
T => gpio_t(i+WING_A'length+WING_B'length) -- 3-state enable input, high=input, low=output
);
end generate;
cpu_top: entity work.bonfire_cpu_top
generic map (
MUL_ARCH => MUL_ARCH,
REG_RAM_STYLE => REG_RAM_STYLE,
START_ADDR => reset_adr(31 downto 2),
CACHE_LINE_SIZE_WORDS =>BurstSize,
CACHE_SIZE_WORDS=>CacheSizeWords,
BRAM_PORT_ADR_SIZE=>ram_adr_width,
ENABLE_TIMER=>true
)
PORT MAP(
clk_i => clk,
rst_i => reset,
bram_dba_i => bram_dba_i,
bram_dba_o => bram_dba_o,
bram_adra_o => bram_adra_o,
bram_ena_o => bram_ena_o,
bram_wrena_o => bram_wrena_o,
bram_dbb_i => bram_dbb_i,
bram_adrb_o => bram_adrb_o,
bram_enb_o => bram_enb_o,
wb_ibus_cyc_o => ibus_cyc_o ,
wb_ibus_stb_o => ibus_stb_o,
wb_ibus_cti_o => ibus_cti_o,
wb_ibus_bte_o => ibus_bte_o,
wb_ibus_ack_i => ibus_ack_i,
wb_ibus_adr_o => ibus_adr_o,
wb_ibus_dat_i => ibus_dat_i,
wb_dbus_cyc_o => dbus_cyc_o,
wb_dbus_stb_o => dbus_stb_o,
wb_dbus_we_o => dbus_we_o,
wb_dbus_sel_o => dbus_sel_o,
wb_dbus_ack_i => dbus_ack_i,
wb_dbus_adr_o => dbus_adr_o,
wb_dbus_dat_o => dbus_dat_o,
wb_dbus_dat_i => dbus_dat_i,
irq_i => irq_i
);
ram: entity work.MainMemory
generic map (
ADDR_WIDTH =>ram_adr_width,
SIZE => ram_size,
RamFileName => RamFileName,
mode => mode,
Swapbytes => Swapbytes,
EnableSecondPort => true
)
PORT MAP(
DBOut => bram_dba_i,
DBIn => bram_dba_o,
AdrBus => bram_adra_o,
ENA => bram_ena_o,
WREN => bram_wrena_o,
CLK => clk,
CLKB => clk,
ENB => bram_enb_o,
AdrBusB => bram_adrb_o,
DBOutB => bram_dbb_i
);
simulate_dram: if FakeDRAM generate
DRAM: entity work.wbs_memory_interface
GENERIC MAP (
ram_adr_width => 12,
ram_size => 4096,
RamFileName => RamFileName,
mode => mode,
wbs_adr_high => slave_adr_high,
Swapbytes => Swapbytes
)
PORT MAP(
clk_i =>clk ,
rst_i => reset,
wbs_cyc_i => mem_cyc,
wbs_stb_i => mem_stb,
wbs_we_i => mem_we,
wbs_sel_i => mem_sel,
wbs_ack_o => mem_ack,
wbs_adr_i => mem_adr,
wbs_dat_i => mem_dat_wr,
wbs_dat_o => mem_dat_rd,
wbs_cti_i => mem_cti
);
end generate;
dram: if not FakeDRAM generate
DRAM: entity work.wbs_sdram_interface
generic map (
wbs_adr_high => mem_adr'high,
wbs_burst_length => BurstSize
)
PORT MAP(
clk_i =>clk ,
rst_i => reset,
wbs_cyc_i => mem_cyc,
wbs_stb_i => mem_stb,
wbs_we_i => mem_we,
wbs_sel_i => mem_sel,
wbs_ack_o => mem_ack,
wbs_adr_i => mem_adr,
wbs_dat_i => mem_dat_wr,
wbs_dat_o => mem_dat_rd,
wbs_cti_i => mem_cti,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CS => SDRAM_CS,
SDRAM_RAS => SDRAM_RAS,
SDRAM_CAS => SDRAM_CAS,
SDRAM_WE => SDRAM_WE,
SDRAM_DQM => SDRAM_DQM,
SDRAM_ADDR => SDRAM_ADDR,
SDRAM_BA => SDRAM_BA,
SDRAM_DATA => SDRAM_DATA
);
end generate;
inst_busconnect: entity work.cpu_dbus_connect PORT MAP(
clk_i => clk,
rst_i => reset,
-- Data bus
s0_cyc_i => dbus_cyc_o,
s0_stb_i => dbus_stb_o,
s0_we_i => dbus_we_o,
s0_sel_i => dbus_sel_o,
s0_ack_o => dbus_ack_i,
s0_adr_i => dbus_adr_o,
s0_dat_i => dbus_dat_o,
s0_dat_o => dbus_dat_i,
-- DRAM at address 0x00000000-0x03FFFFFF
m0_cyc_o => dbmem_cyc,
m0_stb_o => dbmem_stb,
m0_we_o => dbmem_we,
m0_sel_o => dbmem_sel,
m0_ack_i => dbmem_ack,
m0_adr_o => dbmem_adr,
m0_dat_o => dbmem_dat_wr,
m0_dat_i => dbmem_dat_rd,
--IO Space : 0x04000000-0x07FFFFF (Decode 0000 01)
m1_cyc_o => io_cyc,
m1_stb_o => io_stb,
m1_we_o => io_we,
m1_sel_o => io_sel,
m1_ack_i => io_ack,
m1_adr_o => io_adr,
m1_dat_o => io_dat_wr,
m1_dat_i => io_dat_rd
);
no_dcache: if not EnableDCache generate
dcm_cyc <= dbmem_cyc;
dcm_stb <= dbmem_stb;
dcm_adr <= dbmem_adr;
dcm_we <= dbmem_we;
dcm_sel <= dbmem_sel;
dcm_cti <= "000";
dcm_bte <= "00";
dcm_adr <= dbmem_adr;
dcm_dat_wr <= dbmem_dat_wr;
dbmem_dat_rd <= dcm_dat_rd;
dbmem_ack <=dcm_ack;
end generate;
dache: if EnableDCache generate
assert DCacheSizeWords=2048
report "Due to XST synthesis bugs DCache Size will be hard coded to 2048*32Bit (8KByte)"
severity warning;
Inst_bonfire_dcache: entity work.bonfire_dcache
GENERIC MAP (
MASTER_DATA_WIDTH => 32,
LINE_SIZE => BurstSize,
CACHE_SIZE => 2048, -- hard coded currently
ADDRESS_BITS => dcm_adr'length,
DEVICE_FAMILY => "SPARTAN6" -- hard coded work around...
)
PORT MAP(
clk_i => clk,
rst_i => reset,
wbs_cyc_i => dbmem_cyc,
wbs_stb_i => dbmem_stb,
wbs_we_i => dbmem_we,
wbs_sel_i => dbmem_sel,
wbs_ack_o => dbmem_ack,
wbs_adr_i => dbmem_adr,
wbs_dat_o => dbmem_dat_rd,
wbs_dat_i => dbmem_dat_wr,
wbm_cyc_o => dcm_cyc,
wbm_stb_o => dcm_stb,
wbm_we_o => dcm_we,
wbm_cti_o => dcm_cti,
wbm_bte_o => dcm_bte,
wbm_sel_o => dcm_sel,
wbm_ack_i => dcm_ack,
wbm_adr_o => dcm_adr,
wbm_dat_i => dcm_dat_rd,
wbm_dat_o => dcm_dat_wr
);
end generate;
-- Combine Dbus and ibus mem masters to one for interface to DRAM
Inst_dram_arbiter: entity work.dram_arbiter PORT MAP(
clk_i => clk,
rst_i => reset,
-- DBUS has higher prio
s0_cyc_i => dcm_cyc,
s0_stb_i => dcm_stb,
s0_we_i => dcm_we,
s0_sel_i => dcm_sel,
s0_cti_i => dcm_cti,
s0_bte_i => dcm_bte,
s0_ack_o => dcm_ack,
s0_adr_i => dcm_adr,
s0_dat_i => dcm_dat_wr,
s0_dat_o => dcm_dat_rd,
-- IBUS
s1_cyc_i => ibus_cyc_o ,
s1_stb_i => ibus_stb_o,
s1_we_i => '0',
s1_sel_i => "1111",
s1_cti_i => ibus_cti_o,
s1_bte_i => ibus_bte_o,
s1_ack_o => ibus_ack_i,
s1_adr_i => ibus_adr_o(ibus_adr_o'low+23 downto ibus_adr_o'low),
s1_dat_i => (others=>'0'),
s1_dat_o => ibus_dat_i,
-- Interace to memory controller
m0_cyc_o => mem_cyc,
m0_stb_o => mem_stb,
m0_we_o => mem_we,
m0_sel_o => mem_sel,
m0_cti_o => mem_cti,
m0_bte_o => open,
m0_ack_i => mem_ack,
m0_adr_o => mem_adr,
m0_dat_o => mem_dat_wr,
m0_dat_i => mem_dat_rd
);
Inst_bonfire_soc_io: entity work.bonfire_soc_io
GENERIC MAP (
NUM_GPIO_BITS => gpio_o'length,
ADR_HIGH => io_adr'high
)
PORT MAP(
uart0_txd => uart0_txd,
uart0_rxd => uart0_rxd,
uart1_txd => uart1_txd,
uart1_rxd => uart1_rxd,
gpio_o => gpio_o ,
gpio_i => gpio_i,
gpio_t => gpio_t,
flash_spi_cs => flash_spi_cs,
flash_spi_clk => flash_spi_clk,
flash_spi_mosi => flash_spi_mosi,
flash_spi_miso => flash_spi_miso,
irq_o => irq_i,
clk_i => clk,
rst_i => reset,
wb_cyc_i => io_cyc,
wb_stb_i => io_stb,
wb_we_i => io_we,
wb_sel_i => io_sel,
wb_ack_o => io_ack,
wb_adr_i => io_adr,
wb_dat_i => io_dat_wr,
wb_dat_o => io_dat_rd
);
-- Clock
clkgen_inst: clkgen
port map (
clkin => clk32Mhz,
rstin => '0' ,
clkout => clk,
clkout1 => open,
clkout2 => open,
clk32Mhz_out => open,
rstout => clkgen_rst
);
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clk32Mhz,
I => sysclk_32m);
process(clk) begin
if rising_edge(clk) then
res1<= I_RESET;
res2 <= res1;
end if;
end process;
reset <= res2 or clkgen_rst;
end Behavioral;
| gpl-3.0 | 1a04a5db917f3f4e33c3a900e8b5a6a1 | 0.542964 | 3.106821 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_fptrunc_64ns_32_1.vhd | 1 | 1,942 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fptrunc_64ns_32_1 is
generic (
ID : integer := 3;
NUM_STAGE : integer := 1;
din0_WIDTH : integer := 64;
dout_WIDTH : integer := 32
);
port (
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fptrunc_64ns_32_1 is
--------------------- Component ---------------------
component ANN_ap_fptrunc_0_no_dsp_64 is
port (
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fptrunc_0_no_dsp_64_u : component ANN_ap_fptrunc_0_no_dsp_64
port map (
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0;
dout <= r_tdata;
end architecture;
| gpl-3.0 | 9946a615af4e25ab8298eaad6965e09d | 0.490731 | 3.65725 | false | false | false | false |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_sitofp_4_no_dsp_32/synth/ANN_ap_sitofp_4_no_dsp_32.vhd | 1 | 12,393 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_sitofp_4_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_sitofp_4_no_dsp_32;
ARCHITECTURE ANN_ap_sitofp_4_no_dsp_32_arch OF ANN_ap_sitofp_4_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_sitofp_4_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_sitofp_4_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_sitofp_4_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_sitofp_4_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=1,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=0,C_B_WIDTH=32,C_B_FRACTION_WIDTH=0,C_C_WIDTH=32,C_C_FRACTION_WIDTH=0,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=4,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 1,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 0,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 0,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 0,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 4,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_sitofp_4_no_dsp_32_arch;
| gpl-3.0 | 371a3f0033fecb1dbfcfa46d684e5667 | 0.647704 | 3.00801 | false | false | false | false |
airlog/vhdl-rc4 | src/rc4_key_loader_tb.vhd | 1 | 4,149 |
--
-- TODO: zapelnianie pamieci klucza, asercja
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
ENTITY rc4_key_loader_tb IS
END rc4_key_loader_tb;
ARCHITECTURE behavior OF rc4_key_loader_tb IS
component rc4_key_loader
generic (
width: integer := 8;
key_width: integer := 8
);
port (
input : IN std_logic_vector((width - 1) downto 0);
input_ctrl: in std_logic;
input_stop : IN std_logic;
go : IN std_logic;
clk : IN std_logic;
key_ctrl : OUT std_logic;
key_index : OUT std_logic_vector((key_width - 1) downto 0);
key_output : OUT std_logic_vector((width - 1) downto 0);
key_len_ctrl : OUT std_logic;
key_len_output : OUT std_logic_vector((key_width - 1) downto 0);
rdy : OUT std_logic
);
END COMPONENT;
constant width : integer := 8;
constant key_width : integer := 8;
--Inputs
signal input : std_logic_vector((width - 1) downto 0) := (others => '0');
signal input_ctrl : std_logic;
signal input_stop : std_logic := '0';
signal go : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal key_ctrl : std_logic;
signal key_index : std_logic_vector((width - 1) downto 0);
signal key_output : std_logic_vector((width - 1) downto 0);
signal key_len_ctrl : std_logic;
signal key_len_output : std_logic_vector((width - 1) downto 0);
signal rdy : std_logic;
-- constants
constant clk_period : time := 10 ns;
constant keymemsize : integer := 2 ** width;
constant realkeylen : integer := 8;
-- types
subtype rc4int is integer range 0 to (2 ** width) - 1;
type rc4keymem is array (0 to keymemsize - 1) of rc4int;
-- variables
shared variable keymem : rc4keymem := (others => 0);
shared variable keylen : integer := 0;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: rc4_key_loader
generic map (
width => width,
key_width => key_width
)
port map (
input => input,
input_ctrl => input_ctrl,
input_stop => input_stop,
go => go,
clk => clk,
key_ctrl => key_ctrl,
key_index => key_index,
key_output => key_output,
key_len_ctrl => key_len_ctrl,
key_len_output => key_len_output,
rdy => rdy
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
keymem_proc: process(key_ctrl, key_index, key_output)
begin
if key_ctrl = '1' then
keymem(conv_integer(unsigned(key_index))) := conv_integer(unsigned(key_output));
end if;
end process;
keylen_proc: process(key_len_ctrl, key_len_output)
begin
if key_len_ctrl = '1' then
keylen := conv_integer(unsigned(key_len_output));
end if;
end process;
-- Stimulus process
stim_proc: process
type key_array is array (0 to realkeylen - 1) of rc4int;
variable key : key_array := (
16#FA#, 16#EB#, 16#DC#, 16#00#,
16#19#, 16#28#, 16#37#, 16#46#
);
begin
-- hold reset state for 100 ns.
wait for 100 ns;
input_ctrl <= '0';
go <= '1';
-- poczekaj az urzadzenie bedzie gotowe
while rdy = '0' loop
wait for clk_period;
end loop;
-- wprowadzanie danych
for i in 0 to realkeylen - 1 loop
input_ctrl <= '1';
input <= conv_std_logic_vector(key(i), key_width);
wait for clk_period;
end loop;
go <= '0';
input_stop <= '1';
input_stop <= '0' after clk_period;
-- poczekaj az urzadzenie ustawi wartosc klucza (zakonczy prace)
while key_len_ctrl = '0' loop
wait for clk_period;
end loop;
wait for clk_period;
-- sprawdzenie dlugosci klucza
assert (keylen = 8)
report "Otrzymano zly rozmiar klucza!"
severity failure;
-- sprawdzenie pamieci klucza po zakonczeniu czytania
for i in 0 to keymemsize - 1 loop
if i >= keylen then
assert (keymem(i) = 0)
report "Klucz zosta³ zle wczytany!"
severity failure;
else
assert (keymem(i) = key(i))
report "Klucz zosta³ zle wczytany!"
severity failure;
end if;
end loop;
wait;
end process;
END;
| mit | 6391777768a8bc722fb4b434b598e499 | 0.614124 | 2.887265 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_fdiv_32ns_32ns_32_16.vhd | 7 | 3,322 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fdiv_32ns_32ns_32_16 is
generic (
ID : integer := 2;
NUM_STAGE : integer := 16;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fdiv_32ns_32ns_32_16 is
--------------------- Component ---------------------
component ANN_ap_fdiv_14_no_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fdiv_14_no_dsp_32_u : component ANN_ap_fdiv_14_no_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | bb96625586c6e36bd5d84ca608ff2a68 | 0.482842 | 3.485834 | false | false | false | false |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/vhdl/project.srcs/sources_1/ip/ANN_ap_dadd_3_full_dsp_64/synth/ANN_ap_dadd_3_full_dsp_64.vhd | 1 | 12,694 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_dadd_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_dadd_3_full_dsp_64;
ARCHITECTURE ANN_ap_dadd_3_full_dsp_64_arch OF ANN_ap_dadd_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_dadd_3_full_dsp_64_arch : ARCHITECTURE IS "ANN_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_dadd_3_full_dsp_64_arch: ARCHITECTURE IS "ANN_ap_dadd_3_full_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_dadd_3_full_dsp_64_arch;
| gpl-3.0 | ef948d6889f8f35915928c815566583b | 0.649598 | 3.003075 | false | false | false | false |
bonfireprocessor/bonfire-soc | spi/spimaster.vhd | 1 | 6,908 | --+-----------------------------------+-------------------------------------+--
--| ___ ___ | (c) 2013-2014 William R Sowerbutts |--
--| ___ ___ ___ ___( _ ) / _ \ | [email protected] |--
--| / __|/ _ \ / __|_ / _ \| | | | | |--
--| \__ \ (_) | (__ / / (_) | |_| | | A Z80 FPGA computer, just for fun |--
--| |___/\___/ \___/___\___/ \___/ | |--
--| | http://sowerbutts.com/ |--
--+-----------------------------------+-------------------------------------+--
--| A rudimentary SPI master peripheral |--
--+-------------------------------------------------------------------------+--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spimaster is
port ( clk : in std_logic;
reset : in std_logic;
cpu_address : in std_logic_vector(2 downto 0);
cpu_wait : out std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
enable : in std_logic;
req_read : in std_logic;
req_write : in std_logic;
slave_cs : out std_logic;
slave_clk : out std_logic;
slave_mosi : out std_logic;
slave_miso : in std_logic
);
end spimaster;
-- registers:
-- base+0 -- chip select control; bit 0 is slave_cs
-- base+1 -- status register; bit 0 indicates "transmitter busy"
-- base+2 -- transmitter: write a byte here, starts SPI bus transaction
-- base+3 -- receiver: last byte received (updated on each transation)
-- base+4 -- clock divider: clk counts from 0 to whatever is in this register before proceeding
--
-- Note that if an SPI transfer is underway already the CPU will be
-- forced to wait until it completes before any register can be
-- read or written. This is very convenient as it means you can
-- just read or write bytes without checking the status register.
architecture Behavioral of spimaster is
-- start up in idle state
signal slave_cs_register : std_logic := '1';
signal slave_clk_register : std_logic := '1';
signal slave_mosi_register: std_logic := '0';
signal data_out_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal data_in_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal busy_sr : std_logic_vector(7 downto 0) := (others => '0'); -- shifted left ie MSB <- LSB
signal clk_divide_target : unsigned(7 downto 0) := (others => '0');
signal clk_divide_value : unsigned(7 downto 0) := (others => '0');
signal cpu_was_idle : std_logic := '1';
-- cpu visible registers
signal chip_select_out : std_logic_vector(7 downto 0);
signal status_data_out : std_logic_vector(7 downto 0);
signal data_out_enable : std_logic;
begin
chip_select_out <= "0000000" & slave_cs_register;
status_data_out <= "0000000" & busy_sr(7);
cpu_wait <= busy_sr(7);
--TH: Added logic to expose data to bus only when it is really needed
-- I think it wastes energy when uneccesary signal value changes are avoided
data_out_enable <= req_read and not busy_sr(7);
with cpu_address&data_out_enable select
data_out <=
chip_select_out when "0001",
status_data_out when "0011",
data_out_sr when "0101",
data_in_sr when "0111",
std_logic_vector(clk_divide_target) when "1001",
(others=>'0') when others;
slave_cs <= slave_cs_register;
slave_clk <= slave_clk_register;
slave_mosi <= slave_mosi_register;
spimaster_proc: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
slave_cs_register <= '1';
slave_clk_register <= '1';
slave_mosi_register <= '0';
data_out_sr <= (others => '0');
data_in_sr <= (others => '0');
busy_sr <= (others => '0');
clk_divide_target <= (others => '0');
clk_divide_value <= (others => '0');
cpu_was_idle <= '1';
else
-- divide down input clk to get 2 * spi clk
clk_divide_value <= clk_divide_value + 1;
if clk_divide_value = clk_divide_target then
clk_divide_value <= to_unsigned(0, 8);
end if;
if busy_sr(7) = '1' then
if clk_divide_value = clk_divide_target then
-- we're in the midst of a transaction! whoo!
if slave_clk_register = '1' then
-- clk is high; next cycle will be falling edge of clk
slave_clk_register <= '0';
slave_mosi_register <= data_out_sr(7);
-- shift data out
data_out_sr <= data_out_sr(6 downto 0) & '0';
else
-- clk is low; next cycle will be rising edge of clk
slave_clk_register <= '1';
-- shift busy
busy_sr <= busy_sr(6 downto 0) & '0';
-- latch data in
data_in_sr <= data_in_sr(6 downto 0) & slave_miso;
end if;
end if;
end if;
if enable = '1' and req_write = '1' then
if busy_sr(7) = '0' and cpu_was_idle = '1' then
cpu_was_idle <= '0';
case cpu_address is
when "000" =>
slave_cs_register <= data_in(0);
when "010" =>
-- only allow writes when transmitter is idle
data_out_sr <= data_in;
busy_sr <= (others => '1');
when "100" =>
clk_divide_target <= unsigned(data_in);
when others => -- no change
end case;
else
cpu_was_idle <= cpu_was_idle;
end if;
else
cpu_was_idle <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | b1ec2139c3dcdb0ad91bf5318585ec8c | 0.437174 | 4.350126 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fmul_2_max_dsp_32.vhd | 6 | 12,689 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
| gpl-3.0 | 27f73892210591fb57a52c312a1b24d6 | 0.64946 | 3.000473 | false | false | false | false |
bonfireprocessor/bonfire-soc | vhdl_util/txt_util.vhd | 1 | 15,096 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library ieee;
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
library std;
use std.textio.all;
package txt_util is
subtype t_byte is std_logic_vector(7 downto 0);
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- converts a characters ASCII code to a byte (std_logic_vector 7 downto 0)
function char_to_ascii_byte(c: character) return t_byte;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 20);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
function char_to_ascii_byte(c: character) return t_byte is
begin
return std_logic_vector(to_unsigned(character'pos(c),8));
end;
end txt_util;
| gpl-3.0 | ede27d5dc0465e80f6d241033824b16a | 0.482909 | 3.799648 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_ddiv_64ns_64ns_64_31.vhd | 6 | 3,322 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_ddiv_64ns_64ns_64_31 is
generic (
ID : integer := 8;
NUM_STAGE : integer := 31;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_ddiv_64ns_64ns_64_31 is
--------------------- Component ---------------------
component ANN_ap_ddiv_29_no_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_ddiv_29_no_dsp_64_u : component ANN_ap_ddiv_29_no_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | c54cb9e149eea526a3d0977c0f4d7fa4 | 0.482842 | 3.485834 | false | false | false | false |
yahniukov/AES-128_VHDL | Design Sources/Encryption_Module.vhd | 1 | 7,931 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Encryption_Module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( cypher_text : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish_round : out STD_LOGIC;
plain_text : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
key : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
clock : in STD_LOGIC;
reset : in STD_LOGIC;
start_round : in STD_LOGIC;
current_round : in integer range 0 to 11
);
end Encryption_Module;
architecture RTL of Encryption_Module is
-----------------------------
---------- SIGNALS ----------
-----------------------------
-- Signal that store current round
signal round : integer;
-- Signal that module done work
signal finish : std_logic;
-- Current key
signal current_key : std_logic_vector (DATA_LENGTH-1 downto 0);
-- Registers to store:
signal result_register_bank : std_logic_vector (DATA_LENGTH-1 downto 0);
-- Signals to start general blocks
signal start_subbytes_module : std_logic;
signal start_shiftrows_module : std_logic;
signal start_mixcolumns_module : std_logic;
signal start_addroundkey_module : std_logic;
-- Signals that block finished work
signal finish_subbytes_module : std_logic;
signal finish_shiftrows_module : std_logic;
signal finish_mixcolumns_module : std_logic;
signal finish_addroundkey_module : std_logic;
-- Signals thats store state between the components
signal to_subbytes_module : std_logic_vector (DATA_LENGTH-1 downto 0);
signal from_subbytes_module : std_logic_vector (DATA_LENGTH-1 downto 0);
signal to_shiftrows_module : std_logic_vector (DATA_LENGTH-1 downto 0);
signal from_shiftrows_module : std_logic_vector (DATA_LENGTH-1 downto 0);
signal to_mixcolumns_module : std_logic_vector (DATA_LENGTH-1 downto 0);
signal from_mixcolumns_module : std_logic_vector (DATA_LENGTH-1 downto 0);
signal to_addroundkey_module : std_logic_vector (DATA_LENGTH-1 downto 0);
signal from_addroundkey_module : std_logic_vector (DATA_LENGTH-1 downto 0);
-----------------------------
--------- COMPONENTS --------
-----------------------------
component SubBytes_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
start : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC);
end component;
component ShiftRows_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
start : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC);
end component;
component MixColumns_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
start : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC);
end component;
component AddRoundKey_module is
Generic ( DATA_LENGTH : integer := 128 );
Port ( data_out : out STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
finish : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
key : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
start : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC);
end component;
begin
-- Initialize and Reset process
reset_n_init_process : process(reset)
begin
if(rising_edge(reset)) then
round <= 0;
finish <= '0';
current_key <= (others => '0');
result_register_bank <= (others => '0');
start_subbytes_module <= '0';
start_shiftrows_module <= '0';
start_mixcolumns_module <= '0';
start_addroundkey_module <= '0';
finish_subbytes_module <= '0';
finish_shiftrows_module <= '0';
finish_mixcolumns_module <= '0';
finish_addroundkey_module <= '0';
to_subbytes_module <= (others => '0');
from_subbytes_module <= (others => '0');
to_shiftrows_module <= (others => '0');
from_shiftrows_module <= (others => '0');
to_mixcolumns_module <= (others => '0');
from_mixcolumns_module <= (others => '0');
to_addroundkey_module <= (others => '0');
from_addroundkey_module <= (others => '0');
end if;
end process reset_n_init_process;
-- Structure of signals transmission
round <= current_round when rising_edge(start_round);
current_key <= key when rising_edge(start_round);
to_subbytes_module <= plain_text when rising_edge(start_round);
start_subbytes_module <= '1' when rising_edge(start_round);
to_shiftrows_module <= from_subbytes_module when clock = '1';
start_shiftrows_module <= finish_subbytes_module when clock = '1';
to_mixcolumns_module <= from_shiftrows_module when clock = '1';
start_mixcolumns_module <= finish_shiftrows_module when clock = '1';
to_addroundkey_module <= from_shiftrows_module when (round = 10 and clock = '1')
else from_mixcolumns_module when clock = '1';
start_addroundkey_module <= finish_shiftrows_module when (round = 10 and clock = '1')
else finish_mixcolumns_module when clock = '1';
result_register_bank <= from_addroundkey_module when clock = '1';
finish <= finish_addroundkey_module when clock = '1';
SubBytes_module_1 : SubBytes_module
port map ( data_out => from_subbytes_module,
finish => finish_subbytes_module,
data_in => to_subbytes_module,
start => start_subbytes_module,
clock => clock,
reset => reset );
ShiftRows_module_1 : ShiftRows_module
port map ( data_out => from_shiftrows_module,
finish => finish_shiftrows_module,
data_in => to_shiftrows_module,
start => start_shiftrows_module,
clock => clock,
reset => reset );
MixColumns_module_1 : MixColumns_module
port map ( data_out => from_mixcolumns_module,
finish => finish_mixcolumns_module,
data_in => to_mixcolumns_module,
start => start_mixcolumns_module,
clock => clock,
reset => reset );
AddRoundKey_module_1 : AddRoundKey_module
port map ( data_out => from_addroundkey_module,
finish => finish_addroundkey_module,
data_in => to_addroundkey_module,
key => current_key,
start => start_addroundkey_module,
clock => clock,
reset => reset );
-- After work - outstandings result
cypher_text <= result_register_bank when clock = '1' and finish = '1';
finish_round <= finish when clock = '1';
end RTL;
| mit | 17f14d95f1dfcee4ae69b8780f6eaf6a | 0.547346 | 4.357692 | false | false | false | false |
airlog/vhdl-rc4 | src/memory.vhd | 1 | 1,959 | --
-- kod ród³owy urz¹dzenia trzymaj¹cego stan permutacji RC4
-- zasada dzia³ania:
-- Jakiekolwiek operacje s¹ wykonywane co takt zegara (rising_edge).
--
-- W normalnym trybie (SET = 0) zwraca wartoæ INDEX-tej komórki tablicy zawieraj¹cej
-- permutacjê na sygna³ OUTVALUE.
--
-- W trybie zapisywania (SET = 1) ustawia wartoæ INDEX-tej komórki tablicy zawieraj¹cej
-- permutacjê na wartoæ w sygnale INVALUE.
--
-- uwagi:
-- - nie zaimplementowano resetowania bo nie wiadomo dlaczego generowa³ zbyt du¿y schemat RTL;
-- inne urz¹dzenie korzystaj¹ce z tego bêdzie mog³o odpowiednio resetowaæ ten stan
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity memory is
generic (
width: integer := 8; -- ilosc bitow adresów
size: integer := 256 -- rozmiar pamieci w bajtach
);
port (
SET: in STD_LOGIC; -- tryb pracy
CLK: in STD_LOGIC; -- zegar
INDEX: in STD_LOGIC_VECTOR ((width - 1) downto 0); -- indeks elementu tablicy
INVALUE: in STD_LOGIC_VECTOR ((width - 1) downto 0); -- wartoæ wejciowa
OUTVALUE: out STD_LOGIC_VECTOR ((width - 1) downto 0) -- wartoæ wyjciowa
);
end memory;
architecture Behavioral of memory is
type rc4_state_array is array (0 to (size - 1)) of std_logic_vector((width - 1) downto 0);
shared variable state_array : rc4_state_array := (others => (others => '0'));
begin
process (clk, index)
variable arrindex : integer range 0 to (size - 1) := 0;
begin
if rising_edge(clk) then
arrindex := conv_integer(unsigned(index)); -- odczytaj numer ¿¹danej komórki pamiêci
case set is
when '0' => -- tryb odczytu
outvalue <= state_array(arrindex);
when '1' => -- tryb zapisu
state_array(arrindex) := invalue;
when others => -- w innych przypadkach (wymagane przez vhdl)
outvalue <= (others => '0');
end case;
end if;
end process;
end Behavioral;
| mit | 797f7a73f780d6cecffd2e8074939756 | 0.658499 | 2.640162 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fadd_3_full_dsp_32.vhd | 6 | 12,700 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
| gpl-3.0 | a9c31ae03b3e415d5df3879e8477dfa9 | 0.649764 | 3.003074 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ip/design_SWandHW_standalone_v2_ANN_0_0/synth/design_SWandHW_standalone_v2_ANN_0_0.vhd | 1 | 8,745 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: UC3M:MISEA_thesis:ANN:2.1
-- IP Revision: 1609020109
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_SWandHW_standalone_v2_ANN_0_0 IS
PORT (
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END design_SWandHW_standalone_v2_ANN_0_0;
ARCHITECTURE design_SWandHW_standalone_v2_ANN_0_0_arch OF design_SWandHW_standalone_v2_ANN_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_v2_ANN_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ANN IS
GENERIC (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER
);
PORT (
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END COMPONENT ANN;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_v2_ANN_0_0_arch: ARCHITECTURE IS "ANN,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_v2_ANN_0_0_arch : ARCHITECTURE IS "design_SWandHW_standalone_v2_ANN_0_0,ANN,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_AXILiteS_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 s_axi_AXILiteS RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : ANN
GENERIC MAP (
C_S_AXI_AXILITES_ADDR_WIDTH => 7,
C_S_AXI_AXILITES_DATA_WIDTH => 32
)
PORT MAP (
s_axi_AXILiteS_AWADDR => s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID => s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY => s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_WDATA => s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB => s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_WVALID => s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY => s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP => s_axi_AXILiteS_BRESP,
s_axi_AXILiteS_BVALID => s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY => s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR => s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_ARVALID => s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY => s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA => s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP => s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_RVALID => s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY => s_axi_AXILiteS_RREADY,
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
interrupt => interrupt
);
END design_SWandHW_standalone_v2_ANN_0_0_arch;
| gpl-3.0 | 1340b36a5423433ec88e39cef17b9567 | 0.722927 | 3.448344 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_AXILiteS_s_axi.vhd | 1 | 19,607 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ANN_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 7;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
P_mode :out STD_LOGIC_VECTOR(31 downto 0);
P_index1 :out STD_LOGIC_VECTOR(31 downto 0);
P_index2 :out STD_LOGIC_VECTOR(31 downto 0);
P_intIn_index3 :out STD_LOGIC_VECTOR(31 downto 0);
P_floatIn :out STD_LOGIC_VECTOR(31 downto 0);
P_floatOut :in STD_LOGIC_VECTOR(31 downto 0);
P_floatOut_ap_vld :in STD_LOGIC;
P_intOut :in STD_LOGIC_VECTOR(31 downto 0);
P_intOut_ap_vld :in STD_LOGIC
);
end entity ANN_AXILiteS_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of P_mode
-- bit 31~0 - P_mode[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of P_index1
-- bit 31~0 - P_index1[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of P_index2
-- bit 31~0 - P_index2[31:0] (Read/Write)
-- 0x24 : reserved
-- 0x28 : Data signal of P_intIn_index3
-- bit 31~0 - P_intIn_index3[31:0] (Read/Write)
-- 0x2c : reserved
-- 0x30 : Data signal of P_floatIn
-- bit 31~0 - P_floatIn[31:0] (Read/Write)
-- 0x34 : reserved
-- 0x38 : Data signal of P_floatOut
-- bit 31~0 - P_floatOut[31:0] (Read)
-- 0x3c : Control signal of P_floatOut
-- bit 0 - P_floatOut_ap_vld (Read/COR)
-- others - reserved
-- 0x40 : Data signal of P_intOut
-- bit 31~0 - P_intOut[31:0] (Read)
-- 0x44 : Control signal of P_intOut
-- bit 0 - P_intOut_ap_vld (Read/COR)
-- others - reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of ANN_AXILiteS_s_axi is
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write fsm states
signal wstate, wnext, rstate, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_P_MODE_DATA_0 : INTEGER := 16#10#;
constant ADDR_P_MODE_CTRL : INTEGER := 16#14#;
constant ADDR_P_INDEX1_DATA_0 : INTEGER := 16#18#;
constant ADDR_P_INDEX1_CTRL : INTEGER := 16#1c#;
constant ADDR_P_INDEX2_DATA_0 : INTEGER := 16#20#;
constant ADDR_P_INDEX2_CTRL : INTEGER := 16#24#;
constant ADDR_P_INTIN_INDEX3_DATA_0 : INTEGER := 16#28#;
constant ADDR_P_INTIN_INDEX3_CTRL : INTEGER := 16#2c#;
constant ADDR_P_FLOATIN_DATA_0 : INTEGER := 16#30#;
constant ADDR_P_FLOATIN_CTRL : INTEGER := 16#34#;
constant ADDR_P_FLOATOUT_DATA_0 : INTEGER := 16#38#;
constant ADDR_P_FLOATOUT_CTRL : INTEGER := 16#3c#;
constant ADDR_P_INTOUT_DATA_0 : INTEGER := 16#40#;
constant ADDR_P_INTOUT_CTRL : INTEGER := 16#44#;
constant ADDR_BITS : INTEGER := 7;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC;
signal int_ap_start : STD_LOGIC;
signal int_auto_restart : STD_LOGIC;
signal int_gie : STD_LOGIC;
signal int_ier : UNSIGNED(1 downto 0);
signal int_isr : UNSIGNED(1 downto 0);
signal int_P_mode : UNSIGNED(31 downto 0);
signal int_P_index1 : UNSIGNED(31 downto 0);
signal int_P_index2 : UNSIGNED(31 downto 0);
signal int_P_intIn_index3 : UNSIGNED(31 downto 0);
signal int_P_floatIn : UNSIGNED(31 downto 0);
signal int_P_floatOut : UNSIGNED(31 downto 0);
signal int_P_floatOut_ap_vld : STD_LOGIC;
signal int_P_intOut : UNSIGNED(31 downto 0);
signal int_P_intOut_ap_vld : STD_LOGIC;
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_P_MODE_DATA_0 =>
rdata_data <= RESIZE(int_P_mode(31 downto 0), 32);
when ADDR_P_INDEX1_DATA_0 =>
rdata_data <= RESIZE(int_P_index1(31 downto 0), 32);
when ADDR_P_INDEX2_DATA_0 =>
rdata_data <= RESIZE(int_P_index2(31 downto 0), 32);
when ADDR_P_INTIN_INDEX3_DATA_0 =>
rdata_data <= RESIZE(int_P_intIn_index3(31 downto 0), 32);
when ADDR_P_FLOATIN_DATA_0 =>
rdata_data <= RESIZE(int_P_floatIn(31 downto 0), 32);
when ADDR_P_FLOATOUT_DATA_0 =>
rdata_data <= RESIZE(int_P_floatOut(31 downto 0), 32);
when ADDR_P_FLOATOUT_CTRL =>
rdata_data <= (0 => int_P_floatOut_ap_vld, others => '0');
when ADDR_P_INTOUT_DATA_0 =>
rdata_data <= RESIZE(int_P_intOut(31 downto 0), 32);
when ADDR_P_INTOUT_CTRL =>
rdata_data <= (0 => int_P_intOut_ap_vld, others => '0');
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
int_ap_idle <= ap_idle;
int_ap_ready <= ap_ready;
P_mode <= STD_LOGIC_VECTOR(int_P_mode);
P_index1 <= STD_LOGIC_VECTOR(int_P_index1);
P_index2 <= STD_LOGIC_VECTOR(int_P_index2);
P_intIn_index3 <= STD_LOGIC_VECTOR(int_P_intIn_index3);
P_floatIn <= STD_LOGIC_VECTOR(int_P_floatIn);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (int_ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_MODE_DATA_0) then
int_P_mode(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_mode(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INDEX1_DATA_0) then
int_P_index1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_index1(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INDEX2_DATA_0) then
int_P_index2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_index2(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_INTIN_INDEX3_DATA_0) then
int_P_intIn_index3(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_intIn_index3(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_P_FLOATIN_DATA_0) then
int_P_floatIn(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_P_floatIn(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_P_floatOut <= (others => '0');
elsif (ACLK_EN = '1') then
if (P_floatOut_ap_vld = '1') then
int_P_floatOut <= UNSIGNED(P_floatOut); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_P_floatOut_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (P_floatOut_ap_vld = '1') then
int_P_floatOut_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_P_FLOATOUT_CTRL) then
int_P_floatOut_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_P_intOut <= (others => '0');
elsif (ACLK_EN = '1') then
if (P_intOut_ap_vld = '1') then
int_P_intOut <= UNSIGNED(P_intOut); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_P_intOut_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (P_intOut_ap_vld = '1') then
int_P_intOut_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_P_INTOUT_CTRL) then
int_P_intOut_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
| gpl-3.0 | a998abd35691dc1e62bca5f30030bfe2 | 0.470801 | 3.626896 | false | false | false | false |
brotatos/Whack-A-Mole | src/countdown_clk_div.vhd | 1 | 1,815 | ----------------------------------------------------------------------------------
-- Company: Ratner Engineering
-- Engineer: bryan mealy
--
-- Create Date: 15:27:40 12/27/2010
-- Design Name:
-- Module Name: clk_div.vhd
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This divides the input clock frequency into a slower
-- frequency. The frequency is set by the the MAX_COUNT
-- constant in the declarative region of the architecture.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
-----------------------------------------------------------------------
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------------
-- Module to divide the clock
-----------------------------------------------------------------------
entity countdown_clk_div is
Port ( clk : in std_logic;
sclk : out std_logic);
end countdown_clk_div;
architecture my_clk_div of countdown_clk_div is
constant max_count : integer := (25000000);
-- original
--constant max_count : integer := (3000000);
signal tmp_clk : std_logic := '0';
begin
my_div: process (clk,tmp_clk)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = MAX_COUNT) then
tmp_clk <= not tmp_clk;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
sclk <= tmp_clk;
end process my_div;
end my_clk_div;
| mit | 09e1b5f7da7d7bba4b2d0a800153c4ab | 0.450689 | 4.481481 | false | false | false | false |
bonfireprocessor/bonfire-soc | spi/wb_spi_interface.vhd | 1 | 3,095 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:30:47 02/18/2017
-- Design Name:
-- Module Name: wb_spi_interface - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- registers:
-- base+0 -- chip select control; bit 0 is slave_cs
-- base+4 -- status register; bit 0 indicates "transmitter busy"
-- base+8 -- transmitter: write a byte here, starts SPI bus transaction
-- base+0x0C -- receiver: last byte received (updated on each transation)
-- base+0x10 -- clock divider: SPI CLK is clk_i/2*(1+n) ie for 128MHz clock, divisor 0 is 64MHz, 1 is 32MHz, 3 is 16MHz etc
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity wb_spi_interface is
generic (
CLK_FREQUENCY : natural := (96 * 1000000)
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
-- SPI Port:
slave_cs_o : out std_logic;
slave_clk_o : out std_logic;
slave_mosi_o : out std_logic;
slave_miso_i : in std_logic;
-- Interrupt signal:
irq : out std_logic;
-- Wishbone ports:
wb_adr_in : in std_logic_vector(7 downto 0);
wb_dat_in : in std_logic_vector( 7 downto 0);
wb_dat_out : out std_logic_vector( 7 downto 0);
wb_we_in : in std_logic;
wb_cyc_in : in std_logic;
wb_stb_in : in std_logic;
wb_ack_out : out std_logic
);
end wb_spi_interface;
architecture Behavioral of wb_spi_interface is
COMPONENT spimaster
PORT(
clk : IN std_logic;
reset : IN std_logic;
cpu_address : IN std_logic_vector(2 downto 0);
data_in : IN std_logic_vector(7 downto 0);
enable : IN std_logic;
req_read : IN std_logic;
req_write : IN std_logic;
slave_miso : IN std_logic;
cpu_wait : OUT std_logic;
data_out : OUT std_logic_vector(7 downto 0);
slave_cs : OUT std_logic;
slave_clk : OUT std_logic;
slave_mosi : OUT std_logic
);
END COMPONENT;
signal req_read,req_write,enable,cpu_wait : std_logic;
begin
enable <= wb_cyc_in and wb_stb_in;
req_read <= enable and not wb_we_in;
req_write <= wb_we_in;
wb_ack_out <= enable and not cpu_wait;
i_spimaster: spimaster PORT MAP(
clk => clk_i,
reset => reset_i,
cpu_address => wb_adr_in(4 downto 2),
cpu_wait => cpu_wait,
data_in => wb_dat_in,
data_out => wb_dat_out,
enable => enable,
req_read => req_read,
req_write => req_write,
slave_cs => slave_cs_o,
slave_clk => slave_clk_o,
slave_mosi => slave_mosi_o,
slave_miso => slave_miso_i
);
end Behavioral;
| gpl-3.0 | b1e17a1a8251f021a44c131ce43024e7 | 0.598708 | 3.174359 | false | false | false | false |
mjl152/usmt_uarch | smt_test_bench.vhd | 1 | 3,851 | -- The MIT License (MIT)
--
-- Copyright (c) 2013 Michael Lancaster
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- SMT test bench
-- Michael Lancaster <[email protected]>
-- 4 October 2013
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY cputestbench IS
END cputestbench;
ARCHITECTURE behavior OF cputestbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT smt_control_unit
PORT(
CLOCK : IN std_logic;
INSTRUCTION_0 : OUT std_logic_vector(7 downto 0);
INSTRUCTION_1 : OUT std_logic_vector(7 downto 0);
INSTRUCTION_POINTER_0,
INSTRUCTION_POINTER_1,
ARG1_0, ARG1_1,
ARG2_0, ARG2_1,
ARG3_0, ARG3_1 : OUT std_logic_vector (7 downto 0)
);
END COMPONENT;
--Inputs
signal CLOCK : std_logic := '0';
--Outputs
signal INSTRUCTION_0,
INSTRUCTION_1,
INSTRUCTION_POINTER_0,
INSTRUCTION_POINTER_1,
ARG1_0, ARG1_1,
ARG2_0, ARG2_1,
ARG3_0, ARG3_1 : std_logic_vector(7 downto 0);
signal NUM_CYCLES_0, NUM_CYCLES_1 : std_logic_vector (63 downto 0);
shared variable number_cycles_0, number_cycles_1 : integer := 0;
-- Clock period definitions
constant CLOCK_period : time := 10 ps;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: smt_control_unit PORT MAP (
CLOCK => CLOCK,
INSTRUCTION_0 => INSTRUCTION_0,
INSTRUCTION_1 => INSTRUCTION_1,
INSTRUCTION_POINTER_0 => INSTRUCTION_POINTER_0,
INSTRUCTION_POINTER_1 => INSTRUCTION_POINTER_1,
ARG1_0 => ARG1_0,
ARG1_1 => ARG1_1,
ARG2_0 => ARG2_0,
ARG2_1 => ARG2_1,
ARG3_0 => ARG3_0,
ARG3_1 => ARG3_1
);
-- Clock process definitions
CLOCK_process :process
begin
CLOCK <= '0';
wait for CLOCK_period/2;
CLOCK <= '1';
wait for CLOCK_period/2;
end process;
-- logic to calculate the number of cycles per thread
process (INSTRUCTION_0)
begin
if (INSTRUCTION_0 = "00000101") then
number_cycles_0 := number_cycles_0 + 1;
end if;
NUM_CYCLES_0 <= std_logic_vector(to_unsigned(number_cycles_0, 64));
end process;
process (INSTRUCTION_1)
begin
if (INSTRUCTION_1 = "00000101") then
number_cycles_1 := number_cycles_1 + 1;
end if;
NUM_CYCLES_1 <= std_logic_vector(to_unsigned(number_cycles_1, 64));
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLOCK_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 1392391a33663bf85e8d301ee1279a12 | 0.652558 | 3.764418 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fpext_0_no_dsp_32.vhd | 6 | 12,143 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fpext_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END ANN_ap_fpext_0_no_dsp_32;
ARCHITECTURE ANN_ap_fpext_0_no_dsp_32_arch OF ANN_ap_fpext_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fpext_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fpext_0_no_dsp_32_arch;
| gpl-3.0 | 1e0ce1fc4507c0218a95ee6a96ce8f62 | 0.645722 | 2.998272 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_files/bd/design_SW_standalone/hdl/design_SW_standalone.vhd | 1 | 61,867 | --Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4.2 (win64) Build 1494164 Fri Feb 26 04:18:56 MST 2016
--Date : Sun Aug 28 03:14:22 2016
--Host : DESKTOP-I329812 running 64-bit major release (build 9200)
--Command : generate_target design_SW_standalone.bd
--Design : design_SW_standalone
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_14CIMCM is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_14CIMCM;
architecture STRUCTURE of s00_couplers_imp_14CIMCM is
component design_SW_standalone_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component design_SW_standalone_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component design_SW_standalone_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SW_standalone_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end design_SW_standalone_processing_system7_0_axi_periph_0;
architecture STRUCTURE of design_SW_standalone_processing_system7_0_axi_periph_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arvalid <= s00_couplers_to_processing_system7_0_axi_periph_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awvalid <= s00_couplers_to_processing_system7_0_axi_periph_AWVALID;
M00_AXI_bready <= s00_couplers_to_processing_system7_0_axi_periph_BREADY;
M00_AXI_rready <= s00_couplers_to_processing_system7_0_axi_periph_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
processing_system7_0_axi_periph_ACLK_net <= M00_ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= M00_ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_processing_system7_0_axi_periph_ARREADY <= M00_AXI_arready;
s00_couplers_to_processing_system7_0_axi_periph_AWREADY <= M00_AXI_awready;
s00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_BVALID <= M00_AXI_bvalid;
s00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_RVALID <= M00_AXI_rvalid;
s00_couplers_to_processing_system7_0_axi_periph_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_14CIMCM
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => s00_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => s00_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => s00_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => s00_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => s00_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_SW_standalone is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
leds_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
leds_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of design_SW_standalone : entity is "design_SW_standalone,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_SW_standalone,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=4,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,da_axi4_cnt=1,da_board_cnt=1,da_ps7_cnt=3,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of design_SW_standalone : entity is "design_SW_standalone.hwdef";
end design_SW_standalone;
architecture STRUCTURE of design_SW_standalone is
component design_SW_standalone_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component design_SW_standalone_processing_system7_0_0;
component design_SW_standalone_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component design_SW_standalone_axi_gpio_0_0;
component design_SW_standalone_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_SW_standalone_rst_processing_system7_0_100M_0;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_gpio_0_GPIO_TRI_T : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC;
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
axi_gpio_0_GPIO_TRI_I(3 downto 0) <= leds_4bits_tri_i(3 downto 0);
leds_4bits_tri_o(3 downto 0) <= axi_gpio_0_GPIO_TRI_O(3 downto 0);
leds_4bits_tri_t(3 downto 0) <= axi_gpio_0_GPIO_TRI_T(3 downto 0);
axi_gpio_0: component design_SW_standalone_axi_gpio_0_0
port map (
gpio_io_i(3 downto 0) => axi_gpio_0_GPIO_TRI_I(3 downto 0),
gpio_io_o(3 downto 0) => axi_gpio_0_GPIO_TRI_O(3 downto 0),
gpio_io_t(3 downto 0) => axi_gpio_0_GPIO_TRI_T(3 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID
);
processing_system7_0: component design_SW_standalone_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.design_SW_standalone_processing_system7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID,
M00_AXI_bready => processing_system7_0_axi_periph_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => processing_system7_0_axi_periph_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_processing_system7_0_100M: component design_SW_standalone_rst_processing_system7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
end STRUCTURE;
| gpl-3.0 | 5affd981628595a0a7d6ed3cd0523220 | 0.687087 | 2.830146 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kr_fuzman_tb1.vhd | 1 | 2,906 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity kr_fuzman_tb1 is
end kr_fuzman_tb1;
architecture behav of kr_fuzman_tb1 is
component kr_fuzman_system1 is
port
( clock : in std_logic;
V_mux_sel,Z_mux_sel : in std_logic;
V_load,V_load1 : in std_logic;
Z_load,Z_load1 : in std_logic;
Ut : in std_logic_vector(31 downto 0);
Vref : in std_logic_vector(31 downto 0);
Vtminusone : in std_logic_vector(31 downto 0);
Ztminusone : in std_logic_vector(31 downto 0);
Vt : inout std_logic_vector(31 downto 0);
Zt : inout std_logic_vector(31 downto 0)
);
end component;
signal clock,V_mux_sel,Z_mux_sel,V_load,V_load1,Z_load,Z_load1 : std_logic := '0';
signal Ut,Vref,Vtminusone,Ztminusone : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
signal Vt,Zt : std_logic_vector(31 downto 0);
constant clk_period : time := 100 ps;
begin
uut: kr_fuzman_system1 port map
( clock => clock,
V_mux_sel => V_mux_sel,
Z_mux_sel => Z_mux_sel,
V_load => V_load,
V_load1 => V_load1,
Z_load => Z_load,
Z_load1 => Z_load1,
Ut => Ut,
Vref => Vref,
Vtminusone => Vtminusone,
Ztminusone => Ztminusone,
Vt => Vt,
Zt => Zt);
clk_process : process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;
stim_proc : process
begin
wait for 100 ps;
V_mux_sel <= '0';
Z_mux_sel <= '0';
Ut <= "00111110110101110000101000111101";
Vref <= "01000001101000000000000000000000";
Vtminusone <= "01000001101010000000000000000000";
Ztminusone <= "00111111011111010111000010100100";
V_load <= '1';
Z_load <= '1';
wait for 3950 ps;
V_load1 <= '1';
wait for 100 ps;
V_mux_sel <= '1';
wait for 1150ps;
Z_load1 <= '1';
wait for 100 ps;
Z_mux_sel <= '1';
wait for 100 ps;
Vref <= "01000001101001001100110011001101";
Ut <= "01000001100011110111000010100100";
Vtminusone <= Vt;
Ztminusone <= Zt;
wait for 5500 ps;
Vref <= "01000001100110100010100011110110";
Ut <= "01000000111111000100111010100101";
wait;
end process;
end;
| mit | a29869b6321158e84568103d3a484a7d | 0.484515 | 4.181295 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_fpext_0_no_dsp_32.vhd | 4 | 12,231 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fpext_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END feedforward_ap_fpext_0_no_dsp_32;
ARCHITECTURE feedforward_ap_fpext_0_no_dsp_32_arch OF feedforward_ap_fpext_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fpext_0_no_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fpext_0_no_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fpext_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fpext_0_no_dsp_32_arch;
| gpl-3.0 | 8f31955c1508334d37d6b92db9c8d93d | 0.648271 | 3.02 | false | false | false | false |
makestuff/spi-talk | templates/fx2all/vhdl/top_level.vhdl | 1 | 5,035 | --
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic (
NUM_DEVS : integer := 1
);
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 downto 0); -- select FIFO: "00" for EP2OUT, "10" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2OE_out : out std_logic; -- asserted (active-low) to tell FX2LP to drive bus
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Peripheral interface ----------------------------------------------------------------------
spiClk_out : out std_logic;
spiData_out : out std_logic;
spiData_in : in std_logic;
spiCS_out : out std_logic_vector(NUM_DEVS-1 downto 0)
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Needed so that the comm_fpga_fx2 module can drive both fx2Read_out and fx2OE_out
signal fx2Read : std_logic;
-- Reset signal so host can delay startup
signal fx2Reset : std_logic;
begin
-- CommFPGA module
fx2Read_out <= fx2Read;
fx2OE_out <= fx2Read;
fx2Addr_out(0) <= -- So fx2Addr_out(1)='0' selects EP2OUT, fx2Addr_out(1)='1' selects EP6IN
'0' when fx2Reset = '0'
else 'Z';
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => fx2Reset,
-- FX2LP interface
fx2FifoSel_out => fx2Addr_out(1),
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
spi_talk_app : entity work.spi_talk
generic map (
NUM_DEVS => NUM_DEVS
)
port map(
clk_in => fx2Clk_in,
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- Peripheral interface
spiClk_out => spiClk_out,
spiData_out => spiData_out,
spiData_in => spiData_in,
spiCS_out => spiCS_out
);
end architecture;
| gpl-3.0 | fabc25a286e70b2e850cd35ceeff452d | 0.595829 | 3.367893 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_thesis_ANN_2_0/hdl/vhdl/ANN_dadd_64ns_64ns_64_5_full_dsp.vhd | 1 | 3,340 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_dadd_64ns_64ns_64_5_full_dsp is
generic (
ID : integer := 6;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 64;
din1_WIDTH : integer := 64;
dout_WIDTH : integer := 64
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_dadd_64ns_64ns_64_5_full_dsp is
--------------------- Component ---------------------
component ANN_ap_dadd_3_full_dsp_64 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(63 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(63 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(63 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(63 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(63 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(63 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_dadd_3_full_dsp_64_u : component ANN_ap_dadd_3_full_dsp_64
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | ea19645e576cca80e8682b327c912613 | 0.484431 | 3.475546 | false | false | false | false |
pemsac/ANN_project | ANN_project.ip_user_repository/TEST_hls_example_1_0/hdl/vhdl/example.vhd | 1 | 24,060 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity example is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
A_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
A_TVALID : IN STD_LOGIC;
A_TREADY : OUT STD_LOGIC;
B_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
B_TVALID : OUT STD_LOGIC;
B_TREADY : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of example is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"example,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.256000,HLS_SYN_LAT=201,HLS_SYN_TPT=none,HLS_SYN_MEM=1,HLS_SYN_DSP=2,HLS_SYN_FF=339,HLS_SYN_LUT=549}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv6_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_const_lv32_40A00000 : STD_LOGIC_VECTOR (31 downto 0) := "01000000101000000000000000000000";
constant ap_const_lv6_32 : STD_LOGIC_VECTOR (5 downto 0) := "110010";
constant ap_const_lv6_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_26 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal mode : STD_LOGIC_VECTOR (31 downto 0);
signal C_address0 : STD_LOGIC_VECTOR (5 downto 0);
signal C_ce0 : STD_LOGIC;
signal C_we0 : STD_LOGIC;
signal C_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal C_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal example_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal tmp_fu_114_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_reg_154 : STD_LOGIC_VECTOR (0 downto 0);
signal i_3_fu_126_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_3_reg_161 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_98 : BOOLEAN;
signal exitcond1_fu_137_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_108 : BOOLEAN;
signal exitcond_fu_120_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_2_fu_143_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal C_load_reg_179 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_127 : BOOLEAN;
signal i_1_reg_86 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_136 : BOOLEAN;
signal ap_sig_ioackin_B_TREADY : STD_LOGIC;
signal i_reg_97 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_132_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_1_fu_149_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_108_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ioackin_B_TREADY : STD_LOGIC := '0';
signal grp_fu_108_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_bdd_117 : BOOLEAN;
signal ap_sig_bdd_107 : BOOLEAN;
component example_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component example_C IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (5 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component example_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
mode : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
C_U : component example_C
generic map (
DataWidth => 32,
AddressRange => 50,
AddressWidth => 6)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => C_address0,
ce0 => C_ce0,
we0 => C_we0,
d0 => C_d0,
q0 => C_q0);
example_AXILiteS_s_axi_U : component example_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => example_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
mode => mode);
example_fadd_32ns_32ns_32_5_full_dsp_U0 : component example_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => C_load_reg_179,
din1 => ap_const_lv32_40A00000,
ce => grp_fu_108_ce,
dout => grp_fu_108_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_B_TREADY assign process. --
ap_reg_ioackin_B_TREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_B_TREADY))) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = B_TREADY)) then
ap_reg_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- i_1_reg_86 assign process. --
i_1_reg_86_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_fu_114_p2 = ap_const_lv1_0))) then
i_1_reg_86 <= ap_const_lv6_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) then
i_1_reg_86 <= i_3_reg_161;
end if;
end if;
end process;
-- i_reg_97 assign process. --
i_reg_97_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and not((tmp_fu_114_p2 = ap_const_lv1_0)))) then
i_reg_97 <= ap_const_lv6_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_reg_154 = ap_const_lv1_0)) and (ap_const_lv1_0 = exitcond1_fu_137_p2) and not(ap_sig_bdd_108))) then
i_reg_97 <= i_2_fu_143_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
C_load_reg_179 <= C_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_reg_154 = ap_const_lv1_0) and not(ap_sig_bdd_108))) then
i_3_reg_161 <= i_3_fu_126_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
tmp_reg_154 <= tmp_fu_114_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_reg_154, exitcond1_fu_137_p2, ap_sig_bdd_108, exitcond_fu_120_p2, ap_sig_ioackin_B_TREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not(ap_sig_bdd_108) and (((tmp_reg_154 = ap_const_lv1_0) and not((ap_const_lv1_0 = exitcond_fu_120_p2))) or (not((tmp_reg_154 = ap_const_lv1_0)) and not((ap_const_lv1_0 = exitcond1_fu_137_p2)))))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif ((not((tmp_reg_154 = ap_const_lv1_0)) and (ap_const_lv1_0 = exitcond1_fu_137_p2) and not(ap_sig_bdd_108))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif (((tmp_reg_154 = ap_const_lv1_0) and not(ap_sig_bdd_108) and (ap_const_lv1_0 = exitcond_fu_120_p2))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_B_TREADY))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
-- A_TREADY assign process. --
A_TREADY_assign_proc : process(tmp_reg_154, ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_137_p2, ap_sig_bdd_108)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_reg_154 = ap_const_lv1_0)) and (ap_const_lv1_0 = exitcond1_fu_137_p2) and not(ap_sig_bdd_108))) then
A_TREADY <= ap_const_logic_1;
else
A_TREADY <= ap_const_logic_0;
end if;
end process;
B_TDATA <= grp_fu_108_p2;
-- B_TVALID assign process. --
B_TVALID_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7, ap_reg_ioackin_B_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and (ap_const_logic_0 = ap_reg_ioackin_B_TREADY))) then
B_TVALID <= ap_const_logic_1;
else
B_TVALID <= ap_const_logic_0;
end if;
end process;
-- C_address0 assign process. --
C_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_3_fu_132_p1, tmp_1_fu_149_p1, ap_sig_bdd_117, ap_sig_bdd_107)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
if (ap_sig_bdd_107) then
C_address0 <= tmp_1_fu_149_p1(6 - 1 downto 0);
elsif (ap_sig_bdd_117) then
C_address0 <= tmp_3_fu_132_p1(6 - 1 downto 0);
else
C_address0 <= "XXXXXX";
end if;
else
C_address0 <= "XXXXXX";
end if;
end process;
-- C_ce0 assign process. --
C_ce0_assign_proc : process(tmp_reg_154, ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_137_p2, ap_sig_bdd_108, exitcond_fu_120_p2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (tmp_reg_154 = ap_const_lv1_0) and not(ap_sig_bdd_108) and (ap_const_lv1_0 = exitcond_fu_120_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_reg_154 = ap_const_lv1_0)) and (ap_const_lv1_0 = exitcond1_fu_137_p2) and not(ap_sig_bdd_108)))) then
C_ce0 <= ap_const_logic_1;
else
C_ce0 <= ap_const_logic_0;
end if;
end process;
C_d0 <= A_TDATA;
-- C_we0 assign process. --
C_we0_assign_proc : process(tmp_reg_154, ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_137_p2, ap_sig_bdd_108)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((tmp_reg_154 = ap_const_lv1_0)) and (ap_const_lv1_0 = exitcond1_fu_137_p2) and not(ap_sig_bdd_108)))) then
C_we0 <= ap_const_logic_1;
else
C_we0 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_reg_154, ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_137_p2, ap_sig_bdd_108, exitcond_fu_120_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_108) and (((tmp_reg_154 = ap_const_lv1_0) and not((ap_const_lv1_0 = exitcond_fu_120_p2))) or (not((tmp_reg_154 = ap_const_lv1_0)) and not((ap_const_lv1_0 = exitcond1_fu_137_p2)))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_reg_154, ap_sig_cseq_ST_st2_fsm_1, exitcond1_fu_137_p2, ap_sig_bdd_108, exitcond_fu_120_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not(ap_sig_bdd_108) and (((tmp_reg_154 = ap_const_lv1_0) and not((ap_const_lv1_0 = exitcond_fu_120_p2))) or (not((tmp_reg_154 = ap_const_lv1_0)) and not((ap_const_lv1_0 = exitcond1_fu_137_p2)))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_107 assign process. --
ap_sig_bdd_107_assign_proc : process(tmp_reg_154, exitcond1_fu_137_p2)
begin
ap_sig_bdd_107 <= (not((tmp_reg_154 = ap_const_lv1_0)) and (ap_const_lv1_0 = exitcond1_fu_137_p2));
end process;
-- ap_sig_bdd_108 assign process. --
ap_sig_bdd_108_assign_proc : process(A_TVALID, tmp_reg_154, exitcond1_fu_137_p2)
begin
ap_sig_bdd_108 <= ((A_TVALID = ap_const_logic_0) and not((tmp_reg_154 = ap_const_lv1_0)) and (ap_const_lv1_0 = exitcond1_fu_137_p2));
end process;
-- ap_sig_bdd_117 assign process. --
ap_sig_bdd_117_assign_proc : process(tmp_reg_154, exitcond_fu_120_p2)
begin
ap_sig_bdd_117 <= ((tmp_reg_154 = ap_const_lv1_0) and (ap_const_lv1_0 = exitcond_fu_120_p2));
end process;
-- ap_sig_bdd_127 assign process. --
ap_sig_bdd_127_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_127 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_136 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_26 assign process. --
ap_sig_bdd_26_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_98 assign process. --
ap_sig_bdd_98_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_98 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_98)
begin
if (ap_sig_bdd_98) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_127)
begin
if (ap_sig_bdd_127) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_136)
begin
if (ap_sig_bdd_136) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_B_TREADY assign process. --
ap_sig_ioackin_B_TREADY_assign_proc : process(B_TREADY, ap_reg_ioackin_B_TREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_B_TREADY)) then
ap_sig_ioackin_B_TREADY <= B_TREADY;
else
ap_sig_ioackin_B_TREADY <= ap_const_logic_1;
end if;
end process;
example_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
exitcond1_fu_137_p2 <= "1" when (i_reg_97 = ap_const_lv6_32) else "0";
exitcond_fu_120_p2 <= "1" when (i_1_reg_86 = ap_const_lv6_32) else "0";
-- grp_fu_108_ce assign process. --
grp_fu_108_ce_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st8_fsm_7, ap_sig_ioackin_B_TREADY)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and (ap_const_logic_0 = ap_sig_ioackin_B_TREADY)))) then
grp_fu_108_ce <= ap_const_logic_0;
else
grp_fu_108_ce <= ap_const_logic_1;
end if;
end process;
i_2_fu_143_p2 <= std_logic_vector(unsigned(i_reg_97) + unsigned(ap_const_lv6_1));
i_3_fu_126_p2 <= std_logic_vector(unsigned(i_1_reg_86) + unsigned(ap_const_lv6_1));
tmp_1_fu_149_p1 <= std_logic_vector(resize(unsigned(i_reg_97),64));
tmp_3_fu_132_p1 <= std_logic_vector(resize(unsigned(i_1_reg_86),64));
tmp_fu_114_p2 <= "1" when (mode = ap_const_lv32_1) else "0";
end behav;
| gpl-3.0 | c0d3a6eec2340b748b94c237aa5cb05b | 0.571114 | 2.905095 | false | false | false | false |
bonfireprocessor/bonfire-soc | dram_arbiter.vhd | 1 | 4,342 | ---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at Wed May 10 21:03:18 2017
--
-- Configuration:
-- Number of masters: 2
-- Number of slaves: 1
-- Master address width: 26
-- Slave address width: 26
-- Port size: 32
-- Port granularity: 8
-- Entity name: dram_arbiter
-- Pipelined arbiter: no
-- Registered feedback: yes
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e dram_arbiter -r 2 1 26 26 32 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dram_arbiter is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_sel_i: in std_logic_vector(3 downto 0);
s0_cti_i: in std_logic_vector(2 downto 0);
s0_bte_i: in std_logic_vector(1 downto 0);
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(25 downto 2);
s0_dat_i: in std_logic_vector(31 downto 0);
s0_dat_o: out std_logic_vector(31 downto 0);
s1_cyc_i: in std_logic;
s1_stb_i: in std_logic;
s1_we_i: in std_logic;
s1_sel_i: in std_logic_vector(3 downto 0);
s1_cti_i: in std_logic_vector(2 downto 0);
s1_bte_i: in std_logic_vector(1 downto 0);
s1_ack_o: out std_logic;
s1_adr_i: in std_logic_vector(25 downto 2);
s1_dat_i: in std_logic_vector(31 downto 0);
s1_dat_o: out std_logic_vector(31 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_sel_o: out std_logic_vector(3 downto 0);
m0_cti_o: out std_logic_vector(2 downto 0);
m0_bte_o: out std_logic_vector(1 downto 0);
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(25 downto 2);
m0_dat_o: out std_logic_vector(31 downto 0);
m0_dat_i: in std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of dram_arbiter is
signal request: std_logic_vector(1 downto 0);
signal grant_next: std_logic_vector(1 downto 0);
signal grant: std_logic_vector(1 downto 0);
signal grant_reg: std_logic_vector(1 downto 0):=(others=>'0');
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal sel_mux: std_logic_vector(3 downto 0);
signal cti_mux: std_logic_vector(2 downto 0);
signal bte_mux: std_logic_vector(1 downto 0);
signal adr_mux: std_logic_vector(25 downto 2);
signal wdata_mux: std_logic_vector(31 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(31 downto 0);
begin
-- ARBITER
-- Selects the active master. Masters with lower port numbers
-- have higher priority. Ongoing cycles are not interrupted.
request<=s1_cyc_i&s0_cyc_i;
grant_next<="01" when request(0)='1' else
"10" when request(1)='1' else
(others=>'0');
grant<=grant_reg when (request and grant_reg)/="00" else grant_next;
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
grant_reg<=(others=>'0');
else
grant_reg<=grant;
end if;
end if;
end process;
-- MASTER->SLAVE MUX
cyc_mux<=(s0_cyc_i and grant(0)) or
(s1_cyc_i and grant(1));
stb_mux<=(s0_stb_i and grant(0)) or
(s1_stb_i and grant(1));
we_mux<=(s0_we_i and grant(0)) or
(s1_we_i and grant(1));
sel_mux_gen: for i in sel_mux'range generate
sel_mux(i)<=(s0_sel_i(i) and grant(0)) or
(s1_sel_i(i) and grant(1));
end generate;
cti_mux_gen: for i in cti_mux'range generate
cti_mux(i)<=(s0_cti_i(i) and grant(0)) or
(s1_cti_i(i) and grant(1));
end generate;
bte_mux_gen: for i in bte_mux'range generate
bte_mux(i)<=(s0_bte_i(i) and grant(0)) or
(s1_bte_i(i) and grant(1));
end generate;
adr_mux_gen: for i in adr_mux'range generate
adr_mux(i)<=(s0_adr_i(i) and grant(0)) or
(s1_adr_i(i) and grant(1));
end generate;
wdata_mux_gen: for i in wdata_mux'range generate
wdata_mux(i)<=(s0_dat_i(i) and grant(0)) or
(s1_dat_i(i) and grant(1));
end generate;
-- MASTER->SLAVE DEMUX
m0_cyc_o<=cyc_mux;
m0_stb_o<=stb_mux;
m0_we_o<=we_mux;
m0_sel_o<=sel_mux;
m0_cti_o<=cti_mux;
m0_bte_o<=bte_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=m0_ack_i;
rdata_mux<=m0_dat_i;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux and grant(0);
s0_dat_o<=rdata_mux;
s1_ack_o<=ack_mux and grant(1);
s1_dat_o<=rdata_mux;
end architecture;
| gpl-3.0 | ec42dc9976966914ce4ffe6182e41088 | 0.635191 | 2.493969 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/xilinx.com/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 24 | 96,728 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PG0J5RRIuu8K34zw5Z9mZLcupY6QnoBh2vIa6E6pawHg9l3NOpmcnQD8DjlUVHwK1Lk/6lnvrs6A
b2ccUP8BzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
kj1Opmh6opb0EpvZkF6RDB1ya5n5md0eV6tgAJ8PWHtFsv5VHaNZle30baYZxyu2KL/p8B8zupsk
MsANvBFuPXJVi4sKW61Q454dYwpkHoUsC1oDxl5cKtOOzU1ATXzQiwqR3zORDpuNNXOT30fTCyLl
n+2tV+8EQi7TvhMf/14=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
QAZl2aBlCkVZlo7spLtCcYzE2QYDGr+KpghU31tU/K5eiCe0uoaMoKnAlVPIpxlooAnbipo7NkQm
DlYhwtwVOiWtiPGiyA1Uvjb0VOnDjEi/SMcFUirkV00GyXTH8/0u+JIIMhAVOrnTNKUiBdRXPOfZ
m7yN35Z0Gd047WKv2RqSaTMd7VZ1qNvv/PokPcLrwxqBudSkZNp4iGJK7p/7dtQgBfyWpncqLVuY
b78kmtGkj3gQrWjPXHsK6jki0oGxD6JST9XksNOTk+k1YEeeGBmqw3eOSLNQJmTblaef6znViv5B
m2hyr+n8lVaaGtExNXur/bS8rxH1apfAwP3Zcg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
A/OPKlQYmmQNvZ6CmCAVATkxwrwgJfVMraB+VilSZoA89GMCVEr5YMnPCrjfOCFPcbDn6vvfZ0Fp
AireBB3SjuFrXqjVZBYbhWF5ZuEMiElG3SlaNT8tp074+5S5mdlRc8IxOeT9Npm2zjrZW+enfyIt
CNStpVAKjtSDoLZzYlU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
a2YQGe+T0o9974P7/krOQMjPtOgvsObvaKv8+q/TfdA2Y895F5KXQzccAcvpD49de2XrKiJ5YUU/
UY/GJytUK6UQW7I7dUUnhu8NW4EF0P70smulBj7bE00Yu+0BW8r0m+OGRFvNp1eoiDvC1W26i71p
9AmFIgP1p7PEEDv9HuvRE+80+GPWvQqiPcgQp7DYcsrsUjiRvkJyW4LYyhBNX/lf/IAXUGi0afIn
7bJqIXSxG43bpeFspVPPoO8fHok5YN6Y8Bj9ITG858eEUi2WyWCc0BLDVPBg1EUcXGVmv4hgmVF6
bOFMLwtbMZ3T2v3TqCmzsY9JRttXeAMl/TLaTg==
`protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gKTQXJus6sElnermR5xiElH3CJw/U6WuNcvrEqms3f8G3nlY+IErizyEltXl14/AGHnUELlLo7+s
ha9/50P2WDKG/ccuxEnb5kuw4wGN785TpvV5+Hzw4EXlkaJvdcSkvovkSbTLMlLRsmWLyHFGUbss
yXC/t6Lp1DPW56Uym9uruUuz16YewrKNHLd1xHXwouiIpUL9ysZa/9JVrHxyqO0MAz/J8IWUsskF
/iqssBcwF+TO/bcUfJRN4soSbQAbk96yjWA1apJNibQyHJk9HSnCnxZgzXOkF3kHPDmbnAOvttJy
mVO6+Et81XYBVz3w9ngefS3CAFO/ujTStwu4+Q==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 69472)
`protect data_block
uLjt23yh/MM0c4ovvWg4Rl6xLMmA0Qq7Jj/OQd8u7mUBa2cQTQWapKyqJVoy8RJMGHgAJ/TR2C0f
aAttCdAS6/TrqiAlGzIeRWrDOXQEXrBc9RhMXPCZp9ZaqoRy4dnvRMs0PTS9ShTkIJnh4Rpb24UM
MWTB4xndVhbBp6xJ29Yvl9uKVtnNwAVYSUjQeCmhm4sGvN7J0qkwP90laiLPs+EGFIV+Soum7Lzy
AID1B9YL/uRrO82g72YtSCyonulS2t4IpW42L+zOFlP0eTgGEuZUfdbZEPRn1Zh4GUjzvd2137C8
A1Tqq8hWosAiteo0RUA1O3fQ2435OHNk0iI1/yFTRa2DGL7M1r/Ki/qOhx+HFrtNJcIHrvHHXPkI
4xvD/GxaqnUHh/H/96Eq3bxl/SPv+6rQMTdERoMpPVGHIiu1b1+fhPModi6qxuKc3K9HDH6UIcDq
AmFAds7YsCWTaN3FoIAfHWRYqnD0y2ibKgt9tjgpSRGotY4Va+q3CnZVuKTbTkWN42sQ3B7co+0d
yLiETpCjvvCcd9e1G0lf/MaO3jmwIKHSaPygI99/qPbADbNT+AXqxjSKMcHW0Jv1ZVSkzkX+5CM2
YnBHNchQpbfGBS8pT1q/ZqQPZgO+8/M2cnuVH43di3q/vcRNvL0DNEYu907MwjN4AXWJHxFKHYsL
1FSpaCSE5GF44VnOCEglDa0yN6XjdZ+3eCG7G0oyzu9+CxoP8OpjPNBTt+D/F2kv1SD1WPoRf2EU
rsk4M+eU6q9U2a6I2LTAXbzd0lcL3UhqevVANrUgEf6DRPvhGJIFeErWfmBXHjCpa0Ivwlil1aDw
eDzMp0crVOrPkFVwZReBPQ99I+l8TEJTsIRwhSbxqIYgK0E56QXqDfx+OliZRRvRnnjCFCReaHly
z4g372QPPrWTQ1KFp/bZeN+VVq+Jvdi8LzqWtT4tpaxwrtbKfWsg0pzCex0ki4G7moXB+6YYMxwv
NAVvD+kYHnmbi6mcMDwRIIRhBwCmU8pnMOapGgeaJ876nAZuRWu3CtJSRgkTLs/VXkB91sX/EkZ4
gCLSE3TLGTusxMTuomYgFMXpAt139BCzlbkcm2m+4Fo1gsCFmXZfc1U+dIlGvxBGtw9S557ThY7E
WVSt/vejUNq5VFFpTJ5yBqTFS6FPSEdW27xABZWTYQJmOy4SUYX4Of9A/G0cQfiHPu+lEuXG2vU0
xBoPU8oXPfdHE53CmxGh8eIAvQdTJvS3hLLC2DuW8qjqFszdveELGNfEBmMhP8GfHcRoN34rD3pM
1hAzvT+C4R8Y5palo/E7CHhqRtqbRD+AbznfsthY2FY7/EjcmCptOHdzECStItaoV2Ro/ALicZsg
WEVnCrwfp5QB7TGldXlV4kgCA3NvtL8ePay167kCNizvCo1oqqOZG5xt4cwMjpgq7ZN17ckqxmkR
IaFyxvnvq2M9NnLox+V8bMB3Vv+72Mw1tHBKlWdhm4jPgKLusFpG+Kv/LI/qmTQOJPIehvol7oFz
WyGBF9hssqvj+BPBurMC+geA56BEBhXixvWMrwYO53jBIeq0h3ZzjxmdWmHV6bOtBL6wPZluvFRP
lcpkBbuNw9ldYKMkqUt5Y9nGe2AEpFOcYqMrp1eCkpvfexiET54TElU9iBZM34RDMBDi1G7diIEo
wSKv/Qd2m01y36h/fpoLdeFsBzn1PjYPTLnRExp2AZHOl3TgRFSFssLQtreyqchYub5oZvuI/4MM
iH/S3hFbS7kfvnHssu7DhTI4ztoB8pAwJqrYyELDV0kY1tw3YRlVUHEqt6/eC7cm7pTmNHCqmT7A
Jia+XgZODiJb+IO0nlvGAHKIG+KkjRm07Nd82y2iJnu/kjvglQ4fe510dgq1fpxTmKMelJ1s5n4M
LA6WK7KUXnJgydpKIAh8JtbYXemf5sPc0KgqcFRjr55Lr4Gi2uol476ydBNuxFNoX53DMqNsLN+B
VV/kzMejCXSVOOwQTq5W7eDe5IfSvJQHsDEV7FFr8DmJyT/WpY5IIvUGgu4jgt+UT156XM+eArDJ
6iP4ob3mgXgkeZNr2AFG2Q+phm0M37miZ8hEW1rhWJXainEU2CiXtaUOwEapI44pC36Mr7nVC4M0
a36HuJBQzQpDhodul4CSXgmfCMdYLbwfjYBTLjcUvYIsxKb4WdNN/aYILRwsLib+rdlnPcQtU5qM
/tnozYB4tdnCBkIIt48W11qld/ba+YzazCQgyhfozkuwktEzS9nTWxJ/9d5bT9ooMFAb/ieih+rR
rMtOQAM9uOGWsZgSNmaXQ4i8P5auv6UqJO5WdKTLffGwZUab5wfAARqvPu0kv4YXKe+fHrlfs+Pz
m5EuTkT6q1mDj0V+nYPugx3LyYP/L9hMieQfiboBQioC+KrWtyCtrR2OhyBLVjszyMuB0KhGgniD
tAfhI/rTkZxHiuY+K3NX3cqnKVD0Xv4TqrBjwyEmNSNWA9ZiX11/E2T0M1e+7SGgVRXOtc88qepq
mjcAeydtpSOkuNg2vdDawr/jilIp2x1nr6W7U/hnOBoR9Coy756bqKKCr0FqDUkPdJG54jHY/4jR
2IzUL38fTL1H3x1JfTDhDSuqACsXeThWgF1RPRqCp1htfeEbmMW5k5v6NowpYt/mjdcwE+vurjYy
wGplPe2PbCbBdpK+Gp2ovVzBiS2THNi58/XFWrJBmTU2x18pG6h6cZFpY1GU5XiGbm+kORCpaq5N
FgOkUXAQooyYOlj8Zuz3x4HWlJVAMvRMF9VTf/Js8fqyNFqh8U7h3Ds3Law8GgiwSf1oVwH1Tvs/
pGmKVue+DkH9gWfZfHQzbCA8cJPyeve22gufkVKHLmHX/d8pBsoDXOjPzxh/yzAv59J2ue3QMe0G
eOraqWJsGhikSYj3A5f94ctPCBQrcLMecrEQG7Tbg931/2A36wwvPUbn8MKJLpKxISWAcy2qwTuR
7MnDDykkhk32UC1BP25dczmhftYvC+q7uSkyLH509pNPiAZjZHJa5yigPGgOx9k1NYYmMspApKzN
YqQXqocgEC6RQCKEGl7xHF2u3skMhdsbmi4S/ZKOBXCXeQ+MonheaKBcCFTwWlp/f3TgyGSuBMTI
facjA3RBmsuKOWhY6HNidyia7V2+bd7hBoxFBVlKqhUFJBYba3CwStpjcKjyajXO6pCAhiMCN5Xj
7FWKGGxDvXe6Zqi7arEquxMAILMtyj7Mv1mpl6OyAfQd1bWVGmOdOIAvWXEMIc2UpogxhKVHUi0Q
Cn4FmO+9LT1/HqBdzWVPt6WVIN39Y5lXwqwWx0blSMX1VcY2ax2eet9Z0Rrqaxmua5UA4khdOorE
AGA+FujXj7T8ao9ZiMCwx28pc0xowvO7HpNWZ9AkVXMkSIN/nxL6uzD8Q59qC9su1jLiaV4pLu8F
/u/rcP7/iW/VGeQ17gj6L/xNUPLZJT8zYOMeRQvRGl4aWoDFLONpFMBKnkdJ+BHbSj8iXbLUGoG3
uHnHHKzlZMpSYU7ZVBpbB3Mtzu2HTla4sdH6XXBxGaR8wbdUFD9HV6y50ROS0BoEw9UE7NrTCmKX
vwsfrhJX1Zg5kvMOsufP9NbdLad7ekaA0lTQG/SlRoyBKVI68fz5al6lLgrgHKP/MrgFZN7xw3RX
BwgrnjnWPZMHtLm0+/l/BtOzBhR/hYyF0en7n/z3Asp+BBIk+zI6AvL7alOBV+SEDPnYX7aA9G9B
k+fAym/WuRhroJjrgGrkwsMYbJ95foZmCAcFhsadfXSmWENPmmXDA9UmdHcruRYi7M0/AAHAfqsI
FpUxIpKSBRGdIMIPOXIiS+a2fFbB8SgVf7y+2vhePBguLXLrOyqbao5xGlLuPcOl1Z1hLAhWx5Kq
/nwbvYIDZpIl4OJF7OW48FMHew8EaWk8yV0i2VKkMKILaH8ooUqczpqABZ9cSSv1qi5LwMJqN70Y
frR+wwOHRChwx9odgSmNefd/aVSdaq5llJ6E4IWEWsBos07PISgj5BpHr2PUCRdDu83A6CgOGjNc
bCDMrGEHqYXeKFT9xOvxmmRu7zmW5sXvs0pGTUmqW6uOE/RJQ4KAhZUwTm4UL3UdKrP5/xxQ66im
fyGReeYq7Lw+QIMlrmTPvv/QOH04U403jCjatNZj97c+Mvc/VX+xX6goHCVByF1NvTgaqxw1BWiC
h2WthvQ80ZlU75pe7EYobZ0sNQwVEIFL/2tI0Pth+Ffh/bwdY7iIUajgIWuOpyq34Md0C7mO+c35
9X923Ad08V6ejtlt6AAehlBvfeW6+pCHBc6GOJNN9Xc9QK0otgkqGNH6f9iNNSoDaQNzkwoyNEpW
YYzbikjGWYjx0iVzKazi24Av17G+grM2KoWtHTR6W+NiVAf4p/9ZnKYzuub4AER9kmeUSgYuxVhH
ONNHVN8BBUmJ/m9ztoystMHBkkwsYTEe/G2FPJ2ao0+pmkKyC9Bn5k5BhvTcCs6c9M5xljL4scSI
oShx1sfSladDgy5NTHJzh43iKrUaWbbvWoudzNRkDz7a8B5yaeUDSPnCjKhnBM17znb21Dq/7SEo
PwoPDZU33Ptbn5dV6lXWjBU46X/ui/vBg1Qhi/ETjL+3j78QxLzYxoqFqdbHCrMa40j+DwipQknw
QgeV8ApgHP8JAm2vY1Yn3zaivl4UIHmNB4DVKj5hjccSCEKmIxYBr/G9gdcTVo4Aiqqvyo+vJsjt
zHZCA5JIZUya/0CtZs30p9oAoKX8leLv4AaiCa204DWZ7jKP9yTOh6Yu82dFYfiwBb+mcAibtXct
uuuR2xNMKCVsRiBaSJTyHqlS5Pl+uBSn/0LBM1hNkxOr6DnMgsb9zrsoRVOluNvZb2laRdGMO0+b
zjhkmWMMh7EFxhdUt2zrrLDEhsJGppm0htOrQwR3mL1aJyegTPFFCCM8ii2Ahr2wWX2DCUC0EnnX
CK7RKkZAXwo15zXH0WP6lww9zWLsEMmG1VLcVYgCaK+411EDz4CX4CoI1fROHpa0ePrw2BLw+3P0
aTJT/e1rkke19EnjpR3Wm9yvXG/fMmkVYPxWaXQKaxp3hdqZl0xQsTaPfCP/CK47Es63B7QXUzml
ydXYV4jS+PGoY+2KUk+eTgBBjDjrtoSHJv5MjURWQdVAdGnWytvJJlWAQCEzjEfBARSjqosF+xUV
REdT3BSfFZQj7WUVWDn4PWoY+isk7JyE/oLBAXOH8tefpDgzQoULKY5PS+YvD6EHEns0lkmzuNb4
I+UiASpgz1boAoDo6ja2fYZTbyZWvT9BoV2LCeG8fGypbiINPf+w78iyml5rWvF34uml1Vr6uAYU
/BxNhVI8o9vPczRmTOM+WbI6hzRy3vaupSS7NH6CmesH6zToOKaDg7WeAdSQEZzpphVRPDIYAAx4
09AENDdhwsxgV6dXQJd210Qfq7L2ty6uqW+B58TylMIpPiawfDs2TrWuOJlxHr8QOzNr8+OixZTv
eR9g1dlMDYURUt2BwRXP73F5agwhbi3PFF3Q77Xi8jzfJ40z5T3rKVOKJX90OpQgTFd8k99DowK+
SyMtKB6W00qNlvANVtK8OeGsJBLiWHguJYMtAWEH48tXduyGPZ/zNurHH82LSqFFGyUd8P9oOJ+F
pTJUZqCoTE/H/QWZxioy0seZyqzhYoOnKSbxp8iBol+6CzbW16CDjd1ZoVAke4SLgyh2+F5z2FYh
hdw7cUoRGsH8JE43E8rSXLtuw7BbCGMoSjV7+ngWUUrAfQ4VxPrnodFYzpIq/aCc5mJYnS2gCatJ
DGXG+ChQT6CLMI+3Fpi9FujFYYwD9v3+uNYzNETxRMIdfIiKujhTqKFfJkwM25DDtfToX0ZlguAH
Xk0sw+P9q1kC7j6hPN3G1h9sRjn2xByqGEGsl71hBbrYT/FMtwsjTyGPQeKxd9GuA2Wtvfr0kwP8
aoWzDrJtYuiotiALYcHF6vLzO1Gqt5tXPaodeLpz5TTa8vHvmyt4INf6XSAunty1wt88CAiR14Yc
l3ETvO0zLNwJKp7FeDwuhihE5twFuP8IJW3gxInQmypcuz7XgSGhxPQpLyqpkB2uqtBBXGnRS5fj
c1n8PsofMSFvGdyhF5cwqQqyqdXeBMMtX057AdiNrvkeQ2aTp4BzVssU1mA7uj3IObYt2iXnz3wq
9+sW0Gfwwz74TYmFL0p8WTHpT3nK9Su/0uHRpuUYX/YNvlS3IqGUUsSG9vYQJcnkTtXSPJ9FeoEn
Imexbssm/FKtR1b/EPZ8ucOI9Yqg36hybdgodBb6y4ALbFF0EXI8hCevt7mid3PXwDO/2ZjlaS6+
Kee2EnEWS+M4ihF7PD58tzDEXoedvWNS21om2l9f1koMX1W28mTxy17uc+1s4deObTq336jfhL+E
IdM+6/pEcTMjZUzMAghRYBeR0LmWKQmAcbuxURAMVe20cjyU9uwqKhPWhSGxQGxz3tIbb0JxHtvp
Xgfa31rdTIcQtugMa9R2hT1JvVZMm3AI4HQJH3+P0Fe4QXSFNf+NRu83N/kIXagCihmiaT6xskdm
/eZD5WUMbyjpI/EwyLf0k1kF/6miKG7Im3S/V/9PI5vX60IFLcwNhapahSt1whOPWvm7TN0ujnUQ
YqAIg3EZF6zaVoftAQnNB/Uosafy+hgNa9uKRtucIdzAZk1L2rO9UxxDrydm9ee1c4wzqeFMt63a
qHE/78dn3FCjtEvYHLmpBNm9gYB62WRfHJs53glInuDYz7e3XDQv0mIyo4IHkZRwjA9CzNKOlOsn
Gj3amVG5qmw6f+BoCDIirJsOlRj12qXUYq3j6CdHtBhDENcnY7psOBVswpbVRQIbXHJwJ2G3nk6n
XpgpkISO/o/Bbqk1bYuW847YmTJx0Fda/oleoBLdY8HfAYr9ouIIsSymXpMdiuf6IUy36F+PJpH6
5xRHb5lTPdwXz7BdYS6vo1TPQMKohHdbACyPNChxhktoCQeGI3DPaev+/gEzzv935pDq4TMxAEsh
UecWJp78sPiVSajKWaPSEjd0MsCPZX1geWhphI73o8P82mpjmm1tebaAtx/xPiAlq80frMNkeX5w
r9tDIkbL7HsVf6GUn9pbgwvgPVzraQbe8qSQoryZ4585irKe2SapjM02NaZpyEe96psuj7D7QX8L
x0m69/2wDJ3kBiZH/RdiPxIfZI0I7QlvYJOkvwd3mzLAoNRtmLB9ZJgvSQFVJSnba37jTbrXKPoI
1LfaqABac8DqKlIGnNGBOcAzD2fucCgQTyzPqNnrZwoWgVRT669T45xfe3QpURnJhKoG4Eh3w9le
Ph3jWGO9d4mInbmVtHwktZN2XDM3vBK2Gu3Qd8oLANGsdldXxIaRDRaM3EMqe5cQsen9vhoNP3iG
jvM/KTu9Kc39R9duRH86H7U61OhiKUredBEROdY3YqfAd6VCgeTj/MYYQfCLWMLbNPUcl33QEGoM
yEEC0NBXTe8ekQGMh29SRiCB3lxEZKAkpMuoQR52JefQl2tavC1FNSCGqQBEHKYu5pHSWXC7IZKI
bS9ngnUbQ2Yr3pXLDwZDckzcaJBP7OyFdK2lJVRhsydTPwdjS1Gn5rwM3OIV/dPVdPjBi1PbnB7Q
Do9y+6cuWcnJRt5AALTq0ceOTuZKSHbx5ZE/zZ6TVNmSyCqjtphYPERsD9D8/zCuxuspEcAIJuSp
cVBLAQ9GicxHFUUmkYNfULrAXnHb3I06Jr1TqGswzW1McgrsRnTji/TpxHUqGvmL7OmeIo4H0oen
MZHDi07MZCjNtziJx7tzUZQsfRJjxZZ0kF7A2MsSMFvY+vlnxDASfjCfHyQ+750LS7qnulpKbmdj
2a7awYvHuQBW5EKcs5Dybag5tRejB6M0mnrpKI1aspWudjHP8u4ST6BuL4UusBiv0nICejgi/xFx
BjpIzuFR7fuqKchTqxCmaaMI3G4FzTUqwps1qfZzQBh8ed3BFclmah/+viQlF73vYXRIa+OyW+zZ
rsTZugY8fkLGiPU9ACcShRZ+db9EsdshBIuKrTV8zKFa2/OXSiph7nWSphXhluY2dYSaEgnIJm/r
fUNLVxULjnKJhDdDiOfdbp+qWrepAH7T67wC3qkpOAISAV8K8OSuIbu6cqE6ao+6rhFBDqGv5P2n
wb/BygYmOA8/Hi5yCuPqDAjHw6k11gaYXBrHId+iX71sRKVcTMt5arP1pXeeJ1pMJ+LFtGGWtSve
bSy+GfXe9lt+i5BkdYAGn3d31kdfr7UxzV8whs9XRcUcEQ4v0UOf75d3eIxkl5PvvaAXnVjg9OFy
18qh1+5PC0xGJsUQII50kbEMOsHS7pSzLzUfHGUNTR4FM0Cw8vAYB/MzRbvnLuSClL0kSYvkFpq3
CHn48i7ObAvHvIfZux3zop7pvy3bHa7Jx0ZUVAU0Zb+efm7jWtt4qaTNOafXksJJPIyDNTgZvtw4
mMkrb07WrQph1MTVQdqlMmkUOq99qxphCZ+1GbOaXmEhWNO05NrVTwJ0m2ROebfE8yUIDm47IjUf
Xunlymovps1v2/KNpPPQG5CHjIjIaOsDj7Dwam4UfSlt+xtu0unj2BxA4uUxwdGSDSAMptdOkEy7
B4ya8el7TmF/HiQkiMIlCSPUzIVAtV4p/3UyW91JxX7tjUhDb3/tDhBE9IzOObrIYNjFNv5ZuE1o
w2zYbEZ+BQ0OcGgEgOMqmqAjKNSsn2wDQrfSFNKFo61iev32pYmaELM7f36eM+RNd0JWLK+xwl1l
b/ftcewHUMV7jTlqAibt5g3+iVUpiKEyYCpw66ZN8blIp048dIBOzrLTKsYmLmLjCVQHjuWLTEc7
A4fs4FWJluI+KnXcxOYgthqpf/b9N3njGsAxFynEGvq12AGAXeMHtimIrXAHc7kF3i0cvQ/Tt5iA
CT3ASAELAxke2q9V6O3xc2IDAmzVvg/LM9l3FCtKDBmhLjf1d8hFDXxrjW6Q0T6AfbKiDqyR3v+D
tbO4UeDkMb+kVAxTqjPfFy2Mob2usqqkDWG4Talc589cwxvEg5pbyWhMtiTY/9HlW0k3P+kJtoUp
bsOTvVBYNBAYOSkZVEYnW2nFIEAajcpzCBe2ATumH3PcYCr+5TcRsLQlsCqDhh2H1BsaIwWCsmEA
W0x2/rrQd5x9QhVQVh7kdq7B7ZfOMjHf6KGue1cWpWVojSjXnPA5YcTmQHBguOwFMtSaqnXhuESp
ZZjqC36m+ojgfznsIk3R2opbMs8UcdvFRnrrC/IqKxQxh3Uabnk7/jJnXAZZV3D4/Ejqr078LlsM
85Edo+Wy+weCxNbGhg8x8bCGVS5YhcAATDHtbeKnhqSzv0VGRag+H6/x9T+fVhHb3IyO2R+7yQoR
uBN7ao2Byqmnp5Htfmy/dlWwfhr2iwR1euslP0sn3gJTkxgalcZCtgT/MXuWTW7N5LSw/Wsy5c+0
d5WsQjV+zBMbHJEYsyVSrLxvPK9qzDvdrtvtugvyGcqAkzIb0O0eqk91RFYsBqIfxIdJtvL231jD
VLf81byatSjipvdlfAeOC3TacKxhpCgkxMLtZVkccLneSf+HPFNJggMmft9nxGeLuBGykmPTMNMm
OO/e9k41zug8qKkLsuD8EjqJyxF4Cr1QkkuYexoX0pq5PWTXTbOC2lJZKimInIvhjUtdfwDePfHv
K/uIkVLuSoYMmC4kyqcnyGwLnlI8ML9KWNkE+0XRQyKdLhecatd29bWVC5eLPKQOsT51+l23knxC
0n/hn6DQNXWEgnpv3WnWSD0zu/9qhHIm7NLZ4jVly2BB18cSg65tWUp90Oty1gEWG5e6eSXq8K2f
jvRAqA1OnEUeJHXdd1M0pqEsUSFhNzVvTKh/HgyIcCbvmr4vKNKkpbi4QSxEbe9ypg5o3QGJT5Dj
/xhrQrPRZUriEqJP50OuoFsa7FADYiwMyiyyvyyTXQlGj9Xh/FcuahhEJIS55GGCgXHgSUWoaRRx
9YNYydenlSeyXkHjLSkKwfpN09OX6atmvv9kL/5Lx+QmA6EKulRCDv7OU2RrAYc0C3Ffo7LqlTjV
UT5LArT+ZV4erc/F2gnQfRukCIrEblLP58l0ILRw38mZFvXAoYuo8EI6uHIP7lokDsyBxpfy6+Im
Vu0TNkMYez+9PqJg0Fstw09QN4UMQXFt7AGC5V2AhfarfsMH8CAxvjvZFhptBwuRp/GFrjWdJtxE
U5P7NQ6HqklKWCAkGL5IrDRbryMJdEkDdua9fl8utxToDRN7l5TUebU/ihXnv/9i6++q2Jl2ATVn
7qsiNeWmUlBFcmJlXaWSHSHiyvBCrslpRfEtlHtRSYHlvvjWTi1NsrcZUNtuLwI/z4F02c7ulNKe
3NiHJxnMfTBRjZPtwqJjnSvuoMz1N/t1nzXNLkmLRFaE9pI/mLNRkvJvB0+WzxyDCmqdF7Z4GmWT
wmwfDJQyIzS/kgVfBlm9aClA1OmuiIsBhVugCGpi5lYcOEjOL8CeEa7wPt5Hycjag4lMRvPE4r/Y
XXwMoUVI7iSqpeC6Xgdc/H0/2+xhNZ1lYMOG2zfz/largSxcaHXVJpLyTKQ5KrsjgcBaHet1tRsr
R3D4pVksKNSoOxHIQA82QT/Y0j6NR1oM2gyZDlm25kFk1y3mthDIR3pzy2YhFk21r9o5xrr6bmrY
XMML7OCen9dwhd3Gurb66IGRLod2HVRMxd4lbRdVEWni5LAAAnujYr8U/mZQO//xxFQ//CWly/nJ
QIhetgVq+Y48eyXpIuY3wA8CF6S3a87K36SLsAe9hofPVjonqaIu4Geygk8eDYuHIuR4OJh4YHw/
AXnpC8pk7E8TKKrtvau6cJbGVvNtlKQCTQIDhN2noiyClzyv1fc9Gn3KgXkudhUmlReqRNX+xQRM
ESjosVvhhO3X7eI9zEyaPBQUScFNSwp08lK1VMvhMSz4RK7dcFH4rtLk7uMSD0g7aCARJbMbk1bD
zxOq70SfzvSXwTutPfzp7C8lWY6XgvcbBdS+BPqQNb7Wnj2CcEPQbwdp/t1Cpa9zZtkBX0h796M4
Msjb0m4G4UtFcmoL3GjbydwCTD+vqIuNT0NHqzULzQhmHBIguIvUG3C830KFf0BJHMuZcpykHncn
VGu+IDkepWaQVSB+gSdOiMGAq6SAqQ709ECX/twBqGbIBBLyp0LyMtZ4tWO25DAfommGCiUAG6KM
+v+TDMStUwO18pYEI8O6lQLpYbM+UJE1FWm9quAThYbKHH33unooqcZk2H5r1W0nHLGVtTNAssHr
db5YJxk7uAojJIpe75CoksGKQhiQWOVZG+hyaj5+sDAwNe8IZehp8mG1x2JHSgmSeyOVz9ccbvtz
RQR4wxn0a6pXYtpHfR1SsZo2U9ED1aqZFaU+cG4YAqmhdBJtrq6sKkhv7nqMVJbIfs/LzolfJ/qh
Fkma7wgB/ysCQmr0mXpSTsGawxk6PeKa5HIOlKrKt9YZOTIxV0j7tF34IHvUSYrmkkVFTWGGKSHs
jVUWDMvXet8Xu9vPmL4KWXRafIdy2wPOLSv3OAzs1exlAb4rOrVBbeYGmou5bveGsAg5TelPzfNc
PQR+VFFl/j7XzIlU7sbZieAB47RCN7J4YFdcm1LSOAmLRm1mh4OktQIpJM1JvH6xuMm9XKM83mB6
YkHB/J9Rb4w6QhhVcSoYjCQ1ogQOqbt25K6dr/nqU+V4+p5tW4oC+v846ed03COPadTkIvj/YSUg
UgZHJCVky54C+PBfXXxElpdjo6FbBBBkuZs7sUpNprjxeIYf3/9ugmD0SOs8JQ754sdOQd061ssu
IvxBcuq8/tswAekdGUAKwLKYa0E+283afszPJdy3Z2FsR0njVmpu6zk8B4II5CYpOaXSip2GBtmv
7f9Y1NDBSuzN29QWyhUe+g5sYUGTRchZTqrAdCxiMwudo80rdF33SAVnPhivesoGYrkXsBt6PM3w
pHPla1iv5nXD1rDoOMnY4NQC3xBJmBwi8pMqOcOF5/PaaL3IOdeHjlfX6DKEVuwdf82mdpOa8Syq
BwTxsocRgrhmlW5/Fo7oPloE/EnvAUI7IkxzMra1S3BuepSbHZIxX85fIioCmLB4upiqb6R9xCEV
EOIc1oGkocasqPy5gD1v5X+xEIPFu/x407AbZAOK5lSpcIZV0aHXxNGYUH1EtRWqs8moou+eCPMY
2LSb53D7FGO+S5dG8Q4bV/AX5kotvdBPi7a18hBJpppqfrK61b3HjmGlWOCQV2jfNkNQA8dBtHkf
Nd+i09iP8ctLFHmAV3vu6RQ1LX6QgTz/eQDU2HTkP/thnvN/Et9dTQ/utRVx4CIEQZ9UPdOVGrLA
5OyNvjkW48h6ItAj99ra4CzslcveNh0AUPcrkonpZFp5rNOElhej0G3Gkoyy3DVeqb2FKJF5QLpZ
O/jllaPgRYqW5Q3wE+f+D46JGf4N4xhEnANaxF4rgsFxt/21jZjP0bFj1S/gdPvntkxD3F9SchLb
shztlQufdO+XsebobF1O6gk+RD9E7YuQDEtrVbb/ZdcxsED1Rf7VTJt6HljDZ2WratVVDa5+5Xad
RdXjb+ah+CrZRwdCqhcBL95NdjmIRsordfyeZb9QzmC3UzS6XEXAOWVykJfPOO27ac311gTmoV89
deUMfsH6y04Emt2DvZlWU2K8td+VBLEyqpB9KpzOtPUU7hUjgamPOXAL6iLBy8gP5ut2uBgJeLM9
SKD1i5k37QYGoWarfaWEZztoF6AHpT5P7MLRcxXG5NBoItDDUPYiWKIDhz1sXfMYgUD2kDkk7nN4
ZpPxujQ0u/CbTgRro5uvMJ6nNRopV/aCXXvWwxULTt7r4bwUaPCdZaRiaM33L1NHRPz42GJSekUm
iH+qqK10SqUu+wTkyi4NCwb/Iz0vaZEvW3Zn3ySUmzr0W9OXabRUFn/cn33cHC8zbAhnkiEQ7UHZ
W0H7GlUTeKwh+RMvSxXhCp82sVx0lz/M2BN3E6PQ+79jMmahrEkwU1cEHf0M8NFLJf0j/2REtIec
iEgmjR1LoXG+TBZVbcj33lA1IMukFlVytvJxzt/245iSUqtlYjML+VRlAjQgNDT3HqKY45C/U98C
YaHu6B6O/DbbqSLfT8Qk/dGDBIA44/5+biVcCaz2p+wDKbQSnkryAkt18fiNlSKYWIuOZa16NPiE
wuyEaoFkGNBf9PQ7IvU/nA1R1iwcvx97jYqXSNJJvqOy01cPZAbDqU6ZTEs7vQ2dbBlkZHWXg3v4
+FECanTSjc3CS9XytqvUNG4/VyX0fOzfS2b4X0JSlOZThcfgAYMYhUcPml4YQ71IdpEGmu+Yqmrt
w+g9PoR4w+LcsidyHnEo9ijPNPn+xxN6eNtgNlfldsNl2XjBcZsf5qF67v7ntUBaT8BzGppKNND0
5eT7fRUNe5ex0bq1nNxAhZ9sClLQl6uX+QQmS59Rdyo9DxAGUPVWzp8OxGdnUS6IYnbhvuIS1nFw
TtXsfj0ewGj+gQYqvBGgT3aIrFS3fcd0CvF9mSXES4Q3sggQweiwfGEIBunjlWLAAZFXv+hWoe06
efILk2Vv6fwZBkcmV/C+oHHDPOyo6ejiNnaeG84DRFq66Y/xqQi5h2F0rgUlXnxO23m9TwNavkQc
/ifD6fj+V+0mz4exGfR6CUP3oxBvDdOJx0bOm8xg7YNvlAY3i8Nwry12V9OJDSGFLAi4LRJTO/vA
9KeCFpaAT/Ez1zoA3s1cmp6HmkmpKgerUPyAwRZUZN/CxqTjnaU8QycNn1cDshUWhutXLqaUWysl
yboNuuvzfKvsMp/wnMaq6+Yo5D0IcqFZKFmI38/USfmRFZGV3D8G0qaX/LCmZYJ0dTRs96m5ytDa
ZfOYM/1bMNeRDMnsCVVDpDlqD1GMlKa14MpxDoDYCLqtqXBoQnxFnHEOhsfXtKwtGw2T5WCoiStl
tHTR/qUWP9zJGWCttdjFujtebfG4Zz3z2e9hbKJwARROliKzjP/wmm/AaxeWMVw+/TM6IBOlTd56
IktonLltljCp3eNQjQNRsimszM5lHq4Ly4vxnxYcojsledjkS7MjtRMpGNWYj0a8dWU+a6hxm1Y9
lJxUNJLaQvXuhGsSfmrvNqsdYuE0GprYdlH9y/nOIuJdy0VnVZslo6TnEZOKG3S6HJt6B5EHEd/s
uiDT7T7SxPi9Y883N80YoVGa8Y9dnQgxFdJ/fzijQosLQHluoTldfpQBNJCV+uaF43pMfT3utv7R
q+IuE1DzMCrU3/V8JyEFSbUZ7uKvyfCcgmLQrnEirzMDSf4bS8Z6cATk2O7la60zj/r1QpzUCosT
MQrYfW5C87K/yFTo9PpXYRwxa3TPW7awVif4Cj4MUBuZigcD+1MEnAqgBbP0FUco8b9CF+foRHi7
Kvxkn3q7bnxfi7IiMXQUycTgVJSRRZtFmSzZ5IcSKBkPG8Pye11u5101tN90QszCvHj3jvNLBJ2b
lYMomE4d/EXSoRTW8Xy3kbcdO4N9fUpU6D49YaK2x1mnTJ4PvcZtMBjUkoA+k/K1omj6yn5m5yLu
UadzqD8l2213/5C0lkqPpQdbliEER4lF3aoAYMRuFNNgAbHQgAYayfgFEOREwzE9Fqo4nZqwpKAd
W0vsFl9TkOglnmAMkjCI59K579exgODTX8+mR9l5jfOdVltf1R0Kf8tKKuiDJotnaORobV/IBDxj
604PTZ1yd2ryQvKsqtnPciT4alQLHS01XSKa6BKoJdySG6sY//2lFz+JbRfu0zD+szu5W5E3DScX
HAdouW7IATtw8b0wNuLRrwVnJNKdU67G9lw05Bea/QwFpBax8DmORRu8INBVPGExud/7HyLjU0SS
uPv3eKcCPhIIKTQJv0p6FObOllDXxQBSvrr2cqk0fwwZTl4DkF+6lmS5DXMj6b9iIPFiVv9Y1AhA
NUH6cREbs65IcNIswbqVkmQBFSnHcLBUJVpVI2jPVQ1ZaJFjVHVGzxBwYxHqRhzV7hOzhHis6UUx
iDBPxGFYZff/Q57NQqQqqojVasT0peSYhch7rUZKr1lvFIQjVEslgkoxYyY2xhRnbbR/HLIIOaws
9Xa0TsPkLVAkHXvQyHEwsQqxgDs7npwlLLyMu+lmesy52pNFI+SnxArIYGZLE4OqTQQRsFR902OH
eSR9TRSzB8B9MreVZInbr4LK+tE46/u0fXBTUdq8Pf6E8aly4hoqRvPNxmqLovsH4iT+OscGoeb+
62RpwpEfPF5GOO6+3pw0owTvGwkjeuTYvw6ufZZ7AGWbokbHngFUnt+dswh67cHqdjyg8g94Y5uP
bWMm1SvCSWUJGewhVlJ0UIhFvZLy3x/unxmpOJ3V2al2ZVa8CCFdOZzpoXhV5M51pvlvaPEeFXP1
GFYSdOwaN4joMd9bt55wqQGV9gT7PBMv+EP7UBEOy/cDvUm8IMqg41tiEbt09y4UxamSHuVTe+dI
S1BYz+abs2gRyaNOfJfrQgl3/DJw00DvS0nAevi5mlF5ERqoNxRX3qC3CZ4vVvgYS78RW/HSy7qy
ZNY8M+LLN/Arqp7kZn+JXbIa8PbDYf1fpzvPQyLR/5ESEh58ZWpKzTcpUez5W0W7QKiDgwtNyFNp
RZoLpR8Pb/ARe9Ayr5cxuRWk1q6W4vxnfowKaumTl9De1BxyhNTQiq67pP9Z2hSY5z0Iq9M0rZdE
HYFAo+MKAF9H6+Nyr6762NKxnro1FUzpwZE4DVSVioJYFKVIAVpKTSCe9p/7kAPqeCZY7CuUTvYv
U+kvsEA6xf2KYObYHDbPWZorCIwETYtvlf7hZVzUE0GfjQCedE/BicUKnLqwH0czzrrPWLcYF/1C
frFqxi29XJd6aItBnNTs1mZZpSUXVi6he2f4V/6ZKU9Ct19ArWJ7l7eVdxfOm/Q506Jjs+/f6K0d
m8dpdhtzqYgX/+msOZd7Y47Ko4Bjxk2JT7XpeIJn32nqMyjnWFoRJ8gHOld0nJVlUZrmFwImQXCD
HGlodHZD+RigiQyi0dR1HW2fhoica/6leSuPRVdlSdVhaeC4epU9LXaOItSBZulf7HU4TfxuibZ6
U1QB9Xnah22/pcdkY0iTjEC6PuSQU4pVEvg8VlIFJJgt98pLHLeuzoCrDIcATRvGPjlek9gPub6r
/fvS0TkFq0aNQiqy3MESMYWWURz4sKsHMMplY3QSZajsqGWjW8WCwDY2HweByqbM97TmG04Nc03K
b8vdw+YqqbcnjcnqYldsVG8H81LMx7HklrOA6IKa+f8e1+eg42yY1HnVlZbz2sLXj76LBAdMW0y4
UZotv1yOfCIajM9iB++UaA0y+niafTwKhW0qq+8aULEEJ6LDyziu5XpVVO+BxQ2ye9ancIZH8TII
obtaORPH353+jYIJAaeOgksSAgLoukISC06u/wwSyPL+lB1P57TAy6w79vdePbFfS3mwgz1RMdYG
RR/4kP6pvm6eOVW7vLyoJi0TZyZqI4bTZuhVuOBTu1QBQS3ULe2krr+CvlyoWal2Qcsdb6Xo8fZR
yV/ouR2cGun5ms/gC5qRz2chXKLvtevK97AXFJqX/TTL2nvqrQZOqyN+dur6JDgcQv0+TpdGFYvg
Azo7VTCK3cg5gbasKMm0VRv/liSzfmfzjofnlere9RTVvQbOxkDo2H/WNUHHQ2S9MQKaOuMV2gAh
0F6o6ocAXbCxUVnNB83PV+ani59Kf+HbP2rIeRV2N5sJ1OrQa9MDYrnodNdSANrj7YK5idE0E4Ed
wxUVRzwP2weTMu+3CmXTZW0umFmhklNfIHGK0eqvqvI3rCCuRCpzYxwxq6XHEG6i/9ARbydwGnJp
SJ3v91VLfQQveKY9XI30qqVxBLdNAvNh1IZ21opnuBiV5+IwKxkZnxvdRC2nQ98ILBTrktoqKgBp
+UY5uO1pyYslLLS+nzXK+j5zxM0W9lC4HPGNlNPXpetLwsrz3vcwosCumlesJ1kNJjrknRrWQJ7+
9pssHAzCZnKV5dYn07HOsGjILv984eGYezEUUWccRcF6/n+X885KqHRs7URAYsjoiE3AKTC9U+m1
NLj9M95C+DQ/bt33zMl/pLqbz4blPNTb8nWz9aFoHMi5oGDm6I1lYROcJkGXRgs98T6TzWwb9d+z
iRY71dWpMV75iAxIwnGmzGipb38KpOuJy5P5Urx/kEx1M9gDdJ3HWBAG5c/psB4bddU+ZP5bS0av
UEGVmn0U1EDtQ0Yb+0OZykK80+aXQGa7S/w9i06OOem7kMqswoar5xqNUNUZAXzlMSwXakJgGaD5
3mEIDlS+BVhlIgLe2ppYdlk2wwasTKWTEw9GMipukAr7fXZ+UtrLnl732bJ6zCW9ILx7sK7FA0E6
7O+WOoGEg3z8AcU4s/cTKlg56D1E/eJk5Ceir2aqiPj/+SLMh/e94LYG52zdqR+S0tOKAee5LDPM
cmbKCbpi16Cq5EwiEVvxF9ou8K67WGJRxZswcQt1Mk18zCi9OrgLoHsr0/miBtcbm+HuJG2qPFAr
J/1sIQoveXRxxBmEBWdpdJc+BO3MNxUa1fkh6XaOB/inuP/8sbz0s/LFiIBmOAMNO3GjZbOac6C6
qVqJlQm+GqEIiKHAYbCd1wQIbleiYlw7zZTggxmk5pvkbWQxXyN14DX0zr+SXoakBQtpfl0cBvG1
J7JXkZHRLYjGGEcFKd/JeXSJFOoP1d+Cz3fZCaqc9Q8TRIoSopC3V7GEXHK+xfDgh3SYpEwz6iVy
dSw0xl/ltZDV2kfmcvfz2rpdESfkNTfB9s90nLqmxnDFn4SVoVxAAhPpmQE+HDqveaDR2J2RbMWE
75fJIJqZ9QVWlZLK00stOg+ZIxNGZVRIBwSnKpWJ4oQQfGd8UIrIEh2ccaS9sFZ7iUO8gm1V5+mo
qKg+yUrQYlKNMGVn4+UY+yijiom1JgvqdhhT3Kq3+B2sVyl3A8F1sv07LbdbUvTjSAwc/GPhb9kR
Wg4apyWRKF8jXoJgYhwktJ95J6oT/zMIlqA8RGicOYehWcT+XssUMseEW6geGhDHJdauQGr/V4vb
+bbH/cHIW/IF8hTaWPAYNpGK4WAT+ZbOAqUrlWq7LStNTuaVOLfly47looenrBt6QFNIEiE0Q3lG
+74q1iNmTOhMBBTZqfojCrpfaFeMIP3Kl6Mgcy/Mass4hLzIck+cjM3DmzBPXFRA8y1lnL78Jy3C
f9GyKWTEM8PPLg2gOpTlkCXY7KRXcYr9xqNDri68yLG1CSYHTlQchd8/z2S8libbZp0ILXFX3+p9
YA+bDwuXZlrKG7VMU1F3fkFJMCeY7tGVakc8nH4byWQMAH7zJ4NOVNb9imnwpOvuD+s47duliX+r
whLhRB9UJO2moYCETjspzlu+P6KfYVH9uw125YOKNPYOxLMqApqy4IVx0upk6iRycKM+gygP+kRk
6zDHPvEeOEn/DauxZhJijLcgbZfHsfKZoYs9Kv6hkiodAJvKPGBlKuMMytSmxyHLLquIgTjZMBIZ
wU/A0nsoq8wxl8RI/bFQGoaY3wL96rse+FJJU1bkRy+7oa2coQfAqTG9CfAPVCsx52U+irESSTL4
hvnYawAg9W8v2Nepb9KaQSGsgeW5HIw1Jovf+AAj5/cKaE4sZRt0BekpTddwo7bzI9nqRAdGYD73
uiLU3CoyNL2GoLdAnqzQPnz4bCsFWGwj5Dyjt+higt2WUHzv8g5NMimLAB6CSGDmUKMaEFHsH/kd
2EFo1feftDWoVQOoEjhjAcSUY4rwcUrjdYVcVZc8bQW6LuS1gsf8rhnvaN8oKy4yt0do+PTvILm7
hy6Ihv2TMb+7EwCZ0wDA7yyZe5M8zD1RvdZhWOB90L4BVMiBr0v2otlRB0Wo+e/mYp8h8ZkfuziU
x4P97DquT+sUDUXvbeS6R+AIOuUxPPar761d4SgzEhpDjx3lxh2jUKa2VdVCAjEnJ6H61HpEekf1
mhhJxTIJ1ABGAgJLJCj6ViExvbaPNqJ8zcuiVtKgcWfgOtI2kk0AafuwRz3qrgr4Rd8efP+hnxI/
N7Hq2cnIaNlEnLnk6SfkJhtx6JWt7lzFjawC0c8mUHMf20+dcgSv+rTOEoYZXlMb80uDY9+eOSNa
HftqUH+M5+QPfZPtLHybclch+XXDF57DNu4gSYzpsVkatbS7QSyW84IQozi2frN7sbww4d+5X4vo
xmvzSVwiTg5BSeEBIcLecev4VHTxORO05bgo1Ic4sdCzl+C7sLBdQGXkBJz/UFdnBRW9fNT8M14k
I7vvNfdRdArpIgCW3vcLcSTV0gu3O/xKGud0ifPutkBSarcvqTkE1blo/ZpF1HccO/yLr52dpF4r
iuwf9rQoF3Wq3IlfnRmY/JAOnIp8VHzYFFVL0GG+al7w9pTThGySAQdXmG/Zwe1FigWuGhX5oEj5
UWBb5BJ2eM069L9NL2DKG57BBMN07ENhaZMv1H3uU3DwnjOqPWy5NYcHSLixOVt7n9VLw2x0Char
Q0Rz0/WvVj1+a+Ik8nSYA6TbYd7GmeRjtr9Y66PJXdoJJ5jAu2FBkF4qP9j1WenYkvg5QxTD7B9i
hQO9nRYMhT6Ns8/cWVQrdHeusiYEwNWNqFpwmyvEDpxdCqm5g+nPqum29aBBVLuzS83H/eG/rV6y
e1OmSKuWsHB7H6QIlZTZ9W+BEt9KABMDhxHG7tGxK/yCjs5RxiIanAnfFFZdmsTtiPMAjcbkcfwZ
ezpYtCAKz63QCUIjBR3IASGu7XCTfOrlL76A8Zo1W6xYjxxgNEHdBC4pu1dI8jP+6+IqedMl7Svl
m6BbZAyt58vtwW4H28spVlqfDB9KE4b242Vo4ARGvjuZm1gOgbrRSFeAJzU7HR0vJRNPOPiQYKKs
tUcpyMKzGj+r0LSist0mtN35BTy3ecO6gcqXPMeNh97g8e5hea186E64SMUO4DQl4apS4ebYRJZQ
JMTVavGjLqbP6IugQHB7AtZCyHuByvWWAB6wIViUM7TkpRhrP03jIkuHrew5OU/qkQGtMXJuD1m8
gxS1MFtoQmPOeab1+pyTUPFOTXO8eD4rOSuWDifASnEbjuNKhv1KpTr81ueuUkn8gwR3LXFWl+Q8
KwS79UNcQqwFvBdJcvH5epDWQZAdq9q8NJ20wh0Q/diuEeKloA5i0RLewDRMJl8MHmcS4lCtWvf/
QTn9OySAc/byVTb2e7BdS7HreKItBpmO/YwuzbGbtTWe/Bnv661sZednP3+EwsCIIaX9t0cX+KnH
RxN/nLPQcBvMJllchNf3zmhtBya9B8fxeMsUQnsY1q7DLYYHrn9o7/GbaW3bWOvply375Ujzjz+7
7zQqt4vsJlI71dNR0rsZ7Vf6xNYt6PIjCLnUbv9NzUlYyfsn1gOr0oZYlGqGNu+VhOKfJYyjoIyn
3dJYM33zycbjQg2ZKr0yoP3KcAq8dAEFkvjLCviuwAPHWoQKVggkXqucr+2rV8X12Fi2UGgw13kU
KZpOToE1iVb84b7TWgqmtRZAbSJhDJgA6SX7jLAN9/E4jEUG1+74yre76O1VkuiveRx+1Xyk4ucd
Ee3HhK41S3I8zLI05QS3KMRPipaZ8OKX9ep/y990qa5Ped/17w3egnvIaBWpC8kDdYs7fxYhv8Us
wt4rxnwFb8to+aJ29vbZKpnbwbe+8O2CIklAO1QvUIgpfTAnkz/A6L3acwMCcS+cvi+ZCihduiOn
5V4rNGx5Q7YqPK+BiNhvgThicf3O4cquSzbGREmMWnXDEGzXi2Ak8RyWj1PuZHRGbd5AHTijyKbL
AAw/uoVkLiHo8cwQGqkqRSV5eK0Wl2LHxsUP5JZcCQ6+5gV3+TZC17RbRcH0oS4VdMgBQb2qvbVv
MCDPDoJArvWv23BOrFjA+ygr+km/WHqkE+RaHoI7WPl7I66manih26sE3ihWB8D5pKS1MVPR8rSe
EcONdJx93Mq3JZ6l9s3XZUgsTOg0d1+MWJgvxhoMhmZ9zDnTHIqQEUav+0T/L03N9ZTn1m6auxCu
5tc/DddARwsCzpkDU47zwYjcPpBfxNLUKTVMSUVvb/zUeU/U2vwJnljZsAYuGzoA/C0NNXh/o8Th
3vqOrKdxuetUalWpeBUPE0etPdRGIDrM5eeqqsv+gz04WHlk2tko6pOq0KC2SSeqm3USbcdG5XzO
a3XZuQutCteOzet9/+ZhIdkcHC7Is5YrPxoU4iLIi7aN2MnB7DvVwneLdwvBU2Znsx+pSrzUiHyn
vY+VAqYHhb/V12qE+heyav5YVtPaH0jtojj+J9Pul+QbnAc4oLdGz2c69lMlrxmwGeq+JopJm9uQ
Sr+oIWAZ8SwNRBBzOaWQeUNIvsIOtxFMnl2NWKR4MsfLD36hyCiQUjf8EjxTd71KLjyQfgSFTE+g
sFZ23ZeetEdmKjBUIZviRcQ16ZM957a6T/dJy9enigtsPE8O6mmkFKNeViBl10F9qAyr8ZFuEqG0
TkCIIi5beA3GttNCHvBpHjQaGkbuHiNH8R7fhXFFVvGOXLH+CSH57p2O3M0fULmW6XDll8MoU6jN
F5pE+r0RMf8BtR2Mr91iB0WsOZBq0ZYn14Z/K2RV1XpLeTsrusgIisFGJEh3gCGN+uhVhLaT6S3/
qkg+O1smTfyHzb6MBT6ZACxnhRTVnSnOQ4YgGXphr8zUTVKGjRwrKTfDyedMmBKIVxDPMBecD/jP
4PUhp9K6q2prpbNsCuCnC5BSCC22DjpB28+lDnm7ZzsY4zqQwNWyStYNm1e1TdbbDpDsAyu5lKNn
s+UcxgeUx74QDZ5zzeAl6vI11FAo1CESBNRV6N1SbGxBNESY1/B/fwU41X0WeGEMYtHHHsSZ6ik1
2r6DqwlEElhR7bjCgWd2vKjF0MsbokfihimrgMqyLMAtsdhs7hTvwlQtZRRLFjGicKTYHn/X0Bxb
zcqriBf1QhxX8VtqqhQ4FDrMOk0nDjGMPK8v/xkNQOmiesPBCYVBQO8tp002fQhsx4iDF9VhO+fp
ABL06HIbQQsaayKhOg29379QgQlUpq4NzzCRfVICztq3QQ/rw80d/OuM9EqVDSur7FLL/0XvJUol
DRnE2GRvUCNrzVw1tmlOmD+AcMCYnqpb43H2igZ8BUwvgXRKPcyvK+BF0oPx+C5PFDqb0tOF2PPP
DIOzi0RcK4QnmWDKMwJnS/etXzZn5q5s0ZocI5tiLUmMDqdNBrDmJjENiyZOA/j2izYo3FYYV/E1
x7KcDYkqPjs6q2eNQ7t0lCZ2q5Z9wH3gjr1xAjK2zhBQQzX3NwbjmiAp529xFFndgvQPUpIJovpy
ppDqNzJizS+GaEnQ0qlgEjipqXvEAOnvkHNRW4RR6D/5EbpNIh8nTtrWscgTroNkmM5/iqbW5G6O
EMQ77ezfV/vePEGjXRzI9g93x8ReN5eajaX1rJRtWs3XQ767Lx/X5k4oyi7kZc27aUnHChdQwTC5
U88fmTwMY8+7iTTmXvm2qhNB+Cutc7YmX/2/kdElNVAmpyTJsYjoVepIdnCPtPCe8RY+aHL8mn3d
Qqm5YYfmEJRK+rVmEvntkGvi46TyNrvel4rRXA74/nCPzS8UaEaf7/SGuJCKCeaU5qL9QWNr7T6h
PTWQR+y9GJg/y8uj9IoRbKbRvbXBy2U5lbWMx/6aUql9a+9l4IWZHwAa5FeR22d5CCgrnrtalAm5
PCR0U1cCtk9CgHyG3jZ5pFKyQOsHwInZXl6bEBrpForc0fuJSW7ErFjCeoZt5pZMNx9Xgtg7LQI7
6RBM0xHsXgBEJIOjwzINlFaZ2jFjtb4ZhRFb5lujUc+KtCElUIi2IFTmAcOqG9w1xsduk3xPQ2cQ
52oRegvVco7VUDXwXwkbf+G3xynoR6fufkUPnRdSfVzTmyvOefVAn0CzovnB2ohI+onjfAxLUeeS
XOtRhXQEoW8crTS3OtzRviVgj46pJ2dbW6StUBkJsqt1q43xHx6SlNs+oPmtKQ0lfpIykJrqASE4
aKerSas48irNtV0iYi5dOQdQkGZYQ/mbIl6FRm4QS4izWT6bnhGDEO0kF++wkGVEb6J7iJg0cw/c
s24m4Vo+1qeuwx42ZFqj0QhKO0UId/BlBkC9biz7pGcINtpX5QOV1WQ1cGUbHNtH57vCP9sAVDIH
ZmSqEGVK2020EybT8ZTXcROEoGAux3MC5PUHPAObBTc0LxIq0o8OG6Yl9RkhTL0ez24cFudk3nqt
zMLaP0DqUURqO6zpaXCYvDDpzV2NcH9M0vUePzGJrDIiXZN5/WVe26v6DhCZ94Zv3pbGSpxpkXAC
12LpsaLlA+uMaOEGXe9V7boJ3ZDhyeBbYadDAO1uczXgGaOiJdMutHbUfTDF+syAZPTuJSycNogI
J72712Yttjqxi/oum5JWUKKmhXn3hYW1590JvBkM6mqfCXPr0zXGmoEF9w7651K8ntmmExL3eRxp
8jJbNL/LrNo1XdWbeyZws56TsFAMGK660zn71M9tOpYwuyK7S86ufZLL3XDiDkujc3aHXdwXhfGS
Q9IsYovOlE6mvrm2X/sQHSMWErwsuAq1fNOR2xyKeW5PGMPrvoJY7N6mSXxug8tCuHoCyohP5vu1
mtP86ShFUTWeUJMn+lhCGfBTByDa9LkbqlWNPjG3e3yVkH8/22jQ7rrN4TyarZcQVznnCl01ulHs
WX1PbSGY2G1jZUxO830eu/loik9O4Gyn0mdtqttdFIlLhJdeJHSHbKnT7goTjmiD0i7camOsUUFB
7Ct/X/0BiK17Fk2MYQIl4Un0x7STubcBazt3G5zcD5A0H3ouF7y8pzavGHBC7xgYUC8S9NHZ7w/d
VBL7OaqB0hIFigZDmxmYRD79JLNv/sWv7K6PnoAwUJJUx5GEHJLTjwXaJpMrxQCyjaXxkap+LlN6
Hd6EiDY2XLHpSw2BkJXH2upndN2glnkgS+BfJ5ID1ZPDSWsQj0/LTanVjK+BS5Y9Lz6+yExOqwru
e4iJCegSTmyMfUkD+dkWdA2eFQRN1N+3BSXfPAFDDpfSKttKjby3h593f4FGlwmsvp7MBj1f+zpG
R0msXGNu6MSUIvIPxw+cdDREa4jnV4jOsEI1EP5lZROOQzuvcBeMffMZpB7qdlJnh6aI9ue/KkbY
lHxQZU2q8iEIKTmQozRma5w4bvrV6EGHLWhXktTAyLjLJAtMEmbCQQAERsD646jHZJL4rn+/q9xX
syeM9xpeW9xqrdRm2qqw4yx5cqIqwgAd8bvdvfQ5/KHb53wTtgA2GekSFZFOfIr0ocuLCukNXxO4
v3UzK8IP+nrkPJ9Ztmy6nA+lTATL4q3hTvBxbzqxUSFJ6kFJBpVJcynQcWpGI+yXnRT9oVb1t7va
uQPBe5OkqDw+llBBAX/A+MV0lEHcyLd1F64pTz4vhpV878s3az7thF5JpMSU1ZabpdKuupR3+ReD
9G1Ut2W1YN1DdPvEGkYixCCmDD13VdnsJieK9v2VZG06G3DkFSF9/c7uBMF27zDU2RArGV2UPTyd
7ODA7kf0T2ZyawhXQe+OJS80AP6CvzzQT9wGfbQOtFZpBVTL22f3VpAj9uaIjoXulV8GdInj1sTB
nniZregal04Fm1MNs8vC5Qt3V5H4baoiBfMwPhXHT/wVD1saCyFe8TTUcZ4XTYC2ssPQe/gEZ5Ux
6G0No2a71sRDTiWL9JSoVe+Ei9rff4Uj9IQMS5dOkK94pQYME9CUZ8A8o4OH/K3DlwjLj0CW6dDq
j0M8PKBq8NB4QmgvGrDhAxrX+hv9I9SMcDT0tPPdgNrHtu7Ry15/OZv8s8rgA7+zbBT7lTpm/dMD
Sj2OEOiHEI//n/TkqAXsYC+XE1D+0U6azsM9h1wLBaKoDK6covlGPi6TJAytOUBn5lwimHALQGMR
06rTAc17fimGzdoCe+Z4doVehUY7uBFzI+apH0PrbVp/F+LGO4YSbxeKNFFmbKNJ7tiKiu15FsQR
u2hfjPatjJwalG3sLC02QUFVDTebodf20dWS4n0OU8xem8h6l2Sb27Dtk3irHUYKlus+mI/2n6jM
scGlwiw5RXtre2+2I+0LaHpDT1eSTiO/7hB68R6fIcDjChcUNJsqVkDarYM1FqvwH86ab4s7kRxu
QVubM7v7d9e6z00Av2oc99zj9sBE4fe9n6xZkF6nvklePbPRybJW9A+Q94rTz3Rf7X7lzI7tu+Xh
7HkVMP9KfOIkEQvNbJNNaf31Zt2aqrUVRsqDTq7X56U3MHhS8EJpVUBYF7KvlLS7EbJ1Qe/5X3nx
zZkS1lf+q0p0tTrZn++qGJYaL4U9fS2ejPYm8D7Ld7sORFQxIlBvaCdX2EU+fEvCulMXp5f6/ctX
7HcAntjy+rzaSPkVRDncRfKJ4f3hLD31XLR51tUoC0c05oEhn7AXfoM8GUdPnX3CD0Enqg3k17Tp
iyRXdMXdp3R7nWybhQ2L9a9uXZJVSZ6YTfD1xNsli6GXbi0mE92LCDmbAm5JDd+AxBVxXwxVPXQE
MFv/Vh/5zE3Iwj57q+1WPaVADI9eyHWUBmr7qTJe3p8Wdeof8Kkp+1ZMNdmyHlEPHJXYl8du+rPh
cArIJz4Rw8QBB8gsdGuJ7UpdTv8Sv/sZ9LTcp1oFdP40Jp0epTw2tfSPuvSxkHTSWfZIvuHVo0Gc
76m+JdVpwaJpCDNXIOFM2jJkhFbszqqUNe2r+ABjCHUCblgHt2jjt1BwrVz6jf9tbPMECKbMMujU
7HxrCNM+0IPmErYwS4m9C44mBR4sTcE+7g4u1eyeA7U4qoGcK5wNpYBj4iKWBTL9zFFekYI6jEnm
iuRjGGrwLyVnQvLmiDkLxMwV0WI5TOzfxjtZs/IX64cLRjsRnwcUbGFdeGX5FFmfLGrkRXAzuV2p
5UFVkgsLtoMKyWTG3DbfaIshBhAN2Iri1H1ZXFuIICSHYHBXF1ejPRDJL5B8IxCWoSMAGPwkXr+w
xUz8pf3B8K1b+TqsBVECsgcoVKXyQ8YCXZVYxDJt7sqsyBQF1rONq7/Ociz3n+ZKO8qHGzveelFb
mPIwaLZkR0W/AXeBpccH55pTgyopZ88st+lwo70Ys9FztfnfEFU9puRTrxchdwyfFdhCQL14lC1a
1r1UfyNFIWsTpN3juoGdIl6uufKc1fbofiCvSiOjxGS6HUBHzTFfwxnxUFQd8T/V6x4BXDSbyHQK
/VOSIicW3OjK9lOT40IhYmQ34J2OM4otrBbBUSgNZcqnknBK3GQPLEakg2QPufkrSVzopy4bQQ9x
4UzxE+MlT2WnHiX8niAMyQMR3L54QB3ktV8ubg416uIEPPFApyMTYIWGxyQXg5z4T9FTq/SfXxBF
1wETlgVgKC7AgiXQR/teD7QO5uxSGtqgxsoEORClkqzDxfm/Q7tICtAOjArZaMJf6BzJvzH3ZSGE
wRufp4BIpNIMb26BXo91Q2Qqzr7dZt7GfrUYl27KoszrXI2t1i4WDf3C/anVL2XWA/aPno+tqRME
RXwd5Y5vWqtKoCB5I2HGduO3SSk4VtFV6PCn7Cf3ugvkSslkaFpqqG6PGjCVDbM/TgRBr6Vzw/0D
SLYvm8vx/HZnKlVX4KmQXCjdEQJcL5YnNI8j7R+LPk6sX7S2tSAh1asV1msnaNxa/UyR2AHtG/AV
CHGPuyW9KRCEUCTV9P43GUjjAnP0Yc/Hz4DlxAoio+GG1b/a+usji14GbfPPmZFeIy7LHftAcNaS
7B6gqtl0tt6ZtbjHC5xTLR7hOeLvVA9UjOYlGCLTywTRAfEYYjLVqFcKigB//cHptneRr8o2yHFh
GAlV+LSI7/0QQcdfdlYKDhm2cQaU27IHFH/75Y000TqKUUgJMW+UYSZY0iyQHjg8nG4FuKt/bLSw
DCifFi55x8U3MWuIpWNYlUBJkZd76nT9IeVGTbnd9CHDoemkUlSrBEedzQGl3ELHY5P5Z5/6igHJ
W2mhikg4blRw60aZ4zdn0R/Mwe1mJeAMZvMDwHjevXF4BqSzCcJppBjAbfc9sO6JgDnRQejsuXqo
Fbr2D+dAR/ApvzfGkP6hSPnaYciVp69igTawcdsI1gjUeuzBya0q7Axdk94Rkw3YC84JsMSdkDQg
xCYh2TlxF7EgLlvHVRJlLXyGOoH0VKfknU1Qk5KpkQpmH6fbe+TP70yvZJoYCW+sCjFgLmV+KGcp
6l6gyZuByuNAvJOyQMOx78kwtgPeWF/oCmZ/2WQzlwK6VgA9K+L3yCAJoZIN65OKv/qOw1ezWT4g
/9BEJE01tqwA4ddWtMvh5qgjFwFzUt7Tqpf/ElAuraDOuC7XKjVQQX3OOJlzqvpjA8rg9YGKekyX
G+DtoAes6xEnih9TRRzsebQy+Ia/FKOlYKRee58bB6H+I/vd/JIPn+y/+NYbh2NXGJi/LmD5I+Lq
VS2bTcfDEEjR6oq8maiBDaCzHG/oKpn/wirLu8+Ffoj9wa3+QizDEhcS06gvu7HQXWqBGnoph4zH
7Z504NeU8Wb/BSaq1PTfjHI9ThUF6pVxDvZU5eqLxtc5lmX5YKtE2MGt7ZdEyENHlYvVngVyguB5
ErXlT0G8erg1+S5qiKpUzxeKWZJgOj0k5JYjjf4dTHIYOI79MXYlldDYhUK6RXsoKwQo8qbzvwqf
Os60CJv05ciq3w0b60Nvacm/Xkl0xubV/f6eolZkznqMKX1LqENo8t3DrflwcIjON0m+LwTu3pmX
aLEaszvFdiKOZKfUX0tQkbqmpzJMpqUYwMLN6OzQtkmuBYn3A6tKTOpLEwcUbhct6yAiDe5qvH80
bQprHLc7ZnRgm6hJpEc68MomS3jUx6cSsCCl6HKxtkoNdBnBsiHM5g5oJNBD4Q8Nx3I6jHsrq3KG
2AcOwcCIBOXYvkGDqBqXYYdYjZbcQTXxQtoGZHPqKJzhP69Hby1gZtO3k226aZ2j3nzazk9vTD4j
Q0PWGCTW25c5gi5kjCmshbLW9nvldcMXowQPV4g8efBpNZEmSzW91OlNj89xpdDARQCuIi9og/gD
BOSKBp1tOMFqeIka5Tp/1PuymAQsoFoXQsOzyCuSTYsJDxFr/EGUTYAdgZeMbCc/KILTFzVRRnVq
cus8rgVlk15YqTNAmBWxqhCMWmLef1ou2TIYOuozTrrioRw6tXDZ22kLMBlz/XS8BSh/UzJXL1mE
sTF8TVJR0ND6pW4PkZc7BJvSJdiXNw35RIsIySvMVLp/KscGEcUdwgi52OGVN081Z8G0WEhFX028
eule3bXNLYF9ekjArJTe53k9aEN6jlgxxjUmC/xowhYT7JAcKm2cFhJN0HtxqAfuLdKj3xgJEJCj
HLI+1aggmBCZu7f4Ivyr86Qnkowz3m1StAHkhLzQ2Mw0m4M01hnjwpt/B9qTCoD8vZRHoxaKHi6x
NuvlMOpVsdtPZyYmx6gNkwU8eeVnw+fcXDT2fsolrV6vIZYbVhdDg8N1KtQoKW6+ZoXepmaGbC6Y
mZfXUP8mCMkA61EYiNX2BBN69+pIv1G7oGQdNwwJPpv7BjvzPnD1rqsN6C2Vi9boJduEI/fL7zM/
GB9RhgkBmus91fJR49dCyeodPQg1sxKL84OvRIn8iLOaAMwJlv37uvT9iEs/f+ORimX5Iu8qKYIB
rtSkPNh4d2tiWywExwJjk3r6s0KabSD+J9ddhwBh7wClIuwEBUP+zqtOay8ibKHWrjRa8iQBq81H
ty3ydFFWPsLf5yfTdm1JL3EjDfpyNF7uFrN1LWgyDsQC8dLLRM79IcygZXoCRbkEVyedfNs9+EGe
upSKEcdqPtJYpD2zQxPFKWQ8bS11aWNx6gsPmfIFwHDPUCvBb/V9571p4zO2jbABfQwMtlWsBptX
eSMDnFCbpqtGGvChDQ31IsM8BaTWBZv6ytMux/0w4UXoQkkkULPmzvE/k5Kvhw8xjJ+RE5NzSPGO
f2936HZ9PXMNKEdCh/CRhdUR/8Tgfj/M52AS7OpeDP+5dS5mlQSBNP6+8jV1nACBgo9CR8C7l0F3
vQHO8cYcHgHw3IQY0jF1SJ+Nffn456fJdFcSw0wbwPTuFxZAEGcczuLXyPmbTaaKF2LyOPa84Mtv
s2jlhGr4jkew8UcVeXNPLcMfFjVQh6fk9C3mw7eew7FcDDp/L1FSqzgtQw1d4CjK0n6rtYj8XH3f
4J+XUDtwMTILZnMscTVcpzeuctXsE/G6lqKSwzS8WJF/BalcGdBw0x8foFQTs5tG72MljVFhl+ut
ufCi2qkompJTTM0GeozQWXAiKap739KJsJiCK2eQZsryblk0s7U7hzMx7nKyZBiUc1q+hETc2b0q
AtP+KlYj/ZyM9JEtR8mAg14xcm9NXsStcNacMBi06wBVNYbx8oPovmYUzXpSTweuR4ZHjKHWwCo6
lDe+YIFZ7EcV+IL0mBK53YlkdMXjI12l+kwiboMKVqkyrcYufj6Tajh9/aavEQBzRa6lMdX5FBOQ
rMjTx5DFQ/pUKYjGrr/6zJySIn9VfwqrTy2IfrMfDcHFYd4oYd4e1zKVVK48EjhQbNp2qes5SGsj
HRqiO3pxbGe8BQ/UBoHO8RKfBXrF4qaifbBmpTFYv+k874C2Y9B2hgQ7pVwvW/7xsYX/W7QtMHR7
JmO7Vs6NUv69rl9ZS2EQjlDD8+G7n2UjAiMLZPYnVfA7xzllCtQfIUI7frktBoZcOxp8iNZuiAVl
+ZXIhyjwJncb9wvzEdUIQzGJ9k1gXtC4pFVWp7dnC8YZlwrksXfCr8HTmGSxATfBjbX8KQ/hiHOS
vNlko0rgG4PK8MyjLcQe/fUQw+sVYQ0vwur+d1Llvw5LMgHbtqal0cmFL/Rh1VPjOI8j70TCi1FQ
TC0/qz2H8+ap6SPnAmsyQo+XllaR+2dOexKV7RjpIbRcC3Gr0W+JE4xJnW10i8rnnzCQdApdRj4j
S5cwrzZsLgI5ZIdIS02uxIOMNlihm8I5Bf/+g35O5O1ApAYk1oK/pUfAr0pFjlnsIVhC95XnS75T
i3JL0ggkOxJqjswj0aO6n+zUcwwwLg9NCiu6N6Wyl/FbX3toXNeB8w2PNKfYxR40sTWyxC1rjQ9z
G8tfJsbuVUXuzsq09IqsmhAIp7dKJWxzxbS+6aTnsd/3ZqHg4j4Ssy7zwBqCWaxgq7sV2dpmARP/
CFStnDGmBbbj56rXHIklthWUHL/voWPuXSeswcr4KrhanO9tN6alOq7f9CMj5/afGOI5gwmyOqMi
4O1Dn8Ead/cwHGaa6R31Kv/pzpWo4JldncQTouKHyDwTlb9iYlsJH5dHVpSJNQLUyya6lfJ7ZbmI
IEdzFfkX2kv/pQTpajnaReyVyJspi4NZebXwKOEvH2pQLhlZWFwGedC9z1Ta0F6VnfjbvRGEchdm
rDca/e+iYghHcD3Aw0IhP5h27PR4i5/wxkKplUYk8USS9/rnET0uOZ1Yo9xUiPWsce5SrDEEgi1f
B8jxna/06DBcBFUWwKkLiiE595XK+fPjrk8cYaVkNpnBuLdfO1Uw2Gh1EZWfgyckD+7u9WLLXwf0
GVqalDOZ+bLsIkvcWXDVo1Z+y2k99Nt58K/M3Qelpwu3ENdzssmMskPMX4/XvLRcv4Ko9XtiGw6o
lTtnNduosIUIeVTbkjBVhTmjRI1D+88HAshz4m+HDoZc3ti10re81yb72xKRxBBUxk/wC7SCxXiW
4/gmE+qmT8YOd3fAY7KYFnQ627eWaT3Gfx/V5b9mZrWviki/DOnQ4iONIQ2WJeW9kohpXUwwmIny
pXu6W1m5TlmLQEnpZM5xP/sSLsbUdvLKP1LWAMZhoNfHcY1IgnR83h17rG13p5IGCJlLYLCjdNE3
xELkObi3+wu8wfagB7FZrjXAdcJwSavoQwEEmusmo7DIPg2+ExciAzlmjky0QROg+V5t3/xpv5Jz
S55tb8+yi/kqen8hOGP4Yck0u1qsd13WAzIqmLgzJ0c4ibtWaxDhezruZ8/A7WQvs+8AdsJZRmrM
0QPKeB+m2Gf/hGMgE9ozvJx/4VPNqNvD8vmPJPP54xIpIPMqu95J0BLs4CtzLc2fCN8SgpR7+8YX
K83q7bTM2uabMfE7zuvhxnKaqOMPeJxA6iqJjqFIZJbeWGMOtf6q7YmO3laL8mBYW2mK94dENfml
BwtE09fSosXYZZn5NmrNpoP49Wg/kYVUV7UI4AK3ERY8+w98sMFnGE/v+nTuhnlXTCooHA7tjBSE
yakCQnt1PbiartielWQ8kyUEd9YN5+6xhgVg1Xldek3rmpCptYRW/743FSIuSPajCMtAC3ZYPw3d
tzaA81SyGSPg7YgQjOwKs1svth5Xdt1OOUoCpukuhdsLu+gY69Qg16rSkCHoiTQHTjSbEDrjt4Ae
panbTduU5Ey2qIdj3HXDbDHhf+GN8olsjHkSJ0nF8HqoIgGtiOtwg1dW+Js1K9Aojk8z1zSmFCuW
5/aGKjyRIgPgT2U7j3+IejtaXX3+uYEGxNgymYKlbX7J9oLLuc51U05o7zQ7WaAXlhji64sKST/v
QgWeHWKpRaBW+JC5D+KKoY9GPcPu+6Ki+ZOZrOLrjdjhhp5Eg6C1muae6qSVg7hqHDePWbaYox4O
k0yegbaMrtIbp9yZRz1xHQzbFLN5xea2h2XtLCQV2B9hHNqlW09lgLGBGB5s+n/Pay+nPOCUG6pn
Nr58t7XEfhQB6LvKvcq3mcWHZABrrIyR8l/FZeHAZIfg5w9LAjqyWHgATY5Nr77ye+jVxAyyzJWu
0CRSPrwlas4L4SWo6kdBgtGVt/2hxg0icfCtSZqHLVd45l7ypBYzzeHyAZ4wQFkr/JuOTY6+Ae3f
JJ1KSr7/X9DnlzF9wFO+0g6+1Sf4PfmZZIb9SNNuTH0flRm1e8U6GGmpyAV67Li5W6LHlq4dXDcZ
f0Yp1KjIvKQACwVKR2hpbBpQPgJ9lNqefIFnl3RApSlPV+v7HjHNFfGTLogqT9xh+hUcUUfAWuti
gOLPIYdMnIDUUDmkVPqGCU/YnHQuZg7FQH2RPiTBkn3CT4APc664r4SKhIbVbHUX9sv02uiw/+w/
f6zu4Y3h43FKsb7q8ipHmW22lgNEhwIzPokewY678ZGHPvaMvti3sjXh6s45w0VGovsq2lMt3sxt
WgpAQW2mgbyf+Yj+XFP8df99gSg48RsYObVciMdlYvJTU1axWgPjPgCbb3XVhqweJ5PsIb3CR+En
rmLjwBIT+jY2mS40mvjGbImc8ZicLGRbv/iPyrBvlOM8yOCzBuIYipl78O+5rGvK39HahE4YwSEi
O4Vg8jTfotWrUH5PKlaYI02mIVgrKycKejkMclFCEWE3UAupgmB578tgCcrqSlthCv0sG/ANUPbg
wlPZ6uSR9LEXCBaO8YZUUbuKlqG/fgNMS1BMjHbpVjtZNeGtp5pkZMN+VP14jSpE0TcXGFg+jNDw
5lLZxMRF9+ULsQA6BVGWseimsL4j+J7fxtwufae0QYaZaPHOVuyMFfmPb98D4LkRCXjLjXb46a4h
RUAK4aECHLWIBN1AaLDGocglmy1sA+DCVI7kXRq8GSE3aqlKwDq8yibLpokj/3H5UC6slPThDfEE
5jqmjbP2soRh7fRIY/XeRNZo9f/6o+Ut8UOJaHyM11jRgEb8i/gkKggbjFF32KszzCT/Biwe0kLz
55kpskC/ajtkLjbCtJCEGNMZWddHg6t8u5VnhYGEjF/1vL+15aK0i5VDMrPwtb4lBoOZkw6qEYiZ
zE5X02RxU+kGSApUMMwiOoX8BuNT64urWOOpBDgAngXNQmhbqy5K/vQ33YnojWL1xdpd85jK8WW7
V1EaPw1xTIxBrXNN5vweVNZ1c3nDDfiO5kXedVCWIAa/bfbqlVgg1j02oIpyMlyYEqjQzJp99dKS
NSSY3XEi34HRM82tpgAXu/Nhm4MzQuXhzf7agPW2Eg4AXK3uuTL4m5hFwl8XOX23euWBZoH+eYGP
862wy3llSNA6ISRPq+krp1rMY+DPuLXCu8XjyffcuPFEVTF8f8iEHnyTY0KUsnrALmtXhgpBxqRN
4rb4uzprvmmrJjf0SlbXoqJfDYB5JFteRNr+I+i3gmChcgVkkqT0076P4VCfFU0ZmuAzZEZD6z6r
ilTvBuqWQCjhETJdLVeIVSG/CxYSj/gZVcV+R/KxhdAYuyKnr5nIZEzv0DgHbfLWvx0Hy3Poml30
+dQd6J7Or7bKCjEcvQajbMJVO+iEAr3/qUIcTneYrdqBlKguORjW1TqCQ+H8LnHCcxAcIfIuOlf4
cjdCWId6XmxP/XHWylezhN5KBsbQM+DOsacgr6qXCUdDhWNkZdU0LoinxM1N+oOOyF39RafhczXx
Z42LRSaawTX9e2cAYPJKhXJyB6gZMCA9aC8A1jUy0qBIqG+2Fzb90oluziINXvXtkOLSUi6w0GrO
ceM3+qJRx1c6eRS6KEgky3epcnQle+0sElCRZNJs6xoeKOd57xbTRRgDnP5xMBkqKFpTTJitf/5H
B7IJCuYQW7YXrTy4i0UUA+8rlOyRG0zuBCZ90mnH2gb5vfvMHlLNTSSPnaXSta+13Uf1XlZEjGxp
Varq8XCx0N06rst9boHwrlgIlwTOcDosnw8W3aIzL05VocnaUGCfD7srX5dSrQrahIOSmnKRgNA+
vYVTmhVyH+ZNurKAuJta8ShQfRoTHSokIP3ZxlW3vMP82Ctsbj/FD1AznhrOL3ym5kSLsayIQTiM
QShpDB0zSsT5biMcYM3ePx9v+izWnsV2WXOnZMsW1Hc6ohN5xvY3t34tjuxLzusSuI0dKaQOMOXC
vg2q7WRDKu+ClP2B5wS5eAAipKJg3RoFUkRmCw7ImZT64WODXOYgPbAhwlNYFQFpAEwFastYaDLR
ohp6aPNAenBJmbBCJrd5RQ4+xwbMclrs+5egu/ph2HAT4TsS/ISjAGZaMxQqfCI/HI4wA61/0wNO
Hc10kv29+i7g1EC57dcSxKeMiGRYbOHGNJxkBaM0MHnQOhUJUu+Cf65LbOLwGnsrmCAHzU2jl9q1
q/VXvSVIxDcwS/QSfk0513lH2nqEN3Kc2OZTMf+ZWLmAdigT9XciHp1XnyQBlgTxD/7PKXoDdmOV
JpNFVMlWrYrJXxpHV47hikRjcTdDW5sPZ6o85bJBGjY7YALCkBb1CL/kfWjDLoQwQ1D9xwtyXFk/
Y3eK14iH4PDPdDnw5XPbhJJiE0MA07PWz5754I2kkCLkbT1sQtk6dJTS5aoFprTz2WNxRCySIMQa
I000DzX7y85cCkGJmimbTpcGTFrfDZ+odpS09CDm1VM4DrkSRZa47OFNiC2QxaS3oOraqm4QiNGQ
u6lLNozEtEmv0+pZM2jc3gQE8uxUs5IqrXmzntRG9fXqoWuZF33pOcEGbrmad/7D+n6xD21ftCND
ATX9jR90iQTZJNXarC6WbUimDvgy7EU3b9hp/COrDLHkMGUOSYrtj2yj0O9XUNA3+gSc28Gy1eLv
jh/trmijw+FyCruEmzxgMwdRlokd1d97Ku+NgI98PaOPOpQIMYMN6PWlrfKPXgqMl1geERE33q28
BawKxANknD2DWJsdQv6PNCEzI+N4kWFreHM6ozorJ4gdVP1SxVEcRCgWj7ycHP9z0YBiJlwXdf+S
q6RgYgvlX0mnnRdaCSY96DAJkODbbDhVqZv77zmr17tw70AWOsglzyA9c/mZi9Q+SDQL2dGB376y
q5XbZWW5KHu477QSIXF6zngpRB+QToFoMKj8YhmjeP13/q0bW+rZZyB2RRUYICIU/ypAqqdQM5H5
8n8Ete89OkfjSeHMQrxe0/u0RZz1lVH3vkAjn0bRvufsmTtBFEdguEOW8OnuAF9Hf356sOSZYvNO
cI5wM+v9uFZxpwYUUm+1e2eX73Ec0QthBhovVgCuNIAHKFWEWRBjW6fJeth/lw7HzvfMQpIILvY3
0Ni6QOVNxMuMH2JuOU8vinzy4Fan+IgVov0S1YSXt6KvxPL+vyQXjem3Al+jbHmPM0VmJ6NqanRd
ZLPDnq3P39cLtvi6NbBlw8EXKzDFICaBOaIWNzDx0YBdB9lJr+mgtwposE79fklEPPY5bgLE4FuE
2gGqHyYHGrH6ctuAzhq/55fl2RLJbPHLFihlE2Gytlljf9j+g7ZOWDn0SYl1OaCNr4Ku2ZFTtjR+
aubWak4WFv0TwlvX+cse1uEZQcySYUyIZEvXcZlpL0vSiDzU+VbPeGyrhvv6TTvBdvGfq/9eUtQP
MMEBztEXVEr6dm85Q6im/VA0aDwneeodinnb4IO9AuAzpD73X/lfRPDvOcqAFo1zfU+qKbiyrNIY
6vX7JiPm1NfZ8VssTNe+2meDA6ciM0z94z8/9/b5GwzrLf1F6HE3HMZIFnJ5Fv8/zMmPl6EV6LPD
Zkk3VzxHiReHN4vTDu+KKNqn7n76Fu9TaMJKZTmX7CV5zxMmdqYTmsWAKkLGZGbW2wiGu0uBx53J
vLKGy+yNNFHFR8/uf1ZY/RoehFursHwtv3EylXetfNojJeRmIOz3uO1N0Xj1KcfAUE7qZq+gMkKv
2fzYiGair8lo0Ka1h8QETqdf32On1JwvW+0wWGuC0cpcIq66y2hEx/byjoI+6uqwx+egg7R5FTH+
fSAopL9tAbwg6j5GwEYuRpZ+OQgxe3CQC025Hh+g8rLCpfcX8yPk8VucsPcDL1U/sPueHYPTTnLM
zxGBQ0s7EfGU4qHPfQWX1qZAU2uJjt8/DL1UgOjq6MJr5HeUnEYZ2UmIS+lxHD/RspZWORntqObC
YQgeAdd0QOUgAJudrWbvmYuA32LSpWX3ZM94Cj3UJmrKafXk906JmKE9K8TVAymj/PgCVz11wKKN
pRRylYB7nTzioWh3IE2yibXZzmLJLr2HwSxa0+xnKSdK+A/rlZHW+yESrQ8zKD5bUuaYlcYukAHy
ONY0DpK9nPb98I0DoP9dExD97we9AHuaey5R57Eyq/k1Q1sGT6h+utsQxjNk2wnbq59nsn3EGvhl
qBgvFHsKyfYWcF0H9jLXM+JKW2A56aqwPYAUoD+xsF47lMFj5FPZ0kAH+fWn1A0Opf5ssaIn1Qo/
bs0ML93p53UdXKAtWqZ974qg4SKSByoUuhTi8tFaQSYhwAJk13gPthsoPj7o+Pry9idW0wT5Tc4m
OVnQnL8Ivo4rDDfJQrLdRrtUZhhkW94LeLeH+E6MOaqQaLvgY0+urcuiVbUfNOVKLDEtDrJz6sl/
XLhbdierncG/HthFZapxQ8SbelLYUD/s16oOHkRWt0HANeLe8x6OKlmnmQpbyT7Mom8fbgA/Covx
VAPwvREYKdp9cuuAFoVImcipyEENay7Q86/miJJFe0JBGEf1ruXXh/Wsv53TrQbw6G+pKyXSo67I
3qWb7lJDq0DaxSF6EFhWru6cmwJ0t5y68TsiHfEmuMwUOm1yANSmWXjVQ5YMjc5G2wk4yOlwyVKI
uRra2/zyRLwFS+UbDMeT9yfusKG9+6HjgUhMdQ6ciybYKo9g1CUsysMjl+17XJIIC5d2sZiYfh20
Mu23sBR+YYA8TJzdmpEazSz4OAeXqBPq0Gv3jtxK7d85yA2mVjw4H+ei/hqIiBv64svN14r0g6uy
t1pS+HK3IeRQHkN9/vWTJLFTC6zSXv3fVuex8HSu5+4lm32EDBEgCh3nu5BoqgOFPA3+PypyVKyq
YVItBHW50vJ1JoVMZRFIcpfaEw3fpJ7kUieeR/aIt8cAoKqG7ocqbXJgXbc1yD5TiK6h1AmrezrY
G2iLq15Fr0vDxFns2DISZFXfR20jha4EzEajHwjd2rvl6Ngicf2jp0Co3pXDZqY52SGiDelpDGYn
QIYviJy3MSNndsOOMEBed05nEc+z74ibE0xc8Zcd19CK3Lv/MqoNZR3z9bRuP7oDxee+BUcsQCHV
yeAUJ/bfhIGfogH+ORPJEuhrmqsxVkbNfcOSJ74HvgnOq0qZkuuX3287XuCCyfgTXGqrFIMZkJjA
985HhqGkwdpebafsWrT+URhxxWPCI7itjqTiMMLdVgwXl4zOE/SdBthQEuCm6b4MxFisxh6K1RnK
9y0cVsHnDFVDc3we/Ca1gDFLs478WegntMhKIuY3siYA8Wob1kKIVtTwUkOCb3u/dB+FkDNvkDpQ
H9AOp3dFQD7MtS4mr4G54ZhtBMDwb+Iu/ETTkGRkz5cU4IoKXntHnBZfTyrCgjqu7C6L6L7CFd0B
C6YT4sYDT3IEvXy5oFpNlp0xx3+F5a0dNFlKMP/fo7vlIHGY59hB7w31nJqdI2B0kO65taGVa101
iU4rjo5oW8vwcQX90kTZBZUKYUrDVpbR9hFk9FGlTfhmX36GHNXP6B8I5h2bneqNhRWkAXehhLZG
b1b+UlO2hlHuySNzb93cC6adRx26hpGZiIlFk/fivu7YOYFOBBjGYjtx16tB+BYWXiLPAmNHaSX6
uC5/FQCWkKAgfBCXJgpm7OdeHLVaNGoYuWoU8uGUkz3jp/sdl2WRuAD2qDA2FPsGgqcvLWuD7IoB
Fgx3g3jAiPM6HhRUlpua38VJaJvICpCZIfRoKvefUtiVFLTqyRLLLczX7QtOs67G7c89Kw1kzAGe
Np6BAvPCDiwLi1Z8NzXga3fxSRt4/cE7C2VNMmS27MFPx7RYKzh2eHGJJ1VdacoO8EQeuMLF5ZZF
ba6xW/praVVJOKMvwf2ArNIgj93o24zG11MqZfHNCXgBhdgE4J86uWhpVZN96KggkK+LKt4ijSOP
JoyuJgQ8d+AYVNEUYrqmLukZ8k6rrfC2Rh1y9Dg5Gj9uUuXMeG1rgvGujUDWnfssCyr+BCaWvykr
QYFltBqvNzVcWG/QbkyxYPE0Q1fJP/ccM7YpfFvCeTok52aqqPsPU3gss6bJRR1Rtcpmtb6shS/6
ix2YBZd54EcDDfYqG3+PqMvi3sgqQSqDKDTH6eXuc2aKKhHXcN/IrJlL/Kgu71d14/ob7t6VVTy7
1GQ6de3axG0ZkcvGTHTHPQEgTL2MC+RVflaxyMciJElKITO+hpf1qkVdH55uaSBhFvNLqG4PUfLu
iYGRbde1Uyd+rjFL5j7ZRaLIlfrCuPjYWtJ9Dk5JiyOVtAmMfPmlxflDFMX+HUMM0a4iz4OMR+Th
Vc/b7Jf7aFyqh0X03u9lTH1HbQlqEkYs5hRiOo+zf/qMe2hlKbhZ4/I0rvEYv8bI3bvKW/tDwFP7
NY0JW+NY1FSvwd0CNmAY0ixnMu6hhlP9Z1eZy9q88OumoADYYAZj+GlcRMHrnEU0Af2ZObuEOxYb
yr2EUqa+mA+kuCmm5vDU/FyhcUPJsqUNNkASUdGWAXoSmzSfmqFU47FkH8xgt0wNX4gDSxNb/m3m
9oBVrrEQ+ZuyRhKIwP/V6eDYOb1sytQH2L6Hxc1MHF4LI+CLZulWMIKe/NHCUn0eSQSUN/GUWImF
5E1ipwOiccrNclaIkBDUkOfwbVbq5Q3MNDYUCYCP96tZ8iYmtptMOIOv8b1lTUhy8wqcHKME4SHZ
g+1MZkZrErlPlkA6wfjmH0M9aEVO+fOTcO88ElSXBSyhEkaCeMZ3+zyo9pHX7ZYddRYFboyYh2P7
IKirL3Dt3OjhtbLAFBxzrud9B6Ys7xRuehbMqqlnnGXDVno2bKQzzuMwH/HSw4ifNEk1B5PA8uJD
kGW5HeUT3IIYjBbjEM1VFdUEzFuB89SDhUSrH1yBFlXJNj58OpNcjYn37x2yQXNKqMwE7CuJI7jX
BMKHpmXQ+vdro8Mkv/6PhaAvS1j9mHduoEzKDWr5wxfEUVekZKjVbqQ4s57ji1nEDrLHtlrrggQl
IkR77U4n0XNUIBTygDoGahinZtvB+G8Cbd53RBxgx4b98LWpGYuiyRC0ZimZ/oFRuxMP8Vaw8AIF
2tVjqV6Y8AsL/fe6niR1NJkEVZ13cQEMlb+A8MZ6Y+KejEjr8v4AdIAT+d69Em5GXmZIej5mmrDv
rtBAeexaYK/FcMYNkqudjks6cfYBdOVhDX/cyJAB2omP6Hx0PnXAvpAX9bwSYI1JLBtVjTWQAksa
SYJdNwIq37bAUCLXN9qZ8w8seyv9L+zPxBwzCDSVmZp42IcXmH3UKKMOpu3PTAerEgO5ToWIpcnU
ft4Q67uzu6fMStW1gw89OD4VQ8RDHqz/b6bTR1zfnOn++MC1LQOEiFz3PkgCiLi6sSrnHCnXa43W
kIuy1hEiYMX0edzPmxy+kPOUS2TbBlrpAl9HBuwgm4asx27g5mH/8BqVfa3dbxK52jYZsQv1ZRKo
GgWhvkh/wrdUl+R9xFwVskQV//OwsUTQF1Ovuwpyvw/N7nP25R3QYdiW1B8l9Tie06/XyAbknRyg
7qcIMdVRrhFJ+5tPq8Q8zARk92ghizPHnoekvKAJzJO9hDg05SxILE2QAHWfJ7csbDVRHoryZtZf
/Vg2amNvI9kODhh5g8T7GZ9oAJJRqz2/4HaxEwjPKZE3QbZFgBYEpHU9rPUhckdRzTyZu7pJCFCw
WaM+bIsz4YarTA+c8nhRxtOf+Wo1Vi0tZOZyX0GMvpvfPIJIBXL6Ul81BfgvV8durYyIrthvLYGz
SL1Pk2CfN5p1hvpspKgKnkyBePAgOV+myxTH1/049qUWVHx2Prp50nIEND82mxRKX5nE05Y7Ze4+
W5UaOhAzUtmOaCsVqVZDtNEAy7BPxMA1FG8sorig8lJKviqEJ6HjjVcWmi3wxSIG5plMfks29vty
N8pt+ZURK1dB4I9aYqDmlX8DT4jWe0mwIsUBkAo5R/UNNCF+4wnNLwV8KTFPBeJdg+TLDLL4MSD2
rI0/ewkNaPTakq3SJOG0sOx4q/ozS+Zd3oHkYQLNRWleyVwLZ59ybax0JJDJA6PA3EHZcYeGNGw1
q7gja09nWUtwwYpOk9xL4aiWHeYNU9rtQMmAYbjjCKWjJ8Ac6zO4gf/hUIDGfjDOsViKiC62M622
m0KrlZ+VpjmvRg5O16LaE7JmxqF7FnHjVxCX5FPPndkaBgRlgoCBXPysUL/DWW4pz0VohLoRZHB5
9zdkFig2Na2WLVGd1GvIUPB4aOpGulXXLk1ymhjF94i4ftJ0TEyLioQyzFTG+Kldsen11vNvehF5
V45AhPNmBF4kX9uTmGuVqSOFI1l8Yx2ZM42f4cd9bRsxgvrBBOEFywthKZ52QswCTonTlAQr1kxn
EtNvh2/08aqdqx1vVYCj+lDNIj92Jeu3e6+7kvSPZ8yU+C3/HtElfEOCIsh86wkv2Q9s7QbXFDtU
sXHvUJt9oFxtAQ4Sag+I4ZtHHtyWLRSqmKwFU+RomAVGyLYxhwUkh8hP4Busku0t46P2Y10EFpFJ
s3KsBeaiIt/sO5HFtXJgte5aPNQ30hsb/aqj7J7RlhCRcVKWRRxFUuqxBtZ1JTP975Y0CdPDPoKk
8Q1a9tjz2hAc+qD+zb6qeAz0H7PUxoJ5W7e66WIvnqGmRnyJ+dizwmel//PnHjB7W2H6JX0eZnQf
cirwOEw3j8Bo+NzSA0RmykMCNM2nvI3pg0uXuBEEfpNW2j41ZQTJDKO8ZHIY9z9yieznDgedCvc6
4izARtBBkUoGcsyn8sBHD8ejhFDRmdDq5fjae5Hkyjg+jk0Mfh8nsIswq7xjekxW1JYridxv2phF
/vCuwufBvMBQIT142fJEN2jeyH/YezmoZypMX/LwVSiJZ0blX/fuXHGc4hzdsU2YLsFA3c8Lna6K
9faoodyiRgTVNf0gg8NVyDdev6OTZ7/xe1hMA3cA8zWel2z3OCDdRD7S34iaSW4somQ3zMMdwtWp
S2AaDqOTXPq8P+jY8FHzN5CgJUsXKR5hw+B8v3+hsa1MsJBLOzPIWHJCWMAx0/iLjb+uxlgmHuLK
yAvqqvNCF18hOAoA6k0dF1jXjRL5FI8HlxEZJ7qNn61/ZlxoEnI7izcpXOMxifIUKwAE+pjkfJVd
zo4p2dwoCW+eGRnXYHDR2Z1eKmmNwWgd+uk52L0anybiIOoWnxSHkDImVycQnKDmA864i0OyAb9Z
68jXiP1r8Pg9PAQDV16mtDBHHK8QM1kzQ/Z6k2G2+cM5KIM/08oO6KndK4sADArPMr+oe0WYdMLV
+93fAwzXA+Ctth3QBq9qfq6IFzMFOFjKxnv7ZZ0gelP5u+TMw48hvNri6aAlxdClPlzpiWRYRqWu
vWkCp0xfr/9ql3YiXqGhV8RDmuZGagHWQBwjzuIKJpMWsA71c45SI0RvKkhxy+QrUnkCitoTN92F
nxLwqKvhcJRw8LNGw6Ylue3dRZ2dDGWXnNns7EIE2h/9Uq6BVU1SdP4qW4NF/zTF6zy/pHC7NybP
SER/vrQTnkegZTQIfPCQpP6KAQJH3S4A/hTQD/a91XZ3kmjbLU73jYt19SMOoBjlr+EpujJCG3Gq
cteZ/FfwnQKqz/O3xV3vRZ5MA0ddYXBOvxVYKm3RkdY7yovCMP42WGW5UnR93/VzI6elF2RhlSYI
xmwl994CaIxVoVN0a1Ihs8Dc6GNVwl4buRx9iCcj55Md/OqjZzXKHBzRnQ0mcGFuI3wT/7+mClfY
1Q7Ez6+7BcfTcFbIfv323agCRqNW1zEuSQNt6I4JabjOqlb23zaPU3l2gsQ34sv1xik4l1EJ6eyE
mex1+XuHMH/L6I6bst6KQAEGuoMJHnOBb4IJ0XWqR872O1Y5sDVV/bBJDlgm9YAtYzHjMy/sMldu
8aZVG+UNDL5jfBXS0uHhCTiPxIg5hQyNe3hjq65Ou2rgJQQRSrVkW3SjWFOaVvGQlpgnJs2ShCep
T5DjllytdNnDtuA19ZXU/DEJC2m1bvKEzgwHrXSoreW6xb7DwDq6RtLLiSmPkMI0L31tfbgNkzuW
kNvS5IYWytszpL/w9Bt+0jYgqNMo+oGYsgt5cgIZWjqAaunKVadQEa9Y00DLqVuN40qLIOKW4cA7
bnpXMblAEDblha3PvbC2pqMcrMIBg8fEyaUTa8Dj8+3lOQrLAuJDtdSY7Elmv76wOVH77uzEPinH
NotfasGzSG+iD4+lcChC4aUQBOQeuchLi13cval4S0dJtbqNVoIU4JB2Q/rJ9LIlPi93nNP/FE5E
3WLqdHutnD2MJsLeY7J+bmzYVtTSdKDrwIA/D1dmOS9WZVd8U6jeUBnk9+vZSz/6ZqqulMRArFNi
8ylSEA2kZu8ZK8qzDNM97t3ag1ndh6CaXk9m+isn+T1lNGr0eGjh+bY6rUEKIbApgySpmIyUzp7c
MbiMAp0FLAx6Pt+NtTYCVE82XguA+dhPX61VHOZKMuffqMH25fEdnF69KGvdF3+fcnBlPiEJywdF
JFFv/7JuXE7i0qydR59y1a//PxhZ1S2gYjDzdje3T4gcIXlYqOExn4omKeEmlM2WLfja6TA0bq2V
rf/BMSB1W4RV24EUomMQV8gC9HBcmqpnhlg/zArDHTM8AczxB2XNftbwnfj81Vf3cncyHC3euV3U
zcRaCZ3+Jj9Xs95rJD41YJWUKGkOV8Ms6hwcdELKWmhPNkCEHK7apodC4+wENox739I7hWZKl6+T
7j6TpxPOFFP8k7rxxyVBM/GFf1HSynY4+2ly8zxIzQuYyuGcWVBAl+FgupaV1rZp0SVLlqESWfi2
ZxNuoPajDG4fPPlVaQwXElvmynTZihDdsAUgk8qs001sRNTPcAqH5KKCoEsyCPcA5LEl1QdI7hFl
d2xXl7xLkidUh8yPGXuO9o3YDlYooJdpaLWpcUuG2DdPi1ZNq334dKLPXL+J46qG1iEsPHEw2RIv
YcdObpIeCwvJxS31lO54CwYFq5dwJjFCBHwdwsfDR3QLGd5uzasGA7f6tbM4yJqdhI4bi52F0und
XG27P+Ew4SajRs5aIS3taFTDYHv5m2tPjmLYDbcuVVQKKtrahsTjUVvlePneDdlR8qwLneT9/BlJ
LC6VtHcGzLaR/drKFfBlW9BjSyh+1V9XrJ+K7ImtN076vnu4s8MULPctSg7zSRU9JgvHsygHvUR/
agOKWMzXrd9XrQBYRbzjZ0RiedNPeR4nRhYYfzrkcVve3YlKp/M54Sf7j/rLkfwba90qQz1cLH3p
ZpBqDE35BzGADyBeCWDQCm13Wt4BT9nvj9DvEZnHrM8JtvmrXrTE31p3O+lG5hnbCgDK3tmyWfLG
eGEqKT7tqHUHiZFHWkw3RGFtNiD1sbeY1nVIxqFMLFCo+1wg3gwovVfPtdsHnYYY0f1e2Ord7liO
z2VwAuwns9lfi9FCIQZtmRAADl7Xug9ZdrAMzH4gVwONFKKlsyxHkS1bEa6nasBMW6W4CxXal/wG
mIXICPYm+dpuxGM0AqJ4oHFBzFrPvbrbwF7+8NtN/4rxyvZLz5Jdu14JtCT4+hQGwjVvPujSEDvF
h1pHizEwfNDi14zkzNGQ370zt2K+53L9hhduwti0TAe/ax63nHs422qcB1XFAV+ELJstQgBxwqQs
v8IZyNOL8ZLUnfyLpm26n+GSLdsO2wu87NiZUClO8dAPUihBw8lKqyOOlU6TBX8pIHaVcg+ewqLi
jaGjkbMVkss3/YjVuBziuWGQCzvqWqKPTCgmtyzB1sYFXIBE/RnUCiG03PJ7xDnExYGKLmpcP188
XyYf/A17kDsniYcE3rZvLADWEsjmM3YLTyl2sBjlZHInxtfAjz9TCiAkcPgmbA19LuOKYUdu74/M
oNomWs7Df02z3qKkOoVhkSRpHx5npOX5c+WbvXGvQruJstNgSlH1hSSK67VBHaoV5usEpUBmjw3s
DpGS/TOuQP3AelawstNajBOtFPaFd9hOdxSoMZcoVhW5NQxqIn2JNgNbDHDqMjAyE94umT6RmvZP
+bLRqQDE0Nzs14CuzM89Q2lgV/+4/Au69NfyLvcjDZJYL1QBtuUUAl6nopIOocJdJr1jMB9Myg/B
fV93PXxhKrVoJjeyRkR+TTbuRxXxT0rJsHupKr4Piz8kleqB78XTe8qo88/OZHGaZcN0wRk8mcfz
by+qe3aYIjD98Ukc0jJ4yaR01p/xtAYWVIz+FOqO//rGTyzkRWe/jlszF6VjCF1kDko9Zw6gZ+bm
PO436DdvKOR0qj6w/gs5psxvF3hBIcvVKW88tinsoV0O8FuvQu6AeKdpgwpQvUR6s82f2tgvaXpo
FskUgJQ26EoYyNnKxjmmf7+h//usoCKb4skmRNznGKEa+8N/wWzo7gTaoG9X6CUbBeWGuleTuKLl
V56pSypNk05MDxlOPOsfDF2tPR0h2MzhQZoUvi5RBZZDrSqw2O8XsoWm+MYognWurRdM1vv787t9
MJvSB1RpbJ4A8UZe6xNppQBpCsMiJwn80cjX01leHE0knHZQvxMZn6q1SWlap7NNRiOrEMhjpkKp
FwFlMklbdZ3hWjylqo9NksJ6l7CWlEx/mJrhRR27wy3DQlFTIq9H4BXk03MWGI1xV4Tnr7uU2nKJ
F2owW99bPyHZfun6LaKcS12Dr4Wqc7/9uqyeS/bHx8GgIZZua0yYwuuaWzJ12/Bn44QD6/o0Q2ku
YXjKbaMO1D8JqrosWt/hvN4h+clwruzFza5/l3Q+3p4jwV+cj8pfaLg3m7Kr0tNw+g7hGBqhsnPo
YeusCT+TKRCsKsQNFq4rpSt/KgU3yAmWyzxFePwbvhoHmtUOwfkaeWdhhr8hdTj4+Enlt3iSaJob
8xLPFJTWm9rnK/uemaf4A3x8PIX2pD5WRkGO4HtqsLzIdKYvB63uJFmS0VtvN5jpVnXBLueqgbOM
xt0iqxESaUkCY2YLB/G1IS11v+T+vyN20IzRkSI/c9RUwCfsI1JUtgPu/YgMq80JAz6CCzft9+wE
UlEYqx7oGPBmtBN9p8fI/wiWRp8vFLWyMDDtG6pSe/Md2ySBeEIbvCrXHiLmcDHwhv4RDQMUJqbQ
EzjyD4r0R+kwiPzhRdiIATjugqwrASwAH5TBlD6GxwNNYyyx+LxEKprRNu1HJIHKtTak1GK5hMLs
ABMQdINTUmKlEDts54vio5Ma7dpKilxFWG6zLVkTjWMHLH0t2CvCxylGhD6iJXh47eaeDoKUSzTa
XK92FgUjJKBh0UXB7XCzq+GDb7llPZVbcK3OcT/egGohyBq2CF0vKoWm2x2E6/sowMbUdEdQvPT0
JqIuhOfHMcdj/hqG7pBdYTHrLV/8bnC2U4Bx6uP9VgYlKkLdl2nbgtw0msVpT27YBFbH2LNFEDZy
FDWaVEGBtgzmcYVkrP5EgAes41vr1kXa+Ay5T9oC8uv1NDT/SLC8o+xD5Y2CFxJraiRq1LgqRKs1
oYaTZb2WIqrOoG0cZ98a1aRRBtRP7Q52AiFbCOdqcCn40IEVDOX+Wp32tpTRHpun9RcJHWC9gscu
sZ8+/1hr0fq4W7+2Iyi56gjEffXyIJKl+MP+DI14PTKA0oMG9bxnumRwiAXm5xXynuSge+w4IB21
LCwWvGoS3BGeiFyDNLOlGU8uZ3bW2pmBuatqQXqpy0v2/YivMTAcfcAAbKOxenCfQGgsf+pNxaii
xauWRBSzlz0r47Eewt7JN/oezjQbeFRTm0FYkyxYipSIIhhegVrowFwwtMHeLjeYCpXuJ3nhk/s+
iGwwQt+zhBi67WigBlHrtdNs6UhyY/iNeEC4dEuF3C6XRASDroJKBtFUquIJ+WfanpIuTAi03nUV
qwSAi0774/zFfp90xhcDAd4peMBGejBdWLckBhKHrrg/veUCSa1AupF42x/DwHn01tlnZ94zkVRN
eyQZiNBoBJVVBhN+67gh/ogTWfz6DXVnOn/QD+uxtEfUrb4ijvg6hs4s49hEAJPkIKiIn5lzveun
FKfPKB2PmRSqhXpFdWPk9SVqSTkZyrG8rpoqFKvxAyeogKICyKuSQzsK7u6Fbd6rriPvkN6YqUl2
0PvPtftxSmXjNy9bdXGM6cuLuAQAFjwNFtnhabcsX5bA8UMVOh+Y/MqNDl5wnNsFY/C72u9SD2Ly
Vcj86dyv5Y2dKWgGVdvNGxOygavY55jVBlmtxRMk5Uupu0vmzw0aSZ+uX0KV4Uzm4Uoj/5lLdSHl
d5IHkvpd53A0kehKwnpg9NgQVT8x9LbGBWpKYiX1c1nrLeKqmtElu//oOdOZEHfMlnmkXM7eK0sT
yjPubit6cpfhq7IzTvkS3F6lBup01/BHQppQdHUWFoFFQ3Pejn/S2qqSp2rzp4KMu8gi4xU4i52S
Guc/v/ZTrQIhrq8sD93fRqdcBFi1I46wYALQKqNvoNcO52whO48ZoFMdEgel241qH1pTjXGVXM+K
GTyREhrLTrP8E9i6WbEVMrsEkHkCkUT3GB1nlSliF/W6yqj2wiDCOiT9iPvogVhwFk6yBdG4SC94
FvpRpQUbprK57tFvYpBupTtNuVWYvVAUbpt6FherI1haYcrkyJVV2FDUa031bTjSjjnyxTjzRS6l
iPTRSv8bmYRuE+3iry/C95mk99VBK+M+KcyiLSmzcEUMqhPNAyAjeyWJowFnuD9Hb0FNe9R8CEwH
KgXz+MtBwzxvUnUjCj89qEyYORPslBORhloHyg8ci9xP1LYEpnK4aPlo/d6Pn/grxcCP486gqsdl
jTJLmUpXXxk9OPURg8z8W9atMW/zKr+CNbCbQ9lEV17YMrH61/HZuKbvGBnRNTLqfj1NltjWoNO2
9y/lZsRAEwIDpicAPE/Tkbx+pr9/X5Iqpb5WVmZz9LOgs2M8rnV3Hbmhb4XgWZZ/SPaytLGaGcE/
l4iL/iiqWuAhR/IuF9mKeQYfXen/gWp4IYSBZn1ewwjOUJBTdqO23xgESESVuGPhQQb9wqYrkVg2
HQ+/CFaWIChpc0T51KZii3i/jCq+oUeBwFmqzh1YLEBl1jwGF4/tUJytFH8YTpt38OWxUOicQspX
nKW1T9Rq9IFT8SNK/8qaPSQhRPhgcs/DX8whL79kmcIFGXNUf5uSDsT3yHarHGGsuhMvvherEknS
anFSbQMNYU0rttqwcIlPjfSUpg0QoynwM5wFFvTclKvOFNpH8hnxpv7nm+tBJKvm5VEWqJm+1d/w
ZFv1DNqPyHtkv7yaZ3JIBUfwPoN4GU/QSD597w7uOuHjwtOe6Ad+dHpggBt/KlyuxvveMrHXXBi0
YXSC/ETxIGlQHsZ4s2mseGvDutXfSISA3en3tgPzrV4bYR7yYfRRSClNQCv5GuX8tdjRm92SZ5kp
LxaYxCrpwCQIrhnC2nVYlJvdlRS6jD0lzzu//3HSOEqjSf6mLMLQiYtI5KMNfZ34egOw0ifpf6lI
fyfcmiMz2uZSiFwfl2P3dpKx/yOkbkcQxZSwqdGn9pyNEp1CDpEU/jCwiqpUeeC/YX4Y1KUPwwqc
rzM+CnXNFS32sfI7dkx3Z7pWddqLbKePQEYpq+BwZYn77YbDAV0p8ZO3pJMkQlnnnW0T9BfHXvFs
Bw8vASKCcmxg1xp0y8lmmcBU4w5biPBu2AuyVoYCmbdtz8RQ5+D0qw+wECHEK6tG2La1UWTP6gVo
AJDkSjNtcw4FRdLSgvrJVlt7UOp021kJIgwacg769XqzqGkkCmoXVCp0Z+SULWXDJQnaxBoK1ACT
Iln4ZflUxE/7TPxIYtPzQC4ApSxGienCTm3s7ACCKUI5swBxZAFg+x8hDMvRJ2+cHonZnCKfSjAv
G7yxWDIkFeAat3vche2DpkOwIiVlEEQvOJLAOKG2bJ6byQ1Mfge+YR4kDcd0k82gC+kynFV9OlYc
hWrDVrSn5J/o14Ub4WjLw2DhsFukeaX6fUKSVO3oCPEdHJFtKjODihccGJ2wFXFdklel1SLPwP4/
1/OpqADjNMl5LgZNtrjuOslrOf5edjdL+Bs7a0t8rGIPemrWmWoEiMx+UrAsVT3+CyqONjTDL6Ao
YVt2Gl/zI9x8p68/XszQLnGY7IUYvBST99zwvMlJkpkz2xbQ7MQvFjY6uXKFz2vCtyyg3cjBgr1k
lW6ofAaErpCsr9NCM0dvKgb+Q0wPQXoSFhHa2h7OmD+B8HVFJwEkkX1H8cCVM8WtymSNF4Htv8C5
ZTUVhB23kRRO2uISeCD5LtPcxm/4hKH45rbkLHwkXYaCejE7tWvoIPjUdoMJmm7sR8TNTP/lfdSG
T2/aPfj0lKEJuRAr/f/uLg7wq6sMra+NHEPWu9+KW8Cd1N/6qLntfSGw8qiTgEOw1DDKRObmXWfZ
4zWxhb8ZuHlb7bp9QzDFo4e1duXWwzvFZxIvlr7EP4EYvnA+vyNP6I4iWRCb6uPQP0H97RCNmYbe
DTXh1/SJSDfRjxeg+aYeMebS6Ovnbew0XZ2rJYLJsyfDHDsOZOEV18JEhVGWvj4tk2UEjSlWkod8
U26ZgLtng7sHtVfDgpu2EcgUnURGopY3ywTLTRQRu+lq2htj7DDgUUAaWdJZoE5BN4i5hOHh+TWr
JJa3BS0laICOrklfosrN6sUmE2oVJolSBkXTOiEIn7oHXx7istiNl4hde3R82u7QfL8grNW+20G/
csdZZ8KjPj+dvlUpM/hziQC+8ZqcVMKqUxH45xncPuY1Eznil2axF8F5eIs8y+57E9Pz3bMvP6J5
KEfG2fUEyB7blGsX4spsd/8lYJKpkhcM6QDFA7c7yT+aEGR50MboGKQ7/iqy7zm2q3HRHh37UcGI
UkK2EznFCGnMAuq8omhbUzIJBXQB9SMUpYlJ/5uoXiayxArvbzb7VdgWyDOy5T6fKsrAaeHjAUEX
Uy2aaWHeP/dqTRMfGmatkN3ofcpzdcxIgtZ81V98dFeFaRSrOT8uGTmeyYA/KO1wF5pxMb7fWEW/
uXgtDeJrcY4wrn9AkM9mgKGUHt1887pBEJ/zm8tE+a8gyeNMdSjjjR9LI6Q0eY8Y3Bxma2ZxC3IW
e61Cn5DFENlnQ+Z591J4kTTzeSwnvUaqc1WQUQP1CKWceSFmAapIY3ERwwKE1waR83NoMo/5CPuc
cZM3RIvgdCPauDiYIuDxvUbmAtSoAIJQmXdsllrImP+3vDyfIsUN1LPHizQIIH8XwcUMQmBtkb1S
bDrsHXGMIdy2BmVoEo+BPX1RkOy08d+lYq8l009ZmzUcXdtq24jtD1JFExUa6CuObY+jHADkWQwx
M53t0D0PDChm9NHKGzGwNrzge/b6Tl/AB7UeEw8JB3FWAtO7mEC8hMTlVl/W9XbPsPB1dW+47+UF
ZRgxLTju/+9o3nfIWAM6K8o+gQzUqH7u5hrFh+8O31GvywHwkq/x7bI92hxA2uXQZGSjUz26BVEh
9GHKQD8bA8/+DzvTgRNPhYIvltYWTrg/mNptRt1w108uAMOHDEEfr6gwABaSQF7rieDIon+RSl1r
+1i3kGwoA/7ljGo/oQ2ISf5dpRBoYJtG5qJ4GCn8W4xyNFj+eKd5CSoRtrwiJc0BeFs/i58UdOMU
lC2rlNjVdaMDzk7vTNam488eOGE1TprE84DwgAq5/KMQyoQQnwfnsSjMN2rVve3HICQVU2sjh+S8
dlG9NIH3xejLX2vou38tzfCbXCf/Qs1srSgrhqus3Vx9vHUfRVzt3MJoYL5SrRTrEUqSJjuONHFE
Of7q1Kc8ZIdonZwHfFfwZn5bZguVjAt+41SU8ewqDN+Szd7UDEHnvnF5HKNqSEQErqowE1xpmod5
QuS9Gg+K4ujPn5QlMH4eOHs1GHtir7E207fUN1LJuacxNQvrn+9hwvak+2nL/Ewau2om8VoxDvGE
LXZLQvuq0S6I62w9LHHVbQOjLoY74eUu2YsQ49BCny4zof4b75IN5Txhpn6/H3UXexBL9Jy6PXJw
nscf5m4/yXyLSIrmv+U78wJ0HnlFeaBslZdKqXvDyaKTV+nuIvnGHSAoNqJ/z+UKHY4vLtZ7BR2Q
w7dGUE5nGVdNouK4sZ8BlqaNrmSRrSSqxrWBd4Tn7WT4c1YVShoFG5ivxRMzJ8aS1xxxzofMx1+T
mdFdkjkb1UdWGsXyaJ5BGPLUfxaa2S9KqGIOJ8vANB4T6s0KjxQH9rvJcXq0eJP5HcqTeQumEt2w
+dYXBqxZTHoutX1R+0smJMFmGP9aV/wLC8wYy86uB/qzHPrLGk1ah2D/apEp6HXYLzPhL41PyiZV
Etw/JuGdpIb1WnLq3faztB3kcR19rfybRf6zlLIKwh3QoyihvAY7GMbgbRddStUn2yfBSzUxjtYx
3PaZ46k7zyb2JXc3zp480yAjIHljtTI4/XTLNrhJBl7541f5R/Mt5nJnU9IyO0JRF72DJSaWDpEs
rKst5GUJwRm5Bw035a2ogUcmKwUFxy4gOPc10ephbzsTSxh5Uvqzb2hssoLbJjWh++dYLWm2cTLo
ieLRkbRcb1j3Z0g/BW05Lwb6tTnLFhPQHIc20NolooS+UEnBYj9gsLlRLnXahdTpHxOd+3yfXmIf
5Gw3j/APlXdeKNPwt/FYA+H+u+cvUbbJtoQeJcgZOVx73+WK+TT/TL63k1UMTexHtEPZ+dhXqFaJ
fYZnhtYK6y0ruZNWE6yRqRs1CxGMYMC+zrE8HnvF2M0DEFlqfG4CrxrhSusRsjWQOpHLU8T/I5Lp
5Jlbig2CCWWciEr5jeeBMQI03z26ajhAsjRKpbQ9SAMGpEubwcHazMY65W6DU2LW2v4cM0d39VgL
fCG4hRgvqEKRbd7Wl4ssmNUrNr2b22AfCNtSaHMEggTrovI6v6qP0QherPSPnehGqG+EU11AT7nH
/VPMyZLpXTQI5x7rgFWdfIy/9u1JRxvEn/mnZkxoKoVnqwKPrReawj02N2P+lzpiye5bMFZ6B4Oe
U5Rcy4O6/bJnKnFcbDtWoQjUmeyi/zfXxQmVUutVHKlTEICjGjL3wAWhinmKLvhVBOjwqA1jSgNc
wpHcyYFvnu8MxnixfLLs4QTYZrrS+0N9+BYVvB72PD5OgompTHe8zD9nJUyvZ2ViAVY1+DXNfAaT
JghyZ81j0678S+fKx4Ja+2OON4BAN8e+xSy+QTQEwChMcjgVuKfNu4aO/leVQ6WNQWhLLYAyi5mN
IYRUibdqBNZcWhO/SAyuFPVFXH0eXmmJH/x1t4s/jcnPvemOJW4MI0vfdFsq8NCgO2ylvayq2iKb
8YBr5FF873UdfcBXdWOJbPQIoEFW+3khuz35EuRrNojeafxTyw5mcRtp3/bNPuKMSEipF9lKFXJU
6/ZVsUYPQIDq2Ek/unBWYJiCGJb3ClmNX4IvxPq842XRAWJs9y5oq8JOG2HlAElq9r4geOxdh7Ur
hAE8VwDZXDxyqa5b7SvdpklJ9fRjKugdohulFcz4ILEZNO9I56AaZmOURfyGF7/YyD+R7iQVj1bm
aHM/PgSvRPA5Fn0WPlrlPuMqBG7MUozQXEHRFX2M9F89T/TIKkS66iNJrUt6IAJ4swzerGwtwXmA
77vAAVun/BnX8ZDDFKM1zz1zG7xvkBGYsbWndyRn4d9NWlez57B2M9ONBzTgF68hzD7+45XUwY2n
powgXxKxK9CEEd3rB62ymEduuOP7FwrndCB+XZ1I4K9todl/vFMuFgOHZBOisFzGOFXWzXgHcCn+
mIP4WnFB4IVqTdVz/9wwnU8PiemLJQK9VMPemKuV+U+uF477/uaWH+z63PWOwfzEqdyja6MnbVUg
JKeA74QmMZ0HW0hHK7Zkg/3U+DNby0fCuC59Hj9hpZZQZehY/EOlR+QkUkf3Uph2QdA4DhyShIdj
eTkimEvuWWnZAk+eMGktCU6rqnZG7bSgcpJYa4J1J1D477bjGz+kvBpHHDC1WkNjo+usC6Y9vBLu
GYO89MeZiwAws1EumuZZRpNvh/h7PnrN1n3yC/HTYmhDiKUzrErpEvIlF7EecIUX3e1/MSjDvFIO
TfJPpN77Li1VpNTwhGrIK+cOhQPAT3JJjgPCzDKDr1DfwfNHflMq+li0BVtqRPUc6RFDSr18VEuC
+7DgtJpzYdBbHDwsd71Hk6WdV6wqUN2c6Hx1Iw0PYPcRSox/306qpnak3xxX+LU+TmE1zbZVEXQ5
zWXUAS2MHKXK4ZkLJa/32Wvi5/Y9xxQZ7koBZrCGJOjXKkM5qv5RSIuS1FqyNzjoFKQECcXRFgHT
969K6LBbhqLtEEs0tNPiImiazj9DkAhy57nrHvdW+Ojub2SLuciZ5F0J65t/luJomQV8+TdZjjIC
AwBAi6Mt7b2oSZiXQsoLk3TLcCbv70aK5QD08WmFKBJqRtCu2lsCi4Qo0R7WkrC/EynENwxt0dqP
LSJAubwaUDLCbS6h6+fXtdSZEHNZLahm2hIw3kIjTOqkvaAGCAIvGVF8RDuBkoIMByP2FS+ti0rq
aaQ4mqMb+I1hPFa+lpUt5Ny1vdS2M3S3qCTkEE8l4d7jQgsbBN0RfY7wvkZJir681j9JCCTzjEU/
E8awvnjeI+qOD7Hb1mcZv4YOVXmxe6Sbu7+IUXvYsuFYO84fmn25Qe+Yq9yCg/wkGLGCXUIqF+rW
jXA9ZZOUKebA23cra6HcqBwzW+Uzzf9Iya8CFhcW+C4QSY6GeTf+L4bEc2BmN2uhtboh6L5w8Nby
B/dTSdVoIZZG3lFEZ1913ix5tPUn8h19iizqic1UKxD1vh78eVGA+KclUF0jdcsAdCykMfp9CV8b
fawvCiPXvTPBXDVX3j5JNlE/NuXAuwqHn+V+8DivWXDRjffyY/deMNb2ajdabtz4vpjdAkUPAcv/
TEpqujrDe2KRsA81GTdIUEvDhJEOFI5v5P8amwBktep6EMOBcoc+39GiT3z3AfjS4kxaQXz6oDTo
Jv8ac7tfJlm9b5h1UlWU+oyKVuRc8uesEmGTJI7DhzW7ek52OkMCd6D56hgiFi6kDQWx6Q7+jhZh
NkyU2NA0S1ZUPgP7+JO3emHbXxUqSJjJbeiTWmj+Cwo+MA/A63ayYFZNEWu4IsPly6SWw8XN09yq
HeiAiRK7QFGsmKne9o9yAbXhV3RvNwq7gQlTVAlVVzMRZVTVOQ942qox6lmU35m1iyxcolS+pD4z
MQPFLQmGfT7cV3azb3W/UW+Www1/PjS9SX9Viioagl3m+MJsoV93yKWlGZpHyAewLwVz9WsdmnIo
LezA5Qlp0H3TzcUW4SlmHzUfuqC7+hk9nL6KqNhqf9UhdnQvzLrGfM8gNWmW7KfZtvPZukJKGCdx
J6wtalLyg7+R7kUZYbSFk4lpyDByc5sqIRY+/AAkCMzBu7N8OFrBOFI0PCpDEpTt9ygEZlVbGlhH
TqrP0g9r5MKFel1x0ljYFkkFScMQe/RW4UrCeK3Ab5cGxb2nIzUBfdltlROPOymS5vkAjCXlCumu
U8VuTtobBI1GXgdxRn7rvnljSPcmOmTWnt5xMB8KgAJBOP71XajofQ+mEjL/XKNbUeRNqI7NVnE9
liS4h3Myi8zFGDdSDCgwXB2EIDC+D0crdHotJ4X7zua5hBceAJxh0wkiLukljUtIzIFdSN6vPJAa
3dn0rrc4V3o1weJy6qJVU5TbuUldbzVlCbUluzk2Ri/d6hwpPgJUqQN3efKv8hZvZVEjz8Cdpr81
huODyWVW5ra0oRYTtvS3cUFw5K3HZ3y+I4lMwoW5sXvzWuqZk37jOp6TXEjutixyd7oFkYwCbXn1
izwHf8/ONWYLOd+80B/FrHjkdZpelY56kyN7dYeBNTGncXXuG6xm9x61Vx0SxxFPEsbp29u99IsQ
LjlGBC+1G/pNdM1IlPB3lZ8dy6eFHlqmuUtqP76iyFNBSp+Dou1jxnaM3zni18R340nnUHo7ld22
gbr/N7a78X4Dmtchw0uZ6+KzSKg9l/SyMEc/DC/c7AStQ9zsGpJr9ApyGc0NmjcfW98pVivCtJk0
8j/rL071eJCEfiO8jSEEXqe4SVRGA3Vf5uiOGkWmSbNJSyi9+/c410T8b73lwQXiOeT2LySyodwh
1AiF3y6pGoHj67wyRxgIsTZNZsbp3i7KPmVE4id+8mg+t3EOPicEKkrU8Mvkp6WyO1IkwsLLjOMv
g41g9pIrVq0kT86solPGGWhnJaV/ciLuRMhyOAyg0BUH+y0C1QONaueAJgELs6c3HGfj+ZBEvW9v
u2E8s98LEWElU3sg1nFGQxL5Tv8XZKyoLu0RmqT6emXSyUHeABNTZTCojFO+kjQKbuA7hc1LAt4j
1bPNiRwWZTwg8qI99lazFOvtyoJzgOoxZH2whjmvLrsCSVKtHG5wTWYao9D770trQCETa0haoap3
JfYh+S66LHIVjqVxjJNLNW+s0F7gVZIZT+Cw96X2kWgrlMGz/pErsOl4MHU0d2/D0lefWDHK7i1e
47aURfs/guL9wkb8wuBS4s+IaHxQdsEXM1mxsAykxtFd08fij640f2axYu6vfK2ToE4kDcEhccjk
+AjGfI7byL5fu2Rwr1a6VZLTMT2KDOTpHGCdHYNvYuEOC7iJvWci895AnT3Q3QWJiBAS5NXaAysk
+nKKR27MhDuRUn0+FQyiHiOd+m9zN9AaPOHEtIkRsYsJtN29b8eUfaugaWxnDqxmVstZC5yh+EDE
jbsEVRm1z4zBdqtFxGRJjrA+uP3gPKMFptoJ+AWXwH/tWkBNJgk9SfmWm56oi4BqbjPAJJO9gm00
4+HhbBGDiRZ17+E1btHPqPfOtqgqNvUu8PtakTiLnBv8fdpO64z4o+lSJQs2XS+uE3qHLANuR2q1
EpDHjdtd6Ec3cL4ziIJMXlLgbLkLrtf3aYtdMcb+BtpMTTdv4fhH5DmYJI8VugDZ9ojIcq0mx06E
W0BXfZ/oFsL5qo6751bHjNQDHy8W/nMJD4HivG99tytA+6+24zaT3NCPcqCgNQZEETFRK+JHtxwx
JosVqc1VTUab+EW8DaWHHfjTNDO9ZfhYpoBnpI+jL6x5nYjq3CLOQ+44pqRaCmOaQncenE9/uhRa
O5mJMMELNjoEL34ehMs+arBjWsS52W/Kf+Si37+ay9u5+nrKjfpW8aErw9upjmZ1yOP2beROCaOY
YnmvJItVwg6PSrE4d3zjYPSVLoIzc2e2b8Ai4MHbMe6MBrGLB1aH5IVM516u0pwGc1oamwcv10pI
OAPaJxVxcmAVXzsGZjRnFmeeGrGNZlTCMFH3lc9KAL1YvKYhbQBtxBsalZ/c16FE4+S4Fd3yeagk
rDMfqzFeHUf99rz5T0Zj93HX4wHUjBxE/JkubPR3u0woDTGUTmf+un5lMrWKldOdxkZVA9FXQG8/
W6yP9YIPuU+Tz6kJ/U7CZXhszs/l/JKwFMf4A1MkgnJTYuK1pwBIzTxUBkhvHve9kb2rA4hKVYsO
3qEAcOji3jOSddgNBS+vUxDLLDPe5MX8ew3PAcZP93qMxl6+uX+lJ7mIUPxun31VZKMlbEaLGuoV
BecX1kEelOjRLFPv417oF7NSSKAW2zgpuxDakbUIQXAgtswmJMrgbOdYXk9lyWdSHK04R/dihjf4
QboVRW19u1R9KkzSsg9krbKzTL+4j+GUU3T3vIutEiDZkOrI+ls0CrZq1q7u/AjUHpGiXAsDKcVQ
DJ3lNBhii8EkRl0BN0kC1cebhYrpdnqTw5TF6x9BYprXcM55559++hio9szxuVUj9C/e8hg3oh0P
3eBiI4QXMMrFqKRRFeTbv0UKud6PQ/+SSDP2D9Cegfuku8ULwqnJjgLAELyBBJ2K65bMyiggPuAU
oLKmhPGVUerLXpwYclWEifm92OMwThtanXW1Ql0ITNcRcJEOaf5rhf3vWIrNrYzZTmPKafL5/ezC
cQ7BNUHXeHPJgOBrA1JtxzGI7RoL+ubS6W0NQbAWeAtQEG3bPP7rp0haffCpuZ1i55mRUhUWKMzd
/C6b3868MEDrqH8zBftenFVMd/Iz2QA/6nhz/qH/PU4ta8ENjKHYvtQd0yRbwI/DLGWsf/JsgZ6r
+q4BSy5dYmN6ZOsHFxAPCfuPL0ZJvPU0jtCHCp7TFRAdrJmMTKXC7pUox5gopzCC2gpueuj7JmDG
jyVkwWpvg+d8xWnIWIU7/rX6OR0/udzM+/yObv0sZc1hKZInrvX7NkO0pbuM6VEyhApiIj7bFqdK
bl0rdBSvRkVSHdP93FBpYnH5gNb7hsMkHHaIpURhfnfHiGAB98LX6DbqwGZwG1b+pe+VJL265djs
+J0PgVKc/A+OuOCVTO+qtz3RKD77Y0seoLL86/W6Ad1sPUQiIMBlz9chiavqYqgnRMvYK07K5HU0
UhGVHwJZwgP6QeRebsTIxxkmGO5spVQQ7Fj3nC/v8s8mio4dLnvVoPkK6P5hOxcOWJQju8ftFKBN
zV/OWCp729KqxFF2Aks05VRzMkdxAFlRem+yEC+IdNTkNQtZpU6koo0dbuMgu924I/cm2D7sweXA
1tOXGx5XtiPoPjTjIroUjHzs5A1FoLTsw6zz0E1O8QCSLjgPaAnp4a1xGCr4Q2XRBeuh9HJqc/mP
+Q7fJcYyjwowQRXq7zPpqlOWLf0ih720OwdWGqb6Wwi7GMmDISA0heom7ujUost/+TjfMWn08Ia0
VpLI89zz8m+C98W8+XMzi4vNsFPJDe6/Xyhvh5kNVn/fGYYhAidjUWFv8H9h8LTc3jS88dtfs526
wmXP2IhKaI7N0jTUH+44dNKfOkbxaI9KT6eSbARogdsU8KEnWSsu8sJw/LS+yfl/g8qE+AqayAnr
uRicwrsW5O/zrCSa0haR2VejQ0Ml6iOawOOLqVGb1ZpgHOXewx/pwHKYL/xzTAjY2AuxPwh6jmM5
qYLPOWUosun6JyUbENGzBEeVtP0RX2k9oZWTFPMVLJg1MWzvKHdK8adFsmAhGtu1HHhQMxKz4VBs
idTw8TXlmqDKuUSzEBwtj0RlqKl14RLWKsuDbrgNkIlK23aAlDBSqizs567BnPe3vZfFq2KbRJ5K
bur6xKKvw2zh4iHLsEyycpdo51l/iPyX7k9kuP7hz8d+L2Zl0FMDcHRdLLrlKYBOJtri+GKz6rAX
0pZqlAjMB1Ue+jdfceHo9wRf9V16dDp8X5uIjfPr6TMxhsaZC/WE/UUt825DE6TB685hmSXW3mWT
znDTLXA9086FhxUGH/NkO7WAEKu5CmXO1dKPnCCxSpm2nRJhSbFhxTxYZCcMSgzjAje1eiLW7O7G
jo2B3xBZpj1cylRQ7WP1yASoCtF3m7+8ubIRZlqoVM8ag6aKbRIKSZIuYti58ks75P/Cavljjdg+
uOAKaua7/4KNAKBwWlvDOcvy3rdnkDgusuo8W8hZkkGMRaTpiHrNIsqIE8De5OG3amcEa1+kMbWN
+hO4XklzHAKA0Ut7lJOKFM0bAlzGC7OT4TyZNiOWyfidlFMV5Iz5hP1oz1jOC2s39pcoCuwOvaaZ
qIYoYeLzuixZALKVZVF/ijJi26kpcCOoqNJe+b10HxAcuM1MFwgDmCl+UDTCboA+55Ts/zhMxWwY
GUSTNyA2B8XOvczrp5Z7cKj3UCYmYPdl1RA6rgC/zYBV9kG08qWT17QbvoSkWNrinMfRXDafSSBL
llBzomjzjsOcmDRVZAlF5RPzzYtnRbsBVrp9iO5ablWJSeOY7+2MIjMq5D/j3/u+b/ls5GjewS2C
FwIlwFW3UChiyFrVI/4ko622M0P7JMLiKnbtj0jdD+U9ytCHssHKktmtep9T6n0jUKSErNn5nAg/
hvcTkBztxDdWNL+TcQiMS7raCFJtD3f8MqW678j0vwuGmClPz4LELqHfXrjq0BgIypDoNK5Ga2lo
NyE5UTXsF20ddlmy02NplohZXzrwF9hp5JhPaPeqcihjlOfIBFuSpkaUSmQ3Xsa/Lk3/hcr4HM0H
Y5mYDqmmMDddGU4j1FstsQHXV34cu1MzHz/xBTsJykwSH6Pj3EXAOlxAoieh5Ojjcte2OMwdnimb
cN0EjEWQbJjw+1f18ogk/uyTKjt5JP/AtRL1w4A7Q89grw+nJKboYvsMTRogwM6AgTo3iki0pI5R
WZVcapNzepQN+AnpxauBP0i1MAGFkljgeym8Msf4ng+QbcbO564jpXqB7iIDtNeW3Q5RSuKcJDPn
BzIhrC1IOjaMChwXdzQKEYy2WBzvhgRU3cT6kWDRJfAEkZ6ie2YfpNPg0koqT9ytBWTGHCGzq+ef
7QTSBMlBoo++76Lo+q2Ntf2Mpa0cSO30Ge8TWYk0t8powQmBaCj5U/7cQEv0jdVFVgZrvUnd1SXG
RBShkxic/YWHtKOqbT5oSFFZPWP9LP4UokPfKkR4Y6jvhYT4d83thg9bCegOHE4LaMP1Q/WqAKke
TMqjRCrFKwKKKxrfX0F1ui2AfPWWvjGZxO3j3s+yRcdsHRTTWIvDRrPAC3Ak2AZGoL9PZjWbwa4S
QMAuLqH90xpD2pUp+wYQDTUL4zBDBciVh1APifz219SmwXTIPd7D0IKILkewbOa/2MG6QUQcpycb
ZR9s2vDnzqX9LPDV8XoKIbItxX6WZwJ2yi8pYu+C7dqDTTvGC2HJ0Dw1NSNI6Jku0mgycR7Yf6D1
/61HC+cOs09bB5zS0Prxnp00LBYyzu05RcW0bzc3uJAadpn1SiNx8W311G9GC1q8Y2gfPPkJtFI9
YRYCzlLN1kR3I8hZ5J5bTrd77F2Obs0x6KOjYGJF83K6BT0zokHybI31LFipJpOvRMg98DsQCfv+
6tNq/fl1/eahcFNNc3OC/LuI6v3u4OYlrCIY/JcXToi1F7BZTw54ml1ipXyUE6oF3MZ1rnH5KobI
EJjG/ywN8wvNXiPfSLhwelWciLTV/IS4B/2KvHp9MS1/G6nAHHoGMqXoP+lO7FDckzzZ7MNLhVAh
zB36Ne0GwiOo2o41UwS8SxlJAyFhWl0Co0P5aNrZOM4gpK22i/bqWd697LKd9QYiGnaMpFgOAwTw
qv+BgNGzRdSbLRIGwh61RVc9G9Di68if3QNQTJszWgGbhFFfF5BIDOTpME3K++tiy2S4VIyQbG77
iwjtKzljICb/BhoGM3XiV+9IKakYpJdMW/4PWrlUWUVbHkkz3zBuqTYk+k/q3OnJRVFvf4CWBJAF
tHZc2gRP2vOSUzuRGvZ5F0RAzS5UdZsTM21hpOOeCVyPdjlOKYwylrFGFqV/p2FJvxtx9+Xt8WM8
COk4Xhx2DpxJ71qnkO169i83PcQtZIa4R3s44ngt83hBgRZ8nlvLyPIGDDThwJ9YzWdqqOYnaK82
IJFF4PHj6ASyInuiKF4nonsTIXX0jDTe/UlSzmVmVQvbPJFDctLyuKQ1RIoar5QQTKNFVLcs6gPB
aSFJqqpAwlySGzEUeYKAQ0FXtQwPNmtjyndZRoh4v1vQOKU0ptUliDMdoBRRhRZnxSQbNgij/Lsr
B+TgVum/zMLUCjQk3+pYB+UN7d7kIiT5oqibLCrUedc2gtyeMkajGu4IS4FyEfjnLOQR4lcIGKjl
CsyIADJTtFoTiiMJZ4TMvGs5NAyJIqbeCq5LGODXO9TVppxkCc+2vEGNVkOdJ1dMYoye0/zB1Dkg
9Bezlh/yNmGGYRZIB7MGTqvAn3fVK88adka8a+fLnIXFaJ4pNkPUnIFvC28+vGDINP4E3X1YaVbo
sZZMpr5U+LpRJQPZvgdRWQ7uN7J7PV3X1IQo2ZtagsILSmAb2d6RFjz7fynNKefmlQDk7hzk58wt
Kv54zqMPdiZeolFiGE3wFvNbQNq2R5beJHd3t1A4HA3Y9cjRdCP8K4TPtof5Sl+FRKKwFJ6KsNEA
oPCKIqKjXfQsxShRnz+jxERkK+vx6NisZ8AQIN4O9K/Oe51Jt1icDMbDPcFaswi47UKPqoq74riV
ya5VJEd7vyYYv6wxsLcdvIbzVJoQ7h5HdOq2pfb5pfZyMqDT7PTElKHVb6s43B742ZS5IOtIKThX
KVtHDYwJaVfarX5TM9ZpAVFejhREPA09cgzCwt0l1eW1lMh8dp0lk2a2Mm9yWsi6fvAUrRPDuZy0
GCjHhuFavzFj/XitqrQCpup7LZ+3hv1eHgJR+SQACHerXXbrOBiLp1F3lRFfo6Z6OzBpzq9ifN1S
IXa3OoSMQK6cfSupcEo9eXEiKSy2MXVlF3Appq5SqDmF/Sm60pFW+Vai9zAy7YqVtePfPhtEbMkn
wKII7+Xde0S/x08mGwAcnM1G+mgvq6lmLZkbJ8KsHO5kOJVaAMYq9+S+AiOwFAVB0Y6Sg646g8/2
lT0FsxfL8C8KXFNabC/cYiLczLD2uFtPjbPAnygT2KzySy8J/OQ0tE0V+kMAT2lPYh8BgVER2bMa
eWKAONRuAJ3og8GzJkGOqeiAXeMr2g6WwMFgFSr3IUb7h5+JGbAiYID/kTLXm752o+cHBuUxwZVp
ADp2OPofb3i5OaB0ft1h4rG53zMZLuLLzEWIKcDQODSXOEcd6e9JC32YrCRmOkgQTdUuZJ5RGD/U
duTDqQgSZqFCWMnfpJLrukl8PlughIyedZX7/remRN/87Bm4Mx2vJ3jvSLwGz3Kv/kzKh4NtfVFU
l9nB8TiqEnzXSQpSLfYBJfLeX5xBUZA5pAJgg3EiwQebYjVIoPTMKzx3vvPf6q+/WHxIPWfhg2WP
WlP+nh24GtsG8uLnsyeEkwNPjbcFSh6rcSqWalbi9RQWy6BfOuPaJzU651Mg5HTE/42hZz00mYT8
S2fk/fjgOZyMre1MYlGHz+AbP5iRBjL+lXU0uFK7wVM9ZZlylL9yJEtRtutxMbPqQkk7cHS28dcG
dpybPai1Rcxi89M6Q6E+POoatXF6nlSNk+CgR3N6XbiopcDWAfK9n0CI6hDdFoXMTRccwIABLzSh
eOYFVilKpcMYYoDD0bNlwQZwBACbbCSTjUE3kfXTEPn9owOLmEydnvuRovoaciFQ2yS58AM7zqUp
NikKkMstEd8pdd5WPauP1l87Z44uOGGrLvhcDN89M5IJNWJJl45Q4hTG//2SmFx94Ekso4+RJdvC
46/9fne57C/7xn7mGyxKp1V+Mb4W/YoVsEUKgaHPNjkp79Oe6b2uuwM4RRdDdaHxrjvpQBuxPrTM
lhO5dludkA/o5wne9Lfbi0hNJ8E98RcPC6ijVzIT5dv3zLg7j2DtU/1eplTbCi5oElg6cnMmpqKY
9UiXfSKg2wJ878SinRHOUkveRk31y++u+uxSlz1vs2V4YpK6X/wuOxrQUjRfDrT3YnExZHaJm44+
4lnRKBsw68X4V0veNGPJpLyTfNdZPLfuEcvdGe+94rPo3aKXbB5XdvgHyBoQpGcPd/NxM49/u/Sv
DxR5HOS+KaqEgyFS3AG6ShjCsg9Vv9ZyaQ5Ocdy4XZr86+9WTYaN862ecbV62fCMC95E5jUHEvix
hcluSFMKxtpcnVmipT8hErAvwtQSwUMC/LxmrdeAfvBdtrrgn2hbdww+9t95UQy/cG4SjH0OWu7K
ImeWgA9IjOIWwrxsawUFi5amcq1E1BV+1GO14J6cEOkeXz2raPoEQNBgbYPcV0iNOoY+RsukbKaT
JaCmfYnO6H+XVcH4mpGtwh2qNnz4tt9LgSueSKJsLdc+tEXEiU1EWZdwYbtVgIYtPia5BAMqzNMJ
g9bWtTCu7h4sX3CXZD4sxuPCNHznJpcpi8cWE/7s8e56Cwa2qFybFWAXL0/WTBZz+oSBUAJ3uIQM
kNmE8TybKLc5SQyNa0mX+HpK2VluBrOYTQ2IGxcDQoYtK6i7lVo1ZetG+VMok5RQ2ZSXouo+mB4l
s8Sqegk3Fr0QCTh1tL7+nHlYwmpZxCERQ3KnvwYovIHcb1tR/c2qU10HNVBBd7/OBX/fxQzeVM3k
Ycq+RKA35v3r3IFq2WB/s7TaCeJ+mb4ANGluVCfN1hJDRC6E7gZrE76ieZC8i193obzJCf8I1td+
8UUafC1MIeMrd9jGzzApYHuJ3NFCvOUN/OunyKI8IYLIPcbYsACfdnkV5g4sAv07K2b6oGUMP724
+9JUSz3Xrl7sfowoYanq7jzBrj3az0ABUxpuFCtnHtmsrZiailQ3+PloiVe4U6Ki9o8SFJqZ8zed
Z4BeRDyqktJiWHU/aDA/x4GpubJzHDf0mhB5IRJGpVoNU/JCK/UpRG0O5UImYRvTcxPveyDXqUv/
1+JeNuv2Jrk+w1JuDBuN4H0eAvoQzoL75jhH9JhZNbiHfaL5ZZIR/4zJfsVJLyrQhhAAROeJij3r
2DuQZhm7YfYUAUGg/EfhkcOREEcDv27HOpByLEb2IA4B7XiKtjqmuMAFt+1sj6tlZRhfljYnaywH
VgkEuEdH79DgcP4CP28DDmxheGZ1+fr2Z4EJUl/YtCgkgIP+mgJ6ZvbinidjDL+xA5yGzgVAteLx
utkP5gkpWULnaYQQeJMldu31/eJIuBiNM0poL9mMoE4KQOHDoFPksyiUXwVlwj/Xcr1IuWvW7noX
yI9+XS6igBSgL+UHTIPmgaaDyKWXlwAWip916zusyMCli+IaYQHrFGKavM7AvfwI8i2T1pud218e
wvg7nSF7S8n2EYTSUNwyo0KytAUDJQwocXbggub7d3P2Yg+gqh10UaRGWHAc1/0KPSQw6U35Zyaj
qXFAWUWOs+rFh6trugYqJr03ONqcg6OEKEWA2RKKloRqAiICqf4jbm+GMIvCDjVKFqG7aILKbNg/
OpBsVJgQU6MIsUboj4z1SwAI0KPM16QSenyBwaOaQqOKM9KGHSMR87/sgZG912gAb5/6wtUjT8+6
sMjw1jQQrvUpnzQdS4QOWh8eJRIwRCh/LrWe6iSftdTFedghn5ByeGef6as4ulB2kOqTAoOk2IWc
ctq+IcfVOal1fgdXaWBvzARtfozNN8xKPmHTNffgNgkarHckzr6mGtRDHdxIJ0jFqszPzQSrMIZz
VDR33zH4u9jqhepFuUxNAfzEnh1p11fhq88O8d2QbYp3Pp4RykJ3eLwrfhxGf2iH6x8OSyfM09KJ
FLTpTMKfXAJIHdJiG6G/NdyegkgYyv7MVFZQde+Jr4OnNrlLr1DZrQsFrTyU0bLQQH2rqmsJwxTN
QcwzbAo70lMEpQPMcKXG0EyBPDaHWqvLvorUgJVqTo45LssR0gDKso3nq/TGMMfzJGgPioH6B5Ng
aJqztlbWyMsMeF9OqL4vXFpXciScWt0Z6MehDFOcq77n5UcEZh6vB3vI98I0V1zet8L6MnCatN31
t4egLlGhvMvZ/ImEnF1SSJPzAGUB/lQzTZeLgRIrNHDIXkWgcTM+W9ZfOM2szpP2S1eQh55PSmaP
nq7kkBgyFlNgqHUQ0H/v/KLpvshBNdfHmTIIUSKvujKiTkgH4xPx1KDeTNozqcDIXF0dSVEro6zS
T0Ok/T4EF8L0pkboGV4X9hPD91Z1j2CLqy5OE7r1IrK40TANQ6LY3kOfg3BEsLdLEbsQP07HI2JS
DBCfgEGnuHjqHhP0U7DPFVGFbh5iDCF5BNLoC2nSFr6Qpf5SvLjxS12D4Np7gbbvAGJOWdi8eKOu
RoA92KogDlzIfw72LltHkNoxqWn46RaYvO4buhXbNxDQK1637BlLSTcUUw0wHrlSRR6e8hGziBtB
b5RMXvbPZCC+FqXUzqTdzAgFVv+CrF1k3HpmwK3pRozm9jAtXvOGubQeH3QWvluMYwpbl2y9jagH
9xAIITNwk7GNSkiTSlOfuBRS9VHUBYYJdSsyfmfgyLZeopmZnNRUFFZ94bvxqjfyGnYFJjkYidnw
SvURhplLgss3fPGvacXrA575xGyL8nBQsAWiuhDpTACK4R8+mPytWUoQIR35A6njtKCoWlDARDUg
TAIDvPDb1wnCRQIBY1kJshRpMgaEuOp++4lDxl9ARaDdMsw10rOwSy6VVrRUfjZOQvDRVvUGsc8o
wua+qL0G5KumXRakVs4XJJastaLhGV6h9hsm+u6Bb1SD6R4PXcjXKq7Fq2ya8CvlM67NTKpoRjRn
YAX8xV/p4KAVVzn4vVJnMd28ODHhnNZgx2itvJ2p7oRUwhStOBWC7u/XBO0xjLD1iUT/XUppDCk7
oallV3QFgy4PJkFFvZhZUimetdcM/Y7RarGa/HblQIdzn6CwvEEFrIYD+RP/BBQwWm0QnFF36IeR
vSQL1dMaYN1AOn3ALyz4MqXCPvKL1dIxfRrZJyoFeiy7NTXU3UZFi+fkZ9ppuNJ3XJ/UX0+X7GC8
DXI4hIH4KYvhywiAGcx65/hi/vqKT3KqV/rVG+gUXohX1VOfPkdAW2jwcGLiXiIcLMZdkY+qkTVc
/aGf4x0z10ukjVCyxEC+SjWuXoBgMNSY60fVF5fB8+6fQNKl8KhRS2fDqJD1QAC1XxiSy16J2qSL
B3Qbvw4GavfB/uVNWlgl9viCo7GZnTNTn4t0L6g42x7+GwItTZBck+y3Jsty6g61xKBOzUHclVTE
+x9n7Tg9QaXGRx2dHQJUiAFmi/q8+eY0+Koj4t80E0y5xVFFoCTab6X6PixClZL2ZJ5Up0hIuB4l
+61r/nxYR3xONDwmvhmgohN774j/H2MY+UBU43Div/y7/OrA4RWQG1zxmRsKsJS20lRVw/hTY9kR
pnquB1l0AuThwctvkKAQTSUFsOLh8+wD//LFR3yFSE1lHU9pHCU7oO2axK5KdHtx6B8ALDidnNRm
OUuW7mC1MyzmMEXuPw8zpJkP0WtDFJgiHFy6Gey9Iu7QOpIZSWT2GRGnnq5lnNGSEdjoCSEl9D6V
UzyyIR6JNEVqOckF+Jc4WIR3QdhhAShXzvXaYZdkgdga+Z400kkwxqnA4bhagjiaeGkB2jrAy2RJ
/RK29pVxjSQ1xwQWDpVV87g9KgUi1b9birgZgexXUvsFR/mo8FgwOL8s6IXnHmne46ohMkalbyZT
ltlV8nGr88O2VIAfD1E0UsAy/WeAO+Tpmd4bdAcoPVpYPPMh4EDMasriNC5pIVsvTzMpqeaWNa9I
uOmf1zCyahf3x9egGV5C3YX/jKw2Bj5hx/eey0F/Xc3AbWaet4b1L71F6wN4mbKI/gxlRtEQyTOR
C9gEtmtIHF1PC6PX3EHjCSl+B6oGSw6vs4PLciVnSlGSGwybrAdF5/Wku+T2mvRrkaAVwfgD9hry
eOXoC4C49DHy/O3D5/hMF3lHtoijABB0u0mP8r8+GWbsEf5xrwrTeWsNGOES3FG/NJF7IhjhBEnD
OYL3uWr1a4tvxDgirTdwb4HuTgf6ZPMHNuRYPldtMgnklkQpfd5HoINqRMZ0teew3KIWRgP1TKl7
vpoHVtI8/c/VKvEfVeyztocEEdhHJCkNzxxwkHve8CGKpywn3aHKLKemggKkIstV89sNrNti0CGM
vZBOwnBoTyjGQRTfwBoQJdgmLQtzvdRBldGu/H9R7f2iyjhvvsYtCk0uBRHDK7Wt6/1DWCHXQoA5
P/C0ExAy62Q6eUHR48hmDbWdqsrcxIIhPxgnIHxntSXH57GWmr37/nHYmnm98FsU3/Mpx5H2Z807
3p2LOE4O6LqFda2TyiLscpWQeJmQ/w7iazzUSK3HMW8XsyPWpAiHhHUyDIYPYfCwVy7TB4urUMFW
KnmqBKEj0/Nzd7O/lJcpm6wCrxAthXgcGf9t5tgS6o1UegxNlPWnX0SezyYfpvkQKGRIkBYX6Lmf
P7RpqmYBqkuFp3ipgqPu5Xkuc65BMxnUdt+UaXOHHv9xs7rgJ4/xzNqe3xMpfPmgQQuvmPzQhrV+
3aocbx+1z54eZtk6G+DzNwFQ7XErwSxlwuKM+LfZu3qriuwUW3siI1tV9gWDFq4eys2joB3RhuOb
MPGVoEVmE/9M1PM5gUSm4rrJsdQpkPkSOuMYUWZDVWk7zQebmsfULlf5hgHR+VC1AqEfzSuZTDcr
E+5+AHpmuMIOCSTxO1E5zMRxF2yFSnG73pIh4O80TErxy7rFo0L77tz9URaA2D6GJ/H3FAVdWb9w
NFiSc1gJpHRA45Bf9/tE9i7LUnFleBHQjHBq9lQ36D2zrVRzeP+J+Bl7AbPNGmAAmWMBPbbY61Yz
7vOujrWRpzcDC8gTkFShRABrXC2uyto7jBZZvf/OOYSNdMvBLP+xRrw/X7qYOhbIi0hyy9q7kbSI
OUraiBJEC8fpiTDG5b899IJEPhxyj6JufAbfqovWxwJB7uX+IPYnhD3YAAe2Hf39+oZ8Mv5ON8SB
v4ngnVqXTE9hcPkMzLVMw1GVpHF4WWHcHt48iTOIEyg+b/YC4pwZazReZw/8dTyDV1JGwlJdA1M4
gBfDj1yqaWjn8qNwJsP2ntvbUgBga1YGFDd6gfJmT73pUpcaZKaVVK89knsvd/0BzM0YjVNqpjO5
iVl/wXnEsnrcvD/gSNhMlLRcjlZgD9b10TJqE5emQyZD1nNu+xtn5ojUKK8qLJ7/DsuTHgF7w5lu
IPsO9i38q7+voDpQvBIP/e2YEU+VtakCzHov59EHDG4s5RJAlZbjf58fyFlnxJ+RH3jJRH+W/HVK
Og6CWUQCX0wFQTysln/PeHayArCsaYngklputBHwwGOwWpn4xCuvdWB3VPvFLWV1e2USQO7bzpmm
BRpWCt1vCZUucADWxgVW67/cFlb4lSg/qn+szEx/H2l1AyHPACL7ctevy+kWuhkXNovd23YKg4r2
HSifJ/iZgcw7hrz4mZRWgoCoK3z0vZwlFL/aZ/3Vlu2unjKm8mwIN5xn5WAieIQs+uMDWjgiJ7Xm
cs9eZLGmBqFSc51TxPmAUCmQIhUQk+K1265ESI+9+bSDAiQPHUbBg2iqyUriJDO9fa157cGE+XJp
eq4jadghG/ziiNQAARHe1k16UW/reUbl8clRT1tFNdIosm98v1isklBkTaNzWrIMBARnPjY32kWK
4HKDgSgu6BF9KI1saRMDhsBNa9e4UnOJ0C4Ee32+oIy+dLhXusYsN8uUDjgT6kN8I2Vo0qcfI1Ci
5rY7ZWEVEl8Gz7jnt73CZpm/t9MBMPydN94N8QtfFYPYZLfBWeKXBwJ34/6ACWPxzYH+ZnNitQtD
J9vl4rKHD0YAaEgAPjJIGXXBTGZ5GcSznyLa0+7pk2Vki01TfUWKbSB9kcPK4uCo7r09PhOaAXOl
rO3kNCgYNPn3+aAlPlzTwnmmI8AxtXlKBYnBYKDh9aZywXfbxr2i8BIgnUG3IpIwTMFisjkV9t/e
jmQYHb8FwBwvHNrJk99Mvo0KYfOP1wmQ/TOtXQ44OaHkaasPelq08gR5JkOiXFKwomuF9gAHN3EI
gbTH+caA+Okf4ttcocjEul8K4eGU4TkrfhG1PNnjwwvDTAISRZ69uLxqIAYiROTkC5q1SHwh+hJ8
NKrcKhZe1Y5HkmHhu/KM+W9pLfCNWNmF9sy02BI2IGOTtZhH2qbQPD0n2L8T+m3s7CXpMF/ooXe1
7U/Reva3XhvpSvVHQXS+WH09cdKQ6se81lEd6QCoPf+9yZ/gfpsTnfgblyPboIYgsmbYhBvYK07+
sFdxADiUyBUgCYp5lwdY96xOSJF6WH6OqVua6Cvj6HqkrGn/HFOjXFN1gJZ3yCGPyHTCRUbdDfm1
qrkGMoJUVFEKWT+lJHyQupmHQWmh5DlZwmcNUw0mK3IuPp7je9TTlAR6q+Ln3K/dnjAnC8B/v/LG
pkHNqkQ7Mw6UtMUXEvQ9UP9n8CoPj70dxKGocBOFDrV+X1BWNdtVW9CP4/4boUIbZtwRhKCDvHw0
tjgV31WPlafkbLWOVc4jBrX072psmhwykvnIG5jmJPpYZo/LuBPpYpzK6YJjdSm38h6EAUn1m0aE
RitOht9mvkFY8UNbw3QcL9ExJDPSgEfDm0/M/gtyhndusDX+JL9o/KDgdqFsHamO8LLSkN7LhXl/
9+awa5kBbYr4/I3QIkry/QEnj9bMPBI89/ZPufwaMapfngswutonsYXrx5iloJvp1P5ZwK3uf5sq
9jahDuReg0YzYrDb9N6JY+YzTGySbQRECuFjBDbCOwn965A2QLDbQ1GPyDcdLpsZeWBNcbnJ8v+R
PPZSrHD8TRS+FeqfqYM3Zav81Q39qW4xa9emvqJLXAPXqi3r9CccuyiqX5ldQjLaKGTq+naZ4UBH
Lw4XTM4wwifi4B/p+lQhzF5Ghu8JtXDyNNfR3UyjOMS9ZxmDx1MKZH7Y1uhFrBQHEcU8w/dLkGjj
fsLap3iVIGa7BntMAYvVwRSGwyV6KIaF3RrgmVhP3aIa2LQhIDENCDXRYG3ebMwqSNkWOAcObrrW
aZ4dyzawhFcJ6G2bYgZ8/dqjPPuQSsX/FLcyPv90+hY77Eb4+eMwFdXhtDDy/j6DLRdkYMIL1HPq
AOtcCL2Zmb3R8fA+i0VhBSK4ZfAy7uoBihMgwirEXpAbWf9jED1imposLkBJMit+LpEwTa3shwUX
I0zW1Bzi9T5ZegnWD0T+8IqZSrKYCnMpqF9nzpFKoQb9uSJ4JnQLupHl5UFQLxlCF2cAn3YuWx0H
yKCenyLHn1YgHyn+3PkzdQV2U/NVoGHZRrjBD9cbnlwlfXIbglK0/WZ7LKBeZfWbNLMeXCguXfRO
xx4l8XjDUlsEPB04V5inLVRVT1poR2CnMhFUNW6kLi+hubvNzHOvC+Rs4fERalegyBh+V7vXpo0Q
CnACkHQVi3NBz+6KQPZIJQ3VKnclbGlKE7uz66Kicgc0bT8ckud9jIeU3FFJvz7FSXG/lO1kHi/9
be/0vy8vfXqfOKwZcz2WTESvacr0pWmKh0OzskE5QSarw/E01Qxmp7g7iwFr+EjZ9Vdeiu0og/I1
klX6FUq4m3n38aLKK5HQQOA6SvyJELN+WX6huGCzkzcy7ZAhKbvxOEmhncUQpMd5UB5fLZMfzVbr
PUcigS907UCiFwMLuW5SPhaV9AeYEhIeM2aQYkdn97u4dG3MEzSMpEE/b+pMmaImAMneVMwOMXaA
97bFyKEvGXTrJqUPVUKAP+ZJMA8EsGCXNRftT/66Dx1MqPfM1txAsc3HTYPKY0EQomnZvacxfm4T
Y0zb/0yO5kyiwfPc9T+TkVfyrWimOS6hFYZYPYNBpgQelS/QF50mFHYKzLuoyRZZfi5zNLKZ2DxX
roBSthdxMh2a2qaKTFyq7a2iR/OuI41g3tD6zOmQJ8qvMdwNhcluUEkZDO/Gpa7zB2gE/ORDwtMZ
Hy9oJ8LaJqZEVGsVF8rBYVYHwo+7n4+ojePmPtdEWWJEVM4RNvYsYJv99KYkVdlrVD9akk04yvgA
2mQnTh6P0KogLd17f/mKOpOT9E/yOK4pLHY7oxNHTNtSlcLLs1QxEqKB6nphAGrYrv3ZXgv6PJ8f
Y21R5LBV+dEDg6NGEiDSbY1mNSajNBWTSpRncmYnkZ9UGQq0iL1iPAq6LRlqCMtpx+z7mHWTLV54
v7mFcKZtF6PGE/XaGdCrQcQ7mz8KdmaEtyEEINFBLakx8XoHrsi+m7euWYjzzLiD6DjFjyJJ4ZHY
w1lhhNvm8AQrEIBcAqdF+oNNfvLzolq59xRUUCe36/itYXIWaFssI4zDvwtq1YM2reV7+YY26MRH
B/suRE8AM7v6tCgZMfN1OXaQI5i8As+HP5aq4KUkHPtQt0wCE+DPhw1y81LrDZrxvJ8T6zlRwqYH
S0D5NjaWZ2sYwkd5PyeTlDQAICheVP4VgdolJD06YtwnOqW6AeRrytO7VVpasHmkcZTamN2i7vUW
ELDMIdCIhGnZsTJamhogl4pthdF6Cp7VkOkG3qrw54kgm2p3GDKs/1k1aEMPKhRN/lNuCtcX2MCd
nCOfqNNhJECdX7RZXnZdr4psncgdZK5Vz40fD0uIoA3x44hKn/cyPjMaGT6t1nxuBO8i8a8IpDUe
7CqrEoXY80HEIu4zKZnzbIjKW1vkxjsLPU+Lm7B0NXGhNWZmIFdBuvh3y03+/Tx9Ou2G9IUrCYf7
GsPetQR/I1eibJULPXablbzwnVXng19ZGDRsPxHCts17ZUpZlUTVdw31BILAvn1RtKCKt2RsnwqA
m/UOeVVKZkejLUKn/ATcP+y0aZ3TUAiMIsHzoejLBbiYRAaaYZQVVt8GOnW42m4AHgMIsw4ZzUbq
y21s4m9a1dJ90mh0/HIQSpihl9lfgO/LQZqIZhiNAUEsGuQE32TBNpeLLFalFZLEDy85MvBIWEIL
8jhyWJ3gerpqhwJXrmny47ZXyXbRct4ompNqaatlNmR5ZWvOwGp4D1dMxRSd+CfpL1F+b2qzgU0q
d0sp0w5pXUnu75+coOp8iM32wyRz7sjCVWSkvUPdCjtTtCRmNTnar9d9H3aDZ0KbkMuFwoOmr9zH
bVX5IWCvJtCYgtUXEPmbBmmajJLFf/sqij7LL3HP/8eSO0VDju3TEOaq70bhL2gqD3AthRL8DFRq
zHIbGDW+gdtbbeVt/+UZ1yRPpttkaWDuOLViSF/vRRs/+D4dFbzS1F6COKTgeuPqoUgQ3M3RlQK1
7BWhihZQCWzgUKv1TGTZa9yycw7LvRo4O85ghYzKR+JzBxc5he+jpkCSOjE4grvc7Rs6MHqwm3L3
iAfud8473Y3oX91dwqY09QAMWs8kRpNN3+myOyambIsGzG+I+23iKI1vhHxTvzNy3E8ziDxzJqZ9
8KChY9rjwoQrh4+tmXTr37h4r3acVZflbKpdWEiThrV82PcrHAG29CoLknT/End9t5H/pzdAi3+n
EW7keU85CTWuS5nlZmSv6Is76qFKxYipW7BaJGaeT1AJaEbXg1KLmLeWLOK41c0B6mVpHg7YNfAc
VhKHcbmkIwJRQbIPsQTzocjW6Su/0hFBEmzmzsuSR30aa5qrnFZ8ofeq//gjBRAbj10gaTC3AovI
jzRKO7mbc8hMd25FBkbt18f0ygiNoURbQEiNfsqDsrErmUD3K0Dh1jS3CbiEsWTy6Fh+OoBRbXAb
0cK+QDb6B1Rf9kW2b5RJmwi9OSWcmQERXSaOsa/8aAbte+kMQwadZq54rgQPHqp2SI0o8pLUs/YD
7LWInV9CERIGkZoSEFYtRBSFLosTvmRZuGnuQquMGqBsGOfUSnZAhyufE57naUipFDcCRCp6iX9t
hjDhhNjp8fe23uXtEZ/n3MxcMW0KljYqlzewHvvHlpCI1XBJeko2k3Cs81OWBEydnigt09VLS16t
CQCz+sNA+gf+NTv24cIhK7e2VqlHSIdeKomUmD45TGfV7FHG7apPk4CtF7xtdB8BPMBskUmzdgGq
50Ti0tkJj2Bms9/neLvlWt2V0HHK4BSJUXUKvb2Le2fAp29GUqNPZG8V8AzCah488aF90qPvlUKB
UvES1D/wFnMt0z6pNVzStWLKzScEPTfOopdteFw/p8UJBsBClLitL0iEEWRqfINA4qVEH2U2JDLG
Mievd8lj4blT4HRRocV+9iw6nvpRd/kutHm/AVZPhxa1N1LmXBkOl8UJuyUfzxdNMa3f4mS4ZXQK
R8O6/UMwFtBQUeZ0+PwpwVv2Dfpw2vnmbYJFVY459+d7dCPeNZmRr+Ftz75owcGY/diV/duqrWz8
9aDv8wH9Lrky+3f1HNbQJ+cZbw6b2iCSejt7046dpsk8mDHg6vYc7GHViq04z/bbp2M5S5UqYKOY
Nzu+dKbnGT40n3DlcBh5qNSRzQ6VYVae7wx7m2ljbTyOU4tEYZOYFwn3tL06AxlHNFKgU86A9aqE
wsc2f0zLKJ93eik0bRg3Ur1jNN7yV4JYWLjYvVGADV8fnrNkxi73T/CkOfS+YBgXK6LIY/cuY0U6
lmoe3Z+ctuCmlrJqZXFaA/6BZhSyuEJ9tcaCCH53hJdf7xCgtFzvZS8eNVhBkID9rA7Jk7MyD6wo
GgDQo1ptqFJgwSmiujAINOx+7kT+IZbwn0i+SZuB9Wz/EUL29wxw0CBzdynOrdi1v5NvK7htBpR1
hQPfG8LN1YUnV5d2urgDbk7pdQGjABq4P1JzPiG2SfnzVhDTzEn1T4rfXqU7drV/8we+OMOXhGXy
o82SV87muF1XUeRTVlgnTAyytCjTivvGu2hr6rB1JXGQoPa+o2G335CtIS4Ly7q7nWYsJEc7OmPO
9b6eGUKkuNn4JYWpZoKtKA+QCdgLGyjrFTMu/AXhALEJyAg3hKxI/p26Ih+o8C/20/i3xaAC+yEa
EgfMJHlevotWz0Dpe8fEfnu2gR207Un4aecQXE0P31t72wbVxO1zrqJX8OCD7OhNYXUvA9W1If0p
NkrlwJFZb46Kf83TsCTck6ea/vW8RNusMTq6Y9cb0jYCa/ciNTwZEmOyEVBU6mDM9NNX3rFy11/J
fPylUPoAaJT8R37CXaN+csNRyiGC8RLhHIK8bn2jArfGiBFt2BNPVh8raVk3VydEZ3ajJsi2w5r3
7YtecFO5VZrJCd5qt2WfzTX6Zyvhl6oY53qmhxIB7j939GV6jVQjEpn22YxgCd5qdtj9YaKq7Tc9
eT35r8pIw3yekOvCNsf7vb+DLZbJJlWUAwrB3SwVU2TZ4dWssAugevwk69504SEir3jYpp35pf90
PtgTO6UUDcg6PKwMtWjw8ifzl5gDvuq4c7vMYSm/w0Y8x9fSsOxsLkPOSk72cSNgdKgd1ECeGRnE
QxzxINk5AgmD25gXvcdnkpG+MW1N37g7YWAsqhUtg1inHbvBt7N0y7Kw4sQW05osIKsRueEnDO2P
7Vwg9E9Zs3JRoxMeUAdcWRZctk782flvj9hqTlElhxBnktMRn4KnvEjxc8K5Ta5X4yXemMZtK8ZK
DP0Y7UXfrOeJtBkgRBPQMa4vKJpaiMqnS77aANFaZapWa1+Aa7h66bPOj1XsF94dJTUWUeY8FDFJ
zDVZBDfKlLyeH4nYm2HRwOBKrBtbwHrHQrJK7g33YCd1fnh06XgrMZTzUR5JnFsg5A+Yom46UivU
MvmFQG/enY1z2uJP1mWKWXF/XhWgxOyj2H5pBMdHXpXR0Cx1QRSS13IlmJ9o32Tqhxy6/HOMJP2W
RUNR75a48YlZT6OIZHF4V/iVKVmxMpi9HtsRIlI+uXEi15JflkA6jkV8YsA9+PDeBB2epDVNWhWB
h/AgGIDy/RyM4AZBAUDLF7qLRx53c2HmgGaL5L9Nsp08XwUWbsdGSwRsMuj5IdfTCPj1qFo6DEpw
06PYX5GUyBxws73ML0Nv+8kcOgP4tojq1L8p4gn6az/IW9+PW9vJnnPucA1tu6t2XYSvp5gyLXn3
6OzlsjaTSXErsLJoiqZ2X4GBczWR56OvbQm+L9vOV/SL6rcqhaXhg/5vp9VdPXMioC+D2kCiGXl3
Uw1Zx5cPqC8Fdia6rKrM1ve95RaZJ1jnI1uGUbHdXiOeAmmuy3Rsx65mt5Cdawsj8WN+Rw47VGYP
5V9VuWmv+5BimI4KTCJ9vnV7ue7d6t96za3EwzEeEzEGSajj7ciaf9ch3/KIdxZ1S0wrAcbaTnhI
D1dpi1WrmmisfK1W/2ybTJlQyXhyN0hTcjRS0yVivRxlaBR5XL4X4H6XaXyhzVpJhgVYc7KMTyUL
tI/cXMA6DEaCAgtxbASBPrbyh9+74lMfWGrjZ0T9XTFOqpsbOkEYLf7DrKcHUFBmh+HkLmqVIP+/
8fLrYYRZLpkjdxvF/9O5art80PHdV1ybi1u+PwZgCiYC9bWEQmkWRCi/rYbkrIg4xjleNXy+Cb6M
sAMVyS93XeS0/sMw8un6pVsRnvULYQYsvf3rmO/QhX+6iUldBCva42Ze6etdqAL1sNLNaHiC5iKH
rAMs9mqrVaOuy1tQON4EdKjfJ5sgKc8bqlSAL/p3FoNI1BZorqEc2LnTbaq2kYc1/Snm5ul2e2Sv
seEhnlEKarjhCzN9HbNJvuu+3545qZXy8+Lrv7GY05zRs1O/2rh5ez9tSNuyJuEBVJaPlK+5lXdW
BMl+ctoiPriw9bjrIwnVvtvNFTM9bdYrgLZt+d6//CENPwLqBgVo0hZmIGDEWiC/EtIx8HnhqfqL
VkpnQ2mabYRhZgut7qAU2eH742ygtnW+iRGpi2Cev/xdr40XNwXp/hwOSJMZqqU96CAG3oD0fKdw
S2mDtgA4hK50g2s3Bv+rioDilmnF9NSlVs1rP1LI2kFolUUEY2/UpaY8fQt+yK+suVgvC/7Oml1V
YwWDJLRppIOabzBQmsF5TXbO0u7YxdxKVVIRiIgS1gOs213rWG0gddUxrRBEfkb2OrtVUtjesSzj
eI0NsRZgcgo1pnrXzALmzLEhvdIXUgDN5oBa2WXPc0n3nIRSeBkrkuOov2L4nk9WjzfvjCdgkGQ6
JYk/cdQouzxPlJ84zJA2y/kbAtrHo8LBK61rKbf3b8SFGWVuOuLGe+Wk40Ph5LLO3M4/NLuw4IhB
J2J6Cgb7QCmLqiV9TDMJFfMCoUvrA9FPxwFjO3qELU7nvltAlom6UgUuPF7yzvybhi4Frvizu8By
iowiZmaD9wV/xow7PmjbDt/Yk+h7fXftNeNHksGOpleWl1+xezI+FxXubKvFH1NKHmdDYcrWpxlo
EqM+Ez2c0lDaZtPDO1B2IZRkjeKF31CVu92cFdVmucTlnu8jViJ1sMIKbvJYcaTB1Lxitd86bzRk
cVV0o/Deqm90HYyGSAJf6XRlwper+o6u11u3HIfch06DZYB3ztxlkOtAko6WtgBztJ+kkyvZEAWB
DqLRYU0vLKIt7HvaNPGtWa/VYwVZUywm7h/igbbex/KEwfZhwALTFFF2jsTGc3AP1j+MnH84nrPk
zmpyKs+Zpsp+Mu/kJ2KFOtxvlmPYNK6WXH8kiSG/vSLXKD17U4jLxwltwB7IizWAWDsAk/Ctpb0m
qcIIXfUxqjTeQek6MSb3B9ODGX8aUilKPldViLeHPGAkhPHdf3x9a6Ja7wNpi11zyJaMKUKpkDVr
XDREo1hew+AahDMeLgX3p5kPYENuMksH5nBVrfYkSlwYdE9KrKpXyYnOgnJK4OzZ9o1gEFVEvnh6
FFlmZ5xzueE4+UICUzmuWoiDAEZrGSuyJ41ocfcgJFTpPQLtqXTPybPkwAwXBSpmS+8itApns+5J
1wwR2CF3h+tTrgXvpn8GY2AihTVhJxhrasekZC7JyqyalOtxOoxdrnm3RIS8N0hu/Ow3AP1rw8Zg
hOma9XkVWvRtl88UCYf/o0SrhTtaibaT4RK7G6FHp33DOTsaJZixjUwYifSkDApnitqVnqlsMJ7U
uDnjoevUYPjDcosmQiZW5846NylAb8+1bqo029xPCakhPOmI3Sjcn061iu4pRGPuD2Q0U1kD6Lo5
kfB0jcnJfoZqv36OO0aYt9nxLX/zKIWXNHCJPYBXRm8z+FDsSUCr/eth5ANwyuny3mCScv1rjM4G
5MCJyA1XuDlhl/RXTUYQDeKWN9k1EFrGtmfcBrSPMddfYWTfRrxuC5r7RpOSVg6iny4euymFmjai
iOYbkn0I6cSz6JWSwFMUkla1O72rqwHFIXHBNREM3EI4Ou9bT0/WKJg0ALAIr+ilwfAgoDU/GOQa
3GnZBN7VMxpQnwFc1EMDAaKG9BG+ZgzB11tNRRkhVXAUjhguUDBePUGlln+1T7d+L1yS35OBqKzP
OReZRdg0L+RnPLVW4Z7vCn0I10gKdFu3MYUbLHSOCRUHCWeONAOt+4uiB09y7gD28pQ4qOm17aVf
+vdixvdn5ql9VGq3O2sxKzkWdkC25dG9hzL8GziWFfNcGchpXooCzdX0p5HOtAmFl2N5VpkiJz8T
UfNELMAltMq+gWsBkVX04N8LvyFWpXdNpI4XY36mMBg6cQJqeUiuNF9nZOQ4MnzKE8wEsptzqjr+
HJAxSt+2qCuZs9lzgi77UEkJ5mTs3nQF8wH35cLL/mJCv5+y10cFwgjW4G9n2dUhX2010bWNLwZ1
shBfA6FK2nCa+rl7+PW9JlcWcqLMtpKDxxcubVuHdX/s1rUbBM1q1SdQwMGAyza5/fxq259X3Lsx
2LCA/VK/GJ8C0IhzAse2hKl7DjUj3DvSd2kNBGTsqmyB0AJKjZQYGvwz3Pwy9rWARjiLnHdJNNpG
Fo41m8E9RLFP/sMttFQPPPuJMD0YJ2LvgJwKu9C5/s2uBCOTNO2rdZxgtXdoik6svcl10lS8rtda
A8T1xSapWyEKYM8U7aLmmnFukHCXQjNAssVJpELGAicsqZcTg0QWaWsu9jq2Ct9pZBU7oEdjJ1nh
7HeQHAU/tXXtdrklEAxnbRQmNiIw51P0cZa9al7tlzjdQOM7Anf6KQ7bQVV/xreNQRAYsAQ6uPr5
lGHP8lEiOINlOgmbUnXUfoJ2f+4ysENjTLT7blrN2aqYVf86ZPLfwK/n1Yp6bmBncJ+8HgmHF1F8
7LoPYW0Cjg6KCzJ49ACcoqYjLtc0cBhegJBktO3ViNk1v+YAxL4eygInBFSBIRRlsXjQogM6Sksd
VO5DsWPZ1qtbWeSZdBS5RfYcmMCYmNeG2kQ6HXGPjd8mPrOFlbAfBBDfyBQDm5vWhjlzZ7WDUuxe
PyrtncAzX3ZF9xBPpLyax9usKWPa0L5VvRrBJphutS2fX4caK+XNjMRaPxlb1SqgoNsoTvuicEt5
Pca0qWnv9uuTzHw3H6XiI7lsZIe55pN8N00aeMb8p+zjyFQLhd9TrJJmHDkvGyNiKi+cyx6LHpkt
nye/jPkeGn9CLiEPXkH+YNs4i+zOgz6DT7Fjpp24pGq+LgHiZrqaDGKkwLHiOrYVZ3MTelpTAGhq
rqd6Kdy+V+DQJy+FDvbNPK/z4Nda6CVACy1JygLaLvT1SWUFEkyTWcJW7aTBSQkyPGWJgikJYh+M
EoIRq7RdGLFZQaoZWQCouCKXn30rv08PcpWhkcziCXVT8xlQLDvnWAlbfIDswG8EYfXzWrK4pFae
N9zkb5OmXyp2Dd/4BEVZWrwkgv5roznj7vWeVRAxkp9COa77VvCHKxnmEtsjwAcB2pCpea9a5Dvd
bHNbWYMRaWItP7WXB1mg8MatlkVdMnTLGWELuDs+fEfgVRSHpZOYq2GeKQtSnytQi7bUSm4ATcUM
7mSmOsTDQpAoVc/XmpUWRCcMrP4/ta8jAgThH3JWTMdhJdWp0QikJYtbxAmUqkL3ASY2gZGDx+yz
/4svYTTUoWg2/n+hH90WWfuauA5wn1a0009dyDw/gBuFvBriHmfLTQMlqkUtcg6FXrWDy9RScQyh
zuU4olF51hDQYaTP2bP1Zekci6+8S9oLpwWJ6HC2eFakpkbRqItZZGapAkDJGTkruyg9M5/U38ek
xG7ly8pUQzCxwNyea2o/1JKLpDhuyey+w9G6hjEAn0DadXB+Lad/cWARsKLaW45QoZJ6PHYPJW8C
sc7rrbqpWbJFraBMQ+x62nh7ZdqxE4Xk9oQIjoF9SMIR9YbJRDHMM9TvVnIBQR8y5tl04WDPJd/G
k3uvMFOjsYwf9ihmXQtpXDqU4T8MH1zUpvrCzJFXBnXsm7czP3TU5BwvL5g90HiFwyMBq/1yQ8zV
IyMf9TfVdPVL978ZjANG2/hJF9qWp0i254EEzfigOOCKxOpesHFn6sG/bu7e8ANC8UWSyVC+CrjE
O64jvJcmIRM3uKZcsN1/BScpaW/KRi/Y7vQmYgXPLb7Bbc8IhCyZW+cgbwuw79Lzx1dJOL2IJgIA
BbGaBTOtLD+DM2naJBuya7hb3toIlOHCD3OqxS2CA/wBOxaeVzA0p5PKoVsSjfcMKIPv1dwLkMKX
7U46YAL/WiQHU7A/R6YA0BvF+yC7GnpCBRDYWOr33XJ2SQF4hfc4mIEmLGCT6dixZns96EkQ3ZBH
45t5p2RQVdqd76TYv5KdlHWGnsCRsQhwT4jQ9EBgup70V4dl1dLfwg8jtLqOV5alzV7CHJqTMiAm
MRwOlBPx+G0adl56j3FnMID/22NGKpMNzvOLnvoi9hqnNPgpaxCtTEGKp0pjhGjup28IKWAKy3HV
rwPgZ2M6p+miOew4h5uefc/JjfWmj2GpN1yGk5cGDWbqPybbFZm10B7lwL9UewjzyZ22zRVXO7k8
o9MZUhYKCXC/iFhdUPJV0OudmoWbHSt9T6d/BqP2WCH5ACDjlFpX3psM5kYggyN+hdPiizmKKaOR
NUcaL4TkI66IH2OsHfx3+jCqVGKKdf3B+QwNE3mnehae17bIloR56MROurE/kBq6KGVjQ1fvsaYK
43pZKamPIv2xTu6wBzefmaIygw/M7wC0fewru/BY4WEQHanAV2hbt7isiH33ciMZnpz3E7eS35BK
B897VO+uNpQuX6Sfvi6tCjoFn0QHfR7pRBe6PLZcJrtfHyJ913LGT83GM4WYbC2IZ0nZgdX8UNEB
ZQe3np3oS/A+R8ZJodJgqP/tnDMwfstk/6P9MBeHs+gQYPub75Pzk2KbiRXSPYmZ+72ZA/TNpJcg
qfxf5UxEGqkXeaMdwkzcIftk2cdw+f/we1xIphKgHHkOkTRfH6hiYAiBZYPPSEy6MUJFpHT75Qhu
YOUq94Q4yydC4GEdicQse1LGYz3f36pqtkFzLmKbT2dD4pp/00LFQe6I7L6GUSkpGS+s9abKzJlE
WBsca7MzqZY6vJ5lHq990C0bNH1z6baHihQ1X8Ns/4zTS+yW9QOUhkPwbmii//CXrxJP7lGQGQlZ
wOu8v5J9USxIm25GU9TvJr8kRi0O5O0uQDEuJuh0bAsce8oJn+sa6odlR0uCMv4mjLAhIJWI73YJ
I3WEXyq5Oiy68SbUWEzcIytRQeKJgOJFb+95WvLlqSbozyqLRhb3EjLnDNE0GJhlptNKWs9x1XuY
hRLuI5zUqSq18hO5XPMyPLf+gW2xbUvyjUG5jn0zNIiS+pd8D/SU4Kq8FCTejfgqU8R03DPg2UQU
0OyMtt9gzNaq/UBVmHNapPKJBeSujlC+nU3dezLNtH/k0RFwaRtuXcKeYRvvFN/hGmWDWP0Qr0PM
LAp2kQ1NOgkStJxiTMnaryXDXdawfgtL648aopeHE8Qug9eWmCWVesSXl8qoHzelo+axnNwIhGlZ
ZkrGUids4C9R2VL+7qZutoxv4rs51BRCN8Fupfr1I+TQXRsleFVYG62iuoVQwDOojt3dhsxk8h6+
5aejhXZn6xgRcRoBV+Sk8YzIgwmUPYxr2ZzMBM/iggciNKs37HQTn5PuTe3OAm3z6O4lDhroa3lN
fGqMnt+Rg+AER54Ss33n+XqWtungYFJtMgc9yAUNbuD/tHDM5AxqsSRfB79ndEPLymF7aucNcRZK
ufBsZrslgUX0wcZHj1VI2iezYcC4s+JRq0zi6/pf5kqvb0amlxErKuRt+4Grbuq+M+NSQrPOdl14
3M4vSqL4XNHpU9fxcUvjDhGenEnIn0sMDwKXvW+JaNjHi1IgYSwETH0zZJwN7goKZrrXx2Q+IqhE
s0gE4APkeF0CzVe/5Os5fb2jJatwexjOr7niRhVtBM2GzJaLvtxupCE4jQzolmga0XicKoPArlza
sPPH3iU32ARcELfl/du1VMZFokP2Kpu476CDSvui08zrt1+abdtme/8j2xCvHZn3AjFDKvYUB/aV
mtA8/89ujm2b5HGZStr+tfP85gl4unkvCMYxKZ849V0NKYOQOEq0vX2uhDCRS/KmL5SE833hbbpo
ChTLxXpCFzByRHMd6bmWjE69HXNOcyjd6gPV+48PctnOITzZtFHX5LfRfWau88jRm3y50RpDab4l
QsBRUe8c2CH2GGGDo/5gHFOXsBn7cU51XYcNwqzmMA6INpPodS8/ehL+z3xm/0BG48xxXaIDk9bA
lf5dadR+g/++UIOIHwBB9W6Xpp4wtjcGqWZ/ZBloZR+x/cs62KaN3CldShelq1Rg9BF4H6TgvdcG
ERuZVKspqbWeoLxRapAX47R+y7nrWnOyuQ9HNgWGqPBCF2vk4mK0gVpzFryVTOBWHIvRvxC7zcHH
vKm7MuaoLFbb9GLXricYkB0fDcfgTZeQxtBHUpAqYXeC//pi1eiZKNU7H/9fnietuksYhtJLKzbV
ArdV3K8ijkZsXEg7Wbcn9wcp83HTJfam85ZlxSeiSg7dFy4kTpPManj7n756X4o7y5MbCkSk27jp
NcCKw3ryjD+frjHrNVwaqxcL+LJbFh+l1IgtcDrAsLH/Ykk9f1tyF52L+kbb5Ftrq5UXsHmK1Sry
nlpv/5zDVceUH/VAAEID12HIsLGT9MNcaJpbSsHaLe20lBCJEK3VXMwWVyUKwd2FKRwRhCDLGS4R
nfaMiA8xCDHrWoJTZDLp9FTac82EjWfnoeOwvjk5pu9SSVLPnHhcW1ItdcBNrLZfj4wY55d4eK54
WqRc5kqL3glMt9Z5qcE4/fSOTVPXgbG++/8/4q6ZPoG635glTWn+ZSjamxmnHZMJ+Bv1HVlcgrC3
6r5BsQfIk8K5hDfl4zcAs28fjd6j5cHP2HnojpfuSUKzvhVYWuQJ0c/8ty5sfvVvjwgiNNsn2S4U
mphMYq6aHP5YyioIsCzHPMHC37ZEfuZAdC80Nd1n7YvYvodB08yysyxuysZCUolvqNPALwf5m/oz
fyl7b1StHRzB/I/y4Jl1e+75rGCyYJf570vFbffW7+Vqr4DLCz6nOZY07kysAlJPRKk3O6O8/yk2
vz5jUjMdInc7AyISDiRL6XhPyOdUov0cq1MURGqdgvwsHfiPOLhH7RgOkZrXHfCFjpcPhqD8EklT
+hK4Hcld2RhcURXRh8YhxJcYHKRs8O2VazT/mNtNqdtqFal3E5dnISbv/vI7g0RE1Kb7pYxJG9wY
1W8kDKyQ25I5hz4V8iltPQv/3F5/KNJ3TVARaK8AVCiaESyJX/BjHSDfP4p7t0QSe6z4RBnV3SnG
510iZfp3FiH3k1q3BQiDucR5OMBkiGc1DQJAGcxXGI37EXn+NonnEpGEu8lUhgIj0jXDpwIXSXJE
sQN1m9CpzI3BQ796nmNOll76bfbyODuPS1oQzf6ScolxQkdSzkxo7fQoK3iTktEoqk4QJGA1LYbs
CbG7RTFKM9jFJfqt095Y60SyLtgNUN8T5fuWMt8/lHfMsOO/jOtDIR92aURVJUqypvGPKNyB9uur
UCHZbtYiVF90eadQxMvEjgLX36jYeQ8qY1zv/caVWTPTq83Ip5TXqJ9zSSRLLJVQKSAopxKshz/D
XIBkfVhpVw091P1Hdu5nHQllVjQ/S1bTWjDViLLjUrKHPqPRlT0Mus6ARHChh/MOQS5juMKLUZE4
jWWl077wstpcWBkDcrW9KWY3FzLJluL6cqcVVQy/xezPoGWlz9uBPMITCbe2JxRGhN+zaahMDuCP
I3Ngeok6kuKN3gKfKx8SRI1HWVJ2Z2bgwC+F6sevJnHByS+ktE2ll+z/xx19wIQPFTbE7yjuMcBs
18NkqjJz31uFSUi4i4WXxgY7bOC1Qm8wVHYjIdbno78IxfaYfXn6sbb7brikhS1BtuU6OSLDax+U
NDHibDcH2mAO2dJRYXAgE5sXn5mZBJ0yORkPPk1YJyrhumIv16n/GmvjHeB1PBxNs67UzA0yCNAw
btssX+8BJ2mcndbA0RfDUGGzmzEXCvsz7kHYIYfazVco7HFkn79iFfDa3IB3Q0QH/vSgFLuLTdxX
UFzoYPNwa+7H72WUYY6aFC09gQtMVP2FCucMEqYpj9jrgtJSLfbIlOFY3EgWwyIXxil2xIkvV1O4
7fSKQ2JIfaFuADX6SPpMD04SjGqLTfYkWuJgYz/P/x9rGf1pIX5pNvLpPl0bG6dV/x+yXBED6JBn
VkvRw+mG8apguLYd7BMNhnw+hg5dCvg3CyZrAOxIwVNgFPOA1xPETcg8og7TaRpaTySISSrwaGnP
K/3665XlWJYxwU0oc1yUV2ib20lsYNkkzTlt9f4sukN4eILncdigGnDsexuq3oo2A8IvPEEo3JzV
5CIO2TVNFeS00TQ8ALKKl75fWeyAFdmpSyoN7YgAhHlmp1qlzuHn3FroQ3ONE0vDim7EGD/T8ng3
5uO7eeIsdHD39yz7fIXnEnVmV+uun1meSEcSN5bYNhWGHkkz54hqDCp0I7SRS/dcT96ilbWXLH5N
HDAHQCFr/Qql/Rkq0wllAEv37er3717C/KwRV/yur+XRcuB3ENT0q/FtXD0/WYdm6KK9ak6jS3o+
vPrgUNhJ2f/oTbWZj5/kYrDmXeydEEG0HisUrETsP/FMqDW0wN6nXXO4OD5F7JH1F8kdUTMsgIU3
w4sJpXTw6nEHQa/SPVwusCSQhhC5uKW084nicn94DfIpn1Gwq/zrAveC131rIJEQlo/qZ/dHeWYp
7Aad/fBgYPE39G9o2cfshB3fVIhPTuxyy3Nrz8eWm3Zf9Te+y/n0II9Jbi0iZoiMA0roOy9Usr1X
c4DieHTzg93k5M31ARhbqPIy9YpH3TBBGer3amvpNja7PlIHz1Qoiy3oGzeMVqxMdVgksRCIDHUT
u57HM0QX8csg7+iMDb8TM0c3ePAkNw2XfmnCkAoNrpVT9FJ5P/qS5NJemHnnPexMA+T872haNzSg
Di/pTxoa4lR20ynBjbV5M/9VgsZ5sU4Vg6mkofU2ZhEfZNwlAHxW+GOpwBAcxjuXir/1/j0eMkD0
1g8LLgO6qzIh43uwYFmiyGK9f4mUBQQ6Y210/bHQbxtv3Aof4zOmuV1nFCCMOuQef8Pna2+EMr3e
AwUWKNgduS+UNMnBm0FwxCxeFRycFsz4wvmeeHyF4+yc/jQa46zTW/pGgrURYEZ7kov4y7mSePq7
wvFjB7LLEFQ0UZLkSMhEtVXqMQsRiTT2g7o+EZhdNaxH9ejfH+hPIvxC67swBb93qnxR5LHZZoaV
LoIQCgUF9ovgU7pyP+g7yfGiNCdj4EYCS/aE9yQZYE7cEkauAL5ObQ2tZy4TSaTNAI8hMFLpgRRw
sgyZ5Fj1CV/yFuYzh/+xt37M2ofyLcL/YLrhSahQvwx0RMc0pJabkzcTukpyzZBSg7LA67fF5aPx
+8HSM7x6LUheDxyW2tg5mVl5YLwGuCYVFMVMNaFMaIKy2hrupym2sIEB7ZuUZPHBuiE8Effapqju
2wEOUUY0Zt0BP6t6LZ0yghZ5mJcqaMMc5rG1ziu3J8SogMd6Jxb0zWdm0cKXD/GRjmpQtnMHy2Dq
RFwXcSUml64+NnoJmzLN9GKJAfM2Dsr4oysT2IkyuboLC4IJGmaUfEud4HPpE8iMqq8zH1yZON5e
dkbGygORs68hES584xYY//7s1XkFHgiw2AK7sIjN8LjD9Nmm2KZ75mwoNJvLhz9ImIw8bm+83nPt
3AoIhepbSKpUrrmlj9wcGxTdEgQIIYdzjluG6G5BcBye7EPSpemfIz2PHn9YXYn0GbKi1VdLnL/E
j3jiPDf//Fe6PmfKD4gJD6zAEH64Mg64Mddjw93CABpLFJ5CcvomPNbKaXxZ4KzGNt7ppjrED9EI
5aZ4rlfZNSSS+Sv4cK85FK3TUwcLHHB14WQmMKMQ9AXuEKjOg4eOtPOP8GtRpVjq0j6xAcyN+RHu
jWOAHjiE0OmEBkxIMkziXmbvOULyGaFVcHUnO4dS7BrxlIz/NnuWmm+BIZ3S8ZTRTZY3A7VV/Y3P
jfIuxwVF3HyBO6y4fMgsACE2fPyrKw6O7usg/luVzjN7Uompzhl+kiegf+i4NQqcvNRSy5c+lmLL
jMChWhpkED9PdxKlVV7Gnpz6LcLASE85YvDbFMr8Nsb+8s08latgCtLvStALFqz8ntVX3Cawz/Ur
CNqxvNPCKipZX+QfQe0XAeDbAZiXMrqqTq10EQ9q1MKdPFfzaFNvVhQrCdNSMfzLwpKbtjuTrdp4
jMC2Cx3MnDzrsRKn1tH8dsshRkrtY7NPfXH8Giy7imIBv9Xcdc8P1DDlZntKPT+G4oDiJU3h/vxd
3fL7znnfHSZ+x55Q8E8oCoeYo/g0y4b/cC0P4lZyUH4Gi7bYxcUqb6pcz3QiN/I9Ri5sTbFeKN3Y
dLcUdBz2FwxBwPNu39XqRZh1TENYe85DGud+0RdpTM2aoGAUxmX+aOKMk4G6mKfN8CyEVetA5ozt
B1YxiKg3v35dyf/nM7/IOXrhAWr97bEIVnZRpwqXWjtXK9iWtwRRExw5m7ZGzOKNdUjUw6e7lJBQ
puuVs4ITB+exG1IdFEZfnVtgwh1pq1bIrpUpy67NQkQ45aLR2U9NU/1V0jxtegvm4ApGtcvyVH7x
nrjweonxk+AklMriomS4neQdUYIjd6ZINBYJwcViRfk0QV0HTcins4ylbJTmgpzPrgaLcQwZkCl8
mj1/g0huAXeHXw7dVqHEXgkZqKDnw9feCFj6ay4bMox5mqUiK+MLQNZiNIfuhLJ05pLjFEOs0345
csCDuxwQA1YXvM9N1AXj/736Ux57qxYrVRF/yYLoBUpcIU7i7aa/cMGhwcvoX9FqZdKL4am7UcSt
9IhuU+vDX7jNtVq/N5JKgc30WbmKf56N+UKUGY8ywPcK1WseKTUqXEnuLoHhU2a/6p532MXJX3ME
deG1nrr/yGATII3JEpAqWl7K/pK4lqxTR6S+PKQf9CSzBosuZbcu8G0AcNflxIFTmCaJujACec8p
SHU1OUaZovO3RrY8P7f5zNrqlOq68vtEZFHfbi5DuuWmJShV4CspDtseuga+7O+QwN6if5vxTvbQ
oXwz7GoNn6T8wtF11bi6nanDX17mdbWBhp1xHxoZuDoTxXHItpmsI+dzJ0m9Bewj7sgT0qBrZj+B
Ky0R83NRYgJc5J5VjAO4+KyvC/w4TFhFr8Dgebbd+bypTEirzneJFCShexO6tinZnDEf1zxTnvuw
PFzGYTRCD9g4if1ELYUvY236Qrrjn09nB3eh8tgOTgQwqN4beExB3s03IT9D8PTa1u7bbKiIoCnX
gor06RpvvUMrFB77FbIISJxl2Pz4Q76fiLtYNLa6SweYK7TiX9H3tbJNUs/+rZAQat8I98uCS+gZ
yYVwmctTlnkLe7Wr+K5FNobmFxS0S3Wgj1zif2xKiGwf4+papcknsm4q25LffHokBPXm9w6KXlX9
SxzmZVA7+vHigi2E35riFAaleuFFXievzR+/MWgyTUrT+N8tZ1MsyY2Lxd+lyPRJ0GfIMSQOAyMM
bjVoiSLAoLdVv01ASp338AN+hslFZmbuTD+inwCSF7JpzYKqCYzRgracl0sWXNTIYel2wTNEy637
1IgBTvAmLXkpcvc40Eowwu9bvuwCNQ+ZeubEuYl3cNsSd56LvoYEhCdMf08BModdUy8r8HG+A73b
5wgCL9isQMdCojFCoDoYme0VX+QBoV6p1w/Ca48qhlawSfeqBUEBGvUnJE+/eBrkBmeEKrtXecP3
EDjBl1Qoh7Ch30K73mYY8eGnC9/++RVbr5U2NLszneDwR/h46iuMPKMa7eiovwF8Igxg0tgA2fvX
ichZN7MiqP4dL+Wzkgp+HOeiXGV9HIwe4LCLGoY0Zf1NZu7eGme77npmpV+LghP9gKmnrci+shUq
3OzGCLLsQ5dyCyLh7rIZSLoNknjsoqujttArYeho2DsuTWex0evqDoeVpVH9zuXTk+D03Fg6RCWU
0nONZH49dnlG5X9w7FQSxh859RXEIuuxXbUe1LcN2+QS6xevdaYW32aiQAfzj9o/hB9Lz5Spz4Tt
2Fy73g9XmPzUmgCjB+4rxl0uy3GXVpw9pXjtaHL0hIZGfJreznPIsgKtc1CFKV0txP7UrFxYH9X0
bbNVG8zkDZNO9yweZZ3FtDHphoEv4aBxFjehQXFgWjo6eJSGJ62iNoJ/kEkOs9CutMk2A0/R1UR/
5ForpmZQ7NHvN51MRF/jGyjlvRChHWrdzGZPlFKuwWiW5XF4QNqtNuYJJrCBcw1bh+bK/AvzbMj1
2WZY/E8BgJh8BVktxVgniWpFbBaPhdd7xYT14RcjC7N25Mji1l0/w8gilcCIS2zbQUyVG4LMt2qZ
ecaPXiAX5xSGZfEPSQEaurhnD8R0gHvpCeEBVRiq4L1/rp5wopghvSbFunEwMAseP32c4BZ0yPIg
Z3zxaI84vi805CWZK+ULh2imE+eG1ycok8gDeXHdEcvcCkb9Ebz+vzb6JPr41E2g59si3ld93qBC
/LA2Ro2XlRaDsIrxahzmIoL2rHSbMI9UcJArjfS/x5AEJ1FPzB1fBBFNSTxbfujtnP4Eaw3KH5nT
jhifNYfH1SU3qpuKiieA8DmW2zboVLpbp5SWyyTB0p/yUjq6EotO+/siqbZPeoDjGdhIWxephHSH
PYQQ9Re4rvupX51lGq7baf04474sQOiQ7Voq/xFoIJ+nIEeZ5go4issWfS6ntkGnq0fZxEaOgUsI
9iw5LTPTDWWTg/BH7boT57Ukndlem40jzXj+vk2DsD7dRUJ1i6sIgyvguAKJvKecnk/w6A69/Kb3
N1kHo1kBh7xb0w6p4Ub32XDEJ2a2VFHUYIN6fJtp9CjAEfQVCA8gZiqyAjpazVtu+zyh4BcgPRuh
EkmyTkBg9Y2YsWv/kWJyd2oEzUReILE0ajy+kjeVZeTzKTySyV3qQg0NGYOIkGTfriA0lBual5PX
gu00oJ3DZ1u0eOtugog+qfte45HfE6VG2Umtt8w2783qj9urb9VMaRAMlfvxspwg0yQ1NgxybUqu
YNKMOrtYTAfEQIWsVF1SGEzAMClRU3EcAZ4ZdFSiGpBQCF6xtkBJjN9lFgfe8BGbiUjPrufidXca
59dl6jgC4kq/kHCpbUOJMWHKrNk577FBaFJmQdw2+X1p0IXizbojmOzrI06ygShRMNPRwXVacOCh
Q44WzW0aQ8uYIGhxMO166jFBOuRdvv9kW4wUSsBxz2QS2XtW10vLybMQ8emAfbrGCWlbyV1LVEON
BIlUijDuoPVW0vj5Al8a4LgglmK1Ww14ZXnr0WHH/5tvyKV8UZb2emxtPB2T/GwcXRhpFSupMSuv
Z8C0kdzkeLBe0gfsKz5paxDfdNf4zaASCrw+KhaV+1dsD+kjNdQFoDmBOS3uwHmPbcqWK2U1qXi2
D68gswfDisPmzY4wkPhd7mrMCvY6F+Y/Ba6lmDtiOG8l5jVRJ4W6lL1KoXfurFLETBKUqLr+Jr6n
CCu8dLcsIBfZDNyRGLAqMXo1Z6QUsPg6eu+rRqdqpPSUsukKP0tuM12lFL/DNHCcBGoSpifz2/1p
pJVdnL3X8WNbzwfcOM9bGuL4jX/4PsExYiQMe611jrchB2d3kgEXAPRr079e4SE/259ZlQELmwqx
7dAJMKQkpNqGWkVXDlS4MQ7yTEkvr/FfByf1sS+Xoq7sETaD4g+KKPjbusVhahhSirW90UoccVWH
/5TKBFLsi4QHpm32Vnn7DCc78oI37Mn/OnXBstiw+BzYg+RXvUuMvBnIDvhXs9RRsIdLOCqegRsn
0qRV+KGCZG2t4rdvB/0GK9ZHS/f92ULQpGz2A5WHBYNqdfUqm/OCP7PBewmmUBN2b1IRtUYeOKmv
KXnd1WO0unNwt9kTM64EStYArLV+FTDXSdZpERMRenSghmjqJK6YhUNFfrQ2mrKt4bndTDapRejc
aAsHcPJHXcFdtqfTruxvV8OWAEVf/v50pd3cK9TaTYCnPlEQFhNm3Rng7znzyKFeOTRpBGf6vPL/
C0Q8jsIJJNfmkpM7LYFRZDQfTwIdvC/kz7n9m0DqCufRYUhdSD5FLryNvbUgATfFh27+FGsDvpDT
GARyhabtLJUyxNW9jeO/h1zL8IqHAvbsyAm8lDa9mcQ2sVTsDE9yAuBuLerMgowzu38j2VVJs+HS
gCrmoLoohzGApJmf77DgCfn1wCNXE4MhTbsT5FqxgmCGjN+bXxeShDQtmZ+TlKbdnYNUiC4knjEr
QoI+M+hvWBc/GJQSu5lRF+ZoQUU/hGZAcofdhFxDgfXmAygJRnCmCTaCCiIwjTukKz0j5xDoKLHf
6o4TvhxtPxJHNA+CpLsYq4tANI/D0WJHzdMz+H+m8uQ8EHOuti601FlWtS2QUDSuAwFrZKWpfpDX
Hc6m/D4Qatn+TePirA4KdmOU+6Pw/Gitxg5PAlyClqkxjoKY5iLLsd0+OZ31WU9dlgKlk62MFCa9
gEGHtmIEL5KyhCNoVTGSIJEqcVaTswabXUmCTs03wdO8IX+o9U7Y4Sk1/g9XtE1YJ+w5d6rN+6II
SKVdCDW4XityftB2Kcl+9O74MFdhTq46qUtpfT5/u+L8vpS9Zul16iP6xv/bOHunUf+JTbZe9JiA
ljo/Y7cLPIymH9KjzETTGffARGSHManKy6M/eiK4ZN6mtvhuu6mEjaRX59N5IZXYTEd/LAj7SgdF
QfaC8xyiD/H7Hfz3hi18uGviVqozKm9fsxO7N4puMv6ZGi7hgPI6eANY9GPhTL3S0PTLedkV2Vk/
cxrj5FQpJrQWaKL17djlIIFk1VPQxLOcm7sksT0F6lGgYGWtlDYnJ8R6Fbu5hzfq6QxwDpTU1f6y
RLJe4dpe8AeyC7VXGoVpXeBXDDBoxEktjI0bFPZ9rlmQyIIH9A4QGFojovwnqU6CPSHLw4CixlG4
cP9eLZ7EHawvnFFYD2YVX0/2AJQ3tdSOfikE6gkjyvSrM+ufeemtwnJ6wkYvHne2rBEPY4yyrQj/
/dr9E1vtIy4/TcuhxBtOrVlV8J2cvmXTNwWQy7icpBqLUO9W4kzvH0/AAPOYsDM4q6RH1+wS02yP
6At79JbgR8EhYpQxezaN3FglnXJ7am4VpV1iyn2RVQlATfpwuYcVXxFbFCTohzX38ghvJMxqRHwG
625H93ACsy3QmjPPLvj8vFQP38Wg2hgtQFbumaZYqvDwZm1vC0rfqPnkwNY1EmFObInX1Ppk4tB0
gHRRNqTSDuVH3AGFB1ZzCp+kd/yynhChF5hj9W8cCksVzivhVWxxBOJNeR8esubXer5ria+SBed/
A70bfvso2QYJ2dvV0J7is9vY84tv0swvTWeJP6NcM9kDVAjvxU+dYQKNUGF61qX0uA40YNjC1BaB
p2NTxN+0cEyESz6caPEvsEBHgnStz3sr0PNJZZXT+oeGA8w4rgy4sifQagIxmMmYTIOWVCTvJd4c
2WrL9kZg2ocmdsejSjeIPvj7YnZ26WsjwWxmxaFwfL1CS+JM3BxcDieVikt9FfNAR8Gm/UBa4tL/
kjvig0k0WJy6tSJqm0+wVs2TBe/m0ehnZklQT/zrTVXhD1oaHXexkt6vhWlrEdqG2pXwZmqQfF56
3eJetuW2e/ssBTjyrLU54mwJlr/IP3EHchXZdr+FTt+i5oA++qRFviGI5aJb3vsU9NxGr3ZnbcLh
SlB4EtOGWCphcBVQgy+9ftvvaJZ3y5k5H4Jn1h+U/4wG9wyp91f/VrfMWBfm+OZzSuT5qHcJPCdn
BtBfneIzaMwAA3ynJhx8jhOBXUxexc9x2o/LiWXWm4RUtYuOA9eCbP0Gtvulu02jQzCzDau/xDMH
4+TZ1Kr6RF1VgWq5FRUCaY5BAATQO6Fq9yNL/TYDEbJyfDOwhCpyCJpw0Qlo2h4itch+BnspVmhD
lI3yA06eEwkpAkr+C0aMg1if02MIdVW93FsRCa2i9KY0wQk9CJSzFQUzV52Yankp2Rsvz1knKs5j
Wmkj3yIFY3m9IH9YnEpiZxxIpDJLObmy5sAdhqWWK1bzTBuG1NfKQJTJv7/CszUMwIPHMD10z0F1
G6Aemnbk7kMLswumoJRZefunvPOexlYEuhaJAJzQxZP+AxbCvYcyQKolbkCaIiLCz/NfXK31dvVE
KBeKVUXottBvUBZ9GsVM9ZFAXnYOuvy5z4jdU7+YSyAcExmtLm0A8vB8XowFxytIMDxnlkmpXbC2
IBlxX7iHakGNiB8knLgUbuWCauHUbtzJ0qH8o26N1rw7DEc4VDg5rSLdHRtZ/20ZbN+TnvkKi5x+
fB7fUG457giA2tl/pxV/mEOoca/jSj/+Ge+njiHJNmEQrT5yc7N6b/rC2V9L6wYGCCRkocZHnoj2
S3e0KdF4Txs/+WJDy9/w+6mfTM5YdEHKZxCm+vFSk6tEtXkcvIO2qarUJqKE7a+cv3hxr0F3hm6j
TCyiQNgoWFJ0G5Z0KcWPJh1C1uzYA4mrKw/EveOocZPyNBBWoXEYoIBfsTu1zjlmw5BVJpHfJozf
VXD5fBgyo7G/ernUDvo40aM1na/znNoS+9ZjtyTqcuazlJjbHWzNFa4CqLNI8Ac+Nnv6D2BJnpBm
Y1a5iDcVrr/idZxgXoHw8YFeWigvYlbMj1wTFbqALfr5if7aKN2sUDKEbTfA2GudnVoGtFfl11Y2
70w+LQ009AFzy1MTKe6vyahx2oY6M3yug1y8+/5XbQ5mSAgeeoqoTsNpnAatbAdurTvN8I0yIERf
PVrxO30Od8LzL2Ghdd6TLiwEU8eeH4O3NcjO05K5j/WCEVANlqUcHLO5LRJ5CPj0dbGYNQbx9eEW
3V+pl4CcSyz2yBaqTNJlA8zDpvpqL0NFMPZwBFYt2UHTST06kzsvcwqyQTat9/6EtzUVEINUugsP
bz69gdnLvnygBrae/QCgmsdjur4cXUzcgd0+A69axVHw68qzuFKeguf+c8rc0Kqry/8QcBDFQmzP
2+nm1f1msp8txFFQSAaqZECCYjzmerRu9TKgvbyrjoid97I/Z8XU+RfCh039qopfQxNYbyPTcfNg
jVIRvItHlkAIN/fHyH0kDtGurdIcuXA6TxJHQJuo7tyXVxUo6qQqIqmc8XYU+LXfM592syRHTRjX
PhMkTCdKXVa4muKvoF1HBNrIlT6DOPRBDeDcltgswqj5WoRQp3BHsP3PVVzFWKylt+GrN+LPRTDt
jSIWvBw/s+5eLi0XKO8JRxEYyQf8Nhb5jvTNIvUWyjbmQ6CTDZQOTJ0SBgWh+UpZGa0wSUF75YKe
IjU1br77ogXaVHekMp7PzDzVF8EaHbDqhkItCoolCrNQOXH5PXKm3tkwXMKtg6b77hwqzZzPl3Om
VJXQ6Y0kpXA5lwfk5+GXBouSNBfLQBpDjQ6InuCQz3f5l/GRd/xwEEBMgfeH0Fj3sugyoJ5AXEmw
VU7fI7EUk7LSn3dTUXDvFpylnFrFSui/NJEi8bGHFbBgLz0Xs9kJ55SyTgYjS3Hw2DriXMowV4L9
jxDukdGnSs4biKSOjUUyvgE/2APuSjVsSPojlE8+R46HpKt4piPZAAl/PuPmTRyiZTJB5apWMbFT
YHRlergluaRT7gwT7JK5DDt3BMhdWGNakJYOBIhwpGN7JTOtNtmD5Y56HfmA+xZY59g9YZp4FpOh
LMQRuTLhY1dRzBtnClgArCcbSRtbWJ2z/c2+lH+TU1KPyOqMpPKAfhOxUutLguz5QK3app9oS2NC
67w8X/4TYhQzkynaLk3vHZIRfw9pxqwTdI3WWMRE1CdYlwKIMW0h1YRaJZjPwyEjdCQLeRKq7uZY
2lqdGSAjcrcvtdwSHXbFJDVkTkh2mb9H/I8Gdjh0CC3pR5NpOFdV3eS4jIbig15Yts2+WDhNcT86
+Mm10R+1TEhYiM0Rtn+ezSfo2rf+4SejLSw6KP+yduzVC8MU5IrKilGKZNG3bQwXPkY3jRRtbAoO
ek62VE0HnaZvdUaN8cqIIbB6u2Z6i9ODGV0m53qt7pGU7VM3MjrgcM4mfP4UuuJJQFJHxGnSSulR
EexdGXrQ4Ys0U3sgyi2FfQnnmnPGDZYqQK0JCEQyZ28nkxsWv6OStJjHFcQoLnYktsCuEIPSyBeD
+7RJ+0FXXyUCMigqUfgNtqnfkg42yTJYWfW0BOVp2+4c72NuQQRS0epLgsoSH+Dopie8GEiq0wlJ
hdsNxUeyidFuhK3iSPk86HOBd9kUY5oO6sbOqI6oIVSeISHBbRnc05ha5wpSNdh4867QlULMmpq9
THKMRJyb5S+fUENpXBYsBSFUNIW6gNXV1Pcv27fL72j+Ip/yO5l3999DbbkFhyO1qxT2pkwChwTB
37QmAEj3e8aLUlxCWaU+djZ9Ei2WWkqiWloCbL7AKNhL6ZFK1YTVCNMZTqdEpr3B1sQCVRPcjtfS
+40Ld6ksoCJGU9uf9VhpFme6l7OszJdzmVG4g2FMUuIVnv6DmvKYpkYyhlZuHZ3a4diZGYnNHtui
zfklrK2ctoQSsCqygc/1HP7vN/5Lu5XHFJXxlL0F4X9fFzW8N5qr0o54d43Snfwc08wxnB3Dd5E5
qqhvIQmLUwJiRmcMiLL/VQlmiyP8sK/kSdinpAy2Uus5kv6P7pYa/em1//2qcgK/dIwcjaEUCqLg
1A/6aqqlILD35VeGG+PlR1tNdTufvqGtal9p3WLKCwdoll0O1AQs4p6rNXaNEIIX5BV2oZGBvdW/
PnK9srkLBRPpO9dD0g4OSXDHWVghXvQLK/kxs0Ad2jM4fMIFsJAJFyp3KbV5PEeRpmGOE/jkrFv6
QYZYc3kfNx3iYS7F8mPRtgyd5Fy4Y+0qoqs6YxOgK9v885QZytlEPtkrZApE6zikuZDtFx6c9nWr
Vc+PF6MJMfiI+8PZLzE2KUx2BzZqeyfBKnj29KKzz+PadVEk7R5uOBwimiTB0OcFWUtZrWlLBHPC
07Tocoof3Ic64PVFbFiBojRy2AbwvrLeNtHz/RPqUmVY8ue3W/p5q7tF9dIfAsZTfAxzV/wA5nFf
D6/6mfnFxS5il0LNZQvmz2QvS7EwXqFIwvzmHO8Dtm0PNaGtCac1FNn3/qXZRcpc4TO8EhNAkZjE
amVvqLjCok4qVlAyR8SH6fMwNU9tPcBnz8p1YaoS1hAcSEZXLS95yCqhQMUkEcKaSr2v1LMRdm3A
xkJIYcf6BL0XNIysJ1zocf1U5AfP/6CX/q6OqjgmUv4fIcyM1HCzPgj2pCyEEINYdI/Yn0yR6IMx
QBwNvX3hoULu3irHr7OZwioUS7nQw8SNaxh44sbihZ8ebuXc6tAZ6nHya8+GqQ==
`protect end_protected
| gpl-3.0 | a704b643465f3452ad969f11414950b8 | 0.951441 | 1.841 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/ip/feedforward_ap_fcmp_0_no_dsp_32.vhd | 4 | 12,866 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fcmp_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END feedforward_ap_fcmp_0_no_dsp_32;
ARCHITECTURE feedforward_ap_fcmp_0_no_dsp_32_arch OF feedforward_ap_fcmp_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fcmp_0_no_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=1,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=1,C_RESULT_FRACTION_WIDTH=0,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=8,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 1,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 1,
C_RESULT_FRACTION_WIDTH => 0,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 8,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fcmp_0_no_dsp_32_arch;
| gpl-3.0 | 14cd759a80c4597cb55e2ec8dfa7ed73 | 0.652884 | 3.017355 | false | false | false | false |
Cpt-Quantum/VHDL | FPGA_Intro/Clocks.vhd | 1 | 3,044 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19.08.2016 14:48:09
-- Design Name:
-- Module Name: Switches_LEDS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( switches_1 : in STD_LOGIC_VECTOR(7 downto 0);
switches_2 : in STD_LOGIC_VECTOR(3 downto 0);
LEDS_1 : out STD_LOGIC_VECTOR(7 downto 0);
LEDS_2 : out STD_LOGIC_VECTOR(3 downto 0);
clk : in STD_LOGIC
);
end counter;
architecture Behavioral of counter is
signal counter : STD_LOGIC_VECTOR(29 downto 0);
signal LED_state : STD_LOGIC_VECTOR(3 downto 0);
-- Reset signals
signal reset : STD_LOGIC;
begin
--Reset block
reset_proc: process(clk)
begin
if rising_edge(clk) then
if switches_2(0) = '1' then
reset <= '1';
else
reset <= '0';
end if;
end if;
end process;
--End of reset block
--Counter block
counter_proc: process(clk)
begin
if rising_edge(clk) and reset = '0' then
counter <= counter+1;
if counter = STD_LOGIC_VECTOR(to_unsigned(100000000,30)) or reset = '1' then
counter <= (others=>'0');
end if;
end if;
end process;
--End of counter block
--Display 1 second on each LED
LED_proc: process(clk)
begin
if rising_edge(clk) then
if reset= '1' then
LED_state <= "1000";
end if;
if counter = STD_LOGIC_VECTOR(to_unsigned(99999999,30)) then
--Assign LEDds to internal LED state
LEDS_1(7 downto 4) <= LED_state(3 downto 0);
-- Shift register to move along LED chain
LED_state(3 downto 0) <= LED_state(0) & LED_state(3 downto 1);
end if;
--Set lower bits for counter as this is all the counter will reach
LEDS_1(3 downto 0) <= counter(25 downto 22);
end if;
end process;
--Switch off LEDS on board, comment if you want to use these LEDs elesewhere
LEDS_2 <= (others=>'0');
end Behavioral;
| mit | 7106e4f4aa46d3aa31b18d506439c652 | 0.509855 | 4.348571 | false | false | false | false |
Rookfighter/aes-ss17 | ex01/ledblinker.vhd | 1 | 1,446 | -- ledblinker.vhd
--
-- Created on: 12 May 2017
-- Author: Fabian Meyer
--
-- LED blinker with configurable frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ledblinker is
generic(RSTDEF: std_logic := '1');
port (rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
freq: in std_logic_vector(2 downto 0); -- blinking frequency, 000 = stop, 111 = fast
led: out std_logic); -- LED status, active high
end entity ledblinker;
architecture behavioral of ledblinker is
-- define length of counter
constant CNTLEN: natural := 26;
-- counter that is incremented on each clk
signal cnt: std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
-- counter plus zero bit (freq = 0)
signal cnt_tmp: std_logic_vector(CNTLEN downto 0) := (others => '0');
begin
process(rst, clk)
begin
if rst = RSTDEF then
cnt <= (others => '0');
elsif rising_edge(clk) then
-- increment cnt, carry bit defines LED status
cnt <= cnt + 1;
end if;
end process;
-- always keep a leading 0 for freq = 0
cnt_tmp <= '0' & cnt;
-- led status is defined by carry bit
-- position of carry bit is defined by freq
led <= cnt_tmp(CNTLEN - CONV_INTEGER(freq));
end architecture behavioral;
| gpl-3.0 | 9a228db39c93d735376f3ff34ea1a135 | 0.596127 | 3.908108 | false | false | false | false |
Rookfighter/aes-ss17 | ex01/sync_buffer.vhd | 1 | 3,155 | -- sync_buffer.vhd
--
-- Created on: 14 May 2017
-- Author: Fabian Meyer
--
-- Buffer component to debounce signals using hysteresis approach. Waits a
-- certain amount of clock cycles until input signal is applied to output.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sync_buffer is
generic(RSTDEF: std_logic := '1');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
en: in std_logic; -- enable, high active
din: in std_logic; -- data bit, input
dout: out std_logic; -- data bit, output
redge: out std_logic; -- rising edge on din detected
fedge: out std_logic); -- falling edge on din detected
end sync_buffer;
-- sync_buffer waits 2**CNTLEN clock cycles until it puts din on dout
architecture behavioral of sync_buffer is
component flipflop is
generic(RSTDEF: std_logic);
port(rst: in std_logic;
clk: in std_logic;
en: in std_logic;
d: in std_logic;
q: out std_logic);
end component;
-- length of counter
constant CNTLEN : natural := 5; -- after 32 clock cycles value is applied
constant CNTFULL : std_logic_vector(CNTLEN-1 downto 0) := (others => '1');
-- counter until input is applied to output
signal cnt : std_logic_vector(CNTLEN-1 downto 0) := (others => '0');
-- debounced input signal
signal din_deb: std_logic := '0';
-- output signal of flipflop1
signal q1 : std_logic := '0';
-- output signal of flipflop2
signal q2 : std_logic := '0';
begin
-- signal is chained through 2 flipflops to sync with clock
flipflop1 : flipflop
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
en => en,
d => din,
q => q1);
flipflop2 : flipflop
generic map(RSTDEF => RSTDEF)
port map(rst => rst,
clk => clk,
en => en,
d => q1,
q => q2);
-- connect debounced signal to out port
dout <= din_deb;
process (rst, clk)
begin
if rst = RSTDEF then
din_deb <= '0';
cnt <= (others => '0');
redge <= '0';
fedge <= '0';
elsif rising_edge(clk) then
redge <= '0';
fedge <= '0';
if en = '1' then
-- only start counting if q2 != din_deb
-- signal has to stay stable for 2**CNTLEN cycles before it is
-- applied. Otherwise counter will be reset again.
if din_deb = q2 then
cnt <= (others => '0');
else
cnt <= cnt + 1;
end if;
if cnt = CNTFULL then
-- counter is full, apply signal and set if it is a rising
-- or falling edge
redge <= q2;
fedge <= not q2;
din_deb <= q2;
end if;
end if;
end if;
end process;
end behavioral;
| gpl-3.0 | 8a7c9c71bb9f0cc0c10692f2aa7beef5 | 0.522662 | 4.070968 | false | false | false | false |
bonfireprocessor/bonfire-soc | obsolete/lpcbus.vhd | 1 | 1,931 | ---------------------------------------------------------------------
-- Simple WISHBONE interconnect
--
-- Generated by wigen at 09/14/16 20:54:53
--
-- Configuration:
-- Number of masters: 1
-- Number of slaves: 1
-- Master address width: 28
-- Slave address width: 8
-- Port size: 8
-- Port granularity: 8
-- Entity name: lpcbus
-- Pipelined arbiter: no
-- Registered feedback: no
-- Unsafe slave decoder: no
--
-- Command line:
-- wigen -e lpcbus 1 1 28 8 8 8
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity lpcbus is
port(
clk_i: in std_logic;
rst_i: in std_logic;
s0_cyc_i: in std_logic;
s0_stb_i: in std_logic;
s0_we_i: in std_logic;
s0_ack_o: out std_logic;
s0_adr_i: in std_logic_vector(27 downto 0);
s0_dat_i: in std_logic_vector(7 downto 0);
s0_dat_o: out std_logic_vector(7 downto 0);
m0_cyc_o: out std_logic;
m0_stb_o: out std_logic;
m0_we_o: out std_logic;
m0_ack_i: in std_logic;
m0_adr_o: out std_logic_vector(7 downto 0);
m0_dat_o: out std_logic_vector(7 downto 0);
m0_dat_i: in std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of lpcbus is
signal cyc_mux: std_logic;
signal stb_mux: std_logic;
signal we_mux: std_logic;
signal adr_mux: std_logic_vector(27 downto 0);
signal wdata_mux: std_logic_vector(7 downto 0);
signal ack_mux: std_logic;
signal rdata_mux: std_logic_vector(7 downto 0);
begin
-- MASTER->SLAVE MUX
cyc_mux<=s0_cyc_i;
stb_mux<=s0_stb_i;
we_mux<=s0_we_i;
adr_mux<=s0_adr_i;
wdata_mux<=s0_dat_i;
-- MASTER->SLAVE DEMUX
m0_cyc_o<=cyc_mux;
m0_stb_o<=stb_mux;
m0_we_o<=we_mux;
m0_adr_o<=adr_mux(m0_adr_o'range);
m0_dat_o<=wdata_mux;
-- SLAVE->MASTER MUX
ack_mux<=m0_ack_i;
rdata_mux<=m0_dat_i;
-- SLAVE->MASTER DEMUX
s0_ack_o<=ack_mux;
s0_dat_o<=rdata_mux;
end architecture;
| gpl-3.0 | 8fa32d87148c7a101a6e618e1bf159a5 | 0.591921 | 2.59543 | false | false | false | false |
diecaptain/fuzzy_kalman_mppt | kr_fuzman_Vref.vhd | 1 | 1,602 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Vref is
port (clock : in std_logic;
Vref_enable : in std_logic;
Vref : out std_logic_vector(31 downto 0)
);
end kr_fuzman_Vref;
architecture behav of kr_fuzman_Vref is
signal i : integer range 0 to 19:=0; -- change the range value
signal enable : std_logic:='0';
type lut is array ( 0 to 3**3 - 8) of std_logic_vector(31 downto 0);
constant my_lut : lut := (
0 => "01000001101000000000000000000000",
1 => "01000001101001001100110011001101",
2 => "01000001100110100010100011110110",
3 => "01000001101000001100110011001101",
4 => "01000001100111100110011001100110",
5 => "01000001100110101110000101001000",
6 => "01000001100110110101110000101001",
7 => "01000001100111001111010111000011",
8 => "01000001100110110000101000111101",
9 => "01000001101000110011001100110011",
10 => "01000001100110101000111101011100",
11 => "01000001100100001100110011001101",
12 => "01000001100111010001111010111000",
13 => "01000001100110100000000000000000",
14 => "01000001100110111000010100011111",
15 => "01000001100110011010111000010100",
16 => "01000001100111011000010100011111",
17 => "01000001100111010101110000101001",
18 => "01000001100111001111010111000011",
19 => "01000001100111001010001111010111"
);
begin
process (Vref_enable)
begin
if Vref_enable'event and Vref_enable = '1' then
enable <= '1';
end if;
end process;
process (clock)
begin
if rising_edge (clock) then
if (enable = '1') then
if (i <= 19) then
Vref <= my_lut(i);
i <= i + 1;
end if;
end if;
end if;
end process;
end behav; | mit | a92fac85f3f1224d468fa68cc7a17a41 | 0.735955 | 3.640909 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_axi_dma_1_1/synth/design_SWandHW_standalone_axi_dma_1_1.vhd | 1 | 22,263 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_SWandHW_standalone_axi_dma_1_1 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_SWandHW_standalone_axi_dma_1_1;
ARCHITECTURE design_SWandHW_standalone_axi_dma_1_1_arch OF design_SWandHW_standalone_axi_dma_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_SWandHW_standalone_axi_dma_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_SWandHW_standalone_axi_dma_1_1_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_SWandHW_standalone_axi_dma_1_1_arch : ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_1_1,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_SWandHW_standalone_axi_dma_1_1_arch: ARCHITECTURE IS "design_SWandHW_standalone_axi_dma_1_1,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=256,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=1,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 256,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 1,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => '0',
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_arready => '0',
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_mm2s_rlast => '0',
m_axi_mm2s_rvalid => '0',
m_axis_mm2s_tready => '0',
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_SWandHW_standalone_axi_dma_1_1_arch;
| gpl-3.0 | c8114ffc54f1f1996e87fd2686f97a39 | 0.673225 | 2.794051 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/uc3m/feedforward_v1_4/hdl/vhdl/feedforward_mul_7ns_31ns_38_3.vhd | 3 | 2,699 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(7 - 1 downto 0);
b: in std_logic_vector(31 - 1 downto 0);
p: out std_logic_vector(38 - 1 downto 0));
end entity;
architecture behav of feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
signal tmp_product : std_logic_vector(38 - 1 downto 0);
signal a_i : std_logic_vector(7 - 1 downto 0);
signal b_i : std_logic_vector(31 - 1 downto 0);
signal p_tmp : std_logic_vector(38 - 1 downto 0);
signal a_reg0 : std_logic_vector(7 - 1 downto 0);
signal b_reg0 : std_logic_vector(31 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(38 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 38));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity feedforward_mul_7ns_31ns_38_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of feedforward_mul_7ns_31ns_38_3 is
component feedforward_mul_7ns_31ns_38_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
feedforward_mul_7ns_31ns_38_3_Mul3S_0_U : component feedforward_mul_7ns_31ns_38_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
| gpl-3.0 | f91b80ac26915016ac38fccd3c5d7f0d | 0.552797 | 3.25573 | false | false | false | false |
kristapsdreija/IGLOO_NANO_FPGA_VGA_Generator_Libero_SoC | IGLOO_Updated_VGA/smartgen/CLKGEN/CLKGEN.vhd | 1 | 7,140 | -- Version: v11.4 SP1 11.4.1.17
library ieee;
use ieee.std_logic_1164.all;
library igloo;
use igloo.all;
entity CLKGEN is
port( POWERDOWN : in std_logic;
CLKA : in std_logic;
LOCK : out std_logic;
GLA : out std_logic
);
end CLKGEN;
architecture DEF_ARCH of CLKGEN is
component PLL
generic (VCOFREQUENCY:real := 0.0);
port( CLKA : in std_logic := 'U';
EXTFB : in std_logic := 'U';
POWERDOWN : in std_logic := 'U';
GLA : out std_logic;
LOCK : out std_logic;
GLB : out std_logic;
YB : out std_logic;
GLC : out std_logic;
YC : out std_logic;
OADIV0 : in std_logic := 'U';
OADIV1 : in std_logic := 'U';
OADIV2 : in std_logic := 'U';
OADIV3 : in std_logic := 'U';
OADIV4 : in std_logic := 'U';
OAMUX0 : in std_logic := 'U';
OAMUX1 : in std_logic := 'U';
OAMUX2 : in std_logic := 'U';
DLYGLA0 : in std_logic := 'U';
DLYGLA1 : in std_logic := 'U';
DLYGLA2 : in std_logic := 'U';
DLYGLA3 : in std_logic := 'U';
DLYGLA4 : in std_logic := 'U';
OBDIV0 : in std_logic := 'U';
OBDIV1 : in std_logic := 'U';
OBDIV2 : in std_logic := 'U';
OBDIV3 : in std_logic := 'U';
OBDIV4 : in std_logic := 'U';
OBMUX0 : in std_logic := 'U';
OBMUX1 : in std_logic := 'U';
OBMUX2 : in std_logic := 'U';
DLYYB0 : in std_logic := 'U';
DLYYB1 : in std_logic := 'U';
DLYYB2 : in std_logic := 'U';
DLYYB3 : in std_logic := 'U';
DLYYB4 : in std_logic := 'U';
DLYGLB0 : in std_logic := 'U';
DLYGLB1 : in std_logic := 'U';
DLYGLB2 : in std_logic := 'U';
DLYGLB3 : in std_logic := 'U';
DLYGLB4 : in std_logic := 'U';
OCDIV0 : in std_logic := 'U';
OCDIV1 : in std_logic := 'U';
OCDIV2 : in std_logic := 'U';
OCDIV3 : in std_logic := 'U';
OCDIV4 : in std_logic := 'U';
OCMUX0 : in std_logic := 'U';
OCMUX1 : in std_logic := 'U';
OCMUX2 : in std_logic := 'U';
DLYYC0 : in std_logic := 'U';
DLYYC1 : in std_logic := 'U';
DLYYC2 : in std_logic := 'U';
DLYYC3 : in std_logic := 'U';
DLYYC4 : in std_logic := 'U';
DLYGLC0 : in std_logic := 'U';
DLYGLC1 : in std_logic := 'U';
DLYGLC2 : in std_logic := 'U';
DLYGLC3 : in std_logic := 'U';
DLYGLC4 : in std_logic := 'U';
FINDIV0 : in std_logic := 'U';
FINDIV1 : in std_logic := 'U';
FINDIV2 : in std_logic := 'U';
FINDIV3 : in std_logic := 'U';
FINDIV4 : in std_logic := 'U';
FINDIV5 : in std_logic := 'U';
FINDIV6 : in std_logic := 'U';
FBDIV0 : in std_logic := 'U';
FBDIV1 : in std_logic := 'U';
FBDIV2 : in std_logic := 'U';
FBDIV3 : in std_logic := 'U';
FBDIV4 : in std_logic := 'U';
FBDIV5 : in std_logic := 'U';
FBDIV6 : in std_logic := 'U';
FBDLY0 : in std_logic := 'U';
FBDLY1 : in std_logic := 'U';
FBDLY2 : in std_logic := 'U';
FBDLY3 : in std_logic := 'U';
FBDLY4 : in std_logic := 'U';
FBSEL0 : in std_logic := 'U';
FBSEL1 : in std_logic := 'U';
XDLYSEL : in std_logic := 'U';
VCOSEL0 : in std_logic := 'U';
VCOSEL1 : in std_logic := 'U';
VCOSEL2 : in std_logic := 'U'
);
end component;
component GND
port(Y : out std_logic);
end component;
component VCC
port(Y : out std_logic);
end component;
signal \VCC\, \GND\ : std_logic;
signal GND_power_net1 : std_logic;
signal VCC_power_net1 : std_logic;
begin
\GND\ <= GND_power_net1;
\VCC\ <= VCC_power_net1;
Core : PLL
generic map(VCOFREQUENCY => 75.556)
port map(CLKA => CLKA, EXTFB => \GND\, POWERDOWN =>
POWERDOWN, GLA => GLA, LOCK => LOCK, GLB => OPEN, YB =>
OPEN, GLC => OPEN, YC => OPEN, OADIV0 => \GND\, OADIV1
=> \VCC\, OADIV2 => \GND\, OADIV3 => \GND\, OADIV4 =>
\GND\, OAMUX0 => \GND\, OAMUX1 => \GND\, OAMUX2 => \VCC\,
DLYGLA0 => \GND\, DLYGLA1 => \GND\, DLYGLA2 => \GND\,
DLYGLA3 => \GND\, DLYGLA4 => \GND\, OBDIV0 => \GND\,
OBDIV1 => \GND\, OBDIV2 => \GND\, OBDIV3 => \GND\, OBDIV4
=> \GND\, OBMUX0 => \GND\, OBMUX1 => \GND\, OBMUX2 =>
\GND\, DLYYB0 => \GND\, DLYYB1 => \GND\, DLYYB2 => \GND\,
DLYYB3 => \GND\, DLYYB4 => \GND\, DLYGLB0 => \GND\,
DLYGLB1 => \GND\, DLYGLB2 => \GND\, DLYGLB3 => \GND\,
DLYGLB4 => \GND\, OCDIV0 => \GND\, OCDIV1 => \GND\,
OCDIV2 => \GND\, OCDIV3 => \GND\, OCDIV4 => \GND\, OCMUX0
=> \GND\, OCMUX1 => \GND\, OCMUX2 => \GND\, DLYYC0 =>
\GND\, DLYYC1 => \GND\, DLYYC2 => \GND\, DLYYC3 => \GND\,
DLYYC4 => \GND\, DLYGLC0 => \GND\, DLYGLC1 => \GND\,
DLYGLC2 => \GND\, DLYGLC3 => \GND\, DLYGLC4 => \GND\,
FINDIV0 => \GND\, FINDIV1 => \GND\, FINDIV2 => \GND\,
FINDIV3 => \VCC\, FINDIV4 => \GND\, FINDIV5 => \GND\,
FINDIV6 => \GND\, FBDIV0 => \VCC\, FBDIV1 => \GND\,
FBDIV2 => \GND\, FBDIV3 => \GND\, FBDIV4 => \GND\, FBDIV5
=> \VCC\, FBDIV6 => \GND\, FBDLY0 => \GND\, FBDLY1 =>
\GND\, FBDLY2 => \GND\, FBDLY3 => \GND\, FBDLY4 => \GND\,
FBSEL0 => \VCC\, FBSEL1 => \GND\, XDLYSEL => \GND\,
VCOSEL0 => \GND\, VCOSEL1 => \GND\, VCOSEL2 => \VCC\);
GND_power_inst1 : GND
port map( Y => GND_power_net1);
VCC_power_inst1 : VCC
port map( Y => VCC_power_net1);
end DEF_ARCH;
-- _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._
-- _GEN_File_Contents_
-- Version:11.4.1.17
-- ACTGENU_CALL:1
-- BATCH:T
-- FAM:PA3LCLP
-- OUTFORMAT:VHDL
-- LPMTYPE:LPM_PLL_STATIC
-- LPM_HINT:NONE
-- INSERT_PAD:NO
-- INSERT_IOREG:NO
-- GEN_BHV_VHDL_VAL:F
-- GEN_BHV_VERILOG_VAL:F
-- MGNTIMER:F
-- MGNCMPL:T
-- DESDIR:C:/Users/Admin/Desktop/IGLOO_Updated_VGA/smartgen\CLKGEN
-- GEN_BEHV_MODULE:F
-- SMARTGEN_DIE:UM4X4M1LPLV
-- SMARTGEN_PACKAGE:vq100
-- AGENIII_IS_SUBPROJECT_LIBERO:T
-- FIN:20.000000
-- CLKASRC:0
-- FBDLY:1
-- FBMUX:1
-- XDLYSEL:0
-- PRIMFREQ:25.175000
-- PPHASESHIFT:0
-- DLYAVAL:1
-- OAMUX:4
-- POWERDOWN_POLARITY:0
-- LOCK_POLARITY:1
-- LOCK_CTL:0
-- VOLTAGE:1.2
-- _End_Comments_
| gpl-2.0 | 2edd262137c79dd14e21f4503da0c3fa | 0.457563 | 3.15371 | false | false | false | false |
Rookfighter/aes-ss17 | ex01/flipflop.vhd | 1 | 952 | -- flipflop.vhd
--
-- Created on: 14 May 2017
-- Author: Fabian Meyer
--
-- Fliflop component. Apply input to output in sync with clock.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity flipflop is
generic(RSTDEF: std_logic := '1');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
en: in std_logic; -- enable, high active
d: in std_logic; -- data in
q: out std_logic); -- data out, clock synced
end flipflop;
architecture behavioral of flipflop is
-- tmp variable for output data
signal dff: std_logic;
begin
-- link dff to output
q <= dff;
process(rst, clk) is
begin
if rst = RSTDEF then
dff <= '0';
elsif rising_edge(clk) then
if en = '1' then
dff <= d;
end if;
end if;
end process;
end behavioral;
| gpl-3.0 | c72b2ebf22c0bd4bbe10a963512918ad | 0.573529 | 3.606061 | false | false | false | false |
bonfireprocessor/bonfire-soc | sdram/sdram_model.vhd | 1 | 8,520 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:11:26 09/20/2013
-- Design Name:
-- Module Name: sdram_model - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_textio.all;
library STD;
use STD.textio.all;
entity sdram_model is
generic (
RamFileName : string := "";
mode : string := "N";
DRAM_pagesize : natural :=256
);
Port ( CLK : in STD_LOGIC;
CKE : in STD_LOGIC;
CS_N : in STD_LOGIC;
RAS_N : in STD_LOGIC;
CAS_N : in STD_LOGIC;
WE_N : in STD_LOGIC;
BA : in STD_LOGIC_VECTOR (1 downto 0);
DQM : in STD_LOGIC_VECTOR (1 downto 0);
ADDR : in STD_LOGIC_VECTOR (12 downto 0);
DQ : inout STD_LOGIC_VECTOR (15 downto 0));
end sdram_model;
architecture Behavioral of sdram_model is
function LOG2(C:INTEGER) return INTEGER is -- C should be >0
variable TEMP,COUNT:INTEGER;
begin
TEMP:=0;
COUNT:=C;
while COUNT>1 loop
TEMP:=TEMP+1;
COUNT:=COUNT/2;
end loop;
return TEMP;
end;
type decode is (unsel_c, lmr_c, ref_c, pre_c, act_c, wr_c, rd_c, term_c, nop_c);
signal command : decode;
signal dqm_sr : std_logic_vector(3 downto 0) := (others => '0');
signal selected_bank : std_logic_vector( 1 downto 0);
signal column : std_logic_vector( log2(DRAM_pagesize)-1 downto 0) := (others => '0');
-- Only eight rows of four banks are modeled
type memory_array is array (0 to 8 * DRAM_pagesize * 4 -1 ) of std_logic_vector( 15 downto 0);
type row_array is array (0 to 3) of std_logic_vector(2 downto 0);
signal active_row : row_array;
signal is_row_active : std_logic_vector(3 downto 0);
signal mode_reg : std_logic_vector(12 downto 0);
signal data_delay1 : std_logic_vector(15 downto 0);
signal data_delay2 : std_logic_vector(15 downto 0);
signal data_delay3 : std_logic_vector(15 downto 0);
signal addr_index : STD_LOGIC_VECTOR(log2(memory_array'length)-1 downto 0);
signal wr_mask : std_logic_vector( 1 downto 0);
signal wr_data : std_logic_vector(15 downto 0);
signal wr_burst : std_logic_vector( 8 downto 0);
signal rd_burst : std_logic_vector( 9 downto 0);
impure function InitFromFile return memory_array is
FILE RamFile : text; -- is in RamFileName;
variable RamFileLine : line;
variable word : std_logic_vector(31 downto 0);
variable r : memory_array;
variable I : natural;
begin
if (mode="H" or mode="B") and RamFileName'length>0 then
file_open(RamFile,RamFileName,READ_MODE);
I:=0;
while not endfile(RamFile) loop
readline (RamFile, RamFileLine);
if mode="H" then
hread (RamFileLine, word); -- alternative: HEX read
else
read(RamFileLine,word); -- Binary read
end if;
r(I) := word(15 downto 0);
r(I+1) := word(31 downto 16);
I:=I+2;
end loop;
file_close(RamFile);
end if;
return r;
end function;
signal memory : memory_array:=InitFromFile;
begin
addr_index <= active_row(to_integer(unsigned(selected_bank))) & selected_bank & column;
decode_proc: process(CS_N, RAS_N, CAS_N, WE_N)
variable cmd : std_logic_vector(2 downto 0);
begin
if CS_N = '1' then
command <= unsel_c;
else
cmd := RAS_N & CAS_N & WE_N;
case cmd is
when "000" => command <= LMR_c;
when "001" => command <= REF_c;
when "010" => command <= PRE_c;
when "011" => command <= ACT_c;
when "100" => command <= WR_c;
when "101" => command <= RD_c;
when "110" => command <= TERM_c;
when others => command <= NOP_c;
end case;
end if;
end process;
data_process : process(clk)
begin
if rising_edge(clk) then
-- this implements the data masks, gets updated when a read command is sent
rd_burst(8 downto 0) <= rd_burst(9 downto 1);
column <= std_logic_vector(unsigned(column)+1);
wr_burst(7 downto 0) <= wr_burst(8 downto 1);
-- Process any pending writes
if wr_burst(0) = '1' and wr_mask(0) = '1' then
memory(to_integer(unsigned(addr_index)))(7 downto 0) <= wr_data(7 downto 0);
end if;
if wr_burst(0) = '1' and wr_mask(1) = '1' then
memory(to_integer(unsigned(addr_index)))(15 downto 8) <= wr_data(15 downto 8);
end if;
wr_data <= dq;
-- default is not to write
wr_mask <= "00";
if command = wr_c then
rd_burst <= (others => '0');
column <= addr(column'high downto 0);
selected_bank <= ba;
if mode_reg(9) = '1' then
wr_burst <= "000000001";
else
case mode_reg(2 downto 0) is
when "000" => wr_burst <= "000000001";
when "001" => wr_burst <= "000000011";
when "010" => wr_burst <= "000001111";
when "011" => wr_burst <= "011111111";
when "111" => wr_burst <= "111111111"; -- full page
when others =>
end case;
end if;
elsif command = lmr_c then
mode_reg <= addr;
elsif command = act_c then
-- Open a row in a bank
active_row(to_integer(unsigned(ba))) <= addr(2 downto 0);
is_row_active(to_integer(unsigned(ba))) <= '1';
elsif command = pre_c then
-- Close off the row
active_row(to_integer(unsigned(ba))) <= (others => 'X');
is_row_active(to_integer(unsigned(ba))) <= '0';
elsif command = RD_c then
wr_burst <= (others => '0');
column <= addr(column'high downto 0);
selected_bank <= ba;
-- This sets the bust length
case mode_reg(2 downto 0) is
when "000" => rd_burst <= "000000001" & rd_burst(1);
when "001" => rd_burst <= "000000011" & rd_burst(1);
when "010" => rd_burst <= "000001111" & rd_burst(1);
when "011" => rd_burst <= "011111111" & rd_burst(1);
when "111" => rd_burst <= "111111111" & rd_burst(1); -- full page
when others =>
-- full page not implemnted
end case;
end if;
-- This is the logic that implements the CAS delay. Here is enough for CAS=2
if mode_reg(6 downto 4) = "010" then
data_delay1 <= memory(to_integer(unsigned(addr_index)));
elsif mode_reg(6 downto 4) = "011" then
data_delay1 <= data_delay2;
data_delay2 <= memory(to_integer(unsigned(addr_index)));
else
data_delay1 <= data_delay2;
data_delay2 <= data_delay3;
data_delay3 <= memory(to_integer(unsigned(addr_index)));
end if;
-- Output masks lag a cycle
dqm_sr <= dqm & dqm_sr(3 downto 2);
wr_mask <= not dqm;
end if;
end process;
data2_process : process(clk)
begin
if rising_edge(clk) then
if rd_burst(0) = '1' and dqm_sr(0) = '0' then
dq( 7 downto 0) <= data_delay1(7 downto 0) after 4 ns;
else
dq( 7 downto 0) <= "ZZZZZZZZ" after 4.0 ns;
end if;
if rd_burst(0) = '1' and dqm_sr(1) = '0' then
dq(15 downto 8) <= data_delay1(15 downto 8) after 4.0 ns;
-- Move onto the next address in the active row
else
dq(15 downto 8) <= "ZZZZZZZZ" after 4.0 ns;
end if;
elsif falling_edge(clk) then
dq <= (others => 'Z') after 4.5 ns;
end if;
end process;
end Behavioral;
| gpl-3.0 | ac2357548987c602b5fe73700a38b42b | 0.510915 | 3.680346 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/vhdl/ANN_fmul_32ns_32ns_32_4_max_dsp.vhd | 7 | 3,335 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity ANN_fmul_32ns_32ns_32_4_max_dsp is
generic (
ID : integer := 1;
NUM_STAGE : integer := 4;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of ANN_fmul_32ns_32ns_32_4_max_dsp is
--------------------- Component ---------------------
component ANN_ap_fmul_2_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
ANN_ap_fmul_2_max_dsp_32_u : component ANN_ap_fmul_2_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 418b09e5a5a33593c2ec26011da9ac29 | 0.483658 | 3.470343 | false | false | false | false |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone_v2/ipshared/uc3m/ann_v2_1/hdl/ip/ANN_ap_fcmp_0_no_dsp_32.vhd | 6 | 12,778 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fcmp_0_no_dsp_32 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ANN_ap_fcmp_0_no_dsp_32;
ARCHITECTURE ANN_ap_fcmp_0_no_dsp_32_arch OF ANN_ap_fcmp_0_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fcmp_0_no_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fcmp_0_no_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fcmp_0_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=1,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=1,C_RESULT_FRACTION_WIDTH=0,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=1,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=8,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_operation_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_OPERATION TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 1,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 1,
C_RESULT_FRACTION_WIDTH => 0,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 1,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 8,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => s_axis_operation_tvalid,
s_axis_operation_tdata => s_axis_operation_tdata,
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fcmp_0_no_dsp_32_arch;
| gpl-3.0 | 6c32714b7056d8b5f6fdf61a65772f8f | 0.650493 | 2.996717 | false | false | false | false |
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