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// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Portions Copyright (c) 2001 Matrox Graphics Inc.
*
* Version: 1.65 2002/08/14
*
*/
#include "matroxfb_maven.h"
#include "matroxfb_crtc2.h"
#include "matroxfb_misc.h"
#include "matroxfb_DAC1064.h"
#include <linux/matroxfb.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
/* **************************************************** */
static int mem = 8192;
module_param(mem, int, 0);
MODULE_PARM_DESC(mem, "Memory size reserved for dualhead (default=8MB)");
/* **************************************************** */
static int matroxfb_dh_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info* info) {
u_int32_t col;
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
if (regno >= 16)
return 1;
if (m2info->fbcon.var.grayscale) {
/* gray = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
red = CNVT_TOHW(red, m2info->fbcon.var.red.length);
green = CNVT_TOHW(green, m2info->fbcon.var.green.length);
blue = CNVT_TOHW(blue, m2info->fbcon.var.blue.length);
transp = CNVT_TOHW(transp, m2info->fbcon.var.transp.length);
col = (red << m2info->fbcon.var.red.offset) |
(green << m2info->fbcon.var.green.offset) |
(blue << m2info->fbcon.var.blue.offset) |
(transp << m2info->fbcon.var.transp.offset);
switch (m2info->fbcon.var.bits_per_pixel) {
case 16:
m2info->cmap[regno] = col | (col << 16);
break;
case 32:
m2info->cmap[regno] = col;
break;
}
return 0;
#undef m2info
}
static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
struct my_timming* mt,
int mode,
unsigned int pos) {
u_int32_t tmp;
u_int32_t datactl;
struct matrox_fb_info *minfo = m2info->primary_dev;
switch (mode) {
case 15:
tmp = 0x00200000;
break;
case 16:
tmp = 0x00400000;
break;
/* case 32: */
default:
tmp = 0x00800000;
break;
}
tmp |= 0x00000001; /* enable CRTC2 */
datactl = 0;
if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) {
if (minfo->devflags.g450dac) {
tmp |= 0x00000006; /* source from secondary pixel PLL */
/* no vidrst when in monitor mode */
if (minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
tmp |= 0xC0001000; /* Enable H/V vidrst */
}
} else {
tmp |= 0x00000002; /* source from VDOCLK */
tmp |= 0xC0000000; /* enable vvidrst & hvidrst */
/* MGA TVO is our clock source */
}
} else if (minfo->outputs[0].src == MATROXFB_SRC_CRTC2) {
tmp |= 0x00000004; /* source from pixclock */
/* PIXPLL is our clock source */
}
if (minfo->outputs[0].src == MATROXFB_SRC_CRTC2) {
tmp |= 0x00100000; /* connect CRTC2 to DAC */
}
if (mt->interlaced) {
tmp |= 0x02000000; /* interlaced, second field is bigger, as G450 apparently ignores it */
mt->VDisplay >>= 1;
mt->VSyncStart >>= 1;
mt->VSyncEnd >>= 1;
mt->VTotal >>= 1;
}
if ((mt->HTotal & 7) == 2) {
datactl |= 0x00000010;
mt->HTotal &= ~7;
}
tmp |= 0x10000000; /* 0x10000000 is VIDRST polarity */
mga_outl(0x3C14, ((mt->HDisplay - 8) << 16) | (mt->HTotal - 8));
mga_outl(0x3C18, ((mt->HSyncEnd - 8) << 16) | (mt->HSyncStart - 8));
mga_outl(0x3C1C, ((mt->VDisplay - 1) << 16) | (mt->VTotal - 1));
mga_outl(0x3C20, ((mt->VSyncEnd - 1) << 16) | (mt->VSyncStart - 1));
mga_outl(0x3C24, ((mt->VSyncStart) << 16) | (mt->HSyncStart)); /* preload */
{
u_int32_t linelen = m2info->fbcon.var.xres_virtual * (m2info->fbcon.var.bits_per_pixel >> 3);
if (tmp & 0x02000000) {
/* field #0 is smaller, so... */
mga_outl(0x3C2C, pos); /* field #1 vmemory start */
mga_outl(0x3C28, pos + linelen); /* field #0 vmemory start */
linelen <<= 1;
m2info->interlaced = 1;
} else {
mga_outl(0x3C28, pos); /* vmemory start */
m2info->interlaced = 0;
}
mga_outl(0x3C40, linelen);
}
mga_outl(0x3C4C, datactl); /* data control */
if (tmp & 0x02000000) {
int i;
mga_outl(0x3C10, tmp & ~0x02000000);
for (i = 0; i < 2; i++) {
unsigned int nl;
unsigned int lastl = 0;
while ((nl = mga_inl(0x3C48) & 0xFFF) >= lastl) {
lastl = nl;
}
}
}
mga_outl(0x3C10, tmp);
minfo->hw.crtc2.ctl = tmp;
tmp = mt->VDisplay << 16; /* line compare */
if (mt->sync & FB_SYNC_HOR_HIGH_ACT)
tmp |= 0x00000100;
if (mt->sync & FB_SYNC_VERT_HIGH_ACT)
tmp |= 0x00000200;
mga_outl(0x3C44, tmp);
}
static void matroxfb_dh_disable(struct matroxfb_dh_fb_info* m2info) {
struct matrox_fb_info *minfo = m2info->primary_dev;
mga_outl(0x3C10, 0x00000004); /* disable CRTC2, CRTC1->DAC1, PLL as clock source */
minfo->hw.crtc2.ctl = 0x00000004;
}
static void matroxfb_dh_pan_var(struct matroxfb_dh_fb_info* m2info,
struct fb_var_screeninfo* var) {
unsigned int pos;
unsigned int linelen;
unsigned int pixelsize;
struct matrox_fb_info *minfo = m2info->primary_dev;
m2info->fbcon.var.xoffset = var->xoffset;
m2info->fbcon.var.yoffset = var->yoffset;
pixelsize = m2info->fbcon.var.bits_per_pixel >> 3;
linelen = m2info->fbcon.var.xres_virtual * pixelsize;
pos = m2info->fbcon.var.yoffset * linelen + m2info->fbcon.var.xoffset * pixelsize;
pos += m2info->video.offbase;
if (m2info->interlaced) {
mga_outl(0x3C2C, pos);
mga_outl(0x3C28, pos + linelen);
} else {
mga_outl(0x3C28, pos);
}
}
static int matroxfb_dh_decode_var(struct matroxfb_dh_fb_info* m2info,
struct fb_var_screeninfo* var,
int *visual,
int *video_cmap_len,
int *mode) {
unsigned int mask;
unsigned int memlen;
unsigned int vramlen;
switch (var->bits_per_pixel) {
case 16: mask = 0x1F;
break;
case 32: mask = 0x0F;
break;
default: return -EINVAL;
}
vramlen = m2info->video.len_usable;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
var->xres_virtual = (var->xres_virtual + mask) & ~mask;
if (var->yres_virtual > 32767)
return -EINVAL;
memlen = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel >> 3);
if (memlen > vramlen)
return -EINVAL;
if (var->xoffset + var->xres > var->xres_virtual)
var->xoffset = var->xres_virtual - var->xres;
if (var->yoffset + var->yres > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
var->xres &= ~7;
var->left_margin &= ~7;
var->right_margin &= ~7;
var->hsync_len &= ~7;
*mode = var->bits_per_pixel;
if (var->bits_per_pixel == 16) {
if (var->green.length == 5) {
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 15;
var->transp.length = 1;
*mode = 15;
} else {
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
}
} else {
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
}
*visual = FB_VISUAL_TRUECOLOR;
*video_cmap_len = 16;
return 0;
}
static int matroxfb_dh_open(struct fb_info* info, int user) {
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
struct matrox_fb_info *minfo = m2info->primary_dev;
if (minfo) {
int err;
if (minfo->dead) {
return -ENXIO;
}
err = minfo->fbops.fb_open(&minfo->fbcon, user);
if (err) {
return err;
}
}
return 0;
#undef m2info
}
static int matroxfb_dh_release(struct fb_info* info, int user) {
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
int err = 0;
struct matrox_fb_info *minfo = m2info->primary_dev;
if (minfo) {
err = minfo->fbops.fb_release(&minfo->fbcon, user);
}
return err;
#undef m2info
}
/*
* This function is called before the register_framebuffer so
* no locking is needed.
*/
static void matroxfb_dh_init_fix(struct matroxfb_dh_fb_info *m2info)
{
struct fb_fix_screeninfo *fix = &m2info->fbcon.fix;
strcpy(fix->id, "MATROX DH");
fix->smem_start = m2info->video.base;
fix->smem_len = m2info->video.len_usable;
fix->ypanstep = 1;
fix->ywrapstep = 0;
fix->xpanstep = 8; /* TBD */
fix->mmio_start = m2info->mmio.base;
fix->mmio_len = m2info->mmio.len;
fix->accel = 0; /* no accel... */
}
static int matroxfb_dh_check_var(struct fb_var_screeninfo* var, struct fb_info* info) {
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
int visual;
int cmap_len;
int mode;
return matroxfb_dh_decode_var(m2info, var, &visual, &cmap_len, &mode);
#undef m2info
}
static int matroxfb_dh_set_par(struct fb_info* info) {
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
int visual;
int cmap_len;
int mode;
int err;
struct fb_var_screeninfo* var = &info->var;
struct matrox_fb_info *minfo = m2info->primary_dev;
if ((err = matroxfb_dh_decode_var(m2info, var, &visual, &cmap_len, &mode)) != 0)
return err;
/* cmap */
{
m2info->fbcon.screen_base = vaddr_va(m2info->video.vbase);
m2info->fbcon.fix.visual = visual;
m2info->fbcon.fix.type = FB_TYPE_PACKED_PIXELS;
m2info->fbcon.fix.type_aux = 0;
m2info->fbcon.fix.line_length = (var->xres_virtual * var->bits_per_pixel) >> 3;
}
{
struct my_timming mt;
unsigned int pos;
int out;
int cnt;
matroxfb_var2my(&m2info->fbcon.var, &mt);
mt.crtc = MATROXFB_SRC_CRTC2;
/* CRTC2 delay */
mt.delay = 34;
pos = (m2info->fbcon.var.yoffset * m2info->fbcon.var.xres_virtual + m2info->fbcon.var.xoffset) * m2info->fbcon.var.bits_per_pixel >> 3;
pos += m2info->video.offbase;
cnt = 0;
down_read(&minfo->altout.lock);
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
cnt++;
if (minfo->outputs[out].output->compute) {
minfo->outputs[out].output->compute(minfo->outputs[out].data, &mt);
}
}
}
minfo->crtc2.pixclock = mt.pixclock;
minfo->crtc2.mnp = mt.mnp;
up_read(&minfo->altout.lock);
if (cnt) {
matroxfb_dh_restore(m2info, &mt, mode, pos);
} else {
matroxfb_dh_disable(m2info);
}
DAC1064_global_init(minfo);
DAC1064_global_restore(minfo);
down_read(&minfo->altout.lock);
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2 &&
minfo->outputs[out].output->program) {
minfo->outputs[out].output->program(minfo->outputs[out].data);
}
}
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2 &&
minfo->outputs[out].output->start) {
minfo->outputs[out].output->start(minfo->outputs[out].data);
}
}
up_read(&minfo->altout.lock);
}
m2info->initialized = 1;
return 0;
#undef m2info
}
static int matroxfb_dh_pan_display(struct fb_var_screeninfo* var, struct fb_info* info) {
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
matroxfb_dh_pan_var(m2info, var);
return 0;
#undef m2info
}
static int matroxfb_dh_get_vblank(const struct matroxfb_dh_fb_info* m2info, struct fb_vblank* vblank) {
struct matrox_fb_info *minfo = m2info->primary_dev;
matroxfb_enable_irq(minfo, 0);
memset(vblank, 0, sizeof(*vblank));
vblank->flags = FB_VBLANK_HAVE_VCOUNT | FB_VBLANK_HAVE_VBLANK;
/* mask out reserved bits + field number (odd/even) */
vblank->vcount = mga_inl(0x3C48) & 0x000007FF;
/* compatibility stuff */
if (vblank->vcount >= m2info->fbcon.var.yres)
vblank->flags |= FB_VBLANK_VBLANKING;
if (test_bit(0, &minfo->irq_flags)) {
vblank->flags |= FB_VBLANK_HAVE_COUNT;
/* Only one writer, aligned int value...
it should work without lock and without atomic_t */
vblank->count = minfo->crtc2.vsync.cnt;
}
return 0;
}
static int matroxfb_dh_ioctl(struct fb_info *info,
unsigned int cmd,
unsigned long arg)
{
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
struct matrox_fb_info *minfo = m2info->primary_dev;
DBG(__func__)
switch (cmd) {
case FBIOGET_VBLANK:
{
struct fb_vblank vblank;
int err;
err = matroxfb_dh_get_vblank(m2info, &vblank);
if (err)
return err;
if (copy_to_user((void __user *)arg, &vblank, sizeof(vblank)))
return -EFAULT;
return 0;
}
case FBIO_WAITFORVSYNC:
{
u_int32_t crt;
if (get_user(crt, (u_int32_t __user *)arg))
return -EFAULT;
if (crt != 0)
return -ENODEV;
return matroxfb_wait_for_sync(minfo, 1);
}
case MATROXFB_SET_OUTPUT_MODE:
case MATROXFB_GET_OUTPUT_MODE:
case MATROXFB_GET_ALL_OUTPUTS:
{
return minfo->fbcon.fbops->fb_ioctl(&minfo->fbcon, cmd, arg);
}
case MATROXFB_SET_OUTPUT_CONNECTION:
{
u_int32_t tmp;
int out;
int changes;
if (get_user(tmp, (u_int32_t __user *)arg))
return -EFAULT;
for (out = 0; out < 32; out++) {
if (tmp & (1 << out)) {
if (out >= MATROXFB_MAX_OUTPUTS)
return -ENXIO;
if (!minfo->outputs[out].output)
return -ENXIO;
switch (minfo->outputs[out].src) {
case MATROXFB_SRC_NONE:
case MATROXFB_SRC_CRTC2:
break;
default:
return -EBUSY;
}
}
}
if (minfo->devflags.panellink) {
if (tmp & MATROXFB_OUTPUT_CONN_DFP)
return -EINVAL;
if ((minfo->outputs[2].src == MATROXFB_SRC_CRTC1) && tmp)
return -EBUSY;
}
changes = 0;
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (tmp & (1 << out)) {
if (minfo->outputs[out].src != MATROXFB_SRC_CRTC2) {
changes = 1;
minfo->outputs[out].src = MATROXFB_SRC_CRTC2;
}
} else if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
changes = 1;
minfo->outputs[out].src = MATROXFB_SRC_NONE;
}
}
if (!changes)
return 0;
matroxfb_dh_set_par(info);
return 0;
}
case MATROXFB_GET_OUTPUT_CONNECTION:
{
u_int32_t conn = 0;
int out;
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
conn |= 1 << out;
}
}
if (put_user(conn, (u_int32_t __user *)arg))
return -EFAULT;
return 0;
}
case MATROXFB_GET_AVAILABLE_OUTPUTS:
{
u_int32_t tmp = 0;
int out;
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (minfo->outputs[out].output) {
switch (minfo->outputs[out].src) {
case MATROXFB_SRC_NONE:
case MATROXFB_SRC_CRTC2:
tmp |= 1 << out;
break;
}
}
}
if (minfo->devflags.panellink) {
tmp &= ~MATROXFB_OUTPUT_CONN_DFP;
if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1) {
tmp = 0;
}
}
if (put_user(tmp, (u_int32_t __user *)arg))
return -EFAULT;
return 0;
}
}
return -ENOTTY;
#undef m2info
}
static int matroxfb_dh_blank(int blank, struct fb_info* info) {
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
switch (blank) {
case 1:
case 2:
case 3:
case 4:
default:;
}
/* do something... */
return 0;
#undef m2info
}
static const struct fb_ops matroxfb_dh_ops = {
.owner = THIS_MODULE,
.fb_open = matroxfb_dh_open,
.fb_release = matroxfb_dh_release,
.fb_check_var = matroxfb_dh_check_var,
.fb_set_par = matroxfb_dh_set_par,
.fb_setcolreg = matroxfb_dh_setcolreg,
.fb_pan_display =matroxfb_dh_pan_display,
.fb_blank = matroxfb_dh_blank,
.fb_ioctl = matroxfb_dh_ioctl,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static struct fb_var_screeninfo matroxfb_dh_defined = {
640,480,640,480,/* W,H, virtual W,H */
0,0, /* offset */
32, /* depth */
0, /* gray */
{0,0,0}, /* R */
{0,0,0}, /* G */
{0,0,0}, /* B */
{0,0,0}, /* alpha */
0, /* nonstd */
FB_ACTIVATE_NOW,
-1,-1, /* display size */
0, /* accel flags */
39721L,48L,16L,33L,10L,
96L,2,0, /* no sync info */
FB_VMODE_NONINTERLACED,
};
static int matroxfb_dh_regit(const struct matrox_fb_info *minfo,
struct matroxfb_dh_fb_info *m2info)
{
#define minfo (m2info->primary_dev)
void* oldcrtc2;
m2info->fbcon.fbops = &matroxfb_dh_ops;
m2info->fbcon.flags = FBINFO_HWACCEL_XPAN |
FBINFO_HWACCEL_YPAN;
m2info->fbcon.pseudo_palette = m2info->cmap;
fb_alloc_cmap(&m2info->fbcon.cmap, 256, 1);
if (mem < 64)
mem *= 1024;
if (mem < 64*1024)
mem *= 1024;
mem &= ~0x00000FFF; /* PAGE_MASK? */
if (minfo->video.len_usable + mem <= minfo->video.len)
m2info->video.offbase = minfo->video.len - mem;
else if (minfo->video.len < mem) {
return -ENOMEM;
} else { /* check yres on first head... */
m2info->video.borrowed = mem;
minfo->video.len_usable -= mem;
m2info->video.offbase = minfo->video.len_usable;
}
m2info->video.base = minfo->video.base + m2info->video.offbase;
m2info->video.len = m2info->video.len_usable = m2info->video.len_maximum = mem;
m2info->video.vbase.vaddr = vaddr_va(minfo->video.vbase) + m2info->video.offbase;
m2info->mmio.base = minfo->mmio.base;
m2info->mmio.vbase = minfo->mmio.vbase;
m2info->mmio.len = minfo->mmio.len;
matroxfb_dh_init_fix(m2info);
if (register_framebuffer(&m2info->fbcon)) {
return -ENXIO;
}
if (!m2info->initialized)
fb_set_var(&m2info->fbcon, &matroxfb_dh_defined);
down_write(&minfo->crtc2.lock);
oldcrtc2 = minfo->crtc2.info;
minfo->crtc2.info = m2info;
up_write(&minfo->crtc2.lock);
if (oldcrtc2) {
printk(KERN_ERR "matroxfb_crtc2: Internal consistency check failed: crtc2 already present: %p\n",
oldcrtc2);
}
return 0;
#undef minfo
}
/* ************************** */
static int matroxfb_dh_registerfb(struct matroxfb_dh_fb_info* m2info) {
#define minfo (m2info->primary_dev)
if (matroxfb_dh_regit(minfo, m2info)) {
printk(KERN_ERR "matroxfb_crtc2: secondary head failed to register\n");
return -1;
}
printk(KERN_INFO "matroxfb_crtc2: secondary head of fb%u was registered as fb%u\n",
minfo->fbcon.node, m2info->fbcon.node);
m2info->fbcon_registered = 1;
return 0;
#undef minfo
}
static void matroxfb_dh_deregisterfb(struct matroxfb_dh_fb_info* m2info) {
#define minfo (m2info->primary_dev)
if (m2info->fbcon_registered) {
int id;
struct matroxfb_dh_fb_info* crtc2;
down_write(&minfo->crtc2.lock);
crtc2 = minfo->crtc2.info;
if (crtc2 == m2info)
minfo->crtc2.info = NULL;
up_write(&minfo->crtc2.lock);
if (crtc2 != m2info) {
printk(KERN_ERR "matroxfb_crtc2: Internal consistency check failed: crtc2 mismatch at unload: %p != %p\n",
crtc2, m2info);
printk(KERN_ERR "matroxfb_crtc2: Expect kernel crash after module unload.\n");
return;
}
id = m2info->fbcon.node;
unregister_framebuffer(&m2info->fbcon);
/* return memory back to primary head */
minfo->video.len_usable += m2info->video.borrowed;
printk(KERN_INFO "matroxfb_crtc2: fb%u unregistered\n", id);
m2info->fbcon_registered = 0;
}
#undef minfo
}
static void* matroxfb_crtc2_probe(struct matrox_fb_info* minfo) {
struct matroxfb_dh_fb_info* m2info;
/* hardware is CRTC2 incapable... */
if (!minfo->devflags.crtc2)
return NULL;
m2info = kzalloc(sizeof(*m2info), GFP_KERNEL);
if (!m2info)
return NULL;
m2info->primary_dev = minfo;
if (matroxfb_dh_registerfb(m2info)) {
kfree(m2info);
printk(KERN_ERR "matroxfb_crtc2: CRTC2 framebuffer failed to register\n");
return NULL;
}
return m2info;
}
static void matroxfb_crtc2_remove(struct matrox_fb_info* minfo, void* crtc2) {
matroxfb_dh_deregisterfb(crtc2);
kfree(crtc2);
}
static struct matroxfb_driver crtc2 = {
.name = "Matrox G400 CRTC2",
.probe = matroxfb_crtc2_probe,
.remove = matroxfb_crtc2_remove };
static int matroxfb_crtc2_init(void) {
if (fb_get_options("matrox_crtc2fb", NULL))
return -ENODEV;
matroxfb_register_driver(&crtc2);
return 0;
}
static void matroxfb_crtc2_exit(void) {
matroxfb_unregister_driver(&crtc2);
}
MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <[email protected]>");
MODULE_DESCRIPTION("Matrox G400 CRTC2 driver");
MODULE_LICENSE("GPL");
module_init(matroxfb_crtc2_init);
module_exit(matroxfb_crtc2_exit);
/* we do not have __setup() yet */
| linux-master | drivers/video/fbdev/matrox/matroxfb_crtc2.c |
/*
*
* Hardware accelerated Matrox PCI cards - G450/G550 PLL control.
*
* (c) 2001-2002 Petr Vandrovec <[email protected]>
*
* Portions Copyright (c) 2001 Matrox Graphics Inc.
*
* Version: 1.64 2002/06/10
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#include "g450_pll.h"
#include "matroxfb_DAC1064.h"
static inline unsigned int g450_vco2f(unsigned char p, unsigned int fvco) {
return (p & 0x40) ? fvco : fvco >> ((p & 3) + 1);
}
static inline unsigned int g450_f2vco(unsigned char p, unsigned int fin) {
return (p & 0x40) ? fin : fin << ((p & 3) + 1);
}
static unsigned int g450_mnp2vco(const struct matrox_fb_info *minfo,
unsigned int mnp)
{
unsigned int m, n;
m = ((mnp >> 16) & 0x0FF) + 1;
n = ((mnp >> 7) & 0x1FE) + 4;
return (minfo->features.pll.ref_freq * n + (m >> 1)) / m;
}
unsigned int g450_mnp2f(const struct matrox_fb_info *minfo, unsigned int mnp)
{
return g450_vco2f(mnp, g450_mnp2vco(minfo, mnp));
}
static inline unsigned int pll_freq_delta(unsigned int f1, unsigned int f2) {
if (f2 < f1) {
f2 = f1 - f2;
} else {
f2 = f2 - f1;
}
return f2;
}
#define NO_MORE_MNP 0x01FFFFFF
#define G450_MNP_FREQBITS (0xFFFFFF43) /* do not mask high byte so we'll catch NO_MORE_MNP */
static unsigned int g450_nextpll(const struct matrox_fb_info *minfo,
const struct matrox_pll_limits *pi,
unsigned int *fvco, unsigned int mnp)
{
unsigned int m, n, p;
unsigned int tvco = *fvco;
m = (mnp >> 16) & 0xFF;
p = mnp & 0xFF;
do {
if (m == 0 || m == 0xFF) {
if (m == 0) {
if (p & 0x40) {
return NO_MORE_MNP;
}
if (p & 3) {
p--;
} else {
p = 0x40;
}
tvco >>= 1;
if (tvco < pi->vcomin) {
return NO_MORE_MNP;
}
*fvco = tvco;
}
p &= 0x43;
if (tvco < 550000) {
/* p |= 0x00; */
} else if (tvco < 700000) {
p |= 0x08;
} else if (tvco < 1000000) {
p |= 0x10;
} else if (tvco < 1150000) {
p |= 0x18;
} else {
p |= 0x20;
}
m = 9;
} else {
m--;
}
n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2;
} while (n < 0x03 || n > 0x7A);
return (m << 16) | (n << 8) | p;
}
static unsigned int g450_firstpll(const struct matrox_fb_info *minfo,
const struct matrox_pll_limits *pi,
unsigned int *vco, unsigned int fout)
{
unsigned int p;
unsigned int vcomax;
vcomax = pi->vcomax;
if (fout > (vcomax / 2)) {
if (fout > vcomax) {
*vco = vcomax;
} else {
*vco = fout;
}
p = 0x40;
} else {
unsigned int tvco;
p = 3;
tvco = g450_f2vco(p, fout);
while (p && (tvco > vcomax)) {
p--;
tvco >>= 1;
}
if (tvco < pi->vcomin) {
tvco = pi->vcomin;
}
*vco = tvco;
}
return g450_nextpll(minfo, pi, vco, 0xFF0000 | p);
}
static inline unsigned int g450_setpll(const struct matrox_fb_info *minfo,
unsigned int mnp, unsigned int pll)
{
switch (pll) {
case M_PIXEL_PLL_A:
matroxfb_DAC_out(minfo, M1064_XPIXPLLAM, mnp >> 16);
matroxfb_DAC_out(minfo, M1064_XPIXPLLAN, mnp >> 8);
matroxfb_DAC_out(minfo, M1064_XPIXPLLAP, mnp);
return M1064_XPIXPLLSTAT;
case M_PIXEL_PLL_B:
matroxfb_DAC_out(minfo, M1064_XPIXPLLBM, mnp >> 16);
matroxfb_DAC_out(minfo, M1064_XPIXPLLBN, mnp >> 8);
matroxfb_DAC_out(minfo, M1064_XPIXPLLBP, mnp);
return M1064_XPIXPLLSTAT;
case M_PIXEL_PLL_C:
matroxfb_DAC_out(minfo, M1064_XPIXPLLCM, mnp >> 16);
matroxfb_DAC_out(minfo, M1064_XPIXPLLCN, mnp >> 8);
matroxfb_DAC_out(minfo, M1064_XPIXPLLCP, mnp);
return M1064_XPIXPLLSTAT;
case M_SYSTEM_PLL:
matroxfb_DAC_out(minfo, DAC1064_XSYSPLLM, mnp >> 16);
matroxfb_DAC_out(minfo, DAC1064_XSYSPLLN, mnp >> 8);
matroxfb_DAC_out(minfo, DAC1064_XSYSPLLP, mnp);
return DAC1064_XSYSPLLSTAT;
case M_VIDEO_PLL:
matroxfb_DAC_out(minfo, M1064_XVIDPLLM, mnp >> 16);
matroxfb_DAC_out(minfo, M1064_XVIDPLLN, mnp >> 8);
matroxfb_DAC_out(minfo, M1064_XVIDPLLP, mnp);
return M1064_XVIDPLLSTAT;
}
return 0;
}
static inline unsigned int g450_cmppll(const struct matrox_fb_info *minfo,
unsigned int mnp, unsigned int pll)
{
unsigned char m = mnp >> 16;
unsigned char n = mnp >> 8;
unsigned char p = mnp;
switch (pll) {
case M_PIXEL_PLL_A:
return (matroxfb_DAC_in(minfo, M1064_XPIXPLLAM) != m ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLAN) != n ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLAP) != p);
case M_PIXEL_PLL_B:
return (matroxfb_DAC_in(minfo, M1064_XPIXPLLBM) != m ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLBN) != n ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLBP) != p);
case M_PIXEL_PLL_C:
return (matroxfb_DAC_in(minfo, M1064_XPIXPLLCM) != m ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLCN) != n ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLCP) != p);
case M_SYSTEM_PLL:
return (matroxfb_DAC_in(minfo, DAC1064_XSYSPLLM) != m ||
matroxfb_DAC_in(minfo, DAC1064_XSYSPLLN) != n ||
matroxfb_DAC_in(minfo, DAC1064_XSYSPLLP) != p);
case M_VIDEO_PLL:
return (matroxfb_DAC_in(minfo, M1064_XVIDPLLM) != m ||
matroxfb_DAC_in(minfo, M1064_XVIDPLLN) != n ||
matroxfb_DAC_in(minfo, M1064_XVIDPLLP) != p);
}
return 1;
}
static inline int g450_isplllocked(const struct matrox_fb_info *minfo,
unsigned int regidx)
{
unsigned int j;
for (j = 0; j < 1000; j++) {
if (matroxfb_DAC_in(minfo, regidx) & 0x40) {
unsigned int r = 0;
int i;
for (i = 0; i < 100; i++) {
r += matroxfb_DAC_in(minfo, regidx) & 0x40;
}
return r >= (90 * 0x40);
}
/* udelay(1)... but DAC_in is much slower... */
}
return 0;
}
static int g450_testpll(const struct matrox_fb_info *minfo, unsigned int mnp,
unsigned int pll)
{
return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll));
}
static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) {
switch (pll) {
case M_SYSTEM_PLL:
hw->DACclk[3] = mnp >> 16;
hw->DACclk[4] = mnp >> 8;
hw->DACclk[5] = mnp;
break;
}
}
void matroxfb_g450_setpll_cond(struct matrox_fb_info *minfo, unsigned int mnp,
unsigned int pll)
{
if (g450_cmppll(minfo, mnp, pll)) {
g450_setpll(minfo, mnp, pll);
}
}
static inline unsigned int g450_findworkingpll(struct matrox_fb_info *minfo,
unsigned int pll,
unsigned int *mnparray,
unsigned int mnpcount)
{
unsigned int found = 0;
unsigned int idx;
unsigned int mnpfound = mnparray[0];
for (idx = 0; idx < mnpcount; idx++) {
unsigned int sarray[3];
unsigned int *sptr;
{
unsigned int mnp;
sptr = sarray;
mnp = mnparray[idx];
if (mnp & 0x38) {
*sptr++ = mnp - 8;
}
if ((mnp & 0x38) != 0x38) {
*sptr++ = mnp + 8;
}
*sptr = mnp;
}
while (sptr >= sarray) {
unsigned int mnp = *sptr--;
if (g450_testpll(minfo, mnp - 0x0300, pll) &&
g450_testpll(minfo, mnp + 0x0300, pll) &&
g450_testpll(minfo, mnp - 0x0200, pll) &&
g450_testpll(minfo, mnp + 0x0200, pll) &&
g450_testpll(minfo, mnp - 0x0100, pll) &&
g450_testpll(minfo, mnp + 0x0100, pll)) {
if (g450_testpll(minfo, mnp, pll)) {
return mnp;
}
} else if (!found && g450_testpll(minfo, mnp, pll)) {
mnpfound = mnp;
found = 1;
}
}
}
g450_setpll(minfo, mnpfound, pll);
return mnpfound;
}
static void g450_addcache(struct matrox_pll_cache* ci, unsigned int mnp_key, unsigned int mnp_value) {
if (++ci->valid > ARRAY_SIZE(ci->data)) {
ci->valid = ARRAY_SIZE(ci->data);
}
memmove(ci->data + 1, ci->data, (ci->valid - 1) * sizeof(*ci->data));
ci->data[0].mnp_key = mnp_key & G450_MNP_FREQBITS;
ci->data[0].mnp_value = mnp_value;
}
static int g450_checkcache(struct matrox_fb_info *minfo,
struct matrox_pll_cache *ci, unsigned int mnp_key)
{
unsigned int i;
mnp_key &= G450_MNP_FREQBITS;
for (i = 0; i < ci->valid; i++) {
if (ci->data[i].mnp_key == mnp_key) {
unsigned int mnp;
mnp = ci->data[i].mnp_value;
if (i) {
memmove(ci->data + 1, ci->data, i * sizeof(*ci->data));
ci->data[0].mnp_key = mnp_key;
ci->data[0].mnp_value = mnp;
}
return mnp;
}
}
return NO_MORE_MNP;
}
static int __g450_setclk(struct matrox_fb_info *minfo, unsigned int fout,
unsigned int pll, unsigned int *mnparray,
unsigned int *deltaarray)
{
unsigned int mnpcount;
const struct matrox_pll_limits* pi;
struct matrox_pll_cache* ci;
switch (pll) {
case M_PIXEL_PLL_A:
case M_PIXEL_PLL_B:
case M_PIXEL_PLL_C:
{
u_int8_t tmp, xpwrctrl;
unsigned long flags;
matroxfb_DAC_lock_irqsave(flags);
xpwrctrl = matroxfb_DAC_in(minfo, M1064_XPWRCTRL);
matroxfb_DAC_out(minfo, M1064_XPWRCTRL, xpwrctrl & ~M1064_XPWRCTRL_PANELPDN);
mga_outb(M_SEQ_INDEX, M_SEQ1);
mga_outb(M_SEQ_DATA, mga_inb(M_SEQ_DATA) | M_SEQ1_SCROFF);
tmp = matroxfb_DAC_in(minfo, M1064_XPIXCLKCTRL);
tmp |= M1064_XPIXCLKCTRL_DIS;
if (!(tmp & M1064_XPIXCLKCTRL_PLL_UP)) {
tmp |= M1064_XPIXCLKCTRL_PLL_UP;
}
matroxfb_DAC_out(minfo, M1064_XPIXCLKCTRL, tmp);
/* DVI PLL preferred for frequencies up to
panel link max, standard PLL otherwise */
if (fout >= minfo->max_pixel_clock_panellink)
tmp = 0;
else tmp =
M1064_XDVICLKCTRL_DVIDATAPATHSEL |
M1064_XDVICLKCTRL_C1DVICLKSEL |
M1064_XDVICLKCTRL_C1DVICLKEN |
M1064_XDVICLKCTRL_DVILOOPCTL |
M1064_XDVICLKCTRL_P1LOOPBWDTCTL;
/* Setting this breaks PC systems so don't do it */
/* matroxfb_DAC_out(minfo, M1064_XDVICLKCTRL, tmp); */
matroxfb_DAC_out(minfo, M1064_XPWRCTRL,
xpwrctrl);
matroxfb_DAC_unlock_irqrestore(flags);
}
{
u_int8_t misc;
misc = mga_inb(M_MISC_REG_READ) & ~0x0C;
switch (pll) {
case M_PIXEL_PLL_A:
break;
case M_PIXEL_PLL_B:
misc |= 0x04;
break;
default:
misc |= 0x0C;
break;
}
mga_outb(M_MISC_REG, misc);
}
pi = &minfo->limits.pixel;
ci = &minfo->cache.pixel;
break;
case M_SYSTEM_PLL:
{
u_int32_t opt;
pci_read_config_dword(minfo->pcidev, PCI_OPTION_REG, &opt);
if (!(opt & 0x20)) {
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, opt | 0x20);
}
}
pi = &minfo->limits.system;
ci = &minfo->cache.system;
break;
case M_VIDEO_PLL:
{
u_int8_t tmp;
unsigned int mnp;
unsigned long flags;
matroxfb_DAC_lock_irqsave(flags);
tmp = matroxfb_DAC_in(minfo, M1064_XPWRCTRL);
if (!(tmp & 2)) {
matroxfb_DAC_out(minfo, M1064_XPWRCTRL, tmp | 2);
}
mnp = matroxfb_DAC_in(minfo, M1064_XPIXPLLCM) << 16;
mnp |= matroxfb_DAC_in(minfo, M1064_XPIXPLLCN) << 8;
matroxfb_DAC_unlock_irqrestore(flags);
}
pi = &minfo->limits.video;
ci = &minfo->cache.video;
break;
default:
return -EINVAL;
}
mnpcount = 0;
{
unsigned int mnp;
unsigned int xvco;
for (mnp = g450_firstpll(minfo, pi, &xvco, fout); mnp != NO_MORE_MNP; mnp = g450_nextpll(minfo, pi, &xvco, mnp)) {
unsigned int idx;
unsigned int vco;
unsigned int delta;
vco = g450_mnp2vco(minfo, mnp);
delta = pll_freq_delta(fout, g450_vco2f(mnp, vco));
for (idx = mnpcount; idx > 0; idx--) {
/* == is important; due to nextpll algorithm we get
sorted equally good frequencies from lower VCO
frequency to higher - with <= lowest wins, while
with < highest one wins */
if (delta <= deltaarray[idx-1]) {
/* all else being equal except VCO,
* choose VCO not near (within 1/16th or so) VCOmin
* (freqs near VCOmin aren't as stable)
*/
if (delta == deltaarray[idx-1]
&& vco != g450_mnp2vco(minfo, mnparray[idx-1])
&& vco < (pi->vcomin * 17 / 16)) {
break;
}
mnparray[idx] = mnparray[idx-1];
deltaarray[idx] = deltaarray[idx-1];
} else {
break;
}
}
mnparray[idx] = mnp;
deltaarray[idx] = delta;
mnpcount++;
}
}
/* VideoPLL and PixelPLL matched: do nothing... In all other cases we should get at least one frequency */
if (!mnpcount) {
return -EBUSY;
}
{
unsigned long flags;
unsigned int mnp;
matroxfb_DAC_lock_irqsave(flags);
mnp = g450_checkcache(minfo, ci, mnparray[0]);
if (mnp != NO_MORE_MNP) {
matroxfb_g450_setpll_cond(minfo, mnp, pll);
} else {
mnp = g450_findworkingpll(minfo, pll, mnparray, mnpcount);
g450_addcache(ci, mnparray[0], mnp);
}
updatehwstate_clk(&minfo->hw, mnp, pll);
matroxfb_DAC_unlock_irqrestore(flags);
return mnp;
}
}
/* It must be greater than number of possible PLL values.
* Currently there is 5(p) * 10(m) = 50 possible values. */
#define MNP_TABLE_SIZE 64
int matroxfb_g450_setclk(struct matrox_fb_info *minfo, unsigned int fout,
unsigned int pll)
{
unsigned int* arr;
arr = kmalloc(sizeof(*arr) * MNP_TABLE_SIZE * 2, GFP_KERNEL);
if (arr) {
int r;
r = __g450_setclk(minfo, fout, pll, arr, arr + MNP_TABLE_SIZE);
kfree(arr);
return r;
}
return -ENOMEM;
}
EXPORT_SYMBOL(matroxfb_g450_setclk);
EXPORT_SYMBOL(g450_mnp2f);
EXPORT_SYMBOL(matroxfb_g450_setpll_cond);
MODULE_AUTHOR("(c) 2001-2002 Petr Vandrovec <[email protected]>");
MODULE_DESCRIPTION("Matrox G450/G550 PLL driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/matrox/g450_pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Version: 1.64 2002/06/10
*
* See matroxfb_base.c for contributors.
*
*/
#include "matroxfb_base.h"
#include "matroxfb_maven.h"
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/i2c-algo-bit.h>
/* MGA-TVO I2C for G200, G400 */
#define MAT_CLK 0x20
#define MAT_DATA 0x10
/* primary head DDC for Mystique(?), G100, G200, G400 */
#define DDC1_CLK 0x08
#define DDC1_DATA 0x02
/* primary head DDC for Millennium, Millennium II */
#define DDC1B_CLK 0x10
#define DDC1B_DATA 0x04
/* secondary head DDC for G400 */
#define DDC2_CLK 0x04
#define DDC2_DATA 0x01
/******************************************************/
struct matroxfb_dh_maven_info {
struct i2c_bit_adapter maven;
struct i2c_bit_adapter ddc1;
struct i2c_bit_adapter ddc2;
};
static int matroxfb_read_gpio(struct matrox_fb_info* minfo) {
unsigned long flags;
int v;
matroxfb_DAC_lock_irqsave(flags);
v = matroxfb_DAC_in(minfo, DAC_XGENIODATA);
matroxfb_DAC_unlock_irqrestore(flags);
return v;
}
static void matroxfb_set_gpio(struct matrox_fb_info* minfo, int mask, int val) {
unsigned long flags;
int v;
matroxfb_DAC_lock_irqsave(flags);
v = (matroxfb_DAC_in(minfo, DAC_XGENIOCTRL) & mask) | val;
matroxfb_DAC_out(minfo, DAC_XGENIOCTRL, v);
/* We must reset GENIODATA very often... XFree plays with this register */
matroxfb_DAC_out(minfo, DAC_XGENIODATA, 0x00);
matroxfb_DAC_unlock_irqrestore(flags);
}
/* software I2C functions */
static inline void matroxfb_i2c_set(struct matrox_fb_info* minfo, int mask, int state) {
if (state)
state = 0;
else
state = mask;
matroxfb_set_gpio(minfo, ~mask, state);
}
static void matroxfb_gpio_setsda(void* data, int state) {
struct i2c_bit_adapter* b = data;
matroxfb_i2c_set(b->minfo, b->mask.data, state);
}
static void matroxfb_gpio_setscl(void* data, int state) {
struct i2c_bit_adapter* b = data;
matroxfb_i2c_set(b->minfo, b->mask.clock, state);
}
static int matroxfb_gpio_getsda(void* data) {
struct i2c_bit_adapter* b = data;
return (matroxfb_read_gpio(b->minfo) & b->mask.data) ? 1 : 0;
}
static int matroxfb_gpio_getscl(void* data) {
struct i2c_bit_adapter* b = data;
return (matroxfb_read_gpio(b->minfo) & b->mask.clock) ? 1 : 0;
}
static const struct i2c_algo_bit_data matrox_i2c_algo_template =
{
.setsda = matroxfb_gpio_setsda,
.setscl = matroxfb_gpio_setscl,
.getsda = matroxfb_gpio_getsda,
.getscl = matroxfb_gpio_getscl,
.udelay = 10,
.timeout = 100,
};
static int i2c_bus_reg(struct i2c_bit_adapter* b, struct matrox_fb_info* minfo,
unsigned int data, unsigned int clock, const char *name,
int class)
{
int err;
b->minfo = minfo;
b->mask.data = data;
b->mask.clock = clock;
b->adapter.owner = THIS_MODULE;
snprintf(b->adapter.name, sizeof(b->adapter.name), name,
minfo->fbcon.node);
i2c_set_adapdata(&b->adapter, b);
b->adapter.class = class;
b->adapter.algo_data = &b->bac;
b->adapter.dev.parent = &minfo->pcidev->dev;
b->bac = matrox_i2c_algo_template;
b->bac.data = b;
err = i2c_bit_add_bus(&b->adapter);
b->initialized = !err;
return err;
}
static void i2c_bit_bus_del(struct i2c_bit_adapter* b) {
if (b->initialized) {
i2c_del_adapter(&b->adapter);
b->initialized = 0;
}
}
static inline void i2c_maven_done(struct matroxfb_dh_maven_info* minfo2) {
i2c_bit_bus_del(&minfo2->maven);
}
static inline void i2c_ddc1_done(struct matroxfb_dh_maven_info* minfo2) {
i2c_bit_bus_del(&minfo2->ddc1);
}
static inline void i2c_ddc2_done(struct matroxfb_dh_maven_info* minfo2) {
i2c_bit_bus_del(&minfo2->ddc2);
}
static void* i2c_matroxfb_probe(struct matrox_fb_info* minfo) {
int err;
unsigned long flags;
struct matroxfb_dh_maven_info* m2info;
m2info = kzalloc(sizeof(*m2info), GFP_KERNEL);
if (!m2info)
return NULL;
matroxfb_DAC_lock_irqsave(flags);
matroxfb_DAC_out(minfo, DAC_XGENIODATA, 0xFF);
matroxfb_DAC_out(minfo, DAC_XGENIOCTRL, 0x00);
matroxfb_DAC_unlock_irqrestore(flags);
switch (minfo->chip) {
case MGA_2064:
case MGA_2164:
err = i2c_bus_reg(&m2info->ddc1, minfo,
DDC1B_DATA, DDC1B_CLK,
"DDC:fb%u #0", I2C_CLASS_DDC);
break;
default:
err = i2c_bus_reg(&m2info->ddc1, minfo,
DDC1_DATA, DDC1_CLK,
"DDC:fb%u #0", I2C_CLASS_DDC);
break;
}
if (err)
goto fail_ddc1;
if (minfo->devflags.dualhead) {
err = i2c_bus_reg(&m2info->ddc2, minfo,
DDC2_DATA, DDC2_CLK,
"DDC:fb%u #1", I2C_CLASS_DDC);
if (err == -ENODEV) {
printk(KERN_INFO "i2c-matroxfb: VGA->TV plug detected, DDC unavailable.\n");
} else if (err)
printk(KERN_INFO "i2c-matroxfb: Could not register secondary output i2c bus. Continuing anyway.\n");
/* Register maven bus even on G450/G550 */
err = i2c_bus_reg(&m2info->maven, minfo,
MAT_DATA, MAT_CLK, "MAVEN:fb%u", 0);
if (err)
printk(KERN_INFO "i2c-matroxfb: Could not register Maven i2c bus. Continuing anyway.\n");
else {
struct i2c_board_info maven_info = {
I2C_BOARD_INFO("maven", 0x1b),
};
unsigned short const addr_list[2] = {
0x1b, I2C_CLIENT_END
};
i2c_new_scanned_device(&m2info->maven.adapter,
&maven_info, addr_list, NULL);
}
}
return m2info;
fail_ddc1:;
kfree(m2info);
printk(KERN_ERR "i2c-matroxfb: Could not register primary adapter DDC bus.\n");
return NULL;
}
static void i2c_matroxfb_remove(struct matrox_fb_info* minfo, void* data) {
struct matroxfb_dh_maven_info* m2info = data;
i2c_maven_done(m2info);
i2c_ddc2_done(m2info);
i2c_ddc1_done(m2info);
kfree(m2info);
}
static struct matroxfb_driver i2c_matroxfb = {
.node = LIST_HEAD_INIT(i2c_matroxfb.node),
.name = "i2c-matroxfb",
.probe = i2c_matroxfb_probe,
.remove = i2c_matroxfb_remove,
};
static int __init i2c_matroxfb_init(void) {
if (matroxfb_register_driver(&i2c_matroxfb)) {
printk(KERN_ERR "i2c-matroxfb: failed to register driver\n");
return -ENXIO;
}
return 0;
}
static void __exit i2c_matroxfb_exit(void) {
matroxfb_unregister_driver(&i2c_matroxfb);
}
MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <[email protected]>");
MODULE_DESCRIPTION("Support module providing I2C buses present on Matrox videocards");
module_init(i2c_matroxfb_init);
module_exit(i2c_matroxfb_exit);
/* no __setup required */
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/matrox/i2c-matroxfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Portions Copyright (c) 2001 Matrox Graphics Inc.
*
* Version: 1.65 2002/08/14
*
* See matroxfb_base.c for contributors.
*
*/
#include "matroxfb_DAC1064.h"
#include "matroxfb_misc.h"
#include "matroxfb_accel.h"
#include "g450_pll.h"
#include <linux/matroxfb.h>
#ifdef NEED_DAC1064
#define outDAC1064 matroxfb_DAC_out
#define inDAC1064 matroxfb_DAC_in
#define DAC1064_OPT_SCLK_PCI 0x00
#define DAC1064_OPT_SCLK_PLL 0x01
#define DAC1064_OPT_SCLK_EXT 0x02
#define DAC1064_OPT_SCLK_MASK 0x03
#define DAC1064_OPT_GDIV1 0x04 /* maybe it is GDIV2 on G100 ?! */
#define DAC1064_OPT_GDIV3 0x00
#define DAC1064_OPT_MDIV1 0x08
#define DAC1064_OPT_MDIV2 0x00
#define DAC1064_OPT_RESERVED 0x10
static void DAC1064_calcclock(const struct matrox_fb_info *minfo,
unsigned int freq, unsigned int fmax,
unsigned int *in, unsigned int *feed,
unsigned int *post)
{
unsigned int fvco;
unsigned int p;
DBG(__func__)
/* only for devices older than G450 */
fvco = PLL_calcclock(minfo, freq, fmax, in, feed, &p);
p = (1 << p) - 1;
if (fvco <= 100000)
;
else if (fvco <= 140000)
p |= 0x08;
else if (fvco <= 180000)
p |= 0x10;
else
p |= 0x18;
*post = p;
}
/* they must be in POS order */
static const unsigned char MGA1064_DAC_regs[] = {
M1064_XCURADDL, M1064_XCURADDH, M1064_XCURCTRL,
M1064_XCURCOL0RED, M1064_XCURCOL0GREEN, M1064_XCURCOL0BLUE,
M1064_XCURCOL1RED, M1064_XCURCOL1GREEN, M1064_XCURCOL1BLUE,
M1064_XCURCOL2RED, M1064_XCURCOL2GREEN, M1064_XCURCOL2BLUE,
DAC1064_XVREFCTRL, M1064_XMULCTRL, M1064_XPIXCLKCTRL, M1064_XGENCTRL,
M1064_XMISCCTRL,
M1064_XGENIOCTRL, M1064_XGENIODATA, M1064_XZOOMCTRL, M1064_XSENSETEST,
M1064_XCRCBITSEL,
M1064_XCOLKEYMASKL, M1064_XCOLKEYMASKH, M1064_XCOLKEYL, M1064_XCOLKEYH };
static const unsigned char MGA1064_DAC[] = {
0x00, 0x00, M1064_XCURCTRL_DIS,
0x00, 0x00, 0x00, /* black */
0xFF, 0xFF, 0xFF, /* white */
0xFF, 0x00, 0x00, /* red */
0x00, 0,
M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_PLL,
M1064_XGENCTRL_VS_0 | M1064_XGENCTRL_ALPHA_DIS | M1064_XGENCTRL_BLACK_0IRE | M1064_XGENCTRL_NO_SYNC_ON_GREEN,
M1064_XMISCCTRL_DAC_8BIT,
0x00, 0x00, M1064_XZOOMCTRL_1, M1064_XSENSETEST_BCOMP | M1064_XSENSETEST_GCOMP | M1064_XSENSETEST_RCOMP | M1064_XSENSETEST_PDOWN,
0x00,
0x00, 0x00, 0xFF, 0xFF};
static void DAC1064_setpclk(struct matrox_fb_info *minfo, unsigned long fout)
{
unsigned int m, n, p;
DBG(__func__)
DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p);
minfo->hw.DACclk[0] = m;
minfo->hw.DACclk[1] = n;
minfo->hw.DACclk[2] = p;
}
static void DAC1064_setmclk(struct matrox_fb_info *minfo, int oscinfo,
unsigned long fmem)
{
u_int32_t mx;
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
if (minfo->devflags.noinit) {
/* read MCLK and give up... */
hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
return;
}
mx = hw->MXoptionReg | 0x00000004;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
mx &= ~0x000000BB;
if (oscinfo & DAC1064_OPT_GDIV1)
mx |= 0x00000008;
if (oscinfo & DAC1064_OPT_MDIV1)
mx |= 0x00000010;
if (oscinfo & DAC1064_OPT_RESERVED)
mx |= 0x00000080;
if ((oscinfo & DAC1064_OPT_SCLK_MASK) == DAC1064_OPT_SCLK_PLL) {
/* select PCI clock until we have setup oscilator... */
int clk;
unsigned int m, n, p;
/* powerup system PLL, select PCI clock */
mx |= 0x00000020;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
mx &= ~0x00000004;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
/* !!! you must not access device if MCLK is not running !!!
Doing so cause immediate PCI lockup :-( Maybe they should
generate ABORT or I/O (parity...) error and Linux should
recover from this... (kill driver/process). But world is not
perfect... */
/* (bit 2 of PCI_OPTION_REG must be 0... and bits 0,1 must not
select PLL... because of PLL can be stopped at this time) */
DAC1064_calcclock(minfo, fmem, minfo->max_pixel_clock, &m, &n, &p);
outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m);
outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n);
outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p);
for (clk = 65536; clk; --clk) {
if (inDAC1064(minfo, DAC1064_XSYSPLLSTAT) & 0x40)
break;
}
if (!clk)
printk(KERN_ERR "matroxfb: aiee, SYSPLL not locked\n");
/* select PLL */
mx |= 0x00000005;
} else {
/* select specified system clock source */
mx |= oscinfo & DAC1064_OPT_SCLK_MASK;
}
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
mx &= ~0x00000004;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx);
hw->MXoptionReg = mx;
}
#ifdef CONFIG_FB_MATROX_G
static void g450_set_plls(struct matrox_fb_info *minfo)
{
u_int32_t c2_ctl;
unsigned int pxc;
struct matrox_hw_state *hw = &minfo->hw;
int pixelmnp;
int videomnp;
c2_ctl = hw->crtc2.ctl & ~0x4007; /* Clear PLL + enable for CRTC2 */
c2_ctl |= 0x0001; /* Enable CRTC2 */
hw->DACreg[POS1064_XPWRCTRL] &= ~0x02; /* Stop VIDEO PLL */
pixelmnp = minfo->crtc1.mnp;
videomnp = minfo->crtc2.mnp;
if (videomnp < 0) {
c2_ctl &= ~0x0001; /* Disable CRTC2 */
hw->DACreg[POS1064_XPWRCTRL] &= ~0x10; /* Powerdown CRTC2 */
} else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) {
c2_ctl |= 0x4002; /* Use reference directly */
} else if (videomnp == pixelmnp) {
c2_ctl |= 0x0004; /* Use pixel PLL */
} else {
if (0 == ((videomnp ^ pixelmnp) & 0xFFFFFF00)) {
/* PIXEL and VIDEO PLL must not use same frequency. We modify N
of PIXEL PLL in such case because of VIDEO PLL may be source
of TVO clocks, and chroma subcarrier is derived from its
pixel clocks */
pixelmnp += 0x000100;
}
c2_ctl |= 0x0006; /* Use video PLL */
hw->DACreg[POS1064_XPWRCTRL] |= 0x02;
outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
matroxfb_g450_setpll_cond(minfo, videomnp, M_VIDEO_PLL);
}
hw->DACreg[POS1064_XPIXCLKCTRL] &= ~M1064_XPIXCLKCTRL_PLL_UP;
if (pixelmnp >= 0) {
hw->DACreg[POS1064_XPIXCLKCTRL] |= M1064_XPIXCLKCTRL_PLL_UP;
outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
matroxfb_g450_setpll_cond(minfo, pixelmnp, M_PIXEL_PLL_C);
}
if (c2_ctl != hw->crtc2.ctl) {
hw->crtc2.ctl = c2_ctl;
mga_outl(0x3C10, c2_ctl);
}
pxc = minfo->crtc1.pixclock;
if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) {
pxc = minfo->crtc2.pixclock;
}
if (minfo->chip == MGA_G550) {
if (pxc < 45000) {
hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-50 */
} else if (pxc < 55000) {
hw->DACreg[POS1064_XPANMODE] = 0x08; /* 34-62 */
} else if (pxc < 70000) {
hw->DACreg[POS1064_XPANMODE] = 0x10; /* 42-78 */
} else if (pxc < 85000) {
hw->DACreg[POS1064_XPANMODE] = 0x18; /* 62-92 */
} else if (pxc < 100000) {
hw->DACreg[POS1064_XPANMODE] = 0x20; /* 74-108 */
} else if (pxc < 115000) {
hw->DACreg[POS1064_XPANMODE] = 0x28; /* 94-122 */
} else if (pxc < 125000) {
hw->DACreg[POS1064_XPANMODE] = 0x30; /* 108-132 */
} else {
hw->DACreg[POS1064_XPANMODE] = 0x38; /* 120-168 */
}
} else {
/* G450 */
if (pxc < 45000) {
hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-54 */
} else if (pxc < 65000) {
hw->DACreg[POS1064_XPANMODE] = 0x08; /* 38-70 */
} else if (pxc < 85000) {
hw->DACreg[POS1064_XPANMODE] = 0x10; /* 56-96 */
} else if (pxc < 105000) {
hw->DACreg[POS1064_XPANMODE] = 0x18; /* 80-114 */
} else if (pxc < 135000) {
hw->DACreg[POS1064_XPANMODE] = 0x20; /* 102-144 */
} else if (pxc < 160000) {
hw->DACreg[POS1064_XPANMODE] = 0x28; /* 132-166 */
} else if (pxc < 175000) {
hw->DACreg[POS1064_XPANMODE] = 0x30; /* 154-182 */
} else {
hw->DACreg[POS1064_XPANMODE] = 0x38; /* 170-204 */
}
}
}
#endif
void DAC1064_global_init(struct matrox_fb_info *minfo)
{
struct matrox_hw_state *hw = &minfo->hw;
hw->DACreg[POS1064_XMISCCTRL] &= M1064_XMISCCTRL_DAC_WIDTHMASK;
hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_LUT_EN;
hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_PLL;
#ifdef CONFIG_FB_MATROX_G
if (minfo->devflags.g450dac) {
hw->DACreg[POS1064_XPWRCTRL] = 0x1F; /* powerup everything */
hw->DACreg[POS1064_XOUTPUTCONN] = 0x00; /* disable outputs */
hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN;
switch (minfo->outputs[0].src) {
case MATROXFB_SRC_CRTC1:
case MATROXFB_SRC_CRTC2:
hw->DACreg[POS1064_XOUTPUTCONN] |= 0x01; /* enable output; CRTC1/2 selection is in CRTC2 ctl */
break;
case MATROXFB_SRC_NONE:
hw->DACreg[POS1064_XMISCCTRL] &= ~M1064_XMISCCTRL_DAC_EN;
break;
}
switch (minfo->outputs[1].src) {
case MATROXFB_SRC_CRTC1:
hw->DACreg[POS1064_XOUTPUTCONN] |= 0x04;
break;
case MATROXFB_SRC_CRTC2:
if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) {
hw->DACreg[POS1064_XOUTPUTCONN] |= 0x08;
} else {
hw->DACreg[POS1064_XOUTPUTCONN] |= 0x0C;
}
break;
case MATROXFB_SRC_NONE:
hw->DACreg[POS1064_XPWRCTRL] &= ~0x01; /* Poweroff DAC2 */
break;
}
switch (minfo->outputs[2].src) {
case MATROXFB_SRC_CRTC1:
hw->DACreg[POS1064_XOUTPUTCONN] |= 0x20;
break;
case MATROXFB_SRC_CRTC2:
hw->DACreg[POS1064_XOUTPUTCONN] |= 0x40;
break;
case MATROXFB_SRC_NONE:
#if 0
/* HELP! If we boot without DFP connected to DVI, we can
poweroff TMDS. But if we boot with DFP connected,
TMDS generated clocks are used instead of ALL pixclocks
available... If someone knows which register
handles it, please reveal this secret to me... */
hw->DACreg[POS1064_XPWRCTRL] &= ~0x04; /* Poweroff TMDS */
#endif
break;
}
/* Now set timming related variables... */
g450_set_plls(minfo);
} else
#endif
{
if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) {
hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKCTRL_SRC_EXT;
hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_MAFC12;
} else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) {
hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_C2_MAFC12;
} else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1)
hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_PANELLINK | G400_XMISCCTRL_VDO_MAFC12;
else
hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_DIS;
if (minfo->outputs[0].src != MATROXFB_SRC_NONE)
hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN;
}
}
void DAC1064_global_restore(struct matrox_fb_info *minfo)
{
struct matrox_hw_state *hw = &minfo->hw;
outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]);
outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]);
if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
outDAC1064(minfo, 0x20, 0x04);
outDAC1064(minfo, 0x1F, minfo->devflags.dfp_type);
if (minfo->devflags.g450dac) {
outDAC1064(minfo, M1064_XSYNCCTRL, 0xCC);
outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]);
outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]);
outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]);
}
}
}
static int DAC1064_init_1(struct matrox_fb_info *minfo, struct my_timming *m)
{
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
memcpy(hw->DACreg, MGA1064_DAC, sizeof(MGA1064_DAC_regs));
switch (minfo->fbcon.var.bits_per_pixel) {
/* case 4: not supported by MGA1064 DAC */
case 8:
hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_8BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
break;
case 16:
if (minfo->fbcon.var.green.length == 5)
hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_15BPP_1BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
else
hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_16BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
break;
case 24:
hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_24BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
break;
case 32:
hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_32BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED;
break;
default:
return 1; /* unsupported depth */
}
hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl;
hw->DACreg[POS1064_XGENCTRL] &= ~M1064_XGENCTRL_SYNC_ON_GREEN_MASK;
hw->DACreg[POS1064_XGENCTRL] |= (m->sync & FB_SYNC_ON_GREEN)?M1064_XGENCTRL_SYNC_ON_GREEN:M1064_XGENCTRL_NO_SYNC_ON_GREEN;
hw->DACreg[POS1064_XCURADDL] = 0;
hw->DACreg[POS1064_XCURADDH] = 0;
DAC1064_global_init(minfo);
return 0;
}
static int DAC1064_init_2(struct matrox_fb_info *minfo, struct my_timming *m)
{
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */
int i;
for (i = 0; i < 256; i++) {
hw->DACpal[i * 3 + 0] = i;
hw->DACpal[i * 3 + 1] = i;
hw->DACpal[i * 3 + 2] = i;
}
} else if (minfo->fbcon.var.bits_per_pixel > 8) {
if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */
int i;
for (i = 0; i < 32; i++) {
/* with p15 == 0 */
hw->DACpal[i * 3 + 0] = i << 3;
hw->DACpal[i * 3 + 1] = i << 3;
hw->DACpal[i * 3 + 2] = i << 3;
/* with p15 == 1 */
hw->DACpal[(i + 128) * 3 + 0] = i << 3;
hw->DACpal[(i + 128) * 3 + 1] = i << 3;
hw->DACpal[(i + 128) * 3 + 2] = i << 3;
}
} else {
int i;
for (i = 0; i < 64; i++) { /* 0..63 */
hw->DACpal[i * 3 + 0] = i << 3;
hw->DACpal[i * 3 + 1] = i << 2;
hw->DACpal[i * 3 + 2] = i << 3;
}
}
} else {
memset(hw->DACpal, 0, 768);
}
return 0;
}
static void DAC1064_restore_1(struct matrox_fb_info *minfo)
{
struct matrox_hw_state *hw = &minfo->hw;
CRITFLAGS
DBG(__func__)
CRITBEGIN
if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) ||
(inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) ||
(inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) {
outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]);
outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]);
outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]);
}
{
unsigned int i;
for (i = 0; i < sizeof(MGA1064_DAC_regs); i++) {
if ((i != POS1064_XPIXCLKCTRL) && (i != POS1064_XMISCCTRL))
outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]);
}
}
DAC1064_global_restore(minfo);
CRITEND
};
static void DAC1064_restore_2(struct matrox_fb_info *minfo)
{
#ifdef DEBUG
unsigned int i;
#endif
DBG(__func__)
#ifdef DEBUG
dprintk(KERN_DEBUG "DAC1064regs ");
for (i = 0; i < sizeof(MGA1064_DAC_regs); i++) {
dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]);
if ((i & 0x7) == 0x7) dprintk(KERN_DEBUG "continuing... ");
}
dprintk(KERN_DEBUG "DAC1064clk ");
for (i = 0; i < 6; i++)
dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]);
dprintk("\n");
#endif
}
static int m1064_compute(void* out, struct my_timming* m) {
#define minfo ((struct matrox_fb_info*)out)
{
int i;
int tmout;
CRITFLAGS
DAC1064_setpclk(minfo, m->pixclock);
CRITBEGIN
for (i = 0; i < 3; i++)
outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]);
for (tmout = 500000; tmout; tmout--) {
if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40)
break;
udelay(10);
}
CRITEND
if (!tmout)
printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
}
#undef minfo
return 0;
}
static struct matrox_altout m1064 = {
.name = "Primary output",
.compute = m1064_compute,
};
#ifdef CONFIG_FB_MATROX_G
static int g450_compute(void* out, struct my_timming* m) {
#define minfo ((struct matrox_fb_info*)out)
if (m->mnp < 0) {
m->mnp = matroxfb_g450_setclk(minfo, m->pixclock, (m->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
if (m->mnp >= 0) {
m->pixclock = g450_mnp2f(minfo, m->mnp);
}
}
#undef minfo
return 0;
}
static struct matrox_altout g450out = {
.name = "Primary output",
.compute = g450_compute,
};
#endif
#endif /* NEED_DAC1064 */
#ifdef CONFIG_FB_MATROX_MYSTIQUE
static int MGA1064_init(struct matrox_fb_info *minfo, struct my_timming *m)
{
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
if (DAC1064_init_1(minfo, m)) return 1;
if (matroxfb_vgaHWinit(minfo, m)) return 1;
hw->MiscOutReg = 0xCB;
if (m->sync & FB_SYNC_HOR_HIGH_ACT)
hw->MiscOutReg &= ~0x40;
if (m->sync & FB_SYNC_VERT_HIGH_ACT)
hw->MiscOutReg &= ~0x80;
if (m->sync & FB_SYNC_COMP_HIGH_ACT) /* should be only FB_SYNC_COMP */
hw->CRTCEXT[3] |= 0x40;
if (DAC1064_init_2(minfo, m)) return 1;
return 0;
}
#endif
#ifdef CONFIG_FB_MATROX_G
static int MGAG100_init(struct matrox_fb_info *minfo, struct my_timming *m)
{
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
if (DAC1064_init_1(minfo, m)) return 1;
hw->MXoptionReg &= ~0x2000;
if (matroxfb_vgaHWinit(minfo, m)) return 1;
hw->MiscOutReg = 0xEF;
if (m->sync & FB_SYNC_HOR_HIGH_ACT)
hw->MiscOutReg &= ~0x40;
if (m->sync & FB_SYNC_VERT_HIGH_ACT)
hw->MiscOutReg &= ~0x80;
if (m->sync & FB_SYNC_COMP_HIGH_ACT) /* should be only FB_SYNC_COMP */
hw->CRTCEXT[3] |= 0x40;
if (DAC1064_init_2(minfo, m)) return 1;
return 0;
}
#endif /* G */
#ifdef CONFIG_FB_MATROX_MYSTIQUE
static void MGA1064_ramdac_init(struct matrox_fb_info *minfo)
{
DBG(__func__)
/* minfo->features.DAC1064.vco_freq_min = 120000; */
minfo->features.pll.vco_freq_min = 62000;
minfo->features.pll.ref_freq = 14318;
minfo->features.pll.feed_div_min = 100;
minfo->features.pll.feed_div_max = 127;
minfo->features.pll.in_div_min = 1;
minfo->features.pll.in_div_max = 31;
minfo->features.pll.post_shift_max = 3;
minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL;
/* maybe cmdline MCLK= ?, doc says gclk=44MHz, mclk=66MHz... it was 55/83 with old values */
DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PLL, 133333);
}
#endif
#ifdef CONFIG_FB_MATROX_G
/* BIOS environ */
static int x7AF4 = 0x10; /* flags, maybe 0x10 = SDRAM, 0x00 = SGRAM??? */
/* G100 wants 0x10, G200 SGRAM does not care... */
#if 0
static int def50 = 0; /* reg50, & 0x0F, & 0x3000 (only 0x0000, 0x1000, 0x2000 (0x3000 disallowed and treated as 0) */
#endif
static void MGAG100_progPixClock(const struct matrox_fb_info *minfo, int flags,
int m, int n, int p)
{
int reg;
int selClk;
int clk;
DBG(__func__)
outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) | M1064_XPIXCLKCTRL_DIS |
M1064_XPIXCLKCTRL_PLL_UP);
switch (flags & 3) {
case 0: reg = M1064_XPIXPLLAM; break;
case 1: reg = M1064_XPIXPLLBM; break;
default: reg = M1064_XPIXPLLCM; break;
}
outDAC1064(minfo, reg++, m);
outDAC1064(minfo, reg++, n);
outDAC1064(minfo, reg, p);
selClk = mga_inb(M_MISC_REG_READ) & ~0xC;
/* there should be flags & 0x03 & case 0/1/else */
/* and we should first select source and after that we should wait for PLL */
/* and we are waiting for PLL with oscilator disabled... Is it right? */
switch (flags & 0x03) {
case 0x00: break;
case 0x01: selClk |= 4; break;
default: selClk |= 0x0C; break;
}
mga_outb(M_MISC_REG, selClk);
for (clk = 500000; clk; clk--) {
if (inDAC1064(minfo, M1064_XPIXPLLSTAT) & 0x40)
break;
udelay(10);
}
if (!clk)
printk(KERN_ERR "matroxfb: Pixel PLL%c not locked after usual time\n", (reg-M1064_XPIXPLLAM-2)/4 + 'A');
selClk = inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_SRC_MASK;
switch (flags & 0x0C) {
case 0x00: selClk |= M1064_XPIXCLKCTRL_SRC_PCI; break;
case 0x04: selClk |= M1064_XPIXCLKCTRL_SRC_PLL; break;
default: selClk |= M1064_XPIXCLKCTRL_SRC_EXT; break;
}
outDAC1064(minfo, M1064_XPIXCLKCTRL, selClk);
outDAC1064(minfo, M1064_XPIXCLKCTRL, inDAC1064(minfo, M1064_XPIXCLKCTRL) & ~M1064_XPIXCLKCTRL_DIS);
}
static void MGAG100_setPixClock(const struct matrox_fb_info *minfo, int flags,
int freq)
{
unsigned int m, n, p;
DBG(__func__)
DAC1064_calcclock(minfo, freq, minfo->max_pixel_clock, &m, &n, &p);
MGAG100_progPixClock(minfo, flags, m, n, p);
}
#endif
#ifdef CONFIG_FB_MATROX_MYSTIQUE
static int MGA1064_preinit(struct matrox_fb_info *minfo)
{
static const int vxres_mystique[] = { 512, 640, 768, 800, 832, 960,
1024, 1152, 1280, 1600, 1664, 1920,
2048, 0};
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
/* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
minfo->capable.text = 1;
minfo->capable.vxres = vxres_mystique;
minfo->outputs[0].output = &m1064;
minfo->outputs[0].src = minfo->outputs[0].default_src;
minfo->outputs[0].data = minfo;
minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
if (minfo->devflags.noinit)
return 0; /* do not modify settings */
hw->MXoptionReg &= 0xC0000100;
hw->MXoptionReg |= 0x00094E20;
if (minfo->devflags.novga)
hw->MXoptionReg &= ~0x00000100;
if (minfo->devflags.nobios)
hw->MXoptionReg &= ~0x40000000;
if (minfo->devflags.nopciretry)
hw->MXoptionReg |= 0x20000000;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
mga_setr(M_SEQ_INDEX, 0x01, 0x20);
mga_outl(M_CTLWTST, 0x00000000);
udelay(200);
mga_outl(M_MACCESS, 0x00008000);
udelay(100);
mga_outl(M_MACCESS, 0x0000C000);
return 0;
}
static void MGA1064_reset(struct matrox_fb_info *minfo)
{
DBG(__func__);
MGA1064_ramdac_init(minfo);
}
#endif
#ifdef CONFIG_FB_MATROX_G
static void g450_mclk_init(struct matrox_fb_info *minfo)
{
/* switch all clocks to PCI source */
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03);
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) ||
((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) ||
((minfo->values.reg.opt3 & 0x300000) == 0x300000)) {
matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL);
} else {
unsigned long flags;
unsigned int pwr;
matroxfb_DAC_lock_irqsave(flags);
pwr = inDAC1064(minfo, M1064_XPWRCTRL) & ~0x02;
outDAC1064(minfo, M1064_XPWRCTRL, pwr);
matroxfb_DAC_unlock_irqrestore(flags);
}
matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL);
/* switch clocks to their real PLL source(s) */
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4);
pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3);
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
}
static void g450_memory_init(struct matrox_fb_info *minfo)
{
/* disable memory refresh */
minfo->hw.MXoptionReg &= ~0x001F8000;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
/* set memory interface parameters */
minfo->hw.MXoptionReg &= ~0x00207E00;
minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2);
mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
/* first set up memory interface with disabled memory interface clocks */
pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U);
mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
mga_outl(M_MACCESS, minfo->values.reg.maccess);
/* start memory clocks */
pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U);
udelay(200);
if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) {
mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000);
}
mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000);
udelay(200);
minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
/* value is written to memory chips only if old != new */
mga_outl(M_PLNWT, 0);
mga_outl(M_PLNWT, ~0);
if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) {
mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core);
}
}
static void g450_preinit(struct matrox_fb_info *minfo)
{
u_int32_t c2ctl;
u_int8_t curctl;
u_int8_t c1ctl;
/* minfo->hw.MXoptionReg = minfo->values.reg.opt; */
minfo->hw.MXoptionReg &= 0xC0000100;
minfo->hw.MXoptionReg |= 0x00000020;
if (minfo->devflags.novga)
minfo->hw.MXoptionReg &= ~0x00000100;
if (minfo->devflags.nobios)
minfo->hw.MXoptionReg &= ~0x40000000;
if (minfo->devflags.nopciretry)
minfo->hw.MXoptionReg |= 0x20000000;
minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
/* Init system clocks */
/* stop crtc2 */
c2ctl = mga_inl(M_C2CTL);
mga_outl(M_C2CTL, c2ctl & ~1);
/* stop cursor */
curctl = inDAC1064(minfo, M1064_XCURCTRL);
outDAC1064(minfo, M1064_XCURCTRL, 0);
/* stop crtc1 */
c1ctl = mga_readr(M_SEQ_INDEX, 1);
mga_setr(M_SEQ_INDEX, 1, c1ctl | 0x20);
g450_mclk_init(minfo);
g450_memory_init(minfo);
/* set legacy VGA clock sources for DOSEmu or VMware... */
matroxfb_g450_setclk(minfo, 25175, M_PIXEL_PLL_A);
matroxfb_g450_setclk(minfo, 28322, M_PIXEL_PLL_B);
/* restore crtc1 */
mga_setr(M_SEQ_INDEX, 1, c1ctl);
/* restore cursor */
outDAC1064(minfo, M1064_XCURCTRL, curctl);
/* restore crtc2 */
mga_outl(M_C2CTL, c2ctl);
return;
}
static int MGAG100_preinit(struct matrox_fb_info *minfo)
{
static const int vxres_g100[] = { 512, 640, 768, 800, 832, 960,
1024, 1152, 1280, 1600, 1664, 1920,
2048, 0};
struct matrox_hw_state *hw = &minfo->hw;
u_int32_t reg50;
#if 0
u_int32_t q;
#endif
DBG(__func__)
/* there are some instabilities if in_div > 19 && vco < 61000 */
if (minfo->devflags.g450dac) {
minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */
} else {
minfo->features.pll.vco_freq_min = 62000;
}
if (!minfo->features.pll.ref_freq) {
minfo->features.pll.ref_freq = 27000;
}
minfo->features.pll.feed_div_min = 7;
minfo->features.pll.feed_div_max = 127;
minfo->features.pll.in_div_min = 1;
minfo->features.pll.in_div_max = 31;
minfo->features.pll.post_shift_max = 3;
minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT;
/* minfo->capable.cfb4 = 0; ... preinitialized by 0 */
minfo->capable.text = 1;
minfo->capable.vxres = vxres_g100;
minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100
? minfo->devflags.sgram : 1;
if (minfo->devflags.g450dac) {
minfo->outputs[0].output = &g450out;
} else {
minfo->outputs[0].output = &m1064;
}
minfo->outputs[0].src = minfo->outputs[0].default_src;
minfo->outputs[0].data = minfo;
minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
if (minfo->devflags.g450dac) {
/* we must do this always, BIOS does not do it for us
and accelerator dies without it */
mga_outl(0x1C0C, 0);
}
if (minfo->devflags.noinit)
return 0;
if (minfo->devflags.g450dac) {
g450_preinit(minfo);
return 0;
}
hw->MXoptionReg &= 0xC0000100;
hw->MXoptionReg |= 0x00000020;
if (minfo->devflags.novga)
hw->MXoptionReg &= ~0x00000100;
if (minfo->devflags.nobios)
hw->MXoptionReg &= ~0x40000000;
if (minfo->devflags.nopciretry)
hw->MXoptionReg |= 0x20000000;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
DAC1064_setmclk(minfo, DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV3 | DAC1064_OPT_SCLK_PCI, 133333);
if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) {
pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
reg50 &= ~0x3000;
pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
hw->MXoptionReg |= 0x1080;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
udelay(100);
mga_outb(0x1C05, 0x00);
mga_outb(0x1C05, 0x80);
udelay(100);
mga_outb(0x1C05, 0x40);
mga_outb(0x1C05, 0xC0);
udelay(100);
reg50 &= ~0xFF;
reg50 |= 0x07;
pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
/* it should help with G100 */
mga_outb(M_GRAPHICS_INDEX, 6);
mga_outb(M_GRAPHICS_DATA, (mga_inb(M_GRAPHICS_DATA) & 3) | 4);
mga_setr(M_EXTVGA_INDEX, 0x03, 0x81);
mga_setr(M_EXTVGA_INDEX, 0x04, 0x00);
mga_writeb(minfo->video.vbase, 0x0000, 0xAA);
mga_writeb(minfo->video.vbase, 0x0800, 0x55);
mga_writeb(minfo->video.vbase, 0x4000, 0x55);
#if 0
if (mga_readb(minfo->video.vbase, 0x0000) != 0xAA) {
hw->MXoptionReg &= ~0x1000;
}
#endif
hw->MXoptionReg |= 0x00078020;
} else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) {
pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
reg50 &= ~0x3000;
pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
if (minfo->devflags.memtype == -1)
hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
else
hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
if (minfo->devflags.sgram)
hw->MXoptionReg |= 0x4000;
mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
udelay(200);
mga_outl(M_MACCESS, 0x00000000);
mga_outl(M_MACCESS, 0x00008000);
udelay(100);
mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk);
hw->MXoptionReg |= 0x00078020;
} else {
pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50);
reg50 &= ~0x00000100;
reg50 |= 0x00000000;
pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50);
if (minfo->devflags.memtype == -1)
hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00;
else
hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10;
if (minfo->devflags.sgram)
hw->MXoptionReg |= 0x4000;
mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst);
mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
udelay(200);
mga_outl(M_MACCESS, 0x00000000);
mga_outl(M_MACCESS, 0x00008000);
udelay(100);
mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk);
hw->MXoptionReg |= 0x00040020;
}
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
return 0;
}
static void MGAG100_reset(struct matrox_fb_info *minfo)
{
u_int8_t b;
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
{
#ifdef G100_BROKEN_IBM_82351
u_int32_t d;
find 1014/22 (IBM/82351); /* if found and bridging Matrox, do some strange stuff */
pci_read_config_byte(ibm, PCI_SECONDARY_BUS, &b);
if (b == minfo->pcidev->bus->number) {
pci_write_config_byte(ibm, PCI_COMMAND+1, 0); /* disable back-to-back & SERR */
pci_write_config_byte(ibm, 0x41, 0xF4); /* ??? */
pci_write_config_byte(ibm, PCI_IO_BASE, 0xF0); /* ??? */
pci_write_config_byte(ibm, PCI_IO_LIMIT, 0x00); /* ??? */
}
#endif
if (!minfo->devflags.noinit) {
if (x7AF4 & 8) {
hw->MXoptionReg |= 0x40; /* FIXME... */
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
}
mga_setr(M_EXTVGA_INDEX, 0x06, 0x00);
}
}
if (minfo->devflags.g450dac) {
/* either leave MCLK as is... or they were set in preinit */
hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM);
hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN);
hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP);
} else {
DAC1064_setmclk(minfo, DAC1064_OPT_RESERVED | DAC1064_OPT_MDIV2 | DAC1064_OPT_GDIV1 | DAC1064_OPT_SCLK_PLL, 133333);
}
if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) {
if (minfo->devflags.dfp_type == -1) {
minfo->devflags.dfp_type = inDAC1064(minfo, 0x1F);
}
}
if (minfo->devflags.noinit)
return;
if (minfo->devflags.g450dac) {
} else {
MGAG100_setPixClock(minfo, 4, 25175);
MGAG100_setPixClock(minfo, 5, 28322);
if (x7AF4 & 0x10) {
b = inDAC1064(minfo, M1064_XGENIODATA) & ~1;
outDAC1064(minfo, M1064_XGENIODATA, b);
b = inDAC1064(minfo, M1064_XGENIOCTRL) | 1;
outDAC1064(minfo, M1064_XGENIOCTRL, b);
}
}
}
#endif
#ifdef CONFIG_FB_MATROX_MYSTIQUE
static void MGA1064_restore(struct matrox_fb_info *minfo)
{
int i;
struct matrox_hw_state *hw = &minfo->hw;
CRITFLAGS
DBG(__func__)
CRITBEGIN
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
mga_outb(M_IEN, 0x00);
mga_outb(M_CACHEFLUSH, 0x00);
CRITEND
DAC1064_restore_1(minfo);
matroxfb_vgaHWrestore(minfo);
minfo->crtc1.panpos = -1;
for (i = 0; i < 6; i++)
mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
DAC1064_restore_2(minfo);
}
#endif
#ifdef CONFIG_FB_MATROX_G
static void MGAG100_restore(struct matrox_fb_info *minfo)
{
int i;
struct matrox_hw_state *hw = &minfo->hw;
CRITFLAGS
DBG(__func__)
CRITBEGIN
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
CRITEND
DAC1064_restore_1(minfo);
matroxfb_vgaHWrestore(minfo);
if (minfo->devflags.support32MB)
mga_setr(M_EXTVGA_INDEX, 8, hw->CRTCEXT[8]);
minfo->crtc1.panpos = -1;
for (i = 0; i < 6; i++)
mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
DAC1064_restore_2(minfo);
}
#endif
#ifdef CONFIG_FB_MATROX_MYSTIQUE
struct matrox_switch matrox_mystique = {
.preinit = MGA1064_preinit,
.reset = MGA1064_reset,
.init = MGA1064_init,
.restore = MGA1064_restore,
};
EXPORT_SYMBOL(matrox_mystique);
#endif
#ifdef CONFIG_FB_MATROX_G
struct matrox_switch matrox_G100 = {
.preinit = MGAG100_preinit,
.reset = MGAG100_reset,
.init = MGAG100_init,
.restore = MGAG100_restore,
};
EXPORT_SYMBOL(matrox_G100);
#endif
#ifdef NEED_DAC1064
EXPORT_SYMBOL(DAC1064_global_init);
EXPORT_SYMBOL(DAC1064_global_restore);
#endif
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/matrox/matroxfb_DAC1064.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Version: 1.65 2002/08/14
*
* MTRR stuff: 1998 Tom Rini <[email protected]>
*
* Contributors: "menion?" <[email protected]>
* Betatesting, fixes, ideas
*
* "Kurt Garloff" <[email protected]>
* Betatesting, fixes, ideas, videomodes, videomodes timmings
*
* "Tom Rini" <[email protected]>
* MTRR stuff, PPC cleanups, betatesting, fixes, ideas
*
* "Bibek Sahu" <[email protected]>
* Access device through readb|w|l and write b|w|l
* Extensive debugging stuff
*
* "Daniel Haun" <[email protected]>
* Testing, hardware cursor fixes
*
* "Scott Wood" <[email protected]>
* Fixes
*
* "Gerd Knorr" <[email protected]>
* Betatesting
*
* "Kelly French" <[email protected]>
* "Fernando Herrera" <[email protected]>
* Betatesting, bug reporting
*
* "Pablo Bianucci" <[email protected]>
* Fixes, ideas, betatesting
*
* "Inaky Perez Gonzalez" <[email protected]>
* Fixes, enhandcements, ideas, betatesting
*
* "Ryuichi Oikawa" <[email protected]>
* PPC betatesting, PPC support, backward compatibility
*
* "Paul Womar" <[email protected]>
* "Owen Waller" <[email protected]>
* PPC betatesting
*
* "Thomas Pornin" <[email protected]>
* Alpha betatesting
*
* "Pieter van Leuven" <[email protected]>
* "Ulf Jaenicke-Roessler" <[email protected]>
* G100 testing
*
* "H. Peter Arvin" <[email protected]>
* Ideas
*
* "Cort Dougan" <[email protected]>
* CHRP fixes and PReP cleanup
*
* "Mark Vojkovich" <[email protected]>
* G400 support
*
* (following author is not in any relation with this code, but his code
* is included in this driver)
*
* Based on framebuffer driver for VBE 2.0 compliant graphic boards
* (c) 1998 Gerd Knorr <[email protected]>
*
* (following author is not in any relation with this code, but his ideas
* were used when writing this driver)
*
* FreeVBE/AF (Matrox), "Shawn Hargreaves" <[email protected]>
*
*/
#include "matroxfb_accel.h"
#include "matroxfb_DAC1064.h"
#include "matroxfb_Ti3026.h"
#include "matroxfb_misc.h"
#define curr_ydstorg(x) ((x)->curr.ydstorg.pixels)
#define mga_ydstlen(y,l) mga_outl(M_YDSTLEN | M_EXEC, ((y) << 16) | (l))
static inline void matrox_cfb4_pal(u_int32_t* pal) {
unsigned int i;
for (i = 0; i < 16; i++) {
pal[i] = i * 0x11111111U;
}
}
static inline void matrox_cfb8_pal(u_int32_t* pal) {
unsigned int i;
for (i = 0; i < 16; i++) {
pal[i] = i * 0x01010101U;
}
}
static void matroxfb_copyarea(struct fb_info* info, const struct fb_copyarea* area);
static void matroxfb_fillrect(struct fb_info* info, const struct fb_fillrect* rect);
static void matroxfb_imageblit(struct fb_info* info, const struct fb_image* image);
static void matroxfb_cfb4_fillrect(struct fb_info* info, const struct fb_fillrect* rect);
static void matroxfb_cfb4_copyarea(struct fb_info* info, const struct fb_copyarea* area);
void matrox_cfbX_init(struct matrox_fb_info *minfo)
{
u_int32_t maccess;
u_int32_t mpitch;
u_int32_t mopmode;
int accel;
DBG(__func__)
mpitch = minfo->fbcon.var.xres_virtual;
minfo->fbops.fb_copyarea = cfb_copyarea;
minfo->fbops.fb_fillrect = cfb_fillrect;
minfo->fbops.fb_imageblit = cfb_imageblit;
minfo->fbops.fb_cursor = NULL;
accel = (minfo->fbcon.var.accel_flags & FB_ACCELF_TEXT) == FB_ACCELF_TEXT;
switch (minfo->fbcon.var.bits_per_pixel) {
case 4: maccess = 0x00000000; /* accelerate as 8bpp video */
mpitch = (mpitch >> 1) | 0x8000; /* disable linearization */
mopmode = M_OPMODE_4BPP;
matrox_cfb4_pal(minfo->cmap);
if (accel && !(mpitch & 1)) {
minfo->fbops.fb_copyarea = matroxfb_cfb4_copyarea;
minfo->fbops.fb_fillrect = matroxfb_cfb4_fillrect;
}
break;
case 8: maccess = 0x00000000;
mopmode = M_OPMODE_8BPP;
matrox_cfb8_pal(minfo->cmap);
if (accel) {
minfo->fbops.fb_copyarea = matroxfb_copyarea;
minfo->fbops.fb_fillrect = matroxfb_fillrect;
minfo->fbops.fb_imageblit = matroxfb_imageblit;
}
break;
case 16: if (minfo->fbcon.var.green.length == 5)
maccess = 0xC0000001;
else
maccess = 0x40000001;
mopmode = M_OPMODE_16BPP;
if (accel) {
minfo->fbops.fb_copyarea = matroxfb_copyarea;
minfo->fbops.fb_fillrect = matroxfb_fillrect;
minfo->fbops.fb_imageblit = matroxfb_imageblit;
}
break;
case 24: maccess = 0x00000003;
mopmode = M_OPMODE_24BPP;
if (accel) {
minfo->fbops.fb_copyarea = matroxfb_copyarea;
minfo->fbops.fb_fillrect = matroxfb_fillrect;
minfo->fbops.fb_imageblit = matroxfb_imageblit;
}
break;
case 32: maccess = 0x00000002;
mopmode = M_OPMODE_32BPP;
if (accel) {
minfo->fbops.fb_copyarea = matroxfb_copyarea;
minfo->fbops.fb_fillrect = matroxfb_fillrect;
minfo->fbops.fb_imageblit = matroxfb_imageblit;
}
break;
default: maccess = 0x00000000;
mopmode = 0x00000000;
break; /* turn off acceleration!!! */
}
mga_fifo(8);
mga_outl(M_PITCH, mpitch);
mga_outl(M_YDSTORG, curr_ydstorg(minfo));
if (minfo->capable.plnwt)
mga_outl(M_PLNWT, -1);
if (minfo->capable.srcorg) {
mga_outl(M_SRCORG, 0);
mga_outl(M_DSTORG, 0);
}
mga_outl(M_OPMODE, mopmode);
mga_outl(M_CXBNDRY, 0xFFFF0000);
mga_outl(M_YTOP, 0);
mga_outl(M_YBOT, 0x01FFFFFF);
mga_outl(M_MACCESS, maccess);
minfo->accel.m_dwg_rect = M_DWG_TRAP | M_DWG_SOLID | M_DWG_ARZERO | M_DWG_SGNZERO | M_DWG_SHIFTZERO;
if (isMilleniumII(minfo)) minfo->accel.m_dwg_rect |= M_DWG_TRANSC;
minfo->accel.m_opmode = mopmode;
minfo->accel.m_access = maccess;
minfo->accel.m_pitch = mpitch;
}
EXPORT_SYMBOL(matrox_cfbX_init);
static void matrox_accel_restore_maccess(struct matrox_fb_info *minfo)
{
mga_outl(M_MACCESS, minfo->accel.m_access);
mga_outl(M_PITCH, minfo->accel.m_pitch);
}
static void matrox_accel_bmove(struct matrox_fb_info *minfo, int vxres, int sy,
int sx, int dy, int dx, int height, int width)
{
int start, end;
CRITFLAGS
DBG(__func__)
CRITBEGIN
if ((dy < sy) || ((dy == sy) && (dx <= sx))) {
mga_fifo(4);
matrox_accel_restore_maccess(minfo);
mga_outl(M_DWGCTL, M_DWG_BITBLT | M_DWG_SHIFTZERO | M_DWG_SGNZERO |
M_DWG_BFCOL | M_DWG_REPLACE);
mga_outl(M_AR5, vxres);
width--;
start = sy*vxres+sx+curr_ydstorg(minfo);
end = start+width;
} else {
mga_fifo(5);
matrox_accel_restore_maccess(minfo);
mga_outl(M_DWGCTL, M_DWG_BITBLT | M_DWG_SHIFTZERO | M_DWG_BFCOL | M_DWG_REPLACE);
mga_outl(M_SGN, 5);
mga_outl(M_AR5, -vxres);
width--;
end = (sy+height-1)*vxres+sx+curr_ydstorg(minfo);
start = end+width;
dy += height-1;
}
mga_fifo(6);
matrox_accel_restore_maccess(minfo);
mga_outl(M_AR0, end);
mga_outl(M_AR3, start);
mga_outl(M_FXBNDRY, ((dx+width)<<16) | dx);
mga_ydstlen(dy, height);
WaitTillIdle();
CRITEND
}
static void matrox_accel_bmove_lin(struct matrox_fb_info *minfo, int vxres,
int sy, int sx, int dy, int dx, int height,
int width)
{
int start, end;
CRITFLAGS
DBG(__func__)
CRITBEGIN
if ((dy < sy) || ((dy == sy) && (dx <= sx))) {
mga_fifo(4);
matrox_accel_restore_maccess(minfo);
mga_outl(M_DWGCTL, M_DWG_BITBLT | M_DWG_SHIFTZERO | M_DWG_SGNZERO |
M_DWG_BFCOL | M_DWG_REPLACE);
mga_outl(M_AR5, vxres);
width--;
start = sy*vxres+sx+curr_ydstorg(minfo);
end = start+width;
} else {
mga_fifo(5);
matrox_accel_restore_maccess(minfo);
mga_outl(M_DWGCTL, M_DWG_BITBLT | M_DWG_SHIFTZERO | M_DWG_BFCOL | M_DWG_REPLACE);
mga_outl(M_SGN, 5);
mga_outl(M_AR5, -vxres);
width--;
end = (sy+height-1)*vxres+sx+curr_ydstorg(minfo);
start = end+width;
dy += height-1;
}
mga_fifo(7);
matrox_accel_restore_maccess(minfo);
mga_outl(M_AR0, end);
mga_outl(M_AR3, start);
mga_outl(M_FXBNDRY, ((dx+width)<<16) | dx);
mga_outl(M_YDST, dy*vxres >> 5);
mga_outl(M_LEN | M_EXEC, height);
WaitTillIdle();
CRITEND
}
static void matroxfb_cfb4_copyarea(struct fb_info* info, const struct fb_copyarea* area) {
struct matrox_fb_info *minfo = info2minfo(info);
if ((area->sx | area->dx | area->width) & 1)
cfb_copyarea(info, area);
else
matrox_accel_bmove_lin(minfo, minfo->fbcon.var.xres_virtual >> 1, area->sy, area->sx >> 1, area->dy, area->dx >> 1, area->height, area->width >> 1);
}
static void matroxfb_copyarea(struct fb_info* info, const struct fb_copyarea* area) {
struct matrox_fb_info *minfo = info2minfo(info);
matrox_accel_bmove(minfo, minfo->fbcon.var.xres_virtual, area->sy, area->sx, area->dy, area->dx, area->height, area->width);
}
static void matroxfb_accel_clear(struct matrox_fb_info *minfo, u_int32_t color,
int sy, int sx, int height, int width)
{
CRITFLAGS
DBG(__func__)
CRITBEGIN
mga_fifo(7);
matrox_accel_restore_maccess(minfo);
mga_outl(M_DWGCTL, minfo->accel.m_dwg_rect | M_DWG_REPLACE);
mga_outl(M_FCOL, color);
mga_outl(M_FXBNDRY, ((sx + width) << 16) | sx);
mga_ydstlen(sy, height);
WaitTillIdle();
CRITEND
}
static void matroxfb_fillrect(struct fb_info* info, const struct fb_fillrect* rect) {
struct matrox_fb_info *minfo = info2minfo(info);
switch (rect->rop) {
case ROP_COPY:
matroxfb_accel_clear(minfo, ((u_int32_t *)info->pseudo_palette)[rect->color], rect->dy, rect->dx, rect->height, rect->width);
break;
}
}
static void matroxfb_cfb4_clear(struct matrox_fb_info *minfo, u_int32_t bgx,
int sy, int sx, int height, int width)
{
int whattodo;
CRITFLAGS
DBG(__func__)
CRITBEGIN
whattodo = 0;
if (sx & 1) {
sx ++;
if (!width) return;
width --;
whattodo = 1;
}
if (width & 1) {
whattodo |= 2;
}
width >>= 1;
sx >>= 1;
if (width) {
mga_fifo(7);
matrox_accel_restore_maccess(minfo);
mga_outl(M_DWGCTL, minfo->accel.m_dwg_rect | M_DWG_REPLACE2);
mga_outl(M_FCOL, bgx);
mga_outl(M_FXBNDRY, ((sx + width) << 16) | sx);
mga_outl(M_YDST, sy * minfo->fbcon.var.xres_virtual >> 6);
mga_outl(M_LEN | M_EXEC, height);
WaitTillIdle();
}
if (whattodo) {
u_int32_t step = minfo->fbcon.var.xres_virtual >> 1;
vaddr_t vbase = minfo->video.vbase;
if (whattodo & 1) {
unsigned int uaddr = sy * step + sx - 1;
u_int32_t loop;
u_int8_t bgx2 = bgx & 0xF0;
for (loop = height; loop > 0; loop --) {
mga_writeb(vbase, uaddr, (mga_readb(vbase, uaddr) & 0x0F) | bgx2);
uaddr += step;
}
}
if (whattodo & 2) {
unsigned int uaddr = sy * step + sx + width;
u_int32_t loop;
u_int8_t bgx2 = bgx & 0x0F;
for (loop = height; loop > 0; loop --) {
mga_writeb(vbase, uaddr, (mga_readb(vbase, uaddr) & 0xF0) | bgx2);
uaddr += step;
}
}
}
CRITEND
}
static void matroxfb_cfb4_fillrect(struct fb_info* info, const struct fb_fillrect* rect) {
struct matrox_fb_info *minfo = info2minfo(info);
switch (rect->rop) {
case ROP_COPY:
matroxfb_cfb4_clear(minfo, ((u_int32_t *)info->pseudo_palette)[rect->color], rect->dy, rect->dx, rect->height, rect->width);
break;
}
}
static void matroxfb_1bpp_imageblit(struct matrox_fb_info *minfo, u_int32_t fgx,
u_int32_t bgx, const u_int8_t *chardata,
int width, int height, int yy, int xx)
{
u_int32_t step;
u_int32_t ydstlen;
u_int32_t xlen;
u_int32_t ar0;
u_int32_t charcell;
u_int32_t fxbndry;
vaddr_t mmio;
int easy;
CRITFLAGS
DBG_HEAVY(__func__);
step = (width + 7) >> 3;
charcell = height * step;
xlen = (charcell + 3) & ~3;
ydstlen = (yy << 16) | height;
if (width == step << 3) {
ar0 = height * width - 1;
easy = 1;
} else {
ar0 = width - 1;
easy = 0;
}
CRITBEGIN
mga_fifo(5);
matrox_accel_restore_maccess(minfo);
if (easy)
mga_outl(M_DWGCTL, M_DWG_ILOAD | M_DWG_SGNZERO | M_DWG_SHIFTZERO | M_DWG_BMONOWF | M_DWG_LINEAR | M_DWG_REPLACE);
else
mga_outl(M_DWGCTL, M_DWG_ILOAD | M_DWG_SGNZERO | M_DWG_SHIFTZERO | M_DWG_BMONOWF | M_DWG_REPLACE);
mga_outl(M_FCOL, fgx);
mga_outl(M_BCOL, bgx);
fxbndry = ((xx + width - 1) << 16) | xx;
mmio = minfo->mmio.vbase;
mga_fifo(8);
matrox_accel_restore_maccess(minfo);
mga_writel(mmio, M_FXBNDRY, fxbndry);
mga_writel(mmio, M_AR0, ar0);
mga_writel(mmio, M_AR3, 0);
if (easy) {
mga_writel(mmio, M_YDSTLEN | M_EXEC, ydstlen);
mga_memcpy_toio(mmio, chardata, xlen);
} else {
mga_writel(mmio, M_AR5, 0);
mga_writel(mmio, M_YDSTLEN | M_EXEC, ydstlen);
if ((step & 3) == 0) {
/* Great. Source has 32bit aligned lines, so we can feed them
directly to the accelerator. */
mga_memcpy_toio(mmio, chardata, charcell);
} else if (step == 1) {
/* Special case for 1..8bit widths */
while (height--) {
#if defined(__BIG_ENDIAN)
fb_writel((*chardata) << 24, mmio.vaddr);
#else
fb_writel(*chardata, mmio.vaddr);
#endif
chardata++;
}
} else if (step == 2) {
/* Special case for 9..15bit widths */
while (height--) {
#if defined(__BIG_ENDIAN)
fb_writel((*(u_int16_t*)chardata) << 16, mmio.vaddr);
#else
fb_writel(*(u_int16_t*)chardata, mmio.vaddr);
#endif
chardata += 2;
}
} else {
/* Tell... well, why bother... */
while (height--) {
size_t i;
for (i = 0; i < step; i += 4) {
/* Hope that there are at least three readable bytes beyond the end of bitmap */
fb_writel(get_unaligned((u_int32_t*)(chardata + i)),mmio.vaddr);
}
chardata += step;
}
}
}
WaitTillIdle();
CRITEND
}
static void matroxfb_imageblit(struct fb_info* info, const struct fb_image* image) {
struct matrox_fb_info *minfo = info2minfo(info);
DBG_HEAVY(__func__);
if (image->depth == 1) {
u_int32_t fgx, bgx;
fgx = ((u_int32_t*)info->pseudo_palette)[image->fg_color];
bgx = ((u_int32_t*)info->pseudo_palette)[image->bg_color];
matroxfb_1bpp_imageblit(minfo, fgx, bgx, image->data, image->width, image->height, image->dy, image->dx);
} else {
/* Danger! image->depth is useless: logo painting code always
passes framebuffer color depth here, although logo data are
always 8bpp and info->pseudo_palette is changed to contain
logo palette to be used (but only for true/direct-color... sic...).
So do it completely in software... */
cfb_imageblit(info, image);
}
}
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/matrox/matroxfb_accel.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Portions Copyright (c) 2001 Matrox Graphics Inc.
*
* Version: 1.65 2002/08/14
*
* See matroxfb_base.c for contributors.
*
*/
#include "matroxfb_base.h"
#include "matroxfb_misc.h"
#include "matroxfb_DAC1064.h"
#include "g450_pll.h"
#include <linux/matroxfb.h>
#include <asm/div64.h>
#include "matroxfb_g450.h"
/* Definition of the various controls */
struct mctl {
struct v4l2_queryctrl desc;
size_t control;
};
#define BLMIN 0xF3
#define WLMAX 0x3FF
static const struct mctl g450_controls[] =
{ { { V4L2_CID_BRIGHTNESS, V4L2_CTRL_TYPE_INTEGER,
"brightness",
0, WLMAX-BLMIN, 1, 370-BLMIN,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.brightness) },
{ { V4L2_CID_CONTRAST, V4L2_CTRL_TYPE_INTEGER,
"contrast",
0, 1023, 1, 127,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.contrast) },
{ { V4L2_CID_SATURATION, V4L2_CTRL_TYPE_INTEGER,
"saturation",
0, 255, 1, 165,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.saturation) },
{ { V4L2_CID_HUE, V4L2_CTRL_TYPE_INTEGER,
"hue",
0, 255, 1, 0,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.hue) },
{ { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN,
"test output",
0, 1, 1, 0,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
};
#define G450CTRLS ARRAY_SIZE(g450_controls)
/* Return: positive number: id found
-EINVAL: id not found, return failure
-ENOENT: id not found, create fake disabled control */
static int get_ctrl_id(__u32 v4l2_id) {
int i;
for (i = 0; i < G450CTRLS; i++) {
if (v4l2_id < g450_controls[i].desc.id) {
if (g450_controls[i].desc.id == 0x08000000) {
return -EINVAL;
}
return -ENOENT;
}
if (v4l2_id == g450_controls[i].desc.id) {
return i;
}
}
return -EINVAL;
}
static inline int *get_ctrl_ptr(struct matrox_fb_info *minfo, unsigned int idx)
{
return (int*)((char*)minfo + g450_controls[idx].control);
}
static void tvo_fill_defaults(struct matrox_fb_info *minfo)
{
unsigned int i;
for (i = 0; i < G450CTRLS; i++) {
*get_ctrl_ptr(minfo, i) = g450_controls[i].desc.default_value;
}
}
static int cve2_get_reg(struct matrox_fb_info *minfo, int reg)
{
unsigned long flags;
int val;
matroxfb_DAC_lock_irqsave(flags);
matroxfb_DAC_out(minfo, 0x87, reg);
val = matroxfb_DAC_in(minfo, 0x88);
matroxfb_DAC_unlock_irqrestore(flags);
return val;
}
static void cve2_set_reg(struct matrox_fb_info *minfo, int reg, int val)
{
unsigned long flags;
matroxfb_DAC_lock_irqsave(flags);
matroxfb_DAC_out(minfo, 0x87, reg);
matroxfb_DAC_out(minfo, 0x88, val);
matroxfb_DAC_unlock_irqrestore(flags);
}
static void cve2_set_reg10(struct matrox_fb_info *minfo, int reg, int val)
{
unsigned long flags;
matroxfb_DAC_lock_irqsave(flags);
matroxfb_DAC_out(minfo, 0x87, reg);
matroxfb_DAC_out(minfo, 0x88, val >> 2);
matroxfb_DAC_out(minfo, 0x87, reg + 1);
matroxfb_DAC_out(minfo, 0x88, val & 3);
matroxfb_DAC_unlock_irqrestore(flags);
}
static void g450_compute_bwlevel(const struct matrox_fb_info *minfo, int *bl,
int *wl)
{
const int b = minfo->altout.tvo_params.brightness + BLMIN;
const int c = minfo->altout.tvo_params.contrast;
*bl = max(b - c, BLMIN);
*wl = min(b + c, WLMAX);
}
static int g450_query_ctrl(void* md, struct v4l2_queryctrl *p) {
int i;
i = get_ctrl_id(p->id);
if (i >= 0) {
*p = g450_controls[i].desc;
return 0;
}
if (i == -ENOENT) {
static const struct v4l2_queryctrl disctrl =
{ .flags = V4L2_CTRL_FLAG_DISABLED };
i = p->id;
*p = disctrl;
p->id = i;
sprintf(p->name, "Ctrl #%08X", i);
return 0;
}
return -EINVAL;
}
static int g450_set_ctrl(void* md, struct v4l2_control *p) {
int i;
struct matrox_fb_info *minfo = md;
i = get_ctrl_id(p->id);
if (i < 0) return -EINVAL;
/*
* Check if changed.
*/
if (p->value == *get_ctrl_ptr(minfo, i)) return 0;
/*
* Check limits.
*/
if (p->value > g450_controls[i].desc.maximum) return -EINVAL;
if (p->value < g450_controls[i].desc.minimum) return -EINVAL;
/*
* Store new value.
*/
*get_ctrl_ptr(minfo, i) = p->value;
switch (p->id) {
case V4L2_CID_BRIGHTNESS:
case V4L2_CID_CONTRAST:
{
int blacklevel, whitelevel;
g450_compute_bwlevel(minfo, &blacklevel, &whitelevel);
cve2_set_reg10(minfo, 0x0e, blacklevel);
cve2_set_reg10(minfo, 0x1e, whitelevel);
}
break;
case V4L2_CID_SATURATION:
cve2_set_reg(minfo, 0x20, p->value);
cve2_set_reg(minfo, 0x22, p->value);
break;
case V4L2_CID_HUE:
cve2_set_reg(minfo, 0x25, p->value);
break;
case MATROXFB_CID_TESTOUT:
{
unsigned char val = cve2_get_reg(minfo, 0x05);
if (p->value) val |= 0x02;
else val &= ~0x02;
cve2_set_reg(minfo, 0x05, val);
}
break;
}
return 0;
}
static int g450_get_ctrl(void* md, struct v4l2_control *p) {
int i;
struct matrox_fb_info *minfo = md;
i = get_ctrl_id(p->id);
if (i < 0) return -EINVAL;
p->value = *get_ctrl_ptr(minfo, i);
return 0;
}
struct output_desc {
unsigned int h_vis;
unsigned int h_f_porch;
unsigned int h_sync;
unsigned int h_b_porch;
unsigned long long int chromasc;
unsigned int burst;
unsigned int v_total;
};
static void computeRegs(struct matrox_fb_info *minfo, struct mavenregs *r,
struct my_timming *mt, const struct output_desc *outd)
{
u_int32_t chromasc;
u_int32_t hlen;
u_int32_t hsl;
u_int32_t hbp;
u_int32_t hfp;
u_int32_t hvis;
unsigned int pixclock;
unsigned long long piic;
int mnp;
int over;
r->regs[0x80] = 0x03; /* | 0x40 for SCART */
hvis = ((mt->HDisplay << 1) + 3) & ~3;
if (hvis >= 2048) {
hvis = 2044;
}
piic = 1000000000ULL * hvis;
do_div(piic, outd->h_vis);
dprintk(KERN_DEBUG "Want %u kHz pixclock\n", (unsigned int)piic);
mnp = matroxfb_g450_setclk(minfo, piic, M_VIDEO_PLL);
mt->mnp = mnp;
mt->pixclock = g450_mnp2f(minfo, mnp);
dprintk(KERN_DEBUG "MNP=%08X\n", mnp);
pixclock = 1000000000U / mt->pixclock;
dprintk(KERN_DEBUG "Got %u ps pixclock\n", pixclock);
piic = outd->chromasc;
do_div(piic, mt->pixclock);
chromasc = piic;
dprintk(KERN_DEBUG "Chroma is %08X\n", chromasc);
r->regs[0] = piic >> 24;
r->regs[1] = piic >> 16;
r->regs[2] = piic >> 8;
r->regs[3] = piic >> 0;
hbp = (((outd->h_b_porch + pixclock) / pixclock)) & ~1;
hfp = (((outd->h_f_porch + pixclock) / pixclock)) & ~1;
hsl = (((outd->h_sync + pixclock) / pixclock)) & ~1;
hlen = hvis + hfp + hsl + hbp;
over = hlen & 0x0F;
dprintk(KERN_DEBUG "WL: vis=%u, hf=%u, hs=%u, hb=%u, total=%u\n", hvis, hfp, hsl, hbp, hlen);
if (over) {
hfp -= over;
hlen -= over;
if (over <= 2) {
} else if (over < 10) {
hfp += 4;
hlen += 4;
} else {
hfp += 16;
hlen += 16;
}
}
/* maybe cve2 has requirement 800 < hlen < 1184 */
r->regs[0x08] = hsl;
r->regs[0x09] = (outd->burst + pixclock - 1) / pixclock; /* burst length */
r->regs[0x0A] = hbp;
r->regs[0x2C] = hfp;
r->regs[0x31] = hvis / 8;
r->regs[0x32] = hvis & 7;
dprintk(KERN_DEBUG "PG: vis=%04X, hf=%02X, hs=%02X, hb=%02X, total=%04X\n", hvis, hfp, hsl, hbp, hlen);
r->regs[0x84] = 1; /* x sync point */
r->regs[0x85] = 0;
hvis = hvis >> 1;
hlen = hlen >> 1;
dprintk(KERN_DEBUG "hlen=%u hvis=%u\n", hlen, hvis);
mt->interlaced = 1;
mt->HDisplay = hvis & ~7;
mt->HSyncStart = mt->HDisplay + 8;
mt->HSyncEnd = (hlen & ~7) - 8;
mt->HTotal = hlen;
{
int upper;
unsigned int vtotal;
unsigned int vsyncend;
unsigned int vdisplay;
vtotal = mt->VTotal;
vsyncend = mt->VSyncEnd;
vdisplay = mt->VDisplay;
if (vtotal < outd->v_total) {
unsigned int yovr = outd->v_total - vtotal;
vsyncend += yovr >> 1;
} else if (vtotal > outd->v_total) {
vdisplay = outd->v_total - 4;
vsyncend = outd->v_total;
}
upper = (outd->v_total - vsyncend) >> 1; /* in field lines */
r->regs[0x17] = outd->v_total / 4;
r->regs[0x18] = outd->v_total & 3;
r->regs[0x33] = upper - 1; /* upper blanking */
r->regs[0x82] = upper; /* y sync point */
r->regs[0x83] = upper >> 8;
mt->VDisplay = vdisplay;
mt->VSyncStart = outd->v_total - 2;
mt->VSyncEnd = outd->v_total;
mt->VTotal = outd->v_total;
}
}
static void cve2_init_TVdata(int norm, struct mavenregs* data, const struct output_desc** outd) {
static const struct output_desc paloutd = {
.h_vis = 52148148, // ps
.h_f_porch = 1407407, // ps
.h_sync = 4666667, // ps
.h_b_porch = 5777778, // ps
.chromasc = 19042247534182ULL, // 4433618.750 Hz
.burst = 2518518, // ps
.v_total = 625,
};
static const struct output_desc ntscoutd = {
.h_vis = 52888889, // ps
.h_f_porch = 1333333, // ps
.h_sync = 4666667, // ps
.h_b_porch = 4666667, // ps
.chromasc = 15374030659475ULL, // 3579545.454 Hz
.burst = 2418418, // ps
.v_total = 525, // lines
};
static const struct mavenregs palregs = { {
0x2A, 0x09, 0x8A, 0xCB, /* 00: chroma subcarrier */
0x00,
0x00, /* test */
0xF9, /* modified by code (F9 written...) */
0x00, /* ? not written */
0x7E, /* 08 */
0x44, /* 09 */
0x9C, /* 0A */
0x2E, /* 0B */
0x21, /* 0C */
0x00, /* ? not written */
// 0x3F, 0x03, /* 0E-0F */
0x3C, 0x03,
0x3C, 0x03, /* 10-11 */
0x1A, /* 12 */
0x2A, /* 13 */
0x1C, 0x3D, 0x14, /* 14-16 */
0x9C, 0x01, /* 17-18 */
0x00, /* 19 */
0xFE, /* 1A */
0x7E, /* 1B */
0x60, /* 1C */
0x05, /* 1D */
// 0x89, 0x03, /* 1E-1F */
0xAD, 0x03,
// 0x72, /* 20 */
0xA5,
0x07, /* 21 */
// 0x72, /* 22 */
0xA5,
0x00, /* 23 */
0x00, /* 24 */
0x00, /* 25 */
0x08, /* 26 */
0x04, /* 27 */
0x00, /* 28 */
0x1A, /* 29 */
0x55, 0x01, /* 2A-2B */
0x26, /* 2C */
0x07, 0x7E, /* 2D-2E */
0x02, 0x54, /* 2F-30 */
0xB0, 0x00, /* 31-32 */
0x14, /* 33 */
0x49, /* 34 */
0x00, /* 35 written multiple times */
0x00, /* 36 not written */
0xA3, /* 37 */
0xC8, /* 38 */
0x22, /* 39 */
0x02, /* 3A */
0x22, /* 3B */
0x3F, 0x03, /* 3C-3D */
0x00, /* 3E written multiple times */
0x00, /* 3F not written */
} };
static const struct mavenregs ntscregs = { {
0x21, 0xF0, 0x7C, 0x1F, /* 00: chroma subcarrier */
0x00,
0x00, /* test */
0xF9, /* modified by code (F9 written...) */
0x00, /* ? not written */
0x7E, /* 08 */
0x43, /* 09 */
0x7E, /* 0A */
0x3D, /* 0B */
0x00, /* 0C */
0x00, /* ? not written */
0x41, 0x00, /* 0E-0F */
0x3C, 0x00, /* 10-11 */
0x17, /* 12 */
0x21, /* 13 */
0x1B, 0x1B, 0x24, /* 14-16 */
0x83, 0x01, /* 17-18 */
0x00, /* 19 */
0x0F, /* 1A */
0x0F, /* 1B */
0x60, /* 1C */
0x05, /* 1D */
//0x89, 0x02, /* 1E-1F */
0xC0, 0x02, /* 1E-1F */
//0x5F, /* 20 */
0x9C, /* 20 */
0x04, /* 21 */
//0x5F, /* 22 */
0x9C, /* 22 */
0x01, /* 23 */
0x02, /* 24 */
0x00, /* 25 */
0x0A, /* 26 */
0x05, /* 27 */
0x00, /* 28 */
0x10, /* 29 */
0xFF, 0x03, /* 2A-2B */
0x24, /* 2C */
0x0F, 0x78, /* 2D-2E */
0x00, 0x00, /* 2F-30 */
0xB2, 0x04, /* 31-32 */
0x14, /* 33 */
0x02, /* 34 */
0x00, /* 35 written multiple times */
0x00, /* 36 not written */
0xA3, /* 37 */
0xC8, /* 38 */
0x15, /* 39 */
0x05, /* 3A */
0x3B, /* 3B */
0x3C, 0x00, /* 3C-3D */
0x00, /* 3E written multiple times */
0x00, /* never written */
} };
if (norm == MATROXFB_OUTPUT_MODE_PAL) {
*data = palregs;
*outd = &paloutd;
} else {
*data = ntscregs;
*outd = &ntscoutd;
}
return;
}
#define LR(x) cve2_set_reg(minfo, (x), m->regs[(x)])
static void cve2_init_TV(struct matrox_fb_info *minfo,
const struct mavenregs *m)
{
int i;
LR(0x80);
LR(0x82); LR(0x83);
LR(0x84); LR(0x85);
cve2_set_reg(minfo, 0x3E, 0x01);
for (i = 0; i < 0x3E; i++) {
LR(i);
}
cve2_set_reg(minfo, 0x3E, 0x00);
}
static int matroxfb_g450_compute(void* md, struct my_timming* mt) {
struct matrox_fb_info *minfo = md;
dprintk(KERN_DEBUG "Computing, mode=%u\n", minfo->outputs[1].mode);
if (mt->crtc == MATROXFB_SRC_CRTC2 &&
minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
const struct output_desc* outd;
cve2_init_TVdata(minfo->outputs[1].mode, &minfo->hw.maven, &outd);
{
int blacklevel, whitelevel;
g450_compute_bwlevel(minfo, &blacklevel, &whitelevel);
minfo->hw.maven.regs[0x0E] = blacklevel >> 2;
minfo->hw.maven.regs[0x0F] = blacklevel & 3;
minfo->hw.maven.regs[0x1E] = whitelevel >> 2;
minfo->hw.maven.regs[0x1F] = whitelevel & 3;
minfo->hw.maven.regs[0x20] =
minfo->hw.maven.regs[0x22] = minfo->altout.tvo_params.saturation;
minfo->hw.maven.regs[0x25] = minfo->altout.tvo_params.hue;
if (minfo->altout.tvo_params.testout) {
minfo->hw.maven.regs[0x05] |= 0x02;
}
}
computeRegs(minfo, &minfo->hw.maven, mt, outd);
} else if (mt->mnp < 0) {
/* We must program clocks before CRTC2, otherwise interlaced mode
startup may fail */
mt->mnp = matroxfb_g450_setclk(minfo, mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
mt->pixclock = g450_mnp2f(minfo, mt->mnp);
}
dprintk(KERN_DEBUG "Pixclock = %u\n", mt->pixclock);
return 0;
}
static int matroxfb_g450_program(void* md) {
struct matrox_fb_info *minfo = md;
if (minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
cve2_init_TV(minfo, &minfo->hw.maven);
}
return 0;
}
static int matroxfb_g450_verify_mode(void* md, u_int32_t arg) {
switch (arg) {
case MATROXFB_OUTPUT_MODE_PAL:
case MATROXFB_OUTPUT_MODE_NTSC:
case MATROXFB_OUTPUT_MODE_MONITOR:
return 0;
}
return -EINVAL;
}
static int g450_dvi_compute(void* md, struct my_timming* mt) {
struct matrox_fb_info *minfo = md;
if (mt->mnp < 0) {
mt->mnp = matroxfb_g450_setclk(minfo, mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
mt->pixclock = g450_mnp2f(minfo, mt->mnp);
}
return 0;
}
static struct matrox_altout matroxfb_g450_altout = {
.name = "Secondary output",
.compute = matroxfb_g450_compute,
.program = matroxfb_g450_program,
.verifymode = matroxfb_g450_verify_mode,
.getqueryctrl = g450_query_ctrl,
.getctrl = g450_get_ctrl,
.setctrl = g450_set_ctrl,
};
static struct matrox_altout matroxfb_g450_dvi = {
.name = "DVI output",
.compute = g450_dvi_compute,
};
void matroxfb_g450_connect(struct matrox_fb_info *minfo)
{
if (minfo->devflags.g450dac) {
down_write(&minfo->altout.lock);
tvo_fill_defaults(minfo);
minfo->outputs[1].src = minfo->outputs[1].default_src;
minfo->outputs[1].data = minfo;
minfo->outputs[1].output = &matroxfb_g450_altout;
minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
minfo->outputs[2].src = minfo->outputs[2].default_src;
minfo->outputs[2].data = minfo;
minfo->outputs[2].output = &matroxfb_g450_dvi;
minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&minfo->altout.lock);
}
}
void matroxfb_g450_shutdown(struct matrox_fb_info *minfo)
{
if (minfo->devflags.g450dac) {
down_write(&minfo->altout.lock);
minfo->outputs[1].src = MATROXFB_SRC_NONE;
minfo->outputs[1].output = NULL;
minfo->outputs[1].data = NULL;
minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
minfo->outputs[2].src = MATROXFB_SRC_NONE;
minfo->outputs[2].output = NULL;
minfo->outputs[2].data = NULL;
minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&minfo->altout.lock);
}
}
EXPORT_SYMBOL(matroxfb_g450_connect);
EXPORT_SYMBOL(matroxfb_g450_shutdown);
MODULE_AUTHOR("(c) 2000-2002 Petr Vandrovec <[email protected]>");
MODULE_DESCRIPTION("Matrox G450/G550 output driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/matrox/matroxfb_g450.c |
/*-*- linux-c -*-
* linux/drivers/video/i810_dvt.c -- Intel 810 Discrete Video Timings (Intel)
*
* Copyright (C) 2001 Antonino Daplas<[email protected]>
* All Rights Reserved
*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/kernel.h>
#include "i810_regs.h"
#include "i810.h"
#include "i810_main.h"
struct mode_registers std_modes[] = {
/* 640x480 @ 60Hz */
{ 25000, 0x0013, 0x0003, 0x40, 0x5F, 0x4F, 0x50, 0x82, 0x51, 0x9D,
0x0B, 0x10, 0x40, 0xE9, 0x0B, 0xDF, 0x50, 0xE7, 0x04, 0x02,
0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22006000,
0x22002000, 0x22004000, 0x22006000, 0xC0 },
/* 640x480 @ 70Hz */
{ 28000, 0x0053, 0x0010, 0x40, 0x61, 0x4F, 0x4F, 0x85, 0x52, 0x9A,
0xF2, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xF3, 0x01,
0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22005000,
0x22002000, 0x22004000, 0x22005000, 0xC0 },
/* 640x480 @ 72Hz */
{ 31000, 0x0013, 0x0002, 0x40, 0x63, 0x4F, 0x4F, 0x87, 0x52, 0x97,
0x06, 0x0F, 0x40, 0xE8, 0x0B, 0xDF, 0x50, 0xDF, 0x07, 0x02,
0x01, 0x01, 0x01, 0x00, 0x01, 0x22003000, 0x22005000, 0x22007000,
0x22003000, 0x22005000, 0x22007000, 0xC0 },
/* 640x480 @ 75Hz */
{ 31000, 0x0013, 0x0002, 0x40, 0x64, 0x4F, 0x4F, 0x88, 0x51, 0x99,
0xF2, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xF3, 0x01,
0x01, 0x01, 0x01, 0x00, 0x01, 0x22003000, 0x22005000, 0x22007000,
0x22003000, 0x22005000, 0x22007000, 0xC0 },
/* 640x480 @ 85Hz */
{ 36000, 0x0010, 0x0001, 0x40, 0x63, 0x4F, 0x4F, 0x87, 0x56, 0x9D,
0xFB, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xFC, 0x01,
0x01, 0x01, 0x01, 0x00, 0x01, 0x22003000, 0x22005000, 0x22107000,
0x22003000, 0x22005000, 0x22107000, 0xC0 },
/* 800x600 @ 56Hz */
{ 36000, 0x0010, 0x0001, 0x40, 0x7B, 0x63, 0x63, 0x9F, 0x66, 0x8F,
0x6F, 0x10, 0x40, 0x58, 0x0A, 0x57, 0xC8, 0x57, 0x70, 0x02,
0x02, 0x02, 0x02, 0x00, 0x01, 0x22003000, 0x22005000, 0x22107000,
0x22003000, 0x22005000, 0x22107000, 0x00 },
/* 800x600 @ 60Hz */
{ 40000, 0x0008, 0x0001, 0x30, 0x7F, 0x63, 0x63, 0x83, 0x68, 0x18,
0x72, 0x10, 0x40, 0x58, 0x0C, 0x57, 0xC8, 0x57, 0x73, 0x02,
0x02, 0x02, 0x02, 0x00, 0x00, 0x22003000, 0x22006000, 0x22108000,
0x22003000, 0x22006000, 0x22108000, 0x00 },
/* 800x600 @ 70Hz */
{ 45000, 0x0054, 0x0015, 0x30, 0x7D, 0x63, 0x63, 0x81, 0x68, 0x12,
0x6f, 0x10, 0x40, 0x58, 0x0b, 0x57, 0x64, 0x57, 0x70, 0x02,
0x02, 0x02, 0x02, 0x00, 0x00, 0x22004000, 0x22007000, 0x2210A000,
0x22004000, 0x22007000, 0x2210A000, 0x00 },
/* 800x600 @ 72Hz */
{ 50000, 0x0017, 0x0004, 0x30, 0x7D, 0x63, 0x63, 0x81, 0x6A, 0x19,
0x98, 0x10, 0x40, 0x7C, 0x02, 0x57, 0xC8, 0x57, 0x99, 0x02,
0x02, 0x02, 0x02, 0x00, 0x00, 0x22004000, 0x22007000, 0x2210A000,
0x22004000, 0x22007000, 0x2210A000, 0x00 },
/* 800x600 @ 75Hz */
{ 49000, 0x001F, 0x0006, 0x30, 0x7F, 0x63, 0x63, 0x83, 0x65, 0x0F,
0x6F, 0x10, 0x40, 0x58, 0x0B, 0x57, 0xC8, 0x57, 0x70, 0x02,
0x02, 0x02, 0x02, 0x00, 0x00, 0x22004000, 0x22007000, 0x2210B000,
0x22004000, 0x22007000, 0x2210B000, 0x00 },
/* 800x600 @ 85Hz */
{ 56000, 0x0049, 0x000E, 0x30, 0x7E, 0x63, 0x63, 0x82, 0x67, 0x0F,
0x75, 0x10, 0x40, 0x58, 0x0B, 0x57, 0xC8, 0x57, 0x76, 0x02,
0x02, 0x02, 0x02, 0x00, 0x00, 0x22004000, 0x22108000, 0x2210b000,
0x22004000, 0x22108000, 0x2210b000, 0x00 },
/* 1024x768 @ 60Hz */
{ 65000, 0x003F, 0x000A, 0x30, 0xA3, 0x7F, 0x7F, 0x87, 0x83, 0x94,
0x24, 0x10, 0x40, 0x02, 0x08, 0xFF, 0x80, 0xFF, 0x25, 0x03,
0x02, 0x03, 0x02, 0x00, 0x00, 0x22005000, 0x22109000, 0x2220D000,
0x22005000, 0x22109000, 0x2220D000, 0xC0 },
/* 1024x768 @ 70Hz */
{ 75000, 0x0017, 0x0002, 0x30, 0xA1, 0x7F, 0x7F, 0x85, 0x82, 0x93,
0x24, 0x10, 0x40, 0x02, 0x08, 0xFF, 0x80, 0xFF, 0x25, 0x03,
0x02, 0x03, 0x02, 0x00, 0x00, 0x22005000, 0x2210A000, 0x2220F000,
0x22005000, 0x2210A000, 0x2220F000, 0xC0 },
/* 1024x768 @ 75Hz */
{ 78000, 0x0050, 0x0017, 0x20, 0x9F, 0x7F, 0x7F, 0x83, 0x81, 0x8D,
0x1E, 0x10, 0x40, 0x00, 0x03, 0xFF, 0x80, 0xFF, 0x1F, 0x03,
0x02, 0x03, 0x02, 0x00, 0x00, 0x22006000, 0x2210B000, 0x22210000,
0x22006000, 0x2210B000, 0x22210000, 0x00 },
/* 1024x768 @ 85Hz */
{ 94000, 0x003D, 0x000E, 0x20, 0xA7, 0x7F, 0x7F, 0x8B, 0x85, 0x91,
0x26, 0x10, 0x40, 0x00, 0x03, 0xFF, 0x80, 0xFF, 0x27, 0x03,
0x02, 0x03, 0x02, 0x00, 0x00, 0x22007000, 0x2220E000, 0x22212000,
0x22007000, 0x2220E000, 0x22212000, 0x00 },
/* 1152x864 @ 60Hz */
{ 80000, 0x0008, 0x0001, 0x20, 0xB3, 0x8F, 0x8F, 0x97, 0x93, 0x9f,
0x87, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5f, 0x88, 0x03,
0x03, 0x03, 0x03, 0x00, 0x00, 0x2220C000, 0x22210000, 0x22415000,
0x2220C000, 0x22210000, 0x22415000, 0x00 },
/* 1152x864 @ 70Hz */
{ 96000, 0x000a, 0x0001, 0x20, 0xbb, 0x8F, 0x8F, 0x9f, 0x98, 0x87,
0x82, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5F, 0x83, 0x03,
0x03, 0x03, 0x03, 0x00, 0x00, 0x22107000, 0x22210000, 0x22415000,
0x22107000, 0x22210000, 0x22415000, 0x00 },
/* 1152x864 @ 72Hz */
{ 99000, 0x001f, 0x0006, 0x20, 0xbb, 0x8F, 0x8F, 0x9f, 0x98, 0x87,
0x83, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5F, 0x84, 0x03,
0x03, 0x03, 0x03, 0x00, 0x00, 0x22107000, 0x22210000, 0x22415000,
0x22107000, 0x22210000, 0x22415000, 0x00 },
/* 1152x864 @ 75Hz */
{ 108000, 0x0010, 0x0002, 0x20, 0xC3, 0x8F, 0x8F, 0x87, 0x97, 0x07,
0x82, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5F, 0x83, 0x03,
0x03, 0x03, 0x03, 0x00, 0x01, 0x22107000, 0x22210000, 0x22415000,
0x22107000, 0x22210000, 0x22415000, 0x00 },
/* 1152x864 @ 85Hz */
{ 121000, 0x006D, 0x0014, 0x20, 0xc0, 0x8F, 0x8F, 0x84, 0x97, 0x07,
0x93, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5F, 0x94, 0x03,
0x03, 0x03, 0x03, 0x00, 0x01, 0x2220C000, 0x22210000, 0x22415000,
0x2220C000, 0x22210000, 0x22415000, 0x0 },
/* 1280x960 @ 60Hz */
{ 108000, 0x0010, 0x0002, 0x20, 0xDC, 0x9F, 0x9F, 0x80, 0xAB, 0x99,
0xE6, 0x10, 0x40, 0xC0, 0x03, 0xBF, 0xA0, 0xBF, 0xE7, 0x03,
0x03, 0x03, 0x03, 0x00, 0x01, 0x2210A000, 0x22210000, 0x22415000,
0x2210A000, 0x22210000, 0x22415000, 0x00 },
/* 1280x960 @ 75Hz */
{ 129000, 0x0029, 0x0006, 0x20, 0xD3, 0x9F, 0x9F, 0x97, 0xaa, 0x1b,
0xE8, 0x10, 0x40, 0xC0, 0x03, 0xBF, 0xA0, 0xBF, 0xE9, 0x03,
0x03, 0x03, 0x03, 0x00, 0x01, 0x2210A000, 0x22210000, 0x2241B000,
0x2210A000, 0x22210000, 0x2241B000, 0x00 },
/* 1280x960 @ 85Hz */
{ 148000, 0x0042, 0x0009, 0x20, 0xD3, 0x9F, 0x9F, 0x97, 0xA7, 0x1B,
0xF1, 0x10, 0x40, 0xC0, 0x03, 0xBF, 0xA0, 0xBF, 0xF2, 0x03,
0x03, 0x03, 0x03, 0x00, 0x01, 0x2210A000, 0x22220000, 0x2241D000,
0x2210A000, 0x22220000, 0x2241D000, 0x00 },
/* 1600x1200 @ 60Hz */
{ 162000, 0x0019, 0x0006, 0x10, 0x09, 0xC7, 0xC7, 0x8D, 0xcf, 0x07,
0xE0, 0x10, 0x40, 0xB0, 0x03, 0xAF, 0xC8, 0xAF, 0xE1, 0x04,
0x04, 0x04, 0x04, 0x01, 0x00, 0x2210b000, 0x22416000, 0x44419000,
0x2210b000, 0x22416000, 0x44419000, 0x00 },
/* 1600x1200 @ 65 Hz */
{ 175000, 0x005d, 0x0018, 0x10, 0x09, 0xC7, 0xC7, 0x8D, 0xcf, 0x07,
0xE0, 0x10, 0x40, 0xB0, 0x03, 0xAF, 0xC8, 0xAF, 0xE1, 0x04,
0x04, 0x04, 0x04, 0x01, 0x00, 0x2210c000, 0x22416000, 0x44419000,
0x2210c000, 0x22416000, 0x44419000, 0x00 },
/* 1600x1200 @ 70 Hz */
{ 189000, 0x003D, 0x000e, 0x10, 0x09, 0xC7, 0xC7, 0x8d, 0xcf, 0x07,
0xE0, 0x10, 0x40, 0xb0, 0x03, 0xAF, 0xC8, 0xaf, 0xE1, 0x04,
0x04, 0x04, 0x04, 0x01, 0x00, 0x2220e000, 0x22416000, 0x44419000,
0x2220e000, 0x22416000, 0x44419000, 0x00 },
/* 1600x1200 @ 72 Hz */
{ 195000, 0x003f, 0x000e, 0x10, 0x0b, 0xC7, 0xC7, 0x8f, 0xd5, 0x0b,
0xE1, 0x10, 0x40, 0xb0, 0x03, 0xAF, 0xC8, 0xaf, 0xe2, 0x04, 0x04,
0x04, 0x04, 0x01, 0x00, 0x2220e000, 0x22416000, 0x44419000,
0x2220e000, 0x22416000, 0x44419000, 0x00 },
/* 1600x1200 @ 75 Hz */
{ 202000, 0x0024, 0x0007, 0x10, 0x09, 0xC7, 0xC7, 0x8d, 0xcf, 0x07,
0xE0, 0x10, 0x40, 0xb0, 0x03, 0xAF, 0xC8, 0xaf, 0xE1, 0x04, 0x04,
0x04, 0x04, 0x01, 0x00, 0x2220e000, 0x22416000, 0x44419000,
0x2220e000, 0x22416000, 0x44419000, 0x00 },
/* 1600x1200 @ 85 Hz */
{ 229000, 0x0029, 0x0007, 0x10, 0x09, 0xC7, 0xC7, 0x8d, 0xcf, 0x07,
0xE0, 0x10, 0x40, 0xb0, 0x03, 0xAF, 0xC8, 0xaf, 0xE1, 0x04, 0x04,
0x04, 0x04, 0x01, 0x00, 0x22210000, 0x22416000, 0x0,
0x22210000, 0x22416000, 0x0, 0x00 },
};
void round_off_xres(u32 *xres)
{
if (*xres <= 640)
*xres = 640;
else if (*xres <= 800)
*xres = 800;
else if (*xres <= 1024)
*xres = 1024;
else if (*xres <= 1152)
*xres = 1152;
else if (*xres <= 1280)
*xres = 1280;
else
*xres = 1600;
}
inline void round_off_yres(u32 *xres, u32 *yres)
{
*yres = (*xres * 3) >> 2;
}
static int i810fb_find_best_mode(u32 xres, u32 yres, u32 pixclock)
{
u32 diff = 0, diff_best = 0xFFFFFFFF, i = 0, i_best = 0;
u8 hfl = (u8) ((xres >> 3) - 1);
for (i = 0; i < ARRAY_SIZE(std_modes); i++) {
if (std_modes[i].cr01 == hfl) {
if (std_modes[i].pixclock <= pixclock)
diff = pixclock - std_modes[i].pixclock;
if (diff < diff_best) {
i_best = i;
diff_best = diff;
}
}
}
return i_best;
}
void i810fb_encode_registers(const struct fb_var_screeninfo *var,
struct i810fb_par *par, u32 xres, u32 yres)
{
u32 i_best = i810fb_find_best_mode(xres, yres, par->regs.pixclock);
par->regs = std_modes[i_best];
/* overlay */
par->ovract = ((xres + var->right_margin + var->hsync_len +
var->left_margin - 32) | ((xres - 32) << 16));
}
void i810fb_fill_var_timings(struct fb_var_screeninfo *var)
{
u32 total, xres, yres;
u32 mode, pixclock;
xres = var->xres;
yres = var->yres;
pixclock = 1000000000 / var->pixclock;
mode = i810fb_find_best_mode(xres, yres, pixclock);
total = (std_modes[mode].cr00 | (std_modes[mode].cr35 & 1) << 8) + 3;
total <<= 3;
var->pixclock = 1000000000 / std_modes[mode].pixclock;
var->right_margin = (std_modes[mode].cr04 << 3) - xres;
var->hsync_len = ((std_modes[mode].cr05 & 0x1F) -
(std_modes[mode].cr04 & 0x1F)) << 3;
var->left_margin = (total - (xres + var->right_margin +
var->hsync_len));
var->sync = FB_SYNC_ON_GREEN;
if (~(std_modes[mode].msr & (1 << 6)))
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (~(std_modes[mode].msr & (1 << 7)))
var->sync |= FB_SYNC_VERT_HIGH_ACT;
total = (std_modes[mode].cr06 | (std_modes[mode].cr30 & 0xF) << 8) + 2;
var->lower_margin = (std_modes[mode].cr10 |
(std_modes[mode].cr32 & 0x0F) << 8) - yres;
var->vsync_len = (std_modes[mode].cr11 & 0x0F) -
(var->lower_margin & 0x0F);
var->upper_margin = total - (yres + var->lower_margin + var->vsync_len);
}
u32 i810_get_watermark(const struct fb_var_screeninfo *var,
struct i810fb_par *par)
{
struct mode_registers *params = &par->regs;
u32 wmark = 0;
if (par->mem_freq == 100) {
switch (var->bits_per_pixel) {
case 8:
wmark = params->bpp8_100;
break;
case 16:
wmark = params->bpp16_100;
break;
case 24:
case 32:
wmark = params->bpp24_100;
}
} else {
switch (var->bits_per_pixel) {
case 8:
wmark = params->bpp8_133;
break;
case 16:
wmark = params->bpp16_133;
break;
case 24:
case 32:
wmark = params->bpp24_133;
}
}
return wmark;
}
| linux-master | drivers/video/fbdev/i810/i810_dvt.c |
/*-*- linux-c -*-
* linux/drivers/video/i810-i2c.c -- Intel 810/815 I2C support
*
* Copyright (C) 2004 Antonino Daplas<[email protected]>
* All Rights Reserved
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include "i810.h"
#include "i810_regs.h"
#include "i810_main.h"
#include "../edid.h"
/* bit locations in the registers */
#define SCL_DIR_MASK 0x0001
#define SCL_DIR 0x0002
#define SCL_VAL_MASK 0x0004
#define SCL_VAL_OUT 0x0008
#define SCL_VAL_IN 0x0010
#define SDA_DIR_MASK 0x0100
#define SDA_DIR 0x0200
#define SDA_VAL_MASK 0x0400
#define SDA_VAL_OUT 0x0800
#define SDA_VAL_IN 0x1000
#define DEBUG /* define this for verbose EDID parsing output */
#ifdef DEBUG
#define DPRINTK(fmt, args...) printk(fmt,## args)
#else
#define DPRINTK(fmt, args...)
#endif
static void i810i2c_setscl(void *data, int state)
{
struct i810fb_i2c_chan *chan = data;
struct i810fb_par *par = chan->par;
u8 __iomem *mmio = par->mmio_start_virtual;
if (state)
i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK);
else
i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
i810_readl(mmio, chan->ddc_base); /* flush posted write */
}
static void i810i2c_setsda(void *data, int state)
{
struct i810fb_i2c_chan *chan = data;
struct i810fb_par *par = chan->par;
u8 __iomem *mmio = par->mmio_start_virtual;
if (state)
i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK);
else
i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
i810_readl(mmio, chan->ddc_base); /* flush posted write */
}
static int i810i2c_getscl(void *data)
{
struct i810fb_i2c_chan *chan = data;
struct i810fb_par *par = chan->par;
u8 __iomem *mmio = par->mmio_start_virtual;
i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK);
i810_writel(mmio, chan->ddc_base, 0);
return ((i810_readl(mmio, chan->ddc_base) & SCL_VAL_IN) != 0);
}
static int i810i2c_getsda(void *data)
{
struct i810fb_i2c_chan *chan = data;
struct i810fb_par *par = chan->par;
u8 __iomem *mmio = par->mmio_start_virtual;
i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK);
i810_writel(mmio, chan->ddc_base, 0);
return ((i810_readl(mmio, chan->ddc_base) & SDA_VAL_IN) != 0);
}
static int i810_setup_i2c_bus(struct i810fb_i2c_chan *chan, const char *name)
{
int rc;
strcpy(chan->adapter.name, name);
chan->adapter.owner = THIS_MODULE;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->par->dev->dev;
chan->algo.setsda = i810i2c_setsda;
chan->algo.setscl = i810i2c_setscl;
chan->algo.getsda = i810i2c_getsda;
chan->algo.getscl = i810i2c_getscl;
chan->algo.udelay = 10;
chan->algo.timeout = (HZ/2);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
/* Raise SCL and SDA */
chan->algo.setsda(chan, 1);
chan->algo.setscl(chan, 1);
udelay(20);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
dev_dbg(&chan->par->dev->dev, "I2C bus %s registered.\n",name);
else {
dev_warn(&chan->par->dev->dev, "Failed to register I2C bus "
"%s.\n", name);
chan->par = NULL;
}
return rc;
}
void i810_create_i2c_busses(struct i810fb_par *par)
{
par->chan[0].par = par;
par->chan[1].par = par;
par->chan[2].par = par;
par->chan[0].ddc_base = GPIOA;
i810_setup_i2c_bus(&par->chan[0], "I810-DDC");
par->chan[1].ddc_base = GPIOB;
i810_setup_i2c_bus(&par->chan[1], "I810-I2C");
par->chan[2].ddc_base = GPIOC;
i810_setup_i2c_bus(&par->chan[2], "I810-GPIOC");
}
void i810_delete_i2c_busses(struct i810fb_par *par)
{
if (par->chan[0].par)
i2c_del_adapter(&par->chan[0].adapter);
par->chan[0].par = NULL;
if (par->chan[1].par)
i2c_del_adapter(&par->chan[1].adapter);
par->chan[1].par = NULL;
if (par->chan[2].par)
i2c_del_adapter(&par->chan[2].adapter);
par->chan[2].par = NULL;
}
int i810_probe_i2c_connector(struct fb_info *info, u8 **out_edid, int conn)
{
struct i810fb_par *par = info->par;
u8 *edid = NULL;
DPRINTK("i810-i2c: Probe DDC%i Bus\n", conn+1);
if (conn < par->ddc_num) {
edid = fb_ddc_read(&par->chan[conn].adapter);
} else {
const u8 *e = fb_firmware_edid(info->device);
if (e != NULL) {
DPRINTK("i810-i2c: Getting EDID from BIOS\n");
edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
}
}
*out_edid = edid;
return (edid) ? 0 : 1;
}
| linux-master | drivers/video/fbdev/i810/i810-i2c.c |
/*-*- linux-c -*-
* linux/drivers/video/i810_main.c -- Intel 810 frame buffer device
*
* Copyright (C) 2001 Antonino Daplas<[email protected]>
* All Rights Reserved
*
* Contributors:
* Michael Vogt <[email protected]> - added support for Intel 815 chipsets
* and enabling the power-on state of
* external VGA connectors for
* secondary displays
*
* Fredrik Andersson <[email protected]> - alpha testing of
* the VESA GTF
*
* Brad Corrion <[email protected]> - alpha testing of customized
* timings support
*
* The code framework is a modification of vfb.c by Geert Uytterhoeven.
* DotClock and PLL calculations are partly based on i810_driver.c
* in xfree86 v4.0.3 by Precision Insight.
* Watermark calculation and tables are based on i810_wmark.c
* in xfre86 v4.0.3 by Precision Insight. Slight modifications
* only to allow for integer operations instead of floating point.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/resource.h>
#include <linux/unistd.h>
#include <linux/console.h>
#include <linux/io.h>
#include <asm/io.h>
#include <asm/div64.h>
#include <asm/page.h>
#include "i810_regs.h"
#include "i810.h"
#include "i810_main.h"
/*
* voffset - framebuffer offset in MiB from aperture start address. In order for
* the driver to work with X, we must try to use memory holes left untouched by X. The
* following table lists where X's different surfaces start at.
*
* ---------------------------------------------
* : : 64 MiB : 32 MiB :
* ----------------------------------------------
* : FrontBuffer : 0 : 0 :
* : DepthBuffer : 48 : 16 :
* : BackBuffer : 56 : 24 :
* ----------------------------------------------
*
* So for chipsets with 64 MiB Aperture sizes, 32 MiB for v_offset is okay, allowing up to
* 15 + 1 MiB of Framebuffer memory. For 32 MiB Aperture sizes, a v_offset of 8 MiB should
* work, allowing 7 + 1 MiB of Framebuffer memory.
* Note, the size of the hole may change depending on how much memory you allocate to X,
* and how the memory is split up between these surfaces.
*
* Note: Anytime the DepthBuffer or FrontBuffer is overlapped, X would still run but with
* DRI disabled. But if the Frontbuffer is overlapped, X will fail to load.
*
* Experiment with v_offset to find out which works best for you.
*/
static u32 v_offset_default; /* For 32 MiB Aper size, 8 should be the default */
static u32 voffset;
static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor);
static int i810fb_init_pci(struct pci_dev *dev,
const struct pci_device_id *entry);
static void i810fb_remove_pci(struct pci_dev *dev);
static int i810fb_resume(struct pci_dev *dev);
static int i810fb_suspend(struct pci_dev *dev, pm_message_t state);
/* Chipset Specific Functions */
static int i810fb_set_par (struct fb_info *info);
static int i810fb_getcolreg (u8 regno, u8 *red, u8 *green, u8 *blue,
u8 *transp, struct fb_info *info);
static int i810fb_setcolreg (unsigned regno, unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info);
static int i810fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
static int i810fb_blank (int blank_mode, struct fb_info *info);
/* Initialization */
static void i810fb_release_resource (struct fb_info *info, struct i810fb_par *par);
/* PCI */
static const char * const i810_pci_list[] = {
"Intel(R) 810 Framebuffer Device" ,
"Intel(R) 810-DC100 Framebuffer Device" ,
"Intel(R) 810E Framebuffer Device" ,
"Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" ,
"Intel(R) 815 (Internal Graphics only) Framebuffer Device" ,
"Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device"
};
static const struct pci_device_id i810fb_pci_tbl[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
/* mvo: added i815 PCI-ID */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
{ 0 },
};
static struct pci_driver i810fb_driver = {
.name = "i810fb",
.id_table = i810fb_pci_tbl,
.probe = i810fb_init_pci,
.remove = i810fb_remove_pci,
.suspend = i810fb_suspend,
.resume = i810fb_resume,
};
static char *mode_option = NULL;
static int vram = 4;
static int bpp = 8;
static bool mtrr;
static bool accel;
static int hsync1;
static int hsync2;
static int vsync1;
static int vsync2;
static int xres;
static int yres;
static int vyres;
static bool sync;
static bool extvga;
static bool dcolor;
static bool ddc3;
/*------------------------------------------------------------*/
/**************************************************************
* Hardware Low Level Routines *
**************************************************************/
/**
* i810_screen_off - turns off/on display
* @mmio: address of register space
* @mode: on or off
*
* DESCRIPTION:
* Blanks/unblanks the display
*/
static void i810_screen_off(u8 __iomem *mmio, u8 mode)
{
u32 count = WAIT_COUNT;
u8 val;
i810_writeb(SR_INDEX, mmio, SR01);
val = i810_readb(SR_DATA, mmio);
val = (mode == OFF) ? val | SCR_OFF :
val & ~SCR_OFF;
while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
i810_writeb(SR_INDEX, mmio, SR01);
i810_writeb(SR_DATA, mmio, val);
}
/**
* i810_dram_off - turns off/on dram refresh
* @mmio: address of register space
* @mode: on or off
*
* DESCRIPTION:
* Turns off DRAM refresh. Must be off for only 2 vsyncs
* before data becomes corrupt
*/
static void i810_dram_off(u8 __iomem *mmio, u8 mode)
{
u8 val;
val = i810_readb(DRAMCH, mmio);
val &= DRAM_OFF;
val = (mode == OFF) ? val : val | DRAM_ON;
i810_writeb(DRAMCH, mmio, val);
}
/**
* i810_protect_regs - allows rw/ro mode of certain VGA registers
* @mmio: address of register space
* @mode: protect/unprotect
*
* DESCRIPTION:
* The IBM VGA standard allows protection of certain VGA registers.
* This will protect or unprotect them.
*/
static void i810_protect_regs(u8 __iomem *mmio, int mode)
{
u8 reg;
i810_writeb(CR_INDEX_CGA, mmio, CR11);
reg = i810_readb(CR_DATA_CGA, mmio);
reg = (mode == OFF) ? reg & ~0x80 :
reg | 0x80;
i810_writeb(CR_INDEX_CGA, mmio, CR11);
i810_writeb(CR_DATA_CGA, mmio, reg);
}
/**
* i810_load_pll - loads values for the hardware PLL clock
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Loads the P, M, and N registers.
*/
static void i810_load_pll(struct i810fb_par *par)
{
u32 tmp1, tmp2;
u8 __iomem *mmio = par->mmio_start_virtual;
tmp1 = par->regs.M | par->regs.N << 16;
tmp2 = i810_readl(DCLK_2D, mmio);
tmp2 &= ~MN_MASK;
i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
tmp1 = par->regs.P;
tmp2 = i810_readl(DCLK_0DS, mmio);
tmp2 &= ~(P_OR << 16);
i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2);
i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1);
}
/**
* i810_load_vga - load standard VGA registers
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Load values to VGA registers
*/
static void i810_load_vga(struct i810fb_par *par)
{
u8 __iomem *mmio = par->mmio_start_virtual;
/* interlace */
i810_writeb(CR_INDEX_CGA, mmio, CR70);
i810_writeb(CR_DATA_CGA, mmio, par->interlace);
i810_writeb(CR_INDEX_CGA, mmio, CR00);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00);
i810_writeb(CR_INDEX_CGA, mmio, CR01);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01);
i810_writeb(CR_INDEX_CGA, mmio, CR02);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02);
i810_writeb(CR_INDEX_CGA, mmio, CR03);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03);
i810_writeb(CR_INDEX_CGA, mmio, CR04);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04);
i810_writeb(CR_INDEX_CGA, mmio, CR05);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05);
i810_writeb(CR_INDEX_CGA, mmio, CR06);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06);
i810_writeb(CR_INDEX_CGA, mmio, CR09);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09);
i810_writeb(CR_INDEX_CGA, mmio, CR10);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10);
i810_writeb(CR_INDEX_CGA, mmio, CR11);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11);
i810_writeb(CR_INDEX_CGA, mmio, CR12);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12);
i810_writeb(CR_INDEX_CGA, mmio, CR15);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15);
i810_writeb(CR_INDEX_CGA, mmio, CR16);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16);
}
/**
* i810_load_vgax - load extended VGA registers
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Load values to extended VGA registers
*/
static void i810_load_vgax(struct i810fb_par *par)
{
u8 __iomem *mmio = par->mmio_start_virtual;
i810_writeb(CR_INDEX_CGA, mmio, CR30);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30);
i810_writeb(CR_INDEX_CGA, mmio, CR31);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31);
i810_writeb(CR_INDEX_CGA, mmio, CR32);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32);
i810_writeb(CR_INDEX_CGA, mmio, CR33);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33);
i810_writeb(CR_INDEX_CGA, mmio, CR35);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35);
i810_writeb(CR_INDEX_CGA, mmio, CR39);
i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39);
}
/**
* i810_load_2d - load grahics registers
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Load values to graphics registers
*/
static void i810_load_2d(struct i810fb_par *par)
{
u32 tmp;
u8 tmp8;
u8 __iomem *mmio = par->mmio_start_virtual;
i810_writel(FW_BLC, mmio, par->watermark);
tmp = i810_readl(PIXCONF, mmio);
tmp |= 1 | 1 << 20;
i810_writel(PIXCONF, mmio, tmp);
i810_writel(OVRACT, mmio, par->ovract);
i810_writeb(GR_INDEX, mmio, GR10);
tmp8 = i810_readb(GR_DATA, mmio);
tmp8 |= 2;
i810_writeb(GR_INDEX, mmio, GR10);
i810_writeb(GR_DATA, mmio, tmp8);
}
/**
* i810_hires - enables high resolution mode
* @mmio: address of register space
*/
static void i810_hires(u8 __iomem *mmio)
{
u8 val;
i810_writeb(CR_INDEX_CGA, mmio, CR80);
val = i810_readb(CR_DATA_CGA, mmio);
i810_writeb(CR_INDEX_CGA, mmio, CR80);
i810_writeb(CR_DATA_CGA, mmio, val | 1);
/* Stop LCD displays from flickering */
i810_writel(MEM_MODE, mmio, i810_readl(MEM_MODE, mmio) | 4);
}
/**
* i810_load_pitch - loads the characters per line of the display
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Loads the characters per line
*/
static void i810_load_pitch(struct i810fb_par *par)
{
u32 tmp, pitch;
u8 val;
u8 __iomem *mmio = par->mmio_start_virtual;
pitch = par->pitch >> 3;
i810_writeb(SR_INDEX, mmio, SR01);
val = i810_readb(SR_DATA, mmio);
val &= 0xE0;
val |= 1 | 1 << 2;
i810_writeb(SR_INDEX, mmio, SR01);
i810_writeb(SR_DATA, mmio, val);
tmp = pitch & 0xFF;
i810_writeb(CR_INDEX_CGA, mmio, CR13);
i810_writeb(CR_DATA_CGA, mmio, (u8) tmp);
tmp = pitch >> 8;
i810_writeb(CR_INDEX_CGA, mmio, CR41);
val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F;
i810_writeb(CR_INDEX_CGA, mmio, CR41);
i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val);
}
/**
* i810_load_color - loads the color depth of the display
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Loads the color depth of the display and the graphics engine
*/
static void i810_load_color(struct i810fb_par *par)
{
u8 __iomem *mmio = par->mmio_start_virtual;
u32 reg1;
u16 reg2;
reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27);
reg2 = i810_readw(BLTCNTL, mmio) & ~0x30;
reg1 |= 0x8000 | par->pixconf;
reg2 |= par->bltcntl;
i810_writel(PIXCONF, mmio, reg1);
i810_writew(BLTCNTL, mmio, reg2);
}
/**
* i810_load_regs - loads all registers for the mode
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Loads registers
*/
static void i810_load_regs(struct i810fb_par *par)
{
u8 __iomem *mmio = par->mmio_start_virtual;
i810_screen_off(mmio, OFF);
i810_protect_regs(mmio, OFF);
i810_dram_off(mmio, OFF);
i810_load_pll(par);
i810_load_vga(par);
i810_load_vgax(par);
i810_dram_off(mmio, ON);
i810_load_2d(par);
i810_hires(mmio);
i810_screen_off(mmio, ON);
i810_protect_regs(mmio, ON);
i810_load_color(par);
i810_load_pitch(par);
}
static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue,
u8 __iomem *mmio)
{
i810_writeb(CLUT_INDEX_WRITE, mmio, regno);
i810_writeb(CLUT_DATA, mmio, red);
i810_writeb(CLUT_DATA, mmio, green);
i810_writeb(CLUT_DATA, mmio, blue);
}
static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue,
u8 __iomem *mmio)
{
i810_writeb(CLUT_INDEX_READ, mmio, regno);
*red = i810_readb(CLUT_DATA, mmio);
*green = i810_readb(CLUT_DATA, mmio);
*blue = i810_readb(CLUT_DATA, mmio);
}
/************************************************************
* VGA State Restore *
************************************************************/
static void i810_restore_pll(struct i810fb_par *par)
{
u32 tmp1, tmp2;
u8 __iomem *mmio = par->mmio_start_virtual;
tmp1 = par->hw_state.dclk_2d;
tmp2 = i810_readl(DCLK_2D, mmio);
tmp1 &= ~MN_MASK;
tmp2 &= MN_MASK;
i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
tmp1 = par->hw_state.dclk_1d;
tmp2 = i810_readl(DCLK_1D, mmio);
tmp1 &= ~MN_MASK;
tmp2 &= MN_MASK;
i810_writel(DCLK_1D, mmio, tmp1 | tmp2);
i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds);
}
static void i810_restore_dac(struct i810fb_par *par)
{
u32 tmp1, tmp2;
u8 __iomem *mmio = par->mmio_start_virtual;
tmp1 = par->hw_state.pixconf;
tmp2 = i810_readl(PIXCONF, mmio);
tmp1 &= DAC_BIT;
tmp2 &= ~DAC_BIT;
i810_writel(PIXCONF, mmio, tmp1 | tmp2);
}
static void i810_restore_vgax(struct i810fb_par *par)
{
u8 i, j;
u8 __iomem *mmio = par->mmio_start_virtual;
for (i = 0; i < 4; i++) {
i810_writeb(CR_INDEX_CGA, mmio, CR30+i);
i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i));
}
i810_writeb(CR_INDEX_CGA, mmio, CR35);
i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35);
i810_writeb(CR_INDEX_CGA, mmio, CR39);
i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
i810_writeb(CR_INDEX_CGA, mmio, CR41);
i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
/*restore interlace*/
i810_writeb(CR_INDEX_CGA, mmio, CR70);
i = par->hw_state.cr70;
i &= INTERLACE_BIT;
j = i810_readb(CR_DATA_CGA, mmio);
i810_writeb(CR_INDEX_CGA, mmio, CR70);
i810_writeb(CR_DATA_CGA, mmio, j | i);
i810_writeb(CR_INDEX_CGA, mmio, CR80);
i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80);
i810_writeb(MSR_WRITE, mmio, par->hw_state.msr);
i810_writeb(SR_INDEX, mmio, SR01);
i = (par->hw_state.sr01) & ~0xE0 ;
j = i810_readb(SR_DATA, mmio) & 0xE0;
i810_writeb(SR_INDEX, mmio, SR01);
i810_writeb(SR_DATA, mmio, i | j);
}
static void i810_restore_vga(struct i810fb_par *par)
{
u8 i;
u8 __iomem *mmio = par->mmio_start_virtual;
for (i = 0; i < 10; i++) {
i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i));
}
for (i = 0; i < 8; i++) {
i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i));
}
}
static void i810_restore_addr_map(struct i810fb_par *par)
{
u8 tmp;
u8 __iomem *mmio = par->mmio_start_virtual;
i810_writeb(GR_INDEX, mmio, GR10);
tmp = i810_readb(GR_DATA, mmio);
tmp &= ADDR_MAP_MASK;
tmp |= par->hw_state.gr10;
i810_writeb(GR_INDEX, mmio, GR10);
i810_writeb(GR_DATA, mmio, tmp);
}
static void i810_restore_2d(struct i810fb_par *par)
{
u32 tmp_long;
u16 tmp_word;
u8 __iomem *mmio = par->mmio_start_virtual;
tmp_word = i810_readw(BLTCNTL, mmio);
tmp_word &= ~(3 << 4);
tmp_word |= par->hw_state.bltcntl;
i810_writew(BLTCNTL, mmio, tmp_word);
i810_dram_off(mmio, OFF);
i810_writel(PIXCONF, mmio, par->hw_state.pixconf);
i810_dram_off(mmio, ON);
tmp_word = i810_readw(HWSTAM, mmio);
tmp_word &= 3 << 13;
tmp_word |= par->hw_state.hwstam;
i810_writew(HWSTAM, mmio, tmp_word);
tmp_long = i810_readl(FW_BLC, mmio);
tmp_long &= FW_BLC_MASK;
tmp_long |= par->hw_state.fw_blc;
i810_writel(FW_BLC, mmio, tmp_long);
i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga);
i810_writew(IER, mmio, par->hw_state.ier);
i810_writew(IMR, mmio, par->hw_state.imr);
i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas);
}
static void i810_restore_vga_state(struct i810fb_par *par)
{
u8 __iomem *mmio = par->mmio_start_virtual;
i810_screen_off(mmio, OFF);
i810_protect_regs(mmio, OFF);
i810_dram_off(mmio, OFF);
i810_restore_pll(par);
i810_restore_dac(par);
i810_restore_vga(par);
i810_restore_vgax(par);
i810_restore_addr_map(par);
i810_dram_off(mmio, ON);
i810_restore_2d(par);
i810_screen_off(mmio, ON);
i810_protect_regs(mmio, ON);
}
/***********************************************************************
* VGA State Save *
***********************************************************************/
static void i810_save_vgax(struct i810fb_par *par)
{
u8 i;
u8 __iomem *mmio = par->mmio_start_virtual;
for (i = 0; i < 4; i++) {
i810_writeb(CR_INDEX_CGA, mmio, CR30 + i);
*(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio);
}
i810_writeb(CR_INDEX_CGA, mmio, CR35);
par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio);
i810_writeb(CR_INDEX_CGA, mmio, CR39);
par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio);
i810_writeb(CR_INDEX_CGA, mmio, CR41);
par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio);
i810_writeb(CR_INDEX_CGA, mmio, CR70);
par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio);
par->hw_state.msr = i810_readb(MSR_READ, mmio);
i810_writeb(CR_INDEX_CGA, mmio, CR80);
par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio);
i810_writeb(SR_INDEX, mmio, SR01);
par->hw_state.sr01 = i810_readb(SR_DATA, mmio);
}
static void i810_save_vga(struct i810fb_par *par)
{
u8 i;
u8 __iomem *mmio = par->mmio_start_virtual;
for (i = 0; i < 10; i++) {
i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
*((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio);
}
for (i = 0; i < 8; i++) {
i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
*((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio);
}
}
static void i810_save_2d(struct i810fb_par *par)
{
u8 __iomem *mmio = par->mmio_start_virtual;
par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio);
par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio);
par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio);
par->hw_state.pixconf = i810_readl(PIXCONF, mmio);
par->hw_state.fw_blc = i810_readl(FW_BLC, mmio);
par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio);
par->hw_state.hwstam = i810_readw(HWSTAM, mmio);
par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio);
par->hw_state.ier = i810_readw(IER, mmio);
par->hw_state.imr = i810_readw(IMR, mmio);
par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio);
}
static void i810_save_vga_state(struct i810fb_par *par)
{
i810_save_vga(par);
i810_save_vgax(par);
i810_save_2d(par);
}
/************************************************************
* Helpers *
************************************************************/
/**
* get_line_length - calculates buffer pitch in bytes
* @par: pointer to i810fb_par structure
* @xres_virtual: virtual resolution of the frame
* @bpp: bits per pixel
*
* DESCRIPTION:
* Calculates buffer pitch in bytes.
*/
static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp)
{
u32 length;
length = xres_virtual*bpp;
length = (length+31)&-32;
length >>= 3;
return length;
}
/**
* i810_calc_dclk - calculates the P, M, and N values of a pixelclock value
* @freq: target pixelclock in picoseconds
* @m: where to write M register
* @n: where to write N register
* @p: where to write P register
*
* DESCRIPTION:
* Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P)
* Repeatedly computes the Freq until the actual Freq is equal to
* the target Freq or until the loop count is zero. In the latter
* case, the actual frequency nearest the target will be used.
*/
static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p)
{
u32 m_reg, n_reg, p_divisor, n_target_max;
u32 m_target, n_target, p_target, n_best, m_best, mod;
u32 f_out, target_freq, diff = 0, mod_min, diff_min;
diff_min = mod_min = 0xFFFFFFFF;
n_best = m_best = m_target = f_out = 0;
target_freq = freq;
n_target_max = 30;
/*
* find P such that target freq is 16x reference freq (Hz).
*/
p_divisor = 1;
p_target = 0;
while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) &&
p_divisor <= 32) {
p_divisor <<= 1;
p_target++;
}
n_reg = m_reg = n_target = 3;
while (diff_min && mod_min && (n_target < n_target_max)) {
f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg);
mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg);
m_target = m_reg;
n_target = n_reg;
if (f_out <= target_freq) {
n_reg++;
diff = target_freq - f_out;
} else {
m_reg++;
diff = f_out - target_freq;
}
if (diff_min > diff) {
diff_min = diff;
n_best = n_target;
m_best = m_target;
}
if (!diff && mod_min > mod) {
mod_min = mod;
n_best = n_target;
m_best = m_target;
}
}
if (m) *m = (m_best - 2) & 0x3FF;
if (n) *n = (n_best - 2) & 0x3FF;
if (p) *p = (p_target << 4);
}
/*************************************************************
* Hardware Cursor Routines *
*************************************************************/
/**
* i810_enable_cursor - show or hide the hardware cursor
* @mmio: address of register space
* @mode: show (1) or hide (0)
*
* Description:
* Shows or hides the hardware cursor
*/
static void i810_enable_cursor(u8 __iomem *mmio, int mode)
{
u32 temp;
temp = i810_readl(PIXCONF, mmio);
temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK :
temp & ~CURSOR_ENABLE_MASK;
i810_writel(PIXCONF, mmio, temp);
}
static void i810_reset_cursor_image(struct i810fb_par *par)
{
u8 __iomem *addr = par->cursor_heap.virtual;
int i, j;
for (i = 64; i--; ) {
for (j = 0; j < 8; j++) {
i810_writeb(j, addr, 0xff);
i810_writeb(j+8, addr, 0x00);
}
addr +=16;
}
}
static void i810_load_cursor_image(int width, int height, u8 *data,
struct i810fb_par *par)
{
u8 __iomem *addr = par->cursor_heap.virtual;
int i, j, w = width/8;
int mod = width % 8, t_mask, d_mask;
t_mask = 0xff >> mod;
d_mask = ~(0xff >> mod);
for (i = height; i--; ) {
for (j = 0; j < w; j++) {
i810_writeb(j+0, addr, 0x00);
i810_writeb(j+8, addr, *data++);
}
if (mod) {
i810_writeb(j+0, addr, t_mask);
i810_writeb(j+8, addr, *data++ & d_mask);
}
addr += 16;
}
}
static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info)
{
struct i810fb_par *par = info->par;
u8 __iomem *mmio = par->mmio_start_virtual;
u8 red, green, blue, trans, temp;
i810fb_getcolreg(bg, &red, &green, &blue, &trans, info);
temp = i810_readb(PIXCONF1, mmio);
i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
i810_write_dac(4, red, green, blue, mmio);
i810_writeb(PIXCONF1, mmio, temp);
i810fb_getcolreg(fg, &red, &green, &blue, &trans, info);
temp = i810_readb(PIXCONF1, mmio);
i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
i810_write_dac(5, red, green, blue, mmio);
i810_writeb(PIXCONF1, mmio, temp);
}
/**
* i810_init_cursor - initializes the cursor
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Initializes the cursor registers
*/
static void i810_init_cursor(struct i810fb_par *par)
{
u8 __iomem *mmio = par->mmio_start_virtual;
i810_enable_cursor(mmio, OFF);
i810_writel(CURBASE, mmio, par->cursor_heap.physical);
i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR);
}
/*********************************************************************
* Framebuffer hook helpers *
*********************************************************************/
/**
* i810_round_off - Round off values to capability of hardware
* @var: pointer to fb_var_screeninfo structure
*
* DESCRIPTION:
* @var contains user-defined information for the mode to be set.
* This will try modify those values to ones nearest the
* capability of the hardware
*/
static void i810_round_off(struct fb_var_screeninfo *var)
{
u32 xres, yres, vxres, vyres;
/*
* Presently supports only these configurations
*/
xres = var->xres;
yres = var->yres;
vxres = var->xres_virtual;
vyres = var->yres_virtual;
var->bits_per_pixel += 7;
var->bits_per_pixel &= ~7;
if (var->bits_per_pixel < 8)
var->bits_per_pixel = 8;
if (var->bits_per_pixel > 32)
var->bits_per_pixel = 32;
round_off_xres(&xres);
if (xres < 40)
xres = 40;
if (xres > 2048)
xres = 2048;
xres = (xres + 7) & ~7;
if (vxres < xres)
vxres = xres;
round_off_yres(&xres, &yres);
if (yres < 1)
yres = 1;
if (yres >= 2048)
yres = 2048;
if (vyres < yres)
vyres = yres;
if (var->bits_per_pixel == 32)
var->accel_flags = 0;
/* round of horizontal timings to nearest 8 pixels */
var->left_margin = (var->left_margin + 4) & ~7;
var->right_margin = (var->right_margin + 4) & ~7;
var->hsync_len = (var->hsync_len + 4) & ~7;
if (var->vmode & FB_VMODE_INTERLACED) {
if (!((yres + var->upper_margin + var->vsync_len +
var->lower_margin) & 1))
var->upper_margin++;
}
var->xres = xres;
var->yres = yres;
var->xres_virtual = vxres;
var->yres_virtual = vyres;
}
/**
* set_color_bitfields - sets rgba fields
* @var: pointer to fb_var_screeninfo
*
* DESCRIPTION:
* The length, offset and ordering for each color field
* (red, green, blue) will be set as specified
* by the hardware
*/
static void set_color_bitfields(struct fb_var_screeninfo *var)
{
switch (var->bits_per_pixel) {
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16:
var->green.length = (var->green.length == 5) ? 5 : 6;
var->red.length = 5;
var->blue.length = 5;
var->transp.length = 6 - var->green.length;
var->blue.offset = 0;
var->green.offset = 5;
var->red.offset = 5 + var->green.length;
var->transp.offset = (5 + var->red.offset) & 15;
break;
case 24: /* RGB 888 */
case 32: /* RGBA 8888 */
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.length = var->bits_per_pixel - 24;
var->transp.offset = (var->transp.length) ? 24 : 0;
break;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
}
/**
* i810_check_params - check if contents in var are valid
* @var: pointer to fb_var_screeninfo
* @info: pointer to fb_info
*
* DESCRIPTION:
* This will check if the framebuffer size is sufficient
* for the current mode and if the user's monitor has the
* required specifications to display the current mode.
*/
static int i810_check_params(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct i810fb_par *par = info->par;
int line_length, vidmem, mode_valid = 0, retval = 0;
u32 vyres = var->yres_virtual, vxres = var->xres_virtual;
/*
* Memory limit
*/
line_length = get_line_length(par, vxres, var->bits_per_pixel);
vidmem = line_length*vyres;
if (vidmem > par->fb.size) {
vyres = par->fb.size/line_length;
if (vyres < var->yres) {
vyres = info->var.yres;
vxres = par->fb.size/vyres;
vxres /= var->bits_per_pixel >> 3;
line_length = get_line_length(par, vxres,
var->bits_per_pixel);
vidmem = line_length * info->var.yres;
if (vxres < var->xres) {
printk("i810fb: required video memory, "
"%d bytes, for %dx%d-%d (virtual) "
"is out of range\n",
vidmem, vxres, vyres,
var->bits_per_pixel);
return -ENOMEM;
}
}
}
var->xres_virtual = vxres;
var->yres_virtual = vyres;
/*
* Monitor limit
*/
switch (var->bits_per_pixel) {
case 8:
info->monspecs.dclkmax = 234000000;
break;
case 16:
info->monspecs.dclkmax = 229000000;
break;
case 24:
case 32:
info->monspecs.dclkmax = 204000000;
break;
}
info->monspecs.dclkmin = 15000000;
if (!fb_validate_mode(var, info))
mode_valid = 1;
#ifdef CONFIG_FB_I810_I2C
if (!mode_valid && info->monspecs.gtf &&
!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
mode_valid = 1;
if (!mode_valid && info->monspecs.modedb_len) {
const struct fb_videomode *mode;
mode = fb_find_best_mode(var, &info->modelist);
if (mode) {
fb_videomode_to_var(var, mode);
mode_valid = 1;
}
}
#endif
if (!mode_valid && info->monspecs.modedb_len == 0) {
if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) {
int default_sync = (info->monspecs.hfmin-HFMIN)
|(info->monspecs.hfmax-HFMAX)
|(info->monspecs.vfmin-VFMIN)
|(info->monspecs.vfmax-VFMAX);
printk("i810fb: invalid video mode%s\n",
default_sync ? "" : ". Specifying "
"vsyncN/hsyncN parameters may help");
retval = -EINVAL;
}
}
return retval;
}
/**
* encode_fix - fill up fb_fix_screeninfo structure
* @fix: pointer to fb_fix_screeninfo
* @info: pointer to fb_info
*
* DESCRIPTION:
* This will set up parameters that are unmodifiable by the user.
*/
static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
{
struct i810fb_par *par = info->par;
memset(fix, 0, sizeof(struct fb_fix_screeninfo));
strcpy(fix->id, "I810");
mutex_lock(&info->mm_lock);
fix->smem_start = par->fb.physical;
fix->smem_len = par->fb.size;
mutex_unlock(&info->mm_lock);
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
fix->xpanstep = 8;
fix->ypanstep = 1;
switch (info->var.bits_per_pixel) {
case 8:
fix->visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
case 24:
case 32:
if (info->var.nonstd)
fix->visual = FB_VISUAL_DIRECTCOLOR;
else
fix->visual = FB_VISUAL_TRUECOLOR;
break;
default:
return -EINVAL;
}
fix->ywrapstep = 0;
fix->line_length = par->pitch;
fix->mmio_start = par->mmio_start_phys;
fix->mmio_len = MMIO_SIZE;
fix->accel = FB_ACCEL_I810;
return 0;
}
/**
* decode_var - modify par according to contents of var
* @var: pointer to fb_var_screeninfo
* @par: pointer to i810fb_par
*
* DESCRIPTION:
* Based on the contents of @var, @par will be dynamically filled up.
* @par contains all information necessary to modify the hardware.
*/
static void decode_var(const struct fb_var_screeninfo *var,
struct i810fb_par *par)
{
u32 xres, yres, vxres, vyres;
xres = var->xres;
yres = var->yres;
vxres = var->xres_virtual;
vyres = var->yres_virtual;
switch (var->bits_per_pixel) {
case 8:
par->pixconf = PIXCONF8;
par->bltcntl = 0;
par->depth = 1;
par->blit_bpp = BPP8;
break;
case 16:
if (var->green.length == 5)
par->pixconf = PIXCONF15;
else
par->pixconf = PIXCONF16;
par->bltcntl = 16;
par->depth = 2;
par->blit_bpp = BPP16;
break;
case 24:
par->pixconf = PIXCONF24;
par->bltcntl = 32;
par->depth = 3;
par->blit_bpp = BPP24;
break;
case 32:
par->pixconf = PIXCONF32;
par->bltcntl = 0;
par->depth = 4;
par->blit_bpp = 3 << 24;
break;
}
if (var->nonstd && var->bits_per_pixel != 8)
par->pixconf |= 1 << 27;
i810_calc_dclk(var->pixclock, &par->regs.M,
&par->regs.N, &par->regs.P);
i810fb_encode_registers(var, par, xres, yres);
par->watermark = i810_get_watermark(var, par);
par->pitch = get_line_length(par, vxres, var->bits_per_pixel);
}
/**
* i810fb_getcolreg - gets red, green and blue values of the hardware DAC
* @regno: DAC index
* @red: red
* @green: green
* @blue: blue
* @transp: transparency (alpha)
* @info: pointer to fb_info
*
* DESCRIPTION:
* Gets the red, green and blue values of the hardware DAC as pointed by @regno
* and writes them to @red, @green and @blue respectively
*/
static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue,
u8 *transp, struct fb_info *info)
{
struct i810fb_par *par = info->par;
u8 __iomem *mmio = par->mmio_start_virtual;
u8 temp;
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
if ((info->var.green.length == 5 && regno > 31) ||
(info->var.green.length == 6 && regno > 63))
return 1;
}
temp = i810_readb(PIXCONF1, mmio);
i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
info->var.green.length == 5)
i810_read_dac(regno * 8, red, green, blue, mmio);
else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
info->var.green.length == 6) {
u8 tmp;
i810_read_dac(regno * 8, red, &tmp, blue, mmio);
i810_read_dac(regno * 4, &tmp, green, &tmp, mmio);
}
else
i810_read_dac(regno, red, green, blue, mmio);
*transp = 0;
i810_writeb(PIXCONF1, mmio, temp);
return 0;
}
/******************************************************************
* Framebuffer device-specific hooks *
******************************************************************/
static int i810fb_open(struct fb_info *info, int user)
{
struct i810fb_par *par = info->par;
mutex_lock(&par->open_lock);
if (par->use_count == 0) {
memset(&par->state, 0, sizeof(struct vgastate));
par->state.flags = VGA_SAVE_CMAP;
par->state.vgabase = par->mmio_start_virtual;
save_vga(&par->state);
i810_save_vga_state(par);
}
par->use_count++;
mutex_unlock(&par->open_lock);
return 0;
}
static int i810fb_release(struct fb_info *info, int user)
{
struct i810fb_par *par = info->par;
mutex_lock(&par->open_lock);
if (par->use_count == 0) {
mutex_unlock(&par->open_lock);
return -EINVAL;
}
if (par->use_count == 1) {
i810_restore_vga_state(par);
restore_vga(&par->state);
}
par->use_count--;
mutex_unlock(&par->open_lock);
return 0;
}
static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct i810fb_par *par = info->par;
u8 __iomem *mmio = par->mmio_start_virtual;
u8 temp;
int i;
if (regno > 255) return 1;
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
if ((info->var.green.length == 5 && regno > 31) ||
(info->var.green.length == 6 && regno > 63))
return 1;
}
if (info->var.grayscale)
red = green = blue = (19595 * red + 38470 * green +
7471 * blue) >> 16;
temp = i810_readb(PIXCONF1, mmio);
i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
info->var.green.length == 5) {
for (i = 0; i < 8; i++)
i810_write_dac((u8) (regno * 8) + i, (u8) red,
(u8) green, (u8) blue, mmio);
} else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
info->var.green.length == 6) {
u8 r, g, b;
if (regno < 32) {
for (i = 0; i < 8; i++)
i810_write_dac((u8) (regno * 8) + i,
(u8) red, (u8) green,
(u8) blue, mmio);
}
i810_read_dac((u8) (regno*4), &r, &g, &b, mmio);
for (i = 0; i < 4; i++)
i810_write_dac((u8) (regno*4) + i, r, (u8) green,
b, mmio);
} else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
i810_write_dac((u8) regno, (u8) red, (u8) green,
(u8) blue, mmio);
}
i810_writeb(PIXCONF1, mmio, temp);
if (regno < 16) {
switch (info->var.bits_per_pixel) {
case 16:
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
if (info->var.green.length == 5)
((u32 *)info->pseudo_palette)[regno] =
(regno << 10) | (regno << 5) |
regno;
else
((u32 *)info->pseudo_palette)[regno] =
(regno << 11) | (regno << 5) |
regno;
} else {
if (info->var.green.length == 5) {
/* RGB 555 */
((u32 *)info->pseudo_palette)[regno] =
((red & 0xf800) >> 1) |
((green & 0xf800) >> 6) |
((blue & 0xf800) >> 11);
} else {
/* RGB 565 */
((u32 *)info->pseudo_palette)[regno] =
(red & 0xf800) |
((green & 0xf800) >> 5) |
((blue & 0xf800) >> 11);
}
}
break;
case 24: /* RGB 888 */
case 32: /* RGBA 8888 */
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
((u32 *)info->pseudo_palette)[regno] =
(regno << 16) | (regno << 8) |
regno;
else
((u32 *)info->pseudo_palette)[regno] =
((red & 0xff00) << 8) |
(green & 0xff00) |
((blue & 0xff00) >> 8);
break;
}
}
return 0;
}
static int i810fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct i810fb_par *par = info->par;
u32 total;
total = var->xoffset * par->depth +
var->yoffset * info->fix.line_length;
i810fb_load_front(total, info);
return 0;
}
static int i810fb_blank (int blank_mode, struct fb_info *info)
{
struct i810fb_par *par = info->par;
u8 __iomem *mmio = par->mmio_start_virtual;
int mode = 0, pwr, scr_off = 0;
pwr = i810_readl(PWR_CLKC, mmio);
switch (blank_mode) {
case FB_BLANK_UNBLANK:
mode = POWERON;
pwr |= 1;
scr_off = ON;
break;
case FB_BLANK_NORMAL:
mode = POWERON;
pwr |= 1;
scr_off = OFF;
break;
case FB_BLANK_VSYNC_SUSPEND:
mode = STANDBY;
pwr |= 1;
scr_off = OFF;
break;
case FB_BLANK_HSYNC_SUSPEND:
mode = SUSPEND;
pwr |= 1;
scr_off = OFF;
break;
case FB_BLANK_POWERDOWN:
mode = POWERDOWN;
pwr &= ~1;
scr_off = OFF;
break;
default:
return -EINVAL;
}
i810_screen_off(mmio, scr_off);
i810_writel(HVSYNC, mmio, mode);
i810_writel(PWR_CLKC, mmio, pwr);
return 0;
}
static int i810fb_set_par(struct fb_info *info)
{
struct i810fb_par *par = info->par;
decode_var(&info->var, par);
i810_load_regs(par);
i810_init_cursor(par);
encode_fix(&info->fix, info);
if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) {
info->flags = FBINFO_HWACCEL_YPAN |
FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_IMAGEBLIT;
info->pixmap.scan_align = 2;
} else {
info->pixmap.scan_align = 1;
info->flags = FBINFO_HWACCEL_YPAN;
}
return 0;
}
static int i810fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int err;
if (IS_DVT) {
var->vmode &= ~FB_VMODE_MASK;
var->vmode |= FB_VMODE_NONINTERLACED;
}
if (var->vmode & FB_VMODE_DOUBLE) {
var->vmode &= ~FB_VMODE_MASK;
var->vmode |= FB_VMODE_NONINTERLACED;
}
i810_round_off(var);
if ((err = i810_check_params(var, info)))
return err;
i810fb_fill_var_timings(var);
set_color_bitfields(var);
return 0;
}
static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct i810fb_par *par = info->par;
u8 __iomem *mmio = par->mmio_start_virtual;
if (par->dev_flags & LOCKUP)
return -ENXIO;
if (cursor->image.width > 64 || cursor->image.height > 64)
return -ENXIO;
if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) {
i810_init_cursor(par);
cursor->set |= FB_CUR_SETALL;
}
i810_enable_cursor(mmio, OFF);
if (cursor->set & FB_CUR_SETPOS) {
u32 tmp;
tmp = (cursor->image.dx - info->var.xoffset) & 0xffff;
tmp |= (cursor->image.dy - info->var.yoffset) << 16;
i810_writel(CURPOS, mmio, tmp);
}
if (cursor->set & FB_CUR_SETSIZE)
i810_reset_cursor_image(par);
if (cursor->set & FB_CUR_SETCMAP)
i810_load_cursor_colors(cursor->image.fg_color,
cursor->image.bg_color,
info);
if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
int size = ((cursor->image.width + 7) >> 3) *
cursor->image.height;
int i;
u8 *data = kmalloc(64 * 8, GFP_ATOMIC);
if (data == NULL)
return -ENOMEM;
switch (cursor->rop) {
case ROP_XOR:
for (i = 0; i < size; i++)
data[i] = cursor->image.data[i] ^ cursor->mask[i];
break;
case ROP_COPY:
default:
for (i = 0; i < size; i++)
data[i] = cursor->image.data[i] & cursor->mask[i];
break;
}
i810_load_cursor_image(cursor->image.width,
cursor->image.height, data,
par);
kfree(data);
}
if (cursor->enable)
i810_enable_cursor(mmio, ON);
return 0;
}
static const struct fb_ops i810fb_ops = {
.owner = THIS_MODULE,
.fb_open = i810fb_open,
.fb_release = i810fb_release,
.fb_check_var = i810fb_check_var,
.fb_set_par = i810fb_set_par,
.fb_setcolreg = i810fb_setcolreg,
.fb_blank = i810fb_blank,
.fb_pan_display = i810fb_pan_display,
.fb_fillrect = i810fb_fillrect,
.fb_copyarea = i810fb_copyarea,
.fb_imageblit = i810fb_imageblit,
.fb_cursor = i810fb_cursor,
.fb_sync = i810fb_sync,
};
/***********************************************************************
* Power Management *
***********************************************************************/
static int i810fb_suspend(struct pci_dev *dev, pm_message_t mesg)
{
struct fb_info *info = pci_get_drvdata(dev);
struct i810fb_par *par = info->par;
par->cur_state = mesg.event;
switch (mesg.event) {
case PM_EVENT_FREEZE:
case PM_EVENT_PRETHAW:
dev->dev.power.power_state = mesg;
return 0;
}
console_lock();
fb_set_suspend(info, 1);
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
i810fb_blank(FB_BLANK_POWERDOWN, info);
agp_unbind_memory(par->i810_gtt.i810_fb_memory);
agp_unbind_memory(par->i810_gtt.i810_cursor_memory);
pci_save_state(dev);
pci_disable_device(dev);
pci_set_power_state(dev, pci_choose_state(dev, mesg));
console_unlock();
return 0;
}
static int i810fb_resume(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
struct i810fb_par *par = info->par;
int cur_state = par->cur_state;
par->cur_state = PM_EVENT_ON;
if (cur_state == PM_EVENT_FREEZE) {
pci_set_power_state(dev, PCI_D0);
return 0;
}
console_lock();
pci_set_power_state(dev, PCI_D0);
pci_restore_state(dev);
if (pci_enable_device(dev))
goto fail;
pci_set_master(dev);
agp_bind_memory(par->i810_gtt.i810_fb_memory,
par->fb.offset);
agp_bind_memory(par->i810_gtt.i810_cursor_memory,
par->cursor_heap.offset);
i810fb_set_par(info);
fb_set_suspend (info, 0);
info->fbops->fb_blank(VESA_NO_BLANKING, info);
fail:
console_unlock();
return 0;
}
/***********************************************************************
* AGP resource allocation *
***********************************************************************/
static void i810_fix_pointers(struct i810fb_par *par)
{
par->fb.physical = par->aperture.physical+(par->fb.offset << 12);
par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12);
par->iring.physical = par->aperture.physical +
(par->iring.offset << 12);
par->iring.virtual = par->aperture.virtual +
(par->iring.offset << 12);
par->cursor_heap.virtual = par->aperture.virtual+
(par->cursor_heap.offset << 12);
}
static void i810_fix_offsets(struct i810fb_par *par)
{
if (vram + 1 > par->aperture.size >> 20)
vram = (par->aperture.size >> 20) - 1;
if (v_offset_default > (par->aperture.size >> 20))
v_offset_default = (par->aperture.size >> 20);
if (vram + v_offset_default + 1 > par->aperture.size >> 20)
v_offset_default = (par->aperture.size >> 20) - (vram + 1);
par->fb.size = vram << 20;
par->fb.offset = v_offset_default << 20;
par->fb.offset >>= 12;
par->iring.offset = par->fb.offset + (par->fb.size >> 12);
par->iring.size = RINGBUFFER_SIZE;
par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12);
par->cursor_heap.size = 4096;
}
static int i810_alloc_agp_mem(struct fb_info *info)
{
struct i810fb_par *par = info->par;
int size;
struct agp_bridge_data *bridge;
i810_fix_offsets(par);
size = par->fb.size + par->iring.size;
if (!(bridge = agp_backend_acquire(par->dev))) {
printk("i810fb_alloc_fbmem: cannot acquire agpgart\n");
return -ENODEV;
}
if (!(par->i810_gtt.i810_fb_memory =
agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) {
printk("i810fb_alloc_fbmem: can't allocate framebuffer "
"memory\n");
agp_backend_release(bridge);
return -ENOMEM;
}
if (agp_bind_memory(par->i810_gtt.i810_fb_memory,
par->fb.offset)) {
printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n");
agp_backend_release(bridge);
return -EBUSY;
}
if (!(par->i810_gtt.i810_cursor_memory =
agp_allocate_memory(bridge, par->cursor_heap.size >> 12,
AGP_PHYSICAL_MEMORY))) {
printk("i810fb_alloc_cursormem: can't allocate "
"cursor memory\n");
agp_backend_release(bridge);
return -ENOMEM;
}
if (agp_bind_memory(par->i810_gtt.i810_cursor_memory,
par->cursor_heap.offset)) {
printk("i810fb_alloc_cursormem: cannot bind cursor memory\n");
agp_backend_release(bridge);
return -EBUSY;
}
par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical;
i810_fix_pointers(par);
agp_backend_release(bridge);
return 0;
}
/***************************************************************
* Initialization *
***************************************************************/
/**
* i810_init_monspecs
* @info: pointer to device specific info structure
*
* DESCRIPTION:
* Sets the user monitor's horizontal and vertical
* frequency limits
*/
static void i810_init_monspecs(struct fb_info *info)
{
if (!hsync1)
hsync1 = HFMIN;
if (!hsync2)
hsync2 = HFMAX;
if (!info->monspecs.hfmax)
info->monspecs.hfmax = hsync2;
if (!info->monspecs.hfmin)
info->monspecs.hfmin = hsync1;
if (hsync2 < hsync1)
info->monspecs.hfmin = hsync2;
if (!vsync1)
vsync1 = VFMIN;
if (!vsync2)
vsync2 = VFMAX;
if (IS_DVT && vsync1 < 60)
vsync1 = 60;
if (!info->monspecs.vfmax)
info->monspecs.vfmax = vsync2;
if (!info->monspecs.vfmin)
info->monspecs.vfmin = vsync1;
if (vsync2 < vsync1)
info->monspecs.vfmin = vsync2;
}
/**
* i810_init_defaults - initializes default values to use
* @par: pointer to i810fb_par structure
* @info: pointer to current fb_info structure
*/
static void i810_init_defaults(struct i810fb_par *par, struct fb_info *info)
{
mutex_init(&par->open_lock);
if (voffset)
v_offset_default = voffset;
else if (par->aperture.size > 32 * 1024 * 1024)
v_offset_default = 16;
else
v_offset_default = 8;
if (!vram)
vram = 1;
if (accel)
par->dev_flags |= HAS_ACCELERATION;
if (sync)
par->dev_flags |= ALWAYS_SYNC;
par->ddc_num = (ddc3 ? 3 : 2);
if (bpp < 8)
bpp = 8;
par->i810fb_ops = i810fb_ops;
if (xres)
info->var.xres = xres;
else
info->var.xres = 640;
if (yres)
info->var.yres = yres;
else
info->var.yres = 480;
if (!vyres)
vyres = (vram << 20)/(info->var.xres*bpp >> 3);
info->var.yres_virtual = vyres;
info->var.bits_per_pixel = bpp;
if (dcolor)
info->var.nonstd = 1;
if (par->dev_flags & HAS_ACCELERATION)
info->var.accel_flags = 1;
i810_init_monspecs(info);
}
/**
* i810_init_device - initialize device
* @par: pointer to i810fb_par structure
*/
static void i810_init_device(struct i810fb_par *par)
{
u8 reg;
u8 __iomem *mmio = par->mmio_start_virtual;
if (mtrr)
par->wc_cookie= arch_phys_wc_add((u32) par->aperture.physical,
par->aperture.size);
i810_init_cursor(par);
/* mvo: enable external vga-connector (for laptops) */
if (extvga) {
i810_writel(HVSYNC, mmio, 0);
i810_writel(PWR_CLKC, mmio, 3);
}
pci_read_config_byte(par->dev, 0x50, ®);
reg &= FREQ_MASK;
par->mem_freq = (reg) ? 133 : 100;
}
static int i810_allocate_pci_resource(struct i810fb_par *par,
const struct pci_device_id *entry)
{
int err;
if ((err = pci_enable_device(par->dev))) {
printk("i810fb_init: cannot enable device\n");
return err;
}
par->res_flags |= PCI_DEVICE_ENABLED;
if (pci_resource_len(par->dev, 0) > 512 * 1024) {
par->aperture.physical = pci_resource_start(par->dev, 0);
par->aperture.size = pci_resource_len(par->dev, 0);
par->mmio_start_phys = pci_resource_start(par->dev, 1);
} else {
par->aperture.physical = pci_resource_start(par->dev, 1);
par->aperture.size = pci_resource_len(par->dev, 1);
par->mmio_start_phys = pci_resource_start(par->dev, 0);
}
if (!par->aperture.size) {
printk("i810fb_init: device is disabled\n");
return -ENOMEM;
}
if (!request_mem_region(par->aperture.physical,
par->aperture.size,
i810_pci_list[entry->driver_data])) {
printk("i810fb_init: cannot request framebuffer region\n");
return -ENODEV;
}
par->res_flags |= FRAMEBUFFER_REQ;
par->aperture.virtual = ioremap_wc(par->aperture.physical,
par->aperture.size);
if (!par->aperture.virtual) {
printk("i810fb_init: cannot remap framebuffer region\n");
return -ENODEV;
}
if (!request_mem_region(par->mmio_start_phys,
MMIO_SIZE,
i810_pci_list[entry->driver_data])) {
printk("i810fb_init: cannot request mmio region\n");
return -ENODEV;
}
par->res_flags |= MMIO_REQ;
par->mmio_start_virtual = ioremap(par->mmio_start_phys,
MMIO_SIZE);
if (!par->mmio_start_virtual) {
printk("i810fb_init: cannot remap mmio region\n");
return -ENODEV;
}
return 0;
}
static void i810fb_find_init_mode(struct fb_info *info)
{
struct fb_videomode mode;
struct fb_var_screeninfo var;
struct fb_monspecs *specs = &info->monspecs;
int found = 0;
#ifdef CONFIG_FB_I810_I2C
int i;
int err = 1;
struct i810fb_par *par = info->par;
#endif
INIT_LIST_HEAD(&info->modelist);
memset(&mode, 0, sizeof(struct fb_videomode));
var = info->var;
#ifdef CONFIG_FB_I810_I2C
i810_create_i2c_busses(par);
for (i = 0; i < par->ddc_num + 1; i++) {
err = i810_probe_i2c_connector(info, &par->edid, i);
if (!err)
break;
}
if (!err)
printk("i810fb_init_pci: DDC probe successful\n");
fb_edid_to_monspecs(par->edid, specs);
if (specs->modedb == NULL)
printk("i810fb_init_pci: Unable to get Mode Database\n");
fb_videomode_to_modelist(specs->modedb, specs->modedb_len,
&info->modelist);
if (specs->modedb != NULL) {
const struct fb_videomode *m;
if (xres && yres) {
if ((m = fb_find_best_mode(&var, &info->modelist))) {
mode = *m;
found = 1;
}
}
if (!found) {
m = fb_find_best_display(&info->monspecs, &info->modelist);
mode = *m;
found = 1;
}
fb_videomode_to_var(&var, &mode);
}
#endif
if (mode_option)
fb_find_mode(&var, info, mode_option, specs->modedb,
specs->modedb_len, (found) ? &mode : NULL,
info->var.bits_per_pixel);
info->var = var;
fb_destroy_modedb(specs->modedb);
specs->modedb = NULL;
}
#ifndef MODULE
static int i810fb_setup(char *options)
{
char *this_opt, *suffix = NULL;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "mtrr", 4))
mtrr = true;
else if (!strncmp(this_opt, "accel", 5))
accel = true;
else if (!strncmp(this_opt, "extvga", 6))
extvga = true;
else if (!strncmp(this_opt, "sync", 4))
sync = true;
else if (!strncmp(this_opt, "vram:", 5))
vram = (simple_strtoul(this_opt+5, NULL, 0));
else if (!strncmp(this_opt, "voffset:", 8))
voffset = (simple_strtoul(this_opt+8, NULL, 0));
else if (!strncmp(this_opt, "xres:", 5))
xres = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "yres:", 5))
yres = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "vyres:", 6))
vyres = simple_strtoul(this_opt+6, NULL, 0);
else if (!strncmp(this_opt, "bpp:", 4))
bpp = simple_strtoul(this_opt+4, NULL, 0);
else if (!strncmp(this_opt, "hsync1:", 7)) {
hsync1 = simple_strtoul(this_opt+7, &suffix, 0);
if (strncmp(suffix, "H", 1))
hsync1 *= 1000;
} else if (!strncmp(this_opt, "hsync2:", 7)) {
hsync2 = simple_strtoul(this_opt+7, &suffix, 0);
if (strncmp(suffix, "H", 1))
hsync2 *= 1000;
} else if (!strncmp(this_opt, "vsync1:", 7))
vsync1 = simple_strtoul(this_opt+7, NULL, 0);
else if (!strncmp(this_opt, "vsync2:", 7))
vsync2 = simple_strtoul(this_opt+7, NULL, 0);
else if (!strncmp(this_opt, "dcolor", 6))
dcolor = true;
else if (!strncmp(this_opt, "ddc3", 4))
ddc3 = true;
else
mode_option = this_opt;
}
return 0;
}
#endif
static int i810fb_init_pci(struct pci_dev *dev,
const struct pci_device_id *entry)
{
struct fb_info *info;
struct i810fb_par *par = NULL;
struct fb_videomode mode;
int err = -1, vfreq, hfreq, pixclock;
err = aperture_remove_conflicting_pci_devices(dev, "i810fb");
if (err)
return err;
info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev);
if (!info)
return -ENOMEM;
par = info->par;
par->dev = dev;
if (!(info->pixmap.addr = kzalloc(8*1024, GFP_KERNEL))) {
i810fb_release_resource(info, par);
return -ENOMEM;
}
info->pixmap.size = 8*1024;
info->pixmap.buf_align = 8;
info->pixmap.access_align = 32;
info->pixmap.flags = FB_PIXMAP_SYSTEM;
if ((err = i810_allocate_pci_resource(par, entry))) {
i810fb_release_resource(info, par);
return err;
}
i810_init_defaults(par, info);
if ((err = i810_alloc_agp_mem(info))) {
i810fb_release_resource(info, par);
return err;
}
i810_init_device(par);
info->screen_base = par->fb.virtual;
info->fbops = &par->i810fb_ops;
info->pseudo_palette = par->pseudo_palette;
fb_alloc_cmap(&info->cmap, 256, 0);
i810fb_find_init_mode(info);
if ((err = info->fbops->fb_check_var(&info->var, info))) {
i810fb_release_resource(info, par);
return err;
}
fb_var_to_videomode(&mode, &info->var);
fb_add_videomode(&mode, &info->modelist);
i810fb_init_ringbuffer(info);
err = register_framebuffer(info);
if (err < 0) {
i810fb_release_resource(info, par);
printk("i810fb_init: cannot register framebuffer device\n");
return err;
}
pci_set_drvdata(dev, info);
pixclock = 1000000000/(info->var.pixclock);
pixclock *= 1000;
hfreq = pixclock/(info->var.xres + info->var.left_margin +
info->var.hsync_len + info->var.right_margin);
vfreq = hfreq/(info->var.yres + info->var.upper_margin +
info->var.vsync_len + info->var.lower_margin);
printk("I810FB: fb%d : %s v%d.%d.%d%s\n"
"I810FB: Video RAM : %dK\n"
"I810FB: Monitor : H: %d-%d KHz V: %d-%d Hz\n"
"I810FB: Mode : %dx%d-%dbpp@%dHz\n",
info->node,
i810_pci_list[entry->driver_data],
VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION,
(int) par->fb.size>>10, info->monspecs.hfmin/1000,
info->monspecs.hfmax/1000, info->monspecs.vfmin,
info->monspecs.vfmax, info->var.xres,
info->var.yres, info->var.bits_per_pixel, vfreq);
return 0;
}
/***************************************************************
* De-initialization *
***************************************************************/
static void i810fb_release_resource(struct fb_info *info,
struct i810fb_par *par)
{
struct gtt_data *gtt = &par->i810_gtt;
arch_phys_wc_del(par->wc_cookie);
i810_delete_i2c_busses(par);
if (par->i810_gtt.i810_cursor_memory)
agp_free_memory(gtt->i810_cursor_memory);
if (par->i810_gtt.i810_fb_memory)
agp_free_memory(gtt->i810_fb_memory);
if (par->mmio_start_virtual)
iounmap(par->mmio_start_virtual);
if (par->aperture.virtual)
iounmap(par->aperture.virtual);
kfree(par->edid);
if (par->res_flags & FRAMEBUFFER_REQ)
release_mem_region(par->aperture.physical,
par->aperture.size);
if (par->res_flags & MMIO_REQ)
release_mem_region(par->mmio_start_phys, MMIO_SIZE);
framebuffer_release(info);
}
static void i810fb_remove_pci(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
struct i810fb_par *par = info->par;
unregister_framebuffer(info);
i810fb_release_resource(info, par);
printk("cleanup_module: unloaded i810 framebuffer device\n");
}
#ifndef MODULE
static int i810fb_init(void)
{
char *option = NULL;
if (fb_modesetting_disabled("i810fb"))
return -ENODEV;
if (fb_get_options("i810fb", &option))
return -ENODEV;
i810fb_setup(option);
return pci_register_driver(&i810fb_driver);
}
#endif
/*********************************************************************
* Modularization *
*********************************************************************/
#ifdef MODULE
static int i810fb_init(void)
{
if (fb_modesetting_disabled("i810fb"))
return -ENODEV;
hsync1 *= 1000;
hsync2 *= 1000;
return pci_register_driver(&i810fb_driver);
}
module_param(vram, int, 0);
MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB"
" (default=4)");
module_param(voffset, int, 0);
MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer "
"memory (0 to maximum aperture size), in MiB (default = 48)");
module_param(bpp, int, 0);
MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel"
" (default = 8)");
module_param(xres, int, 0);
MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)");
module_param(yres, int, 0);
MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)");
module_param(vyres,int, 0);
MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines"
" (default = 480)");
module_param(hsync1, int, 0);
MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz"
" (default = 29)");
module_param(hsync2, int, 0);
MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz"
" (default = 30)");
module_param(vsync1, int, 0);
MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz"
" (default = 50)");
module_param(vsync2, int, 0);
MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz"
" (default = 60)");
module_param(accel, bool, 0);
MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)");
module_param(mtrr, bool, 0);
MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)");
module_param(extvga, bool, 0);
MODULE_PARM_DESC(extvga, "Enable external VGA connector (default = 0)");
module_param(sync, bool, 0);
MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing"
" (default = 0)");
module_param(dcolor, bool, 0);
MODULE_PARM_DESC(dcolor, "use DirectColor visuals"
" (default = 0 = TrueColor)");
module_param(ddc3, bool, 0);
MODULE_PARM_DESC(ddc3, "Probe DDC bus 3 (default = 0 = no)");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Specify initial video mode");
MODULE_AUTHOR("Tony A. Daplas");
MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and"
" compatible cards");
MODULE_LICENSE("GPL");
static void __exit i810fb_exit(void)
{
pci_unregister_driver(&i810fb_driver);
}
module_exit(i810fb_exit);
#endif /* MODULE */
module_init(i810fb_init);
| linux-master | drivers/video/fbdev/i810/i810_main.c |
/*-*- linux-c -*-
* linux/drivers/video/i810_accel.c -- Hardware Acceleration
*
* Copyright (C) 2001 Antonino Daplas<[email protected]>
* All Rights Reserved
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/fb.h>
#include "i810_regs.h"
#include "i810.h"
#include "i810_main.h"
static u32 i810fb_rop[] = {
COLOR_COPY_ROP, /* ROP_COPY */
XOR_ROP /* ROP_XOR */
};
/* Macros */
#define PUT_RING(n) { \
i810_writel(par->cur_tail, par->iring.virtual, n); \
par->cur_tail += 4; \
par->cur_tail &= RING_SIZE_MASK; \
}
extern void flush_cache(void);
/************************************************************/
/* BLT Engine Routines */
static inline void i810_report_error(u8 __iomem *mmio)
{
printk("IIR : 0x%04x\n"
"EIR : 0x%04x\n"
"PGTBL_ER: 0x%04x\n"
"IPEIR : 0x%04x\n"
"IPEHR : 0x%04x\n",
i810_readw(IIR, mmio),
i810_readb(EIR, mmio),
i810_readl(PGTBL_ER, mmio),
i810_readl(IPEIR, mmio),
i810_readl(IPEHR, mmio));
}
/**
* wait_for_space - check ring buffer free space
* @space: amount of ringbuffer space needed in bytes
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* The function waits until a free space from the ringbuffer
* is available
*/
static inline int wait_for_space(struct fb_info *info, u32 space)
{
struct i810fb_par *par = info->par;
u32 head, count = WAIT_COUNT, tail;
u8 __iomem *mmio = par->mmio_start_virtual;
tail = par->cur_tail;
while (count--) {
head = i810_readl(IRING + 4, mmio) & RBUFFER_HEAD_MASK;
if ((tail == head) ||
(tail > head &&
(par->iring.size - tail + head) >= space) ||
(tail < head && (head - tail) >= space)) {
return 0;
}
}
printk("ringbuffer lockup!!!\n");
i810_report_error(mmio);
par->dev_flags |= LOCKUP;
info->pixmap.scan_align = 1;
return 1;
}
/**
* wait_for_engine_idle - waits for all hardware engines to finish
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* This waits for lring(0), iring(1), and batch(3), etc to finish and
* waits until ringbuffer is empty.
*/
static inline int wait_for_engine_idle(struct fb_info *info)
{
struct i810fb_par *par = info->par;
u8 __iomem *mmio = par->mmio_start_virtual;
int count = WAIT_COUNT;
if (wait_for_space(info, par->iring.size)) /* flush */
return 1;
while((i810_readw(INSTDONE, mmio) & 0x7B) != 0x7B && --count);
if (count) return 0;
printk("accel engine lockup!!!\n");
printk("INSTDONE: 0x%04x\n", i810_readl(INSTDONE, mmio));
i810_report_error(mmio);
par->dev_flags |= LOCKUP;
info->pixmap.scan_align = 1;
return 1;
}
/* begin_iring - prepares the ringbuffer
* @space: length of sequence in dwords
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Checks/waits for sufficient space in ringbuffer of size
* space. Returns the tail of the buffer
*/
static inline u32 begin_iring(struct fb_info *info, u32 space)
{
struct i810fb_par *par = info->par;
if (par->dev_flags & ALWAYS_SYNC)
wait_for_engine_idle(info);
return wait_for_space(info, space);
}
/**
* end_iring - advances the buffer
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* This advances the tail of the ringbuffer, effectively
* beginning the execution of the graphics instruction sequence.
*/
static inline void end_iring(struct i810fb_par *par)
{
u8 __iomem *mmio = par->mmio_start_virtual;
i810_writel(IRING, mmio, par->cur_tail);
}
/**
* source_copy_blit - BLIT transfer operation
* @dwidth: width of rectangular graphics data
* @dheight: height of rectangular graphics data
* @dpitch: bytes per line of destination buffer
* @xdir: direction of copy (left to right or right to left)
* @src: address of first pixel to read from
* @dest: address of first pixel to write to
* @from: source address
* @where: destination address
* @rop: raster operation
* @blit_bpp: pixel format which can be different from the
* framebuffer's pixelformat
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* This is a BLIT operation typically used when doing
* a 'Copy and Paste'
*/
static inline void source_copy_blit(int dwidth, int dheight, int dpitch,
int xdir, int src, int dest, int rop,
int blit_bpp, struct fb_info *info)
{
struct i810fb_par *par = info->par;
if (begin_iring(info, 24 + IRING_PAD)) return;
PUT_RING(BLIT | SOURCE_COPY_BLIT | 4);
PUT_RING(xdir | rop << 16 | dpitch | DYN_COLOR_EN | blit_bpp);
PUT_RING(dheight << 16 | dwidth);
PUT_RING(dest);
PUT_RING(dpitch);
PUT_RING(src);
end_iring(par);
}
/**
* color_blit - solid color BLIT operation
* @width: width of destination
* @height: height of destination
* @pitch: pixels per line of the buffer
* @dest: address of first pixel to write to
* @where: destination
* @rop: raster operation
* @what: color to transfer
* @blit_bpp: pixel format which can be different from the
* framebuffer's pixelformat
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* A BLIT operation which can be used for color fill/rectangular fill
*/
static inline void color_blit(int width, int height, int pitch, int dest,
int rop, int what, int blit_bpp,
struct fb_info *info)
{
struct i810fb_par *par = info->par;
if (begin_iring(info, 24 + IRING_PAD)) return;
PUT_RING(BLIT | COLOR_BLT | 3);
PUT_RING(rop << 16 | pitch | SOLIDPATTERN | DYN_COLOR_EN | blit_bpp);
PUT_RING(height << 16 | width);
PUT_RING(dest);
PUT_RING(what);
PUT_RING(NOP);
end_iring(par);
}
/**
* mono_src_copy_imm_blit - color expand from system memory to framebuffer
* @dwidth: width of destination
* @dheight: height of destination
* @dpitch: pixels per line of the buffer
* @dsize: size of bitmap in double words
* @dest: address of first byte of pixel;
* @rop: raster operation
* @blit_bpp: pixelformat to use which can be different from the
* framebuffer's pixelformat
* @src: address of image data
* @bg: backgound color
* @fg: forground color
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* A color expand operation where the source data is placed in the
* ringbuffer itself. Useful for drawing text.
*
* REQUIREMENT:
* The end of a scanline must be padded to the next word.
*/
static inline void mono_src_copy_imm_blit(int dwidth, int dheight, int dpitch,
int dsize, int blit_bpp, int rop,
int dest, const u32 *src, int bg,
int fg, struct fb_info *info)
{
struct i810fb_par *par = info->par;
if (begin_iring(info, 24 + (dsize << 2) + IRING_PAD)) return;
PUT_RING(BLIT | MONO_SOURCE_COPY_IMMEDIATE | (4 + dsize));
PUT_RING(DYN_COLOR_EN | blit_bpp | rop << 16 | dpitch);
PUT_RING(dheight << 16 | dwidth);
PUT_RING(dest);
PUT_RING(bg);
PUT_RING(fg);
while (dsize--)
PUT_RING(*src++);
end_iring(par);
}
static inline void load_front(int offset, struct fb_info *info)
{
struct i810fb_par *par = info->par;
if (begin_iring(info, 8 + IRING_PAD)) return;
PUT_RING(PARSER | FLUSH);
PUT_RING(NOP);
end_iring(par);
if (begin_iring(info, 8 + IRING_PAD)) return;
PUT_RING(PARSER | FRONT_BUFFER | ((par->pitch >> 3) << 8));
PUT_RING((par->fb.offset << 12) + offset);
end_iring(par);
}
/**
* i810fb_iring_enable - enables/disables the ringbuffer
* @mode: enable or disable
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Enables or disables the ringbuffer, effectively enabling or
* disabling the instruction/acceleration engine.
*/
static inline void i810fb_iring_enable(struct i810fb_par *par, u32 mode)
{
u32 tmp;
u8 __iomem *mmio = par->mmio_start_virtual;
tmp = i810_readl(IRING + 12, mmio);
if (mode == OFF)
tmp &= ~1;
else
tmp |= 1;
flush_cache();
i810_writel(IRING + 12, mmio, tmp);
}
void i810fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct i810fb_par *par = info->par;
u32 dx, dy, width, height, dest, rop = 0, color = 0;
if (!info->var.accel_flags || par->dev_flags & LOCKUP ||
par->depth == 4) {
cfb_fillrect(info, rect);
return;
}
if (par->depth == 1)
color = rect->color;
else
color = ((u32 *) (info->pseudo_palette))[rect->color];
rop = i810fb_rop[rect->rop];
dx = rect->dx * par->depth;
width = rect->width * par->depth;
dy = rect->dy;
height = rect->height;
dest = info->fix.smem_start + (dy * info->fix.line_length) + dx;
color_blit(width, height, info->fix.line_length, dest, rop, color,
par->blit_bpp, info);
}
void i810fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct i810fb_par *par = info->par;
u32 sx, sy, dx, dy, pitch, width, height, src, dest, xdir;
if (!info->var.accel_flags || par->dev_flags & LOCKUP ||
par->depth == 4) {
cfb_copyarea(info, region);
return;
}
dx = region->dx * par->depth;
sx = region->sx * par->depth;
width = region->width * par->depth;
sy = region->sy;
dy = region->dy;
height = region->height;
if (dx <= sx) {
xdir = INCREMENT;
}
else {
xdir = DECREMENT;
sx += width - 1;
dx += width - 1;
}
if (dy <= sy) {
pitch = info->fix.line_length;
}
else {
pitch = (-(info->fix.line_length)) & 0xFFFF;
sy += height - 1;
dy += height - 1;
}
src = info->fix.smem_start + (sy * info->fix.line_length) + sx;
dest = info->fix.smem_start + (dy * info->fix.line_length) + dx;
source_copy_blit(width, height, pitch, xdir, src, dest,
PAT_COPY_ROP, par->blit_bpp, info);
}
void i810fb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct i810fb_par *par = info->par;
u32 fg = 0, bg = 0, size, dst;
if (!info->var.accel_flags || par->dev_flags & LOCKUP ||
par->depth == 4 || image->depth != 1) {
cfb_imageblit(info, image);
return;
}
switch (info->var.bits_per_pixel) {
case 8:
fg = image->fg_color;
bg = image->bg_color;
break;
case 16:
case 24:
fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
break;
}
dst = info->fix.smem_start + (image->dy * info->fix.line_length) +
(image->dx * par->depth);
size = (image->width+7)/8 + 1;
size &= ~1;
size *= image->height;
size += 7;
size &= ~7;
mono_src_copy_imm_blit(image->width * par->depth,
image->height, info->fix.line_length,
size/4, par->blit_bpp,
PAT_COPY_ROP, dst, (u32 *) image->data,
bg, fg, info);
}
int i810fb_sync(struct fb_info *info)
{
struct i810fb_par *par = info->par;
if (!info->var.accel_flags || par->dev_flags & LOCKUP)
return 0;
return wait_for_engine_idle(info);
}
void i810fb_load_front(u32 offset, struct fb_info *info)
{
struct i810fb_par *par = info->par;
u8 __iomem *mmio = par->mmio_start_virtual;
if (!info->var.accel_flags || par->dev_flags & LOCKUP)
i810_writel(DPLYBASE, mmio, par->fb.physical + offset);
else
load_front(offset, info);
}
/**
* i810fb_init_ringbuffer - initialize the ringbuffer
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Initializes the ringbuffer by telling the device the
* size and location of the ringbuffer. It also sets
* the head and tail pointers = 0
*/
void i810fb_init_ringbuffer(struct fb_info *info)
{
struct i810fb_par *par = info->par;
u32 tmp1, tmp2;
u8 __iomem *mmio = par->mmio_start_virtual;
wait_for_engine_idle(info);
i810fb_iring_enable(par, OFF);
i810_writel(IRING, mmio, 0);
i810_writel(IRING + 4, mmio, 0);
par->cur_tail = 0;
tmp2 = i810_readl(IRING + 8, mmio) & ~RBUFFER_START_MASK;
tmp1 = par->iring.physical;
i810_writel(IRING + 8, mmio, tmp2 | tmp1);
tmp1 = i810_readl(IRING + 12, mmio);
tmp1 &= ~RBUFFER_SIZE_MASK;
tmp2 = (par->iring.size - I810_PAGESIZE) & RBUFFER_SIZE_MASK;
i810_writel(IRING + 12, mmio, tmp1 | tmp2);
i810fb_iring_enable(par, ON);
}
| linux-master | drivers/video/fbdev/i810/i810_accel.c |
/*-*- linux-c -*-
* linux/drivers/video/i810_main.h -- Intel 810 Non-discrete Video Timings
* (VESA GTF)
*
* Copyright (C) 2001 Antonino Daplas<[email protected]>
* All Rights Reserved
*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/kernel.h>
#include "i810_regs.h"
#include "i810.h"
#include "i810_main.h"
/*
* FIFO and Watermark tables - based almost wholly on i810_wmark.c in
* XFree86 v4.03 by Precision Insight. Slightly modified for integer
* operation, instead of float
*/
struct wm_info {
u32 freq;
u32 wm;
};
static struct wm_info i810_wm_8_100[] = {
{ 15, 0x0070c000 }, { 19, 0x0070c000 }, { 25, 0x22003000 },
{ 28, 0x22003000 }, { 31, 0x22003000 }, { 36, 0x22007000 },
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
{ 50, 0x22008000 }, { 56, 0x22008000 }, { 65, 0x22008000 },
{ 75, 0x22008000 }, { 78, 0x22008000 }, { 80, 0x22008000 },
{ 94, 0x22008000 }, { 96, 0x22107000 }, { 99, 0x22107000 },
{ 108, 0x22107000 }, { 121, 0x22107000 }, { 128, 0x22107000 },
{ 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
{ 162, 0x2210b000 }, { 175, 0x2210b000 }, { 189, 0x2220e000 },
{ 195, 0x2220e000 }, { 202, 0x2220e000 }, { 204, 0x2220e000 },
{ 218, 0x2220f000 }, { 229, 0x22210000 }, { 234, 0x22210000 },
};
static struct wm_info i810_wm_16_100[] = {
{ 15, 0x0070c000 }, { 19, 0x0020c000 }, { 25, 0x22006000 },
{ 28, 0x22006000 }, { 31, 0x22007000 }, { 36, 0x22007000 },
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
{ 50, 0x22009000 }, { 56, 0x22108000 }, { 65, 0x2210e000 },
{ 75, 0x2210e000 }, { 78, 0x2210e000 }, { 80, 0x22210000 },
{ 94, 0x22210000 }, { 96, 0x22210000 }, { 99, 0x22210000 },
{ 108, 0x22210000 }, { 121, 0x22210000 }, { 128, 0x22210000 },
{ 132, 0x22314000 }, { 135, 0x22314000 }, { 157, 0x22415000 },
{ 162, 0x22416000 }, { 175, 0x22416000 }, { 189, 0x22416000 },
{ 195, 0x22416000 }, { 202, 0x22416000 }, { 204, 0x22416000 },
{ 218, 0x22416000 }, { 229, 0x22416000 },
};
static struct wm_info i810_wm_24_100[] = {
{ 15, 0x0020c000 }, { 19, 0x0040c000 }, { 25, 0x22009000 },
{ 28, 0x22009000 }, { 31, 0x2200a000 }, { 36, 0x2210c000 },
{ 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
{ 50, 0x22111000 }, { 56, 0x22111000 }, { 65, 0x22214000 },
{ 75, 0x22214000 }, { 78, 0x22215000 }, { 80, 0x22216000 },
{ 94, 0x22218000 }, { 96, 0x22418000 }, { 99, 0x22418000 },
{ 108, 0x22418000 }, { 121, 0x22418000 }, { 128, 0x22419000 },
{ 132, 0x22519000 }, { 135, 0x4441d000 }, { 157, 0x44419000 },
{ 162, 0x44419000 }, { 175, 0x44419000 }, { 189, 0x44419000 },
{ 195, 0x44419000 }, { 202, 0x44419000 }, { 204, 0x44419000 },
};
static struct wm_info i810_wm_8_133[] = {
{ 15, 0x0070c000 }, { 19, 0x0070c000 }, { 25, 0x22003000 },
{ 28, 0x22003000 }, { 31, 0x22003000 }, { 36, 0x22007000 },
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
{ 50, 0x22008000 }, { 56, 0x22008000 }, { 65, 0x22008000 },
{ 75, 0x22008000 }, { 78, 0x22008000 }, { 80, 0x22008000 },
{ 94, 0x22008000 }, { 96, 0x22107000 }, { 99, 0x22107000 },
{ 108, 0x22107000 }, { 121, 0x22107000 }, { 128, 0x22107000 },
{ 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
{ 162, 0x2210b000 }, { 175, 0x2210b000 }, { 189, 0x2220e000 },
{ 195, 0x2220e000 }, { 202, 0x2220e000 }, { 204, 0x2220e000 },
{ 218, 0x2220f000 }, { 229, 0x22210000 }, { 234, 0x22210000 },
};
static struct wm_info i810_wm_16_133[] = {
{ 15, 0x0020c000 }, { 19, 0x0020c000 }, { 25, 0x22006000 },
{ 28, 0x22006000 }, { 31, 0x22007000 }, { 36, 0x22007000 },
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
{ 50, 0x22009000 }, { 56, 0x22108000 }, { 65, 0x2210e000 },
{ 75, 0x2210e000 }, { 78, 0x2210e000 }, { 80, 0x22210000 },
{ 94, 0x22210000 }, { 96, 0x22210000 }, { 99, 0x22210000 },
{ 108, 0x22210000 }, { 121, 0x22210000 }, { 128, 0x22210000 },
{ 132, 0x22314000 }, { 135, 0x22314000 }, { 157, 0x22415000 },
{ 162, 0x22416000 }, { 175, 0x22416000 }, { 189, 0x22416000 },
{ 195, 0x22416000 }, { 202, 0x22416000 }, { 204, 0x22416000 },
{ 218, 0x22416000 }, { 229, 0x22416000 },
};
static struct wm_info i810_wm_24_133[] = {
{ 15, 0x0020c000 }, { 19, 0x00408000 }, { 25, 0x22009000 },
{ 28, 0x22009000 }, { 31, 0x2200a000 }, { 36, 0x2210c000 },
{ 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
{ 50, 0x22111000 }, { 56, 0x22111000 }, { 65, 0x22214000 },
{ 75, 0x22214000 }, { 78, 0x22215000 }, { 80, 0x22216000 },
{ 94, 0x22218000 }, { 96, 0x22418000 }, { 99, 0x22418000 },
{ 108, 0x22418000 }, { 121, 0x22418000 }, { 128, 0x22419000 },
{ 132, 0x22519000 }, { 135, 0x4441d000 }, { 157, 0x44419000 },
{ 162, 0x44419000 }, { 175, 0x44419000 }, { 189, 0x44419000 },
{ 195, 0x44419000 }, { 202, 0x44419000 }, { 204, 0x44419000 },
};
void round_off_xres(u32 *xres) { }
void round_off_yres(u32 *xres, u32 *yres) { }
/**
* i810fb_encode_registers - encode @var to hardware register values
* @var: pointer to var structure
* @par: pointer to hardware par structure
*
* DESCRIPTION:
* Timing values in @var will be converted to appropriate
* register values of @par.
*/
void i810fb_encode_registers(const struct fb_var_screeninfo *var,
struct i810fb_par *par, u32 xres, u32 yres)
{
int n, blank_s, blank_e;
u8 __iomem *mmio = par->mmio_start_virtual;
u8 msr = 0;
/* Horizontal */
/* htotal */
n = ((xres + var->right_margin + var->hsync_len +
var->left_margin) >> 3) - 5;
par->regs.cr00 = (u8) n;
par->regs.cr35 = (u8) ((n >> 8) & 1);
/* xres */
par->regs.cr01 = (u8) ((xres >> 3) - 1);
/* hblank */
blank_e = (xres + var->right_margin + var->hsync_len +
var->left_margin) >> 3;
blank_e--;
blank_s = blank_e - 127;
if (blank_s < (xres >> 3))
blank_s = xres >> 3;
par->regs.cr02 = (u8) blank_s;
par->regs.cr03 = (u8) (blank_e & 0x1F);
par->regs.cr05 = (u8) ((blank_e & (1 << 5)) << 2);
par->regs.cr39 = (u8) ((blank_e >> 6) & 1);
/* hsync */
par->regs.cr04 = (u8) ((xres + var->right_margin) >> 3);
par->regs.cr05 |= (u8) (((xres + var->right_margin +
var->hsync_len) >> 3) & 0x1F);
/* Vertical */
/* vtotal */
n = yres + var->lower_margin + var->vsync_len + var->upper_margin - 2;
par->regs.cr06 = (u8) (n & 0xFF);
par->regs.cr30 = (u8) ((n >> 8) & 0x0F);
/* vsync */
n = yres + var->lower_margin;
par->regs.cr10 = (u8) (n & 0xFF);
par->regs.cr32 = (u8) ((n >> 8) & 0x0F);
par->regs.cr11 = i810_readb(CR11, mmio) & ~0x0F;
par->regs.cr11 |= (u8) ((yres + var->lower_margin +
var->vsync_len) & 0x0F);
/* yres */
n = yres - 1;
par->regs.cr12 = (u8) (n & 0xFF);
par->regs.cr31 = (u8) ((n >> 8) & 0x0F);
/* vblank */
blank_e = yres + var->lower_margin + var->vsync_len +
var->upper_margin;
blank_e--;
blank_s = blank_e - 127;
if (blank_s < yres)
blank_s = yres;
par->regs.cr15 = (u8) (blank_s & 0xFF);
par->regs.cr33 = (u8) ((blank_s >> 8) & 0x0F);
par->regs.cr16 = (u8) (blank_e & 0xFF);
par->regs.cr09 = 0;
/* sync polarity */
if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
msr |= 1 << 6;
if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
msr |= 1 << 7;
par->regs.msr = msr;
/* interlace */
if (var->vmode & FB_VMODE_INTERLACED)
par->interlace = (1 << 7) | ((u8) (var->yres >> 4));
else
par->interlace = 0;
if (var->vmode & FB_VMODE_DOUBLE)
par->regs.cr09 |= 1 << 7;
/* overlay */
par->ovract = ((var->xres + var->right_margin + var->hsync_len +
var->left_margin - 32) | ((var->xres - 32) << 16));
}
void i810fb_fill_var_timings(struct fb_var_screeninfo *var) { }
/**
* i810_get_watermark - gets watermark
* @var: pointer to fb_var_screeninfo
* @par: pointer to i810fb_par structure
*
* DESCRIPTION:
* Gets the required watermark based on
* pixelclock and RAMBUS frequency.
*
* RETURNS:
* watermark
*/
u32 i810_get_watermark(const struct fb_var_screeninfo *var,
struct i810fb_par *par)
{
struct wm_info *wmark = NULL;
u32 i, size = 0, pixclock, wm_best = 0, min, diff;
if (par->mem_freq == 100) {
switch (var->bits_per_pixel) {
case 8:
wmark = i810_wm_8_100;
size = ARRAY_SIZE(i810_wm_8_100);
break;
case 16:
wmark = i810_wm_16_100;
size = ARRAY_SIZE(i810_wm_16_100);
break;
case 24:
case 32:
wmark = i810_wm_24_100;
size = ARRAY_SIZE(i810_wm_24_100);
}
} else {
switch(var->bits_per_pixel) {
case 8:
wmark = i810_wm_8_133;
size = ARRAY_SIZE(i810_wm_8_133);
break;
case 16:
wmark = i810_wm_16_133;
size = ARRAY_SIZE(i810_wm_16_133);
break;
case 24:
case 32:
wmark = i810_wm_24_133;
size = ARRAY_SIZE(i810_wm_24_133);
}
}
pixclock = 1000000/var->pixclock;
min = ~0;
for (i = 0; i < size; i++) {
if (pixclock <= wmark[i].freq)
diff = wmark[i].freq - pixclock;
else
diff = pixclock - wmark[i].freq;
if (diff < min) {
wm_best = wmark[i].wm;
min = diff;
}
}
return wm_best;
}
| linux-master | drivers/video/fbdev/i810/i810_gtf.c |
/***************************************************************************\
|* *|
|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
* XFree86 'nv' driver, this source code is provided under MIT-style licensing
* where the source code is provided "as is" without warranty of any kind.
* The only usage restriction is for the copyright notices to be retained
* whenever code is used.
*
* Antonino Daplas <[email protected]> 2005-03-11
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c,v 1.4 2003/11/03 05:11:25 tsi Exp $ */
#include <linux/pci.h>
#include "nv_type.h"
#include "nv_local.h"
#include "nv_proto.h"
void NVLockUnlock(struct nvidia_par *par, int Lock)
{
u8 cr11;
VGA_WR08(par->PCIO, 0x3D4, 0x1F);
VGA_WR08(par->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
VGA_WR08(par->PCIO, 0x3D4, 0x11);
cr11 = VGA_RD08(par->PCIO, 0x3D5);
if (Lock)
cr11 |= 0x80;
else
cr11 &= ~0x80;
VGA_WR08(par->PCIO, 0x3D5, cr11);
}
int NVShowHideCursor(struct nvidia_par *par, int ShowHide)
{
int cur = par->CurrentState->cursor1;
par->CurrentState->cursor1 = (par->CurrentState->cursor1 & 0xFE) |
(ShowHide & 0x01);
VGA_WR08(par->PCIO, 0x3D4, 0x31);
VGA_WR08(par->PCIO, 0x3D5, par->CurrentState->cursor1);
if (par->Architecture == NV_ARCH_40)
NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
return (cur & 0x01);
}
/****************************************************************************\
* *
* The video arbitration routines calculate some "magic" numbers. Fixes *
* the snow seen when accessing the framebuffer without it. *
* It just works (I hope). *
* *
\****************************************************************************/
typedef struct {
int graphics_lwm;
int video_lwm;
int graphics_burst_size;
int video_burst_size;
int valid;
} nv4_fifo_info;
typedef struct {
int pclk_khz;
int mclk_khz;
int nvclk_khz;
char mem_page_miss;
char mem_latency;
int memory_width;
char enable_video;
char gr_during_vid;
char pix_bpp;
char mem_aligned;
char enable_mp;
} nv4_sim_state;
typedef struct {
int graphics_lwm;
int video_lwm;
int graphics_burst_size;
int video_burst_size;
int valid;
} nv10_fifo_info;
typedef struct {
int pclk_khz;
int mclk_khz;
int nvclk_khz;
char mem_page_miss;
char mem_latency;
u32 memory_type;
int memory_width;
char enable_video;
char gr_during_vid;
char pix_bpp;
char mem_aligned;
char enable_mp;
} nv10_sim_state;
static void nvGetClocks(struct nvidia_par *par, unsigned int *MClk,
unsigned int *NVClk)
{
unsigned int pll, N, M, MB, NB, P;
if (par->Architecture >= NV_ARCH_40) {
pll = NV_RD32(par->PMC, 0x4020);
P = (pll >> 16) & 0x07;
pll = NV_RD32(par->PMC, 0x4024);
M = pll & 0xFF;
N = (pll >> 8) & 0xFF;
if (((par->Chipset & 0xfff0) == 0x0290) ||
((par->Chipset & 0xfff0) == 0x0390)) {
MB = 1;
NB = 1;
} else {
MB = (pll >> 16) & 0xFF;
NB = (pll >> 24) & 0xFF;
}
*MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
pll = NV_RD32(par->PMC, 0x4000);
P = (pll >> 16) & 0x07;
pll = NV_RD32(par->PMC, 0x4004);
M = pll & 0xFF;
N = (pll >> 8) & 0xFF;
MB = (pll >> 16) & 0xFF;
NB = (pll >> 24) & 0xFF;
*NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
} else if (par->twoStagePLL) {
pll = NV_RD32(par->PRAMDAC0, 0x0504);
M = pll & 0xFF;
N = (pll >> 8) & 0xFF;
P = (pll >> 16) & 0x0F;
pll = NV_RD32(par->PRAMDAC0, 0x0574);
if (pll & 0x80000000) {
MB = pll & 0xFF;
NB = (pll >> 8) & 0xFF;
} else {
MB = 1;
NB = 1;
}
*MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
pll = NV_RD32(par->PRAMDAC0, 0x0500);
M = pll & 0xFF;
N = (pll >> 8) & 0xFF;
P = (pll >> 16) & 0x0F;
pll = NV_RD32(par->PRAMDAC0, 0x0570);
if (pll & 0x80000000) {
MB = pll & 0xFF;
NB = (pll >> 8) & 0xFF;
} else {
MB = 1;
NB = 1;
}
*NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
} else
if (((par->Chipset & 0x0ff0) == 0x0300) ||
((par->Chipset & 0x0ff0) == 0x0330)) {
pll = NV_RD32(par->PRAMDAC0, 0x0504);
M = pll & 0x0F;
N = (pll >> 8) & 0xFF;
P = (pll >> 16) & 0x07;
if (pll & 0x00000080) {
MB = (pll >> 4) & 0x07;
NB = (pll >> 19) & 0x1f;
} else {
MB = 1;
NB = 1;
}
*MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
pll = NV_RD32(par->PRAMDAC0, 0x0500);
M = pll & 0x0F;
N = (pll >> 8) & 0xFF;
P = (pll >> 16) & 0x07;
if (pll & 0x00000080) {
MB = (pll >> 4) & 0x07;
NB = (pll >> 19) & 0x1f;
} else {
MB = 1;
NB = 1;
}
*NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
} else {
pll = NV_RD32(par->PRAMDAC0, 0x0504);
M = pll & 0xFF;
N = (pll >> 8) & 0xFF;
P = (pll >> 16) & 0x0F;
*MClk = (N * par->CrystalFreqKHz / M) >> P;
pll = NV_RD32(par->PRAMDAC0, 0x0500);
M = pll & 0xFF;
N = (pll >> 8) & 0xFF;
P = (pll >> 16) & 0x0F;
*NVClk = (N * par->CrystalFreqKHz / M) >> P;
}
}
static void nv4CalcArbitration(nv4_fifo_info * fifo, nv4_sim_state * arb)
{
int data, pagemiss, cas, width, video_enable, bpp;
int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
int found, mclk_extra, mclk_loop, cbs, m1, p1;
int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
fifo->valid = 1;
pclk_freq = arb->pclk_khz;
mclk_freq = arb->mclk_khz;
nvclk_freq = arb->nvclk_khz;
pagemiss = arb->mem_page_miss;
cas = arb->mem_latency;
width = arb->memory_width >> 6;
video_enable = arb->enable_video;
bpp = arb->pix_bpp;
mp_enable = arb->enable_mp;
clwm = 0;
vlwm = 0;
cbs = 128;
pclks = 2;
nvclks = 2;
nvclks += 2;
nvclks += 1;
mclks = 5;
mclks += 3;
mclks += 1;
mclks += cas;
mclks += 1;
mclks += 1;
mclks += 1;
mclks += 1;
mclk_extra = 3;
nvclks += 2;
nvclks += 1;
nvclks += 1;
nvclks += 1;
if (mp_enable)
mclks += 4;
nvclks += 0;
pclks += 0;
found = 0;
vbs = 0;
while (found != 1) {
fifo->valid = 1;
found = 1;
mclk_loop = mclks + mclk_extra;
us_m = mclk_loop * 1000 * 1000 / mclk_freq;
us_n = nvclks * 1000 * 1000 / nvclk_freq;
us_p = nvclks * 1000 * 1000 / pclk_freq;
if (video_enable) {
video_drain_rate = pclk_freq * 2;
crtc_drain_rate = pclk_freq * bpp / 8;
vpagemiss = 2;
vpagemiss += 1;
crtpagemiss = 2;
vpm_us =
(vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
if (nvclk_freq * 2 > mclk_freq * width)
video_fill_us =
cbs * 1000 * 1000 / 16 / nvclk_freq;
else
video_fill_us =
cbs * 1000 * 1000 / (8 * width) /
mclk_freq;
us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
vlwm = us_video * video_drain_rate / (1000 * 1000);
vlwm++;
vbs = 128;
if (vlwm > 128)
vbs = 64;
if (vlwm > (256 - 64))
vbs = 32;
if (nvclk_freq * 2 > mclk_freq * width)
video_fill_us =
vbs * 1000 * 1000 / 16 / nvclk_freq;
else
video_fill_us =
vbs * 1000 * 1000 / (8 * width) /
mclk_freq;
cpm_us =
crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
us_crt =
us_video + video_fill_us + cpm_us + us_m + us_n +
us_p;
clwm = us_crt * crtc_drain_rate / (1000 * 1000);
clwm++;
} else {
crtc_drain_rate = pclk_freq * bpp / 8;
crtpagemiss = 2;
crtpagemiss += 1;
cpm_us =
crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
us_crt = cpm_us + us_m + us_n + us_p;
clwm = us_crt * crtc_drain_rate / (1000 * 1000);
clwm++;
}
m1 = clwm + cbs - 512;
p1 = m1 * pclk_freq / mclk_freq;
p1 = p1 * bpp / 8;
if ((p1 < m1) && (m1 > 0)) {
fifo->valid = 0;
found = 0;
if (mclk_extra == 0)
found = 1;
mclk_extra--;
} else if (video_enable) {
if ((clwm > 511) || (vlwm > 255)) {
fifo->valid = 0;
found = 0;
if (mclk_extra == 0)
found = 1;
mclk_extra--;
}
} else {
if (clwm > 519) {
fifo->valid = 0;
found = 0;
if (mclk_extra == 0)
found = 1;
mclk_extra--;
}
}
if (clwm < 384)
clwm = 384;
if (vlwm < 128)
vlwm = 128;
data = (int)(clwm);
fifo->graphics_lwm = data;
fifo->graphics_burst_size = 128;
data = (int)((vlwm + 15));
fifo->video_lwm = data;
fifo->video_burst_size = vbs;
}
}
static void nv4UpdateArbitrationSettings(unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm, struct nvidia_par *par)
{
nv4_fifo_info fifo_data;
nv4_sim_state sim_data;
unsigned int MClk, NVClk, cfg1;
nvGetClocks(par, &MClk, &NVClk);
cfg1 = NV_RD32(par->PFB, 0x00000204);
sim_data.pix_bpp = (char)pixelDepth;
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
128 : 64;
sim_data.mem_latency = (char)cfg1 & 0x0F;
sim_data.mem_aligned = 1;
sim_data.mem_page_miss =
(char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
sim_data.gr_during_vid = 0;
sim_data.pclk_khz = VClk;
sim_data.mclk_khz = MClk;
sim_data.nvclk_khz = NVClk;
nv4CalcArbitration(&fifo_data, &sim_data);
if (fifo_data.valid) {
int b = fifo_data.graphics_burst_size >> 4;
*burst = 0;
while (b >>= 1)
(*burst)++;
*lwm = fifo_data.graphics_lwm >> 3;
}
}
static void nv10CalcArbitration(nv10_fifo_info * fifo, nv10_sim_state * arb)
{
int data, pagemiss, width, video_enable, bpp;
int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
int nvclk_fill;
int found, mclk_extra, mclk_loop, cbs, m1;
int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
int vus_m;
int vpm_us, us_video, cpm_us, us_crt, clwm;
int clwm_rnd_down;
int m2us, us_pipe_min, p1clk, p2;
int min_mclk_extra;
int us_min_mclk_extra;
fifo->valid = 1;
pclk_freq = arb->pclk_khz; /* freq in KHz */
mclk_freq = arb->mclk_khz;
nvclk_freq = arb->nvclk_khz;
pagemiss = arb->mem_page_miss;
width = arb->memory_width / 64;
video_enable = arb->enable_video;
bpp = arb->pix_bpp;
mp_enable = arb->enable_mp;
clwm = 0;
cbs = 512;
pclks = 4; /* lwm detect. */
nvclks = 3; /* lwm -> sync. */
nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
/* 2 edge sync. may be very close to edge so just put one. */
mclks = 1;
mclks += 1; /* arb_hp_req */
mclks += 5; /* ap_hp_req tiling pipeline */
mclks += 2; /* tc_req latency fifo */
mclks += 2; /* fb_cas_n_ memory request to fbio block */
mclks += 7; /* sm_d_rdv data returned from fbio block */
/* fb.rd.d.Put_gc need to accumulate 256 bits for read */
if (arb->memory_type == 0)
if (arb->memory_width == 64) /* 64 bit bus */
mclks += 4;
else
mclks += 2;
else if (arb->memory_width == 64) /* 64 bit bus */
mclks += 2;
else
mclks += 1;
if ((!video_enable) && (arb->memory_width == 128)) {
mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
min_mclk_extra = 17;
} else {
mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
/* mclk_extra = 4; *//* Margin of error */
min_mclk_extra = 18;
}
/* 2 edge sync. may be very close to edge so just put one. */
nvclks += 1;
nvclks += 1; /* fbi_d_rdv_n */
nvclks += 1; /* Fbi_d_rdata */
nvclks += 1; /* crtfifo load */
if (mp_enable)
mclks += 4; /* Mp can get in with a burst of 8. */
/* Extra clocks determined by heuristics */
nvclks += 0;
pclks += 0;
found = 0;
while (found != 1) {
fifo->valid = 1;
found = 1;
mclk_loop = mclks + mclk_extra;
/* Mclk latency in us */
us_m = mclk_loop * 1000 * 1000 / mclk_freq;
/* Minimum Mclk latency in us */
us_m_min = mclks * 1000 * 1000 / mclk_freq;
us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
/* nvclk latency in us */
us_n = nvclks * 1000 * 1000 / nvclk_freq;
/* nvclk latency in us */
us_p = pclks * 1000 * 1000 / pclk_freq;
us_pipe_min = us_m_min + us_n + us_p;
/* Mclk latency in us */
vus_m = mclk_loop * 1000 * 1000 / mclk_freq;
if (video_enable) {
crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */
vpagemiss = 1; /* self generating page miss */
vpagemiss += 1; /* One higher priority before */
crtpagemiss = 2; /* self generating page miss */
if (mp_enable)
crtpagemiss += 1; /* if MA0 conflict */
vpm_us =
(vpagemiss * pagemiss) * 1000 * 1000 / mclk_freq;
/* Video has separate read return path */
us_video = vpm_us + vus_m;
cpm_us =
crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
/* Wait for video */
us_crt = us_video
+ cpm_us /* CRT Page miss */
+ us_m + us_n + us_p /* other latency */
;
clwm = us_crt * crtc_drain_rate / (1000 * 1000);
/* fixed point <= float_point - 1. Fixes that */
clwm++;
} else {
/* bpp * pclk/8 */
crtc_drain_rate = pclk_freq * bpp / 8;
crtpagemiss = 1; /* self generating page miss */
crtpagemiss += 1; /* MA0 page miss */
if (mp_enable)
crtpagemiss += 1; /* if MA0 conflict */
cpm_us =
crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
us_crt = cpm_us + us_m + us_n + us_p;
clwm = us_crt * crtc_drain_rate / (1000 * 1000);
/* fixed point <= float_point - 1. Fixes that */
clwm++;
/* Finally, a heuristic check when width == 64 bits */
if (width == 1) {
nvclk_fill = nvclk_freq * 8;
if (crtc_drain_rate * 100 >= nvclk_fill * 102)
/*Large number to fail */
clwm = 0xfff;
else if (crtc_drain_rate * 100 >=
nvclk_fill * 98) {
clwm = 1024;
cbs = 512;
}
}
}
/*
Overfill check:
*/
clwm_rnd_down = ((int)clwm / 8) * 8;
if (clwm_rnd_down < clwm)
clwm += 8;
m1 = clwm + cbs - 1024; /* Amount of overfill */
m2us = us_pipe_min + us_min_mclk_extra;
/* pclk cycles to drain */
p1clk = m2us * pclk_freq / (1000 * 1000);
p2 = p1clk * bpp / 8; /* bytes drained. */
if ((p2 < m1) && (m1 > 0)) {
fifo->valid = 0;
found = 0;
if (min_mclk_extra == 0) {
if (cbs <= 32) {
/* Can't adjust anymore! */
found = 1;
} else {
/* reduce the burst size */
cbs = cbs / 2;
}
} else {
min_mclk_extra--;
}
} else {
if (clwm > 1023) { /* Have some margin */
fifo->valid = 0;
found = 0;
if (min_mclk_extra == 0)
/* Can't adjust anymore! */
found = 1;
else
min_mclk_extra--;
}
}
if (clwm < (1024 - cbs + 8))
clwm = 1024 - cbs + 8;
data = (int)(clwm);
/* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n",
clwm, data ); */
fifo->graphics_lwm = data;
fifo->graphics_burst_size = cbs;
fifo->video_lwm = 1024;
fifo->video_burst_size = 512;
}
}
static void nv10UpdateArbitrationSettings(unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm,
struct nvidia_par *par)
{
nv10_fifo_info fifo_data;
nv10_sim_state sim_data;
unsigned int MClk, NVClk, cfg1;
nvGetClocks(par, &MClk, &NVClk);
cfg1 = NV_RD32(par->PFB, 0x0204);
sim_data.pix_bpp = (char)pixelDepth;
sim_data.enable_video = 1;
sim_data.enable_mp = 0;
sim_data.memory_type = (NV_RD32(par->PFB, 0x0200) & 0x01) ? 1 : 0;
sim_data.memory_width = (NV_RD32(par->PEXTDEV, 0x0000) & 0x10) ?
128 : 64;
sim_data.mem_latency = (char)cfg1 & 0x0F;
sim_data.mem_aligned = 1;
sim_data.mem_page_miss =
(char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
sim_data.gr_during_vid = 0;
sim_data.pclk_khz = VClk;
sim_data.mclk_khz = MClk;
sim_data.nvclk_khz = NVClk;
nv10CalcArbitration(&fifo_data, &sim_data);
if (fifo_data.valid) {
int b = fifo_data.graphics_burst_size >> 4;
*burst = 0;
while (b >>= 1)
(*burst)++;
*lwm = fifo_data.graphics_lwm >> 3;
}
}
static void nv30UpdateArbitrationSettings (
struct nvidia_par *par,
unsigned int *burst,
unsigned int *lwm
)
{
unsigned int MClk, NVClk;
unsigned int fifo_size, burst_size, graphics_lwm;
fifo_size = 2048;
burst_size = 512;
graphics_lwm = fifo_size - burst_size;
nvGetClocks(par, &MClk, &NVClk);
*burst = 0;
burst_size >>= 5;
while(burst_size >>= 1) (*burst)++;
*lwm = graphics_lwm >> 3;
}
static void nForceUpdateArbitrationSettings(unsigned VClk,
unsigned pixelDepth,
unsigned *burst,
unsigned *lwm,
struct nvidia_par *par)
{
nv10_fifo_info fifo_data;
nv10_sim_state sim_data;
unsigned int M, N, P, pll, MClk, NVClk, memctrl;
struct pci_dev *dev;
int domain = pci_domain_nr(par->pci_dev->bus);
if ((par->Chipset & 0x0FF0) == 0x01A0) {
unsigned int uMClkPostDiv;
dev = pci_get_domain_bus_and_slot(domain, 0, 3);
pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
if (!uMClkPostDiv)
uMClkPostDiv = 4;
MClk = 400000 / uMClkPostDiv;
} else {
dev = pci_get_domain_bus_and_slot(domain, 0, 5);
pci_read_config_dword(dev, 0x4c, &MClk);
MClk /= 1000;
}
pci_dev_put(dev);
pll = NV_RD32(par->PRAMDAC0, 0x0500);
M = (pll >> 0) & 0xFF;
N = (pll >> 8) & 0xFF;
P = (pll >> 16) & 0x0F;
NVClk = (N * par->CrystalFreqKHz / M) >> P;
sim_data.pix_bpp = (char)pixelDepth;
sim_data.enable_video = 0;
sim_data.enable_mp = 0;
dev = pci_get_domain_bus_and_slot(domain, 0, 1);
pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
pci_dev_put(dev);
sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
sim_data.memory_width = 64;
dev = pci_get_domain_bus_and_slot(domain, 0, 3);
pci_read_config_dword(dev, 0, &memctrl);
pci_dev_put(dev);
memctrl >>= 16;
if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
u32 dimm[3];
dev = pci_get_domain_bus_and_slot(domain, 0, 2);
pci_read_config_dword(dev, 0x40, &dimm[0]);
dimm[0] = (dimm[0] >> 8) & 0x4f;
pci_read_config_dword(dev, 0x44, &dimm[1]);
dimm[1] = (dimm[1] >> 8) & 0x4f;
pci_read_config_dword(dev, 0x48, &dimm[2]);
dimm[2] = (dimm[2] >> 8) & 0x4f;
if ((dimm[0] + dimm[1]) != dimm[2]) {
printk("nvidiafb: your nForce DIMMs are not arranged "
"in optimal banks!\n");
}
pci_dev_put(dev);
}
sim_data.mem_latency = 3;
sim_data.mem_aligned = 1;
sim_data.mem_page_miss = 10;
sim_data.gr_during_vid = 0;
sim_data.pclk_khz = VClk;
sim_data.mclk_khz = MClk;
sim_data.nvclk_khz = NVClk;
nv10CalcArbitration(&fifo_data, &sim_data);
if (fifo_data.valid) {
int b = fifo_data.graphics_burst_size >> 4;
*burst = 0;
while (b >>= 1)
(*burst)++;
*lwm = fifo_data.graphics_lwm >> 3;
}
}
/****************************************************************************\
* *
* RIVA Mode State Routines *
* *
\****************************************************************************/
/*
* Calculate the Video Clock parameters for the PLL.
*/
static void CalcVClock(int clockIn,
int *clockOut, u32 * pllOut, struct nvidia_par *par)
{
unsigned lowM, highM;
unsigned DeltaNew, DeltaOld;
unsigned VClk, Freq;
unsigned M, N, P;
DeltaOld = 0xFFFFFFFF;
VClk = (unsigned)clockIn;
if (par->CrystalFreqKHz == 13500) {
lowM = 7;
highM = 13;
} else {
lowM = 8;
highM = 14;
}
for (P = 0; P <= 4; P++) {
Freq = VClk << P;
if ((Freq >= 128000) && (Freq <= 350000)) {
for (M = lowM; M <= highM; M++) {
N = ((VClk << P) * M) / par->CrystalFreqKHz;
if (N <= 255) {
Freq =
((par->CrystalFreqKHz * N) /
M) >> P;
if (Freq > VClk)
DeltaNew = Freq - VClk;
else
DeltaNew = VClk - Freq;
if (DeltaNew < DeltaOld) {
*pllOut =
(P << 16) | (N << 8) | M;
*clockOut = Freq;
DeltaOld = DeltaNew;
}
}
}
}
}
}
static void CalcVClock2Stage(int clockIn,
int *clockOut,
u32 * pllOut,
u32 * pllBOut, struct nvidia_par *par)
{
unsigned DeltaNew, DeltaOld;
unsigned VClk, Freq;
unsigned M, N, P;
DeltaOld = 0xFFFFFFFF;
*pllBOut = 0x80000401; /* fixed at x4 for now */
VClk = (unsigned)clockIn;
for (P = 0; P <= 6; P++) {
Freq = VClk << P;
if ((Freq >= 400000) && (Freq <= 1000000)) {
for (M = 1; M <= 13; M++) {
N = ((VClk << P) * M) /
(par->CrystalFreqKHz << 2);
if ((N >= 5) && (N <= 255)) {
Freq =
(((par->CrystalFreqKHz << 2) * N) /
M) >> P;
if (Freq > VClk)
DeltaNew = Freq - VClk;
else
DeltaNew = VClk - Freq;
if (DeltaNew < DeltaOld) {
*pllOut =
(P << 16) | (N << 8) | M;
*clockOut = Freq;
DeltaOld = DeltaNew;
}
}
}
}
}
}
/*
* Calculate extended mode parameters (SVGA) and save in a
* mode state structure.
*/
void NVCalcStateExt(struct nvidia_par *par,
RIVA_HW_STATE * state,
int bpp,
int width,
int hDisplaySize, int height, int dotClock, int flags)
{
int pixelDepth, VClk = 0;
/*
* Save mode parameters.
*/
state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
state->width = width;
state->height = height;
/*
* Extended RIVA registers.
*/
pixelDepth = (bpp + 1) / 8;
if (par->twoStagePLL)
CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB,
par);
else
CalcVClock(dotClock, &VClk, &state->pll, par);
switch (par->Architecture) {
case NV_ARCH_04:
nv4UpdateArbitrationSettings(VClk,
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1), par);
state->cursor0 = 0x00;
state->cursor1 = 0xbC;
if (flags & FB_VMODE_DOUBLE)
state->cursor1 |= 2;
state->cursor2 = 0x00000000;
state->pllsel = 0x10000700;
state->config = 0x00001114;
state->general = bpp == 16 ? 0x00101100 : 0x00100100;
state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
break;
case NV_ARCH_40:
if (!par->FlatPanel)
state->control = NV_RD32(par->PRAMDAC0, 0x0580) &
0xeffffeff;
fallthrough;
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_30:
default:
if ((par->Chipset & 0xfff0) == 0x0240 ||
(par->Chipset & 0xfff0) == 0x03d0) {
state->arbitration0 = 256;
state->arbitration1 = 0x0480;
} else if (((par->Chipset & 0xffff) == 0x01A0) ||
((par->Chipset & 0xffff) == 0x01f0)) {
nForceUpdateArbitrationSettings(VClk,
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1),
par);
} else if (par->Architecture < NV_ARCH_30) {
nv10UpdateArbitrationSettings(VClk,
pixelDepth * 8,
&(state->arbitration0),
&(state->arbitration1),
par);
} else {
nv30UpdateArbitrationSettings(par,
&(state->arbitration0),
&(state->arbitration1));
}
state->cursor0 = 0x80 | (par->CursorStart >> 17);
state->cursor1 = (par->CursorStart >> 11) << 2;
state->cursor2 = par->CursorStart >> 24;
if (flags & FB_VMODE_DOUBLE)
state->cursor1 |= 2;
state->pllsel = 0x10000700;
state->config = NV_RD32(par->PFB, 0x00000200);
state->general = bpp == 16 ? 0x00101100 : 0x00100100;
state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
break;
}
if (bpp != 8) /* DirectColor */
state->general |= 0x00000030;
state->repaint0 = (((width / 8) * pixelDepth) & 0x700) >> 3;
state->pixel = (pixelDepth > 2) ? 3 : pixelDepth;
}
void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
{
int i, j;
NV_WR32(par->PMC, 0x0140, 0x00000000);
NV_WR32(par->PMC, 0x0200, 0xFFFF00FF);
NV_WR32(par->PMC, 0x0200, 0xFFFFFFFF);
NV_WR32(par->PTIMER, 0x0200 * 4, 0x00000008);
NV_WR32(par->PTIMER, 0x0210 * 4, 0x00000003);
NV_WR32(par->PTIMER, 0x0140 * 4, 0x00000000);
NV_WR32(par->PTIMER, 0x0100 * 4, 0xFFFFFFFF);
if (par->Architecture == NV_ARCH_04) {
if (state)
NV_WR32(par->PFB, 0x0200, state->config);
} else if ((par->Architecture < NV_ARCH_40) ||
(par->Chipset & 0xfff0) == 0x0040) {
for (i = 0; i < 8; i++) {
NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
NV_WR32(par->PFB, 0x0244 + (i * 0x10),
par->FbMapSize - 1);
}
} else {
int regions = 12;
if (((par->Chipset & 0xfff0) == 0x0090) ||
((par->Chipset & 0xfff0) == 0x01D0) ||
((par->Chipset & 0xfff0) == 0x0290) ||
((par->Chipset & 0xfff0) == 0x0390) ||
((par->Chipset & 0xfff0) == 0x03D0))
regions = 15;
for(i = 0; i < regions; i++) {
NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
NV_WR32(par->PFB, 0x0604 + (i * 0x10),
par->FbMapSize - 1);
}
}
if (par->Architecture >= NV_ARCH_40) {
NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
NV_WR32(par->PRAMIN, 0x0001 * 4, 0x00101202);
NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
NV_WR32(par->PRAMIN, 0x0003 * 4, 0x00101204);
NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
NV_WR32(par->PRAMIN, 0x0005 * 4, 0x00101206);
NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
NV_WR32(par->PRAMIN, 0x0007 * 4, 0x00101208);
NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
NV_WR32(par->PRAMIN, 0x0009 * 4, 0x0010120A);
NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
NV_WR32(par->PRAMIN, 0x000B * 4, 0x0010120C);
NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
NV_WR32(par->PRAMIN, 0x000D * 4, 0x0010120E);
NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
NV_WR32(par->PRAMIN, 0x000F * 4, 0x00101210);
NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
NV_WR32(par->PRAMIN, 0x0808 * 4, 0x02080062);
NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x080A * 4, 0x00001200);
NV_WR32(par->PRAMIN, 0x080B * 4, 0x00001200);
NV_WR32(par->PRAMIN, 0x080C * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0810 * 4, 0x02080043);
NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0814 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0818 * 4, 0x02080044);
NV_WR32(par->PRAMIN, 0x0819 * 4, 0x02000000);
NV_WR32(par->PRAMIN, 0x081A * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x081C * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0820 * 4, 0x02080019);
NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0822 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0828 * 4, 0x020A005C);
NV_WR32(par->PRAMIN, 0x0829 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x082A * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x082B * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x082C * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x082D * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0830 * 4, 0x0208009F);
NV_WR32(par->PRAMIN, 0x0831 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0832 * 4, 0x00001200);
NV_WR32(par->PRAMIN, 0x0833 * 4, 0x00001200);
NV_WR32(par->PRAMIN, 0x0834 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0835 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0838 * 4, 0x0208004A);
NV_WR32(par->PRAMIN, 0x0839 * 4, 0x02000000);
NV_WR32(par->PRAMIN, 0x083A * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x083B * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x083C * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x083D * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0840 * 4, 0x02080077);
NV_WR32(par->PRAMIN, 0x0841 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0842 * 4, 0x00001200);
NV_WR32(par->PRAMIN, 0x0843 * 4, 0x00001200);
NV_WR32(par->PRAMIN, 0x0844 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0845 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x084C * 4, 0x00003002);
NV_WR32(par->PRAMIN, 0x084D * 4, 0x00007FFF);
NV_WR32(par->PRAMIN, 0x084E * 4,
par->FbUsableSize | 0x00000002);
#ifdef __BIG_ENDIAN
NV_WR32(par->PRAMIN, 0x080A * 4,
NV_RD32(par->PRAMIN, 0x080A * 4) | 0x01000000);
NV_WR32(par->PRAMIN, 0x0812 * 4,
NV_RD32(par->PRAMIN, 0x0812 * 4) | 0x01000000);
NV_WR32(par->PRAMIN, 0x081A * 4,
NV_RD32(par->PRAMIN, 0x081A * 4) | 0x01000000);
NV_WR32(par->PRAMIN, 0x0822 * 4,
NV_RD32(par->PRAMIN, 0x0822 * 4) | 0x01000000);
NV_WR32(par->PRAMIN, 0x082A * 4,
NV_RD32(par->PRAMIN, 0x082A * 4) | 0x01000000);
NV_WR32(par->PRAMIN, 0x0832 * 4,
NV_RD32(par->PRAMIN, 0x0832 * 4) | 0x01000000);
NV_WR32(par->PRAMIN, 0x083A * 4,
NV_RD32(par->PRAMIN, 0x083A * 4) | 0x01000000);
NV_WR32(par->PRAMIN, 0x0842 * 4,
NV_RD32(par->PRAMIN, 0x0842 * 4) | 0x01000000);
NV_WR32(par->PRAMIN, 0x0819 * 4, 0x01000000);
NV_WR32(par->PRAMIN, 0x0839 * 4, 0x01000000);
#endif
} else {
NV_WR32(par->PRAMIN, 0x0000 * 4, 0x80000010);
NV_WR32(par->PRAMIN, 0x0001 * 4, 0x80011201);
NV_WR32(par->PRAMIN, 0x0002 * 4, 0x80000011);
NV_WR32(par->PRAMIN, 0x0003 * 4, 0x80011202);
NV_WR32(par->PRAMIN, 0x0004 * 4, 0x80000012);
NV_WR32(par->PRAMIN, 0x0005 * 4, 0x80011203);
NV_WR32(par->PRAMIN, 0x0006 * 4, 0x80000013);
NV_WR32(par->PRAMIN, 0x0007 * 4, 0x80011204);
NV_WR32(par->PRAMIN, 0x0008 * 4, 0x80000014);
NV_WR32(par->PRAMIN, 0x0009 * 4, 0x80011205);
NV_WR32(par->PRAMIN, 0x000A * 4, 0x80000015);
NV_WR32(par->PRAMIN, 0x000B * 4, 0x80011206);
NV_WR32(par->PRAMIN, 0x000C * 4, 0x80000016);
NV_WR32(par->PRAMIN, 0x000D * 4, 0x80011207);
NV_WR32(par->PRAMIN, 0x000E * 4, 0x80000017);
NV_WR32(par->PRAMIN, 0x000F * 4, 0x80011208);
NV_WR32(par->PRAMIN, 0x0800 * 4, 0x00003000);
NV_WR32(par->PRAMIN, 0x0801 * 4, par->FbMapSize - 1);
NV_WR32(par->PRAMIN, 0x0802 * 4, 0x00000002);
NV_WR32(par->PRAMIN, 0x0803 * 4, 0x00000002);
if (par->Architecture >= NV_ARCH_10)
NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008062);
else
NV_WR32(par->PRAMIN, 0x0804 * 4, 0x01008042);
NV_WR32(par->PRAMIN, 0x0805 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0806 * 4, 0x12001200);
NV_WR32(par->PRAMIN, 0x0807 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0808 * 4, 0x01008043);
NV_WR32(par->PRAMIN, 0x0809 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x080A * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x080B * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x080C * 4, 0x01008044);
NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000002);
NV_WR32(par->PRAMIN, 0x080E * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x080F * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0810 * 4, 0x01008019);
NV_WR32(par->PRAMIN, 0x0811 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0812 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0813 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0814 * 4, 0x0100A05C);
NV_WR32(par->PRAMIN, 0x0815 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0816 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0817 * 4, 0x00000000);
if (par->WaitVSyncPossible)
NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100809F);
else
NV_WR32(par->PRAMIN, 0x0818 * 4, 0x0100805F);
NV_WR32(par->PRAMIN, 0x0819 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x081A * 4, 0x12001200);
NV_WR32(par->PRAMIN, 0x081B * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x081C * 4, 0x0100804A);
NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000002);
NV_WR32(par->PRAMIN, 0x081E * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x081F * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0820 * 4, 0x01018077);
NV_WR32(par->PRAMIN, 0x0821 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0822 * 4, 0x12001200);
NV_WR32(par->PRAMIN, 0x0823 * 4, 0x00000000);
NV_WR32(par->PRAMIN, 0x0824 * 4, 0x00003002);
NV_WR32(par->PRAMIN, 0x0825 * 4, 0x00007FFF);
NV_WR32(par->PRAMIN, 0x0826 * 4,
par->FbUsableSize | 0x00000002);
NV_WR32(par->PRAMIN, 0x0827 * 4, 0x00000002);
#ifdef __BIG_ENDIAN
NV_WR32(par->PRAMIN, 0x0804 * 4,
NV_RD32(par->PRAMIN, 0x0804 * 4) | 0x00080000);
NV_WR32(par->PRAMIN, 0x0808 * 4,
NV_RD32(par->PRAMIN, 0x0808 * 4) | 0x00080000);
NV_WR32(par->PRAMIN, 0x080C * 4,
NV_RD32(par->PRAMIN, 0x080C * 4) | 0x00080000);
NV_WR32(par->PRAMIN, 0x0810 * 4,
NV_RD32(par->PRAMIN, 0x0810 * 4) | 0x00080000);
NV_WR32(par->PRAMIN, 0x0814 * 4,
NV_RD32(par->PRAMIN, 0x0814 * 4) | 0x00080000);
NV_WR32(par->PRAMIN, 0x0818 * 4,
NV_RD32(par->PRAMIN, 0x0818 * 4) | 0x00080000);
NV_WR32(par->PRAMIN, 0x081C * 4,
NV_RD32(par->PRAMIN, 0x081C * 4) | 0x00080000);
NV_WR32(par->PRAMIN, 0x0820 * 4,
NV_RD32(par->PRAMIN, 0x0820 * 4) | 0x00080000);
NV_WR32(par->PRAMIN, 0x080D * 4, 0x00000001);
NV_WR32(par->PRAMIN, 0x081D * 4, 0x00000001);
#endif
}
if (par->Architecture < NV_ARCH_10) {
if ((par->Chipset & 0x0fff) == 0x0020) {
NV_WR32(par->PRAMIN, 0x0824 * 4,
NV_RD32(par->PRAMIN, 0x0824 * 4) | 0x00020000);
NV_WR32(par->PRAMIN, 0x0826 * 4,
NV_RD32(par->PRAMIN,
0x0826 * 4) + par->FbAddress);
}
NV_WR32(par->PGRAPH, 0x0080, 0x000001FF);
NV_WR32(par->PGRAPH, 0x0080, 0x1230C000);
NV_WR32(par->PGRAPH, 0x0084, 0x72111101);
NV_WR32(par->PGRAPH, 0x0088, 0x11D5F071);
NV_WR32(par->PGRAPH, 0x008C, 0x0004FF31);
NV_WR32(par->PGRAPH, 0x008C, 0x4004FF31);
NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
NV_WR32(par->PGRAPH, 0x0170, 0x10010100);
NV_WR32(par->PGRAPH, 0x0710, 0xFFFFFFFF);
NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
} else {
NV_WR32(par->PGRAPH, 0x0080, 0xFFFFFFFF);
NV_WR32(par->PGRAPH, 0x0080, 0x00000000);
NV_WR32(par->PGRAPH, 0x0140, 0x00000000);
NV_WR32(par->PGRAPH, 0x0100, 0xFFFFFFFF);
NV_WR32(par->PGRAPH, 0x0144, 0x10010100);
NV_WR32(par->PGRAPH, 0x0714, 0xFFFFFFFF);
NV_WR32(par->PGRAPH, 0x0720, 0x00000001);
NV_WR32(par->PGRAPH, 0x0710,
NV_RD32(par->PGRAPH, 0x0710) & 0x0007ff00);
NV_WR32(par->PGRAPH, 0x0710,
NV_RD32(par->PGRAPH, 0x0710) | 0x00020100);
if (par->Architecture == NV_ARCH_10) {
NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
NV_WR32(par->PGRAPH, 0x0088, 0x24E00810);
NV_WR32(par->PGRAPH, 0x008C, 0x55DE0030);
for (i = 0; i < 32; i++)
NV_WR32(&par->PGRAPH[(0x0B00 / 4) + i], 0,
NV_RD32(&par->PFB[(0x0240 / 4) + i],
0));
NV_WR32(par->PGRAPH, 0x640, 0);
NV_WR32(par->PGRAPH, 0x644, 0);
NV_WR32(par->PGRAPH, 0x684, par->FbMapSize - 1);
NV_WR32(par->PGRAPH, 0x688, par->FbMapSize - 1);
NV_WR32(par->PGRAPH, 0x0810, 0x00000000);
NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
} else {
if (par->Architecture >= NV_ARCH_40) {
NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
NV_WR32(par->PGRAPH, 0x0bc4,
NV_RD32(par->PGRAPH, 0x0bc4) |
0x00008000);
j = NV_RD32(par->REGS, 0x1540) & 0xff;
if (j) {
for (i = 0; !(j & 1); j >>= 1, i++);
NV_WR32(par->PGRAPH, 0x5000, i);
}
if ((par->Chipset & 0xfff0) == 0x0040) {
NV_WR32(par->PGRAPH, 0x09b0,
0x83280fff);
NV_WR32(par->PGRAPH, 0x09b4,
0x000000a0);
} else {
NV_WR32(par->PGRAPH, 0x0820,
0x83280eff);
NV_WR32(par->PGRAPH, 0x0824,
0x000000a0);
}
switch (par->Chipset & 0xfff0) {
case 0x0040:
case 0x0210:
NV_WR32(par->PGRAPH, 0x09b8,
0x0078e366);
NV_WR32(par->PGRAPH, 0x09bc,
0x0000014c);
NV_WR32(par->PFB, 0x033C,
NV_RD32(par->PFB, 0x33C) &
0xffff7fff);
break;
case 0x00C0:
case 0x0120:
NV_WR32(par->PGRAPH, 0x0828,
0x007596ff);
NV_WR32(par->PGRAPH, 0x082C,
0x00000108);
break;
case 0x0160:
case 0x01D0:
case 0x0240:
case 0x03D0:
NV_WR32(par->PMC, 0x1700,
NV_RD32(par->PFB, 0x020C));
NV_WR32(par->PMC, 0x1704, 0);
NV_WR32(par->PMC, 0x1708, 0);
NV_WR32(par->PMC, 0x170C,
NV_RD32(par->PFB, 0x020C));
NV_WR32(par->PGRAPH, 0x0860, 0);
NV_WR32(par->PGRAPH, 0x0864, 0);
NV_WR32(par->PRAMDAC, 0x0608,
NV_RD32(par->PRAMDAC,
0x0608) | 0x00100000);
break;
case 0x0140:
NV_WR32(par->PGRAPH, 0x0828,
0x0072cb77);
NV_WR32(par->PGRAPH, 0x082C,
0x00000108);
break;
case 0x0220:
NV_WR32(par->PGRAPH, 0x0860, 0);
NV_WR32(par->PGRAPH, 0x0864, 0);
NV_WR32(par->PRAMDAC, 0x0608,
NV_RD32(par->PRAMDAC, 0x0608) |
0x00100000);
break;
case 0x0090:
case 0x0290:
case 0x0390:
NV_WR32(par->PRAMDAC, 0x0608,
NV_RD32(par->PRAMDAC, 0x0608) |
0x00100000);
NV_WR32(par->PGRAPH, 0x0828,
0x07830610);
NV_WR32(par->PGRAPH, 0x082C,
0x0000016A);
break;
default:
break;
}
NV_WR32(par->PGRAPH, 0x0b38, 0x2ffff800);
NV_WR32(par->PGRAPH, 0x0b3c, 0x00006000);
NV_WR32(par->PGRAPH, 0x032C, 0x01000000);
NV_WR32(par->PGRAPH, 0x0220, 0x00001200);
} else if (par->Architecture == NV_ARCH_30) {
NV_WR32(par->PGRAPH, 0x0084, 0x40108700);
NV_WR32(par->PGRAPH, 0x0890, 0x00140000);
NV_WR32(par->PGRAPH, 0x008C, 0xf00e0431);
NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
NV_WR32(par->PGRAPH, 0x0610, 0xf04b1f36);
NV_WR32(par->PGRAPH, 0x0B80, 0x1002d888);
NV_WR32(par->PGRAPH, 0x0B88, 0x62ff007f);
} else {
NV_WR32(par->PGRAPH, 0x0084, 0x00118700);
NV_WR32(par->PGRAPH, 0x008C, 0xF20E0431);
NV_WR32(par->PGRAPH, 0x0090, 0x00000000);
NV_WR32(par->PGRAPH, 0x009C, 0x00000040);
if ((par->Chipset & 0x0ff0) >= 0x0250) {
NV_WR32(par->PGRAPH, 0x0890,
0x00080000);
NV_WR32(par->PGRAPH, 0x0610,
0x304B1FB6);
NV_WR32(par->PGRAPH, 0x0B80,
0x18B82880);
NV_WR32(par->PGRAPH, 0x0B84,
0x44000000);
NV_WR32(par->PGRAPH, 0x0098,
0x40000080);
NV_WR32(par->PGRAPH, 0x0B88,
0x000000ff);
} else {
NV_WR32(par->PGRAPH, 0x0880,
0x00080000);
NV_WR32(par->PGRAPH, 0x0094,
0x00000005);
NV_WR32(par->PGRAPH, 0x0B80,
0x45CAA208);
NV_WR32(par->PGRAPH, 0x0B84,
0x24000000);
NV_WR32(par->PGRAPH, 0x0098,
0x00000040);
NV_WR32(par->PGRAPH, 0x0750,
0x00E00038);
NV_WR32(par->PGRAPH, 0x0754,
0x00000030);
NV_WR32(par->PGRAPH, 0x0750,
0x00E10038);
NV_WR32(par->PGRAPH, 0x0754,
0x00000030);
}
}
if ((par->Architecture < NV_ARCH_40) ||
((par->Chipset & 0xfff0) == 0x0040)) {
for (i = 0; i < 32; i++) {
NV_WR32(par->PGRAPH, 0x0900 + i*4,
NV_RD32(par->PFB, 0x0240 +i*4));
NV_WR32(par->PGRAPH, 0x6900 + i*4,
NV_RD32(par->PFB, 0x0240 +i*4));
}
} else {
if (((par->Chipset & 0xfff0) == 0x0090) ||
((par->Chipset & 0xfff0) == 0x01D0) ||
((par->Chipset & 0xfff0) == 0x0290) ||
((par->Chipset & 0xfff0) == 0x0390) ||
((par->Chipset & 0xfff0) == 0x03D0)) {
for (i = 0; i < 60; i++) {
NV_WR32(par->PGRAPH,
0x0D00 + i*4,
NV_RD32(par->PFB,
0x0600 + i*4));
NV_WR32(par->PGRAPH,
0x6900 + i*4,
NV_RD32(par->PFB,
0x0600 + i*4));
}
} else {
for (i = 0; i < 48; i++) {
NV_WR32(par->PGRAPH,
0x0900 + i*4,
NV_RD32(par->PFB,
0x0600 + i*4));
if(((par->Chipset & 0xfff0)
!= 0x0160) &&
((par->Chipset & 0xfff0)
!= 0x0220) &&
((par->Chipset & 0xfff0)
!= 0x240))
NV_WR32(par->PGRAPH,
0x6900 + i*4,
NV_RD32(par->PFB,
0x0600 + i*4));
}
}
}
if (par->Architecture >= NV_ARCH_40) {
if ((par->Chipset & 0xfff0) == 0x0040) {
NV_WR32(par->PGRAPH, 0x09A4,
NV_RD32(par->PFB, 0x0200));
NV_WR32(par->PGRAPH, 0x09A8,
NV_RD32(par->PFB, 0x0204));
NV_WR32(par->PGRAPH, 0x69A4,
NV_RD32(par->PFB, 0x0200));
NV_WR32(par->PGRAPH, 0x69A8,
NV_RD32(par->PFB, 0x0204));
NV_WR32(par->PGRAPH, 0x0820, 0);
NV_WR32(par->PGRAPH, 0x0824, 0);
NV_WR32(par->PGRAPH, 0x0864,
par->FbMapSize - 1);
NV_WR32(par->PGRAPH, 0x0868,
par->FbMapSize - 1);
} else {
if ((par->Chipset & 0xfff0) == 0x0090 ||
(par->Chipset & 0xfff0) == 0x01D0 ||
(par->Chipset & 0xfff0) == 0x0290 ||
(par->Chipset & 0xfff0) == 0x0390) {
NV_WR32(par->PGRAPH, 0x0DF0,
NV_RD32(par->PFB, 0x0200));
NV_WR32(par->PGRAPH, 0x0DF4,
NV_RD32(par->PFB, 0x0204));
} else {
NV_WR32(par->PGRAPH, 0x09F0,
NV_RD32(par->PFB, 0x0200));
NV_WR32(par->PGRAPH, 0x09F4,
NV_RD32(par->PFB, 0x0204));
}
NV_WR32(par->PGRAPH, 0x69F0,
NV_RD32(par->PFB, 0x0200));
NV_WR32(par->PGRAPH, 0x69F4,
NV_RD32(par->PFB, 0x0204));
NV_WR32(par->PGRAPH, 0x0840, 0);
NV_WR32(par->PGRAPH, 0x0844, 0);
NV_WR32(par->PGRAPH, 0x08a0,
par->FbMapSize - 1);
NV_WR32(par->PGRAPH, 0x08a4,
par->FbMapSize - 1);
}
} else {
NV_WR32(par->PGRAPH, 0x09A4,
NV_RD32(par->PFB, 0x0200));
NV_WR32(par->PGRAPH, 0x09A8,
NV_RD32(par->PFB, 0x0204));
NV_WR32(par->PGRAPH, 0x0750, 0x00EA0000);
NV_WR32(par->PGRAPH, 0x0754,
NV_RD32(par->PFB, 0x0200));
NV_WR32(par->PGRAPH, 0x0750, 0x00EA0004);
NV_WR32(par->PGRAPH, 0x0754,
NV_RD32(par->PFB, 0x0204));
NV_WR32(par->PGRAPH, 0x0820, 0);
NV_WR32(par->PGRAPH, 0x0824, 0);
NV_WR32(par->PGRAPH, 0x0864,
par->FbMapSize - 1);
NV_WR32(par->PGRAPH, 0x0868,
par->FbMapSize - 1);
}
NV_WR32(par->PGRAPH, 0x0B20, 0x00000000);
NV_WR32(par->PGRAPH, 0x0B04, 0xFFFFFFFF);
}
}
NV_WR32(par->PGRAPH, 0x053C, 0);
NV_WR32(par->PGRAPH, 0x0540, 0);
NV_WR32(par->PGRAPH, 0x0544, 0x00007FFF);
NV_WR32(par->PGRAPH, 0x0548, 0x00007FFF);
NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000);
NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001);
NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000);
NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000);
if (par->Architecture >= NV_ARCH_40)
NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000);
else
NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100);
NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000);
NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000);
if (par->Architecture >= NV_ARCH_40)
NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213);
else
NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209);
NV_WR32(par->PFIFO, 0x0400 * 4, 0x00000000);
NV_WR32(par->PFIFO, 0x0414 * 4, 0x00000000);
NV_WR32(par->PFIFO, 0x0084 * 4, 0x03000100);
NV_WR32(par->PFIFO, 0x0085 * 4, 0x00000110);
NV_WR32(par->PFIFO, 0x0086 * 4, 0x00000112);
NV_WR32(par->PFIFO, 0x0143 * 4, 0x0000FFFF);
NV_WR32(par->PFIFO, 0x0496 * 4, 0x0000FFFF);
NV_WR32(par->PFIFO, 0x0050 * 4, 0x00000000);
NV_WR32(par->PFIFO, 0x0040 * 4, 0xFFFFFFFF);
NV_WR32(par->PFIFO, 0x0415 * 4, 0x00000001);
NV_WR32(par->PFIFO, 0x048C * 4, 0x00000000);
NV_WR32(par->PFIFO, 0x04A0 * 4, 0x00000000);
#ifdef __BIG_ENDIAN
NV_WR32(par->PFIFO, 0x0489 * 4, 0x800F0078);
#else
NV_WR32(par->PFIFO, 0x0489 * 4, 0x000F0078);
#endif
NV_WR32(par->PFIFO, 0x0488 * 4, 0x00000001);
NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000001);
NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000001);
NV_WR32(par->PFIFO, 0x0495 * 4, 0x00000001);
NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000001);
if (!state) {
par->CurrentState = NULL;
return;
}
if (par->Architecture >= NV_ARCH_10) {
if (par->twoHeads) {
NV_WR32(par->PCRTC0, 0x0860, state->head);
NV_WR32(par->PCRTC0, 0x2860, state->head2);
}
NV_WR32(par->PRAMDAC, 0x0404, NV_RD32(par->PRAMDAC, 0x0404) |
(1 << 25));
NV_WR32(par->PMC, 0x8704, 1);
NV_WR32(par->PMC, 0x8140, 0);
NV_WR32(par->PMC, 0x8920, 0);
NV_WR32(par->PMC, 0x8924, 0);
NV_WR32(par->PMC, 0x8908, par->FbMapSize - 1);
NV_WR32(par->PMC, 0x890C, par->FbMapSize - 1);
NV_WR32(par->PMC, 0x1588, 0);
NV_WR32(par->PCRTC, 0x0810, state->cursorConfig);
NV_WR32(par->PCRTC, 0x0830, state->displayV - 3);
NV_WR32(par->PCRTC, 0x0834, state->displayV - 1);
if (par->FlatPanel) {
if ((par->Chipset & 0x0ff0) == 0x0110) {
NV_WR32(par->PRAMDAC, 0x0528, state->dither);
} else if (par->twoHeads) {
NV_WR32(par->PRAMDAC, 0x083C, state->dither);
}
VGA_WR08(par->PCIO, 0x03D4, 0x53);
VGA_WR08(par->PCIO, 0x03D5, state->timingH);
VGA_WR08(par->PCIO, 0x03D4, 0x54);
VGA_WR08(par->PCIO, 0x03D5, state->timingV);
VGA_WR08(par->PCIO, 0x03D4, 0x21);
VGA_WR08(par->PCIO, 0x03D5, 0xfa);
}
VGA_WR08(par->PCIO, 0x03D4, 0x41);
VGA_WR08(par->PCIO, 0x03D5, state->extra);
}
VGA_WR08(par->PCIO, 0x03D4, 0x19);
VGA_WR08(par->PCIO, 0x03D5, state->repaint0);
VGA_WR08(par->PCIO, 0x03D4, 0x1A);
VGA_WR08(par->PCIO, 0x03D5, state->repaint1);
VGA_WR08(par->PCIO, 0x03D4, 0x25);
VGA_WR08(par->PCIO, 0x03D5, state->screen);
VGA_WR08(par->PCIO, 0x03D4, 0x28);
VGA_WR08(par->PCIO, 0x03D5, state->pixel);
VGA_WR08(par->PCIO, 0x03D4, 0x2D);
VGA_WR08(par->PCIO, 0x03D5, state->horiz);
VGA_WR08(par->PCIO, 0x03D4, 0x1C);
VGA_WR08(par->PCIO, 0x03D5, state->fifo);
VGA_WR08(par->PCIO, 0x03D4, 0x1B);
VGA_WR08(par->PCIO, 0x03D5, state->arbitration0);
VGA_WR08(par->PCIO, 0x03D4, 0x20);
VGA_WR08(par->PCIO, 0x03D5, state->arbitration1);
if(par->Architecture >= NV_ARCH_30) {
VGA_WR08(par->PCIO, 0x03D4, 0x47);
VGA_WR08(par->PCIO, 0x03D5, state->arbitration1 >> 8);
}
VGA_WR08(par->PCIO, 0x03D4, 0x30);
VGA_WR08(par->PCIO, 0x03D5, state->cursor0);
VGA_WR08(par->PCIO, 0x03D4, 0x31);
VGA_WR08(par->PCIO, 0x03D5, state->cursor1);
VGA_WR08(par->PCIO, 0x03D4, 0x2F);
VGA_WR08(par->PCIO, 0x03D5, state->cursor2);
VGA_WR08(par->PCIO, 0x03D4, 0x39);
VGA_WR08(par->PCIO, 0x03D5, state->interlace);
if (!par->FlatPanel) {
if (par->Architecture >= NV_ARCH_40)
NV_WR32(par->PRAMDAC0, 0x0580, state->control);
NV_WR32(par->PRAMDAC0, 0x050C, state->pllsel);
NV_WR32(par->PRAMDAC0, 0x0508, state->vpll);
if (par->twoHeads)
NV_WR32(par->PRAMDAC0, 0x0520, state->vpll2);
if (par->twoStagePLL) {
NV_WR32(par->PRAMDAC0, 0x0578, state->vpllB);
NV_WR32(par->PRAMDAC0, 0x057C, state->vpll2B);
}
} else {
NV_WR32(par->PRAMDAC, 0x0848, state->scale);
NV_WR32(par->PRAMDAC, 0x0828, state->crtcSync +
par->PanelTweak);
}
NV_WR32(par->PRAMDAC, 0x0600, state->general);
NV_WR32(par->PCRTC, 0x0140, 0);
NV_WR32(par->PCRTC, 0x0100, 1);
par->CurrentState = state;
}
void NVUnloadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state) {
VGA_WR08(par->PCIO, 0x03D4, 0x19);
state->repaint0 = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x1A);
state->repaint1 = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x25);
state->screen = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x28);
state->pixel = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x2D);
state->horiz = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x1C);
state->fifo = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x1B);
state->arbitration0 = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x20);
state->arbitration1 = VGA_RD08(par->PCIO, 0x03D5);
if(par->Architecture >= NV_ARCH_30) {
VGA_WR08(par->PCIO, 0x03D4, 0x47);
state->arbitration1 |= (VGA_RD08(par->PCIO, 0x03D5) & 1) << 8;
}
VGA_WR08(par->PCIO, 0x03D4, 0x30);
state->cursor0 = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x31);
state->cursor1 = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x2F);
state->cursor2 = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x39);
state->interlace = VGA_RD08(par->PCIO, 0x03D5);
state->vpll = NV_RD32(par->PRAMDAC0, 0x0508);
if (par->twoHeads)
state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
if (par->twoStagePLL) {
state->vpllB = NV_RD32(par->PRAMDAC0, 0x0578);
state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
}
state->pllsel = NV_RD32(par->PRAMDAC0, 0x050C);
state->general = NV_RD32(par->PRAMDAC, 0x0600);
state->scale = NV_RD32(par->PRAMDAC, 0x0848);
state->config = NV_RD32(par->PFB, 0x0200);
if (par->Architecture >= NV_ARCH_40 && !par->FlatPanel)
state->control = NV_RD32(par->PRAMDAC0, 0x0580);
if (par->Architecture >= NV_ARCH_10) {
if (par->twoHeads) {
state->head = NV_RD32(par->PCRTC0, 0x0860);
state->head2 = NV_RD32(par->PCRTC0, 0x2860);
VGA_WR08(par->PCIO, 0x03D4, 0x44);
state->crtcOwner = VGA_RD08(par->PCIO, 0x03D5);
}
VGA_WR08(par->PCIO, 0x03D4, 0x41);
state->extra = VGA_RD08(par->PCIO, 0x03D5);
state->cursorConfig = NV_RD32(par->PCRTC, 0x0810);
if ((par->Chipset & 0x0ff0) == 0x0110) {
state->dither = NV_RD32(par->PRAMDAC, 0x0528);
} else if (par->twoHeads) {
state->dither = NV_RD32(par->PRAMDAC, 0x083C);
}
if (par->FlatPanel) {
VGA_WR08(par->PCIO, 0x03D4, 0x53);
state->timingH = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D4, 0x54);
state->timingV = VGA_RD08(par->PCIO, 0x03D5);
}
}
}
void NVSetStartAddress(struct nvidia_par *par, u32 start)
{
NV_WR32(par->PCRTC, 0x800, start);
}
| linux-master | drivers/video/fbdev/nvidia/nv_hw.c |
/*
* linux/drivers/video/nvidia/nvidia-i2c.c - nVidia i2c
*
* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
*
* Based on rivafb-i2c.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include <asm/io.h>
#include "nv_type.h"
#include "nv_local.h"
#include "nv_proto.h"
#include "../edid.h"
static void nvidia_gpio_setscl(void *data, int state)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val;
val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
if (state)
val |= 0x20;
else
val &= ~0x20;
NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
}
static void nvidia_gpio_setsda(void *data, int state)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val;
val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
if (state)
val |= 0x10;
else
val &= ~0x10;
NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
}
static int nvidia_gpio_getscl(void *data)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val = 0;
if (NVReadCrtc(par, chan->ddc_base) & 0x04)
val = 1;
return val;
}
static int nvidia_gpio_getsda(void *data)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val = 0;
if (NVReadCrtc(par, chan->ddc_base) & 0x08)
val = 1;
return val;
}
static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name,
unsigned int i2c_class)
{
int rc;
strscpy(chan->adapter.name, name, sizeof(chan->adapter.name));
chan->adapter.owner = THIS_MODULE;
chan->adapter.class = i2c_class;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->par->pci_dev->dev;
chan->algo.setsda = nvidia_gpio_setsda;
chan->algo.setscl = nvidia_gpio_setscl;
chan->algo.getsda = nvidia_gpio_getsda;
chan->algo.getscl = nvidia_gpio_getscl;
chan->algo.udelay = 40;
chan->algo.timeout = msecs_to_jiffies(2);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
/* Raise SCL and SDA */
nvidia_gpio_setsda(chan, 1);
nvidia_gpio_setscl(chan, 1);
udelay(20);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
dev_dbg(&chan->par->pci_dev->dev,
"I2C bus %s registered.\n", name);
else {
dev_warn(&chan->par->pci_dev->dev,
"Failed to register I2C bus %s.\n", name);
chan->par = NULL;
}
return rc;
}
void nvidia_create_i2c_busses(struct nvidia_par *par)
{
par->chan[0].par = par;
par->chan[1].par = par;
par->chan[2].par = par;
par->chan[0].ddc_base = (par->reverse_i2c) ? 0x36 : 0x3e;
nvidia_setup_i2c_bus(&par->chan[0], "nvidia #0",
(par->reverse_i2c) ? I2C_CLASS_HWMON : 0);
par->chan[1].ddc_base = (par->reverse_i2c) ? 0x3e : 0x36;
nvidia_setup_i2c_bus(&par->chan[1], "nvidia #1",
(par->reverse_i2c) ? 0 : I2C_CLASS_HWMON);
par->chan[2].ddc_base = 0x50;
nvidia_setup_i2c_bus(&par->chan[2], "nvidia #2", 0);
}
void nvidia_delete_i2c_busses(struct nvidia_par *par)
{
int i;
for (i = 0; i < 3; i++) {
if (!par->chan[i].par)
continue;
i2c_del_adapter(&par->chan[i].adapter);
par->chan[i].par = NULL;
}
}
int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid)
{
struct nvidia_par *par = info->par;
u8 *edid = NULL;
if (par->chan[conn - 1].par)
edid = fb_ddc_read(&par->chan[conn - 1].adapter);
if (!edid && conn == 1) {
/* try to get from firmware */
const u8 *e = fb_firmware_edid(info->device);
if (e != NULL)
edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
}
*out_edid = edid;
return (edid) ? 0 : 1;
}
| linux-master | drivers/video/fbdev/nvidia/nv_i2c.c |
/*
* linux/drivers/video/nvidia/nv_of.c
*
* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
*
* Based on rivafb-i2c.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include <asm/io.h>
#include "nv_type.h"
#include "nv_local.h"
#include "nv_proto.h"
#include "../edid.h"
int nvidia_probe_of_connector(struct fb_info *info, int conn, u8 **out_edid)
{
struct nvidia_par *par = info->par;
struct device_node *parent, *dp;
const unsigned char *pedid = NULL;
static char *propnames[] = {
"DFP,EDID", "LCD,EDID", "EDID", "EDID1",
"EDID,B", "EDID,A", NULL };
int i;
parent = pci_device_to_OF_node(par->pci_dev);
if (parent == NULL)
return -1;
if (par->twoHeads) {
const char *pname;
int len;
for_each_child_of_node(parent, dp) {
pname = of_get_property(dp, "name", NULL);
if (!pname)
continue;
len = strlen(pname);
if ((pname[len-1] == 'A' && conn == 1) ||
(pname[len-1] == 'B' && conn == 2)) {
for (i = 0; propnames[i] != NULL; ++i) {
pedid = of_get_property(dp,
propnames[i], NULL);
if (pedid != NULL)
break;
}
of_node_put(dp);
break;
}
}
}
if (pedid == NULL) {
for (i = 0; propnames[i] != NULL; ++i) {
pedid = of_get_property(parent, propnames[i], NULL);
if (pedid != NULL)
break;
}
}
if (pedid) {
*out_edid = kmemdup(pedid, EDID_LENGTH, GFP_KERNEL);
if (*out_edid == NULL)
return -1;
printk(KERN_DEBUG "nvidiafb: Found OF EDID for head %d\n", conn);
return 0;
}
return -1;
}
| linux-master | drivers/video/fbdev/nvidia/nv_of.c |
/***************************************************************************\
|* *|
|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
* XFree86 'nv' driver, this source code is provided under MIT-style licensing
* where the source code is provided "as is" without warranty of any kind.
* The only usage restriction is for the copyright notices to be retained
* whenever code is used.
*
* Antonino Daplas <[email protected]> 2005-03-11
*/
#include <video/vga.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include "nv_type.h"
#include "nv_local.h"
#include "nv_proto.h"
/*
* Override VGA I/O routines.
*/
void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
{
VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
}
u8 NVReadCrtc(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
}
void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
{
VGA_WR08(par->PVIO, VGA_GFX_I, index);
VGA_WR08(par->PVIO, VGA_GFX_D, value);
}
u8 NVReadGr(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PVIO, VGA_GFX_I, index);
return (VGA_RD08(par->PVIO, VGA_GFX_D));
}
void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
{
VGA_WR08(par->PVIO, VGA_SEQ_I, index);
VGA_WR08(par->PVIO, VGA_SEQ_D, value);
}
u8 NVReadSeq(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PVIO, VGA_SEQ_I, index);
return (VGA_RD08(par->PVIO, VGA_SEQ_D));
}
void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
{
VGA_RD08(par->PCIO, par->IOBase + 0x0a);
if (par->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
VGA_WR08(par->PCIO, VGA_ATT_IW, index);
VGA_WR08(par->PCIO, VGA_ATT_W, value);
}
u8 NVReadAttr(struct nvidia_par *par, u8 index)
{
VGA_RD08(par->PCIO, par->IOBase + 0x0a);
if (par->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
VGA_WR08(par->PCIO, VGA_ATT_IW, index);
return (VGA_RD08(par->PCIO, VGA_ATT_R));
}
void NVWriteMiscOut(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PVIO, VGA_MIS_W, value);
}
u8 NVReadMiscOut(struct nvidia_par *par)
{
return (VGA_RD08(par->PVIO, VGA_MIS_R));
}
void NVWriteDacMask(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
}
void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PDIO, VGA_PEL_IR, value);
}
void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PDIO, VGA_PEL_IW, value);
}
void NVWriteDacData(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PDIO, VGA_PEL_D, value);
}
u8 NVReadDacData(struct nvidia_par *par)
{
return (VGA_RD08(par->PDIO, VGA_PEL_D));
}
static int NVIsConnected(struct nvidia_par *par, int output)
{
volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
u32 reg52C, reg608, dac0_reg608 = 0;
int present;
if (output) {
dac0_reg608 = NV_RD32(PRAMDAC, 0x0608);
PRAMDAC += 0x800;
}
reg52C = NV_RD32(PRAMDAC, 0x052C);
reg608 = NV_RD32(PRAMDAC, 0x0608);
NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
msleep(1);
NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
0x00001000);
msleep(1);
present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
if (present)
printk("nvidiafb: CRTC%i analog found\n", output);
else
printk("nvidiafb: CRTC%i analog not found\n", output);
if (output)
NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
NV_WR32(PRAMDAC, 0x052C, reg52C);
NV_WR32(PRAMDAC, 0x0608, reg608);
return present;
}
static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
{
if (head) {
par->PCIO = par->PCIO0 + 0x2000;
par->PCRTC = par->PCRTC0 + 0x800;
par->PRAMDAC = par->PRAMDAC0 + 0x800;
par->PDIO = par->PDIO0 + 0x2000;
} else {
par->PCIO = par->PCIO0;
par->PCRTC = par->PCRTC0;
par->PRAMDAC = par->PRAMDAC0;
par->PDIO = par->PDIO0;
}
}
static void nv4GetConfig(struct nvidia_par *par)
{
if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
par->RamAmountKBytes =
((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
1024 * 2;
} else {
switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
case 0:
par->RamAmountKBytes = 1024 * 32;
break;
case 1:
par->RamAmountKBytes = 1024 * 4;
break;
case 2:
par->RamAmountKBytes = 1024 * 8;
break;
case 3:
default:
par->RamAmountKBytes = 1024 * 16;
break;
}
}
par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
14318 : 13500;
par->CURSOR = &par->PRAMIN[0x1E00];
par->MinVClockFreqKHz = 12000;
par->MaxVClockFreqKHz = 350000;
}
static void nv10GetConfig(struct nvidia_par *par)
{
struct pci_dev *dev;
u32 implementation = par->Chipset & 0x0ff0;
#ifdef __BIG_ENDIAN
/* turn on big endian register access */
if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
NV_WR32(par->PMC, 0x0004, 0x01000001);
mb();
}
#endif
dev = pci_get_domain_bus_and_slot(pci_domain_nr(par->pci_dev->bus),
0, 1);
if ((par->Chipset & 0xffff) == 0x01a0) {
u32 amt;
pci_read_config_dword(dev, 0x7c, &amt);
par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
} else if ((par->Chipset & 0xffff) == 0x01f0) {
u32 amt;
pci_read_config_dword(dev, 0x84, &amt);
par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
} else {
par->RamAmountKBytes =
(NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
}
pci_dev_put(dev);
par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
14318 : 13500;
if (par->twoHeads && (implementation != 0x0110)) {
if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
par->CrystalFreqKHz = 27000;
}
par->CURSOR = NULL; /* can't set this here */
par->MinVClockFreqKHz = 12000;
par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
}
int NVCommonSetup(struct fb_info *info)
{
struct nvidia_par *par = info->par;
struct fb_var_screeninfo *var;
u16 implementation = par->Chipset & 0x0ff0;
u8 *edidA = NULL, *edidB = NULL;
struct fb_monspecs *monitorA, *monitorB;
struct fb_monspecs *monA = NULL, *monB = NULL;
int mobile = 0;
int tvA = 0;
int tvB = 0;
int FlatPanel = -1; /* really means the CRTC is slaved */
int Television = 0;
int err = 0;
var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
if (!var || !monitorA || !monitorB) {
err = -ENOMEM;
goto done;
}
par->PRAMIN = par->REGS + (0x00710000 / 4);
par->PCRTC0 = par->REGS + (0x00600000 / 4);
par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
par->PFB = par->REGS + (0x00100000 / 4);
par->PFIFO = par->REGS + (0x00002000 / 4);
par->PGRAPH = par->REGS + (0x00400000 / 4);
par->PEXTDEV = par->REGS + (0x00101000 / 4);
par->PTIMER = par->REGS + (0x00009000 / 4);
par->PMC = par->REGS + (0x00000000 / 4);
par->FIFO = par->REGS + (0x00800000 / 4);
/* 8 bit registers */
par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
(implementation != 0x0100) &&
(implementation != 0x0150) &&
(implementation != 0x01A0) && (implementation != 0x0200);
par->fpScaler = (par->FpScale && par->twoHeads &&
(implementation != 0x0110));
par->twoStagePLL = (implementation == 0x0310) ||
(implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
(implementation != 0x0100);
par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
/* look for known laptop chips */
switch (par->Chipset & 0xffff) {
case 0x0112:
case 0x0174:
case 0x0175:
case 0x0176:
case 0x0177:
case 0x0179:
case 0x017C:
case 0x017D:
case 0x0186:
case 0x0187:
case 0x018D:
case 0x01D7:
case 0x0228:
case 0x0286:
case 0x028C:
case 0x0316:
case 0x0317:
case 0x031A:
case 0x031B:
case 0x031C:
case 0x031D:
case 0x031E:
case 0x031F:
case 0x0324:
case 0x0325:
case 0x0328:
case 0x0329:
case 0x032C:
case 0x032D:
case 0x0347:
case 0x0348:
case 0x0349:
case 0x034B:
case 0x034C:
case 0x0160:
case 0x0166:
case 0x0169:
case 0x016B:
case 0x016C:
case 0x016D:
case 0x00C8:
case 0x00CC:
case 0x0144:
case 0x0146:
case 0x0147:
case 0x0148:
case 0x0098:
case 0x0099:
mobile = 1;
break;
default:
break;
}
if (par->Architecture == NV_ARCH_04)
nv4GetConfig(par);
else
nv10GetConfig(par);
NVSelectHeadRegisters(par, 0);
NVLockUnlock(par, 0);
par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
par->Television = 0;
nvidia_create_i2c_busses(par);
if (!par->twoHeads) {
par->CRTCnumber = 0;
if (nvidia_probe_i2c_connector(info, 1, &edidA))
nvidia_probe_of_connector(info, 1, &edidA);
if (edidA && !fb_parse_edid(edidA, var)) {
printk("nvidiafb: EDID found from BUS1\n");
monA = monitorA;
fb_edid_to_monspecs(edidA, monA);
FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
/* NV4 doesn't support FlatPanels */
if ((par->Chipset & 0x0fff) <= 0x0020)
FlatPanel = 0;
} else {
VGA_WR08(par->PCIO, 0x03D4, 0x28);
if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
VGA_WR08(par->PCIO, 0x03D4, 0x33);
if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
Television = 1;
FlatPanel = 1;
} else {
FlatPanel = 0;
}
printk("nvidiafb: HW is currently programmed for %s\n",
FlatPanel ? (Television ? "TV" : "DFP") :
"CRT");
}
if (par->FlatPanel == -1) {
par->FlatPanel = FlatPanel;
par->Television = Television;
} else {
printk("nvidiafb: Forcing display type to %s as "
"specified\n", par->FlatPanel ? "DFP" : "CRT");
}
} else {
u8 outputAfromCRTC, outputBfromCRTC;
int CRTCnumber = -1;
u8 slaved_on_A, slaved_on_B;
int analog_on_A, analog_on_B;
u32 oldhead;
u8 cr44;
if (implementation != 0x0110) {
if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
outputAfromCRTC = 1;
else
outputAfromCRTC = 0;
if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
outputBfromCRTC = 1;
else
outputBfromCRTC = 0;
analog_on_A = NVIsConnected(par, 0);
analog_on_B = NVIsConnected(par, 1);
} else {
outputAfromCRTC = 0;
outputBfromCRTC = 1;
analog_on_A = 0;
analog_on_B = 0;
}
VGA_WR08(par->PCIO, 0x03D4, 0x44);
cr44 = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D5, 3);
NVSelectHeadRegisters(par, 1);
NVLockUnlock(par, 0);
VGA_WR08(par->PCIO, 0x03D4, 0x28);
slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
if (slaved_on_B) {
VGA_WR08(par->PCIO, 0x03D4, 0x33);
tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
}
VGA_WR08(par->PCIO, 0x03D4, 0x44);
VGA_WR08(par->PCIO, 0x03D5, 0);
NVSelectHeadRegisters(par, 0);
NVLockUnlock(par, 0);
VGA_WR08(par->PCIO, 0x03D4, 0x28);
slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
if (slaved_on_A) {
VGA_WR08(par->PCIO, 0x03D4, 0x33);
tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
}
oldhead = NV_RD32(par->PCRTC0, 0x00000860);
NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
if (nvidia_probe_i2c_connector(info, 1, &edidA))
nvidia_probe_of_connector(info, 1, &edidA);
if (edidA && !fb_parse_edid(edidA, var)) {
printk("nvidiafb: EDID found from BUS1\n");
monA = monitorA;
fb_edid_to_monspecs(edidA, monA);
}
if (nvidia_probe_i2c_connector(info, 2, &edidB))
nvidia_probe_of_connector(info, 2, &edidB);
if (edidB && !fb_parse_edid(edidB, var)) {
printk("nvidiafb: EDID found from BUS2\n");
monB = monitorB;
fb_edid_to_monspecs(edidB, monB);
}
if (slaved_on_A && !tvA) {
CRTCnumber = 0;
FlatPanel = 1;
printk("nvidiafb: CRTC 0 is currently programmed for "
"DFP\n");
} else if (slaved_on_B && !tvB) {
CRTCnumber = 1;
FlatPanel = 1;
printk("nvidiafb: CRTC 1 is currently programmed "
"for DFP\n");
} else if (analog_on_A) {
CRTCnumber = outputAfromCRTC;
FlatPanel = 0;
printk("nvidiafb: CRTC %i appears to have a "
"CRT attached\n", CRTCnumber);
} else if (analog_on_B) {
CRTCnumber = outputBfromCRTC;
FlatPanel = 0;
printk("nvidiafb: CRTC %i appears to have a "
"CRT attached\n", CRTCnumber);
} else if (slaved_on_A) {
CRTCnumber = 0;
FlatPanel = 1;
Television = 1;
printk("nvidiafb: CRTC 0 is currently programmed "
"for TV\n");
} else if (slaved_on_B) {
CRTCnumber = 1;
FlatPanel = 1;
Television = 1;
printk("nvidiafb: CRTC 1 is currently programmed for "
"TV\n");
} else if (monA) {
FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
} else if (monB) {
FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
}
if (par->FlatPanel == -1) {
if (FlatPanel != -1) {
par->FlatPanel = FlatPanel;
par->Television = Television;
} else {
printk("nvidiafb: Unable to detect display "
"type...\n");
if (mobile) {
printk("...On a laptop, assuming "
"DFP\n");
par->FlatPanel = 1;
} else {
printk("...Using default of CRT\n");
par->FlatPanel = 0;
}
}
} else {
printk("nvidiafb: Forcing display type to %s as "
"specified\n", par->FlatPanel ? "DFP" : "CRT");
}
if (par->CRTCnumber == -1) {
if (CRTCnumber != -1)
par->CRTCnumber = CRTCnumber;
else {
printk("nvidiafb: Unable to detect which "
"CRTCNumber...\n");
if (par->FlatPanel)
par->CRTCnumber = 1;
else
par->CRTCnumber = 0;
printk("...Defaulting to CRTCNumber %i\n",
par->CRTCnumber);
}
} else {
printk("nvidiafb: Forcing CRTCNumber %i as "
"specified\n", par->CRTCnumber);
}
if (monA) {
if (((monA->input & FB_DISP_DDI) &&
par->FlatPanel) ||
((!(monA->input & FB_DISP_DDI)) &&
!par->FlatPanel)) {
if (monB) {
fb_destroy_modedb(monB->modedb);
monB = NULL;
}
} else {
fb_destroy_modedb(monA->modedb);
monA = NULL;
}
}
if (monB) {
if (((monB->input & FB_DISP_DDI) &&
!par->FlatPanel) ||
((!(monB->input & FB_DISP_DDI)) &&
par->FlatPanel)) {
fb_destroy_modedb(monB->modedb);
monB = NULL;
} else
monA = monB;
}
if (implementation == 0x0110)
cr44 = par->CRTCnumber * 0x3;
NV_WR32(par->PCRTC0, 0x00000860, oldhead);
VGA_WR08(par->PCIO, 0x03D4, 0x44);
VGA_WR08(par->PCIO, 0x03D5, cr44);
NVSelectHeadRegisters(par, par->CRTCnumber);
}
printk("nvidiafb: Using %s on CRTC %i\n",
par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
par->CRTCnumber);
if (par->FlatPanel && !par->Television) {
par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
}
if (monA)
info->monspecs = *monA;
if (!par->FlatPanel || !par->twoHeads)
par->FPDither = 0;
par->LVDS = 0;
if (par->FlatPanel && par->twoHeads) {
NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
par->LVDS = 1;
printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");
}
kfree(edidA);
kfree(edidB);
done:
kfree(var);
kfree(monitorA);
kfree(monitorB);
return err;
}
| linux-master | drivers/video/fbdev/nvidia/nv_setup.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Backlight code for nVidia based graphic cards
*
* Copyright 2004 Antonino Daplas <[email protected]>
* Copyright (c) 2006 Michael Hanselmann <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/fb.h>
#include <linux/pci.h>
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
#include "nv_local.h"
#include "nv_type.h"
#include "nv_proto.h"
/* We do not have any information about which values are allowed, thus
* we used safe values.
*/
#define MIN_LEVEL 0x158
#define MAX_LEVEL 0x534
#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
static int nvidia_bl_get_level_brightness(struct nvidia_par *par,
int level)
{
struct fb_info *info = pci_get_drvdata(par->pci_dev);
int nlevel;
/* Get and convert the value */
/* No locking of bl_curve since we read a single value */
nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
if (nlevel < 0)
nlevel = 0;
else if (nlevel < MIN_LEVEL)
nlevel = MIN_LEVEL;
else if (nlevel > MAX_LEVEL)
nlevel = MAX_LEVEL;
return nlevel;
}
static int nvidia_bl_update_status(struct backlight_device *bd)
{
struct nvidia_par *par = bl_get_data(bd);
u32 tmp_pcrt, tmp_pmc, fpcontrol;
int level = backlight_get_brightness(bd);
if (!par->FlatPanel)
return 0;
tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
if (level > 0) {
tmp_pcrt |= 0x1;
tmp_pmc |= (1 << 31); /* backlight bit */
tmp_pmc |= nvidia_bl_get_level_brightness(par, level) << 16;
fpcontrol |= par->fpSyncs;
} else
fpcontrol |= 0x20000022;
NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
NV_WR32(par->PMC, 0x10F0, tmp_pmc);
NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
return 0;
}
static const struct backlight_ops nvidia_bl_ops = {
.update_status = nvidia_bl_update_status,
};
void nvidia_bl_init(struct nvidia_par *par)
{
struct backlight_properties props;
struct fb_info *info = pci_get_drvdata(par->pci_dev);
struct backlight_device *bd;
char name[12];
if (!par->FlatPanel)
return;
#ifdef CONFIG_PMAC_BACKLIGHT
if (!machine_is(powermac) ||
!pmac_has_backlight_type("mnca"))
return;
#endif
snprintf(name, sizeof(name), "nvidiabl%d", info->node);
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
bd = backlight_device_register(name, info->device, par, &nvidia_bl_ops,
&props);
if (IS_ERR(bd)) {
info->bl_dev = NULL;
printk(KERN_WARNING "nvidia: Backlight registration failed\n");
goto error;
}
info->bl_dev = bd;
fb_bl_default_curve(info, 0,
0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL,
0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL);
bd->props.brightness = bd->props.max_brightness;
bd->props.power = FB_BLANK_UNBLANK;
backlight_update_status(bd);
printk("nvidia: Backlight initialized (%s)\n", name);
error:
return;
}
void nvidia_bl_exit(struct nvidia_par *par)
{
struct fb_info *info = pci_get_drvdata(par->pci_dev);
struct backlight_device *bd = info->bl_dev;
backlight_device_unregister(bd);
printk("nvidia: Backlight unloaded\n");
}
| linux-master | drivers/video/fbdev/nvidia/nv_backlight.c |
/***************************************************************************\
|* *|
|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
* XFree86 'nv' driver, this source code is provided under MIT-style licensing
* where the source code is provided "as is" without warranty of any kind.
* The only usage restriction is for the copyright notices to be retained
* whenever code is used.
*
* Antonino Daplas <[email protected]> 2005-03-11
*/
#include <linux/fb.h>
#include <linux/nmi.h>
#include "nv_type.h"
#include "nv_proto.h"
#include "nv_dma.h"
#include "nv_local.h"
/* There is a HW race condition with videoram command buffers.
You can't jump to the location of your put offset. We write put
at the jump offset + SKIPS dwords with noop padding in between
to solve this problem */
#define SKIPS 8
static const int NVCopyROP[16] = {
0xCC, /* copy */
0x55 /* invert */
};
static const int NVCopyROP_PM[16] = {
0xCA, /* copy */
0x5A, /* invert */
};
static inline void nvidiafb_safe_mode(struct fb_info *info)
{
struct nvidia_par *par = info->par;
touch_softlockup_watchdog();
info->pixmap.scan_align = 1;
par->lockup = 1;
}
static inline void NVFlush(struct fb_info *info)
{
struct nvidia_par *par = info->par;
int count = 1000000000;
while (--count && READ_GET(par) != par->dmaPut) ;
if (!count) {
printk("nvidiafb: DMA Flush lockup\n");
nvidiafb_safe_mode(info);
}
}
static inline void NVSync(struct fb_info *info)
{
struct nvidia_par *par = info->par;
int count = 1000000000;
while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;
if (!count) {
printk("nvidiafb: DMA Sync lockup\n");
nvidiafb_safe_mode(info);
}
}
static void NVDmaKickoff(struct nvidia_par *par)
{
if (par->dmaCurrent != par->dmaPut) {
par->dmaPut = par->dmaCurrent;
WRITE_PUT(par, par->dmaPut);
}
}
static void NVDmaWait(struct fb_info *info, int size)
{
struct nvidia_par *par = info->par;
int dmaGet;
int count = 1000000000, cnt;
size++;
while (par->dmaFree < size && --count && !par->lockup) {
dmaGet = READ_GET(par);
if (par->dmaPut >= dmaGet) {
par->dmaFree = par->dmaMax - par->dmaCurrent;
if (par->dmaFree < size) {
NVDmaNext(par, 0x20000000);
if (dmaGet <= SKIPS) {
if (par->dmaPut <= SKIPS)
WRITE_PUT(par, SKIPS + 1);
cnt = 1000000000;
do {
dmaGet = READ_GET(par);
} while (--cnt && dmaGet <= SKIPS);
if (!cnt) {
printk("DMA Get lockup\n");
par->lockup = 1;
}
}
WRITE_PUT(par, SKIPS);
par->dmaCurrent = par->dmaPut = SKIPS;
par->dmaFree = dmaGet - (SKIPS + 1);
}
} else
par->dmaFree = dmaGet - par->dmaCurrent - 1;
}
if (!count) {
printk("nvidiafb: DMA Wait Lockup\n");
nvidiafb_safe_mode(info);
}
}
static void NVSetPattern(struct fb_info *info, u32 clr0, u32 clr1,
u32 pat0, u32 pat1)
{
struct nvidia_par *par = info->par;
NVDmaStart(info, par, PATTERN_COLOR_0, 4);
NVDmaNext(par, clr0);
NVDmaNext(par, clr1);
NVDmaNext(par, pat0);
NVDmaNext(par, pat1);
}
static void NVSetRopSolid(struct fb_info *info, u32 rop, u32 planemask)
{
struct nvidia_par *par = info->par;
if (planemask != ~0) {
NVSetPattern(info, 0, planemask, ~0, ~0);
if (par->currentRop != (rop + 32)) {
NVDmaStart(info, par, ROP_SET, 1);
NVDmaNext(par, NVCopyROP_PM[rop]);
par->currentRop = rop + 32;
}
} else if (par->currentRop != rop) {
if (par->currentRop >= 16)
NVSetPattern(info, ~0, ~0, ~0, ~0);
NVDmaStart(info, par, ROP_SET, 1);
NVDmaNext(par, NVCopyROP[rop]);
par->currentRop = rop;
}
}
static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
int x2, int y2)
{
struct nvidia_par *par = info->par;
int h = y2 - y1 + 1;
int w = x2 - x1 + 1;
NVDmaStart(info, par, CLIP_POINT, 2);
NVDmaNext(par, (y1 << 16) | x1);
NVDmaNext(par, (h << 16) | w);
}
void NVResetGraphics(struct fb_info *info)
{
struct nvidia_par *par = info->par;
u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
int pitch, i;
pitch = info->fix.line_length;
par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);
for (i = 0; i < SKIPS; i++)
NV_WR32(&par->dmaBase[i], 0, 0x00000000);
NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);
par->dmaPut = 0;
par->dmaCurrent = 16 + SKIPS;
par->dmaMax = 8191;
par->dmaFree = par->dmaMax - par->dmaCurrent;
switch (info->var.bits_per_pixel) {
case 32:
case 24:
surfaceFormat = SURFACE_FORMAT_DEPTH24;
patternFormat = PATTERN_FORMAT_DEPTH24;
rectFormat = RECT_FORMAT_DEPTH24;
lineFormat = LINE_FORMAT_DEPTH24;
break;
case 16:
surfaceFormat = SURFACE_FORMAT_DEPTH16;
patternFormat = PATTERN_FORMAT_DEPTH16;
rectFormat = RECT_FORMAT_DEPTH16;
lineFormat = LINE_FORMAT_DEPTH16;
break;
default:
surfaceFormat = SURFACE_FORMAT_DEPTH8;
patternFormat = PATTERN_FORMAT_DEPTH8;
rectFormat = RECT_FORMAT_DEPTH8;
lineFormat = LINE_FORMAT_DEPTH8;
break;
}
NVDmaStart(info, par, SURFACE_FORMAT, 4);
NVDmaNext(par, surfaceFormat);
NVDmaNext(par, pitch | (pitch << 16));
NVDmaNext(par, 0);
NVDmaNext(par, 0);
NVDmaStart(info, par, PATTERN_FORMAT, 1);
NVDmaNext(par, patternFormat);
NVDmaStart(info, par, RECT_FORMAT, 1);
NVDmaNext(par, rectFormat);
NVDmaStart(info, par, LINE_FORMAT, 1);
NVDmaNext(par, lineFormat);
par->currentRop = ~0; /* set to something invalid */
NVSetRopSolid(info, ROP_COPY, ~0);
NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
info->var.yres_virtual);
NVDmaKickoff(par);
}
int nvidiafb_sync(struct fb_info *info)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return 0;
if (!par->lockup)
NVFlush(info);
if (!par->lockup)
NVSync(info);
return 0;
}
void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (par->lockup) {
cfb_copyarea(info, region);
return;
}
NVDmaStart(info, par, BLIT_POINT_SRC, 3);
NVDmaNext(par, (region->sy << 16) | region->sx);
NVDmaNext(par, (region->dy << 16) | region->dx);
NVDmaNext(par, (region->height << 16) | region->width);
NVDmaKickoff(par);
}
void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct nvidia_par *par = info->par;
u32 color;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (par->lockup) {
cfb_fillrect(info, rect);
return;
}
if (info->var.bits_per_pixel == 8)
color = rect->color;
else
color = ((u32 *) info->pseudo_palette)[rect->color];
if (rect->rop != ROP_COPY)
NVSetRopSolid(info, rect->rop, ~0);
NVDmaStart(info, par, RECT_SOLID_COLOR, 1);
NVDmaNext(par, color);
NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2);
NVDmaNext(par, (rect->dx << 16) | rect->dy);
NVDmaNext(par, (rect->width << 16) | rect->height);
NVDmaKickoff(par);
if (rect->rop != ROP_COPY)
NVSetRopSolid(info, ROP_COPY, ~0);
}
static void nvidiafb_mono_color_expand(struct fb_info *info,
const struct fb_image *image)
{
struct nvidia_par *par = info->par;
u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
u32 dsize, width, *data = (u32 *) image->data, tmp;
int j, k = 0;
width = (image->width + 31) & ~31;
dsize = (width * image->height) >> 5;
if (info->var.bits_per_pixel == 8) {
fg = image->fg_color | mask;
bg = image->bg_color | mask;
} else {
fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask;
bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask;
}
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
NVDmaNext(par, ((image->dy + image->height) << 16) |
((image->dx + image->width) & 0xffff));
NVDmaNext(par, bg);
NVDmaNext(par, fg);
NVDmaNext(par, (image->height << 16) | width);
NVDmaNext(par, (image->height << 16) | width);
NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0),
RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);
for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
tmp = data[k++];
reverse_order(&tmp);
NVDmaNext(par, tmp);
}
dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
}
if (dsize) {
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);
for (j = dsize; j--;) {
tmp = data[k++];
reverse_order(&tmp);
NVDmaNext(par, tmp);
}
}
NVDmaKickoff(par);
}
void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (image->depth == 1 && !par->lockup)
nvidiafb_mono_color_expand(info, image);
else
cfb_imageblit(info, image);
}
| linux-master | drivers/video/fbdev/nvidia/nv_accel.c |
/*
* linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
*
* Copyright 2004 Antonino Daplas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/console.h>
#include <linux/backlight.h>
#ifdef CONFIG_BOOTX_TEXT
#include <asm/btext.h>
#endif
#include "nv_local.h"
#include "nv_type.h"
#include "nv_proto.h"
#include "nv_dma.h"
#ifdef CONFIG_FB_NVIDIA_DEBUG
#define NVTRACE printk
#else
#define NVTRACE if (0) printk
#endif
#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
#ifdef CONFIG_FB_NVIDIA_DEBUG
#define assert(expr) \
if (!(expr)) { \
printk( "Assertion failed! %s,%s,%s,line=%d\n",\
#expr,__FILE__,__func__,__LINE__); \
BUG(); \
}
#else
#define assert(expr)
#endif
#define PFX "nvidiafb: "
/* HW cursor parameters */
#define MAX_CURS 32
static const struct pci_device_id nvidiafb_pci_tbl[] = {
{PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
{ 0, }
};
MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
/* command line data, set in nvidiafb_setup() */
static int flatpanel = -1; /* Autodetect later */
static int fpdither = -1;
static int forceCRTC = -1;
static int hwcur = 0;
static int noaccel = 0;
static int noscale = 0;
static int paneltweak = 0;
static int vram = 0;
static int bpp = 8;
static int reverse_i2c;
static bool nomtrr = false;
static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
static char *mode_option = NULL;
static struct fb_fix_screeninfo nvidiafb_fix = {
.type = FB_TYPE_PACKED_PIXELS,
.xpanstep = 8,
.ypanstep = 1,
};
static struct fb_var_screeninfo nvidiafb_default_var = {
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel = 8,
.red = {0, 8, 0},
.green = {0, 8, 0},
.blue = {0, 8, 0},
.transp = {0, 0, 0},
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.pixclock = 39721,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED
};
static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
u16 bg, u16 fg, u32 w, u32 h)
{
u32 *data = (u32 *) data8;
int i, j, k = 0;
u32 b, tmp;
w = (w + 1) & ~1;
for (i = 0; i < h; i++) {
b = *data++;
reverse_order(&b);
for (j = 0; j < w / 2; j++) {
tmp = 0;
#if defined (__BIG_ENDIAN)
tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
b <<= 1;
tmp |= (b & (1 << 31)) ? fg : bg;
b <<= 1;
#else
tmp = (b & 1) ? fg : bg;
b >>= 1;
tmp |= (b & 1) ? fg << 16 : bg << 16;
b >>= 1;
#endif
NV_WR32(&par->CURSOR[k++], 0, tmp);
}
k += (MAX_CURS - w) / 2;
}
}
static void nvidia_write_clut(struct nvidia_par *par,
u8 regnum, u8 red, u8 green, u8 blue)
{
NVWriteDacMask(par, 0xff);
NVWriteDacWriteAddr(par, regnum);
NVWriteDacData(par, red);
NVWriteDacData(par, green);
NVWriteDacData(par, blue);
}
static void nvidia_read_clut(struct nvidia_par *par,
u8 regnum, u8 * red, u8 * green, u8 * blue)
{
NVWriteDacMask(par, 0xff);
NVWriteDacReadAddr(par, regnum);
*red = NVReadDacData(par);
*green = NVReadDacData(par);
*blue = NVReadDacData(par);
}
static int nvidia_panel_tweak(struct nvidia_par *par,
struct _riva_hw_state *state)
{
int tweak = 0;
if (par->paneltweak) {
tweak = par->paneltweak;
} else {
/* Begin flat panel hacks.
* This is unfortunate, but some chips need this register
* tweaked or else you get artifacts where adjacent pixels are
* swapped. There are no hard rules for what to set here so all
* we can do is experiment and apply hacks.
*/
if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
/* At least one NV34 laptop needs this workaround. */
tweak = -1;
}
if ((par->Chipset & 0xfff0) == 0x0310)
tweak = 1;
/* end flat panel hacks */
}
return tweak;
}
static void nvidia_screen_off(struct nvidia_par *par, int on)
{
unsigned char tmp;
if (on) {
/*
* Turn off screen and disable sequencer.
*/
tmp = NVReadSeq(par, 0x01);
NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
} else {
/*
* Reenable sequencer, then turn on screen.
*/
tmp = NVReadSeq(par, 0x01);
NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
NVWriteSeq(par, 0x00, 0x03); /* End Reset */
}
}
static void nvidia_save_vga(struct nvidia_par *par,
struct _riva_hw_state *state)
{
int i;
NVTRACE_ENTER();
NVLockUnlock(par, 0);
NVUnloadStateExt(par, state);
state->misc_output = NVReadMiscOut(par);
for (i = 0; i < NUM_CRT_REGS; i++)
state->crtc[i] = NVReadCrtc(par, i);
for (i = 0; i < NUM_ATC_REGS; i++)
state->attr[i] = NVReadAttr(par, i);
for (i = 0; i < NUM_GRC_REGS; i++)
state->gra[i] = NVReadGr(par, i);
for (i = 0; i < NUM_SEQ_REGS; i++)
state->seq[i] = NVReadSeq(par, i);
NVTRACE_LEAVE();
}
#undef DUMP_REG
static void nvidia_write_regs(struct nvidia_par *par,
struct _riva_hw_state *state)
{
int i;
NVTRACE_ENTER();
NVLoadStateExt(par, state);
NVWriteMiscOut(par, state->misc_output);
for (i = 1; i < NUM_SEQ_REGS; i++) {
#ifdef DUMP_REG
printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
#endif
NVWriteSeq(par, i, state->seq[i]);
}
/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
for (i = 0; i < NUM_CRT_REGS; i++) {
switch (i) {
case 0x19:
case 0x20 ... 0x40:
break;
default:
#ifdef DUMP_REG
printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
#endif
NVWriteCrtc(par, i, state->crtc[i]);
}
}
for (i = 0; i < NUM_GRC_REGS; i++) {
#ifdef DUMP_REG
printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
#endif
NVWriteGr(par, i, state->gra[i]);
}
for (i = 0; i < NUM_ATC_REGS; i++) {
#ifdef DUMP_REG
printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
#endif
NVWriteAttr(par, i, state->attr[i]);
}
NVTRACE_LEAVE();
}
static int nvidia_calc_regs(struct fb_info *info)
{
struct nvidia_par *par = info->par;
struct _riva_hw_state *state = &par->ModeReg;
int i, depth = fb_get_color_depth(&info->var, &info->fix);
int h_display = info->var.xres / 8 - 1;
int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
int h_end = (info->var.xres + info->var.right_margin +
info->var.hsync_len) / 8 - 1;
int h_total = (info->var.xres + info->var.right_margin +
info->var.hsync_len + info->var.left_margin) / 8 - 5;
int h_blank_s = h_display;
int h_blank_e = h_total + 4;
int v_display = info->var.yres - 1;
int v_start = info->var.yres + info->var.lower_margin - 1;
int v_end = (info->var.yres + info->var.lower_margin +
info->var.vsync_len) - 1;
int v_total = (info->var.yres + info->var.lower_margin +
info->var.vsync_len + info->var.upper_margin) - 2;
int v_blank_s = v_display;
int v_blank_e = v_total + 1;
/*
* Set all CRTC values.
*/
if (info->var.vmode & FB_VMODE_INTERLACED)
v_total |= 1;
if (par->FlatPanel == 1) {
v_start = v_total - 3;
v_end = v_total - 2;
v_blank_s = v_start;
h_start = h_total - 5;
h_end = h_total - 2;
h_blank_e = h_total + 4;
}
state->crtc[0x0] = Set8Bits(h_total);
state->crtc[0x1] = Set8Bits(h_display);
state->crtc[0x2] = Set8Bits(h_blank_s);
state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
| SetBit(7);
state->crtc[0x4] = Set8Bits(h_start);
state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
| SetBitField(h_end, 4: 0, 4:0);
state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
| SetBitField(v_display, 8: 8, 1:1)
| SetBitField(v_start, 8: 8, 2:2)
| SetBitField(v_blank_s, 8: 8, 3:3)
| SetBit(4)
| SetBitField(v_total, 9: 9, 5:5)
| SetBitField(v_display, 9: 9, 6:6)
| SetBitField(v_start, 9: 9, 7:7);
state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
| SetBit(6)
| ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
state->crtc[0x10] = Set8Bits(v_start);
state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
state->crtc[0x12] = Set8Bits(v_display);
state->crtc[0x13] = ((info->var.xres_virtual / 8) *
(info->var.bits_per_pixel / 8));
state->crtc[0x15] = Set8Bits(v_blank_s);
state->crtc[0x16] = Set8Bits(v_blank_e);
state->attr[0x10] = 0x01;
if (par->Television)
state->attr[0x11] = 0x00;
state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
| SetBitField(v_blank_s, 10: 10, 3:3)
| SetBitField(v_start, 10: 10, 2:2)
| SetBitField(v_display, 10: 10, 1:1)
| SetBitField(v_total, 10: 10, 0:0);
state->horiz = SetBitField(h_total, 8: 8, 0:0)
| SetBitField(h_display, 8: 8, 1:1)
| SetBitField(h_blank_s, 8: 8, 2:2)
| SetBitField(h_start, 8: 8, 3:3);
state->extra = SetBitField(v_total, 11: 11, 0:0)
| SetBitField(v_display, 11: 11, 2:2)
| SetBitField(v_start, 11: 11, 4:4)
| SetBitField(v_blank_s, 11: 11, 6:6);
if (info->var.vmode & FB_VMODE_INTERLACED) {
h_total = (h_total >> 1) & ~1;
state->interlace = Set8Bits(h_total);
state->horiz |= SetBitField(h_total, 8: 8, 4:4);
} else {
state->interlace = 0xff; /* interlace off */
}
/*
* Calculate the extended registers.
*/
if (depth < 24)
i = depth;
else
i = 32;
if (par->Architecture >= NV_ARCH_10)
par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
par->CursorStart);
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
state->misc_output &= ~0x40;
else
state->misc_output |= 0x40;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
state->misc_output &= ~0x80;
else
state->misc_output |= 0x80;
NVCalcStateExt(par, state, i, info->var.xres_virtual,
info->var.xres, info->var.yres_virtual,
1000000000 / info->var.pixclock, info->var.vmode);
state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
if (par->FlatPanel == 1) {
state->pixel |= (1 << 7);
if (!par->fpScaler || (par->fpWidth <= info->var.xres)
|| (par->fpHeight <= info->var.yres)) {
state->scale |= (1 << 8);
}
if (!par->crtcSync_read) {
state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
par->crtcSync_read = 1;
}
par->PanelTweak = nvidia_panel_tweak(par, state);
}
state->vpll = state->pll;
state->vpll2 = state->pll;
state->vpllB = state->pllB;
state->vpll2B = state->pllB;
VGA_WR08(par->PCIO, 0x03D4, 0x1C);
state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
if (par->CRTCnumber) {
state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
state->crtcOwner = 3;
state->pllsel |= 0x20000800;
state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
if (par->twoStagePLL)
state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
} else if (par->twoHeads) {
state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
state->crtcOwner = 0;
state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
if (par->twoStagePLL)
state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
}
state->cursorConfig = 0x00000100;
if (info->var.vmode & FB_VMODE_DOUBLE)
state->cursorConfig |= (1 << 4);
if (par->alphaCursor) {
if ((par->Chipset & 0x0ff0) != 0x0110)
state->cursorConfig |= 0x04011000;
else
state->cursorConfig |= 0x14011000;
state->general |= (1 << 29);
} else
state->cursorConfig |= 0x02000000;
if (par->twoHeads) {
if ((par->Chipset & 0x0ff0) == 0x0110) {
state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
~0x00010000;
if (par->FPDither)
state->dither |= 0x00010000;
} else {
state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
if (par->FPDither)
state->dither |= 1;
}
}
state->timingH = 0;
state->timingV = 0;
state->displayV = info->var.xres;
return 0;
}
static void nvidia_init_vga(struct fb_info *info)
{
struct nvidia_par *par = info->par;
struct _riva_hw_state *state = &par->ModeReg;
int i;
for (i = 0; i < 0x10; i++)
state->attr[i] = i;
state->attr[0x10] = 0x41;
state->attr[0x11] = 0xff;
state->attr[0x12] = 0x0f;
state->attr[0x13] = 0x00;
state->attr[0x14] = 0x00;
memset(state->crtc, 0x00, NUM_CRT_REGS);
state->crtc[0x0a] = 0x20;
state->crtc[0x17] = 0xe3;
state->crtc[0x18] = 0xff;
state->crtc[0x28] = 0x40;
memset(state->gra, 0x00, NUM_GRC_REGS);
state->gra[0x05] = 0x40;
state->gra[0x06] = 0x05;
state->gra[0x07] = 0x0f;
state->gra[0x08] = 0xff;
state->seq[0x00] = 0x03;
state->seq[0x01] = 0x01;
state->seq[0x02] = 0x0f;
state->seq[0x03] = 0x00;
state->seq[0x04] = 0x0e;
state->misc_output = 0xeb;
}
static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct nvidia_par *par = info->par;
u8 data[MAX_CURS * MAX_CURS / 8];
int i, set = cursor->set;
u16 fg, bg;
if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
return -ENXIO;
NVShowHideCursor(par, 0);
if (par->cursor_reset) {
set = FB_CUR_SETALL;
par->cursor_reset = 0;
}
if (set & FB_CUR_SETSIZE)
memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
if (set & FB_CUR_SETPOS) {
u32 xx, yy, temp;
yy = cursor->image.dy - info->var.yoffset;
xx = cursor->image.dx - info->var.xoffset;
temp = xx & 0xFFFF;
temp |= yy << 16;
NV_WR32(par->PRAMDAC, 0x0000300, temp);
}
if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
u32 bg_idx = cursor->image.bg_color;
u32 fg_idx = cursor->image.fg_color;
u32 s_pitch = (cursor->image.width + 7) >> 3;
u32 d_pitch = MAX_CURS / 8;
u8 *dat = (u8 *) cursor->image.data;
u8 *msk = (u8 *) cursor->mask;
u8 *src;
src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
if (src) {
switch (cursor->rop) {
case ROP_XOR:
for (i = 0; i < s_pitch * cursor->image.height; i++)
src[i] = dat[i] ^ msk[i];
break;
case ROP_COPY:
default:
for (i = 0; i < s_pitch * cursor->image.height; i++)
src[i] = dat[i] & msk[i];
break;
}
fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
cursor->image.height);
bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
((info->cmap.green[bg_idx] & 0xf8) << 2) |
((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
((info->cmap.green[fg_idx] & 0xf8) << 2) |
((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
NVLockUnlock(par, 0);
nvidiafb_load_cursor_image(par, data, bg, fg,
cursor->image.width,
cursor->image.height);
kfree(src);
}
}
if (cursor->enable)
NVShowHideCursor(par, 1);
return 0;
}
static struct fb_ops nvidia_fb_ops;
static int nvidiafb_set_par(struct fb_info *info)
{
struct nvidia_par *par = info->par;
NVTRACE_ENTER();
NVLockUnlock(par, 1);
if (!par->FlatPanel || !par->twoHeads)
par->FPDither = 0;
if (par->FPDither < 0) {
if ((par->Chipset & 0x0ff0) == 0x0110)
par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
& 0x00010000);
else
par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
printk(KERN_INFO PFX "Flat panel dithering %s\n",
par->FPDither ? "enabled" : "disabled");
}
info->fix.visual = (info->var.bits_per_pixel == 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
nvidia_init_vga(info);
nvidia_calc_regs(info);
NVLockUnlock(par, 0);
if (par->twoHeads) {
VGA_WR08(par->PCIO, 0x03D4, 0x44);
VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
NVLockUnlock(par, 0);
}
nvidia_screen_off(par, 1);
nvidia_write_regs(par, &par->ModeReg);
NVSetStartAddress(par, 0);
#if defined (__BIG_ENDIAN)
/* turn on LFB swapping */
{
unsigned char tmp;
VGA_WR08(par->PCIO, 0x3d4, 0x46);
tmp = VGA_RD08(par->PCIO, 0x3d5);
tmp |= (1 << 7);
VGA_WR08(par->PCIO, 0x3d5, tmp);
}
#endif
info->fix.line_length = (info->var.xres_virtual *
info->var.bits_per_pixel) >> 3;
if (info->var.accel_flags) {
nvidia_fb_ops.fb_imageblit = nvidiafb_imageblit;
nvidia_fb_ops.fb_fillrect = nvidiafb_fillrect;
nvidia_fb_ops.fb_copyarea = nvidiafb_copyarea;
nvidia_fb_ops.fb_sync = nvidiafb_sync;
info->pixmap.scan_align = 4;
info->flags &= ~FBINFO_HWACCEL_DISABLED;
info->flags |= FBINFO_READS_FAST;
NVResetGraphics(info);
} else {
nvidia_fb_ops.fb_imageblit = cfb_imageblit;
nvidia_fb_ops.fb_fillrect = cfb_fillrect;
nvidia_fb_ops.fb_copyarea = cfb_copyarea;
nvidia_fb_ops.fb_sync = NULL;
info->pixmap.scan_align = 1;
info->flags |= FBINFO_HWACCEL_DISABLED;
info->flags &= ~FBINFO_READS_FAST;
}
par->cursor_reset = 1;
nvidia_screen_off(par, 0);
#ifdef CONFIG_BOOTX_TEXT
/* Update debug text engine */
btext_update_display(info->fix.smem_start,
info->var.xres, info->var.yres,
info->var.bits_per_pixel, info->fix.line_length);
#endif
NVLockUnlock(par, 0);
NVTRACE_LEAVE();
return 0;
}
static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct nvidia_par *par = info->par;
int i;
NVTRACE_ENTER();
if (regno >= (1 << info->var.green.length))
return -EINVAL;
if (info->var.grayscale) {
/* gray = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
((u32 *) info->pseudo_palette)[regno] =
(regno << info->var.red.offset) |
(regno << info->var.green.offset) |
(regno << info->var.blue.offset);
}
switch (info->var.bits_per_pixel) {
case 8:
/* "transparent" stuff is completely ignored. */
nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
break;
case 16:
if (info->var.green.length == 5) {
for (i = 0; i < 8; i++) {
nvidia_write_clut(par, regno * 8 + i, red >> 8,
green >> 8, blue >> 8);
}
} else {
u8 r, g, b;
if (regno < 32) {
for (i = 0; i < 8; i++) {
nvidia_write_clut(par, regno * 8 + i,
red >> 8, green >> 8,
blue >> 8);
}
}
nvidia_read_clut(par, regno * 4, &r, &g, &b);
for (i = 0; i < 4; i++)
nvidia_write_clut(par, regno * 4 + i, r,
green >> 8, b);
}
break;
case 32:
nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
break;
default:
/* do nothing */
break;
}
NVTRACE_LEAVE();
return 0;
}
static int nvidiafb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct nvidia_par *par = info->par;
int memlen, vramlen, mode_valid = 0;
int pitch, err = 0;
NVTRACE_ENTER();
if (!var->pixclock)
return -EINVAL;
var->transp.offset = 0;
var->transp.length = 0;
var->xres &= ~7;
if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else
var->bits_per_pixel = 32;
switch (var->bits_per_pixel) {
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16:
var->green.length = (var->green.length < 6) ? 5 : 6;
var->red.length = 5;
var->blue.length = 5;
var->transp.length = 6 - var->green.length;
var->blue.offset = 0;
var->green.offset = 5;
var->red.offset = 5 + var->green.length;
var->transp.offset = (5 + var->red.offset) & 15;
break;
case 32: /* RGBA 8888 */
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.length = 8;
var->transp.offset = 24;
break;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
!info->monspecs.dclkmax || !fb_validate_mode(var, info))
mode_valid = 1;
/* calculate modeline if supported by monitor */
if (!mode_valid && info->monspecs.gtf) {
if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
mode_valid = 1;
}
if (!mode_valid) {
const struct fb_videomode *mode;
mode = fb_find_best_mode(var, &info->modelist);
if (mode) {
fb_videomode_to_var(var, mode);
mode_valid = 1;
}
}
if (!mode_valid && info->monspecs.modedb_len)
return -EINVAL;
/*
* If we're on a flat panel, check if the mode is outside of the
* panel dimensions. If so, cap it and try for the next best mode
* before bailing out.
*/
if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
par->fpHeight < var->yres)) {
const struct fb_videomode *mode;
var->xres = par->fpWidth;
var->yres = par->fpHeight;
mode = fb_find_best_mode(var, &info->modelist);
if (!mode) {
printk(KERN_ERR PFX "mode out of range of flat "
"panel dimensions\n");
return -EINVAL;
}
fb_videomode_to_var(var, mode);
}
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
var->xres_virtual = (var->xres_virtual + 63) & ~63;
vramlen = info->screen_size;
pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
memlen = pitch * var->yres_virtual;
if (memlen > vramlen) {
var->yres_virtual = vramlen / pitch;
if (var->yres_virtual < var->yres) {
var->yres_virtual = var->yres;
var->xres_virtual = vramlen / var->yres_virtual;
var->xres_virtual /= var->bits_per_pixel / 8;
var->xres_virtual &= ~63;
pitch = (var->xres_virtual *
var->bits_per_pixel + 7) / 8;
memlen = pitch * var->yres;
if (var->xres_virtual < var->xres) {
printk("nvidiafb: required video memory, "
"%d bytes, for %dx%d-%d (virtual) "
"is out of range\n",
memlen, var->xres_virtual,
var->yres_virtual, var->bits_per_pixel);
err = -ENOMEM;
}
}
}
if (var->accel_flags) {
if (var->yres_virtual > 0x7fff)
var->yres_virtual = 0x7fff;
if (var->xres_virtual > 0x7fff)
var->xres_virtual = 0x7fff;
}
var->xres_virtual &= ~63;
NVTRACE_LEAVE();
return err;
}
static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct nvidia_par *par = info->par;
u32 total;
total = var->yoffset * info->fix.line_length + var->xoffset;
NVSetStartAddress(par, total);
return 0;
}
static int nvidiafb_blank(int blank, struct fb_info *info)
{
struct nvidia_par *par = info->par;
unsigned char tmp, vesa;
tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
NVTRACE_ENTER();
if (blank)
tmp |= 0x20;
switch (blank) {
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
break;
case FB_BLANK_VSYNC_SUSPEND:
vesa |= 0x80;
break;
case FB_BLANK_HSYNC_SUSPEND:
vesa |= 0x40;
break;
case FB_BLANK_POWERDOWN:
vesa |= 0xc0;
break;
}
NVWriteSeq(par, 0x01, tmp);
NVWriteCrtc(par, 0x1a, vesa);
NVTRACE_LEAVE();
return 0;
}
/*
* Because the VGA registers are not mapped linearly in its MMIO space,
* restrict VGA register saving and restore to x86 only, where legacy VGA IO
* access is legal. Consequently, we must also check if the device is the
* primary display.
*/
#ifdef CONFIG_X86
static void save_vga_x86(struct nvidia_par *par)
{
struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
if (res && res->flags & IORESOURCE_ROM_SHADOW) {
memset(&par->vgastate, 0, sizeof(par->vgastate));
par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS |
VGA_SAVE_CMAP;
save_vga(&par->vgastate);
}
}
static void restore_vga_x86(struct nvidia_par *par)
{
struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE];
if (res && res->flags & IORESOURCE_ROM_SHADOW)
restore_vga(&par->vgastate);
}
#else
#define save_vga_x86(x) do {} while (0)
#define restore_vga_x86(x) do {} while (0)
#endif /* X86 */
static int nvidiafb_open(struct fb_info *info, int user)
{
struct nvidia_par *par = info->par;
if (!par->open_count) {
save_vga_x86(par);
nvidia_save_vga(par, &par->initial_state);
}
par->open_count++;
return 0;
}
static int nvidiafb_release(struct fb_info *info, int user)
{
struct nvidia_par *par = info->par;
int err = 0;
if (!par->open_count) {
err = -EINVAL;
goto done;
}
if (par->open_count == 1) {
nvidia_write_regs(par, &par->initial_state);
restore_vga_x86(par);
}
par->open_count--;
done:
return err;
}
static struct fb_ops nvidia_fb_ops = {
.owner = THIS_MODULE,
.fb_open = nvidiafb_open,
.fb_release = nvidiafb_release,
.fb_check_var = nvidiafb_check_var,
.fb_set_par = nvidiafb_set_par,
.fb_setcolreg = nvidiafb_setcolreg,
.fb_pan_display = nvidiafb_pan_display,
.fb_blank = nvidiafb_blank,
.fb_fillrect = nvidiafb_fillrect,
.fb_copyarea = nvidiafb_copyarea,
.fb_imageblit = nvidiafb_imageblit,
.fb_cursor = nvidiafb_cursor,
.fb_sync = nvidiafb_sync,
};
static int nvidiafb_suspend_late(struct device *dev, pm_message_t mesg)
{
struct fb_info *info = dev_get_drvdata(dev);
struct nvidia_par *par = info->par;
if (mesg.event == PM_EVENT_PRETHAW)
mesg.event = PM_EVENT_FREEZE;
console_lock();
par->pm_state = mesg.event;
if (mesg.event & PM_EVENT_SLEEP) {
fb_set_suspend(info, 1);
nvidiafb_blank(FB_BLANK_POWERDOWN, info);
nvidia_write_regs(par, &par->SavedReg);
}
dev->power.power_state = mesg;
console_unlock();
return 0;
}
static int __maybe_unused nvidiafb_suspend(struct device *dev)
{
return nvidiafb_suspend_late(dev, PMSG_SUSPEND);
}
static int __maybe_unused nvidiafb_hibernate(struct device *dev)
{
return nvidiafb_suspend_late(dev, PMSG_HIBERNATE);
}
static int __maybe_unused nvidiafb_freeze(struct device *dev)
{
return nvidiafb_suspend_late(dev, PMSG_FREEZE);
}
static int __maybe_unused nvidiafb_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct nvidia_par *par = info->par;
console_lock();
par->pm_state = PM_EVENT_ON;
nvidiafb_set_par(info);
fb_set_suspend (info, 0);
nvidiafb_blank(FB_BLANK_UNBLANK, info);
console_unlock();
return 0;
}
static const struct dev_pm_ops nvidiafb_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = nvidiafb_suspend,
.resume = nvidiafb_resume,
.freeze = nvidiafb_freeze,
.thaw = nvidiafb_resume,
.poweroff = nvidiafb_hibernate,
.restore = nvidiafb_resume,
#endif /* CONFIG_PM_SLEEP */
};
static int nvidia_set_fbinfo(struct fb_info *info)
{
struct fb_monspecs *specs = &info->monspecs;
struct fb_videomode modedb;
struct nvidia_par *par = info->par;
int lpitch;
NVTRACE_ENTER();
info->flags =
FBINFO_HWACCEL_IMAGEBLIT
| FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_COPYAREA
| FBINFO_HWACCEL_YPAN;
fb_videomode_to_modelist(info->monspecs.modedb,
info->monspecs.modedb_len, &info->modelist);
fb_var_to_videomode(&modedb, &nvidiafb_default_var);
switch (bpp) {
case 0 ... 8:
bpp = 8;
break;
case 9 ... 16:
bpp = 16;
break;
default:
bpp = 32;
break;
}
if (specs->modedb != NULL) {
const struct fb_videomode *mode;
mode = fb_find_best_display(specs, &info->modelist);
fb_videomode_to_var(&nvidiafb_default_var, mode);
nvidiafb_default_var.bits_per_pixel = bpp;
} else if (par->fpWidth && par->fpHeight) {
char buf[16];
memset(buf, 0, 16);
snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
specs->modedb_len, &modedb, bpp);
}
if (mode_option)
fb_find_mode(&nvidiafb_default_var, info, mode_option,
specs->modedb, specs->modedb_len, &modedb, bpp);
info->var = nvidiafb_default_var;
info->fix.visual = (info->var.bits_per_pixel == 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
info->pseudo_palette = par->pseudo_palette;
fb_alloc_cmap(&info->cmap, 256, 0);
fb_destroy_modedb(info->monspecs.modedb);
info->monspecs.modedb = NULL;
/* maximize virtual vertical length */
lpitch = info->var.xres_virtual *
((info->var.bits_per_pixel + 7) >> 3);
info->var.yres_virtual = info->screen_size / lpitch;
info->pixmap.scan_align = 4;
info->pixmap.buf_align = 4;
info->pixmap.access_align = 32;
info->pixmap.size = 8 * 1024;
info->pixmap.flags = FB_PIXMAP_SYSTEM;
if (!hwcur)
nvidia_fb_ops.fb_cursor = NULL;
info->var.accel_flags = (!noaccel);
switch (par->Architecture) {
case NV_ARCH_04:
info->fix.accel = FB_ACCEL_NV4;
break;
case NV_ARCH_10:
info->fix.accel = FB_ACCEL_NV_10;
break;
case NV_ARCH_20:
info->fix.accel = FB_ACCEL_NV_20;
break;
case NV_ARCH_30:
info->fix.accel = FB_ACCEL_NV_30;
break;
case NV_ARCH_40:
info->fix.accel = FB_ACCEL_NV_40;
break;
}
NVTRACE_LEAVE();
return nvidiafb_check_var(&info->var, info);
}
static u32 nvidia_get_chipset(struct pci_dev *pci_dev,
volatile u32 __iomem *REGS)
{
u32 id = (pci_dev->vendor << 16) | pci_dev->device;
printk(KERN_INFO PFX "Device ID: %x \n", id);
if ((id & 0xfff0) == 0x00f0 ||
(id & 0xfff0) == 0x02e0) {
/* pci-e */
id = NV_RD32(REGS, 0x1800);
if ((id & 0x0000ffff) == 0x000010DE)
id = 0x10DE0000 | (id >> 16);
else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
((id >> 8) & 0x000000ff);
printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
}
return id;
}
static u32 nvidia_get_arch(u32 Chipset)
{
u32 arch = 0;
switch (Chipset & 0x0ff0) {
case 0x0100: /* GeForce 256 */
case 0x0110: /* GeForce2 MX */
case 0x0150: /* GeForce2 */
case 0x0170: /* GeForce4 MX */
case 0x0180: /* GeForce4 MX (8x AGP) */
case 0x01A0: /* nForce */
case 0x01F0: /* nForce2 */
arch = NV_ARCH_10;
break;
case 0x0200: /* GeForce3 */
case 0x0250: /* GeForce4 Ti */
case 0x0280: /* GeForce4 Ti (8x AGP) */
arch = NV_ARCH_20;
break;
case 0x0300: /* GeForceFX 5800 */
case 0x0310: /* GeForceFX 5600 */
case 0x0320: /* GeForceFX 5200 */
case 0x0330: /* GeForceFX 5900 */
case 0x0340: /* GeForceFX 5700 */
arch = NV_ARCH_30;
break;
case 0x0040: /* GeForce 6800 */
case 0x00C0: /* GeForce 6800 */
case 0x0120: /* GeForce 6800 */
case 0x0140: /* GeForce 6600 */
case 0x0160: /* GeForce 6200 */
case 0x01D0: /* GeForce 7200, 7300, 7400 */
case 0x0090: /* GeForce 7800 */
case 0x0210: /* GeForce 6800 */
case 0x0220: /* GeForce 6200 */
case 0x0240: /* GeForce 6100 */
case 0x0290: /* GeForce 7900 */
case 0x0390: /* GeForce 7600 */
case 0x03D0:
arch = NV_ARCH_40;
break;
case 0x0020: /* TNT, TNT2 */
arch = NV_ARCH_04;
break;
default: /* unknown architecture */
break;
}
return arch;
}
static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
{
struct nvidia_par *par;
struct fb_info *info;
unsigned short cmd;
int ret;
volatile u32 __iomem *REGS;
int Chipset;
u32 Architecture;
NVTRACE_ENTER();
assert(pd != NULL);
if (pci_enable_device(pd)) {
printk(KERN_ERR PFX "cannot enable PCI device\n");
return -ENODEV;
}
/* enable IO and mem if not already done */
pci_read_config_word(pd, PCI_COMMAND, &cmd);
cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
pci_write_config_word(pd, PCI_COMMAND, cmd);
nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
if (!REGS) {
printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
return -ENODEV;
}
Chipset = nvidia_get_chipset(pd, REGS);
Architecture = nvidia_get_arch(Chipset);
if (Architecture == 0) {
printk(KERN_ERR PFX "unknown NV_ARCH\n");
goto err_out;
}
ret = aperture_remove_conflicting_pci_devices(pd, "nvidiafb");
if (ret)
goto err_out;
info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
if (!info)
goto err_out;
par = info->par;
par->pci_dev = pd;
info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
if (info->pixmap.addr == NULL)
goto err_out_kfree;
if (pci_request_regions(pd, "nvidiafb")) {
printk(KERN_ERR PFX "cannot request PCI regions\n");
goto err_out_enable;
}
par->FlatPanel = flatpanel;
if (flatpanel == 1)
printk(KERN_INFO PFX "flatpanel support enabled\n");
par->FPDither = fpdither;
par->CRTCnumber = forceCRTC;
par->FpScale = (!noscale);
par->paneltweak = paneltweak;
par->reverse_i2c = reverse_i2c;
nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
par->REGS = REGS;
par->Chipset = Chipset;
par->Architecture = Architecture;
sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
if (NVCommonSetup(info))
goto err_out_free_base0;
par->FbAddress = nvidiafb_fix.smem_start;
par->FbMapSize = par->RamAmountKBytes * 1024;
if (vram && vram * 1024 * 1024 < par->FbMapSize)
par->FbMapSize = vram * 1024 * 1024;
/* Limit amount of vram to 64 MB */
if (par->FbMapSize > 64 * 1024 * 1024)
par->FbMapSize = 64 * 1024 * 1024;
if(par->Architecture >= NV_ARCH_40)
par->FbUsableSize = par->FbMapSize - (560 * 1024);
else
par->FbUsableSize = par->FbMapSize - (128 * 1024);
par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
16 * 1024;
par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
par->CursorStart = par->FbUsableSize + (32 * 1024);
info->screen_base = ioremap_wc(nvidiafb_fix.smem_start,
par->FbMapSize);
info->screen_size = par->FbUsableSize;
nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
if (!info->screen_base) {
printk(KERN_ERR PFX "cannot ioremap FB base\n");
goto err_out_free_base1;
}
par->FbStart = info->screen_base;
if (!nomtrr)
par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start,
par->RamAmountKBytes * 1024);
info->fbops = &nvidia_fb_ops;
info->fix = nvidiafb_fix;
if (nvidia_set_fbinfo(info) < 0) {
printk(KERN_ERR PFX "error setting initial video mode\n");
goto err_out_iounmap_fb;
}
nvidia_save_vga(par, &par->SavedReg);
pci_set_drvdata(pd, info);
if (register_framebuffer(info) < 0) {
printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
goto err_out_iounmap_fb;
}
if (backlight)
nvidia_bl_init(par);
printk(KERN_INFO PFX
"PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
info->fix.id,
par->FbMapSize / (1024 * 1024), info->fix.smem_start);
NVTRACE_LEAVE();
return 0;
err_out_iounmap_fb:
iounmap(info->screen_base);
err_out_free_base1:
fb_destroy_modedb(info->monspecs.modedb);
nvidia_delete_i2c_busses(par);
err_out_free_base0:
pci_release_regions(pd);
err_out_enable:
kfree(info->pixmap.addr);
err_out_kfree:
framebuffer_release(info);
err_out:
iounmap(REGS);
return -ENODEV;
}
static void nvidiafb_remove(struct pci_dev *pd)
{
struct fb_info *info = pci_get_drvdata(pd);
struct nvidia_par *par = info->par;
NVTRACE_ENTER();
nvidia_bl_exit(par);
unregister_framebuffer(info);
arch_phys_wc_del(par->wc_cookie);
iounmap(info->screen_base);
fb_destroy_modedb(info->monspecs.modedb);
nvidia_delete_i2c_busses(par);
iounmap(par->REGS);
pci_release_regions(pd);
kfree(info->pixmap.addr);
framebuffer_release(info);
NVTRACE_LEAVE();
}
/* ------------------------------------------------------------------------- *
*
* initialization
*
* ------------------------------------------------------------------------- */
#ifndef MODULE
static int nvidiafb_setup(char *options)
{
char *this_opt;
NVTRACE_ENTER();
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "forceCRTC", 9)) {
char *p;
p = this_opt + 9;
if (!*p || !*(++p))
continue;
forceCRTC = *p - '0';
if (forceCRTC < 0 || forceCRTC > 1)
forceCRTC = -1;
} else if (!strncmp(this_opt, "flatpanel", 9)) {
flatpanel = 1;
} else if (!strncmp(this_opt, "hwcur", 5)) {
hwcur = 1;
} else if (!strncmp(this_opt, "noaccel", 6)) {
noaccel = 1;
} else if (!strncmp(this_opt, "noscale", 7)) {
noscale = 1;
} else if (!strncmp(this_opt, "reverse_i2c", 11)) {
reverse_i2c = 1;
} else if (!strncmp(this_opt, "paneltweak:", 11)) {
paneltweak = simple_strtoul(this_opt+11, NULL, 0);
} else if (!strncmp(this_opt, "vram:", 5)) {
vram = simple_strtoul(this_opt+5, NULL, 0);
} else if (!strncmp(this_opt, "backlight:", 10)) {
backlight = simple_strtoul(this_opt+10, NULL, 0);
} else if (!strncmp(this_opt, "nomtrr", 6)) {
nomtrr = true;
} else if (!strncmp(this_opt, "fpdither:", 9)) {
fpdither = simple_strtol(this_opt+9, NULL, 0);
} else if (!strncmp(this_opt, "bpp:", 4)) {
bpp = simple_strtoul(this_opt+4, NULL, 0);
} else
mode_option = this_opt;
}
NVTRACE_LEAVE();
return 0;
}
#endif /* !MODULE */
static struct pci_driver nvidiafb_driver = {
.name = "nvidiafb",
.id_table = nvidiafb_pci_tbl,
.probe = nvidiafb_probe,
.driver.pm = &nvidiafb_pm_ops,
.remove = nvidiafb_remove,
};
/* ------------------------------------------------------------------------- *
*
* modularization
*
* ------------------------------------------------------------------------- */
static int nvidiafb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("nvidiafb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("nvidiafb", &option))
return -ENODEV;
nvidiafb_setup(option);
#endif
return pci_register_driver(&nvidiafb_driver);
}
module_init(nvidiafb_init);
static void __exit nvidiafb_exit(void)
{
pci_unregister_driver(&nvidiafb_driver);
}
module_exit(nvidiafb_exit);
module_param(flatpanel, int, 0);
MODULE_PARM_DESC(flatpanel,
"Enables experimental flat panel support for some chipsets. "
"(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
module_param(fpdither, int, 0);
MODULE_PARM_DESC(fpdither,
"Enables dithering of flat panel for 6 bits panels. "
"(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
module_param(hwcur, int, 0);
MODULE_PARM_DESC(hwcur,
"Enables hardware cursor implementation. (0 or 1=enabled) "
"(default=0)");
module_param(noaccel, int, 0);
MODULE_PARM_DESC(noaccel,
"Disables hardware acceleration. (0 or 1=disable) "
"(default=0)");
module_param(noscale, int, 0);
MODULE_PARM_DESC(noscale,
"Disables screen scaling. (0 or 1=disable) "
"(default=0, do scaling)");
module_param(paneltweak, int, 0);
MODULE_PARM_DESC(paneltweak,
"Tweak display settings for flatpanels. "
"(default=0, no tweaks)");
module_param(forceCRTC, int, 0);
MODULE_PARM_DESC(forceCRTC,
"Forces usage of a particular CRTC in case autodetection "
"fails. (0 or 1) (default=autodetect)");
module_param(vram, int, 0);
MODULE_PARM_DESC(vram,
"amount of framebuffer memory to remap in MiB"
"(default=0 - remap entire memory)");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Specify initial video mode");
module_param(bpp, int, 0);
MODULE_PARM_DESC(bpp, "pixel width in bits"
"(default=8)");
module_param(reverse_i2c, int, 0);
MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus");
module_param(nomtrr, bool, false);
MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
"(default=0)");
MODULE_AUTHOR("Antonino Daplas");
MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/nvidia/nvidia.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* driver for VIA VT1632 DVI Transmitter
*/
#include <linux/slab.h>
#include "via_aux.h"
static const char *name = "VT1632 DVI Transmitter";
static void probe(struct via_aux_bus *bus, u8 addr)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = addr,
.name = name};
/* check vendor id and device id */
const u8 id[] = {0x06, 0x11, 0x92, 0x31}, len = ARRAY_SIZE(id);
u8 tmp[ARRAY_SIZE(id)];
if (!via_aux_read(&drv, 0x00, tmp, len) || memcmp(id, tmp, len))
return;
printk(KERN_INFO "viafb: Found %s at address 0x%x\n", name, addr);
via_aux_add(&drv);
}
void via_aux_vt1632_probe(struct via_aux_bus *bus)
{
u8 i;
for (i = 0x08; i <= 0x0F; i++)
probe(bus, i);
}
| linux-master | drivers/video/fbdev/via/via_aux_vt1632.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* generic EDID driver
*/
#include <linux/slab.h>
#include <linux/fb.h>
#include "via_aux.h"
#include "../edid.h"
static const char *name = "EDID";
static void query_edid(struct via_aux_drv *drv)
{
struct fb_monspecs *spec = drv->data;
unsigned char edid[EDID_LENGTH];
bool valid = false;
if (spec) {
fb_destroy_modedb(spec->modedb);
} else {
spec = kmalloc(sizeof(*spec), GFP_KERNEL);
if (!spec)
return;
}
spec->version = spec->revision = 0;
if (via_aux_read(drv, 0x00, edid, EDID_LENGTH)) {
fb_edid_to_monspecs(edid, spec);
valid = spec->version || spec->revision;
}
if (!valid) {
kfree(spec);
spec = NULL;
} else
printk(KERN_DEBUG "EDID: %s %s\n", spec->manufacturer, spec->monitor);
drv->data = spec;
}
static const struct fb_videomode *get_preferred_mode(struct via_aux_drv *drv)
{
struct fb_monspecs *spec = drv->data;
int i;
if (!spec || !spec->modedb || !(spec->misc & FB_MISC_1ST_DETAIL))
return NULL;
for (i = 0; i < spec->modedb_len; i++) {
if (spec->modedb[i].flag & FB_MODE_IS_FIRST &&
spec->modedb[i].flag & FB_MODE_IS_DETAILED)
return &spec->modedb[i];
}
return NULL;
}
static void cleanup(struct via_aux_drv *drv)
{
struct fb_monspecs *spec = drv->data;
if (spec)
fb_destroy_modedb(spec->modedb);
}
void via_aux_edid_probe(struct via_aux_bus *bus)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = 0x50,
.name = name,
.cleanup = cleanup,
.get_preferred_mode = get_preferred_mode};
query_edid(&drv);
/* as EDID devices can be connected/disconnected just add the driver */
via_aux_add(&drv);
}
| linux-master | drivers/video/fbdev/via/via_aux_edid.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* driver for VIA VT1636 LVDS Transmitter
*/
#include <linux/slab.h>
#include "via_aux.h"
static const char *name = "VT1636 LVDS Transmitter";
void via_aux_vt1636_probe(struct via_aux_bus *bus)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = 0x40,
.name = name};
/* check vendor id and device id */
const u8 id[] = {0x06, 0x11, 0x45, 0x33}, len = ARRAY_SIZE(id);
u8 tmp[ARRAY_SIZE(id)];
if (!via_aux_read(&drv, 0x00, tmp, len) || memcmp(id, tmp, len))
return;
printk(KERN_INFO "viafb: Found %s\n", name);
via_aux_add(&drv);
}
| linux-master | drivers/video/fbdev/via/via_aux_vt1636.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* clock and PLL management functions
*/
#include <linux/kernel.h>
#include <linux/via-core.h>
#include "via_clock.h"
#include "global.h"
#include "debug.h"
static const char *via_slap = "Please slap VIA Technologies to motivate them "
"releasing full documentation for your platform!\n";
static inline u32 cle266_encode_pll(struct via_pll_config pll)
{
return (pll.multiplier << 8)
| (pll.rshift << 6)
| pll.divisor;
}
static inline u32 k800_encode_pll(struct via_pll_config pll)
{
return ((pll.divisor - 2) << 16)
| (pll.rshift << 10)
| (pll.multiplier - 2);
}
static inline u32 vx855_encode_pll(struct via_pll_config pll)
{
return (pll.divisor << 16)
| (pll.rshift << 10)
| pll.multiplier;
}
static inline void cle266_set_primary_pll_encoded(u32 data)
{
via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
via_write_reg(VIASR, 0x46, data & 0xFF);
via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
}
static inline void k800_set_primary_pll_encoded(u32 data)
{
via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
via_write_reg(VIASR, 0x44, data & 0xFF);
via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
}
static inline void cle266_set_secondary_pll_encoded(u32 data)
{
via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
via_write_reg(VIASR, 0x44, data & 0xFF);
via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
}
static inline void k800_set_secondary_pll_encoded(u32 data)
{
via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
via_write_reg(VIASR, 0x4A, data & 0xFF);
via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
}
static inline void set_engine_pll_encoded(u32 data)
{
via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */
via_write_reg(VIASR, 0x47, data & 0xFF);
via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF);
via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF);
via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */
}
static void cle266_set_primary_pll(struct via_pll_config config)
{
cle266_set_primary_pll_encoded(cle266_encode_pll(config));
}
static void k800_set_primary_pll(struct via_pll_config config)
{
k800_set_primary_pll_encoded(k800_encode_pll(config));
}
static void vx855_set_primary_pll(struct via_pll_config config)
{
k800_set_primary_pll_encoded(vx855_encode_pll(config));
}
static void cle266_set_secondary_pll(struct via_pll_config config)
{
cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
}
static void k800_set_secondary_pll(struct via_pll_config config)
{
k800_set_secondary_pll_encoded(k800_encode_pll(config));
}
static void vx855_set_secondary_pll(struct via_pll_config config)
{
k800_set_secondary_pll_encoded(vx855_encode_pll(config));
}
static void k800_set_engine_pll(struct via_pll_config config)
{
set_engine_pll_encoded(k800_encode_pll(config));
}
static void vx855_set_engine_pll(struct via_pll_config config)
{
set_engine_pll_encoded(vx855_encode_pll(config));
}
static void set_primary_pll_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x20;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x2D, value, 0x30);
}
static void set_secondary_pll_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x08;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
}
static void set_engine_pll_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x02;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x2D, value, 0x03);
}
static void set_primary_clock_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x20;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x1B, value, 0x30);
}
static void set_secondary_clock_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x80;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
}
static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
{
u8 data = 0;
switch (source) {
case VIA_CLKSRC_X1:
data = 0x00;
break;
case VIA_CLKSRC_TVX1:
data = 0x02;
break;
case VIA_CLKSRC_TVPLL:
data = 0x04; /* 0x06 should be the same */
break;
case VIA_CLKSRC_DVP1TVCLKR:
data = 0x0A;
break;
case VIA_CLKSRC_CAP0:
data = 0xC;
break;
case VIA_CLKSRC_CAP1:
data = 0x0E;
break;
}
if (!use_pll)
data |= 1;
return data;
}
static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
{
u8 data = set_clock_source_common(source, use_pll) << 4;
via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
}
static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
{
u8 data = set_clock_source_common(source, use_pll);
via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
}
static void dummy_set_clock_state(u8 state)
{
printk(KERN_INFO "Using undocumented set clock state.\n%s", via_slap);
}
static void dummy_set_clock_source(enum via_clksrc source, bool use_pll)
{
printk(KERN_INFO "Using undocumented set clock source.\n%s", via_slap);
}
static void dummy_set_pll_state(u8 state)
{
printk(KERN_INFO "Using undocumented set PLL state.\n%s", via_slap);
}
static void dummy_set_pll(struct via_pll_config config)
{
printk(KERN_INFO "Using undocumented set PLL.\n%s", via_slap);
}
static void noop_set_clock_state(u8 state)
{
}
void via_clock_init(struct via_clock *clock, int gfx_chip)
{
switch (gfx_chip) {
case UNICHROME_CLE266:
case UNICHROME_K400:
clock->set_primary_clock_state = dummy_set_clock_state;
clock->set_primary_clock_source = dummy_set_clock_source;
clock->set_primary_pll_state = dummy_set_pll_state;
clock->set_primary_pll = cle266_set_primary_pll;
clock->set_secondary_clock_state = dummy_set_clock_state;
clock->set_secondary_clock_source = dummy_set_clock_source;
clock->set_secondary_pll_state = dummy_set_pll_state;
clock->set_secondary_pll = cle266_set_secondary_pll;
clock->set_engine_pll_state = dummy_set_pll_state;
clock->set_engine_pll = dummy_set_pll;
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_CN750:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
clock->set_primary_clock_state = set_primary_clock_state;
clock->set_primary_clock_source = set_primary_clock_source;
clock->set_primary_pll_state = set_primary_pll_state;
clock->set_primary_pll = k800_set_primary_pll;
clock->set_secondary_clock_state = set_secondary_clock_state;
clock->set_secondary_clock_source = set_secondary_clock_source;
clock->set_secondary_pll_state = set_secondary_pll_state;
clock->set_secondary_pll = k800_set_secondary_pll;
clock->set_engine_pll_state = set_engine_pll_state;
clock->set_engine_pll = k800_set_engine_pll;
break;
case UNICHROME_VX855:
case UNICHROME_VX900:
clock->set_primary_clock_state = set_primary_clock_state;
clock->set_primary_clock_source = set_primary_clock_source;
clock->set_primary_pll_state = set_primary_pll_state;
clock->set_primary_pll = vx855_set_primary_pll;
clock->set_secondary_clock_state = set_secondary_clock_state;
clock->set_secondary_clock_source = set_secondary_clock_source;
clock->set_secondary_pll_state = set_secondary_pll_state;
clock->set_secondary_pll = vx855_set_secondary_pll;
clock->set_engine_pll_state = set_engine_pll_state;
clock->set_engine_pll = vx855_set_engine_pll;
break;
}
if (machine_is_olpc()) {
/* The OLPC XO-1.5 cannot suspend/resume reliably if the
* IGA1/IGA2 clocks are set as on or off (memory rot
* occasionally happens during suspend under such
* configurations).
*
* The only known stable scenario is to leave this bits as-is,
* which in their default states are documented to enable the
* clock only when it is needed.
*/
clock->set_primary_clock_state = noop_set_clock_state;
clock->set_secondary_clock_state = noop_set_clock_state;
}
}
| linux-master | drivers/video/fbdev/via/via_clock.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/via-core.h>
#include "global.h"
#include "via_clock.h"
static struct pll_limit cle266_pll_limits[] = {
{19, 19, 4, 0},
{26, 102, 5, 0},
{53, 112, 6, 0},
{41, 100, 7, 0},
{83, 108, 8, 0},
{87, 118, 9, 0},
{95, 115, 12, 0},
{108, 108, 13, 0},
{83, 83, 17, 0},
{67, 98, 20, 0},
{121, 121, 24, 0},
{99, 99, 29, 0},
{33, 33, 3, 1},
{15, 23, 4, 1},
{37, 121, 5, 1},
{82, 82, 6, 1},
{31, 84, 7, 1},
{83, 83, 8, 1},
{76, 127, 9, 1},
{33, 121, 4, 2},
{91, 118, 5, 2},
{83, 109, 6, 2},
{90, 90, 7, 2},
{93, 93, 2, 3},
{53, 53, 3, 3},
{73, 117, 4, 3},
{101, 127, 5, 3},
{99, 99, 7, 3}
};
static struct pll_limit k800_pll_limits[] = {
{22, 22, 2, 0},
{28, 28, 3, 0},
{81, 112, 3, 1},
{86, 166, 4, 1},
{109, 153, 5, 1},
{66, 116, 3, 2},
{93, 137, 4, 2},
{117, 208, 5, 2},
{30, 30, 2, 3},
{69, 125, 3, 3},
{89, 161, 4, 3},
{121, 208, 5, 3},
{66, 66, 2, 4},
{85, 85, 3, 4},
{141, 161, 4, 4},
{177, 177, 5, 4}
};
static struct pll_limit cx700_pll_limits[] = {
{98, 98, 3, 1},
{86, 86, 4, 1},
{109, 208, 5, 1},
{68, 68, 2, 2},
{95, 116, 3, 2},
{93, 166, 4, 2},
{110, 206, 5, 2},
{174, 174, 7, 2},
{82, 109, 3, 3},
{117, 161, 4, 3},
{112, 208, 5, 3},
{141, 202, 5, 4}
};
static struct pll_limit vx855_pll_limits[] = {
{86, 86, 4, 1},
{108, 208, 5, 1},
{110, 208, 5, 2},
{83, 112, 3, 3},
{103, 161, 4, 3},
{112, 209, 5, 3},
{142, 161, 4, 4},
{141, 176, 5, 4}
};
/* according to VIA Technologies these values are based on experiment */
static struct io_reg scaling_parameters[] = {
{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
};
static struct io_reg common_vga[] = {
{VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8)
[1] vertical display end (bit 8)
[2] vertical retrace start (bit 8)
[3] start vertical blanking (bit 8)
[4] line compare (bit 8)
[5] vertical total (bit 9)
[6] vertical display end (bit 9)
[7] vertical retrace start (bit 9) */
{VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan
[5-6] byte panning */
{VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line
[5] start vertical blanking (bit 9)
[6] line compare (bit 9)
[7] scan doubling */
{VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start
[5] cursor disable */
{VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end
[5-6] cursor skew */
{VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */
{VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */
{VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end
[6] memory refresh bandwidth
[7] CRTC register protect enable */
{VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location
[5] divide memory address clock by 4
[6] double word addressing */
{VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14
[2] divide scan line clock by 2
[3] divide memory address clock by 2
[5] address wrap
[6] byte mode select
[7] sync enable */
{VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */
};
static struct fifo_depth_select display_fifo_depth_reg = {
/* IGA1 FIFO Depth_Select */
{IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
/* IGA2 FIFO Depth_Select */
{IGA2_FIFO_DEPTH_SELECT_REG_NUM,
{{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
};
static struct fifo_threshold_select fifo_threshold_select_reg = {
/* IGA1 FIFO Threshold Select */
{IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
/* IGA2 FIFO Threshold Select */
{IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
};
static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
/* IGA1 FIFO High Threshold Select */
{IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
/* IGA2 FIFO High Threshold Select */
{IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
};
static struct display_queue_expire_num display_queue_expire_num_reg = {
/* IGA1 Display Queue Expire Num */
{IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
/* IGA2 Display Queue Expire Num */
{IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
};
/* Definition Fetch Count Registers*/
static struct fetch_count fetch_count_reg = {
/* IGA1 Fetch Count Register */
{IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
/* IGA2 Fetch Count Register */
{IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
};
static struct rgbLUT palLUT_table[] = {
/* {R,G,B} */
/* Index 0x00~0x03 */
{0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
0x2A,
0x2A},
/* Index 0x04~0x07 */
{0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
0x2A,
0x2A},
/* Index 0x08~0x0B */
{0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
0x3F,
0x3F},
/* Index 0x0C~0x0F */
{0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
0x3F,
0x3F},
/* Index 0x10~0x13 */
{0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
0x0B,
0x0B},
/* Index 0x14~0x17 */
{0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
0x18,
0x18},
/* Index 0x18~0x1B */
{0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
0x28,
0x28},
/* Index 0x1C~0x1F */
{0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
0x3F,
0x3F},
/* Index 0x20~0x23 */
{0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
0x00,
0x3F},
/* Index 0x24~0x27 */
{0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
0x00,
0x10},
/* Index 0x28~0x2B */
{0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
0x2F,
0x00},
/* Index 0x2C~0x2F */
{0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
0x3F,
0x00},
/* Index 0x30~0x33 */
{0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
0x3F,
0x2F},
/* Index 0x34~0x37 */
{0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
0x10,
0x3F},
/* Index 0x38~0x3B */
{0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
0x1F,
0x3F},
/* Index 0x3C~0x3F */
{0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
0x1F,
0x27},
/* Index 0x40~0x43 */
{0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
0x3F,
0x1F},
/* Index 0x44~0x47 */
{0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
0x3F,
0x1F},
/* Index 0x48~0x4B */
{0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
0x3F,
0x37},
/* Index 0x4C~0x4F */
{0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
0x27,
0x3F},
/* Index 0x50~0x53 */
{0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
0x2D,
0x3F},
/* Index 0x54~0x57 */
{0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
0x2D,
0x31},
/* Index 0x58~0x5B */
{0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
0x3A,
0x2D},
/* Index 0x5C~0x5F */
{0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
0x3F,
0x2D},
/* Index 0x60~0x63 */
{0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
0x3F,
0x3A},
/* Index 0x64~0x67 */
{0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
0x31,
0x3F},
/* Index 0x68~0x6B */
{0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
0x00,
0x1C},
/* Index 0x6C~0x6F */
{0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
0x00,
0x07},
/* Index 0x70~0x73 */
{0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
0x15,
0x00},
/* Index 0x74~0x77 */
{0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
0x1C,
0x00},
/* Index 0x78~0x7B */
{0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
0x1C,
0x15},
/* Index 0x7C~0x7F */
{0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
0x07,
0x1C},
/* Index 0x80~0x83 */
{0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
0x0E,
0x1C},
/* Index 0x84~0x87 */
{0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
0x0E,
0x11},
/* Index 0x88~0x8B */
{0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
0x18,
0x0E},
/* Index 0x8C~0x8F */
{0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
0x1C,
0x0E},
/* Index 0x90~0x93 */
{0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
0x1C,
0x18},
/* Index 0x94~0x97 */
{0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
0x11,
0x1C},
/* Index 0x98~0x9B */
{0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
0x14,
0x1C},
/* Index 0x9C~0x9F */
{0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
0x14,
0x16},
/* Index 0xA0~0xA3 */
{0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
0x1A,
0x14},
/* Index 0xA4~0xA7 */
{0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
0x1C,
0x14},
/* Index 0xA8~0xAB */
{0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
0x1C,
0x1A},
/* Index 0xAC~0xAF */
{0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
0x16,
0x1C},
/* Index 0xB0~0xB3 */
{0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
0x00,
0x10},
/* Index 0xB4~0xB7 */
{0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
0x00,
0x04},
/* Index 0xB8~0xBB */
{0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
0x0C,
0x00},
/* Index 0xBC~0xBF */
{0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
0x10,
0x00},
/* Index 0xC0~0xC3 */
{0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
0x10,
0x0C},
/* Index 0xC4~0xC7 */
{0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
0x04,
0x10},
/* Index 0xC8~0xCB */
{0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
0x08,
0x10},
/* Index 0xCC~0xCF */
{0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
0x08,
0x0A},
/* Index 0xD0~0xD3 */
{0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
0x0E,
0x08},
/* Index 0xD4~0xD7 */
{0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
0x10,
0x08},
/* Index 0xD8~0xDB */
{0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
0x10,
0x0E},
/* Index 0xDC~0xDF */
{0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
0x0A,
0x10},
/* Index 0xE0~0xE3 */
{0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
0x0B,
0x10},
/* Index 0xE4~0xE7 */
{0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
0x0B,
0x0C},
/* Index 0xE8~0xEB */
{0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
0x0F,
0x0B},
/* Index 0xEC~0xEF */
{0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
0x10,
0x0B},
/* Index 0xF0~0xF3 */
{0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
0x10,
0x0F},
/* Index 0xF4~0xF7 */
{0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
0x0C,
0x10},
/* Index 0xF8~0xFB */
{0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
0x00,
0x00},
/* Index 0xFC~0xFF */
{0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
0x00,
0x00}
};
static struct via_device_mapping device_mapping[] = {
{VIA_LDVP0, "LDVP0"},
{VIA_LDVP1, "LDVP1"},
{VIA_DVP0, "DVP0"},
{VIA_CRT, "CRT"},
{VIA_DVP1, "DVP1"},
{VIA_LVDS1, "LVDS1"},
{VIA_LVDS2, "LVDS2"}
};
/* structure with function pointers to support clock control */
static struct via_clock clock;
static void load_fix_bit_crtc_reg(void);
static void init_gfx_chip_info(int chip_type);
static void init_tmds_chip_info(void);
static void init_lvds_chip_info(void);
static void device_screen_off(void);
static void device_screen_on(void);
static void set_display_channel(void);
static void device_off(void);
static void device_on(void);
static void enable_second_display_channel(void);
static void disable_second_display_channel(void);
void viafb_lock_crt(void)
{
viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
}
void viafb_unlock_crt(void)
{
viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
}
static void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
{
outb(index, LUT_INDEX_WRITE);
outb(r, LUT_DATA);
outb(g, LUT_DATA);
outb(b, LUT_DATA);
}
static u32 get_dvi_devices(int output_interface)
{
switch (output_interface) {
case INTERFACE_DVP0:
return VIA_DVP0 | VIA_LDVP0;
case INTERFACE_DVP1:
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
return VIA_LDVP1;
else
return VIA_DVP1;
case INTERFACE_DFP_HIGH:
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
return 0;
else
return VIA_LVDS2 | VIA_DVP0;
case INTERFACE_DFP_LOW:
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
return 0;
else
return VIA_DVP1 | VIA_LVDS1;
case INTERFACE_TMDS:
return VIA_LVDS1;
}
return 0;
}
static u32 get_lcd_devices(int output_interface)
{
switch (output_interface) {
case INTERFACE_DVP0:
return VIA_DVP0;
case INTERFACE_DVP1:
return VIA_DVP1;
case INTERFACE_DFP_HIGH:
return VIA_LVDS2 | VIA_DVP0;
case INTERFACE_DFP_LOW:
return VIA_LVDS1 | VIA_DVP1;
case INTERFACE_DFP:
return VIA_LVDS1 | VIA_LVDS2;
case INTERFACE_LVDS0:
case INTERFACE_LVDS0LVDS1:
return VIA_LVDS1;
case INTERFACE_LVDS1:
return VIA_LVDS2;
}
return 0;
}
/*Set IGA path for each device*/
void viafb_set_iga_path(void)
{
int crt_iga_path = 0;
if (viafb_SAMM_ON == 1) {
if (viafb_CRT_ON) {
if (viafb_primary_dev == CRT_Device)
crt_iga_path = IGA1;
else
crt_iga_path = IGA2;
}
if (viafb_DVI_ON) {
if (viafb_primary_dev == DVI_Device)
viaparinfo->tmds_setting_info->iga_path = IGA1;
else
viaparinfo->tmds_setting_info->iga_path = IGA2;
}
if (viafb_LCD_ON) {
if (viafb_primary_dev == LCD_Device) {
if (viafb_dual_fb &&
(viaparinfo->chip_info->gfx_chip_name ==
UNICHROME_CLE266)) {
viaparinfo->
lvds_setting_info->iga_path = IGA2;
crt_iga_path = IGA1;
viaparinfo->
tmds_setting_info->iga_path = IGA1;
} else
viaparinfo->
lvds_setting_info->iga_path = IGA1;
} else {
viaparinfo->lvds_setting_info->iga_path = IGA2;
}
}
if (viafb_LCD2_ON) {
if (LCD2_Device == viafb_primary_dev)
viaparinfo->lvds_setting_info2->iga_path = IGA1;
else
viaparinfo->lvds_setting_info2->iga_path = IGA2;
}
} else {
viafb_SAMM_ON = 0;
if (viafb_CRT_ON && viafb_LCD_ON) {
crt_iga_path = IGA1;
viaparinfo->lvds_setting_info->iga_path = IGA2;
} else if (viafb_CRT_ON && viafb_DVI_ON) {
crt_iga_path = IGA1;
viaparinfo->tmds_setting_info->iga_path = IGA2;
} else if (viafb_LCD_ON && viafb_DVI_ON) {
viaparinfo->tmds_setting_info->iga_path = IGA1;
viaparinfo->lvds_setting_info->iga_path = IGA2;
} else if (viafb_LCD_ON && viafb_LCD2_ON) {
viaparinfo->lvds_setting_info->iga_path = IGA2;
viaparinfo->lvds_setting_info2->iga_path = IGA2;
} else if (viafb_CRT_ON) {
crt_iga_path = IGA1;
} else if (viafb_LCD_ON) {
viaparinfo->lvds_setting_info->iga_path = IGA2;
} else if (viafb_DVI_ON) {
viaparinfo->tmds_setting_info->iga_path = IGA1;
}
}
viaparinfo->shared->iga1_devices = 0;
viaparinfo->shared->iga2_devices = 0;
if (viafb_CRT_ON) {
if (crt_iga_path == IGA1)
viaparinfo->shared->iga1_devices |= VIA_CRT;
else
viaparinfo->shared->iga2_devices |= VIA_CRT;
}
if (viafb_DVI_ON) {
if (viaparinfo->tmds_setting_info->iga_path == IGA1)
viaparinfo->shared->iga1_devices |= get_dvi_devices(
viaparinfo->chip_info->
tmds_chip_info.output_interface);
else
viaparinfo->shared->iga2_devices |= get_dvi_devices(
viaparinfo->chip_info->
tmds_chip_info.output_interface);
}
if (viafb_LCD_ON) {
if (viaparinfo->lvds_setting_info->iga_path == IGA1)
viaparinfo->shared->iga1_devices |= get_lcd_devices(
viaparinfo->chip_info->
lvds_chip_info.output_interface);
else
viaparinfo->shared->iga2_devices |= get_lcd_devices(
viaparinfo->chip_info->
lvds_chip_info.output_interface);
}
if (viafb_LCD2_ON) {
if (viaparinfo->lvds_setting_info2->iga_path == IGA1)
viaparinfo->shared->iga1_devices |= get_lcd_devices(
viaparinfo->chip_info->
lvds_chip_info2.output_interface);
else
viaparinfo->shared->iga2_devices |= get_lcd_devices(
viaparinfo->chip_info->
lvds_chip_info2.output_interface);
}
/* looks like the OLPC has its display wired to DVP1 and LVDS2 */
if (machine_is_olpc())
viaparinfo->shared->iga2_devices = VIA_DVP1 | VIA_LVDS2;
}
static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
{
outb(0xFF, 0x3C6); /* bit mask of palette */
outb(index, 0x3C8);
outb(red, 0x3C9);
outb(green, 0x3C9);
outb(blue, 0x3C9);
}
void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
{
viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
set_color_register(index, red, green, blue);
}
void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
{
viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
set_color_register(index, red, green, blue);
}
static void set_source_common(u8 index, u8 offset, u8 iga)
{
u8 value, mask = 1 << offset;
switch (iga) {
case IGA1:
value = 0x00;
break;
case IGA2:
value = mask;
break;
default:
printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
return;
}
via_write_reg_mask(VIACR, index, value, mask);
}
static void set_crt_source(u8 iga)
{
u8 value;
switch (iga) {
case IGA1:
value = 0x00;
break;
case IGA2:
value = 0x40;
break;
default:
printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga);
return;
}
via_write_reg_mask(VIASR, 0x16, value, 0x40);
}
static inline void set_ldvp0_source(u8 iga)
{
set_source_common(0x6C, 7, iga);
}
static inline void set_ldvp1_source(u8 iga)
{
set_source_common(0x93, 7, iga);
}
static inline void set_dvp0_source(u8 iga)
{
set_source_common(0x96, 4, iga);
}
static inline void set_dvp1_source(u8 iga)
{
set_source_common(0x9B, 4, iga);
}
static inline void set_lvds1_source(u8 iga)
{
set_source_common(0x99, 4, iga);
}
static inline void set_lvds2_source(u8 iga)
{
set_source_common(0x97, 4, iga);
}
void via_set_source(u32 devices, u8 iga)
{
if (devices & VIA_LDVP0)
set_ldvp0_source(iga);
if (devices & VIA_LDVP1)
set_ldvp1_source(iga);
if (devices & VIA_DVP0)
set_dvp0_source(iga);
if (devices & VIA_CRT)
set_crt_source(iga);
if (devices & VIA_DVP1)
set_dvp1_source(iga);
if (devices & VIA_LVDS1)
set_lvds1_source(iga);
if (devices & VIA_LVDS2)
set_lvds2_source(iga);
}
static void set_crt_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x00;
break;
case VIA_STATE_STANDBY:
value = 0x10;
break;
case VIA_STATE_SUSPEND:
value = 0x20;
break;
case VIA_STATE_OFF:
value = 0x30;
break;
default:
return;
}
via_write_reg_mask(VIACR, 0x36, value, 0x30);
}
static void set_dvp0_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0xC0;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x1E, value, 0xC0);
}
static void set_dvp1_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x30;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x1E, value, 0x30);
}
static void set_lvds1_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x03;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x2A, value, 0x03);
}
static void set_lvds2_state(u8 state)
{
u8 value;
switch (state) {
case VIA_STATE_ON:
value = 0x0C;
break;
case VIA_STATE_OFF:
value = 0x00;
break;
default:
return;
}
via_write_reg_mask(VIASR, 0x2A, value, 0x0C);
}
void via_set_state(u32 devices, u8 state)
{
/*
TODO: Can we enable/disable these devices? How?
if (devices & VIA_LDVP0)
if (devices & VIA_LDVP1)
*/
if (devices & VIA_DVP0)
set_dvp0_state(state);
if (devices & VIA_CRT)
set_crt_state(state);
if (devices & VIA_DVP1)
set_dvp1_state(state);
if (devices & VIA_LVDS1)
set_lvds1_state(state);
if (devices & VIA_LVDS2)
set_lvds2_state(state);
}
void via_set_sync_polarity(u32 devices, u8 polarity)
{
if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) {
printk(KERN_WARNING "viafb: Unsupported polarity: %d\n",
polarity);
return;
}
if (devices & VIA_CRT)
via_write_misc_reg_mask(polarity << 6, 0xC0);
if (devices & VIA_DVP1)
via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60);
if (devices & VIA_LVDS1)
via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60);
if (devices & VIA_LVDS2)
via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60);
}
u32 via_parse_odev(char *input, char **end)
{
char *ptr = input;
u32 odev = 0;
bool next = true;
int i, len;
while (next) {
next = false;
for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
len = strlen(device_mapping[i].name);
if (!strncmp(ptr, device_mapping[i].name, len)) {
odev |= device_mapping[i].device;
ptr += len;
if (*ptr == ',') {
ptr++;
next = true;
}
}
}
}
*end = ptr;
return odev;
}
void via_odev_to_seq(struct seq_file *m, u32 odev)
{
int i, count = 0;
for (i = 0; i < ARRAY_SIZE(device_mapping); i++) {
if (odev & device_mapping[i].device) {
if (count > 0)
seq_putc(m, ',');
seq_puts(m, device_mapping[i].name);
count++;
}
}
seq_putc(m, '\n');
}
static void load_fix_bit_crtc_reg(void)
{
viafb_unlock_crt();
/* always set to 1 */
viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
/* line compare should set all bits = 1 (extend modes) */
viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
/* line compare should set all bits = 1 (extend modes) */
viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
/*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
viafb_lock_crt();
/* If K8M800, enable Prefetch Mode. */
if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
|| (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
&& (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
}
void viafb_load_reg(int timing_value, int viafb_load_reg_num,
struct io_register *reg,
int io_type)
{
int reg_mask;
int bit_num = 0;
int data;
int i, j;
int shift_next_reg;
int start_index, end_index, cr_index;
u16 get_bit;
for (i = 0; i < viafb_load_reg_num; i++) {
reg_mask = 0;
data = 0;
start_index = reg[i].start_bit;
end_index = reg[i].end_bit;
cr_index = reg[i].io_addr;
shift_next_reg = bit_num;
for (j = start_index; j <= end_index; j++) {
/*if (bit_num==8) timing_value = timing_value >>8; */
reg_mask = reg_mask | (BIT0 << j);
get_bit = (timing_value & (BIT0 << bit_num));
data =
data | ((get_bit >> shift_next_reg) << start_index);
bit_num++;
}
if (io_type == VIACR)
viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
else
viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
}
}
/* Write Registers */
void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
{
int i;
/*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
for (i = 0; i < ItemNum; i++)
via_write_reg_mask(RegTable[i].port, RegTable[i].index,
RegTable[i].value, RegTable[i].mask);
}
void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
{
int reg_value;
int viafb_load_reg_num;
struct io_register *reg = NULL;
switch (set_iga) {
case IGA1:
reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
viafb_load_reg_num = fetch_count_reg.
iga1_fetch_count_reg.reg_num;
reg = fetch_count_reg.iga1_fetch_count_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
break;
case IGA2:
reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
viafb_load_reg_num = fetch_count_reg.
iga2_fetch_count_reg.reg_num;
reg = fetch_count_reg.iga2_fetch_count_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
break;
}
}
void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
{
int reg_value;
int viafb_load_reg_num;
struct io_register *reg = NULL;
int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
if (set_iga == IGA1) {
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
K800_IGA1_FIFO_HIGH_THRESHOLD;
/* If resolution > 1280x1024, expire length = 64, else
expire length = 128 */
if ((hor_active > 1280) && (ver_active > 1024))
iga1_display_queue_expire_num = 16;
else
iga1_display_queue_expire_num =
K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
P880_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
/* If resolution > 1280x1024, expire length = 64, else
expire length = 128 */
if ((hor_active > 1280) && (ver_active > 1024))
iga1_display_queue_expire_num = 16;
else
iga1_display_queue_expire_num =
P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
CN700_IGA1_FIFO_HIGH_THRESHOLD;
/* If resolution > 1280x1024, expire length = 64,
else expire length = 128 */
if ((hor_active > 1280) && (ver_active > 1024))
iga1_display_queue_expire_num = 16;
else
iga1_display_queue_expire_num =
CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
CX700_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
K8M890_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
P4M890_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
P4M900_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
VX800_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
VX855_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
VX900_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
/* Set Display FIFO Depath Select */
reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
viafb_load_reg_num =
display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
/* Set Display FIFO Threshold Select */
reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
viafb_load_reg_num =
fifo_threshold_select_reg.
iga1_fifo_threshold_select_reg.reg_num;
reg =
fifo_threshold_select_reg.
iga1_fifo_threshold_select_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
/* Set FIFO High Threshold Select */
reg_value =
IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
viafb_load_reg_num =
fifo_high_threshold_select_reg.
iga1_fifo_high_threshold_select_reg.reg_num;
reg =
fifo_high_threshold_select_reg.
iga1_fifo_high_threshold_select_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
/* Set Display Queue Expire Num */
reg_value =
IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
(iga1_display_queue_expire_num);
viafb_load_reg_num =
display_queue_expire_num_reg.
iga1_display_queue_expire_num_reg.reg_num;
reg =
display_queue_expire_num_reg.
iga1_display_queue_expire_num_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
} else {
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
K800_IGA2_FIFO_HIGH_THRESHOLD;
/* If resolution > 1280x1024, expire length = 64,
else expire length = 128 */
if ((hor_active > 1280) && (ver_active > 1024))
iga2_display_queue_expire_num = 16;
else
iga2_display_queue_expire_num =
K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
P880_IGA2_FIFO_HIGH_THRESHOLD;
/* If resolution > 1280x1024, expire length = 64,
else expire length = 128 */
if ((hor_active > 1280) && (ver_active > 1024))
iga2_display_queue_expire_num = 16;
else
iga2_display_queue_expire_num =
P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
CN700_IGA2_FIFO_HIGH_THRESHOLD;
/* If resolution > 1280x1024, expire length = 64,
else expire length = 128 */
if ((hor_active > 1280) && (ver_active > 1024))
iga2_display_queue_expire_num = 16;
else
iga2_display_queue_expire_num =
CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
CX700_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
K8M890_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
P4M890_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
P4M900_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
VX800_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
VX855_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) {
iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
VX900_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
/* Set Display FIFO Depath Select */
reg_value =
IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
- 1;
/* Patch LCD in IGA2 case */
viafb_load_reg_num =
display_fifo_depth_reg.
iga2_fifo_depth_select_reg.reg_num;
reg =
display_fifo_depth_reg.
iga2_fifo_depth_select_reg.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
} else {
/* Set Display FIFO Depath Select */
reg_value =
IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
viafb_load_reg_num =
display_fifo_depth_reg.
iga2_fifo_depth_select_reg.reg_num;
reg =
display_fifo_depth_reg.
iga2_fifo_depth_select_reg.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
}
/* Set Display FIFO Threshold Select */
reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
viafb_load_reg_num =
fifo_threshold_select_reg.
iga2_fifo_threshold_select_reg.reg_num;
reg =
fifo_threshold_select_reg.
iga2_fifo_threshold_select_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
/* Set FIFO High Threshold Select */
reg_value =
IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
viafb_load_reg_num =
fifo_high_threshold_select_reg.
iga2_fifo_high_threshold_select_reg.reg_num;
reg =
fifo_high_threshold_select_reg.
iga2_fifo_high_threshold_select_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
/* Set Display Queue Expire Num */
reg_value =
IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
(iga2_display_queue_expire_num);
viafb_load_reg_num =
display_queue_expire_num_reg.
iga2_display_queue_expire_num_reg.reg_num;
reg =
display_queue_expire_num_reg.
iga2_display_queue_expire_num_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
}
}
static struct via_pll_config get_pll_config(struct pll_limit *limits, int size,
int clk)
{
struct via_pll_config cur, up, down, best = {0, 1, 0};
const u32 f0 = 14318180; /* X1 frequency */
int i, f;
for (i = 0; i < size; i++) {
cur.rshift = limits[i].rshift;
cur.divisor = limits[i].divisor;
cur.multiplier = clk / ((f0 / cur.divisor)>>cur.rshift);
f = abs(get_pll_output_frequency(f0, cur) - clk);
up = down = cur;
up.multiplier++;
down.multiplier--;
if (abs(get_pll_output_frequency(f0, up) - clk) < f)
cur = up;
else if (abs(get_pll_output_frequency(f0, down) - clk) < f)
cur = down;
if (cur.multiplier < limits[i].multiplier_min)
cur.multiplier = limits[i].multiplier_min;
else if (cur.multiplier > limits[i].multiplier_max)
cur.multiplier = limits[i].multiplier_max;
f = abs(get_pll_output_frequency(f0, cur) - clk);
if (f < abs(get_pll_output_frequency(f0, best) - clk))
best = cur;
}
return best;
}
static struct via_pll_config get_best_pll_config(int clk)
{
struct via_pll_config config;
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
config = get_pll_config(cle266_pll_limits,
ARRAY_SIZE(cle266_pll_limits), clk);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
config = get_pll_config(k800_pll_limits,
ARRAY_SIZE(k800_pll_limits), clk);
break;
case UNICHROME_CX700:
case UNICHROME_CN750:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
config = get_pll_config(cx700_pll_limits,
ARRAY_SIZE(cx700_pll_limits), clk);
break;
case UNICHROME_VX855:
case UNICHROME_VX900:
config = get_pll_config(vx855_pll_limits,
ARRAY_SIZE(vx855_pll_limits), clk);
break;
}
return config;
}
/* Set VCLK*/
void viafb_set_vclock(u32 clk, int set_iga)
{
struct via_pll_config config = get_best_pll_config(clk);
if (set_iga == IGA1)
clock.set_primary_pll(config);
if (set_iga == IGA2)
clock.set_secondary_pll(config);
/* Fire! */
via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
}
struct via_display_timing var_to_timing(const struct fb_var_screeninfo *var,
u16 cxres, u16 cyres)
{
struct via_display_timing timing;
u16 dx = (var->xres - cxres) / 2, dy = (var->yres - cyres) / 2;
timing.hor_addr = cxres;
timing.hor_sync_start = timing.hor_addr + var->right_margin + dx;
timing.hor_sync_end = timing.hor_sync_start + var->hsync_len;
timing.hor_total = timing.hor_sync_end + var->left_margin + dx;
timing.hor_blank_start = timing.hor_addr + dx;
timing.hor_blank_end = timing.hor_total - dx;
timing.ver_addr = cyres;
timing.ver_sync_start = timing.ver_addr + var->lower_margin + dy;
timing.ver_sync_end = timing.ver_sync_start + var->vsync_len;
timing.ver_total = timing.ver_sync_end + var->upper_margin + dy;
timing.ver_blank_start = timing.ver_addr + dy;
timing.ver_blank_end = timing.ver_total - dy;
return timing;
}
void viafb_fill_crtc_timing(const struct fb_var_screeninfo *var,
u16 cxres, u16 cyres, int iga)
{
struct via_display_timing crt_reg = var_to_timing(var,
cxres ? cxres : var->xres, cyres ? cyres : var->yres);
if (iga == IGA1)
via_set_primary_timing(&crt_reg);
else if (iga == IGA2)
via_set_secondary_timing(&crt_reg);
viafb_load_fetch_count_reg(var->xres, var->bits_per_pixel / 8, iga);
if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266
&& viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)
viafb_load_FIFO_reg(iga, var->xres, var->yres);
viafb_set_vclock(PICOS2KHZ(var->pixclock) * 1000, iga);
}
void viafb_init_chip_info(int chip_type)
{
via_clock_init(&clock, chip_type);
init_gfx_chip_info(chip_type);
init_tmds_chip_info();
init_lvds_chip_info();
/*Set IGA path for each device */
viafb_set_iga_path();
viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
viaparinfo->lvds_setting_info2->display_method =
viaparinfo->lvds_setting_info->display_method;
viaparinfo->lvds_setting_info2->lcd_mode =
viaparinfo->lvds_setting_info->lcd_mode;
}
void viafb_update_device_setting(int hres, int vres, int bpp, int flag)
{
if (flag == 0) {
viaparinfo->tmds_setting_info->h_active = hres;
viaparinfo->tmds_setting_info->v_active = vres;
} else {
if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
viaparinfo->tmds_setting_info->h_active = hres;
viaparinfo->tmds_setting_info->v_active = vres;
}
}
}
static void init_gfx_chip_info(int chip_type)
{
u8 tmp;
viaparinfo->chip_info->gfx_chip_name = chip_type;
/* Check revision of CLE266 Chip */
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
/* CR4F only define in CLE266.CX chip */
tmp = viafb_read_reg(VIACR, CR4F);
viafb_write_reg(CR4F, VIACR, 0x55);
if (viafb_read_reg(VIACR, CR4F) != 0x55)
viaparinfo->chip_info->gfx_chip_revision =
CLE266_REVISION_AX;
else
viaparinfo->chip_info->gfx_chip_revision =
CLE266_REVISION_CX;
/* restore orignal CR4F value */
viafb_write_reg(CR4F, VIACR, tmp);
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
tmp = viafb_read_reg(VIASR, SR43);
DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
if (tmp & 0x02) {
viaparinfo->chip_info->gfx_chip_revision =
CX700_REVISION_700M2;
} else if (tmp & 0x40) {
viaparinfo->chip_info->gfx_chip_revision =
CX700_REVISION_700M;
} else {
viaparinfo->chip_info->gfx_chip_revision =
CX700_REVISION_700;
}
}
/* Determine which 2D engine we have */
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_VX800:
case UNICHROME_VX855:
case UNICHROME_VX900:
viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1;
break;
case UNICHROME_K8M890:
case UNICHROME_P4M900:
viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5;
break;
default:
viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2;
break;
}
}
static void init_tmds_chip_info(void)
{
viafb_tmds_trasmitter_identify();
if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
output_interface) {
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CX700:
{
/* we should check support by hardware layout.*/
if ((viafb_display_hardware_layout ==
HW_LAYOUT_DVI_ONLY)
|| (viafb_display_hardware_layout ==
HW_LAYOUT_LCD_DVI)) {
viaparinfo->chip_info->tmds_chip_info.
output_interface = INTERFACE_TMDS;
} else {
viaparinfo->chip_info->tmds_chip_info.
output_interface =
INTERFACE_NONE;
}
break;
}
case UNICHROME_K8M890:
case UNICHROME_P4M900:
case UNICHROME_P4M890:
/* TMDS on PCIE, we set DFPLOW as default. */
viaparinfo->chip_info->tmds_chip_info.output_interface =
INTERFACE_DFP_LOW;
break;
default:
{
/* set DVP1 default for DVI */
viaparinfo->chip_info->tmds_chip_info
.output_interface = INTERFACE_DVP1;
}
}
}
DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
&viaparinfo->shared->tmds_setting_info);
}
static void init_lvds_chip_info(void)
{
viafb_lvds_trasmitter_identify();
viafb_init_lcd_size();
viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
viaparinfo->lvds_setting_info);
if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
viafb_init_lvds_output_interface(&viaparinfo->chip_info->
lvds_chip_info2, viaparinfo->lvds_setting_info2);
}
/*If CX700,two singel LCD, we need to reassign
LCD interface to different LVDS port */
if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
&& (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
lvds_chip_name) && (INTEGRATED_LVDS ==
viaparinfo->chip_info->
lvds_chip_info2.lvds_chip_name)) {
viaparinfo->chip_info->lvds_chip_info.output_interface =
INTERFACE_LVDS0;
viaparinfo->chip_info->lvds_chip_info2.
output_interface =
INTERFACE_LVDS1;
}
}
DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
viaparinfo->chip_info->lvds_chip_info.output_interface);
DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
viaparinfo->chip_info->lvds_chip_info.output_interface);
}
void viafb_init_dac(int set_iga)
{
int i;
u8 tmp;
if (set_iga == IGA1) {
/* access Primary Display's LUT */
viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
/* turn off LCK */
viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
for (i = 0; i < 256; i++) {
write_dac_reg(i, palLUT_table[i].red,
palLUT_table[i].green,
palLUT_table[i].blue);
}
/* turn on LCK */
viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
} else {
tmp = viafb_read_reg(VIACR, CR6A);
/* access Secondary Display's LUT */
viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
for (i = 0; i < 256; i++) {
write_dac_reg(i, palLUT_table[i].red,
palLUT_table[i].green,
palLUT_table[i].blue);
}
/* set IGA1 DAC for default */
viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
viafb_write_reg(CR6A, VIACR, tmp);
}
}
static void device_screen_off(void)
{
/* turn off CRT screen (IGA1) */
viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
}
static void device_screen_on(void)
{
/* turn on CRT screen (IGA1) */
viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
}
static void set_display_channel(void)
{
/*If viafb_LCD2_ON, on cx700, internal lvds's information
is keeped on lvds_setting_info2 */
if (viafb_LCD2_ON &&
viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
/* For dual channel LCD: */
/* Set to Dual LVDS channel. */
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
} else if (viafb_LCD_ON && viafb_DVI_ON) {
/* For LCD+DFP: */
/* Set to LVDS1 + TMDS channel. */
viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
} else if (viafb_DVI_ON) {
/* Set to single TMDS channel. */
viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
} else if (viafb_LCD_ON) {
if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
/* For dual channel LCD: */
/* Set to Dual LVDS channel. */
viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
} else {
/* Set to LVDS0 + LVDS1 channel. */
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
}
}
}
static u8 get_sync(struct fb_var_screeninfo *var)
{
u8 polarity = 0;
if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
polarity |= VIA_HSYNC_NEGATIVE;
if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
polarity |= VIA_VSYNC_NEGATIVE;
return polarity;
}
static void hw_init(void)
{
int i;
inb(VIAStatus);
outb(0x00, VIAAR);
/* Write Common Setting for Video Mode */
viafb_write_regx(common_vga, ARRAY_SIZE(common_vga));
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
break;
case UNICHROME_K400:
viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
break;
case UNICHROME_CN700:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
break;
case UNICHROME_CX700:
case UNICHROME_VX800:
viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
break;
case UNICHROME_VX855:
case UNICHROME_VX900:
viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
break;
}
/* magic required on VX900 for correct modesetting on IGA1 */
via_write_reg_mask(VIACR, 0x45, 0x00, 0x01);
/* probably this should go to the scaling code one day */
via_write_reg_mask(VIACR, 0xFD, 0, 0x80); /* VX900 hw scale on IGA2 */
viafb_write_regx(scaling_parameters, ARRAY_SIZE(scaling_parameters));
/* Fill VPIT Parameters */
/* Write Misc Register */
outb(VPIT.Misc, VIA_MISC_REG_WRITE);
/* Write Sequencer */
for (i = 1; i <= StdSR; i++)
via_write_reg(VIASR, i, VPIT.SR[i - 1]);
viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
/* Write Graphic Controller */
for (i = 0; i < StdGR; i++)
via_write_reg(VIAGR, i, VPIT.GR[i]);
/* Write Attribute Controller */
for (i = 0; i < StdAR; i++) {
inb(VIAStatus);
outb(i, VIAAR);
outb(VPIT.AR[i], VIAAR);
}
inb(VIAStatus);
outb(0x20, VIAAR);
load_fix_bit_crtc_reg();
}
int viafb_setmode(void)
{
int j, cxres = 0, cyres = 0;
int port;
u32 devices = viaparinfo->shared->iga1_devices
| viaparinfo->shared->iga2_devices;
u8 value, index, mask;
struct fb_var_screeninfo var2;
device_screen_off();
device_off();
via_set_state(devices, VIA_STATE_OFF);
hw_init();
/* Update Patch Register */
if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
|| viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
&& viafbinfo->var.xres == 1024 && viafbinfo->var.yres == 768) {
for (j = 0; j < res_patch_table[0].table_length; j++) {
index = res_patch_table[0].io_reg_table[j].index;
port = res_patch_table[0].io_reg_table[j].port;
value = res_patch_table[0].io_reg_table[j].value;
mask = res_patch_table[0].io_reg_table[j].mask;
viafb_write_reg_mask(index, port, value, mask);
}
}
via_set_primary_pitch(viafbinfo->fix.line_length);
via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
: viafbinfo->fix.line_length);
via_set_primary_color_depth(viaparinfo->depth);
via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
: viaparinfo->depth);
via_set_source(viaparinfo->shared->iga1_devices, IGA1);
via_set_source(viaparinfo->shared->iga2_devices, IGA2);
if (viaparinfo->shared->iga2_devices)
enable_second_display_channel();
else
disable_second_display_channel();
/* Update Refresh Rate Setting */
/* Clear On Screen */
if (viafb_dual_fb) {
var2 = viafbinfo1->var;
} else if (viafb_SAMM_ON) {
viafb_fill_var_timing_info(&var2, viafb_get_best_mode(
viafb_second_xres, viafb_second_yres, viafb_refresh1));
cxres = viafbinfo->var.xres;
cyres = viafbinfo->var.yres;
var2.bits_per_pixel = viafbinfo->var.bits_per_pixel;
}
/* CRT set mode */
if (viafb_CRT_ON) {
if (viaparinfo->shared->iga2_devices & VIA_CRT
&& viafb_SAMM_ON)
viafb_fill_crtc_timing(&var2, cxres, cyres, IGA2);
else
viafb_fill_crtc_timing(&viafbinfo->var, 0, 0,
(viaparinfo->shared->iga1_devices & VIA_CRT)
? IGA1 : IGA2);
/* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
to 8 alignment (1368),there is several pixels (2 pixels)
on right side of screen. */
if (viafbinfo->var.xres % 8) {
viafb_unlock_crt();
viafb_write_reg(CR02, VIACR,
viafb_read_reg(VIACR, CR02) - 1);
viafb_lock_crt();
}
}
if (viafb_DVI_ON) {
if (viaparinfo->shared->tmds_setting_info.iga_path == IGA2
&& viafb_SAMM_ON)
viafb_dvi_set_mode(&var2, cxres, cyres, IGA2);
else
viafb_dvi_set_mode(&viafbinfo->var, 0, 0,
viaparinfo->tmds_setting_info->iga_path);
}
if (viafb_LCD_ON) {
if (viafb_SAMM_ON &&
(viaparinfo->lvds_setting_info->iga_path == IGA2)) {
viafb_lcd_set_mode(&var2, cxres, cyres,
viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info);
} else {
/* IGA1 doesn't have LCD scaling, so set it center. */
if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
viaparinfo->lvds_setting_info->display_method =
LCD_CENTERING;
}
viafb_lcd_set_mode(&viafbinfo->var, 0, 0,
viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info);
}
}
if (viafb_LCD2_ON) {
if (viafb_SAMM_ON &&
(viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
viafb_lcd_set_mode(&var2, cxres, cyres,
viaparinfo->lvds_setting_info2,
&viaparinfo->chip_info->lvds_chip_info2);
} else {
/* IGA1 doesn't have LCD scaling, so set it center. */
if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
viaparinfo->lvds_setting_info2->display_method =
LCD_CENTERING;
}
viafb_lcd_set_mode(&viafbinfo->var, 0, 0,
viaparinfo->lvds_setting_info2,
&viaparinfo->chip_info->lvds_chip_info2);
}
}
if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
&& (viafb_LCD_ON || viafb_DVI_ON))
set_display_channel();
/* If set mode normally, save resolution information for hot-plug . */
if (!viafb_hotplug) {
viafb_hotplug_Xres = viafbinfo->var.xres;
viafb_hotplug_Yres = viafbinfo->var.yres;
viafb_hotplug_bpp = viafbinfo->var.bits_per_pixel;
viafb_hotplug_refresh = viafb_refresh;
if (viafb_DVI_ON)
viafb_DeviceStatus = DVI_Device;
else
viafb_DeviceStatus = CRT_Device;
}
device_on();
if (!viafb_SAMM_ON)
via_set_sync_polarity(devices, get_sync(&viafbinfo->var));
else {
via_set_sync_polarity(viaparinfo->shared->iga1_devices,
get_sync(&viafbinfo->var));
via_set_sync_polarity(viaparinfo->shared->iga2_devices,
get_sync(&var2));
}
clock.set_engine_pll_state(VIA_STATE_ON);
clock.set_primary_clock_source(VIA_CLKSRC_X1, true);
clock.set_secondary_clock_source(VIA_CLKSRC_X1, true);
#ifdef CONFIG_FB_VIA_X_COMPATIBILITY
clock.set_primary_pll_state(VIA_STATE_ON);
clock.set_primary_clock_state(VIA_STATE_ON);
clock.set_secondary_pll_state(VIA_STATE_ON);
clock.set_secondary_clock_state(VIA_STATE_ON);
#else
if (viaparinfo->shared->iga1_devices) {
clock.set_primary_pll_state(VIA_STATE_ON);
clock.set_primary_clock_state(VIA_STATE_ON);
} else {
clock.set_primary_pll_state(VIA_STATE_OFF);
clock.set_primary_clock_state(VIA_STATE_OFF);
}
if (viaparinfo->shared->iga2_devices) {
clock.set_secondary_pll_state(VIA_STATE_ON);
clock.set_secondary_clock_state(VIA_STATE_ON);
} else {
clock.set_secondary_pll_state(VIA_STATE_OFF);
clock.set_secondary_clock_state(VIA_STATE_OFF);
}
#endif /*CONFIG_FB_VIA_X_COMPATIBILITY*/
via_set_state(devices, VIA_STATE_ON);
device_screen_on();
return 1;
}
int viafb_get_refresh(int hres, int vres, u32 long_refresh)
{
const struct fb_videomode *best;
best = viafb_get_best_mode(hres, vres, long_refresh);
if (!best)
return 60;
if (abs(best->refresh - long_refresh) > 3) {
if (hres == 1200 && vres == 900)
return 49; /* OLPC DCON only supports 50 Hz */
else
return 60;
}
return best->refresh;
}
static void device_off(void)
{
viafb_dvi_disable();
viafb_lcd_disable();
}
static void device_on(void)
{
if (viafb_DVI_ON == 1)
viafb_dvi_enable();
if (viafb_LCD_ON == 1)
viafb_lcd_enable();
}
static void enable_second_display_channel(void)
{
/* to enable second display channel. */
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
}
static void disable_second_display_channel(void)
{
/* to disable second display channel. */
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
}
void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
*p_gfx_dpa_setting)
{
switch (output_interface) {
case INTERFACE_DVP0:
{
/* DVP0 Clock Polarity and Adjust: */
viafb_write_reg_mask(CR96, VIACR,
p_gfx_dpa_setting->DVP0, 0x0F);
/* DVP0 Clock and Data Pads Driving: */
viafb_write_reg_mask(SR1E, VIASR,
p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
viafb_write_reg_mask(SR2A, VIASR,
p_gfx_dpa_setting->DVP0ClockDri_S1,
BIT4);
viafb_write_reg_mask(SR1B, VIASR,
p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
viafb_write_reg_mask(SR2A, VIASR,
p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
break;
}
case INTERFACE_DVP1:
{
/* DVP1 Clock Polarity and Adjust: */
viafb_write_reg_mask(CR9B, VIACR,
p_gfx_dpa_setting->DVP1, 0x0F);
/* DVP1 Clock and Data Pads Driving: */
viafb_write_reg_mask(SR65, VIASR,
p_gfx_dpa_setting->DVP1Driving, 0x0F);
break;
}
case INTERFACE_DFP_HIGH:
{
viafb_write_reg_mask(CR97, VIACR,
p_gfx_dpa_setting->DFPHigh, 0x0F);
break;
}
case INTERFACE_DFP_LOW:
{
viafb_write_reg_mask(CR99, VIACR,
p_gfx_dpa_setting->DFPLow, 0x0F);
break;
}
case INTERFACE_DFP:
{
viafb_write_reg_mask(CR97, VIACR,
p_gfx_dpa_setting->DFPHigh, 0x0F);
viafb_write_reg_mask(CR99, VIACR,
p_gfx_dpa_setting->DFPLow, 0x0F);
break;
}
}
}
void viafb_fill_var_timing_info(struct fb_var_screeninfo *var,
const struct fb_videomode *mode)
{
var->pixclock = mode->pixclock;
var->xres = mode->xres;
var->yres = mode->yres;
var->left_margin = mode->left_margin;
var->right_margin = mode->right_margin;
var->hsync_len = mode->hsync_len;
var->upper_margin = mode->upper_margin;
var->lower_margin = mode->lower_margin;
var->vsync_len = mode->vsync_len;
var->sync = mode->sync;
}
| linux-master | drivers/video/fbdev/via/hw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* driver for Chrontel CH7301 DVI Transmitter
*/
#include <linux/slab.h>
#include "via_aux.h"
static const char *name = "CH7301 DVI Transmitter";
static void probe(struct via_aux_bus *bus, u8 addr)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = addr,
.name = name};
u8 tmp;
if (!via_aux_read(&drv, 0x4B, &tmp, 1) || tmp != 0x17)
return;
printk(KERN_INFO "viafb: Found %s at address 0x%x\n", name, addr);
via_aux_add(&drv);
}
void via_aux_ch7301_probe(struct via_aux_bus *bus)
{
probe(bus, 0x75);
probe(bus, 0x76);
}
| linux-master | drivers/video/fbdev/via/via_aux_ch7301.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/compiler.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <linux/stat.h>
#include <linux/via-core.h>
#include <linux/via_i2c.h>
#define _MASTER_FILE
#include "global.h"
static char *viafb_name = "Via";
static u32 pseudo_pal[17];
/* video mode */
static char *viafb_mode;
static char *viafb_mode1;
static int viafb_bpp = 32;
static int viafb_bpp1 = 32;
static unsigned int viafb_second_offset;
static int viafb_second_size;
static int viafb_accel = 1;
/* Added for specifying active devices.*/
static char *viafb_active_dev;
/*Added for specify lcd output port*/
static char *viafb_lcd_port = "";
static char *viafb_dvi_port = "";
static void retrieve_device_setting(struct viafb_ioctl_setting
*setting_info);
static int viafb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info);
static struct fb_ops viafb_ops;
/* supported output devices on each IGP
* only CX700, VX800, VX855, VX900 were documented
* VIA_CRT should be everywhere
* VIA_6C can be onle pre-CX700 (probably only on CLE266) as 6C is used for PLL
* source selection on CX700 and later
* K400 seems to support VIA_96, VIA_DVP1, VIA_LVDS{1,2} as in viamode.c
*/
static const u32 supported_odev_map[] = {
[UNICHROME_CLE266] = VIA_CRT | VIA_LDVP0 | VIA_LDVP1,
[UNICHROME_K400] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1
| VIA_LVDS2,
[UNICHROME_K800] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1
| VIA_LVDS2,
[UNICHROME_PM800] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1
| VIA_LVDS2,
[UNICHROME_CN700] = VIA_CRT | VIA_DVP0 | VIA_DVP1 | VIA_LVDS1
| VIA_LVDS2,
[UNICHROME_CX700] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
[UNICHROME_CN750] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
[UNICHROME_K8M890] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
[UNICHROME_P4M890] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
[UNICHROME_P4M900] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
[UNICHROME_VX800] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
[UNICHROME_VX855] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
[UNICHROME_VX900] = VIA_CRT | VIA_DVP1 | VIA_LVDS1 | VIA_LVDS2,
};
static void viafb_fill_var_color_info(struct fb_var_screeninfo *var, u8 depth)
{
var->grayscale = 0;
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.offset = 0;
var->transp.length = 0;
var->transp.msb_right = 0;
var->nonstd = 0;
switch (depth) {
case 8:
var->bits_per_pixel = 8;
var->red.offset = 0;
var->green.offset = 0;
var->blue.offset = 0;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
case 15:
var->bits_per_pixel = 16;
var->red.offset = 10;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = 5;
var->green.length = 5;
var->blue.length = 5;
break;
case 16:
var->bits_per_pixel = 16;
var->red.offset = 11;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = 5;
var->green.length = 6;
var->blue.length = 5;
break;
case 24:
var->bits_per_pixel = 32;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
case 30:
var->bits_per_pixel = 32;
var->red.offset = 20;
var->green.offset = 10;
var->blue.offset = 0;
var->red.length = 10;
var->green.length = 10;
var->blue.length = 10;
break;
}
}
static void viafb_update_fix(struct fb_info *info)
{
u32 bpp = info->var.bits_per_pixel;
info->fix.visual =
bpp == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
info->fix.line_length = ALIGN(info->var.xres_virtual * bpp / 8,
VIA_PITCH_SIZE);
}
static void viafb_setup_fixinfo(struct fb_fix_screeninfo *fix,
struct viafb_par *viaparinfo)
{
memset(fix, 0, sizeof(struct fb_fix_screeninfo));
strcpy(fix->id, viafb_name);
fix->smem_start = viaparinfo->fbmem;
fix->smem_len = viaparinfo->fbmem_free;
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
fix->visual = FB_VISUAL_TRUECOLOR;
fix->xpanstep = fix->ywrapstep = 0;
fix->ypanstep = 1;
/* Just tell the accel name */
viafbinfo->fix.accel = FB_ACCEL_VIA_UNICHROME;
}
static int viafb_open(struct fb_info *info, int user)
{
DEBUG_MSG(KERN_INFO "viafb_open!\n");
return 0;
}
static int viafb_release(struct fb_info *info, int user)
{
DEBUG_MSG(KERN_INFO "viafb_release!\n");
return 0;
}
static inline int get_var_refresh(struct fb_var_screeninfo *var)
{
u32 htotal, vtotal;
htotal = var->left_margin + var->xres + var->right_margin
+ var->hsync_len;
vtotal = var->upper_margin + var->yres + var->lower_margin
+ var->vsync_len;
return PICOS2KHZ(var->pixclock) * 1000 / (htotal * vtotal);
}
static int viafb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int depth, refresh;
struct viafb_par *ppar = info->par;
u32 line;
DEBUG_MSG(KERN_INFO "viafb_check_var!\n");
/* Sanity check */
/* HW neither support interlacte nor double-scaned mode */
if (var->vmode & FB_VMODE_INTERLACED || var->vmode & FB_VMODE_DOUBLE)
return -EINVAL;
/* the refresh rate is not important here, as we only want to know
* whether the resolution exists
*/
if (!viafb_get_best_mode(var->xres, var->yres, 60)) {
DEBUG_MSG(KERN_INFO
"viafb: Mode %dx%dx%d not supported!!\n",
var->xres, var->yres, var->bits_per_pixel);
return -EINVAL;
}
depth = fb_get_color_depth(var, &info->fix);
if (!depth)
depth = var->bits_per_pixel;
if (depth < 0 || depth > 32)
return -EINVAL;
else if (!depth)
depth = 24;
else if (depth == 15 && viafb_dual_fb && ppar->iga_path == IGA1)
depth = 15;
else if (depth == 30)
depth = 30;
else if (depth <= 8)
depth = 8;
else if (depth <= 16)
depth = 16;
else
depth = 24;
viafb_fill_var_color_info(var, depth);
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
line = ALIGN(var->xres_virtual * var->bits_per_pixel / 8,
VIA_PITCH_SIZE);
if (line > VIA_PITCH_MAX || line * var->yres_virtual > ppar->memsize)
return -EINVAL;
/* Based on var passed in to calculate the refresh,
* because our driver use some modes special.
*/
refresh = viafb_get_refresh(var->xres, var->yres,
get_var_refresh(var));
/* Adjust var according to our driver's own table */
viafb_fill_var_timing_info(var,
viafb_get_best_mode(var->xres, var->yres, refresh));
if (var->accel_flags & FB_ACCELF_TEXT &&
!ppar->shared->vdev->engine_mmio)
var->accel_flags = 0;
return 0;
}
static int viafb_set_par(struct fb_info *info)
{
struct viafb_par *viapar = info->par;
int refresh;
DEBUG_MSG(KERN_INFO "viafb_set_par!\n");
viafb_update_fix(info);
viapar->depth = fb_get_color_depth(&info->var, &info->fix);
viafb_update_device_setting(viafbinfo->var.xres, viafbinfo->var.yres,
viafbinfo->var.bits_per_pixel, 0);
if (viafb_dual_fb) {
viafb_update_device_setting(viafbinfo1->var.xres,
viafbinfo1->var.yres, viafbinfo1->var.bits_per_pixel,
1);
} else if (viafb_SAMM_ON == 1) {
DEBUG_MSG(KERN_INFO
"viafb_second_xres = %d, viafb_second_yres = %d, bpp = %d\n",
viafb_second_xres, viafb_second_yres, viafb_bpp1);
viafb_update_device_setting(viafb_second_xres,
viafb_second_yres, viafb_bpp1, 1);
}
refresh = get_var_refresh(&info->var);
if (viafb_dual_fb && viapar->iga_path == IGA2) {
viafb_bpp1 = info->var.bits_per_pixel;
viafb_refresh1 = refresh;
} else {
viafb_bpp = info->var.bits_per_pixel;
viafb_refresh = refresh;
}
if (info->var.accel_flags & FB_ACCELF_TEXT)
info->flags &= ~FBINFO_HWACCEL_DISABLED;
else
info->flags |= FBINFO_HWACCEL_DISABLED;
viafb_setmode();
viafb_pan_display(&info->var, info);
return 0;
}
/* Set one color register */
static int viafb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
struct viafb_par *viapar = info->par;
u32 r, g, b;
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
if (regno > 255)
return -EINVAL;
if (!viafb_dual_fb || viapar->iga_path == IGA1)
viafb_set_primary_color_register(regno, red >> 8,
green >> 8, blue >> 8);
if (!viafb_dual_fb || viapar->iga_path == IGA2)
viafb_set_secondary_color_register(regno, red >> 8,
green >> 8, blue >> 8);
} else {
if (regno > 15)
return -EINVAL;
r = (red >> (16 - info->var.red.length))
<< info->var.red.offset;
b = (blue >> (16 - info->var.blue.length))
<< info->var.blue.offset;
g = (green >> (16 - info->var.green.length))
<< info->var.green.offset;
((u32 *) info->pseudo_palette)[regno] = r | g | b;
}
return 0;
}
static int viafb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct viafb_par *viapar = info->par;
u32 vram_addr = viapar->vram_addr
+ var->yoffset * info->fix.line_length
+ var->xoffset * info->var.bits_per_pixel / 8;
DEBUG_MSG(KERN_DEBUG "viafb_pan_display, address = %d\n", vram_addr);
if (!viafb_dual_fb) {
via_set_primary_address(vram_addr);
via_set_secondary_address(vram_addr);
} else if (viapar->iga_path == IGA1)
via_set_primary_address(vram_addr);
else
via_set_secondary_address(vram_addr);
return 0;
}
static int viafb_blank(int blank_mode, struct fb_info *info)
{
DEBUG_MSG(KERN_INFO "viafb_blank!\n");
/* clear DPMS setting */
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* Screen: On, HSync: On, VSync: On */
/* control CRT monitor power management */
via_set_state(VIA_CRT, VIA_STATE_ON);
break;
case FB_BLANK_HSYNC_SUSPEND:
/* Screen: Off, HSync: Off, VSync: On */
/* control CRT monitor power management */
via_set_state(VIA_CRT, VIA_STATE_STANDBY);
break;
case FB_BLANK_VSYNC_SUSPEND:
/* Screen: Off, HSync: On, VSync: Off */
/* control CRT monitor power management */
via_set_state(VIA_CRT, VIA_STATE_SUSPEND);
break;
case FB_BLANK_POWERDOWN:
/* Screen: Off, HSync: Off, VSync: Off */
/* control CRT monitor power management */
via_set_state(VIA_CRT, VIA_STATE_OFF);
break;
}
return 0;
}
static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
{
union {
struct viafb_ioctl_mode viamode;
struct viafb_ioctl_samm viasamm;
struct viafb_driver_version driver_version;
struct fb_var_screeninfo sec_var;
struct _panel_size_pos_info panel_pos_size_para;
struct viafb_ioctl_setting viafb_setting;
struct device_t active_dev;
} u;
u32 state_info = 0;
u32 *viafb_gamma_table;
char driver_name[] = "viafb";
u32 __user *argp = (u32 __user *) arg;
u32 gpu32;
DEBUG_MSG(KERN_INFO "viafb_ioctl: 0x%X !!\n", cmd);
printk(KERN_WARNING "viafb_ioctl: Please avoid this interface as it is unstable and might change or vanish at any time!\n");
memset(&u, 0, sizeof(u));
switch (cmd) {
case VIAFB_GET_CHIP_INFO:
if (copy_to_user(argp, viaparinfo->chip_info,
sizeof(struct chip_information)))
return -EFAULT;
break;
case VIAFB_GET_INFO_SIZE:
return put_user((u32)sizeof(struct viafb_ioctl_info), argp);
case VIAFB_GET_INFO:
return viafb_ioctl_get_viafb_info(arg);
case VIAFB_HOTPLUG:
return put_user(viafb_ioctl_hotplug(info->var.xres,
info->var.yres,
info->var.bits_per_pixel), argp);
case VIAFB_SET_HOTPLUG_FLAG:
if (copy_from_user(&gpu32, argp, sizeof(gpu32)))
return -EFAULT;
viafb_hotplug = (gpu32) ? 1 : 0;
break;
case VIAFB_GET_RESOLUTION:
u.viamode.xres = (u32) viafb_hotplug_Xres;
u.viamode.yres = (u32) viafb_hotplug_Yres;
u.viamode.refresh = (u32) viafb_hotplug_refresh;
u.viamode.bpp = (u32) viafb_hotplug_bpp;
if (viafb_SAMM_ON == 1) {
u.viamode.xres_sec = viafb_second_xres;
u.viamode.yres_sec = viafb_second_yres;
u.viamode.virtual_xres_sec = viafb_dual_fb ? viafbinfo1->var.xres_virtual : viafbinfo->var.xres_virtual;
u.viamode.virtual_yres_sec = viafb_dual_fb ? viafbinfo1->var.yres_virtual : viafbinfo->var.yres_virtual;
u.viamode.refresh_sec = viafb_refresh1;
u.viamode.bpp_sec = viafb_bpp1;
} else {
u.viamode.xres_sec = 0;
u.viamode.yres_sec = 0;
u.viamode.virtual_xres_sec = 0;
u.viamode.virtual_yres_sec = 0;
u.viamode.refresh_sec = 0;
u.viamode.bpp_sec = 0;
}
if (copy_to_user(argp, &u.viamode, sizeof(u.viamode)))
return -EFAULT;
break;
case VIAFB_GET_SAMM_INFO:
u.viasamm.samm_status = viafb_SAMM_ON;
if (viafb_SAMM_ON == 1) {
if (viafb_dual_fb) {
u.viasamm.size_prim = viaparinfo->fbmem_free;
u.viasamm.size_sec = viaparinfo1->fbmem_free;
} else {
if (viafb_second_size) {
u.viasamm.size_prim =
viaparinfo->fbmem_free -
viafb_second_size * 1024 * 1024;
u.viasamm.size_sec =
viafb_second_size * 1024 * 1024;
} else {
u.viasamm.size_prim =
viaparinfo->fbmem_free >> 1;
u.viasamm.size_sec =
(viaparinfo->fbmem_free >> 1);
}
}
u.viasamm.mem_base = viaparinfo->fbmem;
u.viasamm.offset_sec = viafb_second_offset;
} else {
u.viasamm.size_prim =
viaparinfo->memsize - viaparinfo->fbmem_used;
u.viasamm.size_sec = 0;
u.viasamm.mem_base = viaparinfo->fbmem;
u.viasamm.offset_sec = 0;
}
if (copy_to_user(argp, &u.viasamm, sizeof(u.viasamm)))
return -EFAULT;
break;
case VIAFB_TURN_ON_OUTPUT_DEVICE:
if (copy_from_user(&gpu32, argp, sizeof(gpu32)))
return -EFAULT;
if (gpu32 & CRT_Device)
via_set_state(VIA_CRT, VIA_STATE_ON);
if (gpu32 & DVI_Device)
viafb_dvi_enable();
if (gpu32 & LCD_Device)
viafb_lcd_enable();
break;
case VIAFB_TURN_OFF_OUTPUT_DEVICE:
if (copy_from_user(&gpu32, argp, sizeof(gpu32)))
return -EFAULT;
if (gpu32 & CRT_Device)
via_set_state(VIA_CRT, VIA_STATE_OFF);
if (gpu32 & DVI_Device)
viafb_dvi_disable();
if (gpu32 & LCD_Device)
viafb_lcd_disable();
break;
case VIAFB_GET_DEVICE:
u.active_dev.crt = viafb_CRT_ON;
u.active_dev.dvi = viafb_DVI_ON;
u.active_dev.lcd = viafb_LCD_ON;
u.active_dev.samm = viafb_SAMM_ON;
u.active_dev.primary_dev = viafb_primary_dev;
u.active_dev.lcd_dsp_cent = viafb_lcd_dsp_method;
u.active_dev.lcd_panel_id = viafb_lcd_panel_id;
u.active_dev.lcd_mode = viafb_lcd_mode;
u.active_dev.xres = viafb_hotplug_Xres;
u.active_dev.yres = viafb_hotplug_Yres;
u.active_dev.xres1 = viafb_second_xres;
u.active_dev.yres1 = viafb_second_yres;
u.active_dev.bpp = viafb_bpp;
u.active_dev.bpp1 = viafb_bpp1;
u.active_dev.refresh = viafb_refresh;
u.active_dev.refresh1 = viafb_refresh1;
u.active_dev.epia_dvi = viafb_platform_epia_dvi;
u.active_dev.lcd_dual_edge = viafb_device_lcd_dualedge;
u.active_dev.bus_width = viafb_bus_width;
if (copy_to_user(argp, &u.active_dev, sizeof(u.active_dev)))
return -EFAULT;
break;
case VIAFB_GET_DRIVER_VERSION:
u.driver_version.iMajorNum = VERSION_MAJOR;
u.driver_version.iKernelNum = VERSION_KERNEL;
u.driver_version.iOSNum = VERSION_OS;
u.driver_version.iMinorNum = VERSION_MINOR;
if (copy_to_user(argp, &u.driver_version,
sizeof(u.driver_version)))
return -EFAULT;
break;
case VIAFB_GET_DEVICE_INFO:
retrieve_device_setting(&u.viafb_setting);
if (copy_to_user(argp, &u.viafb_setting,
sizeof(u.viafb_setting)))
return -EFAULT;
break;
case VIAFB_GET_DEVICE_SUPPORT:
viafb_get_device_support_state(&state_info);
if (put_user(state_info, argp))
return -EFAULT;
break;
case VIAFB_GET_DEVICE_CONNECT:
viafb_get_device_connect_state(&state_info);
if (put_user(state_info, argp))
return -EFAULT;
break;
case VIAFB_GET_PANEL_SUPPORT_EXPAND:
state_info =
viafb_lcd_get_support_expand_state(info->var.xres,
info->var.yres);
if (put_user(state_info, argp))
return -EFAULT;
break;
case VIAFB_GET_DRIVER_NAME:
if (copy_to_user(argp, driver_name, sizeof(driver_name)))
return -EFAULT;
break;
case VIAFB_SET_GAMMA_LUT:
viafb_gamma_table = memdup_user(argp, 256 * sizeof(u32));
if (IS_ERR(viafb_gamma_table))
return PTR_ERR(viafb_gamma_table);
viafb_set_gamma_table(viafb_bpp, viafb_gamma_table);
kfree(viafb_gamma_table);
break;
case VIAFB_GET_GAMMA_LUT:
viafb_gamma_table = kmalloc_array(256, sizeof(u32),
GFP_KERNEL);
if (!viafb_gamma_table)
return -ENOMEM;
viafb_get_gamma_table(viafb_gamma_table);
if (copy_to_user(argp, viafb_gamma_table,
256 * sizeof(u32))) {
kfree(viafb_gamma_table);
return -EFAULT;
}
kfree(viafb_gamma_table);
break;
case VIAFB_GET_GAMMA_SUPPORT_STATE:
viafb_get_gamma_support_state(viafb_bpp, &state_info);
if (put_user(state_info, argp))
return -EFAULT;
break;
case VIAFB_SYNC_SURFACE:
DEBUG_MSG(KERN_INFO "lobo VIAFB_SYNC_SURFACE\n");
break;
case VIAFB_GET_DRIVER_CAPS:
break;
case VIAFB_GET_PANEL_MAX_SIZE:
if (copy_from_user(&u.panel_pos_size_para, argp,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
u.panel_pos_size_para.x = u.panel_pos_size_para.y = 0;
if (copy_to_user(argp, &u.panel_pos_size_para,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_GET_PANEL_MAX_POSITION:
if (copy_from_user(&u.panel_pos_size_para, argp,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
u.panel_pos_size_para.x = u.panel_pos_size_para.y = 0;
if (copy_to_user(argp, &u.panel_pos_size_para,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_GET_PANEL_POSITION:
if (copy_from_user(&u.panel_pos_size_para, argp,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
u.panel_pos_size_para.x = u.panel_pos_size_para.y = 0;
if (copy_to_user(argp, &u.panel_pos_size_para,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_GET_PANEL_SIZE:
if (copy_from_user(&u.panel_pos_size_para, argp,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
u.panel_pos_size_para.x = u.panel_pos_size_para.y = 0;
if (copy_to_user(argp, &u.panel_pos_size_para,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_SET_PANEL_POSITION:
if (copy_from_user(&u.panel_pos_size_para, argp,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
case VIAFB_SET_PANEL_SIZE:
if (copy_from_user(&u.panel_pos_size_para, argp,
sizeof(u.panel_pos_size_para)))
return -EFAULT;
break;
default:
return -EINVAL;
}
return 0;
}
static void viafb_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
struct viafb_par *viapar = info->par;
struct viafb_shared *shared = viapar->shared;
u32 fg_color;
u8 rop;
if (info->flags & FBINFO_HWACCEL_DISABLED || !shared->hw_bitblt) {
cfb_fillrect(info, rect);
return;
}
if (!rect->width || !rect->height)
return;
if (info->fix.visual == FB_VISUAL_TRUECOLOR)
fg_color = ((u32 *)info->pseudo_palette)[rect->color];
else
fg_color = rect->color;
if (rect->rop == ROP_XOR)
rop = 0x5A;
else
rop = 0xF0;
DEBUG_MSG(KERN_DEBUG "viafb 2D engine: fillrect\n");
if (shared->hw_bitblt(shared->vdev->engine_mmio, VIA_BITBLT_FILL,
rect->width, rect->height, info->var.bits_per_pixel,
viapar->vram_addr, info->fix.line_length, rect->dx, rect->dy,
NULL, 0, 0, 0, 0, fg_color, 0, rop))
cfb_fillrect(info, rect);
}
static void viafb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct viafb_par *viapar = info->par;
struct viafb_shared *shared = viapar->shared;
if (info->flags & FBINFO_HWACCEL_DISABLED || !shared->hw_bitblt) {
cfb_copyarea(info, area);
return;
}
if (!area->width || !area->height)
return;
DEBUG_MSG(KERN_DEBUG "viafb 2D engine: copyarea\n");
if (shared->hw_bitblt(shared->vdev->engine_mmio, VIA_BITBLT_COLOR,
area->width, area->height, info->var.bits_per_pixel,
viapar->vram_addr, info->fix.line_length, area->dx, area->dy,
NULL, viapar->vram_addr, info->fix.line_length,
area->sx, area->sy, 0, 0, 0))
cfb_copyarea(info, area);
}
static void viafb_imageblit(struct fb_info *info,
const struct fb_image *image)
{
struct viafb_par *viapar = info->par;
struct viafb_shared *shared = viapar->shared;
u32 fg_color = 0, bg_color = 0;
u8 op;
if (info->flags & FBINFO_HWACCEL_DISABLED || !shared->hw_bitblt ||
(image->depth != 1 && image->depth != viapar->depth)) {
cfb_imageblit(info, image);
return;
}
if (image->depth == 1) {
op = VIA_BITBLT_MONO;
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
fg_color =
((u32 *)info->pseudo_palette)[image->fg_color];
bg_color =
((u32 *)info->pseudo_palette)[image->bg_color];
} else {
fg_color = image->fg_color;
bg_color = image->bg_color;
}
} else
op = VIA_BITBLT_COLOR;
DEBUG_MSG(KERN_DEBUG "viafb 2D engine: imageblit\n");
if (shared->hw_bitblt(shared->vdev->engine_mmio, op,
image->width, image->height, info->var.bits_per_pixel,
viapar->vram_addr, info->fix.line_length, image->dx, image->dy,
(u32 *)image->data, 0, 0, 0, 0, fg_color, bg_color, 0))
cfb_imageblit(info, image);
}
static int viafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct viafb_par *viapar = info->par;
void __iomem *engine = viapar->shared->vdev->engine_mmio;
u32 temp, xx, yy, bg_color = 0, fg_color = 0,
chip_name = viapar->shared->chip_info.gfx_chip_name;
int i, j = 0, cur_size = 64;
if (info->flags & FBINFO_HWACCEL_DISABLED || info != viafbinfo)
return -ENODEV;
/* LCD ouput does not support hw cursors (at least on VN896) */
if ((chip_name == UNICHROME_CLE266 && viapar->iga_path == IGA2) ||
viafb_LCD_ON)
return -ENODEV;
viafb_show_hw_cursor(info, HW_Cursor_OFF);
if (cursor->set & FB_CUR_SETHOT) {
temp = (cursor->hot.x << 16) + cursor->hot.y;
writel(temp, engine + VIA_REG_CURSOR_ORG);
}
if (cursor->set & FB_CUR_SETPOS) {
yy = cursor->image.dy - info->var.yoffset;
xx = cursor->image.dx - info->var.xoffset;
temp = yy & 0xFFFF;
temp |= (xx << 16);
writel(temp, engine + VIA_REG_CURSOR_POS);
}
if (cursor->image.width <= 32 && cursor->image.height <= 32)
cur_size = 32;
else if (cursor->image.width <= 64 && cursor->image.height <= 64)
cur_size = 64;
else {
printk(KERN_WARNING "viafb_cursor: The cursor is too large "
"%dx%d", cursor->image.width, cursor->image.height);
return -ENXIO;
}
if (cursor->set & FB_CUR_SETSIZE) {
temp = readl(engine + VIA_REG_CURSOR_MODE);
if (cur_size == 32)
temp |= 0x2;
else
temp &= ~0x2;
writel(temp, engine + VIA_REG_CURSOR_MODE);
}
if (cursor->set & FB_CUR_SETCMAP) {
fg_color = cursor->image.fg_color;
bg_color = cursor->image.bg_color;
if (chip_name == UNICHROME_CX700 ||
chip_name == UNICHROME_VX800 ||
chip_name == UNICHROME_VX855 ||
chip_name == UNICHROME_VX900) {
fg_color =
((info->cmap.red[fg_color] & 0xFFC0) << 14) |
((info->cmap.green[fg_color] & 0xFFC0) << 4) |
((info->cmap.blue[fg_color] & 0xFFC0) >> 6);
bg_color =
((info->cmap.red[bg_color] & 0xFFC0) << 14) |
((info->cmap.green[bg_color] & 0xFFC0) << 4) |
((info->cmap.blue[bg_color] & 0xFFC0) >> 6);
} else {
fg_color =
((info->cmap.red[fg_color] & 0xFF00) << 8) |
(info->cmap.green[fg_color] & 0xFF00) |
((info->cmap.blue[fg_color] & 0xFF00) >> 8);
bg_color =
((info->cmap.red[bg_color] & 0xFF00) << 8) |
(info->cmap.green[bg_color] & 0xFF00) |
((info->cmap.blue[bg_color] & 0xFF00) >> 8);
}
writel(bg_color, engine + VIA_REG_CURSOR_BG);
writel(fg_color, engine + VIA_REG_CURSOR_FG);
}
if (cursor->set & FB_CUR_SETSHAPE) {
struct {
u8 data[CURSOR_SIZE];
u32 bak[CURSOR_SIZE / 4];
} *cr_data = kzalloc(sizeof(*cr_data), GFP_ATOMIC);
int size = ((cursor->image.width + 7) >> 3) *
cursor->image.height;
if (!cr_data)
return -ENOMEM;
if (cur_size == 32) {
for (i = 0; i < (CURSOR_SIZE / 4); i++) {
cr_data->bak[i] = 0x0;
cr_data->bak[i + 1] = 0xFFFFFFFF;
i += 1;
}
} else {
for (i = 0; i < (CURSOR_SIZE / 4); i++) {
cr_data->bak[i] = 0x0;
cr_data->bak[i + 1] = 0x0;
cr_data->bak[i + 2] = 0xFFFFFFFF;
cr_data->bak[i + 3] = 0xFFFFFFFF;
i += 3;
}
}
switch (cursor->rop) {
case ROP_XOR:
for (i = 0; i < size; i++)
cr_data->data[i] = cursor->mask[i];
break;
case ROP_COPY:
for (i = 0; i < size; i++)
cr_data->data[i] = cursor->mask[i];
break;
default:
break;
}
if (cur_size == 32) {
for (i = 0; i < size; i++) {
cr_data->bak[j] = (u32) cr_data->data[i];
cr_data->bak[j + 1] = ~cr_data->bak[j];
j += 2;
}
} else {
for (i = 0; i < size; i++) {
cr_data->bak[j] = (u32) cr_data->data[i];
cr_data->bak[j + 1] = 0x0;
cr_data->bak[j + 2] = ~cr_data->bak[j];
cr_data->bak[j + 3] = ~cr_data->bak[j + 1];
j += 4;
}
}
memcpy_toio(viafbinfo->screen_base + viapar->shared->
cursor_vram_addr, cr_data->bak, CURSOR_SIZE);
kfree(cr_data);
}
if (cursor->enable)
viafb_show_hw_cursor(info, HW_Cursor_ON);
return 0;
}
static int viafb_sync(struct fb_info *info)
{
if (!(info->flags & FBINFO_HWACCEL_DISABLED))
viafb_wait_engine_idle(info);
return 0;
}
static int get_primary_device(void)
{
int primary_device = 0;
/* Rule: device on iga1 path are the primary device. */
if (viafb_SAMM_ON) {
if (viafb_CRT_ON) {
if (viaparinfo->shared->iga1_devices & VIA_CRT) {
DEBUG_MSG(KERN_INFO "CRT IGA Path:%d\n", IGA1);
primary_device = CRT_Device;
}
}
if (viafb_DVI_ON) {
if (viaparinfo->tmds_setting_info->iga_path == IGA1) {
DEBUG_MSG(KERN_INFO "DVI IGA Path:%d\n",
viaparinfo->
tmds_setting_info->iga_path);
primary_device = DVI_Device;
}
}
if (viafb_LCD_ON) {
if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
DEBUG_MSG(KERN_INFO "LCD IGA Path:%d\n",
viaparinfo->
lvds_setting_info->iga_path);
primary_device = LCD_Device;
}
}
if (viafb_LCD2_ON) {
if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
DEBUG_MSG(KERN_INFO "LCD2 IGA Path:%d\n",
viaparinfo->
lvds_setting_info2->iga_path);
primary_device = LCD2_Device;
}
}
}
return primary_device;
}
static void retrieve_device_setting(struct viafb_ioctl_setting
*setting_info)
{
/* get device status */
if (viafb_CRT_ON == 1)
setting_info->device_status = CRT_Device;
if (viafb_DVI_ON == 1)
setting_info->device_status |= DVI_Device;
if (viafb_LCD_ON == 1)
setting_info->device_status |= LCD_Device;
if (viafb_LCD2_ON == 1)
setting_info->device_status |= LCD2_Device;
setting_info->samm_status = viafb_SAMM_ON;
setting_info->primary_device = get_primary_device();
setting_info->first_dev_bpp = viafb_bpp;
setting_info->second_dev_bpp = viafb_bpp1;
setting_info->first_dev_refresh = viafb_refresh;
setting_info->second_dev_refresh = viafb_refresh1;
setting_info->first_dev_hor_res = viafb_hotplug_Xres;
setting_info->first_dev_ver_res = viafb_hotplug_Yres;
setting_info->second_dev_hor_res = viafb_second_xres;
setting_info->second_dev_ver_res = viafb_second_yres;
/* Get lcd attributes */
setting_info->lcd_attributes.display_center = viafb_lcd_dsp_method;
setting_info->lcd_attributes.panel_id = viafb_lcd_panel_id;
setting_info->lcd_attributes.lcd_mode = viafb_lcd_mode;
}
static int __init parse_active_dev(void)
{
viafb_CRT_ON = STATE_OFF;
viafb_DVI_ON = STATE_OFF;
viafb_LCD_ON = STATE_OFF;
viafb_LCD2_ON = STATE_OFF;
/* 1. Modify the active status of devices. */
/* 2. Keep the order of devices, so we can set corresponding
IGA path to devices in SAMM case. */
/* Note: The previous of active_dev is primary device,
and the following is secondary device. */
if (!viafb_active_dev) {
if (machine_is_olpc()) { /* LCD only */
viafb_LCD_ON = STATE_ON;
viafb_SAMM_ON = STATE_OFF;
} else {
viafb_CRT_ON = STATE_ON;
viafb_SAMM_ON = STATE_OFF;
}
} else if (!strcmp(viafb_active_dev, "CRT+DVI")) {
/* CRT+DVI */
viafb_CRT_ON = STATE_ON;
viafb_DVI_ON = STATE_ON;
viafb_primary_dev = CRT_Device;
} else if (!strcmp(viafb_active_dev, "DVI+CRT")) {
/* DVI+CRT */
viafb_CRT_ON = STATE_ON;
viafb_DVI_ON = STATE_ON;
viafb_primary_dev = DVI_Device;
} else if (!strcmp(viafb_active_dev, "CRT+LCD")) {
/* CRT+LCD */
viafb_CRT_ON = STATE_ON;
viafb_LCD_ON = STATE_ON;
viafb_primary_dev = CRT_Device;
} else if (!strcmp(viafb_active_dev, "LCD+CRT")) {
/* LCD+CRT */
viafb_CRT_ON = STATE_ON;
viafb_LCD_ON = STATE_ON;
viafb_primary_dev = LCD_Device;
} else if (!strcmp(viafb_active_dev, "DVI+LCD")) {
/* DVI+LCD */
viafb_DVI_ON = STATE_ON;
viafb_LCD_ON = STATE_ON;
viafb_primary_dev = DVI_Device;
} else if (!strcmp(viafb_active_dev, "LCD+DVI")) {
/* LCD+DVI */
viafb_DVI_ON = STATE_ON;
viafb_LCD_ON = STATE_ON;
viafb_primary_dev = LCD_Device;
} else if (!strcmp(viafb_active_dev, "LCD+LCD2")) {
viafb_LCD_ON = STATE_ON;
viafb_LCD2_ON = STATE_ON;
viafb_primary_dev = LCD_Device;
} else if (!strcmp(viafb_active_dev, "LCD2+LCD")) {
viafb_LCD_ON = STATE_ON;
viafb_LCD2_ON = STATE_ON;
viafb_primary_dev = LCD2_Device;
} else if (!strcmp(viafb_active_dev, "CRT")) {
/* CRT only */
viafb_CRT_ON = STATE_ON;
viafb_SAMM_ON = STATE_OFF;
} else if (!strcmp(viafb_active_dev, "DVI")) {
/* DVI only */
viafb_DVI_ON = STATE_ON;
viafb_SAMM_ON = STATE_OFF;
} else if (!strcmp(viafb_active_dev, "LCD")) {
/* LCD only */
viafb_LCD_ON = STATE_ON;
viafb_SAMM_ON = STATE_OFF;
} else
return -EINVAL;
return 0;
}
static int parse_port(char *opt_str, int *output_interface)
{
if (!strncmp(opt_str, "DVP0", 4))
*output_interface = INTERFACE_DVP0;
else if (!strncmp(opt_str, "DVP1", 4))
*output_interface = INTERFACE_DVP1;
else if (!strncmp(opt_str, "DFP_HIGHLOW", 11))
*output_interface = INTERFACE_DFP;
else if (!strncmp(opt_str, "DFP_HIGH", 8))
*output_interface = INTERFACE_DFP_HIGH;
else if (!strncmp(opt_str, "DFP_LOW", 7))
*output_interface = INTERFACE_DFP_LOW;
else
*output_interface = INTERFACE_NONE;
return 0;
}
static void parse_lcd_port(void)
{
parse_port(viafb_lcd_port, &viaparinfo->chip_info->lvds_chip_info.
output_interface);
/*Initialize to avoid unexpected behavior */
viaparinfo->chip_info->lvds_chip_info2.output_interface =
INTERFACE_NONE;
DEBUG_MSG(KERN_INFO "parse_lcd_port: viafb_lcd_port:%s,interface:%d\n",
viafb_lcd_port, viaparinfo->chip_info->lvds_chip_info.
output_interface);
}
static void parse_dvi_port(void)
{
parse_port(viafb_dvi_port, &viaparinfo->chip_info->tmds_chip_info.
output_interface);
DEBUG_MSG(KERN_INFO "parse_dvi_port: viafb_dvi_port:%s,interface:%d\n",
viafb_dvi_port, viaparinfo->chip_info->tmds_chip_info.
output_interface);
}
#ifdef CONFIG_FB_VIA_DIRECT_PROCFS
/*
* The proc filesystem read/write function, a simple proc implement to
* get/set the value of DPA DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
* DVP1Driving, DFPHigh, DFPLow CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2],
* CR9B, SR65, CR97, CR99
*/
static int viafb_dvp0_proc_show(struct seq_file *m, void *v)
{
u8 dvp0_data_dri = 0, dvp0_clk_dri = 0, dvp0 = 0;
dvp0_data_dri =
(viafb_read_reg(VIASR, SR2A) & BIT5) >> 4 |
(viafb_read_reg(VIASR, SR1B) & BIT1) >> 1;
dvp0_clk_dri =
(viafb_read_reg(VIASR, SR2A) & BIT4) >> 3 |
(viafb_read_reg(VIASR, SR1E) & BIT2) >> 2;
dvp0 = viafb_read_reg(VIACR, CR96) & 0x0f;
seq_printf(m, "%x %x %x\n", dvp0, dvp0_data_dri, dvp0_clk_dri);
return 0;
}
static int viafb_dvp0_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, viafb_dvp0_proc_show, NULL);
}
static ssize_t viafb_dvp0_proc_write(struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
char buf[20], *value, *pbuf;
u8 reg_val = 0;
unsigned long length, i;
if (count < 1)
return -EINVAL;
length = count > 20 ? 20 : count;
if (copy_from_user(&buf[0], buffer, length))
return -EFAULT;
buf[length - 1] = '\0'; /*Ensure end string */
pbuf = &buf[0];
for (i = 0; i < 3; i++) {
value = strsep(&pbuf, " ");
if (value != NULL) {
if (kstrtou8(value, 0, ®_val) < 0)
return -EINVAL;
DEBUG_MSG(KERN_INFO "DVP0:reg_val[%lu]=:%x\n", i,
reg_val);
switch (i) {
case 0:
viafb_write_reg_mask(CR96, VIACR,
reg_val, 0x0f);
break;
case 1:
viafb_write_reg_mask(SR2A, VIASR,
reg_val << 4, BIT5);
viafb_write_reg_mask(SR1B, VIASR,
reg_val << 1, BIT1);
break;
case 2:
viafb_write_reg_mask(SR2A, VIASR,
reg_val << 3, BIT4);
viafb_write_reg_mask(SR1E, VIASR,
reg_val << 2, BIT2);
break;
default:
break;
}
} else {
break;
}
}
return count;
}
static const struct proc_ops viafb_dvp0_proc_ops = {
.proc_open = viafb_dvp0_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = viafb_dvp0_proc_write,
};
static int viafb_dvp1_proc_show(struct seq_file *m, void *v)
{
u8 dvp1 = 0, dvp1_data_dri = 0, dvp1_clk_dri = 0;
dvp1 = viafb_read_reg(VIACR, CR9B) & 0x0f;
dvp1_data_dri = (viafb_read_reg(VIASR, SR65) & 0x0c) >> 2;
dvp1_clk_dri = viafb_read_reg(VIASR, SR65) & 0x03;
seq_printf(m, "%x %x %x\n", dvp1, dvp1_data_dri, dvp1_clk_dri);
return 0;
}
static int viafb_dvp1_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, viafb_dvp1_proc_show, NULL);
}
static ssize_t viafb_dvp1_proc_write(struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
char buf[20], *value, *pbuf;
u8 reg_val = 0;
unsigned long length, i;
if (count < 1)
return -EINVAL;
length = count > 20 ? 20 : count;
if (copy_from_user(&buf[0], buffer, length))
return -EFAULT;
buf[length - 1] = '\0'; /*Ensure end string */
pbuf = &buf[0];
for (i = 0; i < 3; i++) {
value = strsep(&pbuf, " ");
if (value != NULL) {
if (kstrtou8(value, 0, ®_val) < 0)
return -EINVAL;
switch (i) {
case 0:
viafb_write_reg_mask(CR9B, VIACR,
reg_val, 0x0f);
break;
case 1:
viafb_write_reg_mask(SR65, VIASR,
reg_val << 2, 0x0c);
break;
case 2:
viafb_write_reg_mask(SR65, VIASR,
reg_val, 0x03);
break;
default:
break;
}
} else {
break;
}
}
return count;
}
static const struct proc_ops viafb_dvp1_proc_ops = {
.proc_open = viafb_dvp1_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = viafb_dvp1_proc_write,
};
static int viafb_dfph_proc_show(struct seq_file *m, void *v)
{
u8 dfp_high = 0;
dfp_high = viafb_read_reg(VIACR, CR97) & 0x0f;
seq_printf(m, "%x\n", dfp_high);
return 0;
}
static int viafb_dfph_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, viafb_dfph_proc_show, NULL);
}
static ssize_t viafb_dfph_proc_write(struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
int err;
u8 reg_val;
err = kstrtou8_from_user(buffer, count, 0, ®_val);
if (err)
return err;
viafb_write_reg_mask(CR97, VIACR, reg_val, 0x0f);
return count;
}
static const struct proc_ops viafb_dfph_proc_ops = {
.proc_open = viafb_dfph_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = viafb_dfph_proc_write,
};
static int viafb_dfpl_proc_show(struct seq_file *m, void *v)
{
u8 dfp_low = 0;
dfp_low = viafb_read_reg(VIACR, CR99) & 0x0f;
seq_printf(m, "%x\n", dfp_low);
return 0;
}
static int viafb_dfpl_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, viafb_dfpl_proc_show, NULL);
}
static ssize_t viafb_dfpl_proc_write(struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
int err;
u8 reg_val;
err = kstrtou8_from_user(buffer, count, 0, ®_val);
if (err)
return err;
viafb_write_reg_mask(CR99, VIACR, reg_val, 0x0f);
return count;
}
static const struct proc_ops viafb_dfpl_proc_ops = {
.proc_open = viafb_dfpl_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = viafb_dfpl_proc_write,
};
static int viafb_vt1636_proc_show(struct seq_file *m, void *v)
{
u8 vt1636_08 = 0, vt1636_09 = 0;
switch (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
case VT1636_LVDS:
vt1636_08 =
viafb_gpio_i2c_read_lvds(viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info, 0x08) & 0x0f;
vt1636_09 =
viafb_gpio_i2c_read_lvds(viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info, 0x09) & 0x1f;
seq_printf(m, "%x %x\n", vt1636_08, vt1636_09);
break;
default:
break;
}
switch (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
case VT1636_LVDS:
vt1636_08 =
viafb_gpio_i2c_read_lvds(viaparinfo->lvds_setting_info2,
&viaparinfo->chip_info->lvds_chip_info2, 0x08) & 0x0f;
vt1636_09 =
viafb_gpio_i2c_read_lvds(viaparinfo->lvds_setting_info2,
&viaparinfo->chip_info->lvds_chip_info2, 0x09) & 0x1f;
seq_printf(m, " %x %x\n", vt1636_08, vt1636_09);
break;
default:
break;
}
return 0;
}
static int viafb_vt1636_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, viafb_vt1636_proc_show, NULL);
}
static ssize_t viafb_vt1636_proc_write(struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
char buf[30], *value, *pbuf;
struct IODATA reg_val;
unsigned long length, i;
if (count < 1)
return -EINVAL;
length = count > 30 ? 30 : count;
if (copy_from_user(&buf[0], buffer, length))
return -EFAULT;
buf[length - 1] = '\0'; /*Ensure end string */
pbuf = &buf[0];
switch (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
case VT1636_LVDS:
for (i = 0; i < 2; i++) {
value = strsep(&pbuf, " ");
if (value != NULL) {
if (kstrtou8(value, 0, ®_val.Data) < 0)
return -EINVAL;
switch (i) {
case 0:
reg_val.Index = 0x08;
reg_val.Mask = 0x0f;
viafb_gpio_i2c_write_mask_lvds
(viaparinfo->lvds_setting_info,
&viaparinfo->
chip_info->lvds_chip_info,
reg_val);
break;
case 1:
reg_val.Index = 0x09;
reg_val.Mask = 0x1f;
viafb_gpio_i2c_write_mask_lvds
(viaparinfo->lvds_setting_info,
&viaparinfo->
chip_info->lvds_chip_info,
reg_val);
break;
default:
break;
}
} else {
break;
}
}
break;
default:
break;
}
switch (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
case VT1636_LVDS:
for (i = 0; i < 2; i++) {
value = strsep(&pbuf, " ");
if (value != NULL) {
if (kstrtou8(value, 0, ®_val.Data) < 0)
return -EINVAL;
switch (i) {
case 0:
reg_val.Index = 0x08;
reg_val.Mask = 0x0f;
viafb_gpio_i2c_write_mask_lvds
(viaparinfo->lvds_setting_info2,
&viaparinfo->
chip_info->lvds_chip_info2,
reg_val);
break;
case 1:
reg_val.Index = 0x09;
reg_val.Mask = 0x1f;
viafb_gpio_i2c_write_mask_lvds
(viaparinfo->lvds_setting_info2,
&viaparinfo->
chip_info->lvds_chip_info2,
reg_val);
break;
default:
break;
}
} else {
break;
}
}
break;
default:
break;
}
return count;
}
static const struct proc_ops viafb_vt1636_proc_ops = {
.proc_open = viafb_vt1636_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = viafb_vt1636_proc_write,
};
#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */
static int __maybe_unused viafb_sup_odev_proc_show(struct seq_file *m, void *v)
{
via_odev_to_seq(m, supported_odev_map[
viaparinfo->shared->chip_info.gfx_chip_name]);
return 0;
}
static ssize_t odev_update(const char __user *buffer, size_t count, u32 *odev)
{
char buf[64], *ptr = buf;
u32 devices;
bool add, sub;
if (count < 1 || count > 63)
return -EINVAL;
if (copy_from_user(&buf[0], buffer, count))
return -EFAULT;
buf[count] = '\0';
add = buf[0] == '+';
sub = buf[0] == '-';
if (add || sub)
ptr++;
devices = via_parse_odev(ptr, &ptr);
if (*ptr == '\n')
ptr++;
if (*ptr != 0)
return -EINVAL;
if (add)
*odev |= devices;
else if (sub)
*odev &= ~devices;
else
*odev = devices;
return count;
}
static int viafb_iga1_odev_proc_show(struct seq_file *m, void *v)
{
via_odev_to_seq(m, viaparinfo->shared->iga1_devices);
return 0;
}
static int viafb_iga1_odev_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, viafb_iga1_odev_proc_show, NULL);
}
static ssize_t viafb_iga1_odev_proc_write(struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
u32 dev_on, dev_off, dev_old, dev_new;
ssize_t res;
dev_old = dev_new = viaparinfo->shared->iga1_devices;
res = odev_update(buffer, count, &dev_new);
if (res != count)
return res;
dev_off = dev_old & ~dev_new;
dev_on = dev_new & ~dev_old;
viaparinfo->shared->iga1_devices = dev_new;
viaparinfo->shared->iga2_devices &= ~dev_new;
via_set_state(dev_off, VIA_STATE_OFF);
via_set_source(dev_new, IGA1);
via_set_state(dev_on, VIA_STATE_ON);
return res;
}
static const struct proc_ops viafb_iga1_odev_proc_ops = {
.proc_open = viafb_iga1_odev_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = viafb_iga1_odev_proc_write,
};
static int viafb_iga2_odev_proc_show(struct seq_file *m, void *v)
{
via_odev_to_seq(m, viaparinfo->shared->iga2_devices);
return 0;
}
static int viafb_iga2_odev_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, viafb_iga2_odev_proc_show, NULL);
}
static ssize_t viafb_iga2_odev_proc_write(struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
u32 dev_on, dev_off, dev_old, dev_new;
ssize_t res;
dev_old = dev_new = viaparinfo->shared->iga2_devices;
res = odev_update(buffer, count, &dev_new);
if (res != count)
return res;
dev_off = dev_old & ~dev_new;
dev_on = dev_new & ~dev_old;
viaparinfo->shared->iga2_devices = dev_new;
viaparinfo->shared->iga1_devices &= ~dev_new;
via_set_state(dev_off, VIA_STATE_OFF);
via_set_source(dev_new, IGA2);
via_set_state(dev_on, VIA_STATE_ON);
return res;
}
static const struct proc_ops viafb_iga2_odev_proc_ops = {
.proc_open = viafb_iga2_odev_proc_open,
.proc_read = seq_read,
.proc_lseek = seq_lseek,
.proc_release = single_release,
.proc_write = viafb_iga2_odev_proc_write,
};
#define IS_VT1636(lvds_chip) ((lvds_chip).lvds_chip_name == VT1636_LVDS)
static void viafb_init_proc(struct viafb_shared *shared)
{
struct proc_dir_entry *iga1_entry, *iga2_entry,
*viafb_entry = proc_mkdir("viafb", NULL);
shared->proc_entry = viafb_entry;
if (viafb_entry) {
#ifdef CONFIG_FB_VIA_DIRECT_PROCFS
proc_create("dvp0", 0, viafb_entry, &viafb_dvp0_proc_ops);
proc_create("dvp1", 0, viafb_entry, &viafb_dvp1_proc_ops);
proc_create("dfph", 0, viafb_entry, &viafb_dfph_proc_ops);
proc_create("dfpl", 0, viafb_entry, &viafb_dfpl_proc_ops);
if (IS_VT1636(shared->chip_info.lvds_chip_info)
|| IS_VT1636(shared->chip_info.lvds_chip_info2))
proc_create("vt1636", 0, viafb_entry,
&viafb_vt1636_proc_ops);
#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */
proc_create_single("supported_output_devices", 0, viafb_entry,
viafb_sup_odev_proc_show);
iga1_entry = proc_mkdir("iga1", viafb_entry);
shared->iga1_proc_entry = iga1_entry;
proc_create("output_devices", 0, iga1_entry,
&viafb_iga1_odev_proc_ops);
iga2_entry = proc_mkdir("iga2", viafb_entry);
shared->iga2_proc_entry = iga2_entry;
proc_create("output_devices", 0, iga2_entry,
&viafb_iga2_odev_proc_ops);
}
}
static void viafb_remove_proc(struct viafb_shared *shared)
{
struct proc_dir_entry *viafb_entry = shared->proc_entry;
if (!viafb_entry)
return;
remove_proc_entry("output_devices", shared->iga2_proc_entry);
remove_proc_entry("iga2", viafb_entry);
remove_proc_entry("output_devices", shared->iga1_proc_entry);
remove_proc_entry("iga1", viafb_entry);
remove_proc_entry("supported_output_devices", viafb_entry);
#ifdef CONFIG_FB_VIA_DIRECT_PROCFS
remove_proc_entry("dvp0", viafb_entry);/* parent dir */
remove_proc_entry("dvp1", viafb_entry);
remove_proc_entry("dfph", viafb_entry);
remove_proc_entry("dfpl", viafb_entry);
if (IS_VT1636(shared->chip_info.lvds_chip_info)
|| IS_VT1636(shared->chip_info.lvds_chip_info2))
remove_proc_entry("vt1636", viafb_entry);
#endif /* CONFIG_FB_VIA_DIRECT_PROCFS */
remove_proc_entry("viafb", NULL);
}
#undef IS_VT1636
static int parse_mode(const char *str, u32 devices, u32 *xres, u32 *yres)
{
const struct fb_videomode *mode = NULL;
char *ptr;
if (!str) {
if (devices == VIA_CRT)
mode = via_aux_get_preferred_mode(
viaparinfo->shared->i2c_26);
else if (devices == VIA_DVP1)
mode = via_aux_get_preferred_mode(
viaparinfo->shared->i2c_31);
if (mode) {
*xres = mode->xres;
*yres = mode->yres;
} else if (machine_is_olpc()) {
*xres = 1200;
*yres = 900;
} else {
*xres = 640;
*yres = 480;
}
return 0;
}
*xres = simple_strtoul(str, &ptr, 10);
if (ptr[0] != 'x')
return -EINVAL;
*yres = simple_strtoul(&ptr[1], &ptr, 10);
if (ptr[0])
return -EINVAL;
return 0;
}
#ifdef CONFIG_PM
static int viafb_suspend(void *unused)
{
console_lock();
fb_set_suspend(viafbinfo, 1);
viafb_sync(viafbinfo);
console_unlock();
return 0;
}
static int viafb_resume(void *unused)
{
console_lock();
if (viaparinfo->shared->vdev->engine_mmio)
viafb_reset_engine(viaparinfo);
viafb_set_par(viafbinfo);
if (viafb_dual_fb)
viafb_set_par(viafbinfo1);
fb_set_suspend(viafbinfo, 0);
console_unlock();
return 0;
}
static struct viafb_pm_hooks viafb_fb_pm_hooks = {
.suspend = viafb_suspend,
.resume = viafb_resume
};
#endif
static void i2c_bus_probe(struct viafb_shared *shared)
{
/* should be always CRT */
printk(KERN_INFO "viafb: Probing I2C bus 0x26\n");
shared->i2c_26 = via_aux_probe(viafb_find_i2c_adapter(VIA_PORT_26));
/* seems to be usually DVP1 */
printk(KERN_INFO "viafb: Probing I2C bus 0x31\n");
shared->i2c_31 = via_aux_probe(viafb_find_i2c_adapter(VIA_PORT_31));
/* FIXME: what is this? */
if (!machine_is_olpc()) {
printk(KERN_INFO "viafb: Probing I2C bus 0x2C\n");
shared->i2c_2C = via_aux_probe(viafb_find_i2c_adapter(VIA_PORT_2C));
}
printk(KERN_INFO "viafb: Finished I2C bus probing");
}
static void i2c_bus_free(struct viafb_shared *shared)
{
via_aux_free(shared->i2c_26);
via_aux_free(shared->i2c_31);
via_aux_free(shared->i2c_2C);
}
int via_fb_pci_probe(struct viafb_dev *vdev)
{
u32 default_xres, default_yres;
struct fb_var_screeninfo default_var;
int rc;
u32 viafb_par_length;
DEBUG_MSG(KERN_INFO "VIAFB PCI Probe!!\n");
memset(&default_var, 0, sizeof(default_var));
viafb_par_length = ALIGN(sizeof(struct viafb_par), BITS_PER_LONG/8);
/* Allocate fb_info and ***_par here, also including some other needed
* variables
*/
viafbinfo = framebuffer_alloc(viafb_par_length +
ALIGN(sizeof(struct viafb_shared), BITS_PER_LONG/8),
&vdev->pdev->dev);
if (!viafbinfo)
return -ENOMEM;
viaparinfo = (struct viafb_par *)viafbinfo->par;
viaparinfo->shared = viafbinfo->par + viafb_par_length;
viaparinfo->shared->vdev = vdev;
viaparinfo->vram_addr = 0;
viaparinfo->tmds_setting_info = &viaparinfo->shared->tmds_setting_info;
viaparinfo->lvds_setting_info = &viaparinfo->shared->lvds_setting_info;
viaparinfo->lvds_setting_info2 =
&viaparinfo->shared->lvds_setting_info2;
viaparinfo->chip_info = &viaparinfo->shared->chip_info;
i2c_bus_probe(viaparinfo->shared);
if (viafb_dual_fb)
viafb_SAMM_ON = 1;
parse_lcd_port();
parse_dvi_port();
viafb_init_chip_info(vdev->chip_type);
/*
* The framebuffer will have been successfully mapped by
* the core (or we'd not be here), but we still need to
* set up our own accounting.
*/
viaparinfo->fbmem = vdev->fbmem_start;
viaparinfo->memsize = vdev->fbmem_len;
viaparinfo->fbmem_free = viaparinfo->memsize;
viaparinfo->fbmem_used = 0;
viafbinfo->screen_base = vdev->fbmem;
viafbinfo->fix.mmio_start = vdev->engine_start;
viafbinfo->fix.mmio_len = vdev->engine_len;
viafbinfo->node = 0;
viafbinfo->fbops = &viafb_ops;
viafbinfo->flags = FBINFO_HWACCEL_YPAN;
viafbinfo->pseudo_palette = pseudo_pal;
if (viafb_accel && !viafb_setup_engine(viafbinfo)) {
viafbinfo->flags |= FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT;
default_var.accel_flags = FB_ACCELF_TEXT;
} else {
viafbinfo->flags |= FBINFO_HWACCEL_DISABLED;
default_var.accel_flags = 0;
}
if (viafb_second_size && (viafb_second_size < 8)) {
viafb_second_offset = viaparinfo->fbmem_free -
viafb_second_size * 1024 * 1024;
} else {
viafb_second_size = 8;
viafb_second_offset = viaparinfo->fbmem_free -
viafb_second_size * 1024 * 1024;
}
parse_mode(viafb_mode, viaparinfo->shared->iga1_devices,
&default_xres, &default_yres);
if (viafb_SAMM_ON == 1)
parse_mode(viafb_mode1, viaparinfo->shared->iga2_devices,
&viafb_second_xres, &viafb_second_yres);
default_var.xres = default_xres;
default_var.yres = default_yres;
default_var.xres_virtual = default_xres;
default_var.yres_virtual = default_yres;
default_var.bits_per_pixel = viafb_bpp;
viafb_fill_var_timing_info(&default_var, viafb_get_best_mode(
default_var.xres, default_var.yres, viafb_refresh));
viafb_setup_fixinfo(&viafbinfo->fix, viaparinfo);
viafbinfo->var = default_var;
if (viafb_dual_fb) {
viafbinfo1 = framebuffer_alloc(viafb_par_length,
&vdev->pdev->dev);
if (!viafbinfo1) {
rc = -ENOMEM;
goto out_fb_release;
}
viaparinfo1 = viafbinfo1->par;
memcpy(viaparinfo1, viaparinfo, viafb_par_length);
viaparinfo1->vram_addr = viafb_second_offset;
viaparinfo1->memsize = viaparinfo->memsize -
viafb_second_offset;
viaparinfo->memsize = viafb_second_offset;
viaparinfo1->fbmem = viaparinfo->fbmem + viafb_second_offset;
viaparinfo1->fbmem_used = viaparinfo->fbmem_used;
viaparinfo1->fbmem_free = viaparinfo1->memsize -
viaparinfo1->fbmem_used;
viaparinfo->fbmem_free = viaparinfo->memsize;
viaparinfo->fbmem_used = 0;
viaparinfo->iga_path = IGA1;
viaparinfo1->iga_path = IGA2;
memcpy(viafbinfo1, viafbinfo, sizeof(struct fb_info));
viafbinfo1->par = viaparinfo1;
viafbinfo1->screen_base = viafbinfo->screen_base +
viafb_second_offset;
default_var.xres = viafb_second_xres;
default_var.yres = viafb_second_yres;
default_var.xres_virtual = viafb_second_xres;
default_var.yres_virtual = viafb_second_yres;
default_var.bits_per_pixel = viafb_bpp1;
viafb_fill_var_timing_info(&default_var, viafb_get_best_mode(
default_var.xres, default_var.yres, viafb_refresh1));
viafb_setup_fixinfo(&viafbinfo1->fix, viaparinfo1);
viafb_check_var(&default_var, viafbinfo1);
viafbinfo1->var = default_var;
viafb_update_fix(viafbinfo1);
viaparinfo1->depth = fb_get_color_depth(&viafbinfo1->var,
&viafbinfo1->fix);
}
viafb_check_var(&viafbinfo->var, viafbinfo);
viafb_update_fix(viafbinfo);
viaparinfo->depth = fb_get_color_depth(&viafbinfo->var,
&viafbinfo->fix);
default_var.activate = FB_ACTIVATE_NOW;
rc = fb_alloc_cmap(&viafbinfo->cmap, 256, 0);
if (rc)
goto out_fb1_release;
if (viafb_dual_fb && (viafb_primary_dev == LCD_Device)
&& (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)) {
rc = register_framebuffer(viafbinfo1);
if (rc)
goto out_dealloc_cmap;
}
rc = register_framebuffer(viafbinfo);
if (rc)
goto out_fb1_unreg_lcd_cle266;
if (viafb_dual_fb && ((viafb_primary_dev != LCD_Device)
|| (viaparinfo->chip_info->gfx_chip_name !=
UNICHROME_CLE266))) {
rc = register_framebuffer(viafbinfo1);
if (rc)
goto out_fb_unreg;
}
DEBUG_MSG(KERN_INFO "fb%d: %s frame buffer device %dx%d-%dbpp\n",
viafbinfo->node, viafbinfo->fix.id, default_var.xres,
default_var.yres, default_var.bits_per_pixel);
viafb_init_proc(viaparinfo->shared);
viafb_init_dac(IGA2);
#ifdef CONFIG_PM
viafb_pm_register(&viafb_fb_pm_hooks);
#endif
return 0;
out_fb_unreg:
unregister_framebuffer(viafbinfo);
out_fb1_unreg_lcd_cle266:
if (viafb_dual_fb && (viafb_primary_dev == LCD_Device)
&& (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266))
unregister_framebuffer(viafbinfo1);
out_dealloc_cmap:
fb_dealloc_cmap(&viafbinfo->cmap);
out_fb1_release:
framebuffer_release(viafbinfo1);
out_fb_release:
i2c_bus_free(viaparinfo->shared);
framebuffer_release(viafbinfo);
return rc;
}
void via_fb_pci_remove(struct pci_dev *pdev)
{
DEBUG_MSG(KERN_INFO "via_pci_remove!\n");
fb_dealloc_cmap(&viafbinfo->cmap);
unregister_framebuffer(viafbinfo);
if (viafb_dual_fb)
unregister_framebuffer(viafbinfo1);
viafb_remove_proc(viaparinfo->shared);
i2c_bus_free(viaparinfo->shared);
framebuffer_release(viafbinfo);
if (viafb_dual_fb)
framebuffer_release(viafbinfo1);
}
#ifndef MODULE
static int __init viafb_setup(void)
{
char *this_opt;
char *options;
DEBUG_MSG(KERN_INFO "viafb_setup!\n");
if (fb_get_options("viafb", &options))
return -ENODEV;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strncmp(this_opt, "viafb_mode1=", 12)) {
viafb_mode1 = kstrdup(this_opt + 12, GFP_KERNEL);
if (!viafb_mode1)
return -ENOMEM;
} else if (!strncmp(this_opt, "viafb_mode=", 11)) {
viafb_mode = kstrdup(this_opt + 11, GFP_KERNEL);
if (!viafb_mode)
return -ENOMEM;
} else if (!strncmp(this_opt, "viafb_bpp1=", 11)) {
if (kstrtouint(this_opt + 11, 0, &viafb_bpp1) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_bpp=", 10)) {
if (kstrtouint(this_opt + 10, 0, &viafb_bpp) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_refresh1=", 15)) {
if (kstrtoint(this_opt + 15, 0, &viafb_refresh1) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_refresh=", 14)) {
if (kstrtoint(this_opt + 14, 0, &viafb_refresh) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_lcd_dsp_method=", 21)) {
if (kstrtoint(this_opt + 21, 0,
&viafb_lcd_dsp_method) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_lcd_panel_id=", 19)) {
if (kstrtoint(this_opt + 19, 0,
&viafb_lcd_panel_id) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_accel=", 12)) {
if (kstrtoint(this_opt + 12, 0, &viafb_accel) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_SAMM_ON=", 14)) {
if (kstrtoint(this_opt + 14, 0, &viafb_SAMM_ON) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_active_dev=", 17)) {
viafb_active_dev = kstrdup(this_opt + 17, GFP_KERNEL);
if (!viafb_active_dev)
return -ENOMEM;
} else if (!strncmp(this_opt,
"viafb_display_hardware_layout=", 30)) {
if (kstrtoint(this_opt + 30, 0,
&viafb_display_hardware_layout) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_second_size=", 18)) {
if (kstrtoint(this_opt + 18, 0, &viafb_second_size) < 0)
return -EINVAL;
} else if (!strncmp(this_opt,
"viafb_platform_epia_dvi=", 24)) {
if (kstrtoint(this_opt + 24, 0,
&viafb_platform_epia_dvi) < 0)
return -EINVAL;
} else if (!strncmp(this_opt,
"viafb_device_lcd_dualedge=", 26)) {
if (kstrtoint(this_opt + 26, 0,
&viafb_device_lcd_dualedge) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_bus_width=", 16)) {
if (kstrtoint(this_opt + 16, 0, &viafb_bus_width) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_lcd_mode=", 15)) {
if (kstrtoint(this_opt + 15, 0, &viafb_lcd_mode) < 0)
return -EINVAL;
} else if (!strncmp(this_opt, "viafb_lcd_port=", 15)) {
viafb_lcd_port = kstrdup(this_opt + 15, GFP_KERNEL);
if (!viafb_lcd_port)
return -ENOMEM;
} else if (!strncmp(this_opt, "viafb_dvi_port=", 15)) {
viafb_dvi_port = kstrdup(this_opt + 15, GFP_KERNEL);
if (!viafb_dvi_port)
return -ENOMEM;
}
}
return 0;
}
#endif
/*
* These are called out of via-core for now.
*/
int __init viafb_init(void)
{
u32 dummy_x, dummy_y;
int r = 0;
if (machine_is_olpc())
/* Apply XO-1.5-specific configuration. */
viafb_lcd_panel_id = 23;
#ifndef MODULE
r = viafb_setup();
if (r < 0)
return r;
#endif
if (parse_mode(viafb_mode, 0, &dummy_x, &dummy_y)
|| !viafb_get_best_mode(dummy_x, dummy_y, viafb_refresh)
|| parse_mode(viafb_mode1, 0, &dummy_x, &dummy_y)
|| !viafb_get_best_mode(dummy_x, dummy_y, viafb_refresh1)
|| viafb_bpp < 0 || viafb_bpp > 32
|| viafb_bpp1 < 0 || viafb_bpp1 > 32
|| parse_active_dev())
return -EINVAL;
printk(KERN_INFO
"VIA Graphics Integration Chipset framebuffer %d.%d initializing\n",
VERSION_MAJOR, VERSION_MINOR);
return r;
}
void __exit viafb_exit(void)
{
DEBUG_MSG(KERN_INFO "viafb_exit!\n");
}
static struct fb_ops viafb_ops = {
.owner = THIS_MODULE,
.fb_open = viafb_open,
.fb_release = viafb_release,
.fb_check_var = viafb_check_var,
.fb_set_par = viafb_set_par,
.fb_setcolreg = viafb_setcolreg,
.fb_pan_display = viafb_pan_display,
.fb_blank = viafb_blank,
.fb_fillrect = viafb_fillrect,
.fb_copyarea = viafb_copyarea,
.fb_imageblit = viafb_imageblit,
.fb_cursor = viafb_cursor,
.fb_ioctl = viafb_ioctl,
.fb_sync = viafb_sync,
};
#ifdef MODULE
module_param(viafb_mode, charp, S_IRUSR);
MODULE_PARM_DESC(viafb_mode, "Set resolution (default=640x480)");
module_param(viafb_mode1, charp, S_IRUSR);
MODULE_PARM_DESC(viafb_mode1, "Set resolution (default=640x480)");
module_param(viafb_bpp, int, S_IRUSR);
MODULE_PARM_DESC(viafb_bpp, "Set color depth (default=32bpp)");
module_param(viafb_bpp1, int, S_IRUSR);
MODULE_PARM_DESC(viafb_bpp1, "Set color depth (default=32bpp)");
module_param(viafb_refresh, int, S_IRUSR);
MODULE_PARM_DESC(viafb_refresh,
"Set CRT viafb_refresh rate (default = 60)");
module_param(viafb_refresh1, int, S_IRUSR);
MODULE_PARM_DESC(viafb_refresh1,
"Set CRT refresh rate (default = 60)");
module_param(viafb_lcd_panel_id, int, S_IRUSR);
MODULE_PARM_DESC(viafb_lcd_panel_id,
"Set Flat Panel type(Default=1024x768)");
module_param(viafb_lcd_dsp_method, int, S_IRUSR);
MODULE_PARM_DESC(viafb_lcd_dsp_method,
"Set Flat Panel display scaling method.(Default=Expansion)");
module_param(viafb_SAMM_ON, int, S_IRUSR);
MODULE_PARM_DESC(viafb_SAMM_ON,
"Turn on/off flag of SAMM(Default=OFF)");
module_param(viafb_accel, int, S_IRUSR);
MODULE_PARM_DESC(viafb_accel,
"Set 2D Hardware Acceleration: 0 = OFF, 1 = ON (default)");
module_param(viafb_active_dev, charp, S_IRUSR);
MODULE_PARM_DESC(viafb_active_dev, "Specify active devices.");
module_param(viafb_display_hardware_layout, int, S_IRUSR);
MODULE_PARM_DESC(viafb_display_hardware_layout,
"Display Hardware Layout (LCD Only, DVI Only...,etc)");
module_param(viafb_second_size, int, S_IRUSR);
MODULE_PARM_DESC(viafb_second_size,
"Set secondary device memory size");
module_param(viafb_dual_fb, int, S_IRUSR);
MODULE_PARM_DESC(viafb_dual_fb,
"Turn on/off flag of dual framebuffer devices.(Default = OFF)");
module_param(viafb_platform_epia_dvi, int, S_IRUSR);
MODULE_PARM_DESC(viafb_platform_epia_dvi,
"Turn on/off flag of DVI devices on EPIA board.(Default = OFF)");
module_param(viafb_device_lcd_dualedge, int, S_IRUSR);
MODULE_PARM_DESC(viafb_device_lcd_dualedge,
"Turn on/off flag of dual edge panel.(Default = OFF)");
module_param(viafb_bus_width, int, S_IRUSR);
MODULE_PARM_DESC(viafb_bus_width,
"Set bus width of panel.(Default = 12)");
module_param(viafb_lcd_mode, int, S_IRUSR);
MODULE_PARM_DESC(viafb_lcd_mode,
"Set Flat Panel mode(Default=OPENLDI)");
module_param(viafb_lcd_port, charp, S_IRUSR);
MODULE_PARM_DESC(viafb_lcd_port, "Specify LCD output port.");
module_param(viafb_dvi_port, charp, S_IRUSR);
MODULE_PARM_DESC(viafb_dvi_port, "Specify DVI output port.");
MODULE_LICENSE("GPL");
#endif
| linux-master | drivers/video/fbdev/via/viafbdev.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* driver for VIA VT1622(M) Digital TV Encoder
*/
#include <linux/slab.h>
#include "via_aux.h"
static const char *name = "VT1622(M) Digital TV Encoder";
static void probe(struct via_aux_bus *bus, u8 addr)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = addr,
.name = name};
u8 tmp;
if (!via_aux_read(&drv, 0x1B, &tmp, 1) || tmp != 0x03)
return;
printk(KERN_INFO "viafb: Found %s at address 0x%x\n", name, addr);
via_aux_add(&drv);
}
void via_aux_vt1622_probe(struct via_aux_bus *bus)
{
probe(bus, 0x20);
probe(bus, 0x21);
}
| linux-master | drivers/video/fbdev/via/via_aux_vt1622.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* driver for VIA VT1631 LVDS Transmitter
*/
#include <linux/slab.h>
#include "via_aux.h"
static const char *name = "VT1631 LVDS Transmitter";
void via_aux_vt1631_probe(struct via_aux_bus *bus)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = 0x38,
.name = name};
/* check vendor id and device id */
const u8 id[] = {0x06, 0x11, 0x91, 0x31}, len = ARRAY_SIZE(id);
u8 tmp[ARRAY_SIZE(id)];
if (!via_aux_read(&drv, 0x00, tmp, len) || memcmp(id, tmp, len))
return;
printk(KERN_INFO "viafb: Found %s\n", name);
via_aux_add(&drv);
}
| linux-master | drivers/video/fbdev/via/via_aux_vt1631.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Support for viafb GPIO ports.
*
* Copyright 2009 Jonathan Corbet <[email protected]>
*/
#include <linux/spinlock.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/machine.h>
#include <linux/platform_device.h>
#include <linux/via-core.h>
#include <linux/export.h>
#include "via-gpio.h"
/*
* The ports we know about. Note that the port-25 gpios are not
* mentioned in the datasheet.
*/
struct viafb_gpio {
char *vg_name; /* Data sheet name */
u16 vg_io_port;
u8 vg_port_index;
int vg_mask_shift;
};
static struct viafb_gpio viafb_all_gpios[] = {
{
.vg_name = "VGPIO0", /* Guess - not in datasheet */
.vg_io_port = VIASR,
.vg_port_index = 0x25,
.vg_mask_shift = 1
},
{
.vg_name = "VGPIO1",
.vg_io_port = VIASR,
.vg_port_index = 0x25,
.vg_mask_shift = 0
},
{
.vg_name = "VGPIO2", /* aka DISPCLKI0 */
.vg_io_port = VIASR,
.vg_port_index = 0x2c,
.vg_mask_shift = 1
},
{
.vg_name = "VGPIO3", /* aka DISPCLKO0 */
.vg_io_port = VIASR,
.vg_port_index = 0x2c,
.vg_mask_shift = 0
},
{
.vg_name = "VGPIO4", /* DISPCLKI1 */
.vg_io_port = VIASR,
.vg_port_index = 0x3d,
.vg_mask_shift = 1
},
{
.vg_name = "VGPIO5", /* DISPCLKO1 */
.vg_io_port = VIASR,
.vg_port_index = 0x3d,
.vg_mask_shift = 0
},
};
#define VIAFB_NUM_GPIOS ARRAY_SIZE(viafb_all_gpios)
/*
* This structure controls the active GPIOs, which may be a subset
* of those which are known.
*/
struct viafb_gpio_cfg {
struct gpio_chip gpio_chip;
struct viafb_dev *vdev;
struct viafb_gpio *active_gpios[VIAFB_NUM_GPIOS];
const char *gpio_names[VIAFB_NUM_GPIOS];
};
/*
* GPIO access functions
*/
static void via_gpio_set(struct gpio_chip *chip, unsigned int nr,
int value)
{
struct viafb_gpio_cfg *cfg = gpiochip_get_data(chip);
u8 reg;
struct viafb_gpio *gpio;
unsigned long flags;
spin_lock_irqsave(&cfg->vdev->reg_lock, flags);
gpio = cfg->active_gpios[nr];
reg = via_read_reg(VIASR, gpio->vg_port_index);
reg |= 0x40 << gpio->vg_mask_shift; /* output enable */
if (value)
reg |= 0x10 << gpio->vg_mask_shift;
else
reg &= ~(0x10 << gpio->vg_mask_shift);
via_write_reg(VIASR, gpio->vg_port_index, reg);
spin_unlock_irqrestore(&cfg->vdev->reg_lock, flags);
}
static int via_gpio_dir_out(struct gpio_chip *chip, unsigned int nr,
int value)
{
via_gpio_set(chip, nr, value);
return 0;
}
/*
* Set the input direction. I'm not sure this is right; we should
* be able to do input without disabling output.
*/
static int via_gpio_dir_input(struct gpio_chip *chip, unsigned int nr)
{
struct viafb_gpio_cfg *cfg = gpiochip_get_data(chip);
struct viafb_gpio *gpio;
unsigned long flags;
spin_lock_irqsave(&cfg->vdev->reg_lock, flags);
gpio = cfg->active_gpios[nr];
via_write_reg_mask(VIASR, gpio->vg_port_index, 0,
0x40 << gpio->vg_mask_shift);
spin_unlock_irqrestore(&cfg->vdev->reg_lock, flags);
return 0;
}
static int via_gpio_get(struct gpio_chip *chip, unsigned int nr)
{
struct viafb_gpio_cfg *cfg = gpiochip_get_data(chip);
u8 reg;
struct viafb_gpio *gpio;
unsigned long flags;
spin_lock_irqsave(&cfg->vdev->reg_lock, flags);
gpio = cfg->active_gpios[nr];
reg = via_read_reg(VIASR, gpio->vg_port_index);
spin_unlock_irqrestore(&cfg->vdev->reg_lock, flags);
return !!(reg & (0x04 << gpio->vg_mask_shift));
}
static struct viafb_gpio_cfg viafb_gpio_config = {
.gpio_chip = {
.label = "VIAFB onboard GPIO",
.owner = THIS_MODULE,
.direction_output = via_gpio_dir_out,
.set = via_gpio_set,
.direction_input = via_gpio_dir_input,
.get = via_gpio_get,
.base = -1,
.ngpio = 0,
.can_sleep = 0
}
};
/*
* Manage the software enable bit.
*/
static void viafb_gpio_enable(struct viafb_gpio *gpio)
{
via_write_reg_mask(VIASR, gpio->vg_port_index, 0x02, 0x02);
}
static void viafb_gpio_disable(struct viafb_gpio *gpio)
{
via_write_reg_mask(VIASR, gpio->vg_port_index, 0, 0x02);
}
#ifdef CONFIG_PM
static int viafb_gpio_suspend(void *private)
{
return 0;
}
static int viafb_gpio_resume(void *private)
{
int i;
for (i = 0; i < viafb_gpio_config.gpio_chip.ngpio; i += 2)
viafb_gpio_enable(viafb_gpio_config.active_gpios[i]);
return 0;
}
static struct viafb_pm_hooks viafb_gpio_pm_hooks = {
.suspend = viafb_gpio_suspend,
.resume = viafb_gpio_resume
};
#endif /* CONFIG_PM */
static struct gpiod_lookup_table viafb_gpio_table = {
.dev_id = "viafb-camera",
.table = {
GPIO_LOOKUP("via-gpio", 2, "VGPIO2", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("via-gpio", 3, "VGPIO3", GPIO_ACTIVE_HIGH),
{ }
},
};
/*
* Platform device stuff.
*/
static int viafb_gpio_probe(struct platform_device *platdev)
{
struct viafb_dev *vdev = platdev->dev.platform_data;
struct via_port_cfg *port_cfg = vdev->port_cfg;
int i, ngpio = 0, ret;
struct viafb_gpio *gpio;
unsigned long flags;
/*
* Set up entries for all GPIOs which have been configured to
* operate as such (as opposed to as i2c ports).
*/
for (i = 0; i < VIAFB_NUM_PORTS; i++) {
if (port_cfg[i].mode != VIA_MODE_GPIO)
continue;
for (gpio = viafb_all_gpios;
gpio < viafb_all_gpios + VIAFB_NUM_GPIOS; gpio++)
if (gpio->vg_port_index == port_cfg[i].ioport_index) {
viafb_gpio_config.active_gpios[ngpio] = gpio;
viafb_gpio_config.gpio_names[ngpio] =
gpio->vg_name;
ngpio++;
}
}
viafb_gpio_config.gpio_chip.ngpio = ngpio;
viafb_gpio_config.gpio_chip.names = viafb_gpio_config.gpio_names;
viafb_gpio_config.vdev = vdev;
if (ngpio == 0) {
printk(KERN_INFO "viafb: no GPIOs configured\n");
return 0;
}
/*
* Enable the ports. They come in pairs, with a single
* enable bit for both.
*/
spin_lock_irqsave(&viafb_gpio_config.vdev->reg_lock, flags);
for (i = 0; i < ngpio; i += 2)
viafb_gpio_enable(viafb_gpio_config.active_gpios[i]);
spin_unlock_irqrestore(&viafb_gpio_config.vdev->reg_lock, flags);
/*
* Get registered.
*/
viafb_gpio_config.gpio_chip.base = -1; /* Dynamic */
viafb_gpio_config.gpio_chip.label = "via-gpio";
ret = gpiochip_add_data(&viafb_gpio_config.gpio_chip,
&viafb_gpio_config);
if (ret) {
printk(KERN_ERR "viafb: failed to add gpios (%d)\n", ret);
viafb_gpio_config.gpio_chip.ngpio = 0;
}
gpiod_add_lookup_table(&viafb_gpio_table);
#ifdef CONFIG_PM
viafb_pm_register(&viafb_gpio_pm_hooks);
#endif
return ret;
}
static void viafb_gpio_remove(struct platform_device *platdev)
{
unsigned long flags;
int i;
#ifdef CONFIG_PM
viafb_pm_unregister(&viafb_gpio_pm_hooks);
#endif
/*
* Get unregistered.
*/
if (viafb_gpio_config.gpio_chip.ngpio > 0) {
gpiochip_remove(&viafb_gpio_config.gpio_chip);
}
/*
* Disable the ports.
*/
spin_lock_irqsave(&viafb_gpio_config.vdev->reg_lock, flags);
for (i = 0; i < viafb_gpio_config.gpio_chip.ngpio; i += 2)
viafb_gpio_disable(viafb_gpio_config.active_gpios[i]);
viafb_gpio_config.gpio_chip.ngpio = 0;
spin_unlock_irqrestore(&viafb_gpio_config.vdev->reg_lock, flags);
}
static struct platform_driver via_gpio_driver = {
.driver = {
.name = "viafb-gpio",
},
.probe = viafb_gpio_probe,
.remove_new = viafb_gpio_remove,
};
int viafb_gpio_init(void)
{
return platform_driver_register(&via_gpio_driver);
}
void viafb_gpio_exit(void)
{
platform_driver_unregister(&via_gpio_driver);
}
| linux-master | drivers/video/fbdev/via/via-gpio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include "global.h"
struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
/* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
DVP1Driving, DFPHigh, DFPLow */
/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
SR65, CR97, CR99 */
/* LCK/VCK < 30000000 will use this value */
{DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00},
/* 30000000 < LCK/VCK < 50000000 will use this value */
{DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
0x00},
/* 50000000 < LCK/VCK < 70000000 will use this value */
{DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
0x00},
/* 70000000 < LCK/VCK < 100000000 will use this value */
{DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
0x00},
/* 100000000 < LCK/VCK < 15000000 will use this value */
{DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
0x00},
/* 15000000 < LCK/VCK will use this value */
{DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00,
0x00},
};
struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
DVP1Driving, DFPHigh, DFPLow */
/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
SR65, CR97, CR99 */
/* LCK/VCK < 30000000 will use this value */
{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
/* 30000000 < LCK/VCK < 50000000 will use this value */
{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
/* 50000000 < LCK/VCK < 70000000 will use this value */
{DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
/* 70000000 < LCK/VCK < 100000000 will use this value */
{DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03},
/* 100000000 < LCK/VCK < 15000000 will use this value */
{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02},
/* 15000000 < LCK/VCK will use this value */
{DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03},
};
/* For VT3364: */
struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = {
/* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1,
DVP1Driving, DFPHigh, DFPLow */
/* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B,
SR65, CR97, CR99 */
/* LCK/VCK < 30000000 will use this value */
{DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
/* 30000000 < LCK/VCK < 50000000 will use this value */
{DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
/* 50000000 < LCK/VCK < 70000000 will use this value */
{DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
/* 70000000 < LCK/VCK < 100000000 will use this value */
{DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
/* 100000000 < LCK/VCK < 15000000 will use this value */
{DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
/* 15000000 < LCK/VCK will use this value */
{DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08},
};
| linux-master | drivers/video/fbdev/via/tblDPASetting.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* driver for VIA VT1625(M) HDTV Encoder
*/
#include <linux/slab.h>
#include "via_aux.h"
static const char *name = "VT1625(M) HDTV Encoder";
static void probe(struct via_aux_bus *bus, u8 addr)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = addr,
.name = name};
u8 tmp;
if (!via_aux_read(&drv, 0x1B, &tmp, 1) || tmp != 0x50)
return;
printk(KERN_INFO "viafb: Found %s at address 0x%x\n", name, addr);
via_aux_add(&drv);
}
void via_aux_vt1625_probe(struct via_aux_bus *bus)
{
probe(bus, 0x20);
probe(bus, 0x21);
}
| linux-master | drivers/video/fbdev/via/via_aux_vt1625.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
* Copyright 2010 Florian Tobias Schandinat <[email protected]>
*/
/*
* basic modesetting functions
*/
#include <linux/kernel.h>
#include <linux/via-core.h>
#include "via_modesetting.h"
#include "share.h"
#include "debug.h"
void via_set_primary_timing(const struct via_display_timing *timing)
{
struct via_display_timing raw;
raw.hor_total = timing->hor_total / 8 - 5;
raw.hor_addr = timing->hor_addr / 8 - 1;
raw.hor_blank_start = timing->hor_blank_start / 8 - 1;
raw.hor_blank_end = timing->hor_blank_end / 8 - 1;
raw.hor_sync_start = timing->hor_sync_start / 8;
raw.hor_sync_end = timing->hor_sync_end / 8;
raw.ver_total = timing->ver_total - 2;
raw.ver_addr = timing->ver_addr - 1;
raw.ver_blank_start = timing->ver_blank_start - 1;
raw.ver_blank_end = timing->ver_blank_end - 1;
raw.ver_sync_start = timing->ver_sync_start - 1;
raw.ver_sync_end = timing->ver_sync_end - 1;
/* unlock timing registers */
via_write_reg_mask(VIACR, 0x11, 0x00, 0x80);
via_write_reg(VIACR, 0x00, raw.hor_total & 0xFF);
via_write_reg(VIACR, 0x01, raw.hor_addr & 0xFF);
via_write_reg(VIACR, 0x02, raw.hor_blank_start & 0xFF);
via_write_reg_mask(VIACR, 0x03, raw.hor_blank_end & 0x1F, 0x1F);
via_write_reg(VIACR, 0x04, raw.hor_sync_start & 0xFF);
via_write_reg_mask(VIACR, 0x05, (raw.hor_sync_end & 0x1F)
| (raw.hor_blank_end << (7 - 5) & 0x80), 0x9F);
via_write_reg(VIACR, 0x06, raw.ver_total & 0xFF);
via_write_reg_mask(VIACR, 0x07, (raw.ver_total >> 8 & 0x01)
| (raw.ver_addr >> (8 - 1) & 0x02)
| (raw.ver_sync_start >> (8 - 2) & 0x04)
| (raw.ver_blank_start >> (8 - 3) & 0x08)
| (raw.ver_total >> (9 - 5) & 0x20)
| (raw.ver_addr >> (9 - 6) & 0x40)
| (raw.ver_sync_start >> (9 - 7) & 0x80), 0xEF);
via_write_reg_mask(VIACR, 0x09, raw.ver_blank_start >> (9 - 5) & 0x20,
0x20);
via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF);
via_write_reg_mask(VIACR, 0x11, raw.ver_sync_end & 0x0F, 0x0F);
via_write_reg(VIACR, 0x12, raw.ver_addr & 0xFF);
via_write_reg(VIACR, 0x15, raw.ver_blank_start & 0xFF);
via_write_reg(VIACR, 0x16, raw.ver_blank_end & 0xFF);
via_write_reg_mask(VIACR, 0x33, (raw.hor_sync_start >> (8 - 4) & 0x10)
| (raw.hor_blank_end >> (6 - 5) & 0x20), 0x30);
via_write_reg_mask(VIACR, 0x35, (raw.ver_total >> 10 & 0x01)
| (raw.ver_sync_start >> (10 - 1) & 0x02)
| (raw.ver_addr >> (10 - 2) & 0x04)
| (raw.ver_blank_start >> (10 - 3) & 0x08), 0x0F);
via_write_reg_mask(VIACR, 0x36, raw.hor_total >> (8 - 3) & 0x08, 0x08);
/* lock timing registers */
via_write_reg_mask(VIACR, 0x11, 0x80, 0x80);
/* reset timing control */
via_write_reg_mask(VIACR, 0x17, 0x00, 0x80);
via_write_reg_mask(VIACR, 0x17, 0x80, 0x80);
}
void via_set_secondary_timing(const struct via_display_timing *timing)
{
struct via_display_timing raw;
raw.hor_total = timing->hor_total - 1;
raw.hor_addr = timing->hor_addr - 1;
raw.hor_blank_start = timing->hor_blank_start - 1;
raw.hor_blank_end = timing->hor_blank_end - 1;
raw.hor_sync_start = timing->hor_sync_start - 1;
raw.hor_sync_end = timing->hor_sync_end - 1;
raw.ver_total = timing->ver_total - 1;
raw.ver_addr = timing->ver_addr - 1;
raw.ver_blank_start = timing->ver_blank_start - 1;
raw.ver_blank_end = timing->ver_blank_end - 1;
raw.ver_sync_start = timing->ver_sync_start - 1;
raw.ver_sync_end = timing->ver_sync_end - 1;
via_write_reg(VIACR, 0x50, raw.hor_total & 0xFF);
via_write_reg(VIACR, 0x51, raw.hor_addr & 0xFF);
via_write_reg(VIACR, 0x52, raw.hor_blank_start & 0xFF);
via_write_reg(VIACR, 0x53, raw.hor_blank_end & 0xFF);
via_write_reg(VIACR, 0x54, (raw.hor_blank_start >> 8 & 0x07)
| (raw.hor_blank_end >> (8 - 3) & 0x38)
| (raw.hor_sync_start >> (8 - 6) & 0xC0));
via_write_reg_mask(VIACR, 0x55, (raw.hor_total >> 8 & 0x0F)
| (raw.hor_addr >> (8 - 4) & 0x70), 0x7F);
via_write_reg(VIACR, 0x56, raw.hor_sync_start & 0xFF);
via_write_reg(VIACR, 0x57, raw.hor_sync_end & 0xFF);
via_write_reg(VIACR, 0x58, raw.ver_total & 0xFF);
via_write_reg(VIACR, 0x59, raw.ver_addr & 0xFF);
via_write_reg(VIACR, 0x5A, raw.ver_blank_start & 0xFF);
via_write_reg(VIACR, 0x5B, raw.ver_blank_end & 0xFF);
via_write_reg(VIACR, 0x5C, (raw.ver_blank_start >> 8 & 0x07)
| (raw.ver_blank_end >> (8 - 3) & 0x38)
| (raw.hor_sync_end >> (8 - 6) & 0x40)
| (raw.hor_sync_start >> (10 - 7) & 0x80));
via_write_reg(VIACR, 0x5D, (raw.ver_total >> 8 & 0x07)
| (raw.ver_addr >> (8 - 3) & 0x38)
| (raw.hor_blank_end >> (11 - 6) & 0x40)
| (raw.hor_sync_start >> (11 - 7) & 0x80));
via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF);
via_write_reg(VIACR, 0x5F, (raw.ver_sync_end & 0x1F)
| (raw.ver_sync_start >> (8 - 5) & 0xE0));
}
void via_set_primary_address(u32 addr)
{
DEBUG_MSG(KERN_DEBUG "via_set_primary_address(0x%08X)\n", addr);
via_write_reg(VIACR, 0x0D, addr & 0xFF);
via_write_reg(VIACR, 0x0C, (addr >> 8) & 0xFF);
via_write_reg(VIACR, 0x34, (addr >> 16) & 0xFF);
via_write_reg_mask(VIACR, 0x48, (addr >> 24) & 0x1F, 0x1F);
}
void via_set_secondary_address(u32 addr)
{
DEBUG_MSG(KERN_DEBUG "via_set_secondary_address(0x%08X)\n", addr);
/* secondary display supports only quadword aligned memory */
via_write_reg_mask(VIACR, 0x62, (addr >> 2) & 0xFE, 0xFE);
via_write_reg(VIACR, 0x63, (addr >> 10) & 0xFF);
via_write_reg(VIACR, 0x64, (addr >> 18) & 0xFF);
via_write_reg_mask(VIACR, 0xA3, (addr >> 26) & 0x07, 0x07);
}
void via_set_primary_pitch(u32 pitch)
{
DEBUG_MSG(KERN_DEBUG "via_set_primary_pitch(0x%08X)\n", pitch);
/* spec does not say that first adapter skips 3 bits but old
* code did it and seems to be reasonable in analogy to 2nd adapter
*/
pitch = pitch >> 3;
via_write_reg(VIACR, 0x13, pitch & 0xFF);
via_write_reg_mask(VIACR, 0x35, (pitch >> (8 - 5)) & 0xE0, 0xE0);
}
void via_set_secondary_pitch(u32 pitch)
{
DEBUG_MSG(KERN_DEBUG "via_set_secondary_pitch(0x%08X)\n", pitch);
pitch = pitch >> 3;
via_write_reg(VIACR, 0x66, pitch & 0xFF);
via_write_reg_mask(VIACR, 0x67, (pitch >> 8) & 0x03, 0x03);
via_write_reg_mask(VIACR, 0x71, (pitch >> (10 - 7)) & 0x80, 0x80);
}
void via_set_primary_color_depth(u8 depth)
{
u8 value;
DEBUG_MSG(KERN_DEBUG "via_set_primary_color_depth(%d)\n", depth);
switch (depth) {
case 8:
value = 0x00;
break;
case 15:
value = 0x04;
break;
case 16:
value = 0x14;
break;
case 24:
value = 0x0C;
break;
case 30:
value = 0x08;
break;
default:
printk(KERN_WARNING "via_set_primary_color_depth: "
"Unsupported depth: %d\n", depth);
return;
}
via_write_reg_mask(VIASR, 0x15, value, 0x1C);
}
void via_set_secondary_color_depth(u8 depth)
{
u8 value;
DEBUG_MSG(KERN_DEBUG "via_set_secondary_color_depth(%d)\n", depth);
switch (depth) {
case 8:
value = 0x00;
break;
case 16:
value = 0x40;
break;
case 24:
value = 0xC0;
break;
case 30:
value = 0x80;
break;
default:
printk(KERN_WARNING "via_set_secondary_color_depth: "
"Unsupported depth: %d\n", depth);
return;
}
via_write_reg_mask(VIACR, 0x67, value, 0xC0);
}
| linux-master | drivers/video/fbdev/via/via_modesetting.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* driver for VIA VT1621(M) TV Encoder
*/
#include <linux/slab.h>
#include "via_aux.h"
static const char *name = "VT1621(M) TV Encoder";
void via_aux_vt1621_probe(struct via_aux_bus *bus)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = 0x20,
.name = name};
u8 tmp;
if (!via_aux_read(&drv, 0x1B, &tmp, 1) || tmp != 0x02)
return;
printk(KERN_INFO "viafb: Found %s\n", name);
via_aux_add(&drv);
}
| linux-master | drivers/video/fbdev/via/via_aux_vt1621.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include "global.h"
int viafb_ioctl_get_viafb_info(u_long arg)
{
struct viafb_ioctl_info viainfo;
memset(&viainfo, 0, sizeof(struct viafb_ioctl_info));
viainfo.viafb_id = VIAID;
viainfo.vendor_id = PCI_VIA_VENDOR_ID;
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
viainfo.device_id = UNICHROME_CLE266_DID;
break;
case UNICHROME_K400:
viainfo.device_id = UNICHROME_K400_DID;
break;
case UNICHROME_K800:
viainfo.device_id = UNICHROME_K800_DID;
break;
case UNICHROME_PM800:
viainfo.device_id = UNICHROME_PM800_DID;
break;
case UNICHROME_CN700:
viainfo.device_id = UNICHROME_CN700_DID;
break;
case UNICHROME_CX700:
viainfo.device_id = UNICHROME_CX700_DID;
break;
case UNICHROME_K8M890:
viainfo.device_id = UNICHROME_K8M890_DID;
break;
case UNICHROME_P4M890:
viainfo.device_id = UNICHROME_P4M890_DID;
break;
case UNICHROME_P4M900:
viainfo.device_id = UNICHROME_P4M900_DID;
break;
}
viainfo.version = VERSION_MAJOR;
viainfo.revision = VERSION_MINOR;
if (copy_to_user((void __user *)arg, &viainfo, sizeof(viainfo)))
return -EFAULT;
return 0;
}
/* Hot-Plug Priority: DVI > CRT*/
int viafb_ioctl_hotplug(int hres, int vres, int bpp)
{
int DVIsense, status = 0;
DEBUG_MSG(KERN_INFO "viafb_ioctl_hotplug!!\n");
if (viaparinfo->chip_info->tmds_chip_info.tmds_chip_name !=
NON_TMDS_TRANSMITTER) {
DVIsense = viafb_dvi_sense();
if (DVIsense) {
DEBUG_MSG(KERN_INFO "DVI Attached...\n");
if (viafb_DeviceStatus != DVI_Device) {
viafb_DVI_ON = 1;
viafb_CRT_ON = 0;
viafb_LCD_ON = 0;
viafb_DeviceStatus = DVI_Device;
viafb_set_iga_path();
return viafb_DeviceStatus;
}
status = 1;
} else
DEBUG_MSG(KERN_INFO "DVI De-attached...\n");
}
if ((viafb_DeviceStatus != CRT_Device) && (status == 0)) {
viafb_CRT_ON = 1;
viafb_DVI_ON = 0;
viafb_LCD_ON = 0;
viafb_DeviceStatus = CRT_Device;
viafb_set_iga_path();
return viafb_DeviceStatus;
}
return 0;
}
| linux-master | drivers/video/fbdev/via/ioctl.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/via-core.h>
#include "global.h"
struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1E, 0x0F, 0x01},
{VIASR, SR2A, 0xFF, 0x00},
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00}
};
/* Video Mode Table for VT3314 chipset*/
/* Common Setting for Video Mode */
struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x82},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1F, 0xFF, 0x00},
{VIASR, SR1E, 0xFF, 0x01},
{VIASR, SR22, 0xFF, 0x1F},
{VIASR, SR2A, 0x0F, 0x00},
{VIASR, SR2E, 0xFF, 0xFF},
{VIASR, SR3F, 0xFF, 0xFF},
{VIASR, SR40, 0xF7, 0x00},
{VIASR, CR30, 0xFF, 0x04},
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0x7F, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0xFF, 0x31},
{VIACR, CR41, 0xFF, 0x80},
{VIACR, CR42, 0xFF, 0x00},
{VIACR, CR55, 0x80, 0x00},
{VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/
{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFD, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */
{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */
{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */
{VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00},
{VIACR, CR9D, 0xFF, 0x80},
{VIACR, CR9E, 0xFF, 0x80}
};
struct io_reg KM400_ModeXregs[] = {
{VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
{VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
{VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
{VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
{VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
{VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
{VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
{VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */
{VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
{VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
{VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
{VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */
{VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
{VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR55, 0x80, 0x00},
{VIACR, CR5D, 0x80, 0x00},
{VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */
{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
{VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x03}, /* DVP0 ; DVP0 Clock Skew */
{VIACR, CR97, 0xFF, 0x03}, /* DFP high ; DFPH Clock Skew */
{VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/
{VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew*/
};
/* For VT3324: Common Setting for Video Mode */
struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1E, 0xFF, 0x01},
{VIASR, SR2A, 0xFF, 0x00},
{VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00}
};
struct io_reg VX855_ModeXregs[] = {
{VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1E, 0x07, 0x01},
{VIASR, SR2A, 0xF0, 0x00},
{VIASR, SR58, 0xFF, 0x00},
{VIASR, SR59, 0xFF, 0x00},
{VIASR, SR2D, 0xC0, 0xC0}, /* delayed E3_ECK */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0x7F, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFD, 0x60},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00},
{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
};
/* Video Mode Table */
/* Common Setting for Video Mode */
struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
{VIASR, SR2A, 0x0F, 0x00},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR6A, 0xFF, 0x80},
{VIACR, CR6A, 0xFF, 0xC0},
{VIACR, CR55, 0x80, 0x00},
{VIACR, CR5D, 0x80, 0x00},
{VIAGR, GR20, 0xFF, 0x00},
{VIAGR, GR21, 0xFF, 0x00},
{VIAGR, GR22, 0xFF, 0x00},
};
/* Mode:1024X768 */
struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
{VIASR, 0x18, 0xFF, 0x4C}
};
struct patch_table res_patch_table[] = {
{ARRAY_SIZE(PM1024x768), PM1024x768}
};
/* struct VPITTable {
unsigned char Misc;
unsigned char SR[StdSR];
unsigned char CR[StdCR];
unsigned char GR[StdGR];
unsigned char AR[StdAR];
};*/
struct VPITTable VPIT = {
/* Msic */
0xC7,
/* Sequencer */
{0x01, 0x0F, 0x00, 0x0E},
/* Graphic Controller */
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
/* Attribute Controller */
{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x01, 0x00, 0x0F, 0x00}
};
/********************/
/* Mode Table */
/********************/
static const struct fb_videomode viafb_modes[] = {
{NULL, 60, 480, 640, 40285, 72, 24, 19, 1, 48, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, 0, 0, 0},
{NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0, 0, 0},
{NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3, 0, 0, 0},
{NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 120, 640, 480, 19081, 104, 40, 31, 1, 64, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 720, 480, 37426, 88, 16, 13, 1, 72, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 720, 576, 30611, 96, 24, 17, 1, 72, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 100, 800, 600, 14667, 136, 48, 32, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 120, 800, 600, 11911, 144, 56, 39, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 800, 480, 33602, 96, 24, 10, 3, 72, 7, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 848, 480, 31565, 104, 24, 12, 3, 80, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 856, 480, 31517, 104, 16, 13, 1, 88, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1024, 512, 24218, 136, 32, 15, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1024, 600, 20423, 144, 40, 18, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6, 0, 0, 0},
{NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1280, 768, 12478, 200, 64, 23, 1, 136, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 50, 1280, 768, 15342, 184, 56, 19, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 960, 600, 21964, 128, 32, 15, 3, 96, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1000, 600, 20803, 144, 40, 18, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1024, 576, 21278, 144, 40, 17, 1, 104, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1088, 612, 18825, 152, 48, 16, 3, 104, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1152, 720, 14974, 168, 56, 19, 3, 112, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1200, 720, 14248, 184, 56, 22, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 49, 1200, 900, 17703, 21, 11, 1, 1, 32, 10, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1280, 600, 16259, 184, 56, 18, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1280, 800, 11938, 200, 72, 22, 3, 128, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1360, 768, 11759, 208, 72, 22, 3, 136, 5, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1368, 768, 11646, 216, 72, 23, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 50, 1368, 768, 14301, 200, 56, 19, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1368, 768, 11646, 216, 72, 23, 1, 144, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1440, 900, 9372, 232, 80, 25, 3, 152, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 75, 1440, 900, 7311, 248, 96, 33, 3, 152, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1440, 1040, 7993, 248, 96, 33, 1, 152, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1600, 900, 8449, 256, 88, 26, 3, 168, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1600, 1024, 7333, 272, 104, 32, 1, 168, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1680, 1050, 6832, 280, 104, 30, 3, 176, 6, 0, 0, 0},
{NULL, 75, 1680, 1050, 5339, 296, 120, 40, 3, 176, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1792, 1344, 4883, 328, 128, 46, 1, 200, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1856, 1392, 4581, 352, 96, 43, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 2048, 1536, 3738, 376, 152, 49, 3, 224, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1280, 720, 13484, 216, 112, 20, 5, 40, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 50, 1280, 720, 16538, 176, 48, 17, 1, 128, 3, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1920, 1080, 5776, 328, 128, 32, 3, 200, 5, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1920, 1200, 5164, 336, 136, 36, 3, 200, 6, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 60, 1400, 1050, 8210, 232, 88, 32, 3, 144, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0},
{NULL, 75, 1400, 1050, 6398, 248, 104, 42, 3, 144, 4, FB_SYNC_VERT_HIGH_ACT, 0, 0} };
static const struct fb_videomode viafb_rb_modes[] = {
{NULL, 60, 1360, 768, 13879, 80, 48, 14, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
{NULL, 60, 1440, 900, 11249, 80, 48, 17, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0},
{NULL, 60, 1400, 1050, 9892, 80, 48, 23, 3, 32, 4, FB_SYNC_HOR_HIGH_ACT, 0, 0},
{NULL, 60, 1600, 900, 10226, 80, 48, 18, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
{NULL, 60, 1680, 1050, 8387, 80, 48, 21, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0},
{NULL, 60, 1920, 1080, 7212, 80, 48, 23, 3, 32, 5, FB_SYNC_HOR_HIGH_ACT, 0, 0},
{NULL, 60, 1920, 1200, 6488, 80, 48, 26, 3, 32, 6, FB_SYNC_HOR_HIGH_ACT, 0, 0} };
int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
static const struct fb_videomode *get_best_mode(
const struct fb_videomode *modes, int n,
int hres, int vres, int refresh)
{
const struct fb_videomode *best = NULL;
int i;
for (i = 0; i < n; i++) {
if (modes[i].xres != hres || modes[i].yres != vres)
continue;
if (!best || abs(modes[i].refresh - refresh) <
abs(best->refresh - refresh))
best = &modes[i];
}
return best;
}
const struct fb_videomode *viafb_get_best_mode(int hres, int vres, int refresh)
{
return get_best_mode(viafb_modes, ARRAY_SIZE(viafb_modes),
hres, vres, refresh);
}
const struct fb_videomode *viafb_get_best_rb_mode(int hres, int vres,
int refresh)
{
return get_best_mode(viafb_rb_modes, ARRAY_SIZE(viafb_rb_modes),
hres, vres, refresh);
}
| linux-master | drivers/video/fbdev/via/viamode.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/module.h>
#include <linux/via-core.h>
#include <linux/via_i2c.h>
/*
* There can only be one set of these, so there's no point in having
* them be dynamically allocated...
*/
#define VIAFB_NUM_I2C 5
static struct via_i2c_stuff via_i2c_par[VIAFB_NUM_I2C];
static struct viafb_dev *i2c_vdev; /* Passed in from core */
static void via_i2c_setscl(void *data, int state)
{
u8 val;
struct via_port_cfg *adap_data = data;
unsigned long flags;
spin_lock_irqsave(&i2c_vdev->reg_lock, flags);
val = via_read_reg(adap_data->io_port, adap_data->ioport_index) & 0xF0;
if (state)
val |= 0x20;
else
val &= ~0x20;
switch (adap_data->type) {
case VIA_PORT_I2C:
val |= 0x01;
break;
case VIA_PORT_GPIO:
val |= 0x82;
break;
default:
printk(KERN_ERR "viafb_i2c: specify wrong i2c type.\n");
}
via_write_reg(adap_data->io_port, adap_data->ioport_index, val);
spin_unlock_irqrestore(&i2c_vdev->reg_lock, flags);
}
static int via_i2c_getscl(void *data)
{
struct via_port_cfg *adap_data = data;
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&i2c_vdev->reg_lock, flags);
if (adap_data->type == VIA_PORT_GPIO)
via_write_reg_mask(adap_data->io_port, adap_data->ioport_index,
0, 0x80);
if (via_read_reg(adap_data->io_port, adap_data->ioport_index) & 0x08)
ret = 1;
spin_unlock_irqrestore(&i2c_vdev->reg_lock, flags);
return ret;
}
static int via_i2c_getsda(void *data)
{
struct via_port_cfg *adap_data = data;
unsigned long flags;
int ret = 0;
spin_lock_irqsave(&i2c_vdev->reg_lock, flags);
if (adap_data->type == VIA_PORT_GPIO)
via_write_reg_mask(adap_data->io_port, adap_data->ioport_index,
0, 0x40);
if (via_read_reg(adap_data->io_port, adap_data->ioport_index) & 0x04)
ret = 1;
spin_unlock_irqrestore(&i2c_vdev->reg_lock, flags);
return ret;
}
static void via_i2c_setsda(void *data, int state)
{
u8 val;
struct via_port_cfg *adap_data = data;
unsigned long flags;
spin_lock_irqsave(&i2c_vdev->reg_lock, flags);
val = via_read_reg(adap_data->io_port, adap_data->ioport_index) & 0xF0;
if (state)
val |= 0x10;
else
val &= ~0x10;
switch (adap_data->type) {
case VIA_PORT_I2C:
val |= 0x01;
break;
case VIA_PORT_GPIO:
val |= 0x42;
break;
default:
printk(KERN_ERR "viafb_i2c: specify wrong i2c type.\n");
}
via_write_reg(adap_data->io_port, adap_data->ioport_index, val);
spin_unlock_irqrestore(&i2c_vdev->reg_lock, flags);
}
int viafb_i2c_readbyte(u8 adap, u8 slave_addr, u8 index, u8 *pdata)
{
int ret;
u8 mm1[] = {0x00};
struct i2c_msg msgs[2];
if (!via_i2c_par[adap].is_active)
return -ENODEV;
*pdata = 0;
msgs[0].flags = 0;
msgs[1].flags = I2C_M_RD;
msgs[0].addr = msgs[1].addr = slave_addr / 2;
mm1[0] = index;
msgs[0].len = 1; msgs[1].len = 1;
msgs[0].buf = mm1; msgs[1].buf = pdata;
ret = i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2);
if (ret == 2)
ret = 0;
else if (ret >= 0)
ret = -EIO;
return ret;
}
int viafb_i2c_writebyte(u8 adap, u8 slave_addr, u8 index, u8 data)
{
int ret;
u8 msg[2] = { index, data };
struct i2c_msg msgs;
if (!via_i2c_par[adap].is_active)
return -ENODEV;
msgs.flags = 0;
msgs.addr = slave_addr / 2;
msgs.len = 2;
msgs.buf = msg;
ret = i2c_transfer(&via_i2c_par[adap].adapter, &msgs, 1);
if (ret == 1)
ret = 0;
else if (ret >= 0)
ret = -EIO;
return ret;
}
int viafb_i2c_readbytes(u8 adap, u8 slave_addr, u8 index, u8 *buff, int buff_len)
{
int ret;
u8 mm1[] = {0x00};
struct i2c_msg msgs[2];
if (!via_i2c_par[adap].is_active)
return -ENODEV;
msgs[0].flags = 0;
msgs[1].flags = I2C_M_RD;
msgs[0].addr = msgs[1].addr = slave_addr / 2;
mm1[0] = index;
msgs[0].len = 1; msgs[1].len = buff_len;
msgs[0].buf = mm1; msgs[1].buf = buff;
ret = i2c_transfer(&via_i2c_par[adap].adapter, msgs, 2);
if (ret == 2)
ret = 0;
else if (ret >= 0)
ret = -EIO;
return ret;
}
/*
* Allow other viafb subdevices to look up a specific adapter
* by port name.
*/
struct i2c_adapter *viafb_find_i2c_adapter(enum viafb_i2c_adap which)
{
struct via_i2c_stuff *stuff = &via_i2c_par[which];
return &stuff->adapter;
}
EXPORT_SYMBOL_GPL(viafb_find_i2c_adapter);
static int create_i2c_bus(struct i2c_adapter *adapter,
struct i2c_algo_bit_data *algo,
struct via_port_cfg *adap_cfg,
struct pci_dev *pdev)
{
algo->setsda = via_i2c_setsda;
algo->setscl = via_i2c_setscl;
algo->getsda = via_i2c_getsda;
algo->getscl = via_i2c_getscl;
algo->udelay = 10;
algo->timeout = 2;
algo->data = adap_cfg;
sprintf(adapter->name, "viafb i2c io_port idx 0x%02x",
adap_cfg->ioport_index);
adapter->owner = THIS_MODULE;
adapter->class = I2C_CLASS_DDC;
adapter->algo_data = algo;
if (pdev)
adapter->dev.parent = &pdev->dev;
else
adapter->dev.parent = NULL;
/* i2c_set_adapdata(adapter, adap_cfg); */
/* Raise SCL and SDA */
via_i2c_setsda(adap_cfg, 1);
via_i2c_setscl(adap_cfg, 1);
udelay(20);
return i2c_bit_add_bus(adapter);
}
static int viafb_i2c_probe(struct platform_device *platdev)
{
int i, ret;
struct via_port_cfg *configs;
i2c_vdev = platdev->dev.platform_data;
configs = i2c_vdev->port_cfg;
for (i = 0; i < VIAFB_NUM_PORTS; i++) {
struct via_port_cfg *adap_cfg = configs++;
struct via_i2c_stuff *i2c_stuff = &via_i2c_par[i];
i2c_stuff->is_active = 0;
if (adap_cfg->type == 0 || adap_cfg->mode != VIA_MODE_I2C)
continue;
ret = create_i2c_bus(&i2c_stuff->adapter,
&i2c_stuff->algo, adap_cfg,
NULL); /* FIXME: PCIDEV */
if (ret < 0) {
printk(KERN_ERR "viafb: cannot create i2c bus %u:%d\n",
i, ret);
continue; /* Still try to make the rest */
}
i2c_stuff->is_active = 1;
}
return 0;
}
static void viafb_i2c_remove(struct platform_device *platdev)
{
int i;
for (i = 0; i < VIAFB_NUM_PORTS; i++) {
struct via_i2c_stuff *i2c_stuff = &via_i2c_par[i];
/*
* Only remove those entries in the array that we've
* actually used (and thus initialized algo_data)
*/
if (i2c_stuff->is_active)
i2c_del_adapter(&i2c_stuff->adapter);
}
}
static struct platform_driver via_i2c_driver = {
.driver = {
.name = "viafb-i2c",
},
.probe = viafb_i2c_probe,
.remove_new = viafb_i2c_remove,
};
int viafb_i2c_init(void)
{
return platform_driver_register(&via_i2c_driver);
}
void viafb_i2c_exit(void)
{
platform_driver_unregister(&via_i2c_driver);
}
| linux-master | drivers/video/fbdev/via/via_i2c.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* infrastructure for devices connected via I2C
*/
#include <linux/slab.h>
#include "via_aux.h"
struct via_aux_bus *via_aux_probe(struct i2c_adapter *adap)
{
struct via_aux_bus *bus;
if (!adap)
return NULL;
bus = kmalloc(sizeof(*bus), GFP_KERNEL);
if (!bus)
return NULL;
bus->adap = adap;
INIT_LIST_HEAD(&bus->drivers);
via_aux_edid_probe(bus);
via_aux_vt1636_probe(bus);
via_aux_vt1632_probe(bus);
via_aux_vt1631_probe(bus);
via_aux_vt1625_probe(bus);
via_aux_vt1622_probe(bus);
via_aux_vt1621_probe(bus);
via_aux_sii164_probe(bus);
via_aux_ch7301_probe(bus);
return bus;
}
void via_aux_free(struct via_aux_bus *bus)
{
struct via_aux_drv *pos, *n;
if (!bus)
return;
list_for_each_entry_safe(pos, n, &bus->drivers, chain) {
if (pos->cleanup)
pos->cleanup(pos);
list_del(&pos->chain);
kfree(pos->data);
kfree(pos);
}
kfree(bus);
}
const struct fb_videomode *via_aux_get_preferred_mode(struct via_aux_bus *bus)
{
struct via_aux_drv *pos;
const struct fb_videomode *mode = NULL;
if (!bus)
return NULL;
list_for_each_entry(pos, &bus->drivers, chain) {
if (pos->get_preferred_mode)
mode = pos->get_preferred_mode(pos);
}
return mode;
}
| linux-master | drivers/video/fbdev/via/via_aux.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Florian Tobias Schandinat <[email protected]>
*/
/*
* driver for Silicon Image SiI 164 PanelLink Transmitter
*/
#include <linux/slab.h>
#include "via_aux.h"
static const char *name = "SiI 164 PanelLink Transmitter";
static void probe(struct via_aux_bus *bus, u8 addr)
{
struct via_aux_drv drv = {
.bus = bus,
.addr = addr,
.name = name};
/* check vendor id and device id */
const u8 id[] = {0x01, 0x00, 0x06, 0x00}, len = ARRAY_SIZE(id);
u8 tmp[ARRAY_SIZE(id)];
if (!via_aux_read(&drv, 0x00, tmp, len) || memcmp(id, tmp, len))
return;
printk(KERN_INFO "viafb: Found %s at address 0x%x\n", name, addr);
via_aux_add(&drv);
}
void via_aux_sii164_probe(struct via_aux_bus *bus)
{
u8 i;
for (i = 0x38; i <= 0x3F; i++)
probe(bus, i);
}
| linux-master | drivers/video/fbdev/via/via_aux_sii164.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/via-core.h>
#include <linux/via_i2c.h>
#include "global.h"
static const struct IODATA common_init_data[] = {
/* Index, Mask, Value */
/* Set panel power sequence timing */
{0x10, 0xC0, 0x00},
/* T1: VDD on - Data on. Each increment is 1 ms. (50ms = 031h) */
{0x0B, 0xFF, 0x40},
/* T2: Data on - Backlight on. Each increment is 2 ms. (210ms = 068h) */
{0x0C, 0xFF, 0x31},
/* T3: Backlight off -Data off. Each increment is 2 ms. (210ms = 068h)*/
{0x0D, 0xFF, 0x31},
/* T4: Data off - VDD off. Each increment is 1 ms. (50ms = 031h) */
{0x0E, 0xFF, 0x68},
/* T5: VDD off - VDD on. Each increment is 100 ms. (500ms = 04h) */
{0x0F, 0xFF, 0x68},
/* LVDS output power up */
{0x09, 0xA0, 0xA0},
/* turn on back light */
{0x10, 0x33, 0x13}
};
/* Index, Mask, Value */
static const struct IODATA dual_channel_enable_data = {0x08, 0xF0, 0xE0};
static const struct IODATA single_channel_enable_data = {0x08, 0xF0, 0x00};
static const struct IODATA dithering_enable_data = {0x0A, 0x70, 0x50};
static const struct IODATA dithering_disable_data = {0x0A, 0x70, 0x00};
static const struct IODATA vdd_on_data = {0x10, 0x20, 0x20};
static const struct IODATA vdd_off_data = {0x10, 0x20, 0x00};
u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
u8 index)
{
u8 data;
viafb_i2c_readbyte(plvds_chip_info->i2c_port,
plvds_chip_info->lvds_chip_slave_addr, index, &data);
return data;
}
void viafb_gpio_i2c_write_mask_lvds(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information
*plvds_chip_info, struct IODATA io_data)
{
int index, data;
index = io_data.Index;
data = viafb_gpio_i2c_read_lvds(plvds_setting_info, plvds_chip_info,
index);
data = (data & (~io_data.Mask)) | io_data.Data;
viafb_i2c_writebyte(plvds_chip_info->i2c_port,
plvds_chip_info->lvds_chip_slave_addr, index, data);
}
void viafb_init_lvds_vt1636(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
{
int reg_num, i;
/* Common settings: */
reg_num = ARRAY_SIZE(common_init_data);
for (i = 0; i < reg_num; i++)
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
plvds_chip_info, common_init_data[i]);
/* Input Data Mode Select */
if (plvds_setting_info->device_lcd_dualedge)
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
plvds_chip_info, dual_channel_enable_data);
else
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
plvds_chip_info, single_channel_enable_data);
if (plvds_setting_info->LCDDithering)
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
plvds_chip_info, dithering_enable_data);
else
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
plvds_chip_info, dithering_disable_data);
}
void viafb_enable_lvds_vt1636(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
vdd_on_data);
}
void viafb_disable_lvds_vt1636(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
vdd_off_data);
}
bool viafb_lvds_identify_vt1636(u8 i2c_adapter)
{
u8 Buffer[2];
DEBUG_MSG(KERN_INFO "viafb_lvds_identify_vt1636.\n");
/* Sense VT1636 LVDS Transmiter */
viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
VT1636_LVDS_I2C_ADDR;
/* Check vendor ID first: */
if (viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR,
0x00, &Buffer[0]))
return false;
viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x01, &Buffer[1]);
if (!((Buffer[0] == 0x06) && (Buffer[1] == 0x11)))
return false;
/* Check Chip ID: */
viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x02, &Buffer[0]);
viafb_i2c_readbyte(i2c_adapter, VT1636_LVDS_I2C_ADDR, 0x03, &Buffer[1]);
if ((Buffer[0] == 0x45) && (Buffer[1] == 0x33)) {
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
VT1636_LVDS;
return true;
}
return false;
}
static int get_clk_range_index(u32 Clk)
{
if (Clk < DPA_CLK_30M)
return DPA_CLK_RANGE_30M;
else if (Clk < DPA_CLK_50M)
return DPA_CLK_RANGE_30_50M;
else if (Clk < DPA_CLK_70M)
return DPA_CLK_RANGE_50_70M;
else if (Clk < DPA_CLK_100M)
return DPA_CLK_RANGE_70_100M;
else if (Clk < DPA_CLK_150M)
return DPA_CLK_RANGE_100_150M;
else
return DPA_CLK_RANGE_150M;
}
static void set_dpa_vt1636(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information *plvds_chip_info,
struct VT1636_DPA_SETTING *p_vt1636_dpa_setting)
{
struct IODATA io_data;
io_data.Index = 0x09;
io_data.Mask = 0x1F;
io_data.Data = p_vt1636_dpa_setting->CLK_SEL_ST1;
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info,
plvds_chip_info, io_data);
io_data.Index = 0x08;
io_data.Mask = 0x0F;
io_data.Data = p_vt1636_dpa_setting->CLK_SEL_ST2;
viafb_gpio_i2c_write_mask_lvds(plvds_setting_info, plvds_chip_info,
io_data);
}
void viafb_vt1636_patch_skew_on_vt3324(
struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
struct VT1636_DPA_SETTING dpa = {0x00, 0x00}, dpa_16x12 = {0x0B, 0x03},
*pdpa;
int index;
DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3324.\n");
/* Graphics DPA settings: */
index = get_clk_range_index(plvds_setting_info->vclk);
viafb_set_dpa_gfx(plvds_chip_info->output_interface,
&GFX_DPA_SETTING_TBL_VT3324[index]);
/* LVDS Transmitter DPA settings: */
if (plvds_setting_info->lcd_panel_hres == 1600 &&
plvds_setting_info->lcd_panel_vres == 1200)
pdpa = &dpa_16x12;
else
pdpa = &dpa;
set_dpa_vt1636(plvds_setting_info, plvds_chip_info, pdpa);
}
void viafb_vt1636_patch_skew_on_vt3327(
struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
struct VT1636_DPA_SETTING dpa = {0x00, 0x00};
int index;
DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3327.\n");
/* Graphics DPA settings: */
index = get_clk_range_index(plvds_setting_info->vclk);
viafb_set_dpa_gfx(plvds_chip_info->output_interface,
&GFX_DPA_SETTING_TBL_VT3327[index]);
/* LVDS Transmitter DPA settings: */
set_dpa_vt1636(plvds_setting_info, plvds_chip_info, &dpa);
}
void viafb_vt1636_patch_skew_on_vt3364(
struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
int index;
DEBUG_MSG(KERN_INFO "viafb_vt1636_patch_skew_on_vt3364.\n");
/* Graphics DPA settings: */
index = get_clk_range_index(plvds_setting_info->vclk);
viafb_set_dpa_gfx(plvds_chip_info->output_interface,
&GFX_DPA_SETTING_TBL_VT3364[index]);
}
| linux-master | drivers/video/fbdev/via/vt1636.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/via-core.h>
#include <linux/via_i2c.h>
#include "global.h"
#define viafb_compact_res(x, y) (((x)<<16)|(y))
/* CLE266 Software Power Sequence */
/* {Mask}, {Data}, {Delay} */
static const int PowerSequenceOn[3][3] = {
{0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01}
};
static const int PowerSequenceOff[3][3] = {
{0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01}
};
static struct _lcd_scaling_factor lcd_scaling_factor = {
/* LCD Horizontal Scaling Factor Register */
{LCD_HOR_SCALING_FACTOR_REG_NUM,
{{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
/* LCD Vertical Scaling Factor Register */
{LCD_VER_SCALING_FACTOR_REG_NUM,
{{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
};
static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
/* LCD Horizontal Scaling Factor Register */
{LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
/* LCD Vertical Scaling Factor Register */
{LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
};
static bool lvds_identify_integratedlvds(void);
static void fp_id_to_vindex(int panel_id);
static int lvds_register_read(int index);
static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
int panel_vres);
static void lcd_patch_skew_dvp0(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info);
static void lcd_patch_skew_dvp1(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info);
static void lcd_patch_skew(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
static void integrated_lvds_disable(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info);
static void integrated_lvds_enable(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info);
static void lcd_powersequence_off(void);
static void lcd_powersequence_on(void);
static void fill_lcd_format(void);
static void check_diport_of_integrated_lvds(
struct lvds_chip_information *plvds_chip_info,
struct lvds_setting_information
*plvds_setting_info);
static inline bool check_lvds_chip(int device_id_subaddr, int device_id)
{
return lvds_register_read(device_id_subaddr) == device_id;
}
void viafb_init_lcd_size(void)
{
DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
fp_id_to_vindex(viafb_lcd_panel_id);
viaparinfo->lvds_setting_info2->lcd_panel_hres =
viaparinfo->lvds_setting_info->lcd_panel_hres;
viaparinfo->lvds_setting_info2->lcd_panel_vres =
viaparinfo->lvds_setting_info->lcd_panel_vres;
viaparinfo->lvds_setting_info2->device_lcd_dualedge =
viaparinfo->lvds_setting_info->device_lcd_dualedge;
viaparinfo->lvds_setting_info2->LCDDithering =
viaparinfo->lvds_setting_info->LCDDithering;
}
static bool lvds_identify_integratedlvds(void)
{
if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
/* Two dual channel LCD (Internal LVDS + External LVDS): */
/* If we have an external LVDS, such as VT1636, we should
have its chip ID already. */
if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
INTEGRATED_LVDS;
DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
"(Internal LVDS + External LVDS)\n");
} else {
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
INTEGRATED_LVDS;
DEBUG_MSG(KERN_INFO "Not found external LVDS, "
"so can't support two dual channel LVDS!\n");
}
} else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
/* Two single channel LCD (Internal LVDS + Internal LVDS): */
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
INTEGRATED_LVDS;
viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
INTEGRATED_LVDS;
DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
"(Internal LVDS + Internal LVDS)\n");
} else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
/* If we have found external LVDS, just use it,
otherwise, we will use internal LVDS as default. */
if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
INTEGRATED_LVDS;
DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
}
} else {
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
NON_LVDS_TRANSMITTER;
DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
return false;
}
return true;
}
bool viafb_lvds_trasmitter_identify(void)
{
if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
DEBUG_MSG(KERN_INFO
"Found VIA VT1636 LVDS on port i2c 0x31\n");
} else {
if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
viaparinfo->chip_info->lvds_chip_info.i2c_port =
VIA_PORT_2C;
DEBUG_MSG(KERN_INFO
"Found VIA VT1636 LVDS on port gpio 0x2c\n");
}
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
lvds_identify_integratedlvds();
if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
return true;
/* Check for VT1631: */
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
VT1631_LVDS_I2C_ADDR;
if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID)) {
DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
DEBUG_MSG(KERN_INFO "\n %2d",
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
DEBUG_MSG(KERN_INFO "\n %2d",
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
return true;
}
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
NON_LVDS_TRANSMITTER;
viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
VT1631_LVDS_I2C_ADDR;
return false;
}
static void fp_id_to_vindex(int panel_id)
{
DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
if (panel_id > LCD_PANEL_ID_MAXIMUM)
viafb_lcd_panel_id = panel_id =
viafb_read_reg(VIACR, CR3F) & 0x0F;
switch (panel_id) {
case 0x0:
viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x1:
viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x2:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x3:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x4:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x5:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x6:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x8:
viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x9:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0xA:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0xB:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0xC:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0xD:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0xE:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0xF:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0x10:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0x11:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x12:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x13:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x14:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0x15:
viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
case 0x16:
viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
break;
case 0x17:
/* OLPC XO-1.5 panel */
viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 0;
break;
default:
viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
viaparinfo->lvds_setting_info->LCDDithering = 1;
}
}
static int lvds_register_read(int index)
{
u8 data;
viafb_i2c_readbyte(VIA_PORT_2C,
(u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
(u8) index, &data);
return data;
}
static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
int panel_vres)
{
int reg_value = 0;
int viafb_load_reg_num;
struct io_register *reg = NULL;
DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
/* LCD Scaling Enable */
viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
/* Check if expansion for horizontal */
if (set_hres < panel_hres) {
/* Load Horizontal Scaling Factor */
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
reg_value =
CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
viafb_load_reg_num =
lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
reg_num;
reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_CN750:
case UNICHROME_VX800:
case UNICHROME_VX855:
case UNICHROME_VX900:
reg_value =
K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
/* Horizontal scaling enabled */
viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
viafb_load_reg_num =
lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
break;
}
DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
} else {
/* Horizontal scaling disabled */
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
}
/* Check if expansion for vertical */
if (set_vres < panel_vres) {
/* Load Vertical Scaling Factor */
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
reg_value =
CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
viafb_load_reg_num =
lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
reg_num;
reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_CN750:
case UNICHROME_VX800:
case UNICHROME_VX855:
case UNICHROME_VX900:
reg_value =
K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
/* Vertical scaling enabled */
viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
viafb_load_reg_num =
lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
viafb_load_reg(reg_value,
viafb_load_reg_num, reg, VIACR);
break;
}
DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
} else {
/* Vertical scaling disabled */
viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
}
}
static void via_pitch_alignment_patch_lcd(int iga_path, int hres, int bpp)
{
unsigned char cr13, cr35, cr65, cr66, cr67;
unsigned long dwScreenPitch = 0;
unsigned long dwPitch;
dwPitch = hres * (bpp >> 3);
if (dwPitch & 0x1F) {
dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
if (iga_path == IGA2) {
if (bpp > 8) {
cr66 = (unsigned char)(dwScreenPitch & 0xFF);
viafb_write_reg(CR66, VIACR, cr66);
cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
cr67 |=
(unsigned
char)((dwScreenPitch & 0x300) >> 8);
viafb_write_reg(CR67, VIACR, cr67);
}
/* Fetch Count */
cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
viafb_write_reg(CR67, VIACR, cr67);
cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
cr65 += 2;
viafb_write_reg(CR65, VIACR, cr65);
} else {
if (bpp > 8) {
cr13 = (unsigned char)(dwScreenPitch & 0xFF);
viafb_write_reg(CR13, VIACR, cr13);
cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
cr35 |=
(unsigned
char)((dwScreenPitch & 0x700) >> 3);
viafb_write_reg(CR35, VIACR, cr35);
}
}
}
}
static void lcd_patch_skew_dvp0(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_P4M900:
viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
plvds_chip_info);
break;
case UNICHROME_P4M890:
viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
plvds_chip_info);
break;
}
}
}
static void lcd_patch_skew_dvp1(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CX700:
viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
plvds_chip_info);
break;
}
}
}
static void lcd_patch_skew(struct lvds_setting_information
*plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
{
DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
switch (plvds_chip_info->output_interface) {
case INTERFACE_DVP0:
lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
break;
case INTERFACE_DVP1:
lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
break;
case INTERFACE_DFP_LOW:
if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
viafb_write_reg_mask(CR99, VIACR, 0x08,
BIT0 + BIT1 + BIT2 + BIT3);
}
break;
}
}
/* LCD Set Mode */
void viafb_lcd_set_mode(const struct fb_var_screeninfo *var, u16 cxres,
u16 cyres, struct lvds_setting_information *plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
int set_iga = plvds_setting_info->iga_path;
int mode_bpp = var->bits_per_pixel;
int set_hres = cxres ? cxres : var->xres;
int set_vres = cyres ? cyres : var->yres;
int panel_hres = plvds_setting_info->lcd_panel_hres;
int panel_vres = plvds_setting_info->lcd_panel_vres;
u32 clock;
struct via_display_timing timing;
struct fb_var_screeninfo panel_var;
const struct fb_videomode *panel_crt_table;
DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
/* Get panel table Pointer */
panel_crt_table = viafb_get_best_mode(panel_hres, panel_vres, 60);
viafb_fill_var_timing_info(&panel_var, panel_crt_table);
DEBUG_MSG(KERN_INFO "below viafb_lcd_set_mode!!\n");
if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
clock = PICOS2KHZ(panel_crt_table->pixclock) * 1000;
plvds_setting_info->vclk = clock;
if (set_iga == IGA2 && (set_hres < panel_hres || set_vres < panel_vres)
&& plvds_setting_info->display_method == LCD_EXPANDSION) {
timing = var_to_timing(&panel_var, panel_hres, panel_vres);
load_lcd_scaling(set_hres, set_vres, panel_hres, panel_vres);
} else {
timing = var_to_timing(&panel_var, set_hres, set_vres);
if (set_iga == IGA2)
/* disable scaling */
via_write_reg_mask(VIACR, 0x79, 0x00,
BIT0 + BIT1 + BIT2);
}
if (set_iga == IGA1)
via_set_primary_timing(&timing);
else if (set_iga == IGA2)
via_set_secondary_timing(&timing);
/* Fetch count for IGA2 only */
viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
&& (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
fill_lcd_format();
viafb_set_vclock(clock, set_iga);
lcd_patch_skew(plvds_setting_info, plvds_chip_info);
/* If K8M800, enable LCD Prefetch Mode. */
if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
|| (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
/* Patch for non 32bit alignment mode */
via_pitch_alignment_patch_lcd(plvds_setting_info->iga_path, set_hres,
var->bits_per_pixel);
}
static void integrated_lvds_disable(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
bool turn_off_first_powersequence = false;
bool turn_off_second_powersequence = false;
if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
turn_off_first_powersequence = true;
if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
turn_off_first_powersequence = true;
if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
turn_off_second_powersequence = true;
if (turn_off_second_powersequence) {
/* Use second power sequence control: */
/* Turn off power sequence. */
viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
/* Turn off back light. */
viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
}
if (turn_off_first_powersequence) {
/* Use first power sequence control: */
/* Turn off power sequence. */
viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
/* Turn off back light. */
viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
}
/* Power off LVDS channel. */
switch (plvds_chip_info->output_interface) {
case INTERFACE_LVDS0:
{
viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
break;
}
case INTERFACE_LVDS1:
{
viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
break;
}
case INTERFACE_LVDS0LVDS1:
{
viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
break;
}
}
}
static void integrated_lvds_enable(struct lvds_setting_information
*plvds_setting_info,
struct lvds_chip_information *plvds_chip_info)
{
DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
plvds_chip_info->output_interface);
if (plvds_setting_info->lcd_mode == LCD_SPWG)
viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
else
viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
switch (plvds_chip_info->output_interface) {
case INTERFACE_LVDS0LVDS1:
case INTERFACE_LVDS0:
/* Use first power sequence control: */
/* Use hardware control power sequence. */
viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
/* Turn on back light. */
viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
/* Turn on hardware power sequence. */
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
break;
case INTERFACE_LVDS1:
/* Use second power sequence control: */
/* Use hardware control power sequence. */
viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
/* Turn on back light. */
viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
/* Turn on hardware power sequence. */
viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
break;
}
/* Power on LVDS channel. */
switch (plvds_chip_info->output_interface) {
case INTERFACE_LVDS0:
{
viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
break;
}
case INTERFACE_LVDS1:
{
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
break;
}
case INTERFACE_LVDS0LVDS1:
{
viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
break;
}
}
}
void viafb_lcd_disable(void)
{
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
lcd_powersequence_off();
/* DI1 pad off */
viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
} else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
if (viafb_LCD2_ON
&& (INTEGRATED_LVDS ==
viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
integrated_lvds_disable(viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info2);
if (INTEGRATED_LVDS ==
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
integrated_lvds_disable(viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info);
if (VT1636_LVDS == viaparinfo->chip_info->
lvds_chip_info.lvds_chip_name)
viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info);
} else if (VT1636_LVDS ==
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info);
} else {
/* Backlight off */
viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
/* 24 bit DI data paht off */
viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
}
/* Disable expansion bit */
viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
/* Simultaneout disabled */
viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
}
static void set_lcd_output_path(int set_iga, int output_interface)
{
switch (output_interface) {
case INTERFACE_DFP:
if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
|| (UNICHROME_P4M890 ==
viaparinfo->chip_info->gfx_chip_name))
viafb_write_reg_mask(CR97, VIACR, 0x84,
BIT7 + BIT2 + BIT1 + BIT0);
fallthrough;
case INTERFACE_DVP0:
case INTERFACE_DVP1:
case INTERFACE_DFP_HIGH:
case INTERFACE_DFP_LOW:
if (set_iga == IGA2)
viafb_write_reg(CR91, VIACR, 0x00);
break;
}
}
void viafb_lcd_enable(void)
{
viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
set_lcd_output_path(viaparinfo->lvds_setting_info->iga_path,
viaparinfo->chip_info->lvds_chip_info.output_interface);
if (viafb_LCD2_ON)
set_lcd_output_path(viaparinfo->lvds_setting_info2->iga_path,
viaparinfo->chip_info->
lvds_chip_info2.output_interface);
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
/* DI1 pad on */
viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
lcd_powersequence_on();
} else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
&viaparinfo->chip_info->lvds_chip_info2);
if (INTEGRATED_LVDS ==
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
integrated_lvds_enable(viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info);
if (VT1636_LVDS == viaparinfo->chip_info->
lvds_chip_info.lvds_chip_name)
viafb_enable_lvds_vt1636(viaparinfo->
lvds_setting_info, &viaparinfo->chip_info->
lvds_chip_info);
} else if (VT1636_LVDS ==
viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
&viaparinfo->chip_info->lvds_chip_info);
} else {
/* Backlight on */
viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
/* 24 bit DI data paht on */
viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
/* LCD enabled */
viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
}
}
static void lcd_powersequence_off(void)
{
int i, mask, data;
/* Software control power sequence */
viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
for (i = 0; i < 3; i++) {
mask = PowerSequenceOff[0][i];
data = PowerSequenceOff[1][i] & mask;
viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
udelay(PowerSequenceOff[2][i]);
}
/* Disable LCD */
viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
}
static void lcd_powersequence_on(void)
{
int i, mask, data;
/* Software control power sequence */
viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
/* Enable LCD */
viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
for (i = 0; i < 3; i++) {
mask = PowerSequenceOn[0][i];
data = PowerSequenceOn[1][i] & mask;
viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
udelay(PowerSequenceOn[2][i]);
}
udelay(1);
}
static void fill_lcd_format(void)
{
u8 bdithering = 0, bdual = 0;
if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
bdual = BIT4;
if (viaparinfo->lvds_setting_info->LCDDithering)
bdithering = BIT0;
/* Dual & Dithering */
viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
}
static void check_diport_of_integrated_lvds(
struct lvds_chip_information *plvds_chip_info,
struct lvds_setting_information
*plvds_setting_info)
{
/* Determine LCD DI Port by hardware layout. */
switch (viafb_display_hardware_layout) {
case HW_LAYOUT_LCD_ONLY:
{
if (plvds_setting_info->device_lcd_dualedge) {
plvds_chip_info->output_interface =
INTERFACE_LVDS0LVDS1;
} else {
plvds_chip_info->output_interface =
INTERFACE_LVDS0;
}
break;
}
case HW_LAYOUT_DVI_ONLY:
{
plvds_chip_info->output_interface = INTERFACE_NONE;
break;
}
case HW_LAYOUT_LCD1_LCD2:
case HW_LAYOUT_LCD_EXTERNAL_LCD2:
{
plvds_chip_info->output_interface =
INTERFACE_LVDS0LVDS1;
break;
}
case HW_LAYOUT_LCD_DVI:
{
plvds_chip_info->output_interface = INTERFACE_LVDS1;
break;
}
default:
{
plvds_chip_info->output_interface = INTERFACE_LVDS1;
break;
}
}
DEBUG_MSG(KERN_INFO
"Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
viafb_display_hardware_layout,
plvds_chip_info->output_interface);
}
void viafb_init_lvds_output_interface(struct lvds_chip_information
*plvds_chip_info,
struct lvds_setting_information
*plvds_setting_info)
{
if (INTERFACE_NONE != plvds_chip_info->output_interface) {
/*Do nothing, lcd port is specified by module parameter */
return;
}
switch (plvds_chip_info->lvds_chip_name) {
case VT1636_LVDS:
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CX700:
plvds_chip_info->output_interface = INTERFACE_DVP1;
break;
case UNICHROME_CN700:
plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
break;
default:
plvds_chip_info->output_interface = INTERFACE_DVP0;
break;
}
break;
case INTEGRATED_LVDS:
check_diport_of_integrated_lvds(plvds_chip_info,
plvds_setting_info);
break;
default:
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
case UNICHROME_P4M890:
plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
break;
default:
plvds_chip_info->output_interface = INTERFACE_DFP;
break;
}
break;
}
}
bool viafb_lcd_get_mobile_state(bool *mobile)
{
unsigned char __iomem *romptr, *tableptr, *biosptr;
u8 core_base;
/* Rom address */
const u32 romaddr = 0x000C0000;
u16 start_pattern;
biosptr = ioremap(romaddr, 0x10000);
start_pattern = readw(biosptr);
/* Compare pattern */
if (start_pattern == 0xAA55) {
/* Get the start of Table */
/* 0x1B means BIOS offset position */
romptr = biosptr + 0x1B;
tableptr = biosptr + readw(romptr);
/* Get the start of biosver structure */
/* 18 means BIOS version position. */
romptr = tableptr + 18;
romptr = biosptr + readw(romptr);
/* The offset should be 44, but the
actual image is less three char. */
/* pRom += 44; */
romptr += 41;
core_base = readb(romptr);
if (core_base & 0x8)
*mobile = false;
else
*mobile = true;
/* release memory */
iounmap(biosptr);
return true;
} else {
iounmap(biosptr);
return false;
}
}
| linux-master | drivers/video/fbdev/via/lcd.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include "global.h"
int viafb_platform_epia_dvi = STATE_OFF;
int viafb_device_lcd_dualedge = STATE_OFF;
int viafb_bus_width = 12;
int viafb_display_hardware_layout = HW_LAYOUT_LCD_DVI;
int viafb_DeviceStatus = CRT_Device;
int viafb_hotplug;
int viafb_refresh = 60;
int viafb_refresh1 = 60;
int viafb_lcd_dsp_method = LCD_EXPANDSION;
int viafb_lcd_mode = LCD_OPENLDI;
int viafb_CRT_ON = 1;
int viafb_DVI_ON;
int viafb_LCD_ON ;
int viafb_LCD2_ON;
int viafb_SAMM_ON;
int viafb_dual_fb;
unsigned int viafb_second_xres = 640;
unsigned int viafb_second_yres = 480;
int viafb_hotplug_Xres = 640;
int viafb_hotplug_Yres = 480;
int viafb_hotplug_bpp = 32;
int viafb_hotplug_refresh = 60;
int viafb_primary_dev = None_Device;
int viafb_lcd_panel_id = LCD_PANEL_ID_MAXIMUM + 1;
struct fb_info *viafbinfo;
struct fb_info *viafbinfo1;
struct viafb_par *viaparinfo;
struct viafb_par *viaparinfo1;
| linux-master | drivers/video/fbdev/via/global.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
* Copyright 2009 Jonathan Corbet <[email protected]>
*/
/*
* Core code for the Via multifunction framebuffer device.
*/
#include <linux/aperture.h>
#include <linux/via-core.h>
#include <linux/via_i2c.h>
#include "via-gpio.h"
#include "global.h"
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/pm.h>
/*
* The default port config.
*/
static struct via_port_cfg adap_configs[] = {
[VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
[VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
[VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
[VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_I2C, VIASR, 0x2c },
[VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x3d },
{ 0, 0, 0, 0 }
};
/*
* The OLPC XO-1.5 puts the camera power and reset lines onto
* GPIO 2C.
*/
static struct via_port_cfg olpc_adap_configs[] = {
[VIA_PORT_26] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x26 },
[VIA_PORT_31] = { VIA_PORT_I2C, VIA_MODE_I2C, VIASR, 0x31 },
[VIA_PORT_25] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x25 },
[VIA_PORT_2C] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x2c },
[VIA_PORT_3D] = { VIA_PORT_GPIO, VIA_MODE_GPIO, VIASR, 0x3d },
{ 0, 0, 0, 0 }
};
/*
* We currently only support one viafb device (will there ever be
* more than one?), so just declare it globally here.
*/
static struct viafb_dev global_dev;
/*
* Basic register access; spinlock required.
*/
static inline void viafb_mmio_write(int reg, u32 v)
{
iowrite32(v, global_dev.engine_mmio + reg);
}
static inline int viafb_mmio_read(int reg)
{
return ioread32(global_dev.engine_mmio + reg);
}
/* ---------------------------------------------------------------------- */
/*
* Interrupt management. We have a single IRQ line for a lot of
* different functions, so we need to share it. The design here
* is that we don't want to reimplement the shared IRQ code here;
* we also want to avoid having contention for a single handler thread.
* So each subdev driver which needs interrupts just requests
* them directly from the kernel. We just have what's needed for
* overall access to the interrupt control register.
*/
/*
* Which interrupts are enabled now?
*/
static u32 viafb_enabled_ints;
static void viafb_int_init(void)
{
viafb_enabled_ints = 0;
viafb_mmio_write(VDE_INTERRUPT, 0);
}
/*
* Allow subdevs to ask for specific interrupts to be enabled. These
* functions must be called with reg_lock held
*/
void viafb_irq_enable(u32 mask)
{
viafb_enabled_ints |= mask;
viafb_mmio_write(VDE_INTERRUPT, viafb_enabled_ints | VDE_I_ENABLE);
}
EXPORT_SYMBOL_GPL(viafb_irq_enable);
void viafb_irq_disable(u32 mask)
{
viafb_enabled_ints &= ~mask;
if (viafb_enabled_ints == 0)
viafb_mmio_write(VDE_INTERRUPT, 0); /* Disable entirely */
else
viafb_mmio_write(VDE_INTERRUPT,
viafb_enabled_ints | VDE_I_ENABLE);
}
EXPORT_SYMBOL_GPL(viafb_irq_disable);
/* ---------------------------------------------------------------------- */
/*
* Currently, the camera driver is the only user of the DMA code, so we
* only compile it in if the camera driver is being built. Chances are,
* most viafb systems will not need to have this extra code for a while.
* As soon as another user comes long, the ifdef can be removed.
*/
#if IS_ENABLED(CONFIG_VIDEO_VIA_CAMERA)
/*
* Access to the DMA engine. This currently provides what the camera
* driver needs (i.e. outgoing only) but is easily expandable if need
* be.
*/
/*
* There are four DMA channels in the vx855. For now, we only
* use one of them, though. Most of the time, the DMA channel
* will be idle, so we keep the IRQ handler unregistered except
* when some subsystem has indicated an interest.
*/
static int viafb_dma_users;
static DECLARE_COMPLETION(viafb_dma_completion);
/*
* This mutex protects viafb_dma_users and our global interrupt
* registration state; it also serializes access to the DMA
* engine.
*/
static DEFINE_MUTEX(viafb_dma_lock);
/*
* The VX855 DMA descriptor (used for s/g transfers) looks
* like this.
*/
struct viafb_vx855_dma_descr {
u32 addr_low; /* Low part of phys addr */
u32 addr_high; /* High 12 bits of addr */
u32 fb_offset; /* Offset into FB memory */
u32 seg_size; /* Size, 16-byte units */
u32 tile_mode; /* "tile mode" setting */
u32 next_desc_low; /* Next descriptor addr */
u32 next_desc_high;
u32 pad; /* Fill out to 64 bytes */
};
/*
* Flags added to the "next descriptor low" pointers
*/
#define VIAFB_DMA_MAGIC 0x01 /* ??? Just has to be there */
#define VIAFB_DMA_FINAL_SEGMENT 0x02 /* Final segment */
/*
* The completion IRQ handler.
*/
static irqreturn_t viafb_dma_irq(int irq, void *data)
{
int csr;
irqreturn_t ret = IRQ_NONE;
spin_lock(&global_dev.reg_lock);
csr = viafb_mmio_read(VDMA_CSR0);
if (csr & VDMA_C_DONE) {
viafb_mmio_write(VDMA_CSR0, VDMA_C_DONE);
complete(&viafb_dma_completion);
ret = IRQ_HANDLED;
}
spin_unlock(&global_dev.reg_lock);
return ret;
}
/*
* Indicate a need for DMA functionality.
*/
int viafb_request_dma(void)
{
int ret = 0;
/*
* Only VX855 is supported currently.
*/
if (global_dev.chip_type != UNICHROME_VX855)
return -ENODEV;
/*
* Note the new user and set up our interrupt handler
* if need be.
*/
mutex_lock(&viafb_dma_lock);
viafb_dma_users++;
if (viafb_dma_users == 1) {
ret = request_irq(global_dev.pdev->irq, viafb_dma_irq,
IRQF_SHARED, "via-dma", &viafb_dma_users);
if (ret)
viafb_dma_users--;
else
viafb_irq_enable(VDE_I_DMA0TDEN);
}
mutex_unlock(&viafb_dma_lock);
return ret;
}
EXPORT_SYMBOL_GPL(viafb_request_dma);
void viafb_release_dma(void)
{
mutex_lock(&viafb_dma_lock);
viafb_dma_users--;
if (viafb_dma_users == 0) {
viafb_irq_disable(VDE_I_DMA0TDEN);
free_irq(global_dev.pdev->irq, &viafb_dma_users);
}
mutex_unlock(&viafb_dma_lock);
}
EXPORT_SYMBOL_GPL(viafb_release_dma);
/*
* Do a scatter/gather DMA copy from FB memory. You must have done
* a successful call to viafb_request_dma() first.
*/
int viafb_dma_copy_out_sg(unsigned int offset, struct scatterlist *sg, int nsg)
{
struct viafb_vx855_dma_descr *descr;
void *descrpages;
dma_addr_t descr_handle;
unsigned long flags;
int i;
struct scatterlist *sgentry;
dma_addr_t nextdesc;
/*
* Get a place to put the descriptors.
*/
descrpages = dma_alloc_coherent(&global_dev.pdev->dev,
nsg*sizeof(struct viafb_vx855_dma_descr),
&descr_handle, GFP_KERNEL);
if (descrpages == NULL) {
dev_err(&global_dev.pdev->dev, "Unable to get descr page.\n");
return -ENOMEM;
}
mutex_lock(&viafb_dma_lock);
/*
* Fill them in.
*/
descr = descrpages;
nextdesc = descr_handle + sizeof(struct viafb_vx855_dma_descr);
for_each_sg(sg, sgentry, nsg, i) {
dma_addr_t paddr = sg_dma_address(sgentry);
descr->addr_low = paddr & 0xfffffff0;
descr->addr_high = ((u64) paddr >> 32) & 0x0fff;
descr->fb_offset = offset;
descr->seg_size = sg_dma_len(sgentry) >> 4;
descr->tile_mode = 0;
descr->next_desc_low = (nextdesc&0xfffffff0) | VIAFB_DMA_MAGIC;
descr->next_desc_high = ((u64) nextdesc >> 32) & 0x0fff;
descr->pad = 0xffffffff; /* VIA driver does this */
offset += sg_dma_len(sgentry);
nextdesc += sizeof(struct viafb_vx855_dma_descr);
descr++;
}
descr[-1].next_desc_low = VIAFB_DMA_FINAL_SEGMENT|VIAFB_DMA_MAGIC;
/*
* Program the engine.
*/
spin_lock_irqsave(&global_dev.reg_lock, flags);
init_completion(&viafb_dma_completion);
viafb_mmio_write(VDMA_DQWCR0, 0);
viafb_mmio_write(VDMA_CSR0, VDMA_C_ENABLE|VDMA_C_DONE);
viafb_mmio_write(VDMA_MR0, VDMA_MR_TDIE | VDMA_MR_CHAIN);
viafb_mmio_write(VDMA_DPRL0, descr_handle | VIAFB_DMA_MAGIC);
viafb_mmio_write(VDMA_DPRH0,
(((u64)descr_handle >> 32) & 0x0fff) | 0xf0000);
(void) viafb_mmio_read(VDMA_CSR0);
viafb_mmio_write(VDMA_CSR0, VDMA_C_ENABLE|VDMA_C_START);
spin_unlock_irqrestore(&global_dev.reg_lock, flags);
/*
* Now we just wait until the interrupt handler says
* we're done. Except that, actually, we need to wait a little
* longer: the interrupts seem to jump the gun a little and we
* get corrupted frames sometimes.
*/
wait_for_completion_timeout(&viafb_dma_completion, 1);
msleep(1);
if ((viafb_mmio_read(VDMA_CSR0)&VDMA_C_DONE) == 0)
printk(KERN_ERR "VIA DMA timeout!\n");
/*
* Clean up and we're done.
*/
viafb_mmio_write(VDMA_CSR0, VDMA_C_DONE);
viafb_mmio_write(VDMA_MR0, 0); /* Reset int enable */
mutex_unlock(&viafb_dma_lock);
dma_free_coherent(&global_dev.pdev->dev,
nsg*sizeof(struct viafb_vx855_dma_descr), descrpages,
descr_handle);
return 0;
}
EXPORT_SYMBOL_GPL(viafb_dma_copy_out_sg);
#endif /* CONFIG_VIDEO_VIA_CAMERA */
/* ---------------------------------------------------------------------- */
/*
* Figure out how big our framebuffer memory is. Kind of ugly,
* but evidently we can't trust the information found in the
* fbdev configuration area.
*/
static u16 via_function3[] = {
CLE266_FUNCTION3, KM400_FUNCTION3, CN400_FUNCTION3, CN700_FUNCTION3,
CX700_FUNCTION3, KM800_FUNCTION3, KM890_FUNCTION3, P4M890_FUNCTION3,
P4M900_FUNCTION3, VX800_FUNCTION3, VX855_FUNCTION3, VX900_FUNCTION3,
};
/* Get the BIOS-configured framebuffer size from PCI configuration space
* of function 3 in the respective chipset */
static int viafb_get_fb_size_from_pci(int chip_type)
{
int i;
u8 offset = 0;
u32 FBSize;
u32 VideoMemSize;
/* search for the "FUNCTION3" device in this chipset */
for (i = 0; i < ARRAY_SIZE(via_function3); i++) {
struct pci_dev *pdev;
pdev = pci_get_device(PCI_VENDOR_ID_VIA, via_function3[i],
NULL);
if (!pdev)
continue;
DEBUG_MSG(KERN_INFO "Device ID = %x\n", pdev->device);
switch (pdev->device) {
case CLE266_FUNCTION3:
case KM400_FUNCTION3:
offset = 0xE0;
break;
case CN400_FUNCTION3:
case CN700_FUNCTION3:
case CX700_FUNCTION3:
case KM800_FUNCTION3:
case KM890_FUNCTION3:
case P4M890_FUNCTION3:
case P4M900_FUNCTION3:
case VX800_FUNCTION3:
case VX855_FUNCTION3:
case VX900_FUNCTION3:
/*case CN750_FUNCTION3: */
offset = 0xA0;
break;
}
if (!offset)
break;
pci_read_config_dword(pdev, offset, &FBSize);
pci_dev_put(pdev);
}
if (!offset) {
printk(KERN_ERR "cannot determine framebuffer size\n");
return -EIO;
}
FBSize = FBSize & 0x00007000;
DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
if (chip_type < UNICHROME_CX700) {
switch (FBSize) {
case 0x00004000:
VideoMemSize = (16 << 20); /*16M */
break;
case 0x00005000:
VideoMemSize = (32 << 20); /*32M */
break;
case 0x00006000:
VideoMemSize = (64 << 20); /*64M */
break;
default:
VideoMemSize = (32 << 20); /*32M */
break;
}
} else {
switch (FBSize) {
case 0x00001000:
VideoMemSize = (8 << 20); /*8M */
break;
case 0x00002000:
VideoMemSize = (16 << 20); /*16M */
break;
case 0x00003000:
VideoMemSize = (32 << 20); /*32M */
break;
case 0x00004000:
VideoMemSize = (64 << 20); /*64M */
break;
case 0x00005000:
VideoMemSize = (128 << 20); /*128M */
break;
case 0x00006000:
VideoMemSize = (256 << 20); /*256M */
break;
case 0x00007000: /* Only on VX855/875 */
VideoMemSize = (512 << 20); /*512M */
break;
default:
VideoMemSize = (32 << 20); /*32M */
break;
}
}
return VideoMemSize;
}
/*
* Figure out and map our MMIO regions.
*/
static int via_pci_setup_mmio(struct viafb_dev *vdev)
{
int ret;
/*
* Hook up to the device registers. Note that we soldier
* on if it fails; the framebuffer can operate (without
* acceleration) without this region.
*/
vdev->engine_start = pci_resource_start(vdev->pdev, 1);
vdev->engine_len = pci_resource_len(vdev->pdev, 1);
vdev->engine_mmio = ioremap(vdev->engine_start,
vdev->engine_len);
if (vdev->engine_mmio == NULL)
dev_err(&vdev->pdev->dev,
"Unable to map engine MMIO; operation will be "
"slow and crippled.\n");
/*
* Map in framebuffer memory. For now, failure here is
* fatal. Unfortunately, in the absence of significant
* vmalloc space, failure here is also entirely plausible.
* Eventually we want to move away from mapping this
* entire region.
*/
if (vdev->chip_type == UNICHROME_VX900)
vdev->fbmem_start = pci_resource_start(vdev->pdev, 2);
else
vdev->fbmem_start = pci_resource_start(vdev->pdev, 0);
ret = vdev->fbmem_len = viafb_get_fb_size_from_pci(vdev->chip_type);
if (ret < 0)
goto out_unmap;
/* try to map less memory on failure, 8 MB should be still enough */
for (; vdev->fbmem_len >= 8 << 20; vdev->fbmem_len /= 2) {
vdev->fbmem = ioremap_wc(vdev->fbmem_start, vdev->fbmem_len);
if (vdev->fbmem)
break;
}
if (vdev->fbmem == NULL) {
ret = -ENOMEM;
goto out_unmap;
}
return 0;
out_unmap:
iounmap(vdev->engine_mmio);
return ret;
}
static void via_pci_teardown_mmio(struct viafb_dev *vdev)
{
iounmap(vdev->fbmem);
iounmap(vdev->engine_mmio);
}
/*
* Create our subsidiary devices.
*/
static struct viafb_subdev_info {
char *name;
struct platform_device *platdev;
} viafb_subdevs[] = {
{
.name = "viafb-gpio",
},
{
.name = "viafb-i2c",
},
#if IS_ENABLED(CONFIG_VIDEO_VIA_CAMERA)
{
.name = "viafb-camera",
},
#endif
};
#define N_SUBDEVS ARRAY_SIZE(viafb_subdevs)
static int via_create_subdev(struct viafb_dev *vdev,
struct viafb_subdev_info *info)
{
int ret;
info->platdev = platform_device_alloc(info->name, -1);
if (!info->platdev) {
dev_err(&vdev->pdev->dev, "Unable to allocate pdev %s\n",
info->name);
return -ENOMEM;
}
info->platdev->dev.parent = &vdev->pdev->dev;
info->platdev->dev.platform_data = vdev;
ret = platform_device_add(info->platdev);
if (ret) {
dev_err(&vdev->pdev->dev, "Unable to add pdev %s\n",
info->name);
platform_device_put(info->platdev);
info->platdev = NULL;
}
return ret;
}
static int via_setup_subdevs(struct viafb_dev *vdev)
{
int i;
/*
* Ignore return values. Even if some of the devices
* fail to be created, we'll still be able to use some
* of the rest.
*/
for (i = 0; i < N_SUBDEVS; i++)
via_create_subdev(vdev, viafb_subdevs + i);
return 0;
}
static void via_teardown_subdevs(void)
{
int i;
for (i = 0; i < N_SUBDEVS; i++)
if (viafb_subdevs[i].platdev) {
viafb_subdevs[i].platdev->dev.platform_data = NULL;
platform_device_unregister(viafb_subdevs[i].platdev);
}
}
/*
* Power management functions
*/
static __maybe_unused LIST_HEAD(viafb_pm_hooks);
static __maybe_unused DEFINE_MUTEX(viafb_pm_hooks_lock);
void viafb_pm_register(struct viafb_pm_hooks *hooks)
{
INIT_LIST_HEAD(&hooks->list);
mutex_lock(&viafb_pm_hooks_lock);
list_add_tail(&hooks->list, &viafb_pm_hooks);
mutex_unlock(&viafb_pm_hooks_lock);
}
EXPORT_SYMBOL_GPL(viafb_pm_register);
void viafb_pm_unregister(struct viafb_pm_hooks *hooks)
{
mutex_lock(&viafb_pm_hooks_lock);
list_del(&hooks->list);
mutex_unlock(&viafb_pm_hooks_lock);
}
EXPORT_SYMBOL_GPL(viafb_pm_unregister);
static int __maybe_unused via_suspend(struct device *dev)
{
struct viafb_pm_hooks *hooks;
/*
* "I've occasionally hit a few drivers that caused suspend
* failures, and each and every time it was a driver bug, and
* the right thing to do was to just ignore the error and suspend
* anyway - returning an error code and trying to undo the suspend
* is not what anybody ever really wants, even if our model
*_allows_ for it."
* -- Linus Torvalds, Dec. 7, 2009
*/
mutex_lock(&viafb_pm_hooks_lock);
list_for_each_entry_reverse(hooks, &viafb_pm_hooks, list)
hooks->suspend(hooks->private);
mutex_unlock(&viafb_pm_hooks_lock);
return 0;
}
static int __maybe_unused via_resume(struct device *dev)
{
struct viafb_pm_hooks *hooks;
/* Now bring back any subdevs */
mutex_lock(&viafb_pm_hooks_lock);
list_for_each_entry(hooks, &viafb_pm_hooks, list)
hooks->resume(hooks->private);
mutex_unlock(&viafb_pm_hooks_lock);
return 0;
}
static int via_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
int ret;
ret = aperture_remove_conflicting_pci_devices(pdev, "viafb");
if (ret)
return ret;
ret = pci_enable_device(pdev);
if (ret)
return ret;
/*
* Global device initialization.
*/
memset(&global_dev, 0, sizeof(global_dev));
global_dev.pdev = pdev;
global_dev.chip_type = ent->driver_data;
global_dev.port_cfg = adap_configs;
if (machine_is_olpc())
global_dev.port_cfg = olpc_adap_configs;
spin_lock_init(&global_dev.reg_lock);
ret = via_pci_setup_mmio(&global_dev);
if (ret)
goto out_disable;
/*
* Set up interrupts and create our subdevices. Continue even if
* some things fail.
*/
viafb_int_init();
via_setup_subdevs(&global_dev);
/*
* Set up the framebuffer device
*/
ret = via_fb_pci_probe(&global_dev);
if (ret)
goto out_subdevs;
return 0;
out_subdevs:
via_teardown_subdevs();
via_pci_teardown_mmio(&global_dev);
out_disable:
pci_disable_device(pdev);
return ret;
}
static void via_pci_remove(struct pci_dev *pdev)
{
via_teardown_subdevs();
via_fb_pci_remove(pdev);
via_pci_teardown_mmio(&global_dev);
pci_disable_device(pdev);
}
static const struct pci_device_id via_pci_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_CLE266_DID),
.driver_data = UNICHROME_CLE266 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_K400_DID),
.driver_data = UNICHROME_K400 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_K800_DID),
.driver_data = UNICHROME_K800 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_PM800_DID),
.driver_data = UNICHROME_PM800 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_CN700_DID),
.driver_data = UNICHROME_CN700 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_CX700_DID),
.driver_data = UNICHROME_CX700 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_CN750_DID),
.driver_data = UNICHROME_CN750 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_K8M890_DID),
.driver_data = UNICHROME_K8M890 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_P4M890_DID),
.driver_data = UNICHROME_P4M890 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_P4M900_DID),
.driver_data = UNICHROME_P4M900 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX800_DID),
.driver_data = UNICHROME_VX800 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX855_DID),
.driver_data = UNICHROME_VX855 },
{ PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX900_DID),
.driver_data = UNICHROME_VX900 },
{ }
};
MODULE_DEVICE_TABLE(pci, via_pci_table);
static const struct dev_pm_ops via_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = via_suspend,
.resume = via_resume,
.freeze = NULL,
.thaw = via_resume,
.poweroff = NULL,
.restore = via_resume,
#endif
};
static struct pci_driver via_driver = {
.name = "viafb",
.id_table = via_pci_table,
.probe = via_pci_probe,
.remove = via_pci_remove,
.driver.pm = &via_pm_ops,
};
static int __init via_core_init(void)
{
int ret;
if (fb_modesetting_disabled("viafb"))
return -ENODEV;
ret = viafb_init();
if (ret)
return ret;
viafb_i2c_init();
viafb_gpio_init();
ret = pci_register_driver(&via_driver);
if (ret) {
viafb_gpio_exit();
viafb_i2c_exit();
return ret;
}
return 0;
}
static void __exit via_core_exit(void)
{
pci_unregister_driver(&via_driver);
viafb_gpio_exit();
viafb_i2c_exit();
viafb_exit();
}
module_init(via_core_init);
module_exit(via_core_exit);
| linux-master | drivers/video/fbdev/via/via-core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/via-core.h>
#include <linux/via_i2c.h>
#include "global.h"
static void tmds_register_write(int index, u8 data);
static int tmds_register_read(int index);
static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
static void dvi_get_panel_size_from_DDCv1(
struct tmds_chip_information *tmds_chip,
struct tmds_setting_information *tmds_setting);
static int viafb_dvi_query_EDID(void);
static inline bool check_tmds_chip(int device_id_subaddr, int device_id)
{
return tmds_register_read(device_id_subaddr) == device_id;
}
void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
struct tmds_setting_information *tmds_setting)
{
DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
viafb_dvi_sense();
if (viafb_dvi_query_EDID() == 1)
dvi_get_panel_size_from_DDCv1(tmds_chip, tmds_setting);
return;
}
bool viafb_tmds_trasmitter_identify(void)
{
unsigned char sr2a = 0, sr1e = 0, sr3e = 0;
/* Turn on ouputting pad */
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_K8M890:
/*=* DFP Low Pad on *=*/
sr2a = viafb_read_reg(VIASR, SR2A);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
break;
case UNICHROME_P4M900:
case UNICHROME_P4M890:
/* DFP Low Pad on */
sr2a = viafb_read_reg(VIASR, SR2A);
viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
/* DVP0 Pad on */
sr1e = viafb_read_reg(VIASR, SR1E);
viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
break;
default:
/* DVP0/DVP1 Pad on */
sr1e = viafb_read_reg(VIASR, SR1E);
viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
BIT5 + BIT6 + BIT7);
/* SR3E[1]Multi-function selection:
0 = Emulate I2C and DDC bus by GPIO2/3/4. */
sr3e = viafb_read_reg(VIASR, SR3E);
viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);
break;
}
/* Check for VT1632: */
viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = VT1632_TMDS;
viaparinfo->chip_info->
tmds_chip_info.tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_31;
if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)) {
/*
* Currently only support 12bits,dual edge,add 24bits mode later
*/
tmds_register_write(0x08, 0x3b);
DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
DEBUG_MSG(KERN_INFO "\n %2d",
viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
DEBUG_MSG(KERN_INFO "\n %2d",
viaparinfo->chip_info->tmds_chip_info.i2c_port);
return true;
} else {
viaparinfo->chip_info->tmds_chip_info.i2c_port = VIA_PORT_2C;
if (check_tmds_chip(VT1632_DEVICE_ID_REG, VT1632_DEVICE_ID)) {
tmds_register_write(0x08, 0x3b);
DEBUG_MSG(KERN_INFO "\n VT1632 TMDS ! \n");
DEBUG_MSG(KERN_INFO "\n %2d",
viaparinfo->chip_info->
tmds_chip_info.tmds_chip_name);
DEBUG_MSG(KERN_INFO "\n %2d",
viaparinfo->chip_info->
tmds_chip_info.i2c_port);
return true;
}
}
viaparinfo->chip_info->tmds_chip_info.tmds_chip_name = INTEGRATED_TMDS;
if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) &&
((viafb_display_hardware_layout == HW_LAYOUT_DVI_ONLY) ||
(viafb_display_hardware_layout == HW_LAYOUT_LCD_DVI))) {
DEBUG_MSG(KERN_INFO "\n Integrated TMDS ! \n");
return true;
}
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_K8M890:
viafb_write_reg(SR2A, VIASR, sr2a);
break;
case UNICHROME_P4M900:
case UNICHROME_P4M890:
viafb_write_reg(SR2A, VIASR, sr2a);
viafb_write_reg(SR1E, VIASR, sr1e);
break;
default:
viafb_write_reg(SR1E, VIASR, sr1e);
viafb_write_reg(SR3E, VIASR, sr3e);
break;
}
viaparinfo->chip_info->
tmds_chip_info.tmds_chip_name = NON_TMDS_TRANSMITTER;
viaparinfo->chip_info->tmds_chip_info.
tmds_chip_slave_addr = VT1632_TMDS_I2C_ADDR;
return false;
}
static void tmds_register_write(int index, u8 data)
{
viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
index, data);
}
static int tmds_register_read(int index)
{
u8 data;
viafb_i2c_readbyte(viaparinfo->chip_info->tmds_chip_info.i2c_port,
(u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
(u8) index, &data);
return data;
}
static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
{
viafb_i2c_readbytes(viaparinfo->chip_info->tmds_chip_info.i2c_port,
(u8) viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr,
(u8) index, buff, buff_len);
return 0;
}
/* DVI Set Mode */
void viafb_dvi_set_mode(const struct fb_var_screeninfo *var,
u16 cxres, u16 cyres, int iga)
{
struct fb_var_screeninfo dvi_var = *var;
const struct fb_videomode *rb_mode;
int maxPixelClock;
maxPixelClock = viaparinfo->shared->tmds_setting_info.max_pixel_clock;
if (maxPixelClock && PICOS2KHZ(var->pixclock) / 1000 > maxPixelClock) {
rb_mode = viafb_get_best_rb_mode(var->xres, var->yres, 60);
if (rb_mode)
viafb_fill_var_timing_info(&dvi_var, rb_mode);
}
viafb_fill_crtc_timing(&dvi_var, cxres, cyres, iga);
}
/* Sense DVI Connector */
int viafb_dvi_sense(void)
{
u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,
RegCR93 = 0, RegCR9B = 0, data;
int ret = false;
DEBUG_MSG(KERN_INFO "viafb_dvi_sense!!\n");
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
/* DI1 Pad on */
RegSR1E = viafb_read_reg(VIASR, SR1E);
viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);
/* CR6B[0]VCK Input Selection: 1 = External clock. */
RegCR6B = viafb_read_reg(VIACR, CR6B);
viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);
/* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
[0] Software Control Power Sequence */
RegCR91 = viafb_read_reg(VIACR, CR91);
viafb_write_reg(CR91, VIACR, 0x1D);
/* CR93[7] DI1 Data Source Selection: 1 = DSP2.
CR93[5] DI1 Clock Source: 1 = internal.
CR93[4] DI1 Clock Polarity.
CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */
RegCR93 = viafb_read_reg(VIACR, CR93);
viafb_write_reg(CR93, VIACR, 0x01);
} else {
/* DVP0/DVP1 Pad on */
RegSR1E = viafb_read_reg(VIASR, SR1E);
viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);
/* SR3E[1]Multi-function selection:
0 = Emulate I2C and DDC bus by GPIO2/3/4. */
RegSR3E = viafb_read_reg(VIASR, SR3E);
viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));
/* CR91[4] VDD On [3] Data On [2] VEE On [1] Back Light Off
[0] Software Control Power Sequence */
RegCR91 = viafb_read_reg(VIACR, CR91);
viafb_write_reg(CR91, VIACR, 0x1D);
/*CR9B[4] DVP1 Data Source Selection: 1 = From secondary
display.CR9B[2:0] DVP1 Clock Adjust */
RegCR9B = viafb_read_reg(VIACR, CR9B);
viafb_write_reg(CR9B, VIACR, 0x01);
}
data = (u8) tmds_register_read(0x09);
if (data & 0x04)
ret = true;
if (ret == false) {
if (viafb_dvi_query_EDID())
ret = true;
}
/* Restore status */
viafb_write_reg(SR1E, VIASR, RegSR1E);
viafb_write_reg(CR91, VIACR, RegCR91);
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
viafb_write_reg(CR6B, VIACR, RegCR6B);
viafb_write_reg(CR93, VIACR, RegCR93);
} else {
viafb_write_reg(SR3E, VIASR, RegSR3E);
viafb_write_reg(CR9B, VIACR, RegCR9B);
}
return ret;
}
/* Query Flat Panel's EDID Table Version Through DVI Connector */
static int viafb_dvi_query_EDID(void)
{
u8 data0, data1;
int restore;
DEBUG_MSG(KERN_INFO "viafb_dvi_query_EDID!!\n");
restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr;
viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0;
data0 = (u8) tmds_register_read(0x00);
data1 = (u8) tmds_register_read(0x01);
if ((data0 == 0) && (data1 == 0xFF)) {
viaparinfo->chip_info->
tmds_chip_info.tmds_chip_slave_addr = restore;
return EDID_VERSION_1; /* Found EDID1 Table */
}
return false;
}
/* Get Panel Size Using EDID1 Table */
static void dvi_get_panel_size_from_DDCv1(
struct tmds_chip_information *tmds_chip,
struct tmds_setting_information *tmds_setting)
{
int i, restore;
unsigned char EDID_DATA[18];
DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
restore = tmds_chip->tmds_chip_slave_addr;
tmds_chip->tmds_chip_slave_addr = 0xA0;
for (i = 0x25; i < 0x6D; i++) {
switch (i) {
case 0x36:
case 0x48:
case 0x5A:
case 0x6C:
tmds_register_read_bytes(i, EDID_DATA, 10);
if (!(EDID_DATA[0] || EDID_DATA[1])) {
/* The first two byte must be zero. */
if (EDID_DATA[3] == 0xFD) {
/* To get max pixel clock. */
tmds_setting->max_pixel_clock =
EDID_DATA[9] * 10;
}
}
break;
default:
break;
}
}
DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
tmds_setting->max_pixel_clock);
tmds_chip->tmds_chip_slave_addr = restore;
}
/* If Disable DVI, turn off pad */
void viafb_dvi_disable(void)
{
if (viaparinfo->chip_info->
tmds_chip_info.output_interface == INTERFACE_TMDS)
/* Turn off TMDS power. */
viafb_write_reg(CRD2, VIACR,
viafb_read_reg(VIACR, CRD2) | 0x08);
}
static void dvi_patch_skew_dvp0(void)
{
/* Reset data driving first: */
viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_P4M890:
{
if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
(viaparinfo->tmds_setting_info->v_active ==
1200))
viafb_write_reg_mask(CR96, VIACR, 0x03,
BIT0 + BIT1 + BIT2);
else
viafb_write_reg_mask(CR96, VIACR, 0x07,
BIT0 + BIT1 + BIT2);
break;
}
case UNICHROME_P4M900:
{
viafb_write_reg_mask(CR96, VIACR, 0x07,
BIT0 + BIT1 + BIT2 + BIT3);
viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
break;
}
default:
{
break;
}
}
}
static void dvi_patch_skew_dvp_low(void)
{
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_K8M890:
{
viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
break;
}
case UNICHROME_P4M900:
{
viafb_write_reg_mask(CR99, VIACR, 0x08,
BIT0 + BIT1 + BIT2 + BIT3);
break;
}
case UNICHROME_P4M890:
{
viafb_write_reg_mask(CR99, VIACR, 0x0F,
BIT0 + BIT1 + BIT2 + BIT3);
break;
}
default:
{
break;
}
}
}
/* If Enable DVI, turn off pad */
void viafb_dvi_enable(void)
{
u8 data;
switch (viaparinfo->chip_info->tmds_chip_info.output_interface) {
case INTERFACE_DVP0:
viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);
dvi_patch_skew_dvp0();
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
tmds_register_write(0x88, 0x3b);
else
/*clear CR91[5] to direct on display period
in the secondary diplay path */
via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
break;
case INTERFACE_DVP1:
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);
/*fix dvi cann't be enabled with MB VT5718C4 - Al Zhang */
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
tmds_register_write(0x88, 0x3b);
else
/*clear CR91[5] to direct on display period
in the secondary diplay path */
via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
/*fix DVI cannot enable on EPIA-M board */
if (viafb_platform_epia_dvi == 1) {
viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);
viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);
if (viafb_bus_width == 24) {
if (viafb_device_lcd_dualedge == 1)
data = 0x3F;
else
data = 0x37;
viafb_i2c_writebyte(viaparinfo->chip_info->
tmds_chip_info.i2c_port,
viaparinfo->chip_info->
tmds_chip_info.tmds_chip_slave_addr,
0x08, data);
}
}
break;
case INTERFACE_DFP_HIGH:
if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
via_write_reg_mask(VIACR, CR97, 0x03, 0x03);
via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
break;
case INTERFACE_DFP_LOW:
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
break;
dvi_patch_skew_dvp_low();
via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);
break;
case INTERFACE_TMDS:
/* Turn on Display period in the panel path. */
viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
/* Turn on TMDS power. */
viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);
break;
}
if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
/* Disable LCD Scaling */
viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
}
}
| linux-master | drivers/video/fbdev/via/dvi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/via-core.h>
#include "global.h"
void viafb_get_device_support_state(u32 *support_state)
{
*support_state = CRT_Device;
if (viaparinfo->chip_info->tmds_chip_info.tmds_chip_name == VT1632_TMDS)
*support_state |= DVI_Device;
if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name == VT1631_LVDS)
*support_state |= LCD_Device;
}
void viafb_get_device_connect_state(u32 *connect_state)
{
bool mobile = false;
*connect_state = CRT_Device;
if (viafb_dvi_sense())
*connect_state |= DVI_Device;
viafb_lcd_get_mobile_state(&mobile);
if (mobile)
*connect_state |= LCD_Device;
}
bool viafb_lcd_get_support_expand_state(u32 xres, u32 yres)
{
unsigned int support_state = 0;
switch (viafb_lcd_panel_id) {
case LCD_PANEL_ID0_640X480:
if ((xres < 640) && (yres < 480))
support_state = true;
break;
case LCD_PANEL_ID1_800X600:
if ((xres < 800) && (yres < 600))
support_state = true;
break;
case LCD_PANEL_ID2_1024X768:
if ((xres < 1024) && (yres < 768))
support_state = true;
break;
case LCD_PANEL_ID3_1280X768:
if ((xres < 1280) && (yres < 768))
support_state = true;
break;
case LCD_PANEL_ID4_1280X1024:
if ((xres < 1280) && (yres < 1024))
support_state = true;
break;
case LCD_PANEL_ID5_1400X1050:
if ((xres < 1400) && (yres < 1050))
support_state = true;
break;
case LCD_PANEL_ID6_1600X1200:
if ((xres < 1600) && (yres < 1200))
support_state = true;
break;
case LCD_PANEL_ID7_1366X768:
if ((xres < 1366) && (yres < 768))
support_state = true;
break;
case LCD_PANEL_ID8_1024X600:
if ((xres < 1024) && (yres < 600))
support_state = true;
break;
case LCD_PANEL_ID9_1280X800:
if ((xres < 1280) && (yres < 800))
support_state = true;
break;
case LCD_PANEL_IDA_800X480:
if ((xres < 800) && (yres < 480))
support_state = true;
break;
case LCD_PANEL_IDB_1360X768:
if ((xres < 1360) && (yres < 768))
support_state = true;
break;
case LCD_PANEL_IDC_480X640:
if ((xres < 480) && (yres < 640))
support_state = true;
break;
default:
support_state = false;
break;
}
return support_state;
}
/*====================================================================*/
/* Gamma Function Implementation*/
/*====================================================================*/
void viafb_set_gamma_table(int bpp, unsigned int *gamma_table)
{
int i, sr1a;
int active_device_amount = 0;
int device_status = viafb_DeviceStatus;
for (i = 0; i < sizeof(viafb_DeviceStatus) * 8; i++) {
if (device_status & 1)
active_device_amount++;
device_status >>= 1;
}
/* 8 bpp mode can't adjust gamma */
if (bpp == 8)
return ;
/* Enable Gamma */
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
break;
}
sr1a = (unsigned int)viafb_read_reg(VIASR, SR1A);
viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
/* Fill IGA1 Gamma Table */
outb(0, LUT_INDEX_WRITE);
for (i = 0; i < 256; i++) {
outb(gamma_table[i] >> 16, LUT_DATA);
outb(gamma_table[i] >> 8 & 0xFF, LUT_DATA);
outb(gamma_table[i] & 0xFF, LUT_DATA);
}
/* If adjust Gamma value in SAMM, fill IGA1,
IGA2 Gamma table simultaneous. */
/* Switch to IGA2 Gamma Table */
if ((active_device_amount > 1) &&
!((viaparinfo->chip_info->gfx_chip_name ==
UNICHROME_CLE266) &&
(viaparinfo->chip_info->gfx_chip_revision < 15))) {
viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1);
/* Fill IGA2 Gamma Table */
outb(0, LUT_INDEX_WRITE);
for (i = 0; i < 256; i++) {
outb(gamma_table[i] >> 16, LUT_DATA);
outb(gamma_table[i] >> 8 & 0xFF, LUT_DATA);
outb(gamma_table[i] & 0xFF, LUT_DATA);
}
}
viafb_write_reg(SR1A, VIASR, sr1a);
}
void viafb_get_gamma_table(unsigned int *gamma_table)
{
unsigned char color_r, color_g, color_b;
unsigned char sr1a = 0;
int i;
/* Enable Gamma */
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
break;
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
break;
}
sr1a = viafb_read_reg(VIASR, SR1A);
viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
/* Reading gamma table to get color value */
outb(0, LUT_INDEX_READ);
for (i = 0; i < 256; i++) {
color_r = inb(LUT_DATA);
color_g = inb(LUT_DATA);
color_b = inb(LUT_DATA);
gamma_table[i] =
((((u32) color_r) << 16) |
(((u16) color_g) << 8)) | color_b;
}
viafb_write_reg(SR1A, VIASR, sr1a);
}
void viafb_get_gamma_support_state(int bpp, unsigned int *support_state)
{
if (bpp == 8)
*support_state = None_Device;
else
*support_state = CRT_Device | DVI_Device | LCD_Device;
}
| linux-master | drivers/video/fbdev/via/via_utility.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
*/
#include <linux/via-core.h>
#include "global.h"
/*
* Figure out an appropriate bytes-per-pixel setting.
*/
static int viafb_set_bpp(void __iomem *engine, u8 bpp)
{
u32 gemode;
/* Preserve the reserved bits */
/* Lowest 2 bits to zero gives us no rotation */
gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc;
switch (bpp) {
case 8:
gemode |= VIA_GEM_8bpp;
break;
case 16:
gemode |= VIA_GEM_16bpp;
break;
case 32:
gemode |= VIA_GEM_32bpp;
break;
default:
printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp);
return -EINVAL;
}
writel(gemode, engine + VIA_REG_GEMODE);
return 0;
}
static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
u32 fg_color, u32 bg_color, u8 fill_rop)
{
u32 ge_cmd = 0, tmp, i;
int ret;
if (!op || op > 3) {
printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
return -EINVAL;
}
if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
if (src_x < dst_x) {
ge_cmd |= 0x00008000;
src_x += width - 1;
dst_x += width - 1;
}
if (src_y < dst_y) {
ge_cmd |= 0x00004000;
src_y += height - 1;
dst_y += height - 1;
}
}
if (op == VIA_BITBLT_FILL) {
switch (fill_rop) {
case 0x00: /* blackness */
case 0x5A: /* pattern inversion */
case 0xF0: /* pattern copy */
case 0xFF: /* whiteness */
break;
default:
printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
"%u\n", fill_rop);
return -EINVAL;
}
}
ret = viafb_set_bpp(engine, dst_bpp);
if (ret)
return ret;
if (op != VIA_BITBLT_FILL) {
if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
|| src_y & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
"x/y %d %d\n", src_x, src_y);
return -EINVAL;
}
tmp = src_x | (src_y << 16);
writel(tmp, engine + 0x08);
}
if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
"%d %d\n", dst_x, dst_y);
return -EINVAL;
}
tmp = dst_x | (dst_y << 16);
writel(tmp, engine + 0x0C);
if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
"%d %d\n", width, height);
return -EINVAL;
}
tmp = (width - 1) | ((height - 1) << 16);
writel(tmp, engine + 0x10);
if (op != VIA_BITBLT_COLOR)
writel(fg_color, engine + 0x18);
if (op == VIA_BITBLT_MONO)
writel(bg_color, engine + 0x1C);
if (op != VIA_BITBLT_FILL) {
tmp = src_mem ? 0 : src_addr;
if (dst_addr & 0xE0000007) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
"address %X\n", tmp);
return -EINVAL;
}
tmp >>= 3;
writel(tmp, engine + 0x30);
}
if (dst_addr & 0xE0000007) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
"address %X\n", dst_addr);
return -EINVAL;
}
tmp = dst_addr >> 3;
writel(tmp, engine + 0x34);
if (op == VIA_BITBLT_FILL)
tmp = 0;
else
tmp = src_pitch;
if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
tmp, dst_pitch);
return -EINVAL;
}
tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3));
writel(tmp, engine + 0x38);
if (op == VIA_BITBLT_FILL)
ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
else {
ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
if (src_mem)
ge_cmd |= 0x00000040;
if (op == VIA_BITBLT_MONO)
ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
else
ge_cmd |= 0x00000001;
}
writel(ge_cmd, engine);
if (op == VIA_BITBLT_FILL || !src_mem)
return 0;
tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
3) >> 2;
for (i = 0; i < tmp; i++)
writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
return 0;
}
static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
u32 fg_color, u32 bg_color, u8 fill_rop)
{
u32 ge_cmd = 0, tmp, i;
int ret;
if (!op || op > 3) {
printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
return -EINVAL;
}
if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
if (src_x < dst_x) {
ge_cmd |= 0x00008000;
src_x += width - 1;
dst_x += width - 1;
}
if (src_y < dst_y) {
ge_cmd |= 0x00004000;
src_y += height - 1;
dst_y += height - 1;
}
}
if (op == VIA_BITBLT_FILL) {
switch (fill_rop) {
case 0x00: /* blackness */
case 0x5A: /* pattern inversion */
case 0xF0: /* pattern copy */
case 0xFF: /* whiteness */
break;
default:
printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
"%u\n", fill_rop);
return -EINVAL;
}
}
ret = viafb_set_bpp(engine, dst_bpp);
if (ret)
return ret;
if (op == VIA_BITBLT_FILL)
tmp = 0;
else
tmp = src_pitch;
if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
tmp, dst_pitch);
return -EINVAL;
}
tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
writel(tmp, engine + 0x08);
if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
"%d %d\n", width, height);
return -EINVAL;
}
tmp = (width - 1) | ((height - 1) << 16);
writel(tmp, engine + 0x0C);
if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
"%d %d\n", dst_x, dst_y);
return -EINVAL;
}
tmp = dst_x | (dst_y << 16);
writel(tmp, engine + 0x10);
if (dst_addr & 0xE0000007) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
"address %X\n", dst_addr);
return -EINVAL;
}
tmp = dst_addr >> 3;
writel(tmp, engine + 0x14);
if (op != VIA_BITBLT_FILL) {
if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
|| src_y & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
"x/y %d %d\n", src_x, src_y);
return -EINVAL;
}
tmp = src_x | (src_y << 16);
writel(tmp, engine + 0x18);
tmp = src_mem ? 0 : src_addr;
if (dst_addr & 0xE0000007) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
"address %X\n", tmp);
return -EINVAL;
}
tmp >>= 3;
writel(tmp, engine + 0x1C);
}
if (op == VIA_BITBLT_FILL) {
writel(fg_color, engine + 0x58);
} else if (op == VIA_BITBLT_MONO) {
writel(fg_color, engine + 0x4C);
writel(bg_color, engine + 0x50);
}
if (op == VIA_BITBLT_FILL)
ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
else {
ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
if (src_mem)
ge_cmd |= 0x00000040;
if (op == VIA_BITBLT_MONO)
ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
else
ge_cmd |= 0x00000001;
}
writel(ge_cmd, engine);
if (op == VIA_BITBLT_FILL || !src_mem)
return 0;
tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
3) >> 2;
for (i = 0; i < tmp; i++)
writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
return 0;
}
int viafb_setup_engine(struct fb_info *info)
{
struct viafb_par *viapar = info->par;
void __iomem *engine;
u32 chip_name = viapar->shared->chip_info.gfx_chip_name;
engine = viapar->shared->vdev->engine_mmio;
if (!engine) {
printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
"hardware acceleration disabled\n");
return -ENOMEM;
}
switch (chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_CN750:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
viapar->shared->hw_bitblt = hw_bitblt_1;
break;
case UNICHROME_VX800:
case UNICHROME_VX855:
case UNICHROME_VX900:
viapar->shared->hw_bitblt = hw_bitblt_2;
break;
default:
viapar->shared->hw_bitblt = NULL;
}
viapar->fbmem_free -= CURSOR_SIZE;
viapar->shared->cursor_vram_addr = viapar->fbmem_free;
viapar->fbmem_used += CURSOR_SIZE;
viapar->fbmem_free -= VQ_SIZE;
viapar->shared->vq_vram_addr = viapar->fbmem_free;
viapar->fbmem_used += VQ_SIZE;
#if IS_ENABLED(CONFIG_VIDEO_VIA_CAMERA)
/*
* Set aside a chunk of framebuffer memory for the camera
* driver. Someday this driver probably needs a proper allocator
* for fbmem; for now, we just have to do this before the
* framebuffer initializes itself.
*
* As for the size: the engine can handle three frames,
* 16 bits deep, up to VGA resolution.
*/
viapar->shared->vdev->camera_fbmem_size = 3*VGA_HEIGHT*VGA_WIDTH*2;
viapar->fbmem_free -= viapar->shared->vdev->camera_fbmem_size;
viapar->fbmem_used += viapar->shared->vdev->camera_fbmem_size;
viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free;
#endif
viafb_reset_engine(viapar);
return 0;
}
void viafb_reset_engine(struct viafb_par *viapar)
{
void __iomem *engine = viapar->shared->vdev->engine_mmio;
int highest_reg, i;
u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
/* Initialize registers to reset the 2D engine */
switch (viapar->shared->chip_info.twod_engine) {
case VIA_2D_ENG_M1:
highest_reg = 0x5c;
break;
default:
highest_reg = 0x40;
break;
}
for (i = 0; i <= highest_reg; i += 4)
writel(0x0, engine + i);
/* Init AGP and VQ regs */
switch (chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
case UNICHROME_VX855:
case UNICHROME_VX900:
writel(0x00100000, engine + VIA_REG_CR_TRANSET);
writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
break;
default:
writel(0x00100000, engine + VIA_REG_TRANSET);
writel(0x00000000, engine + VIA_REG_TRANSPACE);
writel(0x00333004, engine + VIA_REG_TRANSPACE);
writel(0x60000000, engine + VIA_REG_TRANSPACE);
writel(0x61000000, engine + VIA_REG_TRANSPACE);
writel(0x62000000, engine + VIA_REG_TRANSPACE);
writel(0x63000000, engine + VIA_REG_TRANSPACE);
writel(0x64000000, engine + VIA_REG_TRANSPACE);
writel(0x7D000000, engine + VIA_REG_TRANSPACE);
writel(0xFE020000, engine + VIA_REG_TRANSET);
writel(0x00000000, engine + VIA_REG_TRANSPACE);
break;
}
/* Enable VQ */
vq_start_addr = viapar->shared->vq_vram_addr;
vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
((vq_end_addr & 0xFF000000) >> 16);
vq_len = 0x53000000 | (VQ_SIZE >> 3);
switch (chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
case UNICHROME_VX855:
case UNICHROME_VX900:
vq_start_low |= 0x20000000;
vq_end_low |= 0x20000000;
vq_high |= 0x20000000;
vq_len |= 0x20000000;
writel(0x00100000, engine + VIA_REG_CR_TRANSET);
writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
break;
default:
writel(0x00FE0000, engine + VIA_REG_TRANSET);
writel(0x080003FE, engine + VIA_REG_TRANSPACE);
writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
writel(0x0B000260, engine + VIA_REG_TRANSPACE);
writel(0x0C000274, engine + VIA_REG_TRANSPACE);
writel(0x0D000264, engine + VIA_REG_TRANSPACE);
writel(0x0E000000, engine + VIA_REG_TRANSPACE);
writel(0x0F000020, engine + VIA_REG_TRANSPACE);
writel(0x1000027E, engine + VIA_REG_TRANSPACE);
writel(0x110002FE, engine + VIA_REG_TRANSPACE);
writel(0x200F0060, engine + VIA_REG_TRANSPACE);
writel(0x00000006, engine + VIA_REG_TRANSPACE);
writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
writel(0x44000000, engine + VIA_REG_TRANSPACE);
writel(0x45080C04, engine + VIA_REG_TRANSPACE);
writel(0x46800408, engine + VIA_REG_TRANSPACE);
writel(vq_high, engine + VIA_REG_TRANSPACE);
writel(vq_start_low, engine + VIA_REG_TRANSPACE);
writel(vq_end_low, engine + VIA_REG_TRANSPACE);
writel(vq_len, engine + VIA_REG_TRANSPACE);
break;
}
/* Set Cursor Image Base Address */
writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
writel(0x0, engine + VIA_REG_CURSOR_POS);
writel(0x0, engine + VIA_REG_CURSOR_ORG);
writel(0x0, engine + VIA_REG_CURSOR_BG);
writel(0x0, engine + VIA_REG_CURSOR_FG);
return;
}
void viafb_show_hw_cursor(struct fb_info *info, int Status)
{
struct viafb_par *viapar = info->par;
u32 temp, iga_path = viapar->iga_path;
temp = readl(viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
switch (Status) {
case HW_Cursor_ON:
temp |= 0x1;
break;
case HW_Cursor_OFF:
temp &= 0xFFFFFFFE;
break;
}
switch (iga_path) {
case IGA2:
temp |= 0x80000000;
break;
case IGA1:
default:
temp &= 0x7FFFFFFF;
}
writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE);
}
void viafb_wait_engine_idle(struct fb_info *info)
{
struct viafb_par *viapar = info->par;
int loop = 0;
u32 mask;
void __iomem *engine = viapar->shared->vdev->engine_mmio;
switch (viapar->shared->chip_info.twod_engine) {
case VIA_2D_ENG_H5:
case VIA_2D_ENG_M1:
mask = VIA_CMD_RGTR_BUSY_M1 | VIA_2D_ENG_BUSY_M1 |
VIA_3D_ENG_BUSY_M1;
break;
default:
while (!(readl(engine + VIA_REG_STATUS) &
VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
loop++;
cpu_relax();
}
mask = VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY;
break;
}
while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) {
loop++;
cpu_relax();
}
if (loop >= MAXLOOP)
printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
}
| linux-master | drivers/video/fbdev/via/accel.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/mb862xx/mb862xxfb.c
*
* Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
*
* (C) 2008 Anatolij Gustschin <[email protected]>
* DENX Software Engineering
*/
#undef DEBUG
#include <linux/aperture.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/uaccess.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include "mb862xxfb.h"
#include "mb862xx_reg.h"
#define NR_PALETTE 256
#define MB862XX_MEM_SIZE 0x1000000
#define CORALP_MEM_SIZE 0x2000000
#define CARMINE_MEM_SIZE 0x8000000
#define DRV_NAME "mb862xxfb"
#if defined(CONFIG_SOCRATES)
static struct mb862xx_gc_mode socrates_gc_mode = {
/* Mode for Prime View PM070WL4 TFT LCD Panel */
{ "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
/* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
};
#endif
/* Helpers */
static inline int h_total(struct fb_var_screeninfo *var)
{
return var->xres + var->left_margin +
var->right_margin + var->hsync_len;
}
static inline int v_total(struct fb_var_screeninfo *var)
{
return var->yres + var->upper_margin +
var->lower_margin + var->vsync_len;
}
static inline int hsp(struct fb_var_screeninfo *var)
{
return var->xres + var->right_margin - 1;
}
static inline int vsp(struct fb_var_screeninfo *var)
{
return var->yres + var->lower_margin - 1;
}
static inline int d_pitch(struct fb_var_screeninfo *var)
{
return var->xres * var->bits_per_pixel / 8;
}
static inline unsigned int chan_to_field(unsigned int chan,
struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int mb862xxfb_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct mb862xxfb_par *par = info->par;
unsigned int val;
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
if (regno < 16) {
val = chan_to_field(red, &info->var.red);
val |= chan_to_field(green, &info->var.green);
val |= chan_to_field(blue, &info->var.blue);
par->pseudo_palette[regno] = val;
}
break;
case FB_VISUAL_PSEUDOCOLOR:
if (regno < 256) {
val = (red >> 8) << 16;
val |= (green >> 8) << 8;
val |= blue >> 8;
outreg(disp, GC_L0PAL0 + (regno * 4), val);
}
break;
default:
return 1; /* unsupported type */
}
return 0;
}
static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *fbi)
{
unsigned long tmp;
fb_dbg(fbi, "%s\n", __func__);
/* check if these values fit into the registers */
if (var->hsync_len > 255 || var->vsync_len > 255)
return -EINVAL;
if ((var->xres + var->right_margin) >= 4096)
return -EINVAL;
if ((var->yres + var->lower_margin) > 4096)
return -EINVAL;
if (h_total(var) > 4096 || v_total(var) > 4096)
return -EINVAL;
if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
return -EINVAL;
if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel <= 32)
var->bits_per_pixel = 32;
/*
* can cope with 8,16 or 24/32bpp if resulting
* pitch is divisible by 64 without remainder
*/
if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
int r;
var->bits_per_pixel = 0;
do {
var->bits_per_pixel += 8;
r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
} while (r && var->bits_per_pixel <= 32);
if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
return -EINVAL;
}
/* line length is going to be 128 bit aligned */
tmp = (var->xres * var->bits_per_pixel) / 8;
if ((tmp & 15) != 0)
return -EINVAL;
/* set r/g/b positions and validate bpp */
switch (var->bits_per_pixel) {
case 8:
var->red.length = var->bits_per_pixel;
var->green.length = var->bits_per_pixel;
var->blue.length = var->bits_per_pixel;
var->red.offset = 0;
var->green.offset = 0;
var->blue.offset = 0;
var->transp.length = 0;
break;
case 16:
var->red.length = 5;
var->green.length = 5;
var->blue.length = 5;
var->red.offset = 10;
var->green.offset = 5;
var->blue.offset = 0;
var->transp.length = 0;
break;
case 24:
case 32:
var->transp.length = 8;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.offset = 24;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
break;
default:
return -EINVAL;
}
return 0;
}
static struct fb_ops mb862xxfb_ops;
/*
* set display parameters
*/
static int mb862xxfb_set_par(struct fb_info *fbi)
{
struct mb862xxfb_par *par = fbi->par;
unsigned long reg, sc;
dev_dbg(par->dev, "%s\n", __func__);
if (par->type == BT_CORALP)
mb862xxfb_init_accel(fbi, &mb862xxfb_ops, fbi->var.xres);
if (par->pre_init)
return 0;
/* disp off */
reg = inreg(disp, GC_DCM1);
reg &= ~GC_DCM01_DEN;
outreg(disp, GC_DCM1, reg);
/* set display reference clock div. */
sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
reg = inreg(disp, GC_DCM1);
reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
reg |= sc << 8;
outreg(disp, GC_DCM1, reg);
dev_dbg(par->dev, "SC 0x%lx\n", sc);
/* disp dimension, format */
reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
(fbi->var.yres - 1));
if (fbi->var.bits_per_pixel == 16)
reg |= GC_L0M_L0C_16;
outreg(disp, GC_L0M, reg);
if (fbi->var.bits_per_pixel == 32) {
reg = inreg(disp, GC_L0EM);
outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
}
outreg(disp, GC_WY_WX, 0);
reg = pack(fbi->var.yres - 1, fbi->var.xres);
outreg(disp, GC_WH_WW, reg);
outreg(disp, GC_L0OA0, 0);
outreg(disp, GC_L0DA0, 0);
outreg(disp, GC_L0DY_L0DX, 0);
outreg(disp, GC_L0WY_L0WX, 0);
outreg(disp, GC_L0WH_L0WW, reg);
/* both HW-cursors off */
reg = inreg(disp, GC_CPM_CUTC);
reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
outreg(disp, GC_CPM_CUTC, reg);
/* timings */
reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
outreg(disp, GC_HDB_HDP, reg);
reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
outreg(disp, GC_VDP_VSP, reg);
reg = ((fbi->var.vsync_len - 1) << 24) |
pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
outreg(disp, GC_VSW_HSW_HSP, reg);
outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
/* display on */
reg = inreg(disp, GC_DCM1);
reg |= GC_DCM01_DEN | GC_DCM01_L0E;
reg &= ~GC_DCM01_ESY;
outreg(disp, GC_DCM1, reg);
return 0;
}
static int mb862xxfb_pan(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct mb862xxfb_par *par = info->par;
unsigned long reg;
reg = pack(var->yoffset, var->xoffset);
outreg(disp, GC_L0WY_L0WX, reg);
reg = pack(info->var.yres_virtual, info->var.xres_virtual);
outreg(disp, GC_L0WH_L0WW, reg);
return 0;
}
static int mb862xxfb_blank(int mode, struct fb_info *fbi)
{
struct mb862xxfb_par *par = fbi->par;
unsigned long reg;
fb_dbg(fbi, "blank mode=%d\n", mode);
switch (mode) {
case FB_BLANK_POWERDOWN:
reg = inreg(disp, GC_DCM1);
reg &= ~GC_DCM01_DEN;
outreg(disp, GC_DCM1, reg);
break;
case FB_BLANK_UNBLANK:
reg = inreg(disp, GC_DCM1);
reg |= GC_DCM01_DEN;
outreg(disp, GC_DCM1, reg);
break;
case FB_BLANK_NORMAL:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
default:
return 1;
}
return 0;
}
static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
unsigned long arg)
{
struct mb862xxfb_par *par = fbi->par;
struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
void __user *argp = (void __user *)arg;
int *enable;
u32 l1em = 0;
switch (cmd) {
case MB862XX_L1_GET_CFG:
if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
return -EFAULT;
break;
case MB862XX_L1_SET_CFG:
if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
return -EFAULT;
if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
return -EINVAL;
if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
/* downscaling */
outreg(cap, GC_CAP_CSC,
pack((l1_cfg->sh << 11) / l1_cfg->dh,
(l1_cfg->sw << 11) / l1_cfg->dw));
l1em = inreg(disp, GC_L1EM);
l1em &= ~GC_L1EM_DM;
} else if ((l1_cfg->sw <= l1_cfg->dw) &&
(l1_cfg->sh <= l1_cfg->dh)) {
/* upscaling */
outreg(cap, GC_CAP_CSC,
pack((l1_cfg->sh << 11) / l1_cfg->dh,
(l1_cfg->sw << 11) / l1_cfg->dw));
outreg(cap, GC_CAP_CMSS,
pack(l1_cfg->sw >> 1, l1_cfg->sh));
outreg(cap, GC_CAP_CMDS,
pack(l1_cfg->dw >> 1, l1_cfg->dh));
l1em = inreg(disp, GC_L1EM);
l1em |= GC_L1EM_DM;
}
if (l1_cfg->mirror) {
outreg(cap, GC_CAP_CBM,
inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
l1em |= l1_cfg->dw * 2 - 8;
} else {
outreg(cap, GC_CAP_CBM,
inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
l1em &= 0xffff0000;
}
outreg(disp, GC_L1EM, l1em);
break;
case MB862XX_L1_ENABLE:
enable = (int *)arg;
if (*enable) {
outreg(disp, GC_L1DA, par->cap_buf);
outreg(cap, GC_CAP_IMG_START,
pack(l1_cfg->sy >> 1, l1_cfg->sx));
outreg(cap, GC_CAP_IMG_END,
pack(l1_cfg->sh, l1_cfg->sw));
outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
(par->l1_stride << 16));
outreg(disp, GC_L1WY_L1WX,
pack(l1_cfg->dy, l1_cfg->dx));
outreg(disp, GC_L1WH_L1WW,
pack(l1_cfg->dh - 1, l1_cfg->dw));
outreg(disp, GC_DLS, 1);
outreg(cap, GC_CAP_VCM,
GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
GC_DCM1_DEN | GC_DCM1_L1E);
} else {
outreg(cap, GC_CAP_VCM,
inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
outreg(disp, GC_DCM1,
inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
}
break;
case MB862XX_L1_CAP_CTL:
enable = (int *)arg;
if (*enable) {
outreg(cap, GC_CAP_VCM,
inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
} else {
outreg(cap, GC_CAP_VCM,
inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
}
break;
default:
return -EINVAL;
}
return 0;
}
/* framebuffer ops */
static struct fb_ops mb862xxfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = mb862xxfb_check_var,
.fb_set_par = mb862xxfb_set_par,
.fb_setcolreg = mb862xxfb_setcolreg,
.fb_blank = mb862xxfb_blank,
.fb_pan_display = mb862xxfb_pan,
.fb_ioctl = mb862xxfb_ioctl,
};
/* initialize fb_info data */
static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
{
struct mb862xxfb_par *par = fbi->par;
struct mb862xx_gc_mode *mode = par->gc_mode;
unsigned long reg;
int stride;
fbi->fbops = &mb862xxfb_ops;
fbi->pseudo_palette = par->pseudo_palette;
fbi->screen_base = par->fb_base;
fbi->screen_size = par->mapped_vram;
strcpy(fbi->fix.id, DRV_NAME);
fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
fbi->fix.mmio_len = par->mmio_len;
fbi->fix.accel = FB_ACCEL_NONE;
fbi->fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fix.type_aux = 0;
fbi->fix.xpanstep = 1;
fbi->fix.ypanstep = 1;
fbi->fix.ywrapstep = 0;
reg = inreg(disp, GC_DCM1);
if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
/* get the disp mode from active display cfg */
unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
unsigned long hsp, vsp, ht, vt;
dev_dbg(par->dev, "using bootloader's disp. mode\n");
fbi->var.pixclock = (sc * 1000000) / par->refclk;
fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
reg = inreg(disp, GC_VDP_VSP);
fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
vsp = (reg & 0x0fff) + 1;
fbi->var.xres_virtual = fbi->var.xres;
fbi->var.yres_virtual = fbi->var.yres;
reg = inreg(disp, GC_L0EM);
if (reg & GC_L0EM_L0EC_24) {
fbi->var.bits_per_pixel = 32;
} else {
reg = inreg(disp, GC_L0M);
if (reg & GC_L0M_L0C_16)
fbi->var.bits_per_pixel = 16;
else
fbi->var.bits_per_pixel = 8;
}
reg = inreg(disp, GC_VSW_HSW_HSP);
fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
hsp = (reg & 0xffff) + 1;
ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
fbi->var.right_margin = hsp - fbi->var.xres;
fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
fbi->var.lower_margin = vsp - fbi->var.yres;
fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
} else if (mode) {
dev_dbg(par->dev, "using supplied mode\n");
fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
} else {
int ret;
ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
NULL, 0, NULL, 16);
if (ret == 0 || ret == 4) {
dev_err(par->dev,
"failed to get initial mode\n");
return -EINVAL;
}
}
fbi->var.xoffset = 0;
fbi->var.yoffset = 0;
fbi->var.grayscale = 0;
fbi->var.nonstd = 0;
fbi->var.height = -1;
fbi->var.width = -1;
fbi->var.accel_flags = 0;
fbi->var.vmode = FB_VMODE_NONINTERLACED;
fbi->var.activate = FB_ACTIVATE_NOW;
fbi->flags =
#ifdef __BIG_ENDIAN
FBINFO_FOREIGN_ENDIAN |
#endif
FBINFO_HWACCEL_XPAN |
FBINFO_HWACCEL_YPAN;
/* check and possibly fix bpp */
if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
dev_err(par->dev, "check_var() failed on initial setup?\n");
fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
fbi->fix.line_length = (fbi->var.xres_virtual *
fbi->var.bits_per_pixel) / 8;
fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
/*
* reserve space for capture buffers and two cursors
* at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
*/
par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
par->cap_len = 0x1bd800;
par->l1_cfg.sx = 0;
par->l1_cfg.sy = 0;
par->l1_cfg.sw = 720;
par->l1_cfg.sh = 576;
par->l1_cfg.dx = 0;
par->l1_cfg.dy = 0;
par->l1_cfg.dw = 720;
par->l1_cfg.dh = 576;
stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
(par->l1_stride << 16));
outreg(cap, GC_CAP_CBOA, par->cap_buf);
outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
return 0;
}
/*
* show some display controller and cursor registers
*/
static ssize_t dispregs_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct mb862xxfb_par *par = fbi->par;
char *ptr = buf;
unsigned int reg;
for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
ptr += sprintf(ptr, "%08x = %08x\n",
reg, inreg(disp, reg));
for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
ptr += sprintf(ptr, "%08x = %08x\n",
reg, inreg(disp, reg));
for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
ptr += sprintf(ptr, "%08x = %08x\n",
reg, inreg(disp, reg));
for (reg = 0x400; reg <= 0x410; reg += 4)
ptr += sprintf(ptr, "geo %08x = %08x\n",
reg, inreg(geo, reg));
for (reg = 0x400; reg <= 0x410; reg += 4)
ptr += sprintf(ptr, "draw %08x = %08x\n",
reg, inreg(draw, reg));
for (reg = 0x440; reg <= 0x450; reg += 4)
ptr += sprintf(ptr, "draw %08x = %08x\n",
reg, inreg(draw, reg));
return ptr - buf;
}
static DEVICE_ATTR_RO(dispregs);
static irqreturn_t mb862xx_intr(int irq, void *dev_id)
{
struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
unsigned long reg_ist, mask;
if (!par)
return IRQ_NONE;
if (par->type == BT_CARMINE) {
/* Get Interrupt Status */
reg_ist = inreg(ctrl, GC_CTRL_STATUS);
mask = inreg(ctrl, GC_CTRL_INT_MASK);
if (reg_ist == 0)
return IRQ_HANDLED;
reg_ist &= mask;
if (reg_ist == 0)
return IRQ_HANDLED;
/* Clear interrupt status */
outreg(ctrl, 0x0, reg_ist);
} else {
/* Get status */
reg_ist = inreg(host, GC_IST);
mask = inreg(host, GC_IMASK);
reg_ist &= mask;
if (reg_ist == 0)
return IRQ_HANDLED;
/* Clear status */
outreg(host, GC_IST, ~reg_ist);
}
return IRQ_HANDLED;
}
#if defined(CONFIG_FB_MB862XX_LIME)
/*
* GDC (Lime, Coral(B/Q), Mint, ...) on host bus
*/
static int mb862xx_gdc_init(struct mb862xxfb_par *par)
{
unsigned long ccf, mmr;
unsigned long ver, rev;
if (!par)
return -ENODEV;
#if defined(CONFIG_FB_PRE_INIT_FB)
par->pre_init = 1;
#endif
par->host = par->mmio_base;
par->i2c = par->mmio_base + MB862XX_I2C_BASE;
par->disp = par->mmio_base + MB862XX_DISP_BASE;
par->cap = par->mmio_base + MB862XX_CAP_BASE;
par->draw = par->mmio_base + MB862XX_DRAW_BASE;
par->geo = par->mmio_base + MB862XX_GEO_BASE;
par->pio = par->mmio_base + MB862XX_PIO_BASE;
par->refclk = GC_DISP_REFCLK_400;
ver = inreg(host, GC_CID);
rev = inreg(pio, GC_REVISION);
if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
(int)rev & 0xff);
par->type = BT_LIME;
ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
} else {
dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
return -ENODEV;
}
if (!par->pre_init) {
outreg(host, GC_CCF, ccf);
udelay(200);
outreg(host, GC_MMR, mmr);
udelay(10);
}
/* interrupt status */
outreg(host, GC_IST, 0);
outreg(host, GC_IMASK, GC_INT_EN);
return 0;
}
static int of_platform_mb862xx_probe(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
struct device *dev = &ofdev->dev;
struct mb862xxfb_par *par;
struct fb_info *info;
struct resource res;
resource_size_t res_size;
unsigned long ret = -ENODEV;
if (of_address_to_resource(np, 0, &res)) {
dev_err(dev, "Invalid address\n");
return -ENXIO;
}
info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
if (!info)
return -ENOMEM;
par = info->par;
par->info = info;
par->dev = dev;
par->irq = irq_of_parse_and_map(np, 0);
if (!par->irq) {
dev_err(dev, "failed to map irq\n");
ret = -ENODEV;
goto fbrel;
}
res_size = resource_size(&res);
par->res = request_mem_region(res.start, res_size, DRV_NAME);
if (par->res == NULL) {
dev_err(dev, "Cannot claim framebuffer/mmio\n");
ret = -ENXIO;
goto irqdisp;
}
#if defined(CONFIG_SOCRATES)
par->gc_mode = &socrates_gc_mode;
#endif
par->fb_base_phys = res.start;
par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
par->mmio_len = MB862XX_MMIO_SIZE;
if (par->gc_mode)
par->mapped_vram = par->gc_mode->max_vram;
else
par->mapped_vram = MB862XX_MEM_SIZE;
par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
if (par->fb_base == NULL) {
dev_err(dev, "Cannot map framebuffer\n");
goto rel_reg;
}
par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
if (par->mmio_base == NULL) {
dev_err(dev, "Cannot map registers\n");
goto fb_unmap;
}
dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
(u64)par->fb_base_phys, (ulong)par->mapped_vram);
dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
(u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
if (mb862xx_gdc_init(par))
goto io_unmap;
if (request_irq(par->irq, mb862xx_intr, 0,
DRV_NAME, (void *)par)) {
dev_err(dev, "Cannot request irq\n");
goto io_unmap;
}
mb862xxfb_init_fbinfo(info);
if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
dev_err(dev, "Could not allocate cmap for fb_info.\n");
goto free_irq;
}
if ((info->fbops->fb_set_par)(info))
dev_err(dev, "set_var() failed on initial setup?\n");
if (register_framebuffer(info)) {
dev_err(dev, "failed to register framebuffer\n");
goto rel_cmap;
}
dev_set_drvdata(dev, info);
if (device_create_file(dev, &dev_attr_dispregs))
dev_err(dev, "Can't create sysfs regdump file\n");
return 0;
rel_cmap:
fb_dealloc_cmap(&info->cmap);
free_irq:
outreg(host, GC_IMASK, 0);
free_irq(par->irq, (void *)par);
io_unmap:
iounmap(par->mmio_base);
fb_unmap:
iounmap(par->fb_base);
rel_reg:
release_mem_region(res.start, res_size);
irqdisp:
irq_dispose_mapping(par->irq);
fbrel:
framebuffer_release(info);
return ret;
}
static void of_platform_mb862xx_remove(struct platform_device *ofdev)
{
struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
struct mb862xxfb_par *par = fbi->par;
resource_size_t res_size = resource_size(par->res);
unsigned long reg;
fb_dbg(fbi, "%s release\n", fbi->fix.id);
/* display off */
reg = inreg(disp, GC_DCM1);
reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
outreg(disp, GC_DCM1, reg);
/* disable interrupts */
outreg(host, GC_IMASK, 0);
free_irq(par->irq, (void *)par);
irq_dispose_mapping(par->irq);
device_remove_file(&ofdev->dev, &dev_attr_dispregs);
unregister_framebuffer(fbi);
fb_dealloc_cmap(&fbi->cmap);
iounmap(par->mmio_base);
iounmap(par->fb_base);
release_mem_region(par->res->start, res_size);
framebuffer_release(fbi);
}
/*
* common types
*/
static struct of_device_id of_platform_mb862xx_tbl[] = {
{ .compatible = "fujitsu,MB86276", },
{ .compatible = "fujitsu,lime", },
{ .compatible = "fujitsu,MB86277", },
{ .compatible = "fujitsu,mint", },
{ .compatible = "fujitsu,MB86293", },
{ .compatible = "fujitsu,MB86294", },
{ .compatible = "fujitsu,coral", },
{ /* end */ }
};
MODULE_DEVICE_TABLE(of, of_platform_mb862xx_tbl);
static struct platform_driver of_platform_mb862xxfb_driver = {
.driver = {
.name = DRV_NAME,
.of_match_table = of_platform_mb862xx_tbl,
},
.probe = of_platform_mb862xx_probe,
.remove_new = of_platform_mb862xx_remove,
};
#endif
#if defined(CONFIG_FB_MB862XX_PCI_GDC)
static int coralp_init(struct mb862xxfb_par *par)
{
int cn, ver;
par->host = par->mmio_base;
par->i2c = par->mmio_base + MB862XX_I2C_BASE;
par->disp = par->mmio_base + MB862XX_DISP_BASE;
par->cap = par->mmio_base + MB862XX_CAP_BASE;
par->draw = par->mmio_base + MB862XX_DRAW_BASE;
par->geo = par->mmio_base + MB862XX_GEO_BASE;
par->pio = par->mmio_base + MB862XX_PIO_BASE;
par->refclk = GC_DISP_REFCLK_400;
if (par->mapped_vram >= 0x2000000) {
/* relocate gdc registers space */
writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
udelay(1); /* wait at least 20 bus cycles */
}
ver = inreg(host, GC_CID);
cn = (ver & GC_CID_CNAME_MSK) >> 8;
ver = ver & GC_CID_VERSION_MSK;
if (cn == 3) {
unsigned long reg;
dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
(ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
par->pdev->revision);
reg = inreg(disp, GC_DCM1);
if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
par->pre_init = 1;
if (!par->pre_init) {
outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
udelay(200);
outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
udelay(10);
}
/* Clear interrupt status */
outreg(host, GC_IST, 0);
} else {
return -ENODEV;
}
mb862xx_i2c_init(par);
return 0;
}
static int init_dram_ctrl(struct mb862xxfb_par *par)
{
unsigned long i = 0;
/*
* Set io mode first! Spec. says IC may be destroyed
* if not set to SSTL2/LVCMOS before init.
*/
outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
/* DRAM init */
outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
GC_EVB_DCTL_REFRESH_SETTIME2);
outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
/* DLL reset done? */
while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
udelay(GC_DCTL_INIT_WAIT_INTERVAL);
if (i++ > GC_DCTL_INIT_WAIT_CNT) {
dev_err(par->dev, "VRAM init failed.\n");
return -EINVAL;
}
}
outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
return 0;
}
static int carmine_init(struct mb862xxfb_par *par)
{
unsigned long reg;
par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
par->i2c = par->mmio_base + MB86297_I2C_BASE;
par->disp = par->mmio_base + MB86297_DISP0_BASE;
par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
par->cap = par->mmio_base + MB86297_CAP0_BASE;
par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
par->draw = par->mmio_base + MB86297_DRAW_BASE;
par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
par->refclk = GC_DISP_REFCLK_533;
/* warm up */
reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
/* check for engine module revision */
if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
par->pdev->revision);
else
goto err_init;
reg &= ~GC_CTRL_CLK_EN_2D3D;
outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
/* set up vram */
if (init_dram_ctrl(par) < 0)
goto err_init;
outreg(ctrl, GC_CTRL_INT_MASK, 0);
return 0;
err_init:
outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
return -EINVAL;
}
static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
{
switch (par->type) {
case BT_CORALP:
return coralp_init(par);
case BT_CARMINE:
return carmine_init(par);
default:
return -ENODEV;
}
}
#define CHIP_ID(id) \
{ PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
static const struct pci_device_id mb862xx_pci_tbl[] = {
/* MB86295/MB86296 */
CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
/* MB86297 */
CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
{ 0, }
};
MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
static int mb862xx_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct mb862xxfb_par *par;
struct fb_info *info;
struct device *dev = &pdev->dev;
int ret;
ret = aperture_remove_conflicting_pci_devices(pdev, "mb862xxfb");
if (ret)
return ret;
ret = pci_enable_device(pdev);
if (ret < 0) {
dev_err(dev, "Cannot enable PCI device\n");
goto out;
}
info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
if (!info) {
ret = -ENOMEM;
goto dis_dev;
}
par = info->par;
par->info = info;
par->dev = dev;
par->pdev = pdev;
par->irq = pdev->irq;
ret = pci_request_regions(pdev, DRV_NAME);
if (ret < 0) {
dev_err(dev, "Cannot reserve region(s) for PCI device\n");
goto rel_fb;
}
switch (pdev->device) {
case PCI_DEVICE_ID_FUJITSU_CORALP:
case PCI_DEVICE_ID_FUJITSU_CORALPA:
par->fb_base_phys = pci_resource_start(par->pdev, 0);
par->mapped_vram = CORALP_MEM_SIZE;
if (par->mapped_vram >= 0x2000000) {
par->mmio_base_phys = par->fb_base_phys +
MB862XX_MMIO_HIGH_BASE;
} else {
par->mmio_base_phys = par->fb_base_phys +
MB862XX_MMIO_BASE;
}
par->mmio_len = MB862XX_MMIO_SIZE;
par->type = BT_CORALP;
break;
case PCI_DEVICE_ID_FUJITSU_CARMINE:
par->fb_base_phys = pci_resource_start(par->pdev, 2);
par->mmio_base_phys = pci_resource_start(par->pdev, 3);
par->mmio_len = pci_resource_len(par->pdev, 3);
par->mapped_vram = CARMINE_MEM_SIZE;
par->type = BT_CARMINE;
break;
default:
/* should never occur */
ret = -EIO;
goto rel_reg;
}
par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
if (par->fb_base == NULL) {
dev_err(dev, "Cannot map framebuffer\n");
ret = -EIO;
goto rel_reg;
}
par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
if (par->mmio_base == NULL) {
dev_err(dev, "Cannot map registers\n");
ret = -EIO;
goto fb_unmap;
}
dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
(unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
(unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
ret = mb862xx_pci_gdc_init(par);
if (ret)
goto io_unmap;
ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
DRV_NAME, (void *)par);
if (ret) {
dev_err(dev, "Cannot request irq\n");
goto io_unmap;
}
mb862xxfb_init_fbinfo(info);
if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
dev_err(dev, "Could not allocate cmap for fb_info.\n");
ret = -ENOMEM;
goto free_irq;
}
if ((info->fbops->fb_set_par)(info))
dev_err(dev, "set_var() failed on initial setup?\n");
ret = register_framebuffer(info);
if (ret < 0) {
dev_err(dev, "failed to register framebuffer\n");
goto rel_cmap;
}
pci_set_drvdata(pdev, info);
if (device_create_file(dev, &dev_attr_dispregs))
dev_err(dev, "Can't create sysfs regdump file\n");
if (par->type == BT_CARMINE)
outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
else
outreg(host, GC_IMASK, GC_INT_EN);
return 0;
rel_cmap:
fb_dealloc_cmap(&info->cmap);
free_irq:
free_irq(par->irq, (void *)par);
io_unmap:
iounmap(par->mmio_base);
fb_unmap:
iounmap(par->fb_base);
rel_reg:
pci_release_regions(pdev);
rel_fb:
framebuffer_release(info);
dis_dev:
pci_disable_device(pdev);
out:
return ret;
}
static void mb862xx_pci_remove(struct pci_dev *pdev)
{
struct fb_info *fbi = pci_get_drvdata(pdev);
struct mb862xxfb_par *par = fbi->par;
unsigned long reg;
fb_dbg(fbi, "%s release\n", fbi->fix.id);
/* display off */
reg = inreg(disp, GC_DCM1);
reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
outreg(disp, GC_DCM1, reg);
if (par->type == BT_CARMINE) {
outreg(ctrl, GC_CTRL_INT_MASK, 0);
outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
} else {
outreg(host, GC_IMASK, 0);
}
mb862xx_i2c_exit(par);
device_remove_file(&pdev->dev, &dev_attr_dispregs);
unregister_framebuffer(fbi);
fb_dealloc_cmap(&fbi->cmap);
free_irq(par->irq, (void *)par);
iounmap(par->mmio_base);
iounmap(par->fb_base);
pci_release_regions(pdev);
framebuffer_release(fbi);
pci_disable_device(pdev);
}
static struct pci_driver mb862xxfb_pci_driver = {
.name = DRV_NAME,
.id_table = mb862xx_pci_tbl,
.probe = mb862xx_pci_probe,
.remove = mb862xx_pci_remove,
};
#endif
static int mb862xxfb_init(void)
{
int ret = -ENODEV;
if (fb_modesetting_disabled(DRV_NAME))
return -ENODEV;
#if defined(CONFIG_FB_MB862XX_LIME)
ret = platform_driver_register(&of_platform_mb862xxfb_driver);
#endif
#if defined(CONFIG_FB_MB862XX_PCI_GDC)
ret = pci_register_driver(&mb862xxfb_pci_driver);
#endif
return ret;
}
static void __exit mb862xxfb_exit(void)
{
#if defined(CONFIG_FB_MB862XX_LIME)
platform_driver_unregister(&of_platform_mb862xxfb_driver);
#endif
#if defined(CONFIG_FB_MB862XX_PCI_GDC)
pci_unregister_driver(&mb862xxfb_pci_driver);
#endif
}
module_init(mb862xxfb_init);
module_exit(mb862xxfb_exit);
MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
MODULE_AUTHOR("Anatolij Gustschin <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/mb862xx/mb862xxfbdrv.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Coral-P(A)/Lime I2C adapter driver
*
* (C) 2011 DENX Software Engineering, Anatolij Gustschin <[email protected]>
*/
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/export.h>
#include "mb862xxfb.h"
#include "mb862xx_reg.h"
static int mb862xx_i2c_wait_event(struct i2c_adapter *adap)
{
struct mb862xxfb_par *par = adap->algo_data;
u32 reg;
do {
udelay(10);
reg = inreg(i2c, GC_I2C_BCR);
if (reg & (I2C_INT | I2C_BER))
break;
} while (1);
return (reg & I2C_BER) ? 0 : 1;
}
static int mb862xx_i2c_do_address(struct i2c_adapter *adap, int addr)
{
struct mb862xxfb_par *par = adap->algo_data;
outreg(i2c, GC_I2C_DAR, addr);
outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE);
outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START);
if (!mb862xx_i2c_wait_event(adap))
return -EIO;
par->i2c_rs = !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
return par->i2c_rs;
}
static int mb862xx_i2c_write_byte(struct i2c_adapter *adap, u8 byte)
{
struct mb862xxfb_par *par = adap->algo_data;
outreg(i2c, GC_I2C_DAR, byte);
outreg(i2c, GC_I2C_BCR, I2C_START);
if (!mb862xx_i2c_wait_event(adap))
return -EIO;
return !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
}
static int mb862xx_i2c_read_byte(struct i2c_adapter *adap, u8 *byte, int last)
{
struct mb862xxfb_par *par = adap->algo_data;
outreg(i2c, GC_I2C_BCR, I2C_START | (last ? 0 : I2C_ACK));
if (!mb862xx_i2c_wait_event(adap))
return 0;
*byte = inreg(i2c, GC_I2C_DAR);
return 1;
}
static void mb862xx_i2c_stop(struct i2c_adapter *adap)
{
struct mb862xxfb_par *par = adap->algo_data;
outreg(i2c, GC_I2C_BCR, I2C_STOP);
outreg(i2c, GC_I2C_CCR, I2C_DISABLE);
par->i2c_rs = 0;
}
static int mb862xx_i2c_read(struct i2c_adapter *adap, struct i2c_msg *m)
{
int i, ret = 0;
int last = m->len - 1;
for (i = 0; i < m->len; i++) {
if (!mb862xx_i2c_read_byte(adap, &m->buf[i], i == last)) {
ret = -EIO;
break;
}
}
return ret;
}
static int mb862xx_i2c_write(struct i2c_adapter *adap, struct i2c_msg *m)
{
int i, ret = 0;
for (i = 0; i < m->len; i++) {
if (!mb862xx_i2c_write_byte(adap, m->buf[i])) {
ret = -EIO;
break;
}
}
return ret;
}
static int mb862xx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
int num)
{
struct mb862xxfb_par *par = adap->algo_data;
struct i2c_msg *m;
int addr;
int i = 0, err = 0;
dev_dbg(par->dev, "%s: %d msgs\n", __func__, num);
for (i = 0; i < num; i++) {
m = &msgs[i];
if (!m->len) {
dev_dbg(par->dev, "%s: null msgs\n", __func__);
continue;
}
addr = m->addr;
if (m->flags & I2C_M_RD)
addr |= 1;
err = mb862xx_i2c_do_address(adap, addr);
if (err < 0)
break;
if (m->flags & I2C_M_RD)
err = mb862xx_i2c_read(adap, m);
else
err = mb862xx_i2c_write(adap, m);
}
if (i)
mb862xx_i2c_stop(adap);
return (err < 0) ? err : i;
}
static u32 mb862xx_func(struct i2c_adapter *adap)
{
return I2C_FUNC_SMBUS_BYTE_DATA;
}
static const struct i2c_algorithm mb862xx_algo = {
.master_xfer = mb862xx_xfer,
.functionality = mb862xx_func,
};
static struct i2c_adapter mb862xx_i2c_adapter = {
.name = "MB862xx I2C adapter",
.algo = &mb862xx_algo,
.owner = THIS_MODULE,
};
int mb862xx_i2c_init(struct mb862xxfb_par *par)
{
mb862xx_i2c_adapter.algo_data = par;
par->adap = &mb862xx_i2c_adapter;
return i2c_add_adapter(par->adap);
}
void mb862xx_i2c_exit(struct mb862xxfb_par *par)
{
if (par->adap) {
i2c_del_adapter(par->adap);
par->adap = NULL;
}
}
| linux-master | drivers/video/fbdev/mb862xx/mb862xx-i2c.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/mb862xx/mb862xxfb_accel.c
*
* Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver acceleration support
*
* (C) 2007 Alexander Shishkin <[email protected]>
* (C) 2009 Valentin Sitdikov <[email protected]>
* (C) 2009 Siemens AG
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include "mb862xxfb.h"
#include "mb862xx_reg.h"
#include "mb862xxfb_accel.h"
static void mb862xxfb_write_fifo(u32 count, u32 *data, struct fb_info *info)
{
struct mb862xxfb_par *par = info->par;
static u32 free;
u32 total = 0;
while (total < count) {
if (free) {
outreg(geo, GDC_GEO_REG_INPUT_FIFO, data[total]);
total++;
free--;
} else {
free = (u32) inreg(draw, GDC_REG_FIFO_COUNT);
}
}
}
static void mb86290fb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
__u32 cmd[6];
cmd[0] = (GDC_TYPE_SETREGISTER << 24) | (1 << 16) | GDC_REG_MODE_BITMAP;
/* Set raster operation */
cmd[1] = (2 << 7) | (GDC_ROP_COPY << 9);
cmd[2] = GDC_TYPE_BLTCOPYP << 24;
if (area->sx >= area->dx && area->sy >= area->dy)
cmd[2] |= GDC_CMD_BLTCOPY_TOP_LEFT << 16;
else if (area->sx >= area->dx && area->sy <= area->dy)
cmd[2] |= GDC_CMD_BLTCOPY_BOTTOM_LEFT << 16;
else if (area->sx <= area->dx && area->sy >= area->dy)
cmd[2] |= GDC_CMD_BLTCOPY_TOP_RIGHT << 16;
else
cmd[2] |= GDC_CMD_BLTCOPY_BOTTOM_RIGHT << 16;
cmd[3] = (area->sy << 16) | area->sx;
cmd[4] = (area->dy << 16) | area->dx;
cmd[5] = (area->height << 16) | area->width;
mb862xxfb_write_fifo(6, cmd, info);
}
/*
* Fill in the cmd array /GDC FIFO commands/ to draw a 1bit image.
* Make sure cmd has enough room!
*/
static void mb86290fb_imageblit1(u32 *cmd, u16 step, u16 dx, u16 dy,
u16 width, u16 height, u32 fgcolor,
u32 bgcolor, const struct fb_image *image,
struct fb_info *info)
{
int i;
unsigned const char *line;
u16 bytes;
/* set colors and raster operation regs */
cmd[0] = (GDC_TYPE_SETREGISTER << 24) | (1 << 16) | GDC_REG_MODE_BITMAP;
/* Set raster operation */
cmd[1] = (2 << 7) | (GDC_ROP_COPY << 9);
cmd[2] =
(GDC_TYPE_SETCOLORREGISTER << 24) | (GDC_CMD_BODY_FORE_COLOR << 16);
cmd[3] = fgcolor;
cmd[4] =
(GDC_TYPE_SETCOLORREGISTER << 24) | (GDC_CMD_BODY_BACK_COLOR << 16);
cmd[5] = bgcolor;
i = 0;
line = image->data;
bytes = (image->width + 7) >> 3;
/* and the image */
cmd[6] = (GDC_TYPE_DRAWBITMAPP << 24) |
(GDC_CMD_BITMAP << 16) | (2 + (step * height));
cmd[7] = (dy << 16) | dx;
cmd[8] = (height << 16) | width;
while (i < height) {
memcpy(&cmd[9 + i * step], line, step << 2);
#ifdef __LITTLE_ENDIAN
{
int k = 0;
for (k = 0; k < step; k++)
cmd[9 + i * step + k] =
cpu_to_be32(cmd[9 + i * step + k]);
}
#endif
line += bytes;
i++;
}
}
/*
* Fill in the cmd array /GDC FIFO commands/ to draw a 8bit image.
* Make sure cmd has enough room!
*/
static void mb86290fb_imageblit8(u32 *cmd, u16 step, u16 dx, u16 dy,
u16 width, u16 height, u32 fgcolor,
u32 bgcolor, const struct fb_image *image,
struct fb_info *info)
{
int i, j;
unsigned const char *line, *ptr;
u16 bytes;
cmd[0] = (GDC_TYPE_DRAWBITMAPP << 24) |
(GDC_CMD_BLT_DRAW << 16) | (2 + (height * step));
cmd[1] = (dy << 16) | dx;
cmd[2] = (height << 16) | width;
i = 0;
line = image->data;
bytes = image->width;
while (i < height) {
ptr = line;
for (j = 0; j < step; j++) {
cmd[3 + i * step + j] =
(((u32 *) (info->pseudo_palette))[*ptr]) & 0xffff;
ptr++;
cmd[3 + i * step + j] |=
((((u32 *) (info->
pseudo_palette))[*ptr]) & 0xffff) << 16;
ptr++;
}
line += bytes;
i++;
}
}
/*
* Fill in the cmd array /GDC FIFO commands/ to draw a 16bit image.
* Make sure cmd has enough room!
*/
static void mb86290fb_imageblit16(u32 *cmd, u16 step, u16 dx, u16 dy,
u16 width, u16 height, u32 fgcolor,
u32 bgcolor, const struct fb_image *image,
struct fb_info *info)
{
int i;
unsigned const char *line;
u16 bytes;
i = 0;
line = image->data;
bytes = image->width << 1;
cmd[0] = (GDC_TYPE_DRAWBITMAPP << 24) |
(GDC_CMD_BLT_DRAW << 16) | (2 + step * height);
cmd[1] = (dy << 16) | dx;
cmd[2] = (height << 16) | width;
while (i < height) {
memcpy(&cmd[3 + i * step], line, step);
line += bytes;
i++;
}
}
static void mb86290fb_imageblit(struct fb_info *info,
const struct fb_image *image)
{
u32 *cmd = NULL;
void (*cmdfn) (u32 *, u16, u16, u16, u16, u16, u32, u32,
const struct fb_image *, struct fb_info *) = NULL;
u32 cmdlen;
u32 fgcolor = 0, bgcolor = 0;
u16 step;
u16 width = image->width, height = image->height;
u16 dx = image->dx, dy = image->dy;
int x2, y2, vxres, vyres;
x2 = image->dx + image->width;
y2 = image->dy + image->height;
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
x2 = min(x2, vxres);
y2 = min(y2, vyres);
width = x2 - dx;
height = y2 - dy;
switch (image->depth) {
case 1:
step = (width + 31) >> 5;
cmdlen = 9 + height * step;
cmdfn = mb86290fb_imageblit1;
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
fgcolor =
((u32 *) (info->pseudo_palette))[image->fg_color];
bgcolor =
((u32 *) (info->pseudo_palette))[image->bg_color];
} else {
fgcolor = image->fg_color;
bgcolor = image->bg_color;
}
break;
case 8:
step = (width + 1) >> 1;
cmdlen = 3 + height * step;
cmdfn = mb86290fb_imageblit8;
break;
case 16:
step = (width + 1) >> 1;
cmdlen = 3 + height * step;
cmdfn = mb86290fb_imageblit16;
break;
default:
cfb_imageblit(info, image);
return;
}
cmd = kmalloc_array(cmdlen, 4, GFP_DMA);
if (!cmd)
return cfb_imageblit(info, image);
cmdfn(cmd, step, dx, dy, width, height, fgcolor, bgcolor, image, info);
mb862xxfb_write_fifo(cmdlen, cmd, info);
kfree(cmd);
}
static void mb86290fb_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
u32 x2, y2, vxres, vyres, height, width, fg;
u32 cmd[7];
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
if (!rect->width || !rect->height || rect->dx > vxres
|| rect->dy > vyres)
return;
/* We could use hardware clipping but on many cards you get around
* hardware clipping by writing to framebuffer directly. */
x2 = rect->dx + rect->width;
y2 = rect->dy + rect->height;
x2 = min(x2, vxres);
y2 = min(y2, vyres);
width = x2 - rect->dx;
height = y2 - rect->dy;
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR)
fg = ((u32 *) (info->pseudo_palette))[rect->color];
else
fg = rect->color;
switch (rect->rop) {
case ROP_XOR:
/* Set raster operation */
cmd[1] = (2 << 7) | (GDC_ROP_XOR << 9);
break;
case ROP_COPY:
/* Set raster operation */
cmd[1] = (2 << 7) | (GDC_ROP_COPY << 9);
break;
}
cmd[0] = (GDC_TYPE_SETREGISTER << 24) | (1 << 16) | GDC_REG_MODE_BITMAP;
/* cmd[1] set earlier */
cmd[2] =
(GDC_TYPE_SETCOLORREGISTER << 24) | (GDC_CMD_BODY_FORE_COLOR << 16);
cmd[3] = fg;
cmd[4] = (GDC_TYPE_DRAWRECTP << 24) | (GDC_CMD_BLT_FILL << 16);
cmd[5] = (rect->dy << 16) | (rect->dx);
cmd[6] = (height << 16) | width;
mb862xxfb_write_fifo(7, cmd, info);
}
void mb862xxfb_init_accel(struct fb_info *info, struct fb_ops *fbops, int xres)
{
struct mb862xxfb_par *par = info->par;
if (info->var.bits_per_pixel == 32) {
fbops->fb_fillrect = cfb_fillrect;
fbops->fb_copyarea = cfb_copyarea;
fbops->fb_imageblit = cfb_imageblit;
} else {
outreg(disp, GC_L0EM, 3);
fbops->fb_fillrect = mb86290fb_fillrect;
fbops->fb_copyarea = mb86290fb_copyarea;
fbops->fb_imageblit = mb86290fb_imageblit;
}
outreg(draw, GDC_REG_DRAW_BASE, 0);
outreg(draw, GDC_REG_MODE_MISC, 0x8000);
outreg(draw, GDC_REG_X_RESOLUTION, xres);
info->flags |=
FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_IMAGEBLIT;
info->fix.accel = 0xff; /*FIXME: add right define */
}
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/mb862xx/mb862xxfb_accel.c |
/*-*- linux-c -*-
* linux/drivers/video/savage/savage_accel.c -- Hardware Acceleration
*
* Copyright (C) 2004 Antonino Daplas<[email protected]>
* All Rights Reserved
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/module.h>
#include "savagefb.h"
static u32 savagefb_rop[] = {
0xCC, /* ROP_COPY */
0x5A /* ROP_XOR */
};
int savagefb_sync(struct fb_info *info)
{
struct savagefb_par *par = info->par;
par->SavageWaitIdle(par);
return 0;
}
void savagefb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct savagefb_par *par = info->par;
int sx = region->sx, dx = region->dx;
int sy = region->sy, dy = region->dy;
int cmd;
if (!region->width || !region->height)
return;
par->bci_ptr = 0;
cmd = BCI_CMD_RECT | BCI_CMD_DEST_GBD | BCI_CMD_SRC_GBD;
BCI_CMD_SET_ROP(cmd, savagefb_rop[0]);
if (dx <= sx) {
cmd |= BCI_CMD_RECT_XP;
} else {
sx += region->width - 1;
dx += region->width - 1;
}
if (dy <= sy) {
cmd |= BCI_CMD_RECT_YP;
} else {
sy += region->height - 1;
dy += region->height - 1;
}
par->SavageWaitFifo(par,4);
BCI_SEND(cmd);
BCI_SEND(BCI_X_Y(sx, sy));
BCI_SEND(BCI_X_Y(dx, dy));
BCI_SEND(BCI_W_H(region->width, region->height));
}
void savagefb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct savagefb_par *par = info->par;
int cmd, color;
if (!rect->width || !rect->height)
return;
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
color = rect->color;
else
color = ((u32 *)info->pseudo_palette)[rect->color];
cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP |
BCI_CMD_DEST_GBD | BCI_CMD_SRC_SOLID |
BCI_CMD_SEND_COLOR;
par->bci_ptr = 0;
BCI_CMD_SET_ROP(cmd, savagefb_rop[rect->rop]);
par->SavageWaitFifo(par,4);
BCI_SEND(cmd);
BCI_SEND(color);
BCI_SEND( BCI_X_Y(rect->dx, rect->dy) );
BCI_SEND( BCI_W_H(rect->width, rect->height) );
}
void savagefb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct savagefb_par *par = info->par;
int fg, bg, size, i, width;
int cmd;
u32 *src = (u32 *) image->data;
if (!image->width || !image->height)
return;
if (image->depth != 1) {
cfb_imageblit(info, image);
return;
}
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
fg = image->fg_color;
bg = image->bg_color;
} else {
fg = ((u32 *)info->pseudo_palette)[image->fg_color];
bg = ((u32 *)info->pseudo_palette)[image->bg_color];
}
cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP |
BCI_CMD_CLIP_LR | BCI_CMD_DEST_GBD | BCI_CMD_SRC_MONO |
BCI_CMD_SEND_COLOR;
par->bci_ptr = 0;
BCI_CMD_SET_ROP(cmd, savagefb_rop[0]);
width = (image->width + 31) & ~31;
size = (width * image->height)/8;
size >>= 2;
par->SavageWaitFifo(par, size + 5);
BCI_SEND(cmd);
BCI_SEND(BCI_CLIP_LR(image->dx, image->dx + image->width - 1));
BCI_SEND(fg);
BCI_SEND(bg);
BCI_SEND(BCI_X_Y(image->dx, image->dy));
BCI_SEND(BCI_W_H(width, image->height));
for (i = 0; i < size; i++)
BCI_SEND(src[i]);
}
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/savage/savagefb_accel.c |
/*
* linux/drivers/video/savage/savagefb-i2c.c - S3 Savage DDC2
*
* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
*
* Based partly on rivafb-i2c.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include <asm/io.h>
#include "savagefb.h"
#define SAVAGE_DDC 0x50
#define VGA_CR_IX 0x3d4
#define VGA_CR_DATA 0x3d5
#define CR_SERIAL1 0xa0 /* I2C serial communications interface */
#define MM_SERIAL1 0xff20
#define CR_SERIAL2 0xb1 /* DDC2 monitor communications interface */
/* based on vt8365 documentation */
#define PROSAVAGE_I2C_ENAB 0x10
#define PROSAVAGE_I2C_SCL_OUT 0x01
#define PROSAVAGE_I2C_SDA_OUT 0x02
#define PROSAVAGE_I2C_SCL_IN 0x04
#define PROSAVAGE_I2C_SDA_IN 0x08
#define SAVAGE4_I2C_ENAB 0x00000020
#define SAVAGE4_I2C_SCL_OUT 0x00000001
#define SAVAGE4_I2C_SDA_OUT 0x00000002
#define SAVAGE4_I2C_SCL_IN 0x00000008
#define SAVAGE4_I2C_SDA_IN 0x00000010
static void savage4_gpio_setscl(void *data, int val)
{
struct savagefb_i2c_chan *chan = data;
unsigned int r;
r = readl(chan->ioaddr + chan->reg);
if(val)
r |= SAVAGE4_I2C_SCL_OUT;
else
r &= ~SAVAGE4_I2C_SCL_OUT;
writel(r, chan->ioaddr + chan->reg);
readl(chan->ioaddr + chan->reg); /* flush posted write */
}
static void savage4_gpio_setsda(void *data, int val)
{
struct savagefb_i2c_chan *chan = data;
unsigned int r;
r = readl(chan->ioaddr + chan->reg);
if(val)
r |= SAVAGE4_I2C_SDA_OUT;
else
r &= ~SAVAGE4_I2C_SDA_OUT;
writel(r, chan->ioaddr + chan->reg);
readl(chan->ioaddr + chan->reg); /* flush posted write */
}
static int savage4_gpio_getscl(void *data)
{
struct savagefb_i2c_chan *chan = data;
return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN));
}
static int savage4_gpio_getsda(void *data)
{
struct savagefb_i2c_chan *chan = data;
return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SDA_IN));
}
static void prosavage_gpio_setscl(void* data, int val)
{
struct savagefb_i2c_chan *chan = data;
u32 r;
r = VGArCR(chan->reg, chan->par);
r |= PROSAVAGE_I2C_ENAB;
if (val) {
r |= PROSAVAGE_I2C_SCL_OUT;
} else {
r &= ~PROSAVAGE_I2C_SCL_OUT;
}
VGAwCR(chan->reg, r, chan->par);
}
static void prosavage_gpio_setsda(void* data, int val)
{
struct savagefb_i2c_chan *chan = data;
unsigned int r;
r = VGArCR(chan->reg, chan->par);
r |= PROSAVAGE_I2C_ENAB;
if (val) {
r |= PROSAVAGE_I2C_SDA_OUT;
} else {
r &= ~PROSAVAGE_I2C_SDA_OUT;
}
VGAwCR(chan->reg, r, chan->par);
}
static int prosavage_gpio_getscl(void* data)
{
struct savagefb_i2c_chan *chan = data;
return (VGArCR(chan->reg, chan->par) & PROSAVAGE_I2C_SCL_IN) ? 1 : 0;
}
static int prosavage_gpio_getsda(void* data)
{
struct savagefb_i2c_chan *chan = data;
return (VGArCR(chan->reg, chan->par) & PROSAVAGE_I2C_SDA_IN) ? 1 : 0;
}
static int savage_setup_i2c_bus(struct savagefb_i2c_chan *chan,
const char *name)
{
int rc = 0;
if (chan->par) {
strcpy(chan->adapter.name, name);
chan->adapter.owner = THIS_MODULE;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->par->pcidev->dev;
chan->algo.udelay = 10;
chan->algo.timeout = 20;
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
/* Raise SCL and SDA */
chan->algo.setsda(chan, 1);
chan->algo.setscl(chan, 1);
udelay(20);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
dev_dbg(&chan->par->pcidev->dev,
"I2C bus %s registered.\n", name);
else
dev_warn(&chan->par->pcidev->dev,
"Failed to register I2C bus %s.\n", name);
}
return rc;
}
void savagefb_create_i2c_busses(struct fb_info *info)
{
struct savagefb_par *par = info->par;
par->chan.par = par;
switch (par->chip) {
case S3_PROSAVAGE:
case S3_PROSAVAGEDDR:
case S3_TWISTER:
par->chan.reg = CR_SERIAL2;
par->chan.ioaddr = par->mmio.vbase;
par->chan.algo.setsda = prosavage_gpio_setsda;
par->chan.algo.setscl = prosavage_gpio_setscl;
par->chan.algo.getsda = prosavage_gpio_getsda;
par->chan.algo.getscl = prosavage_gpio_getscl;
break;
case S3_SAVAGE4:
par->chan.reg = CR_SERIAL1;
if (par->pcidev->revision > 1 && !(VGArCR(0xa6, par) & 0x40))
par->chan.reg = CR_SERIAL2;
par->chan.ioaddr = par->mmio.vbase;
par->chan.algo.setsda = prosavage_gpio_setsda;
par->chan.algo.setscl = prosavage_gpio_setscl;
par->chan.algo.getsda = prosavage_gpio_getsda;
par->chan.algo.getscl = prosavage_gpio_getscl;
break;
case S3_SAVAGE2000:
par->chan.reg = MM_SERIAL1;
par->chan.ioaddr = par->mmio.vbase;
par->chan.algo.setsda = savage4_gpio_setsda;
par->chan.algo.setscl = savage4_gpio_setscl;
par->chan.algo.getsda = savage4_gpio_getsda;
par->chan.algo.getscl = savage4_gpio_getscl;
break;
default:
par->chan.par = NULL;
}
savage_setup_i2c_bus(&par->chan, "SAVAGE DDC2");
}
void savagefb_delete_i2c_busses(struct fb_info *info)
{
struct savagefb_par *par = info->par;
if (par->chan.par)
i2c_del_adapter(&par->chan.adapter);
par->chan.par = NULL;
}
int savagefb_probe_i2c_connector(struct fb_info *info, u8 **out_edid)
{
struct savagefb_par *par = info->par;
u8 *edid;
if (par->chan.par)
edid = fb_ddc_read(&par->chan.adapter);
else
edid = NULL;
if (!edid) {
/* try to get from firmware */
const u8 *e = fb_firmware_edid(info->device);
if (e)
edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
}
*out_edid = edid;
return (edid) ? 0 : 1;
}
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/savage/savagefb-i2c.c |
/*
* linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
*
* Copyright (c) 2001-2002 Denis Oliver Kropp <[email protected]>
* Sven Neumann <[email protected]>
*
*
* Card specific code is based on XFree86's savage driver.
* Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* 0.4.0 (neo)
* - hardware accelerated clear and move
*
* 0.3.2 (dok)
* - wait for vertical retrace before writing to cr67
* at the beginning of savagefb_set_par
* - use synchronization registers cr23 and cr26
*
* 0.3.1 (dok)
* - reset 3D engine
* - don't return alpha bits for 32bit format
*
* 0.3.0 (dok)
* - added WaitIdle functions for all Savage types
* - do WaitIdle before mode switching
* - code cleanup
*
* 0.2.0 (dok)
* - first working version
*
*
* TODO
* - clock validations in decode_var
*
* BUGS
* - white margin on bootup
*
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/console.h>
#include <asm/io.h>
#include <asm/irq.h>
#include "savagefb.h"
#define SAVAGEFB_VERSION "0.4.0_2.6"
/* --------------------------------------------------------------------- */
static char *mode_option = NULL;
#ifdef MODULE
MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
#endif
/* --------------------------------------------------------------------- */
static void vgaHWSeqReset(struct savagefb_par *par, int start)
{
if (start)
VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */
else
VGAwSEQ(0x00, 0x03, par); /* End Reset */
}
static void vgaHWProtect(struct savagefb_par *par, int on)
{
unsigned char tmp;
if (on) {
/*
* Turn off screen and disable sequencer.
*/
tmp = VGArSEQ(0x01, par);
vgaHWSeqReset(par, 1); /* start synchronous reset */
VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
VGAenablePalette(par);
} else {
/*
* Reenable sequencer, then turn on screen.
*/
tmp = VGArSEQ(0x01, par);
VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
vgaHWSeqReset(par, 0); /* clear synchronous reset */
VGAdisablePalette(par);
}
}
static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)
{
int i;
VGAwMISC(reg->MiscOutReg, par);
for (i = 1; i < 5; i++)
VGAwSEQ(i, reg->Sequencer[i], par);
/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
CRTC[17] */
VGAwCR(17, reg->CRTC[17] & ~0x80, par);
for (i = 0; i < 25; i++)
VGAwCR(i, reg->CRTC[i], par);
for (i = 0; i < 9; i++)
VGAwGR(i, reg->Graphics[i], par);
VGAenablePalette(par);
for (i = 0; i < 21; i++)
VGAwATTR(i, reg->Attribute[i], par);
VGAdisablePalette(par);
}
static void vgaHWInit(struct fb_var_screeninfo *var,
struct savagefb_par *par,
struct xtimings *timings,
struct savage_reg *reg)
{
reg->MiscOutReg = 0x23;
if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
reg->MiscOutReg |= 0x40;
if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
reg->MiscOutReg |= 0x80;
/*
* Time Sequencer
*/
reg->Sequencer[0x00] = 0x00;
reg->Sequencer[0x01] = 0x01;
reg->Sequencer[0x02] = 0x0F;
reg->Sequencer[0x03] = 0x00; /* Font select */
reg->Sequencer[0x04] = 0x0E; /* Misc */
/*
* CRTC Controller
*/
reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
reg->CRTC[0x04] = (timings->HSyncStart >> 3);
reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
(((timings->HSyncEnd >> 3)) & 0x1f);
reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
(((timings->VDisplay - 1) & 0x100) >> 7) |
((timings->VSyncStart & 0x100) >> 6) |
(((timings->VSyncStart - 1) & 0x100) >> 5) |
0x10 |
(((timings->VTotal - 2) & 0x200) >> 4) |
(((timings->VDisplay - 1) & 0x200) >> 3) |
((timings->VSyncStart & 0x200) >> 2);
reg->CRTC[0x08] = 0x00;
reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
if (timings->dblscan)
reg->CRTC[0x09] |= 0x80;
reg->CRTC[0x0a] = 0x00;
reg->CRTC[0x0b] = 0x00;
reg->CRTC[0x0c] = 0x00;
reg->CRTC[0x0d] = 0x00;
reg->CRTC[0x0e] = 0x00;
reg->CRTC[0x0f] = 0x00;
reg->CRTC[0x10] = timings->VSyncStart & 0xff;
reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
reg->CRTC[0x13] = var->xres_virtual >> 4;
reg->CRTC[0x14] = 0x00;
reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
reg->CRTC[0x17] = 0xc3;
reg->CRTC[0x18] = 0xff;
/*
* are these unnecessary?
* vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
* vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
*/
/*
* Graphics Display Controller
*/
reg->Graphics[0x00] = 0x00;
reg->Graphics[0x01] = 0x00;
reg->Graphics[0x02] = 0x00;
reg->Graphics[0x03] = 0x00;
reg->Graphics[0x04] = 0x00;
reg->Graphics[0x05] = 0x40;
reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
reg->Graphics[0x07] = 0x0F;
reg->Graphics[0x08] = 0xFF;
reg->Attribute[0x00] = 0x00; /* standard colormap translation */
reg->Attribute[0x01] = 0x01;
reg->Attribute[0x02] = 0x02;
reg->Attribute[0x03] = 0x03;
reg->Attribute[0x04] = 0x04;
reg->Attribute[0x05] = 0x05;
reg->Attribute[0x06] = 0x06;
reg->Attribute[0x07] = 0x07;
reg->Attribute[0x08] = 0x08;
reg->Attribute[0x09] = 0x09;
reg->Attribute[0x0a] = 0x0A;
reg->Attribute[0x0b] = 0x0B;
reg->Attribute[0x0c] = 0x0C;
reg->Attribute[0x0d] = 0x0D;
reg->Attribute[0x0e] = 0x0E;
reg->Attribute[0x0f] = 0x0F;
reg->Attribute[0x10] = 0x41;
reg->Attribute[0x11] = 0xFF;
reg->Attribute[0x12] = 0x0F;
reg->Attribute[0x13] = 0x00;
reg->Attribute[0x14] = 0x00;
}
/* -------------------- Hardware specific routines ------------------------- */
/*
* Hardware Acceleration for SavageFB
*/
/* Wait for fifo space */
static void
savage3D_waitfifo(struct savagefb_par *par, int space)
{
int slots = MAXFIFO - space;
while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
}
static void
savage4_waitfifo(struct savagefb_par *par, int space)
{
int slots = MAXFIFO - space;
while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
}
static void
savage2000_waitfifo(struct savagefb_par *par, int space)
{
int slots = MAXFIFO - space;
while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
}
/* Wait for idle accelerator */
static void
savage3D_waitidle(struct savagefb_par *par)
{
while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
}
static void
savage4_waitidle(struct savagefb_par *par)
{
while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
}
static void
savage2000_waitidle(struct savagefb_par *par)
{
while ((savage_in32(0x48C60, par) & 0x009fffff));
}
#ifdef CONFIG_FB_SAVAGE_ACCEL
static void
SavageSetup2DEngine(struct savagefb_par *par)
{
unsigned long GlobalBitmapDescriptor;
GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
switch(par->chip) {
case S3_SAVAGE3D:
case S3_SAVAGE_MX:
/* Disable BCI */
savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
/* Setup BCI command overflow buffer */
savage_out32(0x48C14,
(par->cob_offset >> 11) | (par->cob_index << 29),
par);
/* Program shadow status update. */
savage_out32(0x48C10, 0x78207220, par);
savage_out32(0x48C0C, 0, par);
/* Enable BCI and command overflow buffer */
savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
break;
case S3_SAVAGE4:
case S3_TWISTER:
case S3_PROSAVAGE:
case S3_PROSAVAGEDDR:
case S3_SUPERSAVAGE:
/* Disable BCI */
savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
/* Program shadow status update */
savage_out32(0x48C10, 0x00700040, par);
savage_out32(0x48C0C, 0, par);
/* Enable BCI without the COB */
savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
break;
case S3_SAVAGE2000:
/* Disable BCI */
savage_out32(0x48C18, 0, par);
/* Setup BCI command overflow buffer */
savage_out32(0x48C18,
(par->cob_offset >> 7) | (par->cob_index),
par);
/* Disable shadow status update */
savage_out32(0x48A30, 0, par);
/* Enable BCI and command overflow buffer */
savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
par);
break;
default:
break;
}
/* Turn on 16-bit register access. */
vga_out8(0x3d4, 0x31, par);
vga_out8(0x3d5, 0x0c, par);
/* Set stride to use GBD. */
vga_out8(0x3d4, 0x50, par);
vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
/* Enable 2D engine. */
vga_out8(0x3d4, 0x40, par);
vga_out8(0x3d5, 0x01, par);
savage_out32(MONO_PAT_0, ~0, par);
savage_out32(MONO_PAT_1, ~0, par);
/* Setup plane masks */
savage_out32(0x8128, ~0, par); /* enable all write planes */
savage_out32(0x812C, ~0, par); /* enable all read planes */
savage_out16(0x8134, 0x27, par);
savage_out16(0x8136, 0x07, par);
/* Now set the GBD */
par->bci_ptr = 0;
par->SavageWaitFifo(par, 4);
BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
BCI_SEND(0);
BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
BCI_SEND(GlobalBitmapDescriptor);
/*
* I don't know why, sending this twice fixes the initial black screen,
* prevents X from crashing at least in Toshiba laptops with SavageIX.
* --Tony
*/
par->bci_ptr = 0;
par->SavageWaitFifo(par, 4);
BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
BCI_SEND(0);
BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
BCI_SEND(GlobalBitmapDescriptor);
}
static void savagefb_set_clip(struct fb_info *info)
{
struct savagefb_par *par = info->par;
int cmd;
cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
par->bci_ptr = 0;
par->SavageWaitFifo(par,3);
BCI_SEND(cmd);
BCI_SEND(BCI_CLIP_TL(0, 0));
BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
}
#else
static void SavageSetup2DEngine(struct savagefb_par *par) {}
#endif
static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
int min_n2, int max_n2, long freq_min,
long freq_max, unsigned int *mdiv,
unsigned int *ndiv, unsigned int *r)
{
long diff, best_diff;
unsigned int m;
unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
if (freq < freq_min / (1 << max_n2)) {
printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
freq = freq_min / (1 << max_n2);
}
if (freq > freq_max / (1 << min_n2)) {
printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
freq = freq_max / (1 << min_n2);
}
/* work out suitable timings */
best_diff = freq;
for (n2=min_n2; n2<=max_n2; n2++) {
for (n1=min_n1+2; n1<=max_n1+2; n1++) {
m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
BASE_FREQ;
if (m < min_m+2 || m > 127+2)
continue;
if ((m * BASE_FREQ >= freq_min * n1) &&
(m * BASE_FREQ <= freq_max * n1)) {
diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
if (diff < 0)
diff = -diff;
if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n1 = n1;
best_n2 = n2;
}
}
}
}
*ndiv = best_n1 - 2;
*r = best_n2;
*mdiv = best_m - 2;
}
static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
int min_n2, int max_n2, long freq_min,
long freq_max, unsigned char *mdiv,
unsigned char *ndiv)
{
long diff, best_diff;
unsigned int m;
unsigned char n1, n2;
unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
best_diff = freq;
for (n2 = min_n2; n2 <= max_n2; n2++) {
for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
BASE_FREQ;
if (m < min_m + 2 || m > 127+2)
continue;
if ((m * BASE_FREQ >= freq_min * n1) &&
(m * BASE_FREQ <= freq_max * n1)) {
diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
if (diff < 0)
diff = -diff;
if (diff < best_diff) {
best_diff = diff;
best_m = m;
best_n1 = n1;
best_n2 = n2;
}
}
}
}
if (max_n1 == 63)
*ndiv = (best_n1 - 2) | (best_n2 << 6);
else
*ndiv = (best_n1 - 2) | (best_n2 << 5);
*mdiv = best_m - 2;
return 0;
}
#ifdef SAVAGEFB_DEBUG
/* This function is used to debug, it prints out the contents of s3 regs */
static void SavagePrintRegs(struct savagefb_par *par)
{
unsigned char i;
int vgaCRIndex = 0x3d4;
int vgaCRReg = 0x3d5;
printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
"xF");
for (i = 0; i < 0x70; i++) {
if (!(i % 16))
printk(KERN_DEBUG "\nSR%xx ", i >> 4);
vga_out8(0x3c4, i, par);
printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
}
printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
"xD xE xF");
for (i = 0; i < 0xB7; i++) {
if (!(i % 16))
printk(KERN_DEBUG "\nCR%xx ", i >> 4);
vga_out8(vgaCRIndex, i, par);
printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
}
printk(KERN_DEBUG "\n\n");
}
#endif
/* --------------------------------------------------------------------- */
static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
{
unsigned char cr3a, cr53, cr66;
vga_out16(0x3d4, 0x4838, par);
vga_out16(0x3d4, 0xa039, par);
vga_out16(0x3c4, 0x0608, par);
vga_out8(0x3d4, 0x66, par);
cr66 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr66 | 0x80, par);
vga_out8(0x3d4, 0x3a, par);
cr3a = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr3a | 0x80, par);
vga_out8(0x3d4, 0x53, par);
cr53 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr53 & 0x7f, par);
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, cr66, par);
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, cr3a, par);
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, cr66, par);
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, cr3a, par);
/* unlock extended seq regs */
vga_out8(0x3c4, 0x08, par);
reg->SR08 = vga_in8(0x3c5, par);
vga_out8(0x3c5, 0x06, par);
/* now save all the extended regs we need */
vga_out8(0x3d4, 0x31, par);
reg->CR31 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x32, par);
reg->CR32 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x34, par);
reg->CR34 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x36, par);
reg->CR36 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x3a, par);
reg->CR3A = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x40, par);
reg->CR40 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x42, par);
reg->CR42 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x45, par);
reg->CR45 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x50, par);
reg->CR50 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x51, par);
reg->CR51 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x53, par);
reg->CR53 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x58, par);
reg->CR58 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x60, par);
reg->CR60 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x66, par);
reg->CR66 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x67, par);
reg->CR67 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x68, par);
reg->CR68 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x69, par);
reg->CR69 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x6f, par);
reg->CR6F = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x33, par);
reg->CR33 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x86, par);
reg->CR86 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x88, par);
reg->CR88 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x90, par);
reg->CR90 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x91, par);
reg->CR91 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0xb0, par);
reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
/* extended mode timing regs */
vga_out8(0x3d4, 0x3b, par);
reg->CR3B = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x3c, par);
reg->CR3C = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x43, par);
reg->CR43 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x5d, par);
reg->CR5D = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x5e, par);
reg->CR5E = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x65, par);
reg->CR65 = vga_in8(0x3d5, par);
/* save seq extended regs for DCLK PLL programming */
vga_out8(0x3c4, 0x0e, par);
reg->SR0E = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x0f, par);
reg->SR0F = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x10, par);
reg->SR10 = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x11, par);
reg->SR11 = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x12, par);
reg->SR12 = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x13, par);
reg->SR13 = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x29, par);
reg->SR29 = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x15, par);
reg->SR15 = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x30, par);
reg->SR30 = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x18, par);
reg->SR18 = vga_in8(0x3c5, par);
/* Save flat panel expansion registers. */
if (par->chip == S3_SAVAGE_MX) {
int i;
for (i = 0; i < 8; i++) {
vga_out8(0x3c4, 0x54+i, par);
reg->SR54[i] = vga_in8(0x3c5, par);
}
}
vga_out8(0x3d4, 0x66, par);
cr66 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr66 | 0x80, par);
vga_out8(0x3d4, 0x3a, par);
cr3a = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr3a | 0x80, par);
/* now save MIU regs */
if (par->chip != S3_SAVAGE_MX) {
reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
}
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, cr3a, par);
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, cr66, par);
}
static void savage_set_default_par(struct savagefb_par *par,
struct savage_reg *reg)
{
unsigned char cr3a, cr53, cr66;
vga_out16(0x3d4, 0x4838, par);
vga_out16(0x3d4, 0xa039, par);
vga_out16(0x3c4, 0x0608, par);
vga_out8(0x3d4, 0x66, par);
cr66 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr66 | 0x80, par);
vga_out8(0x3d4, 0x3a, par);
cr3a = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr3a | 0x80, par);
vga_out8(0x3d4, 0x53, par);
cr53 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr53 & 0x7f, par);
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, cr66, par);
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, cr3a, par);
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, cr66, par);
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, cr3a, par);
/* unlock extended seq regs */
vga_out8(0x3c4, 0x08, par);
vga_out8(0x3c5, reg->SR08, par);
vga_out8(0x3c5, 0x06, par);
/* now restore all the extended regs we need */
vga_out8(0x3d4, 0x31, par);
vga_out8(0x3d5, reg->CR31, par);
vga_out8(0x3d4, 0x32, par);
vga_out8(0x3d5, reg->CR32, par);
vga_out8(0x3d4, 0x34, par);
vga_out8(0x3d5, reg->CR34, par);
vga_out8(0x3d4, 0x36, par);
vga_out8(0x3d5,reg->CR36, par);
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, reg->CR3A, par);
vga_out8(0x3d4, 0x40, par);
vga_out8(0x3d5, reg->CR40, par);
vga_out8(0x3d4, 0x42, par);
vga_out8(0x3d5, reg->CR42, par);
vga_out8(0x3d4, 0x45, par);
vga_out8(0x3d5, reg->CR45, par);
vga_out8(0x3d4, 0x50, par);
vga_out8(0x3d5, reg->CR50, par);
vga_out8(0x3d4, 0x51, par);
vga_out8(0x3d5, reg->CR51, par);
vga_out8(0x3d4, 0x53, par);
vga_out8(0x3d5, reg->CR53, par);
vga_out8(0x3d4, 0x58, par);
vga_out8(0x3d5, reg->CR58, par);
vga_out8(0x3d4, 0x60, par);
vga_out8(0x3d5, reg->CR60, par);
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, reg->CR66, par);
vga_out8(0x3d4, 0x67, par);
vga_out8(0x3d5, reg->CR67, par);
vga_out8(0x3d4, 0x68, par);
vga_out8(0x3d5, reg->CR68, par);
vga_out8(0x3d4, 0x69, par);
vga_out8(0x3d5, reg->CR69, par);
vga_out8(0x3d4, 0x6f, par);
vga_out8(0x3d5, reg->CR6F, par);
vga_out8(0x3d4, 0x33, par);
vga_out8(0x3d5, reg->CR33, par);
vga_out8(0x3d4, 0x86, par);
vga_out8(0x3d5, reg->CR86, par);
vga_out8(0x3d4, 0x88, par);
vga_out8(0x3d5, reg->CR88, par);
vga_out8(0x3d4, 0x90, par);
vga_out8(0x3d5, reg->CR90, par);
vga_out8(0x3d4, 0x91, par);
vga_out8(0x3d5, reg->CR91, par);
vga_out8(0x3d4, 0xb0, par);
vga_out8(0x3d5, reg->CRB0, par);
/* extended mode timing regs */
vga_out8(0x3d4, 0x3b, par);
vga_out8(0x3d5, reg->CR3B, par);
vga_out8(0x3d4, 0x3c, par);
vga_out8(0x3d5, reg->CR3C, par);
vga_out8(0x3d4, 0x43, par);
vga_out8(0x3d5, reg->CR43, par);
vga_out8(0x3d4, 0x5d, par);
vga_out8(0x3d5, reg->CR5D, par);
vga_out8(0x3d4, 0x5e, par);
vga_out8(0x3d5, reg->CR5E, par);
vga_out8(0x3d4, 0x65, par);
vga_out8(0x3d5, reg->CR65, par);
/* save seq extended regs for DCLK PLL programming */
vga_out8(0x3c4, 0x0e, par);
vga_out8(0x3c5, reg->SR0E, par);
vga_out8(0x3c4, 0x0f, par);
vga_out8(0x3c5, reg->SR0F, par);
vga_out8(0x3c4, 0x10, par);
vga_out8(0x3c5, reg->SR10, par);
vga_out8(0x3c4, 0x11, par);
vga_out8(0x3c5, reg->SR11, par);
vga_out8(0x3c4, 0x12, par);
vga_out8(0x3c5, reg->SR12, par);
vga_out8(0x3c4, 0x13, par);
vga_out8(0x3c5, reg->SR13, par);
vga_out8(0x3c4, 0x29, par);
vga_out8(0x3c5, reg->SR29, par);
vga_out8(0x3c4, 0x15, par);
vga_out8(0x3c5, reg->SR15, par);
vga_out8(0x3c4, 0x30, par);
vga_out8(0x3c5, reg->SR30, par);
vga_out8(0x3c4, 0x18, par);
vga_out8(0x3c5, reg->SR18, par);
/* Save flat panel expansion registers. */
if (par->chip == S3_SAVAGE_MX) {
int i;
for (i = 0; i < 8; i++) {
vga_out8(0x3c4, 0x54+i, par);
vga_out8(0x3c5, reg->SR54[i], par);
}
}
vga_out8(0x3d4, 0x66, par);
cr66 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr66 | 0x80, par);
vga_out8(0x3d4, 0x3a, par);
cr3a = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr3a | 0x80, par);
/* now save MIU regs */
if (par->chip != S3_SAVAGE_MX) {
savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
}
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, cr3a, par);
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, cr66, par);
}
static void savage_update_var(struct fb_var_screeninfo *var,
const struct fb_videomode *modedb)
{
var->xres = var->xres_virtual = modedb->xres;
var->yres = modedb->yres;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
var->xoffset = var->yoffset = 0;
var->pixclock = modedb->pixclock;
var->left_margin = modedb->left_margin;
var->right_margin = modedb->right_margin;
var->upper_margin = modedb->upper_margin;
var->lower_margin = modedb->lower_margin;
var->hsync_len = modedb->hsync_len;
var->vsync_len = modedb->vsync_len;
var->sync = modedb->sync;
var->vmode = modedb->vmode;
}
static int savagefb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct savagefb_par *par = info->par;
int memlen, vramlen, mode_valid = 0;
DBG("savagefb_check_var");
var->transp.offset = 0;
var->transp.length = 0;
switch (var->bits_per_pixel) {
case 8:
var->red.offset = var->green.offset =
var->blue.offset = 0;
var->red.length = var->green.length =
var->blue.length = var->bits_per_pixel;
break;
case 16:
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
break;
case 32:
var->transp.offset = 24;
var->transp.length = 8;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
default:
return -EINVAL;
}
if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
!info->monspecs.dclkmax || !fb_validate_mode(var, info))
mode_valid = 1;
/* calculate modeline if supported by monitor */
if (!mode_valid && info->monspecs.gtf) {
if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
mode_valid = 1;
}
if (!mode_valid) {
const struct fb_videomode *mode;
mode = fb_find_best_mode(var, &info->modelist);
if (mode) {
savage_update_var(var, mode);
mode_valid = 1;
}
}
if (!mode_valid && info->monspecs.modedb_len)
return -EINVAL;
/* Is the mode larger than the LCD panel? */
if (par->SavagePanelWidth &&
(var->xres > par->SavagePanelWidth ||
var->yres > par->SavagePanelHeight)) {
printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
"(%dx%d)\n", var->xres, var->yres,
par->SavagePanelWidth,
par->SavagePanelHeight);
return -1;
}
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
vramlen = info->fix.smem_len;
memlen = var->xres_virtual * var->bits_per_pixel *
var->yres_virtual / 8;
if (memlen > vramlen) {
var->yres_virtual = vramlen * 8 /
(var->xres_virtual * var->bits_per_pixel);
memlen = var->xres_virtual * var->bits_per_pixel *
var->yres_virtual / 8;
}
/* we must round yres/xres down, we already rounded y/xres_virtual up
if it was possible. We should return -EINVAL, but I disagree */
if (var->yres_virtual < var->yres)
var->yres = var->yres_virtual;
if (var->xres_virtual < var->xres)
var->xres = var->xres_virtual;
if (var->xoffset + var->xres > var->xres_virtual)
var->xoffset = var->xres_virtual - var->xres;
if (var->yoffset + var->yres > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
return 0;
}
static int savagefb_decode_var(struct fb_var_screeninfo *var,
struct savagefb_par *par,
struct savage_reg *reg)
{
struct xtimings timings;
int width, dclk, i, j; /*, refresh; */
unsigned int m, n, r;
unsigned char tmp = 0;
unsigned int pixclock = var->pixclock;
DBG("savagefb_decode_var");
memset(&timings, 0, sizeof(timings));
if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
timings.Clock = 1000000000 / pixclock;
if (timings.Clock < 1) timings.Clock = 1;
timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
timings.HDisplay = var->xres;
timings.HSyncStart = timings.HDisplay + var->right_margin;
timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
timings.HTotal = timings.HSyncEnd + var->left_margin;
timings.VDisplay = var->yres;
timings.VSyncStart = timings.VDisplay + var->lower_margin;
timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
timings.VTotal = timings.VSyncEnd + var->upper_margin;
timings.sync = var->sync;
par->depth = var->bits_per_pixel;
par->vwidth = var->xres_virtual;
if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {
timings.HDisplay *= 2;
timings.HSyncStart *= 2;
timings.HSyncEnd *= 2;
timings.HTotal *= 2;
}
/*
* This will allocate the datastructure and initialize all of the
* generic VGA registers.
*/
vgaHWInit(var, par, &timings, reg);
/* We need to set CR67 whether or not we use the BIOS. */
dclk = timings.Clock;
reg->CR67 = 0x00;
switch(var->bits_per_pixel) {
case 8:
if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
else
reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
break;
case 15:
if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
else
reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
break;
case 16:
if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
else
reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
break;
case 24:
reg->CR67 = 0x70;
break;
case 32:
reg->CR67 = 0xd0;
break;
}
/*
* Either BIOS use is disabled, or we failed to find a suitable
* match. Fall back to traditional register-crunching.
*/
vga_out8(0x3d4, 0x3a, par);
tmp = vga_in8(0x3d5, par);
if (1 /*FIXME:psav->pci_burst*/)
reg->CR3A = (tmp & 0x7f) | 0x15;
else
reg->CR3A = tmp | 0x95;
reg->CR53 = 0x00;
reg->CR31 = 0x8c;
reg->CR66 = 0x89;
vga_out8(0x3d4, 0x58, par);
reg->CR58 = vga_in8(0x3d5, par) & 0x80;
reg->CR58 |= 0x13;
reg->SR15 = 0x03 | 0x80;
reg->SR18 = 0x00;
reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
vga_out8(0x3d4, 0x40, par);
reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
reg->MMPR0 = 0x010400;
reg->MMPR1 = 0x00;
reg->MMPR2 = 0x0808;
reg->MMPR3 = 0x08080810;
SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
/* m = 107; n = 4; r = 2; */
if (par->MCLK <= 0) {
reg->SR10 = 255;
reg->SR11 = 255;
} else {
common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
®->SR11, ®->SR10);
/* reg->SR10 = 80; // MCLK == 286000 */
/* reg->SR11 = 125; */
}
reg->SR12 = (r << 6) | (n & 0x3f);
reg->SR13 = m & 0xff;
reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
if (var->bits_per_pixel < 24)
reg->MMPR0 -= 0x8000;
else
reg->MMPR0 -= 0x4000;
if (timings.interlaced)
reg->CR42 = 0x20;
else
reg->CR42 = 0x00;
reg->CR34 = 0x10; /* display fifo */
i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
((timings.HSyncStart & 0x800) >> 7);
if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
i |= 0x08;
if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
i |= 0x20;
j = (reg->CRTC[0] + ((i & 0x01) << 8) +
reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
reg->CRTC[0] + ((i & 0x01) << 8))
j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
else
j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
}
reg->CR3B = j & 0xff;
i |= (j & 0x100) >> 2;
reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
reg->CR5D = i;
reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
(((timings.VDisplay - 1) & 0x400) >> 9) |
(((timings.VSyncStart) & 0x400) >> 8) |
(((timings.VSyncStart) & 0x400) >> 6) | 0x40;
width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
reg->CR91 = reg->CRTC[19] = 0xff & width;
reg->CR51 = (0x300 & width) >> 4;
reg->CR90 = 0x80 | (width >> 8);
reg->MiscOutReg |= 0x0c;
/* Set frame buffer description. */
if (var->bits_per_pixel <= 8)
reg->CR50 = 0;
else if (var->bits_per_pixel <= 16)
reg->CR50 = 0x10;
else
reg->CR50 = 0x30;
if (var->xres_virtual <= 640)
reg->CR50 |= 0x40;
else if (var->xres_virtual == 800)
reg->CR50 |= 0x80;
else if (var->xres_virtual == 1024)
reg->CR50 |= 0x00;
else if (var->xres_virtual == 1152)
reg->CR50 |= 0x01;
else if (var->xres_virtual == 1280)
reg->CR50 |= 0xc0;
else if (var->xres_virtual == 1600)
reg->CR50 |= 0x81;
else
reg->CR50 |= 0xc1; /* Use GBD */
if (par->chip == S3_SAVAGE2000)
reg->CR33 = 0x08;
else
reg->CR33 = 0x20;
reg->CRTC[0x17] = 0xeb;
reg->CR67 |= 1;
vga_out8(0x3d4, 0x36, par);
reg->CR36 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x68, par);
reg->CR68 = vga_in8(0x3d5, par);
reg->CR69 = 0;
vga_out8(0x3d4, 0x6f, par);
reg->CR6F = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x86, par);
reg->CR86 = vga_in8(0x3d5, par);
vga_out8(0x3d4, 0x88, par);
reg->CR88 = vga_in8(0x3d5, par) | 0x08;
vga_out8(0x3d4, 0xb0, par);
reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
return 0;
}
/* --------------------------------------------------------------------- */
/*
* Set a single color register. Return != 0 for invalid regno.
*/
static int savagefb_setcolreg(unsigned regno,
unsigned red,
unsigned green,
unsigned blue,
unsigned transp,
struct fb_info *info)
{
struct savagefb_par *par = info->par;
if (regno >= NR_PALETTE)
return -EINVAL;
par->palette[regno].red = red;
par->palette[regno].green = green;
par->palette[regno].blue = blue;
par->palette[regno].transp = transp;
switch (info->var.bits_per_pixel) {
case 8:
vga_out8(0x3c8, regno, par);
vga_out8(0x3c9, red >> 10, par);
vga_out8(0x3c9, green >> 10, par);
vga_out8(0x3c9, blue >> 10, par);
break;
case 16:
if (regno < 16)
((u32 *)info->pseudo_palette)[regno] =
((red & 0xf800) ) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
break;
case 24:
if (regno < 16)
((u32 *)info->pseudo_palette)[regno] =
((red & 0xff00) << 8) |
((green & 0xff00) ) |
((blue & 0xff00) >> 8);
break;
case 32:
if (regno < 16)
((u32 *)info->pseudo_palette)[regno] =
((transp & 0xff00) << 16) |
((red & 0xff00) << 8) |
((green & 0xff00) ) |
((blue & 0xff00) >> 8);
break;
default:
return 1;
}
return 0;
}
static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)
{
unsigned char tmp, cr3a, cr66, cr67;
DBG("savagefb_set_par_int");
par->SavageWaitIdle(par);
vga_out8(0x3c2, 0x23, par);
vga_out16(0x3d4, 0x4838, par);
vga_out16(0x3d4, 0xa539, par);
vga_out16(0x3c4, 0x0608, par);
vgaHWProtect(par, 1);
/*
* Some Savage/MX and /IX systems go nuts when trying to exit the
* server after WindowMaker has displayed a gradient background. I
* haven't been able to find what causes it, but a non-destructive
* switch to mode 3 here seems to eliminate the issue.
*/
VerticalRetraceWait(par);
vga_out8(0x3d4, 0x67, par);
cr67 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
vga_out8(0x3d4, 0x23, par);
vga_out8(0x3d5, 0x00, par);
vga_out8(0x3d4, 0x26, par);
vga_out8(0x3d5, 0x00, par);
/* restore extended regs */
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, reg->CR66, par);
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, reg->CR3A, par);
vga_out8(0x3d4, 0x31, par);
vga_out8(0x3d5, reg->CR31, par);
vga_out8(0x3d4, 0x32, par);
vga_out8(0x3d5, reg->CR32, par);
vga_out8(0x3d4, 0x58, par);
vga_out8(0x3d5, reg->CR58, par);
vga_out8(0x3d4, 0x53, par);
vga_out8(0x3d5, reg->CR53 & 0x7f, par);
vga_out16(0x3c4, 0x0608, par);
/* Restore DCLK registers. */
vga_out8(0x3c4, 0x0e, par);
vga_out8(0x3c5, reg->SR0E, par);
vga_out8(0x3c4, 0x0f, par);
vga_out8(0x3c5, reg->SR0F, par);
vga_out8(0x3c4, 0x29, par);
vga_out8(0x3c5, reg->SR29, par);
vga_out8(0x3c4, 0x15, par);
vga_out8(0x3c5, reg->SR15, par);
/* Restore flat panel expansion registers. */
if (par->chip == S3_SAVAGE_MX) {
int i;
for (i = 0; i < 8; i++) {
vga_out8(0x3c4, 0x54+i, par);
vga_out8(0x3c5, reg->SR54[i], par);
}
}
vgaHWRestore (par, reg);
/* extended mode timing registers */
vga_out8(0x3d4, 0x53, par);
vga_out8(0x3d5, reg->CR53, par);
vga_out8(0x3d4, 0x5d, par);
vga_out8(0x3d5, reg->CR5D, par);
vga_out8(0x3d4, 0x5e, par);
vga_out8(0x3d5, reg->CR5E, par);
vga_out8(0x3d4, 0x3b, par);
vga_out8(0x3d5, reg->CR3B, par);
vga_out8(0x3d4, 0x3c, par);
vga_out8(0x3d5, reg->CR3C, par);
vga_out8(0x3d4, 0x43, par);
vga_out8(0x3d5, reg->CR43, par);
vga_out8(0x3d4, 0x65, par);
vga_out8(0x3d5, reg->CR65, par);
/* restore the desired video mode with cr67 */
vga_out8(0x3d4, 0x67, par);
/* following part not present in X11 driver */
cr67 = vga_in8(0x3d5, par) & 0xf;
vga_out8(0x3d5, 0x50 | cr67, par);
mdelay(10);
vga_out8(0x3d4, 0x67, par);
/* end of part */
vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
/* other mode timing and extended regs */
vga_out8(0x3d4, 0x34, par);
vga_out8(0x3d5, reg->CR34, par);
vga_out8(0x3d4, 0x40, par);
vga_out8(0x3d5, reg->CR40, par);
vga_out8(0x3d4, 0x42, par);
vga_out8(0x3d5, reg->CR42, par);
vga_out8(0x3d4, 0x45, par);
vga_out8(0x3d5, reg->CR45, par);
vga_out8(0x3d4, 0x50, par);
vga_out8(0x3d5, reg->CR50, par);
vga_out8(0x3d4, 0x51, par);
vga_out8(0x3d5, reg->CR51, par);
/* memory timings */
vga_out8(0x3d4, 0x36, par);
vga_out8(0x3d5, reg->CR36, par);
vga_out8(0x3d4, 0x60, par);
vga_out8(0x3d5, reg->CR60, par);
vga_out8(0x3d4, 0x68, par);
vga_out8(0x3d5, reg->CR68, par);
vga_out8(0x3d4, 0x69, par);
vga_out8(0x3d5, reg->CR69, par);
vga_out8(0x3d4, 0x6f, par);
vga_out8(0x3d5, reg->CR6F, par);
vga_out8(0x3d4, 0x33, par);
vga_out8(0x3d5, reg->CR33, par);
vga_out8(0x3d4, 0x86, par);
vga_out8(0x3d5, reg->CR86, par);
vga_out8(0x3d4, 0x88, par);
vga_out8(0x3d5, reg->CR88, par);
vga_out8(0x3d4, 0x90, par);
vga_out8(0x3d5, reg->CR90, par);
vga_out8(0x3d4, 0x91, par);
vga_out8(0x3d5, reg->CR91, par);
if (par->chip == S3_SAVAGE4) {
vga_out8(0x3d4, 0xb0, par);
vga_out8(0x3d5, reg->CRB0, par);
}
vga_out8(0x3d4, 0x32, par);
vga_out8(0x3d5, reg->CR32, par);
/* unlock extended seq regs */
vga_out8(0x3c4, 0x08, par);
vga_out8(0x3c5, 0x06, par);
/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
* that we should leave the default SR10 and SR11 values there.
*/
if (reg->SR10 != 255) {
vga_out8(0x3c4, 0x10, par);
vga_out8(0x3c5, reg->SR10, par);
vga_out8(0x3c4, 0x11, par);
vga_out8(0x3c5, reg->SR11, par);
}
/* restore extended seq regs for dclk */
vga_out8(0x3c4, 0x0e, par);
vga_out8(0x3c5, reg->SR0E, par);
vga_out8(0x3c4, 0x0f, par);
vga_out8(0x3c5, reg->SR0F, par);
vga_out8(0x3c4, 0x12, par);
vga_out8(0x3c5, reg->SR12, par);
vga_out8(0x3c4, 0x13, par);
vga_out8(0x3c5, reg->SR13, par);
vga_out8(0x3c4, 0x29, par);
vga_out8(0x3c5, reg->SR29, par);
vga_out8(0x3c4, 0x18, par);
vga_out8(0x3c5, reg->SR18, par);
/* load new m, n pll values for dclk & mclk */
vga_out8(0x3c4, 0x15, par);
tmp = vga_in8(0x3c5, par) & ~0x21;
vga_out8(0x3c5, tmp | 0x03, par);
vga_out8(0x3c5, tmp | 0x23, par);
vga_out8(0x3c5, tmp | 0x03, par);
vga_out8(0x3c5, reg->SR15, par);
udelay(100);
vga_out8(0x3c4, 0x30, par);
vga_out8(0x3c5, reg->SR30, par);
vga_out8(0x3c4, 0x08, par);
vga_out8(0x3c5, reg->SR08, par);
/* now write out cr67 in full, possibly starting STREAMS */
VerticalRetraceWait(par);
vga_out8(0x3d4, 0x67, par);
vga_out8(0x3d5, reg->CR67, par);
vga_out8(0x3d4, 0x66, par);
cr66 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr66 | 0x80, par);
vga_out8(0x3d4, 0x3a, par);
cr3a = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr3a | 0x80, par);
if (par->chip != S3_SAVAGE_MX) {
VerticalRetraceWait(par);
savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
par->SavageWaitIdle(par);
savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
par->SavageWaitIdle(par);
savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
par->SavageWaitIdle(par);
savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
}
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, cr66, par);
vga_out8(0x3d4, 0x3a, par);
vga_out8(0x3d5, cr3a, par);
SavageSetup2DEngine(par);
vgaHWProtect(par, 0);
}
static void savagefb_update_start(struct savagefb_par *par, int base)
{
/* program the start address registers */
vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
vga_out8(0x3d4, 0x69, par);
vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
}
static void savagefb_set_fix(struct fb_info *info)
{
info->fix.line_length = info->var.xres_virtual *
info->var.bits_per_pixel / 8;
if (info->var.bits_per_pixel == 8) {
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.xpanstep = 4;
} else {
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.xpanstep = 2;
}
}
static int savagefb_set_par(struct fb_info *info)
{
struct savagefb_par *par = info->par;
struct fb_var_screeninfo *var = &info->var;
int err;
DBG("savagefb_set_par");
err = savagefb_decode_var(var, par, &par->state);
if (err)
return err;
if (par->dacSpeedBpp <= 0) {
if (var->bits_per_pixel > 24)
par->dacSpeedBpp = par->clock[3];
else if (var->bits_per_pixel >= 24)
par->dacSpeedBpp = par->clock[2];
else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
par->dacSpeedBpp = par->clock[1];
else if (var->bits_per_pixel <= 8)
par->dacSpeedBpp = par->clock[0];
}
/* Set ramdac limits */
par->maxClock = par->dacSpeedBpp;
par->minClock = 10000;
savagefb_set_par_int(par, &par->state);
fb_set_cmap(&info->cmap, info);
savagefb_set_fix(info);
savagefb_set_clip(info);
SavagePrintRegs(par);
return 0;
}
/*
* Pan or Wrap the Display
*/
static int savagefb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct savagefb_par *par = info->par;
int base;
base = (var->yoffset * info->fix.line_length
+ (var->xoffset & ~1) * ((info->var.bits_per_pixel+7) / 8)) >> 2;
savagefb_update_start(par, base);
return 0;
}
static int savagefb_blank(int blank, struct fb_info *info)
{
struct savagefb_par *par = info->par;
u8 sr8 = 0, srd = 0;
if (par->display_type == DISP_CRT) {
vga_out8(0x3c4, 0x08, par);
sr8 = vga_in8(0x3c5, par);
sr8 |= 0x06;
vga_out8(0x3c5, sr8, par);
vga_out8(0x3c4, 0x0d, par);
srd = vga_in8(0x3c5, par);
srd &= 0x50;
switch (blank) {
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
break;
case FB_BLANK_VSYNC_SUSPEND:
srd |= 0x10;
break;
case FB_BLANK_HSYNC_SUSPEND:
srd |= 0x40;
break;
case FB_BLANK_POWERDOWN:
srd |= 0x50;
break;
}
vga_out8(0x3c4, 0x0d, par);
vga_out8(0x3c5, srd, par);
}
if (par->display_type == DISP_LCD ||
par->display_type == DISP_DFP) {
switch(blank) {
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
break;
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
break;
}
}
return (blank == FB_BLANK_NORMAL) ? 1 : 0;
}
static int savagefb_open(struct fb_info *info, int user)
{
struct savagefb_par *par = info->par;
mutex_lock(&par->open_lock);
if (!par->open_count) {
memset(&par->vgastate, 0, sizeof(par->vgastate));
par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS |
VGA_SAVE_MODE;
par->vgastate.vgabase = par->mmio.vbase + 0x8000;
save_vga(&par->vgastate);
savage_get_default_par(par, &par->initial);
}
par->open_count++;
mutex_unlock(&par->open_lock);
return 0;
}
static int savagefb_release(struct fb_info *info, int user)
{
struct savagefb_par *par = info->par;
mutex_lock(&par->open_lock);
if (par->open_count == 1) {
savage_set_default_par(par, &par->initial);
restore_vga(&par->vgastate);
}
par->open_count--;
mutex_unlock(&par->open_lock);
return 0;
}
static const struct fb_ops savagefb_ops = {
.owner = THIS_MODULE,
.fb_open = savagefb_open,
.fb_release = savagefb_release,
.fb_check_var = savagefb_check_var,
.fb_set_par = savagefb_set_par,
.fb_setcolreg = savagefb_setcolreg,
.fb_pan_display = savagefb_pan_display,
.fb_blank = savagefb_blank,
#if defined(CONFIG_FB_SAVAGE_ACCEL)
.fb_fillrect = savagefb_fillrect,
.fb_copyarea = savagefb_copyarea,
.fb_imageblit = savagefb_imageblit,
.fb_sync = savagefb_sync,
#else
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
#endif
};
/* --------------------------------------------------------------------- */
static const struct fb_var_screeninfo savagefb_var800x600x8 = {
.accel_flags = FB_ACCELF_TEXT,
.xres = 800,
.yres = 600,
.xres_virtual = 800,
.yres_virtual = 600,
.bits_per_pixel = 8,
.pixclock = 25000,
.left_margin = 88,
.right_margin = 40,
.upper_margin = 23,
.lower_margin = 1,
.hsync_len = 128,
.vsync_len = 4,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static void savage_enable_mmio(struct savagefb_par *par)
{
unsigned char val;
DBG("savage_enable_mmio\n");
val = vga_in8(0x3c3, par);
vga_out8(0x3c3, val | 0x01, par);
val = vga_in8(0x3cc, par);
vga_out8(0x3c2, val | 0x01, par);
if (par->chip >= S3_SAVAGE4) {
vga_out8(0x3d4, 0x40, par);
val = vga_in8(0x3d5, par);
vga_out8(0x3d5, val | 1, par);
}
}
static void savage_disable_mmio(struct savagefb_par *par)
{
unsigned char val;
DBG("savage_disable_mmio\n");
if (par->chip >= S3_SAVAGE4) {
vga_out8(0x3d4, 0x40, par);
val = vga_in8(0x3d5, par);
vga_out8(0x3d5, val | 1, par);
}
}
static int savage_map_mmio(struct fb_info *info)
{
struct savagefb_par *par = info->par;
DBG("savage_map_mmio");
if (S3_SAVAGE3D_SERIES(par->chip))
par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
SAVAGE_NEWMMIO_REGBASE_S3;
else
par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
SAVAGE_NEWMMIO_REGBASE_S4;
par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
if (!par->mmio.vbase) {
printk("savagefb: unable to map memory mapped IO\n");
return -ENOMEM;
} else
printk(KERN_INFO "savagefb: mapped io at %p\n",
par->mmio.vbase);
info->fix.mmio_start = par->mmio.pbase;
info->fix.mmio_len = par->mmio.len;
par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
par->bci_ptr = 0;
savage_enable_mmio(par);
return 0;
}
static void savage_unmap_mmio(struct fb_info *info)
{
struct savagefb_par *par = info->par;
DBG("savage_unmap_mmio");
savage_disable_mmio(par);
if (par->mmio.vbase) {
iounmap(par->mmio.vbase);
par->mmio.vbase = NULL;
}
}
static int savage_map_video(struct fb_info *info, int video_len)
{
struct savagefb_par *par = info->par;
int resource;
DBG("savage_map_video");
if (S3_SAVAGE3D_SERIES(par->chip))
resource = 0;
else
resource = 1;
par->video.pbase = pci_resource_start(par->pcidev, resource);
par->video.len = video_len;
par->video.vbase = ioremap_wc(par->video.pbase, par->video.len);
if (!par->video.vbase) {
printk("savagefb: unable to map screen memory\n");
return -ENOMEM;
} else
printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
"pbase == %x\n", par->video.vbase, par->video.pbase);
info->fix.smem_start = par->video.pbase;
info->fix.smem_len = par->video.len - par->cob_size;
info->screen_base = par->video.vbase;
par->video.wc_cookie = arch_phys_wc_add(par->video.pbase, video_len);
/* Clear framebuffer, it's all white in memory after boot */
memset_io(par->video.vbase, 0, par->video.len);
return 0;
}
static void savage_unmap_video(struct fb_info *info)
{
struct savagefb_par *par = info->par;
DBG("savage_unmap_video");
if (par->video.vbase) {
arch_phys_wc_del(par->video.wc_cookie);
iounmap(par->video.vbase);
par->video.vbase = NULL;
info->screen_base = NULL;
}
}
static int savage_init_hw(struct savagefb_par *par)
{
unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 };
static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
int videoRam, videoRambytes, dvi;
DBG("savage_init_hw");
/* unprotect CRTC[0-7] */
vga_out8(0x3d4, 0x11, par);
tmp = vga_in8(0x3d5, par);
vga_out8(0x3d5, tmp & 0x7f, par);
/* unlock extended regs */
vga_out16(0x3d4, 0x4838, par);
vga_out16(0x3d4, 0xa039, par);
vga_out16(0x3c4, 0x0608, par);
vga_out8(0x3d4, 0x40, par);
tmp = vga_in8(0x3d5, par);
vga_out8(0x3d5, tmp & ~0x01, par);
/* unlock sys regs */
vga_out8(0x3d4, 0x38, par);
vga_out8(0x3d5, 0x48, par);
/* Unlock system registers. */
vga_out16(0x3d4, 0x4838, par);
/* Next go on to detect amount of installed ram */
vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
/* Compute the amount of video memory and offscreen memory. */
switch (par->chip) {
case S3_SAVAGE3D:
videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
break;
case S3_SAVAGE4:
/*
* The Savage4 has one ugly special case to consider. On
* systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
* when it really means 8MB. Why do it the same when you
* can do it different...
*/
vga_out8(0x3d4, 0x68, par); /* memory control 1 */
if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
RamSavage4[1] = 8;
fallthrough;
case S3_SAVAGE2000:
videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
break;
case S3_SAVAGE_MX:
case S3_SUPERSAVAGE:
videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
break;
case S3_PROSAVAGE:
case S3_PROSAVAGEDDR:
case S3_TWISTER:
videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
break;
default:
/* How did we get here? */
videoRam = 0;
break;
}
videoRambytes = videoRam * 1024;
printk(KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
/* reset graphics engine to avoid memory corruption */
vga_out8(0x3d4, 0x66, par);
cr66 = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr66 | 0x02, par);
usleep_range(10000, 11000);
vga_out8(0x3d4, 0x66, par);
vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */
usleep_range(10000, 11000);
/*
* reset memory interface, 3D engine, AGP master, PCI master,
* master engine unit, motion compensation/LPB
*/
vga_out8(0x3d4, 0x3f, par);
cr3f = vga_in8(0x3d5, par);
vga_out8(0x3d5, cr3f | 0x08, par);
usleep_range(10000, 11000);
vga_out8(0x3d4, 0x3f, par);
vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */
usleep_range(10000, 11000);
/* Savage ramdac speeds */
par->numClocks = 4;
par->clock[0] = 250000;
par->clock[1] = 250000;
par->clock[2] = 220000;
par->clock[3] = 220000;
/* detect current mclk */
vga_out8(0x3c4, 0x08, par);
sr8 = vga_in8(0x3c5, par);
vga_out8(0x3c5, 0x06, par);
vga_out8(0x3c4, 0x10, par);
n = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x11, par);
m = vga_in8(0x3c5, par);
vga_out8(0x3c4, 0x08, par);
vga_out8(0x3c5, sr8, par);
m &= 0x7f;
n1 = n & 0x1f;
n2 = (n >> 5) & 0x03;
par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
par->MCLK);
/* check for DVI/flat panel */
dvi = 0;
if (par->chip == S3_SAVAGE4) {
unsigned char sr30 = 0x00;
vga_out8(0x3c4, 0x30, par);
/* clear bit 1 */
vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
sr30 = vga_in8(0x3c5, par);
if (sr30 & 0x02 /*0x04 */) {
dvi = 1;
printk("savagefb: Digital Flat Panel Detected\n");
}
}
if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
par->display_type = DISP_LCD;
else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
par->display_type = DISP_DFP;
else
par->display_type = DISP_CRT;
/* Check LCD panel parrmation */
if (par->display_type == DISP_LCD) {
unsigned char cr6b = VGArCR(0x6b, par);
int panelX = (VGArSEQ(0x61, par) +
((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
int panelY = (VGArSEQ(0x69, par) +
((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
char * sTechnology = "Unknown";
/* OK, I admit it. I don't know how to limit the max dot clock
* for LCD panels of various sizes. I thought I copied the
* formula from the BIOS, but many users have parrmed me of
* my folly.
*
* Instead, I'll abandon any attempt to automatically limit the
* clock, and add an LCDClock option to XF86Config. Some day,
* I should come back to this.
*/
enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
ActiveCRT = 0x01,
ActiveLCD = 0x02,
ActiveTV = 0x04,
ActiveCRT2 = 0x20,
ActiveDUO = 0x80
};
if ((VGArSEQ(0x39, par) & 0x03) == 0) {
sTechnology = "TFT";
} else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
sTechnology = "DSTN";
} else {
sTechnology = "STN";
}
printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
panelX, panelY, sTechnology,
cr6b & ActiveLCD ? "and active" : "but not active");
if (cr6b & ActiveLCD) {
/*
* If the LCD is active and panel expansion is enabled,
* we probably want to kill the HW cursor.
*/
printk(KERN_INFO "savagefb: Limiting video mode to "
"%dx%d\n", panelX, panelY);
par->SavagePanelWidth = panelX;
par->SavagePanelHeight = panelY;
} else
par->display_type = DISP_CRT;
}
savage_get_default_par(par, &par->state);
par->save = par->state;
if (S3_SAVAGE4_SERIES(par->chip)) {
/*
* The Savage4 and ProSavage have COB coherency bugs which
* render the buffer useless. We disable it.
*/
par->cob_index = 2;
par->cob_size = 0x8000 << par->cob_index;
par->cob_offset = videoRambytes;
} else {
/* We use 128kB for the COB on all chips. */
par->cob_index = 7;
par->cob_size = 0x400 << par->cob_index;
par->cob_offset = videoRambytes - par->cob_size;
}
return videoRambytes;
}
static int savage_init_fb_info(struct fb_info *info, struct pci_dev *dev,
const struct pci_device_id *id)
{
struct savagefb_par *par = info->par;
int err = 0;
par->pcidev = dev;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.ypanstep = 1;
info->fix.ywrapstep = 0;
info->fix.accel = id->driver_data;
switch (info->fix.accel) {
case FB_ACCEL_SUPERSAVAGE:
par->chip = S3_SUPERSAVAGE;
snprintf(info->fix.id, 16, "SuperSavage");
break;
case FB_ACCEL_SAVAGE4:
par->chip = S3_SAVAGE4;
snprintf(info->fix.id, 16, "Savage4");
break;
case FB_ACCEL_SAVAGE3D:
par->chip = S3_SAVAGE3D;
snprintf(info->fix.id, 16, "Savage3D");
break;
case FB_ACCEL_SAVAGE3D_MV:
par->chip = S3_SAVAGE3D;
snprintf(info->fix.id, 16, "Savage3D-MV");
break;
case FB_ACCEL_SAVAGE2000:
par->chip = S3_SAVAGE2000;
snprintf(info->fix.id, 16, "Savage2000");
break;
case FB_ACCEL_SAVAGE_MX_MV:
par->chip = S3_SAVAGE_MX;
snprintf(info->fix.id, 16, "Savage/MX-MV");
break;
case FB_ACCEL_SAVAGE_MX:
par->chip = S3_SAVAGE_MX;
snprintf(info->fix.id, 16, "Savage/MX");
break;
case FB_ACCEL_SAVAGE_IX_MV:
par->chip = S3_SAVAGE_MX;
snprintf(info->fix.id, 16, "Savage/IX-MV");
break;
case FB_ACCEL_SAVAGE_IX:
par->chip = S3_SAVAGE_MX;
snprintf(info->fix.id, 16, "Savage/IX");
break;
case FB_ACCEL_PROSAVAGE_PM:
par->chip = S3_PROSAVAGE;
snprintf(info->fix.id, 16, "ProSavagePM");
break;
case FB_ACCEL_PROSAVAGE_KM:
par->chip = S3_PROSAVAGE;
snprintf(info->fix.id, 16, "ProSavageKM");
break;
case FB_ACCEL_S3TWISTER_P:
par->chip = S3_TWISTER;
snprintf(info->fix.id, 16, "TwisterP");
break;
case FB_ACCEL_S3TWISTER_K:
par->chip = S3_TWISTER;
snprintf(info->fix.id, 16, "TwisterK");
break;
case FB_ACCEL_PROSAVAGE_DDR:
par->chip = S3_PROSAVAGEDDR;
snprintf(info->fix.id, 16, "ProSavageDDR");
break;
case FB_ACCEL_PROSAVAGE_DDRK:
par->chip = S3_PROSAVAGEDDR;
snprintf(info->fix.id, 16, "ProSavage8");
break;
}
if (S3_SAVAGE3D_SERIES(par->chip)) {
par->SavageWaitIdle = savage3D_waitidle;
par->SavageWaitFifo = savage3D_waitfifo;
} else if (S3_SAVAGE4_SERIES(par->chip) ||
S3_SUPERSAVAGE == par->chip) {
par->SavageWaitIdle = savage4_waitidle;
par->SavageWaitFifo = savage4_waitfifo;
} else {
par->SavageWaitIdle = savage2000_waitidle;
par->SavageWaitFifo = savage2000_waitfifo;
}
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.width = -1;
info->var.height = -1;
info->var.accel_flags = 0;
info->fbops = &savagefb_ops;
info->flags = FBINFO_HWACCEL_YPAN |
FBINFO_HWACCEL_XPAN;
info->pseudo_palette = par->pseudo_palette;
#if defined(CONFIG_FB_SAVAGE_ACCEL)
/* FIFO size + padding for commands */
info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL);
err = -ENOMEM;
if (info->pixmap.addr) {
info->pixmap.size = 8*1024;
info->pixmap.scan_align = 4;
info->pixmap.buf_align = 4;
info->pixmap.access_align = 32;
err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
if (!err)
info->flags |= FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_IMAGEBLIT;
else
kfree(info->pixmap.addr);
}
#endif
return err;
}
/* --------------------------------------------------------------------- */
static int savagefb_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct fb_info *info;
struct savagefb_par *par;
u_int h_sync, v_sync;
unsigned char __maybe_unused *edid;
int err, lpitch;
int video_len;
DBG("savagefb_probe");
err = aperture_remove_conflicting_pci_devices(dev, "savagefb");
if (err)
return err;
info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
if (!info)
return -ENOMEM;
par = info->par;
mutex_init(&par->open_lock);
err = pci_enable_device(dev);
if (err)
goto failed_enable;
if ((err = pci_request_regions(dev, "savagefb"))) {
printk(KERN_ERR "cannot request PCI regions\n");
goto failed_enable;
}
err = -ENOMEM;
if ((err = savage_init_fb_info(info, dev, id)))
goto failed_init;
err = savage_map_mmio(info);
if (err)
goto failed_mmio;
video_len = savage_init_hw(par);
/* FIXME: can't be negative */
if (video_len < 0) {
err = video_len;
goto failed_mmio;
}
err = savage_map_video(info, video_len);
if (err)
goto failed_video;
INIT_LIST_HEAD(&info->modelist);
#if defined(CONFIG_FB_SAVAGE_I2C)
savagefb_create_i2c_busses(info);
savagefb_probe_i2c_connector(info, &edid);
fb_edid_to_monspecs(edid, &info->monspecs);
kfree(edid);
fb_videomode_to_modelist(info->monspecs.modedb,
info->monspecs.modedb_len,
&info->modelist);
#endif
info->var = savagefb_var800x600x8;
/* if a panel was detected, default to a CVT mode instead */
if (par->SavagePanelWidth) {
struct fb_videomode cvt_mode;
memset(&cvt_mode, 0, sizeof(cvt_mode));
cvt_mode.xres = par->SavagePanelWidth;
cvt_mode.yres = par->SavagePanelHeight;
cvt_mode.refresh = 60;
/* FIXME: if we know there is only the panel
* we can enable reduced blanking as well */
if (fb_find_mode_cvt(&cvt_mode, 0, 0))
printk(KERN_WARNING "No CVT mode found for panel\n");
else if (fb_find_mode(&info->var, info, NULL, NULL, 0,
&cvt_mode, 0) != 3)
info->var = savagefb_var800x600x8;
}
if (mode_option) {
fb_find_mode(&info->var, info, mode_option,
info->monspecs.modedb, info->monspecs.modedb_len,
NULL, 8);
} else if (info->monspecs.modedb != NULL) {
const struct fb_videomode *mode;
mode = fb_find_best_display(&info->monspecs, &info->modelist);
savage_update_var(&info->var, mode);
}
/* maximize virtual vertical length */
lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
info->var.yres_virtual = info->fix.smem_len/lpitch;
if (info->var.yres_virtual < info->var.yres) {
err = -ENOMEM;
goto failed;
}
#if defined(CONFIG_FB_SAVAGE_ACCEL)
/*
* The clipping coordinates are masked with 0xFFF, so limit our
* virtual resolutions to these sizes.
*/
if (info->var.yres_virtual > 0x1000)
info->var.yres_virtual = 0x1000;
if (info->var.xres_virtual > 0x1000)
info->var.xres_virtual = 0x1000;
#endif
savagefb_check_var(&info->var, info);
savagefb_set_fix(info);
/*
* Calculate the hsync and vsync frequencies. Note that
* we split the 1e12 constant up so that we can preserve
* the precision and fit the results into 32-bit registers.
* (1953125000 * 512 = 1e12)
*/
h_sync = 1953125000 / info->var.pixclock;
h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
info->var.right_margin +
info->var.hsync_len);
v_sync = h_sync / (info->var.yres + info->var.upper_margin +
info->var.lower_margin + info->var.vsync_len);
printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
"%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
info->fix.smem_len >> 10,
info->var.xres, info->var.yres,
h_sync / 1000, h_sync % 1000, v_sync);
fb_destroy_modedb(info->monspecs.modedb);
info->monspecs.modedb = NULL;
err = register_framebuffer(info);
if (err < 0)
goto failed;
printk(KERN_INFO "fb: S3 %s frame buffer device\n",
info->fix.id);
/*
* Our driver data
*/
pci_set_drvdata(dev, info);
return 0;
failed:
#ifdef CONFIG_FB_SAVAGE_I2C
savagefb_delete_i2c_busses(info);
#endif
fb_alloc_cmap(&info->cmap, 0, 0);
savage_unmap_video(info);
failed_video:
savage_unmap_mmio(info);
failed_mmio:
kfree(info->pixmap.addr);
failed_init:
pci_release_regions(dev);
failed_enable:
framebuffer_release(info);
return err;
}
static void savagefb_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
DBG("savagefb_remove");
if (info) {
unregister_framebuffer(info);
#ifdef CONFIG_FB_SAVAGE_I2C
savagefb_delete_i2c_busses(info);
#endif
fb_alloc_cmap(&info->cmap, 0, 0);
savage_unmap_video(info);
savage_unmap_mmio(info);
kfree(info->pixmap.addr);
pci_release_regions(dev);
framebuffer_release(info);
}
}
static int savagefb_suspend_late(struct device *dev, pm_message_t mesg)
{
struct fb_info *info = dev_get_drvdata(dev);
struct savagefb_par *par = info->par;
DBG("savagefb_suspend");
if (mesg.event == PM_EVENT_PRETHAW)
mesg.event = PM_EVENT_FREEZE;
par->pm_state = mesg.event;
dev->power.power_state = mesg;
/*
* For PM_EVENT_FREEZE, do not power down so the console
* can remain active.
*/
if (mesg.event == PM_EVENT_FREEZE)
return 0;
console_lock();
fb_set_suspend(info, 1);
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
savagefb_blank(FB_BLANK_POWERDOWN, info);
savage_set_default_par(par, &par->save);
savage_disable_mmio(par);
console_unlock();
return 0;
}
static int __maybe_unused savagefb_suspend(struct device *dev)
{
return savagefb_suspend_late(dev, PMSG_SUSPEND);
}
static int __maybe_unused savagefb_hibernate(struct device *dev)
{
return savagefb_suspend_late(dev, PMSG_HIBERNATE);
}
static int __maybe_unused savagefb_freeze(struct device *dev)
{
return savagefb_suspend_late(dev, PMSG_FREEZE);
}
static int __maybe_unused savagefb_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct savagefb_par *par = info->par;
int cur_state = par->pm_state;
DBG("savage_resume");
par->pm_state = PM_EVENT_ON;
/*
* The adapter was not powered down coming back from a
* PM_EVENT_FREEZE.
*/
if (cur_state == PM_EVENT_FREEZE)
return 0;
console_lock();
savage_enable_mmio(par);
savage_init_hw(par);
savagefb_set_par(info);
fb_set_suspend(info, 0);
savagefb_blank(FB_BLANK_UNBLANK, info);
console_unlock();
return 0;
}
static const struct dev_pm_ops savagefb_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = savagefb_suspend,
.resume = savagefb_resume,
.freeze = savagefb_freeze,
.thaw = savagefb_resume,
.poweroff = savagefb_hibernate,
.restore = savagefb_resume,
#endif
};
static const struct pci_device_id savagefb_devices[] = {
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
{PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
{PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
{PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
{PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
{PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
{PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
{PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
{0, 0, 0, 0, 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, savagefb_devices);
static struct pci_driver savagefb_driver = {
.name = "savagefb",
.id_table = savagefb_devices,
.probe = savagefb_probe,
.driver.pm = &savagefb_pm_ops,
.remove = savagefb_remove,
};
/* **************************** exit-time only **************************** */
static void __exit savage_done(void)
{
DBG("savage_done");
pci_unregister_driver(&savagefb_driver);
}
/* ************************* init in-kernel code ************************** */
static int __init savagefb_setup(char *options)
{
#ifndef MODULE
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
mode_option = this_opt;
}
#endif /* !MODULE */
return 0;
}
static int __init savagefb_init(void)
{
char *option;
DBG("savagefb_init");
if (fb_modesetting_disabled("savagefb"))
return -ENODEV;
if (fb_get_options("savagefb", &option))
return -ENODEV;
savagefb_setup(option);
return pci_register_driver(&savagefb_driver);
}
module_init(savagefb_init);
module_exit(savage_done);
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Specify initial video mode");
| linux-master | drivers/video/fbdev/savage/savagefb_driver.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* LCD panel support for the Palm Tungsten E
*
* Original version : Romain Goyet <[email protected]>
* Current version : Laurent Gonzalez <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include "omapfb.h"
static struct lcd_panel palmte_panel = {
.name = "palmte",
.config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC |
OMAP_LCDC_INV_HSYNC | OMAP_LCDC_HSVS_RISING_EDGE |
OMAP_LCDC_HSVS_OPPOSITE,
.data_lines = 16,
.bpp = 8,
.pixel_clock = 12000,
.x_res = 320,
.y_res = 320,
.hsw = 4,
.hfp = 8,
.hbp = 28,
.vsw = 1,
.vfp = 8,
.vbp = 7,
.pcd = 0,
};
static int palmte_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&palmte_panel);
return 0;
}
static struct platform_driver palmte_panel_driver = {
.probe = palmte_panel_probe,
.driver = {
.name = "lcd_palmte",
},
};
module_platform_driver(palmte_panel_driver);
MODULE_AUTHOR("Romain Goyet <[email protected]>, Laurent Gonzalez <[email protected]>");
MODULE_DESCRIPTION("LCD panel support for the Palm Tungsten E");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap/lcd_palmte.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Based on drivers/video/omap/lcd_inn1510.c
*
* LCD panel support for the Amstrad E3 (Delta) videophone.
*
* Copyright (C) 2006 Jonathan McDowell <[email protected]>
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/lcd.h>
#include <linux/soc/ti/omap1-io.h>
#include "omapfb.h"
#define AMS_DELTA_DEFAULT_CONTRAST 112
#define AMS_DELTA_MAX_CONTRAST 0x00FF
#define AMS_DELTA_LCD_POWER 0x0100
/* LCD class device section */
static int ams_delta_lcd;
static struct gpio_desc *gpiod_vblen;
static struct gpio_desc *gpiod_ndisp;
static int ams_delta_lcd_set_power(struct lcd_device *dev, int power)
{
if (power == FB_BLANK_UNBLANK) {
if (!(ams_delta_lcd & AMS_DELTA_LCD_POWER)) {
omap_writeb(ams_delta_lcd & AMS_DELTA_MAX_CONTRAST,
OMAP_PWL_ENABLE);
omap_writeb(1, OMAP_PWL_CLK_ENABLE);
ams_delta_lcd |= AMS_DELTA_LCD_POWER;
}
} else {
if (ams_delta_lcd & AMS_DELTA_LCD_POWER) {
omap_writeb(0, OMAP_PWL_ENABLE);
omap_writeb(0, OMAP_PWL_CLK_ENABLE);
ams_delta_lcd &= ~AMS_DELTA_LCD_POWER;
}
}
return 0;
}
static int ams_delta_lcd_set_contrast(struct lcd_device *dev, int value)
{
if ((value >= 0) && (value <= AMS_DELTA_MAX_CONTRAST)) {
omap_writeb(value, OMAP_PWL_ENABLE);
ams_delta_lcd &= ~AMS_DELTA_MAX_CONTRAST;
ams_delta_lcd |= value;
}
return 0;
}
#ifdef CONFIG_LCD_CLASS_DEVICE
static int ams_delta_lcd_get_power(struct lcd_device *dev)
{
if (ams_delta_lcd & AMS_DELTA_LCD_POWER)
return FB_BLANK_UNBLANK;
else
return FB_BLANK_POWERDOWN;
}
static int ams_delta_lcd_get_contrast(struct lcd_device *dev)
{
if (!(ams_delta_lcd & AMS_DELTA_LCD_POWER))
return 0;
return ams_delta_lcd & AMS_DELTA_MAX_CONTRAST;
}
static struct lcd_ops ams_delta_lcd_ops = {
.get_power = ams_delta_lcd_get_power,
.set_power = ams_delta_lcd_set_power,
.get_contrast = ams_delta_lcd_get_contrast,
.set_contrast = ams_delta_lcd_set_contrast,
};
#endif
/* omapfb panel section */
static int ams_delta_panel_enable(struct lcd_panel *panel)
{
gpiod_set_value(gpiod_ndisp, 1);
gpiod_set_value(gpiod_vblen, 1);
return 0;
}
static void ams_delta_panel_disable(struct lcd_panel *panel)
{
gpiod_set_value(gpiod_vblen, 0);
gpiod_set_value(gpiod_ndisp, 0);
}
static struct lcd_panel ams_delta_panel = {
.name = "ams-delta",
.config = 0,
.bpp = 12,
.data_lines = 16,
.x_res = 480,
.y_res = 320,
.pixel_clock = 4687,
.hsw = 3,
.hfp = 1,
.hbp = 1,
.vsw = 1,
.vfp = 0,
.vbp = 0,
.pcd = 0,
.acb = 37,
.enable = ams_delta_panel_enable,
.disable = ams_delta_panel_disable,
};
/* platform driver section */
static int ams_delta_panel_probe(struct platform_device *pdev)
{
struct lcd_device *lcd_device = NULL;
gpiod_vblen = devm_gpiod_get(&pdev->dev, "vblen", GPIOD_OUT_LOW);
if (IS_ERR(gpiod_vblen))
return dev_err_probe(&pdev->dev, PTR_ERR(gpiod_vblen),
"VBLEN GPIO request failed\n");
gpiod_ndisp = devm_gpiod_get(&pdev->dev, "ndisp", GPIOD_OUT_LOW);
if (IS_ERR(gpiod_ndisp))
return dev_err_probe(&pdev->dev, PTR_ERR(gpiod_ndisp),
"NDISP GPIO request failed\n");
#ifdef CONFIG_LCD_CLASS_DEVICE
lcd_device = lcd_device_register("omapfb", &pdev->dev, NULL,
&ams_delta_lcd_ops);
if (IS_ERR(lcd_device)) {
int ret = PTR_ERR(lcd_device);
dev_err(&pdev->dev, "failed to register device\n");
return ret;
}
platform_set_drvdata(pdev, lcd_device);
lcd_device->props.max_contrast = AMS_DELTA_MAX_CONTRAST;
#endif
ams_delta_lcd_set_contrast(lcd_device, AMS_DELTA_DEFAULT_CONTRAST);
ams_delta_lcd_set_power(lcd_device, FB_BLANK_UNBLANK);
omapfb_register_panel(&ams_delta_panel);
return 0;
}
static struct platform_driver ams_delta_panel_driver = {
.probe = ams_delta_panel_probe,
.driver = {
.name = "lcd_ams_delta",
},
};
module_platform_driver(ams_delta_panel_driver);
MODULE_AUTHOR("Jonathan McDowell <[email protected]>");
MODULE_DESCRIPTION("LCD panel support for the Amstrad E3 (Delta) videophone");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap/lcd_ams_delta.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Epson HWA742 LCD controller driver
*
* Copyright (C) 2004-2005 Nokia Corporation
* Authors: Juha Yrjölä <[email protected]>
* Imre Deak <[email protected]>
* YUV support: Jussi Laako <[email protected]>
*/
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include "omapfb.h"
#define HWA742_REV_CODE_REG 0x0
#define HWA742_CONFIG_REG 0x2
#define HWA742_PLL_DIV_REG 0x4
#define HWA742_PLL_0_REG 0x6
#define HWA742_PLL_1_REG 0x8
#define HWA742_PLL_2_REG 0xa
#define HWA742_PLL_3_REG 0xc
#define HWA742_PLL_4_REG 0xe
#define HWA742_CLK_SRC_REG 0x12
#define HWA742_PANEL_TYPE_REG 0x14
#define HWA742_H_DISP_REG 0x16
#define HWA742_H_NDP_REG 0x18
#define HWA742_V_DISP_1_REG 0x1a
#define HWA742_V_DISP_2_REG 0x1c
#define HWA742_V_NDP_REG 0x1e
#define HWA742_HS_W_REG 0x20
#define HWA742_HP_S_REG 0x22
#define HWA742_VS_W_REG 0x24
#define HWA742_VP_S_REG 0x26
#define HWA742_PCLK_POL_REG 0x28
#define HWA742_INPUT_MODE_REG 0x2a
#define HWA742_TRANSL_MODE_REG1 0x2e
#define HWA742_DISP_MODE_REG 0x34
#define HWA742_WINDOW_TYPE 0x36
#define HWA742_WINDOW_X_START_0 0x38
#define HWA742_WINDOW_X_START_1 0x3a
#define HWA742_WINDOW_Y_START_0 0x3c
#define HWA742_WINDOW_Y_START_1 0x3e
#define HWA742_WINDOW_X_END_0 0x40
#define HWA742_WINDOW_X_END_1 0x42
#define HWA742_WINDOW_Y_END_0 0x44
#define HWA742_WINDOW_Y_END_1 0x46
#define HWA742_MEMORY_WRITE_LSB 0x48
#define HWA742_MEMORY_WRITE_MSB 0x49
#define HWA742_MEMORY_READ_0 0x4a
#define HWA742_MEMORY_READ_1 0x4c
#define HWA742_MEMORY_READ_2 0x4e
#define HWA742_POWER_SAVE 0x56
#define HWA742_NDP_CTRL 0x58
#define HWA742_AUTO_UPDATE_TIME (HZ / 20)
/* Reserve 4 request slots for requests in irq context */
#define REQ_POOL_SIZE 24
#define IRQ_REQ_POOL_SIZE 4
#define REQ_FROM_IRQ_POOL 0x01
#define REQ_COMPLETE 0
#define REQ_PENDING 1
struct update_param {
int x, y, width, height;
int color_mode;
int flags;
};
struct hwa742_request {
struct list_head entry;
unsigned int flags;
int (*handler)(struct hwa742_request *req);
void (*complete)(void *data);
void *complete_data;
union {
struct update_param update;
struct completion *sync;
} par;
};
struct {
enum omapfb_update_mode update_mode;
enum omapfb_update_mode update_mode_before_suspend;
struct timer_list auto_update_timer;
int stop_auto_update;
struct omapfb_update_window auto_update_window;
unsigned te_connected:1;
unsigned vsync_only:1;
struct hwa742_request req_pool[REQ_POOL_SIZE];
struct list_head pending_req_list;
struct list_head free_req_list;
/*
* @req_lock: protect request slots pool and its tracking lists
* @req_sema: counter; slot allocators from task contexts must
* push it down before acquiring a slot. This
* guarantees that atomic contexts will always have
* a minimum of IRQ_REQ_POOL_SIZE slots available.
*/
struct semaphore req_sema;
spinlock_t req_lock;
struct extif_timings reg_timings, lut_timings;
int prev_color_mode;
int prev_flags;
int window_type;
u32 max_transmit_size;
u32 extif_clk_period;
unsigned long pix_tx_time;
unsigned long line_upd_time;
struct omapfb_device *fbdev;
struct lcd_ctrl_extif *extif;
const struct lcd_ctrl *int_ctrl;
struct clk *sys_ck;
} hwa742;
struct lcd_ctrl hwa742_ctrl;
static u8 hwa742_read_reg(u8 reg)
{
u8 data;
hwa742.extif->set_bits_per_cycle(8);
hwa742.extif->write_command(®, 1);
hwa742.extif->read_data(&data, 1);
return data;
}
static void hwa742_write_reg(u8 reg, u8 data)
{
hwa742.extif->set_bits_per_cycle(8);
hwa742.extif->write_command(®, 1);
hwa742.extif->write_data(&data, 1);
}
static void set_window_regs(int x_start, int y_start, int x_end, int y_end)
{
u8 tmp[8];
u8 cmd;
x_end--;
y_end--;
tmp[0] = x_start;
tmp[1] = x_start >> 8;
tmp[2] = y_start;
tmp[3] = y_start >> 8;
tmp[4] = x_end;
tmp[5] = x_end >> 8;
tmp[6] = y_end;
tmp[7] = y_end >> 8;
hwa742.extif->set_bits_per_cycle(8);
cmd = HWA742_WINDOW_X_START_0;
hwa742.extif->write_command(&cmd, 1);
hwa742.extif->write_data(tmp, 8);
}
static void set_format_regs(int conv, int transl, int flags)
{
if (flags & OMAPFB_FORMAT_FLAG_DOUBLE) {
hwa742.window_type = ((hwa742.window_type & 0xfc) | 0x01);
#ifdef VERBOSE
dev_dbg(hwa742.fbdev->dev, "hwa742: enabled pixel doubling\n");
#endif
} else {
hwa742.window_type = (hwa742.window_type & 0xfc);
#ifdef VERBOSE
dev_dbg(hwa742.fbdev->dev, "hwa742: disabled pixel doubling\n");
#endif
}
hwa742_write_reg(HWA742_INPUT_MODE_REG, conv);
hwa742_write_reg(HWA742_TRANSL_MODE_REG1, transl);
hwa742_write_reg(HWA742_WINDOW_TYPE, hwa742.window_type);
}
static void enable_tearsync(int y, int width, int height, int screen_height,
int force_vsync)
{
u8 b;
b = hwa742_read_reg(HWA742_NDP_CTRL);
b |= 1 << 2;
hwa742_write_reg(HWA742_NDP_CTRL, b);
if (likely(hwa742.vsync_only || force_vsync)) {
hwa742.extif->enable_tearsync(1, 0);
return;
}
if (width * hwa742.pix_tx_time < hwa742.line_upd_time) {
hwa742.extif->enable_tearsync(1, 0);
return;
}
if ((width * hwa742.pix_tx_time / 1000) * height <
(y + height) * (hwa742.line_upd_time / 1000)) {
hwa742.extif->enable_tearsync(1, 0);
return;
}
hwa742.extif->enable_tearsync(1, y + 1);
}
static void disable_tearsync(void)
{
u8 b;
hwa742.extif->enable_tearsync(0, 0);
b = hwa742_read_reg(HWA742_NDP_CTRL);
b &= ~(1 << 2);
hwa742_write_reg(HWA742_NDP_CTRL, b);
}
static inline struct hwa742_request *alloc_req(bool can_sleep)
{
unsigned long flags;
struct hwa742_request *req;
int req_flags = 0;
if (can_sleep)
down(&hwa742.req_sema);
else
req_flags = REQ_FROM_IRQ_POOL;
spin_lock_irqsave(&hwa742.req_lock, flags);
BUG_ON(list_empty(&hwa742.free_req_list));
req = list_entry(hwa742.free_req_list.next,
struct hwa742_request, entry);
list_del(&req->entry);
spin_unlock_irqrestore(&hwa742.req_lock, flags);
INIT_LIST_HEAD(&req->entry);
req->flags = req_flags;
return req;
}
static inline void free_req(struct hwa742_request *req)
{
unsigned long flags;
spin_lock_irqsave(&hwa742.req_lock, flags);
list_move(&req->entry, &hwa742.free_req_list);
if (!(req->flags & REQ_FROM_IRQ_POOL))
up(&hwa742.req_sema);
spin_unlock_irqrestore(&hwa742.req_lock, flags);
}
static void process_pending_requests(void)
{
unsigned long flags;
spin_lock_irqsave(&hwa742.req_lock, flags);
while (!list_empty(&hwa742.pending_req_list)) {
struct hwa742_request *req;
void (*complete)(void *);
void *complete_data;
req = list_entry(hwa742.pending_req_list.next,
struct hwa742_request, entry);
spin_unlock_irqrestore(&hwa742.req_lock, flags);
if (req->handler(req) == REQ_PENDING)
return;
complete = req->complete;
complete_data = req->complete_data;
free_req(req);
if (complete)
complete(complete_data);
spin_lock_irqsave(&hwa742.req_lock, flags);
}
spin_unlock_irqrestore(&hwa742.req_lock, flags);
}
static void submit_req_list(struct list_head *head)
{
unsigned long flags;
int process = 1;
spin_lock_irqsave(&hwa742.req_lock, flags);
if (likely(!list_empty(&hwa742.pending_req_list)))
process = 0;
list_splice_init(head, hwa742.pending_req_list.prev);
spin_unlock_irqrestore(&hwa742.req_lock, flags);
if (process)
process_pending_requests();
}
static void request_complete(void *data)
{
struct hwa742_request *req = (struct hwa742_request *)data;
void (*complete)(void *);
void *complete_data;
complete = req->complete;
complete_data = req->complete_data;
free_req(req);
if (complete)
complete(complete_data);
process_pending_requests();
}
static int send_frame_handler(struct hwa742_request *req)
{
struct update_param *par = &req->par.update;
int x = par->x;
int y = par->y;
int w = par->width;
int h = par->height;
int bpp;
int conv, transl;
unsigned long offset;
int color_mode = par->color_mode;
int flags = par->flags;
int scr_width = hwa742.fbdev->panel->x_res;
int scr_height = hwa742.fbdev->panel->y_res;
#ifdef VERBOSE
dev_dbg(hwa742.fbdev->dev, "x %d y %d w %d h %d scr_width %d "
"color_mode %d flags %d\n",
x, y, w, h, scr_width, color_mode, flags);
#endif
switch (color_mode) {
case OMAPFB_COLOR_YUV422:
bpp = 16;
conv = 0x08;
transl = 0x25;
break;
case OMAPFB_COLOR_YUV420:
bpp = 12;
conv = 0x09;
transl = 0x25;
break;
case OMAPFB_COLOR_RGB565:
bpp = 16;
conv = 0x01;
transl = 0x05;
break;
default:
return -EINVAL;
}
if (hwa742.prev_flags != flags ||
hwa742.prev_color_mode != color_mode) {
set_format_regs(conv, transl, flags);
hwa742.prev_color_mode = color_mode;
hwa742.prev_flags = flags;
}
flags = req->par.update.flags;
if (flags & OMAPFB_FORMAT_FLAG_TEARSYNC)
enable_tearsync(y, scr_width, h, scr_height,
flags & OMAPFB_FORMAT_FLAG_FORCE_VSYNC);
else
disable_tearsync();
set_window_regs(x, y, x + w, y + h);
offset = (scr_width * y + x) * bpp / 8;
hwa742.int_ctrl->setup_plane(OMAPFB_PLANE_GFX,
OMAPFB_CHANNEL_OUT_LCD, offset, scr_width, 0, 0, w, h,
color_mode);
hwa742.extif->set_bits_per_cycle(16);
hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 1);
hwa742.extif->transfer_area(w, h, request_complete, req);
return REQ_PENDING;
}
static void send_frame_complete(void *data)
{
hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 0);
}
#define ADD_PREQ(_x, _y, _w, _h, can_sleep) do {\
req = alloc_req(can_sleep); \
req->handler = send_frame_handler; \
req->complete = send_frame_complete; \
req->par.update.x = _x; \
req->par.update.y = _y; \
req->par.update.width = _w; \
req->par.update.height = _h; \
req->par.update.color_mode = color_mode;\
req->par.update.flags = flags; \
list_add_tail(&req->entry, req_head); \
} while(0)
static void create_req_list(struct omapfb_update_window *win,
struct list_head *req_head,
bool can_sleep)
{
struct hwa742_request *req;
int x = win->x;
int y = win->y;
int width = win->width;
int height = win->height;
int color_mode;
int flags;
flags = win->format & ~OMAPFB_FORMAT_MASK;
color_mode = win->format & OMAPFB_FORMAT_MASK;
if (x & 1) {
ADD_PREQ(x, y, 1, height, can_sleep);
width--;
x++;
flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
}
if (width & ~1) {
unsigned int xspan = width & ~1;
unsigned int ystart = y;
unsigned int yspan = height;
if (xspan * height * 2 > hwa742.max_transmit_size) {
yspan = hwa742.max_transmit_size / (xspan * 2);
ADD_PREQ(x, ystart, xspan, yspan, can_sleep);
ystart += yspan;
yspan = height - yspan;
flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
}
ADD_PREQ(x, ystart, xspan, yspan, can_sleep);
x += xspan;
width -= xspan;
flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
}
if (width)
ADD_PREQ(x, y, 1, height, can_sleep);
}
static void auto_update_complete(void *data)
{
if (!hwa742.stop_auto_update)
mod_timer(&hwa742.auto_update_timer,
jiffies + HWA742_AUTO_UPDATE_TIME);
}
static void __hwa742_update_window_auto(bool can_sleep)
{
LIST_HEAD(req_list);
struct hwa742_request *last;
create_req_list(&hwa742.auto_update_window, &req_list, can_sleep);
last = list_entry(req_list.prev, struct hwa742_request, entry);
last->complete = auto_update_complete;
last->complete_data = NULL;
submit_req_list(&req_list);
}
static void hwa742_update_window_auto(struct timer_list *unused)
{
__hwa742_update_window_auto(false);
}
static int hwa742_update_window_async(struct fb_info *fbi,
struct omapfb_update_window *win,
void (*complete_callback)(void *arg),
void *complete_callback_data)
{
LIST_HEAD(req_list);
struct hwa742_request *last;
int r = 0;
if (hwa742.update_mode != OMAPFB_MANUAL_UPDATE) {
dev_dbg(hwa742.fbdev->dev, "invalid update mode\n");
r = -EINVAL;
goto out;
}
if (unlikely(win->format &
~(0x03 | OMAPFB_FORMAT_FLAG_DOUBLE |
OMAPFB_FORMAT_FLAG_TEARSYNC | OMAPFB_FORMAT_FLAG_FORCE_VSYNC))) {
dev_dbg(hwa742.fbdev->dev, "invalid window flag\n");
r = -EINVAL;
goto out;
}
create_req_list(win, &req_list, true);
last = list_entry(req_list.prev, struct hwa742_request, entry);
last->complete = complete_callback;
last->complete_data = (void *)complete_callback_data;
submit_req_list(&req_list);
out:
return r;
}
static int hwa742_setup_plane(int plane, int channel_out,
unsigned long offset, int screen_width,
int pos_x, int pos_y, int width, int height,
int color_mode)
{
if (plane != OMAPFB_PLANE_GFX ||
channel_out != OMAPFB_CHANNEL_OUT_LCD)
return -EINVAL;
return 0;
}
static int hwa742_enable_plane(int plane, int enable)
{
if (plane != 0)
return -EINVAL;
hwa742.int_ctrl->enable_plane(plane, enable);
return 0;
}
static int sync_handler(struct hwa742_request *req)
{
complete(req->par.sync);
return REQ_COMPLETE;
}
static void hwa742_sync(void)
{
LIST_HEAD(req_list);
struct hwa742_request *req;
struct completion comp;
req = alloc_req(true);
req->handler = sync_handler;
req->complete = NULL;
init_completion(&comp);
req->par.sync = ∁
list_add(&req->entry, &req_list);
submit_req_list(&req_list);
wait_for_completion(&comp);
}
static void hwa742_bind_client(struct omapfb_notifier_block *nb)
{
dev_dbg(hwa742.fbdev->dev, "update_mode %d\n", hwa742.update_mode);
if (hwa742.update_mode == OMAPFB_MANUAL_UPDATE) {
omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
}
}
static int hwa742_set_update_mode(enum omapfb_update_mode mode)
{
if (mode != OMAPFB_MANUAL_UPDATE && mode != OMAPFB_AUTO_UPDATE &&
mode != OMAPFB_UPDATE_DISABLED)
return -EINVAL;
if (mode == hwa742.update_mode)
return 0;
dev_info(hwa742.fbdev->dev, "HWA742: setting update mode to %s\n",
mode == OMAPFB_UPDATE_DISABLED ? "disabled" :
(mode == OMAPFB_AUTO_UPDATE ? "auto" : "manual"));
switch (hwa742.update_mode) {
case OMAPFB_MANUAL_UPDATE:
omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_DISABLED);
break;
case OMAPFB_AUTO_UPDATE:
hwa742.stop_auto_update = 1;
del_timer_sync(&hwa742.auto_update_timer);
break;
case OMAPFB_UPDATE_DISABLED:
break;
}
hwa742.update_mode = mode;
hwa742_sync();
hwa742.stop_auto_update = 0;
switch (mode) {
case OMAPFB_MANUAL_UPDATE:
omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
break;
case OMAPFB_AUTO_UPDATE:
__hwa742_update_window_auto(true);
break;
case OMAPFB_UPDATE_DISABLED:
break;
}
return 0;
}
static enum omapfb_update_mode hwa742_get_update_mode(void)
{
return hwa742.update_mode;
}
static unsigned long round_to_extif_ticks(unsigned long ps, int div)
{
int bus_tick = hwa742.extif_clk_period * div;
return (ps + bus_tick - 1) / bus_tick * bus_tick;
}
static int calc_reg_timing(unsigned long sysclk, int div)
{
struct extif_timings *t;
unsigned long systim;
/* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
* AccessTime 2 ns + 12.2 ns (regs),
* WEOffTime = WEOnTime + 1 ns,
* REOffTime = REOnTime + 16 ns (regs),
* CSOffTime = REOffTime + 1 ns
* ReadCycle = 2ns + 2*SYSCLK (regs),
* WriteCycle = 2*SYSCLK + 2 ns,
* CSPulseWidth = 10 ns */
systim = 1000000000 / (sysclk / 1000);
dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
"extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
t = &hwa742.reg_timings;
memset(t, 0, sizeof(*t));
t->clk_div = div;
t->cs_on_time = 0;
t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
t->access_time = round_to_extif_ticks(t->re_on_time + 12200, div);
t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
t->re_off_time = round_to_extif_ticks(t->re_on_time + 16000, div);
t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
if (t->we_cycle_time < t->we_off_time)
t->we_cycle_time = t->we_off_time;
t->re_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
if (t->re_cycle_time < t->re_off_time)
t->re_cycle_time = t->re_off_time;
t->cs_pulse_width = 0;
dev_dbg(hwa742.fbdev->dev, "[reg]cson %d csoff %d reon %d reoff %d\n",
t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
dev_dbg(hwa742.fbdev->dev, "[reg]weon %d weoff %d recyc %d wecyc %d\n",
t->we_on_time, t->we_off_time, t->re_cycle_time,
t->we_cycle_time);
dev_dbg(hwa742.fbdev->dev, "[reg]rdaccess %d cspulse %d\n",
t->access_time, t->cs_pulse_width);
return hwa742.extif->convert_timings(t);
}
static int calc_lut_timing(unsigned long sysclk, int div)
{
struct extif_timings *t;
unsigned long systim;
/* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
* AccessTime 2 ns + 4 * SYSCLK + 26 (lut),
* WEOffTime = WEOnTime + 1 ns,
* REOffTime = REOnTime + 4*SYSCLK + 26 ns (lut),
* CSOffTime = REOffTime + 1 ns
* ReadCycle = 2ns + 4*SYSCLK + 26 ns (lut),
* WriteCycle = 2*SYSCLK + 2 ns,
* CSPulseWidth = 10 ns
*/
systim = 1000000000 / (sysclk / 1000);
dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
"extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
t = &hwa742.lut_timings;
memset(t, 0, sizeof(*t));
t->clk_div = div;
t->cs_on_time = 0;
t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
t->access_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
26000, div);
t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
t->re_off_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
26000, div);
t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
if (t->we_cycle_time < t->we_off_time)
t->we_cycle_time = t->we_off_time;
t->re_cycle_time = round_to_extif_ticks(2000 + 4 * systim + 26000, div);
if (t->re_cycle_time < t->re_off_time)
t->re_cycle_time = t->re_off_time;
t->cs_pulse_width = 0;
dev_dbg(hwa742.fbdev->dev, "[lut]cson %d csoff %d reon %d reoff %d\n",
t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
dev_dbg(hwa742.fbdev->dev, "[lut]weon %d weoff %d recyc %d wecyc %d\n",
t->we_on_time, t->we_off_time, t->re_cycle_time,
t->we_cycle_time);
dev_dbg(hwa742.fbdev->dev, "[lut]rdaccess %d cspulse %d\n",
t->access_time, t->cs_pulse_width);
return hwa742.extif->convert_timings(t);
}
static int calc_extif_timings(unsigned long sysclk, int *extif_mem_div)
{
int max_clk_div;
int div;
hwa742.extif->get_clk_info(&hwa742.extif_clk_period, &max_clk_div);
for (div = 1; div < max_clk_div; div++) {
if (calc_reg_timing(sysclk, div) == 0)
break;
}
if (div >= max_clk_div)
goto err;
*extif_mem_div = div;
for (div = 1; div < max_clk_div; div++) {
if (calc_lut_timing(sysclk, div) == 0)
break;
}
if (div >= max_clk_div)
goto err;
return 0;
err:
dev_err(hwa742.fbdev->dev, "can't setup timings\n");
return -1;
}
static void calc_hwa742_clk_rates(unsigned long ext_clk,
unsigned long *sys_clk, unsigned long *pix_clk)
{
int pix_clk_src;
int sys_div = 0, sys_mul = 0;
int pix_div;
pix_clk_src = hwa742_read_reg(HWA742_CLK_SRC_REG);
pix_div = ((pix_clk_src >> 3) & 0x1f) + 1;
if ((pix_clk_src & (0x3 << 1)) == 0) {
/* Source is the PLL */
sys_div = (hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x3f) + 1;
sys_mul = (hwa742_read_reg(HWA742_PLL_4_REG) & 0x7f) + 1;
*sys_clk = ext_clk * sys_mul / sys_div;
} else /* else source is ext clk, or oscillator */
*sys_clk = ext_clk;
*pix_clk = *sys_clk / pix_div; /* HZ */
dev_dbg(hwa742.fbdev->dev,
"ext_clk %ld pix_src %d pix_div %d sys_div %d sys_mul %d\n",
ext_clk, pix_clk_src & (0x3 << 1), pix_div, sys_div, sys_mul);
dev_dbg(hwa742.fbdev->dev, "sys_clk %ld pix_clk %ld\n",
*sys_clk, *pix_clk);
}
static int setup_tearsync(unsigned long pix_clk, int extif_div)
{
int hdisp, vdisp;
int hndp, vndp;
int hsw, vsw;
int hs, vs;
int hs_pol_inv, vs_pol_inv;
int use_hsvs, use_ndp;
u8 b;
hsw = hwa742_read_reg(HWA742_HS_W_REG);
vsw = hwa742_read_reg(HWA742_VS_W_REG);
hs_pol_inv = !(hsw & 0x80);
vs_pol_inv = !(vsw & 0x80);
hsw = hsw & 0x7f;
vsw = vsw & 0x3f;
hdisp = (hwa742_read_reg(HWA742_H_DISP_REG) & 0x7f) * 8;
vdisp = hwa742_read_reg(HWA742_V_DISP_1_REG) +
((hwa742_read_reg(HWA742_V_DISP_2_REG) & 0x3) << 8);
hndp = hwa742_read_reg(HWA742_H_NDP_REG) & 0x7f;
vndp = hwa742_read_reg(HWA742_V_NDP_REG);
/* time to transfer one pixel (16bpp) in ps */
hwa742.pix_tx_time = hwa742.reg_timings.we_cycle_time;
if (hwa742.extif->get_max_tx_rate != NULL) {
/*
* The external interface might have a rate limitation,
* if so, we have to maximize our transfer rate.
*/
unsigned long min_tx_time;
unsigned long max_tx_rate = hwa742.extif->get_max_tx_rate();
dev_dbg(hwa742.fbdev->dev, "max_tx_rate %ld HZ\n",
max_tx_rate);
min_tx_time = 1000000000 / (max_tx_rate / 1000); /* ps */
if (hwa742.pix_tx_time < min_tx_time)
hwa742.pix_tx_time = min_tx_time;
}
/* time to update one line in ps */
hwa742.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000);
hwa742.line_upd_time *= 1000;
if (hdisp * hwa742.pix_tx_time > hwa742.line_upd_time)
/*
* transfer speed too low, we might have to use both
* HS and VS
*/
use_hsvs = 1;
else
/* decent transfer speed, we'll always use only VS */
use_hsvs = 0;
if (use_hsvs && (hs_pol_inv || vs_pol_inv)) {
/*
* HS or'ed with VS doesn't work, use the active high
* TE signal based on HNDP / VNDP
*/
use_ndp = 1;
hs_pol_inv = 0;
vs_pol_inv = 0;
hs = hndp;
vs = vndp;
} else {
/*
* Use HS or'ed with VS as a TE signal if both are needed
* or VNDP if only vsync is needed.
*/
use_ndp = 0;
hs = hsw;
vs = vsw;
if (!use_hsvs) {
hs_pol_inv = 0;
vs_pol_inv = 0;
}
}
hs = hs * 1000000 / (pix_clk / 1000); /* ps */
hs *= 1000;
vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000); /* ps */
vs *= 1000;
if (vs <= hs)
return -EDOM;
/* set VS to 120% of HS to minimize VS detection time */
vs = hs * 12 / 10;
/* minimize HS too */
hs = 10000;
b = hwa742_read_reg(HWA742_NDP_CTRL);
b &= ~0x3;
b |= use_hsvs ? 1 : 0;
b |= (use_ndp && use_hsvs) ? 0 : 2;
hwa742_write_reg(HWA742_NDP_CTRL, b);
hwa742.vsync_only = !use_hsvs;
dev_dbg(hwa742.fbdev->dev,
"pix_clk %ld HZ pix_tx_time %ld ps line_upd_time %ld ps\n",
pix_clk, hwa742.pix_tx_time, hwa742.line_upd_time);
dev_dbg(hwa742.fbdev->dev,
"hs %d ps vs %d ps mode %d vsync_only %d\n",
hs, vs, (b & 0x3), !use_hsvs);
return hwa742.extif->setup_tearsync(1, hs, vs,
hs_pol_inv, vs_pol_inv, extif_div);
}
static void hwa742_get_caps(int plane, struct omapfb_caps *caps)
{
hwa742.int_ctrl->get_caps(plane, caps);
caps->ctrl |= OMAPFB_CAPS_MANUAL_UPDATE |
OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE;
if (hwa742.te_connected)
caps->ctrl |= OMAPFB_CAPS_TEARSYNC;
caps->wnd_color |= (1 << OMAPFB_COLOR_RGB565) |
(1 << OMAPFB_COLOR_YUV420);
}
static void hwa742_suspend(void)
{
hwa742.update_mode_before_suspend = hwa742.update_mode;
hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
/* Enable sleep mode */
hwa742_write_reg(HWA742_POWER_SAVE, 1 << 1);
clk_disable(hwa742.sys_ck);
}
static void hwa742_resume(void)
{
clk_enable(hwa742.sys_ck);
/* Disable sleep mode */
hwa742_write_reg(HWA742_POWER_SAVE, 0);
while (1) {
/* Loop until PLL output is stabilized */
if (hwa742_read_reg(HWA742_PLL_DIV_REG) & (1 << 7))
break;
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(msecs_to_jiffies(5));
}
hwa742_set_update_mode(hwa742.update_mode_before_suspend);
}
static int hwa742_init(struct omapfb_device *fbdev, int ext_mode,
struct omapfb_mem_desc *req_vram)
{
int r = 0, i;
u8 rev, conf;
unsigned long ext_clk;
unsigned long sys_clk, pix_clk;
int extif_mem_div;
struct omapfb_platform_data *omapfb_conf;
BUG_ON(!fbdev->ext_if || !fbdev->int_ctrl);
hwa742.fbdev = fbdev;
hwa742.extif = fbdev->ext_if;
hwa742.int_ctrl = fbdev->int_ctrl;
omapfb_conf = dev_get_platdata(fbdev->dev);
hwa742.sys_ck = clk_get(NULL, "hwa_sys_ck");
spin_lock_init(&hwa742.req_lock);
if ((r = hwa742.int_ctrl->init(fbdev, 1, req_vram)) < 0)
goto err1;
if ((r = hwa742.extif->init(fbdev)) < 0)
goto err2;
ext_clk = clk_get_rate(hwa742.sys_ck);
if ((r = calc_extif_timings(ext_clk, &extif_mem_div)) < 0)
goto err3;
hwa742.extif->set_timings(&hwa742.reg_timings);
clk_prepare_enable(hwa742.sys_ck);
calc_hwa742_clk_rates(ext_clk, &sys_clk, &pix_clk);
if ((r = calc_extif_timings(sys_clk, &extif_mem_div)) < 0)
goto err4;
hwa742.extif->set_timings(&hwa742.reg_timings);
rev = hwa742_read_reg(HWA742_REV_CODE_REG);
if ((rev & 0xfc) != 0x80) {
dev_err(fbdev->dev, "HWA742: invalid revision %02x\n", rev);
r = -ENODEV;
goto err4;
}
if (!(hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x80)) {
dev_err(fbdev->dev,
"HWA742: controller not initialized by the bootloader\n");
r = -ENODEV;
goto err4;
}
if ((r = setup_tearsync(pix_clk, extif_mem_div)) < 0) {
dev_err(hwa742.fbdev->dev,
"HWA742: can't setup tearing synchronization\n");
goto err4;
}
hwa742.te_connected = 1;
hwa742.max_transmit_size = hwa742.extif->max_transmit_size;
hwa742.update_mode = OMAPFB_UPDATE_DISABLED;
hwa742.auto_update_window.x = 0;
hwa742.auto_update_window.y = 0;
hwa742.auto_update_window.width = fbdev->panel->x_res;
hwa742.auto_update_window.height = fbdev->panel->y_res;
hwa742.auto_update_window.format = 0;
timer_setup(&hwa742.auto_update_timer, hwa742_update_window_auto, 0);
hwa742.prev_color_mode = -1;
hwa742.prev_flags = 0;
hwa742.fbdev = fbdev;
INIT_LIST_HEAD(&hwa742.free_req_list);
INIT_LIST_HEAD(&hwa742.pending_req_list);
for (i = 0; i < ARRAY_SIZE(hwa742.req_pool); i++)
list_add(&hwa742.req_pool[i].entry, &hwa742.free_req_list);
BUG_ON(i <= IRQ_REQ_POOL_SIZE);
sema_init(&hwa742.req_sema, i - IRQ_REQ_POOL_SIZE);
conf = hwa742_read_reg(HWA742_CONFIG_REG);
dev_info(fbdev->dev, ": Epson HWA742 LCD controller rev %d "
"initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
return 0;
err4:
clk_disable_unprepare(hwa742.sys_ck);
err3:
hwa742.extif->cleanup();
err2:
hwa742.int_ctrl->cleanup();
err1:
return r;
}
static void hwa742_cleanup(void)
{
hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
hwa742.extif->cleanup();
hwa742.int_ctrl->cleanup();
clk_disable_unprepare(hwa742.sys_ck);
}
struct lcd_ctrl hwa742_ctrl = {
.name = "hwa742",
.init = hwa742_init,
.cleanup = hwa742_cleanup,
.bind_client = hwa742_bind_client,
.get_caps = hwa742_get_caps,
.set_update_mode = hwa742_set_update_mode,
.get_update_mode = hwa742_get_update_mode,
.setup_plane = hwa742_setup_plane,
.enable_plane = hwa742_enable_plane,
.update_window = hwa742_update_window_async,
.sync = hwa742_sync,
.suspend = hwa742_suspend,
.resume = hwa742_resume,
};
| linux-master | drivers/video/fbdev/omap/hwa742.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* LCD driver for MIPI DBI-C / DCS compatible LCDs
*
* Copyright (C) 2006 Nokia Corporation
* Author: Imre Deak <[email protected]>
*/
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/platform_data/lcd-mipid.h>
#include "omapfb.h"
#define MIPID_MODULE_NAME "lcd_mipid"
#define MIPID_CMD_READ_DISP_ID 0x04
#define MIPID_CMD_READ_RED 0x06
#define MIPID_CMD_READ_GREEN 0x07
#define MIPID_CMD_READ_BLUE 0x08
#define MIPID_CMD_READ_DISP_STATUS 0x09
#define MIPID_CMD_RDDSDR 0x0F
#define MIPID_CMD_SLEEP_IN 0x10
#define MIPID_CMD_SLEEP_OUT 0x11
#define MIPID_CMD_DISP_OFF 0x28
#define MIPID_CMD_DISP_ON 0x29
#define MIPID_ESD_CHECK_PERIOD msecs_to_jiffies(5000)
#define to_mipid_device(p) container_of(p, struct mipid_device, \
panel)
struct mipid_device {
int enabled;
int revision;
unsigned int saved_bklight_level;
unsigned long hw_guard_end; /* next value of jiffies
when we can issue the
next sleep in/out command */
unsigned long hw_guard_wait; /* max guard time in jiffies */
struct gpio_desc *reset;
struct omapfb_device *fbdev;
struct spi_device *spi;
struct mutex mutex;
struct lcd_panel panel;
struct delayed_work esd_work;
void (*esd_check)(struct mipid_device *m);
};
static void mipid_transfer(struct mipid_device *md, int cmd, const u8 *wbuf,
int wlen, u8 *rbuf, int rlen)
{
struct spi_message m;
struct spi_transfer *x, xfer[4];
u16 w;
int r;
BUG_ON(md->spi == NULL);
spi_message_init(&m);
memset(xfer, 0, sizeof(xfer));
x = &xfer[0];
cmd &= 0xff;
x->tx_buf = &cmd;
x->bits_per_word = 9;
x->len = 2;
spi_message_add_tail(x, &m);
if (wlen) {
x++;
x->tx_buf = wbuf;
x->len = wlen;
x->bits_per_word = 9;
spi_message_add_tail(x, &m);
}
if (rlen) {
x++;
x->rx_buf = &w;
x->len = 1;
spi_message_add_tail(x, &m);
if (rlen > 1) {
/* Arrange for the extra clock before the first
* data bit.
*/
x->bits_per_word = 9;
x->len = 2;
x++;
x->rx_buf = &rbuf[1];
x->len = rlen - 1;
spi_message_add_tail(x, &m);
}
}
r = spi_sync(md->spi, &m);
if (r < 0)
dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
if (rlen)
rbuf[0] = w & 0xff;
}
static inline void mipid_cmd(struct mipid_device *md, int cmd)
{
mipid_transfer(md, cmd, NULL, 0, NULL, 0);
}
static inline void mipid_write(struct mipid_device *md,
int reg, const u8 *buf, int len)
{
mipid_transfer(md, reg, buf, len, NULL, 0);
}
static inline void mipid_read(struct mipid_device *md,
int reg, u8 *buf, int len)
{
mipid_transfer(md, reg, NULL, 0, buf, len);
}
static void set_data_lines(struct mipid_device *md, int data_lines)
{
u16 par;
switch (data_lines) {
case 16:
par = 0x150;
break;
case 18:
par = 0x160;
break;
case 24:
par = 0x170;
break;
}
mipid_write(md, 0x3a, (u8 *)&par, 2);
}
static void send_init_string(struct mipid_device *md)
{
u16 initpar[] = { 0x0102, 0x0100, 0x0100 };
mipid_write(md, 0xc2, (u8 *)initpar, sizeof(initpar));
set_data_lines(md, md->panel.data_lines);
}
static void hw_guard_start(struct mipid_device *md, int guard_msec)
{
md->hw_guard_wait = msecs_to_jiffies(guard_msec);
md->hw_guard_end = jiffies + md->hw_guard_wait;
}
static void hw_guard_wait(struct mipid_device *md)
{
unsigned long wait = md->hw_guard_end - jiffies;
if ((long)wait > 0 && time_before_eq(wait, md->hw_guard_wait)) {
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(wait);
}
}
static void set_sleep_mode(struct mipid_device *md, int on)
{
int cmd, sleep_time = 50;
if (on)
cmd = MIPID_CMD_SLEEP_IN;
else
cmd = MIPID_CMD_SLEEP_OUT;
hw_guard_wait(md);
mipid_cmd(md, cmd);
hw_guard_start(md, 120);
/*
* When we enable the panel, it seems we _have_ to sleep
* 120 ms before sending the init string. When disabling the
* panel we'll sleep for the duration of 2 frames, so that the
* controller can still provide the PCLK,HS,VS signals.
*/
if (!on)
sleep_time = 120;
msleep(sleep_time);
}
static void set_display_state(struct mipid_device *md, int enabled)
{
int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
mipid_cmd(md, cmd);
}
static int mipid_set_bklight_level(struct lcd_panel *panel, unsigned int level)
{
struct mipid_device *md = to_mipid_device(panel);
struct mipid_platform_data *pd = md->spi->dev.platform_data;
if (pd->get_bklight_max == NULL || pd->set_bklight_level == NULL)
return -ENODEV;
if (level > pd->get_bklight_max(pd))
return -EINVAL;
if (!md->enabled) {
md->saved_bklight_level = level;
return 0;
}
pd->set_bklight_level(pd, level);
return 0;
}
static unsigned int mipid_get_bklight_level(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
struct mipid_platform_data *pd = md->spi->dev.platform_data;
if (pd->get_bklight_level == NULL)
return -ENODEV;
return pd->get_bklight_level(pd);
}
static unsigned int mipid_get_bklight_max(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
struct mipid_platform_data *pd = md->spi->dev.platform_data;
if (pd->get_bklight_max == NULL)
return -ENODEV;
return pd->get_bklight_max(pd);
}
static unsigned long mipid_get_caps(struct lcd_panel *panel)
{
return OMAPFB_CAPS_SET_BACKLIGHT;
}
static u16 read_first_pixel(struct mipid_device *md)
{
u16 pixel;
u8 red, green, blue;
mutex_lock(&md->mutex);
mipid_read(md, MIPID_CMD_READ_RED, &red, 1);
mipid_read(md, MIPID_CMD_READ_GREEN, &green, 1);
mipid_read(md, MIPID_CMD_READ_BLUE, &blue, 1);
mutex_unlock(&md->mutex);
switch (md->panel.data_lines) {
case 16:
pixel = ((red >> 1) << 11) | (green << 5) | (blue >> 1);
break;
case 24:
/* 24 bit -> 16 bit */
pixel = ((red >> 3) << 11) | ((green >> 2) << 5) |
(blue >> 3);
break;
default:
pixel = 0;
BUG();
}
return pixel;
}
static int mipid_run_test(struct lcd_panel *panel, int test_num)
{
struct mipid_device *md = to_mipid_device(panel);
static const u16 test_values[4] = {
0x0000, 0xffff, 0xaaaa, 0x5555,
};
int i;
if (test_num != MIPID_TEST_RGB_LINES)
return MIPID_TEST_INVALID;
for (i = 0; i < ARRAY_SIZE(test_values); i++) {
int delay;
unsigned long tmo;
omapfb_write_first_pixel(md->fbdev, test_values[i]);
tmo = jiffies + msecs_to_jiffies(100);
delay = 25;
while (1) {
u16 pixel;
msleep(delay);
pixel = read_first_pixel(md);
if (pixel == test_values[i])
break;
if (time_after(jiffies, tmo)) {
dev_err(&md->spi->dev,
"MIPI LCD RGB I/F test failed: "
"expecting %04x, got %04x\n",
test_values[i], pixel);
return MIPID_TEST_FAILED;
}
delay = 10;
}
}
return 0;
}
static void ls041y3_esd_recover(struct mipid_device *md)
{
dev_err(&md->spi->dev, "performing LCD ESD recovery\n");
set_sleep_mode(md, 1);
set_sleep_mode(md, 0);
}
static void ls041y3_esd_check_mode1(struct mipid_device *md)
{
u8 state1, state2;
mipid_read(md, MIPID_CMD_RDDSDR, &state1, 1);
set_sleep_mode(md, 0);
mipid_read(md, MIPID_CMD_RDDSDR, &state2, 1);
dev_dbg(&md->spi->dev, "ESD mode 1 state1 %02x state2 %02x\n",
state1, state2);
/* Each sleep out command will trigger a self diagnostic and flip
* Bit6 if the test passes.
*/
if (!((state1 ^ state2) & (1 << 6)))
ls041y3_esd_recover(md);
}
static void ls041y3_esd_check_mode2(struct mipid_device *md)
{
int i;
u8 rbuf[2];
static const struct {
int cmd;
int wlen;
u16 wbuf[3];
} *rd, rd_ctrl[7] = {
{ 0xb0, 4, { 0x0101, 0x01fe, } },
{ 0xb1, 4, { 0x01de, 0x0121, } },
{ 0xc2, 4, { 0x0100, 0x0100, } },
{ 0xbd, 2, { 0x0100, } },
{ 0xc2, 4, { 0x01fc, 0x0103, } },
{ 0xb4, 0, },
{ 0x00, 0, },
};
rd = rd_ctrl;
for (i = 0; i < 3; i++, rd++)
mipid_write(md, rd->cmd, (u8 *)rd->wbuf, rd->wlen);
udelay(10);
mipid_read(md, rd->cmd, rbuf, 2);
rd++;
for (i = 0; i < 3; i++, rd++) {
udelay(10);
mipid_write(md, rd->cmd, (u8 *)rd->wbuf, rd->wlen);
}
dev_dbg(&md->spi->dev, "ESD mode 2 state %02x\n", rbuf[1]);
if (rbuf[1] == 0x00)
ls041y3_esd_recover(md);
}
static void ls041y3_esd_check(struct mipid_device *md)
{
ls041y3_esd_check_mode1(md);
if (md->revision >= 0x88)
ls041y3_esd_check_mode2(md);
}
static void mipid_esd_start_check(struct mipid_device *md)
{
if (md->esd_check != NULL)
schedule_delayed_work(&md->esd_work,
MIPID_ESD_CHECK_PERIOD);
}
static void mipid_esd_stop_check(struct mipid_device *md)
{
if (md->esd_check != NULL)
cancel_delayed_work_sync(&md->esd_work);
}
static void mipid_esd_work(struct work_struct *work)
{
struct mipid_device *md = container_of(work, struct mipid_device,
esd_work.work);
mutex_lock(&md->mutex);
md->esd_check(md);
mutex_unlock(&md->mutex);
mipid_esd_start_check(md);
}
static int mipid_enable(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
mutex_lock(&md->mutex);
if (md->enabled) {
mutex_unlock(&md->mutex);
return 0;
}
set_sleep_mode(md, 0);
md->enabled = 1;
send_init_string(md);
set_display_state(md, 1);
mipid_set_bklight_level(panel, md->saved_bklight_level);
mipid_esd_start_check(md);
mutex_unlock(&md->mutex);
return 0;
}
static void mipid_disable(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
/*
* A final ESD work might be called before returning,
* so do this without holding the lock.
*/
mipid_esd_stop_check(md);
mutex_lock(&md->mutex);
if (!md->enabled) {
mutex_unlock(&md->mutex);
return;
}
md->saved_bklight_level = mipid_get_bklight_level(panel);
mipid_set_bklight_level(panel, 0);
set_display_state(md, 0);
set_sleep_mode(md, 1);
md->enabled = 0;
mutex_unlock(&md->mutex);
}
static int panel_enabled(struct mipid_device *md)
{
u32 disp_status;
int enabled;
mipid_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
disp_status = __be32_to_cpu(disp_status);
enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
dev_dbg(&md->spi->dev,
"LCD panel %senabled by bootloader (status 0x%04x)\n",
enabled ? "" : "not ", disp_status);
return enabled;
}
static int mipid_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
struct mipid_device *md = to_mipid_device(panel);
md->fbdev = fbdev;
INIT_DELAYED_WORK(&md->esd_work, mipid_esd_work);
mutex_init(&md->mutex);
md->enabled = panel_enabled(md);
if (md->enabled)
mipid_esd_start_check(md);
else
md->saved_bklight_level = mipid_get_bklight_level(panel);
return 0;
}
static void mipid_cleanup(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
if (md->enabled)
mipid_esd_stop_check(md);
}
static const struct lcd_panel mipid_panel = {
.config = OMAP_LCDC_PANEL_TFT,
.bpp = 16,
.x_res = 800,
.y_res = 480,
.pixel_clock = 21940,
.hsw = 50,
.hfp = 20,
.hbp = 15,
.vsw = 2,
.vfp = 1,
.vbp = 3,
.init = mipid_init,
.cleanup = mipid_cleanup,
.enable = mipid_enable,
.disable = mipid_disable,
.get_caps = mipid_get_caps,
.set_bklight_level = mipid_set_bklight_level,
.get_bklight_level = mipid_get_bklight_level,
.get_bklight_max = mipid_get_bklight_max,
.run_test = mipid_run_test,
};
static int mipid_detect(struct mipid_device *md)
{
struct mipid_platform_data *pdata;
u8 display_id[3];
pdata = md->spi->dev.platform_data;
if (pdata == NULL) {
dev_err(&md->spi->dev, "missing platform data\n");
return -ENOENT;
}
mipid_read(md, MIPID_CMD_READ_DISP_ID, display_id, 3);
dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
display_id[0], display_id[1], display_id[2]);
switch (display_id[0]) {
case 0x45:
md->panel.name = "lph8923";
break;
case 0x83:
md->panel.name = "ls041y3";
md->esd_check = ls041y3_esd_check;
break;
default:
md->panel.name = "unknown";
dev_err(&md->spi->dev, "invalid display ID\n");
return -ENODEV;
}
md->revision = display_id[1];
md->panel.data_lines = pdata->data_lines;
pr_info("omapfb: %s rev %02x LCD detected, %d data lines\n",
md->panel.name, md->revision, md->panel.data_lines);
return 0;
}
static int mipid_spi_probe(struct spi_device *spi)
{
struct mipid_device *md;
int r;
md = kzalloc(sizeof(*md), GFP_KERNEL);
if (md == NULL) {
dev_err(&spi->dev, "out of memory\n");
return -ENOMEM;
}
/* This will de-assert RESET if active */
md->reset = gpiod_get(&spi->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(md->reset))
return dev_err_probe(&spi->dev, PTR_ERR(md->reset),
"no reset GPIO line\n");
spi->mode = SPI_MODE_0;
md->spi = spi;
dev_set_drvdata(&spi->dev, md);
md->panel = mipid_panel;
r = mipid_detect(md);
if (r < 0)
goto free_md;
omapfb_register_panel(&md->panel);
return 0;
free_md:
kfree(md);
return r;
}
static void mipid_spi_remove(struct spi_device *spi)
{
struct mipid_device *md = dev_get_drvdata(&spi->dev);
/* Asserts RESET */
gpiod_set_value(md->reset, 1);
mipid_disable(&md->panel);
kfree(md);
}
static struct spi_driver mipid_spi_driver = {
.driver = {
.name = MIPID_MODULE_NAME,
},
.probe = mipid_spi_probe,
.remove = mipid_spi_remove,
};
module_spi_driver(mipid_spi_driver);
MODULE_DESCRIPTION("MIPI display driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap/lcd_mipid.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* OMAP1 internal LCD controller
*
* Copyright (C) 2004 Nokia Corporation
* Author: Imre Deak <[email protected]>
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/dma-mapping.h>
#include <linux/vmalloc.h>
#include <linux/clk.h>
#include <linux/gfp.h>
#include <linux/soc/ti/omap1-io.h>
#include <linux/soc/ti/omap1-soc.h>
#include <linux/omap-dma.h>
#include <asm/mach-types.h>
#include "omapfb.h"
#include "lcdc.h"
#include "lcd_dma.h"
#define MODULE_NAME "lcdc"
#define MAX_PALETTE_SIZE PAGE_SIZE
enum lcdc_load_mode {
OMAP_LCDC_LOAD_PALETTE,
OMAP_LCDC_LOAD_FRAME,
OMAP_LCDC_LOAD_PALETTE_AND_FRAME
};
static struct omap_lcd_controller {
enum omapfb_update_mode update_mode;
int ext_mode;
unsigned long frame_offset;
int screen_width;
int xres;
int yres;
enum omapfb_color_format color_mode;
int bpp;
void *palette_virt;
dma_addr_t palette_phys;
int palette_code;
int palette_size;
unsigned int irq_mask;
struct completion last_frame_complete;
struct completion palette_load_complete;
struct clk *lcd_ck;
struct omapfb_device *fbdev;
void (*dma_callback)(void *data);
void *dma_callback_data;
dma_addr_t vram_phys;
void *vram_virt;
unsigned long vram_size;
} lcdc;
static inline void enable_irqs(int mask)
{
lcdc.irq_mask |= mask;
}
static inline void disable_irqs(int mask)
{
lcdc.irq_mask &= ~mask;
}
static void set_load_mode(enum lcdc_load_mode mode)
{
u32 l;
l = omap_readl(OMAP_LCDC_CONTROL);
l &= ~(3 << 20);
switch (mode) {
case OMAP_LCDC_LOAD_PALETTE:
l |= 1 << 20;
break;
case OMAP_LCDC_LOAD_FRAME:
l |= 2 << 20;
break;
case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
break;
default:
BUG();
}
omap_writel(l, OMAP_LCDC_CONTROL);
}
static void enable_controller(void)
{
u32 l;
l = omap_readl(OMAP_LCDC_CONTROL);
l |= OMAP_LCDC_CTRL_LCD_EN;
l &= ~OMAP_LCDC_IRQ_MASK;
l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */
omap_writel(l, OMAP_LCDC_CONTROL);
}
static void disable_controller_async(void)
{
u32 l;
u32 mask;
l = omap_readl(OMAP_LCDC_CONTROL);
mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
/*
* Preserve the DONE mask, since we still want to get the
* final DONE irq. It will be disabled in the IRQ handler.
*/
mask &= ~OMAP_LCDC_IRQ_DONE;
l &= ~mask;
omap_writel(l, OMAP_LCDC_CONTROL);
}
static void disable_controller(void)
{
init_completion(&lcdc.last_frame_complete);
disable_controller_async();
if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
msecs_to_jiffies(500)))
dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
}
static void reset_controller(u32 status)
{
static unsigned long reset_count;
static unsigned long last_jiffies;
disable_controller_async();
reset_count++;
if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
dev_err(lcdc.fbdev->dev,
"resetting (status %#010x,reset count %lu)\n",
status, reset_count);
last_jiffies = jiffies;
}
if (reset_count < 100) {
enable_controller();
} else {
reset_count = 0;
dev_err(lcdc.fbdev->dev,
"too many reset attempts, giving up.\n");
}
}
/*
* Configure the LCD DMA according to the current mode specified by parameters
* in lcdc.fbdev and fbdev->var.
*/
static void setup_lcd_dma(void)
{
static const int dma_elem_type[] = {
0,
OMAP_DMA_DATA_TYPE_S8,
OMAP_DMA_DATA_TYPE_S16,
0,
OMAP_DMA_DATA_TYPE_S32,
};
struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
unsigned long src;
int esize, xelem, yelem;
src = lcdc.vram_phys + lcdc.frame_offset;
switch (var->rotate) {
case 0:
if (plane->info.mirror || (src & 3) ||
lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
(lcdc.xres & 1))
esize = 2;
else
esize = 4;
xelem = lcdc.xres * lcdc.bpp / 8 / esize;
yelem = lcdc.yres;
break;
case 90:
case 180:
case 270:
if (cpu_is_omap15xx()) {
BUG();
}
esize = 2;
xelem = lcdc.yres * lcdc.bpp / 16;
yelem = lcdc.xres;
break;
default:
BUG();
return;
}
#ifdef VERBOSE
dev_dbg(lcdc.fbdev->dev,
"setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
src, esize, xelem, yelem);
#endif
omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
if (!cpu_is_omap15xx()) {
int bpp = lcdc.bpp;
/*
* YUV support is only for external mode when we have the
* YUV window embedded in a 16bpp frame buffer.
*/
if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
bpp = 16;
/* Set virtual xres elem size */
omap_set_lcd_dma_b1_vxres(
lcdc.screen_width * bpp / 8 / esize);
/* Setup transformations */
omap_set_lcd_dma_b1_rotation(var->rotate);
omap_set_lcd_dma_b1_mirror(plane->info.mirror);
}
omap_setup_lcd_dma();
}
static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
{
u32 status;
status = omap_readl(OMAP_LCDC_STATUS);
if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
reset_controller(status);
else {
if (status & OMAP_LCDC_STAT_DONE) {
u32 l;
/*
* Disable IRQ_DONE. The status bit will be cleared
* only when the controller is reenabled and we don't
* want to get more interrupts.
*/
l = omap_readl(OMAP_LCDC_CONTROL);
l &= ~OMAP_LCDC_IRQ_DONE;
omap_writel(l, OMAP_LCDC_CONTROL);
complete(&lcdc.last_frame_complete);
}
if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
disable_controller_async();
complete(&lcdc.palette_load_complete);
}
}
/*
* Clear these interrupt status bits.
* Sync_lost, FUF bits were cleared by disabling the LCD controller
* LOADED_PALETTE can be cleared this way only in palette only
* load mode. In other load modes it's cleared by disabling the
* controller.
*/
status &= ~(OMAP_LCDC_STAT_VSYNC |
OMAP_LCDC_STAT_LOADED_PALETTE |
OMAP_LCDC_STAT_ABC |
OMAP_LCDC_STAT_LINE_INT);
omap_writel(status, OMAP_LCDC_STATUS);
return IRQ_HANDLED;
}
/*
* Change to a new video mode. We defer this to a later time to avoid any
* flicker and not to mess up the current LCD DMA context. For this we disable
* the LCD controller, which will generate a DONE irq after the last frame has
* been transferred. Then it'll be safe to reconfigure both the LCD controller
* as well as the LCD DMA.
*/
static int omap_lcdc_setup_plane(int plane, int channel_out,
unsigned long offset, int screen_width,
int pos_x, int pos_y, int width, int height,
int color_mode)
{
struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
struct lcd_panel *panel = lcdc.fbdev->panel;
int rot_x, rot_y;
if (var->rotate == 0) {
rot_x = panel->x_res;
rot_y = panel->y_res;
} else {
rot_x = panel->y_res;
rot_y = panel->x_res;
}
if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
width > rot_x || height > rot_y) {
#ifdef VERBOSE
dev_dbg(lcdc.fbdev->dev,
"invalid plane params plane %d pos_x %d pos_y %d "
"w %d h %d\n", plane, pos_x, pos_y, width, height);
#endif
return -EINVAL;
}
lcdc.frame_offset = offset;
lcdc.xres = width;
lcdc.yres = height;
lcdc.screen_width = screen_width;
lcdc.color_mode = color_mode;
switch (color_mode) {
case OMAPFB_COLOR_CLUT_8BPP:
lcdc.bpp = 8;
lcdc.palette_code = 0x3000;
lcdc.palette_size = 512;
break;
case OMAPFB_COLOR_RGB565:
lcdc.bpp = 16;
lcdc.palette_code = 0x4000;
lcdc.palette_size = 32;
break;
case OMAPFB_COLOR_RGB444:
lcdc.bpp = 16;
lcdc.palette_code = 0x4000;
lcdc.palette_size = 32;
break;
case OMAPFB_COLOR_YUV420:
if (lcdc.ext_mode) {
lcdc.bpp = 12;
break;
}
fallthrough;
case OMAPFB_COLOR_YUV422:
if (lcdc.ext_mode) {
lcdc.bpp = 16;
break;
}
fallthrough;
default:
/* FIXME: other BPPs.
* bpp1: code 0, size 256
* bpp2: code 0x1000 size 256
* bpp4: code 0x2000 size 256
* bpp12: code 0x4000 size 32
*/
dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
BUG();
return -1;
}
if (lcdc.ext_mode) {
setup_lcd_dma();
return 0;
}
if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
disable_controller();
omap_stop_lcd_dma();
setup_lcd_dma();
enable_controller();
}
return 0;
}
static int omap_lcdc_enable_plane(int plane, int enable)
{
dev_dbg(lcdc.fbdev->dev,
"plane %d enable %d update_mode %d ext_mode %d\n",
plane, enable, lcdc.update_mode, lcdc.ext_mode);
if (plane != OMAPFB_PLANE_GFX)
return -EINVAL;
return 0;
}
/*
* Configure the LCD DMA for a palette load operation and do the palette
* downloading synchronously. We don't use the frame+palette load mode of
* the controller, since the palette can always be downloaded separately.
*/
static void load_palette(void)
{
u16 *palette;
palette = (u16 *)lcdc.palette_virt;
*(u16 *)palette &= 0x0fff;
*(u16 *)palette |= lcdc.palette_code;
omap_set_lcd_dma_b1(lcdc.palette_phys,
lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
omap_set_lcd_dma_single_transfer(1);
omap_setup_lcd_dma();
init_completion(&lcdc.palette_load_complete);
enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
set_load_mode(OMAP_LCDC_LOAD_PALETTE);
enable_controller();
if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
msecs_to_jiffies(500)))
dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
/* The controller gets disabled in the irq handler */
disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
omap_stop_lcd_dma();
omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
}
/* Used only in internal controller mode */
static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
u16 transp, int update_hw_pal)
{
u16 *palette;
if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
return -EINVAL;
palette = (u16 *)lcdc.palette_virt;
palette[regno] &= ~0x0fff;
palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
(blue >> 12);
if (update_hw_pal) {
disable_controller();
omap_stop_lcd_dma();
load_palette();
setup_lcd_dma();
set_load_mode(OMAP_LCDC_LOAD_FRAME);
enable_controller();
}
return 0;
}
static void calc_ck_div(int is_tft, int pck, int *pck_div)
{
unsigned long lck;
pck = max(1, pck);
lck = clk_get_rate(lcdc.lcd_ck);
*pck_div = (lck + pck - 1) / pck;
if (is_tft)
*pck_div = max(2, *pck_div);
else
*pck_div = max(3, *pck_div);
if (*pck_div > 255) {
/* FIXME: try to adjust logic clock divider as well */
*pck_div = 255;
dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
pck / 1000);
}
}
static inline void setup_regs(void)
{
u32 l;
struct lcd_panel *panel = lcdc.fbdev->panel;
int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
unsigned long lck;
int pcd;
l = omap_readl(OMAP_LCDC_CONTROL);
l &= ~OMAP_LCDC_CTRL_LCD_TFT;
l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
#ifdef CONFIG_MACH_OMAP_PALMTE
/* FIXME:if (machine_is_omap_palmte()) { */
/* PalmTE uses alternate TFT setting in 8BPP mode */
l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
/* } */
#endif
omap_writel(l, OMAP_LCDC_CONTROL);
l = omap_readl(OMAP_LCDC_TIMING2);
l &= ~(((1 << 6) - 1) << 20);
l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
omap_writel(l, OMAP_LCDC_TIMING2);
l = panel->x_res - 1;
l |= (panel->hsw - 1) << 10;
l |= (panel->hfp - 1) << 16;
l |= (panel->hbp - 1) << 24;
omap_writel(l, OMAP_LCDC_TIMING0);
l = panel->y_res - 1;
l |= (panel->vsw - 1) << 10;
l |= panel->vfp << 16;
l |= panel->vbp << 24;
omap_writel(l, OMAP_LCDC_TIMING1);
l = omap_readl(OMAP_LCDC_TIMING2);
l &= ~0xff;
lck = clk_get_rate(lcdc.lcd_ck);
if (!panel->pcd)
calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
else {
dev_warn(lcdc.fbdev->dev,
"Pixel clock divider value is obsolete.\n"
"Try to set pixel_clock to %lu and pcd to 0 "
"in drivers/video/omap/lcd_%s.c and submit a patch.\n",
lck / panel->pcd / 1000, panel->name);
pcd = panel->pcd;
}
l |= pcd & 0xff;
l |= panel->acb << 8;
omap_writel(l, OMAP_LCDC_TIMING2);
/* update panel info with the exact clock */
panel->pixel_clock = lck / pcd / 1000;
}
/*
* Configure the LCD controller, download the color palette and start a looped
* DMA transfer of the frame image data. Called only in internal
* controller mode.
*/
static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
{
int r = 0;
if (mode != lcdc.update_mode) {
switch (mode) {
case OMAPFB_AUTO_UPDATE:
setup_regs();
load_palette();
/* Setup and start LCD DMA */
setup_lcd_dma();
set_load_mode(OMAP_LCDC_LOAD_FRAME);
enable_irqs(OMAP_LCDC_IRQ_DONE);
/* This will start the actual DMA transfer */
enable_controller();
lcdc.update_mode = mode;
break;
case OMAPFB_UPDATE_DISABLED:
disable_controller();
omap_stop_lcd_dma();
lcdc.update_mode = mode;
break;
default:
r = -EINVAL;
}
}
return r;
}
static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
{
return lcdc.update_mode;
}
/* PM code called only in internal controller mode */
static void omap_lcdc_suspend(void)
{
omap_lcdc_set_update_mode(OMAPFB_UPDATE_DISABLED);
}
static void omap_lcdc_resume(void)
{
omap_lcdc_set_update_mode(OMAPFB_AUTO_UPDATE);
}
static void omap_lcdc_get_caps(int plane, struct omapfb_caps *caps)
{
return;
}
int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
{
BUG_ON(callback == NULL);
if (lcdc.dma_callback)
return -EBUSY;
else {
lcdc.dma_callback = callback;
lcdc.dma_callback_data = data;
}
return 0;
}
EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
void omap_lcdc_free_dma_callback(void)
{
lcdc.dma_callback = NULL;
}
EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
static void lcdc_dma_handler(u16 status, void *data)
{
if (lcdc.dma_callback)
lcdc.dma_callback(lcdc.dma_callback_data);
}
static int alloc_palette_ram(void)
{
lcdc.palette_virt = dma_alloc_wc(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
&lcdc.palette_phys, GFP_KERNEL);
if (lcdc.palette_virt == NULL) {
dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
return -ENOMEM;
}
memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
return 0;
}
static void free_palette_ram(void)
{
dma_free_wc(lcdc.fbdev->dev, MAX_PALETTE_SIZE, lcdc.palette_virt,
lcdc.palette_phys);
}
static int alloc_fbmem(struct omapfb_mem_region *region)
{
int bpp;
int frame_size;
struct lcd_panel *panel = lcdc.fbdev->panel;
bpp = panel->bpp;
if (bpp == 12)
bpp = 16;
frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
if (region->size > frame_size)
frame_size = region->size;
lcdc.vram_size = frame_size;
lcdc.vram_virt = dma_alloc_wc(lcdc.fbdev->dev, lcdc.vram_size,
&lcdc.vram_phys, GFP_KERNEL);
if (lcdc.vram_virt == NULL) {
dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
return -ENOMEM;
}
region->size = frame_size;
region->paddr = lcdc.vram_phys;
region->vaddr = lcdc.vram_virt;
region->alloc = 1;
memset(lcdc.vram_virt, 0, lcdc.vram_size);
return 0;
}
static void free_fbmem(void)
{
dma_free_wc(lcdc.fbdev->dev, lcdc.vram_size, lcdc.vram_virt,
lcdc.vram_phys);
}
static int setup_fbmem(struct omapfb_mem_desc *req_md)
{
if (!req_md->region_cnt) {
dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
return -EINVAL;
}
if (req_md->region_cnt > 1) {
dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
req_md->region_cnt = 1;
}
return alloc_fbmem(&req_md->region[0]);
}
static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
struct omapfb_mem_desc *req_vram)
{
int r;
u32 l;
int rate;
struct clk *tc_ck;
lcdc.irq_mask = 0;
lcdc.fbdev = fbdev;
lcdc.ext_mode = ext_mode;
l = 0;
omap_writel(l, OMAP_LCDC_CONTROL);
/* FIXME:
* According to errata some platforms have a clock rate limitiation
*/
lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck");
if (IS_ERR(lcdc.lcd_ck)) {
dev_err(fbdev->dev, "unable to access LCD clock\n");
r = PTR_ERR(lcdc.lcd_ck);
goto fail0;
}
tc_ck = clk_get(fbdev->dev, "tc_ck");
if (IS_ERR(tc_ck)) {
dev_err(fbdev->dev, "unable to access TC clock\n");
r = PTR_ERR(tc_ck);
goto fail1;
}
rate = clk_get_rate(tc_ck);
clk_put(tc_ck);
if (machine_is_ams_delta())
rate /= 4;
r = clk_set_rate(lcdc.lcd_ck, rate);
if (r) {
dev_err(fbdev->dev, "failed to adjust LCD rate\n");
goto fail1;
}
clk_prepare_enable(lcdc.lcd_ck);
r = request_irq(fbdev->int_irq, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
if (r) {
dev_err(fbdev->dev, "unable to get IRQ\n");
goto fail2;
}
r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
if (r) {
dev_err(fbdev->dev, "unable to get LCD DMA\n");
goto fail3;
}
omap_set_lcd_dma_single_transfer(ext_mode);
omap_set_lcd_dma_ext_controller(ext_mode);
if (!ext_mode)
if ((r = alloc_palette_ram()) < 0)
goto fail4;
if ((r = setup_fbmem(req_vram)) < 0)
goto fail5;
pr_info("omapfb: LCDC initialized\n");
return 0;
fail5:
if (!ext_mode)
free_palette_ram();
fail4:
omap_free_lcd_dma();
fail3:
free_irq(fbdev->int_irq, lcdc.fbdev);
fail2:
clk_disable_unprepare(lcdc.lcd_ck);
fail1:
clk_put(lcdc.lcd_ck);
fail0:
return r;
}
static void omap_lcdc_cleanup(void)
{
if (!lcdc.ext_mode)
free_palette_ram();
free_fbmem();
omap_free_lcd_dma();
free_irq(lcdc.fbdev->int_irq, lcdc.fbdev);
clk_disable_unprepare(lcdc.lcd_ck);
clk_put(lcdc.lcd_ck);
}
const struct lcd_ctrl omap1_int_ctrl = {
.name = "internal",
.init = omap_lcdc_init,
.cleanup = omap_lcdc_cleanup,
.get_caps = omap_lcdc_get_caps,
.set_update_mode = omap_lcdc_set_update_mode,
.get_update_mode = omap_lcdc_get_update_mode,
.update_window = NULL,
.suspend = omap_lcdc_suspend,
.resume = omap_lcdc_resume,
.setup_plane = omap_lcdc_setup_plane,
.enable_plane = omap_lcdc_enable_plane,
.setcolreg = omap_lcdc_setcolreg,
};
| linux-master | drivers/video/fbdev/omap/lcdc.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Framebuffer driver for TI OMAP boards
*
* Copyright (C) 2004 Nokia Corporation
* Author: Imre Deak <[email protected]>
*
* Acknowledgements:
* Alex McMains <[email protected]> - Original driver
* Juha Yrjola <[email protected]> - Original driver and improvements
* Dirk Behme <[email protected]> - changes for 2.6 kernel API
* Texas Instruments - H3 support
*/
#include <linux/platform_device.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/module.h>
#include <linux/sysfs.h>
#include <linux/omap-dma.h>
#include <linux/soc/ti/omap1-soc.h>
#include "omapfb.h"
#include "lcdc.h"
#define MODULE_NAME "omapfb"
static unsigned int def_accel;
static unsigned long def_vram[OMAPFB_PLANE_NUM];
static unsigned int def_vram_cnt;
static unsigned long def_vxres;
static unsigned long def_vyres;
static unsigned int def_rotate;
static unsigned int def_mirror;
static bool manual_update = IS_BUILTIN(CONFIG_FB_OMAP_MANUAL_UPDATE);
static struct platform_device *fbdev_pdev;
static struct lcd_panel *fbdev_panel;
static struct omapfb_device *omapfb_dev;
struct caps_table_struct {
unsigned long flag;
const char *name;
};
static const struct caps_table_struct ctrl_caps[] = {
{ OMAPFB_CAPS_MANUAL_UPDATE, "manual update" },
{ OMAPFB_CAPS_TEARSYNC, "tearing synchronization" },
{ OMAPFB_CAPS_PLANE_RELOCATE_MEM, "relocate plane memory" },
{ OMAPFB_CAPS_PLANE_SCALE, "scale plane" },
{ OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE, "pixel double window" },
{ OMAPFB_CAPS_WINDOW_SCALE, "scale window" },
{ OMAPFB_CAPS_WINDOW_OVERLAY, "overlay window" },
{ OMAPFB_CAPS_WINDOW_ROTATE, "rotate window" },
{ OMAPFB_CAPS_SET_BACKLIGHT, "backlight setting" },
};
static const struct caps_table_struct color_caps[] = {
{ 1 << OMAPFB_COLOR_RGB565, "RGB565", },
{ 1 << OMAPFB_COLOR_YUV422, "YUV422", },
{ 1 << OMAPFB_COLOR_YUV420, "YUV420", },
{ 1 << OMAPFB_COLOR_CLUT_8BPP, "CLUT8", },
{ 1 << OMAPFB_COLOR_CLUT_4BPP, "CLUT4", },
{ 1 << OMAPFB_COLOR_CLUT_2BPP, "CLUT2", },
{ 1 << OMAPFB_COLOR_CLUT_1BPP, "CLUT1", },
{ 1 << OMAPFB_COLOR_RGB444, "RGB444", },
{ 1 << OMAPFB_COLOR_YUY422, "YUY422", },
};
static void omapdss_release(struct device *dev)
{
}
/* dummy device for clocks */
static struct platform_device omapdss_device = {
.name = "omapdss_dss",
.id = -1,
.dev = {
.release = omapdss_release,
},
};
/*
* ---------------------------------------------------------------------------
* LCD panel
* ---------------------------------------------------------------------------
*/
extern struct lcd_ctrl hwa742_ctrl;
static const struct lcd_ctrl *ctrls[] = {
&omap1_int_ctrl,
#ifdef CONFIG_FB_OMAP_LCDC_HWA742
&hwa742_ctrl,
#endif
};
#ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
extern struct lcd_ctrl_extif omap1_ext_if;
#endif
static void omapfb_rqueue_lock(struct omapfb_device *fbdev)
{
mutex_lock(&fbdev->rqueue_mutex);
}
static void omapfb_rqueue_unlock(struct omapfb_device *fbdev)
{
mutex_unlock(&fbdev->rqueue_mutex);
}
/*
* ---------------------------------------------------------------------------
* LCD controller and LCD DMA
* ---------------------------------------------------------------------------
*/
/*
* Allocate resources needed for LCD controller and LCD DMA operations. Video
* memory is allocated from system memory according to the virtual display
* size, except if a bigger memory size is specified explicitly as a kernel
* parameter.
*/
static int ctrl_init(struct omapfb_device *fbdev)
{
int r;
int i;
/* kernel/module vram parameters override boot tags/board config */
if (def_vram_cnt) {
for (i = 0; i < def_vram_cnt; i++)
fbdev->mem_desc.region[i].size =
PAGE_ALIGN(def_vram[i]);
fbdev->mem_desc.region_cnt = i;
}
if (!fbdev->mem_desc.region_cnt) {
struct lcd_panel *panel = fbdev->panel;
int def_size;
int bpp = panel->bpp;
/* 12 bpp is packed in 16 bits */
if (bpp == 12)
bpp = 16;
def_size = def_vxres * def_vyres * bpp / 8;
fbdev->mem_desc.region_cnt = 1;
fbdev->mem_desc.region[0].size = PAGE_ALIGN(def_size);
}
r = fbdev->ctrl->init(fbdev, 0, &fbdev->mem_desc);
if (r < 0) {
dev_err(fbdev->dev, "controller initialization failed (%d)\n",
r);
return r;
}
#ifdef DEBUG
for (i = 0; i < fbdev->mem_desc.region_cnt; i++) {
dev_dbg(fbdev->dev, "region%d phys %08x virt %p size=%lu\n",
i,
fbdev->mem_desc.region[i].paddr,
fbdev->mem_desc.region[i].vaddr,
fbdev->mem_desc.region[i].size);
}
#endif
return 0;
}
static void ctrl_cleanup(struct omapfb_device *fbdev)
{
fbdev->ctrl->cleanup();
}
/* Must be called with fbdev->rqueue_mutex held. */
static int ctrl_change_mode(struct fb_info *fbi)
{
int r;
unsigned long offset;
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
struct fb_var_screeninfo *var = &fbi->var;
offset = var->yoffset * fbi->fix.line_length +
var->xoffset * var->bits_per_pixel / 8;
if (fbdev->ctrl->sync)
fbdev->ctrl->sync();
r = fbdev->ctrl->setup_plane(plane->idx, plane->info.channel_out,
offset, var->xres_virtual,
plane->info.pos_x, plane->info.pos_y,
var->xres, var->yres, plane->color_mode);
if (r < 0)
return r;
if (fbdev->ctrl->set_rotate != NULL) {
r = fbdev->ctrl->set_rotate(var->rotate);
if (r < 0)
return r;
}
if (fbdev->ctrl->set_scale != NULL)
r = fbdev->ctrl->set_scale(plane->idx,
var->xres, var->yres,
plane->info.out_width,
plane->info.out_height);
return r;
}
/*
* ---------------------------------------------------------------------------
* fbdev framework callbacks and the ioctl interface
* ---------------------------------------------------------------------------
*/
/* Called each time the omapfb device is opened */
static int omapfb_open(struct fb_info *info, int user)
{
return 0;
}
static void omapfb_sync(struct fb_info *info);
/* Called when the omapfb device is closed. We make sure that any pending
* gfx DMA operations are ended, before we return. */
static int omapfb_release(struct fb_info *info, int user)
{
omapfb_sync(info);
return 0;
}
/* Store a single color palette entry into a pseudo palette or the hardware
* palette if one is available. For now we support only 16bpp and thus store
* the entry only to the pseudo palette.
*/
static int _setcolreg(struct fb_info *info, u_int regno, u_int red, u_int green,
u_int blue, u_int transp, int update_hw_pal)
{
struct omapfb_plane_struct *plane = info->par;
struct omapfb_device *fbdev = plane->fbdev;
struct fb_var_screeninfo *var = &info->var;
int r = 0;
switch (plane->color_mode) {
case OMAPFB_COLOR_YUV422:
case OMAPFB_COLOR_YUV420:
case OMAPFB_COLOR_YUY422:
r = -EINVAL;
break;
case OMAPFB_COLOR_CLUT_8BPP:
case OMAPFB_COLOR_CLUT_4BPP:
case OMAPFB_COLOR_CLUT_2BPP:
case OMAPFB_COLOR_CLUT_1BPP:
if (fbdev->ctrl->setcolreg)
r = fbdev->ctrl->setcolreg(regno, red, green, blue,
transp, update_hw_pal);
fallthrough;
case OMAPFB_COLOR_RGB565:
case OMAPFB_COLOR_RGB444:
if (r != 0)
break;
if (regno < 16) {
u16 pal;
pal = ((red >> (16 - var->red.length)) <<
var->red.offset) |
((green >> (16 - var->green.length)) <<
var->green.offset) |
(blue >> (16 - var->blue.length));
((u32 *)(info->pseudo_palette))[regno] = pal;
}
break;
default:
BUG();
}
return r;
}
static int omapfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
return _setcolreg(info, regno, red, green, blue, transp, 1);
}
static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
{
int count, index, r;
u16 *red, *green, *blue, *transp;
u16 trans = 0xffff;
red = cmap->red;
green = cmap->green;
blue = cmap->blue;
transp = cmap->transp;
index = cmap->start;
for (count = 0; count < cmap->len; count++) {
if (transp)
trans = *transp++;
r = _setcolreg(info, index++, *red++, *green++, *blue++, trans,
count == cmap->len - 1);
if (r != 0)
return r;
}
return 0;
}
static int omapfb_update_full_screen(struct fb_info *fbi);
static int omapfb_blank(int blank, struct fb_info *fbi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
int do_update = 0;
int r = 0;
omapfb_rqueue_lock(fbdev);
switch (blank) {
case FB_BLANK_UNBLANK:
if (fbdev->state == OMAPFB_SUSPENDED) {
if (fbdev->ctrl->resume)
fbdev->ctrl->resume();
if (fbdev->panel->enable)
fbdev->panel->enable(fbdev->panel);
fbdev->state = OMAPFB_ACTIVE;
if (fbdev->ctrl->get_update_mode() ==
OMAPFB_MANUAL_UPDATE)
do_update = 1;
}
break;
case FB_BLANK_POWERDOWN:
if (fbdev->state == OMAPFB_ACTIVE) {
if (fbdev->panel->disable)
fbdev->panel->disable(fbdev->panel);
if (fbdev->ctrl->suspend)
fbdev->ctrl->suspend();
fbdev->state = OMAPFB_SUSPENDED;
}
break;
default:
r = -EINVAL;
}
omapfb_rqueue_unlock(fbdev);
if (r == 0 && do_update)
r = omapfb_update_full_screen(fbi);
return r;
}
static void omapfb_sync(struct fb_info *fbi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
omapfb_rqueue_lock(fbdev);
if (fbdev->ctrl->sync)
fbdev->ctrl->sync();
omapfb_rqueue_unlock(fbdev);
}
/*
* Set fb_info.fix fields and also updates fbdev.
* When calling this fb_info.var must be set up already.
*/
static void set_fb_fix(struct fb_info *fbi, int from_init)
{
struct fb_fix_screeninfo *fix = &fbi->fix;
struct fb_var_screeninfo *var = &fbi->var;
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_mem_region *rg;
int bpp;
rg = &plane->fbdev->mem_desc.region[plane->idx];
fbi->screen_base = rg->vaddr;
if (!from_init) {
mutex_lock(&fbi->mm_lock);
fix->smem_start = rg->paddr;
fix->smem_len = rg->size;
mutex_unlock(&fbi->mm_lock);
} else {
fix->smem_start = rg->paddr;
fix->smem_len = rg->size;
}
fix->type = FB_TYPE_PACKED_PIXELS;
bpp = var->bits_per_pixel;
if (var->nonstd)
fix->visual = FB_VISUAL_PSEUDOCOLOR;
else switch (var->bits_per_pixel) {
case 16:
case 12:
fix->visual = FB_VISUAL_TRUECOLOR;
/* 12bpp is stored in 16 bits */
bpp = 16;
break;
case 1:
case 2:
case 4:
case 8:
fix->visual = FB_VISUAL_PSEUDOCOLOR;
break;
}
fix->accel = FB_ACCEL_OMAP1610;
fix->line_length = var->xres_virtual * bpp / 8;
}
static int set_color_mode(struct omapfb_plane_struct *plane,
struct fb_var_screeninfo *var)
{
switch (var->nonstd) {
case 0:
break;
case OMAPFB_COLOR_YUV422:
var->bits_per_pixel = 16;
plane->color_mode = var->nonstd;
return 0;
case OMAPFB_COLOR_YUV420:
var->bits_per_pixel = 12;
plane->color_mode = var->nonstd;
return 0;
case OMAPFB_COLOR_YUY422:
var->bits_per_pixel = 16;
plane->color_mode = var->nonstd;
return 0;
default:
return -EINVAL;
}
switch (var->bits_per_pixel) {
case 1:
plane->color_mode = OMAPFB_COLOR_CLUT_1BPP;
return 0;
case 2:
plane->color_mode = OMAPFB_COLOR_CLUT_2BPP;
return 0;
case 4:
plane->color_mode = OMAPFB_COLOR_CLUT_4BPP;
return 0;
case 8:
plane->color_mode = OMAPFB_COLOR_CLUT_8BPP;
return 0;
case 12:
var->bits_per_pixel = 16;
fallthrough;
case 16:
if (plane->fbdev->panel->bpp == 12)
plane->color_mode = OMAPFB_COLOR_RGB444;
else
plane->color_mode = OMAPFB_COLOR_RGB565;
return 0;
default:
return -EINVAL;
}
}
/*
* Check the values in var against our capabilities and in case of out of
* bound values try to adjust them.
*/
static int set_fb_var(struct fb_info *fbi,
struct fb_var_screeninfo *var)
{
int bpp;
unsigned long max_frame_size;
unsigned long line_size;
int xres_min, xres_max;
int yres_min, yres_max;
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
struct lcd_panel *panel = fbdev->panel;
if (set_color_mode(plane, var) < 0)
return -EINVAL;
bpp = var->bits_per_pixel;
if (plane->color_mode == OMAPFB_COLOR_RGB444)
bpp = 16;
switch (var->rotate) {
case 0:
case 180:
xres_min = OMAPFB_PLANE_XRES_MIN;
xres_max = panel->x_res;
yres_min = OMAPFB_PLANE_YRES_MIN;
yres_max = panel->y_res;
if (cpu_is_omap15xx()) {
var->xres = panel->x_res;
var->yres = panel->y_res;
}
break;
case 90:
case 270:
xres_min = OMAPFB_PLANE_YRES_MIN;
xres_max = panel->y_res;
yres_min = OMAPFB_PLANE_XRES_MIN;
yres_max = panel->x_res;
if (cpu_is_omap15xx()) {
var->xres = panel->y_res;
var->yres = panel->x_res;
}
break;
default:
return -EINVAL;
}
if (var->xres < xres_min)
var->xres = xres_min;
if (var->yres < yres_min)
var->yres = yres_min;
if (var->xres > xres_max)
var->xres = xres_max;
if (var->yres > yres_max)
var->yres = yres_max;
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
max_frame_size = fbdev->mem_desc.region[plane->idx].size;
line_size = var->xres_virtual * bpp / 8;
if (line_size * var->yres_virtual > max_frame_size) {
/* Try to keep yres_virtual first */
line_size = max_frame_size / var->yres_virtual;
var->xres_virtual = line_size * 8 / bpp;
if (var->xres_virtual < var->xres) {
/* Still doesn't fit. Shrink yres_virtual too */
var->xres_virtual = var->xres;
line_size = var->xres * bpp / 8;
var->yres_virtual = max_frame_size / line_size;
}
/* Recheck this, as the virtual size changed. */
if (var->xres_virtual < var->xres)
var->xres = var->xres_virtual;
if (var->yres_virtual < var->yres)
var->yres = var->yres_virtual;
if (var->xres < xres_min || var->yres < yres_min)
return -EINVAL;
}
if (var->xres + var->xoffset > var->xres_virtual)
var->xoffset = var->xres_virtual - var->xres;
if (var->yres + var->yoffset > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
if (plane->color_mode == OMAPFB_COLOR_RGB444) {
var->red.offset = 8;
var->red.length = 4;
var->red.msb_right = 0;
var->green.offset = 4;
var->green.length = 4;
var->green.msb_right = 0;
var->blue.offset = 0;
var->blue.length = 4;
var->blue.msb_right = 0;
} else {
var->red.offset = 11;
var->red.length = 5;
var->red.msb_right = 0;
var->green.offset = 5;
var->green.length = 6;
var->green.msb_right = 0;
var->blue.offset = 0;
var->blue.length = 5;
var->blue.msb_right = 0;
}
var->height = -1;
var->width = -1;
var->grayscale = 0;
/* pixclock in ps, the rest in pixclock */
var->pixclock = 10000000 / (panel->pixel_clock / 100);
var->left_margin = panel->hfp;
var->right_margin = panel->hbp;
var->upper_margin = panel->vfp;
var->lower_margin = panel->vbp;
var->hsync_len = panel->hsw;
var->vsync_len = panel->vsw;
/* TODO: get these from panel->config */
var->vmode = FB_VMODE_NONINTERLACED;
var->sync = 0;
return 0;
}
/*
* Set new x,y offsets in the virtual display for the visible area and switch
* to the new mode.
*/
static int omapfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *fbi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
int r = 0;
omapfb_rqueue_lock(fbdev);
if (var->xoffset != fbi->var.xoffset ||
var->yoffset != fbi->var.yoffset) {
struct fb_var_screeninfo *new_var = &fbdev->new_var;
memcpy(new_var, &fbi->var, sizeof(*new_var));
new_var->xoffset = var->xoffset;
new_var->yoffset = var->yoffset;
if (set_fb_var(fbi, new_var))
r = -EINVAL;
else {
memcpy(&fbi->var, new_var, sizeof(*new_var));
ctrl_change_mode(fbi);
}
}
omapfb_rqueue_unlock(fbdev);
return r;
}
/* Set mirror to vertical axis and switch to the new mode. */
static int omapfb_mirror(struct fb_info *fbi, int mirror)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
int r = 0;
omapfb_rqueue_lock(fbdev);
mirror = mirror ? 1 : 0;
if (cpu_is_omap15xx())
r = -EINVAL;
else if (mirror != plane->info.mirror) {
plane->info.mirror = mirror;
r = ctrl_change_mode(fbi);
}
omapfb_rqueue_unlock(fbdev);
return r;
}
/*
* Check values in var, try to adjust them in case of out of bound values if
* possible, or return error.
*/
static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
int r;
omapfb_rqueue_lock(fbdev);
if (fbdev->ctrl->sync != NULL)
fbdev->ctrl->sync();
r = set_fb_var(fbi, var);
omapfb_rqueue_unlock(fbdev);
return r;
}
/*
* Switch to a new mode. The parameters for it has been check already by
* omapfb_check_var.
*/
static int omapfb_set_par(struct fb_info *fbi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
int r = 0;
omapfb_rqueue_lock(fbdev);
set_fb_fix(fbi, 0);
r = ctrl_change_mode(fbi);
omapfb_rqueue_unlock(fbdev);
return r;
}
static int omapfb_update_window_async(struct fb_info *fbi,
struct omapfb_update_window *win,
void (*callback)(void *),
void *callback_data)
{
int xres, yres;
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
struct fb_var_screeninfo *var = &fbi->var;
switch (var->rotate) {
case 0:
case 180:
xres = fbdev->panel->x_res;
yres = fbdev->panel->y_res;
break;
case 90:
case 270:
xres = fbdev->panel->y_res;
yres = fbdev->panel->x_res;
break;
default:
return -EINVAL;
}
if (win->x >= xres || win->y >= yres ||
win->out_x > xres || win->out_y > yres)
return -EINVAL;
if (!fbdev->ctrl->update_window ||
fbdev->ctrl->get_update_mode() != OMAPFB_MANUAL_UPDATE)
return -ENODEV;
if (win->x + win->width > xres)
win->width = xres - win->x;
if (win->y + win->height > yres)
win->height = yres - win->y;
if (win->out_x + win->out_width > xres)
win->out_width = xres - win->out_x;
if (win->out_y + win->out_height > yres)
win->out_height = yres - win->out_y;
if (!win->width || !win->height || !win->out_width || !win->out_height)
return 0;
return fbdev->ctrl->update_window(fbi, win, callback, callback_data);
}
static int omapfb_update_win(struct fb_info *fbi,
struct omapfb_update_window *win)
{
struct omapfb_plane_struct *plane = fbi->par;
int ret;
omapfb_rqueue_lock(plane->fbdev);
ret = omapfb_update_window_async(fbi, win, NULL, NULL);
omapfb_rqueue_unlock(plane->fbdev);
return ret;
}
static int omapfb_update_full_screen(struct fb_info *fbi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
struct omapfb_update_window win;
int r;
if (!fbdev->ctrl->update_window ||
fbdev->ctrl->get_update_mode() != OMAPFB_MANUAL_UPDATE)
return -ENODEV;
win.x = 0;
win.y = 0;
win.width = fbi->var.xres;
win.height = fbi->var.yres;
win.out_x = 0;
win.out_y = 0;
win.out_width = fbi->var.xres;
win.out_height = fbi->var.yres;
win.format = 0;
omapfb_rqueue_lock(fbdev);
r = fbdev->ctrl->update_window(fbi, &win, NULL, NULL);
omapfb_rqueue_unlock(fbdev);
return r;
}
static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
struct lcd_panel *panel = fbdev->panel;
struct omapfb_plane_info old_info;
int r = 0;
if (pi->pos_x + pi->out_width > panel->x_res ||
pi->pos_y + pi->out_height > panel->y_res)
return -EINVAL;
omapfb_rqueue_lock(fbdev);
if (pi->enabled && !fbdev->mem_desc.region[plane->idx].size) {
/*
* This plane's memory was freed, can't enable it
* until it's reallocated.
*/
r = -EINVAL;
goto out;
}
old_info = plane->info;
plane->info = *pi;
if (pi->enabled) {
r = ctrl_change_mode(fbi);
if (r < 0) {
plane->info = old_info;
goto out;
}
}
r = fbdev->ctrl->enable_plane(plane->idx, pi->enabled);
if (r < 0) {
plane->info = old_info;
goto out;
}
out:
omapfb_rqueue_unlock(fbdev);
return r;
}
static int omapfb_query_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
{
struct omapfb_plane_struct *plane = fbi->par;
*pi = plane->info;
return 0;
}
static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
struct omapfb_mem_region *rg = &fbdev->mem_desc.region[plane->idx];
size_t size;
int r = 0;
if (fbdev->ctrl->setup_mem == NULL)
return -ENODEV;
if (mi->type != OMAPFB_MEMTYPE_SDRAM)
return -EINVAL;
size = PAGE_ALIGN(mi->size);
omapfb_rqueue_lock(fbdev);
if (plane->info.enabled) {
r = -EBUSY;
goto out;
}
if (rg->size != size || rg->type != mi->type) {
struct fb_var_screeninfo *new_var = &fbdev->new_var;
unsigned long old_size = rg->size;
u8 old_type = rg->type;
unsigned long paddr;
rg->size = size;
rg->type = mi->type;
/*
* size == 0 is a special case, for which we
* don't check / adjust the screen parameters.
* This isn't a problem since the plane can't
* be reenabled unless its size is > 0.
*/
if (old_size != size && size) {
if (size) {
memcpy(new_var, &fbi->var, sizeof(*new_var));
r = set_fb_var(fbi, new_var);
if (r < 0)
goto out;
}
}
if (fbdev->ctrl->sync)
fbdev->ctrl->sync();
r = fbdev->ctrl->setup_mem(plane->idx, size, mi->type, &paddr);
if (r < 0) {
/* Revert changes. */
rg->size = old_size;
rg->type = old_type;
goto out;
}
rg->paddr = paddr;
if (old_size != size) {
if (size) {
memcpy(&fbi->var, new_var, sizeof(fbi->var));
set_fb_fix(fbi, 0);
} else {
/*
* Set these explicitly to indicate that the
* plane memory is dealloce'd, the other
* screen parameters in var / fix are invalid.
*/
mutex_lock(&fbi->mm_lock);
fbi->fix.smem_start = 0;
fbi->fix.smem_len = 0;
mutex_unlock(&fbi->mm_lock);
}
}
}
out:
omapfb_rqueue_unlock(fbdev);
return r;
}
static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
struct omapfb_mem_region *rg;
rg = &fbdev->mem_desc.region[plane->idx];
memset(mi, 0, sizeof(*mi));
mi->size = rg->size;
mi->type = rg->type;
return 0;
}
static int omapfb_set_color_key(struct omapfb_device *fbdev,
struct omapfb_color_key *ck)
{
int r;
if (!fbdev->ctrl->set_color_key)
return -ENODEV;
omapfb_rqueue_lock(fbdev);
r = fbdev->ctrl->set_color_key(ck);
omapfb_rqueue_unlock(fbdev);
return r;
}
static int omapfb_get_color_key(struct omapfb_device *fbdev,
struct omapfb_color_key *ck)
{
int r;
if (!fbdev->ctrl->get_color_key)
return -ENODEV;
omapfb_rqueue_lock(fbdev);
r = fbdev->ctrl->get_color_key(ck);
omapfb_rqueue_unlock(fbdev);
return r;
}
static struct blocking_notifier_head omapfb_client_list[OMAPFB_PLANE_NUM];
static int notifier_inited;
static void omapfb_init_notifier(void)
{
int i;
for (i = 0; i < OMAPFB_PLANE_NUM; i++)
BLOCKING_INIT_NOTIFIER_HEAD(&omapfb_client_list[i]);
}
int omapfb_register_client(struct omapfb_notifier_block *omapfb_nb,
omapfb_notifier_callback_t callback,
void *callback_data)
{
int r;
if ((unsigned)omapfb_nb->plane_idx >= OMAPFB_PLANE_NUM)
return -EINVAL;
if (!notifier_inited) {
omapfb_init_notifier();
notifier_inited = 1;
}
omapfb_nb->nb.notifier_call = (int (*)(struct notifier_block *,
unsigned long, void *))callback;
omapfb_nb->data = callback_data;
r = blocking_notifier_chain_register(
&omapfb_client_list[omapfb_nb->plane_idx],
&omapfb_nb->nb);
if (r)
return r;
if (omapfb_dev != NULL &&
omapfb_dev->ctrl && omapfb_dev->ctrl->bind_client) {
omapfb_dev->ctrl->bind_client(omapfb_nb);
}
return 0;
}
EXPORT_SYMBOL(omapfb_register_client);
int omapfb_unregister_client(struct omapfb_notifier_block *omapfb_nb)
{
return blocking_notifier_chain_unregister(
&omapfb_client_list[omapfb_nb->plane_idx], &omapfb_nb->nb);
}
EXPORT_SYMBOL(omapfb_unregister_client);
void omapfb_notify_clients(struct omapfb_device *fbdev, unsigned long event)
{
int i;
if (!notifier_inited)
/* no client registered yet */
return;
for (i = 0; i < OMAPFB_PLANE_NUM; i++)
blocking_notifier_call_chain(&omapfb_client_list[i], event,
fbdev->fb_info[i]);
}
EXPORT_SYMBOL(omapfb_notify_clients);
static int omapfb_set_update_mode(struct omapfb_device *fbdev,
enum omapfb_update_mode mode)
{
int r;
omapfb_rqueue_lock(fbdev);
r = fbdev->ctrl->set_update_mode(mode);
omapfb_rqueue_unlock(fbdev);
return r;
}
static enum omapfb_update_mode omapfb_get_update_mode(struct omapfb_device *fbdev)
{
int r;
omapfb_rqueue_lock(fbdev);
r = fbdev->ctrl->get_update_mode();
omapfb_rqueue_unlock(fbdev);
return r;
}
static void omapfb_get_caps(struct omapfb_device *fbdev, int plane,
struct omapfb_caps *caps)
{
memset(caps, 0, sizeof(*caps));
fbdev->ctrl->get_caps(plane, caps);
if (fbdev->panel->get_caps)
caps->ctrl |= fbdev->panel->get_caps(fbdev->panel);
}
/* For lcd testing */
void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval)
{
omapfb_rqueue_lock(fbdev);
*(u16 *)fbdev->mem_desc.region[0].vaddr = pixval;
if (fbdev->ctrl->get_update_mode() == OMAPFB_MANUAL_UPDATE) {
struct omapfb_update_window win;
memset(&win, 0, sizeof(win));
win.width = 2;
win.height = 2;
win.out_width = 2;
win.out_height = 2;
fbdev->ctrl->update_window(fbdev->fb_info[0], &win, NULL, NULL);
}
omapfb_rqueue_unlock(fbdev);
}
EXPORT_SYMBOL(omapfb_write_first_pixel);
/*
* Ioctl interface. Part of the kernel mode frame buffer API is duplicated
* here to be accessible by user mode code.
*/
static int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd,
unsigned long arg)
{
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
const struct fb_ops *ops = fbi->fbops;
union {
struct omapfb_update_window update_window;
struct omapfb_plane_info plane_info;
struct omapfb_mem_info mem_info;
struct omapfb_color_key color_key;
enum omapfb_update_mode update_mode;
struct omapfb_caps caps;
unsigned int mirror;
int plane_out;
int enable_plane;
} p;
int r = 0;
BUG_ON(!ops);
switch (cmd) {
case OMAPFB_MIRROR:
if (get_user(p.mirror, (int __user *)arg))
r = -EFAULT;
else
omapfb_mirror(fbi, p.mirror);
break;
case OMAPFB_SYNC_GFX:
omapfb_sync(fbi);
break;
case OMAPFB_VSYNC:
break;
case OMAPFB_SET_UPDATE_MODE:
if (get_user(p.update_mode, (int __user *)arg))
r = -EFAULT;
else
r = omapfb_set_update_mode(fbdev, p.update_mode);
break;
case OMAPFB_GET_UPDATE_MODE:
p.update_mode = omapfb_get_update_mode(fbdev);
if (put_user(p.update_mode,
(enum omapfb_update_mode __user *)arg))
r = -EFAULT;
break;
case OMAPFB_UPDATE_WINDOW_OLD:
if (copy_from_user(&p.update_window, (void __user *)arg,
sizeof(struct omapfb_update_window_old)))
r = -EFAULT;
else {
struct omapfb_update_window *u = &p.update_window;
u->out_x = u->x;
u->out_y = u->y;
u->out_width = u->width;
u->out_height = u->height;
memset(u->reserved, 0, sizeof(u->reserved));
r = omapfb_update_win(fbi, u);
}
break;
case OMAPFB_UPDATE_WINDOW:
if (copy_from_user(&p.update_window, (void __user *)arg,
sizeof(p.update_window)))
r = -EFAULT;
else
r = omapfb_update_win(fbi, &p.update_window);
break;
case OMAPFB_SETUP_PLANE:
if (copy_from_user(&p.plane_info, (void __user *)arg,
sizeof(p.plane_info)))
r = -EFAULT;
else
r = omapfb_setup_plane(fbi, &p.plane_info);
break;
case OMAPFB_QUERY_PLANE:
if ((r = omapfb_query_plane(fbi, &p.plane_info)) < 0)
break;
if (copy_to_user((void __user *)arg, &p.plane_info,
sizeof(p.plane_info)))
r = -EFAULT;
break;
case OMAPFB_SETUP_MEM:
if (copy_from_user(&p.mem_info, (void __user *)arg,
sizeof(p.mem_info)))
r = -EFAULT;
else
r = omapfb_setup_mem(fbi, &p.mem_info);
break;
case OMAPFB_QUERY_MEM:
if ((r = omapfb_query_mem(fbi, &p.mem_info)) < 0)
break;
if (copy_to_user((void __user *)arg, &p.mem_info,
sizeof(p.mem_info)))
r = -EFAULT;
break;
case OMAPFB_SET_COLOR_KEY:
if (copy_from_user(&p.color_key, (void __user *)arg,
sizeof(p.color_key)))
r = -EFAULT;
else
r = omapfb_set_color_key(fbdev, &p.color_key);
break;
case OMAPFB_GET_COLOR_KEY:
if ((r = omapfb_get_color_key(fbdev, &p.color_key)) < 0)
break;
if (copy_to_user((void __user *)arg, &p.color_key,
sizeof(p.color_key)))
r = -EFAULT;
break;
case OMAPFB_GET_CAPS:
omapfb_get_caps(fbdev, plane->idx, &p.caps);
if (copy_to_user((void __user *)arg, &p.caps, sizeof(p.caps)))
r = -EFAULT;
break;
case OMAPFB_LCD_TEST:
{
int test_num;
if (get_user(test_num, (int __user *)arg)) {
r = -EFAULT;
break;
}
if (!fbdev->panel->run_test) {
r = -EINVAL;
break;
}
r = fbdev->panel->run_test(fbdev->panel, test_num);
break;
}
case OMAPFB_CTRL_TEST:
{
int test_num;
if (get_user(test_num, (int __user *)arg)) {
r = -EFAULT;
break;
}
if (!fbdev->ctrl->run_test) {
r = -EINVAL;
break;
}
r = fbdev->ctrl->run_test(test_num);
break;
}
default:
r = -EINVAL;
}
return r;
}
static int omapfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct omapfb_plane_struct *plane = info->par;
struct omapfb_device *fbdev = plane->fbdev;
int r;
omapfb_rqueue_lock(fbdev);
r = fbdev->ctrl->mmap(info, vma);
omapfb_rqueue_unlock(fbdev);
return r;
}
/*
* Callback table for the frame buffer framework. Some of these pointers
* will be changed according to the current setting of fb_info->accel_flags.
*/
static struct fb_ops omapfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_open = omapfb_open,
.fb_release = omapfb_release,
.fb_setcolreg = omapfb_setcolreg,
.fb_setcmap = omapfb_setcmap,
.fb_blank = omapfb_blank,
.fb_ioctl = omapfb_ioctl,
.fb_check_var = omapfb_check_var,
.fb_set_par = omapfb_set_par,
.fb_pan_display = omapfb_pan_display,
};
/*
* ---------------------------------------------------------------------------
* Sysfs interface
* ---------------------------------------------------------------------------
*/
/* omapfbX sysfs entries */
static ssize_t omapfb_show_caps_num(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct omapfb_device *fbdev = dev_get_drvdata(dev);
int plane;
size_t size;
struct omapfb_caps caps;
plane = 0;
size = 0;
while (size < PAGE_SIZE && plane < OMAPFB_PLANE_NUM) {
omapfb_get_caps(fbdev, plane, &caps);
size += scnprintf(&buf[size], PAGE_SIZE - size,
"plane#%d %#010x %#010x %#010x\n",
plane, caps.ctrl, caps.plane_color, caps.wnd_color);
plane++;
}
return size;
}
static ssize_t omapfb_show_caps_text(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct omapfb_device *fbdev = dev_get_drvdata(dev);
int i;
struct omapfb_caps caps;
int plane;
size_t size;
plane = 0;
size = 0;
while (size < PAGE_SIZE && plane < OMAPFB_PLANE_NUM) {
omapfb_get_caps(fbdev, plane, &caps);
size += scnprintf(&buf[size], PAGE_SIZE - size,
"plane#%d:\n", plane);
for (i = 0; i < ARRAY_SIZE(ctrl_caps) &&
size < PAGE_SIZE; i++) {
if (ctrl_caps[i].flag & caps.ctrl)
size += scnprintf(&buf[size], PAGE_SIZE - size,
" %s\n", ctrl_caps[i].name);
}
size += scnprintf(&buf[size], PAGE_SIZE - size,
" plane colors:\n");
for (i = 0; i < ARRAY_SIZE(color_caps) &&
size < PAGE_SIZE; i++) {
if (color_caps[i].flag & caps.plane_color)
size += scnprintf(&buf[size], PAGE_SIZE - size,
" %s\n", color_caps[i].name);
}
size += scnprintf(&buf[size], PAGE_SIZE - size,
" window colors:\n");
for (i = 0; i < ARRAY_SIZE(color_caps) &&
size < PAGE_SIZE; i++) {
if (color_caps[i].flag & caps.wnd_color)
size += scnprintf(&buf[size], PAGE_SIZE - size,
" %s\n", color_caps[i].name);
}
plane++;
}
return size;
}
static DEVICE_ATTR(caps_num, 0444, omapfb_show_caps_num, NULL);
static DEVICE_ATTR(caps_text, 0444, omapfb_show_caps_text, NULL);
/* panel sysfs entries */
static ssize_t omapfb_show_panel_name(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct omapfb_device *fbdev = dev_get_drvdata(dev);
return sysfs_emit(buf, "%s\n", fbdev->panel->name);
}
static ssize_t omapfb_show_bklight_level(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct omapfb_device *fbdev = dev_get_drvdata(dev);
int r;
if (fbdev->panel->get_bklight_level) {
r = sysfs_emit(buf, "%d\n",
fbdev->panel->get_bklight_level(fbdev->panel));
} else
r = -ENODEV;
return r;
}
static ssize_t omapfb_store_bklight_level(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
struct omapfb_device *fbdev = dev_get_drvdata(dev);
int r;
if (fbdev->panel->set_bklight_level) {
unsigned int level;
if (sscanf(buf, "%10d", &level) == 1) {
r = fbdev->panel->set_bklight_level(fbdev->panel,
level);
} else
r = -EINVAL;
} else
r = -ENODEV;
return r ? r : size;
}
static ssize_t omapfb_show_bklight_max(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct omapfb_device *fbdev = dev_get_drvdata(dev);
int r;
if (fbdev->panel->get_bklight_level) {
r = sysfs_emit(buf, "%d\n",
fbdev->panel->get_bklight_max(fbdev->panel));
} else
r = -ENODEV;
return r;
}
static struct device_attribute dev_attr_panel_name =
__ATTR(name, 0444, omapfb_show_panel_name, NULL);
static DEVICE_ATTR(backlight_level, 0664,
omapfb_show_bklight_level, omapfb_store_bklight_level);
static DEVICE_ATTR(backlight_max, 0444, omapfb_show_bklight_max, NULL);
static struct attribute *panel_attrs[] = {
&dev_attr_panel_name.attr,
&dev_attr_backlight_level.attr,
&dev_attr_backlight_max.attr,
NULL,
};
static const struct attribute_group panel_attr_grp = {
.name = "panel",
.attrs = panel_attrs,
};
/* ctrl sysfs entries */
static ssize_t omapfb_show_ctrl_name(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct omapfb_device *fbdev = dev_get_drvdata(dev);
return sysfs_emit(buf, "%s\n", fbdev->ctrl->name);
}
static struct device_attribute dev_attr_ctrl_name =
__ATTR(name, 0444, omapfb_show_ctrl_name, NULL);
static struct attribute *ctrl_attrs[] = {
&dev_attr_ctrl_name.attr,
NULL,
};
static const struct attribute_group ctrl_attr_grp = {
.name = "ctrl",
.attrs = ctrl_attrs,
};
static int omapfb_register_sysfs(struct omapfb_device *fbdev)
{
int r;
if ((r = device_create_file(fbdev->dev, &dev_attr_caps_num)))
goto fail0;
if ((r = device_create_file(fbdev->dev, &dev_attr_caps_text)))
goto fail1;
if ((r = sysfs_create_group(&fbdev->dev->kobj, &panel_attr_grp)))
goto fail2;
if ((r = sysfs_create_group(&fbdev->dev->kobj, &ctrl_attr_grp)))
goto fail3;
return 0;
fail3:
sysfs_remove_group(&fbdev->dev->kobj, &panel_attr_grp);
fail2:
device_remove_file(fbdev->dev, &dev_attr_caps_text);
fail1:
device_remove_file(fbdev->dev, &dev_attr_caps_num);
fail0:
dev_err(fbdev->dev, "unable to register sysfs interface\n");
return r;
}
static void omapfb_unregister_sysfs(struct omapfb_device *fbdev)
{
sysfs_remove_group(&fbdev->dev->kobj, &ctrl_attr_grp);
sysfs_remove_group(&fbdev->dev->kobj, &panel_attr_grp);
device_remove_file(fbdev->dev, &dev_attr_caps_num);
device_remove_file(fbdev->dev, &dev_attr_caps_text);
}
/*
* ---------------------------------------------------------------------------
* LDM callbacks
* ---------------------------------------------------------------------------
*/
/* Initialize system fb_info object and set the default video mode.
* The frame buffer memory already allocated by lcddma_init
*/
static int fbinfo_init(struct omapfb_device *fbdev, struct fb_info *info)
{
struct fb_var_screeninfo *var = &info->var;
struct fb_fix_screeninfo *fix = &info->fix;
int r = 0;
info->fbops = &omapfb_ops;
strscpy(fix->id, MODULE_NAME, sizeof(fix->id));
info->pseudo_palette = fbdev->pseudo_palette;
var->accel_flags = def_accel ? FB_ACCELF_TEXT : 0;
var->xres = def_vxres;
var->yres = def_vyres;
var->xres_virtual = def_vxres;
var->yres_virtual = def_vyres;
var->rotate = def_rotate;
var->bits_per_pixel = fbdev->panel->bpp;
set_fb_var(info, var);
set_fb_fix(info, 1);
r = fb_alloc_cmap(&info->cmap, 16, 0);
if (r != 0)
dev_err(fbdev->dev, "unable to allocate color map memory\n");
return r;
}
/* Release the fb_info object */
static void fbinfo_cleanup(struct omapfb_device *fbdev, struct fb_info *fbi)
{
fb_dealloc_cmap(&fbi->cmap);
}
static void planes_cleanup(struct omapfb_device *fbdev)
{
int i;
for (i = 0; i < fbdev->mem_desc.region_cnt; i++) {
if (fbdev->fb_info[i] == NULL)
break;
fbinfo_cleanup(fbdev, fbdev->fb_info[i]);
framebuffer_release(fbdev->fb_info[i]);
}
}
static int planes_init(struct omapfb_device *fbdev)
{
struct fb_info *fbi;
int i;
int r;
for (i = 0; i < fbdev->mem_desc.region_cnt; i++) {
struct omapfb_plane_struct *plane;
fbi = framebuffer_alloc(sizeof(struct omapfb_plane_struct),
fbdev->dev);
if (fbi == NULL) {
planes_cleanup(fbdev);
return -ENOMEM;
}
plane = fbi->par;
plane->idx = i;
plane->fbdev = fbdev;
plane->info.mirror = def_mirror;
fbdev->fb_info[i] = fbi;
if ((r = fbinfo_init(fbdev, fbi)) < 0) {
framebuffer_release(fbi);
planes_cleanup(fbdev);
return r;
}
plane->info.out_width = fbi->var.xres;
plane->info.out_height = fbi->var.yres;
}
return 0;
}
/*
* Free driver resources. Can be called to rollback an aborted initialization
* sequence.
*/
static void omapfb_free_resources(struct omapfb_device *fbdev, int state)
{
int i;
switch (state) {
case OMAPFB_ACTIVE:
for (i = 0; i < fbdev->mem_desc.region_cnt; i++)
unregister_framebuffer(fbdev->fb_info[i]);
fallthrough;
case 7:
omapfb_unregister_sysfs(fbdev);
fallthrough;
case 6:
if (fbdev->panel->disable)
fbdev->panel->disable(fbdev->panel);
fallthrough;
case 5:
omapfb_set_update_mode(fbdev, OMAPFB_UPDATE_DISABLED);
fallthrough;
case 4:
planes_cleanup(fbdev);
fallthrough;
case 3:
ctrl_cleanup(fbdev);
fallthrough;
case 2:
if (fbdev->panel->cleanup)
fbdev->panel->cleanup(fbdev->panel);
fallthrough;
case 1:
dev_set_drvdata(fbdev->dev, NULL);
kfree(fbdev);
break;
case 0:
/* nothing to free */
break;
default:
BUG();
}
}
static int omapfb_find_ctrl(struct omapfb_device *fbdev)
{
struct omapfb_platform_data *conf;
char name[17];
int i;
conf = dev_get_platdata(fbdev->dev);
fbdev->ctrl = NULL;
strscpy(name, conf->lcd.ctrl_name, sizeof(name));
if (strcmp(name, "internal") == 0) {
fbdev->ctrl = fbdev->int_ctrl;
return 0;
}
for (i = 0; i < ARRAY_SIZE(ctrls); i++) {
dev_dbg(fbdev->dev, "ctrl %s\n", ctrls[i]->name);
if (strcmp(ctrls[i]->name, name) == 0) {
fbdev->ctrl = ctrls[i];
break;
}
}
if (fbdev->ctrl == NULL) {
dev_dbg(fbdev->dev, "ctrl %s not supported\n", name);
return -1;
}
return 0;
}
/*
* Called by LDM binding to probe and attach a new device.
* Initialization sequence:
* 1. allocate system omapfb_device structure
* 2. select controller type according to platform configuration
* init LCD panel
* 3. init LCD controller and LCD DMA
* 4. init system fb_info structure for all planes
* 5. setup video mode for first plane and enable it
* 6. enable LCD panel
* 7. register sysfs attributes
* OMAPFB_ACTIVE: register system fb_info structure for all planes
*/
static int omapfb_do_probe(struct platform_device *pdev,
struct lcd_panel *panel)
{
struct omapfb_device *fbdev = NULL;
int init_state;
unsigned long phz, hhz, vhz;
unsigned long vram;
int i;
int r = 0;
init_state = 0;
if (pdev->num_resources != 2) {
dev_err(&pdev->dev, "probed for an unknown device\n");
r = -ENODEV;
goto cleanup;
}
if (dev_get_platdata(&pdev->dev) == NULL) {
dev_err(&pdev->dev, "missing platform data\n");
r = -ENOENT;
goto cleanup;
}
fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
if (fbdev == NULL) {
dev_err(&pdev->dev,
"unable to allocate memory for device info\n");
r = -ENOMEM;
goto cleanup;
}
fbdev->int_irq = platform_get_irq(pdev, 0);
if (fbdev->int_irq < 0) {
r = ENXIO;
goto cleanup;
}
fbdev->ext_irq = platform_get_irq(pdev, 1);
if (fbdev->ext_irq < 0) {
r = ENXIO;
goto cleanup;
}
init_state++;
fbdev->dev = &pdev->dev;
fbdev->panel = panel;
fbdev->dssdev = &omapdss_device;
platform_set_drvdata(pdev, fbdev);
mutex_init(&fbdev->rqueue_mutex);
fbdev->int_ctrl = &omap1_int_ctrl;
#ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
fbdev->ext_if = &omap1_ext_if;
#endif
if (omapfb_find_ctrl(fbdev) < 0) {
dev_err(fbdev->dev,
"LCD controller not found, board not supported\n");
r = -ENODEV;
goto cleanup;
}
if (fbdev->panel->init) {
r = fbdev->panel->init(fbdev->panel, fbdev);
if (r)
goto cleanup;
}
pr_info("omapfb: configured for panel %s\n", fbdev->panel->name);
def_vxres = def_vxres ? def_vxres : fbdev->panel->x_res;
def_vyres = def_vyres ? def_vyres : fbdev->panel->y_res;
init_state++;
r = ctrl_init(fbdev);
if (r)
goto cleanup;
if (fbdev->ctrl->mmap != NULL)
omapfb_ops.fb_mmap = omapfb_mmap;
init_state++;
r = planes_init(fbdev);
if (r)
goto cleanup;
init_state++;
#ifdef CONFIG_FB_OMAP_DMA_TUNE
/* Set DMA priority for EMIFF access to highest */
omap_set_dma_priority(0, OMAP_DMA_PORT_EMIFF, 15);
#endif
r = ctrl_change_mode(fbdev->fb_info[0]);
if (r) {
dev_err(fbdev->dev, "mode setting failed\n");
goto cleanup;
}
/* GFX plane is enabled by default */
r = fbdev->ctrl->enable_plane(OMAPFB_PLANE_GFX, 1);
if (r)
goto cleanup;
omapfb_set_update_mode(fbdev, manual_update ?
OMAPFB_MANUAL_UPDATE : OMAPFB_AUTO_UPDATE);
init_state++;
if (fbdev->panel->enable) {
r = fbdev->panel->enable(fbdev->panel);
if (r)
goto cleanup;
}
init_state++;
r = omapfb_register_sysfs(fbdev);
if (r)
goto cleanup;
init_state++;
vram = 0;
for (i = 0; i < fbdev->mem_desc.region_cnt; i++) {
r = register_framebuffer(fbdev->fb_info[i]);
if (r != 0) {
dev_err(fbdev->dev,
"registering framebuffer %d failed\n", i);
goto cleanup;
}
vram += fbdev->mem_desc.region[i].size;
}
fbdev->state = OMAPFB_ACTIVE;
panel = fbdev->panel;
phz = panel->pixel_clock * 1000;
hhz = phz * 10 / (panel->hfp + panel->x_res + panel->hbp + panel->hsw);
vhz = hhz / (panel->vfp + panel->y_res + panel->vbp + panel->vsw);
omapfb_dev = fbdev;
pr_info("omapfb: Framebuffer initialized. Total vram %lu planes %d\n",
vram, fbdev->mem_desc.region_cnt);
pr_info("omapfb: Pixclock %lu kHz hfreq %lu.%lu kHz "
"vfreq %lu.%lu Hz\n",
phz / 1000, hhz / 10000, hhz % 10, vhz / 10, vhz % 10);
return 0;
cleanup:
omapfb_free_resources(fbdev, init_state);
return r;
}
static int omapfb_probe(struct platform_device *pdev)
{
int r;
BUG_ON(fbdev_pdev != NULL);
r = platform_device_register(&omapdss_device);
if (r) {
dev_err(&pdev->dev, "can't register omapdss device\n");
return r;
}
/* Delay actual initialization until the LCD is registered */
fbdev_pdev = pdev;
if (fbdev_panel != NULL)
omapfb_do_probe(fbdev_pdev, fbdev_panel);
return 0;
}
void omapfb_register_panel(struct lcd_panel *panel)
{
BUG_ON(fbdev_panel != NULL);
fbdev_panel = panel;
if (fbdev_pdev != NULL)
omapfb_do_probe(fbdev_pdev, fbdev_panel);
}
EXPORT_SYMBOL_GPL(omapfb_register_panel);
/* Called when the device is being detached from the driver */
static void omapfb_remove(struct platform_device *pdev)
{
struct omapfb_device *fbdev = platform_get_drvdata(pdev);
enum omapfb_state saved_state = fbdev->state;
/* FIXME: wait till completion of pending events */
fbdev->state = OMAPFB_DISABLED;
omapfb_free_resources(fbdev, saved_state);
platform_device_unregister(&omapdss_device);
fbdev->dssdev = NULL;
}
/* PM suspend */
static int omapfb_suspend(struct platform_device *pdev, pm_message_t mesg)
{
struct omapfb_device *fbdev = platform_get_drvdata(pdev);
if (fbdev != NULL)
omapfb_blank(FB_BLANK_POWERDOWN, fbdev->fb_info[0]);
return 0;
}
/* PM resume */
static int omapfb_resume(struct platform_device *pdev)
{
struct omapfb_device *fbdev = platform_get_drvdata(pdev);
if (fbdev != NULL)
omapfb_blank(FB_BLANK_UNBLANK, fbdev->fb_info[0]);
return 0;
}
static struct platform_driver omapfb_driver = {
.probe = omapfb_probe,
.remove_new = omapfb_remove,
.suspend = omapfb_suspend,
.resume = omapfb_resume,
.driver = {
.name = MODULE_NAME,
},
};
#ifndef MODULE
/* Process kernel command line parameters */
static int __init omapfb_setup(char *options)
{
char *this_opt = NULL;
int r = 0;
pr_debug("omapfb: options %s\n", options);
if (!options || !*options)
return 0;
while (!r && (this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "accel", 5))
def_accel = 1;
else if (!strncmp(this_opt, "vram:", 5)) {
char *suffix;
unsigned long vram;
vram = (simple_strtoul(this_opt + 5, &suffix, 0));
switch (suffix[0]) {
case '\0':
break;
case 'm':
case 'M':
vram *= 1024;
fallthrough;
case 'k':
case 'K':
vram *= 1024;
break;
default:
pr_debug("omapfb: invalid vram suffix %c\n",
suffix[0]);
r = -1;
}
def_vram[def_vram_cnt++] = vram;
}
else if (!strncmp(this_opt, "vxres:", 6))
def_vxres = simple_strtoul(this_opt + 6, NULL, 0);
else if (!strncmp(this_opt, "vyres:", 6))
def_vyres = simple_strtoul(this_opt + 6, NULL, 0);
else if (!strncmp(this_opt, "rotate:", 7))
def_rotate = (simple_strtoul(this_opt + 7, NULL, 0));
else if (!strncmp(this_opt, "mirror:", 7))
def_mirror = (simple_strtoul(this_opt + 7, NULL, 0));
else if (!strncmp(this_opt, "manual_update", 13))
manual_update = 1;
else {
pr_debug("omapfb: invalid option\n");
r = -1;
}
}
return r;
}
#endif
/* Register both the driver and the device */
static int __init omapfb_init(void)
{
#ifndef MODULE
char *option;
if (fb_get_options("omapfb", &option))
return -ENODEV;
omapfb_setup(option);
#endif
/* Register the driver with LDM */
if (platform_driver_register(&omapfb_driver)) {
pr_debug("failed to register omapfb driver\n");
return -ENODEV;
}
return 0;
}
static void __exit omapfb_cleanup(void)
{
platform_driver_unregister(&omapfb_driver);
}
module_param_named(accel, def_accel, uint, 0664);
module_param_array_named(vram, def_vram, ulong, &def_vram_cnt, 0664);
module_param_named(vxres, def_vxres, long, 0664);
module_param_named(vyres, def_vyres, long, 0664);
module_param_named(rotate, def_rotate, uint, 0664);
module_param_named(mirror, def_mirror, uint, 0664);
module_param_named(manual_update, manual_update, bool, 0664);
module_init(omapfb_init);
module_exit(omapfb_cleanup);
MODULE_DESCRIPTION("TI OMAP framebuffer driver");
MODULE_AUTHOR("Imre Deak <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap/omapfb_main.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* OMAP1 Special OptimiSed Screen Interface support
*
* Copyright (C) 2004-2005 Nokia Corporation
* Author: Juha Yrjölä <[email protected]>
*/
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/omap-dma.h>
#include <linux/soc/ti/omap1-io.h>
#include "omapfb.h"
#include "lcd_dma.h"
#include "lcdc.h"
#define MODULE_NAME "omapfb-sossi"
#define OMAP_SOSSI_BASE 0xfffbac00
#define SOSSI_ID_REG 0x00
#define SOSSI_INIT1_REG 0x04
#define SOSSI_INIT2_REG 0x08
#define SOSSI_INIT3_REG 0x0c
#define SOSSI_FIFO_REG 0x10
#define SOSSI_REOTABLE_REG 0x14
#define SOSSI_TEARING_REG 0x18
#define SOSSI_INIT1B_REG 0x1c
#define SOSSI_FIFOB_REG 0x20
#define DMA_GSCR 0xfffedc04
#define DMA_LCD_CCR 0xfffee3c2
#define DMA_LCD_CTRL 0xfffee3c4
#define DMA_LCD_LCH_CTRL 0xfffee3ea
#define CONF_SOSSI_RESET_R (1 << 23)
#define RD_ACCESS 0
#define WR_ACCESS 1
#define SOSSI_MAX_XMIT_BYTES (512 * 1024)
static struct {
void __iomem *base;
struct clk *fck;
unsigned long fck_hz;
spinlock_t lock;
int bus_pick_count;
int bus_pick_width;
int tearsync_mode;
int tearsync_line;
void (*lcdc_callback)(void *data);
void *lcdc_callback_data;
int vsync_dma_pending;
/* timing for read and write access */
int clk_div;
u8 clk_tw0[2];
u8 clk_tw1[2];
/*
* if last_access is the same as current we don't have to change
* the timings
*/
int last_access;
struct omapfb_device *fbdev;
} sossi;
static inline u32 sossi_read_reg(int reg)
{
return readl(sossi.base + reg);
}
static inline u16 sossi_read_reg16(int reg)
{
return readw(sossi.base + reg);
}
static inline u8 sossi_read_reg8(int reg)
{
return readb(sossi.base + reg);
}
static inline void sossi_write_reg(int reg, u32 value)
{
writel(value, sossi.base + reg);
}
static inline void sossi_write_reg16(int reg, u16 value)
{
writew(value, sossi.base + reg);
}
static inline void sossi_write_reg8(int reg, u8 value)
{
writeb(value, sossi.base + reg);
}
static void sossi_set_bits(int reg, u32 bits)
{
sossi_write_reg(reg, sossi_read_reg(reg) | bits);
}
static void sossi_clear_bits(int reg, u32 bits)
{
sossi_write_reg(reg, sossi_read_reg(reg) & ~bits);
}
#define HZ_TO_PS(x) (1000000000 / (x / 1000))
static u32 ps_to_sossi_ticks(u32 ps, int div)
{
u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div;
return (clk_period + ps - 1) / clk_period;
}
static int calc_rd_timings(struct extif_timings *t)
{
u32 tw0, tw1;
int reon, reoff, recyc, actim;
int div = t->clk_div;
/*
* Make sure that after conversion it still holds that:
* reoff > reon, recyc >= reoff, actim > reon
*/
reon = ps_to_sossi_ticks(t->re_on_time, div);
/* reon will be exactly one sossi tick */
if (reon > 1)
return -1;
reoff = ps_to_sossi_ticks(t->re_off_time, div);
if (reoff <= reon)
reoff = reon + 1;
tw0 = reoff - reon;
if (tw0 > 0x10)
return -1;
recyc = ps_to_sossi_ticks(t->re_cycle_time, div);
if (recyc <= reoff)
recyc = reoff + 1;
tw1 = recyc - tw0;
/* values less then 3 result in the SOSSI block resetting itself */
if (tw1 < 3)
tw1 = 3;
if (tw1 > 0x40)
return -1;
actim = ps_to_sossi_ticks(t->access_time, div);
if (actim < reoff)
actim++;
/*
* access time (data hold time) will be exactly one sossi
* tick
*/
if (actim - reoff > 1)
return -1;
t->tim[0] = tw0 - 1;
t->tim[1] = tw1 - 1;
return 0;
}
static int calc_wr_timings(struct extif_timings *t)
{
u32 tw0, tw1;
int weon, weoff, wecyc;
int div = t->clk_div;
/*
* Make sure that after conversion it still holds that:
* weoff > weon, wecyc >= weoff
*/
weon = ps_to_sossi_ticks(t->we_on_time, div);
/* weon will be exactly one sossi tick */
if (weon > 1)
return -1;
weoff = ps_to_sossi_ticks(t->we_off_time, div);
if (weoff <= weon)
weoff = weon + 1;
tw0 = weoff - weon;
if (tw0 > 0x10)
return -1;
wecyc = ps_to_sossi_ticks(t->we_cycle_time, div);
if (wecyc <= weoff)
wecyc = weoff + 1;
tw1 = wecyc - tw0;
/* values less then 3 result in the SOSSI block resetting itself */
if (tw1 < 3)
tw1 = 3;
if (tw1 > 0x40)
return -1;
t->tim[2] = tw0 - 1;
t->tim[3] = tw1 - 1;
return 0;
}
static void _set_timing(int div, int tw0, int tw1)
{
u32 l;
#ifdef VERBOSE
dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n",
tw0 + 1, tw1 + 1, div);
#endif
clk_set_rate(sossi.fck, sossi.fck_hz / div);
clk_enable(sossi.fck);
l = sossi_read_reg(SOSSI_INIT1_REG);
l &= ~((0x0f << 20) | (0x3f << 24));
l |= (tw0 << 20) | (tw1 << 24);
sossi_write_reg(SOSSI_INIT1_REG, l);
clk_disable(sossi.fck);
}
static void _set_bits_per_cycle(int bus_pick_count, int bus_pick_width)
{
u32 l;
l = sossi_read_reg(SOSSI_INIT3_REG);
l &= ~0x3ff;
l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
sossi_write_reg(SOSSI_INIT3_REG, l);
}
static void _set_tearsync_mode(int mode, unsigned line)
{
u32 l;
l = sossi_read_reg(SOSSI_TEARING_REG);
l &= ~(((1 << 11) - 1) << 15);
l |= line << 15;
l &= ~(0x3 << 26);
l |= mode << 26;
sossi_write_reg(SOSSI_TEARING_REG, l);
if (mode)
sossi_set_bits(SOSSI_INIT2_REG, 1 << 6); /* TE logic */
else
sossi_clear_bits(SOSSI_INIT2_REG, 1 << 6);
}
static inline void set_timing(int access)
{
if (access != sossi.last_access) {
sossi.last_access = access;
_set_timing(sossi.clk_div,
sossi.clk_tw0[access], sossi.clk_tw1[access]);
}
}
static void sossi_start_transfer(void)
{
/* WE */
sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4);
/* CS active low */
sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30);
}
static void sossi_stop_transfer(void)
{
/* WE */
sossi_set_bits(SOSSI_INIT2_REG, 1 << 4);
/* CS active low */
sossi_set_bits(SOSSI_INIT1_REG, 1 << 30);
}
static void wait_end_of_write(void)
{
/* Before reading we must check if some writings are going on */
while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
}
static void send_data(const void *data, unsigned int len)
{
while (len >= 4) {
sossi_write_reg(SOSSI_FIFO_REG, *(const u32 *) data);
len -= 4;
data += 4;
}
while (len >= 2) {
sossi_write_reg16(SOSSI_FIFO_REG, *(const u16 *) data);
len -= 2;
data += 2;
}
while (len) {
sossi_write_reg8(SOSSI_FIFO_REG, *(const u8 *) data);
len--;
data++;
}
}
static void set_cycles(unsigned int len)
{
unsigned long nr_cycles = len / (sossi.bus_pick_width / 8);
BUG_ON((nr_cycles - 1) & ~0x3ffff);
sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff);
sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
}
static int sossi_convert_timings(struct extif_timings *t)
{
int r = 0;
int div = t->clk_div;
t->converted = 0;
if (div <= 0 || div > 8)
return -1;
/* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
if ((r = calc_rd_timings(t)) < 0)
return r;
if ((r = calc_wr_timings(t)) < 0)
return r;
t->tim[4] = div;
t->converted = 1;
return 0;
}
static void sossi_set_timings(const struct extif_timings *t)
{
BUG_ON(!t->converted);
sossi.clk_tw0[RD_ACCESS] = t->tim[0];
sossi.clk_tw1[RD_ACCESS] = t->tim[1];
sossi.clk_tw0[WR_ACCESS] = t->tim[2];
sossi.clk_tw1[WR_ACCESS] = t->tim[3];
sossi.clk_div = t->tim[4];
}
static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
{
*clk_period = HZ_TO_PS(sossi.fck_hz);
*max_clk_div = 8;
}
static void sossi_set_bits_per_cycle(int bpc)
{
int bus_pick_count, bus_pick_width;
/*
* We set explicitly the bus_pick_count as well, although
* with remapping/reordering disabled it will be calculated by HW
* as (32 / bus_pick_width).
*/
switch (bpc) {
case 8:
bus_pick_count = 4;
bus_pick_width = 8;
break;
case 16:
bus_pick_count = 2;
bus_pick_width = 16;
break;
default:
BUG();
return;
}
sossi.bus_pick_width = bus_pick_width;
sossi.bus_pick_count = bus_pick_count;
}
static int sossi_setup_tearsync(unsigned pin_cnt,
unsigned hs_pulse_time, unsigned vs_pulse_time,
int hs_pol_inv, int vs_pol_inv, int div)
{
int hs, vs;
u32 l;
if (pin_cnt != 1 || div < 1 || div > 8)
return -EINVAL;
hs = ps_to_sossi_ticks(hs_pulse_time, div);
vs = ps_to_sossi_ticks(vs_pulse_time, div);
if (vs < 8 || vs <= hs || vs >= (1 << 12))
return -EDOM;
vs /= 8;
vs--;
if (hs > 8)
hs = 8;
if (hs)
hs--;
dev_dbg(sossi.fbdev->dev,
"setup_tearsync: hs %d vs %d hs_inv %d vs_inv %d\n",
hs, vs, hs_pol_inv, vs_pol_inv);
clk_enable(sossi.fck);
l = sossi_read_reg(SOSSI_TEARING_REG);
l &= ~((1 << 15) - 1);
l |= vs << 3;
l |= hs;
if (hs_pol_inv)
l |= 1 << 29;
else
l &= ~(1 << 29);
if (vs_pol_inv)
l |= 1 << 28;
else
l &= ~(1 << 28);
sossi_write_reg(SOSSI_TEARING_REG, l);
clk_disable(sossi.fck);
return 0;
}
static int sossi_enable_tearsync(int enable, unsigned line)
{
int mode;
dev_dbg(sossi.fbdev->dev, "tearsync %d line %d\n", enable, line);
if (line >= 1 << 11)
return -EINVAL;
if (enable) {
if (line)
mode = 2; /* HS or VS */
else
mode = 3; /* VS only */
} else
mode = 0;
sossi.tearsync_line = line;
sossi.tearsync_mode = mode;
return 0;
}
static void sossi_write_command(const void *data, unsigned int len)
{
clk_enable(sossi.fck);
set_timing(WR_ACCESS);
_set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
/* CMD#/DATA */
sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18);
set_cycles(len);
sossi_start_transfer();
send_data(data, len);
sossi_stop_transfer();
wait_end_of_write();
clk_disable(sossi.fck);
}
static void sossi_write_data(const void *data, unsigned int len)
{
clk_enable(sossi.fck);
set_timing(WR_ACCESS);
_set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
/* CMD#/DATA */
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
set_cycles(len);
sossi_start_transfer();
send_data(data, len);
sossi_stop_transfer();
wait_end_of_write();
clk_disable(sossi.fck);
}
static void sossi_transfer_area(int width, int height,
void (callback)(void *data), void *data)
{
BUG_ON(callback == NULL);
sossi.lcdc_callback = callback;
sossi.lcdc_callback_data = data;
clk_enable(sossi.fck);
set_timing(WR_ACCESS);
_set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
_set_tearsync_mode(sossi.tearsync_mode, sossi.tearsync_line);
/* CMD#/DATA */
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
set_cycles(width * height * sossi.bus_pick_width / 8);
sossi_start_transfer();
if (sossi.tearsync_mode) {
/*
* Wait for the sync signal and start the transfer only
* then. We can't seem to be able to use HW sync DMA for
* this since LCD DMA shows huge latencies, as if it
* would ignore some of the DMA requests from SoSSI.
*/
unsigned long flags;
spin_lock_irqsave(&sossi.lock, flags);
sossi.vsync_dma_pending++;
spin_unlock_irqrestore(&sossi.lock, flags);
} else
/* Just start the transfer right away. */
omap_enable_lcd_dma();
}
static void sossi_dma_callback(void *data)
{
omap_stop_lcd_dma();
sossi_stop_transfer();
clk_disable(sossi.fck);
sossi.lcdc_callback(sossi.lcdc_callback_data);
}
static void sossi_read_data(void *data, unsigned int len)
{
clk_enable(sossi.fck);
set_timing(RD_ACCESS);
_set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
/* CMD#/DATA */
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
set_cycles(len);
sossi_start_transfer();
while (len >= 4) {
*(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG);
len -= 4;
data += 4;
}
while (len >= 2) {
*(u16 *) data = sossi_read_reg16(SOSSI_FIFO_REG);
len -= 2;
data += 2;
}
while (len) {
*(u8 *) data = sossi_read_reg8(SOSSI_FIFO_REG);
len--;
data++;
}
sossi_stop_transfer();
clk_disable(sossi.fck);
}
static irqreturn_t sossi_match_irq(int irq, void *data)
{
unsigned long flags;
spin_lock_irqsave(&sossi.lock, flags);
if (sossi.vsync_dma_pending) {
sossi.vsync_dma_pending--;
omap_enable_lcd_dma();
}
spin_unlock_irqrestore(&sossi.lock, flags);
return IRQ_HANDLED;
}
static int sossi_init(struct omapfb_device *fbdev)
{
u32 l, k;
struct clk *fck;
struct clk *dpll1out_ck;
int r;
sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K);
if (!sossi.base) {
dev_err(fbdev->dev, "can't ioremap SoSSI\n");
return -ENOMEM;
}
sossi.fbdev = fbdev;
spin_lock_init(&sossi.lock);
dpll1out_ck = clk_get(fbdev->dev, "ck_dpll1out");
if (IS_ERR(dpll1out_ck)) {
dev_err(fbdev->dev, "can't get DPLL1OUT clock\n");
return PTR_ERR(dpll1out_ck);
}
/*
* We need the parent clock rate, which we might divide further
* depending on the timing requirements of the controller. See
* _set_timings.
*/
sossi.fck_hz = clk_get_rate(dpll1out_ck);
clk_put(dpll1out_ck);
fck = clk_get(fbdev->dev, "ck_sossi");
if (IS_ERR(fck)) {
dev_err(fbdev->dev, "can't get SoSSI functional clock\n");
return PTR_ERR(fck);
}
sossi.fck = fck;
/* Reset and enable the SoSSI module */
l = omap_readl(MOD_CONF_CTRL_1);
l |= CONF_SOSSI_RESET_R;
omap_writel(l, MOD_CONF_CTRL_1);
l &= ~CONF_SOSSI_RESET_R;
omap_writel(l, MOD_CONF_CTRL_1);
clk_prepare_enable(sossi.fck);
l = omap_readl(ARM_IDLECT2);
l &= ~(1 << 8); /* DMACK_REQ */
omap_writel(l, ARM_IDLECT2);
l = sossi_read_reg(SOSSI_INIT2_REG);
/* Enable and reset the SoSSI block */
l |= (1 << 0) | (1 << 1);
sossi_write_reg(SOSSI_INIT2_REG, l);
/* Take SoSSI out of reset */
l &= ~(1 << 1);
sossi_write_reg(SOSSI_INIT2_REG, l);
sossi_write_reg(SOSSI_ID_REG, 0);
l = sossi_read_reg(SOSSI_ID_REG);
k = sossi_read_reg(SOSSI_ID_REG);
if (l != 0x55555555 || k != 0xaaaaaaaa) {
dev_err(fbdev->dev,
"invalid SoSSI sync pattern: %08x, %08x\n", l, k);
r = -ENODEV;
goto err;
}
if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
dev_err(fbdev->dev, "can't get LCDC IRQ\n");
r = -ENODEV;
goto err;
}
l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
l = sossi_read_reg(SOSSI_ID_REG);
dev_info(fbdev->dev, "SoSSI version %d.%d initialized\n",
l >> 16, l & 0xffff);
l = sossi_read_reg(SOSSI_INIT1_REG);
l |= (1 << 19); /* DMA_MODE */
l &= ~(1 << 31); /* REORDERING */
sossi_write_reg(SOSSI_INIT1_REG, l);
if ((r = request_irq(fbdev->ext_irq, sossi_match_irq,
IRQ_TYPE_EDGE_FALLING,
"sossi_match", sossi.fbdev->dev)) < 0) {
dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n");
goto err;
}
clk_disable(sossi.fck);
return 0;
err:
clk_disable_unprepare(sossi.fck);
clk_put(sossi.fck);
return r;
}
static void sossi_cleanup(void)
{
omap_lcdc_free_dma_callback();
clk_unprepare(sossi.fck);
clk_put(sossi.fck);
iounmap(sossi.base);
}
struct lcd_ctrl_extif omap1_ext_if = {
.init = sossi_init,
.cleanup = sossi_cleanup,
.get_clk_info = sossi_get_clk_info,
.convert_timings = sossi_convert_timings,
.set_timings = sossi_set_timings,
.set_bits_per_cycle = sossi_set_bits_per_cycle,
.setup_tearsync = sossi_setup_tearsync,
.enable_tearsync = sossi_enable_tearsync,
.write_command = sossi_write_command,
.read_data = sossi_read_data,
.write_data = sossi_write_data,
.transfer_area = sossi_transfer_area,
.max_transmit_size = SOSSI_MAX_XMIT_BYTES,
};
| linux-master | drivers/video/fbdev/omap/sossi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-omap1/lcd_dma.c
*
* Extracted from arch/arm/plat-omap/dma.c
* Copyright (C) 2003 - 2008 Nokia Corporation
* Author: Juha Yrjölä <[email protected]>
* DMA channel linking for 1610 by Samuel Ortiz <[email protected]>
* Graphics DMA and LCD DMA graphics tranformations
* by Imre Deak <[email protected]>
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
* Merged to support both OMAP1 and OMAP2 by Tony Lindgren <[email protected]>
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <[email protected]>
*
* Support functions for the OMAP internal DMA channels.
*/
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/omap-dma.h>
#include <linux/soc/ti/omap1-soc.h>
#include <linux/soc/ti/omap1-io.h>
#include "lcdc.h"
#include "lcd_dma.h"
int omap_lcd_dma_running(void)
{
/*
* On OMAP1510, internal LCD controller will start the transfer
* when it gets enabled, so assume DMA running if LCD enabled.
*/
if (cpu_is_omap15xx())
if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN)
return 1;
/* Check if LCD DMA is running */
if (cpu_is_omap16xx())
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
return 1;
return 0;
}
static struct lcd_dma_info {
spinlock_t lock;
int reserved;
void (*callback)(u16 status, void *data);
void *cb_data;
int active;
unsigned long addr;
int rotate, data_type, xres, yres;
int vxres;
int mirror;
int xscale, yscale;
int ext_ctrl;
int src_port;
int single_transfer;
} lcd_dma;
void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type)
{
lcd_dma.addr = addr;
lcd_dma.data_type = data_type;
lcd_dma.xres = fb_xres;
lcd_dma.yres = fb_yres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
void omap_set_lcd_dma_ext_controller(int external)
{
lcd_dma.ext_ctrl = external;
}
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
void omap_set_lcd_dma_single_transfer(int single)
{
lcd_dma.single_transfer = single;
}
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
void omap_set_lcd_dma_b1_rotation(int rotate)
{
if (cpu_is_omap15xx()) {
printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
BUG();
return;
}
lcd_dma.rotate = rotate;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
void omap_set_lcd_dma_b1_mirror(int mirror)
{
if (cpu_is_omap15xx()) {
printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
BUG();
}
lcd_dma.mirror = mirror;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
if (cpu_is_omap15xx()) {
pr_err("DMA virtual resolution is not supported in 1510 mode\n");
BUG();
}
lcd_dma.vxres = vxres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
{
if (cpu_is_omap15xx()) {
printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
BUG();
}
lcd_dma.xscale = xscale;
lcd_dma.yscale = yscale;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
static void set_b1_regs(void)
{
unsigned long top, bottom;
int es;
u16 w;
unsigned long en, fn;
long ei, fi;
unsigned long vxres;
unsigned int xscale, yscale;
switch (lcd_dma.data_type) {
case OMAP_DMA_DATA_TYPE_S8:
es = 1;
break;
case OMAP_DMA_DATA_TYPE_S16:
es = 2;
break;
case OMAP_DMA_DATA_TYPE_S32:
es = 4;
break;
default:
BUG();
return;
}
vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
BUG_ON(vxres < lcd_dma.xres);
#define PIXADDR(x, y) (lcd_dma.addr + \
((y) * vxres * yscale + (x) * xscale) * es)
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
switch (lcd_dma.rotate) {
case 0:
if (!lcd_dma.mirror) {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
/* 1510 DMA requires the bottom address to be 2 more
* than the actual last memory access location. */
if (cpu_is_omap15xx() &&
lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
bottom += 2;
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 90:
if (!lcd_dma.mirror) {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
case 180:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
} else {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 270:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
} else {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
default:
BUG();
return; /* Suppress warning about uninitialized vars */
}
if (cpu_is_omap15xx()) {
omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
return;
}
/* 1610 regs */
omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
w = omap_readw(OMAP1610_DMA_LCD_CSDP);
w &= ~0x03;
w |= lcd_dma.data_type;
omap_writew(w, OMAP1610_DMA_LCD_CSDP);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
/* Always set the source port as SDRAM for now*/
w &= ~(0x03 << 6);
if (lcd_dma.callback != NULL)
w |= 1 << 1; /* Block interrupt enable */
else
w &= ~(1 << 1);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
if (!(lcd_dma.rotate || lcd_dma.mirror ||
lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/* Set the double-indexed addressing mode */
w |= (0x03 << 12);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
}
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
{
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
if (unlikely(!(w & (1 << 3)))) {
printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
return IRQ_NONE;
}
/* Ack the IRQ */
w |= (1 << 3);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 0;
if (lcd_dma.callback != NULL)
lcd_dma.callback(w, lcd_dma.cb_data);
return IRQ_HANDLED;
}
int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data)
{
spin_lock_irq(&lcd_dma.lock);
if (lcd_dma.reserved) {
spin_unlock_irq(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA channel already reserved\n");
BUG();
return -EBUSY;
}
lcd_dma.reserved = 1;
spin_unlock_irq(&lcd_dma.lock);
lcd_dma.callback = callback;
lcd_dma.cb_data = data;
lcd_dma.active = 0;
lcd_dma.single_transfer = 0;
lcd_dma.rotate = 0;
lcd_dma.vxres = 0;
lcd_dma.mirror = 0;
lcd_dma.xscale = 0;
lcd_dma.yscale = 0;
lcd_dma.ext_ctrl = 0;
lcd_dma.src_port = 0;
return 0;
}
EXPORT_SYMBOL(omap_request_lcd_dma);
void omap_free_lcd_dma(void)
{
spin_lock(&lcd_dma.lock);
if (!lcd_dma.reserved) {
spin_unlock(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA is not reserved\n");
BUG();
return;
}
if (!cpu_is_omap15xx())
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
OMAP1610_DMA_LCD_CCR);
lcd_dma.reserved = 0;
spin_unlock(&lcd_dma.lock);
}
EXPORT_SYMBOL(omap_free_lcd_dma);
void omap_enable_lcd_dma(void)
{
u16 w;
/*
* Set the Enable bit only if an external controller is
* connected. Otherwise the OMAP internal controller will
* start the transfer when it gets enabled.
*/
if (cpu_is_omap15xx() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w |= 1 << 8;
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 1;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w |= 1 << 7;
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
EXPORT_SYMBOL(omap_enable_lcd_dma);
void omap_setup_lcd_dma(void)
{
BUG_ON(lcd_dma.active);
if (!cpu_is_omap15xx()) {
/* Set some reasonable defaults */
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
}
set_b1_regs();
if (!cpu_is_omap15xx()) {
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/*
* If DMA was already active set the end_prog bit to have
* the programmed register set loaded into the active
* register set.
*/
w |= 1 << 11; /* End_prog */
if (!lcd_dma.single_transfer)
w |= (3 << 8); /* Auto_init, repeat */
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
}
EXPORT_SYMBOL(omap_setup_lcd_dma);
void omap_stop_lcd_dma(void)
{
u16 w;
lcd_dma.active = 0;
if (cpu_is_omap15xx() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w &= ~(1 << 7);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
EXPORT_SYMBOL(omap_stop_lcd_dma);
static int __init omap_init_lcd_dma(void)
{
int r;
if (!cpu_class_is_omap1())
return -ENODEV;
if (cpu_is_omap16xx()) {
u16 w;
/* this would prevent OMAP sleep */
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
spin_lock_init(&lcd_dma.lock);
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0)
pr_err("unable to request IRQ for LCD DMA (error %d)\n", r);
return r;
}
arch_initcall(omap_init_lcd_dma);
| linux-master | drivers/video/fbdev/omap/lcd_dma.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/omapfb-main.c
*
* Copyright (C) 2008 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/dma-mapping.h>
#include <linux/vmalloc.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/omapfb.h>
#include <video/omapfb_dss.h>
#include <video/omapvrfb.h>
#include "omapfb.h"
#define MODULE_NAME "omapfb"
#define OMAPFB_PLANE_XRES_MIN 8
#define OMAPFB_PLANE_YRES_MIN 8
static char *def_mode;
static char *def_vram;
static bool def_vrfb;
static int def_rotate;
static bool def_mirror;
static bool auto_update;
static unsigned int auto_update_freq;
module_param(auto_update, bool, 0);
module_param(auto_update_freq, uint, 0644);
#ifdef DEBUG
bool omapfb_debug;
module_param_named(debug, omapfb_debug, bool, 0644);
static bool omapfb_test_pattern;
module_param_named(test, omapfb_test_pattern, bool, 0644);
#endif
static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi);
static int omapfb_get_recommended_bpp(struct omapfb2_device *fbdev,
struct omap_dss_device *dssdev);
#ifdef DEBUG
static void draw_pixel(struct fb_info *fbi, int x, int y, unsigned color)
{
struct fb_var_screeninfo *var = &fbi->var;
struct fb_fix_screeninfo *fix = &fbi->fix;
void __iomem *addr = fbi->screen_base;
const unsigned bytespp = var->bits_per_pixel >> 3;
const unsigned line_len = fix->line_length / bytespp;
int r = (color >> 16) & 0xff;
int g = (color >> 8) & 0xff;
int b = (color >> 0) & 0xff;
if (var->bits_per_pixel == 16) {
u16 __iomem *p = (u16 __iomem *)addr;
p += y * line_len + x;
r = r * 32 / 256;
g = g * 64 / 256;
b = b * 32 / 256;
__raw_writew((r << 11) | (g << 5) | (b << 0), p);
} else if (var->bits_per_pixel == 24) {
u8 __iomem *p = (u8 __iomem *)addr;
p += (y * line_len + x) * 3;
__raw_writeb(b, p + 0);
__raw_writeb(g, p + 1);
__raw_writeb(r, p + 2);
} else if (var->bits_per_pixel == 32) {
u32 __iomem *p = (u32 __iomem *)addr;
p += y * line_len + x;
__raw_writel(color, p);
}
}
static void fill_fb(struct fb_info *fbi)
{
struct fb_var_screeninfo *var = &fbi->var;
const short w = var->xres_virtual;
const short h = var->yres_virtual;
void __iomem *addr = fbi->screen_base;
int y, x;
if (!addr)
return;
DBG("fill_fb %dx%d, line_len %d bytes\n", w, h, fbi->fix.line_length);
for (y = 0; y < h; y++) {
for (x = 0; x < w; x++) {
if (x < 20 && y < 20)
draw_pixel(fbi, x, y, 0xffffff);
else if (x < 20 && (y > 20 && y < h - 20))
draw_pixel(fbi, x, y, 0xff);
else if (y < 20 && (x > 20 && x < w - 20))
draw_pixel(fbi, x, y, 0xff00);
else if (x > w - 20 && (y > 20 && y < h - 20))
draw_pixel(fbi, x, y, 0xff0000);
else if (y > h - 20 && (x > 20 && x < w - 20))
draw_pixel(fbi, x, y, 0xffff00);
else if (x == 20 || x == w - 20 ||
y == 20 || y == h - 20)
draw_pixel(fbi, x, y, 0xffffff);
else if (x == y || w - x == h - y)
draw_pixel(fbi, x, y, 0xff00ff);
else if (w - x == y || x == h - y)
draw_pixel(fbi, x, y, 0x00ffff);
else if (x > 20 && y > 20 && x < w - 20 && y < h - 20) {
int t = x * 3 / w;
unsigned r = 0, g = 0, b = 0;
unsigned c;
if (var->bits_per_pixel == 16) {
if (t == 0)
b = (y % 32) * 256 / 32;
else if (t == 1)
g = (y % 64) * 256 / 64;
else if (t == 2)
r = (y % 32) * 256 / 32;
} else {
if (t == 0)
b = (y % 256);
else if (t == 1)
g = (y % 256);
else if (t == 2)
r = (y % 256);
}
c = (r << 16) | (g << 8) | (b << 0);
draw_pixel(fbi, x, y, c);
} else {
draw_pixel(fbi, x, y, 0);
}
}
}
}
#endif
static unsigned omapfb_get_vrfb_offset(const struct omapfb_info *ofbi, int rot)
{
const struct vrfb *vrfb = &ofbi->region->vrfb;
unsigned offset;
switch (rot) {
case FB_ROTATE_UR:
offset = 0;
break;
case FB_ROTATE_CW:
offset = vrfb->yoffset;
break;
case FB_ROTATE_UD:
offset = vrfb->yoffset * OMAP_VRFB_LINE_LEN + vrfb->xoffset;
break;
case FB_ROTATE_CCW:
offset = vrfb->xoffset * OMAP_VRFB_LINE_LEN;
break;
default:
BUG();
return 0;
}
offset *= vrfb->bytespp;
return offset;
}
static u32 omapfb_get_region_rot_paddr(const struct omapfb_info *ofbi, int rot)
{
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
return ofbi->region->vrfb.paddr[rot]
+ omapfb_get_vrfb_offset(ofbi, rot);
} else {
return ofbi->region->paddr;
}
}
static u32 omapfb_get_region_paddr(const struct omapfb_info *ofbi)
{
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
return ofbi->region->vrfb.paddr[0];
else
return ofbi->region->paddr;
}
static void __iomem *omapfb_get_region_vaddr(const struct omapfb_info *ofbi)
{
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
return ofbi->region->vrfb.vaddr[0];
else
return ofbi->region->vaddr;
}
static struct omapfb_colormode omapfb_colormodes[] = {
{
.dssmode = OMAP_DSS_COLOR_UYVY,
.bits_per_pixel = 16,
.nonstd = OMAPFB_COLOR_YUV422,
}, {
.dssmode = OMAP_DSS_COLOR_YUV2,
.bits_per_pixel = 16,
.nonstd = OMAPFB_COLOR_YUY422,
}, {
.dssmode = OMAP_DSS_COLOR_ARGB16,
.bits_per_pixel = 16,
.red = { .length = 4, .offset = 8, .msb_right = 0 },
.green = { .length = 4, .offset = 4, .msb_right = 0 },
.blue = { .length = 4, .offset = 0, .msb_right = 0 },
.transp = { .length = 4, .offset = 12, .msb_right = 0 },
}, {
.dssmode = OMAP_DSS_COLOR_RGB16,
.bits_per_pixel = 16,
.red = { .length = 5, .offset = 11, .msb_right = 0 },
.green = { .length = 6, .offset = 5, .msb_right = 0 },
.blue = { .length = 5, .offset = 0, .msb_right = 0 },
.transp = { .length = 0, .offset = 0, .msb_right = 0 },
}, {
.dssmode = OMAP_DSS_COLOR_RGB24P,
.bits_per_pixel = 24,
.red = { .length = 8, .offset = 16, .msb_right = 0 },
.green = { .length = 8, .offset = 8, .msb_right = 0 },
.blue = { .length = 8, .offset = 0, .msb_right = 0 },
.transp = { .length = 0, .offset = 0, .msb_right = 0 },
}, {
.dssmode = OMAP_DSS_COLOR_RGB24U,
.bits_per_pixel = 32,
.red = { .length = 8, .offset = 16, .msb_right = 0 },
.green = { .length = 8, .offset = 8, .msb_right = 0 },
.blue = { .length = 8, .offset = 0, .msb_right = 0 },
.transp = { .length = 0, .offset = 0, .msb_right = 0 },
}, {
.dssmode = OMAP_DSS_COLOR_ARGB32,
.bits_per_pixel = 32,
.red = { .length = 8, .offset = 16, .msb_right = 0 },
.green = { .length = 8, .offset = 8, .msb_right = 0 },
.blue = { .length = 8, .offset = 0, .msb_right = 0 },
.transp = { .length = 8, .offset = 24, .msb_right = 0 },
}, {
.dssmode = OMAP_DSS_COLOR_RGBA32,
.bits_per_pixel = 32,
.red = { .length = 8, .offset = 24, .msb_right = 0 },
.green = { .length = 8, .offset = 16, .msb_right = 0 },
.blue = { .length = 8, .offset = 8, .msb_right = 0 },
.transp = { .length = 8, .offset = 0, .msb_right = 0 },
}, {
.dssmode = OMAP_DSS_COLOR_RGBX32,
.bits_per_pixel = 32,
.red = { .length = 8, .offset = 24, .msb_right = 0 },
.green = { .length = 8, .offset = 16, .msb_right = 0 },
.blue = { .length = 8, .offset = 8, .msb_right = 0 },
.transp = { .length = 0, .offset = 0, .msb_right = 0 },
},
};
static bool cmp_component(struct fb_bitfield *f1, struct fb_bitfield *f2)
{
return f1->length == f2->length &&
f1->offset == f2->offset &&
f1->msb_right == f2->msb_right;
}
static bool cmp_var_to_colormode(struct fb_var_screeninfo *var,
struct omapfb_colormode *color)
{
if (var->bits_per_pixel == 0 ||
var->red.length == 0 ||
var->blue.length == 0 ||
var->green.length == 0)
return false;
return var->bits_per_pixel == color->bits_per_pixel &&
cmp_component(&var->red, &color->red) &&
cmp_component(&var->green, &color->green) &&
cmp_component(&var->blue, &color->blue) &&
cmp_component(&var->transp, &color->transp);
}
static void assign_colormode_to_var(struct fb_var_screeninfo *var,
struct omapfb_colormode *color)
{
var->bits_per_pixel = color->bits_per_pixel;
var->nonstd = color->nonstd;
var->red = color->red;
var->green = color->green;
var->blue = color->blue;
var->transp = color->transp;
}
static int fb_mode_to_dss_mode(struct fb_var_screeninfo *var,
enum omap_color_mode *mode)
{
enum omap_color_mode dssmode;
int i;
/* first match with nonstd field */
if (var->nonstd) {
for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
struct omapfb_colormode *m = &omapfb_colormodes[i];
if (var->nonstd == m->nonstd) {
assign_colormode_to_var(var, m);
*mode = m->dssmode;
return 0;
}
}
return -EINVAL;
}
/* then try exact match of bpp and colors */
for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
struct omapfb_colormode *m = &omapfb_colormodes[i];
if (cmp_var_to_colormode(var, m)) {
assign_colormode_to_var(var, m);
*mode = m->dssmode;
return 0;
}
}
/* match with bpp if user has not filled color fields
* properly */
switch (var->bits_per_pixel) {
case 1:
dssmode = OMAP_DSS_COLOR_CLUT1;
break;
case 2:
dssmode = OMAP_DSS_COLOR_CLUT2;
break;
case 4:
dssmode = OMAP_DSS_COLOR_CLUT4;
break;
case 8:
dssmode = OMAP_DSS_COLOR_CLUT8;
break;
case 12:
dssmode = OMAP_DSS_COLOR_RGB12U;
break;
case 16:
dssmode = OMAP_DSS_COLOR_RGB16;
break;
case 24:
dssmode = OMAP_DSS_COLOR_RGB24P;
break;
case 32:
dssmode = OMAP_DSS_COLOR_RGB24U;
break;
default:
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
struct omapfb_colormode *m = &omapfb_colormodes[i];
if (dssmode == m->dssmode) {
assign_colormode_to_var(var, m);
*mode = m->dssmode;
return 0;
}
}
return -EINVAL;
}
static int check_fb_res_bounds(struct fb_var_screeninfo *var)
{
int xres_min = OMAPFB_PLANE_XRES_MIN;
int xres_max = 2048;
int yres_min = OMAPFB_PLANE_YRES_MIN;
int yres_max = 2048;
/* XXX: some applications seem to set virtual res to 0. */
if (var->xres_virtual == 0)
var->xres_virtual = var->xres;
if (var->yres_virtual == 0)
var->yres_virtual = var->yres;
if (var->xres_virtual < xres_min || var->yres_virtual < yres_min)
return -EINVAL;
if (var->xres < xres_min)
var->xres = xres_min;
if (var->yres < yres_min)
var->yres = yres_min;
if (var->xres > xres_max)
var->xres = xres_max;
if (var->yres > yres_max)
var->yres = yres_max;
if (var->xres > var->xres_virtual)
var->xres = var->xres_virtual;
if (var->yres > var->yres_virtual)
var->yres = var->yres_virtual;
return 0;
}
static void shrink_height(unsigned long max_frame_size,
struct fb_var_screeninfo *var)
{
DBG("can't fit FB into memory, reducing y\n");
var->yres_virtual = max_frame_size /
(var->xres_virtual * var->bits_per_pixel >> 3);
if (var->yres_virtual < OMAPFB_PLANE_YRES_MIN)
var->yres_virtual = OMAPFB_PLANE_YRES_MIN;
if (var->yres > var->yres_virtual)
var->yres = var->yres_virtual;
}
static void shrink_width(unsigned long max_frame_size,
struct fb_var_screeninfo *var)
{
DBG("can't fit FB into memory, reducing x\n");
var->xres_virtual = max_frame_size / var->yres_virtual /
(var->bits_per_pixel >> 3);
if (var->xres_virtual < OMAPFB_PLANE_XRES_MIN)
var->xres_virtual = OMAPFB_PLANE_XRES_MIN;
if (var->xres > var->xres_virtual)
var->xres = var->xres_virtual;
}
static int check_vrfb_fb_size(unsigned long region_size,
const struct fb_var_screeninfo *var)
{
unsigned long min_phys_size = omap_vrfb_min_phys_size(var->xres_virtual,
var->yres_virtual, var->bits_per_pixel >> 3);
return min_phys_size > region_size ? -EINVAL : 0;
}
static int check_fb_size(const struct omapfb_info *ofbi,
struct fb_var_screeninfo *var)
{
unsigned long max_frame_size = ofbi->region->size;
int bytespp = var->bits_per_pixel >> 3;
unsigned long line_size = var->xres_virtual * bytespp;
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
/* One needs to check for both VRFB and OMAPFB limitations. */
if (check_vrfb_fb_size(max_frame_size, var))
shrink_height(omap_vrfb_max_height(
max_frame_size, var->xres_virtual, bytespp) *
line_size, var);
if (check_vrfb_fb_size(max_frame_size, var)) {
DBG("cannot fit FB to memory\n");
return -EINVAL;
}
return 0;
}
DBG("max frame size %lu, line size %lu\n", max_frame_size, line_size);
if (line_size * var->yres_virtual > max_frame_size)
shrink_height(max_frame_size, var);
if (line_size * var->yres_virtual > max_frame_size) {
shrink_width(max_frame_size, var);
line_size = var->xres_virtual * bytespp;
}
if (line_size * var->yres_virtual > max_frame_size) {
DBG("cannot fit FB to memory\n");
return -EINVAL;
}
return 0;
}
/*
* Consider if VRFB assisted rotation is in use and if the virtual space for
* the zero degree view needs to be mapped. The need for mapping also acts as
* the trigger for setting up the hardware on the context in question. This
* ensures that one does not attempt to access the virtual view before the
* hardware is serving the address translations.
*/
static int setup_vrfb_rotation(struct fb_info *fbi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_mem_region *rg = ofbi->region;
struct vrfb *vrfb = &rg->vrfb;
struct fb_var_screeninfo *var = &fbi->var;
struct fb_fix_screeninfo *fix = &fbi->fix;
unsigned bytespp;
bool yuv_mode;
enum omap_color_mode mode;
int r;
bool reconf;
if (!rg->size || ofbi->rotation_type != OMAP_DSS_ROT_VRFB)
return 0;
DBG("setup_vrfb_rotation\n");
r = fb_mode_to_dss_mode(var, &mode);
if (r)
return r;
bytespp = var->bits_per_pixel >> 3;
yuv_mode = mode == OMAP_DSS_COLOR_YUV2 || mode == OMAP_DSS_COLOR_UYVY;
/* We need to reconfigure VRFB if the resolution changes, if yuv mode
* is enabled/disabled, or if bytes per pixel changes */
/* XXX we shouldn't allow this when framebuffer is mmapped */
reconf = false;
if (yuv_mode != vrfb->yuv_mode)
reconf = true;
else if (bytespp != vrfb->bytespp)
reconf = true;
else if (vrfb->xres != var->xres_virtual ||
vrfb->yres != var->yres_virtual)
reconf = true;
if (vrfb->vaddr[0] && reconf) {
fbi->screen_base = NULL;
fix->smem_start = 0;
fix->smem_len = 0;
iounmap(vrfb->vaddr[0]);
vrfb->vaddr[0] = NULL;
DBG("setup_vrfb_rotation: reset fb\n");
}
if (vrfb->vaddr[0])
return 0;
omap_vrfb_setup(&rg->vrfb, rg->paddr,
var->xres_virtual,
var->yres_virtual,
bytespp, yuv_mode);
/* Now one can ioremap the 0 angle view */
r = omap_vrfb_map_angle(vrfb, var->yres_virtual, 0);
if (r)
return r;
/* used by open/write in fbmem.c */
fbi->screen_base = ofbi->region->vrfb.vaddr[0];
fix->smem_start = ofbi->region->vrfb.paddr[0];
switch (var->nonstd) {
case OMAPFB_COLOR_YUV422:
case OMAPFB_COLOR_YUY422:
fix->line_length =
(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 2;
break;
default:
fix->line_length =
(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
break;
}
fix->smem_len = var->yres_virtual * fix->line_length;
return 0;
}
int dss_mode_to_fb_mode(enum omap_color_mode dssmode,
struct fb_var_screeninfo *var)
{
int i;
for (i = 0; i < ARRAY_SIZE(omapfb_colormodes); ++i) {
struct omapfb_colormode *mode = &omapfb_colormodes[i];
if (dssmode == mode->dssmode) {
assign_colormode_to_var(var, mode);
return 0;
}
}
return -ENOENT;
}
void set_fb_fix(struct fb_info *fbi)
{
struct fb_fix_screeninfo *fix = &fbi->fix;
struct fb_var_screeninfo *var = &fbi->var;
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_mem_region *rg = ofbi->region;
DBG("set_fb_fix\n");
/* used by open/write in fbmem.c */
fbi->screen_base = (char __iomem *)omapfb_get_region_vaddr(ofbi);
/* used by mmap in fbmem.c */
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
switch (var->nonstd) {
case OMAPFB_COLOR_YUV422:
case OMAPFB_COLOR_YUY422:
fix->line_length =
(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 2;
break;
default:
fix->line_length =
(OMAP_VRFB_LINE_LEN * var->bits_per_pixel) >> 3;
break;
}
fix->smem_len = var->yres_virtual * fix->line_length;
} else {
fix->line_length =
(var->xres_virtual * var->bits_per_pixel) >> 3;
fix->smem_len = rg->size;
}
fix->smem_start = omapfb_get_region_paddr(ofbi);
fix->type = FB_TYPE_PACKED_PIXELS;
if (var->nonstd)
fix->visual = FB_VISUAL_PSEUDOCOLOR;
else {
switch (var->bits_per_pixel) {
case 32:
case 24:
case 16:
case 12:
fix->visual = FB_VISUAL_TRUECOLOR;
/* 12bpp is stored in 16 bits */
break;
case 1:
case 2:
case 4:
case 8:
fix->visual = FB_VISUAL_PSEUDOCOLOR;
break;
}
}
fix->accel = FB_ACCEL_NONE;
fix->xpanstep = 1;
fix->ypanstep = 1;
}
/* check new var and possibly modify it to be ok */
int check_fb_var(struct fb_info *fbi, struct fb_var_screeninfo *var)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omap_dss_device *display = fb2display(fbi);
enum omap_color_mode mode = 0;
int i;
int r;
DBG("check_fb_var %d\n", ofbi->id);
WARN_ON(!atomic_read(&ofbi->region->lock_count));
r = fb_mode_to_dss_mode(var, &mode);
if (r) {
DBG("cannot convert var to omap dss mode\n");
return r;
}
for (i = 0; i < ofbi->num_overlays; ++i) {
if ((ofbi->overlays[i]->supported_modes & mode) == 0) {
DBG("invalid mode\n");
return -EINVAL;
}
}
if (var->rotate > 3)
return -EINVAL;
if (check_fb_res_bounds(var))
return -EINVAL;
/* When no memory is allocated ignore the size check */
if (ofbi->region->size != 0 && check_fb_size(ofbi, var))
return -EINVAL;
if (var->xres + var->xoffset > var->xres_virtual)
var->xoffset = var->xres_virtual - var->xres;
if (var->yres + var->yoffset > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
DBG("xres = %d, yres = %d, vxres = %d, vyres = %d\n",
var->xres, var->yres,
var->xres_virtual, var->yres_virtual);
if (display && display->driver->get_dimensions) {
u32 w, h;
display->driver->get_dimensions(display, &w, &h);
var->width = DIV_ROUND_CLOSEST(w, 1000);
var->height = DIV_ROUND_CLOSEST(h, 1000);
} else {
var->height = -1;
var->width = -1;
}
var->grayscale = 0;
if (display && display->driver->get_timings) {
struct omap_video_timings timings;
display->driver->get_timings(display, &timings);
/* pixclock in ps, the rest in pixclock */
var->pixclock = timings.pixelclock != 0 ?
KHZ2PICOS(timings.pixelclock / 1000) :
0;
var->left_margin = timings.hbp;
var->right_margin = timings.hfp;
var->upper_margin = timings.vbp;
var->lower_margin = timings.vfp;
var->hsync_len = timings.hsw;
var->vsync_len = timings.vsw;
var->sync |= timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH ?
FB_SYNC_HOR_HIGH_ACT : 0;
var->sync |= timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH ?
FB_SYNC_VERT_HIGH_ACT : 0;
var->vmode = timings.interlace ?
FB_VMODE_INTERLACED : FB_VMODE_NONINTERLACED;
} else {
var->pixclock = 0;
var->left_margin = 0;
var->right_margin = 0;
var->upper_margin = 0;
var->lower_margin = 0;
var->hsync_len = 0;
var->vsync_len = 0;
var->sync = 0;
var->vmode = FB_VMODE_NONINTERLACED;
}
return 0;
}
/*
* ---------------------------------------------------------------------------
* fbdev framework callbacks
* ---------------------------------------------------------------------------
*/
static int omapfb_open(struct fb_info *fbi, int user)
{
return 0;
}
static int omapfb_release(struct fb_info *fbi, int user)
{
return 0;
}
static unsigned calc_rotation_offset_dma(const struct fb_var_screeninfo *var,
const struct fb_fix_screeninfo *fix, int rotation)
{
unsigned offset;
offset = var->yoffset * fix->line_length +
var->xoffset * (var->bits_per_pixel >> 3);
return offset;
}
static unsigned calc_rotation_offset_vrfb(const struct fb_var_screeninfo *var,
const struct fb_fix_screeninfo *fix, int rotation)
{
unsigned offset;
if (rotation == FB_ROTATE_UD)
offset = (var->yres_virtual - var->yres) *
fix->line_length;
else if (rotation == FB_ROTATE_CW)
offset = (var->yres_virtual - var->yres) *
(var->bits_per_pixel >> 3);
else
offset = 0;
if (rotation == FB_ROTATE_UR)
offset += var->yoffset * fix->line_length +
var->xoffset * (var->bits_per_pixel >> 3);
else if (rotation == FB_ROTATE_UD)
offset -= var->yoffset * fix->line_length +
var->xoffset * (var->bits_per_pixel >> 3);
else if (rotation == FB_ROTATE_CW)
offset -= var->xoffset * fix->line_length +
var->yoffset * (var->bits_per_pixel >> 3);
else if (rotation == FB_ROTATE_CCW)
offset += var->xoffset * fix->line_length +
var->yoffset * (var->bits_per_pixel >> 3);
return offset;
}
static void omapfb_calc_addr(const struct omapfb_info *ofbi,
const struct fb_var_screeninfo *var,
const struct fb_fix_screeninfo *fix,
int rotation, u32 *paddr)
{
u32 data_start_p;
int offset;
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
data_start_p = omapfb_get_region_rot_paddr(ofbi, rotation);
else
data_start_p = omapfb_get_region_paddr(ofbi);
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
offset = calc_rotation_offset_vrfb(var, fix, rotation);
else
offset = calc_rotation_offset_dma(var, fix, rotation);
data_start_p += offset;
if (offset)
DBG("offset %d, %d = %d\n",
var->xoffset, var->yoffset, offset);
DBG("paddr %x\n", data_start_p);
*paddr = data_start_p;
}
/* setup overlay according to the fb */
int omapfb_setup_overlay(struct fb_info *fbi, struct omap_overlay *ovl,
u16 posx, u16 posy, u16 outw, u16 outh)
{
int r = 0;
struct omapfb_info *ofbi = FB2OFB(fbi);
struct fb_var_screeninfo *var = &fbi->var;
struct fb_fix_screeninfo *fix = &fbi->fix;
enum omap_color_mode mode = 0;
u32 data_start_p = 0;
struct omap_overlay_info info;
int xres, yres;
int screen_width;
int mirror;
int rotation = var->rotate;
int i;
WARN_ON(!atomic_read(&ofbi->region->lock_count));
for (i = 0; i < ofbi->num_overlays; i++) {
if (ovl != ofbi->overlays[i])
continue;
rotation = (rotation + ofbi->rotation[i]) % 4;
break;
}
DBG("setup_overlay %d, posx %d, posy %d, outw %d, outh %d\n", ofbi->id,
posx, posy, outw, outh);
if (rotation == FB_ROTATE_CW || rotation == FB_ROTATE_CCW) {
xres = var->yres;
yres = var->xres;
} else {
xres = var->xres;
yres = var->yres;
}
if (ofbi->region->size)
omapfb_calc_addr(ofbi, var, fix, rotation, &data_start_p);
r = fb_mode_to_dss_mode(var, &mode);
if (r) {
DBG("fb_mode_to_dss_mode failed");
goto err;
}
switch (var->nonstd) {
case OMAPFB_COLOR_YUV422:
case OMAPFB_COLOR_YUY422:
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
screen_width = fix->line_length
/ (var->bits_per_pixel >> 2);
break;
}
fallthrough;
default:
screen_width = fix->line_length / (var->bits_per_pixel >> 3);
break;
}
ovl->get_overlay_info(ovl, &info);
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
mirror = 0;
else
mirror = ofbi->mirror;
info.paddr = data_start_p;
info.screen_width = screen_width;
info.width = xres;
info.height = yres;
info.color_mode = mode;
info.rotation_type = ofbi->rotation_type;
info.rotation = rotation;
info.mirror = mirror;
info.pos_x = posx;
info.pos_y = posy;
info.out_width = outw;
info.out_height = outh;
r = ovl->set_overlay_info(ovl, &info);
if (r) {
DBG("ovl->setup_overlay_info failed\n");
goto err;
}
return 0;
err:
DBG("setup_overlay failed\n");
return r;
}
/* apply var to the overlay */
int omapfb_apply_changes(struct fb_info *fbi, int init)
{
int r = 0;
struct omapfb_info *ofbi = FB2OFB(fbi);
struct fb_var_screeninfo *var = &fbi->var;
struct omap_overlay *ovl;
u16 posx, posy;
u16 outw, outh;
int i;
#ifdef DEBUG
if (omapfb_test_pattern)
fill_fb(fbi);
#endif
WARN_ON(!atomic_read(&ofbi->region->lock_count));
for (i = 0; i < ofbi->num_overlays; i++) {
ovl = ofbi->overlays[i];
DBG("apply_changes, fb %d, ovl %d\n", ofbi->id, ovl->id);
if (ofbi->region->size == 0) {
/* the fb is not available. disable the overlay */
omapfb_overlay_enable(ovl, 0);
if (!init && ovl->manager)
ovl->manager->apply(ovl->manager);
continue;
}
if (init || (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
int rotation = (var->rotate + ofbi->rotation[i]) % 4;
if (rotation == FB_ROTATE_CW ||
rotation == FB_ROTATE_CCW) {
outw = var->yres;
outh = var->xres;
} else {
outw = var->xres;
outh = var->yres;
}
} else {
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
outw = info.out_width;
outh = info.out_height;
}
if (init) {
posx = 0;
posy = 0;
} else {
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
posx = info.pos_x;
posy = info.pos_y;
}
r = omapfb_setup_overlay(fbi, ovl, posx, posy, outw, outh);
if (r)
goto err;
if (!init && ovl->manager)
ovl->manager->apply(ovl->manager);
}
return 0;
err:
DBG("apply_changes failed\n");
return r;
}
/* checks var and eventually tweaks it to something supported,
* DO NOT MODIFY PAR */
static int omapfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
int r;
DBG("check_var(%d)\n", FB2OFB(fbi)->id);
omapfb_get_mem_region(ofbi->region);
r = check_fb_var(fbi, var);
omapfb_put_mem_region(ofbi->region);
return r;
}
/* set the video mode according to info->var */
static int omapfb_set_par(struct fb_info *fbi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
int r;
DBG("set_par(%d)\n", FB2OFB(fbi)->id);
omapfb_get_mem_region(ofbi->region);
set_fb_fix(fbi);
r = setup_vrfb_rotation(fbi);
if (r)
goto out;
r = omapfb_apply_changes(fbi, 0);
out:
omapfb_put_mem_region(ofbi->region);
return r;
}
static int omapfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *fbi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct fb_var_screeninfo new_var;
int r;
DBG("pan_display(%d)\n", FB2OFB(fbi)->id);
if (var->xoffset == fbi->var.xoffset &&
var->yoffset == fbi->var.yoffset)
return 0;
new_var = fbi->var;
new_var.xoffset = var->xoffset;
new_var.yoffset = var->yoffset;
fbi->var = new_var;
omapfb_get_mem_region(ofbi->region);
r = omapfb_apply_changes(fbi, 0);
omapfb_put_mem_region(ofbi->region);
return r;
}
static void mmap_user_open(struct vm_area_struct *vma)
{
struct omapfb2_mem_region *rg = vma->vm_private_data;
omapfb_get_mem_region(rg);
atomic_inc(&rg->map_count);
omapfb_put_mem_region(rg);
}
static void mmap_user_close(struct vm_area_struct *vma)
{
struct omapfb2_mem_region *rg = vma->vm_private_data;
omapfb_get_mem_region(rg);
atomic_dec(&rg->map_count);
omapfb_put_mem_region(rg);
}
static const struct vm_operations_struct mmap_user_ops = {
.open = mmap_user_open,
.close = mmap_user_close,
};
static int omapfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct fb_fix_screeninfo *fix = &fbi->fix;
struct omapfb2_mem_region *rg;
unsigned long start;
u32 len;
int r;
rg = omapfb_get_mem_region(ofbi->region);
start = omapfb_get_region_paddr(ofbi);
len = fix->smem_len;
DBG("user mmap region start %lx, len %d, off %lx\n", start, len,
vma->vm_pgoff << PAGE_SHIFT);
vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
vma->vm_ops = &mmap_user_ops;
vma->vm_private_data = rg;
r = vm_iomap_memory(vma, start, len);
if (r)
goto error;
/* vm_ops.open won't be called for mmap itself. */
atomic_inc(&rg->map_count);
omapfb_put_mem_region(rg);
return 0;
error:
omapfb_put_mem_region(ofbi->region);
return r;
}
/* Store a single color palette entry into a pseudo palette or the hardware
* palette if one is available. For now we support only 16bpp and thus store
* the entry only to the pseudo palette.
*/
static int _setcolreg(struct fb_info *fbi, u_int regno, u_int red, u_int green,
u_int blue, u_int transp, int update_hw_pal)
{
/*struct omapfb_info *ofbi = FB2OFB(fbi);*/
/*struct omapfb2_device *fbdev = ofbi->fbdev;*/
struct fb_var_screeninfo *var = &fbi->var;
int r = 0;
enum omapfb_color_format mode = OMAPFB_COLOR_RGB24U; /* XXX */
/*switch (plane->color_mode) {*/
switch (mode) {
case OMAPFB_COLOR_YUV422:
case OMAPFB_COLOR_YUV420:
case OMAPFB_COLOR_YUY422:
r = -EINVAL;
break;
case OMAPFB_COLOR_CLUT_8BPP:
case OMAPFB_COLOR_CLUT_4BPP:
case OMAPFB_COLOR_CLUT_2BPP:
case OMAPFB_COLOR_CLUT_1BPP:
/*
if (fbdev->ctrl->setcolreg)
r = fbdev->ctrl->setcolreg(regno, red, green, blue,
transp, update_hw_pal);
*/
r = -EINVAL;
break;
case OMAPFB_COLOR_RGB565:
case OMAPFB_COLOR_RGB444:
case OMAPFB_COLOR_RGB24P:
case OMAPFB_COLOR_RGB24U:
if (regno < 16) {
u32 pal;
pal = ((red >> (16 - var->red.length)) <<
var->red.offset) |
((green >> (16 - var->green.length)) <<
var->green.offset) |
(blue >> (16 - var->blue.length));
((u32 *)(fbi->pseudo_palette))[regno] = pal;
}
break;
default:
BUG();
}
return r;
}
static int omapfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
DBG("setcolreg\n");
return _setcolreg(info, regno, red, green, blue, transp, 1);
}
static int omapfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
{
int count, index, r;
u16 *red, *green, *blue, *transp;
u16 trans = 0xffff;
DBG("setcmap\n");
red = cmap->red;
green = cmap->green;
blue = cmap->blue;
transp = cmap->transp;
index = cmap->start;
for (count = 0; count < cmap->len; count++) {
if (transp)
trans = *transp++;
r = _setcolreg(info, index++, *red++, *green++, *blue++, trans,
count == cmap->len - 1);
if (r != 0)
return r;
}
return 0;
}
static int omapfb_blank(int blank, struct fb_info *fbi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_dss_device *display = fb2display(fbi);
struct omapfb_display_data *d;
int r = 0;
if (!display)
return -EINVAL;
omapfb_lock(fbdev);
d = get_display_data(fbdev, display);
switch (blank) {
case FB_BLANK_UNBLANK:
if (display->state == OMAP_DSS_DISPLAY_ACTIVE)
goto exit;
r = display->driver->enable(display);
if ((display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) &&
d->update_mode == OMAPFB_AUTO_UPDATE &&
!d->auto_update_work_enabled)
omapfb_start_auto_update(fbdev, display);
break;
case FB_BLANK_NORMAL:
/* FB_BLANK_NORMAL could be implemented.
* Needs DSS additions. */
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
if (display->state != OMAP_DSS_DISPLAY_ACTIVE)
goto exit;
if (d->auto_update_work_enabled)
omapfb_stop_auto_update(fbdev, display);
display->driver->disable(display);
break;
default:
r = -EINVAL;
}
exit:
omapfb_unlock(fbdev);
return r;
}
#if 0
/* XXX fb_read and fb_write are needed for VRFB */
ssize_t omapfb_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos)
{
DBG("omapfb_write %d, %lu\n", count, (unsigned long)*ppos);
/* XXX needed for VRFB */
return count;
}
#endif
static const struct fb_ops omapfb_ops = {
.owner = THIS_MODULE,
.fb_open = omapfb_open,
.fb_release = omapfb_release,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_blank = omapfb_blank,
.fb_ioctl = omapfb_ioctl,
.fb_check_var = omapfb_check_var,
.fb_set_par = omapfb_set_par,
.fb_pan_display = omapfb_pan_display,
.fb_mmap = omapfb_mmap,
.fb_setcolreg = omapfb_setcolreg,
.fb_setcmap = omapfb_setcmap,
/*.fb_write = omapfb_write,*/
};
static void omapfb_free_fbmem(struct fb_info *fbi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omapfb2_mem_region *rg;
rg = ofbi->region;
if (rg->token == NULL)
return;
WARN_ON(atomic_read(&rg->map_count));
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
/* unmap the 0 angle rotation */
if (rg->vrfb.vaddr[0]) {
iounmap(rg->vrfb.vaddr[0]);
rg->vrfb.vaddr[0] = NULL;
}
omap_vrfb_release_ctx(&rg->vrfb);
}
dma_free_attrs(fbdev->dev, rg->size, rg->token, rg->dma_handle,
rg->attrs);
rg->token = NULL;
rg->vaddr = NULL;
rg->paddr = 0;
rg->alloc = 0;
rg->size = 0;
}
static void clear_fb_info(struct fb_info *fbi)
{
memset(&fbi->var, 0, sizeof(fbi->var));
memset(&fbi->fix, 0, sizeof(fbi->fix));
strscpy(fbi->fix.id, MODULE_NAME, sizeof(fbi->fix.id));
}
static int omapfb_free_all_fbmem(struct omapfb2_device *fbdev)
{
int i;
DBG("free all fbmem\n");
for (i = 0; i < fbdev->num_fbs; i++) {
struct fb_info *fbi = fbdev->fbs[i];
omapfb_free_fbmem(fbi);
clear_fb_info(fbi);
}
return 0;
}
static int omapfb_alloc_fbmem(struct fb_info *fbi, unsigned long size,
unsigned long paddr)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omapfb2_mem_region *rg;
void *token;
unsigned long attrs;
dma_addr_t dma_handle;
int r;
rg = ofbi->region;
rg->paddr = 0;
rg->vaddr = NULL;
memset(&rg->vrfb, 0, sizeof rg->vrfb);
rg->size = 0;
rg->type = 0;
rg->alloc = false;
rg->map = false;
size = PAGE_ALIGN(size);
attrs = DMA_ATTR_WRITE_COMBINE;
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB)
attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
DBG("allocating %lu bytes for fb %d\n", size, ofbi->id);
token = dma_alloc_attrs(fbdev->dev, size, &dma_handle,
GFP_KERNEL, attrs);
if (token == NULL) {
dev_err(fbdev->dev, "failed to allocate framebuffer\n");
return -ENOMEM;
}
DBG("allocated VRAM paddr %lx, vaddr %p\n",
(unsigned long)dma_handle, token);
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
r = omap_vrfb_request_ctx(&rg->vrfb);
if (r) {
dma_free_attrs(fbdev->dev, size, token, dma_handle,
attrs);
dev_err(fbdev->dev, "vrfb create ctx failed\n");
return r;
}
}
rg->attrs = attrs;
rg->token = token;
rg->dma_handle = dma_handle;
rg->paddr = (unsigned long)dma_handle;
rg->vaddr = (void __iomem *)token;
rg->size = size;
rg->alloc = 1;
return 0;
}
/* allocate fbmem using display resolution as reference */
static int omapfb_alloc_fbmem_display(struct fb_info *fbi, unsigned long size,
unsigned long paddr)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_dss_device *display;
int bytespp;
display = fb2display(fbi);
if (!display)
return 0;
switch (omapfb_get_recommended_bpp(fbdev, display)) {
case 16:
bytespp = 2;
break;
case 24:
bytespp = 4;
break;
default:
bytespp = 4;
break;
}
if (!size) {
u16 w, h;
display->driver->get_resolution(display, &w, &h);
if (ofbi->rotation_type == OMAP_DSS_ROT_VRFB) {
size = max(omap_vrfb_min_phys_size(w, h, bytespp),
omap_vrfb_min_phys_size(h, w, bytespp));
DBG("adjusting fb mem size for VRFB, %u -> %lu\n",
w * h * bytespp, size);
} else {
size = w * h * bytespp;
}
}
if (!size)
return 0;
return omapfb_alloc_fbmem(fbi, size, paddr);
}
static int omapfb_parse_vram_param(const char *param, int max_entries,
unsigned long *sizes, unsigned long *paddrs)
{
unsigned int fbnum;
unsigned long size;
unsigned long paddr = 0;
char *p, *start;
start = (char *)param;
while (1) {
p = start;
fbnum = simple_strtoul(p, &p, 10);
if (p == start)
return -EINVAL;
if (*p != ':')
return -EINVAL;
if (fbnum >= max_entries)
return -EINVAL;
size = memparse(p + 1, &p);
if (!size)
return -EINVAL;
paddr = 0;
if (*p == '@') {
paddr = simple_strtoul(p + 1, &p, 16);
if (!paddr)
return -EINVAL;
}
WARN_ONCE(paddr,
"reserving memory at predefined address not supported\n");
paddrs[fbnum] = paddr;
sizes[fbnum] = size;
if (*p == 0)
break;
if (*p != ',')
return -EINVAL;
++p;
start = p;
}
return 0;
}
static int omapfb_allocate_all_fbs(struct omapfb2_device *fbdev)
{
int i, r;
unsigned long vram_sizes[10];
unsigned long vram_paddrs[10];
memset(&vram_sizes, 0, sizeof(vram_sizes));
memset(&vram_paddrs, 0, sizeof(vram_paddrs));
if (def_vram && omapfb_parse_vram_param(def_vram, 10,
vram_sizes, vram_paddrs)) {
dev_err(fbdev->dev, "failed to parse vram parameter\n");
memset(&vram_sizes, 0, sizeof(vram_sizes));
memset(&vram_paddrs, 0, sizeof(vram_paddrs));
}
for (i = 0; i < fbdev->num_fbs; i++) {
/* allocate memory automatically only for fb0, or if
* excplicitly defined with vram or plat data option */
if (i == 0 || vram_sizes[i] != 0) {
r = omapfb_alloc_fbmem_display(fbdev->fbs[i],
vram_sizes[i], vram_paddrs[i]);
if (r)
return r;
}
}
for (i = 0; i < fbdev->num_fbs; i++) {
struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
struct omapfb2_mem_region *rg;
rg = ofbi->region;
DBG("region%d phys %08x virt %p size=%lu\n",
i,
rg->paddr,
rg->vaddr,
rg->size);
}
return 0;
}
static void omapfb_clear_fb(struct fb_info *fbi)
{
const struct fb_fillrect rect = {
.dx = 0,
.dy = 0,
.width = fbi->var.xres_virtual,
.height = fbi->var.yres_virtual,
.color = 0,
.rop = ROP_COPY,
};
cfb_fillrect(fbi, &rect);
}
int omapfb_realloc_fbmem(struct fb_info *fbi, unsigned long size, int type)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omapfb2_mem_region *rg = ofbi->region;
unsigned long old_size = rg->size;
unsigned long old_paddr = rg->paddr;
int old_type = rg->type;
int r;
if (type != OMAPFB_MEMTYPE_SDRAM)
return -EINVAL;
size = PAGE_ALIGN(size);
if (old_size == size && old_type == type)
return 0;
omapfb_free_fbmem(fbi);
if (size == 0) {
clear_fb_info(fbi);
return 0;
}
r = omapfb_alloc_fbmem(fbi, size, 0);
if (r) {
if (old_size)
omapfb_alloc_fbmem(fbi, old_size, old_paddr);
if (rg->size == 0)
clear_fb_info(fbi);
return r;
}
if (old_size == size)
return 0;
if (old_size == 0) {
DBG("initializing fb %d\n", ofbi->id);
r = omapfb_fb_init(fbdev, fbi);
if (r) {
DBG("omapfb_fb_init failed\n");
goto err;
}
r = omapfb_apply_changes(fbi, 1);
if (r) {
DBG("omapfb_apply_changes failed\n");
goto err;
}
} else {
struct fb_var_screeninfo new_var;
memcpy(&new_var, &fbi->var, sizeof(new_var));
r = check_fb_var(fbi, &new_var);
if (r)
goto err;
memcpy(&fbi->var, &new_var, sizeof(fbi->var));
set_fb_fix(fbi);
r = setup_vrfb_rotation(fbi);
if (r)
goto err;
}
omapfb_clear_fb(fbi);
return 0;
err:
omapfb_free_fbmem(fbi);
clear_fb_info(fbi);
return r;
}
static void omapfb_auto_update_work(struct work_struct *work)
{
struct omap_dss_device *dssdev;
struct omap_dss_driver *dssdrv;
struct omapfb_display_data *d;
u16 w, h;
unsigned int freq;
struct omapfb2_device *fbdev;
d = container_of(work, struct omapfb_display_data,
auto_update_work.work);
dssdev = d->dssdev;
dssdrv = dssdev->driver;
fbdev = d->fbdev;
if (!dssdrv || !dssdrv->update)
return;
if (dssdrv->sync)
dssdrv->sync(dssdev);
dssdrv->get_resolution(dssdev, &w, &h);
dssdrv->update(dssdev, 0, 0, w, h);
freq = auto_update_freq;
if (freq == 0)
freq = 20;
queue_delayed_work(fbdev->auto_update_wq,
&d->auto_update_work, HZ / freq);
}
void omapfb_start_auto_update(struct omapfb2_device *fbdev,
struct omap_dss_device *display)
{
struct omapfb_display_data *d;
if (fbdev->auto_update_wq == NULL) {
struct workqueue_struct *wq;
wq = create_singlethread_workqueue("omapfb_auto_update");
if (wq == NULL) {
dev_err(fbdev->dev, "Failed to create workqueue for "
"auto-update\n");
return;
}
fbdev->auto_update_wq = wq;
}
d = get_display_data(fbdev, display);
INIT_DELAYED_WORK(&d->auto_update_work, omapfb_auto_update_work);
d->auto_update_work_enabled = true;
omapfb_auto_update_work(&d->auto_update_work.work);
}
void omapfb_stop_auto_update(struct omapfb2_device *fbdev,
struct omap_dss_device *display)
{
struct omapfb_display_data *d;
d = get_display_data(fbdev, display);
cancel_delayed_work_sync(&d->auto_update_work);
d->auto_update_work_enabled = false;
}
/* initialize fb_info, var, fix to something sane based on the display */
static int omapfb_fb_init(struct omapfb2_device *fbdev, struct fb_info *fbi)
{
struct fb_var_screeninfo *var = &fbi->var;
struct omap_dss_device *display = fb2display(fbi);
struct omapfb_info *ofbi = FB2OFB(fbi);
int r = 0;
fbi->fbops = &omapfb_ops;
fbi->pseudo_palette = fbdev->pseudo_palette;
if (ofbi->region->size == 0) {
clear_fb_info(fbi);
return 0;
}
var->nonstd = 0;
var->bits_per_pixel = 0;
var->rotate = def_rotate;
if (display) {
u16 w, h;
int rotation = (var->rotate + ofbi->rotation[0]) % 4;
display->driver->get_resolution(display, &w, &h);
if (rotation == FB_ROTATE_CW ||
rotation == FB_ROTATE_CCW) {
var->xres = h;
var->yres = w;
} else {
var->xres = w;
var->yres = h;
}
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
if (!var->bits_per_pixel) {
switch (omapfb_get_recommended_bpp(fbdev, display)) {
case 16:
var->bits_per_pixel = 16;
break;
case 24:
var->bits_per_pixel = 32;
break;
default:
dev_err(fbdev->dev, "illegal display "
"bpp\n");
return -EINVAL;
}
}
} else {
/* if there's no display, let's just guess some basic values */
var->xres = 320;
var->yres = 240;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
if (!var->bits_per_pixel)
var->bits_per_pixel = 16;
}
r = check_fb_var(fbi, var);
if (r)
goto err;
set_fb_fix(fbi);
r = setup_vrfb_rotation(fbi);
if (r)
goto err;
r = fb_alloc_cmap(&fbi->cmap, 256, 0);
if (r)
dev_err(fbdev->dev, "unable to allocate color map memory\n");
err:
return r;
}
static void fbinfo_cleanup(struct omapfb2_device *fbdev, struct fb_info *fbi)
{
fb_dealloc_cmap(&fbi->cmap);
}
static void omapfb_free_resources(struct omapfb2_device *fbdev)
{
int i;
DBG("free_resources\n");
if (fbdev == NULL)
return;
for (i = 0; i < fbdev->num_overlays; i++) {
struct omap_overlay *ovl = fbdev->overlays[i];
ovl->disable(ovl);
if (ovl->manager)
ovl->unset_manager(ovl);
}
for (i = 0; i < fbdev->num_fbs; i++)
unregister_framebuffer(fbdev->fbs[i]);
/* free the reserved fbmem */
omapfb_free_all_fbmem(fbdev);
for (i = 0; i < fbdev->num_fbs; i++) {
fbinfo_cleanup(fbdev, fbdev->fbs[i]);
framebuffer_release(fbdev->fbs[i]);
}
for (i = 0; i < fbdev->num_displays; i++) {
struct omap_dss_device *dssdev = fbdev->displays[i].dssdev;
if (fbdev->displays[i].auto_update_work_enabled)
omapfb_stop_auto_update(fbdev, dssdev);
if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)
dssdev->driver->disable(dssdev);
dssdev->driver->disconnect(dssdev);
omap_dss_put_device(dssdev);
}
if (fbdev->auto_update_wq != NULL) {
destroy_workqueue(fbdev->auto_update_wq);
fbdev->auto_update_wq = NULL;
}
dev_set_drvdata(fbdev->dev, NULL);
}
static int omapfb_create_framebuffers(struct omapfb2_device *fbdev)
{
int r, i;
fbdev->num_fbs = 0;
DBG("create %d framebuffers\n", CONFIG_FB_OMAP2_NUM_FBS);
/* allocate fb_infos */
for (i = 0; i < CONFIG_FB_OMAP2_NUM_FBS; i++) {
struct fb_info *fbi;
struct omapfb_info *ofbi;
fbi = framebuffer_alloc(sizeof(struct omapfb_info),
fbdev->dev);
if (!fbi)
return -ENOMEM;
clear_fb_info(fbi);
fbdev->fbs[i] = fbi;
ofbi = FB2OFB(fbi);
ofbi->fbdev = fbdev;
ofbi->id = i;
ofbi->region = &fbdev->regions[i];
ofbi->region->id = i;
init_rwsem(&ofbi->region->lock);
/* assign these early, so that fb alloc can use them */
ofbi->rotation_type = def_vrfb ? OMAP_DSS_ROT_VRFB :
OMAP_DSS_ROT_DMA;
ofbi->mirror = def_mirror;
fbdev->num_fbs++;
}
DBG("fb_infos allocated\n");
/* assign overlays for the fbs */
for (i = 0; i < min(fbdev->num_fbs, fbdev->num_overlays); i++) {
struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
ofbi->overlays[0] = fbdev->overlays[i];
ofbi->num_overlays = 1;
}
/* allocate fb memories */
r = omapfb_allocate_all_fbs(fbdev);
if (r) {
dev_err(fbdev->dev, "failed to allocate fbmem\n");
return r;
}
DBG("fbmems allocated\n");
/* setup fb_infos */
for (i = 0; i < fbdev->num_fbs; i++) {
struct fb_info *fbi = fbdev->fbs[i];
struct omapfb_info *ofbi = FB2OFB(fbi);
omapfb_get_mem_region(ofbi->region);
r = omapfb_fb_init(fbdev, fbi);
omapfb_put_mem_region(ofbi->region);
if (r) {
dev_err(fbdev->dev, "failed to setup fb_info\n");
return r;
}
}
for (i = 0; i < fbdev->num_fbs; i++) {
struct fb_info *fbi = fbdev->fbs[i];
struct omapfb_info *ofbi = FB2OFB(fbi);
if (ofbi->region->size == 0)
continue;
omapfb_clear_fb(fbi);
}
DBG("fb_infos initialized\n");
for (i = 0; i < fbdev->num_fbs; i++) {
r = register_framebuffer(fbdev->fbs[i]);
if (r != 0) {
dev_err(fbdev->dev,
"registering framebuffer %d failed\n", i);
return r;
}
}
DBG("framebuffers registered\n");
for (i = 0; i < fbdev->num_fbs; i++) {
struct fb_info *fbi = fbdev->fbs[i];
struct omapfb_info *ofbi = FB2OFB(fbi);
omapfb_get_mem_region(ofbi->region);
r = omapfb_apply_changes(fbi, 1);
omapfb_put_mem_region(ofbi->region);
if (r) {
dev_err(fbdev->dev, "failed to change mode\n");
return r;
}
}
/* Enable fb0 */
if (fbdev->num_fbs > 0) {
struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[0]);
if (ofbi->num_overlays > 0) {
struct omap_overlay *ovl = ofbi->overlays[0];
ovl->manager->apply(ovl->manager);
r = omapfb_overlay_enable(ovl, 1);
if (r) {
dev_err(fbdev->dev,
"failed to enable overlay\n");
return r;
}
}
}
DBG("create_framebuffers done\n");
return 0;
}
static int omapfb_mode_to_timings(const char *mode_str,
struct omap_dss_device *display,
struct omap_video_timings *timings, u8 *bpp)
{
struct fb_info *fbi;
struct fb_var_screeninfo *var;
struct fb_ops *fbops;
int r;
#ifdef CONFIG_OMAP2_DSS_VENC
if (strcmp(mode_str, "pal") == 0) {
*timings = omap_dss_pal_timings;
*bpp = 24;
return 0;
} else if (strcmp(mode_str, "ntsc") == 0) {
*timings = omap_dss_ntsc_timings;
*bpp = 24;
return 0;
}
#endif
/* this is quite a hack, but I wanted to use the modedb and for
* that we need fb_info and var, so we create dummy ones */
*bpp = 0;
fbi = NULL;
var = NULL;
fbops = NULL;
fbi = kzalloc(sizeof(*fbi), GFP_KERNEL);
if (fbi == NULL) {
r = -ENOMEM;
goto err;
}
var = kzalloc(sizeof(*var), GFP_KERNEL);
if (var == NULL) {
r = -ENOMEM;
goto err;
}
fbops = kzalloc(sizeof(*fbops), GFP_KERNEL);
if (fbops == NULL) {
r = -ENOMEM;
goto err;
}
fbi->fbops = fbops;
r = fb_find_mode(var, fbi, mode_str, NULL, 0, NULL, 24);
if (r == 0) {
r = -EINVAL;
goto err;
}
if (display->driver->get_timings) {
display->driver->get_timings(display, timings);
} else {
timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
}
timings->pixelclock = PICOS2KHZ(var->pixclock) * 1000;
timings->hbp = var->left_margin;
timings->hfp = var->right_margin;
timings->vbp = var->upper_margin;
timings->vfp = var->lower_margin;
timings->hsw = var->hsync_len;
timings->vsw = var->vsync_len;
timings->x_res = var->xres;
timings->y_res = var->yres;
timings->hsync_level = var->sync & FB_SYNC_HOR_HIGH_ACT ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
timings->vsync_level = var->sync & FB_SYNC_VERT_HIGH_ACT ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
timings->interlace = var->vmode & FB_VMODE_INTERLACED;
switch (var->bits_per_pixel) {
case 16:
*bpp = 16;
break;
case 24:
case 32:
default:
*bpp = 24;
break;
}
r = 0;
err:
kfree(fbi);
kfree(var);
kfree(fbops);
return r;
}
static int omapfb_set_def_mode(struct omapfb2_device *fbdev,
struct omap_dss_device *display, char *mode_str)
{
int r;
u8 bpp;
struct omap_video_timings timings, temp_timings;
struct omapfb_display_data *d;
r = omapfb_mode_to_timings(mode_str, display, &timings, &bpp);
if (r)
return r;
d = get_display_data(fbdev, display);
d->bpp_override = bpp;
if (display->driver->check_timings) {
r = display->driver->check_timings(display, &timings);
if (r)
return r;
} else {
/* If check_timings is not present compare xres and yres */
if (display->driver->get_timings) {
display->driver->get_timings(display, &temp_timings);
if (temp_timings.x_res != timings.x_res ||
temp_timings.y_res != timings.y_res)
return -EINVAL;
}
}
if (display->driver->set_timings)
display->driver->set_timings(display, &timings);
return 0;
}
static int omapfb_get_recommended_bpp(struct omapfb2_device *fbdev,
struct omap_dss_device *dssdev)
{
struct omapfb_display_data *d;
BUG_ON(dssdev->driver->get_recommended_bpp == NULL);
d = get_display_data(fbdev, dssdev);
if (d->bpp_override != 0)
return d->bpp_override;
return dssdev->driver->get_recommended_bpp(dssdev);
}
static int omapfb_parse_def_modes(struct omapfb2_device *fbdev)
{
char *str, *options, *this_opt;
int r = 0;
str = kstrdup(def_mode, GFP_KERNEL);
if (!str)
return -ENOMEM;
options = str;
while (!r && (this_opt = strsep(&options, ",")) != NULL) {
char *p, *display_str, *mode_str;
struct omap_dss_device *display;
int i;
p = strchr(this_opt, ':');
if (!p) {
r = -EINVAL;
break;
}
*p = 0;
display_str = this_opt;
mode_str = p + 1;
display = NULL;
for (i = 0; i < fbdev->num_displays; ++i) {
if (strcmp(fbdev->displays[i].dssdev->name,
display_str) == 0) {
display = fbdev->displays[i].dssdev;
break;
}
}
if (!display) {
r = -EINVAL;
break;
}
r = omapfb_set_def_mode(fbdev, display, mode_str);
if (r)
break;
}
kfree(str);
return r;
}
static void fb_videomode_to_omap_timings(struct fb_videomode *m,
struct omap_dss_device *display,
struct omap_video_timings *t)
{
if (display->driver->get_timings) {
display->driver->get_timings(display, t);
} else {
t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
t->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
}
t->x_res = m->xres;
t->y_res = m->yres;
t->pixelclock = PICOS2KHZ(m->pixclock) * 1000;
t->hsw = m->hsync_len;
t->hfp = m->right_margin;
t->hbp = m->left_margin;
t->vsw = m->vsync_len;
t->vfp = m->lower_margin;
t->vbp = m->upper_margin;
t->hsync_level = m->sync & FB_SYNC_HOR_HIGH_ACT ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
t->vsync_level = m->sync & FB_SYNC_VERT_HIGH_ACT ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
t->interlace = m->vmode & FB_VMODE_INTERLACED;
}
static int omapfb_find_best_mode(struct omap_dss_device *display,
struct omap_video_timings *timings)
{
struct fb_monspecs *specs;
u8 *edid;
int r, i, best_idx, len;
if (!display->driver->read_edid)
return -ENODEV;
len = 0x80 * 2;
edid = kmalloc(len, GFP_KERNEL);
if (edid == NULL)
return -ENOMEM;
r = display->driver->read_edid(display, edid, len);
if (r < 0)
goto err1;
specs = kzalloc(sizeof(*specs), GFP_KERNEL);
if (specs == NULL) {
r = -ENOMEM;
goto err1;
}
fb_edid_to_monspecs(edid, specs);
best_idx = -1;
for (i = 0; i < specs->modedb_len; ++i) {
struct fb_videomode *m;
struct omap_video_timings t;
m = &specs->modedb[i];
if (m->pixclock == 0)
continue;
/* skip repeated pixel modes */
if (m->xres == 2880 || m->xres == 1440)
continue;
if (m->vmode & FB_VMODE_INTERLACED ||
m->vmode & FB_VMODE_DOUBLE)
continue;
fb_videomode_to_omap_timings(m, display, &t);
r = display->driver->check_timings(display, &t);
if (r == 0) {
best_idx = i;
break;
}
}
if (best_idx == -1) {
r = -ENOENT;
goto err2;
}
fb_videomode_to_omap_timings(&specs->modedb[best_idx], display,
timings);
r = 0;
err2:
fb_destroy_modedb(specs->modedb);
kfree(specs);
err1:
kfree(edid);
return r;
}
static int omapfb_init_display(struct omapfb2_device *fbdev,
struct omap_dss_device *dssdev)
{
struct omap_dss_driver *dssdrv = dssdev->driver;
struct omapfb_display_data *d;
int r;
r = dssdrv->enable(dssdev);
if (r) {
dev_warn(fbdev->dev, "Failed to enable display '%s'\n",
dssdev->name);
return r;
}
d = get_display_data(fbdev, dssdev);
d->fbdev = fbdev;
if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
u16 w, h;
if (auto_update) {
omapfb_start_auto_update(fbdev, dssdev);
d->update_mode = OMAPFB_AUTO_UPDATE;
} else {
d->update_mode = OMAPFB_MANUAL_UPDATE;
}
if (dssdrv->enable_te) {
r = dssdrv->enable_te(dssdev, 1);
if (r) {
dev_err(fbdev->dev, "Failed to set TE\n");
return r;
}
}
dssdrv->get_resolution(dssdev, &w, &h);
r = dssdrv->update(dssdev, 0, 0, w, h);
if (r) {
dev_err(fbdev->dev,
"Failed to update display\n");
return r;
}
} else {
d->update_mode = OMAPFB_AUTO_UPDATE;
}
return 0;
}
static int omapfb_init_connections(struct omapfb2_device *fbdev,
struct omap_dss_device *def_dssdev)
{
int i, r;
struct omap_overlay_manager *mgr;
r = def_dssdev->driver->connect(def_dssdev);
if (r) {
dev_err(fbdev->dev, "failed to connect default display\n");
return r;
}
for (i = 0; i < fbdev->num_displays; ++i) {
struct omap_dss_device *dssdev = fbdev->displays[i].dssdev;
if (dssdev == def_dssdev)
continue;
/*
* We don't care if the connect succeeds or not. We just want to
* connect as many displays as possible.
*/
dssdev->driver->connect(dssdev);
}
mgr = omapdss_find_mgr_from_display(def_dssdev);
if (!mgr) {
dev_err(fbdev->dev, "no ovl manager for the default display\n");
return -EINVAL;
}
for (i = 0; i < fbdev->num_overlays; i++) {
struct omap_overlay *ovl = fbdev->overlays[i];
if (ovl->manager)
ovl->unset_manager(ovl);
r = ovl->set_manager(ovl, mgr);
if (r)
dev_warn(fbdev->dev,
"failed to connect overlay %s to manager %s\n",
ovl->name, mgr->name);
}
return 0;
}
static struct omap_dss_device *
omapfb_find_default_display(struct omapfb2_device *fbdev)
{
const char *def_name;
int i;
/*
* Search with the display name from the user or the board file,
* comparing to display names and aliases
*/
def_name = omapdss_get_default_display_name();
if (def_name) {
for (i = 0; i < fbdev->num_displays; ++i) {
struct omap_dss_device *dssdev;
dssdev = fbdev->displays[i].dssdev;
if (dssdev->name && strcmp(def_name, dssdev->name) == 0)
return dssdev;
if (strcmp(def_name, dssdev->alias) == 0)
return dssdev;
}
/* def_name given but not found */
return NULL;
}
/* then look for DT alias display0 */
for (i = 0; i < fbdev->num_displays; ++i) {
struct omap_dss_device *dssdev;
int id;
dssdev = fbdev->displays[i].dssdev;
if (dssdev->dev->of_node == NULL)
continue;
id = of_alias_get_id(dssdev->dev->of_node, "display");
if (id == 0)
return dssdev;
}
/* return the first display we have in the list */
return fbdev->displays[0].dssdev;
}
static int omapfb_probe(struct platform_device *pdev)
{
struct omapfb2_device *fbdev = NULL;
int r = 0;
int i;
struct omap_dss_device *def_display;
struct omap_dss_device *dssdev;
DBG("omapfb_probe\n");
if (omapdss_is_initialized() == false)
return -EPROBE_DEFER;
if (pdev->num_resources != 0) {
dev_err(&pdev->dev, "probed for an unknown device\n");
r = -ENODEV;
goto err0;
}
fbdev = devm_kzalloc(&pdev->dev, sizeof(struct omapfb2_device),
GFP_KERNEL);
if (fbdev == NULL) {
r = -ENOMEM;
goto err0;
}
if (def_vrfb && !omap_vrfb_supported()) {
def_vrfb = 0;
dev_warn(&pdev->dev, "VRFB is not supported on this hardware, "
"ignoring the module parameter vrfb=y\n");
}
r = omapdss_compat_init();
if (r)
goto err0;
mutex_init(&fbdev->mtx);
fbdev->dev = &pdev->dev;
platform_set_drvdata(pdev, fbdev);
fbdev->num_displays = 0;
dssdev = NULL;
for_each_dss_dev(dssdev) {
struct omapfb_display_data *d;
omap_dss_get_device(dssdev);
if (!dssdev->driver) {
dev_warn(&pdev->dev, "no driver for display: %s\n",
dssdev->name);
omap_dss_put_device(dssdev);
continue;
}
d = &fbdev->displays[fbdev->num_displays++];
d->dssdev = dssdev;
if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE)
d->update_mode = OMAPFB_MANUAL_UPDATE;
else
d->update_mode = OMAPFB_AUTO_UPDATE;
}
if (fbdev->num_displays == 0) {
dev_err(&pdev->dev, "no displays\n");
r = -EPROBE_DEFER;
goto cleanup;
}
fbdev->num_overlays = omap_dss_get_num_overlays();
for (i = 0; i < fbdev->num_overlays; i++)
fbdev->overlays[i] = omap_dss_get_overlay(i);
fbdev->num_managers = omap_dss_get_num_overlay_managers();
for (i = 0; i < fbdev->num_managers; i++)
fbdev->managers[i] = omap_dss_get_overlay_manager(i);
def_display = omapfb_find_default_display(fbdev);
if (def_display == NULL) {
dev_err(fbdev->dev, "failed to find default display\n");
r = -EPROBE_DEFER;
goto cleanup;
}
r = omapfb_init_connections(fbdev, def_display);
if (r) {
dev_err(fbdev->dev, "failed to init overlay connections\n");
goto cleanup;
}
if (def_mode && strlen(def_mode) > 0) {
if (omapfb_parse_def_modes(fbdev))
dev_warn(&pdev->dev, "cannot parse default modes\n");
} else if (def_display && def_display->driver->set_timings &&
def_display->driver->check_timings) {
struct omap_video_timings t;
r = omapfb_find_best_mode(def_display, &t);
if (r == 0)
def_display->driver->set_timings(def_display, &t);
}
r = omapfb_create_framebuffers(fbdev);
if (r)
goto cleanup;
for (i = 0; i < fbdev->num_managers; i++) {
struct omap_overlay_manager *mgr;
mgr = fbdev->managers[i];
r = mgr->apply(mgr);
if (r)
dev_warn(fbdev->dev, "failed to apply dispc config\n");
}
DBG("mgr->apply'ed\n");
if (def_display) {
r = omapfb_init_display(fbdev, def_display);
if (r) {
dev_err(fbdev->dev,
"failed to initialize default "
"display\n");
goto cleanup;
}
}
DBG("create sysfs for fbs\n");
r = omapfb_create_sysfs(fbdev);
if (r) {
dev_err(fbdev->dev, "failed to create sysfs entries\n");
goto cleanup;
}
if (def_display) {
u16 w, h;
def_display->driver->get_resolution(def_display, &w, &h);
dev_info(fbdev->dev, "using display '%s' mode %dx%d\n",
def_display->name, w, h);
}
return 0;
cleanup:
omapfb_free_resources(fbdev);
omapdss_compat_uninit();
err0:
dev_err(&pdev->dev, "failed to setup omapfb\n");
return r;
}
static void omapfb_remove(struct platform_device *pdev)
{
struct omapfb2_device *fbdev = platform_get_drvdata(pdev);
/* FIXME: wait till completion of pending events */
omapfb_remove_sysfs(fbdev);
omapfb_free_resources(fbdev);
omapdss_compat_uninit();
}
static struct platform_driver omapfb_driver = {
.probe = omapfb_probe,
.remove_new = omapfb_remove,
.driver = {
.name = "omapfb",
},
};
module_param_named(mode, def_mode, charp, 0);
module_param_named(vram, def_vram, charp, 0);
module_param_named(rotate, def_rotate, int, 0);
module_param_named(vrfb, def_vrfb, bool, 0);
module_param_named(mirror, def_mirror, bool, 0);
module_platform_driver(omapfb_driver);
MODULE_ALIAS("platform:omapfb");
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("OMAP2/3 Framebuffer");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/omap2/omapfb/omapfb-main.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/omapfb-ioctl.c
*
* Copyright (C) 2008 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#include <linux/fb.h>
#include <linux/device.h>
#include <linux/uaccess.h>
#include <linux/platform_device.h>
#include <linux/mm.h>
#include <linux/omapfb.h>
#include <linux/vmalloc.h>
#include <linux/export.h>
#include <linux/sizes.h>
#include <video/omapfb_dss.h>
#include <video/omapvrfb.h>
#include "omapfb.h"
static u8 get_mem_idx(struct omapfb_info *ofbi)
{
if (ofbi->id == ofbi->region->id)
return 0;
return OMAPFB_MEM_IDX_ENABLED | ofbi->region->id;
}
static struct omapfb2_mem_region *get_mem_region(struct omapfb_info *ofbi,
u8 mem_idx)
{
struct omapfb2_device *fbdev = ofbi->fbdev;
if (mem_idx & OMAPFB_MEM_IDX_ENABLED)
mem_idx &= OMAPFB_MEM_IDX_MASK;
else
mem_idx = ofbi->id;
if (mem_idx >= fbdev->num_fbs)
return NULL;
return &fbdev->regions[mem_idx];
}
static int omapfb_setup_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_overlay *ovl;
struct omap_overlay_info old_info;
struct omapfb2_mem_region *old_rg, *new_rg;
int r = 0;
DBG("omapfb_setup_plane\n");
if (ofbi->num_overlays == 0) {
r = -EINVAL;
goto out;
}
/* XXX uses only the first overlay */
ovl = ofbi->overlays[0];
old_rg = ofbi->region;
new_rg = get_mem_region(ofbi, pi->mem_idx);
if (!new_rg) {
r = -EINVAL;
goto out;
}
/* Take the locks in a specific order to keep lockdep happy */
if (old_rg->id < new_rg->id) {
omapfb_get_mem_region(old_rg);
omapfb_get_mem_region(new_rg);
} else if (new_rg->id < old_rg->id) {
omapfb_get_mem_region(new_rg);
omapfb_get_mem_region(old_rg);
} else
omapfb_get_mem_region(old_rg);
if (pi->enabled && !new_rg->size) {
/*
* This plane's memory was freed, can't enable it
* until it's reallocated.
*/
r = -EINVAL;
goto put_mem;
}
ovl->get_overlay_info(ovl, &old_info);
if (old_rg != new_rg) {
ofbi->region = new_rg;
set_fb_fix(fbi);
}
if (!pi->enabled) {
r = ovl->disable(ovl);
if (r)
goto undo;
}
if (pi->enabled) {
r = omapfb_setup_overlay(fbi, ovl, pi->pos_x, pi->pos_y,
pi->out_width, pi->out_height);
if (r)
goto undo;
} else {
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
info.pos_x = pi->pos_x;
info.pos_y = pi->pos_y;
info.out_width = pi->out_width;
info.out_height = pi->out_height;
r = ovl->set_overlay_info(ovl, &info);
if (r)
goto undo;
}
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
goto undo;
}
if (pi->enabled) {
r = ovl->enable(ovl);
if (r)
goto undo;
}
/* Release the locks in a specific order to keep lockdep happy */
if (old_rg->id > new_rg->id) {
omapfb_put_mem_region(old_rg);
omapfb_put_mem_region(new_rg);
} else if (new_rg->id > old_rg->id) {
omapfb_put_mem_region(new_rg);
omapfb_put_mem_region(old_rg);
} else
omapfb_put_mem_region(old_rg);
return 0;
undo:
if (old_rg != new_rg) {
ofbi->region = old_rg;
set_fb_fix(fbi);
}
ovl->set_overlay_info(ovl, &old_info);
put_mem:
/* Release the locks in a specific order to keep lockdep happy */
if (old_rg->id > new_rg->id) {
omapfb_put_mem_region(old_rg);
omapfb_put_mem_region(new_rg);
} else if (new_rg->id > old_rg->id) {
omapfb_put_mem_region(new_rg);
omapfb_put_mem_region(old_rg);
} else
omapfb_put_mem_region(old_rg);
out:
dev_err(fbdev->dev, "setup_plane failed\n");
return r;
}
static int omapfb_query_plane(struct fb_info *fbi, struct omapfb_plane_info *pi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
if (ofbi->num_overlays == 0) {
memset(pi, 0, sizeof(*pi));
} else {
struct omap_overlay *ovl;
struct omap_overlay_info ovli;
ovl = ofbi->overlays[0];
ovl->get_overlay_info(ovl, &ovli);
pi->pos_x = ovli.pos_x;
pi->pos_y = ovli.pos_y;
pi->enabled = ovl->is_enabled(ovl);
pi->channel_out = 0; /* xxx */
pi->mirror = 0;
pi->mem_idx = get_mem_idx(ofbi);
pi->out_width = ovli.out_width;
pi->out_height = ovli.out_height;
}
return 0;
}
static int omapfb_setup_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_dss_device *display = fb2display(fbi);
struct omapfb2_mem_region *rg;
int r = 0, i;
size_t size;
if (mi->type != OMAPFB_MEMTYPE_SDRAM)
return -EINVAL;
size = PAGE_ALIGN(mi->size);
if (display && display->driver->sync)
display->driver->sync(display);
rg = ofbi->region;
down_write_nested(&rg->lock, rg->id);
atomic_inc(&rg->lock_count);
if (rg->size == size && rg->type == mi->type)
goto out;
if (atomic_read(&rg->map_count)) {
r = -EBUSY;
goto out;
}
for (i = 0; i < fbdev->num_fbs; i++) {
struct omapfb_info *ofbi2 = FB2OFB(fbdev->fbs[i]);
int j;
if (ofbi2->region != rg)
continue;
for (j = 0; j < ofbi2->num_overlays; j++) {
struct omap_overlay *ovl;
ovl = ofbi2->overlays[j];
if (ovl->is_enabled(ovl)) {
r = -EBUSY;
goto out;
}
}
}
r = omapfb_realloc_fbmem(fbi, size, mi->type);
if (r) {
dev_err(fbdev->dev, "realloc fbmem failed\n");
goto out;
}
out:
atomic_dec(&rg->lock_count);
up_write(&rg->lock);
return r;
}
static int omapfb_query_mem(struct fb_info *fbi, struct omapfb_mem_info *mi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_mem_region *rg;
rg = omapfb_get_mem_region(ofbi->region);
memset(mi, 0, sizeof(*mi));
mi->size = rg->size;
mi->type = rg->type;
omapfb_put_mem_region(rg);
return 0;
}
static int omapfb_update_window(struct fb_info *fbi,
u32 x, u32 y, u32 w, u32 h)
{
struct omap_dss_device *display = fb2display(fbi);
u16 dw, dh;
if (!display)
return 0;
if (w == 0 || h == 0)
return 0;
display->driver->get_resolution(display, &dw, &dh);
if (x + w > dw || y + h > dh)
return -EINVAL;
return display->driver->update(display, x, y, w, h);
}
int omapfb_set_update_mode(struct fb_info *fbi,
enum omapfb_update_mode mode)
{
struct omap_dss_device *display = fb2display(fbi);
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omapfb_display_data *d;
int r;
if (!display)
return -EINVAL;
if (mode != OMAPFB_AUTO_UPDATE && mode != OMAPFB_MANUAL_UPDATE)
return -EINVAL;
omapfb_lock(fbdev);
d = get_display_data(fbdev, display);
if (d->update_mode == mode) {
omapfb_unlock(fbdev);
return 0;
}
r = 0;
if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
if (mode == OMAPFB_AUTO_UPDATE)
omapfb_start_auto_update(fbdev, display);
else /* MANUAL_UPDATE */
omapfb_stop_auto_update(fbdev, display);
d->update_mode = mode;
} else { /* AUTO_UPDATE */
if (mode == OMAPFB_MANUAL_UPDATE)
r = -EINVAL;
}
omapfb_unlock(fbdev);
return r;
}
int omapfb_get_update_mode(struct fb_info *fbi,
enum omapfb_update_mode *mode)
{
struct omap_dss_device *display = fb2display(fbi);
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omapfb_display_data *d;
if (!display)
return -EINVAL;
omapfb_lock(fbdev);
d = get_display_data(fbdev, display);
*mode = d->update_mode;
omapfb_unlock(fbdev);
return 0;
}
/* XXX this color key handling is a hack... */
static struct omapfb_color_key omapfb_color_keys[2];
static int _omapfb_set_color_key(struct omap_overlay_manager *mgr,
struct omapfb_color_key *ck)
{
struct omap_overlay_manager_info info;
enum omap_dss_trans_key_type kt;
int r;
mgr->get_manager_info(mgr, &info);
if (ck->key_type == OMAPFB_COLOR_KEY_DISABLED) {
info.trans_enabled = false;
omapfb_color_keys[mgr->id] = *ck;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
return r;
}
switch (ck->key_type) {
case OMAPFB_COLOR_KEY_GFX_DST:
kt = OMAP_DSS_COLOR_KEY_GFX_DST;
break;
case OMAPFB_COLOR_KEY_VID_SRC:
kt = OMAP_DSS_COLOR_KEY_VID_SRC;
break;
default:
return -EINVAL;
}
info.default_color = ck->background;
info.trans_key = ck->trans_key;
info.trans_key_type = kt;
info.trans_enabled = true;
omapfb_color_keys[mgr->id] = *ck;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
return r;
}
static int omapfb_set_color_key(struct fb_info *fbi,
struct omapfb_color_key *ck)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
int r;
int i;
struct omap_overlay_manager *mgr = NULL;
omapfb_lock(fbdev);
for (i = 0; i < ofbi->num_overlays; i++) {
if (ofbi->overlays[i]->manager) {
mgr = ofbi->overlays[i]->manager;
break;
}
}
if (!mgr) {
r = -EINVAL;
goto err;
}
r = _omapfb_set_color_key(mgr, ck);
err:
omapfb_unlock(fbdev);
return r;
}
static int omapfb_get_color_key(struct fb_info *fbi,
struct omapfb_color_key *ck)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_overlay_manager *mgr = NULL;
int r = 0;
int i;
omapfb_lock(fbdev);
for (i = 0; i < ofbi->num_overlays; i++) {
if (ofbi->overlays[i]->manager) {
mgr = ofbi->overlays[i]->manager;
break;
}
}
if (!mgr) {
r = -EINVAL;
goto err;
}
*ck = omapfb_color_keys[mgr->id];
err:
omapfb_unlock(fbdev);
return r;
}
static int omapfb_memory_read(struct fb_info *fbi,
struct omapfb_memory_read *mr)
{
struct omap_dss_device *display = fb2display(fbi);
void *buf;
int r;
if (!display || !display->driver->memory_read)
return -ENOENT;
if (mr->w > 4096 || mr->h > 4096)
return -EINVAL;
if (mr->w * mr->h * 3 > mr->buffer_size)
return -EINVAL;
buf = vmalloc(mr->buffer_size);
if (!buf) {
DBG("vmalloc failed\n");
return -ENOMEM;
}
r = display->driver->memory_read(display, buf, mr->buffer_size,
mr->x, mr->y, mr->w, mr->h);
if (r > 0) {
if (copy_to_user(mr->buffer, buf, r))
r = -EFAULT;
}
vfree(buf);
return r;
}
static int omapfb_get_ovl_colormode(struct omapfb2_device *fbdev,
struct omapfb_ovl_colormode *mode)
{
int ovl_idx = mode->overlay_idx;
int mode_idx = mode->mode_idx;
struct omap_overlay *ovl;
enum omap_color_mode supported_modes;
struct fb_var_screeninfo var;
int i;
if (ovl_idx >= fbdev->num_overlays)
return -ENODEV;
ovl = fbdev->overlays[ovl_idx];
supported_modes = ovl->supported_modes;
mode_idx = mode->mode_idx;
for (i = 0; i < sizeof(supported_modes) * 8; i++) {
if (!(supported_modes & (1 << i)))
continue;
/*
* It's possible that the FB doesn't support a mode
* that is supported by the overlay, so call the
* following here.
*/
if (dss_mode_to_fb_mode(1 << i, &var) < 0)
continue;
mode_idx--;
if (mode_idx < 0)
break;
}
if (i == sizeof(supported_modes) * 8)
return -ENOENT;
mode->bits_per_pixel = var.bits_per_pixel;
mode->nonstd = var.nonstd;
mode->red = var.red;
mode->green = var.green;
mode->blue = var.blue;
mode->transp = var.transp;
return 0;
}
static int omapfb_wait_for_go(struct fb_info *fbi)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
int r = 0;
int i;
for (i = 0; i < ofbi->num_overlays; ++i) {
struct omap_overlay *ovl = ofbi->overlays[i];
r = ovl->wait_for_go(ovl);
if (r)
break;
}
return r;
}
int omapfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
{
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_dss_device *display = fb2display(fbi);
struct omap_overlay_manager *mgr;
union {
struct omapfb_update_window_old uwnd_o;
struct omapfb_update_window uwnd;
struct omapfb_plane_info plane_info;
struct omapfb_caps caps;
struct omapfb_mem_info mem_info;
struct omapfb_color_key color_key;
struct omapfb_ovl_colormode ovl_colormode;
enum omapfb_update_mode update_mode;
int test_num;
struct omapfb_memory_read memory_read;
struct omapfb_vram_info vram_info;
struct omapfb_tearsync_info tearsync_info;
struct omapfb_display_info display_info;
u32 crt;
} p;
int r = 0;
memset(&p, 0, sizeof(p));
switch (cmd) {
case OMAPFB_SYNC_GFX:
DBG("ioctl SYNC_GFX\n");
if (!display || !display->driver->sync) {
/* DSS1 never returns an error here, so we neither */
/*r = -EINVAL;*/
break;
}
r = display->driver->sync(display);
break;
case OMAPFB_UPDATE_WINDOW_OLD:
DBG("ioctl UPDATE_WINDOW_OLD\n");
if (!display || !display->driver->update) {
r = -EINVAL;
break;
}
if (copy_from_user(&p.uwnd_o,
(void __user *)arg,
sizeof(p.uwnd_o))) {
r = -EFAULT;
break;
}
r = omapfb_update_window(fbi, p.uwnd_o.x, p.uwnd_o.y,
p.uwnd_o.width, p.uwnd_o.height);
break;
case OMAPFB_UPDATE_WINDOW:
DBG("ioctl UPDATE_WINDOW\n");
if (!display || !display->driver->update) {
r = -EINVAL;
break;
}
if (copy_from_user(&p.uwnd, (void __user *)arg,
sizeof(p.uwnd))) {
r = -EFAULT;
break;
}
r = omapfb_update_window(fbi, p.uwnd.x, p.uwnd.y,
p.uwnd.width, p.uwnd.height);
break;
case OMAPFB_SETUP_PLANE:
DBG("ioctl SETUP_PLANE\n");
if (copy_from_user(&p.plane_info, (void __user *)arg,
sizeof(p.plane_info)))
r = -EFAULT;
else
r = omapfb_setup_plane(fbi, &p.plane_info);
break;
case OMAPFB_QUERY_PLANE:
DBG("ioctl QUERY_PLANE\n");
r = omapfb_query_plane(fbi, &p.plane_info);
if (r < 0)
break;
if (copy_to_user((void __user *)arg, &p.plane_info,
sizeof(p.plane_info)))
r = -EFAULT;
break;
case OMAPFB_SETUP_MEM:
DBG("ioctl SETUP_MEM\n");
if (copy_from_user(&p.mem_info, (void __user *)arg,
sizeof(p.mem_info)))
r = -EFAULT;
else
r = omapfb_setup_mem(fbi, &p.mem_info);
break;
case OMAPFB_QUERY_MEM:
DBG("ioctl QUERY_MEM\n");
r = omapfb_query_mem(fbi, &p.mem_info);
if (r < 0)
break;
if (copy_to_user((void __user *)arg, &p.mem_info,
sizeof(p.mem_info)))
r = -EFAULT;
break;
case OMAPFB_GET_CAPS:
DBG("ioctl GET_CAPS\n");
if (!display) {
r = -EINVAL;
break;
}
memset(&p.caps, 0, sizeof(p.caps));
if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE)
p.caps.ctrl |= OMAPFB_CAPS_MANUAL_UPDATE;
if (display->caps & OMAP_DSS_DISPLAY_CAP_TEAR_ELIM)
p.caps.ctrl |= OMAPFB_CAPS_TEARSYNC;
if (copy_to_user((void __user *)arg, &p.caps, sizeof(p.caps)))
r = -EFAULT;
break;
case OMAPFB_GET_OVERLAY_COLORMODE:
DBG("ioctl GET_OVERLAY_COLORMODE\n");
if (copy_from_user(&p.ovl_colormode, (void __user *)arg,
sizeof(p.ovl_colormode))) {
r = -EFAULT;
break;
}
r = omapfb_get_ovl_colormode(fbdev, &p.ovl_colormode);
if (r < 0)
break;
if (copy_to_user((void __user *)arg, &p.ovl_colormode,
sizeof(p.ovl_colormode)))
r = -EFAULT;
break;
case OMAPFB_SET_UPDATE_MODE:
DBG("ioctl SET_UPDATE_MODE\n");
if (get_user(p.update_mode, (int __user *)arg))
r = -EFAULT;
else
r = omapfb_set_update_mode(fbi, p.update_mode);
break;
case OMAPFB_GET_UPDATE_MODE:
DBG("ioctl GET_UPDATE_MODE\n");
r = omapfb_get_update_mode(fbi, &p.update_mode);
if (r)
break;
if (put_user(p.update_mode,
(enum omapfb_update_mode __user *)arg))
r = -EFAULT;
break;
case OMAPFB_SET_COLOR_KEY:
DBG("ioctl SET_COLOR_KEY\n");
if (copy_from_user(&p.color_key, (void __user *)arg,
sizeof(p.color_key)))
r = -EFAULT;
else
r = omapfb_set_color_key(fbi, &p.color_key);
break;
case OMAPFB_GET_COLOR_KEY:
DBG("ioctl GET_COLOR_KEY\n");
r = omapfb_get_color_key(fbi, &p.color_key);
if (r)
break;
if (copy_to_user((void __user *)arg, &p.color_key,
sizeof(p.color_key)))
r = -EFAULT;
break;
case FBIO_WAITFORVSYNC:
if (get_user(p.crt, (__u32 __user *)arg)) {
r = -EFAULT;
break;
}
if (p.crt != 0) {
r = -ENODEV;
break;
}
fallthrough;
case OMAPFB_WAITFORVSYNC:
DBG("ioctl WAITFORVSYNC\n");
if (!display) {
r = -EINVAL;
break;
}
mgr = omapdss_find_mgr_from_display(display);
if (!mgr) {
r = -EINVAL;
break;
}
r = mgr->wait_for_vsync(mgr);
break;
case OMAPFB_WAITFORGO:
DBG("ioctl WAITFORGO\n");
if (!display) {
r = -EINVAL;
break;
}
r = omapfb_wait_for_go(fbi);
break;
/* LCD and CTRL tests do the same thing for backward
* compatibility */
case OMAPFB_LCD_TEST:
DBG("ioctl LCD_TEST\n");
if (get_user(p.test_num, (int __user *)arg)) {
r = -EFAULT;
break;
}
if (!display || !display->driver->run_test) {
r = -EINVAL;
break;
}
r = display->driver->run_test(display, p.test_num);
break;
case OMAPFB_CTRL_TEST:
DBG("ioctl CTRL_TEST\n");
if (get_user(p.test_num, (int __user *)arg)) {
r = -EFAULT;
break;
}
if (!display || !display->driver->run_test) {
r = -EINVAL;
break;
}
r = display->driver->run_test(display, p.test_num);
break;
case OMAPFB_MEMORY_READ:
DBG("ioctl MEMORY_READ\n");
if (copy_from_user(&p.memory_read, (void __user *)arg,
sizeof(p.memory_read))) {
r = -EFAULT;
break;
}
r = omapfb_memory_read(fbi, &p.memory_read);
break;
case OMAPFB_GET_VRAM_INFO: {
DBG("ioctl GET_VRAM_INFO\n");
/*
* We don't have the ability to get this vram info anymore.
* Fill in something that should keep the applications working.
*/
p.vram_info.total = SZ_1M * 64;
p.vram_info.free = SZ_1M * 64;
p.vram_info.largest_free_block = SZ_1M * 64;
if (copy_to_user((void __user *)arg, &p.vram_info,
sizeof(p.vram_info)))
r = -EFAULT;
break;
}
case OMAPFB_SET_TEARSYNC: {
DBG("ioctl SET_TEARSYNC\n");
if (copy_from_user(&p.tearsync_info, (void __user *)arg,
sizeof(p.tearsync_info))) {
r = -EFAULT;
break;
}
if (!display || !display->driver->enable_te) {
r = -ENODEV;
break;
}
r = display->driver->enable_te(display,
!!p.tearsync_info.enabled);
break;
}
case OMAPFB_GET_DISPLAY_INFO: {
u16 xres, yres;
DBG("ioctl GET_DISPLAY_INFO\n");
if (display == NULL) {
r = -ENODEV;
break;
}
display->driver->get_resolution(display, &xres, &yres);
p.display_info.xres = xres;
p.display_info.yres = yres;
if (display->driver->get_dimensions) {
u32 w, h;
display->driver->get_dimensions(display, &w, &h);
p.display_info.width = w;
p.display_info.height = h;
} else {
p.display_info.width = 0;
p.display_info.height = 0;
}
if (copy_to_user((void __user *)arg, &p.display_info,
sizeof(p.display_info)))
r = -EFAULT;
break;
}
default:
dev_err(fbdev->dev, "Unknown ioctl 0x%x\n", cmd);
r = -EINVAL;
}
if (r < 0)
DBG("ioctl failed: %d\n", r);
return r;
}
| linux-master | drivers/video/fbdev/omap2/omapfb/omapfb-ioctl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* VRFB Rotation Engine
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*/
/*#define DEBUG*/
#include <linux/err.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <video/omapvrfb.h>
#ifdef DEBUG
#define DBG(format, ...) pr_debug("VRFB: " format, ## __VA_ARGS__)
#else
#define DBG(format, ...)
#endif
#define SMS_ROT_CONTROL(context) (0x0 + 0x10 * context)
#define SMS_ROT_SIZE(context) (0x4 + 0x10 * context)
#define SMS_ROT_PHYSICAL_BA(context) (0x8 + 0x10 * context)
#define SMS_ROT_VIRT_BASE(rot) (0x1000000 * (rot))
#define OMAP_VRFB_SIZE (2048 * 2048 * 4)
#define VRFB_PAGE_WIDTH_EXP 5 /* Assuming SDRAM pagesize= 1024 */
#define VRFB_PAGE_HEIGHT_EXP 5 /* 1024 = 2^5 * 2^5 */
#define VRFB_PAGE_WIDTH (1 << VRFB_PAGE_WIDTH_EXP)
#define VRFB_PAGE_HEIGHT (1 << VRFB_PAGE_HEIGHT_EXP)
#define SMS_IMAGEHEIGHT_OFFSET 16
#define SMS_IMAGEWIDTH_OFFSET 0
#define SMS_PH_OFFSET 8
#define SMS_PW_OFFSET 4
#define SMS_PS_OFFSET 0
/* bitmap of reserved contexts */
static unsigned long ctx_map;
struct vrfb_ctx {
u32 base;
u32 physical_ba;
u32 control;
u32 size;
};
static DEFINE_MUTEX(ctx_lock);
/*
* Access to this happens from client drivers or the PM core after wake-up.
* For the first case we require locking at the driver level, for the second
* we don't need locking, since no drivers will run until after the wake-up
* has finished.
*/
static void __iomem *vrfb_base;
static int num_ctxs;
static struct vrfb_ctx *ctxs;
static bool vrfb_loaded;
static void omap2_sms_write_rot_control(u32 val, unsigned ctx)
{
__raw_writel(val, vrfb_base + SMS_ROT_CONTROL(ctx));
}
static void omap2_sms_write_rot_size(u32 val, unsigned ctx)
{
__raw_writel(val, vrfb_base + SMS_ROT_SIZE(ctx));
}
static void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
{
__raw_writel(val, vrfb_base + SMS_ROT_PHYSICAL_BA(ctx));
}
static inline void restore_hw_context(int ctx)
{
omap2_sms_write_rot_control(ctxs[ctx].control, ctx);
omap2_sms_write_rot_size(ctxs[ctx].size, ctx);
omap2_sms_write_rot_physical_ba(ctxs[ctx].physical_ba, ctx);
}
static u32 get_image_width_roundup(u16 width, u8 bytespp)
{
unsigned long stride = width * bytespp;
unsigned long ceil_pages_per_stride = (stride / VRFB_PAGE_WIDTH) +
(stride % VRFB_PAGE_WIDTH != 0);
return ceil_pages_per_stride * VRFB_PAGE_WIDTH / bytespp;
}
/*
* This the extra space needed in the VRFB physical area for VRFB to safely wrap
* any memory accesses to the invisible part of the virtual view to the physical
* area.
*/
static inline u32 get_extra_physical_size(u16 image_width_roundup, u8 bytespp)
{
return (OMAP_VRFB_LINE_LEN - image_width_roundup) * VRFB_PAGE_HEIGHT *
bytespp;
}
void omap_vrfb_restore_context(void)
{
int i;
unsigned long map = ctx_map;
for (i = ffs(map); i; i = ffs(map)) {
/* i=1..32 */
i--;
map &= ~(1 << i);
restore_hw_context(i);
}
}
void omap_vrfb_adjust_size(u16 *width, u16 *height,
u8 bytespp)
{
*width = ALIGN(*width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
*height = ALIGN(*height, VRFB_PAGE_HEIGHT);
}
EXPORT_SYMBOL(omap_vrfb_adjust_size);
u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
{
unsigned long image_width_roundup = get_image_width_roundup(width,
bytespp);
if (image_width_roundup > OMAP_VRFB_LINE_LEN)
return 0;
return (width * height * bytespp) + get_extra_physical_size(
image_width_roundup, bytespp);
}
EXPORT_SYMBOL(omap_vrfb_min_phys_size);
u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
{
unsigned long image_width_roundup = get_image_width_roundup(width,
bytespp);
unsigned long height;
unsigned long extra;
if (image_width_roundup > OMAP_VRFB_LINE_LEN)
return 0;
extra = get_extra_physical_size(image_width_roundup, bytespp);
if (phys_size < extra)
return 0;
height = (phys_size - extra) / (width * bytespp);
/* Virtual views provided by VRFB are limited to 2048x2048. */
return min_t(unsigned long, height, 2048);
}
EXPORT_SYMBOL(omap_vrfb_max_height);
void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
u16 width, u16 height,
unsigned bytespp, bool yuv_mode)
{
unsigned pixel_size_exp;
u16 vrfb_width;
u16 vrfb_height;
u8 ctx = vrfb->context;
u32 size;
u32 control;
DBG("omapfb_set_vrfb(%d, %lx, %dx%d, %d, %d)\n", ctx, paddr,
width, height, bytespp, yuv_mode);
/* For YUV2 and UYVY modes VRFB needs to handle pixels a bit
* differently. See TRM. */
if (yuv_mode) {
bytespp *= 2;
width /= 2;
}
if (bytespp == 4)
pixel_size_exp = 2;
else if (bytespp == 2)
pixel_size_exp = 1;
else {
BUG();
return;
}
vrfb_width = ALIGN(width * bytespp, VRFB_PAGE_WIDTH) / bytespp;
vrfb_height = ALIGN(height, VRFB_PAGE_HEIGHT);
DBG("vrfb w %u, h %u bytespp %d\n", vrfb_width, vrfb_height, bytespp);
size = vrfb_width << SMS_IMAGEWIDTH_OFFSET;
size |= vrfb_height << SMS_IMAGEHEIGHT_OFFSET;
control = pixel_size_exp << SMS_PS_OFFSET;
control |= VRFB_PAGE_WIDTH_EXP << SMS_PW_OFFSET;
control |= VRFB_PAGE_HEIGHT_EXP << SMS_PH_OFFSET;
ctxs[ctx].physical_ba = paddr;
ctxs[ctx].size = size;
ctxs[ctx].control = control;
omap2_sms_write_rot_physical_ba(paddr, ctx);
omap2_sms_write_rot_size(size, ctx);
omap2_sms_write_rot_control(control, ctx);
DBG("vrfb offset pixels %d, %d\n",
vrfb_width - width, vrfb_height - height);
vrfb->xres = width;
vrfb->yres = height;
vrfb->xoffset = vrfb_width - width;
vrfb->yoffset = vrfb_height - height;
vrfb->bytespp = bytespp;
vrfb->yuv_mode = yuv_mode;
}
EXPORT_SYMBOL(omap_vrfb_setup);
int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
{
unsigned long size = height * OMAP_VRFB_LINE_LEN * vrfb->bytespp;
vrfb->vaddr[rot] = ioremap_wc(vrfb->paddr[rot], size);
if (!vrfb->vaddr[rot]) {
printk(KERN_ERR "vrfb: ioremap failed\n");
return -ENOMEM;
}
DBG("ioremapped vrfb area %d of size %lu into %p\n", rot, size,
vrfb->vaddr[rot]);
return 0;
}
EXPORT_SYMBOL(omap_vrfb_map_angle);
void omap_vrfb_release_ctx(struct vrfb *vrfb)
{
int rot;
int ctx = vrfb->context;
if (ctx == 0xff)
return;
DBG("release ctx %d\n", ctx);
mutex_lock(&ctx_lock);
BUG_ON(!(ctx_map & (1 << ctx)));
clear_bit(ctx, &ctx_map);
for (rot = 0; rot < 4; ++rot) {
if (vrfb->paddr[rot]) {
release_mem_region(vrfb->paddr[rot], OMAP_VRFB_SIZE);
vrfb->paddr[rot] = 0;
}
}
vrfb->context = 0xff;
mutex_unlock(&ctx_lock);
}
EXPORT_SYMBOL(omap_vrfb_release_ctx);
int omap_vrfb_request_ctx(struct vrfb *vrfb)
{
int rot;
u32 paddr;
u8 ctx;
int r;
DBG("request ctx\n");
mutex_lock(&ctx_lock);
for (ctx = 0; ctx < num_ctxs; ++ctx)
if ((ctx_map & (1 << ctx)) == 0)
break;
if (ctx == num_ctxs) {
pr_err("vrfb: no free contexts\n");
r = -EBUSY;
goto out;
}
DBG("found free ctx %d\n", ctx);
set_bit(ctx, &ctx_map);
memset(vrfb, 0, sizeof(*vrfb));
vrfb->context = ctx;
for (rot = 0; rot < 4; ++rot) {
paddr = ctxs[ctx].base + SMS_ROT_VIRT_BASE(rot);
if (!request_mem_region(paddr, OMAP_VRFB_SIZE, "vrfb")) {
pr_err("vrfb: failed to reserve VRFB "
"area for ctx %d, rotation %d\n",
ctx, rot * 90);
omap_vrfb_release_ctx(vrfb);
r = -ENOMEM;
goto out;
}
vrfb->paddr[rot] = paddr;
DBG("VRFB %d/%d: %lx\n", ctx, rot*90, vrfb->paddr[rot]);
}
r = 0;
out:
mutex_unlock(&ctx_lock);
return r;
}
EXPORT_SYMBOL(omap_vrfb_request_ctx);
bool omap_vrfb_supported(void)
{
return vrfb_loaded;
}
EXPORT_SYMBOL(omap_vrfb_supported);
static int __init vrfb_probe(struct platform_device *pdev)
{
struct resource *mem;
int i;
/* first resource is the register res, the rest are vrfb contexts */
vrfb_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(vrfb_base))
return PTR_ERR(vrfb_base);
num_ctxs = pdev->num_resources - 1;
ctxs = devm_kcalloc(&pdev->dev,
num_ctxs, sizeof(struct vrfb_ctx),
GFP_KERNEL);
if (!ctxs)
return -ENOMEM;
for (i = 0; i < num_ctxs; ++i) {
mem = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
if (!mem) {
dev_err(&pdev->dev, "can't get vrfb ctx %d address\n",
i);
return -EINVAL;
}
ctxs[i].base = mem->start;
}
vrfb_loaded = true;
return 0;
}
static void __exit vrfb_remove(struct platform_device *pdev)
{
vrfb_loaded = false;
}
static struct platform_driver vrfb_driver = {
.driver.name = "omapvrfb",
.remove = __exit_p(vrfb_remove),
};
module_platform_driver_probe(vrfb_driver, vrfb_probe);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("OMAP VRFB");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/omap2/omapfb/vrfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/omapfb-sysfs.c
*
* Copyright (C) 2008 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#include <linux/fb.h>
#include <linux/sysfs.h>
#include <linux/device.h>
#include <linux/uaccess.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/kstrtox.h>
#include <linux/mm.h>
#include <linux/omapfb.h>
#include <video/omapfb_dss.h>
#include <video/omapvrfb.h>
#include "omapfb.h"
static ssize_t show_rotate_type(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
return sysfs_emit(buf, "%d\n", ofbi->rotation_type);
}
static ssize_t store_rotate_type(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_mem_region *rg;
int rot_type;
int r;
r = kstrtoint(buf, 0, &rot_type);
if (r)
return r;
if (rot_type != OMAP_DSS_ROT_DMA && rot_type != OMAP_DSS_ROT_VRFB)
return -EINVAL;
lock_fb_info(fbi);
r = 0;
if (rot_type == ofbi->rotation_type)
goto out;
rg = omapfb_get_mem_region(ofbi->region);
if (rg->size) {
r = -EBUSY;
goto put_region;
}
ofbi->rotation_type = rot_type;
/*
* Since the VRAM for this FB is not allocated at the moment we don't
* need to do any further parameter checking at this point.
*/
put_region:
omapfb_put_mem_region(rg);
out:
unlock_fb_info(fbi);
return r ? r : count;
}
static ssize_t show_mirror(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
return sysfs_emit(buf, "%d\n", ofbi->mirror);
}
static ssize_t store_mirror(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
bool mirror;
int r;
struct fb_var_screeninfo new_var;
r = kstrtobool(buf, &mirror);
if (r)
return r;
lock_fb_info(fbi);
ofbi->mirror = mirror;
omapfb_get_mem_region(ofbi->region);
memcpy(&new_var, &fbi->var, sizeof(new_var));
r = check_fb_var(fbi, &new_var);
if (r)
goto out;
memcpy(&fbi->var, &new_var, sizeof(fbi->var));
set_fb_fix(fbi);
r = omapfb_apply_changes(fbi, 0);
if (r)
goto out;
r = count;
out:
omapfb_put_mem_region(ofbi->region);
unlock_fb_info(fbi);
return r;
}
static ssize_t show_overlays(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
ssize_t l = 0;
int t;
lock_fb_info(fbi);
omapfb_lock(fbdev);
for (t = 0; t < ofbi->num_overlays; t++) {
struct omap_overlay *ovl = ofbi->overlays[t];
int ovlnum;
for (ovlnum = 0; ovlnum < fbdev->num_overlays; ++ovlnum)
if (ovl == fbdev->overlays[ovlnum])
break;
l += scnprintf(buf + l, PAGE_SIZE - l, "%s%d",
t == 0 ? "" : ",", ovlnum);
}
l += scnprintf(buf + l, PAGE_SIZE - l, "\n");
omapfb_unlock(fbdev);
unlock_fb_info(fbi);
return l;
}
static struct omapfb_info *get_overlay_fb(struct omapfb2_device *fbdev,
struct omap_overlay *ovl)
{
int i, t;
for (i = 0; i < fbdev->num_fbs; i++) {
struct omapfb_info *ofbi = FB2OFB(fbdev->fbs[i]);
for (t = 0; t < ofbi->num_overlays; t++) {
if (ofbi->overlays[t] == ovl)
return ofbi;
}
}
return NULL;
}
static ssize_t store_overlays(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_overlay *ovls[OMAPFB_MAX_OVL_PER_FB];
struct omap_overlay *ovl;
int num_ovls, r, i;
int len;
bool added = false;
num_ovls = 0;
len = strlen(buf);
if (buf[len - 1] == '\n')
len = len - 1;
lock_fb_info(fbi);
omapfb_lock(fbdev);
if (len > 0) {
char *p = (char *)buf;
int ovlnum;
while (p < buf + len) {
int found;
if (num_ovls == OMAPFB_MAX_OVL_PER_FB) {
r = -EINVAL;
goto out;
}
ovlnum = simple_strtoul(p, &p, 0);
if (ovlnum > fbdev->num_overlays) {
r = -EINVAL;
goto out;
}
found = 0;
for (i = 0; i < num_ovls; ++i) {
if (ovls[i] == fbdev->overlays[ovlnum]) {
found = 1;
break;
}
}
if (!found)
ovls[num_ovls++] = fbdev->overlays[ovlnum];
p++;
}
}
for (i = 0; i < num_ovls; ++i) {
struct omapfb_info *ofbi2 = get_overlay_fb(fbdev, ovls[i]);
if (ofbi2 && ofbi2 != ofbi) {
dev_err(fbdev->dev, "overlay already in use\n");
r = -EINVAL;
goto out;
}
}
/* detach unused overlays */
for (i = 0; i < ofbi->num_overlays; ++i) {
int t, found;
ovl = ofbi->overlays[i];
found = 0;
for (t = 0; t < num_ovls; ++t) {
if (ovl == ovls[t]) {
found = 1;
break;
}
}
if (found)
continue;
DBG("detaching %d\n", ofbi->overlays[i]->id);
omapfb_get_mem_region(ofbi->region);
omapfb_overlay_enable(ovl, 0);
if (ovl->manager)
ovl->manager->apply(ovl->manager);
omapfb_put_mem_region(ofbi->region);
for (t = i + 1; t < ofbi->num_overlays; t++) {
ofbi->rotation[t-1] = ofbi->rotation[t];
ofbi->overlays[t-1] = ofbi->overlays[t];
}
ofbi->num_overlays--;
i--;
}
for (i = 0; i < num_ovls; ++i) {
int t, found;
ovl = ovls[i];
found = 0;
for (t = 0; t < ofbi->num_overlays; ++t) {
if (ovl == ofbi->overlays[t]) {
found = 1;
break;
}
}
if (found)
continue;
ofbi->rotation[ofbi->num_overlays] = 0;
ofbi->overlays[ofbi->num_overlays++] = ovl;
added = true;
}
if (added) {
omapfb_get_mem_region(ofbi->region);
r = omapfb_apply_changes(fbi, 0);
omapfb_put_mem_region(ofbi->region);
if (r)
goto out;
}
r = count;
out:
omapfb_unlock(fbdev);
unlock_fb_info(fbi);
return r;
}
static ssize_t show_overlays_rotate(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
ssize_t l = 0;
int t;
lock_fb_info(fbi);
for (t = 0; t < ofbi->num_overlays; t++) {
l += scnprintf(buf + l, PAGE_SIZE - l, "%s%d",
t == 0 ? "" : ",", ofbi->rotation[t]);
}
l += scnprintf(buf + l, PAGE_SIZE - l, "\n");
unlock_fb_info(fbi);
return l;
}
static ssize_t store_overlays_rotate(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
int num_ovls = 0, r, i;
int len;
bool changed = false;
u8 rotation[OMAPFB_MAX_OVL_PER_FB];
len = strlen(buf);
if (buf[len - 1] == '\n')
len = len - 1;
lock_fb_info(fbi);
if (len > 0) {
char *p = (char *)buf;
while (p < buf + len) {
int rot;
if (num_ovls == ofbi->num_overlays) {
r = -EINVAL;
goto out;
}
rot = simple_strtoul(p, &p, 0);
if (rot < 0 || rot > 3) {
r = -EINVAL;
goto out;
}
if (ofbi->rotation[num_ovls] != rot)
changed = true;
rotation[num_ovls++] = rot;
p++;
}
}
if (num_ovls != ofbi->num_overlays) {
r = -EINVAL;
goto out;
}
if (changed) {
for (i = 0; i < num_ovls; ++i)
ofbi->rotation[i] = rotation[i];
omapfb_get_mem_region(ofbi->region);
r = omapfb_apply_changes(fbi, 0);
omapfb_put_mem_region(ofbi->region);
if (r)
goto out;
/* FIXME error handling? */
}
r = count;
out:
unlock_fb_info(fbi);
return r;
}
static ssize_t show_size(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
return sysfs_emit(buf, "%lu\n", ofbi->region->size);
}
static ssize_t store_size(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_dss_device *display = fb2display(fbi);
struct omapfb2_mem_region *rg;
unsigned long size;
int r;
int i;
r = kstrtoul(buf, 0, &size);
if (r)
return r;
size = PAGE_ALIGN(size);
lock_fb_info(fbi);
if (display && display->driver->sync)
display->driver->sync(display);
rg = ofbi->region;
down_write_nested(&rg->lock, rg->id);
atomic_inc(&rg->lock_count);
if (atomic_read(&rg->map_count)) {
r = -EBUSY;
goto out;
}
for (i = 0; i < fbdev->num_fbs; i++) {
struct omapfb_info *ofbi2 = FB2OFB(fbdev->fbs[i]);
int j;
if (ofbi2->region != rg)
continue;
for (j = 0; j < ofbi2->num_overlays; j++) {
struct omap_overlay *ovl;
ovl = ofbi2->overlays[j];
if (ovl->is_enabled(ovl)) {
r = -EBUSY;
goto out;
}
}
}
if (size != ofbi->region->size) {
r = omapfb_realloc_fbmem(fbi, size, ofbi->region->type);
if (r) {
dev_err(dev, "realloc fbmem failed\n");
goto out;
}
}
r = count;
out:
atomic_dec(&rg->lock_count);
up_write(&rg->lock);
unlock_fb_info(fbi);
return r;
}
static ssize_t show_phys(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
return sysfs_emit(buf, "%0x\n", ofbi->region->paddr);
}
static ssize_t show_virt(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
return sysfs_emit(buf, "%p\n", ofbi->region->vaddr);
}
static ssize_t show_upd_mode(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *fbi = dev_get_drvdata(dev);
enum omapfb_update_mode mode;
int r;
r = omapfb_get_update_mode(fbi, &mode);
if (r)
return r;
return sysfs_emit(buf, "%u\n", (unsigned int)mode);
}
static ssize_t store_upd_mode(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fbi = dev_get_drvdata(dev);
unsigned mode;
int r;
r = kstrtouint(buf, 0, &mode);
if (r)
return r;
r = omapfb_set_update_mode(fbi, mode);
if (r)
return r;
return count;
}
static struct device_attribute omapfb_attrs[] = {
__ATTR(rotate_type, S_IRUGO | S_IWUSR, show_rotate_type,
store_rotate_type),
__ATTR(mirror, S_IRUGO | S_IWUSR, show_mirror, store_mirror),
__ATTR(size, S_IRUGO | S_IWUSR, show_size, store_size),
__ATTR(overlays, S_IRUGO | S_IWUSR, show_overlays, store_overlays),
__ATTR(overlays_rotate, S_IRUGO | S_IWUSR, show_overlays_rotate,
store_overlays_rotate),
__ATTR(phys_addr, S_IRUGO, show_phys, NULL),
__ATTR(virt_addr, S_IRUGO, show_virt, NULL),
__ATTR(update_mode, S_IRUGO | S_IWUSR, show_upd_mode, store_upd_mode),
};
int omapfb_create_sysfs(struct omapfb2_device *fbdev)
{
int i;
int r;
DBG("create sysfs for fbs\n");
for (i = 0; i < fbdev->num_fbs; i++) {
int t;
for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++) {
r = device_create_file(fbdev->fbs[i]->dev,
&omapfb_attrs[t]);
if (r) {
dev_err(fbdev->dev, "failed to create sysfs "
"file\n");
return r;
}
}
}
return 0;
}
void omapfb_remove_sysfs(struct omapfb2_device *fbdev)
{
int i, t;
DBG("remove sysfs for fbs\n");
for (i = 0; i < fbdev->num_fbs; i++) {
for (t = 0; t < ARRAY_SIZE(omapfb_attrs); t++)
device_remove_file(fbdev->fbs[i]->dev,
&omapfb_attrs[t]);
}
}
| linux-master | drivers/video/fbdev/omap2/omapfb/omapfb-sysfs.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HDMI Connector driver
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <drm/drm_edid.h>
#include <video/omapfb_dss.h>
static const struct omap_video_timings hdmic_default_timings = {
.x_res = 640,
.y_res = 480,
.pixelclock = 25175000,
.hsw = 96,
.hfp = 16,
.hbp = 48,
.vsw = 2,
.vfp = 11,
.vbp = 31,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.interlace = false,
};
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct device *dev;
struct omap_video_timings timings;
struct gpio_desc *hpd_gpio;
};
#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
static int hdmic_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(ddata->dev, "connect\n");
if (omapdss_device_is_connected(dssdev))
return 0;
return in->ops.hdmi->connect(in, dssdev);
}
static void hdmic_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(ddata->dev, "disconnect\n");
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.hdmi->disconnect(in, dssdev);
}
static int hdmic_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
dev_dbg(ddata->dev, "enable\n");
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
in->ops.hdmi->set_timings(in, &ddata->timings);
r = in->ops.hdmi->enable(in);
if (r)
return r;
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return r;
}
static void hdmic_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(ddata->dev, "disable\n");
if (!omapdss_device_is_enabled(dssdev))
return;
in->ops.hdmi->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void hdmic_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->timings = *timings;
dssdev->panel.timings = *timings;
in->ops.hdmi->set_timings(in, timings);
}
static void hdmic_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->timings;
}
static int hdmic_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.hdmi->check_timings(in, timings);
}
static int hdmic_read_edid(struct omap_dss_device *dssdev,
u8 *edid, int len)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.hdmi->read_edid(in, edid, len);
}
static bool hdmic_detect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (ddata->hpd_gpio)
return gpiod_get_value_cansleep(ddata->hpd_gpio);
else
return in->ops.hdmi->detect(in);
}
static int hdmic_set_hdmi_mode(struct omap_dss_device *dssdev, bool hdmi_mode)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.hdmi->set_hdmi_mode(in, hdmi_mode);
}
static int hdmic_set_infoframe(struct omap_dss_device *dssdev,
const struct hdmi_avi_infoframe *avi)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.hdmi->set_infoframe(in, avi);
}
static struct omap_dss_driver hdmic_driver = {
.connect = hdmic_connect,
.disconnect = hdmic_disconnect,
.enable = hdmic_enable,
.disable = hdmic_disable,
.set_timings = hdmic_set_timings,
.get_timings = hdmic_get_timings,
.check_timings = hdmic_check_timings,
.get_resolution = omapdss_default_get_resolution,
.read_edid = hdmic_read_edid,
.detect = hdmic_detect,
.set_hdmi_mode = hdmic_set_hdmi_mode,
.set_hdmi_infoframe = hdmic_set_infoframe,
};
static int hdmic_probe(struct platform_device *pdev)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
if (!pdev->dev.of_node)
return -ENODEV;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
ddata->dev = &pdev->dev;
ddata->hpd_gpio = devm_gpiod_get_optional(&pdev->dev, "hpd", GPIOD_IN);
r = PTR_ERR_OR_ZERO(ddata->hpd_gpio);
if (r)
return r;
gpiod_set_consumer_name(ddata->hpd_gpio, "hdmi_hpd");
ddata->in = omapdss_of_find_source_for_first_ep(pdev->dev.of_node);
r = PTR_ERR_OR_ZERO(ddata->in);
if (r) {
dev_err(&pdev->dev, "failed to find video source\n");
return r;
}
ddata->timings = hdmic_default_timings;
dssdev = &ddata->dssdev;
dssdev->driver = &hdmic_driver;
dssdev->dev = &pdev->dev;
dssdev->type = OMAP_DISPLAY_TYPE_HDMI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = hdmic_default_timings;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&pdev->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
return r;
}
static int __exit hdmic_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_display(&ddata->dssdev);
hdmic_disable(dssdev);
hdmic_disconnect(dssdev);
omap_dss_put_device(in);
return 0;
}
static const struct of_device_id hdmic_of_match[] = {
{ .compatible = "omapdss,hdmi-connector", },
{},
};
MODULE_DEVICE_TABLE(of, hdmic_of_match);
static struct platform_driver hdmi_connector_driver = {
.probe = hdmic_probe,
.remove = __exit_p(hdmic_remove),
.driver = {
.name = "connector-hdmi",
.of_match_table = hdmic_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(hdmi_connector_driver);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("HDMI Connector driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/connector-hdmi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Generic DVI Connector driver
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <drm/drm_edid.h>
#include <video/omapfb_dss.h>
static const struct omap_video_timings dvic_default_timings = {
.x_res = 640,
.y_res = 480,
.pixelclock = 23500000,
.hfp = 48,
.hsw = 32,
.hbp = 80,
.vfp = 3,
.vsw = 4,
.vbp = 7,
.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
};
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct omap_video_timings timings;
struct i2c_adapter *i2c_adapter;
};
#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
static int dvic_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (omapdss_device_is_connected(dssdev))
return 0;
return in->ops.dvi->connect(in, dssdev);
}
static void dvic_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.dvi->disconnect(in, dssdev);
}
static int dvic_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
in->ops.dvi->set_timings(in, &ddata->timings);
r = in->ops.dvi->enable(in);
if (r)
return r;
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void dvic_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_enabled(dssdev))
return;
in->ops.dvi->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void dvic_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->timings = *timings;
dssdev->panel.timings = *timings;
in->ops.dvi->set_timings(in, timings);
}
static void dvic_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->timings;
}
static int dvic_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.dvi->check_timings(in, timings);
}
static int dvic_ddc_read(struct i2c_adapter *adapter,
unsigned char *buf, u16 count, u8 offset)
{
int r, retries;
for (retries = 3; retries > 0; retries--) {
struct i2c_msg msgs[] = {
{
.addr = DDC_ADDR,
.flags = 0,
.len = 1,
.buf = &offset,
}, {
.addr = DDC_ADDR,
.flags = I2C_M_RD,
.len = count,
.buf = buf,
}
};
r = i2c_transfer(adapter, msgs, 2);
if (r == 2)
return 0;
if (r != -EAGAIN)
break;
}
return r < 0 ? r : -EIO;
}
static int dvic_read_edid(struct omap_dss_device *dssdev,
u8 *edid, int len)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
int r, l, bytes_read;
if (!ddata->i2c_adapter)
return -ENODEV;
l = min(EDID_LENGTH, len);
r = dvic_ddc_read(ddata->i2c_adapter, edid, l, 0);
if (r)
return r;
bytes_read = l;
/* if there are extensions, read second block */
if (len > EDID_LENGTH && edid[0x7e] > 0) {
l = min(EDID_LENGTH, len - EDID_LENGTH);
r = dvic_ddc_read(ddata->i2c_adapter, edid + EDID_LENGTH,
l, EDID_LENGTH);
if (r)
return r;
bytes_read += l;
}
return bytes_read;
}
static bool dvic_detect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
unsigned char out;
int r;
if (!ddata->i2c_adapter)
return true;
r = dvic_ddc_read(ddata->i2c_adapter, &out, 1, 0);
return r == 0;
}
static struct omap_dss_driver dvic_driver = {
.connect = dvic_connect,
.disconnect = dvic_disconnect,
.enable = dvic_enable,
.disable = dvic_disable,
.set_timings = dvic_set_timings,
.get_timings = dvic_get_timings,
.check_timings = dvic_check_timings,
.get_resolution = omapdss_default_get_resolution,
.read_edid = dvic_read_edid,
.detect = dvic_detect,
};
static int dvic_probe_of(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
struct omap_dss_device *in;
struct device_node *adapter_node;
struct i2c_adapter *adapter;
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&pdev->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
adapter_node = of_parse_phandle(node, "ddc-i2c-bus", 0);
if (adapter_node) {
adapter = of_get_i2c_adapter_by_node(adapter_node);
of_node_put(adapter_node);
if (adapter == NULL) {
dev_err(&pdev->dev, "failed to parse ddc-i2c-bus\n");
omap_dss_put_device(ddata->in);
return -EPROBE_DEFER;
}
ddata->i2c_adapter = adapter;
}
return 0;
}
static int dvic_probe(struct platform_device *pdev)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
if (!pdev->dev.of_node)
return -ENODEV;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
r = dvic_probe_of(pdev);
if (r)
return r;
ddata->timings = dvic_default_timings;
dssdev = &ddata->dssdev;
dssdev->driver = &dvic_driver;
dssdev->dev = &pdev->dev;
dssdev->type = OMAP_DISPLAY_TYPE_DVI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = dvic_default_timings;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&pdev->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
i2c_put_adapter(ddata->i2c_adapter);
return r;
}
static int __exit dvic_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_display(&ddata->dssdev);
dvic_disable(dssdev);
dvic_disconnect(dssdev);
omap_dss_put_device(in);
i2c_put_adapter(ddata->i2c_adapter);
return 0;
}
static const struct of_device_id dvic_of_match[] = {
{ .compatible = "omapdss,dvi-connector", },
{},
};
MODULE_DEVICE_TABLE(of, dvic_of_match);
static struct platform_driver dvi_connector_driver = {
.probe = dvic_probe,
.remove = __exit_p(dvic_remove),
.driver = {
.name = "connector-dvi",
.of_match_table = dvic_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(dvi_connector_driver);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("Generic DVI Connector driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/connector-dvi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Toppoly TD028TTEC1 panel support
*
* Copyright (C) 2008 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Neo 1973 code (jbt6k74.c):
* Copyright (C) 2006-2007 by OpenMoko, Inc.
* Author: Harald Welte <[email protected]>
*
* Ported and adapted from Neo 1973 U-Boot by:
* H. Nikolaus Schaller <[email protected]>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <video/omapfb_dss.h>
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
int data_lines;
struct omap_video_timings videomode;
struct spi_device *spi_dev;
};
static const struct omap_video_timings td028ttec1_panel_timings = {
.x_res = 480,
.y_res = 640,
.pixelclock = 22153000,
.hfp = 24,
.hsw = 8,
.hbp = 8,
.vfp = 4,
.vsw = 2,
.vbp = 2,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
};
#define JBT_COMMAND 0x000
#define JBT_DATA 0x100
static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
{
int rc;
u16 tx_buf = JBT_COMMAND | reg;
rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
1*sizeof(u16));
if (rc != 0)
dev_err(&ddata->spi_dev->dev,
"jbt_ret_write_0 spi_write ret %d\n", rc);
return rc;
}
static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
{
int rc;
u16 tx_buf[2];
tx_buf[0] = JBT_COMMAND | reg;
tx_buf[1] = JBT_DATA | data;
rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
2*sizeof(u16));
if (rc != 0)
dev_err(&ddata->spi_dev->dev,
"jbt_reg_write_1 spi_write ret %d\n", rc);
return rc;
}
static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
{
int rc;
u16 tx_buf[3];
tx_buf[0] = JBT_COMMAND | reg;
tx_buf[1] = JBT_DATA | (data >> 8);
tx_buf[2] = JBT_DATA | (data & 0xff);
rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
3*sizeof(u16));
if (rc != 0)
dev_err(&ddata->spi_dev->dev,
"jbt_reg_write_2 spi_write ret %d\n", rc);
return rc;
}
enum jbt_register {
JBT_REG_SLEEP_IN = 0x10,
JBT_REG_SLEEP_OUT = 0x11,
JBT_REG_DISPLAY_OFF = 0x28,
JBT_REG_DISPLAY_ON = 0x29,
JBT_REG_RGB_FORMAT = 0x3a,
JBT_REG_QUAD_RATE = 0x3b,
JBT_REG_POWER_ON_OFF = 0xb0,
JBT_REG_BOOSTER_OP = 0xb1,
JBT_REG_BOOSTER_MODE = 0xb2,
JBT_REG_BOOSTER_FREQ = 0xb3,
JBT_REG_OPAMP_SYSCLK = 0xb4,
JBT_REG_VSC_VOLTAGE = 0xb5,
JBT_REG_VCOM_VOLTAGE = 0xb6,
JBT_REG_EXT_DISPL = 0xb7,
JBT_REG_OUTPUT_CONTROL = 0xb8,
JBT_REG_DCCLK_DCEV = 0xb9,
JBT_REG_DISPLAY_MODE1 = 0xba,
JBT_REG_DISPLAY_MODE2 = 0xbb,
JBT_REG_DISPLAY_MODE = 0xbc,
JBT_REG_ASW_SLEW = 0xbd,
JBT_REG_DUMMY_DISPLAY = 0xbe,
JBT_REG_DRIVE_SYSTEM = 0xbf,
JBT_REG_SLEEP_OUT_FR_A = 0xc0,
JBT_REG_SLEEP_OUT_FR_B = 0xc1,
JBT_REG_SLEEP_OUT_FR_C = 0xc2,
JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
JBT_REG_GAMMA1_FINE_1 = 0xc7,
JBT_REG_GAMMA1_FINE_2 = 0xc8,
JBT_REG_GAMMA1_INCLINATION = 0xc9,
JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
JBT_REG_BLANK_CONTROL = 0xcf,
JBT_REG_BLANK_TH_TV = 0xd0,
JBT_REG_CKV_ON_OFF = 0xd1,
JBT_REG_CKV_1_2 = 0xd2,
JBT_REG_OEV_TIMING = 0xd3,
JBT_REG_ASW_TIMING_1 = 0xd4,
JBT_REG_ASW_TIMING_2 = 0xd5,
JBT_REG_HCLOCK_VGA = 0xec,
JBT_REG_HCLOCK_QVGA = 0xed,
};
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (omapdss_device_is_connected(dssdev))
return 0;
r = in->ops.dpi->connect(in, dssdev);
if (r)
return r;
return 0;
}
static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.dpi->disconnect(in, dssdev);
}
static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
if (ddata->data_lines)
in->ops.dpi->set_data_lines(in, ddata->data_lines);
in->ops.dpi->set_timings(in, &ddata->videomode);
r = in->ops.dpi->enable(in);
if (r)
return r;
dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
dssdev->state);
/* three times command zero */
r |= jbt_ret_write_0(ddata, 0x00);
usleep_range(1000, 2000);
r |= jbt_ret_write_0(ddata, 0x00);
usleep_range(1000, 2000);
r |= jbt_ret_write_0(ddata, 0x00);
usleep_range(1000, 2000);
if (r) {
dev_warn(dssdev->dev, "transfer error\n");
goto transfer_err;
}
/* deep standby out */
r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
/* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
/* Quad mode off */
r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
/* AVDD on, XVDD on */
r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
/* Output control */
r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
/* Sleep mode off */
r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
/* at this point we have like 50% grey */
/* initialize register set */
r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
/*
* default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
* to avoid red / blue flicker
*/
r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
transfer_err:
return r ? -EIO : 0;
}
static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_enabled(dssdev))
return;
dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
in->ops.dpi->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->videomode = *timings;
dssdev->panel.timings = *timings;
in->ops.dpi->set_timings(in, timings);
}
static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->videomode;
}
static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.dpi->check_timings(in, timings);
}
static struct omap_dss_driver td028ttec1_ops = {
.connect = td028ttec1_panel_connect,
.disconnect = td028ttec1_panel_disconnect,
.enable = td028ttec1_panel_enable,
.disable = td028ttec1_panel_disable,
.set_timings = td028ttec1_panel_set_timings,
.get_timings = td028ttec1_panel_get_timings,
.check_timings = td028ttec1_panel_check_timings,
};
static int td028ttec1_probe_of(struct spi_device *spi)
{
struct device_node *node = spi->dev.of_node;
struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
struct omap_dss_device *in;
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&spi->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
return 0;
}
static int td028ttec1_panel_probe(struct spi_device *spi)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
dev_dbg(&spi->dev, "%s\n", __func__);
if (!spi->dev.of_node)
return -ENODEV;
spi->bits_per_word = 9;
spi->mode = SPI_MODE_3;
r = spi_setup(spi);
if (r < 0) {
dev_err(&spi->dev, "spi_setup failed: %d\n", r);
return r;
}
ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
if (ddata == NULL)
return -ENOMEM;
dev_set_drvdata(&spi->dev, ddata);
ddata->spi_dev = spi;
r = td028ttec1_probe_of(spi);
if (r)
return r;
ddata->videomode = td028ttec1_panel_timings;
dssdev = &ddata->dssdev;
dssdev->dev = &spi->dev;
dssdev->driver = &td028ttec1_ops;
dssdev->type = OMAP_DISPLAY_TYPE_DPI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = ddata->videomode;
dssdev->phy.dpi.data_lines = ddata->data_lines;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&spi->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
return r;
}
static void td028ttec1_panel_remove(struct spi_device *spi)
{
struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
omapdss_unregister_display(dssdev);
td028ttec1_panel_disable(dssdev);
td028ttec1_panel_disconnect(dssdev);
omap_dss_put_device(in);
}
static const struct of_device_id td028ttec1_of_match[] = {
{ .compatible = "omapdss,tpo,td028ttec1", },
/* keep to not break older DTB */
{ .compatible = "omapdss,toppoly,td028ttec1", },
{},
};
MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
static const struct spi_device_id td028ttec1_ids[] = {
{ "toppoly,td028ttec1", 0 },
{ "tpo,td028ttec1", 0},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
static struct spi_driver td028ttec1_spi_driver = {
.probe = td028ttec1_panel_probe,
.remove = td028ttec1_panel_remove,
.id_table = td028ttec1_ids,
.driver = {
.name = "panel-tpo-td028ttec1",
.of_match_table = td028ttec1_of_match,
.suppress_bind_attrs = true,
},
};
module_spi_driver(td028ttec1_spi_driver);
MODULE_AUTHOR("H. Nikolaus Schaller <[email protected]>");
MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td028ttec1.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Generic MIPI DPI Panel Driver
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <video/omapfb_dss.h>
#include <video/of_display_timing.h>
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
int data_lines;
struct omap_video_timings videomode;
struct gpio_desc *enable_gpio;
};
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
static int panel_dpi_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (omapdss_device_is_connected(dssdev))
return 0;
return in->ops.dpi->connect(in, dssdev);
}
static void panel_dpi_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.dpi->disconnect(in, dssdev);
}
static int panel_dpi_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
if (ddata->data_lines)
in->ops.dpi->set_data_lines(in, ddata->data_lines);
in->ops.dpi->set_timings(in, &ddata->videomode);
r = in->ops.dpi->enable(in);
if (r)
return r;
gpiod_set_value_cansleep(ddata->enable_gpio, 1);
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void panel_dpi_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_enabled(dssdev))
return;
gpiod_set_value_cansleep(ddata->enable_gpio, 0);
in->ops.dpi->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void panel_dpi_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->videomode = *timings;
dssdev->panel.timings = *timings;
in->ops.dpi->set_timings(in, timings);
}
static void panel_dpi_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->videomode;
}
static int panel_dpi_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.dpi->check_timings(in, timings);
}
static struct omap_dss_driver panel_dpi_ops = {
.connect = panel_dpi_connect,
.disconnect = panel_dpi_disconnect,
.enable = panel_dpi_enable,
.disable = panel_dpi_disable,
.set_timings = panel_dpi_set_timings,
.get_timings = panel_dpi_get_timings,
.check_timings = panel_dpi_check_timings,
.get_resolution = omapdss_default_get_resolution,
};
static int panel_dpi_probe_of(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
struct omap_dss_device *in;
int r;
struct display_timing timing;
struct videomode vm;
struct gpio_desc *gpio;
gpio = devm_gpiod_get_optional(&pdev->dev, "enable", GPIOD_OUT_LOW);
if (IS_ERR(gpio))
return PTR_ERR(gpio);
ddata->enable_gpio = gpio;
r = of_get_display_timing(node, "panel-timing", &timing);
if (r) {
dev_err(&pdev->dev, "failed to get video timing\n");
return r;
}
videomode_from_timing(&timing, &vm);
videomode_to_omap_video_timings(&vm, &ddata->videomode);
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&pdev->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
return 0;
}
static int panel_dpi_probe(struct platform_device *pdev)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
if (!pdev->dev.of_node)
return -ENODEV;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (ddata == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
r = panel_dpi_probe_of(pdev);
if (r)
return r;
dssdev = &ddata->dssdev;
dssdev->dev = &pdev->dev;
dssdev->driver = &panel_dpi_ops;
dssdev->type = OMAP_DISPLAY_TYPE_DPI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = ddata->videomode;
dssdev->phy.dpi.data_lines = ddata->data_lines;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&pdev->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
return r;
}
static int __exit panel_dpi_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_display(dssdev);
panel_dpi_disable(dssdev);
panel_dpi_disconnect(dssdev);
omap_dss_put_device(in);
return 0;
}
static const struct of_device_id panel_dpi_of_match[] = {
{ .compatible = "omapdss,panel-dpi", },
{},
};
MODULE_DEVICE_TABLE(of, panel_dpi_of_match);
static struct platform_driver panel_dpi_driver = {
.probe = panel_dpi_probe,
.remove = __exit_p(panel_dpi_remove),
.driver = {
.name = "panel-dpi",
.of_match_table = panel_dpi_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(panel_dpi_driver);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("Generic MIPI DPI Panel Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/panel-dpi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Analog TV Connector driver
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <video/omapfb_dss.h>
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct device *dev;
struct omap_video_timings timings;
bool invert_polarity;
};
static const struct omap_video_timings tvc_pal_timings = {
.x_res = 720,
.y_res = 574,
.pixelclock = 13500000,
.hsw = 64,
.hfp = 12,
.hbp = 68,
.vsw = 5,
.vfp = 5,
.vbp = 41,
.interlace = true,
};
static const struct of_device_id tvc_of_match[];
#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
static int tvc_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(ddata->dev, "connect\n");
if (omapdss_device_is_connected(dssdev))
return 0;
return in->ops.atv->connect(in, dssdev);
}
static void tvc_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(ddata->dev, "disconnect\n");
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.atv->disconnect(in, dssdev);
}
static int tvc_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
dev_dbg(ddata->dev, "enable\n");
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
in->ops.atv->set_timings(in, &ddata->timings);
if (!ddata->dev->of_node) {
in->ops.atv->set_type(in, OMAP_DSS_VENC_TYPE_COMPOSITE);
in->ops.atv->invert_vid_out_polarity(in,
ddata->invert_polarity);
}
r = in->ops.atv->enable(in);
if (r)
return r;
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return r;
}
static void tvc_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(ddata->dev, "disable\n");
if (!omapdss_device_is_enabled(dssdev))
return;
in->ops.atv->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void tvc_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->timings = *timings;
dssdev->panel.timings = *timings;
in->ops.atv->set_timings(in, timings);
}
static void tvc_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->timings;
}
static int tvc_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.atv->check_timings(in, timings);
}
static u32 tvc_get_wss(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.atv->get_wss(in);
}
static int tvc_set_wss(struct omap_dss_device *dssdev, u32 wss)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.atv->set_wss(in, wss);
}
static struct omap_dss_driver tvc_driver = {
.connect = tvc_connect,
.disconnect = tvc_disconnect,
.enable = tvc_enable,
.disable = tvc_disable,
.set_timings = tvc_set_timings,
.get_timings = tvc_get_timings,
.check_timings = tvc_check_timings,
.get_resolution = omapdss_default_get_resolution,
.get_wss = tvc_get_wss,
.set_wss = tvc_set_wss,
};
static int tvc_probe(struct platform_device *pdev)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
if (!pdev->dev.of_node)
return -ENODEV;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
ddata->dev = &pdev->dev;
ddata->in = omapdss_of_find_source_for_first_ep(pdev->dev.of_node);
r = PTR_ERR_OR_ZERO(ddata->in);
if (r) {
dev_err(&pdev->dev, "failed to find video source\n");
return r;
}
ddata->timings = tvc_pal_timings;
dssdev = &ddata->dssdev;
dssdev->driver = &tvc_driver;
dssdev->dev = &pdev->dev;
dssdev->type = OMAP_DISPLAY_TYPE_VENC;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = tvc_pal_timings;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&pdev->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
return r;
}
static int __exit tvc_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_display(&ddata->dssdev);
tvc_disable(dssdev);
tvc_disconnect(dssdev);
omap_dss_put_device(in);
return 0;
}
static const struct of_device_id tvc_of_match[] = {
{ .compatible = "omapdss,svideo-connector", },
{ .compatible = "omapdss,composite-video-connector", },
{},
};
MODULE_DEVICE_TABLE(of, tvc_of_match);
static struct platform_driver tvc_connector_driver = {
.probe = tvc_probe,
.remove = __exit_p(tvc_remove),
.driver = {
.name = "connector-analog-tv",
.of_match_table = tvc_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(tvc_connector_driver);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("Analog TV Connector driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/connector-analog-tv.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OPA362 analog video amplifier with output/power control
*
* Copyright (C) 2014 Golden Delicious Computers
* Author: H. Nikolaus Schaller <[email protected]>
*
* based on encoder-tfp410
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <video/omapfb_dss.h>
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct gpio_desc *enable_gpio;
struct omap_video_timings timings;
};
#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
static int opa362_connect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
dev_dbg(dssdev->dev, "connect\n");
if (omapdss_device_is_connected(dssdev))
return -EBUSY;
r = in->ops.atv->connect(in, dssdev);
if (r)
return r;
dst->src = dssdev;
dssdev->dst = dst;
return 0;
}
static void opa362_disconnect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(dssdev->dev, "disconnect\n");
WARN_ON(!omapdss_device_is_connected(dssdev));
if (!omapdss_device_is_connected(dssdev))
return;
WARN_ON(dst != dssdev->dst);
if (dst != dssdev->dst)
return;
dst->src = NULL;
dssdev->dst = NULL;
in->ops.atv->disconnect(in, &ddata->dssdev);
}
static int opa362_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
dev_dbg(dssdev->dev, "enable\n");
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
in->ops.atv->set_timings(in, &ddata->timings);
r = in->ops.atv->enable(in);
if (r)
return r;
if (ddata->enable_gpio)
gpiod_set_value_cansleep(ddata->enable_gpio, 1);
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void opa362_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(dssdev->dev, "disable\n");
if (!omapdss_device_is_enabled(dssdev))
return;
if (ddata->enable_gpio)
gpiod_set_value_cansleep(ddata->enable_gpio, 0);
in->ops.atv->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void opa362_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(dssdev->dev, "set_timings\n");
ddata->timings = *timings;
dssdev->panel.timings = *timings;
in->ops.atv->set_timings(in, timings);
}
static void opa362_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
dev_dbg(dssdev->dev, "get_timings\n");
*timings = ddata->timings;
}
static int opa362_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(dssdev->dev, "check_timings\n");
return in->ops.atv->check_timings(in, timings);
}
static void opa362_set_type(struct omap_dss_device *dssdev,
enum omap_dss_venc_type type)
{
/* we can only drive a COMPOSITE output */
WARN_ON(type != OMAP_DSS_VENC_TYPE_COMPOSITE);
}
static const struct omapdss_atv_ops opa362_atv_ops = {
.connect = opa362_connect,
.disconnect = opa362_disconnect,
.enable = opa362_enable,
.disable = opa362_disable,
.check_timings = opa362_check_timings,
.set_timings = opa362_set_timings,
.get_timings = opa362_get_timings,
.set_type = opa362_set_type,
};
static int opa362_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev, *in;
struct gpio_desc *gpio;
int r;
dev_dbg(&pdev->dev, "probe\n");
if (node == NULL) {
dev_err(&pdev->dev, "Unable to find device tree\n");
return -EINVAL;
}
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
gpio = devm_gpiod_get_optional(&pdev->dev, "enable", GPIOD_OUT_LOW);
if (IS_ERR(gpio))
return PTR_ERR(gpio);
ddata->enable_gpio = gpio;
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&pdev->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
dssdev = &ddata->dssdev;
dssdev->ops.atv = &opa362_atv_ops;
dssdev->dev = &pdev->dev;
dssdev->type = OMAP_DISPLAY_TYPE_VENC;
dssdev->output_type = OMAP_DISPLAY_TYPE_VENC;
dssdev->owner = THIS_MODULE;
r = omapdss_register_output(dssdev);
if (r) {
dev_err(&pdev->dev, "Failed to register output\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
return r;
}
static int __exit opa362_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_output(&ddata->dssdev);
WARN_ON(omapdss_device_is_enabled(dssdev));
if (omapdss_device_is_enabled(dssdev))
opa362_disable(dssdev);
WARN_ON(omapdss_device_is_connected(dssdev));
if (omapdss_device_is_connected(dssdev))
opa362_disconnect(dssdev, dssdev->dst);
omap_dss_put_device(in);
return 0;
}
static const struct of_device_id opa362_of_match[] = {
{ .compatible = "omapdss,ti,opa362", },
{},
};
MODULE_DEVICE_TABLE(of, opa362_of_match);
static struct platform_driver opa362_driver = {
.probe = opa362_probe,
.remove = __exit_p(opa362_remove),
.driver = {
.name = "amplifier-opa362",
.of_match_table = opa362_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(opa362_driver);
MODULE_AUTHOR("H. Nikolaus Schaller <[email protected]>");
MODULE_DESCRIPTION("OPA362 analog video amplifier with output/power control");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/encoder-opa362.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Sony ACX565AKM LCD Panel driver
*
* Copyright (C) 2010 Nokia Corporation
*
* Original Driver Author: Imre Deak <[email protected]>
* Based on panel-generic.c by Tomi Valkeinen <[email protected]>
* Adapted to new DSS2 framework: Roger Quadros <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/jiffies.h>
#include <linux/sched.h>
#include <linux/backlight.h>
#include <linux/fb.h>
#include <linux/gpio/consumer.h>
#include <linux/of.h>
#include <video/omapfb_dss.h>
#define MIPID_CMD_READ_DISP_ID 0x04
#define MIPID_CMD_READ_RED 0x06
#define MIPID_CMD_READ_GREEN 0x07
#define MIPID_CMD_READ_BLUE 0x08
#define MIPID_CMD_READ_DISP_STATUS 0x09
#define MIPID_CMD_RDDSDR 0x0F
#define MIPID_CMD_SLEEP_IN 0x10
#define MIPID_CMD_SLEEP_OUT 0x11
#define MIPID_CMD_DISP_OFF 0x28
#define MIPID_CMD_DISP_ON 0x29
#define MIPID_CMD_WRITE_DISP_BRIGHTNESS 0x51
#define MIPID_CMD_READ_DISP_BRIGHTNESS 0x52
#define MIPID_CMD_WRITE_CTRL_DISP 0x53
#define CTRL_DISP_BRIGHTNESS_CTRL_ON (1 << 5)
#define CTRL_DISP_AMBIENT_LIGHT_CTRL_ON (1 << 4)
#define CTRL_DISP_BACKLIGHT_ON (1 << 2)
#define CTRL_DISP_AUTO_BRIGHTNESS_ON (1 << 1)
#define MIPID_CMD_READ_CTRL_DISP 0x54
#define MIPID_CMD_WRITE_CABC 0x55
#define MIPID_CMD_READ_CABC 0x56
#define MIPID_VER_LPH8923 3
#define MIPID_VER_LS041Y3 4
#define MIPID_VER_L4F00311 8
#define MIPID_VER_ACX565AKM 9
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct gpio_desc *reset_gpio;
int datapairs;
struct omap_video_timings videomode;
char *name;
int enabled;
int model;
int revision;
u8 display_id[3];
unsigned has_bc:1;
unsigned has_cabc:1;
unsigned cabc_mode;
unsigned long hw_guard_end; /* next value of jiffies
when we can issue the
next sleep in/out command */
unsigned long hw_guard_wait; /* max guard time in jiffies */
struct spi_device *spi;
struct mutex mutex;
struct backlight_device *bl_dev;
};
static const struct omap_video_timings acx565akm_panel_timings = {
.x_res = 800,
.y_res = 480,
.pixelclock = 24000000,
.hfp = 28,
.hsw = 4,
.hbp = 24,
.vfp = 3,
.vsw = 3,
.vbp = 4,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
};
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
static void acx565akm_transfer(struct panel_drv_data *ddata, int cmd,
const u8 *wbuf, int wlen, u8 *rbuf, int rlen)
{
struct spi_message m;
struct spi_transfer *x, xfer[5];
int r;
BUG_ON(ddata->spi == NULL);
spi_message_init(&m);
memset(xfer, 0, sizeof(xfer));
x = &xfer[0];
cmd &= 0xff;
x->tx_buf = &cmd;
x->bits_per_word = 9;
x->len = 2;
if (rlen > 1 && wlen == 0) {
/*
* Between the command and the response data there is a
* dummy clock cycle. Add an extra bit after the command
* word to account for this.
*/
x->bits_per_word = 10;
cmd <<= 1;
}
spi_message_add_tail(x, &m);
if (wlen) {
x++;
x->tx_buf = wbuf;
x->len = wlen;
x->bits_per_word = 9;
spi_message_add_tail(x, &m);
}
if (rlen) {
x++;
x->rx_buf = rbuf;
x->len = rlen;
spi_message_add_tail(x, &m);
}
r = spi_sync(ddata->spi, &m);
if (r < 0)
dev_dbg(&ddata->spi->dev, "spi_sync %d\n", r);
}
static inline void acx565akm_cmd(struct panel_drv_data *ddata, int cmd)
{
acx565akm_transfer(ddata, cmd, NULL, 0, NULL, 0);
}
static inline void acx565akm_write(struct panel_drv_data *ddata,
int reg, const u8 *buf, int len)
{
acx565akm_transfer(ddata, reg, buf, len, NULL, 0);
}
static inline void acx565akm_read(struct panel_drv_data *ddata,
int reg, u8 *buf, int len)
{
acx565akm_transfer(ddata, reg, NULL, 0, buf, len);
}
static void hw_guard_start(struct panel_drv_data *ddata, int guard_msec)
{
ddata->hw_guard_wait = msecs_to_jiffies(guard_msec);
ddata->hw_guard_end = jiffies + ddata->hw_guard_wait;
}
static void hw_guard_wait(struct panel_drv_data *ddata)
{
unsigned long wait = ddata->hw_guard_end - jiffies;
if ((long)wait > 0 && wait <= ddata->hw_guard_wait) {
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(wait);
}
}
static void set_sleep_mode(struct panel_drv_data *ddata, int on)
{
int cmd;
if (on)
cmd = MIPID_CMD_SLEEP_IN;
else
cmd = MIPID_CMD_SLEEP_OUT;
/*
* We have to keep 120msec between sleep in/out commands.
* (8.2.15, 8.2.16).
*/
hw_guard_wait(ddata);
acx565akm_cmd(ddata, cmd);
hw_guard_start(ddata, 120);
}
static void set_display_state(struct panel_drv_data *ddata, int enabled)
{
int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
acx565akm_cmd(ddata, cmd);
}
static int panel_enabled(struct panel_drv_data *ddata)
{
u32 disp_status;
int enabled;
acx565akm_read(ddata, MIPID_CMD_READ_DISP_STATUS,
(u8 *)&disp_status, 4);
disp_status = __be32_to_cpu(disp_status);
enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
dev_dbg(&ddata->spi->dev,
"LCD panel %senabled by bootloader (status 0x%04x)\n",
enabled ? "" : "not ", disp_status);
return enabled;
}
static int panel_detect(struct panel_drv_data *ddata)
{
acx565akm_read(ddata, MIPID_CMD_READ_DISP_ID, ddata->display_id, 3);
dev_dbg(&ddata->spi->dev, "MIPI display ID: %02x%02x%02x\n",
ddata->display_id[0],
ddata->display_id[1],
ddata->display_id[2]);
switch (ddata->display_id[0]) {
case 0x10:
ddata->model = MIPID_VER_ACX565AKM;
ddata->name = "acx565akm";
ddata->has_bc = 1;
ddata->has_cabc = 1;
break;
case 0x29:
ddata->model = MIPID_VER_L4F00311;
ddata->name = "l4f00311";
break;
case 0x45:
ddata->model = MIPID_VER_LPH8923;
ddata->name = "lph8923";
break;
case 0x83:
ddata->model = MIPID_VER_LS041Y3;
ddata->name = "ls041y3";
break;
default:
ddata->name = "unknown";
dev_err(&ddata->spi->dev, "invalid display ID\n");
return -ENODEV;
}
ddata->revision = ddata->display_id[1];
dev_info(&ddata->spi->dev, "omapfb: %s rev %02x LCD detected\n",
ddata->name, ddata->revision);
return 0;
}
/*----------------------Backlight Control-------------------------*/
static void enable_backlight_ctrl(struct panel_drv_data *ddata, int enable)
{
u16 ctrl;
acx565akm_read(ddata, MIPID_CMD_READ_CTRL_DISP, (u8 *)&ctrl, 1);
if (enable) {
ctrl |= CTRL_DISP_BRIGHTNESS_CTRL_ON |
CTRL_DISP_BACKLIGHT_ON;
} else {
ctrl &= ~(CTRL_DISP_BRIGHTNESS_CTRL_ON |
CTRL_DISP_BACKLIGHT_ON);
}
ctrl |= 1 << 8;
acx565akm_write(ddata, MIPID_CMD_WRITE_CTRL_DISP, (u8 *)&ctrl, 2);
}
static void set_cabc_mode(struct panel_drv_data *ddata, unsigned mode)
{
u16 cabc_ctrl;
ddata->cabc_mode = mode;
if (!ddata->enabled)
return;
cabc_ctrl = 0;
acx565akm_read(ddata, MIPID_CMD_READ_CABC, (u8 *)&cabc_ctrl, 1);
cabc_ctrl &= ~3;
cabc_ctrl |= (1 << 8) | (mode & 3);
acx565akm_write(ddata, MIPID_CMD_WRITE_CABC, (u8 *)&cabc_ctrl, 2);
}
static unsigned get_cabc_mode(struct panel_drv_data *ddata)
{
return ddata->cabc_mode;
}
static unsigned get_hw_cabc_mode(struct panel_drv_data *ddata)
{
u8 cabc_ctrl;
acx565akm_read(ddata, MIPID_CMD_READ_CABC, &cabc_ctrl, 1);
return cabc_ctrl & 3;
}
static void acx565akm_set_brightness(struct panel_drv_data *ddata, int level)
{
int bv;
bv = level | (1 << 8);
acx565akm_write(ddata, MIPID_CMD_WRITE_DISP_BRIGHTNESS, (u8 *)&bv, 2);
if (level)
enable_backlight_ctrl(ddata, 1);
else
enable_backlight_ctrl(ddata, 0);
}
static int acx565akm_get_actual_brightness(struct panel_drv_data *ddata)
{
u8 bv;
acx565akm_read(ddata, MIPID_CMD_READ_DISP_BRIGHTNESS, &bv, 1);
return bv;
}
static int acx565akm_bl_update_status(struct backlight_device *dev)
{
struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev);
int level;
dev_dbg(&ddata->spi->dev, "%s\n", __func__);
if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
dev->props.power == FB_BLANK_UNBLANK)
level = dev->props.brightness;
else
level = 0;
if (ddata->has_bc)
acx565akm_set_brightness(ddata, level);
else
return -ENODEV;
return 0;
}
static int acx565akm_bl_get_intensity(struct backlight_device *dev)
{
struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev);
dev_dbg(&dev->dev, "%s\n", __func__);
if (!ddata->has_bc)
return -ENODEV;
if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
dev->props.power == FB_BLANK_UNBLANK) {
if (ddata->has_bc)
return acx565akm_get_actual_brightness(ddata);
else
return dev->props.brightness;
}
return 0;
}
static int acx565akm_bl_update_status_locked(struct backlight_device *dev)
{
struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev);
int r;
mutex_lock(&ddata->mutex);
r = acx565akm_bl_update_status(dev);
mutex_unlock(&ddata->mutex);
return r;
}
static int acx565akm_bl_get_intensity_locked(struct backlight_device *dev)
{
struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev);
int r;
mutex_lock(&ddata->mutex);
r = acx565akm_bl_get_intensity(dev);
mutex_unlock(&ddata->mutex);
return r;
}
static const struct backlight_ops acx565akm_bl_ops = {
.get_brightness = acx565akm_bl_get_intensity_locked,
.update_status = acx565akm_bl_update_status_locked,
};
/*--------------------Auto Brightness control via Sysfs---------------------*/
static const char * const cabc_modes[] = {
"off", /* always used when CABC is not supported */
"ui",
"still-image",
"moving-image",
};
static ssize_t show_cabc_mode(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
const char *mode_str;
int mode;
int len;
if (!ddata->has_cabc)
mode = 0;
else
mode = get_cabc_mode(ddata);
mode_str = "unknown";
if (mode >= 0 && mode < ARRAY_SIZE(cabc_modes))
mode_str = cabc_modes[mode];
len = snprintf(buf, PAGE_SIZE, "%s\n", mode_str);
return len < PAGE_SIZE - 1 ? len : PAGE_SIZE - 1;
}
static ssize_t store_cabc_mode(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
int i;
for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) {
const char *mode_str = cabc_modes[i];
int cmp_len = strlen(mode_str);
if (count > 0 && buf[count - 1] == '\n')
count--;
if (count != cmp_len)
continue;
if (strncmp(buf, mode_str, cmp_len) == 0)
break;
}
if (i == ARRAY_SIZE(cabc_modes))
return -EINVAL;
if (!ddata->has_cabc && i != 0)
return -EINVAL;
mutex_lock(&ddata->mutex);
set_cabc_mode(ddata, i);
mutex_unlock(&ddata->mutex);
return count;
}
static ssize_t show_cabc_available_modes(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
int len;
int i;
if (!ddata->has_cabc)
return sysfs_emit(buf, "%s\n", cabc_modes[0]);
for (i = 0, len = 0;
len < PAGE_SIZE && i < ARRAY_SIZE(cabc_modes); i++)
len += snprintf(&buf[len], PAGE_SIZE - len, "%s%s%s",
i ? " " : "", cabc_modes[i],
i == ARRAY_SIZE(cabc_modes) - 1 ? "\n" : "");
return len < PAGE_SIZE ? len : PAGE_SIZE - 1;
}
static DEVICE_ATTR(cabc_mode, S_IRUGO | S_IWUSR,
show_cabc_mode, store_cabc_mode);
static DEVICE_ATTR(cabc_available_modes, S_IRUGO,
show_cabc_available_modes, NULL);
static struct attribute *bldev_attrs[] = {
&dev_attr_cabc_mode.attr,
&dev_attr_cabc_available_modes.attr,
NULL,
};
static const struct attribute_group bldev_attr_group = {
.attrs = bldev_attrs,
};
static int acx565akm_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (omapdss_device_is_connected(dssdev))
return 0;
return in->ops.sdi->connect(in, dssdev);
}
static void acx565akm_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.sdi->disconnect(in, dssdev);
}
static int acx565akm_panel_power_on(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
dev_dbg(&ddata->spi->dev, "%s\n", __func__);
in->ops.sdi->set_timings(in, &ddata->videomode);
if (ddata->datapairs > 0)
in->ops.sdi->set_datapairs(in, ddata->datapairs);
r = in->ops.sdi->enable(in);
if (r) {
pr_err("%s sdi enable failed\n", __func__);
return r;
}
/*FIXME tweak me */
msleep(50);
/*
* Note that we appear to activate the reset line here. However
* existing DTSes specified incorrect polarity for it (active high),
* so in fact this deasserts the reset line.
*/
if (ddata->reset_gpio)
gpiod_set_value_cansleep(ddata->reset_gpio, 1);
if (ddata->enabled) {
dev_dbg(&ddata->spi->dev, "panel already enabled\n");
return 0;
}
/*
* We have to meet all the following delay requirements:
* 1. tRW: reset pulse width 10usec (7.12.1)
* 2. tRT: reset cancel time 5msec (7.12.1)
* 3. Providing PCLK,HS,VS signals for 2 frames = ~50msec worst
* case (7.6.2)
* 4. 120msec before the sleep out command (7.12.1)
*/
msleep(120);
set_sleep_mode(ddata, 0);
ddata->enabled = 1;
/* 5msec between sleep out and the next command. (8.2.16) */
usleep_range(5000, 10000);
set_display_state(ddata, 1);
set_cabc_mode(ddata, ddata->cabc_mode);
return acx565akm_bl_update_status(ddata->bl_dev);
}
static void acx565akm_panel_power_off(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(dssdev->dev, "%s\n", __func__);
if (!ddata->enabled)
return;
set_display_state(ddata, 0);
set_sleep_mode(ddata, 1);
ddata->enabled = 0;
/*
* We have to provide PCLK,HS,VS signals for 2 frames (worst case
* ~50msec) after sending the sleep in command and asserting the
* reset signal. We probably could assert the reset w/o the delay
* but we still delay to avoid possible artifacts. (7.6.1)
*/
msleep(50);
/* see comment in acx565akm_panel_power_on() */
if (ddata->reset_gpio)
gpiod_set_value_cansleep(ddata->reset_gpio, 0);
/* FIXME need to tweak this delay */
msleep(100);
in->ops.sdi->disable(in);
}
static int acx565akm_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
int r;
dev_dbg(dssdev->dev, "%s\n", __func__);
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
mutex_lock(&ddata->mutex);
r = acx565akm_panel_power_on(dssdev);
mutex_unlock(&ddata->mutex);
if (r)
return r;
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void acx565akm_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
dev_dbg(dssdev->dev, "%s\n", __func__);
if (!omapdss_device_is_enabled(dssdev))
return;
mutex_lock(&ddata->mutex);
acx565akm_panel_power_off(dssdev);
mutex_unlock(&ddata->mutex);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void acx565akm_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->videomode = *timings;
dssdev->panel.timings = *timings;
in->ops.sdi->set_timings(in, timings);
}
static void acx565akm_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->videomode;
}
static int acx565akm_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.sdi->check_timings(in, timings);
}
static struct omap_dss_driver acx565akm_ops = {
.connect = acx565akm_connect,
.disconnect = acx565akm_disconnect,
.enable = acx565akm_enable,
.disable = acx565akm_disable,
.set_timings = acx565akm_set_timings,
.get_timings = acx565akm_get_timings,
.check_timings = acx565akm_check_timings,
.get_resolution = omapdss_default_get_resolution,
};
static int acx565akm_probe(struct spi_device *spi)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
struct backlight_device *bldev;
int max_brightness, brightness;
struct backlight_properties props;
int r;
dev_dbg(&spi->dev, "%s\n", __func__);
if (!spi->dev.of_node)
return -ENODEV;
spi->mode = SPI_MODE_3;
ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
if (ddata == NULL)
return -ENOMEM;
dev_set_drvdata(&spi->dev, ddata);
ddata->spi = spi;
mutex_init(&ddata->mutex);
ddata->in = omapdss_of_find_source_for_first_ep(spi->dev.of_node);
r = PTR_ERR_OR_ZERO(ddata->in);
if (r) {
dev_err(&spi->dev, "failed to find video source\n");
return r;
}
ddata->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
GPIOD_OUT_LOW);
r = PTR_ERR_OR_ZERO(ddata->reset_gpio);
if (r)
goto err_gpio;
if (ddata->reset_gpio) {
gpiod_set_consumer_name(ddata->reset_gpio, "lcd reset");
/* release the reset line */
gpiod_set_value_cansleep(ddata->reset_gpio, 1);
}
/*
* After reset we have to wait 5 msec before the first
* command can be sent.
*/
usleep_range(5000, 10000);
ddata->enabled = panel_enabled(ddata);
r = panel_detect(ddata);
if (!ddata->enabled && ddata->reset_gpio)
gpiod_set_value_cansleep(ddata->reset_gpio, 0);
if (r) {
dev_err(&spi->dev, "%s panel detect error\n", __func__);
goto err_detect;
}
memset(&props, 0, sizeof(props));
props.fb_blank = FB_BLANK_UNBLANK;
props.power = FB_BLANK_UNBLANK;
props.type = BACKLIGHT_RAW;
bldev = backlight_device_register("acx565akm", &ddata->spi->dev,
ddata, &acx565akm_bl_ops, &props);
if (IS_ERR(bldev)) {
r = PTR_ERR(bldev);
goto err_reg_bl;
}
ddata->bl_dev = bldev;
if (ddata->has_cabc) {
r = sysfs_create_group(&bldev->dev.kobj, &bldev_attr_group);
if (r) {
dev_err(&bldev->dev,
"%s failed to create sysfs files\n", __func__);
goto err_sysfs;
}
ddata->cabc_mode = get_hw_cabc_mode(ddata);
}
max_brightness = 255;
if (ddata->has_bc)
brightness = acx565akm_get_actual_brightness(ddata);
else
brightness = 0;
bldev->props.max_brightness = max_brightness;
bldev->props.brightness = brightness;
acx565akm_bl_update_status(bldev);
ddata->videomode = acx565akm_panel_timings;
dssdev = &ddata->dssdev;
dssdev->dev = &spi->dev;
dssdev->driver = &acx565akm_ops;
dssdev->type = OMAP_DISPLAY_TYPE_SDI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = ddata->videomode;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&spi->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
sysfs_remove_group(&bldev->dev.kobj, &bldev_attr_group);
err_sysfs:
backlight_device_unregister(bldev);
err_reg_bl:
err_detect:
err_gpio:
omap_dss_put_device(ddata->in);
return r;
}
static void acx565akm_remove(struct spi_device *spi)
{
struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
dev_dbg(&ddata->spi->dev, "%s\n", __func__);
sysfs_remove_group(&ddata->bl_dev->dev.kobj, &bldev_attr_group);
backlight_device_unregister(ddata->bl_dev);
omapdss_unregister_display(dssdev);
acx565akm_disable(dssdev);
acx565akm_disconnect(dssdev);
omap_dss_put_device(in);
}
static const struct of_device_id acx565akm_of_match[] = {
{ .compatible = "omapdss,sony,acx565akm", },
{},
};
MODULE_DEVICE_TABLE(of, acx565akm_of_match);
static struct spi_driver acx565akm_driver = {
.driver = {
.name = "acx565akm",
.of_match_table = acx565akm_of_match,
.suppress_bind_attrs = true,
},
.probe = acx565akm_probe,
.remove = acx565akm_remove,
};
module_spi_driver(acx565akm_driver);
MODULE_AUTHOR("Nokia Corporation");
MODULE_DESCRIPTION("acx565akm LCD Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/panel-sony-acx565akm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Generic DSI Command Mode panel driver
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
/* #define DEBUG */
#include <linux/backlight.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/jiffies.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/sched/signal.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <video/omapfb_dss.h>
#include <video/mipi_display.h>
/* DSI Virtual channel. Hardcoded for now. */
#define TCH 0
#define DCS_READ_NUM_ERRORS 0x05
#define DCS_BRIGHTNESS 0x51
#define DCS_CTRL_DISPLAY 0x53
#define DCS_GET_ID1 0xda
#define DCS_GET_ID2 0xdb
#define DCS_GET_ID3 0xdc
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct omap_video_timings timings;
struct platform_device *pdev;
struct mutex lock;
struct backlight_device *bldev;
unsigned long hw_guard_end; /* next value of jiffies when we can
* issue the next sleep in/out command
*/
unsigned long hw_guard_wait; /* max guard time in jiffies */
/* panel HW configuration from DT or platform data */
struct gpio_desc *reset_gpio;
struct gpio_desc *ext_te_gpio;
bool use_dsi_backlight;
struct omap_dsi_pin_config pin_config;
/* runtime variables */
bool enabled;
bool te_enabled;
atomic_t do_update;
int channel;
struct delayed_work te_timeout_work;
bool intro_printed;
bool ulps_enabled;
unsigned ulps_timeout;
struct delayed_work ulps_work;
};
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
static irqreturn_t dsicm_te_isr(int irq, void *data);
static void dsicm_te_timeout_work_callback(struct work_struct *work);
static int _dsicm_enable_te(struct panel_drv_data *ddata, bool enable);
static int dsicm_panel_reset(struct panel_drv_data *ddata);
static void dsicm_ulps_work(struct work_struct *work);
static void hw_guard_start(struct panel_drv_data *ddata, int guard_msec)
{
ddata->hw_guard_wait = msecs_to_jiffies(guard_msec);
ddata->hw_guard_end = jiffies + ddata->hw_guard_wait;
}
static void hw_guard_wait(struct panel_drv_data *ddata)
{
unsigned long wait = ddata->hw_guard_end - jiffies;
if ((long)wait > 0 && time_before_eq(wait, ddata->hw_guard_wait)) {
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(wait);
}
}
static int dsicm_dcs_read_1(struct panel_drv_data *ddata, u8 dcs_cmd, u8 *data)
{
struct omap_dss_device *in = ddata->in;
int r;
u8 buf[1];
r = in->ops.dsi->dcs_read(in, ddata->channel, dcs_cmd, buf, 1);
if (r < 0)
return r;
*data = buf[0];
return 0;
}
static int dsicm_dcs_write_0(struct panel_drv_data *ddata, u8 dcs_cmd)
{
struct omap_dss_device *in = ddata->in;
return in->ops.dsi->dcs_write(in, ddata->channel, &dcs_cmd, 1);
}
static int dsicm_dcs_write_1(struct panel_drv_data *ddata, u8 dcs_cmd, u8 param)
{
struct omap_dss_device *in = ddata->in;
u8 buf[2] = { dcs_cmd, param };
return in->ops.dsi->dcs_write(in, ddata->channel, buf, 2);
}
static int dsicm_sleep_in(struct panel_drv_data *ddata)
{
struct omap_dss_device *in = ddata->in;
u8 cmd;
int r;
hw_guard_wait(ddata);
cmd = MIPI_DCS_ENTER_SLEEP_MODE;
r = in->ops.dsi->dcs_write_nosync(in, ddata->channel, &cmd, 1);
if (r)
return r;
hw_guard_start(ddata, 120);
usleep_range(5000, 10000);
return 0;
}
static int dsicm_sleep_out(struct panel_drv_data *ddata)
{
int r;
hw_guard_wait(ddata);
r = dsicm_dcs_write_0(ddata, MIPI_DCS_EXIT_SLEEP_MODE);
if (r)
return r;
hw_guard_start(ddata, 120);
usleep_range(5000, 10000);
return 0;
}
static int dsicm_get_id(struct panel_drv_data *ddata, u8 *id1, u8 *id2, u8 *id3)
{
int r;
r = dsicm_dcs_read_1(ddata, DCS_GET_ID1, id1);
if (r)
return r;
r = dsicm_dcs_read_1(ddata, DCS_GET_ID2, id2);
if (r)
return r;
r = dsicm_dcs_read_1(ddata, DCS_GET_ID3, id3);
if (r)
return r;
return 0;
}
static int dsicm_set_update_window(struct panel_drv_data *ddata,
u16 x, u16 y, u16 w, u16 h)
{
struct omap_dss_device *in = ddata->in;
int r;
u16 x1 = x;
u16 x2 = x + w - 1;
u16 y1 = y;
u16 y2 = y + h - 1;
u8 buf[5];
buf[0] = MIPI_DCS_SET_COLUMN_ADDRESS;
buf[1] = (x1 >> 8) & 0xff;
buf[2] = (x1 >> 0) & 0xff;
buf[3] = (x2 >> 8) & 0xff;
buf[4] = (x2 >> 0) & 0xff;
r = in->ops.dsi->dcs_write_nosync(in, ddata->channel, buf, sizeof(buf));
if (r)
return r;
buf[0] = MIPI_DCS_SET_PAGE_ADDRESS;
buf[1] = (y1 >> 8) & 0xff;
buf[2] = (y1 >> 0) & 0xff;
buf[3] = (y2 >> 8) & 0xff;
buf[4] = (y2 >> 0) & 0xff;
r = in->ops.dsi->dcs_write_nosync(in, ddata->channel, buf, sizeof(buf));
if (r)
return r;
in->ops.dsi->bta_sync(in, ddata->channel);
return r;
}
static void dsicm_queue_ulps_work(struct panel_drv_data *ddata)
{
if (ddata->ulps_timeout > 0)
schedule_delayed_work(&ddata->ulps_work,
msecs_to_jiffies(ddata->ulps_timeout));
}
static void dsicm_cancel_ulps_work(struct panel_drv_data *ddata)
{
cancel_delayed_work(&ddata->ulps_work);
}
static int dsicm_enter_ulps(struct panel_drv_data *ddata)
{
struct omap_dss_device *in = ddata->in;
int r;
if (ddata->ulps_enabled)
return 0;
dsicm_cancel_ulps_work(ddata);
r = _dsicm_enable_te(ddata, false);
if (r)
goto err;
if (ddata->ext_te_gpio)
disable_irq(gpiod_to_irq(ddata->ext_te_gpio));
in->ops.dsi->disable(in, false, true);
ddata->ulps_enabled = true;
return 0;
err:
dev_err(&ddata->pdev->dev, "enter ULPS failed");
dsicm_panel_reset(ddata);
ddata->ulps_enabled = false;
dsicm_queue_ulps_work(ddata);
return r;
}
static int dsicm_exit_ulps(struct panel_drv_data *ddata)
{
struct omap_dss_device *in = ddata->in;
int r;
if (!ddata->ulps_enabled)
return 0;
r = in->ops.dsi->enable(in);
if (r) {
dev_err(&ddata->pdev->dev, "failed to enable DSI\n");
goto err1;
}
in->ops.dsi->enable_hs(in, ddata->channel, true);
r = _dsicm_enable_te(ddata, true);
if (r) {
dev_err(&ddata->pdev->dev, "failed to re-enable TE");
goto err2;
}
if (ddata->ext_te_gpio)
enable_irq(gpiod_to_irq(ddata->ext_te_gpio));
dsicm_queue_ulps_work(ddata);
ddata->ulps_enabled = false;
return 0;
err2:
dev_err(&ddata->pdev->dev, "failed to exit ULPS");
r = dsicm_panel_reset(ddata);
if (!r) {
if (ddata->ext_te_gpio)
enable_irq(gpiod_to_irq(ddata->ext_te_gpio));
ddata->ulps_enabled = false;
}
err1:
dsicm_queue_ulps_work(ddata);
return r;
}
static int dsicm_wake_up(struct panel_drv_data *ddata)
{
if (ddata->ulps_enabled)
return dsicm_exit_ulps(ddata);
dsicm_cancel_ulps_work(ddata);
dsicm_queue_ulps_work(ddata);
return 0;
}
static int dsicm_bl_update_status(struct backlight_device *dev)
{
struct panel_drv_data *ddata = dev_get_drvdata(&dev->dev);
struct omap_dss_device *in = ddata->in;
int r;
int level = backlight_get_brightness(dev);
dev_dbg(&ddata->pdev->dev, "update brightness to %d\n", level);
mutex_lock(&ddata->lock);
if (ddata->enabled) {
in->ops.dsi->bus_lock(in);
r = dsicm_wake_up(ddata);
if (!r)
r = dsicm_dcs_write_1(ddata, DCS_BRIGHTNESS, level);
in->ops.dsi->bus_unlock(in);
} else {
r = 0;
}
mutex_unlock(&ddata->lock);
return r;
}
static int dsicm_bl_get_intensity(struct backlight_device *dev)
{
if (dev->props.fb_blank == FB_BLANK_UNBLANK &&
dev->props.power == FB_BLANK_UNBLANK)
return dev->props.brightness;
return 0;
}
static const struct backlight_ops dsicm_bl_ops = {
.get_brightness = dsicm_bl_get_intensity,
.update_status = dsicm_bl_update_status,
};
static void dsicm_get_resolution(struct omap_dss_device *dssdev,
u16 *xres, u16 *yres)
{
*xres = dssdev->panel.timings.x_res;
*yres = dssdev->panel.timings.y_res;
}
static ssize_t dsicm_num_errors_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
struct omap_dss_device *in = ddata->in;
u8 errors = 0;
int r;
mutex_lock(&ddata->lock);
if (ddata->enabled) {
in->ops.dsi->bus_lock(in);
r = dsicm_wake_up(ddata);
if (!r)
r = dsicm_dcs_read_1(ddata, DCS_READ_NUM_ERRORS,
&errors);
in->ops.dsi->bus_unlock(in);
} else {
r = -ENODEV;
}
mutex_unlock(&ddata->lock);
if (r)
return r;
return sysfs_emit(buf, "%d\n", errors);
}
static ssize_t dsicm_hw_revision_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
struct omap_dss_device *in = ddata->in;
u8 id1, id2, id3;
int r;
mutex_lock(&ddata->lock);
if (ddata->enabled) {
in->ops.dsi->bus_lock(in);
r = dsicm_wake_up(ddata);
if (!r)
r = dsicm_get_id(ddata, &id1, &id2, &id3);
in->ops.dsi->bus_unlock(in);
} else {
r = -ENODEV;
}
mutex_unlock(&ddata->lock);
if (r)
return r;
return sysfs_emit(buf, "%02x.%02x.%02x\n", id1, id2, id3);
}
static ssize_t dsicm_store_ulps(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
struct omap_dss_device *in = ddata->in;
unsigned long t;
int r;
r = kstrtoul(buf, 0, &t);
if (r)
return r;
mutex_lock(&ddata->lock);
if (ddata->enabled) {
in->ops.dsi->bus_lock(in);
if (t)
r = dsicm_enter_ulps(ddata);
else
r = dsicm_wake_up(ddata);
in->ops.dsi->bus_unlock(in);
}
mutex_unlock(&ddata->lock);
if (r)
return r;
return count;
}
static ssize_t dsicm_show_ulps(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
unsigned t;
mutex_lock(&ddata->lock);
t = ddata->ulps_enabled;
mutex_unlock(&ddata->lock);
return sysfs_emit(buf, "%u\n", t);
}
static ssize_t dsicm_store_ulps_timeout(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
struct omap_dss_device *in = ddata->in;
unsigned long t;
int r;
r = kstrtoul(buf, 0, &t);
if (r)
return r;
mutex_lock(&ddata->lock);
ddata->ulps_timeout = t;
if (ddata->enabled) {
/* dsicm_wake_up will restart the timer */
in->ops.dsi->bus_lock(in);
r = dsicm_wake_up(ddata);
in->ops.dsi->bus_unlock(in);
}
mutex_unlock(&ddata->lock);
if (r)
return r;
return count;
}
static ssize_t dsicm_show_ulps_timeout(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
unsigned t;
mutex_lock(&ddata->lock);
t = ddata->ulps_timeout;
mutex_unlock(&ddata->lock);
return sysfs_emit(buf, "%u\n", t);
}
static DEVICE_ATTR(num_dsi_errors, S_IRUGO, dsicm_num_errors_show, NULL);
static DEVICE_ATTR(hw_revision, S_IRUGO, dsicm_hw_revision_show, NULL);
static DEVICE_ATTR(ulps, S_IRUGO | S_IWUSR,
dsicm_show_ulps, dsicm_store_ulps);
static DEVICE_ATTR(ulps_timeout, S_IRUGO | S_IWUSR,
dsicm_show_ulps_timeout, dsicm_store_ulps_timeout);
static struct attribute *dsicm_attrs[] = {
&dev_attr_num_dsi_errors.attr,
&dev_attr_hw_revision.attr,
&dev_attr_ulps.attr,
&dev_attr_ulps_timeout.attr,
NULL,
};
static const struct attribute_group dsicm_attr_group = {
.attrs = dsicm_attrs,
};
static void dsicm_hw_reset(struct panel_drv_data *ddata)
{
/*
* Note that we appear to activate the reset line here. However
* existing DTSes specified incorrect polarity for it (active high),
* so in fact this deasserts the reset line.
*/
gpiod_set_value_cansleep(ddata->reset_gpio, 1);
udelay(10);
/* reset the panel */
gpiod_set_value_cansleep(ddata->reset_gpio, 0);
/* keep reset asserted */
udelay(10);
/* release reset line */
gpiod_set_value_cansleep(ddata->reset_gpio, 1);
/* wait after releasing reset */
usleep_range(5000, 10000);
}
static int dsicm_power_on(struct panel_drv_data *ddata)
{
struct omap_dss_device *in = ddata->in;
u8 id1, id2, id3;
int r;
struct omap_dss_dsi_config dsi_config = {
.mode = OMAP_DSS_DSI_CMD_MODE,
.pixel_format = OMAP_DSS_DSI_FMT_RGB888,
.timings = &ddata->timings,
.hs_clk_min = 150000000,
.hs_clk_max = 300000000,
.lp_clk_min = 7000000,
.lp_clk_max = 10000000,
};
if (ddata->pin_config.num_pins > 0) {
r = in->ops.dsi->configure_pins(in, &ddata->pin_config);
if (r) {
dev_err(&ddata->pdev->dev,
"failed to configure DSI pins\n");
goto err0;
}
}
r = in->ops.dsi->set_config(in, &dsi_config);
if (r) {
dev_err(&ddata->pdev->dev, "failed to configure DSI\n");
goto err0;
}
r = in->ops.dsi->enable(in);
if (r) {
dev_err(&ddata->pdev->dev, "failed to enable DSI\n");
goto err0;
}
dsicm_hw_reset(ddata);
in->ops.dsi->enable_hs(in, ddata->channel, false);
r = dsicm_sleep_out(ddata);
if (r)
goto err;
r = dsicm_get_id(ddata, &id1, &id2, &id3);
if (r)
goto err;
r = dsicm_dcs_write_1(ddata, DCS_BRIGHTNESS, 0xff);
if (r)
goto err;
r = dsicm_dcs_write_1(ddata, DCS_CTRL_DISPLAY,
(1<<2) | (1<<5)); /* BL | BCTRL */
if (r)
goto err;
r = dsicm_dcs_write_1(ddata, MIPI_DCS_SET_PIXEL_FORMAT,
MIPI_DCS_PIXEL_FMT_24BIT);
if (r)
goto err;
r = dsicm_dcs_write_0(ddata, MIPI_DCS_SET_DISPLAY_ON);
if (r)
goto err;
r = _dsicm_enable_te(ddata, ddata->te_enabled);
if (r)
goto err;
r = in->ops.dsi->enable_video_output(in, ddata->channel);
if (r)
goto err;
ddata->enabled = 1;
if (!ddata->intro_printed) {
dev_info(&ddata->pdev->dev, "panel revision %02x.%02x.%02x\n",
id1, id2, id3);
ddata->intro_printed = true;
}
in->ops.dsi->enable_hs(in, ddata->channel, true);
return 0;
err:
dev_err(&ddata->pdev->dev, "error while enabling panel, issuing HW reset\n");
dsicm_hw_reset(ddata);
in->ops.dsi->disable(in, true, false);
err0:
return r;
}
static void dsicm_power_off(struct panel_drv_data *ddata)
{
struct omap_dss_device *in = ddata->in;
int r;
in->ops.dsi->disable_video_output(in, ddata->channel);
r = dsicm_dcs_write_0(ddata, MIPI_DCS_SET_DISPLAY_OFF);
if (!r)
r = dsicm_sleep_in(ddata);
if (r) {
dev_err(&ddata->pdev->dev,
"error disabling panel, issuing HW reset\n");
dsicm_hw_reset(ddata);
}
in->ops.dsi->disable(in, true, false);
ddata->enabled = 0;
}
static int dsicm_panel_reset(struct panel_drv_data *ddata)
{
dev_err(&ddata->pdev->dev, "performing LCD reset\n");
dsicm_power_off(ddata);
dsicm_hw_reset(ddata);
return dsicm_power_on(ddata);
}
static int dsicm_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
struct device *dev = &ddata->pdev->dev;
int r;
if (omapdss_device_is_connected(dssdev))
return 0;
r = in->ops.dsi->connect(in, dssdev);
if (r) {
dev_err(dev, "Failed to connect to video source\n");
return r;
}
r = in->ops.dsi->request_vc(ddata->in, &ddata->channel);
if (r) {
dev_err(dev, "failed to get virtual channel\n");
goto err_req_vc;
}
r = in->ops.dsi->set_vc_id(ddata->in, ddata->channel, TCH);
if (r) {
dev_err(dev, "failed to set VC_ID\n");
goto err_vc_id;
}
return 0;
err_vc_id:
in->ops.dsi->release_vc(ddata->in, ddata->channel);
err_req_vc:
in->ops.dsi->disconnect(in, dssdev);
return r;
}
static void dsicm_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.dsi->release_vc(in, ddata->channel);
in->ops.dsi->disconnect(in, dssdev);
}
static int dsicm_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
dev_dbg(&ddata->pdev->dev, "enable\n");
mutex_lock(&ddata->lock);
if (!omapdss_device_is_connected(dssdev)) {
r = -ENODEV;
goto err;
}
if (omapdss_device_is_enabled(dssdev)) {
r = 0;
goto err;
}
in->ops.dsi->bus_lock(in);
r = dsicm_power_on(ddata);
in->ops.dsi->bus_unlock(in);
if (r)
goto err;
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
mutex_unlock(&ddata->lock);
return 0;
err:
dev_dbg(&ddata->pdev->dev, "enable failed\n");
mutex_unlock(&ddata->lock);
return r;
}
static void dsicm_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
dev_dbg(&ddata->pdev->dev, "disable\n");
mutex_lock(&ddata->lock);
dsicm_cancel_ulps_work(ddata);
in->ops.dsi->bus_lock(in);
if (omapdss_device_is_enabled(dssdev)) {
r = dsicm_wake_up(ddata);
if (!r)
dsicm_power_off(ddata);
}
in->ops.dsi->bus_unlock(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
mutex_unlock(&ddata->lock);
}
static void dsicm_framedone_cb(int err, void *data)
{
struct panel_drv_data *ddata = data;
struct omap_dss_device *in = ddata->in;
dev_dbg(&ddata->pdev->dev, "framedone, err %d\n", err);
in->ops.dsi->bus_unlock(ddata->in);
}
static irqreturn_t dsicm_te_isr(int irq, void *data)
{
struct panel_drv_data *ddata = data;
struct omap_dss_device *in = ddata->in;
int old;
int r;
old = atomic_cmpxchg(&ddata->do_update, 1, 0);
if (old) {
cancel_delayed_work(&ddata->te_timeout_work);
r = in->ops.dsi->update(in, ddata->channel, dsicm_framedone_cb,
ddata);
if (r)
goto err;
}
return IRQ_HANDLED;
err:
dev_err(&ddata->pdev->dev, "start update failed\n");
in->ops.dsi->bus_unlock(in);
return IRQ_HANDLED;
}
static void dsicm_te_timeout_work_callback(struct work_struct *work)
{
struct panel_drv_data *ddata = container_of(work, struct panel_drv_data,
te_timeout_work.work);
struct omap_dss_device *in = ddata->in;
dev_err(&ddata->pdev->dev, "TE not received for 250ms!\n");
atomic_set(&ddata->do_update, 0);
in->ops.dsi->bus_unlock(in);
}
static int dsicm_update(struct omap_dss_device *dssdev,
u16 x, u16 y, u16 w, u16 h)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
dev_dbg(&ddata->pdev->dev, "update %d, %d, %d x %d\n", x, y, w, h);
mutex_lock(&ddata->lock);
in->ops.dsi->bus_lock(in);
r = dsicm_wake_up(ddata);
if (r)
goto err;
if (!ddata->enabled) {
r = 0;
goto err;
}
/* XXX no need to send this every frame, but dsi break if not done */
r = dsicm_set_update_window(ddata, 0, 0,
dssdev->panel.timings.x_res,
dssdev->panel.timings.y_res);
if (r)
goto err;
if (ddata->te_enabled && ddata->ext_te_gpio) {
schedule_delayed_work(&ddata->te_timeout_work,
msecs_to_jiffies(250));
atomic_set(&ddata->do_update, 1);
} else {
r = in->ops.dsi->update(in, ddata->channel, dsicm_framedone_cb,
ddata);
if (r)
goto err;
}
/* note: no bus_unlock here. unlock is in framedone_cb */
mutex_unlock(&ddata->lock);
return 0;
err:
in->ops.dsi->bus_unlock(in);
mutex_unlock(&ddata->lock);
return r;
}
static int dsicm_sync(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
dev_dbg(&ddata->pdev->dev, "sync\n");
mutex_lock(&ddata->lock);
in->ops.dsi->bus_lock(in);
in->ops.dsi->bus_unlock(in);
mutex_unlock(&ddata->lock);
dev_dbg(&ddata->pdev->dev, "sync done\n");
return 0;
}
static int _dsicm_enable_te(struct panel_drv_data *ddata, bool enable)
{
struct omap_dss_device *in = ddata->in;
int r;
if (enable)
r = dsicm_dcs_write_1(ddata, MIPI_DCS_SET_TEAR_ON, 0);
else
r = dsicm_dcs_write_0(ddata, MIPI_DCS_SET_TEAR_OFF);
if (!ddata->ext_te_gpio)
in->ops.dsi->enable_te(in, enable);
/* possible panel bug */
msleep(100);
return r;
}
static int dsicm_enable_te(struct omap_dss_device *dssdev, bool enable)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
mutex_lock(&ddata->lock);
if (ddata->te_enabled == enable)
goto end;
in->ops.dsi->bus_lock(in);
if (ddata->enabled) {
r = dsicm_wake_up(ddata);
if (r)
goto err;
r = _dsicm_enable_te(ddata, enable);
if (r)
goto err;
}
ddata->te_enabled = enable;
in->ops.dsi->bus_unlock(in);
end:
mutex_unlock(&ddata->lock);
return 0;
err:
in->ops.dsi->bus_unlock(in);
mutex_unlock(&ddata->lock);
return r;
}
static int dsicm_get_te(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
int r;
mutex_lock(&ddata->lock);
r = ddata->te_enabled;
mutex_unlock(&ddata->lock);
return r;
}
static int dsicm_memory_read(struct omap_dss_device *dssdev,
void *buf, size_t size,
u16 x, u16 y, u16 w, u16 h)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
int first = 1;
int plen;
unsigned buf_used = 0;
if (size < w * h * 3)
return -ENOMEM;
mutex_lock(&ddata->lock);
if (!ddata->enabled) {
r = -ENODEV;
goto err1;
}
size = min(w * h * 3,
dssdev->panel.timings.x_res *
dssdev->panel.timings.y_res * 3);
in->ops.dsi->bus_lock(in);
r = dsicm_wake_up(ddata);
if (r)
goto err2;
/* plen 1 or 2 goes into short packet. until checksum error is fixed,
* use short packets. plen 32 works, but bigger packets seem to cause
* an error. */
if (size % 2)
plen = 1;
else
plen = 2;
dsicm_set_update_window(ddata, x, y, w, h);
r = in->ops.dsi->set_max_rx_packet_size(in, ddata->channel, plen);
if (r)
goto err2;
while (buf_used < size) {
u8 dcs_cmd = first ? 0x2e : 0x3e;
first = 0;
r = in->ops.dsi->dcs_read(in, ddata->channel, dcs_cmd,
buf + buf_used, size - buf_used);
if (r < 0) {
dev_err(dssdev->dev, "read error\n");
goto err3;
}
buf_used += r;
if (r < plen) {
dev_err(&ddata->pdev->dev, "short read\n");
break;
}
if (signal_pending(current)) {
dev_err(&ddata->pdev->dev, "signal pending, "
"aborting memory read\n");
r = -ERESTARTSYS;
goto err3;
}
}
r = buf_used;
err3:
in->ops.dsi->set_max_rx_packet_size(in, ddata->channel, 1);
err2:
in->ops.dsi->bus_unlock(in);
err1:
mutex_unlock(&ddata->lock);
return r;
}
static void dsicm_ulps_work(struct work_struct *work)
{
struct panel_drv_data *ddata = container_of(work, struct panel_drv_data,
ulps_work.work);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
mutex_lock(&ddata->lock);
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE || !ddata->enabled) {
mutex_unlock(&ddata->lock);
return;
}
in->ops.dsi->bus_lock(in);
dsicm_enter_ulps(ddata);
in->ops.dsi->bus_unlock(in);
mutex_unlock(&ddata->lock);
}
static struct omap_dss_driver dsicm_ops = {
.connect = dsicm_connect,
.disconnect = dsicm_disconnect,
.enable = dsicm_enable,
.disable = dsicm_disable,
.update = dsicm_update,
.sync = dsicm_sync,
.get_resolution = dsicm_get_resolution,
.get_recommended_bpp = omapdss_default_get_recommended_bpp,
.enable_te = dsicm_enable_te,
.get_te = dsicm_get_te,
.memory_read = dsicm_memory_read,
};
static int dsicm_probe(struct platform_device *pdev)
{
struct backlight_properties props;
struct panel_drv_data *ddata;
struct backlight_device *bldev = NULL;
struct device *dev = &pdev->dev;
struct omap_dss_device *dssdev;
int r;
dev_dbg(dev, "probe\n");
if (!pdev->dev.of_node)
return -ENODEV;
ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
ddata->pdev = pdev;
ddata->in = omapdss_of_find_source_for_first_ep(pdev->dev.of_node);
r = PTR_ERR_OR_ZERO(ddata->in);
if (r) {
dev_err(&pdev->dev, "failed to find video source: %d\n", r);
return r;
}
ddata->timings.x_res = 864;
ddata->timings.y_res = 480;
ddata->timings.pixelclock = 864 * 480 * 60;
dssdev = &ddata->dssdev;
dssdev->dev = dev;
dssdev->driver = &dsicm_ops;
dssdev->panel.timings = ddata->timings;
dssdev->type = OMAP_DISPLAY_TYPE_DSI;
dssdev->owner = THIS_MODULE;
dssdev->panel.dsi_pix_fmt = OMAP_DSS_DSI_FMT_RGB888;
dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(dev, "Failed to register panel\n");
goto err_reg;
}
mutex_init(&ddata->lock);
atomic_set(&ddata->do_update, 0);
ddata->reset_gpio = devm_gpiod_get(&pdev->dev, "reset", GPIOD_OUT_LOW);
r = PTR_ERR_OR_ZERO(ddata->reset_gpio);
if (r) {
dev_err(&pdev->dev, "Failed to request reset gpio: %d\n", r);
return r;
}
gpiod_set_consumer_name(ddata->reset_gpio, "taal rst");
ddata->ext_te_gpio = devm_gpiod_get_optional(&pdev->dev, "te",
GPIOD_IN);
r = PTR_ERR_OR_ZERO(ddata->ext_te_gpio);
if (r) {
dev_err(&pdev->dev, "Failed to request TE gpio: %d\n", r);
return r;
}
if (ddata->ext_te_gpio) {
gpiod_set_consumer_name(ddata->ext_te_gpio, "taal irq");
r = devm_request_irq(dev, gpiod_to_irq(ddata->ext_te_gpio),
dsicm_te_isr,
IRQF_TRIGGER_RISING,
"taal vsync", ddata);
if (r) {
dev_err(dev, "IRQ request failed\n");
return r;
}
INIT_DEFERRABLE_WORK(&ddata->te_timeout_work,
dsicm_te_timeout_work_callback);
dev_dbg(dev, "Using GPIO TE\n");
}
INIT_DELAYED_WORK(&ddata->ulps_work, dsicm_ulps_work);
dsicm_hw_reset(ddata);
if (ddata->use_dsi_backlight) {
memset(&props, 0, sizeof(struct backlight_properties));
props.max_brightness = 255;
props.type = BACKLIGHT_RAW;
bldev = backlight_device_register(dev_name(dev),
dev, ddata, &dsicm_bl_ops, &props);
if (IS_ERR(bldev)) {
r = PTR_ERR(bldev);
goto err_reg;
}
ddata->bldev = bldev;
bldev->props.fb_blank = FB_BLANK_UNBLANK;
bldev->props.power = FB_BLANK_UNBLANK;
bldev->props.brightness = 255;
dsicm_bl_update_status(bldev);
}
r = sysfs_create_group(&dev->kobj, &dsicm_attr_group);
if (r) {
dev_err(dev, "failed to create sysfs files\n");
goto err_sysfs_create;
}
return 0;
err_sysfs_create:
if (bldev != NULL)
backlight_device_unregister(bldev);
err_reg:
return r;
}
static int __exit dsicm_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct backlight_device *bldev;
dev_dbg(&pdev->dev, "remove\n");
omapdss_unregister_display(dssdev);
dsicm_disable(dssdev);
dsicm_disconnect(dssdev);
sysfs_remove_group(&pdev->dev.kobj, &dsicm_attr_group);
bldev = ddata->bldev;
if (bldev != NULL) {
bldev->props.power = FB_BLANK_POWERDOWN;
dsicm_bl_update_status(bldev);
backlight_device_unregister(bldev);
}
omap_dss_put_device(ddata->in);
dsicm_cancel_ulps_work(ddata);
/* reset, to be sure that the panel is in a valid state */
dsicm_hw_reset(ddata);
return 0;
}
static const struct of_device_id dsicm_of_match[] = {
{ .compatible = "omapdss,panel-dsi-cm", },
{},
};
MODULE_DEVICE_TABLE(of, dsicm_of_match);
static struct platform_driver dsicm_driver = {
.probe = dsicm_probe,
.remove = __exit_p(dsicm_remove),
.driver = {
.name = "panel-dsi-cm",
.of_match_table = dsicm_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(dsicm_driver);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("Generic DSI Command Mode Panel Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/panel-dsi-cm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TFP410 DPI-to-DVI encoder driver
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <video/omapfb_dss.h>
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct gpio_desc *pd_gpio;
int data_lines;
struct omap_video_timings timings;
};
#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
static int tfp410_connect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (omapdss_device_is_connected(dssdev))
return -EBUSY;
r = in->ops.dpi->connect(in, dssdev);
if (r)
return r;
dst->src = dssdev;
dssdev->dst = dst;
return 0;
}
static void tfp410_disconnect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
WARN_ON(!omapdss_device_is_connected(dssdev));
if (!omapdss_device_is_connected(dssdev))
return;
WARN_ON(dst != dssdev->dst);
if (dst != dssdev->dst)
return;
dst->src = NULL;
dssdev->dst = NULL;
in->ops.dpi->disconnect(in, &ddata->dssdev);
}
static int tfp410_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
in->ops.dpi->set_timings(in, &ddata->timings);
if (ddata->data_lines)
in->ops.dpi->set_data_lines(in, ddata->data_lines);
r = in->ops.dpi->enable(in);
if (r)
return r;
if (ddata->pd_gpio)
gpiod_set_value_cansleep(ddata->pd_gpio, 0);
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void tfp410_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_enabled(dssdev))
return;
if (ddata->pd_gpio)
gpiod_set_value_cansleep(ddata->pd_gpio, 1);
in->ops.dpi->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void tfp410_fix_timings(struct omap_video_timings *timings)
{
timings->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
timings->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
timings->de_level = OMAPDSS_SIG_ACTIVE_HIGH;
}
static void tfp410_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
tfp410_fix_timings(timings);
ddata->timings = *timings;
dssdev->panel.timings = *timings;
in->ops.dpi->set_timings(in, timings);
}
static void tfp410_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->timings;
}
static int tfp410_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
tfp410_fix_timings(timings);
return in->ops.dpi->check_timings(in, timings);
}
static const struct omapdss_dvi_ops tfp410_dvi_ops = {
.connect = tfp410_connect,
.disconnect = tfp410_disconnect,
.enable = tfp410_enable,
.disable = tfp410_disable,
.check_timings = tfp410_check_timings,
.set_timings = tfp410_set_timings,
.get_timings = tfp410_get_timings,
};
static int tfp410_probe(struct platform_device *pdev)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
if (!pdev->dev.of_node)
return -ENODEV;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
ddata->pd_gpio = devm_gpiod_get_optional(&pdev->dev, "powerdown",
GPIOD_OUT_HIGH);
r = PTR_ERR_OR_ZERO(ddata->pd_gpio);
if (r) {
dev_err(&pdev->dev, "Failed to request PD GPIO: %d\n", r);
return r;
}
gpiod_set_consumer_name(ddata->pd_gpio, "tfp410 PD");
ddata->in = omapdss_of_find_source_for_first_ep(pdev->dev.of_node);
r = PTR_ERR_OR_ZERO(ddata->in);
if (r) {
dev_err(&pdev->dev, "failed to find video source: %d\n", r);
return r;
}
dssdev = &ddata->dssdev;
dssdev->ops.dvi = &tfp410_dvi_ops;
dssdev->dev = &pdev->dev;
dssdev->type = OMAP_DISPLAY_TYPE_DPI;
dssdev->output_type = OMAP_DISPLAY_TYPE_DVI;
dssdev->owner = THIS_MODULE;
dssdev->phy.dpi.data_lines = ddata->data_lines;
dssdev->port_num = 1;
r = omapdss_register_output(dssdev);
if (r) {
dev_err(&pdev->dev, "Failed to register output\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
return r;
}
static int __exit tfp410_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_output(&ddata->dssdev);
WARN_ON(omapdss_device_is_enabled(dssdev));
if (omapdss_device_is_enabled(dssdev))
tfp410_disable(dssdev);
WARN_ON(omapdss_device_is_connected(dssdev));
if (omapdss_device_is_connected(dssdev))
tfp410_disconnect(dssdev, dssdev->dst);
omap_dss_put_device(in);
return 0;
}
static const struct of_device_id tfp410_of_match[] = {
{ .compatible = "omapdss,ti,tfp410", },
{},
};
MODULE_DEVICE_TABLE(of, tfp410_of_match);
static struct platform_driver tfp410_driver = {
.probe = tfp410_probe,
.remove = __exit_p(tfp410_remove),
.driver = {
.name = "tfp410",
.of_match_table = tfp410_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(tfp410_driver);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("TFP410 DPI to DVI encoder driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/encoder-tfp410.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* TPD12S015 HDMI ESD protection & level shifter chip driver
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/gpio/consumer.h>
#include <video/omapfb_dss.h>
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct gpio_desc *ct_cp_hpd_gpio;
struct gpio_desc *ls_oe_gpio;
struct gpio_desc *hpd_gpio;
struct omap_video_timings timings;
};
#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
static int tpd_connect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
r = in->ops.hdmi->connect(in, dssdev);
if (r)
return r;
dst->src = dssdev;
dssdev->dst = dst;
if (ddata->ct_cp_hpd_gpio) {
gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 1);
/* DC-DC converter needs at max 300us to get to 90% of 5V */
udelay(300);
}
return 0;
}
static void tpd_disconnect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
WARN_ON(dst != dssdev->dst);
if (dst != dssdev->dst)
return;
gpiod_set_value_cansleep(ddata->ct_cp_hpd_gpio, 0);
dst->src = NULL;
dssdev->dst = NULL;
in->ops.hdmi->disconnect(in, &ddata->dssdev);
}
static int tpd_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
return 0;
in->ops.hdmi->set_timings(in, &ddata->timings);
r = in->ops.hdmi->enable(in);
if (r)
return r;
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return r;
}
static void tpd_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
return;
in->ops.hdmi->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void tpd_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->timings = *timings;
dssdev->panel.timings = *timings;
in->ops.hdmi->set_timings(in, timings);
}
static void tpd_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->timings;
}
static int tpd_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
r = in->ops.hdmi->check_timings(in, timings);
return r;
}
static int tpd_read_edid(struct omap_dss_device *dssdev,
u8 *edid, int len)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!gpiod_get_value_cansleep(ddata->hpd_gpio))
return -ENODEV;
gpiod_set_value_cansleep(ddata->ls_oe_gpio, 1);
r = in->ops.hdmi->read_edid(in, edid, len);
gpiod_set_value_cansleep(ddata->ls_oe_gpio, 0);
return r;
}
static bool tpd_detect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
return gpiod_get_value_cansleep(ddata->hpd_gpio);
}
static int tpd_set_infoframe(struct omap_dss_device *dssdev,
const struct hdmi_avi_infoframe *avi)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.hdmi->set_infoframe(in, avi);
}
static int tpd_set_hdmi_mode(struct omap_dss_device *dssdev,
bool hdmi_mode)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.hdmi->set_hdmi_mode(in, hdmi_mode);
}
static const struct omapdss_hdmi_ops tpd_hdmi_ops = {
.connect = tpd_connect,
.disconnect = tpd_disconnect,
.enable = tpd_enable,
.disable = tpd_disable,
.check_timings = tpd_check_timings,
.set_timings = tpd_set_timings,
.get_timings = tpd_get_timings,
.read_edid = tpd_read_edid,
.detect = tpd_detect,
.set_infoframe = tpd_set_infoframe,
.set_hdmi_mode = tpd_set_hdmi_mode,
};
static int tpd_probe_of(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
struct omap_dss_device *in;
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&pdev->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
return 0;
}
static int tpd_probe(struct platform_device *pdev)
{
struct omap_dss_device *dssdev;
struct panel_drv_data *ddata;
int r;
struct gpio_desc *gpio;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (!ddata)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
if (pdev->dev.of_node) {
r = tpd_probe_of(pdev);
if (r)
return r;
} else {
return -ENODEV;
}
gpio = devm_gpiod_get_index_optional(&pdev->dev, NULL, 0,
GPIOD_OUT_LOW);
if (IS_ERR(gpio)) {
r = PTR_ERR(gpio);
goto err_gpio;
}
ddata->ct_cp_hpd_gpio = gpio;
gpio = devm_gpiod_get_index_optional(&pdev->dev, NULL, 1,
GPIOD_OUT_LOW);
if (IS_ERR(gpio)) {
r = PTR_ERR(gpio);
goto err_gpio;
}
ddata->ls_oe_gpio = gpio;
gpio = devm_gpiod_get_index(&pdev->dev, NULL, 2,
GPIOD_IN);
if (IS_ERR(gpio)) {
r = PTR_ERR(gpio);
goto err_gpio;
}
ddata->hpd_gpio = gpio;
dssdev = &ddata->dssdev;
dssdev->ops.hdmi = &tpd_hdmi_ops;
dssdev->dev = &pdev->dev;
dssdev->type = OMAP_DISPLAY_TYPE_HDMI;
dssdev->output_type = OMAP_DISPLAY_TYPE_HDMI;
dssdev->owner = THIS_MODULE;
dssdev->port_num = 1;
r = omapdss_register_output(dssdev);
if (r) {
dev_err(&pdev->dev, "Failed to register output\n");
goto err_reg;
}
return 0;
err_reg:
err_gpio:
omap_dss_put_device(ddata->in);
return r;
}
static int __exit tpd_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_output(&ddata->dssdev);
WARN_ON(omapdss_device_is_enabled(dssdev));
if (omapdss_device_is_enabled(dssdev))
tpd_disable(dssdev);
WARN_ON(omapdss_device_is_connected(dssdev));
if (omapdss_device_is_connected(dssdev))
tpd_disconnect(dssdev, dssdev->dst);
omap_dss_put_device(in);
return 0;
}
static const struct of_device_id tpd_of_match[] = {
{ .compatible = "omapdss,ti,tpd12s015", },
{},
};
MODULE_DEVICE_TABLE(of, tpd_of_match);
static struct platform_driver tpd_driver = {
.probe = tpd_probe,
.remove = __exit_p(tpd_remove),
.driver = {
.name = "tpd12s015",
.of_match_table = tpd_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(tpd_driver);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("TPD12S015 driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/encoder-tpd12s015.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* TPO TD043MTEA1 Panel driver
*
* Author: Gražvydas Ignotas <[email protected]>
* Converted to new DSS device model: Tomi Valkeinen <[email protected]>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <video/omapfb_dss.h>
#define TPO_R02_MODE(x) ((x) & 7)
#define TPO_R02_MODE_800x480 7
#define TPO_R02_NCLK_RISING BIT(3)
#define TPO_R02_HSYNC_HIGH BIT(4)
#define TPO_R02_VSYNC_HIGH BIT(5)
#define TPO_R03_NSTANDBY BIT(0)
#define TPO_R03_EN_CP_CLK BIT(1)
#define TPO_R03_EN_VGL_PUMP BIT(2)
#define TPO_R03_EN_PWM BIT(3)
#define TPO_R03_DRIVING_CAP_100 BIT(4)
#define TPO_R03_EN_PRE_CHARGE BIT(6)
#define TPO_R03_SOFTWARE_CTL BIT(7)
#define TPO_R04_NFLIP_H BIT(0)
#define TPO_R04_NFLIP_V BIT(1)
#define TPO_R04_CP_CLK_FREQ_1H BIT(2)
#define TPO_R04_VGL_FREQ_1H BIT(4)
#define TPO_R03_VAL_NORMAL (TPO_R03_NSTANDBY | TPO_R03_EN_CP_CLK | \
TPO_R03_EN_VGL_PUMP | TPO_R03_EN_PWM | \
TPO_R03_DRIVING_CAP_100 | TPO_R03_EN_PRE_CHARGE | \
TPO_R03_SOFTWARE_CTL)
#define TPO_R03_VAL_STANDBY (TPO_R03_DRIVING_CAP_100 | \
TPO_R03_EN_PRE_CHARGE | TPO_R03_SOFTWARE_CTL)
static const u16 tpo_td043_def_gamma[12] = {
105, 315, 381, 431, 490, 537, 579, 686, 780, 837, 880, 1023
};
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct omap_video_timings videomode;
int data_lines;
struct spi_device *spi;
struct regulator *vcc_reg;
struct gpio_desc *reset_gpio;
u16 gamma[12];
u32 mode;
u32 hmirror:1;
u32 vmirror:1;
u32 powered_on:1;
u32 spi_suspended:1;
u32 power_on_resume:1;
};
static const struct omap_video_timings tpo_td043_timings = {
.x_res = 800,
.y_res = 480,
.pixelclock = 36000000,
.hsw = 1,
.hfp = 68,
.hbp = 214,
.vsw = 1,
.vfp = 39,
.vbp = 34,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
};
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
static int tpo_td043_write(struct spi_device *spi, u8 addr, u8 data)
{
struct spi_message m;
struct spi_transfer xfer;
u16 w;
int r;
spi_message_init(&m);
memset(&xfer, 0, sizeof(xfer));
w = ((u16)addr << 10) | (1 << 8) | data;
xfer.tx_buf = &w;
xfer.bits_per_word = 16;
xfer.len = 2;
spi_message_add_tail(&xfer, &m);
r = spi_sync(spi, &m);
if (r < 0)
dev_warn(&spi->dev, "failed to write to LCD reg (%d)\n", r);
return r;
}
static void tpo_td043_write_gamma(struct spi_device *spi, u16 gamma[12])
{
u8 i, val;
/* gamma bits [9:8] */
for (val = i = 0; i < 4; i++)
val |= (gamma[i] & 0x300) >> ((i + 1) * 2);
tpo_td043_write(spi, 0x11, val);
for (val = i = 0; i < 4; i++)
val |= (gamma[i+4] & 0x300) >> ((i + 1) * 2);
tpo_td043_write(spi, 0x12, val);
for (val = i = 0; i < 4; i++)
val |= (gamma[i+8] & 0x300) >> ((i + 1) * 2);
tpo_td043_write(spi, 0x13, val);
/* gamma bits [7:0] */
for (val = i = 0; i < 12; i++)
tpo_td043_write(spi, 0x14 + i, gamma[i] & 0xff);
}
static int tpo_td043_write_mirror(struct spi_device *spi, bool h, bool v)
{
u8 reg4 = TPO_R04_NFLIP_H | TPO_R04_NFLIP_V |
TPO_R04_CP_CLK_FREQ_1H | TPO_R04_VGL_FREQ_1H;
if (h)
reg4 &= ~TPO_R04_NFLIP_H;
if (v)
reg4 &= ~TPO_R04_NFLIP_V;
return tpo_td043_write(spi, 4, reg4);
}
static int tpo_td043_set_hmirror(struct omap_dss_device *dssdev, bool enable)
{
struct panel_drv_data *ddata = dev_get_drvdata(dssdev->dev);
ddata->hmirror = enable;
return tpo_td043_write_mirror(ddata->spi, ddata->hmirror,
ddata->vmirror);
}
static bool tpo_td043_get_hmirror(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = dev_get_drvdata(dssdev->dev);
return ddata->hmirror;
}
static ssize_t tpo_td043_vmirror_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", ddata->vmirror);
}
static ssize_t tpo_td043_vmirror_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
int val;
int ret;
ret = kstrtoint(buf, 0, &val);
if (ret < 0)
return ret;
val = !!val;
ret = tpo_td043_write_mirror(ddata->spi, ddata->hmirror, val);
if (ret < 0)
return ret;
ddata->vmirror = val;
return count;
}
static ssize_t tpo_td043_mode_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
return sysfs_emit(buf, "%d\n", ddata->mode);
}
static ssize_t tpo_td043_mode_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
long val;
int ret;
ret = kstrtol(buf, 0, &val);
if (ret != 0 || val & ~7)
return -EINVAL;
ddata->mode = val;
val |= TPO_R02_NCLK_RISING;
tpo_td043_write(ddata->spi, 2, val);
return count;
}
static ssize_t tpo_td043_gamma_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
ssize_t len = 0;
int ret;
int i;
for (i = 0; i < ARRAY_SIZE(ddata->gamma); i++) {
ret = snprintf(buf + len, PAGE_SIZE - len, "%u ",
ddata->gamma[i]);
if (ret < 0)
return ret;
len += ret;
}
buf[len - 1] = '\n';
return len;
}
static ssize_t tpo_td043_gamma_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
unsigned int g[12];
int ret;
int i;
ret = sscanf(buf, "%u %u %u %u %u %u %u %u %u %u %u %u",
&g[0], &g[1], &g[2], &g[3], &g[4], &g[5],
&g[6], &g[7], &g[8], &g[9], &g[10], &g[11]);
if (ret != 12)
return -EINVAL;
for (i = 0; i < 12; i++)
ddata->gamma[i] = g[i];
tpo_td043_write_gamma(ddata->spi, ddata->gamma);
return count;
}
static DEVICE_ATTR(vmirror, S_IRUGO | S_IWUSR,
tpo_td043_vmirror_show, tpo_td043_vmirror_store);
static DEVICE_ATTR(mode, S_IRUGO | S_IWUSR,
tpo_td043_mode_show, tpo_td043_mode_store);
static DEVICE_ATTR(gamma, S_IRUGO | S_IWUSR,
tpo_td043_gamma_show, tpo_td043_gamma_store);
static struct attribute *tpo_td043_attrs[] = {
&dev_attr_vmirror.attr,
&dev_attr_mode.attr,
&dev_attr_gamma.attr,
NULL,
};
static const struct attribute_group tpo_td043_attr_group = {
.attrs = tpo_td043_attrs,
};
static int tpo_td043_power_on(struct panel_drv_data *ddata)
{
int r;
if (ddata->powered_on)
return 0;
r = regulator_enable(ddata->vcc_reg);
if (r != 0)
return r;
/* wait for panel to stabilize */
msleep(160);
gpiod_set_value_cansleep(ddata->reset_gpio, 0);
tpo_td043_write(ddata->spi, 2,
TPO_R02_MODE(ddata->mode) | TPO_R02_NCLK_RISING);
tpo_td043_write(ddata->spi, 3, TPO_R03_VAL_NORMAL);
tpo_td043_write(ddata->spi, 0x20, 0xf0);
tpo_td043_write(ddata->spi, 0x21, 0xf0);
tpo_td043_write_mirror(ddata->spi, ddata->hmirror,
ddata->vmirror);
tpo_td043_write_gamma(ddata->spi, ddata->gamma);
ddata->powered_on = 1;
return 0;
}
static void tpo_td043_power_off(struct panel_drv_data *ddata)
{
if (!ddata->powered_on)
return;
tpo_td043_write(ddata->spi, 3,
TPO_R03_VAL_STANDBY | TPO_R03_EN_PWM);
gpiod_set_value_cansleep(ddata->reset_gpio, 1);
/* wait for at least 2 vsyncs before cutting off power */
msleep(50);
tpo_td043_write(ddata->spi, 3, TPO_R03_VAL_STANDBY);
regulator_disable(ddata->vcc_reg);
ddata->powered_on = 0;
}
static int tpo_td043_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (omapdss_device_is_connected(dssdev))
return 0;
return in->ops.dpi->connect(in, dssdev);
}
static void tpo_td043_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.dpi->disconnect(in, dssdev);
}
static int tpo_td043_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
if (ddata->data_lines)
in->ops.dpi->set_data_lines(in, ddata->data_lines);
in->ops.dpi->set_timings(in, &ddata->videomode);
r = in->ops.dpi->enable(in);
if (r)
return r;
/*
* If we are resuming from system suspend, SPI clocks might not be
* enabled yet, so we'll program the LCD from SPI PM resume callback.
*/
if (!ddata->spi_suspended) {
r = tpo_td043_power_on(ddata);
if (r) {
in->ops.dpi->disable(in);
return r;
}
}
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void tpo_td043_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_enabled(dssdev))
return;
in->ops.dpi->disable(in);
if (!ddata->spi_suspended)
tpo_td043_power_off(ddata);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void tpo_td043_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->videomode = *timings;
dssdev->panel.timings = *timings;
in->ops.dpi->set_timings(in, timings);
}
static void tpo_td043_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->videomode;
}
static int tpo_td043_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.dpi->check_timings(in, timings);
}
static struct omap_dss_driver tpo_td043_ops = {
.connect = tpo_td043_connect,
.disconnect = tpo_td043_disconnect,
.enable = tpo_td043_enable,
.disable = tpo_td043_disable,
.set_timings = tpo_td043_set_timings,
.get_timings = tpo_td043_get_timings,
.check_timings = tpo_td043_check_timings,
.set_mirror = tpo_td043_set_hmirror,
.get_mirror = tpo_td043_get_hmirror,
.get_resolution = omapdss_default_get_resolution,
};
static int tpo_td043_probe(struct spi_device *spi)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
dev_dbg(&spi->dev, "%s\n", __func__);
if (!spi->dev.of_node)
return -ENODEV;
spi->bits_per_word = 16;
spi->mode = SPI_MODE_0;
r = spi_setup(spi);
if (r < 0) {
dev_err(&spi->dev, "spi_setup failed: %d\n", r);
return r;
}
ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
if (ddata == NULL)
return -ENOMEM;
dev_set_drvdata(&spi->dev, ddata);
ddata->spi = spi;
ddata->in = omapdss_of_find_source_for_first_ep(spi->dev.of_node);
r = PTR_ERR_OR_ZERO(ddata->in);
if (r) {
dev_err(&spi->dev, "failed to find video source: %d\n", r);
return r;
}
ddata->mode = TPO_R02_MODE_800x480;
memcpy(ddata->gamma, tpo_td043_def_gamma, sizeof(ddata->gamma));
ddata->vcc_reg = devm_regulator_get(&spi->dev, "vcc");
if (IS_ERR(ddata->vcc_reg)) {
r = dev_err_probe(&spi->dev, PTR_ERR(ddata->vcc_reg),
"failed to get LCD VCC regulator\n");
goto err_regulator;
}
ddata->reset_gpio = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH);
r = PTR_ERR_OR_ZERO(ddata->reset_gpio);
if (r) {
dev_err(&spi->dev, "couldn't request reset GPIO\n");
goto err_gpio_req;
}
gpiod_set_consumer_name(ddata->reset_gpio, "lcd reset");
r = sysfs_create_group(&spi->dev.kobj, &tpo_td043_attr_group);
if (r) {
dev_err(&spi->dev, "failed to create sysfs files\n");
goto err_sysfs;
}
ddata->videomode = tpo_td043_timings;
dssdev = &ddata->dssdev;
dssdev->dev = &spi->dev;
dssdev->driver = &tpo_td043_ops;
dssdev->type = OMAP_DISPLAY_TYPE_DPI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = ddata->videomode;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&spi->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
sysfs_remove_group(&spi->dev.kobj, &tpo_td043_attr_group);
err_sysfs:
err_gpio_req:
err_regulator:
omap_dss_put_device(ddata->in);
return r;
}
static void tpo_td043_remove(struct spi_device *spi)
{
struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
dev_dbg(&ddata->spi->dev, "%s\n", __func__);
omapdss_unregister_display(dssdev);
tpo_td043_disable(dssdev);
tpo_td043_disconnect(dssdev);
omap_dss_put_device(in);
sysfs_remove_group(&spi->dev.kobj, &tpo_td043_attr_group);
}
#ifdef CONFIG_PM_SLEEP
static int tpo_td043_spi_suspend(struct device *dev)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
dev_dbg(dev, "tpo_td043_spi_suspend, tpo %p\n", ddata);
ddata->power_on_resume = ddata->powered_on;
tpo_td043_power_off(ddata);
ddata->spi_suspended = 1;
return 0;
}
static int tpo_td043_spi_resume(struct device *dev)
{
struct panel_drv_data *ddata = dev_get_drvdata(dev);
int ret;
dev_dbg(dev, "tpo_td043_spi_resume\n");
if (ddata->power_on_resume) {
ret = tpo_td043_power_on(ddata);
if (ret)
return ret;
}
ddata->spi_suspended = 0;
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(tpo_td043_spi_pm,
tpo_td043_spi_suspend, tpo_td043_spi_resume);
static const struct of_device_id tpo_td043_of_match[] = {
{ .compatible = "omapdss,tpo,td043mtea1", },
{},
};
MODULE_DEVICE_TABLE(of, tpo_td043_of_match);
static struct spi_driver tpo_td043_spi_driver = {
.driver = {
.name = "panel-tpo-td043mtea1",
.pm = &tpo_td043_spi_pm,
.of_match_table = tpo_td043_of_match,
.suppress_bind_attrs = true,
},
.probe = tpo_td043_probe,
.remove = tpo_td043_remove,
};
module_spi_driver(tpo_td043_spi_driver);
MODULE_ALIAS("spi:tpo,td043mtea1");
MODULE_AUTHOR("Gražvydas Ignotas <[email protected]>");
MODULE_DESCRIPTION("TPO TD043MTEA1 LCD Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/panel-tpo-td043mtea1.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* NEC NL8048HL11 Panel driver
*
* Copyright (C) 2010 Texas Instruments Inc.
* Author: Erik Gilling <[email protected]>
* Converted to new DSS device model: Tomi Valkeinen <[email protected]>
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <video/omapfb_dss.h>
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct omap_video_timings videomode;
int data_lines;
struct gpio_desc *res_gpio;
struct spi_device *spi;
};
#define LCD_XRES 800
#define LCD_YRES 480
/*
* NEC PIX Clock Ratings
* MIN:21.8MHz TYP:23.8MHz MAX:25.7MHz
*/
#define LCD_PIXEL_CLOCK 23800000
static const struct {
unsigned char addr;
unsigned char dat;
} nec_8048_init_seq[] = {
{ 3, 0x01 }, { 0, 0x00 }, { 1, 0x01 }, { 4, 0x00 }, { 5, 0x14 },
{ 6, 0x24 }, { 16, 0xD7 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x55 },
{ 20, 0x01 }, { 21, 0x70 }, { 22, 0x1E }, { 23, 0x25 }, { 24, 0x25 },
{ 25, 0x02 }, { 26, 0x02 }, { 27, 0xA0 }, { 32, 0x2F }, { 33, 0x0F },
{ 34, 0x0F }, { 35, 0x0F }, { 36, 0x0F }, { 37, 0x0F }, { 38, 0x0F },
{ 39, 0x00 }, { 40, 0x02 }, { 41, 0x02 }, { 42, 0x02 }, { 43, 0x0F },
{ 44, 0x0F }, { 45, 0x0F }, { 46, 0x0F }, { 47, 0x0F }, { 48, 0x0F },
{ 49, 0x0F }, { 50, 0x00 }, { 51, 0x02 }, { 52, 0x02 }, { 53, 0x02 },
{ 80, 0x0C }, { 83, 0x42 }, { 84, 0x42 }, { 85, 0x41 }, { 86, 0x14 },
{ 89, 0x88 }, { 90, 0x01 }, { 91, 0x00 }, { 92, 0x02 }, { 93, 0x0C },
{ 94, 0x1C }, { 95, 0x27 }, { 98, 0x49 }, { 99, 0x27 }, { 102, 0x76 },
{ 103, 0x27 }, { 112, 0x01 }, { 113, 0x0E }, { 114, 0x02 },
{ 115, 0x0C }, { 118, 0x0C }, { 121, 0x30 }, { 130, 0x00 },
{ 131, 0x00 }, { 132, 0xFC }, { 134, 0x00 }, { 136, 0x00 },
{ 138, 0x00 }, { 139, 0x00 }, { 140, 0x00 }, { 141, 0xFC },
{ 143, 0x00 }, { 145, 0x00 }, { 147, 0x00 }, { 148, 0x00 },
{ 149, 0x00 }, { 150, 0xFC }, { 152, 0x00 }, { 154, 0x00 },
{ 156, 0x00 }, { 157, 0x00 }, { 2, 0x00 },
};
static const struct omap_video_timings nec_8048_panel_timings = {
.x_res = LCD_XRES,
.y_res = LCD_YRES,
.pixelclock = LCD_PIXEL_CLOCK,
.hfp = 6,
.hsw = 1,
.hbp = 4,
.vfp = 3,
.vsw = 1,
.vbp = 4,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
};
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
static int nec_8048_spi_send(struct spi_device *spi, unsigned char reg_addr,
unsigned char reg_data)
{
int ret = 0;
unsigned int cmd = 0, data = 0;
cmd = 0x0000 | reg_addr; /* register address write */
data = 0x0100 | reg_data; /* register data write */
data = (cmd << 16) | data;
ret = spi_write(spi, (unsigned char *)&data, 4);
if (ret)
pr_err("error in spi_write %x\n", data);
return ret;
}
static int init_nec_8048_wvga_lcd(struct spi_device *spi)
{
unsigned int i;
/* Initialization Sequence */
/* nec_8048_spi_send(spi, REG, VAL) */
for (i = 0; i < (ARRAY_SIZE(nec_8048_init_seq) - 1); i++)
nec_8048_spi_send(spi, nec_8048_init_seq[i].addr,
nec_8048_init_seq[i].dat);
udelay(20);
nec_8048_spi_send(spi, nec_8048_init_seq[i].addr,
nec_8048_init_seq[i].dat);
return 0;
}
static int nec_8048_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (omapdss_device_is_connected(dssdev))
return 0;
return in->ops.dpi->connect(in, dssdev);
}
static void nec_8048_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.dpi->disconnect(in, dssdev);
}
static int nec_8048_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
if (ddata->data_lines)
in->ops.dpi->set_data_lines(in, ddata->data_lines);
in->ops.dpi->set_timings(in, &ddata->videomode);
r = in->ops.dpi->enable(in);
if (r)
return r;
/* Apparently existing DTSes use incorrect polarity (active high) */
gpiod_set_value_cansleep(ddata->res_gpio, 1);
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void nec_8048_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_enabled(dssdev))
return;
/* Apparently existing DTSes use incorrect polarity (active high) */
gpiod_set_value_cansleep(ddata->res_gpio, 0);
in->ops.dpi->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void nec_8048_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->videomode = *timings;
dssdev->panel.timings = *timings;
in->ops.dpi->set_timings(in, timings);
}
static void nec_8048_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->videomode;
}
static int nec_8048_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.dpi->check_timings(in, timings);
}
static struct omap_dss_driver nec_8048_ops = {
.connect = nec_8048_connect,
.disconnect = nec_8048_disconnect,
.enable = nec_8048_enable,
.disable = nec_8048_disable,
.set_timings = nec_8048_set_timings,
.get_timings = nec_8048_get_timings,
.check_timings = nec_8048_check_timings,
.get_resolution = omapdss_default_get_resolution,
};
static int nec_8048_probe(struct spi_device *spi)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
dev_dbg(&spi->dev, "%s\n", __func__);
if (!spi->dev.of_node)
return -ENODEV;
spi->mode = SPI_MODE_0;
spi->bits_per_word = 32;
r = spi_setup(spi);
if (r < 0) {
dev_err(&spi->dev, "spi_setup failed: %d\n", r);
return r;
}
init_nec_8048_wvga_lcd(spi);
ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
if (ddata == NULL)
return -ENOMEM;
dev_set_drvdata(&spi->dev, ddata);
ddata->spi = spi;
ddata->in = omapdss_of_find_source_for_first_ep(spi->dev.of_node);
r = PTR_ERR_OR_ZERO(ddata->in);
if (r) {
dev_err(&spi->dev, "failed to find video source: %d\n", r);
return r;
}
ddata->res_gpio = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_LOW);
r = PTR_ERR_OR_ZERO(ddata->res_gpio);
if (r) {
dev_err(&spi->dev, "failed to request reset gpio: %d\n", r);
goto err_gpio;
}
gpiod_set_consumer_name(ddata->res_gpio, "lcd RES");
ddata->videomode = nec_8048_panel_timings;
dssdev = &ddata->dssdev;
dssdev->dev = &spi->dev;
dssdev->driver = &nec_8048_ops;
dssdev->type = OMAP_DISPLAY_TYPE_DPI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = ddata->videomode;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&spi->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
err_gpio:
omap_dss_put_device(ddata->in);
return r;
}
static void nec_8048_remove(struct spi_device *spi)
{
struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
dev_dbg(&ddata->spi->dev, "%s\n", __func__);
omapdss_unregister_display(dssdev);
nec_8048_disable(dssdev);
nec_8048_disconnect(dssdev);
omap_dss_put_device(in);
}
#ifdef CONFIG_PM_SLEEP
static int nec_8048_suspend(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
nec_8048_spi_send(spi, 2, 0x01);
mdelay(40);
return 0;
}
static int nec_8048_resume(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
/* reinitialize the panel */
spi_setup(spi);
nec_8048_spi_send(spi, 2, 0x00);
init_nec_8048_wvga_lcd(spi);
return 0;
}
static SIMPLE_DEV_PM_OPS(nec_8048_pm_ops, nec_8048_suspend,
nec_8048_resume);
#define NEC_8048_PM_OPS (&nec_8048_pm_ops)
#else
#define NEC_8048_PM_OPS NULL
#endif
static const struct of_device_id nec_8048_of_match[] = {
{ .compatible = "omapdss,nec,nl8048hl11", },
{},
};
MODULE_DEVICE_TABLE(of, nec_8048_of_match);
static struct spi_driver nec_8048_driver = {
.driver = {
.name = "panel-nec-nl8048hl11",
.pm = NEC_8048_PM_OPS,
.of_match_table = nec_8048_of_match,
.suppress_bind_attrs = true,
},
.probe = nec_8048_probe,
.remove = nec_8048_remove,
};
module_spi_driver(nec_8048_driver);
MODULE_ALIAS("spi:nec,nl8048hl11");
MODULE_AUTHOR("Erik Gilling <[email protected]>");
MODULE_DESCRIPTION("NEC-NL8048HL11 Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/panel-nec-nl8048hl11.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* LCD panel driver for Sharp LS037V7DW01
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <video/omapfb_dss.h>
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct regulator *vcc;
int data_lines;
struct omap_video_timings videomode;
struct gpio_desc *resb_gpio; /* low = reset active min 20 us */
struct gpio_desc *ini_gpio; /* high = power on */
struct gpio_desc *mo_gpio; /* low = 480x640, high = 240x320 */
struct gpio_desc *lr_gpio; /* high = conventional horizontal scanning */
struct gpio_desc *ud_gpio; /* high = conventional vertical scanning */
};
static const struct omap_video_timings sharp_ls_timings = {
.x_res = 480,
.y_res = 640,
.pixelclock = 19200000,
.hsw = 2,
.hfp = 1,
.hbp = 28,
.vsw = 1,
.vfp = 1,
.vbp = 1,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
};
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
static int sharp_ls_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (omapdss_device_is_connected(dssdev))
return 0;
return in->ops.dpi->connect(in, dssdev);
}
static void sharp_ls_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.dpi->disconnect(in, dssdev);
}
static int sharp_ls_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
if (ddata->data_lines)
in->ops.dpi->set_data_lines(in, ddata->data_lines);
in->ops.dpi->set_timings(in, &ddata->videomode);
if (ddata->vcc) {
r = regulator_enable(ddata->vcc);
if (r != 0)
return r;
}
r = in->ops.dpi->enable(in);
if (r) {
regulator_disable(ddata->vcc);
return r;
}
/* wait couple of vsyncs until enabling the LCD */
msleep(50);
if (ddata->resb_gpio)
gpiod_set_value_cansleep(ddata->resb_gpio, 1);
if (ddata->ini_gpio)
gpiod_set_value_cansleep(ddata->ini_gpio, 1);
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void sharp_ls_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_enabled(dssdev))
return;
if (ddata->ini_gpio)
gpiod_set_value_cansleep(ddata->ini_gpio, 0);
if (ddata->resb_gpio)
gpiod_set_value_cansleep(ddata->resb_gpio, 0);
/* wait at least 5 vsyncs after disabling the LCD */
msleep(100);
in->ops.dpi->disable(in);
if (ddata->vcc)
regulator_disable(ddata->vcc);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void sharp_ls_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->videomode = *timings;
dssdev->panel.timings = *timings;
in->ops.dpi->set_timings(in, timings);
}
static void sharp_ls_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->videomode;
}
static int sharp_ls_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.dpi->check_timings(in, timings);
}
static struct omap_dss_driver sharp_ls_ops = {
.connect = sharp_ls_connect,
.disconnect = sharp_ls_disconnect,
.enable = sharp_ls_enable,
.disable = sharp_ls_disable,
.set_timings = sharp_ls_set_timings,
.get_timings = sharp_ls_get_timings,
.check_timings = sharp_ls_check_timings,
.get_resolution = omapdss_default_get_resolution,
};
static int sharp_ls_get_gpio_of(struct device *dev, int index, int val,
const char *desc, struct gpio_desc **gpiod)
{
struct gpio_desc *gd;
*gpiod = NULL;
gd = devm_gpiod_get_index(dev, desc, index, GPIOD_OUT_LOW);
if (IS_ERR(gd))
return PTR_ERR(gd);
*gpiod = gd;
return 0;
}
static int sharp_ls_probe_of(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
struct omap_dss_device *in;
int r;
ddata->vcc = devm_regulator_get(&pdev->dev, "envdd");
if (IS_ERR(ddata->vcc))
return dev_err_probe(&pdev->dev, PTR_ERR(ddata->vcc),
"failed to get regulator\n");
/* lcd INI */
r = sharp_ls_get_gpio_of(&pdev->dev, 0, 0, "enable", &ddata->ini_gpio);
if (r)
return r;
/* lcd RESB */
r = sharp_ls_get_gpio_of(&pdev->dev, 0, 0, "reset", &ddata->resb_gpio);
if (r)
return r;
/* lcd MO */
r = sharp_ls_get_gpio_of(&pdev->dev, 0, 0, "mode", &ddata->mo_gpio);
if (r)
return r;
/* lcd LR */
r = sharp_ls_get_gpio_of(&pdev->dev, 1, 1, "mode", &ddata->lr_gpio);
if (r)
return r;
/* lcd UD */
r = sharp_ls_get_gpio_of(&pdev->dev, 2, 1, "mode", &ddata->ud_gpio);
if (r)
return r;
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&pdev->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
return 0;
}
static int sharp_ls_probe(struct platform_device *pdev)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
if (!pdev->dev.of_node)
return -ENODEV;
ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
if (ddata == NULL)
return -ENOMEM;
platform_set_drvdata(pdev, ddata);
r = sharp_ls_probe_of(pdev);
if (r)
return r;
ddata->videomode = sharp_ls_timings;
dssdev = &ddata->dssdev;
dssdev->dev = &pdev->dev;
dssdev->driver = &sharp_ls_ops;
dssdev->type = OMAP_DISPLAY_TYPE_DPI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = ddata->videomode;
dssdev->phy.dpi.data_lines = ddata->data_lines;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&pdev->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
return r;
}
static int __exit sharp_ls_remove(struct platform_device *pdev)
{
struct panel_drv_data *ddata = platform_get_drvdata(pdev);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_display(dssdev);
sharp_ls_disable(dssdev);
sharp_ls_disconnect(dssdev);
omap_dss_put_device(in);
return 0;
}
static const struct of_device_id sharp_ls_of_match[] = {
{ .compatible = "omapdss,sharp,ls037v7dw01", },
{},
};
MODULE_DEVICE_TABLE(of, sharp_ls_of_match);
static struct platform_driver sharp_ls_driver = {
.probe = sharp_ls_probe,
.remove = __exit_p(sharp_ls_remove),
.driver = {
.name = "panel-sharp-ls037v7dw01",
.of_match_table = sharp_ls_of_match,
.suppress_bind_attrs = true,
},
};
module_platform_driver(sharp_ls_driver);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("Sharp LS037V7DW01 Panel Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/panel-sharp-ls037v7dw01.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* LG.Philips LB035Q02 LCD Panel driver
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
* Based on a driver by: Steve Sakoman <[email protected]>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/mutex.h>
#include <linux/gpio/consumer.h>
#include <video/omapfb_dss.h>
static const struct omap_video_timings lb035q02_timings = {
.x_res = 320,
.y_res = 240,
.pixelclock = 6500000,
.hsw = 2,
.hfp = 20,
.hbp = 68,
.vsw = 2,
.vfp = 4,
.vbp = 18,
.vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
.de_level = OMAPDSS_SIG_ACTIVE_HIGH,
.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
};
struct panel_drv_data {
struct omap_dss_device dssdev;
struct omap_dss_device *in;
struct spi_device *spi;
int data_lines;
struct omap_video_timings videomode;
struct gpio_desc *enable_gpio;
};
#define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
static int lb035q02_write_reg(struct spi_device *spi, u8 reg, u16 val)
{
struct spi_message msg;
struct spi_transfer index_xfer = {
.len = 3,
.cs_change = 1,
};
struct spi_transfer value_xfer = {
.len = 3,
};
u8 buffer[16];
spi_message_init(&msg);
/* register index */
buffer[0] = 0x70;
buffer[1] = 0x00;
buffer[2] = reg & 0x7f;
index_xfer.tx_buf = buffer;
spi_message_add_tail(&index_xfer, &msg);
/* register value */
buffer[4] = 0x72;
buffer[5] = val >> 8;
buffer[6] = val;
value_xfer.tx_buf = buffer + 4;
spi_message_add_tail(&value_xfer, &msg);
return spi_sync(spi, &msg);
}
static void init_lb035q02_panel(struct spi_device *spi)
{
/* Init sequence from page 28 of the lb035q02 spec */
lb035q02_write_reg(spi, 0x01, 0x6300);
lb035q02_write_reg(spi, 0x02, 0x0200);
lb035q02_write_reg(spi, 0x03, 0x0177);
lb035q02_write_reg(spi, 0x04, 0x04c7);
lb035q02_write_reg(spi, 0x05, 0xffc0);
lb035q02_write_reg(spi, 0x06, 0xe806);
lb035q02_write_reg(spi, 0x0a, 0x4008);
lb035q02_write_reg(spi, 0x0b, 0x0000);
lb035q02_write_reg(spi, 0x0d, 0x0030);
lb035q02_write_reg(spi, 0x0e, 0x2800);
lb035q02_write_reg(spi, 0x0f, 0x0000);
lb035q02_write_reg(spi, 0x16, 0x9f80);
lb035q02_write_reg(spi, 0x17, 0x0a0f);
lb035q02_write_reg(spi, 0x1e, 0x00c1);
lb035q02_write_reg(spi, 0x30, 0x0300);
lb035q02_write_reg(spi, 0x31, 0x0007);
lb035q02_write_reg(spi, 0x32, 0x0000);
lb035q02_write_reg(spi, 0x33, 0x0000);
lb035q02_write_reg(spi, 0x34, 0x0707);
lb035q02_write_reg(spi, 0x35, 0x0004);
lb035q02_write_reg(spi, 0x36, 0x0302);
lb035q02_write_reg(spi, 0x37, 0x0202);
lb035q02_write_reg(spi, 0x3a, 0x0a0d);
lb035q02_write_reg(spi, 0x3b, 0x0806);
}
static int lb035q02_connect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (omapdss_device_is_connected(dssdev))
return 0;
r = in->ops.dpi->connect(in, dssdev);
if (r)
return r;
init_lb035q02_panel(ddata->spi);
return 0;
}
static void lb035q02_disconnect(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_connected(dssdev))
return;
in->ops.dpi->disconnect(in, dssdev);
}
static int lb035q02_enable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
int r;
if (!omapdss_device_is_connected(dssdev))
return -ENODEV;
if (omapdss_device_is_enabled(dssdev))
return 0;
if (ddata->data_lines)
in->ops.dpi->set_data_lines(in, ddata->data_lines);
in->ops.dpi->set_timings(in, &ddata->videomode);
r = in->ops.dpi->enable(in);
if (r)
return r;
if (ddata->enable_gpio)
gpiod_set_value_cansleep(ddata->enable_gpio, 1);
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
return 0;
}
static void lb035q02_disable(struct omap_dss_device *dssdev)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
if (!omapdss_device_is_enabled(dssdev))
return;
if (ddata->enable_gpio)
gpiod_set_value_cansleep(ddata->enable_gpio, 0);
in->ops.dpi->disable(in);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
}
static void lb035q02_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
ddata->videomode = *timings;
dssdev->panel.timings = *timings;
in->ops.dpi->set_timings(in, timings);
}
static void lb035q02_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
*timings = ddata->videomode;
}
static int lb035q02_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct panel_drv_data *ddata = to_panel_data(dssdev);
struct omap_dss_device *in = ddata->in;
return in->ops.dpi->check_timings(in, timings);
}
static struct omap_dss_driver lb035q02_ops = {
.connect = lb035q02_connect,
.disconnect = lb035q02_disconnect,
.enable = lb035q02_enable,
.disable = lb035q02_disable,
.set_timings = lb035q02_set_timings,
.get_timings = lb035q02_get_timings,
.check_timings = lb035q02_check_timings,
.get_resolution = omapdss_default_get_resolution,
};
static int lb035q02_probe_of(struct spi_device *spi)
{
struct device_node *node = spi->dev.of_node;
struct panel_drv_data *ddata = spi_get_drvdata(spi);
struct omap_dss_device *in;
struct gpio_desc *gpio;
gpio = devm_gpiod_get(&spi->dev, "enable", GPIOD_OUT_LOW);
if (IS_ERR(gpio))
return dev_err_probe(&spi->dev, PTR_ERR(gpio),
"failed to parse enable gpio\n");
ddata->enable_gpio = gpio;
in = omapdss_of_find_source_for_first_ep(node);
if (IS_ERR(in)) {
dev_err(&spi->dev, "failed to find video source\n");
return PTR_ERR(in);
}
ddata->in = in;
return 0;
}
static int lb035q02_panel_spi_probe(struct spi_device *spi)
{
struct panel_drv_data *ddata;
struct omap_dss_device *dssdev;
int r;
if (!spi->dev.of_node)
return -ENODEV;
ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
if (ddata == NULL)
return -ENOMEM;
spi_set_drvdata(spi, ddata);
ddata->spi = spi;
r = lb035q02_probe_of(spi);
if (r)
return r;
ddata->videomode = lb035q02_timings;
dssdev = &ddata->dssdev;
dssdev->dev = &spi->dev;
dssdev->driver = &lb035q02_ops;
dssdev->type = OMAP_DISPLAY_TYPE_DPI;
dssdev->owner = THIS_MODULE;
dssdev->panel.timings = ddata->videomode;
dssdev->phy.dpi.data_lines = ddata->data_lines;
r = omapdss_register_display(dssdev);
if (r) {
dev_err(&spi->dev, "Failed to register panel\n");
goto err_reg;
}
return 0;
err_reg:
omap_dss_put_device(ddata->in);
return r;
}
static void lb035q02_panel_spi_remove(struct spi_device *spi)
{
struct panel_drv_data *ddata = spi_get_drvdata(spi);
struct omap_dss_device *dssdev = &ddata->dssdev;
struct omap_dss_device *in = ddata->in;
omapdss_unregister_display(dssdev);
lb035q02_disable(dssdev);
lb035q02_disconnect(dssdev);
omap_dss_put_device(in);
}
static const struct of_device_id lb035q02_of_match[] = {
{ .compatible = "omapdss,lgphilips,lb035q02", },
{},
};
MODULE_DEVICE_TABLE(of, lb035q02_of_match);
static struct spi_driver lb035q02_spi_driver = {
.probe = lb035q02_panel_spi_probe,
.remove = lb035q02_panel_spi_remove,
.driver = {
.name = "panel_lgphilips_lb035q02",
.of_match_table = lb035q02_of_match,
.suppress_bind_attrs = true,
},
};
module_spi_driver(lb035q02_spi_driver);
MODULE_ALIAS("spi:lgphilips,lb035q02");
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("LG.Philips LB035Q02 LCD Panel driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/omap2/omapfb/displays/panel-lgphilips-lb035q02.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* OMAP5 HDMI CORE IP driver library
*
* Copyright (C) 2014 Texas Instruments Incorporated
*
* Authors:
* Yong Zhi
* Mythri pk
* Archit Taneja <[email protected]>
* Tomi Valkeinen <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/seq_file.h>
#include <drm/drm_edid.h>
#include <sound/asound.h>
#include <sound/asoundef.h>
#include "hdmi5_core.h"
/* only 24 bit color depth used for now */
static const struct csc_table csc_table_deepcolor[] = {
/* HDMI_DEEP_COLOR_24BIT */
[0] = { 7036, 0, 0, 32, 0, 7036, 0, 32, 0, 0, 7036, 32, },
/* HDMI_DEEP_COLOR_30BIT */
[1] = { 7015, 0, 0, 128, 0, 7015, 0, 128, 0, 0, 7015, 128, },
/* HDMI_DEEP_COLOR_36BIT */
[2] = { 7010, 0, 0, 512, 0, 7010, 0, 512, 0, 0, 7010, 512, },
/* FULL RANGE */
[3] = { 8192, 0, 0, 0, 0, 8192, 0, 0, 0, 0, 8192, 0, },
};
static void hdmi_core_ddc_init(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
const unsigned ss_scl_high = 4600; /* ns */
const unsigned ss_scl_low = 5400; /* ns */
const unsigned fs_scl_high = 600; /* ns */
const unsigned fs_scl_low = 1300; /* ns */
const unsigned sda_hold = 1000; /* ns */
const unsigned sfr_div = 10;
unsigned long long sfr;
unsigned v;
sfr = iclk / sfr_div; /* SFR_DIV */
sfr /= 1000; /* SFR clock in kHz */
/* Reset */
REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0);
if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ,
0, 0, 1) != 1)
DSSERR("HDMI I2CM reset failed\n");
/* Standard (0) or Fast (1) Mode */
REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3);
/* Standard Mode SCL High counter */
v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000);
REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR,
(v >> 8) & 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR,
v & 0xff, 7, 0);
/* Standard Mode SCL Low counter */
v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000);
REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR,
(v >> 8) & 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR,
v & 0xff, 7, 0);
/* Fast Mode SCL High Counter */
v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000);
REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR,
(v >> 8) & 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR,
v & 0xff, 7, 0);
/* Fast Mode SCL Low Counter */
v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000);
REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR,
(v >> 8) & 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR,
v & 0xff, 7, 0);
/* SDA Hold Time */
v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000);
REG_FLD_MOD(base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, v & 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
/* NACK_POL to high */
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 7, 7);
/* NACK_MASK to unmasked */
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
/* ARBITRATION_POL to high */
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 3, 3);
/* ARBITRATION_MASK to unmasked */
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
/* DONE_POL to high */
REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 3, 3);
/* DONE_MASK to unmasked */
REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
}
static void hdmi_core_ddc_uninit(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
/* Mask I2C interrupts */
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
}
static int hdmi_core_ddc_edid(struct hdmi_core_data *core, u8 *pedid, u8 ext)
{
void __iomem *base = core->base;
u8 cur_addr;
const int retries = 1000;
u8 seg_ptr = ext / 2;
u8 edidbase = ((ext % 2) * 0x80);
REG_FLD_MOD(base, HDMI_CORE_I2CM_SEGPTR, seg_ptr, 7, 0);
/*
* TODO: We use polling here, although we probably should use proper
* interrupts.
*/
for (cur_addr = 0; cur_addr < 128; ++cur_addr) {
int i;
/* clear ERROR and DONE */
REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
REG_FLD_MOD(base, HDMI_CORE_I2CM_ADDRESS,
edidbase + cur_addr, 7, 0);
if (seg_ptr)
REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 1, 1);
else
REG_FLD_MOD(base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
for (i = 0; i < retries; ++i) {
u32 stat;
stat = REG_GET(base, HDMI_CORE_IH_I2CM_STAT0, 1, 0);
/* I2CM_ERROR */
if (stat & 1) {
DSSERR("HDMI I2C Master Error\n");
return -EIO;
}
/* I2CM_DONE */
if (stat & (1 << 1))
break;
usleep_range(250, 1000);
}
if (i == retries) {
DSSERR("HDMI I2C timeout reading EDID\n");
return -EIO;
}
pedid[cur_addr] = REG_GET(base, HDMI_CORE_I2CM_DATAI, 7, 0);
}
return 0;
}
int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
{
int r, n, i;
int max_ext_blocks = (len / 128) - 1;
if (len < 128)
return -EINVAL;
hdmi_core_ddc_init(core);
r = hdmi_core_ddc_edid(core, edid, 0);
if (r)
goto out;
n = edid[0x7e];
if (n > max_ext_blocks)
n = max_ext_blocks;
for (i = 1; i <= n; i++) {
r = hdmi_core_ddc_edid(core, edid + i * EDID_LENGTH, i);
if (r)
goto out;
}
out:
hdmi_core_ddc_uninit(core);
return r ? r : len;
}
void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s)
{
#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
hdmi_read_reg(core->base, r))
DUMPCORE(HDMI_CORE_FC_INVIDCONF);
DUMPCORE(HDMI_CORE_FC_INHACTIV0);
DUMPCORE(HDMI_CORE_FC_INHACTIV1);
DUMPCORE(HDMI_CORE_FC_INHBLANK0);
DUMPCORE(HDMI_CORE_FC_INHBLANK1);
DUMPCORE(HDMI_CORE_FC_INVACTIV0);
DUMPCORE(HDMI_CORE_FC_INVACTIV1);
DUMPCORE(HDMI_CORE_FC_INVBLANK);
DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY0);
DUMPCORE(HDMI_CORE_FC_HSYNCINDELAY1);
DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH0);
DUMPCORE(HDMI_CORE_FC_HSYNCINWIDTH1);
DUMPCORE(HDMI_CORE_FC_VSYNCINDELAY);
DUMPCORE(HDMI_CORE_FC_VSYNCINWIDTH);
DUMPCORE(HDMI_CORE_FC_CTRLDUR);
DUMPCORE(HDMI_CORE_FC_EXCTRLDUR);
DUMPCORE(HDMI_CORE_FC_EXCTRLSPAC);
DUMPCORE(HDMI_CORE_FC_CH0PREAM);
DUMPCORE(HDMI_CORE_FC_CH1PREAM);
DUMPCORE(HDMI_CORE_FC_CH2PREAM);
DUMPCORE(HDMI_CORE_FC_AVICONF0);
DUMPCORE(HDMI_CORE_FC_AVICONF1);
DUMPCORE(HDMI_CORE_FC_AVICONF2);
DUMPCORE(HDMI_CORE_FC_AVIVID);
DUMPCORE(HDMI_CORE_FC_PRCONF);
DUMPCORE(HDMI_CORE_MC_CLKDIS);
DUMPCORE(HDMI_CORE_MC_SWRSTZREQ);
DUMPCORE(HDMI_CORE_MC_FLOWCTRL);
DUMPCORE(HDMI_CORE_MC_PHYRSTZ);
DUMPCORE(HDMI_CORE_MC_LOCKONCLOCK);
DUMPCORE(HDMI_CORE_I2CM_SLAVE);
DUMPCORE(HDMI_CORE_I2CM_ADDRESS);
DUMPCORE(HDMI_CORE_I2CM_DATAO);
DUMPCORE(HDMI_CORE_I2CM_DATAI);
DUMPCORE(HDMI_CORE_I2CM_OPERATION);
DUMPCORE(HDMI_CORE_I2CM_INT);
DUMPCORE(HDMI_CORE_I2CM_CTLINT);
DUMPCORE(HDMI_CORE_I2CM_DIV);
DUMPCORE(HDMI_CORE_I2CM_SEGADDR);
DUMPCORE(HDMI_CORE_I2CM_SOFTRSTZ);
DUMPCORE(HDMI_CORE_I2CM_SEGPTR);
DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR);
DUMPCORE(HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR);
DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR);
DUMPCORE(HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR);
DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR);
DUMPCORE(HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR);
DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR);
DUMPCORE(HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR);
DUMPCORE(HDMI_CORE_I2CM_SDA_HOLD_ADDR);
}
static void hdmi_core_init(struct hdmi_core_vid_config *video_cfg,
struct hdmi_config *cfg)
{
DSSDBG("hdmi_core_init\n");
/* video core */
video_cfg->data_enable_pol = 1; /* It is always 1*/
video_cfg->v_fc_config.timings.hsync_level = cfg->timings.hsync_level;
video_cfg->v_fc_config.timings.x_res = cfg->timings.x_res;
video_cfg->v_fc_config.timings.hsw = cfg->timings.hsw - 1;
video_cfg->v_fc_config.timings.hbp = cfg->timings.hbp;
video_cfg->v_fc_config.timings.hfp = cfg->timings.hfp;
video_cfg->hblank = cfg->timings.hfp +
cfg->timings.hbp + cfg->timings.hsw - 1;
video_cfg->v_fc_config.timings.vsync_level = cfg->timings.vsync_level;
video_cfg->v_fc_config.timings.y_res = cfg->timings.y_res;
video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw;
video_cfg->v_fc_config.timings.vfp = cfg->timings.vfp;
video_cfg->v_fc_config.timings.vbp = cfg->timings.vbp;
video_cfg->vblank_osc = 0; /* Always 0 - need to confirm */
video_cfg->vblank = cfg->timings.vsw +
cfg->timings.vfp + cfg->timings.vbp;
video_cfg->v_fc_config.hdmi_dvi_mode = cfg->hdmi_dvi_mode;
video_cfg->v_fc_config.timings.interlace = cfg->timings.interlace;
}
/* DSS_HDMI_CORE_VIDEO_CONFIG */
static void hdmi_core_video_config(struct hdmi_core_data *core,
struct hdmi_core_vid_config *cfg)
{
void __iomem *base = core->base;
unsigned char r = 0;
bool vsync_pol, hsync_pol;
vsync_pol =
cfg->v_fc_config.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
hsync_pol =
cfg->v_fc_config.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
/* Set hsync, vsync and data-enable polarity */
r = hdmi_read_reg(base, HDMI_CORE_FC_INVIDCONF);
r = FLD_MOD(r, vsync_pol, 6, 6);
r = FLD_MOD(r, hsync_pol, 5, 5);
r = FLD_MOD(r, cfg->data_enable_pol, 4, 4);
r = FLD_MOD(r, cfg->vblank_osc, 1, 1);
r = FLD_MOD(r, cfg->v_fc_config.timings.interlace, 0, 0);
hdmi_write_reg(base, HDMI_CORE_FC_INVIDCONF, r);
/* set x resolution */
REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV1,
cfg->v_fc_config.timings.x_res >> 8, 4, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_INHACTIV0,
cfg->v_fc_config.timings.x_res & 0xFF, 7, 0);
/* set y resolution */
REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV1,
cfg->v_fc_config.timings.y_res >> 8, 4, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_INVACTIV0,
cfg->v_fc_config.timings.y_res & 0xFF, 7, 0);
/* set horizontal blanking pixels */
REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK1, cfg->hblank >> 8, 4, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_INHBLANK0, cfg->hblank & 0xFF, 7, 0);
/* set vertial blanking pixels */
REG_FLD_MOD(base, HDMI_CORE_FC_INVBLANK, cfg->vblank, 7, 0);
/* set horizontal sync offset */
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY1,
cfg->v_fc_config.timings.hfp >> 8, 4, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINDELAY0,
cfg->v_fc_config.timings.hfp & 0xFF, 7, 0);
/* set vertical sync offset */
REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINDELAY,
cfg->v_fc_config.timings.vfp, 7, 0);
/* set horizontal sync pulse width */
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH1,
(cfg->v_fc_config.timings.hsw >> 8), 1, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_HSYNCINWIDTH0,
cfg->v_fc_config.timings.hsw & 0xFF, 7, 0);
/* set vertical sync pulse width */
REG_FLD_MOD(base, HDMI_CORE_FC_VSYNCINWIDTH,
cfg->v_fc_config.timings.vsw, 5, 0);
/* select DVI mode */
REG_FLD_MOD(base, HDMI_CORE_FC_INVIDCONF,
cfg->v_fc_config.hdmi_dvi_mode, 3, 3);
}
static void hdmi_core_config_video_packetizer(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
int clr_depth = 0; /* 24 bit color depth */
/* COLOR_DEPTH */
REG_FLD_MOD(base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
/* BYPASS_EN */
REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
/* PP_EN */
REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
/* YCC422_EN */
REG_FLD_MOD(base, HDMI_CORE_VP_CONF, 0, 3, 3);
/* PP_STUFFING */
REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
/* YCC422_STUFFING */
REG_FLD_MOD(base, HDMI_CORE_VP_STUFF, 1, 2, 2);
/* OUTPUT_SELECTOR */
REG_FLD_MOD(base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
}
static void hdmi_core_config_csc(struct hdmi_core_data *core)
{
int clr_depth = 0; /* 24 bit color depth */
/* CSC_COLORDEPTH */
REG_FLD_MOD(core->base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
}
static void hdmi_core_config_video_sampler(struct hdmi_core_data *core)
{
int video_mapping = 1; /* for 24 bit color depth */
/* VIDEO_MAPPING */
REG_FLD_MOD(core->base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
}
static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
struct hdmi_avi_infoframe *frame)
{
void __iomem *base = core->base;
u8 data[HDMI_INFOFRAME_SIZE(AVI)];
u8 *ptr;
unsigned y, a, b, s;
unsigned c, m, r;
unsigned itc, ec, q, sc;
unsigned vic;
unsigned yq, cn, pr;
hdmi_avi_infoframe_pack(frame, data, sizeof(data));
print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
HDMI_INFOFRAME_SIZE(AVI), false);
ptr = data + HDMI_INFOFRAME_HEADER_SIZE;
y = (ptr[0] >> 5) & 0x3;
a = (ptr[0] >> 4) & 0x1;
b = (ptr[0] >> 2) & 0x3;
s = (ptr[0] >> 0) & 0x3;
c = (ptr[1] >> 6) & 0x3;
m = (ptr[1] >> 4) & 0x3;
r = (ptr[1] >> 0) & 0xf;
itc = (ptr[2] >> 7) & 0x1;
ec = (ptr[2] >> 4) & 0x7;
q = (ptr[2] >> 2) & 0x3;
sc = (ptr[2] >> 0) & 0x3;
vic = ptr[3];
yq = (ptr[4] >> 6) & 0x3;
cn = (ptr[4] >> 4) & 0x3;
pr = (ptr[4] >> 0) & 0xf;
hdmi_write_reg(base, HDMI_CORE_FC_AVICONF0,
(a << 6) | (s << 4) | (b << 2) | (y << 0));
hdmi_write_reg(base, HDMI_CORE_FC_AVICONF1,
(c << 6) | (m << 4) | (r << 0));
hdmi_write_reg(base, HDMI_CORE_FC_AVICONF2,
(itc << 7) | (ec << 4) | (q << 2) | (sc << 0));
hdmi_write_reg(base, HDMI_CORE_FC_AVIVID, vic);
hdmi_write_reg(base, HDMI_CORE_FC_AVICONF3,
(yq << 2) | (cn << 0));
REG_FLD_MOD(base, HDMI_CORE_FC_PRCONF, pr, 3, 0);
}
static void hdmi_core_csc_config(struct hdmi_core_data *core,
struct csc_table csc_coeff)
{
void __iomem *base = core->base;
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_MSB, csc_coeff.a1 >> 8 , 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A1_LSB, csc_coeff.a1, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_MSB, csc_coeff.a2 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A2_LSB, csc_coeff.a2, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_MSB, csc_coeff.a3 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A3_LSB, csc_coeff.a3, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_MSB, csc_coeff.a4 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_A4_LSB, csc_coeff.a4, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_MSB, csc_coeff.b1 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B1_LSB, csc_coeff.b1, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_MSB, csc_coeff.b2 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B2_LSB, csc_coeff.b2, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_MSB, csc_coeff.b3 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B3_LSB, csc_coeff.b3, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_MSB, csc_coeff.b4 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_B4_LSB, csc_coeff.b4, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_MSB, csc_coeff.c1 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C1_LSB, csc_coeff.c1, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_MSB, csc_coeff.c2 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C2_LSB, csc_coeff.c2, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_MSB, csc_coeff.c3 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C3_LSB, csc_coeff.c3, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_MSB, csc_coeff.c4 >> 8, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_CSC_COEF_C4_LSB, csc_coeff.c4, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_MC_FLOWCTRL, 0x1, 0, 0);
}
static void hdmi_core_configure_range(struct hdmi_core_data *core)
{
struct csc_table csc_coeff = { 0 };
/* support limited range with 24 bit color depth for now */
csc_coeff = csc_table_deepcolor[0];
hdmi_core_csc_config(core, csc_coeff);
}
static void hdmi_core_enable_video_path(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
DSSDBG("hdmi_core_enable_video_path\n");
REG_FLD_MOD(base, HDMI_CORE_FC_CTRLDUR, 0x0C, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLDUR, 0x20, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_EXCTRLSPAC, 0x01, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_CH0PREAM, 0x0B, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_CH1PREAM, 0x16, 5, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_CH2PREAM, 0x21, 5, 0);
REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 0, 0);
REG_FLD_MOD(base, HDMI_CORE_MC_CLKDIS, 0x00, 1, 1);
}
static void hdmi_core_mask_interrupts(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
/* Master IRQ mask */
REG_FLD_MOD(base, HDMI_CORE_IH_MUTE, 0x3, 1, 0);
/* Mask all the interrupts in HDMI core */
REG_FLD_MOD(base, HDMI_CORE_VP_MASK, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_MASK0, 0xe7, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_MASK1, 0xfb, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_MASK2, 0x3, 1, 0);
REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 0x3, 3, 2);
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 0x3, 1, 0);
REG_FLD_MOD(base, HDMI_CORE_CEC_MASK, 0x7f, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
REG_FLD_MOD(base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
REG_FLD_MOD(base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
REG_FLD_MOD(base, HDMI_CORE_PHY_MASK0, 0xf3, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
/* Clear all the current interrupt bits */
REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xe7, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xfb, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0x3, 1, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0x7, 2, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0x7f, 6, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0x3, 1, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
}
static void hdmi_core_enable_interrupts(struct hdmi_core_data *core)
{
/* Unmute interrupts */
REG_FLD_MOD(core->base, HDMI_CORE_IH_MUTE, 0x0, 1, 0);
}
int hdmi5_core_handle_irqs(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT0, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT1, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_FC_STAT2, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_AS_STAT0, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_PHY_STAT0, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_I2CM_STAT0, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_CEC_STAT0, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_VP_STAT0, 0xff, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_IH_I2CMPHY_STAT0, 0xff, 7, 0);
return 0;
}
void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
struct hdmi_config *cfg)
{
struct omap_video_timings video_timing;
struct hdmi_video_format video_format;
struct hdmi_core_vid_config v_core_cfg;
hdmi_core_mask_interrupts(core);
hdmi_core_init(&v_core_cfg, cfg);
hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
hdmi_wp_video_config_timing(wp, &video_timing);
/* video config */
video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
hdmi_wp_video_config_format(wp, &video_format);
hdmi_wp_video_config_interface(wp, &video_timing);
/* support limited range with 24 bit color depth for now */
hdmi_core_configure_range(core);
cfg->infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED;
/*
* configure core video part, set software reset in the core
*/
v_core_cfg.packet_mode = HDMI_PACKETMODE24BITPERPIXEL;
hdmi_core_video_config(core, &v_core_cfg);
hdmi_core_config_video_packetizer(core);
hdmi_core_config_csc(core);
hdmi_core_config_video_sampler(core);
if (cfg->hdmi_dvi_mode == HDMI_HDMI)
hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
hdmi_core_enable_video_path(core);
hdmi_core_enable_interrupts(core);
}
static void hdmi5_core_audio_config(struct hdmi_core_data *core,
struct hdmi_core_audio_config *cfg)
{
void __iomem *base = core->base;
u8 val;
/* Mute audio before configuring */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0xf, 7, 4);
/* Set the N parameter */
REG_FLD_MOD(base, HDMI_CORE_AUD_N1, cfg->n, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_AUD_N2, cfg->n >> 8, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_AUD_N3, cfg->n >> 16, 3, 0);
/*
* CTS manual mode. Automatic mode is not supported when using audio
* parallel interface.
*/
REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, 1, 4, 4);
REG_FLD_MOD(base, HDMI_CORE_AUD_CTS1, cfg->cts, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_AUD_CTS2, cfg->cts >> 8, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_AUD_CTS3, cfg->cts >> 16, 3, 0);
/* Layout of Audio Sample Packets: 2-channel or multichannels */
if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 0, 0);
else
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 1, 0, 0);
/* Configure IEC-609580 Validity bits */
/* Channel 0 is valid */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 0, 0);
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, 0, 4, 4);
if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH)
val = 1;
else
val = 0;
/* Channels 1, 2 setting */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 1, 1);
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 5, 5);
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 2, 2);
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 6, 6);
/* Channel 3 setting */
if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH)
val = 1;
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 3, 3);
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSV, val, 7, 7);
/* Configure IEC-60958 User bits */
/* TODO: should be set by user. */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSU, 0, 7, 0);
/* Configure IEC-60958 Channel Status word */
/* CGMSA */
val = cfg->iec60958_cfg->status[5] & IEC958_AES5_CON_CGMSA;
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 5, 4);
/* Copyright */
val = (cfg->iec60958_cfg->status[0] &
IEC958_AES0_CON_NOT_COPYRIGHT) >> 2;
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(0), val, 0, 0);
/* Category */
hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(1),
cfg->iec60958_cfg->status[1]);
/* PCM audio mode */
val = (cfg->iec60958_cfg->status[0] & IEC958_AES0_CON_MODE) >> 6;
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 6, 4);
/* Source number */
val = cfg->iec60958_cfg->status[2] & IEC958_AES2_CON_SOURCE;
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(2), val, 3, 0);
/* Channel number right 0 */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 2, 3, 0);
/* Channel number right 1*/
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(3), 4, 7, 4);
/* Channel number right 2 */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 6, 3, 0);
/* Channel number right 3*/
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(4), 8, 7, 4);
/* Channel number left 0 */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 1, 3, 0);
/* Channel number left 1*/
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(5), 3, 7, 4);
/* Channel number left 2 */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 5, 3, 0);
/* Channel number left 3*/
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCHNLS(6), 7, 7, 4);
/* Clock accuracy and sample rate */
hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(7),
cfg->iec60958_cfg->status[3]);
/* Original sample rate and word length */
hdmi_write_reg(base, HDMI_CORE_FC_AUDSCHNLS(8),
cfg->iec60958_cfg->status[4]);
/* Enable FIFO empty and full interrupts */
REG_FLD_MOD(base, HDMI_CORE_AUD_INT, 3, 3, 2);
/* Configure GPA */
/* select HBR/SPDIF interfaces */
if (cfg->layout == HDMI_AUDIO_LAYOUT_2CH) {
/* select HBR/SPDIF interfaces */
REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
/* enable two channels in GPA */
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 3, 7, 0);
} else if (cfg->layout == HDMI_AUDIO_LAYOUT_6CH) {
/* select HBR/SPDIF interfaces */
REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
/* enable six channels in GPA */
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0x3F, 7, 0);
} else {
/* select HBR/SPDIF interfaces */
REG_FLD_MOD(base, HDMI_CORE_AUD_CONF0, 0, 5, 5);
/* enable eight channels in GPA */
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF1, 0xFF, 7, 0);
}
/* disable HBR */
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 0, 0, 0);
/* enable PCUV */
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_CONF2, 1, 1, 1);
/* enable GPA FIFO full and empty mask */
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_MASK, 3, 1, 0);
/* set polarity of GPA FIFO empty interrupts */
REG_FLD_MOD(base, HDMI_CORE_AUD_GP_POL, 1, 0, 0);
/* unmute audio */
REG_FLD_MOD(base, HDMI_CORE_FC_AUDSCONF, 0, 7, 4);
}
static void hdmi5_core_audio_infoframe_cfg(struct hdmi_core_data *core,
struct snd_cea_861_aud_if *info_aud)
{
void __iomem *base = core->base;
/* channel count and coding type fields in AUDICONF0 are swapped */
hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF0,
(info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC) << 4 |
(info_aud->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CT) >> 4);
hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF1, info_aud->db2_sf_ss);
hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF2, info_aud->db4_ca);
hdmi_write_reg(base, HDMI_CORE_FC_AUDICONF3,
(info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_DM_INH) >> 3 |
(info_aud->db5_dminh_lsv & CEA861_AUDIO_INFOFRAME_DB5_LSV));
}
int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
struct omap_dss_audio *audio, u32 pclk)
{
struct hdmi_audio_format audio_format;
struct hdmi_audio_dma audio_dma;
struct hdmi_core_audio_config core_cfg;
int n, cts, channel_count;
unsigned int fs_nr;
bool word_length_16b = false;
if (!audio || !audio->iec || !audio->cea || !core)
return -EINVAL;
core_cfg.iec60958_cfg = audio->iec;
if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) &&
(audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16))
word_length_16b = true;
/* only 16-bit word length supported atm */
if (!word_length_16b)
return -EINVAL;
switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
case IEC958_AES3_CON_FS_32000:
fs_nr = 32000;
break;
case IEC958_AES3_CON_FS_44100:
fs_nr = 44100;
break;
case IEC958_AES3_CON_FS_48000:
fs_nr = 48000;
break;
case IEC958_AES3_CON_FS_88200:
fs_nr = 88200;
break;
case IEC958_AES3_CON_FS_96000:
fs_nr = 96000;
break;
case IEC958_AES3_CON_FS_176400:
fs_nr = 176400;
break;
case IEC958_AES3_CON_FS_192000:
fs_nr = 192000;
break;
default:
return -EINVAL;
}
hdmi_compute_acr(pclk, fs_nr, &n, &cts);
core_cfg.n = n;
core_cfg.cts = cts;
/* Audio channels settings */
channel_count = (audio->cea->db1_ct_cc & CEA861_AUDIO_INFOFRAME_DB1CC)
+ 1;
if (channel_count == 2)
core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
else if (channel_count == 6)
core_cfg.layout = HDMI_AUDIO_LAYOUT_6CH;
else
core_cfg.layout = HDMI_AUDIO_LAYOUT_8CH;
/* DMA settings */
if (word_length_16b)
audio_dma.transfer_size = 0x10;
else
audio_dma.transfer_size = 0x20;
audio_dma.block_size = 0xC0;
audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
audio_dma.fifo_threshold = 0x20; /* in number of samples */
/* audio FIFO format settings for 16-bit samples*/
audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
/* only LPCM atm */
audio_format.type = HDMI_AUDIO_TYPE_LPCM;
/* only allowed option */
audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
/* disable start/stop signals of IEC 60958 blocks */
audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
/* configure DMA and audio FIFO format*/
hdmi_wp_audio_config_dma(wp, &audio_dma);
hdmi_wp_audio_config_format(wp, &audio_format);
/* configure the core */
hdmi5_core_audio_config(core, &core_cfg);
/* configure CEA 861 audio infoframe */
hdmi5_core_audio_infoframe_cfg(core, audio->cea);
return 0;
}
int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
{
core->base = devm_platform_ioremap_resource_byname(pdev, "core");
if (IS_ERR(core->base)) {
DSSERR("can't ioremap HDMI core\n");
return PTR_ERR(core->base);
}
return 0;
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HDMI driver for OMAP5
*
* Copyright (C) 2014 Texas Instruments Incorporated
*
* Authors:
* Yong Zhi
* Mythri pk
* Archit Taneja <[email protected]>
* Tomi Valkeinen <[email protected]>
*/
#define DSS_SUBSYS_NAME "HDMI"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <linux/component.h>
#include <video/omapfb_dss.h>
#include <sound/omap-hdmi-audio.h>
#include "hdmi5_core.h"
#include "dss.h"
#include "dss_features.h"
static struct omap_hdmi hdmi;
static int hdmi_runtime_get(void)
{
int r;
DSSDBG("hdmi_runtime_get\n");
r = pm_runtime_resume_and_get(&hdmi.pdev->dev);
if (WARN_ON(r < 0))
return r;
return 0;
}
static void hdmi_runtime_put(void)
{
int r;
DSSDBG("hdmi_runtime_put\n");
r = pm_runtime_put_sync(&hdmi.pdev->dev);
WARN_ON(r < 0 && r != -ENOSYS);
}
static irqreturn_t hdmi_irq_handler(int irq, void *data)
{
struct hdmi_wp_data *wp = data;
u32 irqstatus;
irqstatus = hdmi_wp_get_irqstatus(wp);
hdmi_wp_set_irqstatus(wp, irqstatus);
if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
u32 v;
/*
* If we get both connect and disconnect interrupts at the same
* time, turn off the PHY, clear interrupts, and restart, which
* raises connect interrupt if a cable is connected, or nothing
* if cable is not connected.
*/
hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
/*
* We always get bogus CONNECT & DISCONNECT interrupts when
* setting the PHY to LDOON. To ignore those, we force the RXDET
* line to 0 until the PHY power state has been changed.
*/
v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
HDMI_IRQ_LINK_DISCONNECT);
hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
} else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
}
return IRQ_HANDLED;
}
static int hdmi_init_regulator(void)
{
struct regulator *reg;
if (hdmi.vdda_reg != NULL)
return 0;
reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
if (IS_ERR(reg)) {
DSSERR("can't get VDDA regulator\n");
return PTR_ERR(reg);
}
hdmi.vdda_reg = reg;
return 0;
}
static int hdmi_power_on_core(struct omap_dss_device *dssdev)
{
int r;
r = regulator_enable(hdmi.vdda_reg);
if (r)
return r;
r = hdmi_runtime_get();
if (r)
goto err_runtime_get;
/* Make selection of HDMI in DSS */
dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
hdmi.core_enabled = true;
return 0;
err_runtime_get:
regulator_disable(hdmi.vdda_reg);
return r;
}
static void hdmi_power_off_core(struct omap_dss_device *dssdev)
{
hdmi.core_enabled = false;
hdmi_runtime_put();
regulator_disable(hdmi.vdda_reg);
}
static int hdmi_power_on_full(struct omap_dss_device *dssdev)
{
int r;
struct omap_video_timings *p;
struct omap_overlay_manager *mgr = hdmi.output.manager;
struct dss_pll_clock_info hdmi_cinfo = { 0 };
r = hdmi_power_on_core(dssdev);
if (r)
return r;
p = &hdmi.cfg.timings;
DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);
/* disable and clear irqs */
hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
hdmi_wp_set_irqstatus(&hdmi.wp,
hdmi_wp_get_irqstatus(&hdmi.wp));
r = dss_pll_enable(&hdmi.pll.pll);
if (r) {
DSSERR("Failed to enable PLL\n");
goto err_pll_enable;
}
r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
if (r) {
DSSERR("Failed to configure PLL\n");
goto err_pll_cfg;
}
r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
hdmi_cinfo.clkout[0]);
if (r) {
DSSDBG("Failed to start PHY\n");
goto err_phy_cfg;
}
r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
if (r)
goto err_phy_pwr;
hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
/* bypass TV gamma table */
dispc_enable_gamma_table(0);
/* tv size */
dss_mgr_set_timings(mgr, p);
r = hdmi_wp_video_start(&hdmi.wp);
if (r)
goto err_vid_enable;
r = dss_mgr_enable(mgr);
if (r)
goto err_mgr_enable;
hdmi_wp_set_irqenable(&hdmi.wp,
HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
return 0;
err_mgr_enable:
hdmi_wp_video_stop(&hdmi.wp);
err_vid_enable:
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
err_phy_pwr:
err_phy_cfg:
err_pll_cfg:
dss_pll_disable(&hdmi.pll.pll);
err_pll_enable:
hdmi_power_off_core(dssdev);
return -EIO;
}
static void hdmi_power_off_full(struct omap_dss_device *dssdev)
{
struct omap_overlay_manager *mgr = hdmi.output.manager;
hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
dss_mgr_disable(mgr);
hdmi_wp_video_stop(&hdmi.wp);
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
dss_pll_disable(&hdmi.pll.pll);
hdmi_power_off_core(dssdev);
}
static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct omap_dss_device *out = &hdmi.output;
/* TODO: proper interlace support */
if (timings->interlace)
return -EINVAL;
if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
return -EINVAL;
return 0;
}
static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
mutex_lock(&hdmi.lock);
hdmi.cfg.timings = *timings;
dispc_set_tv_pclk(timings->pixelclock);
mutex_unlock(&hdmi.lock);
}
static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
*timings = hdmi.cfg.timings;
}
static void hdmi_dump_regs(struct seq_file *s)
{
mutex_lock(&hdmi.lock);
if (hdmi_runtime_get()) {
mutex_unlock(&hdmi.lock);
return;
}
hdmi_wp_dump(&hdmi.wp, s);
hdmi_pll_dump(&hdmi.pll, s);
hdmi_phy_dump(&hdmi.phy, s);
hdmi5_core_dump(&hdmi.core, s);
hdmi_runtime_put();
mutex_unlock(&hdmi.lock);
}
static int read_edid(u8 *buf, int len)
{
int r;
int idlemode;
mutex_lock(&hdmi.lock);
r = hdmi_runtime_get();
BUG_ON(r);
idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
/* No-idle mode */
REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
r = hdmi5_read_edid(&hdmi.core, buf, len);
REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
hdmi_runtime_put();
mutex_unlock(&hdmi.lock);
return r;
}
static void hdmi_start_audio_stream(struct omap_hdmi *hd)
{
REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
hdmi_wp_audio_enable(&hd->wp, true);
hdmi_wp_audio_core_req_enable(&hd->wp, true);
}
static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
{
hdmi_wp_audio_core_req_enable(&hd->wp, false);
hdmi_wp_audio_enable(&hd->wp, false);
REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
}
static int hdmi_display_enable(struct omap_dss_device *dssdev)
{
struct omap_dss_device *out = &hdmi.output;
unsigned long flags;
int r = 0;
DSSDBG("ENTER hdmi_display_enable\n");
mutex_lock(&hdmi.lock);
if (out->manager == NULL) {
DSSERR("failed to enable display: no output/manager\n");
r = -ENODEV;
goto err0;
}
r = hdmi_power_on_full(dssdev);
if (r) {
DSSERR("failed to power on device\n");
goto err0;
}
if (hdmi.audio_configured) {
r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
hdmi.cfg.timings.pixelclock);
if (r) {
DSSERR("Error restoring audio configuration: %d", r);
hdmi.audio_abort_cb(&hdmi.pdev->dev);
hdmi.audio_configured = false;
}
}
spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
if (hdmi.audio_configured && hdmi.audio_playing)
hdmi_start_audio_stream(&hdmi);
hdmi.display_enabled = true;
spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
mutex_unlock(&hdmi.lock);
return 0;
err0:
mutex_unlock(&hdmi.lock);
return r;
}
static void hdmi_display_disable(struct omap_dss_device *dssdev)
{
unsigned long flags;
DSSDBG("Enter hdmi_display_disable\n");
mutex_lock(&hdmi.lock);
spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
hdmi_stop_audio_stream(&hdmi);
hdmi.display_enabled = false;
spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
hdmi_power_off_full(dssdev);
mutex_unlock(&hdmi.lock);
}
static int hdmi_core_enable(struct omap_dss_device *dssdev)
{
int r = 0;
DSSDBG("ENTER omapdss_hdmi_core_enable\n");
mutex_lock(&hdmi.lock);
r = hdmi_power_on_core(dssdev);
if (r) {
DSSERR("failed to power on device\n");
goto err0;
}
mutex_unlock(&hdmi.lock);
return 0;
err0:
mutex_unlock(&hdmi.lock);
return r;
}
static void hdmi_core_disable(struct omap_dss_device *dssdev)
{
DSSDBG("Enter omapdss_hdmi_core_disable\n");
mutex_lock(&hdmi.lock);
hdmi_power_off_core(dssdev);
mutex_unlock(&hdmi.lock);
}
static int hdmi_connect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct omap_overlay_manager *mgr;
int r;
r = hdmi_init_regulator();
if (r)
return r;
mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
if (!mgr)
return -ENODEV;
r = dss_mgr_connect(mgr, dssdev);
if (r)
return r;
r = omapdss_output_set_device(dssdev, dst);
if (r) {
DSSERR("failed to connect output to new device: %s\n",
dst->name);
dss_mgr_disconnect(mgr, dssdev);
return r;
}
return 0;
}
static void hdmi_disconnect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
WARN_ON(dst != dssdev->dst);
if (dst != dssdev->dst)
return;
omapdss_output_unset_device(dssdev);
if (dssdev->manager)
dss_mgr_disconnect(dssdev->manager, dssdev);
}
static int hdmi_read_edid(struct omap_dss_device *dssdev,
u8 *edid, int len)
{
bool need_enable;
int r;
need_enable = hdmi.core_enabled == false;
if (need_enable) {
r = hdmi_core_enable(dssdev);
if (r)
return r;
}
r = read_edid(edid, len);
if (need_enable)
hdmi_core_disable(dssdev);
return r;
}
static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
const struct hdmi_avi_infoframe *avi)
{
hdmi.cfg.infoframe = *avi;
return 0;
}
static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
bool hdmi_mode)
{
hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
return 0;
}
static const struct omapdss_hdmi_ops hdmi_ops = {
.connect = hdmi_connect,
.disconnect = hdmi_disconnect,
.enable = hdmi_display_enable,
.disable = hdmi_display_disable,
.check_timings = hdmi_display_check_timing,
.set_timings = hdmi_display_set_timing,
.get_timings = hdmi_display_get_timings,
.read_edid = hdmi_read_edid,
.set_infoframe = hdmi_set_infoframe,
.set_hdmi_mode = hdmi_set_hdmi_mode,
};
static void hdmi_init_output(struct platform_device *pdev)
{
struct omap_dss_device *out = &hdmi.output;
out->dev = &pdev->dev;
out->id = OMAP_DSS_OUTPUT_HDMI;
out->output_type = OMAP_DISPLAY_TYPE_HDMI;
out->name = "hdmi.0";
out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
out->ops.hdmi = &hdmi_ops;
out->owner = THIS_MODULE;
omapdss_register_output(out);
}
static void hdmi_uninit_output(struct platform_device *pdev)
{
struct omap_dss_device *out = &hdmi.output;
omapdss_unregister_output(out);
}
static int hdmi_probe_of(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct device_node *ep;
int r;
ep = omapdss_of_get_first_endpoint(node);
if (!ep)
return 0;
r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
if (r)
goto err;
of_node_put(ep);
return 0;
err:
of_node_put(ep);
return r;
}
/* Audio callbacks */
static int hdmi_audio_startup(struct device *dev,
void (*abort_cb)(struct device *dev))
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
int ret = 0;
mutex_lock(&hd->lock);
if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
ret = -EPERM;
goto out;
}
hd->audio_abort_cb = abort_cb;
out:
mutex_unlock(&hd->lock);
return ret;
}
static int hdmi_audio_shutdown(struct device *dev)
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
mutex_lock(&hd->lock);
hd->audio_abort_cb = NULL;
hd->audio_configured = false;
hd->audio_playing = false;
mutex_unlock(&hd->lock);
return 0;
}
static int hdmi_audio_start(struct device *dev)
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
unsigned long flags;
WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
spin_lock_irqsave(&hd->audio_playing_lock, flags);
if (hd->display_enabled)
hdmi_start_audio_stream(hd);
hd->audio_playing = true;
spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
return 0;
}
static void hdmi_audio_stop(struct device *dev)
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
unsigned long flags;
WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
spin_lock_irqsave(&hd->audio_playing_lock, flags);
if (hd->display_enabled)
hdmi_stop_audio_stream(hd);
hd->audio_playing = false;
spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
}
static int hdmi_audio_config(struct device *dev,
struct omap_dss_audio *dss_audio)
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
int ret;
mutex_lock(&hd->lock);
if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
ret = -EPERM;
goto out;
}
ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
hd->cfg.timings.pixelclock);
if (!ret) {
hd->audio_configured = true;
hd->audio_config = *dss_audio;
}
out:
mutex_unlock(&hd->lock);
return ret;
}
static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
.audio_startup = hdmi_audio_startup,
.audio_shutdown = hdmi_audio_shutdown,
.audio_start = hdmi_audio_start,
.audio_stop = hdmi_audio_stop,
.audio_config = hdmi_audio_config,
};
static int hdmi_audio_register(struct device *dev)
{
struct omap_hdmi_audio_pdata pdata = {
.dev = dev,
.version = 5,
.audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
.ops = &hdmi_audio_ops,
};
hdmi.audio_pdev = platform_device_register_data(
dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
&pdata, sizeof(pdata));
if (IS_ERR(hdmi.audio_pdev))
return PTR_ERR(hdmi.audio_pdev);
hdmi_runtime_get();
hdmi.wp_idlemode =
REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
hdmi_runtime_put();
return 0;
}
/* HDMI HW IP initialisation */
static int hdmi5_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
int r;
int irq;
hdmi.pdev = pdev;
platform_set_drvdata(pdev, &hdmi);
mutex_init(&hdmi.lock);
spin_lock_init(&hdmi.audio_playing_lock);
if (pdev->dev.of_node) {
r = hdmi_probe_of(pdev);
if (r)
return r;
}
r = hdmi_wp_init(pdev, &hdmi.wp);
if (r)
return r;
r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
if (r)
return r;
r = hdmi_phy_init(pdev, &hdmi.phy);
if (r)
goto err;
r = hdmi5_core_init(pdev, &hdmi.core);
if (r)
goto err;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
DSSERR("platform_get_irq failed\n");
r = -ENODEV;
goto err;
}
r = devm_request_threaded_irq(&pdev->dev, irq,
NULL, hdmi_irq_handler,
IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
if (r) {
DSSERR("HDMI IRQ request failed\n");
goto err;
}
pm_runtime_enable(&pdev->dev);
hdmi_init_output(pdev);
r = hdmi_audio_register(&pdev->dev);
if (r) {
DSSERR("Registering HDMI audio failed %d\n", r);
hdmi_uninit_output(pdev);
pm_runtime_disable(&pdev->dev);
return r;
}
dss_debugfs_create_file("hdmi", hdmi_dump_regs);
return 0;
err:
hdmi_pll_uninit(&hdmi.pll);
return r;
}
static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
if (hdmi.audio_pdev)
platform_device_unregister(hdmi.audio_pdev);
hdmi_uninit_output(pdev);
hdmi_pll_uninit(&hdmi.pll);
pm_runtime_disable(&pdev->dev);
}
static const struct component_ops hdmi5_component_ops = {
.bind = hdmi5_bind,
.unbind = hdmi5_unbind,
};
static int hdmi5_probe(struct platform_device *pdev)
{
return component_add(&pdev->dev, &hdmi5_component_ops);
}
static void hdmi5_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &hdmi5_component_ops);
}
static int hdmi_runtime_suspend(struct device *dev)
{
dispc_runtime_put();
return 0;
}
static int hdmi_runtime_resume(struct device *dev)
{
int r;
r = dispc_runtime_get();
if (r < 0)
return r;
return 0;
}
static const struct dev_pm_ops hdmi_pm_ops = {
.runtime_suspend = hdmi_runtime_suspend,
.runtime_resume = hdmi_runtime_resume,
};
static const struct of_device_id hdmi_of_match[] = {
{ .compatible = "ti,omap5-hdmi", },
{ .compatible = "ti,dra7-hdmi", },
{},
};
static struct platform_driver omapdss_hdmihw_driver = {
.probe = hdmi5_probe,
.remove_new = hdmi5_remove,
.driver = {
.name = "omapdss_hdmi5",
.pm = &hdmi_pm_ops,
.of_match_table = hdmi_of_match,
.suppress_bind_attrs = true,
},
};
int __init hdmi5_init_platform_driver(void)
{
return platform_driver_register(&omapdss_hdmihw_driver);
}
void hdmi5_uninit_platform_driver(void)
{
platform_driver_unregister(&omapdss_hdmihw_driver);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/hdmi5.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/display.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "DISPLAY"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
u16 *xres, u16 *yres)
{
*xres = dssdev->panel.timings.x_res;
*yres = dssdev->panel.timings.y_res;
}
EXPORT_SYMBOL(omapdss_default_get_resolution);
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev)
{
switch (dssdev->type) {
case OMAP_DISPLAY_TYPE_DPI:
if (dssdev->phy.dpi.data_lines == 24)
return 24;
else
return 16;
case OMAP_DISPLAY_TYPE_DBI:
if (dssdev->ctrl.pixel_size == 24)
return 24;
else
return 16;
case OMAP_DISPLAY_TYPE_DSI:
if (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) > 16)
return 24;
else
return 16;
case OMAP_DISPLAY_TYPE_VENC:
case OMAP_DISPLAY_TYPE_SDI:
case OMAP_DISPLAY_TYPE_HDMI:
case OMAP_DISPLAY_TYPE_DVI:
return 24;
default:
BUG();
return 0;
}
}
EXPORT_SYMBOL(omapdss_default_get_recommended_bpp);
void omapdss_default_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
*timings = dssdev->panel.timings;
}
EXPORT_SYMBOL(omapdss_default_get_timings);
int dss_suspend_all_devices(void)
{
struct omap_dss_device *dssdev = NULL;
for_each_dss_dev(dssdev) {
if (!dssdev->driver)
continue;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
dssdev->driver->disable(dssdev);
dssdev->activate_after_resume = true;
} else {
dssdev->activate_after_resume = false;
}
}
return 0;
}
int dss_resume_all_devices(void)
{
struct omap_dss_device *dssdev = NULL;
for_each_dss_dev(dssdev) {
if (!dssdev->driver)
continue;
if (dssdev->activate_after_resume) {
dssdev->driver->enable(dssdev);
dssdev->activate_after_resume = false;
}
}
return 0;
}
void dss_disable_all_devices(void)
{
struct omap_dss_device *dssdev = NULL;
for_each_dss_dev(dssdev) {
if (!dssdev->driver)
continue;
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
dssdev->driver->disable(dssdev);
}
}
static LIST_HEAD(panel_list);
static DEFINE_MUTEX(panel_list_mutex);
static int disp_num_counter;
int omapdss_register_display(struct omap_dss_device *dssdev)
{
struct omap_dss_driver *drv = dssdev->driver;
int id;
/*
* Note: this presumes all the displays are either using DT or non-DT,
* which normally should be the case. This also presumes that all
* displays either have an DT alias, or none has.
*/
if (dssdev->dev->of_node) {
id = of_alias_get_id(dssdev->dev->of_node, "display");
if (id < 0)
id = disp_num_counter++;
} else {
id = disp_num_counter++;
}
snprintf(dssdev->alias, sizeof(dssdev->alias), "display%d", id);
/* Use 'label' property for name, if it exists */
if (dssdev->dev->of_node)
of_property_read_string(dssdev->dev->of_node, "label",
&dssdev->name);
if (dssdev->name == NULL)
dssdev->name = dssdev->alias;
if (drv && drv->get_resolution == NULL)
drv->get_resolution = omapdss_default_get_resolution;
if (drv && drv->get_recommended_bpp == NULL)
drv->get_recommended_bpp = omapdss_default_get_recommended_bpp;
if (drv && drv->get_timings == NULL)
drv->get_timings = omapdss_default_get_timings;
mutex_lock(&panel_list_mutex);
list_add_tail(&dssdev->panel_list, &panel_list);
mutex_unlock(&panel_list_mutex);
return 0;
}
EXPORT_SYMBOL(omapdss_register_display);
void omapdss_unregister_display(struct omap_dss_device *dssdev)
{
mutex_lock(&panel_list_mutex);
list_del(&dssdev->panel_list);
mutex_unlock(&panel_list_mutex);
}
EXPORT_SYMBOL(omapdss_unregister_display);
struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev)
{
if (!try_module_get(dssdev->owner))
return NULL;
if (get_device(dssdev->dev) == NULL) {
module_put(dssdev->owner);
return NULL;
}
return dssdev;
}
EXPORT_SYMBOL(omap_dss_get_device);
void omap_dss_put_device(struct omap_dss_device *dssdev)
{
put_device(dssdev->dev);
module_put(dssdev->owner);
}
EXPORT_SYMBOL(omap_dss_put_device);
/*
* ref count of the found device is incremented.
* ref count of from-device is decremented.
*/
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from)
{
struct list_head *l;
struct omap_dss_device *dssdev;
mutex_lock(&panel_list_mutex);
if (list_empty(&panel_list)) {
dssdev = NULL;
goto out;
}
if (from == NULL) {
dssdev = list_first_entry(&panel_list, struct omap_dss_device,
panel_list);
omap_dss_get_device(dssdev);
goto out;
}
omap_dss_put_device(from);
list_for_each(l, &panel_list) {
dssdev = list_entry(l, struct omap_dss_device, panel_list);
if (dssdev == from) {
if (list_is_last(l, &panel_list)) {
dssdev = NULL;
goto out;
}
dssdev = list_entry(l->next, struct omap_dss_device,
panel_list);
omap_dss_get_device(dssdev);
goto out;
}
}
WARN(1, "'from' dssdev not found\n");
dssdev = NULL;
out:
mutex_unlock(&panel_list_mutex);
return dssdev;
}
EXPORT_SYMBOL(omap_dss_get_next_device);
struct omap_dss_device *omap_dss_find_device(void *data,
int (*match)(struct omap_dss_device *dssdev, void *data))
{
struct omap_dss_device *dssdev = NULL;
while ((dssdev = omap_dss_get_next_device(dssdev)) != NULL) {
if (match(dssdev, data))
return dssdev;
}
return NULL;
}
EXPORT_SYMBOL(omap_dss_find_device);
void videomode_to_omap_video_timings(const struct videomode *vm,
struct omap_video_timings *ovt)
{
memset(ovt, 0, sizeof(*ovt));
ovt->pixelclock = vm->pixelclock;
ovt->x_res = vm->hactive;
ovt->hbp = vm->hback_porch;
ovt->hfp = vm->hfront_porch;
ovt->hsw = vm->hsync_len;
ovt->y_res = vm->vactive;
ovt->vbp = vm->vback_porch;
ovt->vfp = vm->vfront_porch;
ovt->vsw = vm->vsync_len;
ovt->vsync_level = vm->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
ovt->hsync_level = vm->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
ovt->de_level = vm->flags & DISPLAY_FLAGS_DE_HIGH ?
OMAPDSS_SIG_ACTIVE_HIGH :
OMAPDSS_SIG_ACTIVE_LOW;
ovt->data_pclk_edge = vm->flags & DISPLAY_FLAGS_PIXDATA_POSEDGE ?
OMAPDSS_DRIVE_SIG_RISING_EDGE :
OMAPDSS_DRIVE_SIG_FALLING_EDGE;
ovt->sync_pclk_edge = ovt->data_pclk_edge;
}
EXPORT_SYMBOL(videomode_to_omap_video_timings);
void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
struct videomode *vm)
{
memset(vm, 0, sizeof(*vm));
vm->pixelclock = ovt->pixelclock;
vm->hactive = ovt->x_res;
vm->hback_porch = ovt->hbp;
vm->hfront_porch = ovt->hfp;
vm->hsync_len = ovt->hsw;
vm->vactive = ovt->y_res;
vm->vback_porch = ovt->vbp;
vm->vfront_porch = ovt->vfp;
vm->vsync_len = ovt->vsw;
if (ovt->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
vm->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
else
vm->flags |= DISPLAY_FLAGS_HSYNC_LOW;
if (ovt->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH)
vm->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
else
vm->flags |= DISPLAY_FLAGS_VSYNC_LOW;
if (ovt->de_level == OMAPDSS_SIG_ACTIVE_HIGH)
vm->flags |= DISPLAY_FLAGS_DE_HIGH;
else
vm->flags |= DISPLAY_FLAGS_DE_LOW;
if (ovt->data_pclk_edge == OMAPDSS_DRIVE_SIG_RISING_EDGE)
vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE;
else
vm->flags |= DISPLAY_FLAGS_PIXDATA_NEGEDGE;
}
EXPORT_SYMBOL(omap_video_timings_to_videomode);
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/display.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HDMI PLL
*
* Copyright (C) 2013 Texas Instruments Incorporated
*/
#define DSS_SUBSYS_NAME "HDMIPLL"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/seq_file.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "hdmi.h"
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
{
#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
hdmi_read_reg(pll->base, r))
DUMPPLL(PLLCTRL_PLL_CONTROL);
DUMPPLL(PLLCTRL_PLL_STATUS);
DUMPPLL(PLLCTRL_PLL_GO);
DUMPPLL(PLLCTRL_CFG1);
DUMPPLL(PLLCTRL_CFG2);
DUMPPLL(PLLCTRL_CFG3);
DUMPPLL(PLLCTRL_SSC_CFG1);
DUMPPLL(PLLCTRL_SSC_CFG2);
DUMPPLL(PLLCTRL_CFG4);
}
void hdmi_pll_compute(struct hdmi_pll_data *pll,
unsigned long target_tmds, struct dss_pll_clock_info *pi)
{
unsigned long fint, clkdco, clkout;
unsigned long target_bitclk, target_clkdco;
unsigned long min_dco;
unsigned n, m, mf, m2, sd;
unsigned long clkin;
const struct dss_pll_hw *hw = pll->pll.hw;
clkin = clk_get_rate(pll->pll.clkin);
DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
target_bitclk = target_tmds * 10;
/* Fint */
n = DIV_ROUND_UP(clkin, hw->fint_max);
fint = clkin / n;
/* adjust m2 so that the clkdco will be high enough */
min_dco = roundup(hw->clkdco_min, fint);
m2 = DIV_ROUND_UP(min_dco, target_bitclk);
if (m2 == 0)
m2 = 1;
target_clkdco = target_bitclk * m2;
m = target_clkdco / fint;
clkdco = fint * m;
/* adjust clkdco with fractional mf */
if (WARN_ON(target_clkdco - clkdco > fint))
mf = 0;
else
mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
if (mf > 0)
clkdco += (u32)div_u64((u64)mf * fint, 262144);
clkout = clkdco / m2;
/* sigma-delta */
sd = DIV_ROUND_UP(fint * m, 250000000);
DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
n, m, mf, m2, sd);
DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
pi->n = n;
pi->m = m;
pi->mf = mf;
pi->mX[0] = m2;
pi->sd = sd;
pi->fint = fint;
pi->clkdco = clkdco;
pi->clkout[0] = clkout;
}
static int hdmi_pll_enable(struct dss_pll *dsspll)
{
struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
struct hdmi_wp_data *wp = pll->wp;
dss_ctrl_pll_enable(DSS_PLL_HDMI, true);
return hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
}
static void hdmi_pll_disable(struct dss_pll *dsspll)
{
struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
struct hdmi_wp_data *wp = pll->wp;
hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
dss_ctrl_pll_enable(DSS_PLL_HDMI, false);
}
static const struct dss_pll_ops dsi_pll_ops = {
.enable = hdmi_pll_enable,
.disable = hdmi_pll_disable,
.set_config = dss_pll_write_config_type_b,
};
static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
.n_max = 255,
.m_min = 20,
.m_max = 4095,
.mX_max = 127,
.fint_min = 500000,
.fint_max = 2500000,
.clkdco_min = 500000000,
.clkdco_low = 1000000000,
.clkdco_max = 2000000000,
.n_msb = 8,
.n_lsb = 1,
.m_msb = 20,
.m_lsb = 9,
.mX_msb[0] = 24,
.mX_lsb[0] = 18,
.has_selfreqdco = true,
};
static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
.n_max = 255,
.m_min = 20,
.m_max = 2045,
.mX_max = 127,
.fint_min = 620000,
.fint_max = 2500000,
.clkdco_min = 750000000,
.clkdco_low = 1500000000,
.clkdco_max = 2500000000UL,
.n_msb = 8,
.n_lsb = 1,
.m_msb = 20,
.m_lsb = 9,
.mX_msb[0] = 24,
.mX_lsb[0] = 18,
.has_selfreqdco = true,
.has_refsel = true,
};
static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll)
{
struct dss_pll *pll = &hpll->pll;
struct clk *clk;
clk = devm_clk_get(&pdev->dev, "sys_clk");
if (IS_ERR(clk)) {
DSSERR("can't get sys_clk\n");
return PTR_ERR(clk);
}
pll->name = "hdmi";
pll->id = DSS_PLL_HDMI;
pll->base = hpll->base;
pll->clkin = clk;
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
pll->hw = &dss_omap4_hdmi_pll_hw;
break;
case OMAPDSS_VER_OMAP5:
case OMAPDSS_VER_DRA7xx:
pll->hw = &dss_omap5_hdmi_pll_hw;
break;
default:
return -ENODEV;
}
pll->ops = &dsi_pll_ops;
return dss_pll_register(pll);
}
int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
struct hdmi_wp_data *wp)
{
int r;
pll->wp = wp;
pll->base = devm_platform_ioremap_resource_byname(pdev, "pll");
if (IS_ERR(pll->base)) {
DSSERR("can't ioremap PLLCTRL\n");
return PTR_ERR(pll->base);
}
r = dsi_init_pll_data(pdev, pll);
if (r) {
DSSERR("failed to init HDMI PLL\n");
return r;
}
return 0;
}
void hdmi_pll_uninit(struct hdmi_pll_data *hpll)
{
struct dss_pll *pll = &hpll->pll;
dss_pll_unregister(pll);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/hdmi_pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "OVERLAY"
#include <linux/module.h>
#include <linux/err.h>
#include <linux/sysfs.h>
#include <linux/kobject.h>
#include <linux/kstrtox.h>
#include <linux/platform_device.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
static ssize_t overlay_name_show(struct omap_overlay *ovl, char *buf)
{
return sysfs_emit(buf, "%s\n", ovl->name);
}
static ssize_t overlay_manager_show(struct omap_overlay *ovl, char *buf)
{
return sysfs_emit(buf, "%s\n",
ovl->manager ? ovl->manager->name : "<none>");
}
static ssize_t overlay_manager_store(struct omap_overlay *ovl, const char *buf,
size_t size)
{
int i, r;
struct omap_overlay_manager *mgr = NULL;
struct omap_overlay_manager *old_mgr;
int len = size;
if (buf[size-1] == '\n')
--len;
if (len > 0) {
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
mgr = omap_dss_get_overlay_manager(i);
if (sysfs_streq(buf, mgr->name))
break;
mgr = NULL;
}
}
if (len > 0 && mgr == NULL)
return -EINVAL;
if (mgr)
DSSDBG("manager %s found\n", mgr->name);
if (mgr == ovl->manager)
return size;
old_mgr = ovl->manager;
r = dispc_runtime_get();
if (r)
return r;
/* detach old manager */
if (old_mgr) {
r = ovl->unset_manager(ovl);
if (r) {
DSSERR("detach failed\n");
goto err;
}
r = old_mgr->apply(old_mgr);
if (r)
goto err;
}
if (mgr) {
r = ovl->set_manager(ovl, mgr);
if (r) {
DSSERR("Failed to attach overlay\n");
goto err;
}
r = mgr->apply(mgr);
if (r)
goto err;
}
dispc_runtime_put();
return size;
err:
dispc_runtime_put();
return r;
}
static ssize_t overlay_input_size_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return sysfs_emit(buf, "%d,%d\n",
info.width, info.height);
}
static ssize_t overlay_screen_width_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return sysfs_emit(buf, "%d\n", info.screen_width);
}
static ssize_t overlay_position_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return sysfs_emit(buf, "%d,%d\n",
info.pos_x, info.pos_y);
}
static ssize_t overlay_position_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
char *last;
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
info.pos_x = simple_strtoul(buf, &last, 10);
++last;
if (last - buf >= size)
return -EINVAL;
info.pos_y = simple_strtoul(last, &last, 10);
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
static ssize_t overlay_output_size_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return sysfs_emit(buf, "%d,%d\n",
info.out_width, info.out_height);
}
static ssize_t overlay_output_size_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
char *last;
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
info.out_width = simple_strtoul(buf, &last, 10);
++last;
if (last - buf >= size)
return -EINVAL;
info.out_height = simple_strtoul(last, &last, 10);
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
static ssize_t overlay_enabled_show(struct omap_overlay *ovl, char *buf)
{
return sysfs_emit(buf, "%d\n", ovl->is_enabled(ovl));
}
static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf,
size_t size)
{
int r;
bool enable;
r = kstrtobool(buf, &enable);
if (r)
return r;
if (enable)
r = ovl->enable(ovl);
else
r = ovl->disable(ovl);
if (r)
return r;
return size;
}
static ssize_t overlay_global_alpha_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return sysfs_emit(buf, "%d\n",
info.global_alpha);
}
static ssize_t overlay_global_alpha_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
u8 alpha;
struct omap_overlay_info info;
if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
return -ENODEV;
r = kstrtou8(buf, 0, &alpha);
if (r)
return r;
ovl->get_overlay_info(ovl, &info);
info.global_alpha = alpha;
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
static ssize_t overlay_pre_mult_alpha_show(struct omap_overlay *ovl,
char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return sysfs_emit(buf, "%d\n",
info.pre_mult_alpha);
}
static ssize_t overlay_pre_mult_alpha_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
u8 alpha;
struct omap_overlay_info info;
if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
return -ENODEV;
r = kstrtou8(buf, 0, &alpha);
if (r)
return r;
ovl->get_overlay_info(ovl, &info);
info.pre_mult_alpha = alpha;
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
static ssize_t overlay_zorder_show(struct omap_overlay *ovl, char *buf)
{
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
return sysfs_emit(buf, "%d\n", info.zorder);
}
static ssize_t overlay_zorder_store(struct omap_overlay *ovl,
const char *buf, size_t size)
{
int r;
u8 zorder;
struct omap_overlay_info info;
if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
return -ENODEV;
r = kstrtou8(buf, 0, &zorder);
if (r)
return r;
ovl->get_overlay_info(ovl, &info);
info.zorder = zorder;
r = ovl->set_overlay_info(ovl, &info);
if (r)
return r;
if (ovl->manager) {
r = ovl->manager->apply(ovl->manager);
if (r)
return r;
}
return size;
}
struct overlay_attribute {
struct attribute attr;
ssize_t (*show)(struct omap_overlay *, char *);
ssize_t (*store)(struct omap_overlay *, const char *, size_t);
};
#define OVERLAY_ATTR(_name, _mode, _show, _store) \
struct overlay_attribute overlay_attr_##_name = \
__ATTR(_name, _mode, _show, _store)
static OVERLAY_ATTR(name, S_IRUGO, overlay_name_show, NULL);
static OVERLAY_ATTR(manager, S_IRUGO|S_IWUSR,
overlay_manager_show, overlay_manager_store);
static OVERLAY_ATTR(input_size, S_IRUGO, overlay_input_size_show, NULL);
static OVERLAY_ATTR(screen_width, S_IRUGO, overlay_screen_width_show, NULL);
static OVERLAY_ATTR(position, S_IRUGO|S_IWUSR,
overlay_position_show, overlay_position_store);
static OVERLAY_ATTR(output_size, S_IRUGO|S_IWUSR,
overlay_output_size_show, overlay_output_size_store);
static OVERLAY_ATTR(enabled, S_IRUGO|S_IWUSR,
overlay_enabled_show, overlay_enabled_store);
static OVERLAY_ATTR(global_alpha, S_IRUGO|S_IWUSR,
overlay_global_alpha_show, overlay_global_alpha_store);
static OVERLAY_ATTR(pre_mult_alpha, S_IRUGO|S_IWUSR,
overlay_pre_mult_alpha_show,
overlay_pre_mult_alpha_store);
static OVERLAY_ATTR(zorder, S_IRUGO|S_IWUSR,
overlay_zorder_show, overlay_zorder_store);
static struct attribute *overlay_sysfs_attrs[] = {
&overlay_attr_name.attr,
&overlay_attr_manager.attr,
&overlay_attr_input_size.attr,
&overlay_attr_screen_width.attr,
&overlay_attr_position.attr,
&overlay_attr_output_size.attr,
&overlay_attr_enabled.attr,
&overlay_attr_global_alpha.attr,
&overlay_attr_pre_mult_alpha.attr,
&overlay_attr_zorder.attr,
NULL
};
ATTRIBUTE_GROUPS(overlay_sysfs);
static ssize_t overlay_attr_show(struct kobject *kobj, struct attribute *attr,
char *buf)
{
struct omap_overlay *overlay;
struct overlay_attribute *overlay_attr;
overlay = container_of(kobj, struct omap_overlay, kobj);
overlay_attr = container_of(attr, struct overlay_attribute, attr);
if (!overlay_attr->show)
return -ENOENT;
return overlay_attr->show(overlay, buf);
}
static ssize_t overlay_attr_store(struct kobject *kobj, struct attribute *attr,
const char *buf, size_t size)
{
struct omap_overlay *overlay;
struct overlay_attribute *overlay_attr;
overlay = container_of(kobj, struct omap_overlay, kobj);
overlay_attr = container_of(attr, struct overlay_attribute, attr);
if (!overlay_attr->store)
return -ENOENT;
return overlay_attr->store(overlay, buf, size);
}
static const struct sysfs_ops overlay_sysfs_ops = {
.show = overlay_attr_show,
.store = overlay_attr_store,
};
static struct kobj_type overlay_ktype = {
.sysfs_ops = &overlay_sysfs_ops,
.default_groups = overlay_sysfs_groups,
};
int dss_overlay_kobj_init(struct omap_overlay *ovl,
struct platform_device *pdev)
{
return kobject_init_and_add(&ovl->kobj, &overlay_ktype,
&pdev->dev.kobj, "overlay%d", ovl->id);
}
void dss_overlay_kobj_uninit(struct omap_overlay *ovl)
{
kobject_del(&ovl->kobj);
kobject_put(&ovl->kobj);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/overlay-sysfs.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "MANAGER"
#include <linux/kernel.h>
#include <linux/kstrtox.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/jiffies.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
static ssize_t manager_name_show(struct omap_overlay_manager *mgr, char *buf)
{
return sysfs_emit(buf, "%s\n", mgr->name);
}
static ssize_t manager_display_show(struct omap_overlay_manager *mgr, char *buf)
{
struct omap_dss_device *dssdev = mgr->get_device(mgr);
return sysfs_emit(buf, "%s\n", dssdev ?
dssdev->name : "<none>");
}
static int manager_display_match(struct omap_dss_device *dssdev, void *data)
{
const char *str = data;
return sysfs_streq(dssdev->name, str);
}
static ssize_t manager_display_store(struct omap_overlay_manager *mgr,
const char *buf, size_t size)
{
int r = 0;
size_t len = size;
struct omap_dss_device *dssdev = NULL;
struct omap_dss_device *old_dssdev;
if (buf[size-1] == '\n')
--len;
if (len > 0)
dssdev = omap_dss_find_device((void *)buf,
manager_display_match);
if (len > 0 && dssdev == NULL)
return -EINVAL;
if (dssdev) {
DSSDBG("display %s found\n", dssdev->name);
if (omapdss_device_is_connected(dssdev)) {
DSSERR("new display is already connected\n");
r = -EINVAL;
goto put_device;
}
if (omapdss_device_is_enabled(dssdev)) {
DSSERR("new display is not disabled\n");
r = -EINVAL;
goto put_device;
}
}
old_dssdev = mgr->get_device(mgr);
if (old_dssdev) {
if (omapdss_device_is_enabled(old_dssdev)) {
DSSERR("old display is not disabled\n");
r = -EINVAL;
goto put_device;
}
old_dssdev->driver->disconnect(old_dssdev);
}
if (dssdev) {
r = dssdev->driver->connect(dssdev);
if (r) {
DSSERR("failed to connect new device\n");
goto put_device;
}
old_dssdev = mgr->get_device(mgr);
if (old_dssdev != dssdev) {
DSSERR("failed to connect device to this manager\n");
dssdev->driver->disconnect(dssdev);
goto put_device;
}
r = mgr->apply(mgr);
if (r) {
DSSERR("failed to apply dispc config\n");
goto put_device;
}
}
put_device:
if (dssdev)
omap_dss_put_device(dssdev);
return r ? r : size;
}
static ssize_t manager_default_color_show(struct omap_overlay_manager *mgr,
char *buf)
{
struct omap_overlay_manager_info info;
mgr->get_manager_info(mgr, &info);
return sysfs_emit(buf, "%#x\n", info.default_color);
}
static ssize_t manager_default_color_store(struct omap_overlay_manager *mgr,
const char *buf, size_t size)
{
struct omap_overlay_manager_info info;
u32 color;
int r;
r = kstrtouint(buf, 0, &color);
if (r)
return r;
mgr->get_manager_info(mgr, &info);
info.default_color = color;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
if (r)
return r;
return size;
}
static const char *trans_key_type_str[] = {
"gfx-destination",
"video-source",
};
static ssize_t manager_trans_key_type_show(struct omap_overlay_manager *mgr,
char *buf)
{
enum omap_dss_trans_key_type key_type;
struct omap_overlay_manager_info info;
mgr->get_manager_info(mgr, &info);
key_type = info.trans_key_type;
BUG_ON(key_type >= ARRAY_SIZE(trans_key_type_str));
return sysfs_emit(buf, "%s\n", trans_key_type_str[key_type]);
}
static ssize_t manager_trans_key_type_store(struct omap_overlay_manager *mgr,
const char *buf, size_t size)
{
struct omap_overlay_manager_info info;
int r;
r = sysfs_match_string(trans_key_type_str, buf);
if (r < 0)
return r;
mgr->get_manager_info(mgr, &info);
info.trans_key_type = r;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
if (r)
return r;
return size;
}
static ssize_t manager_trans_key_value_show(struct omap_overlay_manager *mgr,
char *buf)
{
struct omap_overlay_manager_info info;
mgr->get_manager_info(mgr, &info);
return sysfs_emit(buf, "%#x\n", info.trans_key);
}
static ssize_t manager_trans_key_value_store(struct omap_overlay_manager *mgr,
const char *buf, size_t size)
{
struct omap_overlay_manager_info info;
u32 key_value;
int r;
r = kstrtouint(buf, 0, &key_value);
if (r)
return r;
mgr->get_manager_info(mgr, &info);
info.trans_key = key_value;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
if (r)
return r;
return size;
}
static ssize_t manager_trans_key_enabled_show(struct omap_overlay_manager *mgr,
char *buf)
{
struct omap_overlay_manager_info info;
mgr->get_manager_info(mgr, &info);
return sysfs_emit(buf, "%d\n", info.trans_enabled);
}
static ssize_t manager_trans_key_enabled_store(struct omap_overlay_manager *mgr,
const char *buf, size_t size)
{
struct omap_overlay_manager_info info;
bool enable;
int r;
r = kstrtobool(buf, &enable);
if (r)
return r;
mgr->get_manager_info(mgr, &info);
info.trans_enabled = enable;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
if (r)
return r;
return size;
}
static ssize_t manager_alpha_blending_enabled_show(
struct omap_overlay_manager *mgr, char *buf)
{
struct omap_overlay_manager_info info;
if(!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
return -ENODEV;
mgr->get_manager_info(mgr, &info);
return sysfs_emit(buf, "%d\n",
info.partial_alpha_enabled);
}
static ssize_t manager_alpha_blending_enabled_store(
struct omap_overlay_manager *mgr,
const char *buf, size_t size)
{
struct omap_overlay_manager_info info;
bool enable;
int r;
if(!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
return -ENODEV;
r = kstrtobool(buf, &enable);
if (r)
return r;
mgr->get_manager_info(mgr, &info);
info.partial_alpha_enabled = enable;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
if (r)
return r;
return size;
}
static ssize_t manager_cpr_enable_show(struct omap_overlay_manager *mgr,
char *buf)
{
struct omap_overlay_manager_info info;
mgr->get_manager_info(mgr, &info);
return sysfs_emit(buf, "%d\n", info.cpr_enable);
}
static ssize_t manager_cpr_enable_store(struct omap_overlay_manager *mgr,
const char *buf, size_t size)
{
struct omap_overlay_manager_info info;
int r;
bool enable;
if (!dss_has_feature(FEAT_CPR))
return -ENODEV;
r = kstrtobool(buf, &enable);
if (r)
return r;
mgr->get_manager_info(mgr, &info);
if (info.cpr_enable == enable)
return size;
info.cpr_enable = enable;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
if (r)
return r;
return size;
}
static ssize_t manager_cpr_coef_show(struct omap_overlay_manager *mgr,
char *buf)
{
struct omap_overlay_manager_info info;
mgr->get_manager_info(mgr, &info);
return sysfs_emit(buf,
"%d %d %d %d %d %d %d %d %d\n",
info.cpr_coefs.rr,
info.cpr_coefs.rg,
info.cpr_coefs.rb,
info.cpr_coefs.gr,
info.cpr_coefs.gg,
info.cpr_coefs.gb,
info.cpr_coefs.br,
info.cpr_coefs.bg,
info.cpr_coefs.bb);
}
static ssize_t manager_cpr_coef_store(struct omap_overlay_manager *mgr,
const char *buf, size_t size)
{
struct omap_overlay_manager_info info;
struct omap_dss_cpr_coefs coefs;
int r, i;
s16 *arr;
if (!dss_has_feature(FEAT_CPR))
return -ENODEV;
if (sscanf(buf, "%hd %hd %hd %hd %hd %hd %hd %hd %hd",
&coefs.rr, &coefs.rg, &coefs.rb,
&coefs.gr, &coefs.gg, &coefs.gb,
&coefs.br, &coefs.bg, &coefs.bb) != 9)
return -EINVAL;
arr = (s16[]){ coefs.rr, coefs.rg, coefs.rb,
coefs.gr, coefs.gg, coefs.gb,
coefs.br, coefs.bg, coefs.bb };
for (i = 0; i < 9; ++i) {
if (arr[i] < -512 || arr[i] > 511)
return -EINVAL;
}
mgr->get_manager_info(mgr, &info);
info.cpr_coefs = coefs;
r = mgr->set_manager_info(mgr, &info);
if (r)
return r;
r = mgr->apply(mgr);
if (r)
return r;
return size;
}
struct manager_attribute {
struct attribute attr;
ssize_t (*show)(struct omap_overlay_manager *, char *);
ssize_t (*store)(struct omap_overlay_manager *, const char *, size_t);
};
#define MANAGER_ATTR(_name, _mode, _show, _store) \
struct manager_attribute manager_attr_##_name = \
__ATTR(_name, _mode, _show, _store)
static MANAGER_ATTR(name, S_IRUGO, manager_name_show, NULL);
static MANAGER_ATTR(display, S_IRUGO|S_IWUSR,
manager_display_show, manager_display_store);
static MANAGER_ATTR(default_color, S_IRUGO|S_IWUSR,
manager_default_color_show, manager_default_color_store);
static MANAGER_ATTR(trans_key_type, S_IRUGO|S_IWUSR,
manager_trans_key_type_show, manager_trans_key_type_store);
static MANAGER_ATTR(trans_key_value, S_IRUGO|S_IWUSR,
manager_trans_key_value_show, manager_trans_key_value_store);
static MANAGER_ATTR(trans_key_enabled, S_IRUGO|S_IWUSR,
manager_trans_key_enabled_show,
manager_trans_key_enabled_store);
static MANAGER_ATTR(alpha_blending_enabled, S_IRUGO|S_IWUSR,
manager_alpha_blending_enabled_show,
manager_alpha_blending_enabled_store);
static MANAGER_ATTR(cpr_enable, S_IRUGO|S_IWUSR,
manager_cpr_enable_show,
manager_cpr_enable_store);
static MANAGER_ATTR(cpr_coef, S_IRUGO|S_IWUSR,
manager_cpr_coef_show,
manager_cpr_coef_store);
static struct attribute *manager_sysfs_attrs[] = {
&manager_attr_name.attr,
&manager_attr_display.attr,
&manager_attr_default_color.attr,
&manager_attr_trans_key_type.attr,
&manager_attr_trans_key_value.attr,
&manager_attr_trans_key_enabled.attr,
&manager_attr_alpha_blending_enabled.attr,
&manager_attr_cpr_enable.attr,
&manager_attr_cpr_coef.attr,
NULL
};
ATTRIBUTE_GROUPS(manager_sysfs);
static ssize_t manager_attr_show(struct kobject *kobj, struct attribute *attr,
char *buf)
{
struct omap_overlay_manager *manager;
struct manager_attribute *manager_attr;
manager = container_of(kobj, struct omap_overlay_manager, kobj);
manager_attr = container_of(attr, struct manager_attribute, attr);
if (!manager_attr->show)
return -ENOENT;
return manager_attr->show(manager, buf);
}
static ssize_t manager_attr_store(struct kobject *kobj, struct attribute *attr,
const char *buf, size_t size)
{
struct omap_overlay_manager *manager;
struct manager_attribute *manager_attr;
manager = container_of(kobj, struct omap_overlay_manager, kobj);
manager_attr = container_of(attr, struct manager_attribute, attr);
if (!manager_attr->store)
return -ENOENT;
return manager_attr->store(manager, buf, size);
}
static const struct sysfs_ops manager_sysfs_ops = {
.show = manager_attr_show,
.store = manager_attr_store,
};
static struct kobj_type manager_ktype = {
.sysfs_ops = &manager_sysfs_ops,
.default_groups = manager_sysfs_groups,
};
int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
struct platform_device *pdev)
{
return kobject_init_and_add(&mgr->kobj, &manager_ktype,
&pdev->dev.kobj, "manager%d", mgr->id);
}
void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr)
{
kobject_del(&mgr->kobj);
kobject_put(&mgr->kobj);
memset(&mgr->kobj, 0, sizeof(mgr->kobj));
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/manager-sysfs.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/dpi.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "DPI"
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/string.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
#define HSDIV_DISPC 0
struct dpi_data {
struct platform_device *pdev;
struct regulator *vdds_dsi_reg;
struct dss_pll *pll;
struct mutex lock;
struct omap_video_timings timings;
struct dss_lcd_mgr_config mgr_config;
int data_lines;
struct omap_dss_device output;
bool port_initialized;
};
static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev)
{
return container_of(dssdev, struct dpi_data, output);
}
/* only used in non-DT mode */
static struct dpi_data *dpi_get_data_from_pdev(struct platform_device *pdev)
{
return platform_get_drvdata(pdev);
}
static struct dss_pll *dpi_get_pll(enum omap_channel channel)
{
/*
* XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
* would also be used for DISPC fclk. Meaning, when the DPI output is
* disabled, DISPC clock will be disabled, and TV out will stop.
*/
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP24xx:
case OMAPDSS_VER_OMAP34xx_ES1:
case OMAPDSS_VER_OMAP34xx_ES3:
case OMAPDSS_VER_OMAP3630:
case OMAPDSS_VER_AM35xx:
case OMAPDSS_VER_AM43xx:
return NULL;
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
return dss_pll_find("dsi0");
case OMAP_DSS_CHANNEL_LCD2:
return dss_pll_find("dsi1");
default:
return NULL;
}
case OMAPDSS_VER_OMAP5:
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
return dss_pll_find("dsi0");
case OMAP_DSS_CHANNEL_LCD3:
return dss_pll_find("dsi1");
default:
return NULL;
}
case OMAPDSS_VER_DRA7xx:
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
case OMAP_DSS_CHANNEL_LCD2:
return dss_pll_find("video0");
case OMAP_DSS_CHANNEL_LCD3:
return dss_pll_find("video1");
default:
return NULL;
}
default:
return NULL;
}
}
static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
{
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
case OMAP_DSS_CHANNEL_LCD2:
return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
case OMAP_DSS_CHANNEL_LCD3:
return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
default:
/* this shouldn't happen */
WARN_ON(1);
return OMAP_DSS_CLK_SRC_FCK;
}
}
struct dpi_clk_calc_ctx {
struct dss_pll *pll;
/* inputs */
unsigned long pck_min, pck_max;
/* outputs */
struct dss_pll_clock_info dsi_cinfo;
unsigned long fck;
struct dispc_clock_info dispc_cinfo;
};
static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
unsigned long pck, void *data)
{
struct dpi_clk_calc_ctx *ctx = data;
/*
* Odd dividers give us uneven duty cycle, causing problem when level
* shifted. So skip all odd dividers when the pixel clock is on the
* higher side.
*/
if (ctx->pck_min >= 100000000) {
if (lckd > 1 && lckd % 2 != 0)
return false;
if (pckd > 1 && pckd % 2 != 0)
return false;
}
ctx->dispc_cinfo.lck_div = lckd;
ctx->dispc_cinfo.pck_div = pckd;
ctx->dispc_cinfo.lck = lck;
ctx->dispc_cinfo.pck = pck;
return true;
}
static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
void *data)
{
struct dpi_clk_calc_ctx *ctx = data;
/*
* Odd dividers give us uneven duty cycle, causing problem when level
* shifted. So skip all odd dividers when the pixel clock is on the
* higher side.
*/
if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000)
return false;
ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
dpi_calc_dispc_cb, ctx);
}
static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
unsigned long clkdco,
void *data)
{
struct dpi_clk_calc_ctx *ctx = data;
ctx->dsi_cinfo.n = n;
ctx->dsi_cinfo.m = m;
ctx->dsi_cinfo.fint = fint;
ctx->dsi_cinfo.clkdco = clkdco;
return dss_pll_hsdiv_calc(ctx->pll, clkdco,
ctx->pck_min, dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
dpi_calc_hsdiv_cb, ctx);
}
static bool dpi_calc_dss_cb(unsigned long fck, void *data)
{
struct dpi_clk_calc_ctx *ctx = data;
ctx->fck = fck;
return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
dpi_calc_dispc_cb, ctx);
}
static bool dpi_dsi_clk_calc(struct dpi_data *dpi, unsigned long pck,
struct dpi_clk_calc_ctx *ctx)
{
unsigned long clkin;
unsigned long pll_min, pll_max;
memset(ctx, 0, sizeof(*ctx));
ctx->pll = dpi->pll;
ctx->pck_min = pck - 1000;
ctx->pck_max = pck + 1000;
pll_min = 0;
pll_max = 0;
clkin = clk_get_rate(ctx->pll->clkin);
return dss_pll_calc(ctx->pll, clkin,
pll_min, pll_max,
dpi_calc_pll_cb, ctx);
}
static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
{
int i;
/*
* DSS fck gives us very few possibilities, so finding a good pixel
* clock may not be possible. We try multiple times to find the clock,
* each time widening the pixel clock range we look for, up to
* +/- ~15MHz.
*/
for (i = 0; i < 25; ++i) {
bool ok;
memset(ctx, 0, sizeof(*ctx));
if (pck > 1000 * i * i * i)
ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
else
ctx->pck_min = 0;
ctx->pck_max = pck + 1000 * i * i * i;
ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx);
if (ok)
return ok;
}
return false;
}
static int dpi_set_dsi_clk(struct dpi_data *dpi, enum omap_channel channel,
unsigned long pck_req, unsigned long *fck, int *lck_div,
int *pck_div)
{
struct dpi_clk_calc_ctx ctx;
int r;
bool ok;
ok = dpi_dsi_clk_calc(dpi, pck_req, &ctx);
if (!ok)
return -EINVAL;
r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo);
if (r)
return r;
dss_select_lcd_clk_source(channel,
dpi_get_alt_clk_src(channel));
dpi->mgr_config.clock_info = ctx.dispc_cinfo;
*fck = ctx.dsi_cinfo.clkout[HSDIV_DISPC];
*lck_div = ctx.dispc_cinfo.lck_div;
*pck_div = ctx.dispc_cinfo.pck_div;
return 0;
}
static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req,
unsigned long *fck, int *lck_div, int *pck_div)
{
struct dpi_clk_calc_ctx ctx;
int r;
bool ok;
ok = dpi_dss_clk_calc(pck_req, &ctx);
if (!ok)
return -EINVAL;
r = dss_set_fck_rate(ctx.fck);
if (r)
return r;
dpi->mgr_config.clock_info = ctx.dispc_cinfo;
*fck = ctx.fck;
*lck_div = ctx.dispc_cinfo.lck_div;
*pck_div = ctx.dispc_cinfo.pck_div;
return 0;
}
static int dpi_set_mode(struct dpi_data *dpi)
{
struct omap_dss_device *out = &dpi->output;
struct omap_overlay_manager *mgr = out->manager;
struct omap_video_timings *t = &dpi->timings;
int lck_div = 0, pck_div = 0;
unsigned long fck = 0;
unsigned long pck;
int r = 0;
if (dpi->pll)
r = dpi_set_dsi_clk(dpi, mgr->id, t->pixelclock, &fck,
&lck_div, &pck_div);
else
r = dpi_set_dispc_clk(dpi, t->pixelclock, &fck,
&lck_div, &pck_div);
if (r)
return r;
pck = fck / lck_div / pck_div;
if (pck != t->pixelclock) {
DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
t->pixelclock, pck);
t->pixelclock = pck;
}
dss_mgr_set_timings(mgr, t);
return 0;
}
static void dpi_config_lcd_manager(struct dpi_data *dpi)
{
struct omap_dss_device *out = &dpi->output;
struct omap_overlay_manager *mgr = out->manager;
dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
dpi->mgr_config.stallmode = false;
dpi->mgr_config.fifohandcheck = false;
dpi->mgr_config.video_port_width = dpi->data_lines;
dpi->mgr_config.lcden_sig_polarity = 0;
dss_mgr_set_lcd_config(mgr, &dpi->mgr_config);
}
static int dpi_display_enable(struct omap_dss_device *dssdev)
{
struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
struct omap_dss_device *out = &dpi->output;
int r;
mutex_lock(&dpi->lock);
if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi->vdds_dsi_reg) {
DSSERR("no VDSS_DSI regulator\n");
r = -ENODEV;
goto err_no_reg;
}
if (out->manager == NULL) {
DSSERR("failed to enable display: no output/manager\n");
r = -ENODEV;
goto err_no_out_mgr;
}
if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) {
r = regulator_enable(dpi->vdds_dsi_reg);
if (r)
goto err_reg_enable;
}
r = dispc_runtime_get();
if (r)
goto err_get_dispc;
r = dss_dpi_select_source(out->port_num, out->manager->id);
if (r)
goto err_src_sel;
if (dpi->pll) {
r = dss_pll_enable(dpi->pll);
if (r)
goto err_dsi_pll_init;
}
r = dpi_set_mode(dpi);
if (r)
goto err_set_mode;
dpi_config_lcd_manager(dpi);
mdelay(2);
r = dss_mgr_enable(out->manager);
if (r)
goto err_mgr_enable;
mutex_unlock(&dpi->lock);
return 0;
err_mgr_enable:
err_set_mode:
if (dpi->pll)
dss_pll_disable(dpi->pll);
err_dsi_pll_init:
err_src_sel:
dispc_runtime_put();
err_get_dispc:
if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
regulator_disable(dpi->vdds_dsi_reg);
err_reg_enable:
err_no_out_mgr:
err_no_reg:
mutex_unlock(&dpi->lock);
return r;
}
static void dpi_display_disable(struct omap_dss_device *dssdev)
{
struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
struct omap_overlay_manager *mgr = dpi->output.manager;
mutex_lock(&dpi->lock);
dss_mgr_disable(mgr);
if (dpi->pll) {
dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
dss_pll_disable(dpi->pll);
}
dispc_runtime_put();
if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
regulator_disable(dpi->vdds_dsi_reg);
mutex_unlock(&dpi->lock);
}
static void dpi_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
DSSDBG("dpi_set_timings\n");
mutex_lock(&dpi->lock);
dpi->timings = *timings;
mutex_unlock(&dpi->lock);
}
static void dpi_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
mutex_lock(&dpi->lock);
*timings = dpi->timings;
mutex_unlock(&dpi->lock);
}
static int dpi_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
struct omap_overlay_manager *mgr = dpi->output.manager;
int lck_div, pck_div;
unsigned long fck;
unsigned long pck;
struct dpi_clk_calc_ctx ctx;
bool ok;
if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
return -EINVAL;
if (timings->pixelclock == 0)
return -EINVAL;
if (dpi->pll) {
ok = dpi_dsi_clk_calc(dpi, timings->pixelclock, &ctx);
if (!ok)
return -EINVAL;
fck = ctx.dsi_cinfo.clkout[HSDIV_DISPC];
} else {
ok = dpi_dss_clk_calc(timings->pixelclock, &ctx);
if (!ok)
return -EINVAL;
fck = ctx.fck;
}
lck_div = ctx.dispc_cinfo.lck_div;
pck_div = ctx.dispc_cinfo.pck_div;
pck = fck / lck_div / pck_div;
timings->pixelclock = pck;
return 0;
}
static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
{
struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
mutex_lock(&dpi->lock);
dpi->data_lines = data_lines;
mutex_unlock(&dpi->lock);
}
static int dpi_verify_dsi_pll(struct dss_pll *pll)
{
int r;
/* do initial setup with the PLL to see if it is operational */
r = dss_pll_enable(pll);
if (r)
return r;
dss_pll_disable(pll);
return 0;
}
static int dpi_init_regulator(struct dpi_data *dpi)
{
struct regulator *vdds_dsi;
if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
return 0;
if (dpi->vdds_dsi_reg)
return 0;
vdds_dsi = devm_regulator_get(&dpi->pdev->dev, "vdds_dsi");
if (IS_ERR(vdds_dsi)) {
if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
DSSERR("can't get VDDS_DSI regulator\n");
return PTR_ERR(vdds_dsi);
}
dpi->vdds_dsi_reg = vdds_dsi;
return 0;
}
static void dpi_init_pll(struct dpi_data *dpi)
{
struct dss_pll *pll;
if (dpi->pll)
return;
pll = dpi_get_pll(dpi->output.dispc_channel);
if (!pll)
return;
/* On DRA7 we need to set a mux to use the PLL */
if (omapdss_get_version() == OMAPDSS_VER_DRA7xx)
dss_ctrl_pll_set_control_mux(pll->id, dpi->output.dispc_channel);
if (dpi_verify_dsi_pll(pll)) {
DSSWARN("DSI PLL not operational\n");
return;
}
dpi->pll = pll;
}
/*
* Return a hardcoded channel for the DPI output. This should work for
* current use cases, but this can be later expanded to either resolve
* the channel in some more dynamic manner, or get the channel as a user
* parameter.
*/
static enum omap_channel dpi_get_channel(int port_num)
{
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP24xx:
case OMAPDSS_VER_OMAP34xx_ES1:
case OMAPDSS_VER_OMAP34xx_ES3:
case OMAPDSS_VER_OMAP3630:
case OMAPDSS_VER_AM35xx:
case OMAPDSS_VER_AM43xx:
return OMAP_DSS_CHANNEL_LCD;
case OMAPDSS_VER_DRA7xx:
switch (port_num) {
case 2:
return OMAP_DSS_CHANNEL_LCD3;
case 1:
return OMAP_DSS_CHANNEL_LCD2;
case 0:
default:
return OMAP_DSS_CHANNEL_LCD;
}
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
return OMAP_DSS_CHANNEL_LCD2;
case OMAPDSS_VER_OMAP5:
return OMAP_DSS_CHANNEL_LCD3;
default:
DSSWARN("unsupported DSS version\n");
return OMAP_DSS_CHANNEL_LCD;
}
}
static int dpi_connect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
struct omap_overlay_manager *mgr;
int r;
r = dpi_init_regulator(dpi);
if (r)
return r;
dpi_init_pll(dpi);
mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
if (!mgr)
return -ENODEV;
r = dss_mgr_connect(mgr, dssdev);
if (r)
return r;
r = omapdss_output_set_device(dssdev, dst);
if (r) {
DSSERR("failed to connect output to new device: %s\n",
dst->name);
dss_mgr_disconnect(mgr, dssdev);
return r;
}
return 0;
}
static void dpi_disconnect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
WARN_ON(dst != dssdev->dst);
if (dst != dssdev->dst)
return;
omapdss_output_unset_device(dssdev);
if (dssdev->manager)
dss_mgr_disconnect(dssdev->manager, dssdev);
}
static const struct omapdss_dpi_ops dpi_ops = {
.connect = dpi_connect,
.disconnect = dpi_disconnect,
.enable = dpi_display_enable,
.disable = dpi_display_disable,
.check_timings = dpi_check_timings,
.set_timings = dpi_set_timings,
.get_timings = dpi_get_timings,
.set_data_lines = dpi_set_data_lines,
};
static void dpi_init_output(struct platform_device *pdev)
{
struct dpi_data *dpi = dpi_get_data_from_pdev(pdev);
struct omap_dss_device *out = &dpi->output;
out->dev = &pdev->dev;
out->id = OMAP_DSS_OUTPUT_DPI;
out->output_type = OMAP_DISPLAY_TYPE_DPI;
out->name = "dpi.0";
out->dispc_channel = dpi_get_channel(0);
out->ops.dpi = &dpi_ops;
out->owner = THIS_MODULE;
omapdss_register_output(out);
}
static void dpi_uninit_output(struct platform_device *pdev)
{
struct dpi_data *dpi = dpi_get_data_from_pdev(pdev);
struct omap_dss_device *out = &dpi->output;
omapdss_unregister_output(out);
}
static void dpi_init_output_port(struct platform_device *pdev,
struct device_node *port)
{
struct dpi_data *dpi = port->data;
struct omap_dss_device *out = &dpi->output;
int r;
u32 port_num;
r = of_property_read_u32(port, "reg", &port_num);
if (r)
port_num = 0;
switch (port_num) {
case 2:
out->name = "dpi.2";
break;
case 1:
out->name = "dpi.1";
break;
case 0:
default:
out->name = "dpi.0";
break;
}
out->dev = &pdev->dev;
out->id = OMAP_DSS_OUTPUT_DPI;
out->output_type = OMAP_DISPLAY_TYPE_DPI;
out->dispc_channel = dpi_get_channel(port_num);
out->port_num = port_num;
out->ops.dpi = &dpi_ops;
out->owner = THIS_MODULE;
omapdss_register_output(out);
}
static void dpi_uninit_output_port(struct device_node *port)
{
struct dpi_data *dpi = port->data;
struct omap_dss_device *out = &dpi->output;
omapdss_unregister_output(out);
}
static int dpi_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
struct dpi_data *dpi;
dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
if (!dpi)
return -ENOMEM;
dpi->pdev = pdev;
platform_set_drvdata(pdev, dpi);
mutex_init(&dpi->lock);
dpi_init_output(pdev);
return 0;
}
static void dpi_unbind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
dpi_uninit_output(pdev);
}
static const struct component_ops dpi_component_ops = {
.bind = dpi_bind,
.unbind = dpi_unbind,
};
static int dpi_probe(struct platform_device *pdev)
{
return component_add(&pdev->dev, &dpi_component_ops);
}
static void dpi_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &dpi_component_ops);
}
static struct platform_driver omap_dpi_driver = {
.probe = dpi_probe,
.remove_new = dpi_remove,
.driver = {
.name = "omapdss_dpi",
.suppress_bind_attrs = true,
},
};
int __init dpi_init_platform_driver(void)
{
return platform_driver_register(&omap_dpi_driver);
}
void dpi_uninit_platform_driver(void)
{
platform_driver_unregister(&omap_dpi_driver);
}
int dpi_init_port(struct platform_device *pdev, struct device_node *port)
{
struct dpi_data *dpi;
struct device_node *ep;
u32 datalines;
int r;
dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
if (!dpi)
return -ENOMEM;
ep = omapdss_of_get_next_endpoint(port, NULL);
if (!ep)
return 0;
r = of_property_read_u32(ep, "data-lines", &datalines);
if (r) {
DSSERR("failed to parse datalines\n");
goto err_datalines;
}
dpi->data_lines = datalines;
of_node_put(ep);
dpi->pdev = pdev;
port->data = dpi;
mutex_init(&dpi->lock);
dpi_init_output_port(pdev, port);
dpi->port_initialized = true;
return 0;
err_datalines:
of_node_put(ep);
return r;
}
void dpi_uninit_port(struct device_node *port)
{
struct dpi_data *dpi = port->data;
if (!dpi->port_initialized)
return;
dpi_uninit_output_port(port);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/dpi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/seq_file.h>
#include <video/omapfb_dss.h>
#include "dss.h"
struct device_node *
omapdss_of_get_next_port(const struct device_node *parent,
struct device_node *prev)
{
struct device_node *port = NULL;
if (!parent)
return NULL;
if (!prev) {
struct device_node *ports;
/*
* It's the first call, we have to find a port subnode
* within this node or within an optional 'ports' node.
*/
ports = of_get_child_by_name(parent, "ports");
if (ports)
parent = ports;
port = of_get_child_by_name(parent, "port");
/* release the 'ports' node */
of_node_put(ports);
} else {
struct device_node *ports;
ports = of_get_parent(prev);
if (!ports)
return NULL;
do {
port = of_get_next_child(ports, prev);
if (!port) {
of_node_put(ports);
return NULL;
}
prev = port;
} while (!of_node_name_eq(port, "port"));
of_node_put(ports);
}
return port;
}
EXPORT_SYMBOL_GPL(omapdss_of_get_next_port);
struct device_node *
omapdss_of_get_next_endpoint(const struct device_node *parent,
struct device_node *prev)
{
struct device_node *ep = NULL;
if (!parent)
return NULL;
do {
ep = of_get_next_child(parent, prev);
if (!ep)
return NULL;
prev = ep;
} while (!of_node_name_eq(ep, "endpoint"));
return ep;
}
EXPORT_SYMBOL_GPL(omapdss_of_get_next_endpoint);
struct device_node *dss_of_port_get_parent_device(struct device_node *port)
{
struct device_node *np;
int i;
if (!port)
return NULL;
np = of_get_parent(port);
for (i = 0; i < 2 && np; ++i) {
struct property *prop;
prop = of_find_property(np, "compatible", NULL);
if (prop)
return np;
np = of_get_next_parent(np);
}
return NULL;
}
u32 dss_of_port_get_port_number(struct device_node *port)
{
int r;
u32 reg;
r = of_property_read_u32(port, "reg", ®);
if (r)
reg = 0;
return reg;
}
static struct device_node *omapdss_of_get_remote_port(const struct device_node *node)
{
struct device_node *np;
np = of_graph_get_remote_endpoint(node);
if (!np)
return NULL;
np = of_get_next_parent(np);
return np;
}
struct device_node *
omapdss_of_get_first_endpoint(const struct device_node *parent)
{
struct device_node *port, *ep;
port = omapdss_of_get_next_port(parent, NULL);
if (!port)
return NULL;
ep = omapdss_of_get_next_endpoint(port, NULL);
of_node_put(port);
return ep;
}
EXPORT_SYMBOL_GPL(omapdss_of_get_first_endpoint);
struct omap_dss_device *
omapdss_of_find_source_for_first_ep(struct device_node *node)
{
struct device_node *ep;
struct device_node *src_port;
struct omap_dss_device *src;
ep = omapdss_of_get_first_endpoint(node);
if (!ep)
return ERR_PTR(-EINVAL);
src_port = omapdss_of_get_remote_port(ep);
if (!src_port) {
of_node_put(ep);
return ERR_PTR(-EINVAL);
}
of_node_put(ep);
src = omap_dss_find_output_by_port_node(src_port);
of_node_put(src_port);
return src ? src : ERR_PTR(-EPROBE_DEFER);
}
EXPORT_SYMBOL_GPL(omapdss_of_find_source_for_first_ep);
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/dss-of.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#define DSS_SUBSYS_NAME "APPLY"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/jiffies.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
#include "dispc-compat.h"
/*
* We have 4 levels of cache for the dispc settings. First two are in SW and
* the latter two in HW.
*
* set_info()
* v
* +--------------------+
* | user_info |
* +--------------------+
* v
* apply()
* v
* +--------------------+
* | info |
* +--------------------+
* v
* write_regs()
* v
* +--------------------+
* | shadow registers |
* +--------------------+
* v
* VFP or lcd/digit_enable
* v
* +--------------------+
* | registers |
* +--------------------+
*/
struct ovl_priv_data {
bool user_info_dirty;
struct omap_overlay_info user_info;
bool info_dirty;
struct omap_overlay_info info;
bool shadow_info_dirty;
bool extra_info_dirty;
bool shadow_extra_info_dirty;
bool enabled;
u32 fifo_low, fifo_high;
/*
* True if overlay is to be enabled. Used to check and calculate configs
* for the overlay before it is enabled in the HW.
*/
bool enabling;
};
struct mgr_priv_data {
bool user_info_dirty;
struct omap_overlay_manager_info user_info;
bool info_dirty;
struct omap_overlay_manager_info info;
bool shadow_info_dirty;
/* If true, GO bit is up and shadow registers cannot be written.
* Never true for manual update displays */
bool busy;
/* If true, dispc output is enabled */
bool updating;
/* If true, a display is enabled using this manager */
bool enabled;
bool extra_info_dirty;
bool shadow_extra_info_dirty;
struct omap_video_timings timings;
struct dss_lcd_mgr_config lcd_config;
void (*framedone_handler)(void *);
void *framedone_handler_data;
};
static struct {
struct ovl_priv_data ovl_priv_data_array[MAX_DSS_OVERLAYS];
struct mgr_priv_data mgr_priv_data_array[MAX_DSS_MANAGERS];
bool irq_enabled;
} dss_data;
/* protects dss_data */
static DEFINE_SPINLOCK(data_lock);
/* lock for blocking functions */
static DEFINE_MUTEX(apply_lock);
static DECLARE_COMPLETION(extra_updated_completion);
static void dss_register_vsync_isr(void);
static struct ovl_priv_data *get_ovl_priv(struct omap_overlay *ovl)
{
return &dss_data.ovl_priv_data_array[ovl->id];
}
static struct mgr_priv_data *get_mgr_priv(struct omap_overlay_manager *mgr)
{
return &dss_data.mgr_priv_data_array[mgr->id];
}
static void apply_init_priv(void)
{
const int num_ovls = dss_feat_get_num_ovls();
struct mgr_priv_data *mp;
int i;
for (i = 0; i < num_ovls; ++i) {
struct ovl_priv_data *op;
op = &dss_data.ovl_priv_data_array[i];
op->info.color_mode = OMAP_DSS_COLOR_RGB16;
op->info.rotation_type = OMAP_DSS_ROT_DMA;
op->info.global_alpha = 255;
switch (i) {
case 0:
op->info.zorder = 0;
break;
case 1:
op->info.zorder =
dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 3 : 0;
break;
case 2:
op->info.zorder =
dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 2 : 0;
break;
case 3:
op->info.zorder =
dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 1 : 0;
break;
}
op->user_info = op->info;
}
/*
* Initialize some of the lcd_config fields for TV manager, this lets
* us prevent checking if the manager is LCD or TV at some places
*/
mp = &dss_data.mgr_priv_data_array[OMAP_DSS_CHANNEL_DIGIT];
mp->lcd_config.video_port_width = 24;
mp->lcd_config.clock_info.lck_div = 1;
mp->lcd_config.clock_info.pck_div = 1;
}
/*
* A LCD manager's stallmode decides whether it is in manual or auto update. TV
* manager is always auto update, stallmode field for TV manager is false by
* default
*/
static bool ovl_manual_update(struct omap_overlay *ovl)
{
struct mgr_priv_data *mp = get_mgr_priv(ovl->manager);
return mp->lcd_config.stallmode;
}
static bool mgr_manual_update(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
return mp->lcd_config.stallmode;
}
static int dss_check_settings_low(struct omap_overlay_manager *mgr,
bool applying)
{
struct omap_overlay_info *oi;
struct omap_overlay_manager_info *mi;
struct omap_overlay *ovl;
struct omap_overlay_info *ois[MAX_DSS_OVERLAYS];
struct ovl_priv_data *op;
struct mgr_priv_data *mp;
mp = get_mgr_priv(mgr);
if (!mp->enabled)
return 0;
if (applying && mp->user_info_dirty)
mi = &mp->user_info;
else
mi = &mp->info;
/* collect the infos to be tested into the array */
list_for_each_entry(ovl, &mgr->overlays, list) {
op = get_ovl_priv(ovl);
if (!op->enabled && !op->enabling)
oi = NULL;
else if (applying && op->user_info_dirty)
oi = &op->user_info;
else
oi = &op->info;
ois[ovl->id] = oi;
}
return dss_mgr_check(mgr, mi, &mp->timings, &mp->lcd_config, ois);
}
/*
* check manager and overlay settings using overlay_info from data->info
*/
static int dss_check_settings(struct omap_overlay_manager *mgr)
{
return dss_check_settings_low(mgr, false);
}
/*
* check manager and overlay settings using overlay_info from ovl->info if
* dirty and from data->info otherwise
*/
static int dss_check_settings_apply(struct omap_overlay_manager *mgr)
{
return dss_check_settings_low(mgr, true);
}
static bool need_isr(void)
{
const int num_mgrs = dss_feat_get_num_mgrs();
int i;
for (i = 0; i < num_mgrs; ++i) {
struct omap_overlay_manager *mgr;
struct mgr_priv_data *mp;
struct omap_overlay *ovl;
mgr = omap_dss_get_overlay_manager(i);
mp = get_mgr_priv(mgr);
if (!mp->enabled)
continue;
if (mgr_manual_update(mgr)) {
/* to catch FRAMEDONE */
if (mp->updating)
return true;
} else {
/* to catch GO bit going down */
if (mp->busy)
return true;
/* to write new values to registers */
if (mp->info_dirty)
return true;
/* to set GO bit */
if (mp->shadow_info_dirty)
return true;
/*
* NOTE: we don't check extra_info flags for disabled
* managers, once the manager is enabled, the extra_info
* related manager changes will be taken in by HW.
*/
/* to write new values to registers */
if (mp->extra_info_dirty)
return true;
/* to set GO bit */
if (mp->shadow_extra_info_dirty)
return true;
list_for_each_entry(ovl, &mgr->overlays, list) {
struct ovl_priv_data *op;
op = get_ovl_priv(ovl);
/*
* NOTE: we check extra_info flags even for
* disabled overlays, as extra_infos need to be
* always written.
*/
/* to write new values to registers */
if (op->extra_info_dirty)
return true;
/* to set GO bit */
if (op->shadow_extra_info_dirty)
return true;
if (!op->enabled)
continue;
/* to write new values to registers */
if (op->info_dirty)
return true;
/* to set GO bit */
if (op->shadow_info_dirty)
return true;
}
}
}
return false;
}
static bool need_go(struct omap_overlay_manager *mgr)
{
struct omap_overlay *ovl;
struct mgr_priv_data *mp;
struct ovl_priv_data *op;
mp = get_mgr_priv(mgr);
if (mp->shadow_info_dirty || mp->shadow_extra_info_dirty)
return true;
list_for_each_entry(ovl, &mgr->overlays, list) {
op = get_ovl_priv(ovl);
if (op->shadow_info_dirty || op->shadow_extra_info_dirty)
return true;
}
return false;
}
/* returns true if an extra_info field is currently being updated */
static bool extra_info_update_ongoing(void)
{
const int num_mgrs = dss_feat_get_num_mgrs();
int i;
for (i = 0; i < num_mgrs; ++i) {
struct omap_overlay_manager *mgr;
struct omap_overlay *ovl;
struct mgr_priv_data *mp;
mgr = omap_dss_get_overlay_manager(i);
mp = get_mgr_priv(mgr);
if (!mp->enabled)
continue;
if (!mp->updating)
continue;
if (mp->extra_info_dirty || mp->shadow_extra_info_dirty)
return true;
list_for_each_entry(ovl, &mgr->overlays, list) {
struct ovl_priv_data *op = get_ovl_priv(ovl);
if (op->extra_info_dirty || op->shadow_extra_info_dirty)
return true;
}
}
return false;
}
/* wait until no extra_info updates are pending */
static void wait_pending_extra_info_updates(void)
{
bool updating;
unsigned long flags;
unsigned long t;
int r;
spin_lock_irqsave(&data_lock, flags);
updating = extra_info_update_ongoing();
if (!updating) {
spin_unlock_irqrestore(&data_lock, flags);
return;
}
init_completion(&extra_updated_completion);
spin_unlock_irqrestore(&data_lock, flags);
t = msecs_to_jiffies(500);
r = wait_for_completion_timeout(&extra_updated_completion, t);
if (r == 0)
DSSWARN("timeout in wait_pending_extra_info_updates\n");
}
static struct omap_dss_device *dss_mgr_get_device(struct omap_overlay_manager *mgr)
{
struct omap_dss_device *dssdev;
dssdev = mgr->output;
if (dssdev == NULL)
return NULL;
while (dssdev->dst)
dssdev = dssdev->dst;
if (dssdev->driver)
return dssdev;
else
return NULL;
}
static struct omap_dss_device *dss_ovl_get_device(struct omap_overlay *ovl)
{
return ovl->manager ? dss_mgr_get_device(ovl->manager) : NULL;
}
static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
{
unsigned long timeout = msecs_to_jiffies(500);
u32 irq;
int r;
if (mgr->output == NULL)
return -ENODEV;
r = dispc_runtime_get();
if (r)
return r;
switch (mgr->output->id) {
case OMAP_DSS_OUTPUT_VENC:
irq = DISPC_IRQ_EVSYNC_ODD;
break;
case OMAP_DSS_OUTPUT_HDMI:
irq = DISPC_IRQ_EVSYNC_EVEN;
break;
default:
irq = dispc_mgr_get_vsync_irq(mgr->id);
break;
}
r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
dispc_runtime_put();
return r;
}
static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
{
unsigned long timeout = msecs_to_jiffies(500);
struct mgr_priv_data *mp = get_mgr_priv(mgr);
u32 irq;
unsigned long flags;
int r;
int i;
spin_lock_irqsave(&data_lock, flags);
if (mgr_manual_update(mgr)) {
spin_unlock_irqrestore(&data_lock, flags);
return 0;
}
if (!mp->enabled) {
spin_unlock_irqrestore(&data_lock, flags);
return 0;
}
spin_unlock_irqrestore(&data_lock, flags);
r = dispc_runtime_get();
if (r)
return r;
irq = dispc_mgr_get_vsync_irq(mgr->id);
i = 0;
while (1) {
bool shadow_dirty, dirty;
spin_lock_irqsave(&data_lock, flags);
dirty = mp->info_dirty;
shadow_dirty = mp->shadow_info_dirty;
spin_unlock_irqrestore(&data_lock, flags);
if (!dirty && !shadow_dirty) {
r = 0;
break;
}
/* 4 iterations is the worst case:
* 1 - initial iteration, dirty = true (between VFP and VSYNC)
* 2 - first VSYNC, dirty = true
* 3 - dirty = false, shadow_dirty = true
* 4 - shadow_dirty = false */
if (i++ == 3) {
DSSERR("mgr(%d)->wait_for_go() not finishing\n",
mgr->id);
r = 0;
break;
}
r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
if (r == -ERESTARTSYS)
break;
if (r) {
DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id);
break;
}
}
dispc_runtime_put();
return r;
}
static int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
{
unsigned long timeout = msecs_to_jiffies(500);
struct ovl_priv_data *op;
struct mgr_priv_data *mp;
u32 irq;
unsigned long flags;
int r;
int i;
if (!ovl->manager)
return 0;
mp = get_mgr_priv(ovl->manager);
spin_lock_irqsave(&data_lock, flags);
if (ovl_manual_update(ovl)) {
spin_unlock_irqrestore(&data_lock, flags);
return 0;
}
if (!mp->enabled) {
spin_unlock_irqrestore(&data_lock, flags);
return 0;
}
spin_unlock_irqrestore(&data_lock, flags);
r = dispc_runtime_get();
if (r)
return r;
irq = dispc_mgr_get_vsync_irq(ovl->manager->id);
op = get_ovl_priv(ovl);
i = 0;
while (1) {
bool shadow_dirty, dirty;
spin_lock_irqsave(&data_lock, flags);
dirty = op->info_dirty;
shadow_dirty = op->shadow_info_dirty;
spin_unlock_irqrestore(&data_lock, flags);
if (!dirty && !shadow_dirty) {
r = 0;
break;
}
/* 4 iterations is the worst case:
* 1 - initial iteration, dirty = true (between VFP and VSYNC)
* 2 - first VSYNC, dirty = true
* 3 - dirty = false, shadow_dirty = true
* 4 - shadow_dirty = false */
if (i++ == 3) {
DSSERR("ovl(%d)->wait_for_go() not finishing\n",
ovl->id);
r = 0;
break;
}
r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
if (r == -ERESTARTSYS)
break;
if (r) {
DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id);
break;
}
}
dispc_runtime_put();
return r;
}
static void dss_ovl_write_regs(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
struct omap_overlay_info *oi;
bool replication;
struct mgr_priv_data *mp;
int r;
DSSDBG("writing ovl %d regs\n", ovl->id);
if (!op->enabled || !op->info_dirty)
return;
oi = &op->info;
mp = get_mgr_priv(ovl->manager);
replication = dss_ovl_use_replication(mp->lcd_config, oi->color_mode);
r = dispc_ovl_setup(ovl->id, oi, replication, &mp->timings, false);
if (r) {
/*
* We can't do much here, as this function can be called from
* vsync interrupt.
*/
DSSERR("dispc_ovl_setup failed for ovl %d\n", ovl->id);
/* This will leave fifo configurations in a nonoptimal state */
op->enabled = false;
dispc_ovl_enable(ovl->id, false);
return;
}
op->info_dirty = false;
if (mp->updating)
op->shadow_info_dirty = true;
}
static void dss_ovl_write_regs_extra(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
struct mgr_priv_data *mp;
DSSDBG("writing ovl %d regs extra\n", ovl->id);
if (!op->extra_info_dirty)
return;
/* note: write also when op->enabled == false, so that the ovl gets
* disabled */
dispc_ovl_enable(ovl->id, op->enabled);
dispc_ovl_set_fifo_threshold(ovl->id, op->fifo_low, op->fifo_high);
mp = get_mgr_priv(ovl->manager);
op->extra_info_dirty = false;
if (mp->updating)
op->shadow_extra_info_dirty = true;
}
static void dss_mgr_write_regs(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
struct omap_overlay *ovl;
DSSDBG("writing mgr %d regs\n", mgr->id);
if (!mp->enabled)
return;
WARN_ON(mp->busy);
/* Commit overlay settings */
list_for_each_entry(ovl, &mgr->overlays, list) {
dss_ovl_write_regs(ovl);
dss_ovl_write_regs_extra(ovl);
}
if (mp->info_dirty) {
dispc_mgr_setup(mgr->id, &mp->info);
mp->info_dirty = false;
if (mp->updating)
mp->shadow_info_dirty = true;
}
}
static void dss_mgr_write_regs_extra(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
DSSDBG("writing mgr %d regs extra\n", mgr->id);
if (!mp->extra_info_dirty)
return;
dispc_mgr_set_timings(mgr->id, &mp->timings);
/* lcd_config parameters */
if (dss_mgr_is_lcd(mgr->id))
dispc_mgr_set_lcd_config(mgr->id, &mp->lcd_config);
mp->extra_info_dirty = false;
if (mp->updating)
mp->shadow_extra_info_dirty = true;
}
static void dss_write_regs(void)
{
const int num_mgrs = omap_dss_get_num_overlay_managers();
int i;
for (i = 0; i < num_mgrs; ++i) {
struct omap_overlay_manager *mgr;
struct mgr_priv_data *mp;
int r;
mgr = omap_dss_get_overlay_manager(i);
mp = get_mgr_priv(mgr);
if (!mp->enabled || mgr_manual_update(mgr) || mp->busy)
continue;
r = dss_check_settings(mgr);
if (r) {
DSSERR("cannot write registers for manager %s: "
"illegal configuration\n", mgr->name);
continue;
}
dss_mgr_write_regs(mgr);
dss_mgr_write_regs_extra(mgr);
}
}
static void dss_set_go_bits(void)
{
const int num_mgrs = omap_dss_get_num_overlay_managers();
int i;
for (i = 0; i < num_mgrs; ++i) {
struct omap_overlay_manager *mgr;
struct mgr_priv_data *mp;
mgr = omap_dss_get_overlay_manager(i);
mp = get_mgr_priv(mgr);
if (!mp->enabled || mgr_manual_update(mgr) || mp->busy)
continue;
if (!need_go(mgr))
continue;
mp->busy = true;
if (!dss_data.irq_enabled && need_isr())
dss_register_vsync_isr();
dispc_mgr_go(mgr->id);
}
}
static void mgr_clear_shadow_dirty(struct omap_overlay_manager *mgr)
{
struct omap_overlay *ovl;
struct mgr_priv_data *mp;
struct ovl_priv_data *op;
mp = get_mgr_priv(mgr);
mp->shadow_info_dirty = false;
mp->shadow_extra_info_dirty = false;
list_for_each_entry(ovl, &mgr->overlays, list) {
op = get_ovl_priv(ovl);
op->shadow_info_dirty = false;
op->shadow_extra_info_dirty = false;
}
}
static int dss_mgr_connect_compat(struct omap_overlay_manager *mgr,
struct omap_dss_device *dst)
{
return mgr->set_output(mgr, dst);
}
static void dss_mgr_disconnect_compat(struct omap_overlay_manager *mgr,
struct omap_dss_device *dst)
{
mgr->unset_output(mgr);
}
static void dss_mgr_start_update_compat(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
unsigned long flags;
int r;
spin_lock_irqsave(&data_lock, flags);
WARN_ON(mp->updating);
r = dss_check_settings(mgr);
if (r) {
DSSERR("cannot start manual update: illegal configuration\n");
spin_unlock_irqrestore(&data_lock, flags);
return;
}
dss_mgr_write_regs(mgr);
dss_mgr_write_regs_extra(mgr);
mp->updating = true;
if (!dss_data.irq_enabled && need_isr())
dss_register_vsync_isr();
dispc_mgr_enable_sync(mgr->id);
spin_unlock_irqrestore(&data_lock, flags);
}
static void dss_apply_irq_handler(void *data, u32 mask);
static void dss_register_vsync_isr(void)
{
const int num_mgrs = dss_feat_get_num_mgrs();
u32 mask;
int r, i;
mask = 0;
for (i = 0; i < num_mgrs; ++i)
mask |= dispc_mgr_get_vsync_irq(i);
for (i = 0; i < num_mgrs; ++i)
mask |= dispc_mgr_get_framedone_irq(i);
r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
WARN_ON(r);
dss_data.irq_enabled = true;
}
static void dss_unregister_vsync_isr(void)
{
const int num_mgrs = dss_feat_get_num_mgrs();
u32 mask;
int r, i;
mask = 0;
for (i = 0; i < num_mgrs; ++i)
mask |= dispc_mgr_get_vsync_irq(i);
for (i = 0; i < num_mgrs; ++i)
mask |= dispc_mgr_get_framedone_irq(i);
r = omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, mask);
WARN_ON(r);
dss_data.irq_enabled = false;
}
static void dss_apply_irq_handler(void *data, u32 mask)
{
const int num_mgrs = dss_feat_get_num_mgrs();
int i;
bool extra_updating;
spin_lock(&data_lock);
/* clear busy, updating flags, shadow_dirty flags */
for (i = 0; i < num_mgrs; i++) {
struct omap_overlay_manager *mgr;
struct mgr_priv_data *mp;
mgr = omap_dss_get_overlay_manager(i);
mp = get_mgr_priv(mgr);
if (!mp->enabled)
continue;
mp->updating = dispc_mgr_is_enabled(i);
if (!mgr_manual_update(mgr)) {
bool was_busy = mp->busy;
mp->busy = dispc_mgr_go_busy(i);
if (was_busy && !mp->busy)
mgr_clear_shadow_dirty(mgr);
}
}
dss_write_regs();
dss_set_go_bits();
extra_updating = extra_info_update_ongoing();
if (!extra_updating)
complete_all(&extra_updated_completion);
/* call framedone handlers for manual update displays */
for (i = 0; i < num_mgrs; i++) {
struct omap_overlay_manager *mgr;
struct mgr_priv_data *mp;
mgr = omap_dss_get_overlay_manager(i);
mp = get_mgr_priv(mgr);
if (!mgr_manual_update(mgr) || !mp->framedone_handler)
continue;
if (mask & dispc_mgr_get_framedone_irq(i))
mp->framedone_handler(mp->framedone_handler_data);
}
if (!need_isr())
dss_unregister_vsync_isr();
spin_unlock(&data_lock);
}
static void omap_dss_mgr_apply_ovl(struct omap_overlay *ovl)
{
struct ovl_priv_data *op;
op = get_ovl_priv(ovl);
if (!op->user_info_dirty)
return;
op->user_info_dirty = false;
op->info_dirty = true;
op->info = op->user_info;
}
static void omap_dss_mgr_apply_mgr(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp;
mp = get_mgr_priv(mgr);
if (!mp->user_info_dirty)
return;
mp->user_info_dirty = false;
mp->info_dirty = true;
mp->info = mp->user_info;
}
static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
{
unsigned long flags;
struct omap_overlay *ovl;
int r;
DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
spin_lock_irqsave(&data_lock, flags);
r = dss_check_settings_apply(mgr);
if (r) {
spin_unlock_irqrestore(&data_lock, flags);
DSSERR("failed to apply settings: illegal configuration.\n");
return r;
}
/* Configure overlays */
list_for_each_entry(ovl, &mgr->overlays, list)
omap_dss_mgr_apply_ovl(ovl);
/* Configure manager */
omap_dss_mgr_apply_mgr(mgr);
dss_write_regs();
dss_set_go_bits();
spin_unlock_irqrestore(&data_lock, flags);
return 0;
}
static void dss_apply_ovl_enable(struct omap_overlay *ovl, bool enable)
{
struct ovl_priv_data *op;
op = get_ovl_priv(ovl);
if (op->enabled == enable)
return;
op->enabled = enable;
op->extra_info_dirty = true;
}
static void dss_apply_ovl_fifo_thresholds(struct omap_overlay *ovl,
u32 fifo_low, u32 fifo_high)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
if (op->fifo_low == fifo_low && op->fifo_high == fifo_high)
return;
op->fifo_low = fifo_low;
op->fifo_high = fifo_high;
op->extra_info_dirty = true;
}
static void dss_ovl_setup_fifo(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
u32 fifo_low, fifo_high;
bool use_fifo_merge = false;
if (!op->enabled && !op->enabling)
return;
dispc_ovl_compute_fifo_thresholds(ovl->id, &fifo_low, &fifo_high,
use_fifo_merge, ovl_manual_update(ovl));
dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high);
}
static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr)
{
struct omap_overlay *ovl;
struct mgr_priv_data *mp;
mp = get_mgr_priv(mgr);
if (!mp->enabled)
return;
list_for_each_entry(ovl, &mgr->overlays, list)
dss_ovl_setup_fifo(ovl);
}
static void dss_setup_fifos(void)
{
const int num_mgrs = omap_dss_get_num_overlay_managers();
struct omap_overlay_manager *mgr;
int i;
for (i = 0; i < num_mgrs; ++i) {
mgr = omap_dss_get_overlay_manager(i);
dss_mgr_setup_fifos(mgr);
}
}
static int dss_mgr_enable_compat(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
unsigned long flags;
int r;
mutex_lock(&apply_lock);
if (mp->enabled)
goto out;
spin_lock_irqsave(&data_lock, flags);
mp->enabled = true;
r = dss_check_settings(mgr);
if (r) {
DSSERR("failed to enable manager %d: check_settings failed\n",
mgr->id);
goto err;
}
dss_setup_fifos();
dss_write_regs();
dss_set_go_bits();
if (!mgr_manual_update(mgr))
mp->updating = true;
if (!dss_data.irq_enabled && need_isr())
dss_register_vsync_isr();
spin_unlock_irqrestore(&data_lock, flags);
if (!mgr_manual_update(mgr))
dispc_mgr_enable_sync(mgr->id);
out:
mutex_unlock(&apply_lock);
return 0;
err:
mp->enabled = false;
spin_unlock_irqrestore(&data_lock, flags);
mutex_unlock(&apply_lock);
return r;
}
static void dss_mgr_disable_compat(struct omap_overlay_manager *mgr)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
unsigned long flags;
mutex_lock(&apply_lock);
if (!mp->enabled)
goto out;
wait_pending_extra_info_updates();
if (!mgr_manual_update(mgr))
dispc_mgr_disable_sync(mgr->id);
spin_lock_irqsave(&data_lock, flags);
mp->updating = false;
mp->enabled = false;
spin_unlock_irqrestore(&data_lock, flags);
out:
mutex_unlock(&apply_lock);
}
static int dss_mgr_set_info(struct omap_overlay_manager *mgr,
struct omap_overlay_manager_info *info)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
unsigned long flags;
int r;
r = dss_mgr_simple_check(mgr, info);
if (r)
return r;
spin_lock_irqsave(&data_lock, flags);
mp->user_info = *info;
mp->user_info_dirty = true;
spin_unlock_irqrestore(&data_lock, flags);
return 0;
}
static void dss_mgr_get_info(struct omap_overlay_manager *mgr,
struct omap_overlay_manager_info *info)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
unsigned long flags;
spin_lock_irqsave(&data_lock, flags);
*info = mp->user_info;
spin_unlock_irqrestore(&data_lock, flags);
}
static int dss_mgr_set_output(struct omap_overlay_manager *mgr,
struct omap_dss_device *output)
{
int r;
mutex_lock(&apply_lock);
if (mgr->output) {
DSSERR("manager %s is already connected to an output\n",
mgr->name);
r = -EINVAL;
goto err;
}
if ((mgr->supported_outputs & output->id) == 0) {
DSSERR("output does not support manager %s\n",
mgr->name);
r = -EINVAL;
goto err;
}
output->manager = mgr;
mgr->output = output;
mutex_unlock(&apply_lock);
return 0;
err:
mutex_unlock(&apply_lock);
return r;
}
static int dss_mgr_unset_output(struct omap_overlay_manager *mgr)
{
int r;
struct mgr_priv_data *mp = get_mgr_priv(mgr);
unsigned long flags;
mutex_lock(&apply_lock);
if (!mgr->output) {
DSSERR("failed to unset output, output not set\n");
r = -EINVAL;
goto err;
}
spin_lock_irqsave(&data_lock, flags);
if (mp->enabled) {
DSSERR("output can't be unset when manager is enabled\n");
r = -EINVAL;
goto err1;
}
spin_unlock_irqrestore(&data_lock, flags);
mgr->output->manager = NULL;
mgr->output = NULL;
mutex_unlock(&apply_lock);
return 0;
err1:
spin_unlock_irqrestore(&data_lock, flags);
err:
mutex_unlock(&apply_lock);
return r;
}
static void dss_apply_mgr_timings(struct omap_overlay_manager *mgr,
const struct omap_video_timings *timings)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
mp->timings = *timings;
mp->extra_info_dirty = true;
}
static void dss_mgr_set_timings_compat(struct omap_overlay_manager *mgr,
const struct omap_video_timings *timings)
{
unsigned long flags;
struct mgr_priv_data *mp = get_mgr_priv(mgr);
spin_lock_irqsave(&data_lock, flags);
if (mp->updating) {
DSSERR("cannot set timings for %s: manager needs to be disabled\n",
mgr->name);
goto out;
}
dss_apply_mgr_timings(mgr, timings);
out:
spin_unlock_irqrestore(&data_lock, flags);
}
static void dss_apply_mgr_lcd_config(struct omap_overlay_manager *mgr,
const struct dss_lcd_mgr_config *config)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
mp->lcd_config = *config;
mp->extra_info_dirty = true;
}
static void dss_mgr_set_lcd_config_compat(struct omap_overlay_manager *mgr,
const struct dss_lcd_mgr_config *config)
{
unsigned long flags;
struct mgr_priv_data *mp = get_mgr_priv(mgr);
spin_lock_irqsave(&data_lock, flags);
if (mp->enabled) {
DSSERR("cannot apply lcd config for %s: manager needs to be disabled\n",
mgr->name);
goto out;
}
dss_apply_mgr_lcd_config(mgr, config);
out:
spin_unlock_irqrestore(&data_lock, flags);
}
static int dss_ovl_set_info(struct omap_overlay *ovl,
struct omap_overlay_info *info)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
int r;
r = dss_ovl_simple_check(ovl, info);
if (r)
return r;
spin_lock_irqsave(&data_lock, flags);
op->user_info = *info;
op->user_info_dirty = true;
spin_unlock_irqrestore(&data_lock, flags);
return 0;
}
static void dss_ovl_get_info(struct omap_overlay *ovl,
struct omap_overlay_info *info)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
spin_lock_irqsave(&data_lock, flags);
*info = op->user_info;
spin_unlock_irqrestore(&data_lock, flags);
}
static int dss_ovl_set_manager(struct omap_overlay *ovl,
struct omap_overlay_manager *mgr)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
int r;
if (!mgr)
return -EINVAL;
mutex_lock(&apply_lock);
if (ovl->manager) {
DSSERR("overlay '%s' already has a manager '%s'\n",
ovl->name, ovl->manager->name);
r = -EINVAL;
goto err;
}
r = dispc_runtime_get();
if (r)
goto err;
spin_lock_irqsave(&data_lock, flags);
if (op->enabled) {
spin_unlock_irqrestore(&data_lock, flags);
DSSERR("overlay has to be disabled to change the manager\n");
r = -EINVAL;
goto err1;
}
dispc_ovl_set_channel_out(ovl->id, mgr->id);
ovl->manager = mgr;
list_add_tail(&ovl->list, &mgr->overlays);
spin_unlock_irqrestore(&data_lock, flags);
dispc_runtime_put();
mutex_unlock(&apply_lock);
return 0;
err1:
dispc_runtime_put();
err:
mutex_unlock(&apply_lock);
return r;
}
static int dss_ovl_unset_manager(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
int r;
mutex_lock(&apply_lock);
if (!ovl->manager) {
DSSERR("failed to detach overlay: manager not set\n");
r = -EINVAL;
goto err;
}
spin_lock_irqsave(&data_lock, flags);
if (op->enabled) {
spin_unlock_irqrestore(&data_lock, flags);
DSSERR("overlay has to be disabled to unset the manager\n");
r = -EINVAL;
goto err;
}
spin_unlock_irqrestore(&data_lock, flags);
/* wait for pending extra_info updates to ensure the ovl is disabled */
wait_pending_extra_info_updates();
/*
* For a manual update display, there is no guarantee that the overlay
* is really disabled in HW, we may need an extra update from this
* manager before the configurations can go in. Return an error if the
* overlay needed an update from the manager.
*
* TODO: Instead of returning an error, try to do a dummy manager update
* here to disable the overlay in hardware. Use the *GATED fields in
* the DISPC_CONFIG registers to do a dummy update.
*/
spin_lock_irqsave(&data_lock, flags);
if (ovl_manual_update(ovl) && op->extra_info_dirty) {
spin_unlock_irqrestore(&data_lock, flags);
DSSERR("need an update to change the manager\n");
r = -EINVAL;
goto err;
}
ovl->manager = NULL;
list_del(&ovl->list);
spin_unlock_irqrestore(&data_lock, flags);
mutex_unlock(&apply_lock);
return 0;
err:
mutex_unlock(&apply_lock);
return r;
}
static bool dss_ovl_is_enabled(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
bool e;
spin_lock_irqsave(&data_lock, flags);
e = op->enabled;
spin_unlock_irqrestore(&data_lock, flags);
return e;
}
static int dss_ovl_enable(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
int r;
mutex_lock(&apply_lock);
if (op->enabled) {
r = 0;
goto err1;
}
if (ovl->manager == NULL || ovl->manager->output == NULL) {
r = -EINVAL;
goto err1;
}
spin_lock_irqsave(&data_lock, flags);
op->enabling = true;
r = dss_check_settings(ovl->manager);
if (r) {
DSSERR("failed to enable overlay %d: check_settings failed\n",
ovl->id);
goto err2;
}
dss_setup_fifos();
op->enabling = false;
dss_apply_ovl_enable(ovl, true);
dss_write_regs();
dss_set_go_bits();
spin_unlock_irqrestore(&data_lock, flags);
mutex_unlock(&apply_lock);
return 0;
err2:
op->enabling = false;
spin_unlock_irqrestore(&data_lock, flags);
err1:
mutex_unlock(&apply_lock);
return r;
}
static int dss_ovl_disable(struct omap_overlay *ovl)
{
struct ovl_priv_data *op = get_ovl_priv(ovl);
unsigned long flags;
int r;
mutex_lock(&apply_lock);
if (!op->enabled) {
r = 0;
goto err;
}
if (ovl->manager == NULL || ovl->manager->output == NULL) {
r = -EINVAL;
goto err;
}
spin_lock_irqsave(&data_lock, flags);
dss_apply_ovl_enable(ovl, false);
dss_write_regs();
dss_set_go_bits();
spin_unlock_irqrestore(&data_lock, flags);
mutex_unlock(&apply_lock);
return 0;
err:
mutex_unlock(&apply_lock);
return r;
}
static int dss_mgr_register_framedone_handler_compat(struct omap_overlay_manager *mgr,
void (*handler)(void *), void *data)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
if (mp->framedone_handler)
return -EBUSY;
mp->framedone_handler = handler;
mp->framedone_handler_data = data;
return 0;
}
static void dss_mgr_unregister_framedone_handler_compat(struct omap_overlay_manager *mgr,
void (*handler)(void *), void *data)
{
struct mgr_priv_data *mp = get_mgr_priv(mgr);
WARN_ON(mp->framedone_handler != handler ||
mp->framedone_handler_data != data);
mp->framedone_handler = NULL;
mp->framedone_handler_data = NULL;
}
static const struct dss_mgr_ops apply_mgr_ops = {
.connect = dss_mgr_connect_compat,
.disconnect = dss_mgr_disconnect_compat,
.start_update = dss_mgr_start_update_compat,
.enable = dss_mgr_enable_compat,
.disable = dss_mgr_disable_compat,
.set_timings = dss_mgr_set_timings_compat,
.set_lcd_config = dss_mgr_set_lcd_config_compat,
.register_framedone_handler = dss_mgr_register_framedone_handler_compat,
.unregister_framedone_handler = dss_mgr_unregister_framedone_handler_compat,
};
static int compat_refcnt;
static DEFINE_MUTEX(compat_init_lock);
int omapdss_compat_init(void)
{
struct platform_device *pdev = dss_get_core_pdev();
int i, r;
mutex_lock(&compat_init_lock);
if (compat_refcnt++ > 0)
goto out;
apply_init_priv();
dss_init_overlay_managers_sysfs(pdev);
dss_init_overlays(pdev);
for (i = 0; i < omap_dss_get_num_overlay_managers(); i++) {
struct omap_overlay_manager *mgr;
mgr = omap_dss_get_overlay_manager(i);
mgr->set_output = &dss_mgr_set_output;
mgr->unset_output = &dss_mgr_unset_output;
mgr->apply = &omap_dss_mgr_apply;
mgr->set_manager_info = &dss_mgr_set_info;
mgr->get_manager_info = &dss_mgr_get_info;
mgr->wait_for_go = &dss_mgr_wait_for_go;
mgr->wait_for_vsync = &dss_mgr_wait_for_vsync;
mgr->get_device = &dss_mgr_get_device;
}
for (i = 0; i < omap_dss_get_num_overlays(); i++) {
struct omap_overlay *ovl = omap_dss_get_overlay(i);
ovl->is_enabled = &dss_ovl_is_enabled;
ovl->enable = &dss_ovl_enable;
ovl->disable = &dss_ovl_disable;
ovl->set_manager = &dss_ovl_set_manager;
ovl->unset_manager = &dss_ovl_unset_manager;
ovl->set_overlay_info = &dss_ovl_set_info;
ovl->get_overlay_info = &dss_ovl_get_info;
ovl->wait_for_go = &dss_mgr_wait_for_go_ovl;
ovl->get_device = &dss_ovl_get_device;
}
r = dss_install_mgr_ops(&apply_mgr_ops);
if (r)
goto err_mgr_ops;
r = display_init_sysfs(pdev);
if (r)
goto err_disp_sysfs;
dispc_runtime_get();
r = dss_dispc_initialize_irq();
if (r)
goto err_init_irq;
dispc_runtime_put();
out:
mutex_unlock(&compat_init_lock);
return 0;
err_init_irq:
dispc_runtime_put();
display_uninit_sysfs(pdev);
err_disp_sysfs:
dss_uninstall_mgr_ops();
err_mgr_ops:
dss_uninit_overlay_managers_sysfs(pdev);
dss_uninit_overlays(pdev);
compat_refcnt--;
mutex_unlock(&compat_init_lock);
return r;
}
EXPORT_SYMBOL(omapdss_compat_init);
void omapdss_compat_uninit(void)
{
struct platform_device *pdev = dss_get_core_pdev();
mutex_lock(&compat_init_lock);
if (--compat_refcnt > 0)
goto out;
dss_dispc_uninitialize_irq();
display_uninit_sysfs(pdev);
dss_uninstall_mgr_ops();
dss_uninit_overlay_managers_sysfs(pdev);
dss_uninit_overlays(pdev);
out:
mutex_unlock(&compat_init_lock);
}
EXPORT_SYMBOL(omapdss_compat_uninit);
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/apply.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HDMI wrapper
*
* Copyright (C) 2013 Texas Instruments Incorporated
*/
#define DSS_SUBSYS_NAME "HDMIWP"
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "hdmi.h"
void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)
{
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))
DUMPREG(HDMI_WP_REVISION);
DUMPREG(HDMI_WP_SYSCONFIG);
DUMPREG(HDMI_WP_IRQSTATUS_RAW);
DUMPREG(HDMI_WP_IRQSTATUS);
DUMPREG(HDMI_WP_IRQENABLE_SET);
DUMPREG(HDMI_WP_IRQENABLE_CLR);
DUMPREG(HDMI_WP_IRQWAKEEN);
DUMPREG(HDMI_WP_PWR_CTRL);
DUMPREG(HDMI_WP_DEBOUNCE);
DUMPREG(HDMI_WP_VIDEO_CFG);
DUMPREG(HDMI_WP_VIDEO_SIZE);
DUMPREG(HDMI_WP_VIDEO_TIMING_H);
DUMPREG(HDMI_WP_VIDEO_TIMING_V);
DUMPREG(HDMI_WP_CLK);
DUMPREG(HDMI_WP_AUDIO_CFG);
DUMPREG(HDMI_WP_AUDIO_CFG2);
DUMPREG(HDMI_WP_AUDIO_CTRL);
DUMPREG(HDMI_WP_AUDIO_DATA);
}
u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)
{
return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
}
void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)
{
hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);
/* flush posted write */
hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);
}
void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)
{
hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);
}
void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)
{
hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);
}
/* PHY_PWR_CMD */
int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)
{
/* Return if already the state */
if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)
return 0;
/* Command for power control of HDMI PHY */
REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);
/* Status of the power control of HDMI PHY */
if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)
!= val) {
DSSERR("Failed to set PHY power mode to %d\n", val);
return -ETIMEDOUT;
}
return 0;
}
/* PLL_PWR_CMD */
int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)
{
/* Command for power control of HDMI PLL */
REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);
/* wait till PHY_PWR_STATUS is set */
if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)
!= val) {
DSSERR("Failed to set PLL_PWR_STATUS\n");
return -ETIMEDOUT;
}
return 0;
}
int hdmi_wp_video_start(struct hdmi_wp_data *wp)
{
REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);
return 0;
}
void hdmi_wp_video_stop(struct hdmi_wp_data *wp)
{
int i;
hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);
REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);
for (i = 0; i < 50; ++i) {
u32 v;
msleep(20);
v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);
if (v & HDMI_IRQ_VIDEO_FRAME_DONE)
return;
}
DSSERR("no HDMI FRAMEDONE when disabling output\n");
}
void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
struct hdmi_video_format *video_fmt)
{
u32 l = 0;
REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,
10, 8);
l |= FLD_VAL(video_fmt->y_res, 31, 16);
l |= FLD_VAL(video_fmt->x_res, 15, 0);
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);
}
void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
struct omap_video_timings *timings)
{
u32 r;
bool vsync_pol, hsync_pol;
DSSDBG("Enter hdmi_wp_video_config_interface\n");
vsync_pol = timings->vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
hsync_pol = timings->hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);
r = FLD_MOD(r, vsync_pol, 7, 7);
r = FLD_MOD(r, hsync_pol, 6, 6);
r = FLD_MOD(r, timings->interlace, 3, 3);
r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);
}
void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
struct omap_video_timings *timings)
{
u32 timing_h = 0;
u32 timing_v = 0;
DSSDBG("Enter hdmi_wp_video_config_timing\n");
timing_h |= FLD_VAL(timings->hbp, 31, 20);
timing_h |= FLD_VAL(timings->hfp, 19, 8);
timing_h |= FLD_VAL(timings->hsw, 7, 0);
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);
timing_v |= FLD_VAL(timings->vbp, 31, 20);
timing_v |= FLD_VAL(timings->vfp, 19, 8);
timing_v |= FLD_VAL(timings->vsw, 7, 0);
hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);
}
void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
struct omap_video_timings *timings, struct hdmi_config *param)
{
DSSDBG("Enter hdmi_wp_video_init_format\n");
video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
video_fmt->y_res = param->timings.y_res;
video_fmt->x_res = param->timings.x_res;
if (param->timings.interlace)
video_fmt->y_res /= 2;
timings->hbp = param->timings.hbp;
timings->hfp = param->timings.hfp;
timings->hsw = param->timings.hsw;
timings->vbp = param->timings.vbp;
timings->vfp = param->timings.vfp;
timings->vsw = param->timings.vsw;
timings->vsync_level = param->timings.vsync_level;
timings->hsync_level = param->timings.hsync_level;
timings->interlace = param->timings.interlace;
}
void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
struct hdmi_audio_format *aud_fmt)
{
u32 r;
DSSDBG("Enter hdmi_wp_audio_config_format\n");
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);
if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 ||
omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 ||
omapdss_get_version() == OMAPDSS_VER_OMAP4) {
r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
}
r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
r = FLD_MOD(r, aud_fmt->type, 4, 4);
r = FLD_MOD(r, aud_fmt->justification, 3, 3);
r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);
}
void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
struct hdmi_audio_dma *aud_dma)
{
u32 r;
DSSDBG("Enter hdmi_wp_audio_config_dma\n");
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);
r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
r = FLD_MOD(r, aud_dma->block_size, 7, 0);
hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);
r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);
r = FLD_MOD(r, aud_dma->mode, 9, 9);
r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);
}
int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)
{
REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);
return 0;
}
int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)
{
REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);
return 0;
}
int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)
{
struct resource *res;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");
if (!res) {
DSSERR("can't get WP mem resource\n");
return -EINVAL;
}
wp->phys_base = res->start;
wp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(wp->base)) {
DSSERR("can't ioremap HDMI WP\n");
return PTR_ERR(wp->base);
}
return 0;
}
phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)
{
return wp->phys_base + HDMI_WP_AUDIO_DATA;
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/hdmi_wp.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/dss.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "DSS"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/export.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/gfp.h>
#include <linux/sizes.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <linux/suspend.h>
#include <linux/component.h>
#include <linux/pinctrl/consumer.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
#define DSS_SZ_REGS SZ_512
struct dss_reg {
u16 idx;
};
#define DSS_REG(idx) ((const struct dss_reg) { idx })
#define DSS_REVISION DSS_REG(0x0000)
#define DSS_SYSCONFIG DSS_REG(0x0010)
#define DSS_SYSSTATUS DSS_REG(0x0014)
#define DSS_CONTROL DSS_REG(0x0040)
#define DSS_SDI_CONTROL DSS_REG(0x0044)
#define DSS_PLL_CONTROL DSS_REG(0x0048)
#define DSS_SDI_STATUS DSS_REG(0x005C)
#define REG_GET(idx, start, end) \
FLD_GET(dss_read_reg(idx), start, end)
#define REG_FLD_MOD(idx, val, start, end) \
dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
struct dss_features {
u8 fck_div_max;
u8 dss_fck_multiplier;
const char *parent_clk_name;
const enum omap_display_type *ports;
int num_ports;
int (*dpi_select_source)(int port, enum omap_channel channel);
};
static struct {
struct platform_device *pdev;
void __iomem *base;
struct regmap *syscon_pll_ctrl;
u32 syscon_pll_ctrl_offset;
struct clk *parent_clk;
struct clk *dss_clk;
unsigned long dss_clk_rate;
unsigned long cache_req_pck;
unsigned long cache_prate;
struct dispc_clock_info cache_dispc_cinfo;
enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
enum omap_dss_clk_source dispc_clk_source;
enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
bool ctx_valid;
u32 ctx[DSS_SZ_REGS / sizeof(u32)];
const struct dss_features *feat;
struct dss_pll *video1_pll;
struct dss_pll *video2_pll;
} dss;
static const char * const dss_generic_clk_source_names[] = {
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC",
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI",
[OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK",
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DSI_PLL2_HSDIV_DSI",
};
static bool dss_initialized;
bool omapdss_is_initialized(void)
{
return dss_initialized;
}
EXPORT_SYMBOL(omapdss_is_initialized);
static inline void dss_write_reg(const struct dss_reg idx, u32 val)
{
__raw_writel(val, dss.base + idx.idx);
}
static inline u32 dss_read_reg(const struct dss_reg idx)
{
return __raw_readl(dss.base + idx.idx);
}
#define SR(reg) \
dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
#define RR(reg) \
dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
static void dss_save_context(void)
{
DSSDBG("dss_save_context\n");
SR(CONTROL);
if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
OMAP_DISPLAY_TYPE_SDI) {
SR(SDI_CONTROL);
SR(PLL_CONTROL);
}
dss.ctx_valid = true;
DSSDBG("context saved\n");
}
static void dss_restore_context(void)
{
DSSDBG("dss_restore_context\n");
if (!dss.ctx_valid)
return;
RR(CONTROL);
if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
OMAP_DISPLAY_TYPE_SDI) {
RR(SDI_CONTROL);
RR(PLL_CONTROL);
}
DSSDBG("context restored\n");
}
#undef SR
#undef RR
void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
{
unsigned shift;
unsigned val;
if (!dss.syscon_pll_ctrl)
return;
val = !enable;
switch (pll_id) {
case DSS_PLL_VIDEO1:
shift = 0;
break;
case DSS_PLL_VIDEO2:
shift = 1;
break;
case DSS_PLL_HDMI:
shift = 2;
break;
default:
DSSERR("illegal DSS PLL ID %d\n", pll_id);
return;
}
regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
1 << shift, val << shift);
}
void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id,
enum omap_channel channel)
{
unsigned shift, val;
if (!dss.syscon_pll_ctrl)
return;
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
shift = 3;
switch (pll_id) {
case DSS_PLL_VIDEO1:
val = 0; break;
case DSS_PLL_HDMI:
val = 1; break;
default:
DSSERR("error in PLL mux config for LCD\n");
return;
}
break;
case OMAP_DSS_CHANNEL_LCD2:
shift = 5;
switch (pll_id) {
case DSS_PLL_VIDEO1:
val = 0; break;
case DSS_PLL_VIDEO2:
val = 1; break;
case DSS_PLL_HDMI:
val = 2; break;
default:
DSSERR("error in PLL mux config for LCD2\n");
return;
}
break;
case OMAP_DSS_CHANNEL_LCD3:
shift = 7;
switch (pll_id) {
case DSS_PLL_VIDEO1:
val = 1; break;
case DSS_PLL_VIDEO2:
val = 0; break;
case DSS_PLL_HDMI:
val = 2; break;
default:
DSSERR("error in PLL mux config for LCD3\n");
return;
}
break;
default:
DSSERR("error in PLL mux config\n");
return;
}
regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset,
0x3 << shift, val << shift);
}
void dss_sdi_init(int datapairs)
{
u32 l;
BUG_ON(datapairs > 3 || datapairs < 1);
l = dss_read_reg(DSS_SDI_CONTROL);
l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
dss_write_reg(DSS_SDI_CONTROL, l);
l = dss_read_reg(DSS_PLL_CONTROL);
l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
dss_write_reg(DSS_PLL_CONTROL, l);
}
int dss_sdi_enable(void)
{
unsigned long timeout;
dispc_pck_free_enable(1);
/* Reset SDI PLL */
REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
udelay(1); /* wait 2x PCLK */
/* Lock SDI PLL */
REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
/* Waiting for PLL lock request to complete */
timeout = jiffies + msecs_to_jiffies(500);
while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
if (time_after_eq(jiffies, timeout)) {
DSSERR("PLL lock request timed out\n");
goto err1;
}
}
/* Clearing PLL_GO bit */
REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
/* Waiting for PLL to lock */
timeout = jiffies + msecs_to_jiffies(500);
while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
if (time_after_eq(jiffies, timeout)) {
DSSERR("PLL lock timed out\n");
goto err1;
}
}
dispc_lcd_enable_signal(1);
/* Waiting for SDI reset to complete */
timeout = jiffies + msecs_to_jiffies(500);
while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
if (time_after_eq(jiffies, timeout)) {
DSSERR("SDI reset timed out\n");
goto err2;
}
}
return 0;
err2:
dispc_lcd_enable_signal(0);
err1:
/* Reset SDI PLL */
REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
dispc_pck_free_enable(0);
return -ETIMEDOUT;
}
void dss_sdi_disable(void)
{
dispc_lcd_enable_signal(0);
dispc_pck_free_enable(0);
/* Reset SDI PLL */
REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
}
const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
{
return dss_generic_clk_source_names[clk_src];
}
void dss_dump_clocks(struct seq_file *s)
{
const char *fclk_name, *fclk_real_name;
unsigned long fclk_rate;
if (dss_runtime_get())
return;
seq_printf(s, "- DSS -\n");
fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
fclk_rate = clk_get_rate(dss.dss_clk);
seq_printf(s, "%s (%s) = %lu\n",
fclk_name, fclk_real_name,
fclk_rate);
dss_runtime_put();
}
static void dss_dump_regs(struct seq_file *s)
{
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
if (dss_runtime_get())
return;
DUMPREG(DSS_REVISION);
DUMPREG(DSS_SYSCONFIG);
DUMPREG(DSS_SYSSTATUS);
DUMPREG(DSS_CONTROL);
if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
OMAP_DISPLAY_TYPE_SDI) {
DUMPREG(DSS_SDI_CONTROL);
DUMPREG(DSS_PLL_CONTROL);
DUMPREG(DSS_SDI_STATUS);
}
dss_runtime_put();
#undef DUMPREG
}
static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
{
int b;
u8 start, end;
switch (clk_src) {
case OMAP_DSS_CLK_SRC_FCK:
b = 0;
break;
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
b = 1;
break;
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
b = 2;
break;
default:
BUG();
return;
}
dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
dss.dispc_clk_source = clk_src;
}
void dss_select_dsi_clk_source(int dsi_module,
enum omap_dss_clk_source clk_src)
{
int b, pos;
switch (clk_src) {
case OMAP_DSS_CLK_SRC_FCK:
b = 0;
break;
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
BUG_ON(dsi_module != 0);
b = 1;
break;
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
BUG_ON(dsi_module != 1);
b = 1;
break;
default:
BUG();
return;
}
pos = dsi_module == 0 ? 1 : 10;
REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
dss.dsi_clk_source[dsi_module] = clk_src;
}
void dss_select_lcd_clk_source(enum omap_channel channel,
enum omap_dss_clk_source clk_src)
{
int b, ix, pos;
if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
dss_select_dispc_clk_source(clk_src);
return;
}
switch (clk_src) {
case OMAP_DSS_CLK_SRC_FCK:
b = 0;
break;
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
b = 1;
break;
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
channel != OMAP_DSS_CHANNEL_LCD3);
b = 1;
break;
default:
BUG();
return;
}
pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
(channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
(channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
dss.lcd_clk_source[ix] = clk_src;
}
enum omap_dss_clk_source dss_get_dispc_clk_source(void)
{
return dss.dispc_clk_source;
}
enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
{
return dss.dsi_clk_source[dsi_module];
}
enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
{
if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
(channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
return dss.lcd_clk_source[ix];
} else {
/* LCD_CLK source is the same as DISPC_FCLK source for
* OMAP2 and OMAP3 */
return dss.dispc_clk_source;
}
}
bool dss_div_calc(unsigned long pck, unsigned long fck_min,
dss_div_calc_func func, void *data)
{
int fckd, fckd_start, fckd_stop;
unsigned long fck;
unsigned long fck_hw_max;
unsigned long fckd_hw_max;
unsigned long prate;
unsigned m;
fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
if (dss.parent_clk == NULL) {
unsigned pckd;
pckd = fck_hw_max / pck;
fck = pck * pckd;
fck = clk_round_rate(dss.dss_clk, fck);
return func(fck, data);
}
fckd_hw_max = dss.feat->fck_div_max;
m = dss.feat->dss_fck_multiplier;
prate = clk_get_rate(dss.parent_clk);
fck_min = fck_min ? fck_min : 1;
fckd_start = min(prate * m / fck_min, fckd_hw_max);
fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
fck = DIV_ROUND_UP(prate, fckd) * m;
if (func(fck, data))
return true;
}
return false;
}
int dss_set_fck_rate(unsigned long rate)
{
int r;
DSSDBG("set fck to %lu\n", rate);
r = clk_set_rate(dss.dss_clk, rate);
if (r)
return r;
dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
WARN_ONCE(dss.dss_clk_rate != rate,
"clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
rate);
return 0;
}
unsigned long dss_get_dispc_clk_rate(void)
{
return dss.dss_clk_rate;
}
static int dss_setup_default_clock(void)
{
unsigned long max_dss_fck, prate;
unsigned long fck;
unsigned fck_div;
int r;
max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
if (dss.parent_clk == NULL) {
fck = clk_round_rate(dss.dss_clk, max_dss_fck);
} else {
prate = clk_get_rate(dss.parent_clk);
fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
max_dss_fck);
fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier;
}
r = dss_set_fck_rate(fck);
if (r)
return r;
return 0;
}
void dss_set_venc_output(enum omap_dss_venc_type type)
{
int l = 0;
if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
l = 0;
else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
l = 1;
else
BUG();
/* venc out selection. 0 = comp, 1 = svideo */
REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
}
void dss_set_dac_pwrdn_bgz(bool enable)
{
REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
}
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
{
enum omap_display_type dp;
dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
/* Complain about invalid selections */
WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
/* Select only if we have options */
if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */
}
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
{
enum omap_display_type displays;
displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
return DSS_VENC_TV_CLK;
if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
return DSS_HDMI_M_PCLK;
return REG_GET(DSS_CONTROL, 15, 15);
}
static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel)
{
if (channel != OMAP_DSS_CHANNEL_LCD)
return -EINVAL;
return 0;
}
static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
{
int val;
switch (channel) {
case OMAP_DSS_CHANNEL_LCD2:
val = 0;
break;
case OMAP_DSS_CHANNEL_DIGIT:
val = 1;
break;
default:
return -EINVAL;
}
REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
return 0;
}
static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
{
int val;
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
val = 1;
break;
case OMAP_DSS_CHANNEL_LCD2:
val = 2;
break;
case OMAP_DSS_CHANNEL_LCD3:
val = 3;
break;
case OMAP_DSS_CHANNEL_DIGIT:
val = 0;
break;
default:
return -EINVAL;
}
REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
return 0;
}
static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
{
switch (port) {
case 0:
return dss_dpi_select_source_omap5(port, channel);
case 1:
if (channel != OMAP_DSS_CHANNEL_LCD2)
return -EINVAL;
break;
case 2:
if (channel != OMAP_DSS_CHANNEL_LCD3)
return -EINVAL;
break;
default:
return -EINVAL;
}
return 0;
}
int dss_dpi_select_source(int port, enum omap_channel channel)
{
return dss.feat->dpi_select_source(port, channel);
}
static int dss_get_clocks(void)
{
struct clk *clk;
clk = devm_clk_get(&dss.pdev->dev, "fck");
if (IS_ERR(clk)) {
DSSERR("can't get clock fck\n");
return PTR_ERR(clk);
}
dss.dss_clk = clk;
if (dss.feat->parent_clk_name) {
clk = clk_get(NULL, dss.feat->parent_clk_name);
if (IS_ERR(clk)) {
DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
return PTR_ERR(clk);
}
} else {
clk = NULL;
}
dss.parent_clk = clk;
return 0;
}
static void dss_put_clocks(void)
{
if (dss.parent_clk)
clk_put(dss.parent_clk);
}
int dss_runtime_get(void)
{
int r;
DSSDBG("dss_runtime_get\n");
r = pm_runtime_resume_and_get(&dss.pdev->dev);
if (WARN_ON(r < 0))
return r;
return 0;
}
void dss_runtime_put(void)
{
int r;
DSSDBG("dss_runtime_put\n");
r = pm_runtime_put_sync(&dss.pdev->dev);
WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
}
/* DEBUGFS */
#if defined(CONFIG_FB_OMAP2_DSS_DEBUGFS)
void dss_debug_dump_clocks(struct seq_file *s)
{
dss_dump_clocks(s);
dispc_dump_clocks(s);
#ifdef CONFIG_FB_OMAP2_DSS_DSI
dsi_dump_clocks(s);
#endif
}
#endif
static const enum omap_display_type omap2plus_ports[] = {
OMAP_DISPLAY_TYPE_DPI,
};
static const enum omap_display_type omap34xx_ports[] = {
OMAP_DISPLAY_TYPE_DPI,
OMAP_DISPLAY_TYPE_SDI,
};
static const enum omap_display_type dra7xx_ports[] = {
OMAP_DISPLAY_TYPE_DPI,
OMAP_DISPLAY_TYPE_DPI,
OMAP_DISPLAY_TYPE_DPI,
};
static const struct dss_features omap24xx_dss_feats = {
/*
* fck div max is really 16, but the divider range has gaps. The range
* from 1 to 6 has no gaps, so let's use that as a max.
*/
.fck_div_max = 6,
.dss_fck_multiplier = 2,
.parent_clk_name = "core_ck",
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
};
static const struct dss_features omap34xx_dss_feats = {
.fck_div_max = 16,
.dss_fck_multiplier = 2,
.parent_clk_name = "dpll4_ck",
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
.ports = omap34xx_ports,
.num_ports = ARRAY_SIZE(omap34xx_ports),
};
static const struct dss_features omap3630_dss_feats = {
.fck_div_max = 31,
.dss_fck_multiplier = 1,
.parent_clk_name = "dpll4_ck",
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
};
static const struct dss_features omap44xx_dss_feats = {
.fck_div_max = 32,
.dss_fck_multiplier = 1,
.parent_clk_name = "dpll_per_x2_ck",
.dpi_select_source = &dss_dpi_select_source_omap4,
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
};
static const struct dss_features omap54xx_dss_feats = {
.fck_div_max = 64,
.dss_fck_multiplier = 1,
.parent_clk_name = "dpll_per_x2_ck",
.dpi_select_source = &dss_dpi_select_source_omap5,
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
};
static const struct dss_features am43xx_dss_feats = {
.fck_div_max = 0,
.dss_fck_multiplier = 0,
.parent_clk_name = NULL,
.dpi_select_source = &dss_dpi_select_source_omap2_omap3,
.ports = omap2plus_ports,
.num_ports = ARRAY_SIZE(omap2plus_ports),
};
static const struct dss_features dra7xx_dss_feats = {
.fck_div_max = 64,
.dss_fck_multiplier = 1,
.parent_clk_name = "dpll_per_x2_ck",
.dpi_select_source = &dss_dpi_select_source_dra7xx,
.ports = dra7xx_ports,
.num_ports = ARRAY_SIZE(dra7xx_ports),
};
static const struct dss_features *dss_get_features(void)
{
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP24xx:
return &omap24xx_dss_feats;
case OMAPDSS_VER_OMAP34xx_ES1:
case OMAPDSS_VER_OMAP34xx_ES3:
case OMAPDSS_VER_AM35xx:
return &omap34xx_dss_feats;
case OMAPDSS_VER_OMAP3630:
return &omap3630_dss_feats;
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
return &omap44xx_dss_feats;
case OMAPDSS_VER_OMAP5:
return &omap54xx_dss_feats;
case OMAPDSS_VER_AM43xx:
return &am43xx_dss_feats;
case OMAPDSS_VER_DRA7xx:
return &dra7xx_dss_feats;
default:
return NULL;
}
}
static void dss_uninit_ports(struct platform_device *pdev);
static int dss_init_ports(struct platform_device *pdev)
{
struct device_node *parent = pdev->dev.of_node;
struct device_node *port;
int r, ret = 0;
if (parent == NULL)
return 0;
port = omapdss_of_get_next_port(parent, NULL);
if (!port)
return 0;
if (dss.feat->num_ports == 0)
return 0;
do {
enum omap_display_type port_type;
u32 reg;
r = of_property_read_u32(port, "reg", ®);
if (r)
reg = 0;
if (reg >= dss.feat->num_ports)
continue;
port_type = dss.feat->ports[reg];
switch (port_type) {
case OMAP_DISPLAY_TYPE_DPI:
ret = dpi_init_port(pdev, port);
break;
case OMAP_DISPLAY_TYPE_SDI:
ret = sdi_init_port(pdev, port);
break;
default:
break;
}
} while (!ret &&
(port = omapdss_of_get_next_port(parent, port)) != NULL);
if (ret)
dss_uninit_ports(pdev);
return ret;
}
static void dss_uninit_ports(struct platform_device *pdev)
{
struct device_node *parent = pdev->dev.of_node;
struct device_node *port;
if (parent == NULL)
return;
port = omapdss_of_get_next_port(parent, NULL);
if (!port)
return;
if (dss.feat->num_ports == 0)
return;
do {
enum omap_display_type port_type;
u32 reg;
int r;
r = of_property_read_u32(port, "reg", ®);
if (r)
reg = 0;
if (reg >= dss.feat->num_ports)
continue;
port_type = dss.feat->ports[reg];
switch (port_type) {
case OMAP_DISPLAY_TYPE_DPI:
dpi_uninit_port(port);
break;
case OMAP_DISPLAY_TYPE_SDI:
sdi_uninit_port(port);
break;
default:
break;
}
} while ((port = omapdss_of_get_next_port(parent, port)) != NULL);
}
static int dss_video_pll_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct regulator *pll_regulator;
int r;
if (!np)
return 0;
if (of_property_read_bool(np, "syscon-pll-ctrl")) {
dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
"syscon-pll-ctrl");
if (IS_ERR(dss.syscon_pll_ctrl)) {
dev_err(&pdev->dev,
"failed to get syscon-pll-ctrl regmap\n");
return PTR_ERR(dss.syscon_pll_ctrl);
}
if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
&dss.syscon_pll_ctrl_offset)) {
dev_err(&pdev->dev,
"failed to get syscon-pll-ctrl offset\n");
return -EINVAL;
}
}
pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video");
if (IS_ERR(pll_regulator)) {
r = PTR_ERR(pll_regulator);
switch (r) {
case -ENOENT:
pll_regulator = NULL;
break;
case -EPROBE_DEFER:
return -EPROBE_DEFER;
default:
DSSERR("can't get DPLL VDDA regulator\n");
return r;
}
}
if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator);
if (IS_ERR(dss.video1_pll))
return PTR_ERR(dss.video1_pll);
}
if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator);
if (IS_ERR(dss.video2_pll)) {
dss_video_pll_uninit(dss.video1_pll);
return PTR_ERR(dss.video2_pll);
}
}
return 0;
}
/* DSS HW IP initialisation */
static int dss_bind(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct resource *dss_mem;
u32 rev;
int r;
dss.pdev = pdev;
dss.feat = dss_get_features();
if (!dss.feat)
return -ENODEV;
dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
if (!dss_mem) {
DSSERR("can't get IORESOURCE_MEM DSS\n");
return -EINVAL;
}
dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
resource_size(dss_mem));
if (!dss.base) {
DSSERR("can't ioremap DSS\n");
return -ENOMEM;
}
r = dss_get_clocks();
if (r)
return r;
r = dss_setup_default_clock();
if (r)
goto err_setup_clocks;
r = dss_video_pll_probe(pdev);
if (r)
goto err_pll_init;
r = dss_init_ports(pdev);
if (r)
goto err_init_ports;
pm_runtime_enable(&pdev->dev);
r = dss_runtime_get();
if (r)
goto err_runtime_get;
dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
/* Select DPLL */
REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
#ifdef CONFIG_FB_OMAP2_DSS_VENC
REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
#endif
dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
rev = dss_read_reg(DSS_REVISION);
printk(KERN_INFO "OMAP DSS rev %d.%d\n",
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
dss_runtime_put();
r = component_bind_all(&pdev->dev, NULL);
if (r)
goto err_component;
dss_debugfs_create_file("dss", dss_dump_regs);
pm_set_vt_switch(0);
dss_initialized = true;
return 0;
err_component:
err_runtime_get:
pm_runtime_disable(&pdev->dev);
dss_uninit_ports(pdev);
err_init_ports:
if (dss.video1_pll)
dss_video_pll_uninit(dss.video1_pll);
if (dss.video2_pll)
dss_video_pll_uninit(dss.video2_pll);
err_pll_init:
err_setup_clocks:
dss_put_clocks();
return r;
}
static void dss_unbind(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
dss_initialized = false;
component_unbind_all(&pdev->dev, NULL);
if (dss.video1_pll)
dss_video_pll_uninit(dss.video1_pll);
if (dss.video2_pll)
dss_video_pll_uninit(dss.video2_pll);
dss_uninit_ports(pdev);
pm_runtime_disable(&pdev->dev);
dss_put_clocks();
}
static const struct component_master_ops dss_component_ops = {
.bind = dss_bind,
.unbind = dss_unbind,
};
static int dss_add_child_component(struct device *dev, void *data)
{
struct component_match **match = data;
/*
* HACK
* We don't have a working driver for rfbi, so skip it here always.
* Otherwise dss will never get probed successfully, as it will wait
* for rfbi to get probed.
*/
if (strstr(dev_name(dev), "rfbi"))
return 0;
component_match_add(dev->parent, match, component_compare_dev, dev);
return 0;
}
static int dss_probe(struct platform_device *pdev)
{
struct component_match *match = NULL;
int r;
/* add all the child devices as components */
device_for_each_child(&pdev->dev, &match, dss_add_child_component);
r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
if (r)
return r;
return 0;
}
static void dss_remove(struct platform_device *pdev)
{
component_master_del(&pdev->dev, &dss_component_ops);
}
static int dss_runtime_suspend(struct device *dev)
{
dss_save_context();
dss_set_min_bus_tput(dev, 0);
pinctrl_pm_select_sleep_state(dev);
return 0;
}
static int dss_runtime_resume(struct device *dev)
{
int r;
pinctrl_pm_select_default_state(dev);
/*
* Set an arbitrarily high tput request to ensure OPP100.
* What we should really do is to make a request to stay in OPP100,
* without any tput requirements, but that is not currently possible
* via the PM layer.
*/
r = dss_set_min_bus_tput(dev, 1000000000);
if (r)
return r;
dss_restore_context();
return 0;
}
static const struct dev_pm_ops dss_pm_ops = {
.runtime_suspend = dss_runtime_suspend,
.runtime_resume = dss_runtime_resume,
};
static const struct of_device_id dss_of_match[] = {
{ .compatible = "ti,omap2-dss", },
{ .compatible = "ti,omap3-dss", },
{ .compatible = "ti,omap4-dss", },
{ .compatible = "ti,omap5-dss", },
{ .compatible = "ti,dra7-dss", },
{},
};
MODULE_DEVICE_TABLE(of, dss_of_match);
static struct platform_driver omap_dsshw_driver = {
.probe = dss_probe,
.remove_new = dss_remove,
.driver = {
.name = "omapdss_dss",
.pm = &dss_pm_ops,
.of_match_table = dss_of_match,
.suppress_bind_attrs = true,
},
};
int __init dss_init_platform_driver(void)
{
return platform_driver_register(&omap_dsshw_driver);
}
void dss_uninit_platform_driver(void)
{
platform_driver_unregister(&omap_dsshw_driver);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/dss.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HDMI PHY
*
* Copyright (C) 2013 Texas Instruments Incorporated
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/seq_file.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "hdmi.h"
struct hdmi_phy_features {
bool bist_ctrl;
bool ldo_voltage;
unsigned long max_phy;
};
static const struct hdmi_phy_features *phy_feat;
void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
{
#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
hdmi_read_reg(phy->base, r))
DUMPPHY(HDMI_TXPHY_TX_CTRL);
DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
DUMPPHY(HDMI_TXPHY_POWER_CTRL);
DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
if (phy_feat->bist_ctrl)
DUMPPHY(HDMI_TXPHY_BIST_CONTROL);
}
int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes)
{
int i;
for (i = 0; i < 8; i += 2) {
u8 lane, pol;
int dx, dy;
dx = lanes[i];
dy = lanes[i + 1];
if (dx < 0 || dx >= 8)
return -EINVAL;
if (dy < 0 || dy >= 8)
return -EINVAL;
if (dx & 1) {
if (dy != dx - 1)
return -EINVAL;
pol = 1;
} else {
if (dy != dx + 1)
return -EINVAL;
pol = 0;
}
lane = dx / 2;
phy->lane_function[lane] = i / 2;
phy->lane_polarity[lane] = pol;
}
return 0;
}
static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)
{
static const u16 pad_cfg_list[] = {
0x0123,
0x0132,
0x0312,
0x0321,
0x0231,
0x0213,
0x1023,
0x1032,
0x3012,
0x3021,
0x2031,
0x2013,
0x1203,
0x1302,
0x3102,
0x3201,
0x2301,
0x2103,
0x1230,
0x1320,
0x3120,
0x3210,
0x2310,
0x2130,
};
u16 lane_cfg = 0;
int i;
unsigned lane_cfg_val;
u16 pol_val = 0;
for (i = 0; i < 4; ++i)
lane_cfg |= phy->lane_function[i] << ((3 - i) * 4);
pol_val |= phy->lane_polarity[0] << 0;
pol_val |= phy->lane_polarity[1] << 3;
pol_val |= phy->lane_polarity[2] << 2;
pol_val |= phy->lane_polarity[3] << 1;
for (i = 0; i < ARRAY_SIZE(pad_cfg_list); ++i)
if (pad_cfg_list[i] == lane_cfg)
break;
if (WARN_ON(i == ARRAY_SIZE(pad_cfg_list)))
i = 0;
lane_cfg_val = i;
REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22);
REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);
}
int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
unsigned long lfbitclk)
{
u8 freqout;
/*
* Read address 0 in order to get the SCP reset done completed
* Dummy access performed to make sure reset is done
*/
hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
/*
* In OMAP5+, the HFBITCLK must be divided by 2 before issuing the
* HDMI_PHYPWRCMD_LDOON command.
*/
if (phy_feat->bist_ctrl)
REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
/*
* If the hfbitclk != lfbitclk, it means the lfbitclk was configured
* to be used for TMDS.
*/
if (hfbitclk != lfbitclk)
freqout = 0;
else if (hfbitclk / 10 < phy_feat->max_phy)
freqout = 1;
else
freqout = 2;
/*
* Write to phy address 0 to configure the clock
* use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
*/
REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30);
/* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
/* Setup max LDO voltage */
if (phy_feat->ldo_voltage)
REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
hdmi_phy_configure_lanes(phy);
return 0;
}
static const struct hdmi_phy_features omap44xx_phy_feats = {
.bist_ctrl = false,
.ldo_voltage = true,
.max_phy = 185675000,
};
static const struct hdmi_phy_features omap54xx_phy_feats = {
.bist_ctrl = true,
.ldo_voltage = false,
.max_phy = 186000000,
};
static const struct hdmi_phy_features *hdmi_phy_get_features(void)
{
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
return &omap44xx_phy_feats;
case OMAPDSS_VER_OMAP5:
case OMAPDSS_VER_DRA7xx:
return &omap54xx_phy_feats;
default:
return NULL;
}
}
int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)
{
phy_feat = hdmi_phy_get_features();
if (!phy_feat)
return -ENODEV;
phy->base = devm_platform_ioremap_resource_byname(pdev, "phy");
if (IS_ERR(phy->base)) {
DSSERR("can't ioremap TX PHY\n");
return PTR_ERR(phy->base);
}
return 0;
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Texas Instruments Ltd
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
struct dss_video_pll {
struct dss_pll pll;
struct device *dev;
void __iomem *clkctrl_base;
};
#define REG_MOD(reg, val, start, end) \
writel_relaxed(FLD_MOD(readl_relaxed(reg), val, start, end), reg)
static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll)
{
REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */
}
static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll)
{
REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */
}
static void dss_dpll_power_enable(struct dss_video_pll *vpll)
{
REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */
/*
* DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0,
* so we have to use fixed delay here.
*/
msleep(1);
}
static void dss_dpll_power_disable(struct dss_video_pll *vpll)
{
REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */
}
static int dss_video_pll_enable(struct dss_pll *pll)
{
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
int r;
r = dss_runtime_get();
if (r)
return r;
dss_ctrl_pll_enable(pll->id, true);
dss_dpll_enable_scp_clk(vpll);
r = dss_pll_wait_reset_done(pll);
if (r)
goto err_reset;
dss_dpll_power_enable(vpll);
return 0;
err_reset:
dss_dpll_disable_scp_clk(vpll);
dss_ctrl_pll_enable(pll->id, false);
dss_runtime_put();
return r;
}
static void dss_video_pll_disable(struct dss_pll *pll)
{
struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
dss_dpll_power_disable(vpll);
dss_dpll_disable_scp_clk(vpll);
dss_ctrl_pll_enable(pll->id, false);
dss_runtime_put();
}
static const struct dss_pll_ops dss_pll_ops = {
.enable = dss_video_pll_enable,
.disable = dss_video_pll_disable,
.set_config = dss_pll_write_config_type_a,
};
static const struct dss_pll_hw dss_dra7_video_pll_hw = {
.n_max = (1 << 8) - 1,
.m_max = (1 << 12) - 1,
.mX_max = (1 << 5) - 1,
.fint_min = 500000,
.fint_max = 2500000,
.clkdco_max = 1800000000,
.n_msb = 8,
.n_lsb = 1,
.m_msb = 20,
.m_lsb = 9,
.mX_msb[0] = 25,
.mX_lsb[0] = 21,
.mX_msb[1] = 30,
.mX_lsb[1] = 26,
.has_refsel = true,
};
struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
struct regulator *regulator)
{
const char * const reg_name[] = { "pll1", "pll2" };
const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
const char * const clkin_name[] = { "video1_clk", "video2_clk" };
struct dss_video_pll *vpll;
void __iomem *pll_base, *clkctrl_base;
struct clk *clk;
struct dss_pll *pll;
int r;
/* PLL CONTROL */
pll_base = devm_platform_ioremap_resource_byname(pdev, reg_name[id]);
if (IS_ERR(pll_base)) {
dev_err(&pdev->dev, "failed to ioremap pll%d reg_name\n", id);
return ERR_CAST(pll_base);
}
/* CLOCK CONTROL */
clkctrl_base = devm_platform_ioremap_resource_byname(pdev, clkctrl_name[id]);
if (IS_ERR(clkctrl_base)) {
dev_err(&pdev->dev, "failed to ioremap pll%d clkctrl\n", id);
return ERR_CAST(clkctrl_base);
}
/* CLKIN */
clk = devm_clk_get(&pdev->dev, clkin_name[id]);
if (IS_ERR(clk)) {
DSSERR("can't get video pll clkin\n");
return ERR_CAST(clk);
}
vpll = devm_kzalloc(&pdev->dev, sizeof(*vpll), GFP_KERNEL);
if (!vpll)
return ERR_PTR(-ENOMEM);
vpll->dev = &pdev->dev;
vpll->clkctrl_base = clkctrl_base;
pll = &vpll->pll;
pll->name = id == 0 ? "video0" : "video1";
pll->id = id == 0 ? DSS_PLL_VIDEO1 : DSS_PLL_VIDEO2;
pll->clkin = clk;
pll->regulator = regulator;
pll->base = pll_base;
pll->hw = &dss_dra7_video_pll_hw;
pll->ops = &dss_pll_ops;
r = dss_pll_register(pll);
if (r)
return ERR_PTR(r);
return pll;
}
void dss_video_pll_uninit(struct dss_pll *pll)
{
dss_pll_unregister(pll);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/video-pll.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
/*
* As omapdss panel drivers are omapdss specific, but we want to define the
* DT-data in generic manner, we convert the compatible strings of the panel and
* encoder nodes from "panel-foo" to "omapdss,panel-foo". This way we can have
* both correct DT data and omapdss specific drivers.
*
* When we get generic panel drivers to the kernel, this file will be removed.
*/
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_graph.h>
#include <linux/slab.h>
#include <linux/list.h>
static struct list_head dss_conv_list __initdata;
static const char prefix[] __initconst = "omapdss,";
struct dss_conv_node {
struct list_head list;
struct device_node *node;
bool root;
};
static int __init omapdss_count_strings(const struct property *prop)
{
const char *p = prop->value;
int l = 0, total = 0;
int i;
for (i = 0; total < prop->length; total += l, p += l, i++)
l = strlen(p) + 1;
return i;
}
static void __init omapdss_update_prop(struct device_node *node, char *compat,
int len)
{
struct property *prop;
prop = kzalloc(sizeof(*prop), GFP_KERNEL);
if (!prop)
return;
prop->name = "compatible";
prop->value = compat;
prop->length = len;
of_update_property(node, prop);
}
static void __init omapdss_prefix_strcpy(char *dst, int dst_len,
const char *src, int src_len)
{
size_t total = 0;
while (total < src_len) {
size_t l = strlen(src) + 1;
strcpy(dst, prefix);
dst += strlen(prefix);
strcpy(dst, src);
dst += l;
src += l;
total += l;
}
}
/* prepend compatible property strings with "omapdss," */
static void __init omapdss_omapify_node(struct device_node *node)
{
struct property *prop;
char *new_compat;
int num_strs;
int new_len;
prop = of_find_property(node, "compatible", NULL);
if (!prop || !prop->value)
return;
if (strnlen(prop->value, prop->length) >= prop->length)
return;
/* is it already prefixed? */
if (strncmp(prefix, prop->value, strlen(prefix)) == 0)
return;
num_strs = omapdss_count_strings(prop);
new_len = prop->length + strlen(prefix) * num_strs;
new_compat = kmalloc(new_len, GFP_KERNEL);
if (!new_compat)
return;
omapdss_prefix_strcpy(new_compat, new_len, prop->value, prop->length);
omapdss_update_prop(node, new_compat, new_len);
}
static void __init omapdss_add_to_list(struct device_node *node, bool root)
{
struct dss_conv_node *n = kmalloc(sizeof(struct dss_conv_node),
GFP_KERNEL);
if (n) {
n->node = node;
n->root = root;
list_add(&n->list, &dss_conv_list);
}
}
static bool __init omapdss_list_contains(const struct device_node *node)
{
struct dss_conv_node *n;
list_for_each_entry(n, &dss_conv_list, list) {
if (n->node == node)
return true;
}
return false;
}
static void __init omapdss_walk_device(struct device_node *node, bool root)
{
struct device_node *n;
omapdss_add_to_list(node, root);
/*
* of_graph_get_remote_port_parent() prints an error if there is no
* port/ports node. To avoid that, check first that there's the node.
*/
n = of_get_child_by_name(node, "ports");
if (!n)
n = of_get_child_by_name(node, "port");
if (!n)
return;
of_node_put(n);
n = NULL;
while ((n = of_graph_get_next_endpoint(node, n)) != NULL) {
struct device_node *pn;
pn = of_graph_get_remote_port_parent(n);
if (!pn)
continue;
if (!of_device_is_available(pn) || omapdss_list_contains(pn)) {
of_node_put(pn);
continue;
}
omapdss_walk_device(pn, false);
}
}
static const struct of_device_id omapdss_of_match[] __initconst = {
{ .compatible = "ti,omap2-dss", },
{ .compatible = "ti,omap3-dss", },
{ .compatible = "ti,omap4-dss", },
{ .compatible = "ti,omap5-dss", },
{ .compatible = "ti,dra7-dss", },
{},
};
static int __init omapdss_boot_init(void)
{
struct device_node *dss, *child;
INIT_LIST_HEAD(&dss_conv_list);
dss = of_find_matching_node(NULL, omapdss_of_match);
if (dss == NULL || !of_device_is_available(dss)) {
of_node_put(dss);
return 0;
}
omapdss_walk_device(dss, true);
for_each_available_child_of_node(dss, child) {
if (!of_property_present(child, "compatible"))
continue;
omapdss_walk_device(child, true);
}
while (!list_empty(&dss_conv_list)) {
struct dss_conv_node *n;
n = list_first_entry(&dss_conv_list, struct dss_conv_node,
list);
if (!n->root)
omapdss_omapify_node(n->node);
list_del(&n->list);
of_node_put(n->node);
kfree(n);
}
return 0;
}
subsys_initcall(omapdss_boot_init);
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/omapdss-boot-init.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/core.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "CORE"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/debugfs.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/regulator/consumer.h>
#include <linux/suspend.h>
#include <linux/slab.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
static struct {
struct platform_device *pdev;
const char *default_display_name;
} core;
static char *def_disp_name;
module_param_named(def_disp, def_disp_name, charp, 0);
MODULE_PARM_DESC(def_disp, "default display name");
const char *omapdss_get_default_display_name(void)
{
return core.default_display_name;
}
EXPORT_SYMBOL(omapdss_get_default_display_name);
enum omapdss_version omapdss_get_version(void)
{
struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
return pdata->version;
}
EXPORT_SYMBOL(omapdss_get_version);
struct platform_device *dss_get_core_pdev(void)
{
return core.pdev;
}
int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
struct omap_dss_board_info *board_data = core.pdev->dev.platform_data;
if (!board_data->dsi_enable_pads)
return -ENOENT;
return board_data->dsi_enable_pads(dsi_id, lane_mask);
}
void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
struct omap_dss_board_info *board_data = core.pdev->dev.platform_data;
if (!board_data->dsi_disable_pads)
return;
return board_data->dsi_disable_pads(dsi_id, lane_mask);
}
int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
if (pdata->set_min_bus_tput)
return pdata->set_min_bus_tput(dev, tput);
else
return 0;
}
#if defined(CONFIG_FB_OMAP2_DSS_DEBUGFS)
static int dss_show(struct seq_file *s, void *unused)
{
void (*func)(struct seq_file *) = s->private;
func(s);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(dss);
static struct dentry *dss_debugfs_dir;
static void dss_initialize_debugfs(void)
{
dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
&dss_debug_dump_clocks, &dss_fops);
}
static void dss_uninitialize_debugfs(void)
{
debugfs_remove_recursive(dss_debugfs_dir);
}
void dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *))
{
debugfs_create_file(name, S_IRUGO, dss_debugfs_dir, write, &dss_fops);
}
#else /* CONFIG_FB_OMAP2_DSS_DEBUGFS */
static inline void dss_initialize_debugfs(void)
{
}
static inline void dss_uninitialize_debugfs(void)
{
}
void dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *))
{
}
#endif /* CONFIG_FB_OMAP2_DSS_DEBUGFS */
/* PLATFORM DEVICE */
static int omap_dss_pm_notif(struct notifier_block *b, unsigned long v, void *d)
{
DSSDBG("pm notif %lu\n", v);
switch (v) {
case PM_SUSPEND_PREPARE:
case PM_HIBERNATION_PREPARE:
case PM_RESTORE_PREPARE:
DSSDBG("suspending displays\n");
return dss_suspend_all_devices();
case PM_POST_SUSPEND:
case PM_POST_HIBERNATION:
case PM_POST_RESTORE:
DSSDBG("resuming displays\n");
return dss_resume_all_devices();
default:
return 0;
}
}
static struct notifier_block omap_dss_pm_notif_block = {
.notifier_call = omap_dss_pm_notif,
};
static int __init omap_dss_probe(struct platform_device *pdev)
{
core.pdev = pdev;
dss_features_init(omapdss_get_version());
dss_initialize_debugfs();
if (def_disp_name)
core.default_display_name = def_disp_name;
register_pm_notifier(&omap_dss_pm_notif_block);
return 0;
}
static void omap_dss_remove(struct platform_device *pdev)
{
unregister_pm_notifier(&omap_dss_pm_notif_block);
dss_uninitialize_debugfs();
}
static void omap_dss_shutdown(struct platform_device *pdev)
{
DSSDBG("shutdown\n");
dss_disable_all_devices();
}
static struct platform_driver omap_dss_driver = {
.remove_new = omap_dss_remove,
.shutdown = omap_dss_shutdown,
.driver = {
.name = "omapdss",
},
};
/* INIT */
static int (*dss_output_drv_reg_funcs[])(void) __initdata = {
dss_init_platform_driver,
dispc_init_platform_driver,
#ifdef CONFIG_FB_OMAP2_DSS_DSI
dsi_init_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP2_DSS_DPI
dpi_init_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP2_DSS_SDI
sdi_init_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP2_DSS_VENC
venc_init_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP4_DSS_HDMI
hdmi4_init_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP5_DSS_HDMI
hdmi5_init_platform_driver,
#endif
};
static void (*dss_output_drv_unreg_funcs[])(void) = {
#ifdef CONFIG_FB_OMAP5_DSS_HDMI
hdmi5_uninit_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP4_DSS_HDMI
hdmi4_uninit_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP2_DSS_VENC
venc_uninit_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP2_DSS_SDI
sdi_uninit_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP2_DSS_DPI
dpi_uninit_platform_driver,
#endif
#ifdef CONFIG_FB_OMAP2_DSS_DSI
dsi_uninit_platform_driver,
#endif
dispc_uninit_platform_driver,
dss_uninit_platform_driver,
};
static int __init omap_dss_init(void)
{
int r;
int i;
r = platform_driver_probe(&omap_dss_driver, omap_dss_probe);
if (r)
return r;
for (i = 0; i < ARRAY_SIZE(dss_output_drv_reg_funcs); ++i) {
r = dss_output_drv_reg_funcs[i]();
if (r)
goto err_reg;
}
return 0;
err_reg:
for (i = ARRAY_SIZE(dss_output_drv_reg_funcs) - i;
i < ARRAY_SIZE(dss_output_drv_reg_funcs);
++i)
dss_output_drv_unreg_funcs[i]();
platform_driver_unregister(&omap_dss_driver);
return r;
}
static void __exit omap_dss_exit(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(dss_output_drv_unreg_funcs); ++i)
dss_output_drv_unreg_funcs[i]();
platform_driver_unregister(&omap_dss_driver);
}
module_init(omap_dss_init);
module_exit(omap_dss_exit);
MODULE_AUTHOR("Tomi Valkeinen <[email protected]>");
MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/dispc.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "DISPC"
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/vmalloc.h>
#include <linux/export.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/seq_file.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/hardirq.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/of.h>
#include <linux/component.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
#include "dispc.h"
/* DISPC */
#define DISPC_SZ_REGS SZ_4K
enum omap_burst_size {
BURST_SIZE_X2 = 0,
BURST_SIZE_X4 = 1,
BURST_SIZE_X8 = 2,
};
#define REG_GET(idx, start, end) \
FLD_GET(dispc_read_reg(idx), start, end)
#define REG_FLD_MOD(idx, val, start, end) \
dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
struct dispc_features {
u8 sw_start;
u8 fp_start;
u8 bp_start;
u16 sw_max;
u16 vp_max;
u16 hp_max;
u8 mgr_width_start;
u8 mgr_height_start;
u16 mgr_width_max;
u16 mgr_height_max;
unsigned long max_lcd_pclk;
unsigned long max_tv_pclk;
int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
unsigned long (*calc_core_clk) (unsigned long pclk,
u16 width, u16 height, u16 out_width, u16 out_height,
bool mem_to_mem);
u8 num_fifos;
/* swap GFX & WB fifos */
bool gfx_fifo_workaround:1;
/* no DISPC_IRQ_FRAMEDONETV on this SoC */
bool no_framedone_tv:1;
/* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
bool mstandby_workaround:1;
bool set_max_preload:1;
/* PIXEL_INC is not added to the last pixel of a line */
bool last_pixel_inc_missing:1;
/* POL_FREQ has ALIGN bit */
bool supports_sync_align:1;
bool has_writeback:1;
};
#define DISPC_MAX_NR_FIFOS 5
static struct {
struct platform_device *pdev;
void __iomem *base;
int irq;
irq_handler_t user_handler;
void *user_data;
unsigned long core_clk_rate;
unsigned long tv_pclk_rate;
u32 fifo_size[DISPC_MAX_NR_FIFOS];
/* maps which plane is using a fifo. fifo-id -> plane-id */
int fifo_assignment[DISPC_MAX_NR_FIFOS];
bool ctx_valid;
u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
const struct dispc_features *feat;
bool is_enabled;
struct regmap *syscon_pol;
u32 syscon_pol_offset;
/* DISPC_CONTROL & DISPC_CONFIG lock*/
spinlock_t control_lock;
} dispc;
enum omap_color_component {
/* used for all color formats for OMAP3 and earlier
* and for RGB and Y color component on OMAP4
*/
DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
/* used for UV component for
* OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
* color formats on OMAP4
*/
DISPC_COLOR_COMPONENT_UV = 1 << 1,
};
enum mgr_reg_fields {
DISPC_MGR_FLD_ENABLE,
DISPC_MGR_FLD_STNTFT,
DISPC_MGR_FLD_GO,
DISPC_MGR_FLD_TFTDATALINES,
DISPC_MGR_FLD_STALLMODE,
DISPC_MGR_FLD_TCKENABLE,
DISPC_MGR_FLD_TCKSELECTION,
DISPC_MGR_FLD_CPR,
DISPC_MGR_FLD_FIFOHANDCHECK,
/* used to maintain a count of the above fields */
DISPC_MGR_FLD_NUM,
};
struct dispc_reg_field {
u16 reg;
u8 high;
u8 low;
};
static const struct {
const char *name;
u32 vsync_irq;
u32 framedone_irq;
u32 sync_lost_irq;
struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
} mgr_desc[] = {
[OMAP_DSS_CHANNEL_LCD] = {
.name = "LCD",
.vsync_irq = DISPC_IRQ_VSYNC,
.framedone_irq = DISPC_IRQ_FRAMEDONE,
.sync_lost_irq = DISPC_IRQ_SYNC_LOST,
.reg_desc = {
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
},
},
[OMAP_DSS_CHANNEL_DIGIT] = {
.name = "DIGIT",
.vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
.framedone_irq = DISPC_IRQ_FRAMEDONETV,
.sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
.reg_desc = {
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
[DISPC_MGR_FLD_STNTFT] = { },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
[DISPC_MGR_FLD_TFTDATALINES] = { },
[DISPC_MGR_FLD_STALLMODE] = { },
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
[DISPC_MGR_FLD_CPR] = { },
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
},
},
[OMAP_DSS_CHANNEL_LCD2] = {
.name = "LCD2",
.vsync_irq = DISPC_IRQ_VSYNC2,
.framedone_irq = DISPC_IRQ_FRAMEDONE2,
.sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
.reg_desc = {
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
},
},
[OMAP_DSS_CHANNEL_LCD3] = {
.name = "LCD3",
.vsync_irq = DISPC_IRQ_VSYNC3,
.framedone_irq = DISPC_IRQ_FRAMEDONE3,
.sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
.reg_desc = {
[DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
[DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
[DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
[DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
[DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
[DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
[DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
[DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
[DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
},
},
};
struct color_conv_coef {
int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
int full_range;
};
static unsigned long dispc_fclk_rate(void);
static unsigned long dispc_core_clk_rate(void);
static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
static inline void dispc_write_reg(const u16 idx, u32 val)
{
__raw_writel(val, dispc.base + idx);
}
static inline u32 dispc_read_reg(const u16 idx)
{
return __raw_readl(dispc.base + idx);
}
static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
{
const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
return REG_GET(rfld.reg, rfld.high, rfld.low);
}
static void mgr_fld_write(enum omap_channel channel,
enum mgr_reg_fields regfld, int val) {
const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
unsigned long flags;
if (need_lock)
spin_lock_irqsave(&dispc.control_lock, flags);
REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
if (need_lock)
spin_unlock_irqrestore(&dispc.control_lock, flags);
}
#define SR(reg) \
dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
#define RR(reg) \
dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
static void dispc_save_context(void)
{
int i, j;
DSSDBG("dispc_save_context\n");
SR(IRQENABLE);
SR(CONTROL);
SR(CONFIG);
SR(LINE_NUMBER);
if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
SR(GLOBAL_ALPHA);
if (dss_has_feature(FEAT_MGR_LCD2)) {
SR(CONTROL2);
SR(CONFIG2);
}
if (dss_has_feature(FEAT_MGR_LCD3)) {
SR(CONTROL3);
SR(CONFIG3);
}
for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
SR(DEFAULT_COLOR(i));
SR(TRANS_COLOR(i));
SR(SIZE_MGR(i));
if (i == OMAP_DSS_CHANNEL_DIGIT)
continue;
SR(TIMING_H(i));
SR(TIMING_V(i));
SR(POL_FREQ(i));
SR(DIVISORo(i));
SR(DATA_CYCLE1(i));
SR(DATA_CYCLE2(i));
SR(DATA_CYCLE3(i));
if (dss_has_feature(FEAT_CPR)) {
SR(CPR_COEF_R(i));
SR(CPR_COEF_G(i));
SR(CPR_COEF_B(i));
}
}
for (i = 0; i < dss_feat_get_num_ovls(); i++) {
SR(OVL_BA0(i));
SR(OVL_BA1(i));
SR(OVL_POSITION(i));
SR(OVL_SIZE(i));
SR(OVL_ATTRIBUTES(i));
SR(OVL_FIFO_THRESHOLD(i));
SR(OVL_ROW_INC(i));
SR(OVL_PIXEL_INC(i));
if (dss_has_feature(FEAT_PRELOAD))
SR(OVL_PRELOAD(i));
if (i == OMAP_DSS_GFX) {
SR(OVL_WINDOW_SKIP(i));
SR(OVL_TABLE_BA(i));
continue;
}
SR(OVL_FIR(i));
SR(OVL_PICTURE_SIZE(i));
SR(OVL_ACCU0(i));
SR(OVL_ACCU1(i));
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_H(i, j));
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_HV(i, j));
for (j = 0; j < 5; j++)
SR(OVL_CONV_COEF(i, j));
if (dss_has_feature(FEAT_FIR_COEF_V)) {
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_V(i, j));
}
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
SR(OVL_BA0_UV(i));
SR(OVL_BA1_UV(i));
SR(OVL_FIR2(i));
SR(OVL_ACCU2_0(i));
SR(OVL_ACCU2_1(i));
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_H2(i, j));
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_HV2(i, j));
for (j = 0; j < 8; j++)
SR(OVL_FIR_COEF_V2(i, j));
}
if (dss_has_feature(FEAT_ATTR2))
SR(OVL_ATTRIBUTES2(i));
}
if (dss_has_feature(FEAT_CORE_CLK_DIV))
SR(DIVISOR);
dispc.ctx_valid = true;
DSSDBG("context saved\n");
}
static void dispc_restore_context(void)
{
int i, j;
DSSDBG("dispc_restore_context\n");
if (!dispc.ctx_valid)
return;
/*RR(IRQENABLE);*/
/*RR(CONTROL);*/
RR(CONFIG);
RR(LINE_NUMBER);
if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
RR(GLOBAL_ALPHA);
if (dss_has_feature(FEAT_MGR_LCD2))
RR(CONFIG2);
if (dss_has_feature(FEAT_MGR_LCD3))
RR(CONFIG3);
for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
RR(DEFAULT_COLOR(i));
RR(TRANS_COLOR(i));
RR(SIZE_MGR(i));
if (i == OMAP_DSS_CHANNEL_DIGIT)
continue;
RR(TIMING_H(i));
RR(TIMING_V(i));
RR(POL_FREQ(i));
RR(DIVISORo(i));
RR(DATA_CYCLE1(i));
RR(DATA_CYCLE2(i));
RR(DATA_CYCLE3(i));
if (dss_has_feature(FEAT_CPR)) {
RR(CPR_COEF_R(i));
RR(CPR_COEF_G(i));
RR(CPR_COEF_B(i));
}
}
for (i = 0; i < dss_feat_get_num_ovls(); i++) {
RR(OVL_BA0(i));
RR(OVL_BA1(i));
RR(OVL_POSITION(i));
RR(OVL_SIZE(i));
RR(OVL_ATTRIBUTES(i));
RR(OVL_FIFO_THRESHOLD(i));
RR(OVL_ROW_INC(i));
RR(OVL_PIXEL_INC(i));
if (dss_has_feature(FEAT_PRELOAD))
RR(OVL_PRELOAD(i));
if (i == OMAP_DSS_GFX) {
RR(OVL_WINDOW_SKIP(i));
RR(OVL_TABLE_BA(i));
continue;
}
RR(OVL_FIR(i));
RR(OVL_PICTURE_SIZE(i));
RR(OVL_ACCU0(i));
RR(OVL_ACCU1(i));
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_H(i, j));
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_HV(i, j));
for (j = 0; j < 5; j++)
RR(OVL_CONV_COEF(i, j));
if (dss_has_feature(FEAT_FIR_COEF_V)) {
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_V(i, j));
}
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
RR(OVL_BA0_UV(i));
RR(OVL_BA1_UV(i));
RR(OVL_FIR2(i));
RR(OVL_ACCU2_0(i));
RR(OVL_ACCU2_1(i));
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_H2(i, j));
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_HV2(i, j));
for (j = 0; j < 8; j++)
RR(OVL_FIR_COEF_V2(i, j));
}
if (dss_has_feature(FEAT_ATTR2))
RR(OVL_ATTRIBUTES2(i));
}
if (dss_has_feature(FEAT_CORE_CLK_DIV))
RR(DIVISOR);
/* enable last, because LCD & DIGIT enable are here */
RR(CONTROL);
if (dss_has_feature(FEAT_MGR_LCD2))
RR(CONTROL2);
if (dss_has_feature(FEAT_MGR_LCD3))
RR(CONTROL3);
/* clear spurious SYNC_LOST_DIGIT interrupts */
dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
/*
* enable last so IRQs won't trigger before
* the context is fully restored
*/
RR(IRQENABLE);
DSSDBG("context restored\n");
}
#undef SR
#undef RR
int dispc_runtime_get(void)
{
int r;
DSSDBG("dispc_runtime_get\n");
r = pm_runtime_resume_and_get(&dispc.pdev->dev);
if (WARN_ON(r < 0))
return r;
return 0;
}
EXPORT_SYMBOL(dispc_runtime_get);
void dispc_runtime_put(void)
{
int r;
DSSDBG("dispc_runtime_put\n");
r = pm_runtime_put_sync(&dispc.pdev->dev);
WARN_ON(r < 0 && r != -ENOSYS);
}
EXPORT_SYMBOL(dispc_runtime_put);
u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
{
return mgr_desc[channel].vsync_irq;
}
EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
{
if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
return 0;
return mgr_desc[channel].framedone_irq;
}
EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
{
return mgr_desc[channel].sync_lost_irq;
}
EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
bool dispc_mgr_go_busy(enum omap_channel channel)
{
return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
}
EXPORT_SYMBOL(dispc_mgr_go_busy);
void dispc_mgr_go(enum omap_channel channel)
{
WARN_ON(!dispc_mgr_is_enabled(channel));
WARN_ON(dispc_mgr_go_busy(channel));
DSSDBG("GO %s\n", mgr_desc[channel].name);
mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
}
EXPORT_SYMBOL(dispc_mgr_go);
static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
{
dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
}
static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
{
dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
}
static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
{
dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
}
static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);
dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
}
static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);
dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
}
static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
{
BUG_ON(plane == OMAP_DSS_GFX);
dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
}
static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
int fir_vinc, int five_taps,
enum omap_color_component color_comp)
{
const struct dispc_coef *h_coef, *v_coef;
int i;
h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
for (i = 0; i < 8; i++) {
u32 h, hv;
h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
| FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
| FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
| FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
| FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
| FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
| FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
dispc_ovl_write_firh_reg(plane, i, h);
dispc_ovl_write_firhv_reg(plane, i, hv);
} else {
dispc_ovl_write_firh2_reg(plane, i, h);
dispc_ovl_write_firhv2_reg(plane, i, hv);
}
}
if (five_taps) {
for (i = 0; i < 8; i++) {
u32 v;
v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
| FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
dispc_ovl_write_firv_reg(plane, i, v);
else
dispc_ovl_write_firv2_reg(plane, i, v);
}
}
}
static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
const struct color_conv_coef *ct)
{
#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
#undef CVAL
}
static void dispc_setup_color_conv_coef(void)
{
int i;
int num_ovl = dss_feat_get_num_ovls();
const struct color_conv_coef ctbl_bt601_5_ovl = {
/* YUV -> RGB */
298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
};
const struct color_conv_coef ctbl_bt601_5_wb = {
/* RGB -> YUV */
66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
};
for (i = 1; i < num_ovl; i++)
dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
if (dispc.feat->has_writeback)
dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
}
static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
{
dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
}
static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
{
dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
}
static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
{
dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
}
static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
{
dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
}
static void dispc_ovl_set_pos(enum omap_plane plane,
enum omap_overlay_caps caps, int x, int y)
{
u32 val;
if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
return;
val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
dispc_write_reg(DISPC_OVL_POSITION(plane), val);
}
static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
int height)
{
u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
dispc_write_reg(DISPC_OVL_SIZE(plane), val);
else
dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
}
static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
int height)
{
u32 val;
BUG_ON(plane == OMAP_DSS_GFX);
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
if (plane == OMAP_DSS_WB)
dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
else
dispc_write_reg(DISPC_OVL_SIZE(plane), val);
}
static void dispc_ovl_set_zorder(enum omap_plane plane,
enum omap_overlay_caps caps, u8 zorder)
{
if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
return;
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
}
static void dispc_ovl_enable_zorder_planes(void)
{
int i;
if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
return;
for (i = 0; i < dss_feat_get_num_ovls(); i++)
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
}
static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
enum omap_overlay_caps caps, bool enable)
{
if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
return;
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
}
static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
enum omap_overlay_caps caps, u8 global_alpha)
{
static const unsigned shifts[] = { 0, 8, 16, 24, };
int shift;
if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
return;
shift = shifts[plane];
REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
}
static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
{
dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
}
static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
{
dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
}
static void dispc_ovl_set_color_mode(enum omap_plane plane,
enum omap_color_mode color_mode)
{
u32 m = 0;
if (plane != OMAP_DSS_GFX) {
switch (color_mode) {
case OMAP_DSS_COLOR_NV12:
m = 0x0; break;
case OMAP_DSS_COLOR_RGBX16:
m = 0x1; break;
case OMAP_DSS_COLOR_RGBA16:
m = 0x2; break;
case OMAP_DSS_COLOR_RGB12U:
m = 0x4; break;
case OMAP_DSS_COLOR_ARGB16:
m = 0x5; break;
case OMAP_DSS_COLOR_RGB16:
m = 0x6; break;
case OMAP_DSS_COLOR_ARGB16_1555:
m = 0x7; break;
case OMAP_DSS_COLOR_RGB24U:
m = 0x8; break;
case OMAP_DSS_COLOR_RGB24P:
m = 0x9; break;
case OMAP_DSS_COLOR_YUV2:
m = 0xa; break;
case OMAP_DSS_COLOR_UYVY:
m = 0xb; break;
case OMAP_DSS_COLOR_ARGB32:
m = 0xc; break;
case OMAP_DSS_COLOR_RGBA32:
m = 0xd; break;
case OMAP_DSS_COLOR_RGBX32:
m = 0xe; break;
case OMAP_DSS_COLOR_XRGB16_1555:
m = 0xf; break;
default:
BUG(); return;
}
} else {
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
m = 0x0; break;
case OMAP_DSS_COLOR_CLUT2:
m = 0x1; break;
case OMAP_DSS_COLOR_CLUT4:
m = 0x2; break;
case OMAP_DSS_COLOR_CLUT8:
m = 0x3; break;
case OMAP_DSS_COLOR_RGB12U:
m = 0x4; break;
case OMAP_DSS_COLOR_ARGB16:
m = 0x5; break;
case OMAP_DSS_COLOR_RGB16:
m = 0x6; break;
case OMAP_DSS_COLOR_ARGB16_1555:
m = 0x7; break;
case OMAP_DSS_COLOR_RGB24U:
m = 0x8; break;
case OMAP_DSS_COLOR_RGB24P:
m = 0x9; break;
case OMAP_DSS_COLOR_RGBX16:
m = 0xa; break;
case OMAP_DSS_COLOR_RGBA16:
m = 0xb; break;
case OMAP_DSS_COLOR_ARGB32:
m = 0xc; break;
case OMAP_DSS_COLOR_RGBA32:
m = 0xd; break;
case OMAP_DSS_COLOR_RGBX32:
m = 0xe; break;
case OMAP_DSS_COLOR_XRGB16_1555:
m = 0xf; break;
default:
BUG(); return;
}
}
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
}
static void dispc_ovl_configure_burst_type(enum omap_plane plane,
enum omap_dss_rotation_type rotation_type)
{
if (!dss_has_feature(FEAT_BURST_2D))
return;
if (rotation_type == OMAP_DSS_ROT_TILER)
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
else
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
}
void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
{
int shift;
u32 val;
int chan = 0, chan2 = 0;
switch (plane) {
case OMAP_DSS_GFX:
shift = 8;
break;
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
case OMAP_DSS_VIDEO3:
shift = 16;
break;
default:
BUG();
return;
}
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
if (dss_has_feature(FEAT_MGR_LCD2)) {
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
chan = 0;
chan2 = 0;
break;
case OMAP_DSS_CHANNEL_DIGIT:
chan = 1;
chan2 = 0;
break;
case OMAP_DSS_CHANNEL_LCD2:
chan = 0;
chan2 = 1;
break;
case OMAP_DSS_CHANNEL_LCD3:
if (dss_has_feature(FEAT_MGR_LCD3)) {
chan = 0;
chan2 = 2;
} else {
BUG();
return;
}
break;
case OMAP_DSS_CHANNEL_WB:
chan = 0;
chan2 = 3;
break;
default:
BUG();
return;
}
val = FLD_MOD(val, chan, shift, shift);
val = FLD_MOD(val, chan2, 31, 30);
} else {
val = FLD_MOD(val, channel, shift, shift);
}
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
}
EXPORT_SYMBOL(dispc_ovl_set_channel_out);
static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
{
int shift;
u32 val;
switch (plane) {
case OMAP_DSS_GFX:
shift = 8;
break;
case OMAP_DSS_VIDEO1:
case OMAP_DSS_VIDEO2:
case OMAP_DSS_VIDEO3:
shift = 16;
break;
default:
BUG();
return 0;
}
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
if (FLD_GET(val, shift, shift) == 1)
return OMAP_DSS_CHANNEL_DIGIT;
if (!dss_has_feature(FEAT_MGR_LCD2))
return OMAP_DSS_CHANNEL_LCD;
switch (FLD_GET(val, 31, 30)) {
case 0:
default:
return OMAP_DSS_CHANNEL_LCD;
case 1:
return OMAP_DSS_CHANNEL_LCD2;
case 2:
return OMAP_DSS_CHANNEL_LCD3;
case 3:
return OMAP_DSS_CHANNEL_WB;
}
}
static void dispc_ovl_set_burst_size(enum omap_plane plane,
enum omap_burst_size burst_size)
{
static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
int shift;
shift = shifts[plane];
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
}
static void dispc_configure_burst_sizes(void)
{
int i;
const int burst_size = BURST_SIZE_X8;
/* Configure burst size always to maximum size */
for (i = 0; i < dss_feat_get_num_ovls(); ++i)
dispc_ovl_set_burst_size(i, burst_size);
if (dispc.feat->has_writeback)
dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
}
static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
{
unsigned unit = dss_feat_get_burst_size_unit();
/* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
return unit * 8;
}
void dispc_enable_gamma_table(bool enable)
{
/*
* This is partially implemented to support only disabling of
* the gamma table.
*/
if (enable) {
DSSWARN("Gamma table enabling for TV not yet supported");
return;
}
REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
}
static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
{
if (channel == OMAP_DSS_CHANNEL_DIGIT)
return;
mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
}
static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
const struct omap_dss_cpr_coefs *coefs)
{
u32 coef_r, coef_g, coef_b;
if (!dss_mgr_is_lcd(channel))
return;
coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
FLD_VAL(coefs->rb, 9, 0);
coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
FLD_VAL(coefs->gb, 9, 0);
coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
FLD_VAL(coefs->bb, 9, 0);
dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
}
static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
{
u32 val;
BUG_ON(plane == OMAP_DSS_GFX);
val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
val = FLD_MOD(val, enable, 9, 9);
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
}
static void dispc_ovl_enable_replication(enum omap_plane plane,
enum omap_overlay_caps caps, bool enable)
{
static const unsigned shifts[] = { 5, 10, 10, 10 };
int shift;
if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
return;
shift = shifts[plane];
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
}
static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
u16 height)
{
u32 val;
val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
dispc_write_reg(DISPC_SIZE_MGR(channel), val);
}
static void dispc_init_fifos(void)
{
u32 size;
int fifo;
u8 start, end;
u32 unit;
int i;
unit = dss_feat_get_buffer_size_unit();
dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
size *= unit;
dispc.fifo_size[fifo] = size;
/*
* By default fifos are mapped directly to overlays, fifo 0 to
* ovl 0, fifo 1 to ovl 1, etc.
*/
dispc.fifo_assignment[fifo] = fifo;
}
/*
* The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
* causes problems with certain use cases, like using the tiler in 2D
* mode. The below hack swaps the fifos of GFX and WB planes, thus
* giving GFX plane a larger fifo. WB but should work fine with a
* smaller fifo.
*/
if (dispc.feat->gfx_fifo_workaround) {
u32 v;
v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
}
/*
* Setup default fifo thresholds.
*/
for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
u32 low, high;
const bool use_fifomerge = false;
const bool manual_update = false;
dispc_ovl_compute_fifo_thresholds(i, &low, &high,
use_fifomerge, manual_update);
dispc_ovl_set_fifo_threshold(i, low, high);
}
if (dispc.feat->has_writeback) {
u32 low, high;
const bool use_fifomerge = false;
const bool manual_update = false;
dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
use_fifomerge, manual_update);
dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
}
}
static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
{
int fifo;
u32 size = 0;
for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
if (dispc.fifo_assignment[fifo] == plane)
size += dispc.fifo_size[fifo];
}
return size;
}
void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
{
u8 hi_start, hi_end, lo_start, lo_end;
u32 unit;
unit = dss_feat_get_buffer_size_unit();
WARN_ON(low % unit != 0);
WARN_ON(high % unit != 0);
low /= unit;
high /= unit;
dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
plane,
REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
lo_start, lo_end) * unit,
REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
hi_start, hi_end) * unit,
low * unit, high * unit);
dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
FLD_VAL(high, hi_start, hi_end) |
FLD_VAL(low, lo_start, lo_end));
/*
* configure the preload to the pipeline's high threhold, if HT it's too
* large for the preload field, set the threshold to the maximum value
* that can be held by the preload register
*/
if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
plane != OMAP_DSS_WB)
dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
}
void dispc_enable_fifomerge(bool enable)
{
if (!dss_has_feature(FEAT_FIFO_MERGE)) {
WARN_ON(enable);
return;
}
DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
}
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
bool manual_update)
{
/*
* All sizes are in bytes. Both the buffer and burst are made of
* buffer_units, and the fifo thresholds must be buffer_unit aligned.
*/
unsigned buf_unit = dss_feat_get_buffer_size_unit();
unsigned ovl_fifo_size, total_fifo_size, burst_size;
int i;
burst_size = dispc_ovl_get_burst_size(plane);
ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
if (use_fifomerge) {
total_fifo_size = 0;
for (i = 0; i < dss_feat_get_num_ovls(); ++i)
total_fifo_size += dispc_ovl_get_fifo_size(i);
} else {
total_fifo_size = ovl_fifo_size;
}
/*
* We use the same low threshold for both fifomerge and non-fifomerge
* cases, but for fifomerge we calculate the high threshold using the
* combined fifo size
*/
if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
*fifo_low = ovl_fifo_size - burst_size * 2;
*fifo_high = total_fifo_size - burst_size;
} else if (plane == OMAP_DSS_WB) {
/*
* Most optimal configuration for writeback is to push out data
* to the interconnect the moment writeback pushes enough pixels
* in the FIFO to form a burst
*/
*fifo_low = 0;
*fifo_high = burst_size;
} else {
*fifo_low = ovl_fifo_size - burst_size;
*fifo_high = total_fifo_size - buf_unit;
}
}
static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
{
int bit;
if (plane == OMAP_DSS_GFX)
bit = 14;
else
bit = 23;
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
}
static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
int low, int high)
{
dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
}
static void dispc_init_mflag(void)
{
int i;
/*
* HACK: NV12 color format and MFLAG seem to have problems working
* together: using two displays, and having an NV12 overlay on one of
* the displays will cause underflows/synclosts when MFLAG_CTRL=2.
* Changing MFLAG thresholds and PRELOAD to certain values seem to
* remove the errors, but there doesn't seem to be a clear logic on
* which values work and which not.
*
* As a work-around, set force MFLAG to always on.
*/
dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
(1 << 0) | /* MFLAG_CTRL = force always on */
(0 << 2)); /* MFLAG_START = disable */
for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
u32 size = dispc_ovl_get_fifo_size(i);
u32 unit = dss_feat_get_buffer_size_unit();
u32 low, high;
dispc_ovl_set_mflag(i, true);
/*
* Simulation team suggests below thesholds:
* HT = fifosize * 5 / 8;
* LT = fifosize * 4 / 8;
*/
low = size * 4 / 8 / unit;
high = size * 5 / 8 / unit;
dispc_ovl_set_mflag_threshold(i, low, high);
}
if (dispc.feat->has_writeback) {
u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
u32 unit = dss_feat_get_buffer_size_unit();
u32 low, high;
dispc_ovl_set_mflag(OMAP_DSS_WB, true);
/*
* Simulation team suggests below thesholds:
* HT = fifosize * 5 / 8;
* LT = fifosize * 4 / 8;
*/
low = size * 4 / 8 / unit;
high = size * 5 / 8 / unit;
dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
}
}
static void dispc_ovl_set_fir(enum omap_plane plane,
int hinc, int vinc,
enum omap_color_component color_comp)
{
u32 val;
if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
u8 hinc_start, hinc_end, vinc_start, vinc_end;
dss_feat_get_reg_field(FEAT_REG_FIRHINC,
&hinc_start, &hinc_end);
dss_feat_get_reg_field(FEAT_REG_FIRVINC,
&vinc_start, &vinc_end);
val = FLD_VAL(vinc, vinc_start, vinc_end) |
FLD_VAL(hinc, hinc_start, hinc_end);
dispc_write_reg(DISPC_OVL_FIR(plane), val);
} else {
val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
dispc_write_reg(DISPC_OVL_FIR2(plane), val);
}
}
static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
{
u32 val;
u8 hor_start, hor_end, vert_start, vert_end;
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
val = FLD_VAL(vaccu, vert_start, vert_end) |
FLD_VAL(haccu, hor_start, hor_end);
dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
}
static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
{
u32 val;
u8 hor_start, hor_end, vert_start, vert_end;
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
val = FLD_VAL(vaccu, vert_start, vert_end) |
FLD_VAL(haccu, hor_start, hor_end);
dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
}
static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
int vaccu)
{
u32 val;
val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
}
static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
int vaccu)
{
u32 val;
val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
}
static void dispc_ovl_set_scale_param(enum omap_plane plane,
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
bool five_taps, u8 rotation,
enum omap_color_component color_comp)
{
int fir_hinc, fir_vinc;
fir_hinc = 1024 * orig_width / out_width;
fir_vinc = 1024 * orig_height / out_height;
dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
color_comp);
dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
}
static void dispc_ovl_set_accu_uv(enum omap_plane plane,
u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
bool ilace, enum omap_color_mode color_mode, u8 rotation)
{
int h_accu2_0, h_accu2_1;
int v_accu2_0, v_accu2_1;
int chroma_hinc, chroma_vinc;
int idx;
struct accu {
s8 h0_m, h0_n;
s8 h1_m, h1_n;
s8 v0_m, v0_n;
s8 v1_m, v1_n;
};
const struct accu *accu_table;
const struct accu *accu_val;
static const struct accu accu_nv12[4] = {
{ 0, 1, 0, 1 , -1, 2, 0, 1 },
{ 1, 2, -3, 4 , 0, 1, 0, 1 },
{ -1, 1, 0, 1 , -1, 2, 0, 1 },
{ -1, 2, -1, 2 , -1, 1, 0, 1 },
};
static const struct accu accu_nv12_ilace[4] = {
{ 0, 1, 0, 1 , -3, 4, -1, 4 },
{ -1, 4, -3, 4 , 0, 1, 0, 1 },
{ -1, 1, 0, 1 , -1, 4, -3, 4 },
{ -3, 4, -3, 4 , -1, 1, 0, 1 },
};
static const struct accu accu_yuv[4] = {
{ 0, 1, 0, 1, 0, 1, 0, 1 },
{ 0, 1, 0, 1, 0, 1, 0, 1 },
{ -1, 1, 0, 1, 0, 1, 0, 1 },
{ 0, 1, 0, 1, -1, 1, 0, 1 },
};
switch (rotation) {
case OMAP_DSS_ROT_0:
idx = 0;
break;
case OMAP_DSS_ROT_90:
idx = 1;
break;
case OMAP_DSS_ROT_180:
idx = 2;
break;
case OMAP_DSS_ROT_270:
idx = 3;
break;
default:
BUG();
return;
}
switch (color_mode) {
case OMAP_DSS_COLOR_NV12:
if (ilace)
accu_table = accu_nv12_ilace;
else
accu_table = accu_nv12;
break;
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
accu_table = accu_yuv;
break;
default:
BUG();
return;
}
accu_val = &accu_table[idx];
chroma_hinc = 1024 * orig_width / out_width;
chroma_vinc = 1024 * orig_height / out_height;
h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
}
static void dispc_ovl_set_scaling_common(enum omap_plane plane,
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
bool ilace, bool five_taps,
bool fieldmode, enum omap_color_mode color_mode,
u8 rotation)
{
int accu0 = 0;
int accu1 = 0;
u32 l;
dispc_ovl_set_scale_param(plane, orig_width, orig_height,
out_width, out_height, five_taps,
rotation, DISPC_COLOR_COMPONENT_RGB_Y);
l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
/* RESIZEENABLE and VERTICALTAPS */
l &= ~((0x3 << 5) | (0x1 << 21));
l |= (orig_width != out_width) ? (1 << 5) : 0;
l |= (orig_height != out_height) ? (1 << 6) : 0;
l |= five_taps ? (1 << 21) : 0;
/* VRESIZECONF and HRESIZECONF */
if (dss_has_feature(FEAT_RESIZECONF)) {
l &= ~(0x3 << 7);
l |= (orig_width <= out_width) ? 0 : (1 << 7);
l |= (orig_height <= out_height) ? 0 : (1 << 8);
}
/* LINEBUFFERSPLIT */
if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
l &= ~(0x1 << 22);
l |= five_taps ? (1 << 22) : 0;
}
dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
*/
if (ilace && !fieldmode) {
accu1 = 0;
accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
if (accu0 >= 1024/2) {
accu1 = 1024/2;
accu0 -= accu1;
}
}
dispc_ovl_set_vid_accu0(plane, 0, accu0);
dispc_ovl_set_vid_accu1(plane, 0, accu1);
}
static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
bool ilace, bool five_taps,
bool fieldmode, enum omap_color_mode color_mode,
u8 rotation)
{
int scale_x = out_width != orig_width;
int scale_y = out_height != orig_height;
bool chroma_upscale = plane != OMAP_DSS_WB;
if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
return;
if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
color_mode != OMAP_DSS_COLOR_UYVY &&
color_mode != OMAP_DSS_COLOR_NV12)) {
/* reset chroma resampling for RGB formats */
if (plane != OMAP_DSS_WB)
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
return;
}
dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
out_height, ilace, color_mode, rotation);
switch (color_mode) {
case OMAP_DSS_COLOR_NV12:
if (chroma_upscale) {
/* UV is subsampled by 2 horizontally and vertically */
orig_height >>= 1;
orig_width >>= 1;
} else {
/* UV is downsampled by 2 horizontally and vertically */
orig_height <<= 1;
orig_width <<= 1;
}
break;
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
/* For YUV422 with 90/270 rotation, we don't upsample chroma */
if (rotation == OMAP_DSS_ROT_0 ||
rotation == OMAP_DSS_ROT_180) {
if (chroma_upscale)
/* UV is subsampled by 2 horizontally */
orig_width >>= 1;
else
/* UV is downsampled by 2 horizontally */
orig_width <<= 1;
}
/* must use FIR for YUV422 if rotated */
if (rotation != OMAP_DSS_ROT_0)
scale_x = scale_y = true;
break;
default:
BUG();
return;
}
if (out_width != orig_width)
scale_x = true;
if (out_height != orig_height)
scale_y = true;
dispc_ovl_set_scale_param(plane, orig_width, orig_height,
out_width, out_height, five_taps,
rotation, DISPC_COLOR_COMPONENT_UV);
if (plane != OMAP_DSS_WB)
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
(scale_x || scale_y) ? 1 : 0, 8, 8);
/* set H scaling */
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
/* set V scaling */
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
}
static void dispc_ovl_set_scaling(enum omap_plane plane,
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
bool ilace, bool five_taps,
bool fieldmode, enum omap_color_mode color_mode,
u8 rotation)
{
BUG_ON(plane == OMAP_DSS_GFX);
dispc_ovl_set_scaling_common(plane,
orig_width, orig_height,
out_width, out_height,
ilace, five_taps,
fieldmode, color_mode,
rotation);
dispc_ovl_set_scaling_uv(plane,
orig_width, orig_height,
out_width, out_height,
ilace, five_taps,
fieldmode, color_mode,
rotation);
}
static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
enum omap_dss_rotation_type rotation_type,
bool mirroring, enum omap_color_mode color_mode)
{
bool row_repeat = false;
int vidrot = 0;
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY) {
if (mirroring) {
switch (rotation) {
case OMAP_DSS_ROT_0:
vidrot = 2;
break;
case OMAP_DSS_ROT_90:
vidrot = 1;
break;
case OMAP_DSS_ROT_180:
vidrot = 0;
break;
case OMAP_DSS_ROT_270:
vidrot = 3;
break;
}
} else {
switch (rotation) {
case OMAP_DSS_ROT_0:
vidrot = 0;
break;
case OMAP_DSS_ROT_90:
vidrot = 1;
break;
case OMAP_DSS_ROT_180:
vidrot = 2;
break;
case OMAP_DSS_ROT_270:
vidrot = 3;
break;
}
}
if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
row_repeat = true;
else
row_repeat = false;
}
/*
* OMAP4/5 Errata i631:
* NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
* rows beyond the framebuffer, which may cause OCP error.
*/
if (color_mode == OMAP_DSS_COLOR_NV12 &&
rotation_type != OMAP_DSS_ROT_TILER)
vidrot = 1;
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
if (dss_has_feature(FEAT_ROWREPEATENABLE))
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
row_repeat ? 1 : 0, 18, 18);
if (color_mode == OMAP_DSS_COLOR_NV12) {
bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
(rotation == OMAP_DSS_ROT_0 ||
rotation == OMAP_DSS_ROT_180);
/* DOUBLESTRIDE */
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
}
}
static int color_mode_to_bpp(enum omap_color_mode color_mode)
{
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
return 1;
case OMAP_DSS_COLOR_CLUT2:
return 2;
case OMAP_DSS_COLOR_CLUT4:
return 4;
case OMAP_DSS_COLOR_CLUT8:
case OMAP_DSS_COLOR_NV12:
return 8;
case OMAP_DSS_COLOR_RGB12U:
case OMAP_DSS_COLOR_RGB16:
case OMAP_DSS_COLOR_ARGB16:
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
case OMAP_DSS_COLOR_RGBA16:
case OMAP_DSS_COLOR_RGBX16:
case OMAP_DSS_COLOR_ARGB16_1555:
case OMAP_DSS_COLOR_XRGB16_1555:
return 16;
case OMAP_DSS_COLOR_RGB24P:
return 24;
case OMAP_DSS_COLOR_RGB24U:
case OMAP_DSS_COLOR_ARGB32:
case OMAP_DSS_COLOR_RGBA32:
case OMAP_DSS_COLOR_RGBX32:
return 32;
default:
BUG();
return 0;
}
}
static s32 pixinc(int pixels, u8 ps)
{
if (pixels == 1)
return 1;
else if (pixels > 1)
return 1 + (pixels - 1) * ps;
else if (pixels < 0)
return 1 - (-pixels + 1) * ps;
else
BUG();
return 0;
}
static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
u16 screen_width,
u16 width, u16 height,
enum omap_color_mode color_mode, bool fieldmode,
unsigned int field_offset,
unsigned *offset0, unsigned *offset1,
s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
{
u8 ps;
/* FIXME CLUT formats */
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
case OMAP_DSS_COLOR_CLUT2:
case OMAP_DSS_COLOR_CLUT4:
case OMAP_DSS_COLOR_CLUT8:
BUG();
return;
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
ps = 4;
break;
default:
ps = color_mode_to_bpp(color_mode) / 8;
break;
}
DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
width, height);
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
*/
switch (rotation + mirror * 4) {
case OMAP_DSS_ROT_0:
case OMAP_DSS_ROT_180:
/*
* If the pixel format is YUV or UYVY divide the width
* of the image by 2 for 0 and 180 degree rotation.
*/
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
width = width >> 1;
fallthrough;
case OMAP_DSS_ROT_90:
case OMAP_DSS_ROT_270:
*offset1 = 0;
if (field_offset)
*offset0 = field_offset * screen_width * ps;
else
*offset0 = 0;
*row_inc = pixinc(1 +
(y_predecim * screen_width - x_predecim * width) +
(fieldmode ? screen_width : 0), ps);
*pix_inc = pixinc(x_predecim, ps);
break;
case OMAP_DSS_ROT_0 + 4:
case OMAP_DSS_ROT_180 + 4:
/* If the pixel format is YUV or UYVY divide the width
* of the image by 2 for 0 degree and 180 degree
*/
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
width = width >> 1;
fallthrough;
case OMAP_DSS_ROT_90 + 4:
case OMAP_DSS_ROT_270 + 4:
*offset1 = 0;
if (field_offset)
*offset0 = field_offset * screen_width * ps;
else
*offset0 = 0;
*row_inc = pixinc(1 -
(y_predecim * screen_width + x_predecim * width) -
(fieldmode ? screen_width : 0), ps);
*pix_inc = pixinc(x_predecim, ps);
break;
default:
BUG();
return;
}
}
static void calc_dma_rotation_offset(u8 rotation, bool mirror,
u16 screen_width,
u16 width, u16 height,
enum omap_color_mode color_mode, bool fieldmode,
unsigned int field_offset,
unsigned *offset0, unsigned *offset1,
s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
{
u8 ps;
u16 fbw, fbh;
/* FIXME CLUT formats */
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
case OMAP_DSS_COLOR_CLUT2:
case OMAP_DSS_COLOR_CLUT4:
case OMAP_DSS_COLOR_CLUT8:
BUG();
return;
default:
ps = color_mode_to_bpp(color_mode) / 8;
break;
}
DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
width, height);
/* width & height are overlay sizes, convert to fb sizes */
if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
fbw = width;
fbh = height;
} else {
fbw = height;
fbh = width;
}
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
*/
switch (rotation + mirror * 4) {
case OMAP_DSS_ROT_0:
*offset1 = 0;
if (field_offset)
*offset0 = *offset1 + field_offset * screen_width * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(1 +
(y_predecim * screen_width - fbw * x_predecim) +
(fieldmode ? screen_width : 0), ps);
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(x_predecim, 2 * ps);
else
*pix_inc = pixinc(x_predecim, ps);
break;
case OMAP_DSS_ROT_90:
*offset1 = screen_width * (fbh - 1) * ps;
if (field_offset)
*offset0 = *offset1 + field_offset * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
y_predecim + (fieldmode ? 1 : 0), ps);
*pix_inc = pixinc(-x_predecim * screen_width, ps);
break;
case OMAP_DSS_ROT_180:
*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
if (field_offset)
*offset0 = *offset1 - field_offset * screen_width * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(-1 -
(y_predecim * screen_width - fbw * x_predecim) -
(fieldmode ? screen_width : 0), ps);
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(-x_predecim, 2 * ps);
else
*pix_inc = pixinc(-x_predecim, ps);
break;
case OMAP_DSS_ROT_270:
*offset1 = (fbw - 1) * ps;
if (field_offset)
*offset0 = *offset1 - field_offset * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
y_predecim - (fieldmode ? 1 : 0), ps);
*pix_inc = pixinc(x_predecim * screen_width, ps);
break;
/* mirroring */
case OMAP_DSS_ROT_0 + 4:
*offset1 = (fbw - 1) * ps;
if (field_offset)
*offset0 = *offset1 + field_offset * screen_width * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
(fieldmode ? screen_width : 0),
ps);
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(-x_predecim, 2 * ps);
else
*pix_inc = pixinc(-x_predecim, ps);
break;
case OMAP_DSS_ROT_90 + 4:
*offset1 = 0;
if (field_offset)
*offset0 = *offset1 + field_offset * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
y_predecim + (fieldmode ? 1 : 0),
ps);
*pix_inc = pixinc(x_predecim * screen_width, ps);
break;
case OMAP_DSS_ROT_180 + 4:
*offset1 = screen_width * (fbh - 1) * ps;
if (field_offset)
*offset0 = *offset1 - field_offset * screen_width * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(1 - y_predecim * screen_width * 2 -
(fieldmode ? screen_width : 0),
ps);
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(x_predecim, 2 * ps);
else
*pix_inc = pixinc(x_predecim, ps);
break;
case OMAP_DSS_ROT_270 + 4:
*offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
if (field_offset)
*offset0 = *offset1 - field_offset * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
y_predecim - (fieldmode ? 1 : 0),
ps);
*pix_inc = pixinc(-x_predecim * screen_width, ps);
break;
default:
BUG();
return;
}
}
static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
enum omap_color_mode color_mode, bool fieldmode,
unsigned int field_offset, unsigned *offset0, unsigned *offset1,
s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
{
u8 ps;
switch (color_mode) {
case OMAP_DSS_COLOR_CLUT1:
case OMAP_DSS_COLOR_CLUT2:
case OMAP_DSS_COLOR_CLUT4:
case OMAP_DSS_COLOR_CLUT8:
BUG();
return;
default:
ps = color_mode_to_bpp(color_mode) / 8;
break;
}
DSSDBG("scrw %d, width %d\n", screen_width, width);
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
*/
*offset1 = 0;
if (field_offset)
*offset0 = *offset1 + field_offset * screen_width * ps;
else
*offset0 = *offset1;
*row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
(fieldmode ? screen_width : 0), ps);
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY)
*pix_inc = pixinc(x_predecim, 2 * ps);
else
*pix_inc = pixinc(x_predecim, ps);
}
/*
* This function is used to avoid synclosts in OMAP3, because of some
* undocumented horizontal position and timing related limitations.
*/
static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
const struct omap_video_timings *t, u16 pos_x,
u16 width, u16 height, u16 out_width, u16 out_height,
bool five_taps)
{
const int ds = DIV_ROUND_UP(height, out_height);
unsigned long nonactive;
static const u8 limits[3] = { 8, 10, 20 };
u64 val, blank;
int i;
nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
i = 0;
if (out_height < height)
i++;
if (out_width < width)
i++;
blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
if (blank <= limits[i])
return -EINVAL;
/* FIXME add checks for 3-tap filter once the limitations are known */
if (!five_taps)
return 0;
/*
* Pixel data should be prepared before visible display point starts.
* So, atleast DS-2 lines must have already been fetched by DISPC
* during nonactive - pos_x period.
*/
val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
val, max(0, ds - 2) * width);
if (val < max(0, ds - 2) * width)
return -EINVAL;
/*
* All lines need to be refilled during the nonactive period of which
* only one line can be loaded during the active period. So, atleast
* DS - 1 lines should be loaded during nonactive period.
*/
val = div_u64((u64)nonactive * lclk, pclk);
DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
val, max(0, ds - 1) * width);
if (val < max(0, ds - 1) * width)
return -EINVAL;
return 0;
}
static unsigned long calc_core_clk_five_taps(unsigned long pclk,
const struct omap_video_timings *mgr_timings, u16 width,
u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode)
{
u32 core_clk = 0;
u64 tmp;
if (height <= out_height && width <= out_width)
return (unsigned long) pclk;
if (height > out_height) {
unsigned int ppl = mgr_timings->x_res;
tmp = (u64)pclk * height * out_width;
do_div(tmp, 2 * out_height * ppl);
core_clk = tmp;
if (height > 2 * out_height) {
if (ppl == out_width)
return 0;
tmp = (u64)pclk * (height - 2 * out_height) * out_width;
do_div(tmp, 2 * out_height * (ppl - out_width));
core_clk = max_t(u32, core_clk, tmp);
}
}
if (width > out_width) {
tmp = (u64)pclk * width;
do_div(tmp, out_width);
core_clk = max_t(u32, core_clk, tmp);
if (color_mode == OMAP_DSS_COLOR_RGB24U)
core_clk <<= 1;
}
return core_clk;
}
static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
{
if (height > out_height && width > out_width)
return pclk * 4;
else
return pclk * 2;
}
static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
{
unsigned int hf, vf;
/*
* FIXME how to determine the 'A' factor
* for the no downscaling case ?
*/
if (width > 3 * out_width)
hf = 4;
else if (width > 2 * out_width)
hf = 3;
else if (width > out_width)
hf = 2;
else
hf = 1;
if (height > out_height)
vf = 2;
else
vf = 1;
return pclk * vf * hf;
}
static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
{
/*
* If the overlay/writeback is in mem to mem mode, there are no
* downscaling limitations with respect to pixel clock, return 1 as
* required core clock to represent that we have sufficient enough
* core clock to do maximum downscaling
*/
if (mem_to_mem)
return 1;
if (width > out_width)
return DIV_ROUND_UP(pclk, out_width) * width;
else
return pclk;
}
static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
{
int error;
u16 in_width, in_height;
int min_factor = min(*decim_x, *decim_y);
const int maxsinglelinewidth =
dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
*five_taps = false;
do {
in_height = height / *decim_y;
in_width = width / *decim_x;
*core_clk = dispc.feat->calc_core_clk(pclk, in_width,
in_height, out_width, out_height, mem_to_mem);
error = (in_width > maxsinglelinewidth || !*core_clk ||
*core_clk > dispc_core_clk_rate());
if (error) {
if (*decim_x == *decim_y) {
*decim_x = min_factor;
++*decim_y;
} else {
swap(*decim_x, *decim_y);
if (*decim_x < *decim_y)
++*decim_x;
}
}
} while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
if (error) {
DSSERR("failed to find scaling settings\n");
return -EINVAL;
}
if (in_width > maxsinglelinewidth) {
DSSERR("Cannot scale max input width exceeded");
return -EINVAL;
}
return 0;
}
static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
{
int error;
u16 in_width, in_height;
const int maxsinglelinewidth =
dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
do {
in_height = height / *decim_y;
in_width = width / *decim_x;
*five_taps = in_height > out_height;
if (in_width > maxsinglelinewidth)
if (in_height > out_height &&
in_height < out_height * 2)
*five_taps = false;
again:
if (*five_taps)
*core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
in_width, in_height, out_width,
out_height, color_mode);
else
*core_clk = dispc.feat->calc_core_clk(pclk, in_width,
in_height, out_width, out_height,
mem_to_mem);
error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
pos_x, in_width, in_height, out_width,
out_height, *five_taps);
if (error && *five_taps) {
*five_taps = false;
goto again;
}
error = (error || in_width > maxsinglelinewidth * 2 ||
(in_width > maxsinglelinewidth && *five_taps) ||
!*core_clk || *core_clk > dispc_core_clk_rate());
if (!error) {
/* verify that we're inside the limits of scaler */
if (in_width / 4 > out_width)
error = 1;
if (*five_taps) {
if (in_height / 4 > out_height)
error = 1;
} else {
if (in_height / 2 > out_height)
error = 1;
}
}
if (error)
++*decim_y;
} while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
if (error) {
DSSERR("failed to find scaling settings\n");
return -EINVAL;
}
if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
in_height, out_width, out_height, *five_taps)) {
DSSERR("horizontal timing too tight\n");
return -EINVAL;
}
if (in_width > (maxsinglelinewidth * 2)) {
DSSERR("Cannot setup scaling");
DSSERR("width exceeds maximum width possible");
return -EINVAL;
}
if (in_width > maxsinglelinewidth && *five_taps) {
DSSERR("cannot setup scaling with five taps");
return -EINVAL;
}
return 0;
}
static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
{
u16 in_width, in_width_max;
int decim_x_min = *decim_x;
u16 in_height = height / *decim_y;
const int maxsinglelinewidth =
dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
if (mem_to_mem) {
in_width_max = out_width * maxdownscale;
} else {
in_width_max = dispc_core_clk_rate() /
DIV_ROUND_UP(pclk, out_width);
}
*decim_x = DIV_ROUND_UP(width, in_width_max);
*decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
if (*decim_x > *x_predecim)
return -EINVAL;
do {
in_width = width / *decim_x;
} while (*decim_x <= *x_predecim &&
in_width > maxsinglelinewidth && ++*decim_x);
if (in_width > maxsinglelinewidth) {
DSSERR("Cannot scale width exceeds max line width");
return -EINVAL;
}
*core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
out_width, out_height, mem_to_mem);
return 0;
}
#define DIV_FRAC(dividend, divisor) \
((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
enum omap_overlay_caps caps,
const struct omap_video_timings *mgr_timings,
u16 width, u16 height, u16 out_width, u16 out_height,
enum omap_color_mode color_mode, bool *five_taps,
int *x_predecim, int *y_predecim, u16 pos_x,
enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
{
const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
const int max_decim_limit = 16;
unsigned long core_clk = 0;
int decim_x, decim_y, ret;
if (width == out_width && height == out_height)
return 0;
if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
DSSERR("cannot calculate scaling settings: pclk is zero\n");
return -EINVAL;
}
if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
return -EINVAL;
if (mem_to_mem) {
*x_predecim = *y_predecim = 1;
} else {
*x_predecim = max_decim_limit;
*y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
dss_has_feature(FEAT_BURST_2D)) ?
2 : max_decim_limit;
}
if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
color_mode == OMAP_DSS_COLOR_CLUT2 ||
color_mode == OMAP_DSS_COLOR_CLUT4 ||
color_mode == OMAP_DSS_COLOR_CLUT8) {
*x_predecim = 1;
*y_predecim = 1;
*five_taps = false;
return 0;
}
decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
if (decim_x > *x_predecim || out_width > width * 8)
return -EINVAL;
if (decim_y > *y_predecim || out_height > height * 8)
return -EINVAL;
ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
out_width, out_height, color_mode, five_taps,
x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
mem_to_mem);
if (ret)
return ret;
DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
width, height,
out_width, out_height,
out_width / width, DIV_FRAC(out_width, width),
out_height / height, DIV_FRAC(out_height, height),
decim_x, decim_y,
width / decim_x, height / decim_y,
out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
*five_taps ? 5 : 3,
core_clk, dispc_core_clk_rate());
if (!core_clk || core_clk > dispc_core_clk_rate()) {
DSSERR("failed to set up scaling, "
"required core clk rate = %lu Hz, "
"current core clk rate = %lu Hz\n",
core_clk, dispc_core_clk_rate());
return -EINVAL;
}
*x_predecim = decim_x;
*y_predecim = decim_y;
return 0;
}
int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
const struct omap_overlay_info *oi,
const struct omap_video_timings *timings,
int *x_predecim, int *y_predecim)
{
enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
bool five_taps = true;
bool fieldmode = false;
u16 in_height = oi->height;
u16 in_width = oi->width;
bool ilace = timings->interlace;
u16 out_width, out_height;
int pos_x = oi->pos_x;
unsigned long pclk = dispc_mgr_pclk_rate(channel);
unsigned long lclk = dispc_mgr_lclk_rate(channel);
out_width = oi->out_width == 0 ? oi->width : oi->out_width;
out_height = oi->out_height == 0 ? oi->height : oi->out_height;
if (ilace && oi->height == out_height)
fieldmode = true;
if (ilace) {
if (fieldmode)
in_height /= 2;
out_height /= 2;
DSSDBG("adjusting for ilace: height %d, out_height %d\n",
in_height, out_height);
}
if (!dss_feat_color_mode_supported(plane, oi->color_mode))
return -EINVAL;
return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
in_height, out_width, out_height, oi->color_mode,
&five_taps, x_predecim, y_predecim, pos_x,
oi->rotation_type, false);
}
EXPORT_SYMBOL(dispc_ovl_check);
static int dispc_ovl_setup_common(enum omap_plane plane,
enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
u16 out_width, u16 out_height, enum omap_color_mode color_mode,
u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
u8 global_alpha, enum omap_dss_rotation_type rotation_type,
bool replication, const struct omap_video_timings *mgr_timings,
bool mem_to_mem)
{
bool five_taps = true;
bool fieldmode = false;
int r, cconv = 0;
unsigned offset0, offset1;
s32 row_inc;
s32 pix_inc;
u16 frame_width, frame_height;
unsigned int field_offset = 0;
u16 in_height = height;
u16 in_width = width;
int x_predecim = 1, y_predecim = 1;
bool ilace = mgr_timings->interlace;
unsigned long pclk = dispc_plane_pclk_rate(plane);
unsigned long lclk = dispc_plane_lclk_rate(plane);
if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
return -EINVAL;
switch (color_mode) {
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
case OMAP_DSS_COLOR_NV12:
if (in_width & 1) {
DSSERR("input width %d is not even for YUV format\n",
in_width);
return -EINVAL;
}
break;
default:
break;
}
out_width = out_width == 0 ? width : out_width;
out_height = out_height == 0 ? height : out_height;
if (ilace && height == out_height)
fieldmode = true;
if (ilace) {
if (fieldmode)
in_height /= 2;
pos_y /= 2;
out_height /= 2;
DSSDBG("adjusting for ilace: height %d, pos_y %d, "
"out_height %d\n", in_height, pos_y,
out_height);
}
if (!dss_feat_color_mode_supported(plane, color_mode))
return -EINVAL;
r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
in_height, out_width, out_height, color_mode,
&five_taps, &x_predecim, &y_predecim, pos_x,
rotation_type, mem_to_mem);
if (r)
return r;
in_width = in_width / x_predecim;
in_height = in_height / y_predecim;
if (x_predecim > 1 || y_predecim > 1)
DSSDBG("predecimation %d x %x, new input size %d x %d\n",
x_predecim, y_predecim, in_width, in_height);
switch (color_mode) {
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
case OMAP_DSS_COLOR_NV12:
if (in_width & 1) {
DSSDBG("predecimated input width is not even for YUV format\n");
DSSDBG("adjusting input width %d -> %d\n",
in_width, in_width & ~1);
in_width &= ~1;
}
break;
default:
break;
}
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
color_mode == OMAP_DSS_COLOR_UYVY ||
color_mode == OMAP_DSS_COLOR_NV12)
cconv = 1;
if (ilace && !fieldmode) {
/*
* when downscaling the bottom field may have to start several
* source lines below the top field. Unfortunately ACCUI
* registers will only hold the fractional part of the offset
* so the integer part must be added to the base address of the
* bottom field.
*/
if (!in_height || in_height == out_height)
field_offset = 0;
else
field_offset = in_height / out_height / 2;
}
/* Fields are independent but interleaved in memory. */
if (fieldmode)
field_offset = 1;
offset0 = 0;
offset1 = 0;
row_inc = 0;
pix_inc = 0;
if (plane == OMAP_DSS_WB) {
frame_width = out_width;
frame_height = out_height;
} else {
frame_width = in_width;
frame_height = height;
}
if (rotation_type == OMAP_DSS_ROT_TILER)
calc_tiler_rotation_offset(screen_width, frame_width,
color_mode, fieldmode, field_offset,
&offset0, &offset1, &row_inc, &pix_inc,
x_predecim, y_predecim);
else if (rotation_type == OMAP_DSS_ROT_DMA)
calc_dma_rotation_offset(rotation, mirror, screen_width,
frame_width, frame_height,
color_mode, fieldmode, field_offset,
&offset0, &offset1, &row_inc, &pix_inc,
x_predecim, y_predecim);
else
calc_vrfb_rotation_offset(rotation, mirror,
screen_width, frame_width, frame_height,
color_mode, fieldmode, field_offset,
&offset0, &offset1, &row_inc, &pix_inc,
x_predecim, y_predecim);
DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
offset0, offset1, row_inc, pix_inc);
dispc_ovl_set_color_mode(plane, color_mode);
dispc_ovl_configure_burst_type(plane, rotation_type);
dispc_ovl_set_ba0(plane, paddr + offset0);
dispc_ovl_set_ba1(plane, paddr + offset1);
if (OMAP_DSS_COLOR_NV12 == color_mode) {
dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
}
if (dispc.feat->last_pixel_inc_missing)
row_inc += pix_inc - 1;
dispc_ovl_set_row_inc(plane, row_inc);
dispc_ovl_set_pix_inc(plane, pix_inc);
DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
in_height, out_width, out_height);
dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
dispc_ovl_set_input_size(plane, in_width, in_height);
if (caps & OMAP_DSS_OVL_CAP_SCALE) {
dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
out_height, ilace, five_taps, fieldmode,
color_mode, rotation);
dispc_ovl_set_output_size(plane, out_width, out_height);
dispc_ovl_set_vid_color_conv(plane, cconv);
}
dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
color_mode);
dispc_ovl_set_zorder(plane, caps, zorder);
dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
dispc_ovl_enable_replication(plane, caps, replication);
return 0;
}
int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
bool replication, const struct omap_video_timings *mgr_timings,
bool mem_to_mem)
{
int r;
enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
enum omap_channel channel;
channel = dispc_ovl_get_channel_out(plane);
DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
" %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
oi->color_mode, oi->rotation, oi->mirror, channel, replication);
r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
oi->rotation_type, replication, mgr_timings, mem_to_mem);
return r;
}
EXPORT_SYMBOL(dispc_ovl_setup);
int dispc_ovl_enable(enum omap_plane plane, bool enable)
{
DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
return 0;
}
EXPORT_SYMBOL(dispc_ovl_enable);
bool dispc_ovl_enabled(enum omap_plane plane)
{
return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
}
EXPORT_SYMBOL(dispc_ovl_enabled);
void dispc_mgr_enable(enum omap_channel channel, bool enable)
{
mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
/* flush posted write */
mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
}
EXPORT_SYMBOL(dispc_mgr_enable);
bool dispc_mgr_is_enabled(enum omap_channel channel)
{
return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
}
EXPORT_SYMBOL(dispc_mgr_is_enabled);
static void dispc_lcd_enable_signal_polarity(bool act_high)
{
if (!dss_has_feature(FEAT_LCDENABLEPOL))
return;
REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
}
void dispc_lcd_enable_signal(bool enable)
{
if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
return;
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
}
void dispc_pck_free_enable(bool enable)
{
if (!dss_has_feature(FEAT_PCKFREEENABLE))
return;
REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
}
static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
{
mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
}
static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
{
mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
}
static void dispc_set_loadmode(enum omap_dss_load_mode mode)
{
REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
}
static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
{
dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
}
static void dispc_mgr_set_trans_key(enum omap_channel ch,
enum omap_dss_trans_key_type type,
u32 trans_key)
{
mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
}
static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
{
mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
}
static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
bool enable)
{
if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
return;
if (ch == OMAP_DSS_CHANNEL_LCD)
REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
else if (ch == OMAP_DSS_CHANNEL_DIGIT)
REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
}
void dispc_mgr_setup(enum omap_channel channel,
const struct omap_overlay_manager_info *info)
{
dispc_mgr_set_default_color(channel, info->default_color);
dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
dispc_mgr_enable_trans_key(channel, info->trans_enabled);
dispc_mgr_enable_alpha_fixed_zorder(channel,
info->partial_alpha_enabled);
if (dss_has_feature(FEAT_CPR)) {
dispc_mgr_enable_cpr(channel, info->cpr_enable);
dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
}
}
EXPORT_SYMBOL(dispc_mgr_setup);
static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
{
int code;
switch (data_lines) {
case 12:
code = 0;
break;
case 16:
code = 1;
break;
case 18:
code = 2;
break;
case 24:
code = 3;
break;
default:
BUG();
return;
}
mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
}
static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
{
u32 l;
int gpout0, gpout1;
switch (mode) {
case DSS_IO_PAD_MODE_RESET:
gpout0 = 0;
gpout1 = 0;
break;
case DSS_IO_PAD_MODE_RFBI:
gpout0 = 1;
gpout1 = 0;
break;
case DSS_IO_PAD_MODE_BYPASS:
gpout0 = 1;
gpout1 = 1;
break;
default:
BUG();
return;
}
l = dispc_read_reg(DISPC_CONTROL);
l = FLD_MOD(l, gpout0, 15, 15);
l = FLD_MOD(l, gpout1, 16, 16);
dispc_write_reg(DISPC_CONTROL, l);
}
static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
{
mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
}
void dispc_mgr_set_lcd_config(enum omap_channel channel,
const struct dss_lcd_mgr_config *config)
{
dispc_mgr_set_io_pad_mode(config->io_pad_mode);
dispc_mgr_enable_stallmode(channel, config->stallmode);
dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
dispc_mgr_set_clock_div(channel, &config->clock_info);
dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
dispc_mgr_set_lcd_type_tft(channel);
}
EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
static bool _dispc_mgr_size_ok(u16 width, u16 height)
{
return width <= dispc.feat->mgr_width_max &&
height <= dispc.feat->mgr_height_max;
}
static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
int vsw, int vfp, int vbp)
{
if (hsw < 1 || hsw > dispc.feat->sw_max ||
hfp < 1 || hfp > dispc.feat->hp_max ||
hbp < 1 || hbp > dispc.feat->hp_max ||
vsw < 1 || vsw > dispc.feat->sw_max ||
vfp < 0 || vfp > dispc.feat->vp_max ||
vbp < 0 || vbp > dispc.feat->vp_max)
return false;
return true;
}
static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
unsigned long pclk)
{
if (dss_mgr_is_lcd(channel))
return pclk <= dispc.feat->max_lcd_pclk;
else
return pclk <= dispc.feat->max_tv_pclk;
}
bool dispc_mgr_timings_ok(enum omap_channel channel,
const struct omap_video_timings *timings)
{
if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
return false;
if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
return false;
if (dss_mgr_is_lcd(channel)) {
/* TODO: OMAP4+ supports interlace for LCD outputs */
if (timings->interlace)
return false;
if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
timings->hbp, timings->vsw, timings->vfp,
timings->vbp))
return false;
}
return true;
}
static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
int hfp, int hbp, int vsw, int vfp, int vbp,
enum omap_dss_signal_level vsync_level,
enum omap_dss_signal_level hsync_level,
enum omap_dss_signal_edge data_pclk_edge,
enum omap_dss_signal_level de_level,
enum omap_dss_signal_edge sync_pclk_edge)
{
u32 timing_h, timing_v, l;
bool onoff, rf, ipc, vs, hs, de;
timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
FLD_VAL(vfp, dispc.feat->fp_start, 8) |
FLD_VAL(vbp, dispc.feat->bp_start, 20);
dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
switch (vsync_level) {
case OMAPDSS_SIG_ACTIVE_LOW:
vs = true;
break;
case OMAPDSS_SIG_ACTIVE_HIGH:
vs = false;
break;
default:
BUG();
}
switch (hsync_level) {
case OMAPDSS_SIG_ACTIVE_LOW:
hs = true;
break;
case OMAPDSS_SIG_ACTIVE_HIGH:
hs = false;
break;
default:
BUG();
}
switch (de_level) {
case OMAPDSS_SIG_ACTIVE_LOW:
de = true;
break;
case OMAPDSS_SIG_ACTIVE_HIGH:
de = false;
break;
default:
BUG();
}
switch (data_pclk_edge) {
case OMAPDSS_DRIVE_SIG_RISING_EDGE:
ipc = false;
break;
case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
ipc = true;
break;
default:
BUG();
}
/* always use the 'rf' setting */
onoff = true;
switch (sync_pclk_edge) {
case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
rf = false;
break;
case OMAPDSS_DRIVE_SIG_RISING_EDGE:
rf = true;
break;
default:
BUG();
}
l = FLD_VAL(onoff, 17, 17) |
FLD_VAL(rf, 16, 16) |
FLD_VAL(de, 15, 15) |
FLD_VAL(ipc, 14, 14) |
FLD_VAL(hs, 13, 13) |
FLD_VAL(vs, 12, 12);
/* always set ALIGN bit when available */
if (dispc.feat->supports_sync_align)
l |= (1 << 18);
dispc_write_reg(DISPC_POL_FREQ(channel), l);
if (dispc.syscon_pol) {
const int shifts[] = {
[OMAP_DSS_CHANNEL_LCD] = 0,
[OMAP_DSS_CHANNEL_LCD2] = 1,
[OMAP_DSS_CHANNEL_LCD3] = 2,
};
u32 mask, val;
mask = (1 << 0) | (1 << 3) | (1 << 6);
val = (rf << 0) | (ipc << 3) | (onoff << 6);
mask <<= 16 + shifts[channel];
val <<= 16 + shifts[channel];
regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
mask, val);
}
}
/* change name to mode? */
void dispc_mgr_set_timings(enum omap_channel channel,
const struct omap_video_timings *timings)
{
unsigned xtot, ytot;
unsigned long ht, vt;
struct omap_video_timings t = *timings;
DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
if (!dispc_mgr_timings_ok(channel, &t)) {
BUG();
return;
}
if (dss_mgr_is_lcd(channel)) {
_dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
t.vfp, t.vbp, t.vsync_level, t.hsync_level,
t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
xtot = t.x_res + t.hfp + t.hsw + t.hbp;
ytot = t.y_res + t.vfp + t.vsw + t.vbp;
ht = timings->pixelclock / xtot;
vt = timings->pixelclock / xtot / ytot;
DSSDBG("pck %u\n", timings->pixelclock);
DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
t.vsync_level, t.hsync_level, t.data_pclk_edge,
t.de_level, t.sync_pclk_edge);
DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
} else {
if (t.interlace)
t.y_res /= 2;
}
dispc_mgr_set_size(channel, t.x_res, t.y_res);
}
EXPORT_SYMBOL(dispc_mgr_set_timings);
static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
u16 pck_div)
{
BUG_ON(lck_div < 1);
BUG_ON(pck_div < 1);
dispc_write_reg(DISPC_DIVISORo(channel),
FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
channel == OMAP_DSS_CHANNEL_LCD)
dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
}
static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
int *pck_div)
{
u32 l;
l = dispc_read_reg(DISPC_DIVISORo(channel));
*lck_div = FLD_GET(l, 23, 16);
*pck_div = FLD_GET(l, 7, 0);
}
static unsigned long dispc_fclk_rate(void)
{
struct dss_pll *pll;
unsigned long r = 0;
switch (dss_get_dispc_clk_source()) {
case OMAP_DSS_CLK_SRC_FCK:
r = dss_get_dispc_clk_rate();
break;
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
pll = dss_pll_find("dsi0");
if (!pll)
pll = dss_pll_find("video0");
r = pll->cinfo.clkout[0];
break;
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
pll = dss_pll_find("dsi1");
if (!pll)
pll = dss_pll_find("video1");
r = pll->cinfo.clkout[0];
break;
default:
BUG();
return 0;
}
return r;
}
static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
{
struct dss_pll *pll;
int lcd;
unsigned long r;
u32 l;
if (dss_mgr_is_lcd(channel)) {
l = dispc_read_reg(DISPC_DIVISORo(channel));
lcd = FLD_GET(l, 23, 16);
switch (dss_get_lcd_clk_source(channel)) {
case OMAP_DSS_CLK_SRC_FCK:
r = dss_get_dispc_clk_rate();
break;
case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
pll = dss_pll_find("dsi0");
if (!pll)
pll = dss_pll_find("video0");
r = pll->cinfo.clkout[0];
break;
case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
pll = dss_pll_find("dsi1");
if (!pll)
pll = dss_pll_find("video1");
r = pll->cinfo.clkout[0];
break;
default:
BUG();
return 0;
}
return r / lcd;
} else {
return dispc_fclk_rate();
}
}
static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
{
unsigned long r;
if (dss_mgr_is_lcd(channel)) {
int pcd;
u32 l;
l = dispc_read_reg(DISPC_DIVISORo(channel));
pcd = FLD_GET(l, 7, 0);
r = dispc_mgr_lclk_rate(channel);
return r / pcd;
} else {
return dispc.tv_pclk_rate;
}
}
void dispc_set_tv_pclk(unsigned long pclk)
{
dispc.tv_pclk_rate = pclk;
}
static unsigned long dispc_core_clk_rate(void)
{
return dispc.core_clk_rate;
}
static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
{
enum omap_channel channel;
if (plane == OMAP_DSS_WB)
return 0;
channel = dispc_ovl_get_channel_out(plane);
return dispc_mgr_pclk_rate(channel);
}
static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
{
enum omap_channel channel;
if (plane == OMAP_DSS_WB)
return 0;
channel = dispc_ovl_get_channel_out(plane);
return dispc_mgr_lclk_rate(channel);
}
static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
{
int lcd, pcd;
enum omap_dss_clk_source lcd_clk_src;
seq_printf(s, "- %s -\n", mgr_desc[channel].name);
lcd_clk_src = dss_get_lcd_clk_source(channel);
seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
dss_get_generic_clk_source_name(lcd_clk_src),
dss_feat_get_clk_source_name(lcd_clk_src));
dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
dispc_mgr_lclk_rate(channel), lcd);
seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
dispc_mgr_pclk_rate(channel), pcd);
}
void dispc_dump_clocks(struct seq_file *s)
{
int lcd;
u32 l;
enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
if (dispc_runtime_get())
return;
seq_printf(s, "- DISPC -\n");
seq_printf(s, "dispc fclk source = %s (%s)\n",
dss_get_generic_clk_source_name(dispc_clk_src),
dss_feat_get_clk_source_name(dispc_clk_src));
seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
seq_printf(s, "- DISPC-CORE-CLK -\n");
l = dispc_read_reg(DISPC_DIVISOR);
lcd = FLD_GET(l, 23, 16);
seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
(dispc_fclk_rate()/lcd), lcd);
}
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
if (dss_has_feature(FEAT_MGR_LCD2))
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
if (dss_has_feature(FEAT_MGR_LCD3))
dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
dispc_runtime_put();
}
static void dispc_dump_regs(struct seq_file *s)
{
int i, j;
const char *mgr_names[] = {
[OMAP_DSS_CHANNEL_LCD] = "LCD",
[OMAP_DSS_CHANNEL_DIGIT] = "TV",
[OMAP_DSS_CHANNEL_LCD2] = "LCD2",
[OMAP_DSS_CHANNEL_LCD3] = "LCD3",
};
const char *ovl_names[] = {
[OMAP_DSS_GFX] = "GFX",
[OMAP_DSS_VIDEO1] = "VID1",
[OMAP_DSS_VIDEO2] = "VID2",
[OMAP_DSS_VIDEO3] = "VID3",
[OMAP_DSS_WB] = "WB",
};
const char **p_names;
#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
if (dispc_runtime_get())
return;
/* DISPC common registers */
DUMPREG(DISPC_REVISION);
DUMPREG(DISPC_SYSCONFIG);
DUMPREG(DISPC_SYSSTATUS);
DUMPREG(DISPC_IRQSTATUS);
DUMPREG(DISPC_IRQENABLE);
DUMPREG(DISPC_CONTROL);
DUMPREG(DISPC_CONFIG);
DUMPREG(DISPC_CAPABLE);
DUMPREG(DISPC_LINE_STATUS);
DUMPREG(DISPC_LINE_NUMBER);
if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
DUMPREG(DISPC_GLOBAL_ALPHA);
if (dss_has_feature(FEAT_MGR_LCD2)) {
DUMPREG(DISPC_CONTROL2);
DUMPREG(DISPC_CONFIG2);
}
if (dss_has_feature(FEAT_MGR_LCD3)) {
DUMPREG(DISPC_CONTROL3);
DUMPREG(DISPC_CONFIG3);
}
if (dss_has_feature(FEAT_MFLAG))
DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
#undef DUMPREG
#define DISPC_REG(i, name) name(i)
#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
(int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
dispc_read_reg(DISPC_REG(i, r)))
p_names = mgr_names;
/* DISPC channel specific registers */
for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
DUMPREG(i, DISPC_DEFAULT_COLOR);
DUMPREG(i, DISPC_TRANS_COLOR);
DUMPREG(i, DISPC_SIZE_MGR);
if (i == OMAP_DSS_CHANNEL_DIGIT)
continue;
DUMPREG(i, DISPC_TIMING_H);
DUMPREG(i, DISPC_TIMING_V);
DUMPREG(i, DISPC_POL_FREQ);
DUMPREG(i, DISPC_DIVISORo);
DUMPREG(i, DISPC_DATA_CYCLE1);
DUMPREG(i, DISPC_DATA_CYCLE2);
DUMPREG(i, DISPC_DATA_CYCLE3);
if (dss_has_feature(FEAT_CPR)) {
DUMPREG(i, DISPC_CPR_COEF_R);
DUMPREG(i, DISPC_CPR_COEF_G);
DUMPREG(i, DISPC_CPR_COEF_B);
}
}
p_names = ovl_names;
for (i = 0; i < dss_feat_get_num_ovls(); i++) {
DUMPREG(i, DISPC_OVL_BA0);
DUMPREG(i, DISPC_OVL_BA1);
DUMPREG(i, DISPC_OVL_POSITION);
DUMPREG(i, DISPC_OVL_SIZE);
DUMPREG(i, DISPC_OVL_ATTRIBUTES);
DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
DUMPREG(i, DISPC_OVL_ROW_INC);
DUMPREG(i, DISPC_OVL_PIXEL_INC);
if (dss_has_feature(FEAT_PRELOAD))
DUMPREG(i, DISPC_OVL_PRELOAD);
if (dss_has_feature(FEAT_MFLAG))
DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
if (i == OMAP_DSS_GFX) {
DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
DUMPREG(i, DISPC_OVL_TABLE_BA);
continue;
}
DUMPREG(i, DISPC_OVL_FIR);
DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
DUMPREG(i, DISPC_OVL_ACCU0);
DUMPREG(i, DISPC_OVL_ACCU1);
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
DUMPREG(i, DISPC_OVL_BA0_UV);
DUMPREG(i, DISPC_OVL_BA1_UV);
DUMPREG(i, DISPC_OVL_FIR2);
DUMPREG(i, DISPC_OVL_ACCU2_0);
DUMPREG(i, DISPC_OVL_ACCU2_1);
}
if (dss_has_feature(FEAT_ATTR2))
DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
}
if (dispc.feat->has_writeback) {
i = OMAP_DSS_WB;
DUMPREG(i, DISPC_OVL_BA0);
DUMPREG(i, DISPC_OVL_BA1);
DUMPREG(i, DISPC_OVL_SIZE);
DUMPREG(i, DISPC_OVL_ATTRIBUTES);
DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
DUMPREG(i, DISPC_OVL_ROW_INC);
DUMPREG(i, DISPC_OVL_PIXEL_INC);
if (dss_has_feature(FEAT_MFLAG))
DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
DUMPREG(i, DISPC_OVL_FIR);
DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
DUMPREG(i, DISPC_OVL_ACCU0);
DUMPREG(i, DISPC_OVL_ACCU1);
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
DUMPREG(i, DISPC_OVL_BA0_UV);
DUMPREG(i, DISPC_OVL_BA1_UV);
DUMPREG(i, DISPC_OVL_FIR2);
DUMPREG(i, DISPC_OVL_ACCU2_0);
DUMPREG(i, DISPC_OVL_ACCU2_1);
}
if (dss_has_feature(FEAT_ATTR2))
DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
}
#undef DISPC_REG
#undef DUMPREG
#define DISPC_REG(plane, name, i) name(plane, i)
#define DUMPREG(plane, name, i) \
seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
(int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
dispc_read_reg(DISPC_REG(plane, name, i)))
/* Video pipeline coefficient registers */
/* start from OMAP_DSS_VIDEO1 */
for (i = 1; i < dss_feat_get_num_ovls(); i++) {
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
for (j = 0; j < 5; j++)
DUMPREG(i, DISPC_OVL_CONV_COEF, j);
if (dss_has_feature(FEAT_FIR_COEF_V)) {
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
}
if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
for (j = 0; j < 8; j++)
DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
}
}
dispc_runtime_put();
#undef DISPC_REG
#undef DUMPREG
}
/* calculate clock rates using dividers in cinfo */
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
struct dispc_clock_info *cinfo)
{
if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
return -EINVAL;
if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
return -EINVAL;
cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
cinfo->pck = cinfo->lck / cinfo->pck_div;
return 0;
}
bool dispc_div_calc(unsigned long dispc,
unsigned long pck_min, unsigned long pck_max,
dispc_div_calc_func func, void *data)
{
int lckd, lckd_start, lckd_stop;
int pckd, pckd_start, pckd_stop;
unsigned long pck, lck;
unsigned long lck_max;
unsigned long pckd_hw_min, pckd_hw_max;
unsigned min_fck_per_pck;
unsigned long fck;
#ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
#else
min_fck_per_pck = 0;
#endif
pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
pck_min = pck_min ? pck_min : 1;
pck_max = pck_max ? pck_max : ULONG_MAX;
lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
lckd_stop = min(dispc / pck_min, 255ul);
for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
lck = dispc / lckd;
pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
pckd_stop = min(lck / pck_min, pckd_hw_max);
for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
pck = lck / pckd;
/*
* For OMAP2/3 the DISPC fclk is the same as LCD's logic
* clock, which means we're configuring DISPC fclk here
* also. Thus we need to use the calculated lck. For
* OMAP4+ the DISPC fclk is a separate clock.
*/
if (dss_has_feature(FEAT_CORE_CLK_DIV))
fck = dispc_core_clk_rate();
else
fck = lck;
if (fck < pck * min_fck_per_pck)
continue;
if (func(lckd, pckd, lck, pck, data))
return true;
}
}
return false;
}
void dispc_mgr_set_clock_div(enum omap_channel channel,
const struct dispc_clock_info *cinfo)
{
DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
}
int dispc_mgr_get_clock_div(enum omap_channel channel,
struct dispc_clock_info *cinfo)
{
unsigned long fck;
fck = dispc_fclk_rate();
cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
cinfo->lck = fck / cinfo->lck_div;
cinfo->pck = cinfo->lck / cinfo->pck_div;
return 0;
}
u32 dispc_read_irqstatus(void)
{
return dispc_read_reg(DISPC_IRQSTATUS);
}
EXPORT_SYMBOL(dispc_read_irqstatus);
void dispc_clear_irqstatus(u32 mask)
{
dispc_write_reg(DISPC_IRQSTATUS, mask);
}
EXPORT_SYMBOL(dispc_clear_irqstatus);
u32 dispc_read_irqenable(void)
{
return dispc_read_reg(DISPC_IRQENABLE);
}
EXPORT_SYMBOL(dispc_read_irqenable);
void dispc_write_irqenable(u32 mask)
{
u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
/* clear the irqstatus for newly enabled irqs */
dispc_clear_irqstatus((mask ^ old_mask) & mask);
dispc_write_reg(DISPC_IRQENABLE, mask);
}
EXPORT_SYMBOL(dispc_write_irqenable);
void dispc_enable_sidle(void)
{
REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
}
void dispc_disable_sidle(void)
{
REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
}
static void _omap_dispc_initial_config(void)
{
u32 l;
/* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
l = dispc_read_reg(DISPC_DIVISOR);
/* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
l = FLD_MOD(l, 1, 0, 0);
l = FLD_MOD(l, 1, 23, 16);
dispc_write_reg(DISPC_DIVISOR, l);
dispc.core_clk_rate = dispc_fclk_rate();
}
/* FUNCGATED */
if (dss_has_feature(FEAT_FUNCGATED))
REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
dispc_setup_color_conv_coef();
dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
dispc_init_fifos();
dispc_configure_burst_sizes();
dispc_ovl_enable_zorder_planes();
if (dispc.feat->mstandby_workaround)
REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
if (dss_has_feature(FEAT_MFLAG))
dispc_init_mflag();
}
static const struct dispc_features omap24xx_dispc_feats = {
.sw_start = 5,
.fp_start = 15,
.bp_start = 27,
.sw_max = 64,
.vp_max = 255,
.hp_max = 256,
.mgr_width_start = 10,
.mgr_height_start = 26,
.mgr_width_max = 2048,
.mgr_height_max = 2048,
.max_lcd_pclk = 66500000,
.calc_scaling = dispc_ovl_calc_scaling_24xx,
.calc_core_clk = calc_core_clk_24xx,
.num_fifos = 3,
.no_framedone_tv = true,
.set_max_preload = false,
.last_pixel_inc_missing = true,
};
static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
.sw_start = 5,
.fp_start = 15,
.bp_start = 27,
.sw_max = 64,
.vp_max = 255,
.hp_max = 256,
.mgr_width_start = 10,
.mgr_height_start = 26,
.mgr_width_max = 2048,
.mgr_height_max = 2048,
.max_lcd_pclk = 173000000,
.max_tv_pclk = 59000000,
.calc_scaling = dispc_ovl_calc_scaling_34xx,
.calc_core_clk = calc_core_clk_34xx,
.num_fifos = 3,
.no_framedone_tv = true,
.set_max_preload = false,
.last_pixel_inc_missing = true,
};
static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
.sw_start = 7,
.fp_start = 19,
.bp_start = 31,
.sw_max = 256,
.vp_max = 4095,
.hp_max = 4096,
.mgr_width_start = 10,
.mgr_height_start = 26,
.mgr_width_max = 2048,
.mgr_height_max = 2048,
.max_lcd_pclk = 173000000,
.max_tv_pclk = 59000000,
.calc_scaling = dispc_ovl_calc_scaling_34xx,
.calc_core_clk = calc_core_clk_34xx,
.num_fifos = 3,
.no_framedone_tv = true,
.set_max_preload = false,
.last_pixel_inc_missing = true,
};
static const struct dispc_features omap44xx_dispc_feats = {
.sw_start = 7,
.fp_start = 19,
.bp_start = 31,
.sw_max = 256,
.vp_max = 4095,
.hp_max = 4096,
.mgr_width_start = 10,
.mgr_height_start = 26,
.mgr_width_max = 2048,
.mgr_height_max = 2048,
.max_lcd_pclk = 170000000,
.max_tv_pclk = 185625000,
.calc_scaling = dispc_ovl_calc_scaling_44xx,
.calc_core_clk = calc_core_clk_44xx,
.num_fifos = 5,
.gfx_fifo_workaround = true,
.set_max_preload = true,
.supports_sync_align = true,
.has_writeback = true,
};
static const struct dispc_features omap54xx_dispc_feats = {
.sw_start = 7,
.fp_start = 19,
.bp_start = 31,
.sw_max = 256,
.vp_max = 4095,
.hp_max = 4096,
.mgr_width_start = 11,
.mgr_height_start = 27,
.mgr_width_max = 4096,
.mgr_height_max = 4096,
.max_lcd_pclk = 170000000,
.max_tv_pclk = 186000000,
.calc_scaling = dispc_ovl_calc_scaling_44xx,
.calc_core_clk = calc_core_clk_44xx,
.num_fifos = 5,
.gfx_fifo_workaround = true,
.mstandby_workaround = true,
.set_max_preload = true,
.supports_sync_align = true,
.has_writeback = true,
};
static const struct dispc_features *dispc_get_features(void)
{
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP24xx:
return &omap24xx_dispc_feats;
case OMAPDSS_VER_OMAP34xx_ES1:
return &omap34xx_rev1_0_dispc_feats;
case OMAPDSS_VER_OMAP34xx_ES3:
case OMAPDSS_VER_OMAP3630:
case OMAPDSS_VER_AM35xx:
case OMAPDSS_VER_AM43xx:
return &omap34xx_rev3_0_dispc_feats;
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
return &omap44xx_dispc_feats;
case OMAPDSS_VER_OMAP5:
case OMAPDSS_VER_DRA7xx:
return &omap54xx_dispc_feats;
default:
return NULL;
}
}
static irqreturn_t dispc_irq_handler(int irq, void *arg)
{
if (!dispc.is_enabled)
return IRQ_NONE;
return dispc.user_handler(irq, dispc.user_data);
}
int dispc_request_irq(irq_handler_t handler, void *dev_id)
{
int r;
if (dispc.user_handler != NULL)
return -EBUSY;
dispc.user_handler = handler;
dispc.user_data = dev_id;
/* ensure the dispc_irq_handler sees the values above */
smp_wmb();
r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
IRQF_SHARED, "OMAP DISPC", &dispc);
if (r) {
dispc.user_handler = NULL;
dispc.user_data = NULL;
}
return r;
}
EXPORT_SYMBOL(dispc_request_irq);
void dispc_free_irq(void *dev_id)
{
devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
dispc.user_handler = NULL;
dispc.user_data = NULL;
}
EXPORT_SYMBOL(dispc_free_irq);
/* DISPC HW IP initialisation */
static int dispc_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
u32 rev;
int r = 0;
struct resource *dispc_mem;
struct device_node *np = pdev->dev.of_node;
dispc.pdev = pdev;
spin_lock_init(&dispc.control_lock);
dispc.feat = dispc_get_features();
if (!dispc.feat)
return -ENODEV;
dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
if (!dispc_mem) {
DSSERR("can't get IORESOURCE_MEM DISPC\n");
return -EINVAL;
}
dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
resource_size(dispc_mem));
if (!dispc.base) {
DSSERR("can't ioremap DISPC\n");
return -ENOMEM;
}
dispc.irq = platform_get_irq(dispc.pdev, 0);
if (dispc.irq < 0) {
DSSERR("platform_get_irq failed\n");
return -ENODEV;
}
if (np && of_property_read_bool(np, "syscon-pol")) {
dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
if (IS_ERR(dispc.syscon_pol)) {
dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
return PTR_ERR(dispc.syscon_pol);
}
if (of_property_read_u32_index(np, "syscon-pol", 1,
&dispc.syscon_pol_offset)) {
dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
return -EINVAL;
}
}
pm_runtime_enable(&pdev->dev);
r = dispc_runtime_get();
if (r)
goto err_runtime_get;
_omap_dispc_initial_config();
rev = dispc_read_reg(DISPC_REVISION);
dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
dispc_runtime_put();
dss_init_overlay_managers();
dss_debugfs_create_file("dispc", dispc_dump_regs);
return 0;
err_runtime_get:
pm_runtime_disable(&pdev->dev);
return r;
}
static void dispc_unbind(struct device *dev, struct device *master,
void *data)
{
pm_runtime_disable(dev);
dss_uninit_overlay_managers();
}
static const struct component_ops dispc_component_ops = {
.bind = dispc_bind,
.unbind = dispc_unbind,
};
static int dispc_probe(struct platform_device *pdev)
{
return component_add(&pdev->dev, &dispc_component_ops);
}
static void dispc_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &dispc_component_ops);
}
static int dispc_runtime_suspend(struct device *dev)
{
dispc.is_enabled = false;
/* ensure the dispc_irq_handler sees the is_enabled value */
smp_wmb();
/* wait for current handler to finish before turning the DISPC off */
synchronize_irq(dispc.irq);
dispc_save_context();
return 0;
}
static int dispc_runtime_resume(struct device *dev)
{
/*
* The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
* but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
* _omap_dispc_initial_config(). We can thus use it to detect if
* we have lost register context.
*/
if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
_omap_dispc_initial_config();
dispc_restore_context();
}
dispc.is_enabled = true;
/* ensure the dispc_irq_handler sees the is_enabled value */
smp_wmb();
return 0;
}
static const struct dev_pm_ops dispc_pm_ops = {
.runtime_suspend = dispc_runtime_suspend,
.runtime_resume = dispc_runtime_resume,
};
static const struct of_device_id dispc_of_match[] = {
{ .compatible = "ti,omap2-dispc", },
{ .compatible = "ti,omap3-dispc", },
{ .compatible = "ti,omap4-dispc", },
{ .compatible = "ti,omap5-dispc", },
{ .compatible = "ti,dra7-dispc", },
{},
};
static struct platform_driver omap_dispchw_driver = {
.probe = dispc_probe,
.remove_new = dispc_remove,
.driver = {
.name = "omapdss_dispc",
.pm = &dispc_pm_ops,
.of_match_table = dispc_of_match,
.suppress_bind_attrs = true,
},
};
int __init dispc_init_platform_driver(void)
{
return platform_driver_register(&omap_dispchw_driver);
}
void dispc_uninit_platform_driver(void)
{
platform_driver_unregister(&omap_dispchw_driver);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/dispc.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* ti_hdmi_4xxx_ip.c
*
* HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
* Authors: Yong Zhi
* Mythri pk <[email protected]>
*/
#define DSS_SUBSYS_NAME "HDMICORE"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <linux/seq_file.h>
#include <sound/asound.h>
#include <sound/asoundef.h>
#include "hdmi4_core.h"
#include "dss_features.h"
#define HDMI_CORE_AV 0x500
static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core)
{
return core->base + HDMI_CORE_AV;
}
static int hdmi_core_ddc_init(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
/* Turn on CLK for DDC */
REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
/* IN_PROG */
if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
/* Abort transaction */
REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
/* IN_PROG */
if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
4, 4, 0) != 0) {
DSSERR("Timeout aborting DDC transaction\n");
return -ETIMEDOUT;
}
}
/* Clk SCL Devices */
REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
/* HDMI_CORE_DDC_STATUS_IN_PROG */
if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
4, 4, 0) != 0) {
DSSERR("Timeout starting SCL clock\n");
return -ETIMEDOUT;
}
/* Clear FIFO */
REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
/* HDMI_CORE_DDC_STATUS_IN_PROG */
if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
4, 4, 0) != 0) {
DSSERR("Timeout clearing DDC fifo\n");
return -ETIMEDOUT;
}
return 0;
}
static int hdmi_core_ddc_edid(struct hdmi_core_data *core,
u8 *pedid, int ext)
{
void __iomem *base = core->base;
u32 i;
char checksum;
u32 offset = 0;
/* HDMI_CORE_DDC_STATUS_IN_PROG */
if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
4, 4, 0) != 0) {
DSSERR("Timeout waiting DDC to be ready\n");
return -ETIMEDOUT;
}
if (ext % 2 != 0)
offset = 0x80;
/* Load Segment Address Register */
REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
/* Load Slave Address Register */
REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
/* Load Offset Address Register */
REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
/* Load Byte Count */
REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
/* Set DDC_CMD */
if (ext)
REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
else
REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
/* HDMI_CORE_DDC_STATUS_BUS_LOW */
if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
DSSERR("I2C Bus Low?\n");
return -EIO;
}
/* HDMI_CORE_DDC_STATUS_NO_ACK */
if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
DSSERR("I2C No Ack\n");
return -EIO;
}
for (i = 0; i < 0x80; ++i) {
int t;
/* IN_PROG */
if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
DSSERR("operation stopped when reading edid\n");
return -EIO;
}
t = 0;
/* FIFO_EMPTY */
while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
if (t++ > 10000) {
DSSERR("timeout reading edid\n");
return -ETIMEDOUT;
}
udelay(1);
}
pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
}
checksum = 0;
for (i = 0; i < 0x80; ++i)
checksum += pedid[i];
if (checksum != 0) {
DSSERR("E-EDID checksum failed!!\n");
return -EIO;
}
return 0;
}
int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len)
{
int r, l;
if (len < 128)
return -EINVAL;
r = hdmi_core_ddc_init(core);
if (r)
return r;
r = hdmi_core_ddc_edid(core, edid, 0);
if (r)
return r;
l = 128;
if (len >= 128 * 2 && edid[0x7e] > 0) {
r = hdmi_core_ddc_edid(core, edid + 0x80, 1);
if (r)
return r;
l += 128;
}
return l;
}
static void hdmi_core_init(struct hdmi_core_video_config *video_cfg)
{
DSSDBG("Enter hdmi_core_init\n");
/* video core */
video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
video_cfg->hdmi_dvi = HDMI_DVI;
video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
}
static void hdmi_core_powerdown_disable(struct hdmi_core_data *core)
{
DSSDBG("Enter hdmi_core_powerdown_disable\n");
REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x0, 0, 0);
}
static void hdmi_core_swreset_release(struct hdmi_core_data *core)
{
DSSDBG("Enter hdmi_core_swreset_release\n");
REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0);
}
static void hdmi_core_swreset_assert(struct hdmi_core_data *core)
{
DSSDBG("Enter hdmi_core_swreset_assert\n");
REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0);
}
/* HDMI_CORE_VIDEO_CONFIG */
static void hdmi_core_video_config(struct hdmi_core_data *core,
struct hdmi_core_video_config *cfg)
{
u32 r = 0;
void __iomem *core_sys_base = core->base;
void __iomem *core_av_base = hdmi_av_base(core);
/* sys_ctrl1 default configuration not tunable */
r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1);
r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2);
r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1);
hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r);
REG_FLD_MOD(core_sys_base,
HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
/* Vid_Mode */
r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
/* dither truncation configuration */
if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
r = FLD_MOD(r, 1, 5, 5);
} else {
r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
r = FLD_MOD(r, 0, 5, 5);
}
hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
/* HDMI_Ctrl */
r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL);
r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r);
/* TMDS_CTRL */
REG_FLD_MOD(core_sys_base,
HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
}
static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
struct hdmi_avi_infoframe *frame)
{
void __iomem *av_base = hdmi_av_base(core);
u8 data[HDMI_INFOFRAME_SIZE(AVI)];
int i;
hdmi_avi_infoframe_pack(frame, data, sizeof(data));
print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data,
HDMI_INFOFRAME_SIZE(AVI), false);
for (i = 0; i < sizeof(data); ++i) {
hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4,
data[i]);
}
}
static void hdmi_core_av_packet_config(struct hdmi_core_data *core,
struct hdmi_core_packet_enable_repeat repeat_cfg)
{
/* enable/repeat the infoframe */
hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1,
(repeat_cfg.audio_pkt << 5) |
(repeat_cfg.audio_pkt_repeat << 4) |
(repeat_cfg.avi_infoframe << 1) |
(repeat_cfg.avi_infoframe_repeat));
/* enable/repeat the packet */
hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2,
(repeat_cfg.gen_cntrl_pkt << 3) |
(repeat_cfg.gen_cntrl_pkt_repeat << 2) |
(repeat_cfg.generic_pkt << 1) |
(repeat_cfg.generic_pkt_repeat));
}
void hdmi4_configure(struct hdmi_core_data *core,
struct hdmi_wp_data *wp, struct hdmi_config *cfg)
{
/* HDMI */
struct omap_video_timings video_timing;
struct hdmi_video_format video_format;
/* HDMI core */
struct hdmi_core_video_config v_core_cfg;
struct hdmi_core_packet_enable_repeat repeat_cfg = { 0 };
hdmi_core_init(&v_core_cfg);
hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg);
hdmi_wp_video_config_timing(wp, &video_timing);
/* video config */
video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
hdmi_wp_video_config_format(wp, &video_format);
hdmi_wp_video_config_interface(wp, &video_timing);
/*
* configure core video part
* set software reset in the core
*/
hdmi_core_swreset_assert(core);
/* power down off */
hdmi_core_powerdown_disable(core);
v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode;
hdmi_core_video_config(core, &v_core_cfg);
/* release software reset in the core */
hdmi_core_swreset_release(core);
if (cfg->hdmi_dvi_mode == HDMI_HDMI) {
hdmi_core_write_avi_infoframe(core, &cfg->infoframe);
/* enable/repeat the infoframe */
repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
/* wakeup */
repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
}
hdmi_core_av_packet_config(core, repeat_cfg);
}
void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s)
{
int i;
#define CORE_REG(i, name) name(i)
#define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
hdmi_read_reg(core->base, r))
#define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
hdmi_read_reg(hdmi_av_base(core), r))
#define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
(i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \
hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r)))
DUMPCORE(HDMI_CORE_SYS_VND_IDL);
DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
DUMPCORE(HDMI_CORE_SYS_DEV_REV);
DUMPCORE(HDMI_CORE_SYS_SRST);
DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1);
DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3);
DUMPCORE(HDMI_CORE_SYS_DE_DLY);
DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
DUMPCORE(HDMI_CORE_SYS_DE_TOP);
DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
DUMPCORE(HDMI_CORE_SYS_DE_LINL);
DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
DUMPCORE(HDMI_CORE_SYS_HRES_L);
DUMPCORE(HDMI_CORE_SYS_HRES_H);
DUMPCORE(HDMI_CORE_SYS_VRES_L);
DUMPCORE(HDMI_CORE_SYS_VRES_H);
DUMPCORE(HDMI_CORE_SYS_IADJUST);
DUMPCORE(HDMI_CORE_SYS_POLDETECT);
DUMPCORE(HDMI_CORE_SYS_HWIDTH1);
DUMPCORE(HDMI_CORE_SYS_HWIDTH2);
DUMPCORE(HDMI_CORE_SYS_VWIDTH);
DUMPCORE(HDMI_CORE_SYS_VID_CTRL);
DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
DUMPCORE(HDMI_CORE_SYS_VID_MODE);
DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
DUMPCORE(HDMI_CORE_SYS_VID_BLANK3);
DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);
DUMPCORE(HDMI_CORE_SYS_DC_HEADER);
DUMPCORE(HDMI_CORE_SYS_VID_DITHER);
DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT);
DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW);
DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP);
DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW);
DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP);
DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW);
DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP);
DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW);
DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP);
DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
DUMPCORE(HDMI_CORE_SYS_INTR1);
DUMPCORE(HDMI_CORE_SYS_INTR2);
DUMPCORE(HDMI_CORE_SYS_INTR3);
DUMPCORE(HDMI_CORE_SYS_INTR4);
DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1);
DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2);
DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3);
DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4);
DUMPCORE(HDMI_CORE_SYS_INTR_CTRL);
DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
DUMPCORE(HDMI_CORE_DDC_ADDR);
DUMPCORE(HDMI_CORE_DDC_SEGM);
DUMPCORE(HDMI_CORE_DDC_OFFSET);
DUMPCORE(HDMI_CORE_DDC_COUNT1);
DUMPCORE(HDMI_CORE_DDC_COUNT2);
DUMPCORE(HDMI_CORE_DDC_STATUS);
DUMPCORE(HDMI_CORE_DDC_CMD);
DUMPCORE(HDMI_CORE_DDC_DATA);
DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
DUMPCOREAV(HDMI_CORE_AV_ASRC);
DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
DUMPCOREAV(HDMI_CORE_AV_DPD);
DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
}
static void hdmi_core_audio_config(struct hdmi_core_data *core,
struct hdmi_core_audio_config *cfg)
{
u32 r;
void __iomem *av_base = hdmi_av_base(core);
/*
* Parameters for generation of Audio Clock Recovery packets
*/
REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
REG_FLD_MOD(av_base,
HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
REG_FLD_MOD(av_base,
HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
} else {
REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
cfg->aud_par_busclk, 7, 0);
REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
(cfg->aud_par_busclk >> 8), 7, 0);
REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
(cfg->aud_par_busclk >> 16), 7, 0);
}
/* Set ACR clock divisor */
REG_FLD_MOD(av_base,
HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
/*
* Use TMDS clock for ACR packets. For devices that use
* the MCLK, this is the first part of the MCLK initialization.
*/
r = FLD_MOD(r, 0, 2, 2);
r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
r = FLD_MOD(r, cfg->cts_mode, 0, 0);
hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
/* For devices using MCLK, this completes its initialization. */
if (cfg->use_mclk)
REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
/* Override of SPDIF sample frequency with value in I2S_CHST4 */
REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
cfg->fs_override, 1, 1);
/*
* Set IEC-60958-3 channel status word. It is passed to the IP
* just as it is received. The user of the driver is responsible
* for its contents.
*/
hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
cfg->iec60958_cfg->status[0]);
hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
cfg->iec60958_cfg->status[1]);
hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
cfg->iec60958_cfg->status[2]);
/* yes, this is correct: status[3] goes to CHST4 register */
hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
cfg->iec60958_cfg->status[3]);
/* yes, this is correct: status[4] goes to CHST5 register */
hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
cfg->iec60958_cfg->status[4]);
/* set I2S parameters */
r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
cfg->i2s_cfg.in_length_bits, 3, 0);
/* Audio channels and mode parameters */
REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
r = FLD_MOD(r, cfg->en_spdif, 1, 1);
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
/* Audio channel mappings */
/* TODO: Make channel mapping dynamic. For now, map channels
* in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
* HDMI speaker order is different. See CEA-861 Section 6.6.2.
*/
hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
}
static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core,
struct snd_cea_861_aud_if *info_aud)
{
u8 sum = 0, checksum = 0;
void __iomem *av_base = hdmi_av_base(core);
/*
* Set audio info frame type, version and length as
* described in HDMI 1.4a Section 8.2.2 specification.
* Checksum calculation is defined in Section 5.3.5.
*/
hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
sum += 0x84 + 0x001 + 0x00a;
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
info_aud->db1_ct_cc);
sum += info_aud->db1_ct_cc;
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
info_aud->db2_sf_ss);
sum += info_aud->db2_sf_ss;
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
sum += info_aud->db3;
/*
* The OMAP HDMI IP requires to use the 8-channel channel code when
* transmitting more than two channels.
*/
if (info_aud->db4_ca != 0x00)
info_aud->db4_ca = 0x13;
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
sum += info_aud->db4_ca;
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
info_aud->db5_dminh_lsv);
sum += info_aud->db5_dminh_lsv;
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
checksum = 0x100 - sum;
hdmi_write_reg(av_base,
HDMI_CORE_AV_AUDIO_CHSUM, checksum);
/*
* TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
* is available.
*/
}
int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
struct omap_dss_audio *audio, u32 pclk)
{
struct hdmi_audio_format audio_format;
struct hdmi_audio_dma audio_dma;
struct hdmi_core_audio_config acore;
int n, cts, channel_count;
unsigned int fs_nr;
bool word_length_16b = false;
if (!audio || !audio->iec || !audio->cea || !core)
return -EINVAL;
acore.iec60958_cfg = audio->iec;
/*
* In the IEC-60958 status word, check if the audio sample word length
* is 16-bit as several optimizations can be performed in such case.
*/
if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
word_length_16b = true;
/* I2S configuration. See Phillips' specification */
if (word_length_16b)
acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
else
acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
/*
* The I2S input word length is twice the length given in the IEC-60958
* status word. If the word size is greater than
* 20 bits, increment by one.
*/
acore.i2s_cfg.in_length_bits = audio->iec->status[4]
& IEC958_AES4_CON_WORDLEN;
if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
acore.i2s_cfg.in_length_bits++;
acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
/* convert sample frequency to a number */
switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
case IEC958_AES3_CON_FS_32000:
fs_nr = 32000;
break;
case IEC958_AES3_CON_FS_44100:
fs_nr = 44100;
break;
case IEC958_AES3_CON_FS_48000:
fs_nr = 48000;
break;
case IEC958_AES3_CON_FS_88200:
fs_nr = 88200;
break;
case IEC958_AES3_CON_FS_96000:
fs_nr = 96000;
break;
case IEC958_AES3_CON_FS_176400:
fs_nr = 176400;
break;
case IEC958_AES3_CON_FS_192000:
fs_nr = 192000;
break;
default:
return -EINVAL;
}
hdmi_compute_acr(pclk, fs_nr, &n, &cts);
/* Audio clock regeneration settings */
acore.n = n;
acore.cts = cts;
if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
acore.aud_par_busclk = 0;
acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
acore.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
} else {
acore.aud_par_busclk = (((128 * 31) - 1) << 8);
acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
acore.use_mclk = true;
}
if (acore.use_mclk)
acore.mclk_mode = HDMI_AUDIO_MCLK_128FS;
/* Audio channels settings */
channel_count = (audio->cea->db1_ct_cc &
CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
switch (channel_count) {
case 2:
audio_format.active_chnnls_msk = 0x03;
break;
case 3:
audio_format.active_chnnls_msk = 0x07;
break;
case 4:
audio_format.active_chnnls_msk = 0x0f;
break;
case 5:
audio_format.active_chnnls_msk = 0x1f;
break;
case 6:
audio_format.active_chnnls_msk = 0x3f;
break;
case 7:
audio_format.active_chnnls_msk = 0x7f;
break;
case 8:
audio_format.active_chnnls_msk = 0xff;
break;
default:
return -EINVAL;
}
/*
* the HDMI IP needs to enable four stereo channels when transmitting
* more than 2 audio channels. Similarly, the channel count in the
* Audio InfoFrame has to match the sample_present bits (some channels
* are padded with zeroes)
*/
if (channel_count == 2) {
audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
acore.layout = HDMI_AUDIO_LAYOUT_2CH;
} else {
audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
HDMI_AUDIO_I2S_SD3_EN;
acore.layout = HDMI_AUDIO_LAYOUT_8CH;
audio->cea->db1_ct_cc = 7;
}
acore.en_spdif = false;
/* use sample frequency from channel status word */
acore.fs_override = true;
/* enable ACR packets */
acore.en_acr_pkt = true;
/* disable direct streaming digital audio */
acore.en_dsd_audio = false;
/* use parallel audio interface */
acore.en_parallel_aud_input = true;
/* DMA settings */
if (word_length_16b)
audio_dma.transfer_size = 0x10;
else
audio_dma.transfer_size = 0x20;
audio_dma.block_size = 0xC0;
audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
audio_dma.fifo_threshold = 0x20; /* in number of samples */
/* audio FIFO format settings */
if (word_length_16b) {
audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
} else {
audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
}
audio_format.type = HDMI_AUDIO_TYPE_LPCM;
audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
/* disable start/stop signals of IEC 60958 blocks */
audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
/* configure DMA and audio FIFO format*/
hdmi_wp_audio_config_dma(wp, &audio_dma);
hdmi_wp_audio_config_format(wp, &audio_format);
/* configure the core*/
hdmi_core_audio_config(core, &acore);
/* configure CEA 861 audio infoframe*/
hdmi_core_audio_infoframe_cfg(core, audio->cea);
return 0;
}
int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
{
REG_FLD_MOD(hdmi_av_base(core),
HDMI_CORE_AV_AUD_MODE, true, 0, 0);
hdmi_wp_audio_core_req_enable(wp, true);
return 0;
}
void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp)
{
REG_FLD_MOD(hdmi_av_base(core),
HDMI_CORE_AV_AUD_MODE, false, 0, 0);
hdmi_wp_audio_core_req_enable(wp, false);
}
int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core)
{
core->base = devm_platform_ioremap_resource_byname(pdev, "core");
if (IS_ERR(core->base)) {
DSSERR("can't ioremap CORE\n");
return PTR_ERR(core->base);
}
return 0;
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/hdmi4_core.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments
* Author: Tomi Valkeinen <[email protected]>
*/
#define DSS_SUBSYS_NAME "APPLY"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/jiffies.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/seq_file.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
#include "dispc-compat.h"
#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
DISPC_IRQ_OCP_ERR | \
DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
DISPC_IRQ_SYNC_LOST | \
DISPC_IRQ_SYNC_LOST_DIGIT)
#define DISPC_MAX_NR_ISRS 8
struct omap_dispc_isr_data {
omap_dispc_isr_t isr;
void *arg;
u32 mask;
};
struct dispc_irq_stats {
unsigned long last_reset;
unsigned irq_count;
unsigned irqs[32];
};
static struct {
spinlock_t irq_lock;
u32 irq_error_mask;
struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
u32 error_irqs;
struct work_struct error_work;
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
spinlock_t irq_stats_lock;
struct dispc_irq_stats irq_stats;
#endif
} dispc_compat;
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
static void dispc_dump_irqs(struct seq_file *s)
{
unsigned long flags;
struct dispc_irq_stats stats;
spin_lock_irqsave(&dispc_compat.irq_stats_lock, flags);
stats = dispc_compat.irq_stats;
memset(&dispc_compat.irq_stats, 0, sizeof(dispc_compat.irq_stats));
dispc_compat.irq_stats.last_reset = jiffies;
spin_unlock_irqrestore(&dispc_compat.irq_stats_lock, flags);
seq_printf(s, "period %u ms\n",
jiffies_to_msecs(jiffies - stats.last_reset));
seq_printf(s, "irqs %d\n", stats.irq_count);
#define PIS(x) \
seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1])
PIS(FRAMEDONE);
PIS(VSYNC);
PIS(EVSYNC_EVEN);
PIS(EVSYNC_ODD);
PIS(ACBIAS_COUNT_STAT);
PIS(PROG_LINE_NUM);
PIS(GFX_FIFO_UNDERFLOW);
PIS(GFX_END_WIN);
PIS(PAL_GAMMA_MASK);
PIS(OCP_ERR);
PIS(VID1_FIFO_UNDERFLOW);
PIS(VID1_END_WIN);
PIS(VID2_FIFO_UNDERFLOW);
PIS(VID2_END_WIN);
if (dss_feat_get_num_ovls() > 3) {
PIS(VID3_FIFO_UNDERFLOW);
PIS(VID3_END_WIN);
}
PIS(SYNC_LOST);
PIS(SYNC_LOST_DIGIT);
PIS(WAKEUP);
if (dss_has_feature(FEAT_MGR_LCD2)) {
PIS(FRAMEDONE2);
PIS(VSYNC2);
PIS(ACBIAS_COUNT_STAT2);
PIS(SYNC_LOST2);
}
if (dss_has_feature(FEAT_MGR_LCD3)) {
PIS(FRAMEDONE3);
PIS(VSYNC3);
PIS(ACBIAS_COUNT_STAT3);
PIS(SYNC_LOST3);
}
#undef PIS
}
#endif
/* dispc.irq_lock has to be locked by the caller */
static void _omap_dispc_set_irqs(void)
{
u32 mask;
int i;
struct omap_dispc_isr_data *isr_data;
mask = dispc_compat.irq_error_mask;
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
isr_data = &dispc_compat.registered_isr[i];
if (isr_data->isr == NULL)
continue;
mask |= isr_data->mask;
}
dispc_write_irqenable(mask);
}
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
{
int i;
int ret;
unsigned long flags;
struct omap_dispc_isr_data *isr_data;
if (isr == NULL)
return -EINVAL;
spin_lock_irqsave(&dispc_compat.irq_lock, flags);
/* check for duplicate entry */
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
isr_data = &dispc_compat.registered_isr[i];
if (isr_data->isr == isr && isr_data->arg == arg &&
isr_data->mask == mask) {
ret = -EINVAL;
goto err;
}
}
isr_data = NULL;
ret = -EBUSY;
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
isr_data = &dispc_compat.registered_isr[i];
if (isr_data->isr != NULL)
continue;
isr_data->isr = isr;
isr_data->arg = arg;
isr_data->mask = mask;
ret = 0;
break;
}
if (ret)
goto err;
_omap_dispc_set_irqs();
spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);
return 0;
err:
spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);
return ret;
}
EXPORT_SYMBOL(omap_dispc_register_isr);
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
{
int i;
unsigned long flags;
int ret = -EINVAL;
struct omap_dispc_isr_data *isr_data;
spin_lock_irqsave(&dispc_compat.irq_lock, flags);
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
isr_data = &dispc_compat.registered_isr[i];
if (isr_data->isr != isr || isr_data->arg != arg ||
isr_data->mask != mask)
continue;
/* found the correct isr */
isr_data->isr = NULL;
isr_data->arg = NULL;
isr_data->mask = 0;
ret = 0;
break;
}
if (ret == 0)
_omap_dispc_set_irqs();
spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);
return ret;
}
EXPORT_SYMBOL(omap_dispc_unregister_isr);
static void print_irq_status(u32 status)
{
if ((status & dispc_compat.irq_error_mask) == 0)
return;
#define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : ""
pr_debug("DISPC IRQ: 0x%x: %s%s%s%s%s%s%s%s%s\n",
status,
PIS(OCP_ERR),
PIS(GFX_FIFO_UNDERFLOW),
PIS(VID1_FIFO_UNDERFLOW),
PIS(VID2_FIFO_UNDERFLOW),
dss_feat_get_num_ovls() > 3 ? PIS(VID3_FIFO_UNDERFLOW) : "",
PIS(SYNC_LOST),
PIS(SYNC_LOST_DIGIT),
dss_has_feature(FEAT_MGR_LCD2) ? PIS(SYNC_LOST2) : "",
dss_has_feature(FEAT_MGR_LCD3) ? PIS(SYNC_LOST3) : "");
#undef PIS
}
/* Called from dss.c. Note that we don't touch clocks here,
* but we presume they are on because we got an IRQ. However,
* an irq handler may turn the clocks off, so we may not have
* clock later in the function. */
static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
{
int i;
u32 irqstatus, irqenable;
u32 handledirqs = 0;
u32 unhandled_errors;
struct omap_dispc_isr_data *isr_data;
struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
spin_lock(&dispc_compat.irq_lock);
irqstatus = dispc_read_irqstatus();
irqenable = dispc_read_irqenable();
/* IRQ is not for us */
if (!(irqstatus & irqenable)) {
spin_unlock(&dispc_compat.irq_lock);
return IRQ_NONE;
}
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
spin_lock(&dispc_compat.irq_stats_lock);
dispc_compat.irq_stats.irq_count++;
dss_collect_irq_stats(irqstatus, dispc_compat.irq_stats.irqs);
spin_unlock(&dispc_compat.irq_stats_lock);
#endif
print_irq_status(irqstatus);
/* Ack the interrupt. Do it here before clocks are possibly turned
* off */
dispc_clear_irqstatus(irqstatus);
/* flush posted write */
dispc_read_irqstatus();
/* make a copy and unlock, so that isrs can unregister
* themselves */
memcpy(registered_isr, dispc_compat.registered_isr,
sizeof(registered_isr));
spin_unlock(&dispc_compat.irq_lock);
for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
isr_data = ®istered_isr[i];
if (!isr_data->isr)
continue;
if (isr_data->mask & irqstatus) {
isr_data->isr(isr_data->arg, irqstatus);
handledirqs |= isr_data->mask;
}
}
spin_lock(&dispc_compat.irq_lock);
unhandled_errors = irqstatus & ~handledirqs & dispc_compat.irq_error_mask;
if (unhandled_errors) {
dispc_compat.error_irqs |= unhandled_errors;
dispc_compat.irq_error_mask &= ~unhandled_errors;
_omap_dispc_set_irqs();
schedule_work(&dispc_compat.error_work);
}
spin_unlock(&dispc_compat.irq_lock);
return IRQ_HANDLED;
}
static void dispc_error_worker(struct work_struct *work)
{
int i;
u32 errors;
unsigned long flags;
static const unsigned fifo_underflow_bits[] = {
DISPC_IRQ_GFX_FIFO_UNDERFLOW,
DISPC_IRQ_VID1_FIFO_UNDERFLOW,
DISPC_IRQ_VID2_FIFO_UNDERFLOW,
DISPC_IRQ_VID3_FIFO_UNDERFLOW,
};
spin_lock_irqsave(&dispc_compat.irq_lock, flags);
errors = dispc_compat.error_irqs;
dispc_compat.error_irqs = 0;
spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);
dispc_runtime_get();
for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
struct omap_overlay *ovl;
unsigned bit;
ovl = omap_dss_get_overlay(i);
bit = fifo_underflow_bits[i];
if (bit & errors) {
DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
ovl->name);
ovl->disable(ovl);
msleep(50);
}
}
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
struct omap_overlay_manager *mgr;
unsigned bit;
mgr = omap_dss_get_overlay_manager(i);
bit = dispc_mgr_get_sync_lost_irq(i);
if (bit & errors) {
int j;
DSSERR("SYNC_LOST on channel %s, restarting the output "
"with video overlays disabled\n",
mgr->name);
dss_mgr_disable(mgr);
for (j = 0; j < omap_dss_get_num_overlays(); ++j) {
struct omap_overlay *ovl;
ovl = omap_dss_get_overlay(j);
if (ovl->id != OMAP_DSS_GFX &&
ovl->manager == mgr)
ovl->disable(ovl);
}
dss_mgr_enable(mgr);
}
}
if (errors & DISPC_IRQ_OCP_ERR) {
DSSERR("OCP_ERR\n");
for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
struct omap_overlay_manager *mgr;
mgr = omap_dss_get_overlay_manager(i);
dss_mgr_disable(mgr);
}
}
spin_lock_irqsave(&dispc_compat.irq_lock, flags);
dispc_compat.irq_error_mask |= errors;
_omap_dispc_set_irqs();
spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);
dispc_runtime_put();
}
int dss_dispc_initialize_irq(void)
{
int r;
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
spin_lock_init(&dispc_compat.irq_stats_lock);
dispc_compat.irq_stats.last_reset = jiffies;
dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
#endif
spin_lock_init(&dispc_compat.irq_lock);
memset(dispc_compat.registered_isr, 0,
sizeof(dispc_compat.registered_isr));
dispc_compat.irq_error_mask = DISPC_IRQ_MASK_ERROR;
if (dss_has_feature(FEAT_MGR_LCD2))
dispc_compat.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
if (dss_has_feature(FEAT_MGR_LCD3))
dispc_compat.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
if (dss_feat_get_num_ovls() > 3)
dispc_compat.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
/*
* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
* so clear it
*/
dispc_clear_irqstatus(dispc_read_irqstatus());
INIT_WORK(&dispc_compat.error_work, dispc_error_worker);
_omap_dispc_set_irqs();
r = dispc_request_irq(omap_dispc_irq_handler, &dispc_compat);
if (r) {
DSSERR("dispc_request_irq failed\n");
return r;
}
return 0;
}
void dss_dispc_uninitialize_irq(void)
{
dispc_free_irq(&dispc_compat);
}
static void dispc_mgr_disable_isr(void *data, u32 mask)
{
struct completion *compl = data;
complete(compl);
}
static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
{
dispc_mgr_enable(channel, true);
}
static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
{
DECLARE_COMPLETION_ONSTACK(framedone_compl);
int r;
u32 irq;
if (!dispc_mgr_is_enabled(channel))
return;
/*
* When we disable LCD output, we need to wait for FRAMEDONE to know
* that DISPC has finished with the LCD output.
*/
irq = dispc_mgr_get_framedone_irq(channel);
r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
irq);
if (r)
DSSERR("failed to register FRAMEDONE isr\n");
dispc_mgr_enable(channel, false);
/* if we couldn't register for framedone, just sleep and exit */
if (r) {
msleep(100);
return;
}
if (!wait_for_completion_timeout(&framedone_compl,
msecs_to_jiffies(100)))
DSSERR("timeout waiting for FRAME DONE\n");
r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
irq);
if (r)
DSSERR("failed to unregister FRAMEDONE isr\n");
}
static void dispc_digit_out_enable_isr(void *data, u32 mask)
{
struct completion *compl = data;
/* ignore any sync lost interrupts */
if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
complete(compl);
}
static void dispc_mgr_enable_digit_out(void)
{
DECLARE_COMPLETION_ONSTACK(vsync_compl);
int r;
u32 irq_mask;
if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT))
return;
/*
* Digit output produces some sync lost interrupts during the first
* frame when enabling. Those need to be ignored, so we register for the
* sync lost irq to prevent the error handler from triggering.
*/
irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
irq_mask);
if (r) {
DSSERR("failed to register %x isr\n", irq_mask);
return;
}
dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, true);
/* wait for the first evsync */
if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
DSSERR("timeout waiting for digit out to start\n");
r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
irq_mask);
if (r)
DSSERR("failed to unregister %x isr\n", irq_mask);
}
static void dispc_mgr_disable_digit_out(void)
{
DECLARE_COMPLETION_ONSTACK(framedone_compl);
int r, i;
u32 irq_mask;
int num_irqs;
if (!dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT))
return;
/*
* When we disable the digit output, we need to wait for FRAMEDONE to
* know that DISPC has finished with the output.
*/
irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
num_irqs = 1;
if (!irq_mask) {
/*
* omap 2/3 don't have framedone irq for TV, so we need to use
* vsyncs for this.
*/
irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
/*
* We need to wait for both even and odd vsyncs. Note that this
* is not totally reliable, as we could get a vsync interrupt
* before we disable the output, which leads to timeout in the
* wait_for_completion.
*/
num_irqs = 2;
}
r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
irq_mask);
if (r)
DSSERR("failed to register %x isr\n", irq_mask);
dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, false);
/* if we couldn't register the irq, just sleep and exit */
if (r) {
msleep(100);
return;
}
for (i = 0; i < num_irqs; ++i) {
if (!wait_for_completion_timeout(&framedone_compl,
msecs_to_jiffies(100)))
DSSERR("timeout waiting for digit out to stop\n");
}
r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
irq_mask);
if (r)
DSSERR("failed to unregister %x isr\n", irq_mask);
}
void dispc_mgr_enable_sync(enum omap_channel channel)
{
if (dss_mgr_is_lcd(channel))
dispc_mgr_enable_lcd_out(channel);
else if (channel == OMAP_DSS_CHANNEL_DIGIT)
dispc_mgr_enable_digit_out();
else
WARN_ON(1);
}
void dispc_mgr_disable_sync(enum omap_channel channel)
{
if (dss_mgr_is_lcd(channel))
dispc_mgr_disable_lcd_out(channel);
else if (channel == OMAP_DSS_CHANNEL_DIGIT)
dispc_mgr_disable_digit_out();
else
WARN_ON(1);
}
static inline void dispc_irq_wait_handler(void *data, u32 mask)
{
complete((struct completion *)data);
}
int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
unsigned long timeout)
{
int r;
long time_left;
DECLARE_COMPLETION_ONSTACK(completion);
r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
irqmask);
if (r)
return r;
time_left = wait_for_completion_interruptible_timeout(&completion,
timeout);
omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
if (time_left == 0)
return -ETIMEDOUT;
if (time_left == -ERESTARTSYS)
return -ERESTARTSYS;
return 0;
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/sdi.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*/
#define DSS_SUBSYS_NAME "SDI"
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/export.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <linux/of.h>
#include <linux/component.h>
#include <video/omapfb_dss.h>
#include "dss.h"
static struct {
struct platform_device *pdev;
bool update_enabled;
struct regulator *vdds_sdi_reg;
struct dss_lcd_mgr_config mgr_config;
struct omap_video_timings timings;
int datapairs;
struct omap_dss_device output;
bool port_initialized;
} sdi;
struct sdi_clk_calc_ctx {
unsigned long pck_min, pck_max;
unsigned long fck;
struct dispc_clock_info dispc_cinfo;
};
static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
unsigned long pck, void *data)
{
struct sdi_clk_calc_ctx *ctx = data;
ctx->dispc_cinfo.lck_div = lckd;
ctx->dispc_cinfo.pck_div = pckd;
ctx->dispc_cinfo.lck = lck;
ctx->dispc_cinfo.pck = pck;
return true;
}
static bool dpi_calc_dss_cb(unsigned long fck, void *data)
{
struct sdi_clk_calc_ctx *ctx = data;
ctx->fck = fck;
return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
dpi_calc_dispc_cb, ctx);
}
static int sdi_calc_clock_div(unsigned long pclk,
unsigned long *fck,
struct dispc_clock_info *dispc_cinfo)
{
int i;
struct sdi_clk_calc_ctx ctx;
/*
* DSS fclk gives us very few possibilities, so finding a good pixel
* clock may not be possible. We try multiple times to find the clock,
* each time widening the pixel clock range we look for, up to
* +/- 1MHz.
*/
for (i = 0; i < 10; ++i) {
bool ok;
memset(&ctx, 0, sizeof(ctx));
if (pclk > 1000 * i * i * i)
ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
else
ctx.pck_min = 0;
ctx.pck_max = pclk + 1000 * i * i * i;
ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx);
if (ok) {
*fck = ctx.fck;
*dispc_cinfo = ctx.dispc_cinfo;
return 0;
}
}
return -EINVAL;
}
static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
{
struct omap_overlay_manager *mgr = sdi.output.manager;
sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
sdi.mgr_config.stallmode = false;
sdi.mgr_config.fifohandcheck = false;
sdi.mgr_config.video_port_width = 24;
sdi.mgr_config.lcden_sig_polarity = 1;
dss_mgr_set_lcd_config(mgr, &sdi.mgr_config);
}
static int sdi_display_enable(struct omap_dss_device *dssdev)
{
struct omap_dss_device *out = &sdi.output;
struct omap_video_timings *t = &sdi.timings;
unsigned long fck;
struct dispc_clock_info dispc_cinfo;
unsigned long pck;
int r;
if (out->manager == NULL) {
DSSERR("failed to enable display: no output/manager\n");
return -ENODEV;
}
r = regulator_enable(sdi.vdds_sdi_reg);
if (r)
goto err_reg_enable;
r = dispc_runtime_get();
if (r)
goto err_get_dispc;
/* 15.5.9.1.2 */
t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo);
if (r)
goto err_calc_clock_div;
sdi.mgr_config.clock_info = dispc_cinfo;
pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
if (pck != t->pixelclock) {
DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
t->pixelclock, pck);
t->pixelclock = pck;
}
dss_mgr_set_timings(out->manager, t);
r = dss_set_fck_rate(fck);
if (r)
goto err_set_dss_clock_div;
sdi_config_lcd_manager(dssdev);
/*
* LCLK and PCLK divisors are located in shadow registers, and we
* normally write them to DISPC registers when enabling the output.
* However, SDI uses pck-free as source clock for its PLL, and pck-free
* is affected by the divisors. And as we need the PLL before enabling
* the output, we need to write the divisors early.
*
* It seems just writing to the DISPC register is enough, and we don't
* need to care about the shadow register mechanism for pck-free. The
* exact reason for this is unknown.
*/
dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
dss_sdi_init(sdi.datapairs);
r = dss_sdi_enable();
if (r)
goto err_sdi_enable;
mdelay(2);
r = dss_mgr_enable(out->manager);
if (r)
goto err_mgr_enable;
return 0;
err_mgr_enable:
dss_sdi_disable();
err_sdi_enable:
err_set_dss_clock_div:
err_calc_clock_div:
dispc_runtime_put();
err_get_dispc:
regulator_disable(sdi.vdds_sdi_reg);
err_reg_enable:
return r;
}
static void sdi_display_disable(struct omap_dss_device *dssdev)
{
struct omap_overlay_manager *mgr = sdi.output.manager;
dss_mgr_disable(mgr);
dss_sdi_disable();
dispc_runtime_put();
regulator_disable(sdi.vdds_sdi_reg);
}
static void sdi_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
sdi.timings = *timings;
}
static void sdi_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
*timings = sdi.timings;
}
static int sdi_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct omap_overlay_manager *mgr = sdi.output.manager;
if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
return -EINVAL;
if (timings->pixelclock == 0)
return -EINVAL;
return 0;
}
static void sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
{
sdi.datapairs = datapairs;
}
static int sdi_init_regulator(void)
{
struct regulator *vdds_sdi;
if (sdi.vdds_sdi_reg)
return 0;
vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
if (IS_ERR(vdds_sdi)) {
if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
DSSERR("can't get VDDS_SDI regulator\n");
return PTR_ERR(vdds_sdi);
}
sdi.vdds_sdi_reg = vdds_sdi;
return 0;
}
static int sdi_connect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct omap_overlay_manager *mgr;
int r;
r = sdi_init_regulator();
if (r)
return r;
mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
if (!mgr)
return -ENODEV;
r = dss_mgr_connect(mgr, dssdev);
if (r)
return r;
r = omapdss_output_set_device(dssdev, dst);
if (r) {
DSSERR("failed to connect output to new device: %s\n",
dst->name);
dss_mgr_disconnect(mgr, dssdev);
return r;
}
return 0;
}
static void sdi_disconnect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
WARN_ON(dst != dssdev->dst);
if (dst != dssdev->dst)
return;
omapdss_output_unset_device(dssdev);
if (dssdev->manager)
dss_mgr_disconnect(dssdev->manager, dssdev);
}
static const struct omapdss_sdi_ops sdi_ops = {
.connect = sdi_connect,
.disconnect = sdi_disconnect,
.enable = sdi_display_enable,
.disable = sdi_display_disable,
.check_timings = sdi_check_timings,
.set_timings = sdi_set_timings,
.get_timings = sdi_get_timings,
.set_datapairs = sdi_set_datapairs,
};
static void sdi_init_output(struct platform_device *pdev)
{
struct omap_dss_device *out = &sdi.output;
out->dev = &pdev->dev;
out->id = OMAP_DSS_OUTPUT_SDI;
out->output_type = OMAP_DISPLAY_TYPE_SDI;
out->name = "sdi.0";
out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
/* We have SDI only on OMAP3, where it's on port 1 */
out->port_num = 1;
out->ops.sdi = &sdi_ops;
out->owner = THIS_MODULE;
omapdss_register_output(out);
}
static void sdi_uninit_output(struct platform_device *pdev)
{
struct omap_dss_device *out = &sdi.output;
omapdss_unregister_output(out);
}
static int sdi_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
sdi.pdev = pdev;
sdi_init_output(pdev);
return 0;
}
static void sdi_unbind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
sdi_uninit_output(pdev);
}
static const struct component_ops sdi_component_ops = {
.bind = sdi_bind,
.unbind = sdi_unbind,
};
static int sdi_probe(struct platform_device *pdev)
{
return component_add(&pdev->dev, &sdi_component_ops);
}
static void sdi_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &sdi_component_ops);
}
static struct platform_driver omap_sdi_driver = {
.probe = sdi_probe,
.remove_new = sdi_remove,
.driver = {
.name = "omapdss_sdi",
.suppress_bind_attrs = true,
},
};
int __init sdi_init_platform_driver(void)
{
return platform_driver_register(&omap_sdi_driver);
}
void sdi_uninit_platform_driver(void)
{
platform_driver_unregister(&omap_sdi_driver);
}
int sdi_init_port(struct platform_device *pdev, struct device_node *port)
{
struct device_node *ep;
u32 datapairs;
int r;
ep = omapdss_of_get_next_endpoint(port, NULL);
if (!ep)
return 0;
r = of_property_read_u32(ep, "datapairs", &datapairs);
if (r) {
DSSERR("failed to parse datapairs\n");
goto err_datapairs;
}
sdi.datapairs = datapairs;
of_node_put(ep);
sdi.pdev = pdev;
sdi_init_output(pdev);
sdi.port_initialized = true;
return 0;
err_datapairs:
of_node_put(ep);
return r;
}
void sdi_uninit_port(struct device_node *port)
{
if (!sdi.port_initialized)
return;
sdi_uninit_output(sdi.pdev);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/sdi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/dss_features.c
*
* Copyright (C) 2010 Texas Instruments
* Author: Archit Taneja <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
/* Defines a generic omap register field */
struct dss_reg_field {
u8 start, end;
};
struct dss_param_range {
int min, max;
};
struct omap_dss_features {
const struct dss_reg_field *reg_fields;
const int num_reg_fields;
const enum dss_feat_id *features;
const int num_features;
const int num_mgrs;
const int num_ovls;
const enum omap_display_type *supported_displays;
const enum omap_dss_output_id *supported_outputs;
const enum omap_color_mode *supported_color_modes;
const enum omap_overlay_caps *overlay_caps;
const char * const *clksrc_names;
const struct dss_param_range *dss_params;
const enum omap_dss_rotation_type supported_rotation_types;
const u32 buffer_size_unit;
const u32 burst_size_unit;
};
/* This struct is assigned to one of the below during initialization */
static const struct omap_dss_features *omap_current_dss_features;
static const struct dss_reg_field omap2_dss_reg_fields[] = {
[FEAT_REG_FIRHINC] = { 11, 0 },
[FEAT_REG_FIRVINC] = { 27, 16 },
[FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
[FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
[FEAT_REG_FIFOSIZE] = { 8, 0 },
[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
[FEAT_REG_VERTICALACCU] = { 25, 16 },
[FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
};
static const struct dss_reg_field omap3_dss_reg_fields[] = {
[FEAT_REG_FIRHINC] = { 12, 0 },
[FEAT_REG_FIRVINC] = { 28, 16 },
[FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
[FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
[FEAT_REG_FIFOSIZE] = { 10, 0 },
[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
[FEAT_REG_VERTICALACCU] = { 25, 16 },
[FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
};
static const struct dss_reg_field am43xx_dss_reg_fields[] = {
[FEAT_REG_FIRHINC] = { 12, 0 },
[FEAT_REG_FIRVINC] = { 28, 16 },
[FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
[FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
[FEAT_REG_FIFOSIZE] = { 10, 0 },
[FEAT_REG_HORIZONTALACCU] = { 9, 0 },
[FEAT_REG_VERTICALACCU] = { 25, 16 },
[FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
};
static const struct dss_reg_field omap4_dss_reg_fields[] = {
[FEAT_REG_FIRHINC] = { 12, 0 },
[FEAT_REG_FIRVINC] = { 28, 16 },
[FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
[FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
[FEAT_REG_FIFOSIZE] = { 15, 0 },
[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
[FEAT_REG_VERTICALACCU] = { 26, 16 },
[FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
};
static const struct dss_reg_field omap5_dss_reg_fields[] = {
[FEAT_REG_FIRHINC] = { 12, 0 },
[FEAT_REG_FIRVINC] = { 28, 16 },
[FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
[FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
[FEAT_REG_FIFOSIZE] = { 15, 0 },
[FEAT_REG_HORIZONTALACCU] = { 10, 0 },
[FEAT_REG_VERTICALACCU] = { 26, 16 },
[FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 },
};
static const enum omap_display_type omap2_dss_supported_displays[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DISPLAY_TYPE_VENC,
};
static const enum omap_display_type omap3430_dss_supported_displays[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DISPLAY_TYPE_VENC,
};
static const enum omap_display_type omap3630_dss_supported_displays[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
OMAP_DISPLAY_TYPE_DSI,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DISPLAY_TYPE_VENC,
};
static const enum omap_display_type am43xx_dss_supported_displays[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
};
static const enum omap_display_type omap4_dss_supported_displays[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
/* OMAP_DSS_CHANNEL_LCD2 */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
OMAP_DISPLAY_TYPE_DSI,
};
static const enum omap_display_type omap5_dss_supported_displays[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
OMAP_DISPLAY_TYPE_DSI,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
/* OMAP_DSS_CHANNEL_LCD2 */
OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
OMAP_DISPLAY_TYPE_DSI,
};
static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DSS_OUTPUT_VENC,
};
static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
OMAP_DSS_OUTPUT_SDI | OMAP_DSS_OUTPUT_DSI1,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DSS_OUTPUT_VENC,
};
static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
OMAP_DSS_OUTPUT_DSI1,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DSS_OUTPUT_VENC,
};
static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
};
static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DSS_OUTPUT_DBI | OMAP_DSS_OUTPUT_DSI1,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DSS_OUTPUT_VENC | OMAP_DSS_OUTPUT_HDMI,
/* OMAP_DSS_CHANNEL_LCD2 */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
OMAP_DSS_OUTPUT_DSI2,
};
static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
OMAP_DSS_OUTPUT_DSI1 | OMAP_DSS_OUTPUT_DSI2,
/* OMAP_DSS_CHANNEL_DIGIT */
OMAP_DSS_OUTPUT_HDMI,
/* OMAP_DSS_CHANNEL_LCD2 */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
OMAP_DSS_OUTPUT_DSI1,
/* OMAP_DSS_CHANNEL_LCD3 */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI |
OMAP_DSS_OUTPUT_DSI2,
};
static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
OMAP_DSS_COLOR_UYVY,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
OMAP_DSS_COLOR_UYVY,
};
static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
};
static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
OMAP_DSS_COLOR_RGBX32,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
OMAP_DSS_COLOR_RGBX32,
/* OMAP_DSS_VIDEO3 */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
OMAP_DSS_COLOR_RGBX32,
/* OMAP_DSS_WB */
OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
OMAP_DSS_COLOR_RGBX32,
};
static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
OMAP_DSS_OVL_CAP_REPLICATION,
};
static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS |
OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
};
static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS |
OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS |
OMAP_DSS_OVL_CAP_REPLICATION,
};
static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS |
OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO1 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO2 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
/* OMAP_DSS_VIDEO3 */
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER |
OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
};
static const char * const omap2_dss_clk_source_names[] = {
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
[OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
};
static const char * const omap3_dss_clk_source_names[] = {
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
[OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
};
static const char * const omap4_dss_clk_source_names[] = {
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
[OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
};
static const char * const omap5_dss_clk_source_names[] = {
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DPLL_DSI1_A_CLK1",
[OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DPLL_DSI1_A_CLK2",
[OMAP_DSS_CLK_SRC_FCK] = "DSS_CLK",
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DPLL_DSI1_C_CLK1",
[OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DPLL_DSI1_C_CLK2",
};
static const struct dss_param_range omap2_dss_param_range[] = {
[FEAT_PARAM_DSS_FCK] = { 0, 133000000 },
[FEAT_PARAM_DSS_PCD] = { 2, 255 },
[FEAT_PARAM_DOWNSCALE] = { 1, 2 },
/*
* Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
* scaler cannot scale a image with width more than 768.
*/
[FEAT_PARAM_LINEWIDTH] = { 1, 768 },
};
static const struct dss_param_range omap3_dss_param_range[] = {
[FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
[FEAT_PARAM_DSS_PCD] = { 1, 255 },
[FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
[FEAT_PARAM_DSI_FCK] = { 0, 173000000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
};
static const struct dss_param_range am43xx_dss_param_range[] = {
[FEAT_PARAM_DSS_FCK] = { 0, 200000000 },
[FEAT_PARAM_DSS_PCD] = { 1, 255 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
};
static const struct dss_param_range omap4_dss_param_range[] = {
[FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
[FEAT_PARAM_DSS_PCD] = { 1, 255 },
[FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
[FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
};
static const struct dss_param_range omap5_dss_param_range[] = {
[FEAT_PARAM_DSS_FCK] = { 0, 209250000 },
[FEAT_PARAM_DSS_PCD] = { 1, 255 },
[FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
[FEAT_PARAM_DSI_FCK] = { 0, 209250000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
};
static const enum dss_feat_id omap2_dss_feat_list[] = {
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
};
static const enum dss_feat_id omap3430_dss_feat_list[] = {
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_LINEBUFFERSPLIT,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
FEAT_DSI_REVERSE_TXCLKESC,
FEAT_VENC_REQUIRES_TV_DAC_CLK,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FIXED_ZORDER,
FEAT_FIFO_MERGE,
FEAT_OMAP3_DSI_FIFO_BUG,
FEAT_DPI_USES_VDDS_DSI,
};
static const enum dss_feat_id am35xx_dss_feat_list[] = {
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_LINEBUFFERSPLIT,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
FEAT_DSI_REVERSE_TXCLKESC,
FEAT_VENC_REQUIRES_TV_DAC_CLK,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FIXED_ZORDER,
FEAT_FIFO_MERGE,
FEAT_OMAP3_DSI_FIFO_BUG,
};
static const enum dss_feat_id am43xx_dss_feat_list[] = {
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_LINEBUFFERSPLIT,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FIXED_ZORDER,
FEAT_FIFO_MERGE,
};
static const enum dss_feat_id omap3630_dss_feat_list[] = {
FEAT_LCDENABLEPOL,
FEAT_LCDENABLESIGNAL,
FEAT_PCKFREEENABLE,
FEAT_FUNCGATED,
FEAT_LINEBUFFERSPLIT,
FEAT_ROWREPEATENABLE,
FEAT_RESIZECONF,
FEAT_DSI_PLL_PWR_BUG,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FIXED_ZORDER,
FEAT_FIFO_MERGE,
FEAT_OMAP3_DSI_FIFO_BUG,
FEAT_DPI_USES_VDDS_DSI,
};
static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
FEAT_MGR_LCD2,
FEAT_CORE_CLK_DIV,
FEAT_LCD_CLK_SRC,
FEAT_DSI_DCS_CMD_CONFIG_VC,
FEAT_DSI_VC_OCP_WIDTH,
FEAT_DSI_GNQ,
FEAT_HANDLE_UV_SEPARATE,
FEAT_ATTR2,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FREE_ZORDER,
FEAT_FIFO_MERGE,
FEAT_BURST_2D,
};
static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
FEAT_MGR_LCD2,
FEAT_CORE_CLK_DIV,
FEAT_LCD_CLK_SRC,
FEAT_DSI_DCS_CMD_CONFIG_VC,
FEAT_DSI_VC_OCP_WIDTH,
FEAT_DSI_GNQ,
FEAT_HDMI_CTS_SWMODE,
FEAT_HANDLE_UV_SEPARATE,
FEAT_ATTR2,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FREE_ZORDER,
FEAT_FIFO_MERGE,
FEAT_BURST_2D,
};
static const enum dss_feat_id omap4_dss_feat_list[] = {
FEAT_MGR_LCD2,
FEAT_CORE_CLK_DIV,
FEAT_LCD_CLK_SRC,
FEAT_DSI_DCS_CMD_CONFIG_VC,
FEAT_DSI_VC_OCP_WIDTH,
FEAT_DSI_GNQ,
FEAT_HDMI_CTS_SWMODE,
FEAT_HDMI_AUDIO_USE_MCLK,
FEAT_HANDLE_UV_SEPARATE,
FEAT_ATTR2,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FREE_ZORDER,
FEAT_FIFO_MERGE,
FEAT_BURST_2D,
};
static const enum dss_feat_id omap5_dss_feat_list[] = {
FEAT_MGR_LCD2,
FEAT_MGR_LCD3,
FEAT_CORE_CLK_DIV,
FEAT_LCD_CLK_SRC,
FEAT_DSI_DCS_CMD_CONFIG_VC,
FEAT_DSI_VC_OCP_WIDTH,
FEAT_DSI_GNQ,
FEAT_HDMI_CTS_SWMODE,
FEAT_HDMI_AUDIO_USE_MCLK,
FEAT_HANDLE_UV_SEPARATE,
FEAT_ATTR2,
FEAT_CPR,
FEAT_PRELOAD,
FEAT_FIR_COEF_V,
FEAT_ALPHA_FREE_ZORDER,
FEAT_FIFO_MERGE,
FEAT_BURST_2D,
FEAT_DSI_PHY_DCC,
FEAT_MFLAG,
};
/* OMAP2 DSS Features */
static const struct omap_dss_features omap2_dss_features = {
.reg_fields = omap2_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
.features = omap2_dss_feat_list,
.num_features = ARRAY_SIZE(omap2_dss_feat_list),
.num_mgrs = 2,
.num_ovls = 3,
.supported_displays = omap2_dss_supported_displays,
.supported_outputs = omap2_dss_supported_outputs,
.supported_color_modes = omap2_dss_supported_color_modes,
.overlay_caps = omap2_dss_overlay_caps,
.clksrc_names = omap2_dss_clk_source_names,
.dss_params = omap2_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
.buffer_size_unit = 1,
.burst_size_unit = 8,
};
/* OMAP3 DSS Features */
static const struct omap_dss_features omap3430_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
.features = omap3430_dss_feat_list,
.num_features = ARRAY_SIZE(omap3430_dss_feat_list),
.num_mgrs = 2,
.num_ovls = 3,
.supported_displays = omap3430_dss_supported_displays,
.supported_outputs = omap3430_dss_supported_outputs,
.supported_color_modes = omap3_dss_supported_color_modes,
.overlay_caps = omap3430_dss_overlay_caps,
.clksrc_names = omap3_dss_clk_source_names,
.dss_params = omap3_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
.buffer_size_unit = 1,
.burst_size_unit = 8,
};
/*
* AM35xx DSS Features. This is basically OMAP3 DSS Features without the
* vdds_dsi regulator.
*/
static const struct omap_dss_features am35xx_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
.features = am35xx_dss_feat_list,
.num_features = ARRAY_SIZE(am35xx_dss_feat_list),
.num_mgrs = 2,
.num_ovls = 3,
.supported_displays = omap3430_dss_supported_displays,
.supported_outputs = omap3430_dss_supported_outputs,
.supported_color_modes = omap3_dss_supported_color_modes,
.overlay_caps = omap3430_dss_overlay_caps,
.clksrc_names = omap3_dss_clk_source_names,
.dss_params = omap3_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
.buffer_size_unit = 1,
.burst_size_unit = 8,
};
static const struct omap_dss_features am43xx_dss_features = {
.reg_fields = am43xx_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields),
.features = am43xx_dss_feat_list,
.num_features = ARRAY_SIZE(am43xx_dss_feat_list),
.num_mgrs = 1,
.num_ovls = 3,
.supported_displays = am43xx_dss_supported_displays,
.supported_outputs = am43xx_dss_supported_outputs,
.supported_color_modes = omap3_dss_supported_color_modes,
.overlay_caps = omap3430_dss_overlay_caps,
.clksrc_names = omap2_dss_clk_source_names,
.dss_params = am43xx_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA,
.buffer_size_unit = 1,
.burst_size_unit = 8,
};
static const struct omap_dss_features omap3630_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
.features = omap3630_dss_feat_list,
.num_features = ARRAY_SIZE(omap3630_dss_feat_list),
.num_mgrs = 2,
.num_ovls = 3,
.supported_displays = omap3630_dss_supported_displays,
.supported_outputs = omap3630_dss_supported_outputs,
.supported_color_modes = omap3_dss_supported_color_modes,
.overlay_caps = omap3630_dss_overlay_caps,
.clksrc_names = omap3_dss_clk_source_names,
.dss_params = omap3_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
.buffer_size_unit = 1,
.burst_size_unit = 8,
};
/* OMAP4 DSS Features */
/* For OMAP4430 ES 1.0 revision */
static const struct omap_dss_features omap4430_es1_0_dss_features = {
.reg_fields = omap4_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
.features = omap4430_es1_0_dss_feat_list,
.num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
.num_mgrs = 3,
.num_ovls = 4,
.supported_displays = omap4_dss_supported_displays,
.supported_outputs = omap4_dss_supported_outputs,
.supported_color_modes = omap4_dss_supported_color_modes,
.overlay_caps = omap4_dss_overlay_caps,
.clksrc_names = omap4_dss_clk_source_names,
.dss_params = omap4_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
.buffer_size_unit = 16,
.burst_size_unit = 16,
};
/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
.reg_fields = omap4_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
.features = omap4430_es2_0_1_2_dss_feat_list,
.num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
.num_mgrs = 3,
.num_ovls = 4,
.supported_displays = omap4_dss_supported_displays,
.supported_outputs = omap4_dss_supported_outputs,
.supported_color_modes = omap4_dss_supported_color_modes,
.overlay_caps = omap4_dss_overlay_caps,
.clksrc_names = omap4_dss_clk_source_names,
.dss_params = omap4_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
.buffer_size_unit = 16,
.burst_size_unit = 16,
};
/* For all the other OMAP4 versions */
static const struct omap_dss_features omap4_dss_features = {
.reg_fields = omap4_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
.features = omap4_dss_feat_list,
.num_features = ARRAY_SIZE(omap4_dss_feat_list),
.num_mgrs = 3,
.num_ovls = 4,
.supported_displays = omap4_dss_supported_displays,
.supported_outputs = omap4_dss_supported_outputs,
.supported_color_modes = omap4_dss_supported_color_modes,
.overlay_caps = omap4_dss_overlay_caps,
.clksrc_names = omap4_dss_clk_source_names,
.dss_params = omap4_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
.buffer_size_unit = 16,
.burst_size_unit = 16,
};
/* OMAP5 DSS Features */
static const struct omap_dss_features omap5_dss_features = {
.reg_fields = omap5_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
.features = omap5_dss_feat_list,
.num_features = ARRAY_SIZE(omap5_dss_feat_list),
.num_mgrs = 4,
.num_ovls = 4,
.supported_displays = omap5_dss_supported_displays,
.supported_outputs = omap5_dss_supported_outputs,
.supported_color_modes = omap4_dss_supported_color_modes,
.overlay_caps = omap4_dss_overlay_caps,
.clksrc_names = omap5_dss_clk_source_names,
.dss_params = omap5_dss_param_range,
.supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
.buffer_size_unit = 16,
.burst_size_unit = 16,
};
/* Functions returning values related to a DSS feature */
int dss_feat_get_num_mgrs(void)
{
return omap_current_dss_features->num_mgrs;
}
EXPORT_SYMBOL(dss_feat_get_num_mgrs);
int dss_feat_get_num_ovls(void)
{
return omap_current_dss_features->num_ovls;
}
EXPORT_SYMBOL(dss_feat_get_num_ovls);
unsigned long dss_feat_get_param_min(enum dss_range_param param)
{
return omap_current_dss_features->dss_params[param].min;
}
unsigned long dss_feat_get_param_max(enum dss_range_param param)
{
return omap_current_dss_features->dss_params[param].max;
}
enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
{
return omap_current_dss_features->supported_displays[channel];
}
enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel)
{
return omap_current_dss_features->supported_outputs[channel];
}
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
{
return omap_current_dss_features->supported_color_modes[plane];
}
EXPORT_SYMBOL(dss_feat_get_supported_color_modes);
enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
{
return omap_current_dss_features->overlay_caps[plane];
}
bool dss_feat_color_mode_supported(enum omap_plane plane,
enum omap_color_mode color_mode)
{
return omap_current_dss_features->supported_color_modes[plane] &
color_mode;
}
const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
{
return omap_current_dss_features->clksrc_names[id];
}
u32 dss_feat_get_buffer_size_unit(void)
{
return omap_current_dss_features->buffer_size_unit;
}
u32 dss_feat_get_burst_size_unit(void)
{
return omap_current_dss_features->burst_size_unit;
}
/* DSS has_feature check */
bool dss_has_feature(enum dss_feat_id id)
{
int i;
const enum dss_feat_id *features = omap_current_dss_features->features;
const int num_features = omap_current_dss_features->num_features;
for (i = 0; i < num_features; i++) {
if (features[i] == id)
return true;
}
return false;
}
void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
{
BUG_ON(id >= omap_current_dss_features->num_reg_fields);
*start = omap_current_dss_features->reg_fields[id].start;
*end = omap_current_dss_features->reg_fields[id].end;
}
bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
{
return omap_current_dss_features->supported_rotation_types & rot_type;
}
void dss_features_init(enum omapdss_version version)
{
switch (version) {
case OMAPDSS_VER_OMAP24xx:
omap_current_dss_features = &omap2_dss_features;
break;
case OMAPDSS_VER_OMAP34xx_ES1:
case OMAPDSS_VER_OMAP34xx_ES3:
omap_current_dss_features = &omap3430_dss_features;
break;
case OMAPDSS_VER_OMAP3630:
omap_current_dss_features = &omap3630_dss_features;
break;
case OMAPDSS_VER_OMAP4430_ES1:
omap_current_dss_features = &omap4430_es1_0_dss_features;
break;
case OMAPDSS_VER_OMAP4430_ES2:
omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
break;
case OMAPDSS_VER_OMAP4:
omap_current_dss_features = &omap4_dss_features;
break;
case OMAPDSS_VER_OMAP5:
case OMAPDSS_VER_DRA7xx:
omap_current_dss_features = &omap5_dss_features;
break;
case OMAPDSS_VER_AM35xx:
omap_current_dss_features = &am35xx_dss_features;
break;
case OMAPDSS_VER_AM43xx:
omap_current_dss_features = &am43xx_dss_features;
break;
default:
DSSWARN("Unsupported OMAP version");
break;
}
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/dss_features.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HDMI interface DSS driver for TI's OMAP4 family of SoCs.
* Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
* Authors: Yong Zhi
* Mythri pk <[email protected]>
*/
#define DSS_SUBSYS_NAME "HDMI"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
#include <linux/component.h>
#include <video/omapfb_dss.h>
#include <sound/omap-hdmi-audio.h>
#include "hdmi4_core.h"
#include "dss.h"
#include "dss_features.h"
#include "hdmi.h"
static struct omap_hdmi hdmi;
static int hdmi_runtime_get(void)
{
int r;
DSSDBG("hdmi_runtime_get\n");
r = pm_runtime_resume_and_get(&hdmi.pdev->dev);
if (WARN_ON(r < 0))
return r;
return 0;
}
static void hdmi_runtime_put(void)
{
int r;
DSSDBG("hdmi_runtime_put\n");
r = pm_runtime_put_sync(&hdmi.pdev->dev);
WARN_ON(r < 0 && r != -ENOSYS);
}
static irqreturn_t hdmi_irq_handler(int irq, void *data)
{
struct hdmi_wp_data *wp = data;
u32 irqstatus;
irqstatus = hdmi_wp_get_irqstatus(wp);
hdmi_wp_set_irqstatus(wp, irqstatus);
if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
/*
* If we get both connect and disconnect interrupts at the same
* time, turn off the PHY, clear interrupts, and restart, which
* raises connect interrupt if a cable is connected, or nothing
* if cable is not connected.
*/
hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
HDMI_IRQ_LINK_DISCONNECT);
hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
} else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
}
return IRQ_HANDLED;
}
static int hdmi_init_regulator(void)
{
struct regulator *reg;
if (hdmi.vdda_reg != NULL)
return 0;
reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
if (IS_ERR(reg)) {
if (PTR_ERR(reg) != -EPROBE_DEFER)
DSSERR("can't get VDDA regulator\n");
return PTR_ERR(reg);
}
hdmi.vdda_reg = reg;
return 0;
}
static int hdmi_power_on_core(struct omap_dss_device *dssdev)
{
int r;
r = regulator_enable(hdmi.vdda_reg);
if (r)
return r;
r = hdmi_runtime_get();
if (r)
goto err_runtime_get;
/* Make selection of HDMI in DSS */
dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
hdmi.core_enabled = true;
return 0;
err_runtime_get:
regulator_disable(hdmi.vdda_reg);
return r;
}
static void hdmi_power_off_core(struct omap_dss_device *dssdev)
{
hdmi.core_enabled = false;
hdmi_runtime_put();
regulator_disable(hdmi.vdda_reg);
}
static int hdmi_power_on_full(struct omap_dss_device *dssdev)
{
int r;
struct omap_video_timings *p;
struct omap_overlay_manager *mgr = hdmi.output.manager;
struct hdmi_wp_data *wp = &hdmi.wp;
struct dss_pll_clock_info hdmi_cinfo = { 0 };
r = hdmi_power_on_core(dssdev);
if (r)
return r;
/* disable and clear irqs */
hdmi_wp_clear_irqenable(wp, 0xffffffff);
hdmi_wp_set_irqstatus(wp, 0xffffffff);
p = &hdmi.cfg.timings;
DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);
r = dss_pll_enable(&hdmi.pll.pll);
if (r) {
DSSERR("Failed to enable PLL\n");
goto err_pll_enable;
}
r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
if (r) {
DSSERR("Failed to configure PLL\n");
goto err_pll_cfg;
}
r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
hdmi_cinfo.clkout[0]);
if (r) {
DSSDBG("Failed to configure PHY\n");
goto err_phy_cfg;
}
r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
if (r)
goto err_phy_pwr;
hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
/* bypass TV gamma table */
dispc_enable_gamma_table(0);
/* tv size */
dss_mgr_set_timings(mgr, p);
r = hdmi_wp_video_start(&hdmi.wp);
if (r)
goto err_vid_enable;
r = dss_mgr_enable(mgr);
if (r)
goto err_mgr_enable;
hdmi_wp_set_irqenable(wp,
HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
return 0;
err_mgr_enable:
hdmi_wp_video_stop(&hdmi.wp);
err_vid_enable:
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
err_phy_pwr:
err_phy_cfg:
err_pll_cfg:
dss_pll_disable(&hdmi.pll.pll);
err_pll_enable:
hdmi_power_off_core(dssdev);
return -EIO;
}
static void hdmi_power_off_full(struct omap_dss_device *dssdev)
{
struct omap_overlay_manager *mgr = hdmi.output.manager;
hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
dss_mgr_disable(mgr);
hdmi_wp_video_stop(&hdmi.wp);
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
dss_pll_disable(&hdmi.pll.pll);
hdmi_power_off_core(dssdev);
}
static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
struct omap_dss_device *out = &hdmi.output;
if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
return -EINVAL;
return 0;
}
static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
mutex_lock(&hdmi.lock);
hdmi.cfg.timings = *timings;
dispc_set_tv_pclk(timings->pixelclock);
mutex_unlock(&hdmi.lock);
}
static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
*timings = hdmi.cfg.timings;
}
static void hdmi_dump_regs(struct seq_file *s)
{
mutex_lock(&hdmi.lock);
if (hdmi_runtime_get()) {
mutex_unlock(&hdmi.lock);
return;
}
hdmi_wp_dump(&hdmi.wp, s);
hdmi_pll_dump(&hdmi.pll, s);
hdmi_phy_dump(&hdmi.phy, s);
hdmi4_core_dump(&hdmi.core, s);
hdmi_runtime_put();
mutex_unlock(&hdmi.lock);
}
static int read_edid(u8 *buf, int len)
{
int r;
mutex_lock(&hdmi.lock);
r = hdmi_runtime_get();
BUG_ON(r);
r = hdmi4_read_edid(&hdmi.core, buf, len);
hdmi_runtime_put();
mutex_unlock(&hdmi.lock);
return r;
}
static void hdmi_start_audio_stream(struct omap_hdmi *hd)
{
hdmi_wp_audio_enable(&hd->wp, true);
hdmi4_audio_start(&hd->core, &hd->wp);
}
static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
{
hdmi4_audio_stop(&hd->core, &hd->wp);
hdmi_wp_audio_enable(&hd->wp, false);
}
static int hdmi_display_enable(struct omap_dss_device *dssdev)
{
struct omap_dss_device *out = &hdmi.output;
unsigned long flags;
int r = 0;
DSSDBG("ENTER hdmi_display_enable\n");
mutex_lock(&hdmi.lock);
if (out->manager == NULL) {
DSSERR("failed to enable display: no output/manager\n");
r = -ENODEV;
goto err0;
}
r = hdmi_power_on_full(dssdev);
if (r) {
DSSERR("failed to power on device\n");
goto err0;
}
if (hdmi.audio_configured) {
r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
hdmi.cfg.timings.pixelclock);
if (r) {
DSSERR("Error restoring audio configuration: %d", r);
hdmi.audio_abort_cb(&hdmi.pdev->dev);
hdmi.audio_configured = false;
}
}
spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
if (hdmi.audio_configured && hdmi.audio_playing)
hdmi_start_audio_stream(&hdmi);
hdmi.display_enabled = true;
spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
mutex_unlock(&hdmi.lock);
return 0;
err0:
mutex_unlock(&hdmi.lock);
return r;
}
static void hdmi_display_disable(struct omap_dss_device *dssdev)
{
unsigned long flags;
DSSDBG("Enter hdmi_display_disable\n");
mutex_lock(&hdmi.lock);
spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
hdmi_stop_audio_stream(&hdmi);
hdmi.display_enabled = false;
spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
hdmi_power_off_full(dssdev);
mutex_unlock(&hdmi.lock);
}
static int hdmi_core_enable(struct omap_dss_device *dssdev)
{
int r = 0;
DSSDBG("ENTER omapdss_hdmi_core_enable\n");
mutex_lock(&hdmi.lock);
r = hdmi_power_on_core(dssdev);
if (r) {
DSSERR("failed to power on device\n");
goto err0;
}
mutex_unlock(&hdmi.lock);
return 0;
err0:
mutex_unlock(&hdmi.lock);
return r;
}
static void hdmi_core_disable(struct omap_dss_device *dssdev)
{
DSSDBG("Enter omapdss_hdmi_core_disable\n");
mutex_lock(&hdmi.lock);
hdmi_power_off_core(dssdev);
mutex_unlock(&hdmi.lock);
}
static int hdmi_connect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct omap_overlay_manager *mgr;
int r;
r = hdmi_init_regulator();
if (r)
return r;
mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
if (!mgr)
return -ENODEV;
r = dss_mgr_connect(mgr, dssdev);
if (r)
return r;
r = omapdss_output_set_device(dssdev, dst);
if (r) {
DSSERR("failed to connect output to new device: %s\n",
dst->name);
dss_mgr_disconnect(mgr, dssdev);
return r;
}
return 0;
}
static void hdmi_disconnect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
WARN_ON(dst != dssdev->dst);
if (dst != dssdev->dst)
return;
omapdss_output_unset_device(dssdev);
if (dssdev->manager)
dss_mgr_disconnect(dssdev->manager, dssdev);
}
static int hdmi_read_edid(struct omap_dss_device *dssdev,
u8 *edid, int len)
{
bool need_enable = !hdmi.core_enabled;
int r;
if (need_enable) {
r = hdmi_core_enable(dssdev);
if (r)
return r;
}
r = read_edid(edid, len);
if (need_enable)
hdmi_core_disable(dssdev);
return r;
}
static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
const struct hdmi_avi_infoframe *avi)
{
hdmi.cfg.infoframe = *avi;
return 0;
}
static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
bool hdmi_mode)
{
hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
return 0;
}
static const struct omapdss_hdmi_ops hdmi_ops = {
.connect = hdmi_connect,
.disconnect = hdmi_disconnect,
.enable = hdmi_display_enable,
.disable = hdmi_display_disable,
.check_timings = hdmi_display_check_timing,
.set_timings = hdmi_display_set_timing,
.get_timings = hdmi_display_get_timings,
.read_edid = hdmi_read_edid,
.set_infoframe = hdmi_set_infoframe,
.set_hdmi_mode = hdmi_set_hdmi_mode,
};
static void hdmi_init_output(struct platform_device *pdev)
{
struct omap_dss_device *out = &hdmi.output;
out->dev = &pdev->dev;
out->id = OMAP_DSS_OUTPUT_HDMI;
out->output_type = OMAP_DISPLAY_TYPE_HDMI;
out->name = "hdmi.0";
out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
out->ops.hdmi = &hdmi_ops;
out->owner = THIS_MODULE;
omapdss_register_output(out);
}
static void hdmi_uninit_output(struct platform_device *pdev)
{
struct omap_dss_device *out = &hdmi.output;
omapdss_unregister_output(out);
}
static int hdmi_probe_of(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct device_node *ep;
int r;
ep = omapdss_of_get_first_endpoint(node);
if (!ep)
return 0;
r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
if (r)
goto err;
of_node_put(ep);
return 0;
err:
of_node_put(ep);
return r;
}
/* Audio callbacks */
static int hdmi_audio_startup(struct device *dev,
void (*abort_cb)(struct device *dev))
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
int ret = 0;
mutex_lock(&hd->lock);
if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
ret = -EPERM;
goto out;
}
hd->audio_abort_cb = abort_cb;
out:
mutex_unlock(&hd->lock);
return ret;
}
static int hdmi_audio_shutdown(struct device *dev)
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
mutex_lock(&hd->lock);
hd->audio_abort_cb = NULL;
hd->audio_configured = false;
hd->audio_playing = false;
mutex_unlock(&hd->lock);
return 0;
}
static int hdmi_audio_start(struct device *dev)
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
unsigned long flags;
WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
spin_lock_irqsave(&hd->audio_playing_lock, flags);
if (hd->display_enabled)
hdmi_start_audio_stream(hd);
hd->audio_playing = true;
spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
return 0;
}
static void hdmi_audio_stop(struct device *dev)
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
unsigned long flags;
WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
spin_lock_irqsave(&hd->audio_playing_lock, flags);
if (hd->display_enabled)
hdmi_stop_audio_stream(hd);
hd->audio_playing = false;
spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
}
static int hdmi_audio_config(struct device *dev,
struct omap_dss_audio *dss_audio)
{
struct omap_hdmi *hd = dev_get_drvdata(dev);
int ret;
mutex_lock(&hd->lock);
if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
ret = -EPERM;
goto out;
}
ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,
hd->cfg.timings.pixelclock);
if (!ret) {
hd->audio_configured = true;
hd->audio_config = *dss_audio;
}
out:
mutex_unlock(&hd->lock);
return ret;
}
static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
.audio_startup = hdmi_audio_startup,
.audio_shutdown = hdmi_audio_shutdown,
.audio_start = hdmi_audio_start,
.audio_stop = hdmi_audio_stop,
.audio_config = hdmi_audio_config,
};
static int hdmi_audio_register(struct device *dev)
{
struct omap_hdmi_audio_pdata pdata = {
.dev = dev,
.version = 4,
.audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
.ops = &hdmi_audio_ops,
};
hdmi.audio_pdev = platform_device_register_data(
dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
&pdata, sizeof(pdata));
return PTR_ERR_OR_ZERO(hdmi.audio_pdev);
}
/* HDMI HW IP initialisation */
static int hdmi4_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
int r;
int irq;
hdmi.pdev = pdev;
platform_set_drvdata(pdev, &hdmi);
mutex_init(&hdmi.lock);
spin_lock_init(&hdmi.audio_playing_lock);
if (pdev->dev.of_node) {
r = hdmi_probe_of(pdev);
if (r)
return r;
}
r = hdmi_wp_init(pdev, &hdmi.wp);
if (r)
return r;
r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
if (r)
return r;
r = hdmi_phy_init(pdev, &hdmi.phy);
if (r)
goto err;
r = hdmi4_core_init(pdev, &hdmi.core);
if (r)
goto err;
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
DSSERR("platform_get_irq failed\n");
r = -ENODEV;
goto err;
}
r = devm_request_threaded_irq(&pdev->dev, irq,
NULL, hdmi_irq_handler,
IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
if (r) {
DSSERR("HDMI IRQ request failed\n");
goto err;
}
pm_runtime_enable(&pdev->dev);
hdmi_init_output(pdev);
r = hdmi_audio_register(&pdev->dev);
if (r) {
DSSERR("Registering HDMI audio failed\n");
hdmi_uninit_output(pdev);
pm_runtime_disable(&pdev->dev);
return r;
}
dss_debugfs_create_file("hdmi", hdmi_dump_regs);
return 0;
err:
hdmi_pll_uninit(&hdmi.pll);
return r;
}
static void hdmi4_unbind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
if (hdmi.audio_pdev)
platform_device_unregister(hdmi.audio_pdev);
hdmi_uninit_output(pdev);
hdmi_pll_uninit(&hdmi.pll);
pm_runtime_disable(&pdev->dev);
}
static const struct component_ops hdmi4_component_ops = {
.bind = hdmi4_bind,
.unbind = hdmi4_unbind,
};
static int hdmi4_probe(struct platform_device *pdev)
{
return component_add(&pdev->dev, &hdmi4_component_ops);
}
static void hdmi4_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &hdmi4_component_ops);
}
static int hdmi_runtime_suspend(struct device *dev)
{
dispc_runtime_put();
return 0;
}
static int hdmi_runtime_resume(struct device *dev)
{
int r;
r = dispc_runtime_get();
if (r < 0)
return r;
return 0;
}
static const struct dev_pm_ops hdmi_pm_ops = {
.runtime_suspend = hdmi_runtime_suspend,
.runtime_resume = hdmi_runtime_resume,
};
static const struct of_device_id hdmi_of_match[] = {
{ .compatible = "ti,omap4-hdmi", },
{},
};
static struct platform_driver omapdss_hdmihw_driver = {
.probe = hdmi4_probe,
.remove_new = hdmi4_remove,
.driver = {
.name = "omapdss_hdmi",
.pm = &hdmi_pm_ops,
.of_match_table = hdmi_of_match,
.suppress_bind_attrs = true,
},
};
int __init hdmi4_init_platform_driver(void)
{
return platform_driver_register(&omapdss_hdmihw_driver);
}
void hdmi4_uninit_platform_driver(void)
{
platform_driver_unregister(&omapdss_hdmihw_driver);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/hdmi4.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/overlay.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "OVERLAY"
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/sysfs.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
static int num_overlays;
static struct omap_overlay *overlays;
int omap_dss_get_num_overlays(void)
{
return num_overlays;
}
EXPORT_SYMBOL(omap_dss_get_num_overlays);
struct omap_overlay *omap_dss_get_overlay(int num)
{
if (num >= num_overlays)
return NULL;
return &overlays[num];
}
EXPORT_SYMBOL(omap_dss_get_overlay);
void dss_init_overlays(struct platform_device *pdev)
{
int i, r;
num_overlays = dss_feat_get_num_ovls();
overlays = kcalloc(num_overlays, sizeof(struct omap_overlay),
GFP_KERNEL);
BUG_ON(overlays == NULL);
for (i = 0; i < num_overlays; ++i) {
struct omap_overlay *ovl = &overlays[i];
switch (i) {
case 0:
ovl->name = "gfx";
ovl->id = OMAP_DSS_GFX;
break;
case 1:
ovl->name = "vid1";
ovl->id = OMAP_DSS_VIDEO1;
break;
case 2:
ovl->name = "vid2";
ovl->id = OMAP_DSS_VIDEO2;
break;
case 3:
ovl->name = "vid3";
ovl->id = OMAP_DSS_VIDEO3;
break;
}
ovl->caps = dss_feat_get_overlay_caps(ovl->id);
ovl->supported_modes =
dss_feat_get_supported_color_modes(ovl->id);
r = dss_overlay_kobj_init(ovl, pdev);
if (r)
DSSERR("failed to create sysfs file\n");
}
}
void dss_uninit_overlays(struct platform_device *pdev)
{
int i;
for (i = 0; i < num_overlays; ++i) {
struct omap_overlay *ovl = &overlays[i];
dss_overlay_kobj_uninit(ovl);
}
kfree(overlays);
overlays = NULL;
num_overlays = 0;
}
int dss_ovl_simple_check(struct omap_overlay *ovl,
const struct omap_overlay_info *info)
{
if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
if (info->out_width != 0 && info->width != info->out_width) {
DSSERR("check_overlay: overlay %d doesn't support "
"scaling\n", ovl->id);
return -EINVAL;
}
if (info->out_height != 0 && info->height != info->out_height) {
DSSERR("check_overlay: overlay %d doesn't support "
"scaling\n", ovl->id);
return -EINVAL;
}
}
if ((ovl->supported_modes & info->color_mode) == 0) {
DSSERR("check_overlay: overlay %d doesn't support mode %d\n",
ovl->id, info->color_mode);
return -EINVAL;
}
if (info->zorder >= omap_dss_get_num_overlays()) {
DSSERR("check_overlay: zorder %d too high\n", info->zorder);
return -EINVAL;
}
if (dss_feat_rotation_type_supported(info->rotation_type) == 0) {
DSSERR("check_overlay: rotation type %d not supported\n",
info->rotation_type);
return -EINVAL;
}
return 0;
}
int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
const struct omap_video_timings *mgr_timings)
{
u16 outw, outh;
u16 dw, dh;
dw = mgr_timings->x_res;
dh = mgr_timings->y_res;
if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
outw = info->width;
outh = info->height;
} else {
if (info->out_width == 0)
outw = info->width;
else
outw = info->out_width;
if (info->out_height == 0)
outh = info->height;
else
outh = info->out_height;
}
if (dw < info->pos_x + outw) {
DSSERR("overlay %d horizontally not inside the display area "
"(%d + %d >= %d)\n",
ovl->id, info->pos_x, outw, dw);
return -EINVAL;
}
if (dh < info->pos_y + outh) {
DSSERR("overlay %d vertically not inside the display area "
"(%d + %d >= %d)\n",
ovl->id, info->pos_y, outh, dh);
return -EINVAL;
}
return 0;
}
/*
* Checks if replication logic should be used. Only use when overlay is in
* RGB12U or RGB16 mode, and video port width interface is 18bpp or 24bpp
*/
bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
enum omap_color_mode mode)
{
if (mode != OMAP_DSS_COLOR_RGB12U && mode != OMAP_DSS_COLOR_RGB16)
return false;
return config.video_port_width > 16;
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/overlay.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/dsi.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*/
#define DSS_SUBSYS_NAME "DSI"
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/module.h>
#include <linux/semaphore.h>
#include <linux/seq_file.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/debugfs.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/component.h>
#include <video/omapfb_dss.h>
#include <video/mipi_display.h>
#include "dss.h"
#include "dss_features.h"
#define DSI_CATCH_MISSING_TE
struct dsi_reg { u16 module; u16 idx; };
#define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
/* DSI Protocol Engine */
#define DSI_PROTO 0
#define DSI_PROTO_SZ 0x200
#define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
#define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
#define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
#define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
#define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
#define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
#define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
#define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
#define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
#define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
#define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
#define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
#define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
#define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
#define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
#define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
#define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
#define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
#define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
#define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
#define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
#define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
#define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
#define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
#define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
#define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
#define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
/* DSIPHY_SCP */
#define DSI_PHY 1
#define DSI_PHY_OFFSET 0x200
#define DSI_PHY_SZ 0x40
#define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
#define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
#define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
#define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
#define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
/* DSI_PLL_CTRL_SCP */
#define DSI_PLL 2
#define DSI_PLL_OFFSET 0x300
#define DSI_PLL_SZ 0x20
#define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
#define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
#define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
#define REG_GET(dsidev, idx, start, end) \
FLD_GET(dsi_read_reg(dsidev, idx), start, end)
#define REG_FLD_MOD(dsidev, idx, val, start, end) \
dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
/* Global interrupts */
#define DSI_IRQ_VC0 (1 << 0)
#define DSI_IRQ_VC1 (1 << 1)
#define DSI_IRQ_VC2 (1 << 2)
#define DSI_IRQ_VC3 (1 << 3)
#define DSI_IRQ_WAKEUP (1 << 4)
#define DSI_IRQ_RESYNC (1 << 5)
#define DSI_IRQ_PLL_LOCK (1 << 7)
#define DSI_IRQ_PLL_UNLOCK (1 << 8)
#define DSI_IRQ_PLL_RECALL (1 << 9)
#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
#define DSI_IRQ_TE_TRIGGER (1 << 16)
#define DSI_IRQ_ACK_TRIGGER (1 << 17)
#define DSI_IRQ_SYNC_LOST (1 << 18)
#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
#define DSI_IRQ_TA_TIMEOUT (1 << 20)
#define DSI_IRQ_ERROR_MASK \
(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
DSI_IRQ_TA_TIMEOUT)
#define DSI_IRQ_CHANNEL_MASK 0xf
/* Virtual channel interrupts */
#define DSI_VC_IRQ_CS (1 << 0)
#define DSI_VC_IRQ_ECC_CORR (1 << 1)
#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
#define DSI_VC_IRQ_BTA (1 << 5)
#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
#define DSI_VC_IRQ_ERROR_MASK \
(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
DSI_VC_IRQ_FIFO_TX_UDF)
/* ComplexIO interrupts */
#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
#define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
#define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
#define DSI_CIO_IRQ_ERRESC4 (1 << 8)
#define DSI_CIO_IRQ_ERRESC5 (1 << 9)
#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
#define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
#define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
#define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
#define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
#define DSI_CIO_IRQ_ERROR_MASK \
(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
DSI_CIO_IRQ_ERRSYNCESC5 | \
DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
DSI_CIO_IRQ_ERRESC5 | \
DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
DSI_CIO_IRQ_ERRCONTROL5 | \
DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
static int dsi_display_init_dispc(struct platform_device *dsidev,
struct omap_overlay_manager *mgr);
static void dsi_display_uninit_dispc(struct platform_device *dsidev,
struct omap_overlay_manager *mgr);
static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
/* DSI PLL HSDIV indices */
#define HSDIV_DISPC 0
#define HSDIV_DSI 1
#define DSI_MAX_NR_ISRS 2
#define DSI_MAX_NR_LANES 5
enum dsi_lane_function {
DSI_LANE_UNUSED = 0,
DSI_LANE_CLK,
DSI_LANE_DATA1,
DSI_LANE_DATA2,
DSI_LANE_DATA3,
DSI_LANE_DATA4,
};
struct dsi_lane_config {
enum dsi_lane_function function;
u8 polarity;
};
struct dsi_isr_data {
omap_dsi_isr_t isr;
void *arg;
u32 mask;
};
enum fifo_size {
DSI_FIFO_SIZE_0 = 0,
DSI_FIFO_SIZE_32 = 1,
DSI_FIFO_SIZE_64 = 2,
DSI_FIFO_SIZE_96 = 3,
DSI_FIFO_SIZE_128 = 4,
};
enum dsi_vc_source {
DSI_VC_SOURCE_L4 = 0,
DSI_VC_SOURCE_VP,
};
struct dsi_irq_stats {
unsigned long last_reset;
unsigned irq_count;
unsigned dsi_irqs[32];
unsigned vc_irqs[4][32];
unsigned cio_irqs[32];
};
struct dsi_isr_tables {
struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
};
struct dsi_clk_calc_ctx {
struct platform_device *dsidev;
struct dss_pll *pll;
/* inputs */
const struct omap_dss_dsi_config *config;
unsigned long req_pck_min, req_pck_nom, req_pck_max;
/* outputs */
struct dss_pll_clock_info dsi_cinfo;
struct dispc_clock_info dispc_cinfo;
struct omap_video_timings dispc_vm;
struct omap_dss_dsi_videomode_timings dsi_vm;
};
struct dsi_lp_clock_info {
unsigned long lp_clk;
u16 lp_clk_div;
};
struct dsi_data {
struct platform_device *pdev;
void __iomem *proto_base;
void __iomem *phy_base;
void __iomem *pll_base;
int module_id;
int irq;
bool is_enabled;
struct clk *dss_clk;
struct dispc_clock_info user_dispc_cinfo;
struct dss_pll_clock_info user_dsi_cinfo;
struct dsi_lp_clock_info user_lp_cinfo;
struct dsi_lp_clock_info current_lp_cinfo;
struct dss_pll pll;
bool vdds_dsi_enabled;
struct regulator *vdds_dsi_reg;
struct {
enum dsi_vc_source source;
struct omap_dss_device *dssdev;
enum fifo_size tx_fifo_size;
enum fifo_size rx_fifo_size;
int vc_id;
} vc[4];
struct mutex lock;
struct semaphore bus_lock;
spinlock_t irq_lock;
struct dsi_isr_tables isr_tables;
/* space for a copy used by the interrupt handler */
struct dsi_isr_tables isr_tables_copy;
int update_channel;
#ifdef DSI_PERF_MEASURE
unsigned update_bytes;
#endif
bool te_enabled;
bool ulps_enabled;
void (*framedone_callback)(int, void *);
void *framedone_data;
struct delayed_work framedone_timeout_work;
#ifdef DSI_CATCH_MISSING_TE
struct timer_list te_timer;
#endif
unsigned long cache_req_pck;
unsigned long cache_clk_freq;
struct dss_pll_clock_info cache_cinfo;
u32 errors;
spinlock_t errors_lock;
#ifdef DSI_PERF_MEASURE
ktime_t perf_setup_time;
ktime_t perf_start_time;
#endif
int debug_read;
int debug_write;
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
spinlock_t irq_stats_lock;
struct dsi_irq_stats irq_stats;
#endif
unsigned num_lanes_supported;
unsigned line_buffer_size;
struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
unsigned num_lanes_used;
unsigned scp_clk_refcount;
struct dss_lcd_mgr_config mgr_config;
struct omap_video_timings timings;
enum omap_dss_dsi_pixel_format pix_fmt;
enum omap_dss_dsi_mode mode;
struct omap_dss_dsi_videomode_timings vm_timings;
struct omap_dss_device output;
};
struct dsi_packet_sent_handler_data {
struct platform_device *dsidev;
struct completion *completion;
};
struct dsi_module_id_data {
u32 address;
int id;
};
static const struct of_device_id dsi_of_match[];
#ifdef DSI_PERF_MEASURE
static bool dsi_perf;
module_param(dsi_perf, bool, 0644);
#endif
static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
{
return platform_get_drvdata(dsidev);
}
static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
{
return to_platform_device(dssdev->dev);
}
static struct platform_device *dsi_get_dsidev_from_id(int module)
{
struct omap_dss_device *out;
enum omap_dss_output_id id;
switch (module) {
case 0:
id = OMAP_DSS_OUTPUT_DSI1;
break;
case 1:
id = OMAP_DSS_OUTPUT_DSI2;
break;
default:
return NULL;
}
out = omap_dss_get_output(id);
return out ? to_platform_device(out->dev) : NULL;
}
static inline void dsi_write_reg(struct platform_device *dsidev,
const struct dsi_reg idx, u32 val)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
void __iomem *base;
switch(idx.module) {
case DSI_PROTO: base = dsi->proto_base; break;
case DSI_PHY: base = dsi->phy_base; break;
case DSI_PLL: base = dsi->pll_base; break;
default: return;
}
__raw_writel(val, base + idx.idx);
}
static inline u32 dsi_read_reg(struct platform_device *dsidev,
const struct dsi_reg idx)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
void __iomem *base;
switch(idx.module) {
case DSI_PROTO: base = dsi->proto_base; break;
case DSI_PHY: base = dsi->phy_base; break;
case DSI_PLL: base = dsi->pll_base; break;
default: return 0;
}
return __raw_readl(base + idx.idx);
}
static void dsi_bus_lock(struct omap_dss_device *dssdev)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
down(&dsi->bus_lock);
}
static void dsi_bus_unlock(struct omap_dss_device *dssdev)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
up(&dsi->bus_lock);
}
static bool dsi_bus_is_locked(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
return dsi->bus_lock.count == 0;
}
static void dsi_completion_handler(void *data, u32 mask)
{
complete((struct completion *)data);
}
static inline int wait_for_bit_change(struct platform_device *dsidev,
const struct dsi_reg idx, int bitnum, int value)
{
unsigned long timeout;
ktime_t wait;
int t;
/* first busyloop to see if the bit changes right away */
t = 100;
while (t-- > 0) {
if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
return value;
}
/* then loop for 500ms, sleeping for 1ms in between */
timeout = jiffies + msecs_to_jiffies(500);
while (time_before(jiffies, timeout)) {
if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
return value;
wait = ns_to_ktime(1000 * 1000);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
}
return !value;
}
u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
{
switch (fmt) {
case OMAP_DSS_DSI_FMT_RGB888:
case OMAP_DSS_DSI_FMT_RGB666:
return 24;
case OMAP_DSS_DSI_FMT_RGB666_PACKED:
return 18;
case OMAP_DSS_DSI_FMT_RGB565:
return 16;
default:
BUG();
return 0;
}
}
#ifdef DSI_PERF_MEASURE
static void dsi_perf_mark_setup(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
dsi->perf_setup_time = ktime_get();
}
static void dsi_perf_mark_start(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
dsi->perf_start_time = ktime_get();
}
static void dsi_perf_show(struct platform_device *dsidev, const char *name)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
ktime_t t, setup_time, trans_time;
u32 total_bytes;
u32 setup_us, trans_us, total_us;
if (!dsi_perf)
return;
t = ktime_get();
setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
setup_us = (u32)ktime_to_us(setup_time);
if (setup_us == 0)
setup_us = 1;
trans_time = ktime_sub(t, dsi->perf_start_time);
trans_us = (u32)ktime_to_us(trans_time);
if (trans_us == 0)
trans_us = 1;
total_us = setup_us + trans_us;
total_bytes = dsi->update_bytes;
printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
"%u bytes, %u kbytes/sec\n",
name,
setup_us,
trans_us,
total_us,
1000*1000 / total_us,
total_bytes,
total_bytes * 1000 / total_us);
}
#else
static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
{
}
static inline void dsi_perf_mark_start(struct platform_device *dsidev)
{
}
static inline void dsi_perf_show(struct platform_device *dsidev,
const char *name)
{
}
#endif
static int verbose_irq;
static void print_irq_status(u32 status)
{
if (status == 0)
return;
if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
return;
#define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
status,
verbose_irq ? PIS(VC0) : "",
verbose_irq ? PIS(VC1) : "",
verbose_irq ? PIS(VC2) : "",
verbose_irq ? PIS(VC3) : "",
PIS(WAKEUP),
PIS(RESYNC),
PIS(PLL_LOCK),
PIS(PLL_UNLOCK),
PIS(PLL_RECALL),
PIS(COMPLEXIO_ERR),
PIS(HS_TX_TIMEOUT),
PIS(LP_RX_TIMEOUT),
PIS(TE_TRIGGER),
PIS(ACK_TRIGGER),
PIS(SYNC_LOST),
PIS(LDO_POWER_GOOD),
PIS(TA_TIMEOUT));
#undef PIS
}
static void print_irq_status_vc(int channel, u32 status)
{
if (status == 0)
return;
if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
return;
#define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
channel,
status,
PIS(CS),
PIS(ECC_CORR),
PIS(ECC_NO_CORR),
verbose_irq ? PIS(PACKET_SENT) : "",
PIS(BTA),
PIS(FIFO_TX_OVF),
PIS(FIFO_RX_OVF),
PIS(FIFO_TX_UDF),
PIS(PP_BUSY_CHANGE));
#undef PIS
}
static void print_irq_status_cio(u32 status)
{
if (status == 0)
return;
#define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
status,
PIS(ERRSYNCESC1),
PIS(ERRSYNCESC2),
PIS(ERRSYNCESC3),
PIS(ERRESC1),
PIS(ERRESC2),
PIS(ERRESC3),
PIS(ERRCONTROL1),
PIS(ERRCONTROL2),
PIS(ERRCONTROL3),
PIS(STATEULPS1),
PIS(STATEULPS2),
PIS(STATEULPS3),
PIS(ERRCONTENTIONLP0_1),
PIS(ERRCONTENTIONLP1_1),
PIS(ERRCONTENTIONLP0_2),
PIS(ERRCONTENTIONLP1_2),
PIS(ERRCONTENTIONLP0_3),
PIS(ERRCONTENTIONLP1_3),
PIS(ULPSACTIVENOT_ALL0),
PIS(ULPSACTIVENOT_ALL1));
#undef PIS
}
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
u32 *vcstatus, u32 ciostatus)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
spin_lock(&dsi->irq_stats_lock);
dsi->irq_stats.irq_count++;
dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
for (i = 0; i < 4; ++i)
dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
spin_unlock(&dsi->irq_stats_lock);
}
#else
#define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
#endif
static int debug_irq;
static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
u32 *vcstatus, u32 ciostatus)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
if (irqstatus & DSI_IRQ_ERROR_MASK) {
DSSERR("DSI error, irqstatus %x\n", irqstatus);
print_irq_status(irqstatus);
spin_lock(&dsi->errors_lock);
dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
spin_unlock(&dsi->errors_lock);
} else if (debug_irq) {
print_irq_status(irqstatus);
}
for (i = 0; i < 4; ++i) {
if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
i, vcstatus[i]);
print_irq_status_vc(i, vcstatus[i]);
} else if (debug_irq) {
print_irq_status_vc(i, vcstatus[i]);
}
}
if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
print_irq_status_cio(ciostatus);
} else if (debug_irq) {
print_irq_status_cio(ciostatus);
}
}
static void dsi_call_isrs(struct dsi_isr_data *isr_array,
unsigned isr_array_size, u32 irqstatus)
{
struct dsi_isr_data *isr_data;
int i;
for (i = 0; i < isr_array_size; i++) {
isr_data = &isr_array[i];
if (isr_data->isr && isr_data->mask & irqstatus)
isr_data->isr(isr_data->arg, irqstatus);
}
}
static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
u32 irqstatus, u32 *vcstatus, u32 ciostatus)
{
int i;
dsi_call_isrs(isr_tables->isr_table,
ARRAY_SIZE(isr_tables->isr_table),
irqstatus);
for (i = 0; i < 4; ++i) {
if (vcstatus[i] == 0)
continue;
dsi_call_isrs(isr_tables->isr_table_vc[i],
ARRAY_SIZE(isr_tables->isr_table_vc[i]),
vcstatus[i]);
}
if (ciostatus != 0)
dsi_call_isrs(isr_tables->isr_table_cio,
ARRAY_SIZE(isr_tables->isr_table_cio),
ciostatus);
}
static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
{
struct platform_device *dsidev;
struct dsi_data *dsi;
u32 irqstatus, vcstatus[4], ciostatus;
int i;
dsidev = (struct platform_device *) arg;
dsi = dsi_get_dsidrv_data(dsidev);
if (!dsi->is_enabled)
return IRQ_NONE;
spin_lock(&dsi->irq_lock);
irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
/* IRQ is not for us */
if (!irqstatus) {
spin_unlock(&dsi->irq_lock);
return IRQ_NONE;
}
dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
/* flush posted write */
dsi_read_reg(dsidev, DSI_IRQSTATUS);
for (i = 0; i < 4; ++i) {
if ((irqstatus & (1 << i)) == 0) {
vcstatus[i] = 0;
continue;
}
vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
/* flush posted write */
dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
}
if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
/* flush posted write */
dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
} else {
ciostatus = 0;
}
#ifdef DSI_CATCH_MISSING_TE
if (irqstatus & DSI_IRQ_TE_TRIGGER)
del_timer(&dsi->te_timer);
#endif
/* make a copy and unlock, so that isrs can unregister
* themselves */
memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
sizeof(dsi->isr_tables));
spin_unlock(&dsi->irq_lock);
dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
return IRQ_HANDLED;
}
/* dsi->irq_lock has to be locked by the caller */
static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
struct dsi_isr_data *isr_array,
unsigned isr_array_size, u32 default_mask,
const struct dsi_reg enable_reg,
const struct dsi_reg status_reg)
{
struct dsi_isr_data *isr_data;
u32 mask;
u32 old_mask;
int i;
mask = default_mask;
for (i = 0; i < isr_array_size; i++) {
isr_data = &isr_array[i];
if (isr_data->isr == NULL)
continue;
mask |= isr_data->mask;
}
old_mask = dsi_read_reg(dsidev, enable_reg);
/* clear the irqstatus for newly enabled irqs */
dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
dsi_write_reg(dsidev, enable_reg, mask);
/* flush posted writes */
dsi_read_reg(dsidev, enable_reg);
dsi_read_reg(dsidev, status_reg);
}
/* dsi->irq_lock has to be locked by the caller */
static void _omap_dsi_set_irqs(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 mask = DSI_IRQ_ERROR_MASK;
#ifdef DSI_CATCH_MISSING_TE
mask |= DSI_IRQ_TE_TRIGGER;
#endif
_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
DSI_IRQENABLE, DSI_IRQSTATUS);
}
/* dsi->irq_lock has to be locked by the caller */
static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
DSI_VC_IRQ_ERROR_MASK,
DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
}
/* dsi->irq_lock has to be locked by the caller */
static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
DSI_CIO_IRQ_ERROR_MASK,
DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
}
static void _dsi_initialize_irq(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int vc;
spin_lock_irqsave(&dsi->irq_lock, flags);
memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
_omap_dsi_set_irqs(dsidev);
for (vc = 0; vc < 4; ++vc)
_omap_dsi_set_irqs_vc(dsidev, vc);
_omap_dsi_set_irqs_cio(dsidev);
spin_unlock_irqrestore(&dsi->irq_lock, flags);
}
static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
struct dsi_isr_data *isr_array, unsigned isr_array_size)
{
struct dsi_isr_data *isr_data;
int free_idx;
int i;
BUG_ON(isr == NULL);
/* check for duplicate entry and find a free slot */
free_idx = -1;
for (i = 0; i < isr_array_size; i++) {
isr_data = &isr_array[i];
if (isr_data->isr == isr && isr_data->arg == arg &&
isr_data->mask == mask) {
return -EINVAL;
}
if (isr_data->isr == NULL && free_idx == -1)
free_idx = i;
}
if (free_idx == -1)
return -EBUSY;
isr_data = &isr_array[free_idx];
isr_data->isr = isr;
isr_data->arg = arg;
isr_data->mask = mask;
return 0;
}
static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
struct dsi_isr_data *isr_array, unsigned isr_array_size)
{
struct dsi_isr_data *isr_data;
int i;
for (i = 0; i < isr_array_size; i++) {
isr_data = &isr_array[i];
if (isr_data->isr != isr || isr_data->arg != arg ||
isr_data->mask != mask)
continue;
isr_data->isr = NULL;
isr_data->arg = NULL;
isr_data->mask = 0;
return 0;
}
return -EINVAL;
}
static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
void *arg, u32 mask)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
spin_lock_irqsave(&dsi->irq_lock, flags);
r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
ARRAY_SIZE(dsi->isr_tables.isr_table));
if (r == 0)
_omap_dsi_set_irqs(dsidev);
spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
static int dsi_unregister_isr(struct platform_device *dsidev,
omap_dsi_isr_t isr, void *arg, u32 mask)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
spin_lock_irqsave(&dsi->irq_lock, flags);
r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
ARRAY_SIZE(dsi->isr_tables.isr_table));
if (r == 0)
_omap_dsi_set_irqs(dsidev);
spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
omap_dsi_isr_t isr, void *arg, u32 mask)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
spin_lock_irqsave(&dsi->irq_lock, flags);
r = _dsi_register_isr(isr, arg, mask,
dsi->isr_tables.isr_table_vc[channel],
ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
if (r == 0)
_omap_dsi_set_irqs_vc(dsidev, channel);
spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
omap_dsi_isr_t isr, void *arg, u32 mask)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
spin_lock_irqsave(&dsi->irq_lock, flags);
r = _dsi_unregister_isr(isr, arg, mask,
dsi->isr_tables.isr_table_vc[channel],
ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
if (r == 0)
_omap_dsi_set_irqs_vc(dsidev, channel);
spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
static int dsi_register_isr_cio(struct platform_device *dsidev,
omap_dsi_isr_t isr, void *arg, u32 mask)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
spin_lock_irqsave(&dsi->irq_lock, flags);
r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
if (r == 0)
_omap_dsi_set_irqs_cio(dsidev);
spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
static int dsi_unregister_isr_cio(struct platform_device *dsidev,
omap_dsi_isr_t isr, void *arg, u32 mask)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
spin_lock_irqsave(&dsi->irq_lock, flags);
r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
if (r == 0)
_omap_dsi_set_irqs_cio(dsidev);
spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
static u32 dsi_get_errors(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
u32 e;
spin_lock_irqsave(&dsi->errors_lock, flags);
e = dsi->errors;
dsi->errors = 0;
spin_unlock_irqrestore(&dsi->errors_lock, flags);
return e;
}
static int dsi_runtime_get(struct platform_device *dsidev)
{
int r;
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
DSSDBG("dsi_runtime_get\n");
r = pm_runtime_resume_and_get(&dsi->pdev->dev);
if (WARN_ON(r < 0))
return r;
return 0;
}
static void dsi_runtime_put(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r;
DSSDBG("dsi_runtime_put\n");
r = pm_runtime_put_sync(&dsi->pdev->dev);
WARN_ON(r < 0 && r != -ENOSYS);
}
static int dsi_regulator_init(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct regulator *vdds_dsi;
if (dsi->vdds_dsi_reg != NULL)
return 0;
vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
if (IS_ERR(vdds_dsi)) {
if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
DSSERR("can't get DSI VDD regulator\n");
return PTR_ERR(vdds_dsi);
}
dsi->vdds_dsi_reg = vdds_dsi;
return 0;
}
static void _dsi_print_reset_status(struct platform_device *dsidev)
{
int b0, b1, b2;
/* A dummy read using the SCP interface to any DSIPHY register is
* required after DSIPHY reset to complete the reset of the DSI complex
* I/O. */
dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
b0 = 28;
b1 = 27;
b2 = 26;
} else {
b0 = 24;
b1 = 25;
b2 = 26;
}
#define DSI_FLD_GET(fld, start, end)\
FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
DSI_FLD_GET(PLL_STATUS, 0, 0),
DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
#undef DSI_FLD_GET
}
static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
{
DSSDBG("dsi_if_enable(%d)\n", enable);
enable = enable ? 1 : 0;
REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
DSSERR("Failed to set dsi_if_enable to %d\n", enable);
return -EIO;
}
return 0;
}
static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
return dsi->pll.cinfo.clkout[HSDIV_DISPC];
}
static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
return dsi->pll.cinfo.clkout[HSDIV_DSI];
}
static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
return dsi->pll.cinfo.clkdco / 16;
}
static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
{
unsigned long r;
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
/* DSI FCLK source is DSS_CLK_FCK */
r = clk_get_rate(dsi->dss_clk);
} else {
/* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
}
return r;
}
static int dsi_lp_clock_calc(unsigned long dsi_fclk,
unsigned long lp_clk_min, unsigned long lp_clk_max,
struct dsi_lp_clock_info *lp_cinfo)
{
unsigned lp_clk_div;
unsigned long lp_clk;
lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
lp_clk = dsi_fclk / 2 / lp_clk_div;
if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
return -EINVAL;
lp_cinfo->lp_clk_div = lp_clk_div;
lp_cinfo->lp_clk = lp_clk;
return 0;
}
static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long dsi_fclk;
unsigned lp_clk_div;
unsigned long lp_clk;
unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
return -EINVAL;
dsi_fclk = dsi_fclk_rate(dsidev);
lp_clk = dsi_fclk / 2 / lp_clk_div;
DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
dsi->current_lp_cinfo.lp_clk = lp_clk;
dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
/* LP_CLK_DIVISOR */
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
/* LP_RX_SYNCHRO_ENABLE */
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
return 0;
}
static void dsi_enable_scp_clk(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
if (dsi->scp_clk_refcount++ == 0)
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
}
static void dsi_disable_scp_clk(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
WARN_ON(dsi->scp_clk_refcount == 0);
if (--dsi->scp_clk_refcount == 0)
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
}
enum dsi_pll_power_state {
DSI_PLL_POWER_OFF = 0x0,
DSI_PLL_POWER_ON_HSCLK = 0x1,
DSI_PLL_POWER_ON_ALL = 0x2,
DSI_PLL_POWER_ON_DIV = 0x3,
};
static int dsi_pll_power(struct platform_device *dsidev,
enum dsi_pll_power_state state)
{
int t = 0;
/* DSI-PLL power command 0x3 is not working */
if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
state == DSI_PLL_POWER_ON_DIV)
state = DSI_PLL_POWER_ON_ALL;
/* PLL_PWR_CMD */
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
/* PLL_PWR_STATUS */
while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
if (++t > 1000) {
DSSERR("Failed to set DSI PLL power mode to %d\n",
state);
return -ENODEV;
}
udelay(1);
}
return 0;
}
static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo)
{
unsigned long max_dsi_fck;
max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck);
cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI];
}
static int dsi_pll_enable(struct dss_pll *pll)
{
struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
struct platform_device *dsidev = dsi->pdev;
int r = 0;
DSSDBG("PLL init\n");
r = dsi_regulator_init(dsidev);
if (r)
return r;
r = dsi_runtime_get(dsidev);
if (r)
return r;
/*
* Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
*/
dsi_enable_scp_clk(dsidev);
if (!dsi->vdds_dsi_enabled) {
r = regulator_enable(dsi->vdds_dsi_reg);
if (r)
goto err0;
dsi->vdds_dsi_enabled = true;
}
/* XXX PLL does not come out of reset without this... */
dispc_pck_free_enable(1);
if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
DSSERR("PLL not coming out of reset.\n");
r = -ENODEV;
dispc_pck_free_enable(0);
goto err1;
}
/* XXX ... but if left on, we get problems when planes do not
* fill the whole display. No idea about this */
dispc_pck_free_enable(0);
r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL);
if (r)
goto err1;
DSSDBG("PLL init done\n");
return 0;
err1:
if (dsi->vdds_dsi_enabled) {
regulator_disable(dsi->vdds_dsi_reg);
dsi->vdds_dsi_enabled = false;
}
err0:
dsi_disable_scp_clk(dsidev);
dsi_runtime_put(dsidev);
return r;
}
static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
if (disconnect_lanes) {
WARN_ON(!dsi->vdds_dsi_enabled);
regulator_disable(dsi->vdds_dsi_reg);
dsi->vdds_dsi_enabled = false;
}
dsi_disable_scp_clk(dsidev);
dsi_runtime_put(dsidev);
DSSDBG("PLL uninit done\n");
}
static void dsi_pll_disable(struct dss_pll *pll)
{
struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
struct platform_device *dsidev = dsi->pdev;
dsi_pll_uninit(dsidev, true);
}
static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
struct seq_file *s)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
int dsi_module = dsi->module_id;
struct dss_pll *pll = &dsi->pll;
dispc_clk_src = dss_get_dispc_clk_source();
dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
if (dsi_runtime_get(dsidev))
return;
seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin));
seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n);
seq_printf(s, "CLKIN4DDR\t%-16lum %u\n",
cinfo->clkdco, cinfo->m);
seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n",
dss_feat_get_clk_source_name(dsi_module == 0 ?
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
cinfo->clkout[HSDIV_DISPC],
cinfo->mX[HSDIV_DISPC],
dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
"off" : "on");
seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n",
dss_feat_get_clk_source_name(dsi_module == 0 ?
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
cinfo->clkout[HSDIV_DSI],
cinfo->mX[HSDIV_DSI],
dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
"off" : "on");
seq_printf(s, "- DSI%d -\n", dsi_module + 1);
seq_printf(s, "dsi fclk source = %s (%s)\n",
dss_get_generic_clk_source_name(dsi_clk_src),
dss_feat_get_clk_source_name(dsi_clk_src));
seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
seq_printf(s, "DDR_CLK\t\t%lu\n",
cinfo->clkdco / 4);
seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
dsi_runtime_put(dsidev);
}
void dsi_dump_clocks(struct seq_file *s)
{
struct platform_device *dsidev;
int i;
for (i = 0; i < MAX_NUM_DSI; i++) {
dsidev = dsi_get_dsidev_from_id(i);
if (dsidev)
dsi_dump_dsidev_clocks(dsidev, s);
}
}
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
struct seq_file *s)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
struct dsi_irq_stats *stats;
stats = kzalloc(sizeof(*stats), GFP_KERNEL);
if (!stats) {
seq_printf(s, "out of memory\n");
return;
}
spin_lock_irqsave(&dsi->irq_stats_lock, flags);
*stats = dsi->irq_stats;
memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
dsi->irq_stats.last_reset = jiffies;
spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
seq_printf(s, "period %u ms\n",
jiffies_to_msecs(jiffies - stats->last_reset));
seq_printf(s, "irqs %d\n", stats->irq_count);
#define PIS(x) \
seq_printf(s, "%-20s %10d\n", #x, stats->dsi_irqs[ffs(DSI_IRQ_##x)-1])
seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
PIS(VC0);
PIS(VC1);
PIS(VC2);
PIS(VC3);
PIS(WAKEUP);
PIS(RESYNC);
PIS(PLL_LOCK);
PIS(PLL_UNLOCK);
PIS(PLL_RECALL);
PIS(COMPLEXIO_ERR);
PIS(HS_TX_TIMEOUT);
PIS(LP_RX_TIMEOUT);
PIS(TE_TRIGGER);
PIS(ACK_TRIGGER);
PIS(SYNC_LOST);
PIS(LDO_POWER_GOOD);
PIS(TA_TIMEOUT);
#undef PIS
#define PIS(x) \
seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
stats->vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
stats->vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
stats->vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
stats->vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
seq_printf(s, "-- VC interrupts --\n");
PIS(CS);
PIS(ECC_CORR);
PIS(PACKET_SENT);
PIS(FIFO_TX_OVF);
PIS(FIFO_RX_OVF);
PIS(BTA);
PIS(ECC_NO_CORR);
PIS(FIFO_TX_UDF);
PIS(PP_BUSY_CHANGE);
#undef PIS
#define PIS(x) \
seq_printf(s, "%-20s %10d\n", #x, \
stats->cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
seq_printf(s, "-- CIO interrupts --\n");
PIS(ERRSYNCESC1);
PIS(ERRSYNCESC2);
PIS(ERRSYNCESC3);
PIS(ERRESC1);
PIS(ERRESC2);
PIS(ERRESC3);
PIS(ERRCONTROL1);
PIS(ERRCONTROL2);
PIS(ERRCONTROL3);
PIS(STATEULPS1);
PIS(STATEULPS2);
PIS(STATEULPS3);
PIS(ERRCONTENTIONLP0_1);
PIS(ERRCONTENTIONLP1_1);
PIS(ERRCONTENTIONLP0_2);
PIS(ERRCONTENTIONLP1_2);
PIS(ERRCONTENTIONLP0_3);
PIS(ERRCONTENTIONLP1_3);
PIS(ULPSACTIVENOT_ALL0);
PIS(ULPSACTIVENOT_ALL1);
#undef PIS
kfree(stats);
}
static void dsi1_dump_irqs(struct seq_file *s)
{
struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
dsi_dump_dsidev_irqs(dsidev, s);
}
static void dsi2_dump_irqs(struct seq_file *s)
{
struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
dsi_dump_dsidev_irqs(dsidev, s);
}
#endif
static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
struct seq_file *s)
{
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
if (dsi_runtime_get(dsidev))
return;
dsi_enable_scp_clk(dsidev);
DUMPREG(DSI_REVISION);
DUMPREG(DSI_SYSCONFIG);
DUMPREG(DSI_SYSSTATUS);
DUMPREG(DSI_IRQSTATUS);
DUMPREG(DSI_IRQENABLE);
DUMPREG(DSI_CTRL);
DUMPREG(DSI_COMPLEXIO_CFG1);
DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
DUMPREG(DSI_CLK_CTRL);
DUMPREG(DSI_TIMING1);
DUMPREG(DSI_TIMING2);
DUMPREG(DSI_VM_TIMING1);
DUMPREG(DSI_VM_TIMING2);
DUMPREG(DSI_VM_TIMING3);
DUMPREG(DSI_CLK_TIMING);
DUMPREG(DSI_TX_FIFO_VC_SIZE);
DUMPREG(DSI_RX_FIFO_VC_SIZE);
DUMPREG(DSI_COMPLEXIO_CFG2);
DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
DUMPREG(DSI_VM_TIMING4);
DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
DUMPREG(DSI_VM_TIMING5);
DUMPREG(DSI_VM_TIMING6);
DUMPREG(DSI_VM_TIMING7);
DUMPREG(DSI_STOPCLK_TIMING);
DUMPREG(DSI_VC_CTRL(0));
DUMPREG(DSI_VC_TE(0));
DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
DUMPREG(DSI_VC_IRQSTATUS(0));
DUMPREG(DSI_VC_IRQENABLE(0));
DUMPREG(DSI_VC_CTRL(1));
DUMPREG(DSI_VC_TE(1));
DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
DUMPREG(DSI_VC_IRQSTATUS(1));
DUMPREG(DSI_VC_IRQENABLE(1));
DUMPREG(DSI_VC_CTRL(2));
DUMPREG(DSI_VC_TE(2));
DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
DUMPREG(DSI_VC_IRQSTATUS(2));
DUMPREG(DSI_VC_IRQENABLE(2));
DUMPREG(DSI_VC_CTRL(3));
DUMPREG(DSI_VC_TE(3));
DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
DUMPREG(DSI_VC_IRQSTATUS(3));
DUMPREG(DSI_VC_IRQENABLE(3));
DUMPREG(DSI_DSIPHY_CFG0);
DUMPREG(DSI_DSIPHY_CFG1);
DUMPREG(DSI_DSIPHY_CFG2);
DUMPREG(DSI_DSIPHY_CFG5);
DUMPREG(DSI_PLL_CONTROL);
DUMPREG(DSI_PLL_STATUS);
DUMPREG(DSI_PLL_GO);
DUMPREG(DSI_PLL_CONFIGURATION1);
DUMPREG(DSI_PLL_CONFIGURATION2);
dsi_disable_scp_clk(dsidev);
dsi_runtime_put(dsidev);
#undef DUMPREG
}
static void dsi1_dump_regs(struct seq_file *s)
{
struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
dsi_dump_dsidev_regs(dsidev, s);
}
static void dsi2_dump_regs(struct seq_file *s)
{
struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
dsi_dump_dsidev_regs(dsidev, s);
}
enum dsi_cio_power_state {
DSI_COMPLEXIO_POWER_OFF = 0x0,
DSI_COMPLEXIO_POWER_ON = 0x1,
DSI_COMPLEXIO_POWER_ULPS = 0x2,
};
static int dsi_cio_power(struct platform_device *dsidev,
enum dsi_cio_power_state state)
{
int t = 0;
/* PWR_CMD */
REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
/* PWR_STATUS */
while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
26, 25) != state) {
if (++t > 1000) {
DSSERR("failed to set complexio power state to "
"%d\n", state);
return -ENODEV;
}
udelay(1);
}
return 0;
}
static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
{
int val;
/* line buffer on OMAP3 is 1024 x 24bits */
/* XXX: for some reason using full buffer size causes
* considerable TX slowdown with update sizes that fill the
* whole buffer */
if (!dss_has_feature(FEAT_DSI_GNQ))
return 1023 * 3;
val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
switch (val) {
case 1:
return 512 * 3; /* 512x24 bits */
case 2:
return 682 * 3; /* 682x24 bits */
case 3:
return 853 * 3; /* 853x24 bits */
case 4:
return 1024 * 3; /* 1024x24 bits */
case 5:
return 1194 * 3; /* 1194x24 bits */
case 6:
return 1365 * 3; /* 1365x24 bits */
case 7:
return 1920 * 3; /* 1920x24 bits */
default:
BUG();
return 0;
}
}
static int dsi_set_lane_config(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
static const u8 offsets[] = { 0, 4, 8, 12, 16 };
static const enum dsi_lane_function functions[] = {
DSI_LANE_CLK,
DSI_LANE_DATA1,
DSI_LANE_DATA2,
DSI_LANE_DATA3,
DSI_LANE_DATA4,
};
u32 r;
int i;
r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
for (i = 0; i < dsi->num_lanes_used; ++i) {
unsigned offset = offsets[i];
unsigned polarity, lane_number;
unsigned t;
for (t = 0; t < dsi->num_lanes_supported; ++t)
if (dsi->lanes[t].function == functions[i])
break;
if (t == dsi->num_lanes_supported)
return -EINVAL;
lane_number = t;
polarity = dsi->lanes[t].polarity;
r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
r = FLD_MOD(r, polarity, offset + 3, offset + 3);
}
/* clear the unused lanes */
for (; i < dsi->num_lanes_supported; ++i) {
unsigned offset = offsets[i];
r = FLD_MOD(r, 0, offset + 2, offset);
r = FLD_MOD(r, 0, offset + 3, offset + 3);
}
dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
return 0;
}
static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
/* convert time in ns to ddr ticks, rounding up */
unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
}
static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
return ddr * 1000 * 1000 / (ddr_clk / 1000);
}
static void dsi_cio_timings(struct platform_device *dsidev)
{
u32 r;
u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
u32 tlpx_half, tclk_trail, tclk_zero;
u32 tclk_prepare;
/* calculate timings */
/* 1 * DDR_CLK = 2 * UI */
/* min 40ns + 4*UI max 85ns + 6*UI */
ths_prepare = ns2ddr(dsidev, 70) + 2;
/* min 145ns + 10*UI */
ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
/* min max(8*UI, 60ns+4*UI) */
ths_trail = ns2ddr(dsidev, 60) + 5;
/* min 100ns */
ths_exit = ns2ddr(dsidev, 145);
/* tlpx min 50n */
tlpx_half = ns2ddr(dsidev, 25);
/* min 60ns */
tclk_trail = ns2ddr(dsidev, 60) + 2;
/* min 38ns, max 95ns */
tclk_prepare = ns2ddr(dsidev, 65);
/* min tclk-prepare + tclk-zero = 300ns */
tclk_zero = ns2ddr(dsidev, 260);
DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
ths_prepare, ddr2ns(dsidev, ths_prepare),
ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
ths_trail, ddr2ns(dsidev, ths_trail),
ths_exit, ddr2ns(dsidev, ths_exit));
DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
"tclk_zero %u (%uns)\n",
tlpx_half, ddr2ns(dsidev, tlpx_half),
tclk_trail, ddr2ns(dsidev, tclk_trail),
tclk_zero, ddr2ns(dsidev, tclk_zero));
DSSDBG("tclk_prepare %u (%uns)\n",
tclk_prepare, ddr2ns(dsidev, tclk_prepare));
/* program timings */
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
r = FLD_MOD(r, ths_prepare, 31, 24);
r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
r = FLD_MOD(r, ths_trail, 15, 8);
r = FLD_MOD(r, ths_exit, 7, 0);
dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
r = FLD_MOD(r, tlpx_half, 20, 16);
r = FLD_MOD(r, tclk_trail, 15, 8);
r = FLD_MOD(r, tclk_zero, 7, 0);
if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
}
dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
r = FLD_MOD(r, tclk_prepare, 7, 0);
dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
}
/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
unsigned mask_p, unsigned mask_n)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
u32 l;
u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
l = 0;
for (i = 0; i < dsi->num_lanes_supported; ++i) {
unsigned p = dsi->lanes[i].polarity;
if (mask_p & (1 << i))
l |= 1 << (i * 2 + (p ? 0 : 1));
if (mask_n & (1 << i))
l |= 1 << (i * 2 + (p ? 1 : 0));
}
/*
* Bits in REGLPTXSCPDAT4TO0DXDY:
* 17: DY0 18: DX0
* 19: DY1 20: DX1
* 21: DY2 22: DX2
* 23: DY3 24: DX3
* 25: DY4 26: DX4
*/
/* Set the lane override configuration */
/* REGLPTXSCPDAT4TO0DXDY */
REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
/* Enable lane override */
/* ENLPTXSCPDAT */
REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
}
static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
{
/* Disable lane override */
REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
/* Reset the lane override configuration */
/* REGLPTXSCPDAT4TO0DXDY */
REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
}
static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int t, i;
bool in_use[DSI_MAX_NR_LANES];
static const u8 offsets_old[] = { 28, 27, 26 };
static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
const u8 *offsets;
if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
offsets = offsets_old;
else
offsets = offsets_new;
for (i = 0; i < dsi->num_lanes_supported; ++i)
in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
t = 100000;
while (true) {
u32 l;
int ok;
l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
ok = 0;
for (i = 0; i < dsi->num_lanes_supported; ++i) {
if (!in_use[i] || (l & (1 << offsets[i])))
ok++;
}
if (ok == dsi->num_lanes_supported)
break;
if (--t == 0) {
for (i = 0; i < dsi->num_lanes_supported; ++i) {
if (!in_use[i] || (l & (1 << offsets[i])))
continue;
DSSERR("CIO TXCLKESC%d domain not coming " \
"out of reset\n", i);
}
return -EIO;
}
}
return 0;
}
/* return bitmask of enabled lanes, lane0 being the lsb */
static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned mask = 0;
int i;
for (i = 0; i < dsi->num_lanes_supported; ++i) {
if (dsi->lanes[i].function != DSI_LANE_UNUSED)
mask |= 1 << i;
}
return mask;
}
static int dsi_cio_init(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r;
u32 l;
DSSDBG("DSI CIO init starts");
r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
if (r)
return r;
dsi_enable_scp_clk(dsidev);
/* A dummy read using the SCP interface to any DSIPHY register is
* required after DSIPHY reset to complete the reset of the DSI complex
* I/O. */
dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
DSSERR("CIO SCP Clock domain not coming out of reset.\n");
r = -EIO;
goto err_scp_clk_dom;
}
r = dsi_set_lane_config(dsidev);
if (r)
goto err_scp_clk_dom;
/* set TX STOP MODE timer to maximum for this operation */
l = dsi_read_reg(dsidev, DSI_TIMING1);
l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
dsi_write_reg(dsidev, DSI_TIMING1, l);
if (dsi->ulps_enabled) {
unsigned mask_p;
int i;
DSSDBG("manual ulps exit\n");
/* ULPS is exited by Mark-1 state for 1ms, followed by
* stop state. DSS HW cannot do this via the normal
* ULPS exit sequence, as after reset the DSS HW thinks
* that we are not in ULPS mode, and refuses to send the
* sequence. So we need to send the ULPS exit sequence
* manually by setting positive lines high and negative lines
* low for 1ms.
*/
mask_p = 0;
for (i = 0; i < dsi->num_lanes_supported; ++i) {
if (dsi->lanes[i].function == DSI_LANE_UNUSED)
continue;
mask_p |= 1 << i;
}
dsi_cio_enable_lane_override(dsidev, mask_p, 0);
}
r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
if (r)
goto err_cio_pwr;
if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
DSSERR("CIO PWR clock domain not coming out of reset.\n");
r = -ENODEV;
goto err_cio_pwr_dom;
}
dsi_if_enable(dsidev, true);
dsi_if_enable(dsidev, false);
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
if (r)
goto err_tx_clk_esc_rst;
if (dsi->ulps_enabled) {
/* Keep Mark-1 state for 1ms (as per DSI spec) */
ktime_t wait = ns_to_ktime(1000 * 1000);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
/* Disable the override. The lanes should be set to Mark-11
* state by the HW */
dsi_cio_disable_lane_override(dsidev);
}
/* FORCE_TX_STOP_MODE_IO */
REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
dsi_cio_timings(dsidev);
if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
/* DDR_CLK_ALWAYS_ON */
REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
dsi->vm_timings.ddr_clk_always_on, 13, 13);
}
dsi->ulps_enabled = false;
DSSDBG("CIO init done\n");
return 0;
err_tx_clk_esc_rst:
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
err_cio_pwr_dom:
dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
err_cio_pwr:
if (dsi->ulps_enabled)
dsi_cio_disable_lane_override(dsidev);
err_scp_clk_dom:
dsi_disable_scp_clk(dsidev);
dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
return r;
}
static void dsi_cio_uninit(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
/* DDR_CLK_ALWAYS_ON */
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
dsi_disable_scp_clk(dsidev);
dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
}
static void dsi_config_tx_fifo(struct platform_device *dsidev,
enum fifo_size size1, enum fifo_size size2,
enum fifo_size size3, enum fifo_size size4)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 r = 0;
int add = 0;
int i;
dsi->vc[0].tx_fifo_size = size1;
dsi->vc[1].tx_fifo_size = size2;
dsi->vc[2].tx_fifo_size = size3;
dsi->vc[3].tx_fifo_size = size4;
for (i = 0; i < 4; i++) {
u8 v;
int size = dsi->vc[i].tx_fifo_size;
if (add + size > 4) {
DSSERR("Illegal FIFO configuration\n");
BUG();
return;
}
v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
r |= v << (8 * i);
/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
add += size;
}
dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
}
static void dsi_config_rx_fifo(struct platform_device *dsidev,
enum fifo_size size1, enum fifo_size size2,
enum fifo_size size3, enum fifo_size size4)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 r = 0;
int add = 0;
int i;
dsi->vc[0].rx_fifo_size = size1;
dsi->vc[1].rx_fifo_size = size2;
dsi->vc[2].rx_fifo_size = size3;
dsi->vc[3].rx_fifo_size = size4;
for (i = 0; i < 4; i++) {
u8 v;
int size = dsi->vc[i].rx_fifo_size;
if (add + size > 4) {
DSSERR("Illegal FIFO configuration\n");
BUG();
return;
}
v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
r |= v << (8 * i);
/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
add += size;
}
dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
}
static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
{
u32 r;
r = dsi_read_reg(dsidev, DSI_TIMING1);
r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
dsi_write_reg(dsidev, DSI_TIMING1, r);
if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
DSSERR("TX_STOP bit not going down\n");
return -EIO;
}
return 0;
}
static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
{
return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
}
static void dsi_packet_sent_handler_vp(void *data, u32 mask)
{
struct dsi_packet_sent_handler_data *vp_data =
(struct dsi_packet_sent_handler_data *) data;
struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
const int channel = dsi->update_channel;
u8 bit = dsi->te_enabled ? 30 : 31;
if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
complete(vp_data->completion);
}
static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
DECLARE_COMPLETION_ONSTACK(completion);
struct dsi_packet_sent_handler_data vp_data = {
.dsidev = dsidev,
.completion = &completion
};
int r = 0;
u8 bit;
bit = dsi->te_enabled ? 30 : 31;
r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
&vp_data, DSI_VC_IRQ_PACKET_SENT);
if (r)
goto err0;
/* Wait for completion only if TE_EN/TE_START is still set */
if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
if (wait_for_completion_timeout(&completion,
msecs_to_jiffies(10)) == 0) {
DSSERR("Failed to complete previous frame transfer\n");
r = -EIO;
goto err1;
}
}
dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
&vp_data, DSI_VC_IRQ_PACKET_SENT);
return 0;
err1:
dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
&vp_data, DSI_VC_IRQ_PACKET_SENT);
err0:
return r;
}
static void dsi_packet_sent_handler_l4(void *data, u32 mask)
{
struct dsi_packet_sent_handler_data *l4_data =
(struct dsi_packet_sent_handler_data *) data;
struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
const int channel = dsi->update_channel;
if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
complete(l4_data->completion);
}
static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
{
DECLARE_COMPLETION_ONSTACK(completion);
struct dsi_packet_sent_handler_data l4_data = {
.dsidev = dsidev,
.completion = &completion
};
int r = 0;
r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
&l4_data, DSI_VC_IRQ_PACKET_SENT);
if (r)
goto err0;
/* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
if (wait_for_completion_timeout(&completion,
msecs_to_jiffies(10)) == 0) {
DSSERR("Failed to complete previous l4 transfer\n");
r = -EIO;
goto err1;
}
}
dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
&l4_data, DSI_VC_IRQ_PACKET_SENT);
return 0;
err1:
dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
&l4_data, DSI_VC_IRQ_PACKET_SENT);
err0:
return r;
}
static int dsi_sync_vc(struct platform_device *dsidev, int channel)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
WARN_ON(!dsi_bus_is_locked(dsidev));
if (!dsi_vc_is_enabled(dsidev, channel))
return 0;
switch (dsi->vc[channel].source) {
case DSI_VC_SOURCE_VP:
return dsi_sync_vc_vp(dsidev, channel);
case DSI_VC_SOURCE_L4:
return dsi_sync_vc_l4(dsidev, channel);
default:
BUG();
return -EINVAL;
}
}
static int dsi_vc_enable(struct platform_device *dsidev, int channel,
bool enable)
{
DSSDBG("dsi_vc_enable channel %d, enable %d\n",
channel, enable);
enable = enable ? 1 : 0;
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
0, enable) != enable) {
DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
return -EIO;
}
return 0;
}
static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 r;
DSSDBG("Initial config of virtual channel %d", channel);
r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
if (FLD_GET(r, 15, 15)) /* VC_BUSY */
DSSERR("VC(%d) busy when trying to configure it!\n",
channel);
r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
dsi->vc[channel].source = DSI_VC_SOURCE_L4;
}
static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
enum dsi_vc_source source)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
if (dsi->vc[channel].source == source)
return 0;
DSSDBG("Source config of virtual channel %d", channel);
dsi_sync_vc(dsidev, channel);
dsi_vc_enable(dsidev, channel, 0);
/* VC_BUSY */
if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
DSSERR("vc(%d) busy when trying to config for VP\n", channel);
return -EIO;
}
/* SOURCE, 0 = L4, 1 = video port */
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
/* DCS_CMD_ENABLE */
if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
bool enable = source == DSI_VC_SOURCE_VP;
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
}
dsi_vc_enable(dsidev, channel, 1);
dsi->vc[channel].source = source;
return 0;
}
static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
bool enable)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
WARN_ON(!dsi_bus_is_locked(dsidev));
dsi_vc_enable(dsidev, channel, 0);
dsi_if_enable(dsidev, 0);
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
dsi_vc_enable(dsidev, channel, 1);
dsi_if_enable(dsidev, 1);
dsi_force_tx_stop_mode_io(dsidev);
/* start the DDR clock by sending a NULL packet */
if (dsi->vm_timings.ddr_clk_always_on && enable)
dsi_vc_send_null(dssdev, channel);
}
static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
{
while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
u32 val;
val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
(val >> 0) & 0xff,
(val >> 8) & 0xff,
(val >> 16) & 0xff,
(val >> 24) & 0xff);
}
}
static void dsi_show_rx_ack_with_err(u16 err)
{
DSSERR("\tACK with ERROR (%#x):\n", err);
if (err & (1 << 0))
DSSERR("\t\tSoT Error\n");
if (err & (1 << 1))
DSSERR("\t\tSoT Sync Error\n");
if (err & (1 << 2))
DSSERR("\t\tEoT Sync Error\n");
if (err & (1 << 3))
DSSERR("\t\tEscape Mode Entry Command Error\n");
if (err & (1 << 4))
DSSERR("\t\tLP Transmit Sync Error\n");
if (err & (1 << 5))
DSSERR("\t\tHS Receive Timeout Error\n");
if (err & (1 << 6))
DSSERR("\t\tFalse Control Error\n");
if (err & (1 << 7))
DSSERR("\t\t(reserved7)\n");
if (err & (1 << 8))
DSSERR("\t\tECC Error, single-bit (corrected)\n");
if (err & (1 << 9))
DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
if (err & (1 << 10))
DSSERR("\t\tChecksum Error\n");
if (err & (1 << 11))
DSSERR("\t\tData type not recognized\n");
if (err & (1 << 12))
DSSERR("\t\tInvalid VC ID\n");
if (err & (1 << 13))
DSSERR("\t\tInvalid Transmission Length\n");
if (err & (1 << 14))
DSSERR("\t\t(reserved14)\n");
if (err & (1 << 15))
DSSERR("\t\tDSI Protocol Violation\n");
}
static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
int channel)
{
/* RX_FIFO_NOT_EMPTY */
while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
u32 val;
u8 dt;
val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
DSSERR("\trawval %#08x\n", val);
dt = FLD_GET(val, 5, 0);
if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
u16 err = FLD_GET(val, 23, 8);
dsi_show_rx_ack_with_err(err);
} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
DSSERR("\tDCS short response, 1 byte: %#x\n",
FLD_GET(val, 23, 8));
} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
DSSERR("\tDCS short response, 2 byte: %#x\n",
FLD_GET(val, 23, 8));
} else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
DSSERR("\tDCS long response, len %d\n",
FLD_GET(val, 23, 8));
dsi_vc_flush_long_data(dsidev, channel);
} else {
DSSERR("\tunknown datatype 0x%02x\n", dt);
}
}
return 0;
}
static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
if (dsi->debug_write || dsi->debug_read)
DSSDBG("dsi_vc_send_bta %d\n", channel);
WARN_ON(!dsi_bus_is_locked(dsidev));
/* RX_FIFO_NOT_EMPTY */
if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
dsi_vc_flush_receive_data(dsidev, channel);
}
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
/* flush posted write */
dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
return 0;
}
static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
DECLARE_COMPLETION_ONSTACK(completion);
int r = 0;
u32 err;
r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
&completion, DSI_VC_IRQ_BTA);
if (r)
goto err0;
r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
DSI_IRQ_ERROR_MASK);
if (r)
goto err1;
r = dsi_vc_send_bta(dsidev, channel);
if (r)
goto err2;
if (wait_for_completion_timeout(&completion,
msecs_to_jiffies(500)) == 0) {
DSSERR("Failed to receive BTA\n");
r = -EIO;
goto err2;
}
err = dsi_get_errors(dsidev);
if (err) {
DSSERR("Error while sending BTA: %x\n", err);
r = -EIO;
goto err2;
}
err2:
dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
DSI_IRQ_ERROR_MASK);
err1:
dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
&completion, DSI_VC_IRQ_BTA);
err0:
return r;
}
static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
int channel, u8 data_type, u16 len, u8 ecc)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 val;
u8 data_id;
WARN_ON(!dsi_bus_is_locked(dsidev));
data_id = data_type | dsi->vc[channel].vc_id << 6;
val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
FLD_VAL(ecc, 31, 24);
dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
}
static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
int channel, u8 b1, u8 b2, u8 b3, u8 b4)
{
u32 val;
val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
b1, b2, b3, b4, val); */
dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
}
static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
u8 data_type, u8 *data, u16 len, u8 ecc)
{
/*u32 val; */
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
u8 *p;
int r = 0;
u8 b1, b2, b3, b4;
if (dsi->debug_write)
DSSDBG("dsi_vc_send_long, %d bytes\n", len);
/* len + header */
if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
DSSERR("unable to send long packet: packet too long.\n");
return -EINVAL;
}
dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
p = data;
for (i = 0; i < len >> 2; i++) {
if (dsi->debug_write)
DSSDBG("\tsending full packet %d\n", i);
b1 = *p++;
b2 = *p++;
b3 = *p++;
b4 = *p++;
dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
}
i = len % 4;
if (i) {
b1 = 0; b2 = 0; b3 = 0;
if (dsi->debug_write)
DSSDBG("\tsending remainder bytes %d\n", i);
switch (i) {
case 3:
b1 = *p++;
b2 = *p++;
b3 = *p++;
break;
case 2:
b1 = *p++;
b2 = *p++;
break;
case 1:
b1 = *p++;
break;
}
dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
}
return r;
}
static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
u8 data_type, u16 data, u8 ecc)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 r;
u8 data_id;
WARN_ON(!dsi_bus_is_locked(dsidev));
if (dsi->debug_write)
DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
channel,
data_type, data & 0xff, (data >> 8) & 0xff);
dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
DSSERR("ERROR FIFO FULL, aborting transfer\n");
return -EINVAL;
}
data_id = data_type | dsi->vc[channel].vc_id << 6;
r = (data_id << 0) | (data << 8) | (ecc << 24);
dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
return 0;
}
static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
0, 0);
}
static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
int channel, u8 *data, int len, enum dss_dsi_content_type type)
{
int r;
if (len == 0) {
BUG_ON(type == DSS_DSI_CONTENT_DCS);
r = dsi_vc_send_short(dsidev, channel,
MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
} else if (len == 1) {
r = dsi_vc_send_short(dsidev, channel,
type == DSS_DSI_CONTENT_GENERIC ?
MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
} else if (len == 2) {
r = dsi_vc_send_short(dsidev, channel,
type == DSS_DSI_CONTENT_GENERIC ?
MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
MIPI_DSI_DCS_SHORT_WRITE_PARAM,
data[0] | (data[1] << 8), 0);
} else {
r = dsi_vc_send_long(dsidev, channel,
type == DSS_DSI_CONTENT_GENERIC ?
MIPI_DSI_GENERIC_LONG_WRITE :
MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
}
return r;
}
static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
u8 *data, int len)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
return dsi_vc_write_nosync_common(dsidev, channel, data, len,
DSS_DSI_CONTENT_DCS);
}
static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
u8 *data, int len)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
return dsi_vc_write_nosync_common(dsidev, channel, data, len,
DSS_DSI_CONTENT_GENERIC);
}
static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
u8 *data, int len, enum dss_dsi_content_type type)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
int r;
r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
if (r)
goto err;
r = dsi_vc_send_bta_sync(dssdev, channel);
if (r)
goto err;
/* RX_FIFO_NOT_EMPTY */
if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
DSSERR("rx fifo not empty after write, dumping data:\n");
dsi_vc_flush_receive_data(dsidev, channel);
r = -EIO;
goto err;
}
return 0;
err:
DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
channel, data[0], len);
return r;
}
static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
int len)
{
return dsi_vc_write_common(dssdev, channel, data, len,
DSS_DSI_CONTENT_DCS);
}
static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
int len)
{
return dsi_vc_write_common(dssdev, channel, data, len,
DSS_DSI_CONTENT_GENERIC);
}
static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
int channel, u8 dcs_cmd)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r;
if (dsi->debug_read)
DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
channel, dcs_cmd);
r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
if (r) {
DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
" failed\n", channel, dcs_cmd);
return r;
}
return 0;
}
static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
int channel, u8 *reqdata, int reqlen)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u16 data;
u8 data_type;
int r;
if (dsi->debug_read)
DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
channel, reqlen);
if (reqlen == 0) {
data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
data = 0;
} else if (reqlen == 1) {
data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
data = reqdata[0];
} else if (reqlen == 2) {
data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
data = reqdata[0] | (reqdata[1] << 8);
} else {
BUG();
return -EINVAL;
}
r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
if (r) {
DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
" failed\n", channel, reqlen);
return r;
}
return 0;
}
static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
u8 *buf, int buflen, enum dss_dsi_content_type type)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 val;
u8 dt;
int r;
/* RX_FIFO_NOT_EMPTY */
if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
DSSERR("RX fifo empty when trying to read.\n");
r = -EIO;
goto err;
}
val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
if (dsi->debug_read)
DSSDBG("\theader: %08x\n", val);
dt = FLD_GET(val, 5, 0);
if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
u16 err = FLD_GET(val, 23, 8);
dsi_show_rx_ack_with_err(err);
r = -EIO;
goto err;
} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
u8 data = FLD_GET(val, 15, 8);
if (dsi->debug_read)
DSSDBG("\t%s short response, 1 byte: %02x\n",
type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
"DCS", data);
if (buflen < 1) {
r = -EIO;
goto err;
}
buf[0] = data;
return 1;
} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
u16 data = FLD_GET(val, 23, 8);
if (dsi->debug_read)
DSSDBG("\t%s short response, 2 byte: %04x\n",
type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
"DCS", data);
if (buflen < 2) {
r = -EIO;
goto err;
}
buf[0] = data & 0xff;
buf[1] = (data >> 8) & 0xff;
return 2;
} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
int w;
int len = FLD_GET(val, 23, 8);
if (dsi->debug_read)
DSSDBG("\t%s long response, len %d\n",
type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
"DCS", len);
if (len > buflen) {
r = -EIO;
goto err;
}
/* two byte checksum ends the packet, not included in len */
for (w = 0; w < len + 2;) {
int b;
val = dsi_read_reg(dsidev,
DSI_VC_SHORT_PACKET_HEADER(channel));
if (dsi->debug_read)
DSSDBG("\t\t%02x %02x %02x %02x\n",
(val >> 0) & 0xff,
(val >> 8) & 0xff,
(val >> 16) & 0xff,
(val >> 24) & 0xff);
for (b = 0; b < 4; ++b) {
if (w < len)
buf[w] = (val >> (b * 8)) & 0xff;
/* we discard the 2 byte checksum */
++w;
}
}
return len;
} else {
DSSERR("\tunknown datatype 0x%02x\n", dt);
r = -EIO;
goto err;
}
err:
DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
return r;
}
static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
u8 *buf, int buflen)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
int r;
r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
if (r)
goto err;
r = dsi_vc_send_bta_sync(dssdev, channel);
if (r)
goto err;
r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
DSS_DSI_CONTENT_DCS);
if (r < 0)
goto err;
if (r != buflen) {
r = -EIO;
goto err;
}
return 0;
err:
DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
return r;
}
static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
u8 *reqdata, int reqlen, u8 *buf, int buflen)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
int r;
r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
if (r)
return r;
r = dsi_vc_send_bta_sync(dssdev, channel);
if (r)
return r;
r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
DSS_DSI_CONTENT_GENERIC);
if (r < 0)
return r;
if (r != buflen) {
r = -EIO;
return r;
}
return 0;
}
static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
u16 len)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
return dsi_vc_send_short(dsidev, channel,
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
}
static int dsi_enter_ulps(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
DECLARE_COMPLETION_ONSTACK(completion);
int r, i;
unsigned mask;
DSSDBG("Entering ULPS");
WARN_ON(!dsi_bus_is_locked(dsidev));
WARN_ON(dsi->ulps_enabled);
if (dsi->ulps_enabled)
return 0;
/* DDR_CLK_ALWAYS_ON */
if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
dsi_if_enable(dsidev, 0);
REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
dsi_if_enable(dsidev, 1);
}
dsi_sync_vc(dsidev, 0);
dsi_sync_vc(dsidev, 1);
dsi_sync_vc(dsidev, 2);
dsi_sync_vc(dsidev, 3);
dsi_force_tx_stop_mode_io(dsidev);
dsi_vc_enable(dsidev, 0, false);
dsi_vc_enable(dsidev, 1, false);
dsi_vc_enable(dsidev, 2, false);
dsi_vc_enable(dsidev, 3, false);
if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
DSSERR("HS busy when enabling ULPS\n");
return -EIO;
}
if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
DSSERR("LP busy when enabling ULPS\n");
return -EIO;
}
r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
if (r)
return r;
mask = 0;
for (i = 0; i < dsi->num_lanes_supported; ++i) {
if (dsi->lanes[i].function == DSI_LANE_UNUSED)
continue;
mask |= 1 << i;
}
/* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
/* LANEx_ULPS_SIG2 */
REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
/* flush posted write and wait for SCP interface to finish the write */
dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
if (wait_for_completion_timeout(&completion,
msecs_to_jiffies(1000)) == 0) {
DSSERR("ULPS enable timeout\n");
r = -EIO;
goto err;
}
dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
/* Reset LANEx_ULPS_SIG2 */
REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
/* flush posted write and wait for SCP interface to finish the write */
dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
dsi_if_enable(dsidev, false);
dsi->ulps_enabled = true;
return 0;
err:
dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
return r;
}
static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
unsigned ticks, bool x4, bool x16)
{
unsigned long fck;
unsigned long total_ticks;
u32 r;
BUG_ON(ticks > 0x1fff);
/* ticks in DSI_FCK */
fck = dsi_fclk_rate(dsidev);
r = dsi_read_reg(dsidev, DSI_TIMING2);
r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
dsi_write_reg(dsidev, DSI_TIMING2, r);
total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
total_ticks,
ticks, x4 ? " x4" : "", x16 ? " x16" : "",
(total_ticks * 1000) / (fck / 1000 / 1000));
}
static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
bool x8, bool x16)
{
unsigned long fck;
unsigned long total_ticks;
u32 r;
BUG_ON(ticks > 0x1fff);
/* ticks in DSI_FCK */
fck = dsi_fclk_rate(dsidev);
r = dsi_read_reg(dsidev, DSI_TIMING1);
r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
dsi_write_reg(dsidev, DSI_TIMING1, r);
total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
total_ticks,
ticks, x8 ? " x8" : "", x16 ? " x16" : "",
(total_ticks * 1000) / (fck / 1000 / 1000));
}
static void dsi_set_stop_state_counter(struct platform_device *dsidev,
unsigned ticks, bool x4, bool x16)
{
unsigned long fck;
unsigned long total_ticks;
u32 r;
BUG_ON(ticks > 0x1fff);
/* ticks in DSI_FCK */
fck = dsi_fclk_rate(dsidev);
r = dsi_read_reg(dsidev, DSI_TIMING1);
r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
dsi_write_reg(dsidev, DSI_TIMING1, r);
total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
total_ticks,
ticks, x4 ? " x4" : "", x16 ? " x16" : "",
(total_ticks * 1000) / (fck / 1000 / 1000));
}
static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
unsigned ticks, bool x4, bool x16)
{
unsigned long fck;
unsigned long total_ticks;
u32 r;
BUG_ON(ticks > 0x1fff);
/* ticks in TxByteClkHS */
fck = dsi_get_txbyteclkhs(dsidev);
r = dsi_read_reg(dsidev, DSI_TIMING2);
r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
dsi_write_reg(dsidev, DSI_TIMING2, r);
total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
total_ticks,
ticks, x4 ? " x4" : "", x16 ? " x16" : "",
(total_ticks * 1000) / (fck / 1000 / 1000));
}
static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int num_line_buffers;
if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
int bpp = dsi_get_pixel_size(dsi->pix_fmt);
struct omap_video_timings *timings = &dsi->timings;
/*
* Don't use line buffers if width is greater than the video
* port's line buffer size
*/
if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
num_line_buffers = 0;
else
num_line_buffers = 2;
} else {
/* Use maximum number of line buffers in command mode */
num_line_buffers = 2;
}
/* LINE_BUFFER */
REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
}
static void dsi_config_vp_sync_events(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
bool sync_end;
u32 r;
if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
sync_end = true;
else
sync_end = false;
r = dsi_read_reg(dsidev, DSI_CTRL);
r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
dsi_write_reg(dsidev, DSI_CTRL, r);
}
static void dsi_config_blanking_modes(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int blanking_mode = dsi->vm_timings.blanking_mode;
int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
u32 r;
/*
* 0 = TX FIFO packets sent or LPS in corresponding blanking periods
* 1 = Long blanking packets are sent in corresponding blanking periods
*/
r = dsi_read_reg(dsidev, DSI_CTRL);
r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
dsi_write_reg(dsidev, DSI_CTRL, r);
}
/*
* According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
* results in maximum transition time for data and clock lanes to enter and
* exit HS mode. Hence, this is the scenario where the least amount of command
* mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
* clock cycles that can be used to interleave command mode data in HS so that
* all scenarios are satisfied.
*/
static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
{
int transition;
/*
* If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
* time of data lanes only, if it isn't set, we need to consider HS
* transition time of both data and clock lanes. HS transition time
* of Scenario 3 is considered.
*/
if (ddr_alwon) {
transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
} else {
int trans1, trans2;
trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
enter_hs + 1;
transition = max(trans1, trans2);
}
return blank > transition ? blank - transition : 0;
}
/*
* According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
* results in maximum transition time for data lanes to enter and exit LP mode.
* Hence, this is the scenario where the least amount of command mode data can
* be interleaved. We program the minimum amount of bytes that can be
* interleaved in LP so that all scenarios are satisfied.
*/
static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
int lp_clk_div, int tdsi_fclk)
{
int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
int lp_inter; /* cmd mode data that can be interleaved, in bytes */
/* maximum LP transition time according to Scenario 1 */
trans_lp = exit_hs + max(enter_hs, 2) + 1;
/* CLKIN4DDR = 16 * TXBYTECLKHS */
tlp_avail = thsbyte_clk * (blank - trans_lp);
ttxclkesc = tdsi_fclk * lp_clk_div;
lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
26) / 16;
return max(lp_inter, 0);
}
static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int blanking_mode;
int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
int tclk_trail, ths_exit, exiths_clk;
bool ddr_alwon;
struct omap_video_timings *timings = &dsi->timings;
int bpp = dsi_get_pixel_size(dsi->pix_fmt);
int ndl = dsi->num_lanes_used - 1;
int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1;
int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
int bl_interleave_hs = 0, bl_interleave_lp = 0;
u32 r;
r = dsi_read_reg(dsidev, DSI_CTRL);
blanking_mode = FLD_GET(r, 20, 20);
hfp_blanking_mode = FLD_GET(r, 21, 21);
hbp_blanking_mode = FLD_GET(r, 22, 22);
hsa_blanking_mode = FLD_GET(r, 23, 23);
r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
hbp = FLD_GET(r, 11, 0);
hfp = FLD_GET(r, 23, 12);
hsa = FLD_GET(r, 31, 24);
r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
ddr_clk_post = FLD_GET(r, 7, 0);
ddr_clk_pre = FLD_GET(r, 15, 8);
r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
exit_hs_mode_lat = FLD_GET(r, 15, 0);
enter_hs_mode_lat = FLD_GET(r, 31, 16);
r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
lp_clk_div = FLD_GET(r, 12, 0);
ddr_alwon = FLD_GET(r, 13, 13);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
ths_exit = FLD_GET(r, 7, 0);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
tclk_trail = FLD_GET(r, 15, 8);
exiths_clk = ths_exit + tclk_trail;
width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
if (!hsa_blanking_mode) {
hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
enter_hs_mode_lat, exit_hs_mode_lat,
exiths_clk, ddr_clk_pre, ddr_clk_post);
hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
enter_hs_mode_lat, exit_hs_mode_lat,
lp_clk_div, dsi_fclk_hsdiv);
}
if (!hfp_blanking_mode) {
hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
enter_hs_mode_lat, exit_hs_mode_lat,
exiths_clk, ddr_clk_pre, ddr_clk_post);
hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
enter_hs_mode_lat, exit_hs_mode_lat,
lp_clk_div, dsi_fclk_hsdiv);
}
if (!hbp_blanking_mode) {
hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
enter_hs_mode_lat, exit_hs_mode_lat,
exiths_clk, ddr_clk_pre, ddr_clk_post);
hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
enter_hs_mode_lat, exit_hs_mode_lat,
lp_clk_div, dsi_fclk_hsdiv);
}
if (!blanking_mode) {
bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
enter_hs_mode_lat, exit_hs_mode_lat,
exiths_clk, ddr_clk_pre, ddr_clk_post);
bl_interleave_lp = dsi_compute_interleave_lp(bllp,
enter_hs_mode_lat, exit_hs_mode_lat,
lp_clk_div, dsi_fclk_hsdiv);
}
DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
bl_interleave_hs);
DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
bl_interleave_lp);
r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
r = FLD_MOD(r, bl_interleave_hs, 31, 15);
r = FLD_MOD(r, bl_interleave_lp, 16, 0);
dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
}
static int dsi_proto_config(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 r;
int buswidth = 0;
dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32);
dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32);
/* XXX what values for the timeouts? */
dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
switch (dsi_get_pixel_size(dsi->pix_fmt)) {
case 16:
buswidth = 0;
break;
case 18:
buswidth = 1;
break;
case 24:
buswidth = 2;
break;
default:
BUG();
return -EINVAL;
}
r = dsi_read_reg(dsidev, DSI_CTRL);
r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
/* DCS_CMD_CODE, 1=start, 0=continue */
r = FLD_MOD(r, 0, 25, 25);
}
dsi_write_reg(dsidev, DSI_CTRL, r);
dsi_config_vp_num_line_buffers(dsidev);
if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
dsi_config_vp_sync_events(dsidev);
dsi_config_blanking_modes(dsidev);
dsi_config_cmd_mode_interleaving(dsidev);
}
dsi_vc_initial_config(dsidev, 0);
dsi_vc_initial_config(dsidev, 1);
dsi_vc_initial_config(dsidev, 2);
dsi_vc_initial_config(dsidev, 3);
return 0;
}
static void dsi_proto_timings(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned tlpx, tclk_zero, tclk_prepare;
unsigned tclk_pre, tclk_post;
unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
unsigned ths_trail, ths_exit;
unsigned ddr_clk_pre, ddr_clk_post;
unsigned enter_hs_mode_lat, exit_hs_mode_lat;
unsigned ths_eot;
int ndl = dsi->num_lanes_used - 1;
u32 r;
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
ths_prepare = FLD_GET(r, 31, 24);
ths_prepare_ths_zero = FLD_GET(r, 23, 16);
ths_zero = ths_prepare_ths_zero - ths_prepare;
ths_trail = FLD_GET(r, 15, 8);
ths_exit = FLD_GET(r, 7, 0);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
tlpx = FLD_GET(r, 20, 16) * 2;
tclk_zero = FLD_GET(r, 7, 0);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
tclk_prepare = FLD_GET(r, 7, 0);
/* min 8*UI */
tclk_pre = 20;
/* min 60ns + 52*UI */
tclk_post = ns2ddr(dsidev, 60) + 26;
ths_eot = DIV_ROUND_UP(4, ndl);
ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
4);
ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
r = FLD_MOD(r, ddr_clk_pre, 15, 8);
r = FLD_MOD(r, ddr_clk_post, 7, 0);
dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
ddr_clk_pre,
ddr_clk_post);
enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
DIV_ROUND_UP(ths_prepare, 4) +
DIV_ROUND_UP(ths_zero + 3, 4);
exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
FLD_VAL(exit_hs_mode_lat, 15, 0);
dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
enter_hs_mode_lat, exit_hs_mode_lat);
if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
/* TODO: Implement a video mode check_timings function */
int hsa = dsi->vm_timings.hsa;
int hfp = dsi->vm_timings.hfp;
int hbp = dsi->vm_timings.hbp;
int vsa = dsi->vm_timings.vsa;
int vfp = dsi->vm_timings.vfp;
int vbp = dsi->vm_timings.vbp;
int window_sync = dsi->vm_timings.window_sync;
bool hsync_end;
struct omap_video_timings *timings = &dsi->timings;
int bpp = dsi_get_pixel_size(dsi->pix_fmt);
int tl, t_he, width_bytes;
hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
t_he = hsync_end ?
((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
/* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
hfp, hsync_end ? hsa : 0, tl);
DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
vsa, timings->y_res);
r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
r = FLD_MOD(r, hbp, 11, 0); /* HBP */
r = FLD_MOD(r, hfp, 23, 12); /* HFP */
r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
r = FLD_MOD(r, vbp, 7, 0); /* VBP */
r = FLD_MOD(r, vfp, 15, 8); /* VFP */
r = FLD_MOD(r, vsa, 23, 16); /* VSA */
r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
r = FLD_MOD(r, tl, 31, 16); /* TL */
dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
}
}
static int dsi_configure_pins(struct omap_dss_device *dssdev,
const struct omap_dsi_pin_config *pin_cfg)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int num_pins;
const int *pins;
struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
int num_lanes;
int i;
static const enum dsi_lane_function functions[] = {
DSI_LANE_CLK,
DSI_LANE_DATA1,
DSI_LANE_DATA2,
DSI_LANE_DATA3,
DSI_LANE_DATA4,
};
num_pins = pin_cfg->num_pins;
pins = pin_cfg->pins;
if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
|| num_pins % 2 != 0)
return -EINVAL;
for (i = 0; i < DSI_MAX_NR_LANES; ++i)
lanes[i].function = DSI_LANE_UNUSED;
num_lanes = 0;
for (i = 0; i < num_pins; i += 2) {
u8 lane, pol;
int dx, dy;
dx = pins[i];
dy = pins[i + 1];
if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
return -EINVAL;
if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
return -EINVAL;
if (dx & 1) {
if (dy != dx - 1)
return -EINVAL;
pol = 1;
} else {
if (dy != dx + 1)
return -EINVAL;
pol = 0;
}
lane = dx / 2;
lanes[lane].function = functions[i / 2];
lanes[lane].polarity = pol;
num_lanes++;
}
memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
dsi->num_lanes_used = num_lanes;
return 0;
}
static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct omap_overlay_manager *mgr = dsi->output.manager;
int bpp = dsi_get_pixel_size(dsi->pix_fmt);
struct omap_dss_device *out = &dsi->output;
u8 data_type;
u16 word_count;
int r;
if (out->manager == NULL) {
DSSERR("failed to enable display: no output/manager\n");
return -ENODEV;
}
r = dsi_display_init_dispc(dsidev, mgr);
if (r)
goto err_init_dispc;
if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
switch (dsi->pix_fmt) {
case OMAP_DSS_DSI_FMT_RGB888:
data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
break;
case OMAP_DSS_DSI_FMT_RGB666:
data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
break;
case OMAP_DSS_DSI_FMT_RGB666_PACKED:
data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
break;
case OMAP_DSS_DSI_FMT_RGB565:
data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
break;
default:
r = -EINVAL;
goto err_pix_fmt;
}
dsi_if_enable(dsidev, false);
dsi_vc_enable(dsidev, channel, false);
/* MODE, 1 = video mode */
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
dsi_vc_write_long_header(dsidev, channel, data_type,
word_count, 0);
dsi_vc_enable(dsidev, channel, true);
dsi_if_enable(dsidev, true);
}
r = dss_mgr_enable(mgr);
if (r)
goto err_mgr_enable;
return 0;
err_mgr_enable:
if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
dsi_if_enable(dsidev, false);
dsi_vc_enable(dsidev, channel, false);
}
err_pix_fmt:
dsi_display_uninit_dispc(dsidev, mgr);
err_init_dispc:
return r;
}
static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct omap_overlay_manager *mgr = dsi->output.manager;
if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
dsi_if_enable(dsidev, false);
dsi_vc_enable(dsidev, channel, false);
/* MODE, 0 = command mode */
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
dsi_vc_enable(dsidev, channel, true);
dsi_if_enable(dsidev, true);
}
dss_mgr_disable(mgr);
dsi_display_uninit_dispc(dsidev, mgr);
}
static void dsi_update_screen_dispc(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct omap_overlay_manager *mgr = dsi->output.manager;
unsigned bytespp;
unsigned bytespl;
unsigned bytespf;
unsigned total_len;
unsigned packet_payload;
unsigned packet_len;
u32 l;
int r;
const unsigned channel = dsi->update_channel;
const unsigned line_buf_size = dsi->line_buffer_size;
u16 w = dsi->timings.x_res;
u16 h = dsi->timings.y_res;
DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
bytespl = w * bytespp;
bytespf = bytespl * h;
/* NOTE: packet_payload has to be equal to N * bytespl, where N is
* number of lines in a packet. See errata about VP_CLK_RATIO */
if (bytespf < line_buf_size)
packet_payload = bytespf;
else
packet_payload = (line_buf_size) / bytespl * bytespl;
packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
total_len = (bytespf / packet_payload) * packet_len;
if (bytespf % packet_payload)
total_len += (bytespf % packet_payload) + 1;
l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
packet_len, 0);
if (dsi->te_enabled)
l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
else
l = FLD_MOD(l, 1, 31, 31); /* TE_START */
dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
/* We put SIDLEMODE to no-idle for the duration of the transfer,
* because DSS interrupts are not capable of waking up the CPU and the
* framedone interrupt could be delayed for quite a long time. I think
* the same goes for any DSS interrupts, but for some reason I have not
* seen the problem anywhere else than here.
*/
dispc_disable_sidle();
dsi_perf_mark_start(dsidev);
r = schedule_delayed_work(&dsi->framedone_timeout_work,
msecs_to_jiffies(250));
BUG_ON(r == 0);
dss_mgr_set_timings(mgr, &dsi->timings);
dss_mgr_start_update(mgr);
if (dsi->te_enabled) {
/* disable LP_RX_TO, so that we can receive TE. Time to wait
* for TE is longer than the timer allows */
REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
dsi_vc_send_bta(dsidev, channel);
#ifdef DSI_CATCH_MISSING_TE
mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
#endif
}
}
#ifdef DSI_CATCH_MISSING_TE
static void dsi_te_timeout(struct timer_list *unused)
{
DSSERR("TE not received for 250ms!\n");
}
#endif
static void dsi_handle_framedone(struct platform_device *dsidev, int error)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
/* SIDLEMODE back to smart-idle */
dispc_enable_sidle();
if (dsi->te_enabled) {
/* enable LP_RX_TO again after the TE */
REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
}
dsi->framedone_callback(error, dsi->framedone_data);
if (!error)
dsi_perf_show(dsidev, "DISPC");
}
static void dsi_framedone_timeout_work_callback(struct work_struct *work)
{
struct dsi_data *dsi = container_of(work, struct dsi_data,
framedone_timeout_work.work);
/* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
* 250ms which would conflict with this timeout work. What should be
* done is first cancel the transfer on the HW, and then cancel the
* possibly scheduled framedone work. However, cancelling the transfer
* on the HW is buggy, and would probably require resetting the whole
* DSI */
DSSERR("Framedone not received for 250ms!\n");
dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
}
static void dsi_framedone_irq_callback(void *data)
{
struct platform_device *dsidev = (struct platform_device *) data;
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
* turns itself off. However, DSI still has the pixels in its buffers,
* and is sending the data.
*/
cancel_delayed_work(&dsi->framedone_timeout_work);
dsi_handle_framedone(dsidev, 0);
}
static int dsi_update(struct omap_dss_device *dssdev, int channel,
void (*callback)(int, void *), void *data)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
dsi_perf_mark_setup(dsidev);
dsi->update_channel = channel;
dsi->framedone_callback = callback;
dsi->framedone_data = data;
#ifdef DSI_PERF_MEASURE
dsi->update_bytes = dsi->timings.x_res * dsi->timings.y_res *
dsi_get_pixel_size(dsi->pix_fmt) / 8;
#endif
dsi_update_screen_dispc(dsidev);
return 0;
}
/* Display funcs */
static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct dispc_clock_info dispc_cinfo;
int r;
unsigned long fck;
fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
r = dispc_calc_clock_rates(fck, &dispc_cinfo);
if (r) {
DSSERR("Failed to calc dispc clocks\n");
return r;
}
dsi->mgr_config.clock_info = dispc_cinfo;
return 0;
}
static int dsi_display_init_dispc(struct platform_device *dsidev,
struct omap_overlay_manager *mgr)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r;
dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
r = dss_mgr_register_framedone_handler(mgr,
dsi_framedone_irq_callback, dsidev);
if (r) {
DSSERR("can't register FRAMEDONE handler\n");
goto err;
}
dsi->mgr_config.stallmode = true;
dsi->mgr_config.fifohandcheck = true;
} else {
dsi->mgr_config.stallmode = false;
dsi->mgr_config.fifohandcheck = false;
}
/*
* override interlace, logic level and edge related parameters in
* omap_video_timings with default values
*/
dsi->timings.interlace = false;
dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE;
dss_mgr_set_timings(mgr, &dsi->timings);
r = dsi_configure_dispc_clocks(dsidev);
if (r)
goto err1;
dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
dsi->mgr_config.video_port_width =
dsi_get_pixel_size(dsi->pix_fmt);
dsi->mgr_config.lcden_sig_polarity = 0;
dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
return 0;
err1:
if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
dss_mgr_unregister_framedone_handler(mgr,
dsi_framedone_irq_callback, dsidev);
err:
dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
return r;
}
static void dsi_display_uninit_dispc(struct platform_device *dsidev,
struct omap_overlay_manager *mgr)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
dss_mgr_unregister_framedone_handler(mgr,
dsi_framedone_irq_callback, dsidev);
dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
}
static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct dss_pll_clock_info cinfo;
int r;
cinfo = dsi->user_dsi_cinfo;
r = dss_pll_set_config(&dsi->pll, &cinfo);
if (r) {
DSSERR("Failed to set dsi clocks\n");
return r;
}
return 0;
}
static int dsi_display_init_dsi(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r;
r = dss_pll_enable(&dsi->pll);
if (r)
goto err0;
r = dsi_configure_dsi_clocks(dsidev);
if (r)
goto err1;
dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
DSSDBG("PLL OK\n");
r = dsi_cio_init(dsidev);
if (r)
goto err2;
_dsi_print_reset_status(dsidev);
dsi_proto_timings(dsidev);
dsi_set_lp_clk_divisor(dsidev);
if (1)
_dsi_print_reset_status(dsidev);
r = dsi_proto_config(dsidev);
if (r)
goto err3;
/* enable interface */
dsi_vc_enable(dsidev, 0, 1);
dsi_vc_enable(dsidev, 1, 1);
dsi_vc_enable(dsidev, 2, 1);
dsi_vc_enable(dsidev, 3, 1);
dsi_if_enable(dsidev, 1);
dsi_force_tx_stop_mode_io(dsidev);
return 0;
err3:
dsi_cio_uninit(dsidev);
err2:
dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
err1:
dss_pll_disable(&dsi->pll);
err0:
return r;
}
static void dsi_display_uninit_dsi(struct platform_device *dsidev,
bool disconnect_lanes, bool enter_ulps)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
if (enter_ulps && !dsi->ulps_enabled)
dsi_enter_ulps(dsidev);
/* disable interface */
dsi_if_enable(dsidev, 0);
dsi_vc_enable(dsidev, 0, 0);
dsi_vc_enable(dsidev, 1, 0);
dsi_vc_enable(dsidev, 2, 0);
dsi_vc_enable(dsidev, 3, 0);
dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
dsi_cio_uninit(dsidev);
dsi_pll_uninit(dsidev, disconnect_lanes);
}
static int dsi_display_enable(struct omap_dss_device *dssdev)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r = 0;
DSSDBG("dsi_display_enable\n");
WARN_ON(!dsi_bus_is_locked(dsidev));
mutex_lock(&dsi->lock);
r = dsi_runtime_get(dsidev);
if (r)
goto err_get_dsi;
_dsi_initialize_irq(dsidev);
r = dsi_display_init_dsi(dsidev);
if (r)
goto err_init_dsi;
mutex_unlock(&dsi->lock);
return 0;
err_init_dsi:
dsi_runtime_put(dsidev);
err_get_dsi:
mutex_unlock(&dsi->lock);
DSSDBG("dsi_display_enable FAILED\n");
return r;
}
static void dsi_display_disable(struct omap_dss_device *dssdev,
bool disconnect_lanes, bool enter_ulps)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
DSSDBG("dsi_display_disable\n");
WARN_ON(!dsi_bus_is_locked(dsidev));
mutex_lock(&dsi->lock);
dsi_sync_vc(dsidev, 0);
dsi_sync_vc(dsidev, 1);
dsi_sync_vc(dsidev, 2);
dsi_sync_vc(dsidev, 3);
dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
dsi_runtime_put(dsidev);
mutex_unlock(&dsi->lock);
}
static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
dsi->te_enabled = enable;
return 0;
}
#ifdef PRINT_VERBOSE_VM_TIMINGS
static void print_dsi_vm(const char *str,
const struct omap_dss_dsi_videomode_timings *t)
{
unsigned long byteclk = t->hsclk / 4;
int bl, wc, pps, tot;
wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
tot = bl + pps;
#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
"%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
str,
byteclk,
t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
bl, pps, tot,
TO_DSI_T(t->hss),
TO_DSI_T(t->hsa),
TO_DSI_T(t->hse),
TO_DSI_T(t->hbp),
TO_DSI_T(pps),
TO_DSI_T(t->hfp),
TO_DSI_T(bl),
TO_DSI_T(pps),
TO_DSI_T(tot));
#undef TO_DSI_T
}
static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
{
unsigned long pck = t->pixelclock;
int hact, bl, tot;
hact = t->x_res;
bl = t->hsw + t->hbp + t->hfp;
tot = hact + bl;
#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
"%u/%u/%u/%u = %u + %u = %u\n",
str,
pck,
t->hsw, t->hbp, hact, t->hfp,
bl, hact, tot,
TO_DISPC_T(t->hsw),
TO_DISPC_T(t->hbp),
TO_DISPC_T(hact),
TO_DISPC_T(t->hfp),
TO_DISPC_T(bl),
TO_DISPC_T(hact),
TO_DISPC_T(tot));
#undef TO_DISPC_T
}
/* note: this is not quite accurate */
static void print_dsi_dispc_vm(const char *str,
const struct omap_dss_dsi_videomode_timings *t)
{
struct omap_video_timings vm = { 0 };
unsigned long byteclk = t->hsclk / 4;
unsigned long pck;
u64 dsi_tput;
int dsi_hact, dsi_htot;
dsi_tput = (u64)byteclk * t->ndl * 8;
pck = (u32)div64_u64(dsi_tput, t->bitspp);
dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
vm.pixelclock = pck;
vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
vm.x_res = t->hact;
print_dispc_vm(str, &vm);
}
#endif /* PRINT_VERBOSE_VM_TIMINGS */
static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
unsigned long pck, void *data)
{
struct dsi_clk_calc_ctx *ctx = data;
struct omap_video_timings *t = &ctx->dispc_vm;
ctx->dispc_cinfo.lck_div = lckd;
ctx->dispc_cinfo.pck_div = pckd;
ctx->dispc_cinfo.lck = lck;
ctx->dispc_cinfo.pck = pck;
*t = *ctx->config->timings;
t->pixelclock = pck;
t->x_res = ctx->config->timings->x_res;
t->y_res = ctx->config->timings->y_res;
t->hsw = t->hfp = t->hbp = t->vsw = 1;
t->vfp = t->vbp = 0;
return true;
}
static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
void *data)
{
struct dsi_clk_calc_ctx *ctx = data;
ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
dsi_cm_calc_dispc_cb, ctx);
}
static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
unsigned long clkdco, void *data)
{
struct dsi_clk_calc_ctx *ctx = data;
ctx->dsi_cinfo.n = n;
ctx->dsi_cinfo.m = m;
ctx->dsi_cinfo.fint = fint;
ctx->dsi_cinfo.clkdco = clkdco;
return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
dsi_cm_calc_hsdiv_cb, ctx);
}
static bool dsi_cm_calc(struct dsi_data *dsi,
const struct omap_dss_dsi_config *cfg,
struct dsi_clk_calc_ctx *ctx)
{
unsigned long clkin;
int bitspp, ndl;
unsigned long pll_min, pll_max;
unsigned long pck, txbyteclk;
clkin = clk_get_rate(dsi->pll.clkin);
bitspp = dsi_get_pixel_size(cfg->pixel_format);
ndl = dsi->num_lanes_used - 1;
/*
* Here we should calculate minimum txbyteclk to be able to send the
* frame in time, and also to handle TE. That's not very simple, though,
* especially as we go to LP between each pixel packet due to HW
* "feature". So let's just estimate very roughly and multiply by 1.5.
*/
pck = cfg->timings->pixelclock;
pck = pck * 3 / 2;
txbyteclk = pck * bitspp / 8 / ndl;
memset(ctx, 0, sizeof(*ctx));
ctx->dsidev = dsi->pdev;
ctx->pll = &dsi->pll;
ctx->config = cfg;
ctx->req_pck_min = pck;
ctx->req_pck_nom = pck;
ctx->req_pck_max = pck * 3 / 2;
pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
pll_max = cfg->hs_clk_max * 4;
return dss_pll_calc(ctx->pll, clkin,
pll_min, pll_max,
dsi_cm_calc_pll_cb, ctx);
}
static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
const struct omap_dss_dsi_config *cfg = ctx->config;
int bitspp = dsi_get_pixel_size(cfg->pixel_format);
int ndl = dsi->num_lanes_used - 1;
unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4;
unsigned long byteclk = hsclk / 4;
unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
int xres;
int panel_htot, panel_hbl; /* pixels */
int dispc_htot, dispc_hbl; /* pixels */
int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
int hfp, hsa, hbp;
const struct omap_video_timings *req_vm;
struct omap_video_timings *dispc_vm;
struct omap_dss_dsi_videomode_timings *dsi_vm;
u64 dsi_tput, dispc_tput;
dsi_tput = (u64)byteclk * ndl * 8;
req_vm = cfg->timings;
req_pck_min = ctx->req_pck_min;
req_pck_max = ctx->req_pck_max;
req_pck_nom = ctx->req_pck_nom;
dispc_pck = ctx->dispc_cinfo.pck;
dispc_tput = (u64)dispc_pck * bitspp;
xres = req_vm->x_res;
panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
panel_htot = xres + panel_hbl;
dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
/*
* When there are no line buffers, DISPC and DSI must have the
* same tput. Otherwise DISPC tput needs to be higher than DSI's.
*/
if (dsi->line_buffer_size < xres * bitspp / 8) {
if (dispc_tput != dsi_tput)
return false;
} else {
if (dispc_tput < dsi_tput)
return false;
}
/* DSI tput must be over the min requirement */
if (dsi_tput < (u64)bitspp * req_pck_min)
return false;
/* When non-burst mode, DSI tput must be below max requirement. */
if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
if (dsi_tput > (u64)bitspp * req_pck_max)
return false;
}
hss = DIV_ROUND_UP(4, ndl);
if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
if (ndl == 3 && req_vm->hsw == 0)
hse = 1;
else
hse = DIV_ROUND_UP(4, ndl);
} else {
hse = 0;
}
/* DSI htot to match the panel's nominal pck */
dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
/* fail if there would be no time for blanking */
if (dsi_htot < hss + hse + dsi_hact)
return false;
/* total DSI blanking needed to achieve panel's TL */
dsi_hbl = dsi_htot - dsi_hact;
/* DISPC htot to match the DSI TL */
dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
/* verify that the DSI and DISPC TLs are the same */
if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
return false;
dispc_hbl = dispc_htot - xres;
/* setup DSI videomode */
dsi_vm = &ctx->dsi_vm;
memset(dsi_vm, 0, sizeof(*dsi_vm));
dsi_vm->hsclk = hsclk;
dsi_vm->ndl = ndl;
dsi_vm->bitspp = bitspp;
if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
hsa = 0;
} else if (ndl == 3 && req_vm->hsw == 0) {
hsa = 0;
} else {
hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
hsa = max(hsa - hse, 1);
}
hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
hbp = max(hbp, 1);
hfp = dsi_hbl - (hss + hsa + hse + hbp);
if (hfp < 1) {
int t;
/* we need to take cycles from hbp */
t = 1 - hfp;
hbp = max(hbp - t, 1);
hfp = dsi_hbl - (hss + hsa + hse + hbp);
if (hfp < 1 && hsa > 0) {
/* we need to take cycles from hsa */
t = 1 - hfp;
hsa = max(hsa - t, 1);
hfp = dsi_hbl - (hss + hsa + hse + hbp);
}
}
if (hfp < 1)
return false;
dsi_vm->hss = hss;
dsi_vm->hsa = hsa;
dsi_vm->hse = hse;
dsi_vm->hbp = hbp;
dsi_vm->hact = xres;
dsi_vm->hfp = hfp;
dsi_vm->vsa = req_vm->vsw;
dsi_vm->vbp = req_vm->vbp;
dsi_vm->vact = req_vm->y_res;
dsi_vm->vfp = req_vm->vfp;
dsi_vm->trans_mode = cfg->trans_mode;
dsi_vm->blanking_mode = 0;
dsi_vm->hsa_blanking_mode = 1;
dsi_vm->hfp_blanking_mode = 1;
dsi_vm->hbp_blanking_mode = 1;
dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
dsi_vm->window_sync = 4;
/* setup DISPC videomode */
dispc_vm = &ctx->dispc_vm;
*dispc_vm = *req_vm;
dispc_vm->pixelclock = dispc_pck;
if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
req_pck_nom);
hsa = max(hsa, 1);
} else {
hsa = 1;
}
hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
hbp = max(hbp, 1);
hfp = dispc_hbl - hsa - hbp;
if (hfp < 1) {
int t;
/* we need to take cycles from hbp */
t = 1 - hfp;
hbp = max(hbp - t, 1);
hfp = dispc_hbl - hsa - hbp;
if (hfp < 1) {
/* we need to take cycles from hsa */
t = 1 - hfp;
hsa = max(hsa - t, 1);
hfp = dispc_hbl - hsa - hbp;
}
}
if (hfp < 1)
return false;
dispc_vm->hfp = hfp;
dispc_vm->hsw = hsa;
dispc_vm->hbp = hbp;
return true;
}
static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
unsigned long pck, void *data)
{
struct dsi_clk_calc_ctx *ctx = data;
ctx->dispc_cinfo.lck_div = lckd;
ctx->dispc_cinfo.pck_div = pckd;
ctx->dispc_cinfo.lck = lck;
ctx->dispc_cinfo.pck = pck;
if (dsi_vm_calc_blanking(ctx) == false)
return false;
#ifdef PRINT_VERBOSE_VM_TIMINGS
print_dispc_vm("dispc", &ctx->dispc_vm);
print_dsi_vm("dsi ", &ctx->dsi_vm);
print_dispc_vm("req ", ctx->config->timings);
print_dsi_dispc_vm("act ", &ctx->dsi_vm);
#endif
return true;
}
static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
void *data)
{
struct dsi_clk_calc_ctx *ctx = data;
unsigned long pck_max;
ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
/*
* In burst mode we can let the dispc pck be arbitrarily high, but it
* limits our scaling abilities. So for now, don't aim too high.
*/
if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
pck_max = ctx->req_pck_max + 10000000;
else
pck_max = ctx->req_pck_max;
return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
dsi_vm_calc_dispc_cb, ctx);
}
static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
unsigned long clkdco, void *data)
{
struct dsi_clk_calc_ctx *ctx = data;
ctx->dsi_cinfo.n = n;
ctx->dsi_cinfo.m = m;
ctx->dsi_cinfo.fint = fint;
ctx->dsi_cinfo.clkdco = clkdco;
return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min,
dss_feat_get_param_max(FEAT_PARAM_DSS_FCK),
dsi_vm_calc_hsdiv_cb, ctx);
}
static bool dsi_vm_calc(struct dsi_data *dsi,
const struct omap_dss_dsi_config *cfg,
struct dsi_clk_calc_ctx *ctx)
{
const struct omap_video_timings *t = cfg->timings;
unsigned long clkin;
unsigned long pll_min;
unsigned long pll_max;
int ndl = dsi->num_lanes_used - 1;
int bitspp = dsi_get_pixel_size(cfg->pixel_format);
unsigned long byteclk_min;
clkin = clk_get_rate(dsi->pll.clkin);
memset(ctx, 0, sizeof(*ctx));
ctx->dsidev = dsi->pdev;
ctx->pll = &dsi->pll;
ctx->config = cfg;
/* these limits should come from the panel driver */
ctx->req_pck_min = t->pixelclock - 1000;
ctx->req_pck_nom = t->pixelclock;
ctx->req_pck_max = t->pixelclock + 1000;
byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
pll_max = cfg->hs_clk_max * 4;
} else {
unsigned long byteclk_max;
byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
ndl * 8);
pll_max = byteclk_max * 4 * 4;
}
return dss_pll_calc(ctx->pll, clkin,
pll_min, pll_max,
dsi_vm_calc_pll_cb, ctx);
}
static int dsi_set_config(struct omap_dss_device *dssdev,
const struct omap_dss_dsi_config *config)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct dsi_clk_calc_ctx ctx;
bool ok;
int r;
mutex_lock(&dsi->lock);
dsi->pix_fmt = config->pixel_format;
dsi->mode = config->mode;
if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
ok = dsi_vm_calc(dsi, config, &ctx);
else
ok = dsi_cm_calc(dsi, config, &ctx);
if (!ok) {
DSSERR("failed to find suitable DSI clock settings\n");
r = -EINVAL;
goto err;
}
dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI],
config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo);
if (r) {
DSSERR("failed to find suitable DSI LP clock settings\n");
goto err;
}
dsi->user_dsi_cinfo = ctx.dsi_cinfo;
dsi->user_dispc_cinfo = ctx.dispc_cinfo;
dsi->timings = ctx.dispc_vm;
dsi->vm_timings = ctx.dsi_vm;
mutex_unlock(&dsi->lock);
return 0;
err:
mutex_unlock(&dsi->lock);
return r;
}
/*
* Return a hardcoded channel for the DSI output. This should work for
* current use cases, but this can be later expanded to either resolve
* the channel in some more dynamic manner, or get the channel as a user
* parameter.
*/
static enum omap_channel dsi_get_channel(int module_id)
{
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP24xx:
case OMAPDSS_VER_AM43xx:
DSSWARN("DSI not supported\n");
return OMAP_DSS_CHANNEL_LCD;
case OMAPDSS_VER_OMAP34xx_ES1:
case OMAPDSS_VER_OMAP34xx_ES3:
case OMAPDSS_VER_OMAP3630:
case OMAPDSS_VER_AM35xx:
return OMAP_DSS_CHANNEL_LCD;
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
switch (module_id) {
case 0:
return OMAP_DSS_CHANNEL_LCD;
case 1:
return OMAP_DSS_CHANNEL_LCD2;
default:
DSSWARN("unsupported module id\n");
return OMAP_DSS_CHANNEL_LCD;
}
case OMAPDSS_VER_OMAP5:
switch (module_id) {
case 0:
return OMAP_DSS_CHANNEL_LCD;
case 1:
return OMAP_DSS_CHANNEL_LCD3;
default:
DSSWARN("unsupported module id\n");
return OMAP_DSS_CHANNEL_LCD;
}
default:
DSSWARN("unsupported DSS version\n");
return OMAP_DSS_CHANNEL_LCD;
}
}
static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
if (!dsi->vc[i].dssdev) {
dsi->vc[i].dssdev = dssdev;
*channel = i;
return 0;
}
}
DSSERR("cannot get VC for display %s", dssdev->name);
return -ENOSPC;
}
static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
if (vc_id < 0 || vc_id > 3) {
DSSERR("VC ID out of range\n");
return -EINVAL;
}
if (channel < 0 || channel > 3) {
DSSERR("Virtual Channel out of range\n");
return -EINVAL;
}
if (dsi->vc[channel].dssdev != dssdev) {
DSSERR("Virtual Channel not allocated to display %s\n",
dssdev->name);
return -EINVAL;
}
dsi->vc[channel].vc_id = vc_id;
return 0;
}
static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
if ((channel >= 0 && channel <= 3) &&
dsi->vc[channel].dssdev == dssdev) {
dsi->vc[channel].dssdev = NULL;
dsi->vc[channel].vc_id = 0;
}
}
static int dsi_get_clocks(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct clk *clk;
clk = devm_clk_get(&dsidev->dev, "fck");
if (IS_ERR(clk)) {
DSSERR("can't get fck\n");
return PTR_ERR(clk);
}
dsi->dss_clk = clk;
return 0;
}
static int dsi_connect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct omap_overlay_manager *mgr;
int r;
r = dsi_regulator_init(dsidev);
if (r)
return r;
mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
if (!mgr)
return -ENODEV;
r = dss_mgr_connect(mgr, dssdev);
if (r)
return r;
r = omapdss_output_set_device(dssdev, dst);
if (r) {
DSSERR("failed to connect output to new device: %s\n",
dssdev->name);
dss_mgr_disconnect(mgr, dssdev);
return r;
}
return 0;
}
static void dsi_disconnect(struct omap_dss_device *dssdev,
struct omap_dss_device *dst)
{
WARN_ON(dst != dssdev->dst);
if (dst != dssdev->dst)
return;
omapdss_output_unset_device(dssdev);
if (dssdev->manager)
dss_mgr_disconnect(dssdev->manager, dssdev);
}
static const struct omapdss_dsi_ops dsi_ops = {
.connect = dsi_connect,
.disconnect = dsi_disconnect,
.bus_lock = dsi_bus_lock,
.bus_unlock = dsi_bus_unlock,
.enable = dsi_display_enable,
.disable = dsi_display_disable,
.enable_hs = dsi_vc_enable_hs,
.configure_pins = dsi_configure_pins,
.set_config = dsi_set_config,
.enable_video_output = dsi_enable_video_output,
.disable_video_output = dsi_disable_video_output,
.update = dsi_update,
.enable_te = dsi_enable_te,
.request_vc = dsi_request_vc,
.set_vc_id = dsi_set_vc_id,
.release_vc = dsi_release_vc,
.dcs_write = dsi_vc_dcs_write,
.dcs_write_nosync = dsi_vc_dcs_write_nosync,
.dcs_read = dsi_vc_dcs_read,
.gen_write = dsi_vc_generic_write,
.gen_write_nosync = dsi_vc_generic_write_nosync,
.gen_read = dsi_vc_generic_read,
.bta_sync = dsi_vc_send_bta_sync,
.set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
};
static void dsi_init_output(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct omap_dss_device *out = &dsi->output;
out->dev = &dsidev->dev;
out->id = dsi->module_id == 0 ?
OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
out->output_type = OMAP_DISPLAY_TYPE_DSI;
out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
out->dispc_channel = dsi_get_channel(dsi->module_id);
out->ops.dsi = &dsi_ops;
out->owner = THIS_MODULE;
omapdss_register_output(out);
}
static void dsi_uninit_output(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct omap_dss_device *out = &dsi->output;
omapdss_unregister_output(out);
}
static int dsi_probe_of(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
struct property *prop;
u32 lane_arr[10];
int len, num_pins;
int r, i;
struct device_node *ep;
struct omap_dsi_pin_config pin_cfg;
ep = omapdss_of_get_first_endpoint(node);
if (!ep)
return 0;
prop = of_find_property(ep, "lanes", &len);
if (prop == NULL) {
dev_err(&pdev->dev, "failed to find lane data\n");
r = -EINVAL;
goto err;
}
num_pins = len / sizeof(u32);
if (num_pins < 4 || num_pins % 2 != 0 ||
num_pins > dsi->num_lanes_supported * 2) {
dev_err(&pdev->dev, "bad number of lanes\n");
r = -EINVAL;
goto err;
}
r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
if (r) {
dev_err(&pdev->dev, "failed to read lane data\n");
goto err;
}
pin_cfg.num_pins = num_pins;
for (i = 0; i < num_pins; ++i)
pin_cfg.pins[i] = (int)lane_arr[i];
r = dsi_configure_pins(&dsi->output, &pin_cfg);
if (r) {
dev_err(&pdev->dev, "failed to configure pins");
goto err;
}
of_node_put(ep);
return 0;
err:
of_node_put(ep);
return r;
}
static const struct dss_pll_ops dsi_pll_ops = {
.enable = dsi_pll_enable,
.disable = dsi_pll_disable,
.set_config = dss_pll_write_config_type_a,
};
static const struct dss_pll_hw dss_omap3_dsi_pll_hw = {
.n_max = (1 << 7) - 1,
.m_max = (1 << 11) - 1,
.mX_max = (1 << 4) - 1,
.fint_min = 750000,
.fint_max = 2100000,
.clkdco_low = 1000000000,
.clkdco_max = 1800000000,
.n_msb = 7,
.n_lsb = 1,
.m_msb = 18,
.m_lsb = 8,
.mX_msb[0] = 22,
.mX_lsb[0] = 19,
.mX_msb[1] = 26,
.mX_lsb[1] = 23,
.has_stopmode = true,
.has_freqsel = true,
.has_selfreqdco = false,
.has_refsel = false,
};
static const struct dss_pll_hw dss_omap4_dsi_pll_hw = {
.n_max = (1 << 8) - 1,
.m_max = (1 << 12) - 1,
.mX_max = (1 << 5) - 1,
.fint_min = 500000,
.fint_max = 2500000,
.clkdco_low = 1000000000,
.clkdco_max = 1800000000,
.n_msb = 8,
.n_lsb = 1,
.m_msb = 20,
.m_lsb = 9,
.mX_msb[0] = 25,
.mX_lsb[0] = 21,
.mX_msb[1] = 30,
.mX_lsb[1] = 26,
.has_stopmode = true,
.has_freqsel = false,
.has_selfreqdco = false,
.has_refsel = false,
};
static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
.n_max = (1 << 8) - 1,
.m_max = (1 << 12) - 1,
.mX_max = (1 << 5) - 1,
.fint_min = 150000,
.fint_max = 52000000,
.clkdco_low = 1000000000,
.clkdco_max = 1800000000,
.n_msb = 8,
.n_lsb = 1,
.m_msb = 20,
.m_lsb = 9,
.mX_msb[0] = 25,
.mX_lsb[0] = 21,
.mX_msb[1] = 30,
.mX_lsb[1] = 26,
.has_stopmode = true,
.has_freqsel = false,
.has_selfreqdco = true,
.has_refsel = true,
};
static int dsi_init_pll_data(struct platform_device *dsidev)
{
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct dss_pll *pll = &dsi->pll;
struct clk *clk;
int r;
clk = devm_clk_get(&dsidev->dev, "sys_clk");
if (IS_ERR(clk)) {
DSSERR("can't get sys_clk\n");
return PTR_ERR(clk);
}
pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1";
pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2;
pll->clkin = clk;
pll->base = dsi->pll_base;
switch (omapdss_get_version()) {
case OMAPDSS_VER_OMAP34xx_ES1:
case OMAPDSS_VER_OMAP34xx_ES3:
case OMAPDSS_VER_OMAP3630:
case OMAPDSS_VER_AM35xx:
pll->hw = &dss_omap3_dsi_pll_hw;
break;
case OMAPDSS_VER_OMAP4430_ES1:
case OMAPDSS_VER_OMAP4430_ES2:
case OMAPDSS_VER_OMAP4:
pll->hw = &dss_omap4_dsi_pll_hw;
break;
case OMAPDSS_VER_OMAP5:
pll->hw = &dss_omap5_dsi_pll_hw;
break;
default:
return -ENODEV;
}
pll->ops = &dsi_pll_ops;
r = dss_pll_register(pll);
if (r)
return r;
return 0;
}
/* DSI1 HW IP initialisation */
static int dsi_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *dsidev = to_platform_device(dev);
u32 rev;
int r, i;
struct dsi_data *dsi;
struct resource *dsi_mem;
struct resource *res;
struct resource temp_res;
dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
if (!dsi)
return -ENOMEM;
dsi->pdev = dsidev;
platform_set_drvdata(dsidev, dsi);
spin_lock_init(&dsi->irq_lock);
spin_lock_init(&dsi->errors_lock);
dsi->errors = 0;
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
spin_lock_init(&dsi->irq_stats_lock);
dsi->irq_stats.last_reset = jiffies;
#endif
mutex_init(&dsi->lock);
sema_init(&dsi->bus_lock, 1);
INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
dsi_framedone_timeout_work_callback);
#ifdef DSI_CATCH_MISSING_TE
timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
#endif
res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
if (!res) {
res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
if (!res) {
DSSERR("can't get IORESOURCE_MEM DSI\n");
return -EINVAL;
}
temp_res.start = res->start;
temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
res = &temp_res;
}
dsi_mem = res;
dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
resource_size(res));
if (!dsi->proto_base) {
DSSERR("can't ioremap DSI protocol engine\n");
return -ENOMEM;
}
res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
if (!res) {
res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
if (!res) {
DSSERR("can't get IORESOURCE_MEM DSI\n");
return -EINVAL;
}
temp_res.start = res->start + DSI_PHY_OFFSET;
temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
res = &temp_res;
}
dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
resource_size(res));
if (!dsi->phy_base) {
DSSERR("can't ioremap DSI PHY\n");
return -ENOMEM;
}
res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
if (!res) {
res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
if (!res) {
DSSERR("can't get IORESOURCE_MEM DSI\n");
return -EINVAL;
}
temp_res.start = res->start + DSI_PLL_OFFSET;
temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
res = &temp_res;
}
dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
resource_size(res));
if (!dsi->pll_base) {
DSSERR("can't ioremap DSI PLL\n");
return -ENOMEM;
}
dsi->irq = platform_get_irq(dsi->pdev, 0);
if (dsi->irq < 0) {
DSSERR("platform_get_irq failed\n");
return -ENODEV;
}
r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
if (r < 0) {
DSSERR("request_irq failed\n");
return r;
}
if (dsidev->dev.of_node) {
const struct of_device_id *match;
const struct dsi_module_id_data *d;
match = of_match_node(dsi_of_match, dsidev->dev.of_node);
if (!match) {
DSSERR("unsupported DSI module\n");
return -ENODEV;
}
d = match->data;
while (d->address != 0 && d->address != dsi_mem->start)
d++;
if (d->address == 0) {
DSSERR("unsupported DSI module\n");
return -ENODEV;
}
dsi->module_id = d->id;
} else {
dsi->module_id = dsidev->id;
}
/* DSI VCs initialization */
for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
dsi->vc[i].source = DSI_VC_SOURCE_L4;
dsi->vc[i].dssdev = NULL;
dsi->vc[i].vc_id = 0;
}
r = dsi_get_clocks(dsidev);
if (r)
return r;
dsi_init_pll_data(dsidev);
pm_runtime_enable(&dsidev->dev);
r = dsi_runtime_get(dsidev);
if (r)
goto err_runtime_get;
rev = dsi_read_reg(dsidev, DSI_REVISION);
dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
* of data to 3 by default */
if (dss_has_feature(FEAT_DSI_GNQ))
/* NB_DATA_LANES */
dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
else
dsi->num_lanes_supported = 3;
dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
dsi_init_output(dsidev);
if (dsidev->dev.of_node) {
r = dsi_probe_of(dsidev);
if (r) {
DSSERR("Invalid DSI DT data\n");
goto err_probe_of;
}
r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
&dsidev->dev);
if (r)
DSSERR("Failed to populate DSI child devices: %d\n", r);
}
dsi_runtime_put(dsidev);
if (dsi->module_id == 0)
dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
else if (dsi->module_id == 1)
dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
#ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS
if (dsi->module_id == 0)
dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
else if (dsi->module_id == 1)
dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
#endif
return 0;
err_probe_of:
dsi_uninit_output(dsidev);
dsi_runtime_put(dsidev);
err_runtime_get:
pm_runtime_disable(&dsidev->dev);
return r;
}
static void dsi_unbind(struct device *dev, struct device *master, void *data)
{
struct platform_device *dsidev = to_platform_device(dev);
struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
of_platform_depopulate(&dsidev->dev);
WARN_ON(dsi->scp_clk_refcount > 0);
dss_pll_unregister(&dsi->pll);
dsi_uninit_output(dsidev);
pm_runtime_disable(&dsidev->dev);
if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
regulator_disable(dsi->vdds_dsi_reg);
dsi->vdds_dsi_enabled = false;
}
}
static const struct component_ops dsi_component_ops = {
.bind = dsi_bind,
.unbind = dsi_unbind,
};
static int dsi_probe(struct platform_device *pdev)
{
return component_add(&pdev->dev, &dsi_component_ops);
}
static void dsi_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &dsi_component_ops);
}
static int dsi_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
dsi->is_enabled = false;
/* ensure the irq handler sees the is_enabled value */
smp_wmb();
/* wait for current handler to finish before turning the DSI off */
synchronize_irq(dsi->irq);
dispc_runtime_put();
return 0;
}
static int dsi_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
int r;
r = dispc_runtime_get();
if (r)
return r;
dsi->is_enabled = true;
/* ensure the irq handler sees the is_enabled value */
smp_wmb();
return 0;
}
static const struct dev_pm_ops dsi_pm_ops = {
.runtime_suspend = dsi_runtime_suspend,
.runtime_resume = dsi_runtime_resume,
};
static const struct dsi_module_id_data dsi_of_data_omap3[] = {
{ .address = 0x4804fc00, .id = 0, },
{ },
};
static const struct dsi_module_id_data dsi_of_data_omap4[] = {
{ .address = 0x58004000, .id = 0, },
{ .address = 0x58005000, .id = 1, },
{ },
};
static const struct dsi_module_id_data dsi_of_data_omap5[] = {
{ .address = 0x58004000, .id = 0, },
{ .address = 0x58009000, .id = 1, },
{ },
};
static const struct of_device_id dsi_of_match[] = {
{ .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
{ .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
{ .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, },
{},
};
static struct platform_driver omap_dsihw_driver = {
.probe = dsi_probe,
.remove_new = dsi_remove,
.driver = {
.name = "omapdss_dsi",
.pm = &dsi_pm_ops,
.of_match_table = dsi_of_match,
.suppress_bind_attrs = true,
},
};
int __init dsi_init_platform_driver(void)
{
return platform_driver_register(&omap_dsihw_driver);
}
void dsi_uninit_platform_driver(void)
{
platform_driver_unregister(&omap_dsihw_driver);
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/dsi.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/omap2/dss/manager.c
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <[email protected]>
*
* Some code and ideas taken from drivers/video/omap/ driver
* by Imre Deak.
*/
#define DSS_SUBSYS_NAME "MANAGER"
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/jiffies.h>
#include <video/omapfb_dss.h>
#include "dss.h"
#include "dss_features.h"
static int num_managers;
static struct omap_overlay_manager *managers;
int dss_init_overlay_managers(void)
{
int i;
num_managers = dss_feat_get_num_mgrs();
managers = kcalloc(num_managers, sizeof(struct omap_overlay_manager),
GFP_KERNEL);
BUG_ON(managers == NULL);
for (i = 0; i < num_managers; ++i) {
struct omap_overlay_manager *mgr = &managers[i];
switch (i) {
case 0:
mgr->name = "lcd";
mgr->id = OMAP_DSS_CHANNEL_LCD;
break;
case 1:
mgr->name = "tv";
mgr->id = OMAP_DSS_CHANNEL_DIGIT;
break;
case 2:
mgr->name = "lcd2";
mgr->id = OMAP_DSS_CHANNEL_LCD2;
break;
case 3:
mgr->name = "lcd3";
mgr->id = OMAP_DSS_CHANNEL_LCD3;
break;
}
mgr->supported_displays =
dss_feat_get_supported_displays(mgr->id);
mgr->supported_outputs =
dss_feat_get_supported_outputs(mgr->id);
INIT_LIST_HEAD(&mgr->overlays);
}
return 0;
}
int dss_init_overlay_managers_sysfs(struct platform_device *pdev)
{
int i, r;
for (i = 0; i < num_managers; ++i) {
struct omap_overlay_manager *mgr = &managers[i];
r = dss_manager_kobj_init(mgr, pdev);
if (r)
DSSERR("failed to create sysfs file\n");
}
return 0;
}
void dss_uninit_overlay_managers(void)
{
kfree(managers);
managers = NULL;
num_managers = 0;
}
void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev)
{
int i;
for (i = 0; i < num_managers; ++i) {
struct omap_overlay_manager *mgr = &managers[i];
dss_manager_kobj_uninit(mgr);
}
}
int omap_dss_get_num_overlay_managers(void)
{
return num_managers;
}
EXPORT_SYMBOL(omap_dss_get_num_overlay_managers);
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num)
{
if (num >= num_managers)
return NULL;
return &managers[num];
}
EXPORT_SYMBOL(omap_dss_get_overlay_manager);
int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
const struct omap_overlay_manager_info *info)
{
if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) {
/*
* OMAP3 supports only graphics source transparency color key
* and alpha blending simultaneously. See TRM 15.4.2.4.2.2
* Alpha Mode.
*/
if (info->partial_alpha_enabled && info->trans_enabled
&& info->trans_key_type != OMAP_DSS_COLOR_KEY_GFX_DST) {
DSSERR("check_manager: illegal transparency key\n");
return -EINVAL;
}
}
return 0;
}
static int dss_mgr_check_zorder(struct omap_overlay_manager *mgr,
struct omap_overlay_info **overlay_infos)
{
struct omap_overlay *ovl1, *ovl2;
struct omap_overlay_info *info1, *info2;
list_for_each_entry(ovl1, &mgr->overlays, list) {
info1 = overlay_infos[ovl1->id];
if (info1 == NULL)
continue;
list_for_each_entry(ovl2, &mgr->overlays, list) {
if (ovl1 == ovl2)
continue;
info2 = overlay_infos[ovl2->id];
if (info2 == NULL)
continue;
if (info1->zorder == info2->zorder) {
DSSERR("overlays %d and %d have the same "
"zorder %d\n",
ovl1->id, ovl2->id, info1->zorder);
return -EINVAL;
}
}
}
return 0;
}
int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
const struct omap_video_timings *timings)
{
if (!dispc_mgr_timings_ok(mgr->id, timings)) {
DSSERR("check_manager: invalid timings\n");
return -EINVAL;
}
return 0;
}
static int dss_mgr_check_lcd_config(struct omap_overlay_manager *mgr,
const struct dss_lcd_mgr_config *config)
{
struct dispc_clock_info cinfo = config->clock_info;
int dl = config->video_port_width;
bool stallmode = config->stallmode;
bool fifohandcheck = config->fifohandcheck;
if (cinfo.lck_div < 1 || cinfo.lck_div > 255)
return -EINVAL;
if (cinfo.pck_div < 1 || cinfo.pck_div > 255)
return -EINVAL;
if (dl != 12 && dl != 16 && dl != 18 && dl != 24)
return -EINVAL;
/* fifohandcheck should be used only with stallmode */
if (!stallmode && fifohandcheck)
return -EINVAL;
/*
* io pad mode can be only checked by using dssdev connected to the
* manager. Ignore checking these for now, add checks when manager
* is capable of holding information related to the connected interface
*/
return 0;
}
int dss_mgr_check(struct omap_overlay_manager *mgr,
struct omap_overlay_manager_info *info,
const struct omap_video_timings *mgr_timings,
const struct dss_lcd_mgr_config *lcd_config,
struct omap_overlay_info **overlay_infos)
{
struct omap_overlay *ovl;
int r;
if (dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) {
r = dss_mgr_check_zorder(mgr, overlay_infos);
if (r)
return r;
}
r = dss_mgr_check_timings(mgr, mgr_timings);
if (r)
return r;
r = dss_mgr_check_lcd_config(mgr, lcd_config);
if (r)
return r;
list_for_each_entry(ovl, &mgr->overlays, list) {
struct omap_overlay_info *oi;
int r;
oi = overlay_infos[ovl->id];
if (oi == NULL)
continue;
r = dss_ovl_check(ovl, oi, mgr_timings);
if (r)
return r;
}
return 0;
}
| linux-master | drivers/video/fbdev/omap2/omapfb/dss/manager.c |
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