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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* lms501kf03 TFT LCD panel driver.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* Author: Jingoo Han <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/lcd.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#include <linux/wait.h>
#define COMMAND_ONLY 0x00
#define DATA_ONLY 0x01
struct lms501kf03 {
struct device *dev;
struct spi_device *spi;
unsigned int power;
struct lcd_device *ld;
struct lcd_platform_data *lcd_pd;
};
static const unsigned char seq_password[] = {
0xb9, 0xff, 0x83, 0x69,
};
static const unsigned char seq_power[] = {
0xb1, 0x01, 0x00, 0x34, 0x06, 0x00, 0x14, 0x14, 0x20, 0x28,
0x12, 0x12, 0x17, 0x0a, 0x01, 0xe6, 0xe6, 0xe6, 0xe6, 0xe6,
};
static const unsigned char seq_display[] = {
0xb2, 0x00, 0x2b, 0x03, 0x03, 0x70, 0x00, 0xff, 0x00, 0x00,
0x00, 0x00, 0x03, 0x03, 0x00, 0x01,
};
static const unsigned char seq_rgb_if[] = {
0xb3, 0x09,
};
static const unsigned char seq_display_inv[] = {
0xb4, 0x01, 0x08, 0x77, 0x0e, 0x06,
};
static const unsigned char seq_vcom[] = {
0xb6, 0x4c, 0x2e,
};
static const unsigned char seq_gate[] = {
0xd5, 0x00, 0x05, 0x03, 0x29, 0x01, 0x07, 0x17, 0x68, 0x13,
0x37, 0x20, 0x31, 0x8a, 0x46, 0x9b, 0x57, 0x13, 0x02, 0x75,
0xb9, 0x64, 0xa8, 0x07, 0x0f, 0x04, 0x07,
};
static const unsigned char seq_panel[] = {
0xcc, 0x02,
};
static const unsigned char seq_col_mod[] = {
0x3a, 0x77,
};
static const unsigned char seq_w_gamma[] = {
0xe0, 0x00, 0x04, 0x09, 0x0f, 0x1f, 0x3f, 0x1f, 0x2f, 0x0a,
0x0f, 0x10, 0x16, 0x18, 0x16, 0x17, 0x0d, 0x15, 0x00, 0x04,
0x09, 0x0f, 0x38, 0x3f, 0x20, 0x39, 0x0a, 0x0f, 0x10, 0x16,
0x18, 0x16, 0x17, 0x0d, 0x15,
};
static const unsigned char seq_rgb_gamma[] = {
0xc1, 0x01, 0x03, 0x07, 0x0f, 0x1a, 0x22, 0x2c, 0x33, 0x3c,
0x46, 0x4f, 0x58, 0x60, 0x69, 0x71, 0x79, 0x82, 0x89, 0x92,
0x9a, 0xa1, 0xa9, 0xb1, 0xb9, 0xc1, 0xc9, 0xcf, 0xd6, 0xde,
0xe5, 0xec, 0xf3, 0xf9, 0xff, 0xdd, 0x39, 0x07, 0x1c, 0xcb,
0xab, 0x5f, 0x49, 0x80, 0x03, 0x07, 0x0f, 0x19, 0x20, 0x2a,
0x31, 0x39, 0x42, 0x4b, 0x53, 0x5b, 0x63, 0x6b, 0x73, 0x7b,
0x83, 0x8a, 0x92, 0x9b, 0xa2, 0xaa, 0xb2, 0xba, 0xc2, 0xca,
0xd0, 0xd8, 0xe1, 0xe8, 0xf0, 0xf8, 0xff, 0xf7, 0xd8, 0xbe,
0xa7, 0x39, 0x40, 0x85, 0x8c, 0xc0, 0x04, 0x07, 0x0c, 0x17,
0x1c, 0x23, 0x2b, 0x34, 0x3b, 0x43, 0x4c, 0x54, 0x5b, 0x63,
0x6a, 0x73, 0x7a, 0x82, 0x8a, 0x91, 0x98, 0xa1, 0xa8, 0xb0,
0xb7, 0xc1, 0xc9, 0xcf, 0xd9, 0xe3, 0xea, 0xf4, 0xff, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
static const unsigned char seq_sleep_out[] = {
0x11,
};
static const unsigned char seq_display_on[] = {
0x29,
};
static const unsigned char seq_display_off[] = {
0x10,
};
static int lms501kf03_spi_write_byte(struct lms501kf03 *lcd, int addr, int data)
{
u16 buf[1];
struct spi_message msg;
struct spi_transfer xfer = {
.len = 2,
.tx_buf = buf,
};
buf[0] = (addr << 8) | data;
spi_message_init(&msg);
spi_message_add_tail(&xfer, &msg);
return spi_sync(lcd->spi, &msg);
}
static int lms501kf03_spi_write(struct lms501kf03 *lcd, unsigned char address,
unsigned char command)
{
return lms501kf03_spi_write_byte(lcd, address, command);
}
static int lms501kf03_panel_send_sequence(struct lms501kf03 *lcd,
const unsigned char *wbuf,
unsigned int len)
{
int ret = 0, i = 0;
while (i < len) {
if (i == 0)
ret = lms501kf03_spi_write(lcd, COMMAND_ONLY, wbuf[i]);
else
ret = lms501kf03_spi_write(lcd, DATA_ONLY, wbuf[i]);
if (ret)
break;
i += 1;
}
return ret;
}
static int lms501kf03_ldi_init(struct lms501kf03 *lcd)
{
int ret, i;
static const unsigned char *init_seq[] = {
seq_password,
seq_power,
seq_display,
seq_rgb_if,
seq_display_inv,
seq_vcom,
seq_gate,
seq_panel,
seq_col_mod,
seq_w_gamma,
seq_rgb_gamma,
seq_sleep_out,
};
static const unsigned int size_seq[] = {
ARRAY_SIZE(seq_password),
ARRAY_SIZE(seq_power),
ARRAY_SIZE(seq_display),
ARRAY_SIZE(seq_rgb_if),
ARRAY_SIZE(seq_display_inv),
ARRAY_SIZE(seq_vcom),
ARRAY_SIZE(seq_gate),
ARRAY_SIZE(seq_panel),
ARRAY_SIZE(seq_col_mod),
ARRAY_SIZE(seq_w_gamma),
ARRAY_SIZE(seq_rgb_gamma),
ARRAY_SIZE(seq_sleep_out),
};
for (i = 0; i < ARRAY_SIZE(init_seq); i++) {
ret = lms501kf03_panel_send_sequence(lcd, init_seq[i],
size_seq[i]);
if (ret)
break;
}
/*
* According to the datasheet, 120ms delay time is required.
* After sleep out sequence, command is blocked for 120ms.
* Thus, LDI should wait for 120ms.
*/
msleep(120);
return ret;
}
static int lms501kf03_ldi_enable(struct lms501kf03 *lcd)
{
return lms501kf03_panel_send_sequence(lcd, seq_display_on,
ARRAY_SIZE(seq_display_on));
}
static int lms501kf03_ldi_disable(struct lms501kf03 *lcd)
{
return lms501kf03_panel_send_sequence(lcd, seq_display_off,
ARRAY_SIZE(seq_display_off));
}
static int lms501kf03_power_is_on(int power)
{
return (power) <= FB_BLANK_NORMAL;
}
static int lms501kf03_power_on(struct lms501kf03 *lcd)
{
int ret = 0;
struct lcd_platform_data *pd;
pd = lcd->lcd_pd;
if (!pd->power_on) {
dev_err(lcd->dev, "power_on is NULL.\n");
return -EINVAL;
}
pd->power_on(lcd->ld, 1);
msleep(pd->power_on_delay);
if (!pd->reset) {
dev_err(lcd->dev, "reset is NULL.\n");
return -EINVAL;
}
pd->reset(lcd->ld);
msleep(pd->reset_delay);
ret = lms501kf03_ldi_init(lcd);
if (ret) {
dev_err(lcd->dev, "failed to initialize ldi.\n");
return ret;
}
ret = lms501kf03_ldi_enable(lcd);
if (ret) {
dev_err(lcd->dev, "failed to enable ldi.\n");
return ret;
}
return 0;
}
static int lms501kf03_power_off(struct lms501kf03 *lcd)
{
int ret = 0;
struct lcd_platform_data *pd;
pd = lcd->lcd_pd;
ret = lms501kf03_ldi_disable(lcd);
if (ret) {
dev_err(lcd->dev, "lcd setting failed.\n");
return -EIO;
}
msleep(pd->power_off_delay);
pd->power_on(lcd->ld, 0);
return 0;
}
static int lms501kf03_power(struct lms501kf03 *lcd, int power)
{
int ret = 0;
if (lms501kf03_power_is_on(power) &&
!lms501kf03_power_is_on(lcd->power))
ret = lms501kf03_power_on(lcd);
else if (!lms501kf03_power_is_on(power) &&
lms501kf03_power_is_on(lcd->power))
ret = lms501kf03_power_off(lcd);
if (!ret)
lcd->power = power;
return ret;
}
static int lms501kf03_get_power(struct lcd_device *ld)
{
struct lms501kf03 *lcd = lcd_get_data(ld);
return lcd->power;
}
static int lms501kf03_set_power(struct lcd_device *ld, int power)
{
struct lms501kf03 *lcd = lcd_get_data(ld);
if (power != FB_BLANK_UNBLANK && power != FB_BLANK_POWERDOWN &&
power != FB_BLANK_NORMAL) {
dev_err(lcd->dev, "power value should be 0, 1 or 4.\n");
return -EINVAL;
}
return lms501kf03_power(lcd, power);
}
static struct lcd_ops lms501kf03_lcd_ops = {
.get_power = lms501kf03_get_power,
.set_power = lms501kf03_set_power,
};
static int lms501kf03_probe(struct spi_device *spi)
{
struct lms501kf03 *lcd = NULL;
struct lcd_device *ld = NULL;
int ret = 0;
lcd = devm_kzalloc(&spi->dev, sizeof(struct lms501kf03), GFP_KERNEL);
if (!lcd)
return -ENOMEM;
/* lms501kf03 lcd panel uses 3-wire 9-bit SPI Mode. */
spi->bits_per_word = 9;
ret = spi_setup(spi);
if (ret < 0) {
dev_err(&spi->dev, "spi setup failed.\n");
return ret;
}
lcd->spi = spi;
lcd->dev = &spi->dev;
lcd->lcd_pd = dev_get_platdata(&spi->dev);
if (!lcd->lcd_pd) {
dev_err(&spi->dev, "platform data is NULL\n");
return -EINVAL;
}
ld = devm_lcd_device_register(&spi->dev, "lms501kf03", &spi->dev, lcd,
&lms501kf03_lcd_ops);
if (IS_ERR(ld))
return PTR_ERR(ld);
lcd->ld = ld;
if (!lcd->lcd_pd->lcd_enabled) {
/*
* if lcd panel was off from bootloader then
* current lcd status is powerdown and then
* it enables lcd panel.
*/
lcd->power = FB_BLANK_POWERDOWN;
lms501kf03_power(lcd, FB_BLANK_UNBLANK);
} else {
lcd->power = FB_BLANK_UNBLANK;
}
spi_set_drvdata(spi, lcd);
dev_info(&spi->dev, "lms501kf03 panel driver has been probed.\n");
return 0;
}
static void lms501kf03_remove(struct spi_device *spi)
{
struct lms501kf03 *lcd = spi_get_drvdata(spi);
lms501kf03_power(lcd, FB_BLANK_POWERDOWN);
}
#ifdef CONFIG_PM_SLEEP
static int lms501kf03_suspend(struct device *dev)
{
struct lms501kf03 *lcd = dev_get_drvdata(dev);
dev_dbg(dev, "lcd->power = %d\n", lcd->power);
/*
* when lcd panel is suspend, lcd panel becomes off
* regardless of status.
*/
return lms501kf03_power(lcd, FB_BLANK_POWERDOWN);
}
static int lms501kf03_resume(struct device *dev)
{
struct lms501kf03 *lcd = dev_get_drvdata(dev);
lcd->power = FB_BLANK_POWERDOWN;
return lms501kf03_power(lcd, FB_BLANK_UNBLANK);
}
#endif
static SIMPLE_DEV_PM_OPS(lms501kf03_pm_ops, lms501kf03_suspend,
lms501kf03_resume);
static void lms501kf03_shutdown(struct spi_device *spi)
{
struct lms501kf03 *lcd = spi_get_drvdata(spi);
lms501kf03_power(lcd, FB_BLANK_POWERDOWN);
}
static struct spi_driver lms501kf03_driver = {
.driver = {
.name = "lms501kf03",
.pm = &lms501kf03_pm_ops,
},
.probe = lms501kf03_probe,
.remove = lms501kf03_remove,
.shutdown = lms501kf03_shutdown,
};
module_spi_driver(lms501kf03_driver);
MODULE_AUTHOR("Jingoo Han <[email protected]>");
MODULE_DESCRIPTION("lms501kf03 LCD Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/backlight/lms501kf03.c |
// SPDX-License-Identifier: GPL-2.0
/*
* AS3711 PMIC backlight driver, using DCDC Step Up Converters
*
* Copyright (C) 2012 Renesas Electronics Corporation
* Author: Guennadi Liakhovetski, <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/kernel.h>
#include <linux/mfd/as3711.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
enum as3711_bl_type {
AS3711_BL_SU1,
AS3711_BL_SU2,
};
struct as3711_bl_data {
bool powered;
enum as3711_bl_type type;
int brightness;
struct backlight_device *bl;
};
struct as3711_bl_supply {
struct as3711_bl_data su1;
struct as3711_bl_data su2;
const struct as3711_bl_pdata *pdata;
struct as3711 *as3711;
};
static struct as3711_bl_supply *to_supply(struct as3711_bl_data *su)
{
switch (su->type) {
case AS3711_BL_SU1:
return container_of(su, struct as3711_bl_supply, su1);
case AS3711_BL_SU2:
return container_of(su, struct as3711_bl_supply, su2);
}
return NULL;
}
static int as3711_set_brightness_auto_i(struct as3711_bl_data *data,
unsigned int brightness)
{
struct as3711_bl_supply *supply = to_supply(data);
struct as3711 *as3711 = supply->as3711;
const struct as3711_bl_pdata *pdata = supply->pdata;
int ret = 0;
/* Only all equal current values are supported */
if (pdata->su2_auto_curr1)
ret = regmap_write(as3711->regmap, AS3711_CURR1_VALUE,
brightness);
if (!ret && pdata->su2_auto_curr2)
ret = regmap_write(as3711->regmap, AS3711_CURR2_VALUE,
brightness);
if (!ret && pdata->su2_auto_curr3)
ret = regmap_write(as3711->regmap, AS3711_CURR3_VALUE,
brightness);
return ret;
}
static int as3711_set_brightness_v(struct as3711 *as3711,
unsigned int brightness,
unsigned int reg)
{
if (brightness > 31)
return -EINVAL;
return regmap_update_bits(as3711->regmap, reg, 0xf0,
brightness << 4);
}
static int as3711_bl_su2_reset(struct as3711_bl_supply *supply)
{
struct as3711 *as3711 = supply->as3711;
int ret = regmap_update_bits(as3711->regmap, AS3711_STEPUP_CONTROL_5,
3, supply->pdata->su2_fbprot);
if (!ret)
ret = regmap_update_bits(as3711->regmap,
AS3711_STEPUP_CONTROL_2, 1, 0);
if (!ret)
ret = regmap_update_bits(as3711->regmap,
AS3711_STEPUP_CONTROL_2, 1, 1);
return ret;
}
/*
* Someone with less fragile or less expensive hardware could try to simplify
* the brightness adjustment procedure.
*/
static int as3711_bl_update_status(struct backlight_device *bl)
{
struct as3711_bl_data *data = bl_get_data(bl);
struct as3711_bl_supply *supply = to_supply(data);
struct as3711 *as3711 = supply->as3711;
int brightness;
int ret = 0;
brightness = backlight_get_brightness(bl);
if (data->type == AS3711_BL_SU1) {
ret = as3711_set_brightness_v(as3711, brightness,
AS3711_STEPUP_CONTROL_1);
} else {
const struct as3711_bl_pdata *pdata = supply->pdata;
switch (pdata->su2_feedback) {
case AS3711_SU2_VOLTAGE:
ret = as3711_set_brightness_v(as3711, brightness,
AS3711_STEPUP_CONTROL_2);
break;
case AS3711_SU2_CURR_AUTO:
ret = as3711_set_brightness_auto_i(data, brightness / 4);
if (ret < 0)
return ret;
if (brightness) {
ret = as3711_bl_su2_reset(supply);
if (ret < 0)
return ret;
udelay(500);
ret = as3711_set_brightness_auto_i(data, brightness);
} else {
ret = regmap_update_bits(as3711->regmap,
AS3711_STEPUP_CONTROL_2, 1, 0);
}
break;
/* Manual one current feedback pin below */
case AS3711_SU2_CURR1:
ret = regmap_write(as3711->regmap, AS3711_CURR1_VALUE,
brightness);
break;
case AS3711_SU2_CURR2:
ret = regmap_write(as3711->regmap, AS3711_CURR2_VALUE,
brightness);
break;
case AS3711_SU2_CURR3:
ret = regmap_write(as3711->regmap, AS3711_CURR3_VALUE,
brightness);
break;
default:
ret = -EINVAL;
}
}
if (!ret)
data->brightness = brightness;
return ret;
}
static int as3711_bl_get_brightness(struct backlight_device *bl)
{
struct as3711_bl_data *data = bl_get_data(bl);
return data->brightness;
}
static const struct backlight_ops as3711_bl_ops = {
.update_status = as3711_bl_update_status,
.get_brightness = as3711_bl_get_brightness,
};
static int as3711_bl_init_su2(struct as3711_bl_supply *supply)
{
struct as3711 *as3711 = supply->as3711;
const struct as3711_bl_pdata *pdata = supply->pdata;
u8 ctl = 0;
int ret;
dev_dbg(as3711->dev, "%s(): use %u\n", __func__, pdata->su2_feedback);
/* Turn SU2 off */
ret = regmap_write(as3711->regmap, AS3711_STEPUP_CONTROL_2, 0);
if (ret < 0)
return ret;
switch (pdata->su2_feedback) {
case AS3711_SU2_VOLTAGE:
ret = regmap_update_bits(as3711->regmap, AS3711_STEPUP_CONTROL_4, 3, 0);
break;
case AS3711_SU2_CURR1:
ctl = 1;
ret = regmap_update_bits(as3711->regmap, AS3711_STEPUP_CONTROL_4, 3, 1);
break;
case AS3711_SU2_CURR2:
ctl = 4;
ret = regmap_update_bits(as3711->regmap, AS3711_STEPUP_CONTROL_4, 3, 2);
break;
case AS3711_SU2_CURR3:
ctl = 0x10;
ret = regmap_update_bits(as3711->regmap, AS3711_STEPUP_CONTROL_4, 3, 3);
break;
case AS3711_SU2_CURR_AUTO:
if (pdata->su2_auto_curr1)
ctl = 2;
if (pdata->su2_auto_curr2)
ctl |= 8;
if (pdata->su2_auto_curr3)
ctl |= 0x20;
ret = 0;
break;
default:
return -EINVAL;
}
if (!ret)
ret = regmap_write(as3711->regmap, AS3711_CURR_CONTROL, ctl);
return ret;
}
static int as3711_bl_register(struct platform_device *pdev,
unsigned int max_brightness, struct as3711_bl_data *su)
{
struct backlight_properties props = {.type = BACKLIGHT_RAW,};
struct backlight_device *bl;
/* max tuning I = 31uA for voltage- and 38250uA for current-feedback */
props.max_brightness = max_brightness;
bl = devm_backlight_device_register(&pdev->dev,
su->type == AS3711_BL_SU1 ?
"as3711-su1" : "as3711-su2",
&pdev->dev, su,
&as3711_bl_ops, &props);
if (IS_ERR(bl)) {
dev_err(&pdev->dev, "failed to register backlight\n");
return PTR_ERR(bl);
}
bl->props.brightness = props.max_brightness;
backlight_update_status(bl);
su->bl = bl;
return 0;
}
static int as3711_backlight_parse_dt(struct device *dev)
{
struct as3711_bl_pdata *pdata = dev_get_platdata(dev);
struct device_node *bl, *fb;
int ret;
bl = of_get_child_by_name(dev->parent->of_node, "backlight");
if (!bl) {
dev_dbg(dev, "backlight node not found\n");
return -ENODEV;
}
fb = of_parse_phandle(bl, "su1-dev", 0);
if (fb) {
of_node_put(fb);
pdata->su1_fb = true;
ret = of_property_read_u32(bl, "su1-max-uA", &pdata->su1_max_uA);
if (pdata->su1_max_uA <= 0)
ret = -EINVAL;
if (ret < 0)
goto err_put_bl;
}
fb = of_parse_phandle(bl, "su2-dev", 0);
if (fb) {
int count = 0;
of_node_put(fb);
pdata->su2_fb = true;
ret = of_property_read_u32(bl, "su2-max-uA", &pdata->su2_max_uA);
if (pdata->su2_max_uA <= 0)
ret = -EINVAL;
if (ret < 0)
goto err_put_bl;
if (of_property_read_bool(bl, "su2-feedback-voltage")) {
pdata->su2_feedback = AS3711_SU2_VOLTAGE;
count++;
}
if (of_property_read_bool(bl, "su2-feedback-curr1")) {
pdata->su2_feedback = AS3711_SU2_CURR1;
count++;
}
if (of_property_read_bool(bl, "su2-feedback-curr2")) {
pdata->su2_feedback = AS3711_SU2_CURR2;
count++;
}
if (of_property_read_bool(bl, "su2-feedback-curr3")) {
pdata->su2_feedback = AS3711_SU2_CURR3;
count++;
}
if (of_property_read_bool(bl, "su2-feedback-curr-auto")) {
pdata->su2_feedback = AS3711_SU2_CURR_AUTO;
count++;
}
if (count != 1) {
ret = -EINVAL;
goto err_put_bl;
}
count = 0;
if (of_property_read_bool(bl, "su2-fbprot-lx-sd4")) {
pdata->su2_fbprot = AS3711_SU2_LX_SD4;
count++;
}
if (of_property_read_bool(bl, "su2-fbprot-gpio2")) {
pdata->su2_fbprot = AS3711_SU2_GPIO2;
count++;
}
if (of_property_read_bool(bl, "su2-fbprot-gpio3")) {
pdata->su2_fbprot = AS3711_SU2_GPIO3;
count++;
}
if (of_property_read_bool(bl, "su2-fbprot-gpio4")) {
pdata->su2_fbprot = AS3711_SU2_GPIO4;
count++;
}
if (count != 1) {
ret = -EINVAL;
goto err_put_bl;
}
count = 0;
if (of_property_read_bool(bl, "su2-auto-curr1")) {
pdata->su2_auto_curr1 = true;
count++;
}
if (of_property_read_bool(bl, "su2-auto-curr2")) {
pdata->su2_auto_curr2 = true;
count++;
}
if (of_property_read_bool(bl, "su2-auto-curr3")) {
pdata->su2_auto_curr3 = true;
count++;
}
/*
* At least one su2-auto-curr* must be specified iff
* AS3711_SU2_CURR_AUTO is used
*/
if (!count ^ (pdata->su2_feedback != AS3711_SU2_CURR_AUTO)) {
ret = -EINVAL;
goto err_put_bl;
}
}
of_node_put(bl);
return 0;
err_put_bl:
of_node_put(bl);
return ret;
}
static int as3711_backlight_probe(struct platform_device *pdev)
{
struct as3711_bl_pdata *pdata = dev_get_platdata(&pdev->dev);
struct as3711 *as3711 = dev_get_drvdata(pdev->dev.parent);
struct as3711_bl_supply *supply;
struct as3711_bl_data *su;
unsigned int max_brightness;
int ret;
if (!pdata) {
dev_err(&pdev->dev, "No platform data, exiting...\n");
return -ENODEV;
}
if (pdev->dev.parent->of_node) {
ret = as3711_backlight_parse_dt(&pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "DT parsing failed: %d\n", ret);
return ret;
}
}
if (!pdata->su1_fb && !pdata->su2_fb) {
dev_err(&pdev->dev, "No framebuffer specified\n");
return -EINVAL;
}
/*
* Due to possible hardware damage I chose to block all modes,
* unsupported on my hardware. Anyone, wishing to use any of those modes
* will have to first review the code, then activate and test it.
*/
if (pdata->su1_fb ||
pdata->su2_fbprot != AS3711_SU2_GPIO4 ||
pdata->su2_feedback != AS3711_SU2_CURR_AUTO) {
dev_warn(&pdev->dev,
"Attention! An untested mode has been chosen!\n"
"Please, review the code, enable, test, and report success:-)\n");
return -EINVAL;
}
supply = devm_kzalloc(&pdev->dev, sizeof(*supply), GFP_KERNEL);
if (!supply)
return -ENOMEM;
supply->as3711 = as3711;
supply->pdata = pdata;
if (pdata->su1_fb) {
su = &supply->su1;
su->type = AS3711_BL_SU1;
max_brightness = min(pdata->su1_max_uA, 31);
ret = as3711_bl_register(pdev, max_brightness, su);
if (ret < 0)
return ret;
}
if (pdata->su2_fb) {
su = &supply->su2;
su->type = AS3711_BL_SU2;
switch (pdata->su2_fbprot) {
case AS3711_SU2_GPIO2:
case AS3711_SU2_GPIO3:
case AS3711_SU2_GPIO4:
case AS3711_SU2_LX_SD4:
break;
default:
return -EINVAL;
}
switch (pdata->su2_feedback) {
case AS3711_SU2_VOLTAGE:
max_brightness = min(pdata->su2_max_uA, 31);
break;
case AS3711_SU2_CURR1:
case AS3711_SU2_CURR2:
case AS3711_SU2_CURR3:
case AS3711_SU2_CURR_AUTO:
max_brightness = min(pdata->su2_max_uA / 150, 255);
break;
default:
return -EINVAL;
}
ret = as3711_bl_init_su2(supply);
if (ret < 0)
return ret;
ret = as3711_bl_register(pdev, max_brightness, su);
if (ret < 0)
return ret;
}
platform_set_drvdata(pdev, supply);
return 0;
}
static struct platform_driver as3711_backlight_driver = {
.driver = {
.name = "as3711-backlight",
},
.probe = as3711_backlight_probe,
};
module_platform_driver(as3711_backlight_driver);
MODULE_DESCRIPTION("Backlight Driver for AS3711 PMICs");
MODULE_AUTHOR("Guennadi Liakhovetski <[email protected]");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:as3711-backlight");
| linux-master | drivers/video/backlight/as3711_bl.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/
* Author: Tomi Valkeinen <[email protected]>
*
* Based on pwm_bl.c
*/
#include <linux/backlight.h>
#include <linux/leds.h>
#include <linux/module.h>
#include <linux/platform_device.h>
struct led_bl_data {
struct device *dev;
struct backlight_device *bl_dev;
struct led_classdev **leds;
bool enabled;
int nb_leds;
unsigned int *levels;
unsigned int default_brightness;
unsigned int max_brightness;
};
static void led_bl_set_brightness(struct led_bl_data *priv, int level)
{
int i;
int bkl_brightness;
if (priv->levels)
bkl_brightness = priv->levels[level];
else
bkl_brightness = level;
for (i = 0; i < priv->nb_leds; i++)
led_set_brightness(priv->leds[i], bkl_brightness);
priv->enabled = true;
}
static void led_bl_power_off(struct led_bl_data *priv)
{
int i;
if (!priv->enabled)
return;
for (i = 0; i < priv->nb_leds; i++)
led_set_brightness(priv->leds[i], LED_OFF);
priv->enabled = false;
}
static int led_bl_update_status(struct backlight_device *bl)
{
struct led_bl_data *priv = bl_get_data(bl);
int brightness = backlight_get_brightness(bl);
if (brightness > 0)
led_bl_set_brightness(priv, brightness);
else
led_bl_power_off(priv);
return 0;
}
static const struct backlight_ops led_bl_ops = {
.update_status = led_bl_update_status,
};
static int led_bl_get_leds(struct device *dev,
struct led_bl_data *priv)
{
int i, nb_leds, ret;
struct device_node *node = dev->of_node;
struct led_classdev **leds;
unsigned int max_brightness;
unsigned int default_brightness;
ret = of_count_phandle_with_args(node, "leds", NULL);
if (ret < 0) {
dev_err(dev, "Unable to get led count\n");
return -EINVAL;
}
nb_leds = ret;
if (nb_leds < 1) {
dev_err(dev, "At least one LED must be specified!\n");
return -EINVAL;
}
leds = devm_kzalloc(dev, sizeof(struct led_classdev *) * nb_leds,
GFP_KERNEL);
if (!leds)
return -ENOMEM;
for (i = 0; i < nb_leds; i++) {
leds[i] = devm_of_led_get(dev, i);
if (IS_ERR(leds[i]))
return PTR_ERR(leds[i]);
}
/* check that the LEDs all have the same brightness range */
max_brightness = leds[0]->max_brightness;
for (i = 1; i < nb_leds; i++) {
if (max_brightness != leds[i]->max_brightness) {
dev_err(dev, "LEDs must have identical ranges\n");
return -EINVAL;
}
}
/* get the default brightness from the first LED from the list */
default_brightness = leds[0]->brightness;
priv->nb_leds = nb_leds;
priv->leds = leds;
priv->max_brightness = max_brightness;
priv->default_brightness = default_brightness;
return 0;
}
static int led_bl_parse_levels(struct device *dev,
struct led_bl_data *priv)
{
struct device_node *node = dev->of_node;
int num_levels;
u32 value;
int ret;
if (!node)
return -ENODEV;
num_levels = of_property_count_u32_elems(node, "brightness-levels");
if (num_levels > 1) {
int i;
unsigned int db;
u32 *levels = NULL;
levels = devm_kzalloc(dev, sizeof(u32) * num_levels,
GFP_KERNEL);
if (!levels)
return -ENOMEM;
ret = of_property_read_u32_array(node, "brightness-levels",
levels,
num_levels);
if (ret < 0)
return ret;
/*
* Try to map actual LED brightness to backlight brightness
* level
*/
db = priv->default_brightness;
for (i = 0 ; i < num_levels; i++) {
if ((i && db > levels[i-1]) && db <= levels[i])
break;
}
priv->default_brightness = i;
priv->max_brightness = num_levels - 1;
priv->levels = levels;
} else if (num_levels >= 0)
dev_warn(dev, "Not enough levels defined\n");
ret = of_property_read_u32(node, "default-brightness-level", &value);
if (!ret && value <= priv->max_brightness)
priv->default_brightness = value;
else if (!ret && value > priv->max_brightness)
dev_warn(dev, "Invalid default brightness. Ignoring it\n");
return 0;
}
static int led_bl_probe(struct platform_device *pdev)
{
struct backlight_properties props;
struct led_bl_data *priv;
int ret, i;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
platform_set_drvdata(pdev, priv);
priv->dev = &pdev->dev;
ret = led_bl_get_leds(&pdev->dev, priv);
if (ret)
return ret;
ret = led_bl_parse_levels(&pdev->dev, priv);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to parse DT data\n");
return ret;
}
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = priv->max_brightness;
props.brightness = priv->default_brightness;
props.power = (priv->default_brightness > 0) ? FB_BLANK_POWERDOWN :
FB_BLANK_UNBLANK;
priv->bl_dev = backlight_device_register(dev_name(&pdev->dev),
&pdev->dev, priv, &led_bl_ops, &props);
if (IS_ERR(priv->bl_dev)) {
dev_err(&pdev->dev, "Failed to register backlight\n");
return PTR_ERR(priv->bl_dev);
}
for (i = 0; i < priv->nb_leds; i++) {
mutex_lock(&priv->leds[i]->led_access);
led_sysfs_disable(priv->leds[i]);
mutex_unlock(&priv->leds[i]->led_access);
}
backlight_update_status(priv->bl_dev);
return 0;
}
static void led_bl_remove(struct platform_device *pdev)
{
struct led_bl_data *priv = platform_get_drvdata(pdev);
struct backlight_device *bl = priv->bl_dev;
int i;
backlight_device_unregister(bl);
led_bl_power_off(priv);
for (i = 0; i < priv->nb_leds; i++)
led_sysfs_enable(priv->leds[i]);
}
static const struct of_device_id led_bl_of_match[] = {
{ .compatible = "led-backlight" },
{ }
};
MODULE_DEVICE_TABLE(of, led_bl_of_match);
static struct platform_driver led_bl_driver = {
.driver = {
.name = "led-backlight",
.of_match_table = led_bl_of_match,
},
.probe = led_bl_probe,
.remove_new = led_bl_remove,
};
module_platform_driver(led_bl_driver);
MODULE_DESCRIPTION("LED based Backlight Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:led-backlight");
| linux-master | drivers/video/backlight/led_bl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2022 Richtek Technology Corp.
*
* Author: ChiaEn Wu <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/minmax.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#define MT6370_REG_DEV_INFO 0x100
#define MT6370_REG_BL_EN 0x1A0
#define MT6370_REG_BL_BSTCTRL 0x1A1
#define MT6370_REG_BL_PWM 0x1A2
#define MT6370_REG_BL_DIM2 0x1A4
#define MT6370_VENID_MASK GENMASK(7, 4)
#define MT6370_BL_EXT_EN_MASK BIT(7)
#define MT6370_BL_EN_MASK BIT(6)
#define MT6370_BL_CODE_MASK BIT(0)
#define MT6370_BL_CH_MASK GENMASK(5, 2)
#define MT6370_BL_CH_SHIFT 2
#define MT6370_BL_DIM2_COMMON_MASK GENMASK(2, 0)
#define MT6370_BL_DIM2_COMMON_SHIFT 3
#define MT6370_BL_DIM2_6372_MASK GENMASK(5, 0)
#define MT6370_BL_DIM2_6372_SHIFT 6
#define MT6370_BL_PWM_EN_MASK BIT(7)
#define MT6370_BL_PWM_HYS_EN_MASK BIT(2)
#define MT6370_BL_PWM_HYS_SEL_MASK GENMASK(1, 0)
#define MT6370_BL_OVP_EN_MASK BIT(7)
#define MT6370_BL_OVP_SEL_MASK GENMASK(6, 5)
#define MT6370_BL_OVP_SEL_SHIFT 5
#define MT6370_BL_OC_EN_MASK BIT(3)
#define MT6370_BL_OC_SEL_MASK GENMASK(2, 1)
#define MT6370_BL_OC_SEL_SHIFT 1
#define MT6370_BL_PWM_HYS_TH_MIN_STEP 1
#define MT6370_BL_PWM_HYS_TH_MAX_STEP 64
#define MT6370_BL_OVP_MIN_UV 17000000
#define MT6370_BL_OVP_MAX_UV 29000000
#define MT6370_BL_OVP_STEP_UV 4000000
#define MT6370_BL_OCP_MIN_UA 900000
#define MT6370_BL_OCP_MAX_UA 1800000
#define MT6370_BL_OCP_STEP_UA 300000
#define MT6370_BL_MAX_COMMON_BRIGHTNESS 2048
#define MT6370_BL_MAX_6372_BRIGHTNESS 16384
#define MT6370_BL_MAX_CH 15
enum {
MT6370_VID_COMMON = 1,
MT6370_VID_6372,
};
struct mt6370_priv {
u8 dim2_mask;
u8 dim2_shift;
int def_max_brightness;
struct backlight_device *bl;
struct device *dev;
struct gpio_desc *enable_gpio;
struct regmap *regmap;
};
static int mt6370_bl_update_status(struct backlight_device *bl_dev)
{
struct mt6370_priv *priv = bl_get_data(bl_dev);
int brightness = backlight_get_brightness(bl_dev);
unsigned int enable_val;
u8 brightness_val[2];
int ret;
if (brightness) {
brightness_val[0] = (brightness - 1) & priv->dim2_mask;
brightness_val[1] = (brightness - 1) >> priv->dim2_shift;
ret = regmap_raw_write(priv->regmap, MT6370_REG_BL_DIM2,
brightness_val, sizeof(brightness_val));
if (ret)
return ret;
}
gpiod_set_value(priv->enable_gpio, !!brightness);
enable_val = brightness ? MT6370_BL_EN_MASK : 0;
return regmap_update_bits(priv->regmap, MT6370_REG_BL_EN,
MT6370_BL_EN_MASK, enable_val);
}
static int mt6370_bl_get_brightness(struct backlight_device *bl_dev)
{
struct mt6370_priv *priv = bl_get_data(bl_dev);
unsigned int enable;
u8 brightness_val[2];
int brightness, ret;
ret = regmap_read(priv->regmap, MT6370_REG_BL_EN, &enable);
if (ret)
return ret;
if (!(enable & MT6370_BL_EN_MASK))
return 0;
ret = regmap_raw_read(priv->regmap, MT6370_REG_BL_DIM2,
brightness_val, sizeof(brightness_val));
if (ret)
return ret;
brightness = brightness_val[1] << priv->dim2_shift;
brightness += brightness_val[0] & priv->dim2_mask;
return brightness + 1;
}
static const struct backlight_ops mt6370_bl_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = mt6370_bl_update_status,
.get_brightness = mt6370_bl_get_brightness,
};
static int mt6370_init_backlight_properties(struct mt6370_priv *priv,
struct backlight_properties *props)
{
struct device *dev = priv->dev;
u8 prop_val;
u32 brightness, ovp_uV, ocp_uA;
unsigned int mask, val;
int ret;
/* Vendor optional properties */
val = 0;
if (device_property_read_bool(dev, "mediatek,bled-pwm-enable"))
val |= MT6370_BL_PWM_EN_MASK;
if (device_property_read_bool(dev, "mediatek,bled-pwm-hys-enable"))
val |= MT6370_BL_PWM_HYS_EN_MASK;
ret = device_property_read_u8(dev,
"mediatek,bled-pwm-hys-input-th-steps",
&prop_val);
if (!ret) {
prop_val = clamp_val(prop_val,
MT6370_BL_PWM_HYS_TH_MIN_STEP,
MT6370_BL_PWM_HYS_TH_MAX_STEP);
prop_val = prop_val <= 1 ? 0 :
prop_val <= 4 ? 1 :
prop_val <= 16 ? 2 : 3;
val |= prop_val;
}
ret = regmap_update_bits(priv->regmap, MT6370_REG_BL_PWM,
val, val);
if (ret)
return ret;
val = 0;
if (device_property_read_bool(dev, "mediatek,bled-ovp-shutdown"))
val |= MT6370_BL_OVP_EN_MASK;
ret = device_property_read_u32(dev, "mediatek,bled-ovp-microvolt",
&ovp_uV);
if (!ret) {
ovp_uV = clamp_val(ovp_uV, MT6370_BL_OVP_MIN_UV,
MT6370_BL_OVP_MAX_UV);
ovp_uV = DIV_ROUND_UP(ovp_uV - MT6370_BL_OVP_MIN_UV,
MT6370_BL_OVP_STEP_UV);
val |= ovp_uV << MT6370_BL_OVP_SEL_SHIFT;
}
if (device_property_read_bool(dev, "mediatek,bled-ocp-shutdown"))
val |= MT6370_BL_OC_EN_MASK;
ret = device_property_read_u32(dev, "mediatek,bled-ocp-microamp",
&ocp_uA);
if (!ret) {
ocp_uA = clamp_val(ocp_uA, MT6370_BL_OCP_MIN_UA,
MT6370_BL_OCP_MAX_UA);
ocp_uA = DIV_ROUND_UP(ocp_uA - MT6370_BL_OCP_MIN_UA,
MT6370_BL_OCP_STEP_UA);
val |= ocp_uA << MT6370_BL_OC_SEL_SHIFT;
}
ret = regmap_update_bits(priv->regmap, MT6370_REG_BL_BSTCTRL,
val, val);
if (ret)
return ret;
/* Common properties */
ret = device_property_read_u32(dev, "max-brightness", &brightness);
if (ret)
brightness = priv->def_max_brightness;
props->max_brightness = min_t(u32, brightness, priv->def_max_brightness);
ret = device_property_read_u32(dev, "default-brightness", &brightness);
if (ret)
brightness = props->max_brightness;
props->brightness = min_t(u32, brightness, props->max_brightness);
val = 0;
if (device_property_read_bool(dev, "mediatek,bled-exponential-mode-enable")) {
val |= MT6370_BL_CODE_MASK;
props->scale = BACKLIGHT_SCALE_NON_LINEAR;
} else
props->scale = BACKLIGHT_SCALE_LINEAR;
ret = device_property_read_u8(dev, "mediatek,bled-channel-use",
&prop_val);
if (ret) {
dev_err(dev, "mediatek,bled-channel-use DT property missing\n");
return ret;
}
if (!prop_val || prop_val > MT6370_BL_MAX_CH) {
dev_err(dev,
"No channel specified or over than upper bound (%d)\n",
prop_val);
return -EINVAL;
}
mask = MT6370_BL_EXT_EN_MASK | MT6370_BL_CH_MASK;
val |= prop_val << MT6370_BL_CH_SHIFT;
if (priv->enable_gpio)
val |= MT6370_BL_EXT_EN_MASK;
return regmap_update_bits(priv->regmap, MT6370_REG_BL_EN, mask, val);
}
static int mt6370_check_vendor_info(struct mt6370_priv *priv)
{
/*
* Because MT6372 uses 14 bits to control the brightness,
* MT6370 and MT6371 use 11 bits. This function is used
* to check the vendor's ID and set the relative hardware
* mask, shift and default maximum brightness value that
* should be used.
*/
unsigned int dev_info, hw_vid, of_vid;
int ret;
ret = regmap_read(priv->regmap, MT6370_REG_DEV_INFO, &dev_info);
if (ret)
return ret;
of_vid = (uintptr_t)device_get_match_data(priv->dev);
hw_vid = FIELD_GET(MT6370_VENID_MASK, dev_info);
hw_vid = (hw_vid == 0x9 || hw_vid == 0xb) ? MT6370_VID_6372 : MT6370_VID_COMMON;
if (hw_vid != of_vid)
return dev_err_probe(priv->dev, -EINVAL,
"Buggy DT, wrong compatible string\n");
if (hw_vid == MT6370_VID_6372) {
priv->dim2_mask = MT6370_BL_DIM2_6372_MASK;
priv->dim2_shift = MT6370_BL_DIM2_6372_SHIFT;
priv->def_max_brightness = MT6370_BL_MAX_6372_BRIGHTNESS;
} else {
priv->dim2_mask = MT6370_BL_DIM2_COMMON_MASK;
priv->dim2_shift = MT6370_BL_DIM2_COMMON_SHIFT;
priv->def_max_brightness = MT6370_BL_MAX_COMMON_BRIGHTNESS;
}
return 0;
}
static int mt6370_bl_probe(struct platform_device *pdev)
{
struct backlight_properties props = {
.type = BACKLIGHT_RAW,
};
struct device *dev = &pdev->dev;
struct mt6370_priv *priv;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
priv->regmap = dev_get_regmap(dev->parent, NULL);
if (!priv->regmap)
return dev_err_probe(dev, -ENODEV, "Failed to get regmap\n");
ret = mt6370_check_vendor_info(priv);
if (ret)
return dev_err_probe(dev, ret, "Failed to check vendor info\n");
priv->enable_gpio = devm_gpiod_get_optional(dev, "enable",
GPIOD_OUT_HIGH);
if (IS_ERR(priv->enable_gpio))
return dev_err_probe(dev, PTR_ERR(priv->enable_gpio),
"Failed to get 'enable' gpio\n");
ret = mt6370_init_backlight_properties(priv, &props);
if (ret)
return dev_err_probe(dev, ret,
"Failed to init backlight properties\n");
priv->bl = devm_backlight_device_register(dev, pdev->name, dev, priv,
&mt6370_bl_ops, &props);
if (IS_ERR(priv->bl))
return dev_err_probe(dev, PTR_ERR(priv->bl),
"Failed to register backlight\n");
backlight_update_status(priv->bl);
platform_set_drvdata(pdev, priv);
return 0;
}
static void mt6370_bl_remove(struct platform_device *pdev)
{
struct mt6370_priv *priv = platform_get_drvdata(pdev);
struct backlight_device *bl_dev = priv->bl;
bl_dev->props.brightness = 0;
backlight_update_status(priv->bl);
}
static const struct of_device_id mt6370_bl_of_match[] = {
{ .compatible = "mediatek,mt6370-backlight", .data = (void *)MT6370_VID_COMMON },
{ .compatible = "mediatek,mt6372-backlight", .data = (void *)MT6370_VID_6372 },
{}
};
MODULE_DEVICE_TABLE(of, mt6370_bl_of_match);
static struct platform_driver mt6370_bl_driver = {
.driver = {
.name = "mt6370-backlight",
.of_match_table = mt6370_bl_of_match,
},
.probe = mt6370_bl_probe,
.remove_new = mt6370_bl_remove,
};
module_platform_driver(mt6370_bl_driver);
MODULE_AUTHOR("ChiaEn Wu <[email protected]>");
MODULE_DESCRIPTION("MediaTek MT6370 Backlight Driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/backlight/mt6370-backlight.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Backlight driver for the Kinetic KTD253
* Based on code and know-how from the Samsung GT-S7710
* Gareth Phillips <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/limits.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/slab.h>
/* Current ratio is n/32 from 1/32 to 32/32 */
#define KTD253_MIN_RATIO 1
#define KTD253_MAX_RATIO 32
#define KTD253_DEFAULT_RATIO 13
#define KTD253_T_LOW_NS (200 + 10) /* Additional 10ns as safety factor */
#define KTD253_T_HIGH_NS (200 + 10) /* Additional 10ns as safety factor */
#define KTD253_T_OFF_CRIT_NS 100000 /* 100 us, now it doesn't look good */
#define KTD253_T_OFF_MS 3
struct ktd253_backlight {
struct device *dev;
struct backlight_device *bl;
struct gpio_desc *gpiod;
u16 ratio;
};
static void ktd253_backlight_set_max_ratio(struct ktd253_backlight *ktd253)
{
gpiod_set_value_cansleep(ktd253->gpiod, 1);
ndelay(KTD253_T_HIGH_NS);
/* We always fall back to this when we power on */
}
static int ktd253_backlight_stepdown(struct ktd253_backlight *ktd253)
{
/*
* These GPIO operations absolutely can NOT sleep so no _cansleep
* suffixes, and no using GPIO expanders on slow buses for this!
*
* The maximum number of cycles of the loop is 32 so the time taken
* should nominally be:
* (T_LOW_NS + T_HIGH_NS + loop_time) * 32
*
* Architectures do not always support ndelay() and we will get a few us
* instead. If we get to a critical time limit an interrupt has likely
* occured in the low part of the loop and we need to restart from the
* top so we have the backlight in a known state.
*/
u64 ns;
ns = ktime_get_ns();
gpiod_set_value(ktd253->gpiod, 0);
ndelay(KTD253_T_LOW_NS);
gpiod_set_value(ktd253->gpiod, 1);
ns = ktime_get_ns() - ns;
if (ns >= KTD253_T_OFF_CRIT_NS) {
dev_err(ktd253->dev, "PCM on backlight took too long (%llu ns)\n", ns);
return -EAGAIN;
}
ndelay(KTD253_T_HIGH_NS);
return 0;
}
static int ktd253_backlight_update_status(struct backlight_device *bl)
{
struct ktd253_backlight *ktd253 = bl_get_data(bl);
int brightness = backlight_get_brightness(bl);
u16 target_ratio;
u16 current_ratio = ktd253->ratio;
int ret;
dev_dbg(ktd253->dev, "new brightness/ratio: %d/32\n", brightness);
target_ratio = brightness;
if (target_ratio == current_ratio)
/* This is already right */
return 0;
if (target_ratio == 0) {
gpiod_set_value_cansleep(ktd253->gpiod, 0);
/*
* We need to keep the GPIO low for at least this long
* to actually switch the KTD253 off.
*/
msleep(KTD253_T_OFF_MS);
ktd253->ratio = 0;
return 0;
}
if (current_ratio == 0) {
ktd253_backlight_set_max_ratio(ktd253);
current_ratio = KTD253_MAX_RATIO;
}
while (current_ratio != target_ratio) {
/*
* These GPIO operations absolutely can NOT sleep so no
* _cansleep suffixes, and no using GPIO expanders on
* slow buses for this!
*/
ret = ktd253_backlight_stepdown(ktd253);
if (ret == -EAGAIN) {
/*
* Something disturbed the backlight setting code when
* running so we need to bring the PWM back to a known
* state. This shouldn't happen too much.
*/
gpiod_set_value_cansleep(ktd253->gpiod, 0);
msleep(KTD253_T_OFF_MS);
ktd253_backlight_set_max_ratio(ktd253);
current_ratio = KTD253_MAX_RATIO;
} else if (current_ratio == KTD253_MIN_RATIO) {
/* After 1/32 we loop back to 32/32 */
current_ratio = KTD253_MAX_RATIO;
} else {
current_ratio--;
}
}
ktd253->ratio = current_ratio;
dev_dbg(ktd253->dev, "new ratio set to %d/32\n", target_ratio);
return 0;
}
static const struct backlight_ops ktd253_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = ktd253_backlight_update_status,
};
static int ktd253_backlight_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct backlight_device *bl;
struct ktd253_backlight *ktd253;
u32 max_brightness;
u32 brightness;
int ret;
ktd253 = devm_kzalloc(dev, sizeof(*ktd253), GFP_KERNEL);
if (!ktd253)
return -ENOMEM;
ktd253->dev = dev;
ret = device_property_read_u32(dev, "max-brightness", &max_brightness);
if (ret)
max_brightness = KTD253_MAX_RATIO;
if (max_brightness > KTD253_MAX_RATIO) {
/* Clamp brightness to hardware max */
dev_err(dev, "illegal max brightness specified\n");
max_brightness = KTD253_MAX_RATIO;
}
ret = device_property_read_u32(dev, "default-brightness", &brightness);
if (ret)
brightness = KTD253_DEFAULT_RATIO;
if (brightness > max_brightness) {
/* Clamp default brightness to max brightness */
dev_err(dev, "default brightness exceeds max brightness\n");
brightness = max_brightness;
}
ktd253->gpiod = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
if (IS_ERR(ktd253->gpiod))
return dev_err_probe(dev, PTR_ERR(ktd253->gpiod),
"gpio line missing or invalid.\n");
gpiod_set_consumer_name(ktd253->gpiod, dev_name(dev));
/* Bring backlight to a known off state */
msleep(KTD253_T_OFF_MS);
bl = devm_backlight_device_register(dev, dev_name(dev), dev, ktd253,
&ktd253_backlight_ops, NULL);
if (IS_ERR(bl)) {
dev_err(dev, "failed to register backlight\n");
return PTR_ERR(bl);
}
bl->props.max_brightness = max_brightness;
/* When we just enable the GPIO line we set max brightness */
if (brightness) {
bl->props.brightness = brightness;
bl->props.power = FB_BLANK_UNBLANK;
} else {
bl->props.brightness = 0;
bl->props.power = FB_BLANK_POWERDOWN;
}
ktd253->bl = bl;
platform_set_drvdata(pdev, bl);
backlight_update_status(bl);
return 0;
}
static const struct of_device_id ktd253_backlight_of_match[] = {
{ .compatible = "kinetic,ktd253" },
{ .compatible = "kinetic,ktd259" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, ktd253_backlight_of_match);
static struct platform_driver ktd253_backlight_driver = {
.driver = {
.name = "ktd253-backlight",
.of_match_table = ktd253_backlight_of_match,
},
.probe = ktd253_backlight_probe,
};
module_platform_driver(ktd253_backlight_driver);
MODULE_AUTHOR("Linus Walleij <[email protected]>");
MODULE_DESCRIPTION("Kinetic KTD253 Backlight Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ktd253-backlight");
| linux-master | drivers/video/backlight/ktd253-backlight.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Simple driver for Texas Instruments LM3639 Backlight + Flash LED driver chip
* Copyright (C) 2012 Texas Instruments
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/leds.h>
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/uaccess.h>
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/platform_data/lm3639_bl.h>
#define REG_DEV_ID 0x00
#define REG_CHECKSUM 0x01
#define REG_BL_CONF_1 0x02
#define REG_BL_CONF_2 0x03
#define REG_BL_CONF_3 0x04
#define REG_BL_CONF_4 0x05
#define REG_FL_CONF_1 0x06
#define REG_FL_CONF_2 0x07
#define REG_FL_CONF_3 0x08
#define REG_IO_CTRL 0x09
#define REG_ENABLE 0x0A
#define REG_FLAG 0x0B
#define REG_MAX REG_FLAG
struct lm3639_chip_data {
struct device *dev;
struct lm3639_platform_data *pdata;
struct backlight_device *bled;
struct led_classdev cdev_flash;
struct led_classdev cdev_torch;
struct regmap *regmap;
unsigned int bled_mode;
unsigned int bled_map;
unsigned int last_flag;
};
/* initialize chip */
static int lm3639_chip_init(struct lm3639_chip_data *pchip)
{
int ret;
unsigned int reg_val;
struct lm3639_platform_data *pdata = pchip->pdata;
/* input pins config. */
ret =
regmap_update_bits(pchip->regmap, REG_BL_CONF_1, 0x08,
pdata->pin_pwm);
if (ret < 0)
goto out;
reg_val = (pdata->pin_pwm & 0x40) | pdata->pin_strobe | pdata->pin_tx;
ret = regmap_update_bits(pchip->regmap, REG_IO_CTRL, 0x7C, reg_val);
if (ret < 0)
goto out;
/* init brightness */
ret = regmap_write(pchip->regmap, REG_BL_CONF_4, pdata->init_brt_led);
if (ret < 0)
goto out;
ret = regmap_write(pchip->regmap, REG_BL_CONF_3, pdata->init_brt_led);
if (ret < 0)
goto out;
/* output pins config. */
if (!pdata->init_brt_led) {
reg_val = pdata->fled_pins;
reg_val |= pdata->bled_pins;
} else {
reg_val = pdata->fled_pins;
reg_val |= pdata->bled_pins | 0x01;
}
ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x79, reg_val);
if (ret < 0)
goto out;
return ret;
out:
dev_err(pchip->dev, "i2c failed to access register\n");
return ret;
}
/* update and get brightness */
static int lm3639_bled_update_status(struct backlight_device *bl)
{
int ret;
unsigned int reg_val;
struct lm3639_chip_data *pchip = bl_get_data(bl);
struct lm3639_platform_data *pdata = pchip->pdata;
ret = regmap_read(pchip->regmap, REG_FLAG, ®_val);
if (ret < 0)
goto out;
if (reg_val != 0)
dev_info(pchip->dev, "last flag is 0x%x\n", reg_val);
/* pwm control */
if (pdata->pin_pwm) {
if (pdata->pwm_set_intensity)
pdata->pwm_set_intensity(bl->props.brightness,
pdata->max_brt_led);
else
dev_err(pchip->dev,
"No pwm control func. in plat-data\n");
return bl->props.brightness;
}
/* i2c control and set brigtness */
ret = regmap_write(pchip->regmap, REG_BL_CONF_4, bl->props.brightness);
if (ret < 0)
goto out;
ret = regmap_write(pchip->regmap, REG_BL_CONF_3, bl->props.brightness);
if (ret < 0)
goto out;
if (!bl->props.brightness)
ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x01, 0x00);
else
ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x01, 0x01);
if (ret < 0)
goto out;
return bl->props.brightness;
out:
dev_err(pchip->dev, "i2c failed to access registers\n");
return bl->props.brightness;
}
static int lm3639_bled_get_brightness(struct backlight_device *bl)
{
int ret;
unsigned int reg_val;
struct lm3639_chip_data *pchip = bl_get_data(bl);
struct lm3639_platform_data *pdata = pchip->pdata;
if (pdata->pin_pwm) {
if (pdata->pwm_get_intensity)
bl->props.brightness = pdata->pwm_get_intensity();
else
dev_err(pchip->dev,
"No pwm control func. in plat-data\n");
return bl->props.brightness;
}
ret = regmap_read(pchip->regmap, REG_BL_CONF_1, ®_val);
if (ret < 0)
goto out;
if (reg_val & 0x10)
ret = regmap_read(pchip->regmap, REG_BL_CONF_4, ®_val);
else
ret = regmap_read(pchip->regmap, REG_BL_CONF_3, ®_val);
if (ret < 0)
goto out;
bl->props.brightness = reg_val;
return bl->props.brightness;
out:
dev_err(pchip->dev, "i2c failed to access register\n");
return bl->props.brightness;
}
static const struct backlight_ops lm3639_bled_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = lm3639_bled_update_status,
.get_brightness = lm3639_bled_get_brightness,
};
/* backlight mapping mode */
static ssize_t lm3639_bled_mode_store(struct device *dev,
struct device_attribute *devAttr,
const char *buf, size_t size)
{
ssize_t ret;
struct lm3639_chip_data *pchip = dev_get_drvdata(dev);
unsigned int state;
ret = kstrtouint(buf, 10, &state);
if (ret)
goto out_input;
if (!state)
ret =
regmap_update_bits(pchip->regmap, REG_BL_CONF_1, 0x10,
0x00);
else
ret =
regmap_update_bits(pchip->regmap, REG_BL_CONF_1, 0x10,
0x10);
if (ret < 0)
goto out;
return size;
out:
dev_err(pchip->dev, "%s:i2c access fail to register\n", __func__);
return ret;
out_input:
dev_err(pchip->dev, "%s:input conversion fail\n", __func__);
return ret;
}
static DEVICE_ATTR(bled_mode, S_IWUSR, NULL, lm3639_bled_mode_store);
/* torch */
static void lm3639_torch_brightness_set(struct led_classdev *cdev,
enum led_brightness brightness)
{
int ret;
unsigned int reg_val;
struct lm3639_chip_data *pchip;
pchip = container_of(cdev, struct lm3639_chip_data, cdev_torch);
ret = regmap_read(pchip->regmap, REG_FLAG, ®_val);
if (ret < 0)
goto out;
if (reg_val != 0)
dev_info(pchip->dev, "last flag is 0x%x\n", reg_val);
/* brightness 0 means off state */
if (!brightness) {
ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x06, 0x00);
if (ret < 0)
goto out;
return;
}
ret = regmap_update_bits(pchip->regmap,
REG_FL_CONF_1, 0x70, (brightness - 1) << 4);
if (ret < 0)
goto out;
ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x06, 0x02);
if (ret < 0)
goto out;
return;
out:
dev_err(pchip->dev, "i2c failed to access register\n");
}
/* flash */
static void lm3639_flash_brightness_set(struct led_classdev *cdev,
enum led_brightness brightness)
{
int ret;
unsigned int reg_val;
struct lm3639_chip_data *pchip;
pchip = container_of(cdev, struct lm3639_chip_data, cdev_flash);
ret = regmap_read(pchip->regmap, REG_FLAG, ®_val);
if (ret < 0)
goto out;
if (reg_val != 0)
dev_info(pchip->dev, "last flag is 0x%x\n", reg_val);
/* torch off before flash control */
ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x06, 0x00);
if (ret < 0)
goto out;
/* brightness 0 means off state */
if (!brightness)
return;
ret = regmap_update_bits(pchip->regmap,
REG_FL_CONF_1, 0x0F, brightness - 1);
if (ret < 0)
goto out;
ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x06, 0x06);
if (ret < 0)
goto out;
return;
out:
dev_err(pchip->dev, "i2c failed to access register\n");
}
static const struct regmap_config lm3639_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = REG_MAX,
};
static int lm3639_probe(struct i2c_client *client)
{
int ret;
struct lm3639_chip_data *pchip;
struct lm3639_platform_data *pdata = dev_get_platdata(&client->dev);
struct backlight_properties props;
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
dev_err(&client->dev, "i2c functionality check fail.\n");
return -EOPNOTSUPP;
}
if (pdata == NULL) {
dev_err(&client->dev, "Needs Platform Data.\n");
return -ENODATA;
}
pchip = devm_kzalloc(&client->dev,
sizeof(struct lm3639_chip_data), GFP_KERNEL);
if (!pchip)
return -ENOMEM;
pchip->pdata = pdata;
pchip->dev = &client->dev;
pchip->regmap = devm_regmap_init_i2c(client, &lm3639_regmap);
if (IS_ERR(pchip->regmap)) {
ret = PTR_ERR(pchip->regmap);
dev_err(&client->dev, "fail : allocate register map: %d\n",
ret);
return ret;
}
i2c_set_clientdata(client, pchip);
/* chip initialize */
ret = lm3639_chip_init(pchip);
if (ret < 0) {
dev_err(&client->dev, "fail : chip init\n");
goto err_out;
}
/* backlight */
props.type = BACKLIGHT_RAW;
props.brightness = pdata->init_brt_led;
props.max_brightness = pdata->max_brt_led;
pchip->bled =
devm_backlight_device_register(pchip->dev, "lm3639_bled",
pchip->dev, pchip, &lm3639_bled_ops,
&props);
if (IS_ERR(pchip->bled)) {
dev_err(&client->dev, "fail : backlight register\n");
ret = PTR_ERR(pchip->bled);
goto err_out;
}
ret = device_create_file(&(pchip->bled->dev), &dev_attr_bled_mode);
if (ret < 0) {
dev_err(&client->dev, "failed : add sysfs entries\n");
goto err_out;
}
/* flash */
pchip->cdev_flash.name = "lm3639_flash";
pchip->cdev_flash.max_brightness = 16;
pchip->cdev_flash.brightness_set = lm3639_flash_brightness_set;
ret = led_classdev_register((struct device *)
&client->dev, &pchip->cdev_flash);
if (ret < 0) {
dev_err(&client->dev, "fail : flash register\n");
goto err_flash;
}
/* torch */
pchip->cdev_torch.name = "lm3639_torch";
pchip->cdev_torch.max_brightness = 8;
pchip->cdev_torch.brightness_set = lm3639_torch_brightness_set;
ret = led_classdev_register((struct device *)
&client->dev, &pchip->cdev_torch);
if (ret < 0) {
dev_err(&client->dev, "fail : torch register\n");
goto err_torch;
}
return 0;
err_torch:
led_classdev_unregister(&pchip->cdev_flash);
err_flash:
device_remove_file(&(pchip->bled->dev), &dev_attr_bled_mode);
err_out:
return ret;
}
static void lm3639_remove(struct i2c_client *client)
{
struct lm3639_chip_data *pchip = i2c_get_clientdata(client);
regmap_write(pchip->regmap, REG_ENABLE, 0x00);
led_classdev_unregister(&pchip->cdev_torch);
led_classdev_unregister(&pchip->cdev_flash);
if (pchip->bled)
device_remove_file(&(pchip->bled->dev), &dev_attr_bled_mode);
}
static const struct i2c_device_id lm3639_id[] = {
{LM3639_NAME, 0},
{}
};
MODULE_DEVICE_TABLE(i2c, lm3639_id);
static struct i2c_driver lm3639_i2c_driver = {
.driver = {
.name = LM3639_NAME,
},
.probe = lm3639_probe,
.remove = lm3639_remove,
.id_table = lm3639_id,
};
module_i2c_driver(lm3639_i2c_driver);
MODULE_DESCRIPTION("Texas Instruments Backlight+Flash LED driver for LM3639");
MODULE_AUTHOR("Daniel Jeong <[email protected]>");
MODULE_AUTHOR("Ldd Mlp <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/backlight/lm3639_bl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Backlight driver for Dialog Semiconductor DA9030/DA9034
*
* Copyright (C) 2008 Compulab, Ltd.
* Mike Rapoport <[email protected]>
*
* Copyright (C) 2006-2008 Marvell International Ltd.
* Eric Miao <[email protected]>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/backlight.h>
#include <linux/mfd/da903x.h>
#include <linux/slab.h>
#include <linux/module.h>
#define DA9030_WLED_CONTROL 0x25
#define DA9030_WLED_CP_EN (1 << 6)
#define DA9030_WLED_TRIM(x) ((x) & 0x7)
#define DA9034_WLED_CONTROL1 0x3C
#define DA9034_WLED_CONTROL2 0x3D
#define DA9034_WLED_ISET(x) ((x) & 0x1f)
#define DA9034_WLED_BOOST_EN (1 << 5)
#define DA9030_MAX_BRIGHTNESS 7
#define DA9034_MAX_BRIGHTNESS 0x7f
struct da903x_backlight_data {
struct device *da903x_dev;
int id;
int current_brightness;
};
static int da903x_backlight_set(struct backlight_device *bl, int brightness)
{
struct da903x_backlight_data *data = bl_get_data(bl);
struct device *dev = data->da903x_dev;
uint8_t val;
int ret = 0;
switch (data->id) {
case DA9034_ID_WLED:
ret = da903x_update(dev, DA9034_WLED_CONTROL1,
brightness, 0x7f);
if (ret)
return ret;
if (data->current_brightness && brightness == 0)
ret = da903x_clr_bits(dev,
DA9034_WLED_CONTROL2,
DA9034_WLED_BOOST_EN);
if (data->current_brightness == 0 && brightness)
ret = da903x_set_bits(dev,
DA9034_WLED_CONTROL2,
DA9034_WLED_BOOST_EN);
break;
case DA9030_ID_WLED:
val = DA9030_WLED_TRIM(brightness);
val |= brightness ? DA9030_WLED_CP_EN : 0;
ret = da903x_write(dev, DA9030_WLED_CONTROL, val);
break;
}
if (ret)
return ret;
data->current_brightness = brightness;
return 0;
}
static int da903x_backlight_update_status(struct backlight_device *bl)
{
return da903x_backlight_set(bl, backlight_get_brightness(bl));
}
static int da903x_backlight_get_brightness(struct backlight_device *bl)
{
struct da903x_backlight_data *data = bl_get_data(bl);
return data->current_brightness;
}
static const struct backlight_ops da903x_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = da903x_backlight_update_status,
.get_brightness = da903x_backlight_get_brightness,
};
static int da903x_backlight_probe(struct platform_device *pdev)
{
struct da9034_backlight_pdata *pdata = dev_get_platdata(&pdev->dev);
struct da903x_backlight_data *data;
struct backlight_device *bl;
struct backlight_properties props;
int max_brightness;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
switch (pdev->id) {
case DA9030_ID_WLED:
max_brightness = DA9030_MAX_BRIGHTNESS;
break;
case DA9034_ID_WLED:
max_brightness = DA9034_MAX_BRIGHTNESS;
break;
default:
dev_err(&pdev->dev, "invalid backlight device ID(%d)\n",
pdev->id);
return -EINVAL;
}
data->id = pdev->id;
data->da903x_dev = pdev->dev.parent;
data->current_brightness = 0;
/* adjust the WLED output current */
if (pdata)
da903x_write(data->da903x_dev, DA9034_WLED_CONTROL2,
DA9034_WLED_ISET(pdata->output_current));
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
props.max_brightness = max_brightness;
bl = devm_backlight_device_register(&pdev->dev, pdev->name,
data->da903x_dev, data,
&da903x_backlight_ops, &props);
if (IS_ERR(bl)) {
dev_err(&pdev->dev, "failed to register backlight\n");
return PTR_ERR(bl);
}
bl->props.brightness = max_brightness;
platform_set_drvdata(pdev, bl);
backlight_update_status(bl);
return 0;
}
static struct platform_driver da903x_backlight_driver = {
.driver = {
.name = "da903x-backlight",
},
.probe = da903x_backlight_probe,
};
module_platform_driver(da903x_backlight_driver);
MODULE_DESCRIPTION("Backlight Driver for Dialog Semiconductor DA9030/DA9034");
MODULE_AUTHOR("Eric Miao <[email protected]>");
MODULE_AUTHOR("Mike Rapoport <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:da903x-backlight");
| linux-master | drivers/video/backlight/da903x_bl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* LCD Lowlevel Control Abstraction
*
* Copyright (C) 2003,2004 Hewlett-Packard Company
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/lcd.h>
#include <linux/notifier.h>
#include <linux/ctype.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/slab.h>
#if defined(CONFIG_FB) || (defined(CONFIG_FB_MODULE) && \
defined(CONFIG_LCD_CLASS_DEVICE_MODULE))
/* This callback gets called when something important happens inside a
* framebuffer driver. We're looking if that important event is blanking,
* and if it is, we're switching lcd power as well ...
*/
static int fb_notifier_callback(struct notifier_block *self,
unsigned long event, void *data)
{
struct lcd_device *ld;
struct fb_event *evdata = data;
ld = container_of(self, struct lcd_device, fb_notif);
if (!ld->ops)
return 0;
mutex_lock(&ld->ops_lock);
if (!ld->ops->check_fb || ld->ops->check_fb(ld, evdata->info)) {
if (event == FB_EVENT_BLANK) {
if (ld->ops->set_power)
ld->ops->set_power(ld, *(int *)evdata->data);
} else {
if (ld->ops->set_mode)
ld->ops->set_mode(ld, evdata->data);
}
}
mutex_unlock(&ld->ops_lock);
return 0;
}
static int lcd_register_fb(struct lcd_device *ld)
{
memset(&ld->fb_notif, 0, sizeof(ld->fb_notif));
ld->fb_notif.notifier_call = fb_notifier_callback;
return fb_register_client(&ld->fb_notif);
}
static void lcd_unregister_fb(struct lcd_device *ld)
{
fb_unregister_client(&ld->fb_notif);
}
#else
static int lcd_register_fb(struct lcd_device *ld)
{
return 0;
}
static inline void lcd_unregister_fb(struct lcd_device *ld)
{
}
#endif /* CONFIG_FB */
static ssize_t lcd_power_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
int rc;
struct lcd_device *ld = to_lcd_device(dev);
mutex_lock(&ld->ops_lock);
if (ld->ops && ld->ops->get_power)
rc = sprintf(buf, "%d\n", ld->ops->get_power(ld));
else
rc = -ENXIO;
mutex_unlock(&ld->ops_lock);
return rc;
}
static ssize_t lcd_power_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
int rc;
struct lcd_device *ld = to_lcd_device(dev);
unsigned long power;
rc = kstrtoul(buf, 0, &power);
if (rc)
return rc;
rc = -ENXIO;
mutex_lock(&ld->ops_lock);
if (ld->ops && ld->ops->set_power) {
pr_debug("set power to %lu\n", power);
ld->ops->set_power(ld, power);
rc = count;
}
mutex_unlock(&ld->ops_lock);
return rc;
}
static DEVICE_ATTR_RW(lcd_power);
static ssize_t contrast_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
int rc = -ENXIO;
struct lcd_device *ld = to_lcd_device(dev);
mutex_lock(&ld->ops_lock);
if (ld->ops && ld->ops->get_contrast)
rc = sprintf(buf, "%d\n", ld->ops->get_contrast(ld));
mutex_unlock(&ld->ops_lock);
return rc;
}
static ssize_t contrast_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
int rc;
struct lcd_device *ld = to_lcd_device(dev);
unsigned long contrast;
rc = kstrtoul(buf, 0, &contrast);
if (rc)
return rc;
rc = -ENXIO;
mutex_lock(&ld->ops_lock);
if (ld->ops && ld->ops->set_contrast) {
pr_debug("set contrast to %lu\n", contrast);
ld->ops->set_contrast(ld, contrast);
rc = count;
}
mutex_unlock(&ld->ops_lock);
return rc;
}
static DEVICE_ATTR_RW(contrast);
static ssize_t max_contrast_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct lcd_device *ld = to_lcd_device(dev);
return sprintf(buf, "%d\n", ld->props.max_contrast);
}
static DEVICE_ATTR_RO(max_contrast);
static struct class *lcd_class;
static void lcd_device_release(struct device *dev)
{
struct lcd_device *ld = to_lcd_device(dev);
kfree(ld);
}
static struct attribute *lcd_device_attrs[] = {
&dev_attr_lcd_power.attr,
&dev_attr_contrast.attr,
&dev_attr_max_contrast.attr,
NULL,
};
ATTRIBUTE_GROUPS(lcd_device);
/**
* lcd_device_register - register a new object of lcd_device class.
* @name: the name of the new object(must be the same as the name of the
* respective framebuffer device).
* @parent: pointer to the parent's struct device .
* @devdata: an optional pointer to be stored in the device. The
* methods may retrieve it by using lcd_get_data(ld).
* @ops: the lcd operations structure.
*
* Creates and registers a new lcd device. Returns either an ERR_PTR()
* or a pointer to the newly allocated device.
*/
struct lcd_device *lcd_device_register(const char *name, struct device *parent,
void *devdata, struct lcd_ops *ops)
{
struct lcd_device *new_ld;
int rc;
pr_debug("lcd_device_register: name=%s\n", name);
new_ld = kzalloc(sizeof(struct lcd_device), GFP_KERNEL);
if (!new_ld)
return ERR_PTR(-ENOMEM);
mutex_init(&new_ld->ops_lock);
mutex_init(&new_ld->update_lock);
new_ld->dev.class = lcd_class;
new_ld->dev.parent = parent;
new_ld->dev.release = lcd_device_release;
dev_set_name(&new_ld->dev, "%s", name);
dev_set_drvdata(&new_ld->dev, devdata);
new_ld->ops = ops;
rc = device_register(&new_ld->dev);
if (rc) {
put_device(&new_ld->dev);
return ERR_PTR(rc);
}
rc = lcd_register_fb(new_ld);
if (rc) {
device_unregister(&new_ld->dev);
return ERR_PTR(rc);
}
return new_ld;
}
EXPORT_SYMBOL(lcd_device_register);
/**
* lcd_device_unregister - unregisters a object of lcd_device class.
* @ld: the lcd device object to be unregistered and freed.
*
* Unregisters a previously registered via lcd_device_register object.
*/
void lcd_device_unregister(struct lcd_device *ld)
{
if (!ld)
return;
mutex_lock(&ld->ops_lock);
ld->ops = NULL;
mutex_unlock(&ld->ops_lock);
lcd_unregister_fb(ld);
device_unregister(&ld->dev);
}
EXPORT_SYMBOL(lcd_device_unregister);
static void devm_lcd_device_release(struct device *dev, void *res)
{
struct lcd_device *lcd = *(struct lcd_device **)res;
lcd_device_unregister(lcd);
}
static int devm_lcd_device_match(struct device *dev, void *res, void *data)
{
struct lcd_device **r = res;
return *r == data;
}
/**
* devm_lcd_device_register - resource managed lcd_device_register()
* @dev: the device to register
* @name: the name of the device
* @parent: a pointer to the parent device
* @devdata: an optional pointer to be stored for private driver use
* @ops: the lcd operations structure
*
* @return a struct lcd on success, or an ERR_PTR on error
*
* Managed lcd_device_register(). The lcd_device returned from this function
* are automatically freed on driver detach. See lcd_device_register()
* for more information.
*/
struct lcd_device *devm_lcd_device_register(struct device *dev,
const char *name, struct device *parent,
void *devdata, struct lcd_ops *ops)
{
struct lcd_device **ptr, *lcd;
ptr = devres_alloc(devm_lcd_device_release, sizeof(*ptr), GFP_KERNEL);
if (!ptr)
return ERR_PTR(-ENOMEM);
lcd = lcd_device_register(name, parent, devdata, ops);
if (!IS_ERR(lcd)) {
*ptr = lcd;
devres_add(dev, ptr);
} else {
devres_free(ptr);
}
return lcd;
}
EXPORT_SYMBOL(devm_lcd_device_register);
/**
* devm_lcd_device_unregister - resource managed lcd_device_unregister()
* @dev: the device to unregister
* @ld: the lcd device to unregister
*
* Deallocated a lcd allocated with devm_lcd_device_register(). Normally
* this function will not need to be called and the resource management
* code will ensure that the resource is freed.
*/
void devm_lcd_device_unregister(struct device *dev, struct lcd_device *ld)
{
int rc;
rc = devres_release(dev, devm_lcd_device_release,
devm_lcd_device_match, ld);
WARN_ON(rc);
}
EXPORT_SYMBOL(devm_lcd_device_unregister);
static void __exit lcd_class_exit(void)
{
class_destroy(lcd_class);
}
static int __init lcd_class_init(void)
{
lcd_class = class_create("lcd");
if (IS_ERR(lcd_class)) {
pr_warn("Unable to create backlight class; errno = %ld\n",
PTR_ERR(lcd_class));
return PTR_ERR(lcd_class);
}
lcd_class->dev_groups = lcd_device_groups;
return 0;
}
/*
* if this is compiled into the kernel, we need to ensure that the
* class is registered before users of the class try to register lcd's
*/
postcore_initcall(lcd_class_init);
module_exit(lcd_class_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jamey Hicks <[email protected]>, Andrew Zabolotny <[email protected]>");
MODULE_DESCRIPTION("LCD Lowlevel Control Abstraction");
| linux-master | drivers/video/backlight/lcd.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Backlight driver for Maxim MAX8925
*
* Copyright (C) 2009 Marvell International Ltd.
* Haojian Zhuang <[email protected]>
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/backlight.h>
#include <linux/mfd/max8925.h>
#include <linux/slab.h>
#include <linux/module.h>
#define MAX_BRIGHTNESS (0xff)
#define MIN_BRIGHTNESS (0)
#define LWX_FREQ(x) (((x - 601) / 100) & 0x7)
struct max8925_backlight_data {
struct max8925_chip *chip;
int current_brightness;
int reg_mode_cntl;
int reg_cntl;
};
static int max8925_backlight_set(struct backlight_device *bl, int brightness)
{
struct max8925_backlight_data *data = bl_get_data(bl);
struct max8925_chip *chip = data->chip;
unsigned char value;
int ret;
if (brightness > MAX_BRIGHTNESS)
value = MAX_BRIGHTNESS;
else
value = brightness;
ret = max8925_reg_write(chip->i2c, data->reg_cntl, value);
if (ret < 0)
goto out;
if (!data->current_brightness && brightness)
/* enable WLED output */
ret = max8925_set_bits(chip->i2c, data->reg_mode_cntl, 1, 1);
else if (!brightness)
/* disable WLED output */
ret = max8925_set_bits(chip->i2c, data->reg_mode_cntl, 1, 0);
if (ret < 0)
goto out;
dev_dbg(chip->dev, "set brightness %d\n", value);
data->current_brightness = value;
return 0;
out:
dev_dbg(chip->dev, "set brightness %d failure with return value:%d\n",
value, ret);
return ret;
}
static int max8925_backlight_update_status(struct backlight_device *bl)
{
return max8925_backlight_set(bl, backlight_get_brightness(bl));
}
static int max8925_backlight_get_brightness(struct backlight_device *bl)
{
struct max8925_backlight_data *data = bl_get_data(bl);
struct max8925_chip *chip = data->chip;
int ret;
ret = max8925_reg_read(chip->i2c, data->reg_cntl);
if (ret < 0)
return -EINVAL;
data->current_brightness = ret;
dev_dbg(chip->dev, "get brightness %d\n", data->current_brightness);
return ret;
}
static const struct backlight_ops max8925_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = max8925_backlight_update_status,
.get_brightness = max8925_backlight_get_brightness,
};
static void max8925_backlight_dt_init(struct platform_device *pdev)
{
struct device_node *nproot = pdev->dev.parent->of_node, *np;
struct max8925_backlight_pdata *pdata;
u32 val;
if (!nproot || !IS_ENABLED(CONFIG_OF))
return;
pdata = devm_kzalloc(&pdev->dev,
sizeof(struct max8925_backlight_pdata),
GFP_KERNEL);
if (!pdata)
return;
np = of_get_child_by_name(nproot, "backlight");
if (!np) {
dev_err(&pdev->dev, "failed to find backlight node\n");
return;
}
if (!of_property_read_u32(np, "maxim,max8925-dual-string", &val))
pdata->dual_string = val;
of_node_put(np);
pdev->dev.platform_data = pdata;
}
static int max8925_backlight_probe(struct platform_device *pdev)
{
struct max8925_chip *chip = dev_get_drvdata(pdev->dev.parent);
struct max8925_backlight_pdata *pdata;
struct max8925_backlight_data *data;
struct backlight_device *bl;
struct backlight_properties props;
struct resource *res;
unsigned char value;
int ret = 0;
data = devm_kzalloc(&pdev->dev, sizeof(struct max8925_backlight_data),
GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_REG, 0);
if (!res) {
dev_err(&pdev->dev, "No REG resource for mode control!\n");
return -ENXIO;
}
data->reg_mode_cntl = res->start;
res = platform_get_resource(pdev, IORESOURCE_REG, 1);
if (!res) {
dev_err(&pdev->dev, "No REG resource for control!\n");
return -ENXIO;
}
data->reg_cntl = res->start;
data->chip = chip;
data->current_brightness = 0;
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = MAX_BRIGHTNESS;
bl = devm_backlight_device_register(&pdev->dev, "max8925-backlight",
&pdev->dev, data,
&max8925_backlight_ops, &props);
if (IS_ERR(bl)) {
dev_err(&pdev->dev, "failed to register backlight\n");
return PTR_ERR(bl);
}
bl->props.brightness = MAX_BRIGHTNESS;
platform_set_drvdata(pdev, bl);
value = 0;
if (!pdev->dev.platform_data)
max8925_backlight_dt_init(pdev);
pdata = pdev->dev.platform_data;
if (pdata) {
if (pdata->lxw_scl)
value |= (1 << 7);
if (pdata->lxw_freq)
value |= (LWX_FREQ(pdata->lxw_freq) << 4);
if (pdata->dual_string)
value |= (1 << 1);
}
ret = max8925_set_bits(chip->i2c, data->reg_mode_cntl, 0xfe, value);
if (ret < 0)
return ret;
backlight_update_status(bl);
return 0;
}
static struct platform_driver max8925_backlight_driver = {
.driver = {
.name = "max8925-backlight",
},
.probe = max8925_backlight_probe,
};
module_platform_driver(max8925_backlight_driver);
MODULE_DESCRIPTION("Backlight Driver for Maxim MAX8925");
MODULE_AUTHOR("Haojian Zhuang <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:max8925-backlight");
| linux-master | drivers/video/backlight/max8925_bl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* gpio_backlight.c - Simple GPIO-controlled backlight
*/
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_data/gpio_backlight.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/slab.h>
struct gpio_backlight {
struct device *dev;
struct gpio_desc *gpiod;
};
static int gpio_backlight_update_status(struct backlight_device *bl)
{
struct gpio_backlight *gbl = bl_get_data(bl);
gpiod_set_value_cansleep(gbl->gpiod, backlight_get_brightness(bl));
return 0;
}
static int gpio_backlight_check_fb(struct backlight_device *bl,
struct fb_info *info)
{
struct gpio_backlight *gbl = bl_get_data(bl);
return !gbl->dev || gbl->dev == info->device;
}
static const struct backlight_ops gpio_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = gpio_backlight_update_status,
.check_fb = gpio_backlight_check_fb,
};
static int gpio_backlight_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct gpio_backlight_platform_data *pdata = dev_get_platdata(dev);
struct device_node *of_node = dev->of_node;
struct backlight_properties props;
struct backlight_device *bl;
struct gpio_backlight *gbl;
int ret, init_brightness, def_value;
gbl = devm_kzalloc(dev, sizeof(*gbl), GFP_KERNEL);
if (gbl == NULL)
return -ENOMEM;
if (pdata)
gbl->dev = pdata->dev;
def_value = device_property_read_bool(dev, "default-on");
gbl->gpiod = devm_gpiod_get(dev, NULL, GPIOD_ASIS);
if (IS_ERR(gbl->gpiod)) {
ret = PTR_ERR(gbl->gpiod);
if (ret != -EPROBE_DEFER)
dev_err(dev,
"Error: The gpios parameter is missing or invalid.\n");
return ret;
}
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
props.max_brightness = 1;
bl = devm_backlight_device_register(dev, dev_name(dev), dev, gbl,
&gpio_backlight_ops, &props);
if (IS_ERR(bl)) {
dev_err(dev, "failed to register backlight\n");
return PTR_ERR(bl);
}
/* Set the initial power state */
if (!of_node || !of_node->phandle)
/* Not booted with device tree or no phandle link to the node */
bl->props.power = def_value ? FB_BLANK_UNBLANK
: FB_BLANK_POWERDOWN;
else if (gpiod_get_value_cansleep(gbl->gpiod) == 0)
bl->props.power = FB_BLANK_POWERDOWN;
else
bl->props.power = FB_BLANK_UNBLANK;
bl->props.brightness = 1;
init_brightness = backlight_get_brightness(bl);
ret = gpiod_direction_output(gbl->gpiod, init_brightness);
if (ret) {
dev_err(dev, "failed to set initial brightness\n");
return ret;
}
platform_set_drvdata(pdev, bl);
return 0;
}
static struct of_device_id gpio_backlight_of_match[] = {
{ .compatible = "gpio-backlight" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, gpio_backlight_of_match);
static struct platform_driver gpio_backlight_driver = {
.driver = {
.name = "gpio-backlight",
.of_match_table = gpio_backlight_of_match,
},
.probe = gpio_backlight_probe,
};
module_platform_driver(gpio_backlight_driver);
MODULE_AUTHOR("Laurent Pinchart <[email protected]>");
MODULE_DESCRIPTION("GPIO-based Backlight Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:gpio-backlight");
| linux-master | drivers/video/backlight/gpio_backlight.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Backlight driver for the Kinetic KTZ8866
*
* Copyright (C) 2022, 2023 Jianhua Lu <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#define DEFAULT_BRIGHTNESS 1500
#define MAX_BRIGHTNESS 2047
#define REG_MAX 0x15
/* reg */
#define DEVICE_ID 0x01
#define BL_CFG1 0x02
#define BL_CFG2 0x03
#define BL_BRT_LSB 0x04
#define BL_BRT_MSB 0x05
#define BL_EN 0x08
#define LCD_BIAS_CFG1 0x09
#define LCD_BIAS_CFG2 0x0A
#define LCD_BIAS_CFG3 0x0B
#define LCD_BOOST_CFG 0x0C
#define OUTP_CFG 0x0D
#define OUTN_CFG 0x0E
#define FLAG 0x0F
#define BL_OPTION1 0x10
#define BL_OPTION2 0x11
#define PWM2DIG_LSBs 0x12
#define PWM2DIG_MSBs 0x13
#define BL_DIMMING 0x14
#define PWM_RAMP_TIME 0x15
/* definition */
#define BL_EN_BIT BIT(6)
#define LCD_BIAS_EN 0x9F
#define PWM_HYST 0x5
struct ktz8866 {
struct i2c_client *client;
struct regmap *regmap;
bool led_on;
struct gpio_desc *enable_gpio;
};
static const struct regmap_config ktz8866_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.max_register = REG_MAX,
};
static int ktz8866_write(struct ktz8866 *ktz, unsigned int reg,
unsigned int val)
{
return regmap_write(ktz->regmap, reg, val);
}
static int ktz8866_update_bits(struct ktz8866 *ktz, unsigned int reg,
unsigned int mask, unsigned int val)
{
return regmap_update_bits(ktz->regmap, reg, mask, val);
}
static int ktz8866_backlight_update_status(struct backlight_device *backlight_dev)
{
struct ktz8866 *ktz = bl_get_data(backlight_dev);
unsigned int brightness = backlight_get_brightness(backlight_dev);
if (!ktz->led_on && brightness > 0) {
ktz8866_update_bits(ktz, BL_EN, BL_EN_BIT, BL_EN_BIT);
ktz->led_on = true;
} else if (brightness == 0) {
ktz8866_update_bits(ktz, BL_EN, BL_EN_BIT, 0);
ktz->led_on = false;
}
/* Set brightness */
ktz8866_write(ktz, BL_BRT_LSB, brightness & 0x7);
ktz8866_write(ktz, BL_BRT_MSB, (brightness >> 3) & 0xFF);
return 0;
}
static const struct backlight_ops ktz8866_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = ktz8866_backlight_update_status,
};
static void ktz8866_init(struct ktz8866 *ktz)
{
unsigned int val = 0;
if (of_property_read_u32(ktz->client->dev.of_node, "current-num-sinks", &val))
ktz8866_write(ktz, BL_EN, BIT(val) - 1);
else
/* Enable all 6 current sinks if the number of current sinks isn't specified. */
ktz8866_write(ktz, BL_EN, BIT(6) - 1);
if (of_property_read_u32(ktz->client->dev.of_node, "kinetic,current-ramp-delay-ms", &val)) {
if (val <= 128)
ktz8866_write(ktz, BL_CFG2, BIT(7) | (ilog2(val) << 3) | PWM_HYST);
else
ktz8866_write(ktz, BL_CFG2, BIT(7) | ((5 + val / 64) << 3) | PWM_HYST);
}
if (of_property_read_u32(ktz->client->dev.of_node, "kinetic,led-enable-ramp-delay-ms", &val)) {
if (val == 0)
ktz8866_write(ktz, BL_DIMMING, 0);
else {
unsigned int ramp_off_time = ilog2(val) + 1;
unsigned int ramp_on_time = ramp_off_time << 4;
ktz8866_write(ktz, BL_DIMMING, ramp_on_time | ramp_off_time);
}
}
if (of_property_read_bool(ktz->client->dev.of_node, "kinetic,enable-lcd-bias"))
ktz8866_write(ktz, LCD_BIAS_CFG1, LCD_BIAS_EN);
}
static int ktz8866_probe(struct i2c_client *client)
{
struct backlight_device *backlight_dev;
struct backlight_properties props;
struct ktz8866 *ktz;
int ret = 0;
ktz = devm_kzalloc(&client->dev, sizeof(*ktz), GFP_KERNEL);
if (!ktz)
return -ENOMEM;
ktz->client = client;
ktz->regmap = devm_regmap_init_i2c(client, &ktz8866_regmap_config);
if (IS_ERR(ktz->regmap))
return dev_err_probe(&client->dev, PTR_ERR(ktz->regmap), "failed to init regmap\n");
ret = devm_regulator_get_enable(&client->dev, "vddpos");
if (ret)
return dev_err_probe(&client->dev, ret, "get regulator vddpos failed\n");
ret = devm_regulator_get_enable(&client->dev, "vddneg");
if (ret)
return dev_err_probe(&client->dev, ret, "get regulator vddneg failed\n");
ktz->enable_gpio = devm_gpiod_get_optional(&client->dev, "enable", GPIOD_OUT_HIGH);
if (IS_ERR(ktz->enable_gpio))
return PTR_ERR(ktz->enable_gpio);
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
props.max_brightness = MAX_BRIGHTNESS;
props.brightness = DEFAULT_BRIGHTNESS;
props.scale = BACKLIGHT_SCALE_LINEAR;
backlight_dev = devm_backlight_device_register(&client->dev, "ktz8866-backlight",
&client->dev, ktz, &ktz8866_backlight_ops, &props);
if (IS_ERR(backlight_dev))
return dev_err_probe(&client->dev, PTR_ERR(backlight_dev),
"failed to register backlight device\n");
ktz8866_init(ktz);
i2c_set_clientdata(client, backlight_dev);
backlight_update_status(backlight_dev);
return 0;
}
static void ktz8866_remove(struct i2c_client *client)
{
struct backlight_device *backlight_dev = i2c_get_clientdata(client);
backlight_dev->props.brightness = 0;
backlight_update_status(backlight_dev);
}
static const struct i2c_device_id ktz8866_ids[] = {
{ "ktz8866", 0 },
{},
};
MODULE_DEVICE_TABLE(i2c, ktz8866_ids);
static const struct of_device_id ktz8866_match_table[] = {
{
.compatible = "kinetic,ktz8866",
},
{},
};
static struct i2c_driver ktz8866_driver = {
.driver = {
.name = "ktz8866",
.of_match_table = ktz8866_match_table,
},
.probe = ktz8866_probe,
.remove = ktz8866_remove,
.id_table = ktz8866_ids,
};
module_i2c_driver(ktz8866_driver);
MODULE_DESCRIPTION("Kinetic KTZ8866 Backlight Driver");
MODULE_AUTHOR("Jianhua Lu <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/backlight/ktz8866.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Simple PWM based backlight control, board code has to setup
* 1) pin configuration so PWM waveforms can output
* 2) platform_data being correctly configured
*/
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
struct pwm_bl_data {
struct pwm_device *pwm;
struct device *dev;
unsigned int lth_brightness;
unsigned int *levels;
bool enabled;
struct regulator *power_supply;
struct gpio_desc *enable_gpio;
unsigned int scale;
unsigned int post_pwm_on_delay;
unsigned int pwm_off_delay;
int (*notify)(struct device *,
int brightness);
void (*notify_after)(struct device *,
int brightness);
int (*check_fb)(struct device *, struct fb_info *);
void (*exit)(struct device *);
};
static void pwm_backlight_power_on(struct pwm_bl_data *pb)
{
int err;
if (pb->enabled)
return;
if (pb->power_supply) {
err = regulator_enable(pb->power_supply);
if (err < 0)
dev_err(pb->dev, "failed to enable power supply\n");
}
if (pb->post_pwm_on_delay)
msleep(pb->post_pwm_on_delay);
gpiod_set_value_cansleep(pb->enable_gpio, 1);
pb->enabled = true;
}
static void pwm_backlight_power_off(struct pwm_bl_data *pb)
{
if (!pb->enabled)
return;
gpiod_set_value_cansleep(pb->enable_gpio, 0);
if (pb->pwm_off_delay)
msleep(pb->pwm_off_delay);
if (pb->power_supply)
regulator_disable(pb->power_supply);
pb->enabled = false;
}
static int compute_duty_cycle(struct pwm_bl_data *pb, int brightness, struct pwm_state *state)
{
unsigned int lth = pb->lth_brightness;
u64 duty_cycle;
if (pb->levels)
duty_cycle = pb->levels[brightness];
else
duty_cycle = brightness;
duty_cycle *= state->period - lth;
do_div(duty_cycle, pb->scale);
return duty_cycle + lth;
}
static int pwm_backlight_update_status(struct backlight_device *bl)
{
struct pwm_bl_data *pb = bl_get_data(bl);
int brightness = backlight_get_brightness(bl);
struct pwm_state state;
if (pb->notify)
brightness = pb->notify(pb->dev, brightness);
if (brightness > 0) {
pwm_get_state(pb->pwm, &state);
state.duty_cycle = compute_duty_cycle(pb, brightness, &state);
state.enabled = true;
pwm_apply_state(pb->pwm, &state);
pwm_backlight_power_on(pb);
} else {
pwm_backlight_power_off(pb);
pwm_get_state(pb->pwm, &state);
state.duty_cycle = 0;
/*
* We cannot assume a disabled PWM to drive its output to the
* inactive state. If we have an enable GPIO and/or a regulator
* we assume that this isn't relevant and we can disable the PWM
* to save power. If however there is neither an enable GPIO nor
* a regulator keep the PWM on be sure to get a constant
* inactive output.
*/
state.enabled = !pb->power_supply && !pb->enable_gpio;
pwm_apply_state(pb->pwm, &state);
}
if (pb->notify_after)
pb->notify_after(pb->dev, brightness);
return 0;
}
static int pwm_backlight_check_fb(struct backlight_device *bl,
struct fb_info *info)
{
struct pwm_bl_data *pb = bl_get_data(bl);
return !pb->check_fb || pb->check_fb(pb->dev, info);
}
static const struct backlight_ops pwm_backlight_ops = {
.update_status = pwm_backlight_update_status,
.check_fb = pwm_backlight_check_fb,
};
#ifdef CONFIG_OF
#define PWM_LUMINANCE_SHIFT 16
#define PWM_LUMINANCE_SCALE (1 << PWM_LUMINANCE_SHIFT) /* luminance scale */
/*
* CIE lightness to PWM conversion.
*
* The CIE 1931 lightness formula is what actually describes how we perceive
* light:
* Y = (L* / 903.3) if L* ≤ 8
* Y = ((L* + 16) / 116)^3 if L* > 8
*
* Where Y is the luminance, the amount of light coming out of the screen, and
* is a number between 0.0 and 1.0; and L* is the lightness, how bright a human
* perceives the screen to be, and is a number between 0 and 100.
*
* The following function does the fixed point maths needed to implement the
* above formula.
*/
static u64 cie1931(unsigned int lightness)
{
u64 retval;
/*
* @lightness is given as a number between 0 and 1, expressed
* as a fixed-point number in scale
* PWM_LUMINANCE_SCALE. Convert to a percentage, still
* expressed as a fixed-point number, so the above formulas
* can be applied.
*/
lightness *= 100;
if (lightness <= (8 * PWM_LUMINANCE_SCALE)) {
retval = DIV_ROUND_CLOSEST(lightness * 10, 9033);
} else {
retval = (lightness + (16 * PWM_LUMINANCE_SCALE)) / 116;
retval *= retval * retval;
retval += 1ULL << (2*PWM_LUMINANCE_SHIFT - 1);
retval >>= 2*PWM_LUMINANCE_SHIFT;
}
return retval;
}
/*
* Create a default correction table for PWM values to create linear brightness
* for LED based backlights using the CIE1931 algorithm.
*/
static
int pwm_backlight_brightness_default(struct device *dev,
struct platform_pwm_backlight_data *data,
unsigned int period)
{
unsigned int i;
u64 retval;
/*
* Once we have 4096 levels there's little point going much higher...
* neither interactive sliders nor animation benefits from having
* more values in the table.
*/
data->max_brightness =
min((int)DIV_ROUND_UP(period, fls(period)), 4096);
data->levels = devm_kcalloc(dev, data->max_brightness,
sizeof(*data->levels), GFP_KERNEL);
if (!data->levels)
return -ENOMEM;
/* Fill the table using the cie1931 algorithm */
for (i = 0; i < data->max_brightness; i++) {
retval = cie1931((i * PWM_LUMINANCE_SCALE) /
data->max_brightness) * period;
retval = DIV_ROUND_CLOSEST_ULL(retval, PWM_LUMINANCE_SCALE);
if (retval > UINT_MAX)
return -EINVAL;
data->levels[i] = (unsigned int)retval;
}
data->dft_brightness = data->max_brightness / 2;
data->max_brightness--;
return 0;
}
static int pwm_backlight_parse_dt(struct device *dev,
struct platform_pwm_backlight_data *data)
{
struct device_node *node = dev->of_node;
unsigned int num_levels;
unsigned int num_steps = 0;
struct property *prop;
unsigned int *table;
int length;
u32 value;
int ret;
if (!node)
return -ENODEV;
memset(data, 0, sizeof(*data));
/*
* These values are optional and set as 0 by default, the out values
* are modified only if a valid u32 value can be decoded.
*/
of_property_read_u32(node, "post-pwm-on-delay-ms",
&data->post_pwm_on_delay);
of_property_read_u32(node, "pwm-off-delay-ms", &data->pwm_off_delay);
/*
* Determine the number of brightness levels, if this property is not
* set a default table of brightness levels will be used.
*/
prop = of_find_property(node, "brightness-levels", &length);
if (!prop)
return 0;
num_levels = length / sizeof(u32);
/* read brightness levels from DT property */
if (num_levels > 0) {
data->levels = devm_kcalloc(dev, num_levels,
sizeof(*data->levels), GFP_KERNEL);
if (!data->levels)
return -ENOMEM;
ret = of_property_read_u32_array(node, "brightness-levels",
data->levels,
num_levels);
if (ret < 0)
return ret;
ret = of_property_read_u32(node, "default-brightness-level",
&value);
if (ret < 0)
return ret;
data->dft_brightness = value;
/*
* This property is optional, if is set enables linear
* interpolation between each of the values of brightness levels
* and creates a new pre-computed table.
*/
of_property_read_u32(node, "num-interpolated-steps",
&num_steps);
/*
* Make sure that there is at least two entries in the
* brightness-levels table, otherwise we can't interpolate
* between two points.
*/
if (num_steps) {
unsigned int num_input_levels = num_levels;
unsigned int i;
u32 x1, x2, x, dx;
u32 y1, y2;
s64 dy;
if (num_input_levels < 2) {
dev_err(dev, "can't interpolate\n");
return -EINVAL;
}
/*
* Recalculate the number of brightness levels, now
* taking in consideration the number of interpolated
* steps between two levels.
*/
num_levels = (num_input_levels - 1) * num_steps + 1;
dev_dbg(dev, "new number of brightness levels: %d\n",
num_levels);
/*
* Create a new table of brightness levels with all the
* interpolated steps.
*/
table = devm_kcalloc(dev, num_levels, sizeof(*table),
GFP_KERNEL);
if (!table)
return -ENOMEM;
/*
* Fill the interpolated table[x] = y
* by draw lines between each (x1, y1) to (x2, y2).
*/
dx = num_steps;
for (i = 0; i < num_input_levels - 1; i++) {
x1 = i * dx;
x2 = x1 + dx;
y1 = data->levels[i];
y2 = data->levels[i + 1];
dy = (s64)y2 - y1;
for (x = x1; x < x2; x++) {
table[x] = y1 +
div_s64(dy * (x - x1), dx);
}
}
/* Fill in the last point, since no line starts here. */
table[x2] = y2;
/*
* As we use interpolation lets remove current
* brightness levels table and replace for the
* new interpolated table.
*/
devm_kfree(dev, data->levels);
data->levels = table;
}
data->max_brightness = num_levels - 1;
}
return 0;
}
static const struct of_device_id pwm_backlight_of_match[] = {
{ .compatible = "pwm-backlight" },
{ }
};
MODULE_DEVICE_TABLE(of, pwm_backlight_of_match);
#else
static int pwm_backlight_parse_dt(struct device *dev,
struct platform_pwm_backlight_data *data)
{
return -ENODEV;
}
static
int pwm_backlight_brightness_default(struct device *dev,
struct platform_pwm_backlight_data *data,
unsigned int period)
{
return -ENODEV;
}
#endif
static bool pwm_backlight_is_linear(struct platform_pwm_backlight_data *data)
{
unsigned int nlevels = data->max_brightness + 1;
unsigned int min_val = data->levels[0];
unsigned int max_val = data->levels[nlevels - 1];
/*
* Multiplying by 128 means that even in pathological cases such
* as (max_val - min_val) == nlevels the error at max_val is less
* than 1%.
*/
unsigned int slope = (128 * (max_val - min_val)) / nlevels;
unsigned int margin = (max_val - min_val) / 20; /* 5% */
int i;
for (i = 1; i < nlevels; i++) {
unsigned int linear_value = min_val + ((i * slope) / 128);
unsigned int delta = abs(linear_value - data->levels[i]);
if (delta > margin)
return false;
}
return true;
}
static int pwm_backlight_initial_power_state(const struct pwm_bl_data *pb)
{
struct device_node *node = pb->dev->of_node;
bool active = true;
/*
* If the enable GPIO is present, observable (either as input
* or output) and off then the backlight is not currently active.
* */
if (pb->enable_gpio && gpiod_get_value_cansleep(pb->enable_gpio) == 0)
active = false;
if (pb->power_supply && !regulator_is_enabled(pb->power_supply))
active = false;
if (!pwm_is_enabled(pb->pwm))
active = false;
/*
* Synchronize the enable_gpio with the observed state of the
* hardware.
*/
gpiod_direction_output(pb->enable_gpio, active);
/*
* Do not change pb->enabled here! pb->enabled essentially
* tells us if we own one of the regulator's use counts and
* right now we do not.
*/
/* Not booted with device tree or no phandle link to the node */
if (!node || !node->phandle)
return FB_BLANK_UNBLANK;
/*
* If the driver is probed from the device tree and there is a
* phandle link pointing to the backlight node, it is safe to
* assume that another driver will enable the backlight at the
* appropriate time. Therefore, if it is disabled, keep it so.
*/
return active ? FB_BLANK_UNBLANK: FB_BLANK_POWERDOWN;
}
static int pwm_backlight_probe(struct platform_device *pdev)
{
struct platform_pwm_backlight_data *data = dev_get_platdata(&pdev->dev);
struct platform_pwm_backlight_data defdata;
struct backlight_properties props;
struct backlight_device *bl;
struct pwm_bl_data *pb;
struct pwm_state state;
unsigned int i;
int ret;
if (!data) {
ret = pwm_backlight_parse_dt(&pdev->dev, &defdata);
if (ret < 0) {
dev_err(&pdev->dev, "failed to find platform data\n");
return ret;
}
data = &defdata;
}
if (data->init) {
ret = data->init(&pdev->dev);
if (ret < 0)
return ret;
}
pb = devm_kzalloc(&pdev->dev, sizeof(*pb), GFP_KERNEL);
if (!pb) {
ret = -ENOMEM;
goto err_alloc;
}
pb->notify = data->notify;
pb->notify_after = data->notify_after;
pb->check_fb = data->check_fb;
pb->exit = data->exit;
pb->dev = &pdev->dev;
pb->enabled = false;
pb->post_pwm_on_delay = data->post_pwm_on_delay;
pb->pwm_off_delay = data->pwm_off_delay;
pb->enable_gpio = devm_gpiod_get_optional(&pdev->dev, "enable",
GPIOD_ASIS);
if (IS_ERR(pb->enable_gpio)) {
ret = PTR_ERR(pb->enable_gpio);
goto err_alloc;
}
pb->power_supply = devm_regulator_get_optional(&pdev->dev, "power");
if (IS_ERR(pb->power_supply)) {
ret = PTR_ERR(pb->power_supply);
if (ret == -ENODEV)
pb->power_supply = NULL;
else
goto err_alloc;
}
pb->pwm = devm_pwm_get(&pdev->dev, NULL);
if (IS_ERR(pb->pwm)) {
ret = PTR_ERR(pb->pwm);
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev, "unable to request PWM\n");
goto err_alloc;
}
dev_dbg(&pdev->dev, "got pwm for backlight\n");
/* Sync up PWM state. */
pwm_init_state(pb->pwm, &state);
/*
* The DT case will set the pwm_period_ns field to 0 and store the
* period, parsed from the DT, in the PWM device. For the non-DT case,
* set the period from platform data if it has not already been set
* via the PWM lookup table.
*/
if (!state.period && (data->pwm_period_ns > 0))
state.period = data->pwm_period_ns;
ret = pwm_apply_state(pb->pwm, &state);
if (ret) {
dev_err(&pdev->dev, "failed to apply initial PWM state: %d\n",
ret);
goto err_alloc;
}
memset(&props, 0, sizeof(struct backlight_properties));
if (data->levels) {
pb->levels = data->levels;
/*
* For the DT case, only when brightness levels is defined
* data->levels is filled. For the non-DT case, data->levels
* can come from platform data, however is not usual.
*/
for (i = 0; i <= data->max_brightness; i++)
if (data->levels[i] > pb->scale)
pb->scale = data->levels[i];
if (pwm_backlight_is_linear(data))
props.scale = BACKLIGHT_SCALE_LINEAR;
else
props.scale = BACKLIGHT_SCALE_NON_LINEAR;
} else if (!data->max_brightness) {
/*
* If no brightness levels are provided and max_brightness is
* not set, use the default brightness table. For the DT case,
* max_brightness is set to 0 when brightness levels is not
* specified. For the non-DT case, max_brightness is usually
* set to some value.
*/
/* Get the PWM period (in nanoseconds) */
pwm_get_state(pb->pwm, &state);
ret = pwm_backlight_brightness_default(&pdev->dev, data,
state.period);
if (ret < 0) {
dev_err(&pdev->dev,
"failed to setup default brightness table\n");
goto err_alloc;
}
for (i = 0; i <= data->max_brightness; i++) {
if (data->levels[i] > pb->scale)
pb->scale = data->levels[i];
pb->levels = data->levels;
}
props.scale = BACKLIGHT_SCALE_NON_LINEAR;
} else {
/*
* That only happens for the non-DT case, where platform data
* sets the max_brightness value.
*/
pb->scale = data->max_brightness;
}
pb->lth_brightness = data->lth_brightness * (div_u64(state.period,
pb->scale));
props.type = BACKLIGHT_RAW;
props.max_brightness = data->max_brightness;
bl = backlight_device_register(dev_name(&pdev->dev), &pdev->dev, pb,
&pwm_backlight_ops, &props);
if (IS_ERR(bl)) {
dev_err(&pdev->dev, "failed to register backlight\n");
ret = PTR_ERR(bl);
goto err_alloc;
}
if (data->dft_brightness > data->max_brightness) {
dev_warn(&pdev->dev,
"invalid default brightness level: %u, using %u\n",
data->dft_brightness, data->max_brightness);
data->dft_brightness = data->max_brightness;
}
bl->props.brightness = data->dft_brightness;
bl->props.power = pwm_backlight_initial_power_state(pb);
backlight_update_status(bl);
platform_set_drvdata(pdev, bl);
return 0;
err_alloc:
if (data->exit)
data->exit(&pdev->dev);
return ret;
}
static void pwm_backlight_remove(struct platform_device *pdev)
{
struct backlight_device *bl = platform_get_drvdata(pdev);
struct pwm_bl_data *pb = bl_get_data(bl);
backlight_device_unregister(bl);
pwm_backlight_power_off(pb);
if (pb->exit)
pb->exit(&pdev->dev);
}
static void pwm_backlight_shutdown(struct platform_device *pdev)
{
struct backlight_device *bl = platform_get_drvdata(pdev);
struct pwm_bl_data *pb = bl_get_data(bl);
pwm_backlight_power_off(pb);
}
#ifdef CONFIG_PM_SLEEP
static int pwm_backlight_suspend(struct device *dev)
{
struct backlight_device *bl = dev_get_drvdata(dev);
struct pwm_bl_data *pb = bl_get_data(bl);
if (pb->notify)
pb->notify(pb->dev, 0);
pwm_backlight_power_off(pb);
if (pb->notify_after)
pb->notify_after(pb->dev, 0);
return 0;
}
static int pwm_backlight_resume(struct device *dev)
{
struct backlight_device *bl = dev_get_drvdata(dev);
backlight_update_status(bl);
return 0;
}
#endif
static const struct dev_pm_ops pwm_backlight_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = pwm_backlight_suspend,
.resume = pwm_backlight_resume,
.poweroff = pwm_backlight_suspend,
.restore = pwm_backlight_resume,
#endif
};
static struct platform_driver pwm_backlight_driver = {
.driver = {
.name = "pwm-backlight",
.pm = &pwm_backlight_pm_ops,
.of_match_table = of_match_ptr(pwm_backlight_of_match),
},
.probe = pwm_backlight_probe,
.remove_new = pwm_backlight_remove,
.shutdown = pwm_backlight_shutdown,
};
module_platform_driver(pwm_backlight_driver);
MODULE_DESCRIPTION("PWM based Backlight Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:pwm-backlight");
| linux-master | drivers/video/backlight/pwm_bl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* iPAQ microcontroller backlight support
* Author : Linus Walleij <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/mfd/ipaq-micro.h>
#include <linux/module.h>
#include <linux/platform_device.h>
static int micro_bl_update_status(struct backlight_device *bd)
{
struct ipaq_micro *micro = dev_get_drvdata(&bd->dev);
int intensity = backlight_get_brightness(bd);
struct ipaq_micro_msg msg = {
.id = MSG_BACKLIGHT,
.tx_len = 3,
};
/*
* Message format:
* Byte 0: backlight instance (usually 1)
* Byte 1: on/off
* Byte 2: intensity, 0-255
*/
msg.tx_data[0] = 0x01;
msg.tx_data[1] = intensity > 0 ? 1 : 0;
msg.tx_data[2] = intensity;
return ipaq_micro_tx_msg_sync(micro, &msg);
}
static const struct backlight_ops micro_bl_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = micro_bl_update_status,
};
static const struct backlight_properties micro_bl_props = {
.type = BACKLIGHT_RAW,
.max_brightness = 255,
.power = FB_BLANK_UNBLANK,
.brightness = 64,
};
static int micro_backlight_probe(struct platform_device *pdev)
{
struct backlight_device *bd;
struct ipaq_micro *micro = dev_get_drvdata(pdev->dev.parent);
bd = devm_backlight_device_register(&pdev->dev, "ipaq-micro-backlight",
&pdev->dev, micro, µ_bl_ops,
µ_bl_props);
if (IS_ERR(bd))
return PTR_ERR(bd);
platform_set_drvdata(pdev, bd);
backlight_update_status(bd);
return 0;
}
static struct platform_driver micro_backlight_device_driver = {
.driver = {
.name = "ipaq-micro-backlight",
},
.probe = micro_backlight_probe,
};
module_platform_driver(micro_backlight_device_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("driver for iPAQ Atmel micro backlight");
MODULE_ALIAS("platform:ipaq-micro-backlight");
| linux-master | drivers/video/backlight/ipaq_micro_bl.c |
// SPDX-License-Identifier: GPL-2.0
/* Driver for ORISE Technology OTM3225A SOC for TFT LCD
* Copyright (C) 2017, EETS GmbH, Felix Brack <[email protected]>
*
* This driver implements a lcd device for the ORISE OTM3225A display
* controller. The control interface to the display is SPI and the display's
* memory is updated over the 16-bit RGB interface.
* The main source of information for writing this driver was provided by the
* OTM3225A datasheet from ORISE Technology. Some information arise from the
* ILI9328 datasheet from ILITEK as well as from the datasheets and sample code
* provided by Crystalfontz America Inc. who sells the CFAF240320A-032T, a 3.2"
* TFT LC display using the OTM3225A controller.
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/lcd.h>
#include <linux/module.h>
#include <linux/spi/spi.h>
#define OTM3225A_INDEX_REG 0x70
#define OTM3225A_DATA_REG 0x72
/* instruction register list */
#define DRIVER_OUTPUT_CTRL_1 0x01
#define DRIVER_WAVEFORM_CTRL 0x02
#define ENTRY_MODE 0x03
#define SCALING_CTRL 0x04
#define DISPLAY_CTRL_1 0x07
#define DISPLAY_CTRL_2 0x08
#define DISPLAY_CTRL_3 0x09
#define FRAME_CYCLE_CTRL 0x0A
#define EXT_DISP_IFACE_CTRL_1 0x0C
#define FRAME_MAKER_POS 0x0D
#define EXT_DISP_IFACE_CTRL_2 0x0F
#define POWER_CTRL_1 0x10
#define POWER_CTRL_2 0x11
#define POWER_CTRL_3 0x12
#define POWER_CTRL_4 0x13
#define GRAM_ADDR_HORIZ_SET 0x20
#define GRAM_ADDR_VERT_SET 0x21
#define GRAM_READ_WRITE 0x22
#define POWER_CTRL_7 0x29
#define FRAME_RATE_CTRL 0x2B
#define GAMMA_CTRL_1 0x30
#define GAMMA_CTRL_2 0x31
#define GAMMA_CTRL_3 0x32
#define GAMMA_CTRL_4 0x35
#define GAMMA_CTRL_5 0x36
#define GAMMA_CTRL_6 0x37
#define GAMMA_CTRL_7 0x38
#define GAMMA_CTRL_8 0x39
#define GAMMA_CTRL_9 0x3C
#define GAMMA_CTRL_10 0x3D
#define WINDOW_HORIZ_RAM_START 0x50
#define WINDOW_HORIZ_RAM_END 0x51
#define WINDOW_VERT_RAM_START 0x52
#define WINDOW_VERT_RAM_END 0x53
#define DRIVER_OUTPUT_CTRL_2 0x60
#define BASE_IMG_DISPLAY_CTRL 0x61
#define VERT_SCROLL_CTRL 0x6A
#define PD1_DISPLAY_POS 0x80
#define PD1_RAM_START 0x81
#define PD1_RAM_END 0x82
#define PD2_DISPLAY_POS 0x83
#define PD2_RAM_START 0x84
#define PD2_RAM_END 0x85
#define PANEL_IFACE_CTRL_1 0x90
#define PANEL_IFACE_CTRL_2 0x92
#define PANEL_IFACE_CTRL_4 0x95
#define PANEL_IFACE_CTRL_5 0x97
struct otm3225a_data {
struct spi_device *spi;
struct lcd_device *ld;
int power;
};
struct otm3225a_spi_instruction {
unsigned char reg; /* register to write */
unsigned short value; /* data to write to 'reg' */
unsigned short delay; /* delay in ms after write */
};
static struct otm3225a_spi_instruction display_init[] = {
{ DRIVER_OUTPUT_CTRL_1, 0x0000, 0 },
{ DRIVER_WAVEFORM_CTRL, 0x0700, 0 },
{ ENTRY_MODE, 0x50A0, 0 },
{ SCALING_CTRL, 0x0000, 0 },
{ DISPLAY_CTRL_2, 0x0606, 0 },
{ DISPLAY_CTRL_3, 0x0000, 0 },
{ FRAME_CYCLE_CTRL, 0x0000, 0 },
{ EXT_DISP_IFACE_CTRL_1, 0x0000, 0 },
{ FRAME_MAKER_POS, 0x0000, 0 },
{ EXT_DISP_IFACE_CTRL_2, 0x0002, 0 },
{ POWER_CTRL_2, 0x0007, 0 },
{ POWER_CTRL_3, 0x0000, 0 },
{ POWER_CTRL_4, 0x0000, 200 },
{ DISPLAY_CTRL_1, 0x0101, 0 },
{ POWER_CTRL_1, 0x12B0, 0 },
{ POWER_CTRL_2, 0x0007, 0 },
{ POWER_CTRL_3, 0x01BB, 50 },
{ POWER_CTRL_4, 0x0013, 0 },
{ POWER_CTRL_7, 0x0010, 50 },
{ GAMMA_CTRL_1, 0x000A, 0 },
{ GAMMA_CTRL_2, 0x1326, 0 },
{ GAMMA_CTRL_3, 0x0A29, 0 },
{ GAMMA_CTRL_4, 0x0A0A, 0 },
{ GAMMA_CTRL_5, 0x1E03, 0 },
{ GAMMA_CTRL_6, 0x031E, 0 },
{ GAMMA_CTRL_7, 0x0706, 0 },
{ GAMMA_CTRL_8, 0x0303, 0 },
{ GAMMA_CTRL_9, 0x010E, 0 },
{ GAMMA_CTRL_10, 0x040E, 0 },
{ WINDOW_HORIZ_RAM_START, 0x0000, 0 },
{ WINDOW_HORIZ_RAM_END, 0x00EF, 0 },
{ WINDOW_VERT_RAM_START, 0x0000, 0 },
{ WINDOW_VERT_RAM_END, 0x013F, 0 },
{ DRIVER_OUTPUT_CTRL_2, 0x2700, 0 },
{ BASE_IMG_DISPLAY_CTRL, 0x0001, 0 },
{ VERT_SCROLL_CTRL, 0x0000, 0 },
{ PD1_DISPLAY_POS, 0x0000, 0 },
{ PD1_RAM_START, 0x0000, 0 },
{ PD1_RAM_END, 0x0000, 0 },
{ PD2_DISPLAY_POS, 0x0000, 0 },
{ PD2_RAM_START, 0x0000, 0 },
{ PD2_RAM_END, 0x0000, 0 },
{ PANEL_IFACE_CTRL_1, 0x0010, 0 },
{ PANEL_IFACE_CTRL_2, 0x0000, 0 },
{ PANEL_IFACE_CTRL_4, 0x0210, 0 },
{ PANEL_IFACE_CTRL_5, 0x0000, 0 },
{ DISPLAY_CTRL_1, 0x0133, 0 },
};
static struct otm3225a_spi_instruction display_enable_rgb_interface[] = {
{ ENTRY_MODE, 0x1080, 0 },
{ GRAM_ADDR_HORIZ_SET, 0x0000, 0 },
{ GRAM_ADDR_VERT_SET, 0x0000, 0 },
{ EXT_DISP_IFACE_CTRL_1, 0x0111, 500 },
};
static struct otm3225a_spi_instruction display_off[] = {
{ DISPLAY_CTRL_1, 0x0131, 100 },
{ DISPLAY_CTRL_1, 0x0130, 100 },
{ DISPLAY_CTRL_1, 0x0100, 0 },
{ POWER_CTRL_1, 0x0280, 0 },
{ POWER_CTRL_3, 0x018B, 0 },
};
static struct otm3225a_spi_instruction display_on[] = {
{ POWER_CTRL_1, 0x1280, 0 },
{ DISPLAY_CTRL_1, 0x0101, 100 },
{ DISPLAY_CTRL_1, 0x0121, 0 },
{ DISPLAY_CTRL_1, 0x0123, 100 },
{ DISPLAY_CTRL_1, 0x0133, 10 },
};
static void otm3225a_write(struct spi_device *spi,
struct otm3225a_spi_instruction *instruction,
unsigned int count)
{
unsigned char buf[3];
while (count--) {
/* address register using index register */
buf[0] = OTM3225A_INDEX_REG;
buf[1] = 0x00;
buf[2] = instruction->reg;
spi_write(spi, buf, 3);
/* write data to addressed register */
buf[0] = OTM3225A_DATA_REG;
buf[1] = (instruction->value >> 8) & 0xff;
buf[2] = instruction->value & 0xff;
spi_write(spi, buf, 3);
/* execute delay if any */
if (instruction->delay)
msleep(instruction->delay);
instruction++;
}
}
static int otm3225a_set_power(struct lcd_device *ld, int power)
{
struct otm3225a_data *dd = lcd_get_data(ld);
if (power == dd->power)
return 0;
if (power > FB_BLANK_UNBLANK)
otm3225a_write(dd->spi, display_off, ARRAY_SIZE(display_off));
else
otm3225a_write(dd->spi, display_on, ARRAY_SIZE(display_on));
dd->power = power;
return 0;
}
static int otm3225a_get_power(struct lcd_device *ld)
{
struct otm3225a_data *dd = lcd_get_data(ld);
return dd->power;
}
static struct lcd_ops otm3225a_ops = {
.set_power = otm3225a_set_power,
.get_power = otm3225a_get_power,
};
static int otm3225a_probe(struct spi_device *spi)
{
struct otm3225a_data *dd;
struct lcd_device *ld;
struct device *dev = &spi->dev;
dd = devm_kzalloc(dev, sizeof(struct otm3225a_data), GFP_KERNEL);
if (dd == NULL)
return -ENOMEM;
ld = devm_lcd_device_register(dev, dev_name(dev), dev, dd,
&otm3225a_ops);
if (IS_ERR(ld))
return PTR_ERR(ld);
dd->spi = spi;
dd->ld = ld;
dev_set_drvdata(dev, dd);
dev_info(dev, "Initializing and switching to RGB interface");
otm3225a_write(spi, display_init, ARRAY_SIZE(display_init));
otm3225a_write(spi, display_enable_rgb_interface,
ARRAY_SIZE(display_enable_rgb_interface));
return 0;
}
static struct spi_driver otm3225a_driver = {
.driver = {
.name = "otm3225a",
.owner = THIS_MODULE,
},
.probe = otm3225a_probe,
};
module_spi_driver(otm3225a_driver);
MODULE_AUTHOR("Felix Brack <[email protected]>");
MODULE_DESCRIPTION("OTM3225A TFT LCD driver");
MODULE_VERSION("1.0.0");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/backlight/otm3225a.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Sanyo LV5207LP LED Driver
*
* Copyright (C) 2013 Ideas on board SPRL
*
* Contact: Laurent Pinchart <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/platform_data/lv5207lp.h>
#include <linux/slab.h>
#define LV5207LP_CTRL1 0x00
#define LV5207LP_CPSW (1 << 7)
#define LV5207LP_SCTEN (1 << 6)
#define LV5207LP_C10 (1 << 5)
#define LV5207LP_CKSW (1 << 4)
#define LV5207LP_RSW (1 << 3)
#define LV5207LP_GSW (1 << 2)
#define LV5207LP_BSW (1 << 1)
#define LV5207LP_CTRL2 0x01
#define LV5207LP_MSW (1 << 7)
#define LV5207LP_MLED4 (1 << 6)
#define LV5207LP_RED 0x02
#define LV5207LP_GREEN 0x03
#define LV5207LP_BLUE 0x04
#define LV5207LP_MAX_BRIGHTNESS 32
struct lv5207lp {
struct i2c_client *client;
struct backlight_device *backlight;
struct lv5207lp_platform_data *pdata;
};
static int lv5207lp_write(struct lv5207lp *lv, u8 reg, u8 data)
{
return i2c_smbus_write_byte_data(lv->client, reg, data);
}
static int lv5207lp_backlight_update_status(struct backlight_device *backlight)
{
struct lv5207lp *lv = bl_get_data(backlight);
int brightness = backlight_get_brightness(backlight);
if (brightness) {
lv5207lp_write(lv, LV5207LP_CTRL1,
LV5207LP_CPSW | LV5207LP_C10 | LV5207LP_CKSW);
lv5207lp_write(lv, LV5207LP_CTRL2,
LV5207LP_MSW | LV5207LP_MLED4 |
(brightness - 1));
} else {
lv5207lp_write(lv, LV5207LP_CTRL1, 0);
lv5207lp_write(lv, LV5207LP_CTRL2, 0);
}
return 0;
}
static int lv5207lp_backlight_check_fb(struct backlight_device *backlight,
struct fb_info *info)
{
struct lv5207lp *lv = bl_get_data(backlight);
return !lv->pdata->dev || lv->pdata->dev == info->device;
}
static const struct backlight_ops lv5207lp_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = lv5207lp_backlight_update_status,
.check_fb = lv5207lp_backlight_check_fb,
};
static int lv5207lp_probe(struct i2c_client *client)
{
struct lv5207lp_platform_data *pdata = dev_get_platdata(&client->dev);
struct backlight_device *backlight;
struct backlight_properties props;
struct lv5207lp *lv;
if (pdata == NULL) {
dev_err(&client->dev, "No platform data supplied\n");
return -EINVAL;
}
if (!i2c_check_functionality(client->adapter,
I2C_FUNC_SMBUS_BYTE_DATA)) {
dev_warn(&client->dev,
"I2C adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
return -EIO;
}
lv = devm_kzalloc(&client->dev, sizeof(*lv), GFP_KERNEL);
if (!lv)
return -ENOMEM;
lv->client = client;
lv->pdata = pdata;
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
props.max_brightness = min_t(unsigned int, pdata->max_value,
LV5207LP_MAX_BRIGHTNESS);
props.brightness = clamp_t(unsigned int, pdata->def_value, 0,
props.max_brightness);
backlight = devm_backlight_device_register(&client->dev,
dev_name(&client->dev), &lv->client->dev,
lv, &lv5207lp_backlight_ops, &props);
if (IS_ERR(backlight)) {
dev_err(&client->dev, "failed to register backlight\n");
return PTR_ERR(backlight);
}
backlight_update_status(backlight);
i2c_set_clientdata(client, backlight);
return 0;
}
static void lv5207lp_remove(struct i2c_client *client)
{
struct backlight_device *backlight = i2c_get_clientdata(client);
backlight->props.brightness = 0;
backlight_update_status(backlight);
}
static const struct i2c_device_id lv5207lp_ids[] = {
{ "lv5207lp", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, lv5207lp_ids);
static struct i2c_driver lv5207lp_driver = {
.driver = {
.name = "lv5207lp",
},
.probe = lv5207lp_probe,
.remove = lv5207lp_remove,
.id_table = lv5207lp_ids,
};
module_i2c_driver(lv5207lp_driver);
MODULE_DESCRIPTION("Sanyo LV5207LP Backlight Driver");
MODULE_AUTHOR("Laurent Pinchart <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/backlight/lv5207lp.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Himax HX-8357 LCD Controller
*
* Copyright 2012 Free Electrons
*/
#include <linux/delay.h>
#include <linux/lcd.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/spi/spi.h>
#define HX8357_NUM_IM_PINS 3
#define HX8357_SWRESET 0x01
#define HX8357_GET_RED_CHANNEL 0x06
#define HX8357_GET_GREEN_CHANNEL 0x07
#define HX8357_GET_BLUE_CHANNEL 0x08
#define HX8357_GET_POWER_MODE 0x0a
#define HX8357_GET_MADCTL 0x0b
#define HX8357_GET_PIXEL_FORMAT 0x0c
#define HX8357_GET_DISPLAY_MODE 0x0d
#define HX8357_GET_SIGNAL_MODE 0x0e
#define HX8357_GET_DIAGNOSTIC_RESULT 0x0f
#define HX8357_ENTER_SLEEP_MODE 0x10
#define HX8357_EXIT_SLEEP_MODE 0x11
#define HX8357_ENTER_PARTIAL_MODE 0x12
#define HX8357_ENTER_NORMAL_MODE 0x13
#define HX8357_EXIT_INVERSION_MODE 0x20
#define HX8357_ENTER_INVERSION_MODE 0x21
#define HX8357_SET_DISPLAY_OFF 0x28
#define HX8357_SET_DISPLAY_ON 0x29
#define HX8357_SET_COLUMN_ADDRESS 0x2a
#define HX8357_SET_PAGE_ADDRESS 0x2b
#define HX8357_WRITE_MEMORY_START 0x2c
#define HX8357_READ_MEMORY_START 0x2e
#define HX8357_SET_PARTIAL_AREA 0x30
#define HX8357_SET_SCROLL_AREA 0x33
#define HX8357_SET_TEAR_OFF 0x34
#define HX8357_SET_TEAR_ON 0x35
#define HX8357_SET_ADDRESS_MODE 0x36
#define HX8357_SET_SCROLL_START 0x37
#define HX8357_EXIT_IDLE_MODE 0x38
#define HX8357_ENTER_IDLE_MODE 0x39
#define HX8357_SET_PIXEL_FORMAT 0x3a
#define HX8357_SET_PIXEL_FORMAT_DBI_3BIT (0x1)
#define HX8357_SET_PIXEL_FORMAT_DBI_16BIT (0x5)
#define HX8357_SET_PIXEL_FORMAT_DBI_18BIT (0x6)
#define HX8357_SET_PIXEL_FORMAT_DPI_3BIT (0x1 << 4)
#define HX8357_SET_PIXEL_FORMAT_DPI_16BIT (0x5 << 4)
#define HX8357_SET_PIXEL_FORMAT_DPI_18BIT (0x6 << 4)
#define HX8357_WRITE_MEMORY_CONTINUE 0x3c
#define HX8357_READ_MEMORY_CONTINUE 0x3e
#define HX8357_SET_TEAR_SCAN_LINES 0x44
#define HX8357_GET_SCAN_LINES 0x45
#define HX8357_READ_DDB_START 0xa1
#define HX8357_SET_DISPLAY_MODE 0xb4
#define HX8357_SET_DISPLAY_MODE_RGB_THROUGH (0x3)
#define HX8357_SET_DISPLAY_MODE_RGB_INTERFACE (1 << 4)
#define HX8357_SET_PANEL_DRIVING 0xc0
#define HX8357_SET_DISPLAY_FRAME 0xc5
#define HX8357_SET_RGB 0xc6
#define HX8357_SET_RGB_ENABLE_HIGH (1 << 1)
#define HX8357_SET_GAMMA 0xc8
#define HX8357_SET_POWER 0xd0
#define HX8357_SET_VCOM 0xd1
#define HX8357_SET_POWER_NORMAL 0xd2
#define HX8357_SET_PANEL_RELATED 0xe9
#define HX8369_SET_DISPLAY_BRIGHTNESS 0x51
#define HX8369_WRITE_CABC_DISPLAY_VALUE 0x53
#define HX8369_WRITE_CABC_BRIGHT_CTRL 0x55
#define HX8369_WRITE_CABC_MIN_BRIGHTNESS 0x5e
#define HX8369_SET_POWER 0xb1
#define HX8369_SET_DISPLAY_MODE 0xb2
#define HX8369_SET_DISPLAY_WAVEFORM_CYC 0xb4
#define HX8369_SET_VCOM 0xb6
#define HX8369_SET_EXTENSION_COMMAND 0xb9
#define HX8369_SET_GIP 0xd5
#define HX8369_SET_GAMMA_CURVE_RELATED 0xe0
struct hx8357_data {
unsigned im_pins[HX8357_NUM_IM_PINS];
unsigned reset;
struct spi_device *spi;
int state;
bool use_im_pins;
};
static u8 hx8357_seq_power[] = {
HX8357_SET_POWER, 0x44, 0x41, 0x06,
};
static u8 hx8357_seq_vcom[] = {
HX8357_SET_VCOM, 0x40, 0x10,
};
static u8 hx8357_seq_power_normal[] = {
HX8357_SET_POWER_NORMAL, 0x05, 0x12,
};
static u8 hx8357_seq_panel_driving[] = {
HX8357_SET_PANEL_DRIVING, 0x14, 0x3b, 0x00, 0x02, 0x11,
};
static u8 hx8357_seq_display_frame[] = {
HX8357_SET_DISPLAY_FRAME, 0x0c,
};
static u8 hx8357_seq_panel_related[] = {
HX8357_SET_PANEL_RELATED, 0x01,
};
static u8 hx8357_seq_undefined1[] = {
0xea, 0x03, 0x00, 0x00,
};
static u8 hx8357_seq_undefined2[] = {
0xeb, 0x40, 0x54, 0x26, 0xdb,
};
static u8 hx8357_seq_gamma[] = {
HX8357_SET_GAMMA, 0x00, 0x15, 0x00, 0x22, 0x00,
0x08, 0x77, 0x26, 0x77, 0x22, 0x04, 0x00,
};
static u8 hx8357_seq_address_mode[] = {
HX8357_SET_ADDRESS_MODE, 0xc0,
};
static u8 hx8357_seq_pixel_format[] = {
HX8357_SET_PIXEL_FORMAT,
HX8357_SET_PIXEL_FORMAT_DPI_18BIT |
HX8357_SET_PIXEL_FORMAT_DBI_18BIT,
};
static u8 hx8357_seq_column_address[] = {
HX8357_SET_COLUMN_ADDRESS, 0x00, 0x00, 0x01, 0x3f,
};
static u8 hx8357_seq_page_address[] = {
HX8357_SET_PAGE_ADDRESS, 0x00, 0x00, 0x01, 0xdf,
};
static u8 hx8357_seq_rgb[] = {
HX8357_SET_RGB, 0x02,
};
static u8 hx8357_seq_display_mode[] = {
HX8357_SET_DISPLAY_MODE,
HX8357_SET_DISPLAY_MODE_RGB_THROUGH |
HX8357_SET_DISPLAY_MODE_RGB_INTERFACE,
};
static u8 hx8369_seq_write_CABC_min_brightness[] = {
HX8369_WRITE_CABC_MIN_BRIGHTNESS, 0x00,
};
static u8 hx8369_seq_write_CABC_control[] = {
HX8369_WRITE_CABC_DISPLAY_VALUE, 0x24,
};
static u8 hx8369_seq_set_display_brightness[] = {
HX8369_SET_DISPLAY_BRIGHTNESS, 0xFF,
};
static u8 hx8369_seq_write_CABC_control_setting[] = {
HX8369_WRITE_CABC_BRIGHT_CTRL, 0x02,
};
static u8 hx8369_seq_extension_command[] = {
HX8369_SET_EXTENSION_COMMAND, 0xff, 0x83, 0x69,
};
static u8 hx8369_seq_display_related[] = {
HX8369_SET_DISPLAY_MODE, 0x00, 0x2b, 0x03, 0x03, 0x70, 0x00,
0xff, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x01,
};
static u8 hx8369_seq_panel_waveform_cycle[] = {
HX8369_SET_DISPLAY_WAVEFORM_CYC, 0x0a, 0x1d, 0x80, 0x06, 0x02,
};
static u8 hx8369_seq_set_address_mode[] = {
HX8357_SET_ADDRESS_MODE, 0x00,
};
static u8 hx8369_seq_vcom[] = {
HX8369_SET_VCOM, 0x3e, 0x3e,
};
static u8 hx8369_seq_gip[] = {
HX8369_SET_GIP, 0x00, 0x01, 0x03, 0x25, 0x01, 0x02, 0x28, 0x70,
0x11, 0x13, 0x00, 0x00, 0x40, 0x26, 0x51, 0x37, 0x00, 0x00, 0x71,
0x35, 0x60, 0x24, 0x07, 0x0f, 0x04, 0x04,
};
static u8 hx8369_seq_power[] = {
HX8369_SET_POWER, 0x01, 0x00, 0x34, 0x03, 0x00, 0x11, 0x11, 0x32,
0x2f, 0x3f, 0x3f, 0x01, 0x3a, 0x01, 0xe6, 0xe6, 0xe6, 0xe6, 0xe6,
};
static u8 hx8369_seq_gamma_curve_related[] = {
HX8369_SET_GAMMA_CURVE_RELATED, 0x00, 0x0d, 0x19, 0x2f, 0x3b, 0x3d,
0x2e, 0x4a, 0x08, 0x0e, 0x0f, 0x14, 0x16, 0x14, 0x14, 0x14, 0x1e,
0x00, 0x0d, 0x19, 0x2f, 0x3b, 0x3d, 0x2e, 0x4a, 0x08, 0x0e, 0x0f,
0x14, 0x16, 0x14, 0x14, 0x14, 0x1e,
};
static int hx8357_spi_write_then_read(struct lcd_device *lcdev,
u8 *txbuf, u16 txlen,
u8 *rxbuf, u16 rxlen)
{
struct hx8357_data *lcd = lcd_get_data(lcdev);
struct spi_message msg;
struct spi_transfer xfer[2];
u16 *local_txbuf = NULL;
int ret = 0;
memset(xfer, 0, sizeof(xfer));
spi_message_init(&msg);
if (txlen) {
int i;
local_txbuf = kcalloc(txlen, sizeof(*local_txbuf), GFP_KERNEL);
if (!local_txbuf)
return -ENOMEM;
for (i = 0; i < txlen; i++) {
local_txbuf[i] = txbuf[i];
if (i > 0)
local_txbuf[i] |= 1 << 8;
}
xfer[0].len = 2 * txlen;
xfer[0].bits_per_word = 9;
xfer[0].tx_buf = local_txbuf;
spi_message_add_tail(&xfer[0], &msg);
}
if (rxlen) {
xfer[1].len = rxlen;
xfer[1].bits_per_word = 8;
xfer[1].rx_buf = rxbuf;
spi_message_add_tail(&xfer[1], &msg);
}
ret = spi_sync(lcd->spi, &msg);
if (ret < 0)
dev_err(&lcdev->dev, "Couldn't send SPI data\n");
if (txlen)
kfree(local_txbuf);
return ret;
}
static inline int hx8357_spi_write_array(struct lcd_device *lcdev,
u8 *value, u8 len)
{
return hx8357_spi_write_then_read(lcdev, value, len, NULL, 0);
}
static inline int hx8357_spi_write_byte(struct lcd_device *lcdev,
u8 value)
{
return hx8357_spi_write_then_read(lcdev, &value, 1, NULL, 0);
}
static int hx8357_enter_standby(struct lcd_device *lcdev)
{
int ret;
ret = hx8357_spi_write_byte(lcdev, HX8357_SET_DISPLAY_OFF);
if (ret < 0)
return ret;
usleep_range(10000, 12000);
ret = hx8357_spi_write_byte(lcdev, HX8357_ENTER_SLEEP_MODE);
if (ret < 0)
return ret;
/*
* The controller needs 120ms when entering in sleep mode before we can
* send the command to go off sleep mode
*/
msleep(120);
return 0;
}
static int hx8357_exit_standby(struct lcd_device *lcdev)
{
int ret;
ret = hx8357_spi_write_byte(lcdev, HX8357_EXIT_SLEEP_MODE);
if (ret < 0)
return ret;
/*
* The controller needs 120ms when exiting from sleep mode before we
* can send the command to enter in sleep mode
*/
msleep(120);
ret = hx8357_spi_write_byte(lcdev, HX8357_SET_DISPLAY_ON);
if (ret < 0)
return ret;
return 0;
}
static void hx8357_lcd_reset(struct lcd_device *lcdev)
{
struct hx8357_data *lcd = lcd_get_data(lcdev);
/* Reset the screen */
gpio_set_value(lcd->reset, 1);
usleep_range(10000, 12000);
gpio_set_value(lcd->reset, 0);
usleep_range(10000, 12000);
gpio_set_value(lcd->reset, 1);
/* The controller needs 120ms to recover from reset */
msleep(120);
}
static int hx8357_lcd_init(struct lcd_device *lcdev)
{
struct hx8357_data *lcd = lcd_get_data(lcdev);
int ret;
/*
* Set the interface selection pins to SPI mode, with three
* wires
*/
if (lcd->use_im_pins) {
gpio_set_value_cansleep(lcd->im_pins[0], 1);
gpio_set_value_cansleep(lcd->im_pins[1], 0);
gpio_set_value_cansleep(lcd->im_pins[2], 1);
}
ret = hx8357_spi_write_array(lcdev, hx8357_seq_power,
ARRAY_SIZE(hx8357_seq_power));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_vcom,
ARRAY_SIZE(hx8357_seq_vcom));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_power_normal,
ARRAY_SIZE(hx8357_seq_power_normal));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_panel_driving,
ARRAY_SIZE(hx8357_seq_panel_driving));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_display_frame,
ARRAY_SIZE(hx8357_seq_display_frame));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_panel_related,
ARRAY_SIZE(hx8357_seq_panel_related));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_undefined1,
ARRAY_SIZE(hx8357_seq_undefined1));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_undefined2,
ARRAY_SIZE(hx8357_seq_undefined2));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_gamma,
ARRAY_SIZE(hx8357_seq_gamma));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_address_mode,
ARRAY_SIZE(hx8357_seq_address_mode));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_pixel_format,
ARRAY_SIZE(hx8357_seq_pixel_format));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_column_address,
ARRAY_SIZE(hx8357_seq_column_address));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_page_address,
ARRAY_SIZE(hx8357_seq_page_address));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_rgb,
ARRAY_SIZE(hx8357_seq_rgb));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8357_seq_display_mode,
ARRAY_SIZE(hx8357_seq_display_mode));
if (ret < 0)
return ret;
ret = hx8357_spi_write_byte(lcdev, HX8357_EXIT_SLEEP_MODE);
if (ret < 0)
return ret;
/*
* The controller needs 120ms to fully recover from exiting sleep mode
*/
msleep(120);
ret = hx8357_spi_write_byte(lcdev, HX8357_SET_DISPLAY_ON);
if (ret < 0)
return ret;
usleep_range(5000, 7000);
ret = hx8357_spi_write_byte(lcdev, HX8357_WRITE_MEMORY_START);
if (ret < 0)
return ret;
return 0;
}
static int hx8369_lcd_init(struct lcd_device *lcdev)
{
int ret;
ret = hx8357_spi_write_array(lcdev, hx8369_seq_extension_command,
ARRAY_SIZE(hx8369_seq_extension_command));
if (ret < 0)
return ret;
usleep_range(10000, 12000);
ret = hx8357_spi_write_array(lcdev, hx8369_seq_display_related,
ARRAY_SIZE(hx8369_seq_display_related));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8369_seq_panel_waveform_cycle,
ARRAY_SIZE(hx8369_seq_panel_waveform_cycle));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8369_seq_set_address_mode,
ARRAY_SIZE(hx8369_seq_set_address_mode));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8369_seq_vcom,
ARRAY_SIZE(hx8369_seq_vcom));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8369_seq_gip,
ARRAY_SIZE(hx8369_seq_gip));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev, hx8369_seq_power,
ARRAY_SIZE(hx8369_seq_power));
if (ret < 0)
return ret;
ret = hx8357_spi_write_byte(lcdev, HX8357_EXIT_SLEEP_MODE);
if (ret < 0)
return ret;
/*
* The controller needs 120ms to fully recover from exiting sleep mode
*/
msleep(120);
ret = hx8357_spi_write_array(lcdev, hx8369_seq_gamma_curve_related,
ARRAY_SIZE(hx8369_seq_gamma_curve_related));
if (ret < 0)
return ret;
ret = hx8357_spi_write_byte(lcdev, HX8357_EXIT_SLEEP_MODE);
if (ret < 0)
return ret;
usleep_range(1000, 1200);
ret = hx8357_spi_write_array(lcdev, hx8369_seq_write_CABC_control,
ARRAY_SIZE(hx8369_seq_write_CABC_control));
if (ret < 0)
return ret;
usleep_range(10000, 12000);
ret = hx8357_spi_write_array(lcdev,
hx8369_seq_write_CABC_control_setting,
ARRAY_SIZE(hx8369_seq_write_CABC_control_setting));
if (ret < 0)
return ret;
ret = hx8357_spi_write_array(lcdev,
hx8369_seq_write_CABC_min_brightness,
ARRAY_SIZE(hx8369_seq_write_CABC_min_brightness));
if (ret < 0)
return ret;
usleep_range(10000, 12000);
ret = hx8357_spi_write_array(lcdev, hx8369_seq_set_display_brightness,
ARRAY_SIZE(hx8369_seq_set_display_brightness));
if (ret < 0)
return ret;
ret = hx8357_spi_write_byte(lcdev, HX8357_SET_DISPLAY_ON);
if (ret < 0)
return ret;
return 0;
}
#define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
static int hx8357_set_power(struct lcd_device *lcdev, int power)
{
struct hx8357_data *lcd = lcd_get_data(lcdev);
int ret = 0;
if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->state))
ret = hx8357_exit_standby(lcdev);
else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->state))
ret = hx8357_enter_standby(lcdev);
if (ret == 0)
lcd->state = power;
else
dev_warn(&lcdev->dev, "failed to set power mode %d\n", power);
return ret;
}
static int hx8357_get_power(struct lcd_device *lcdev)
{
struct hx8357_data *lcd = lcd_get_data(lcdev);
return lcd->state;
}
static struct lcd_ops hx8357_ops = {
.set_power = hx8357_set_power,
.get_power = hx8357_get_power,
};
static const struct of_device_id hx8357_dt_ids[] = {
{
.compatible = "himax,hx8357",
.data = hx8357_lcd_init,
},
{
.compatible = "himax,hx8369",
.data = hx8369_lcd_init,
},
{},
};
MODULE_DEVICE_TABLE(of, hx8357_dt_ids);
static int hx8357_probe(struct spi_device *spi)
{
struct lcd_device *lcdev;
struct hx8357_data *lcd;
const struct of_device_id *match;
int i, ret;
lcd = devm_kzalloc(&spi->dev, sizeof(*lcd), GFP_KERNEL);
if (!lcd)
return -ENOMEM;
ret = spi_setup(spi);
if (ret < 0) {
dev_err(&spi->dev, "SPI setup failed.\n");
return ret;
}
lcd->spi = spi;
match = of_match_device(hx8357_dt_ids, &spi->dev);
if (!match || !match->data)
return -EINVAL;
lcd->reset = of_get_named_gpio(spi->dev.of_node, "gpios-reset", 0);
if (!gpio_is_valid(lcd->reset)) {
dev_err(&spi->dev, "Missing dt property: gpios-reset\n");
return -EINVAL;
}
ret = devm_gpio_request_one(&spi->dev, lcd->reset,
GPIOF_OUT_INIT_HIGH,
"hx8357-reset");
if (ret) {
dev_err(&spi->dev,
"failed to request gpio %d: %d\n",
lcd->reset, ret);
return -EINVAL;
}
if (of_property_present(spi->dev.of_node, "im-gpios")) {
lcd->use_im_pins = 1;
for (i = 0; i < HX8357_NUM_IM_PINS; i++) {
lcd->im_pins[i] = of_get_named_gpio(spi->dev.of_node,
"im-gpios", i);
if (lcd->im_pins[i] == -EPROBE_DEFER) {
dev_info(&spi->dev, "GPIO requested is not here yet, deferring the probe\n");
return -EPROBE_DEFER;
}
if (!gpio_is_valid(lcd->im_pins[i])) {
dev_err(&spi->dev, "Missing dt property: im-gpios\n");
return -EINVAL;
}
ret = devm_gpio_request_one(&spi->dev, lcd->im_pins[i],
GPIOF_OUT_INIT_LOW,
"im_pins");
if (ret) {
dev_err(&spi->dev, "failed to request gpio %d: %d\n",
lcd->im_pins[i], ret);
return -EINVAL;
}
}
} else {
lcd->use_im_pins = 0;
}
lcdev = devm_lcd_device_register(&spi->dev, "mxsfb", &spi->dev, lcd,
&hx8357_ops);
if (IS_ERR(lcdev)) {
ret = PTR_ERR(lcdev);
return ret;
}
spi_set_drvdata(spi, lcdev);
hx8357_lcd_reset(lcdev);
ret = ((int (*)(struct lcd_device *))match->data)(lcdev);
if (ret) {
dev_err(&spi->dev, "Couldn't initialize panel\n");
return ret;
}
dev_info(&spi->dev, "Panel probed\n");
return 0;
}
static struct spi_driver hx8357_driver = {
.probe = hx8357_probe,
.driver = {
.name = "hx8357",
.of_match_table = hx8357_dt_ids,
},
};
module_spi_driver(hx8357_driver);
MODULE_AUTHOR("Maxime Ripard <[email protected]>");
MODULE_DESCRIPTION("Himax HX-8357 LCD Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/backlight/hx8357.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
*
* Copyright (C) 2008 Marvell International Ltd.
* Eric Miao <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/spi/tdo24m.h>
#include <linux/fb.h>
#include <linux/lcd.h>
#include <linux/slab.h>
#define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
#define TDO24M_SPI_BUFF_SIZE (4)
#define MODE_QVGA 0
#define MODE_VGA 1
struct tdo24m {
struct spi_device *spi_dev;
struct lcd_device *lcd_dev;
struct spi_message msg;
struct spi_transfer xfer;
uint8_t *buf;
int (*adj_mode)(struct tdo24m *lcd, int mode);
int color_invert;
int power;
int mode;
};
/* use bit 30, 31 as the indicator of command parameter number */
#define CMD0(x) ((0 << 30) | (x))
#define CMD1(x, x1) ((1 << 30) | ((x) << 9) | 0x100 | (x1))
#define CMD2(x, x1, x2) ((2 << 30) | ((x) << 18) | 0x20000 |\
((x1) << 9) | 0x100 | (x2))
#define CMD_NULL (-1)
static const uint32_t lcd_panel_reset[] = {
CMD0(0x1), /* reset */
CMD0(0x0), /* nop */
CMD0(0x0), /* nop */
CMD0(0x0), /* nop */
CMD_NULL,
};
static const uint32_t lcd_panel_on[] = {
CMD0(0x29), /* Display ON */
CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
CMD0(0x11), /* Sleep out */
CMD1(0xB0, 0x16), /* Wake */
CMD_NULL,
};
static const uint32_t lcd_panel_off[] = {
CMD0(0x28), /* Display OFF */
CMD2(0xB8, 0x80, 0x02), /* Output Control */
CMD0(0x10), /* Sleep in */
CMD1(0xB0, 0x00), /* Deep stand by in */
CMD_NULL,
};
static const uint32_t lcd_vga_pass_through_tdo24m[] = {
CMD1(0xB0, 0x16),
CMD1(0xBC, 0x80),
CMD1(0xE1, 0x00),
CMD1(0x36, 0x50),
CMD1(0x3B, 0x00),
CMD_NULL,
};
static const uint32_t lcd_qvga_pass_through_tdo24m[] = {
CMD1(0xB0, 0x16),
CMD1(0xBC, 0x81),
CMD1(0xE1, 0x00),
CMD1(0x36, 0x50),
CMD1(0x3B, 0x22),
CMD_NULL,
};
static const uint32_t lcd_vga_transfer_tdo24m[] = {
CMD1(0xcf, 0x02), /* Blanking period control (1) */
CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
CMD1(0xd1, 0x01), /* CKV timing control on/off */
CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
CMD1(0xd5, 0x14), /* ASW timing control (2) */
CMD0(0x21), /* Invert for normally black display */
CMD0(0x29), /* Display on */
CMD_NULL,
};
static const uint32_t lcd_qvga_transfer[] = {
CMD1(0xd6, 0x02), /* Blanking period control (1) */
CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
CMD1(0xd8, 0x01), /* CKV timing control on/off */
CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
CMD1(0xe0, 0x0a), /* ASW timing control (2) */
CMD0(0x21), /* Invert for normally black display */
CMD0(0x29), /* Display on */
CMD_NULL,
};
static const uint32_t lcd_vga_pass_through_tdo35s[] = {
CMD1(0xB0, 0x16),
CMD1(0xBC, 0x80),
CMD1(0xE1, 0x00),
CMD1(0x3B, 0x00),
CMD_NULL,
};
static const uint32_t lcd_qvga_pass_through_tdo35s[] = {
CMD1(0xB0, 0x16),
CMD1(0xBC, 0x81),
CMD1(0xE1, 0x00),
CMD1(0x3B, 0x22),
CMD_NULL,
};
static const uint32_t lcd_vga_transfer_tdo35s[] = {
CMD1(0xcf, 0x02), /* Blanking period control (1) */
CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
CMD1(0xd1, 0x01), /* CKV timing control on/off */
CMD2(0xd2, 0x00, 0x1e), /* CKV 1,2 timing control */
CMD2(0xd3, 0x14, 0x28), /* OEV timing control */
CMD2(0xd4, 0x28, 0x64), /* ASW timing control (1) */
CMD1(0xd5, 0x28), /* ASW timing control (2) */
CMD0(0x21), /* Invert for normally black display */
CMD0(0x29), /* Display on */
CMD_NULL,
};
static const uint32_t lcd_panel_config[] = {
CMD2(0xb8, 0xff, 0xf9), /* Output control */
CMD0(0x11), /* sleep out */
CMD1(0xba, 0x01), /* Display mode (1) */
CMD1(0xbb, 0x00), /* Display mode (2) */
CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
CMD1(0xbf, 0x10), /* Drive system change control */
CMD1(0xb1, 0x56), /* Booster operation setup */
CMD1(0xb2, 0x33), /* Booster mode setup */
CMD1(0xb3, 0x11), /* Booster frequency setup */
CMD1(0xb4, 0x02), /* Op amp/system clock */
CMD1(0xb5, 0x35), /* VCS voltage */
CMD1(0xb6, 0x40), /* VCOM voltage */
CMD1(0xb7, 0x03), /* External display signal */
CMD1(0xbd, 0x00), /* ASW slew rate */
CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */
CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
CMD_NULL,
};
static int tdo24m_writes(struct tdo24m *lcd, const uint32_t *array)
{
struct spi_transfer *x = &lcd->xfer;
const uint32_t *p = array;
uint32_t data;
int nparams, err = 0;
for (; *p != CMD_NULL; p++) {
if (!lcd->color_invert && *p == CMD0(0x21))
continue;
nparams = (*p >> 30) & 0x3;
data = *p << (7 - nparams);
switch (nparams) {
case 0:
lcd->buf[0] = (data >> 8) & 0xff;
lcd->buf[1] = data & 0xff;
break;
case 1:
lcd->buf[0] = (data >> 16) & 0xff;
lcd->buf[1] = (data >> 8) & 0xff;
lcd->buf[2] = data & 0xff;
break;
case 2:
lcd->buf[0] = (data >> 24) & 0xff;
lcd->buf[1] = (data >> 16) & 0xff;
lcd->buf[2] = (data >> 8) & 0xff;
lcd->buf[3] = data & 0xff;
break;
default:
continue;
}
x->len = nparams + 2;
err = spi_sync(lcd->spi_dev, &lcd->msg);
if (err)
break;
}
return err;
}
static int tdo24m_adj_mode(struct tdo24m *lcd, int mode)
{
switch (mode) {
case MODE_VGA:
tdo24m_writes(lcd, lcd_vga_pass_through_tdo24m);
tdo24m_writes(lcd, lcd_panel_config);
tdo24m_writes(lcd, lcd_vga_transfer_tdo24m);
break;
case MODE_QVGA:
tdo24m_writes(lcd, lcd_qvga_pass_through_tdo24m);
tdo24m_writes(lcd, lcd_panel_config);
tdo24m_writes(lcd, lcd_qvga_transfer);
break;
default:
return -EINVAL;
}
lcd->mode = mode;
return 0;
}
static int tdo35s_adj_mode(struct tdo24m *lcd, int mode)
{
switch (mode) {
case MODE_VGA:
tdo24m_writes(lcd, lcd_vga_pass_through_tdo35s);
tdo24m_writes(lcd, lcd_panel_config);
tdo24m_writes(lcd, lcd_vga_transfer_tdo35s);
break;
case MODE_QVGA:
tdo24m_writes(lcd, lcd_qvga_pass_through_tdo35s);
tdo24m_writes(lcd, lcd_panel_config);
tdo24m_writes(lcd, lcd_qvga_transfer);
break;
default:
return -EINVAL;
}
lcd->mode = mode;
return 0;
}
static int tdo24m_power_on(struct tdo24m *lcd)
{
int err;
err = tdo24m_writes(lcd, lcd_panel_on);
if (err)
goto out;
err = tdo24m_writes(lcd, lcd_panel_reset);
if (err)
goto out;
err = lcd->adj_mode(lcd, lcd->mode);
out:
return err;
}
static int tdo24m_power_off(struct tdo24m *lcd)
{
return tdo24m_writes(lcd, lcd_panel_off);
}
static int tdo24m_power(struct tdo24m *lcd, int power)
{
int ret = 0;
if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
ret = tdo24m_power_on(lcd);
else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
ret = tdo24m_power_off(lcd);
if (!ret)
lcd->power = power;
return ret;
}
static int tdo24m_set_power(struct lcd_device *ld, int power)
{
struct tdo24m *lcd = lcd_get_data(ld);
return tdo24m_power(lcd, power);
}
static int tdo24m_get_power(struct lcd_device *ld)
{
struct tdo24m *lcd = lcd_get_data(ld);
return lcd->power;
}
static int tdo24m_set_mode(struct lcd_device *ld, struct fb_videomode *m)
{
struct tdo24m *lcd = lcd_get_data(ld);
int mode = MODE_QVGA;
if (m->xres == 640 || m->xres == 480)
mode = MODE_VGA;
if (lcd->mode == mode)
return 0;
return lcd->adj_mode(lcd, mode);
}
static struct lcd_ops tdo24m_ops = {
.get_power = tdo24m_get_power,
.set_power = tdo24m_set_power,
.set_mode = tdo24m_set_mode,
};
static int tdo24m_probe(struct spi_device *spi)
{
struct tdo24m *lcd;
struct spi_message *m;
struct spi_transfer *x;
struct tdo24m_platform_data *pdata;
enum tdo24m_model model;
int err;
pdata = dev_get_platdata(&spi->dev);
if (pdata)
model = pdata->model;
else
model = TDO24M;
spi->bits_per_word = 8;
spi->mode = SPI_MODE_3;
err = spi_setup(spi);
if (err)
return err;
lcd = devm_kzalloc(&spi->dev, sizeof(struct tdo24m), GFP_KERNEL);
if (!lcd)
return -ENOMEM;
lcd->spi_dev = spi;
lcd->power = FB_BLANK_POWERDOWN;
lcd->mode = MODE_VGA; /* default to VGA */
lcd->buf = devm_kzalloc(&spi->dev, TDO24M_SPI_BUFF_SIZE, GFP_KERNEL);
if (lcd->buf == NULL)
return -ENOMEM;
m = &lcd->msg;
x = &lcd->xfer;
spi_message_init(m);
x->cs_change = 0;
x->tx_buf = &lcd->buf[0];
spi_message_add_tail(x, m);
switch (model) {
case TDO24M:
lcd->color_invert = 1;
lcd->adj_mode = tdo24m_adj_mode;
break;
case TDO35S:
lcd->adj_mode = tdo35s_adj_mode;
lcd->color_invert = 0;
break;
default:
dev_err(&spi->dev, "Unsupported model");
return -EINVAL;
}
lcd->lcd_dev = devm_lcd_device_register(&spi->dev, "tdo24m", &spi->dev,
lcd, &tdo24m_ops);
if (IS_ERR(lcd->lcd_dev))
return PTR_ERR(lcd->lcd_dev);
spi_set_drvdata(spi, lcd);
err = tdo24m_power(lcd, FB_BLANK_UNBLANK);
if (err)
return err;
return 0;
}
static void tdo24m_remove(struct spi_device *spi)
{
struct tdo24m *lcd = spi_get_drvdata(spi);
tdo24m_power(lcd, FB_BLANK_POWERDOWN);
}
#ifdef CONFIG_PM_SLEEP
static int tdo24m_suspend(struct device *dev)
{
struct tdo24m *lcd = dev_get_drvdata(dev);
return tdo24m_power(lcd, FB_BLANK_POWERDOWN);
}
static int tdo24m_resume(struct device *dev)
{
struct tdo24m *lcd = dev_get_drvdata(dev);
return tdo24m_power(lcd, FB_BLANK_UNBLANK);
}
#endif
static SIMPLE_DEV_PM_OPS(tdo24m_pm_ops, tdo24m_suspend, tdo24m_resume);
/* Power down all displays on reboot, poweroff or halt */
static void tdo24m_shutdown(struct spi_device *spi)
{
struct tdo24m *lcd = spi_get_drvdata(spi);
tdo24m_power(lcd, FB_BLANK_POWERDOWN);
}
static struct spi_driver tdo24m_driver = {
.driver = {
.name = "tdo24m",
.pm = &tdo24m_pm_ops,
},
.probe = tdo24m_probe,
.remove = tdo24m_remove,
.shutdown = tdo24m_shutdown,
};
module_spi_driver(tdo24m_driver);
MODULE_AUTHOR("Eric Miao <[email protected]>");
MODULE_DESCRIPTION("Driver for Toppoly TDO24M LCD Panel");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:tdo24m");
| linux-master | drivers/video/backlight/tdo24m.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
*
* Backlight driver for HP Jornada 700 series (710/720/728)
* Copyright (C) 2006-2009 Kristoffer Ericson <[email protected]>
*/
#include <linux/backlight.h>
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <mach/jornada720.h>
#include <mach/hardware.h>
#include <video/s1d13xxxfb.h>
#define BL_MAX_BRIGHT 255
#define BL_DEF_BRIGHT 25
static int jornada_bl_get_brightness(struct backlight_device *bd)
{
int ret;
/* check if backlight is on */
if (!(PPSR & PPC_LDD1))
return 0;
jornada_ssp_start();
/* cmd should return txdummy */
ret = jornada_ssp_byte(GETBRIGHTNESS);
if (jornada_ssp_byte(GETBRIGHTNESS) != TXDUMMY) {
dev_err(&bd->dev, "get brightness timeout\n");
jornada_ssp_end();
return -ETIMEDOUT;
}
/* exchange txdummy for value */
ret = jornada_ssp_byte(TXDUMMY);
jornada_ssp_end();
return BL_MAX_BRIGHT - ret;
}
static int jornada_bl_update_status(struct backlight_device *bd)
{
int ret = 0;
jornada_ssp_start();
/* If backlight is off then really turn it off */
if (backlight_is_blank(bd)) {
ret = jornada_ssp_byte(BRIGHTNESSOFF);
if (ret != TXDUMMY) {
dev_info(&bd->dev, "brightness off timeout\n");
/* turn off backlight */
PPSR &= ~PPC_LDD1;
PPDR |= PPC_LDD1;
ret = -ETIMEDOUT;
}
} else /* turn on backlight */
PPSR |= PPC_LDD1;
/* send command to our mcu */
if (jornada_ssp_byte(SETBRIGHTNESS) != TXDUMMY) {
dev_info(&bd->dev, "failed to set brightness\n");
ret = -ETIMEDOUT;
goto out;
}
/*
* at this point we expect that the mcu has accepted
* our command and is waiting for our new value
* please note that maximum brightness is 255,
* but due to physical layout it is equal to 0, so we simply
* invert the value (MAX VALUE - NEW VALUE).
*/
if (jornada_ssp_byte(BL_MAX_BRIGHT - bd->props.brightness)
!= TXDUMMY) {
dev_err(&bd->dev, "set brightness failed\n");
ret = -ETIMEDOUT;
}
/*
* If infact we get an TXDUMMY as output we are happy and dont
* make any further comments about it
*/
out:
jornada_ssp_end();
return ret;
}
static const struct backlight_ops jornada_bl_ops = {
.get_brightness = jornada_bl_get_brightness,
.update_status = jornada_bl_update_status,
.options = BL_CORE_SUSPENDRESUME,
};
static int jornada_bl_probe(struct platform_device *pdev)
{
struct backlight_properties props;
int ret;
struct backlight_device *bd;
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = BL_MAX_BRIGHT;
bd = devm_backlight_device_register(&pdev->dev, S1D_DEVICENAME,
&pdev->dev, NULL, &jornada_bl_ops,
&props);
if (IS_ERR(bd)) {
ret = PTR_ERR(bd);
dev_err(&pdev->dev, "failed to register device, err=%x\n", ret);
return ret;
}
bd->props.power = FB_BLANK_UNBLANK;
bd->props.brightness = BL_DEF_BRIGHT;
/*
* note. make sure max brightness is set otherwise
* you will get seemingly non-related errors when
* trying to change brightness
*/
jornada_bl_update_status(bd);
platform_set_drvdata(pdev, bd);
dev_info(&pdev->dev, "HP Jornada 700 series backlight driver\n");
return 0;
}
static struct platform_driver jornada_bl_driver = {
.probe = jornada_bl_probe,
.driver = {
.name = "jornada_bl",
},
};
module_platform_driver(jornada_bl_driver);
MODULE_AUTHOR("Kristoffer Ericson <kristoffer.ericson>");
MODULE_DESCRIPTION("HP Jornada 710/720/728 Backlight driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/backlight/jornada720_bl.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Backlight Driver for Intel-based Apples
*
* Copyright (c) Red Hat <[email protected]>
* Based on code from Pommed:
* Copyright (C) 2006 Nicolas Boichat <nicolas @boichat.ch>
* Copyright (C) 2006 Felipe Alfaro Solana <felipe_alfaro @linuxmail.org>
* Copyright (C) 2007 Julien BLACHE <[email protected]>
*
* This driver triggers SMIs which cause the firmware to change the
* backlight brightness. This is icky in many ways, but it's impractical to
* get at the firmware code in order to figure out what it's actually doing.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/backlight.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/atomic.h>
#include <acpi/video.h>
static struct backlight_device *apple_backlight_device;
struct hw_data {
/* I/O resource to allocate. */
unsigned long iostart;
unsigned long iolen;
/* Backlight operations structure. */
const struct backlight_ops backlight_ops;
void (*set_brightness)(int);
};
static const struct hw_data *hw_data;
/* Module parameters. */
static int debug;
module_param_named(debug, debug, int, 0644);
MODULE_PARM_DESC(debug, "Set to one to enable debugging messages.");
/*
* Implementation for machines with Intel chipset.
*/
static void intel_chipset_set_brightness(int intensity)
{
outb(0x04 | (intensity << 4), 0xb3);
outb(0xbf, 0xb2);
}
static int intel_chipset_send_intensity(struct backlight_device *bd)
{
int intensity = bd->props.brightness;
if (debug)
pr_debug("setting brightness to %d\n", intensity);
intel_chipset_set_brightness(intensity);
return 0;
}
static int intel_chipset_get_intensity(struct backlight_device *bd)
{
int intensity;
outb(0x03, 0xb3);
outb(0xbf, 0xb2);
intensity = inb(0xb3) >> 4;
if (debug)
pr_debug("read brightness of %d\n", intensity);
return intensity;
}
static const struct hw_data intel_chipset_data = {
.iostart = 0xb2,
.iolen = 2,
.backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.get_brightness = intel_chipset_get_intensity,
.update_status = intel_chipset_send_intensity,
},
.set_brightness = intel_chipset_set_brightness,
};
/*
* Implementation for machines with Nvidia chipset.
*/
static void nvidia_chipset_set_brightness(int intensity)
{
outb(0x04 | (intensity << 4), 0x52f);
outb(0xbf, 0x52e);
}
static int nvidia_chipset_send_intensity(struct backlight_device *bd)
{
int intensity = bd->props.brightness;
if (debug)
pr_debug("setting brightness to %d\n", intensity);
nvidia_chipset_set_brightness(intensity);
return 0;
}
static int nvidia_chipset_get_intensity(struct backlight_device *bd)
{
int intensity;
outb(0x03, 0x52f);
outb(0xbf, 0x52e);
intensity = inb(0x52f) >> 4;
if (debug)
pr_debug("read brightness of %d\n", intensity);
return intensity;
}
static const struct hw_data nvidia_chipset_data = {
.iostart = 0x52e,
.iolen = 2,
.backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.get_brightness = nvidia_chipset_get_intensity,
.update_status = nvidia_chipset_send_intensity
},
.set_brightness = nvidia_chipset_set_brightness,
};
static int apple_bl_add(struct acpi_device *dev)
{
struct backlight_properties props;
struct pci_dev *host;
int intensity;
host = pci_get_domain_bus_and_slot(0, 0, 0);
if (!host) {
pr_err("unable to find PCI host\n");
return -ENODEV;
}
if (host->vendor == PCI_VENDOR_ID_INTEL)
hw_data = &intel_chipset_data;
else if (host->vendor == PCI_VENDOR_ID_NVIDIA)
hw_data = &nvidia_chipset_data;
pci_dev_put(host);
if (!hw_data) {
pr_err("unknown hardware\n");
return -ENODEV;
}
/* Check that the hardware responds - this may not work under EFI */
intensity = hw_data->backlight_ops.get_brightness(NULL);
if (!intensity) {
hw_data->set_brightness(1);
if (!hw_data->backlight_ops.get_brightness(NULL))
return -ENODEV;
hw_data->set_brightness(0);
}
if (!request_region(hw_data->iostart, hw_data->iolen,
"Apple backlight"))
return -ENXIO;
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_PLATFORM;
props.max_brightness = 15;
apple_backlight_device = backlight_device_register("apple_backlight",
NULL, NULL, &hw_data->backlight_ops, &props);
if (IS_ERR(apple_backlight_device)) {
release_region(hw_data->iostart, hw_data->iolen);
return PTR_ERR(apple_backlight_device);
}
apple_backlight_device->props.brightness =
hw_data->backlight_ops.get_brightness(apple_backlight_device);
backlight_update_status(apple_backlight_device);
return 0;
}
static void apple_bl_remove(struct acpi_device *dev)
{
backlight_device_unregister(apple_backlight_device);
release_region(hw_data->iostart, hw_data->iolen);
hw_data = NULL;
}
static const struct acpi_device_id apple_bl_ids[] = {
{"APP0002", 0},
{"", 0},
};
static struct acpi_driver apple_bl_driver = {
.name = "Apple backlight",
.ids = apple_bl_ids,
.ops = {
.add = apple_bl_add,
.remove = apple_bl_remove,
},
};
static int __init apple_bl_init(void)
{
/*
* Use ACPI video detection code to see if this driver should register
* or if another driver, e.g. the apple-gmux driver should be used.
*/
if (acpi_video_get_backlight_type() != acpi_backlight_vendor)
return -ENODEV;
return acpi_bus_register_driver(&apple_bl_driver);
}
static void __exit apple_bl_exit(void)
{
acpi_bus_unregister_driver(&apple_bl_driver);
}
module_init(apple_bl_init);
module_exit(apple_bl_exit);
MODULE_AUTHOR("Matthew Garrett <[email protected]>");
MODULE_DESCRIPTION("Apple Backlight Driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(acpi, apple_bl_ids);
MODULE_ALIAS("mbp_nvidia_bl");
| linux-master | drivers/video/backlight/apple_bl.c |
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015, Sony Mobile Communications, AB.
*/
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/ktime.h>
#include <linux/kernel.h>
#include <linux/backlight.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
/* From DT binding */
#define WLED_MAX_STRINGS 4
#define MOD_A 0
#define MOD_B 1
#define WLED_DEFAULT_BRIGHTNESS 2048
#define WLED_SOFT_START_DLY_US 10000
#define WLED3_SINK_REG_BRIGHT_MAX 0xFFF
#define WLED5_SINK_REG_BRIGHT_MAX_12B 0xFFF
#define WLED5_SINK_REG_BRIGHT_MAX_15B 0x7FFF
/* WLED3/WLED4 control registers */
#define WLED3_CTRL_REG_FAULT_STATUS 0x08
#define WLED3_CTRL_REG_ILIM_FAULT_BIT BIT(0)
#define WLED3_CTRL_REG_OVP_FAULT_BIT BIT(1)
#define WLED4_CTRL_REG_SC_FAULT_BIT BIT(2)
#define WLED5_CTRL_REG_OVP_PRE_ALARM_BIT BIT(4)
#define WLED3_CTRL_REG_INT_RT_STS 0x10
#define WLED3_CTRL_REG_OVP_FAULT_STATUS BIT(1)
#define WLED3_CTRL_REG_MOD_EN 0x46
#define WLED3_CTRL_REG_MOD_EN_MASK BIT(7)
#define WLED3_CTRL_REG_MOD_EN_SHIFT 7
#define WLED3_CTRL_REG_FEEDBACK_CONTROL 0x48
#define WLED3_CTRL_REG_FREQ 0x4c
#define WLED3_CTRL_REG_FREQ_MASK GENMASK(3, 0)
#define WLED3_CTRL_REG_OVP 0x4d
#define WLED3_CTRL_REG_OVP_MASK GENMASK(1, 0)
#define WLED5_CTRL_REG_OVP_MASK GENMASK(3, 0)
#define WLED3_CTRL_REG_ILIMIT 0x4e
#define WLED3_CTRL_REG_ILIMIT_MASK GENMASK(2, 0)
/* WLED3/WLED4 sink registers */
#define WLED3_SINK_REG_SYNC 0x47
#define WLED3_SINK_REG_SYNC_CLEAR 0x00
#define WLED3_SINK_REG_CURR_SINK 0x4f
#define WLED3_SINK_REG_CURR_SINK_MASK GENMASK(7, 5)
#define WLED3_SINK_REG_CURR_SINK_SHFT 5
/* WLED3 specific per-'string' registers below */
#define WLED3_SINK_REG_BRIGHT(n) (0x40 + n)
#define WLED3_SINK_REG_STR_MOD_EN(n) (0x60 + (n * 0x10))
#define WLED3_SINK_REG_STR_MOD_MASK BIT(7)
#define WLED3_SINK_REG_STR_FULL_SCALE_CURR(n) (0x62 + (n * 0x10))
#define WLED3_SINK_REG_STR_FULL_SCALE_CURR_MASK GENMASK(4, 0)
#define WLED3_SINK_REG_STR_MOD_SRC(n) (0x63 + (n * 0x10))
#define WLED3_SINK_REG_STR_MOD_SRC_MASK BIT(0)
#define WLED3_SINK_REG_STR_MOD_SRC_INT 0x00
#define WLED3_SINK_REG_STR_MOD_SRC_EXT 0x01
#define WLED3_SINK_REG_STR_CABC(n) (0x66 + (n * 0x10))
#define WLED3_SINK_REG_STR_CABC_MASK BIT(7)
/* WLED4 specific control registers */
#define WLED4_CTRL_REG_SHORT_PROTECT 0x5e
#define WLED4_CTRL_REG_SHORT_EN_MASK BIT(7)
#define WLED4_CTRL_REG_SEC_ACCESS 0xd0
#define WLED4_CTRL_REG_SEC_UNLOCK 0xa5
#define WLED4_CTRL_REG_TEST1 0xe2
#define WLED4_CTRL_REG_TEST1_EXT_FET_DTEST2 0x09
/* WLED4 specific sink registers */
#define WLED4_SINK_REG_CURR_SINK 0x46
#define WLED4_SINK_REG_CURR_SINK_MASK GENMASK(7, 4)
#define WLED4_SINK_REG_CURR_SINK_SHFT 4
/* WLED4 specific per-'string' registers below */
#define WLED4_SINK_REG_STR_MOD_EN(n) (0x50 + (n * 0x10))
#define WLED4_SINK_REG_STR_MOD_MASK BIT(7)
#define WLED4_SINK_REG_STR_FULL_SCALE_CURR(n) (0x52 + (n * 0x10))
#define WLED4_SINK_REG_STR_FULL_SCALE_CURR_MASK GENMASK(3, 0)
#define WLED4_SINK_REG_STR_MOD_SRC(n) (0x53 + (n * 0x10))
#define WLED4_SINK_REG_STR_MOD_SRC_MASK BIT(0)
#define WLED4_SINK_REG_STR_MOD_SRC_INT 0x00
#define WLED4_SINK_REG_STR_MOD_SRC_EXT 0x01
#define WLED4_SINK_REG_STR_CABC(n) (0x56 + (n * 0x10))
#define WLED4_SINK_REG_STR_CABC_MASK BIT(7)
#define WLED4_SINK_REG_BRIGHT(n) (0x57 + (n * 0x10))
/* WLED5 specific control registers */
#define WLED5_CTRL_REG_OVP_INT_CTL 0x5f
#define WLED5_CTRL_REG_OVP_INT_TIMER_MASK GENMASK(2, 0)
/* WLED5 specific sink registers */
#define WLED5_SINK_REG_MOD_A_EN 0x50
#define WLED5_SINK_REG_MOD_B_EN 0x60
#define WLED5_SINK_REG_MOD_EN_MASK BIT(7)
#define WLED5_SINK_REG_MOD_A_SRC_SEL 0x51
#define WLED5_SINK_REG_MOD_B_SRC_SEL 0x61
#define WLED5_SINK_REG_MOD_SRC_SEL_HIGH 0
#define WLED5_SINK_REG_MOD_SRC_SEL_EXT 0x03
#define WLED5_SINK_REG_MOD_SRC_SEL_MASK GENMASK(1, 0)
#define WLED5_SINK_REG_MOD_A_BRIGHTNESS_WIDTH_SEL 0x52
#define WLED5_SINK_REG_MOD_B_BRIGHTNESS_WIDTH_SEL 0x62
#define WLED5_SINK_REG_BRIGHTNESS_WIDTH_12B 0
#define WLED5_SINK_REG_BRIGHTNESS_WIDTH_15B 1
#define WLED5_SINK_REG_MOD_A_BRIGHTNESS_LSB 0x53
#define WLED5_SINK_REG_MOD_A_BRIGHTNESS_MSB 0x54
#define WLED5_SINK_REG_MOD_B_BRIGHTNESS_LSB 0x63
#define WLED5_SINK_REG_MOD_B_BRIGHTNESS_MSB 0x64
#define WLED5_SINK_REG_MOD_SYNC_BIT 0x65
#define WLED5_SINK_REG_SYNC_MOD_A_BIT BIT(0)
#define WLED5_SINK_REG_SYNC_MOD_B_BIT BIT(1)
#define WLED5_SINK_REG_SYNC_MASK GENMASK(1, 0)
/* WLED5 specific per-'string' registers below */
#define WLED5_SINK_REG_STR_FULL_SCALE_CURR(n) (0x72 + (n * 0x10))
#define WLED5_SINK_REG_STR_SRC_SEL(n) (0x73 + (n * 0x10))
#define WLED5_SINK_REG_SRC_SEL_MOD_A 0
#define WLED5_SINK_REG_SRC_SEL_MOD_B 1
#define WLED5_SINK_REG_SRC_SEL_MASK GENMASK(1, 0)
struct wled_var_cfg {
const u32 *values;
u32 (*fn)(u32);
int size;
};
struct wled_u32_opts {
const char *name;
u32 *val_ptr;
const struct wled_var_cfg *cfg;
};
struct wled_bool_opts {
const char *name;
bool *val_ptr;
};
struct wled_config {
u32 boost_i_limit;
u32 ovp;
u32 switch_freq;
u32 num_strings;
u32 string_i_limit;
u32 enabled_strings[WLED_MAX_STRINGS];
u32 mod_sel;
u32 cabc_sel;
bool cs_out_en;
bool ext_gen;
bool cabc;
bool external_pfet;
bool auto_detection_enabled;
};
struct wled {
const char *name;
struct device *dev;
struct regmap *regmap;
struct mutex lock; /* Lock to avoid race from thread irq handler */
ktime_t last_short_event;
ktime_t start_ovp_fault_time;
u16 ctrl_addr;
u16 sink_addr;
u16 max_string_count;
u16 auto_detection_ovp_count;
u32 brightness;
u32 max_brightness;
u32 short_count;
u32 auto_detect_count;
u32 version;
bool disabled_by_short;
bool has_short_detect;
bool cabc_disabled;
int short_irq;
int ovp_irq;
struct wled_config cfg;
struct delayed_work ovp_work;
/* Configures the brightness. Applicable for wled3, wled4 and wled5 */
int (*wled_set_brightness)(struct wled *wled, u16 brightness);
/* Configures the cabc register. Applicable for wled4 and wled5 */
int (*wled_cabc_config)(struct wled *wled, bool enable);
/*
* Toggles the sync bit for the brightness update to take place.
* Applicable for WLED3, WLED4 and WLED5.
*/
int (*wled_sync_toggle)(struct wled *wled);
/*
* Time to wait before checking the OVP status after wled module enable.
* Applicable for WLED4 and WLED5.
*/
int (*wled_ovp_delay)(struct wled *wled);
/*
* Determines if the auto string detection is required.
* Applicable for WLED4 and WLED5
*/
bool (*wled_auto_detection_required)(struct wled *wled);
};
static int wled3_set_brightness(struct wled *wled, u16 brightness)
{
int rc, i;
__le16 v;
v = cpu_to_le16(brightness & WLED3_SINK_REG_BRIGHT_MAX);
for (i = 0; i < wled->cfg.num_strings; ++i) {
rc = regmap_bulk_write(wled->regmap, wled->ctrl_addr +
WLED3_SINK_REG_BRIGHT(wled->cfg.enabled_strings[i]),
&v, sizeof(v));
if (rc < 0)
return rc;
}
return 0;
}
static int wled4_set_brightness(struct wled *wled, u16 brightness)
{
int rc, i;
u16 low_limit = wled->max_brightness * 4 / 1000;
__le16 v;
/* WLED4's lower limit of operation is 0.4% */
if (brightness > 0 && brightness < low_limit)
brightness = low_limit;
v = cpu_to_le16(brightness & WLED3_SINK_REG_BRIGHT_MAX);
for (i = 0; i < wled->cfg.num_strings; ++i) {
rc = regmap_bulk_write(wled->regmap, wled->sink_addr +
WLED4_SINK_REG_BRIGHT(wled->cfg.enabled_strings[i]),
&v, sizeof(v));
if (rc < 0)
return rc;
}
return 0;
}
static int wled5_set_brightness(struct wled *wled, u16 brightness)
{
int rc, offset;
u16 low_limit = wled->max_brightness * 1 / 1000;
__le16 v;
/* WLED5's lower limit is 0.1% */
if (brightness < low_limit)
brightness = low_limit;
v = cpu_to_le16(brightness & WLED5_SINK_REG_BRIGHT_MAX_15B);
offset = (wled->cfg.mod_sel == MOD_A) ?
WLED5_SINK_REG_MOD_A_BRIGHTNESS_LSB :
WLED5_SINK_REG_MOD_B_BRIGHTNESS_LSB;
rc = regmap_bulk_write(wled->regmap, wled->sink_addr + offset,
&v, sizeof(v));
return rc;
}
static void wled_ovp_work(struct work_struct *work)
{
struct wled *wled = container_of(work,
struct wled, ovp_work.work);
enable_irq(wled->ovp_irq);
}
static int wled_module_enable(struct wled *wled, int val)
{
int rc;
if (wled->disabled_by_short)
return -ENXIO;
rc = regmap_update_bits(wled->regmap, wled->ctrl_addr +
WLED3_CTRL_REG_MOD_EN,
WLED3_CTRL_REG_MOD_EN_MASK,
val << WLED3_CTRL_REG_MOD_EN_SHIFT);
if (rc < 0)
return rc;
if (wled->ovp_irq > 0) {
if (val) {
/*
* The hardware generates a storm of spurious OVP
* interrupts during soft start operations. So defer
* enabling the IRQ for 10ms to ensure that the
* soft start is complete.
*/
schedule_delayed_work(&wled->ovp_work, HZ / 100);
} else {
if (!cancel_delayed_work_sync(&wled->ovp_work))
disable_irq(wled->ovp_irq);
}
}
return 0;
}
static int wled3_sync_toggle(struct wled *wled)
{
int rc;
unsigned int mask = GENMASK(wled->max_string_count - 1, 0);
rc = regmap_update_bits(wled->regmap,
wled->sink_addr + WLED3_SINK_REG_SYNC,
mask, WLED3_SINK_REG_SYNC_CLEAR);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->sink_addr + WLED3_SINK_REG_SYNC,
mask, mask);
return rc;
}
static int wled5_mod_sync_toggle(struct wled *wled)
{
int rc;
u8 val;
rc = regmap_update_bits(wled->regmap,
wled->sink_addr + WLED5_SINK_REG_MOD_SYNC_BIT,
WLED5_SINK_REG_SYNC_MASK, 0);
if (rc < 0)
return rc;
val = (wled->cfg.mod_sel == MOD_A) ? WLED5_SINK_REG_SYNC_MOD_A_BIT :
WLED5_SINK_REG_SYNC_MOD_B_BIT;
return regmap_update_bits(wled->regmap,
wled->sink_addr + WLED5_SINK_REG_MOD_SYNC_BIT,
WLED5_SINK_REG_SYNC_MASK, val);
}
static int wled_ovp_fault_status(struct wled *wled, bool *fault_set)
{
int rc;
u32 int_rt_sts, fault_sts;
*fault_set = false;
rc = regmap_read(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_INT_RT_STS,
&int_rt_sts);
if (rc < 0) {
dev_err(wled->dev, "Failed to read INT_RT_STS rc=%d\n", rc);
return rc;
}
rc = regmap_read(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_FAULT_STATUS,
&fault_sts);
if (rc < 0) {
dev_err(wled->dev, "Failed to read FAULT_STATUS rc=%d\n", rc);
return rc;
}
if (int_rt_sts & WLED3_CTRL_REG_OVP_FAULT_STATUS)
*fault_set = true;
if (wled->version == 4 && (fault_sts & WLED3_CTRL_REG_OVP_FAULT_BIT))
*fault_set = true;
if (wled->version == 5 && (fault_sts & (WLED3_CTRL_REG_OVP_FAULT_BIT |
WLED5_CTRL_REG_OVP_PRE_ALARM_BIT)))
*fault_set = true;
if (*fault_set)
dev_dbg(wled->dev, "WLED OVP fault detected, int_rt_sts=0x%x fault_sts=0x%x\n",
int_rt_sts, fault_sts);
return rc;
}
static int wled4_ovp_delay(struct wled *wled)
{
return WLED_SOFT_START_DLY_US;
}
static int wled5_ovp_delay(struct wled *wled)
{
int rc, delay_us;
u32 val;
u8 ovp_timer_ms[8] = {1, 2, 4, 8, 12, 16, 20, 24};
/* For WLED5, get the delay based on OVP timer */
rc = regmap_read(wled->regmap, wled->ctrl_addr +
WLED5_CTRL_REG_OVP_INT_CTL, &val);
if (rc < 0)
delay_us =
ovp_timer_ms[val & WLED5_CTRL_REG_OVP_INT_TIMER_MASK] * 1000;
else
delay_us = 2 * WLED_SOFT_START_DLY_US;
dev_dbg(wled->dev, "delay_time_us: %d\n", delay_us);
return delay_us;
}
static int wled_update_status(struct backlight_device *bl)
{
struct wled *wled = bl_get_data(bl);
u16 brightness = backlight_get_brightness(bl);
int rc = 0;
mutex_lock(&wled->lock);
if (brightness) {
rc = wled->wled_set_brightness(wled, brightness);
if (rc < 0) {
dev_err(wled->dev, "wled failed to set brightness rc:%d\n",
rc);
goto unlock_mutex;
}
if (wled->version < 5) {
rc = wled->wled_sync_toggle(wled);
if (rc < 0) {
dev_err(wled->dev, "wled sync failed rc:%d\n", rc);
goto unlock_mutex;
}
} else {
/*
* For WLED5 toggling the MOD_SYNC_BIT updates the
* brightness
*/
rc = wled5_mod_sync_toggle(wled);
if (rc < 0) {
dev_err(wled->dev, "wled mod sync failed rc:%d\n",
rc);
goto unlock_mutex;
}
}
}
if (!!brightness != !!wled->brightness) {
rc = wled_module_enable(wled, !!brightness);
if (rc < 0) {
dev_err(wled->dev, "wled enable failed rc:%d\n", rc);
goto unlock_mutex;
}
}
wled->brightness = brightness;
unlock_mutex:
mutex_unlock(&wled->lock);
return rc;
}
static int wled4_cabc_config(struct wled *wled, bool enable)
{
int i, j, rc;
u8 val;
for (i = 0; i < wled->cfg.num_strings; i++) {
j = wled->cfg.enabled_strings[i];
val = enable ? WLED4_SINK_REG_STR_CABC_MASK : 0;
rc = regmap_update_bits(wled->regmap, wled->sink_addr +
WLED4_SINK_REG_STR_CABC(j),
WLED4_SINK_REG_STR_CABC_MASK, val);
if (rc < 0)
return rc;
}
return 0;
}
static int wled5_cabc_config(struct wled *wled, bool enable)
{
int rc, offset;
u8 reg;
if (wled->cabc_disabled)
return 0;
reg = enable ? wled->cfg.cabc_sel : 0;
offset = (wled->cfg.mod_sel == MOD_A) ? WLED5_SINK_REG_MOD_A_SRC_SEL :
WLED5_SINK_REG_MOD_B_SRC_SEL;
rc = regmap_update_bits(wled->regmap, wled->sink_addr + offset,
WLED5_SINK_REG_MOD_SRC_SEL_MASK, reg);
if (rc < 0) {
pr_err("Error in configuring CABC rc=%d\n", rc);
return rc;
}
if (!wled->cfg.cabc_sel)
wled->cabc_disabled = true;
return 0;
}
#define WLED_SHORT_DLY_MS 20
#define WLED_SHORT_CNT_MAX 5
#define WLED_SHORT_RESET_CNT_DLY_US USEC_PER_SEC
static irqreturn_t wled_short_irq_handler(int irq, void *_wled)
{
struct wled *wled = _wled;
int rc;
s64 elapsed_time;
wled->short_count++;
mutex_lock(&wled->lock);
rc = wled_module_enable(wled, false);
if (rc < 0) {
dev_err(wled->dev, "wled disable failed rc:%d\n", rc);
goto unlock_mutex;
}
elapsed_time = ktime_us_delta(ktime_get(),
wled->last_short_event);
if (elapsed_time > WLED_SHORT_RESET_CNT_DLY_US)
wled->short_count = 1;
if (wled->short_count > WLED_SHORT_CNT_MAX) {
dev_err(wled->dev, "Short triggered %d times, disabling WLED forever!\n",
wled->short_count);
wled->disabled_by_short = true;
goto unlock_mutex;
}
wled->last_short_event = ktime_get();
msleep(WLED_SHORT_DLY_MS);
rc = wled_module_enable(wled, true);
if (rc < 0)
dev_err(wled->dev, "wled enable failed rc:%d\n", rc);
unlock_mutex:
mutex_unlock(&wled->lock);
return IRQ_HANDLED;
}
#define AUTO_DETECT_BRIGHTNESS 200
static void wled_auto_string_detection(struct wled *wled)
{
int rc = 0, i, j, delay_time_us;
u32 sink_config = 0;
u8 sink_test = 0, sink_valid = 0, val;
bool fault_set;
/* Read configured sink configuration */
rc = regmap_read(wled->regmap, wled->sink_addr +
WLED4_SINK_REG_CURR_SINK, &sink_config);
if (rc < 0) {
dev_err(wled->dev, "Failed to read SINK configuration rc=%d\n",
rc);
goto failed_detect;
}
/* Disable the module before starting detection */
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_MOD_EN,
WLED3_CTRL_REG_MOD_EN_MASK, 0);
if (rc < 0) {
dev_err(wled->dev, "Failed to disable WLED module rc=%d\n", rc);
goto failed_detect;
}
/* Set low brightness across all sinks */
rc = wled4_set_brightness(wled, AUTO_DETECT_BRIGHTNESS);
if (rc < 0) {
dev_err(wled->dev, "Failed to set brightness for auto detection rc=%d\n",
rc);
goto failed_detect;
}
if (wled->cfg.cabc) {
rc = wled->wled_cabc_config(wled, false);
if (rc < 0)
goto failed_detect;
}
/* Disable all sinks */
rc = regmap_write(wled->regmap,
wled->sink_addr + WLED4_SINK_REG_CURR_SINK, 0);
if (rc < 0) {
dev_err(wled->dev, "Failed to disable all sinks rc=%d\n", rc);
goto failed_detect;
}
/* Iterate through the strings one by one */
for (i = 0; i < wled->cfg.num_strings; i++) {
j = wled->cfg.enabled_strings[i];
sink_test = BIT((WLED4_SINK_REG_CURR_SINK_SHFT + j));
/* Enable feedback control */
rc = regmap_write(wled->regmap, wled->ctrl_addr +
WLED3_CTRL_REG_FEEDBACK_CONTROL, j + 1);
if (rc < 0) {
dev_err(wled->dev, "Failed to enable feedback for SINK %d rc = %d\n",
j + 1, rc);
goto failed_detect;
}
/* Enable the sink */
rc = regmap_write(wled->regmap, wled->sink_addr +
WLED4_SINK_REG_CURR_SINK, sink_test);
if (rc < 0) {
dev_err(wled->dev, "Failed to configure SINK %d rc=%d\n",
j + 1, rc);
goto failed_detect;
}
/* Enable the module */
rc = regmap_update_bits(wled->regmap, wled->ctrl_addr +
WLED3_CTRL_REG_MOD_EN,
WLED3_CTRL_REG_MOD_EN_MASK,
WLED3_CTRL_REG_MOD_EN_MASK);
if (rc < 0) {
dev_err(wled->dev, "Failed to enable WLED module rc=%d\n",
rc);
goto failed_detect;
}
delay_time_us = wled->wled_ovp_delay(wled);
usleep_range(delay_time_us, delay_time_us + 1000);
rc = wled_ovp_fault_status(wled, &fault_set);
if (rc < 0) {
dev_err(wled->dev, "Error in getting OVP fault_sts, rc=%d\n",
rc);
goto failed_detect;
}
if (fault_set)
dev_dbg(wled->dev, "WLED OVP fault detected with SINK %d\n",
j + 1);
else
sink_valid |= sink_test;
/* Disable the module */
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_MOD_EN,
WLED3_CTRL_REG_MOD_EN_MASK, 0);
if (rc < 0) {
dev_err(wled->dev, "Failed to disable WLED module rc=%d\n",
rc);
goto failed_detect;
}
}
if (!sink_valid) {
dev_err(wled->dev, "No valid WLED sinks found\n");
wled->disabled_by_short = true;
goto failed_detect;
}
if (sink_valid != sink_config) {
dev_warn(wled->dev, "%x is not a valid sink configuration - using %x instead\n",
sink_config, sink_valid);
sink_config = sink_valid;
}
/* Write the new sink configuration */
rc = regmap_write(wled->regmap,
wled->sink_addr + WLED4_SINK_REG_CURR_SINK,
sink_config);
if (rc < 0) {
dev_err(wled->dev, "Failed to reconfigure the default sink rc=%d\n",
rc);
goto failed_detect;
}
/* Enable valid sinks */
if (wled->version == 4) {
for (i = 0; i < wled->cfg.num_strings; i++) {
j = wled->cfg.enabled_strings[i];
if (sink_config &
BIT(WLED4_SINK_REG_CURR_SINK_SHFT + j))
val = WLED4_SINK_REG_STR_MOD_MASK;
else
/* Disable modulator_en for unused sink */
val = 0;
rc = regmap_write(wled->regmap, wled->sink_addr +
WLED4_SINK_REG_STR_MOD_EN(j), val);
if (rc < 0) {
dev_err(wled->dev, "Failed to configure MODULATOR_EN rc=%d\n",
rc);
goto failed_detect;
}
}
}
/* Enable CABC */
rc = wled->wled_cabc_config(wled, true);
if (rc < 0)
goto failed_detect;
/* Restore the feedback setting */
rc = regmap_write(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_FEEDBACK_CONTROL, 0);
if (rc < 0) {
dev_err(wled->dev, "Failed to restore feedback setting rc=%d\n",
rc);
goto failed_detect;
}
/* Restore brightness */
rc = wled4_set_brightness(wled, wled->brightness);
if (rc < 0) {
dev_err(wled->dev, "Failed to set brightness after auto detection rc=%d\n",
rc);
goto failed_detect;
}
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_MOD_EN,
WLED3_CTRL_REG_MOD_EN_MASK,
WLED3_CTRL_REG_MOD_EN_MASK);
if (rc < 0) {
dev_err(wled->dev, "Failed to enable WLED module rc=%d\n", rc);
goto failed_detect;
}
failed_detect:
return;
}
#define WLED_AUTO_DETECT_OVP_COUNT 5
#define WLED_AUTO_DETECT_CNT_DLY_US USEC_PER_SEC
static bool wled4_auto_detection_required(struct wled *wled)
{
s64 elapsed_time_us;
if (!wled->cfg.auto_detection_enabled)
return false;
/*
* Check if the OVP fault was an occasional one
* or if it's firing continuously, the latter qualifies
* for an auto-detection check.
*/
if (!wled->auto_detection_ovp_count) {
wled->start_ovp_fault_time = ktime_get();
wled->auto_detection_ovp_count++;
} else {
elapsed_time_us = ktime_us_delta(ktime_get(),
wled->start_ovp_fault_time);
if (elapsed_time_us > WLED_AUTO_DETECT_CNT_DLY_US)
wled->auto_detection_ovp_count = 0;
else
wled->auto_detection_ovp_count++;
if (wled->auto_detection_ovp_count >=
WLED_AUTO_DETECT_OVP_COUNT) {
wled->auto_detection_ovp_count = 0;
return true;
}
}
return false;
}
static bool wled5_auto_detection_required(struct wled *wled)
{
if (!wled->cfg.auto_detection_enabled)
return false;
/*
* Unlike WLED4, WLED5 has OVP fault density interrupt configuration
* i.e. to count the number of OVP alarms for a certain duration before
* triggering OVP fault interrupt. By default, number of OVP fault
* events counted before an interrupt is fired is 32 and the time
* interval is 12 ms. If we see one OVP fault interrupt, then that
* should qualify for a real OVP fault condition to run auto detection
* algorithm.
*/
return true;
}
static int wled_auto_detection_at_init(struct wled *wled)
{
int rc;
bool fault_set;
if (!wled->cfg.auto_detection_enabled)
return 0;
rc = wled_ovp_fault_status(wled, &fault_set);
if (rc < 0) {
dev_err(wled->dev, "Error in getting OVP fault_sts, rc=%d\n",
rc);
return rc;
}
if (fault_set) {
mutex_lock(&wled->lock);
wled_auto_string_detection(wled);
mutex_unlock(&wled->lock);
}
return rc;
}
static irqreturn_t wled_ovp_irq_handler(int irq, void *_wled)
{
struct wled *wled = _wled;
int rc;
u32 int_sts, fault_sts;
rc = regmap_read(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_INT_RT_STS, &int_sts);
if (rc < 0) {
dev_err(wled->dev, "Error in reading WLED3_INT_RT_STS rc=%d\n",
rc);
return IRQ_HANDLED;
}
rc = regmap_read(wled->regmap, wled->ctrl_addr +
WLED3_CTRL_REG_FAULT_STATUS, &fault_sts);
if (rc < 0) {
dev_err(wled->dev, "Error in reading WLED_FAULT_STATUS rc=%d\n",
rc);
return IRQ_HANDLED;
}
if (fault_sts & (WLED3_CTRL_REG_OVP_FAULT_BIT |
WLED3_CTRL_REG_ILIM_FAULT_BIT))
dev_dbg(wled->dev, "WLED OVP fault detected, int_sts=%x fault_sts= %x\n",
int_sts, fault_sts);
if (fault_sts & WLED3_CTRL_REG_OVP_FAULT_BIT) {
if (wled->wled_auto_detection_required(wled)) {
mutex_lock(&wled->lock);
wled_auto_string_detection(wled);
mutex_unlock(&wled->lock);
}
}
return IRQ_HANDLED;
}
static int wled3_setup(struct wled *wled)
{
u16 addr;
u8 sink_en = 0;
int rc, i, j;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_OVP,
WLED3_CTRL_REG_OVP_MASK, wled->cfg.ovp);
if (rc)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_ILIMIT,
WLED3_CTRL_REG_ILIMIT_MASK,
wled->cfg.boost_i_limit);
if (rc)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_FREQ,
WLED3_CTRL_REG_FREQ_MASK,
wled->cfg.switch_freq);
if (rc)
return rc;
for (i = 0; i < wled->cfg.num_strings; ++i) {
j = wled->cfg.enabled_strings[i];
addr = wled->ctrl_addr + WLED3_SINK_REG_STR_MOD_EN(j);
rc = regmap_update_bits(wled->regmap, addr,
WLED3_SINK_REG_STR_MOD_MASK,
WLED3_SINK_REG_STR_MOD_MASK);
if (rc)
return rc;
if (wled->cfg.ext_gen) {
addr = wled->ctrl_addr + WLED3_SINK_REG_STR_MOD_SRC(j);
rc = regmap_update_bits(wled->regmap, addr,
WLED3_SINK_REG_STR_MOD_SRC_MASK,
WLED3_SINK_REG_STR_MOD_SRC_EXT);
if (rc)
return rc;
}
addr = wled->ctrl_addr + WLED3_SINK_REG_STR_FULL_SCALE_CURR(j);
rc = regmap_update_bits(wled->regmap, addr,
WLED3_SINK_REG_STR_FULL_SCALE_CURR_MASK,
wled->cfg.string_i_limit);
if (rc)
return rc;
addr = wled->ctrl_addr + WLED3_SINK_REG_STR_CABC(j);
rc = regmap_update_bits(wled->regmap, addr,
WLED3_SINK_REG_STR_CABC_MASK,
wled->cfg.cabc ?
WLED3_SINK_REG_STR_CABC_MASK : 0);
if (rc)
return rc;
sink_en |= BIT(j + WLED3_SINK_REG_CURR_SINK_SHFT);
}
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_SINK_REG_CURR_SINK,
WLED3_SINK_REG_CURR_SINK_MASK, sink_en);
if (rc)
return rc;
return 0;
}
static const struct wled_config wled3_config_defaults = {
.boost_i_limit = 3,
.string_i_limit = 20,
.ovp = 2,
.num_strings = 3,
.switch_freq = 5,
.cs_out_en = false,
.ext_gen = false,
.cabc = false,
.enabled_strings = {0, 1, 2},
};
static int wled4_setup(struct wled *wled)
{
int rc, temp, i, j;
u16 addr;
u8 sink_en = 0;
u32 sink_cfg;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_OVP,
WLED3_CTRL_REG_OVP_MASK, wled->cfg.ovp);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_ILIMIT,
WLED3_CTRL_REG_ILIMIT_MASK,
wled->cfg.boost_i_limit);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_FREQ,
WLED3_CTRL_REG_FREQ_MASK,
wled->cfg.switch_freq);
if (rc < 0)
return rc;
if (wled->cfg.external_pfet) {
/* Unlock the secure register access */
rc = regmap_write(wled->regmap, wled->ctrl_addr +
WLED4_CTRL_REG_SEC_ACCESS,
WLED4_CTRL_REG_SEC_UNLOCK);
if (rc < 0)
return rc;
rc = regmap_write(wled->regmap,
wled->ctrl_addr + WLED4_CTRL_REG_TEST1,
WLED4_CTRL_REG_TEST1_EXT_FET_DTEST2);
if (rc < 0)
return rc;
}
rc = regmap_read(wled->regmap, wled->sink_addr +
WLED4_SINK_REG_CURR_SINK, &sink_cfg);
if (rc < 0)
return rc;
for (i = 0; i < wled->cfg.num_strings; i++) {
j = wled->cfg.enabled_strings[i];
temp = j + WLED4_SINK_REG_CURR_SINK_SHFT;
sink_en |= 1 << temp;
}
if (sink_cfg == sink_en) {
rc = wled_auto_detection_at_init(wled);
return rc;
}
rc = regmap_update_bits(wled->regmap,
wled->sink_addr + WLED4_SINK_REG_CURR_SINK,
WLED4_SINK_REG_CURR_SINK_MASK, 0);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap, wled->ctrl_addr +
WLED3_CTRL_REG_MOD_EN,
WLED3_CTRL_REG_MOD_EN_MASK, 0);
if (rc < 0)
return rc;
/* Per sink/string configuration */
for (i = 0; i < wled->cfg.num_strings; i++) {
j = wled->cfg.enabled_strings[i];
addr = wled->sink_addr +
WLED4_SINK_REG_STR_MOD_EN(j);
rc = regmap_update_bits(wled->regmap, addr,
WLED4_SINK_REG_STR_MOD_MASK,
WLED4_SINK_REG_STR_MOD_MASK);
if (rc < 0)
return rc;
addr = wled->sink_addr +
WLED4_SINK_REG_STR_FULL_SCALE_CURR(j);
rc = regmap_update_bits(wled->regmap, addr,
WLED4_SINK_REG_STR_FULL_SCALE_CURR_MASK,
wled->cfg.string_i_limit);
if (rc < 0)
return rc;
}
rc = wled4_cabc_config(wled, wled->cfg.cabc);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap, wled->ctrl_addr +
WLED3_CTRL_REG_MOD_EN,
WLED3_CTRL_REG_MOD_EN_MASK,
WLED3_CTRL_REG_MOD_EN_MASK);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->sink_addr + WLED4_SINK_REG_CURR_SINK,
WLED4_SINK_REG_CURR_SINK_MASK, sink_en);
if (rc < 0)
return rc;
rc = wled->wled_sync_toggle(wled);
if (rc < 0) {
dev_err(wled->dev, "Failed to toggle sync reg rc:%d\n", rc);
return rc;
}
rc = wled_auto_detection_at_init(wled);
return rc;
}
static const struct wled_config wled4_config_defaults = {
.boost_i_limit = 4,
.string_i_limit = 10,
.ovp = 1,
.num_strings = 4,
.switch_freq = 11,
.cabc = false,
.external_pfet = false,
.auto_detection_enabled = false,
.enabled_strings = {0, 1, 2, 3},
};
static int wled5_setup(struct wled *wled)
{
int rc, temp, i, j, offset;
u8 sink_en = 0;
u16 addr;
u32 val;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_OVP,
WLED5_CTRL_REG_OVP_MASK, wled->cfg.ovp);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_ILIMIT,
WLED3_CTRL_REG_ILIMIT_MASK,
wled->cfg.boost_i_limit);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->ctrl_addr + WLED3_CTRL_REG_FREQ,
WLED3_CTRL_REG_FREQ_MASK,
wled->cfg.switch_freq);
if (rc < 0)
return rc;
/* Per sink/string configuration */
for (i = 0; i < wled->cfg.num_strings; ++i) {
j = wled->cfg.enabled_strings[i];
addr = wled->sink_addr +
WLED4_SINK_REG_STR_FULL_SCALE_CURR(j);
rc = regmap_update_bits(wled->regmap, addr,
WLED4_SINK_REG_STR_FULL_SCALE_CURR_MASK,
wled->cfg.string_i_limit);
if (rc < 0)
return rc;
addr = wled->sink_addr + WLED5_SINK_REG_STR_SRC_SEL(j);
rc = regmap_update_bits(wled->regmap, addr,
WLED5_SINK_REG_SRC_SEL_MASK,
wled->cfg.mod_sel == MOD_A ?
WLED5_SINK_REG_SRC_SEL_MOD_A :
WLED5_SINK_REG_SRC_SEL_MOD_B);
temp = j + WLED4_SINK_REG_CURR_SINK_SHFT;
sink_en |= 1 << temp;
}
rc = wled5_cabc_config(wled, wled->cfg.cabc_sel ? true : false);
if (rc < 0)
return rc;
/* Enable one of the modulators A or B based on mod_sel */
addr = wled->sink_addr + WLED5_SINK_REG_MOD_A_EN;
val = (wled->cfg.mod_sel == MOD_A) ? WLED5_SINK_REG_MOD_EN_MASK : 0;
rc = regmap_update_bits(wled->regmap, addr,
WLED5_SINK_REG_MOD_EN_MASK, val);
if (rc < 0)
return rc;
addr = wled->sink_addr + WLED5_SINK_REG_MOD_B_EN;
val = (wled->cfg.mod_sel == MOD_B) ? WLED5_SINK_REG_MOD_EN_MASK : 0;
rc = regmap_update_bits(wled->regmap, addr,
WLED5_SINK_REG_MOD_EN_MASK, val);
if (rc < 0)
return rc;
offset = (wled->cfg.mod_sel == MOD_A) ?
WLED5_SINK_REG_MOD_A_BRIGHTNESS_WIDTH_SEL :
WLED5_SINK_REG_MOD_B_BRIGHTNESS_WIDTH_SEL;
addr = wled->sink_addr + offset;
val = (wled->max_brightness == WLED5_SINK_REG_BRIGHT_MAX_15B) ?
WLED5_SINK_REG_BRIGHTNESS_WIDTH_15B :
WLED5_SINK_REG_BRIGHTNESS_WIDTH_12B;
rc = regmap_write(wled->regmap, addr, val);
if (rc < 0)
return rc;
rc = regmap_update_bits(wled->regmap,
wled->sink_addr + WLED4_SINK_REG_CURR_SINK,
WLED4_SINK_REG_CURR_SINK_MASK, sink_en);
if (rc < 0)
return rc;
/* This updates only FSC configuration in WLED5 */
rc = wled->wled_sync_toggle(wled);
if (rc < 0) {
pr_err("Failed to toggle sync reg rc:%d\n", rc);
return rc;
}
rc = wled_auto_detection_at_init(wled);
if (rc < 0)
return rc;
return 0;
}
static const struct wled_config wled5_config_defaults = {
.boost_i_limit = 5,
.string_i_limit = 10,
.ovp = 4,
.num_strings = 4,
.switch_freq = 11,
.mod_sel = 0,
.cabc_sel = 0,
.cabc = false,
.external_pfet = false,
.auto_detection_enabled = false,
.enabled_strings = {0, 1, 2, 3},
};
static const u32 wled3_boost_i_limit_values[] = {
105, 385, 525, 805, 980, 1260, 1400, 1680,
};
static const struct wled_var_cfg wled3_boost_i_limit_cfg = {
.values = wled3_boost_i_limit_values,
.size = ARRAY_SIZE(wled3_boost_i_limit_values),
};
static const u32 wled4_boost_i_limit_values[] = {
105, 280, 450, 620, 970, 1150, 1300, 1500,
};
static const struct wled_var_cfg wled4_boost_i_limit_cfg = {
.values = wled4_boost_i_limit_values,
.size = ARRAY_SIZE(wled4_boost_i_limit_values),
};
static inline u32 wled5_boost_i_limit_values_fn(u32 idx)
{
return 525 + (idx * 175);
}
static const struct wled_var_cfg wled5_boost_i_limit_cfg = {
.fn = wled5_boost_i_limit_values_fn,
.size = 8,
};
static const u32 wled3_ovp_values[] = {
35, 32, 29, 27,
};
static const struct wled_var_cfg wled3_ovp_cfg = {
.values = wled3_ovp_values,
.size = ARRAY_SIZE(wled3_ovp_values),
};
static const u32 wled4_ovp_values[] = {
31100, 29600, 19600, 18100,
};
static const struct wled_var_cfg wled4_ovp_cfg = {
.values = wled4_ovp_values,
.size = ARRAY_SIZE(wled4_ovp_values),
};
static inline u32 wled5_ovp_values_fn(u32 idx)
{
/*
* 0000 - 38.5 V
* 0001 - 37 V ..
* 1111 - 16 V
*/
return 38500 - (idx * 1500);
}
static const struct wled_var_cfg wled5_ovp_cfg = {
.fn = wled5_ovp_values_fn,
.size = 16,
};
static u32 wled3_switch_freq_values_fn(u32 idx)
{
return 19200 / (2 * (1 + idx));
}
static const struct wled_var_cfg wled3_switch_freq_cfg = {
.fn = wled3_switch_freq_values_fn,
.size = 16,
};
static const struct wled_var_cfg wled3_string_i_limit_cfg = {
.size = 26,
};
static const u32 wled4_string_i_limit_values[] = {
0, 2500, 5000, 7500, 10000, 12500, 15000, 17500, 20000,
22500, 25000, 27500, 30000,
};
static const struct wled_var_cfg wled4_string_i_limit_cfg = {
.values = wled4_string_i_limit_values,
.size = ARRAY_SIZE(wled4_string_i_limit_values),
};
static const struct wled_var_cfg wled5_mod_sel_cfg = {
.size = 2,
};
static const struct wled_var_cfg wled5_cabc_sel_cfg = {
.size = 4,
};
static u32 wled_values(const struct wled_var_cfg *cfg, u32 idx)
{
if (idx >= cfg->size)
return UINT_MAX;
if (cfg->fn)
return cfg->fn(idx);
if (cfg->values)
return cfg->values[idx];
return idx;
}
static int wled_configure(struct wled *wled)
{
struct wled_config *cfg = &wled->cfg;
struct device *dev = wled->dev;
const __be32 *prop_addr;
u32 size, val, c;
int rc, i, j, string_len;
const struct wled_u32_opts *u32_opts = NULL;
const struct wled_u32_opts wled3_opts[] = {
{
.name = "qcom,current-boost-limit",
.val_ptr = &cfg->boost_i_limit,
.cfg = &wled3_boost_i_limit_cfg,
},
{
.name = "qcom,current-limit",
.val_ptr = &cfg->string_i_limit,
.cfg = &wled3_string_i_limit_cfg,
},
{
.name = "qcom,ovp",
.val_ptr = &cfg->ovp,
.cfg = &wled3_ovp_cfg,
},
{
.name = "qcom,switching-freq",
.val_ptr = &cfg->switch_freq,
.cfg = &wled3_switch_freq_cfg,
},
};
const struct wled_u32_opts wled4_opts[] = {
{
.name = "qcom,current-boost-limit",
.val_ptr = &cfg->boost_i_limit,
.cfg = &wled4_boost_i_limit_cfg,
},
{
.name = "qcom,current-limit-microamp",
.val_ptr = &cfg->string_i_limit,
.cfg = &wled4_string_i_limit_cfg,
},
{
.name = "qcom,ovp-millivolt",
.val_ptr = &cfg->ovp,
.cfg = &wled4_ovp_cfg,
},
{
.name = "qcom,switching-freq",
.val_ptr = &cfg->switch_freq,
.cfg = &wled3_switch_freq_cfg,
},
};
const struct wled_u32_opts wled5_opts[] = {
{
.name = "qcom,current-boost-limit",
.val_ptr = &cfg->boost_i_limit,
.cfg = &wled5_boost_i_limit_cfg,
},
{
.name = "qcom,current-limit-microamp",
.val_ptr = &cfg->string_i_limit,
.cfg = &wled4_string_i_limit_cfg,
},
{
.name = "qcom,ovp-millivolt",
.val_ptr = &cfg->ovp,
.cfg = &wled5_ovp_cfg,
},
{
.name = "qcom,switching-freq",
.val_ptr = &cfg->switch_freq,
.cfg = &wled3_switch_freq_cfg,
},
{
.name = "qcom,modulator-sel",
.val_ptr = &cfg->mod_sel,
.cfg = &wled5_mod_sel_cfg,
},
{
.name = "qcom,cabc-sel",
.val_ptr = &cfg->cabc_sel,
.cfg = &wled5_cabc_sel_cfg,
},
};
const struct wled_bool_opts bool_opts[] = {
{ "qcom,cs-out", &cfg->cs_out_en, },
{ "qcom,ext-gen", &cfg->ext_gen, },
{ "qcom,cabc", &cfg->cabc, },
{ "qcom,external-pfet", &cfg->external_pfet, },
{ "qcom,auto-string-detection", &cfg->auto_detection_enabled, },
};
prop_addr = of_get_address(dev->of_node, 0, NULL, NULL);
if (!prop_addr) {
dev_err(wled->dev, "invalid IO resources\n");
return -EINVAL;
}
wled->ctrl_addr = be32_to_cpu(*prop_addr);
rc = of_property_read_string(dev->of_node, "label", &wled->name);
if (rc)
wled->name = devm_kasprintf(dev, GFP_KERNEL, "%pOFn", dev->of_node);
switch (wled->version) {
case 3:
u32_opts = wled3_opts;
size = ARRAY_SIZE(wled3_opts);
*cfg = wled3_config_defaults;
wled->wled_set_brightness = wled3_set_brightness;
wled->wled_sync_toggle = wled3_sync_toggle;
wled->max_string_count = 3;
wled->sink_addr = wled->ctrl_addr;
break;
case 4:
u32_opts = wled4_opts;
size = ARRAY_SIZE(wled4_opts);
*cfg = wled4_config_defaults;
wled->wled_set_brightness = wled4_set_brightness;
wled->wled_sync_toggle = wled3_sync_toggle;
wled->wled_cabc_config = wled4_cabc_config;
wled->wled_ovp_delay = wled4_ovp_delay;
wled->wled_auto_detection_required =
wled4_auto_detection_required;
wled->max_string_count = 4;
prop_addr = of_get_address(dev->of_node, 1, NULL, NULL);
if (!prop_addr) {
dev_err(wled->dev, "invalid IO resources\n");
return -EINVAL;
}
wled->sink_addr = be32_to_cpu(*prop_addr);
break;
case 5:
u32_opts = wled5_opts;
size = ARRAY_SIZE(wled5_opts);
*cfg = wled5_config_defaults;
wled->wled_set_brightness = wled5_set_brightness;
wled->wled_sync_toggle = wled3_sync_toggle;
wled->wled_cabc_config = wled5_cabc_config;
wled->wled_ovp_delay = wled5_ovp_delay;
wled->wled_auto_detection_required =
wled5_auto_detection_required;
wled->max_string_count = 4;
prop_addr = of_get_address(dev->of_node, 1, NULL, NULL);
if (!prop_addr) {
dev_err(wled->dev, "invalid IO resources\n");
return -EINVAL;
}
wled->sink_addr = be32_to_cpu(*prop_addr);
break;
default:
dev_err(wled->dev, "Invalid WLED version\n");
return -EINVAL;
}
for (i = 0; i < size; ++i) {
rc = of_property_read_u32(dev->of_node, u32_opts[i].name, &val);
if (rc == -EINVAL) {
continue;
} else if (rc) {
dev_err(dev, "error reading '%s'\n", u32_opts[i].name);
return rc;
}
c = UINT_MAX;
for (j = 0; c != val; j++) {
c = wled_values(u32_opts[i].cfg, j);
if (c == UINT_MAX) {
dev_err(dev, "invalid value for '%s'\n",
u32_opts[i].name);
return -EINVAL;
}
if (c == val)
break;
}
dev_dbg(dev, "'%s' = %u\n", u32_opts[i].name, c);
*u32_opts[i].val_ptr = j;
}
for (i = 0; i < ARRAY_SIZE(bool_opts); ++i) {
if (of_property_read_bool(dev->of_node, bool_opts[i].name))
*bool_opts[i].val_ptr = true;
}
string_len = of_property_count_elems_of_size(dev->of_node,
"qcom,enabled-strings",
sizeof(u32));
if (string_len > 0) {
if (string_len > wled->max_string_count) {
dev_err(dev, "Cannot have more than %d strings\n",
wled->max_string_count);
return -EINVAL;
}
rc = of_property_read_u32_array(dev->of_node,
"qcom,enabled-strings",
wled->cfg.enabled_strings,
string_len);
if (rc) {
dev_err(dev, "Failed to read %d elements from qcom,enabled-strings: %d\n",
string_len, rc);
return rc;
}
for (i = 0; i < string_len; ++i) {
if (wled->cfg.enabled_strings[i] >= wled->max_string_count) {
dev_err(dev,
"qcom,enabled-strings index %d at %d is out of bounds\n",
wled->cfg.enabled_strings[i], i);
return -EINVAL;
}
}
cfg->num_strings = string_len;
}
rc = of_property_read_u32(dev->of_node, "qcom,num-strings", &val);
if (!rc) {
if (val < 1 || val > wled->max_string_count) {
dev_err(dev, "qcom,num-strings must be between 1 and %d\n",
wled->max_string_count);
return -EINVAL;
}
if (string_len > 0) {
dev_warn(dev, "Only one of qcom,num-strings or qcom,enabled-strings"
" should be set\n");
if (val > string_len) {
dev_err(dev, "qcom,num-strings exceeds qcom,enabled-strings\n");
return -EINVAL;
}
}
cfg->num_strings = val;
}
return 0;
}
static int wled_configure_short_irq(struct wled *wled,
struct platform_device *pdev)
{
int rc;
if (!wled->has_short_detect)
return 0;
rc = regmap_update_bits(wled->regmap, wled->ctrl_addr +
WLED4_CTRL_REG_SHORT_PROTECT,
WLED4_CTRL_REG_SHORT_EN_MASK,
WLED4_CTRL_REG_SHORT_EN_MASK);
if (rc < 0)
return rc;
wled->short_irq = platform_get_irq_byname(pdev, "short");
if (wled->short_irq < 0) {
dev_dbg(&pdev->dev, "short irq is not used\n");
return 0;
}
rc = devm_request_threaded_irq(wled->dev, wled->short_irq,
NULL, wled_short_irq_handler,
IRQF_ONESHOT,
"wled_short_irq", wled);
if (rc < 0)
dev_err(wled->dev, "Unable to request short_irq (err:%d)\n",
rc);
return rc;
}
static int wled_configure_ovp_irq(struct wled *wled,
struct platform_device *pdev)
{
int rc;
u32 val;
wled->ovp_irq = platform_get_irq_byname(pdev, "ovp");
if (wled->ovp_irq < 0) {
dev_dbg(&pdev->dev, "OVP IRQ not found - disabling automatic string detection\n");
return 0;
}
rc = devm_request_threaded_irq(wled->dev, wled->ovp_irq, NULL,
wled_ovp_irq_handler, IRQF_ONESHOT,
"wled_ovp_irq", wled);
if (rc < 0) {
dev_err(wled->dev, "Unable to request ovp_irq (err:%d)\n",
rc);
wled->ovp_irq = 0;
return 0;
}
rc = regmap_read(wled->regmap, wled->ctrl_addr +
WLED3_CTRL_REG_MOD_EN, &val);
if (rc < 0)
return rc;
/* Keep OVP irq disabled until module is enabled */
if (!(val & WLED3_CTRL_REG_MOD_EN_MASK))
disable_irq(wled->ovp_irq);
return 0;
}
static const struct backlight_ops wled_ops = {
.update_status = wled_update_status,
};
static int wled_probe(struct platform_device *pdev)
{
struct backlight_properties props;
struct backlight_device *bl;
struct wled *wled;
struct regmap *regmap;
u32 val;
int rc;
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap) {
dev_err(&pdev->dev, "Unable to get regmap\n");
return -EINVAL;
}
wled = devm_kzalloc(&pdev->dev, sizeof(*wled), GFP_KERNEL);
if (!wled)
return -ENOMEM;
wled->regmap = regmap;
wled->dev = &pdev->dev;
wled->version = (uintptr_t)of_device_get_match_data(&pdev->dev);
if (!wled->version) {
dev_err(&pdev->dev, "Unknown device version\n");
return -ENODEV;
}
mutex_init(&wled->lock);
rc = wled_configure(wled);
if (rc)
return rc;
val = WLED3_SINK_REG_BRIGHT_MAX;
of_property_read_u32(pdev->dev.of_node, "max-brightness", &val);
wled->max_brightness = val;
switch (wled->version) {
case 3:
wled->cfg.auto_detection_enabled = false;
rc = wled3_setup(wled);
if (rc) {
dev_err(&pdev->dev, "wled3_setup failed\n");
return rc;
}
break;
case 4:
wled->has_short_detect = true;
rc = wled4_setup(wled);
if (rc) {
dev_err(&pdev->dev, "wled4_setup failed\n");
return rc;
}
break;
case 5:
wled->has_short_detect = true;
if (wled->cfg.cabc_sel)
wled->max_brightness = WLED5_SINK_REG_BRIGHT_MAX_12B;
rc = wled5_setup(wled);
if (rc) {
dev_err(&pdev->dev, "wled5_setup failed\n");
return rc;
}
break;
default:
dev_err(wled->dev, "Invalid WLED version\n");
break;
}
INIT_DELAYED_WORK(&wled->ovp_work, wled_ovp_work);
rc = wled_configure_short_irq(wled, pdev);
if (rc < 0)
return rc;
rc = wled_configure_ovp_irq(wled, pdev);
if (rc < 0)
return rc;
val = WLED_DEFAULT_BRIGHTNESS;
of_property_read_u32(pdev->dev.of_node, "default-brightness", &val);
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.brightness = val;
props.max_brightness = wled->max_brightness;
bl = devm_backlight_device_register(&pdev->dev, wled->name,
&pdev->dev, wled,
&wled_ops, &props);
return PTR_ERR_OR_ZERO(bl);
};
static void wled_remove(struct platform_device *pdev)
{
struct wled *wled = platform_get_drvdata(pdev);
mutex_destroy(&wled->lock);
cancel_delayed_work_sync(&wled->ovp_work);
disable_irq(wled->short_irq);
disable_irq(wled->ovp_irq);
}
static const struct of_device_id wled_match_table[] = {
{ .compatible = "qcom,pm8941-wled", .data = (void *)3 },
{ .compatible = "qcom,pmi8950-wled", .data = (void *)4 },
{ .compatible = "qcom,pmi8994-wled", .data = (void *)4 },
{ .compatible = "qcom,pmi8998-wled", .data = (void *)4 },
{ .compatible = "qcom,pm660l-wled", .data = (void *)4 },
{ .compatible = "qcom,pm6150l-wled", .data = (void *)5 },
{ .compatible = "qcom,pm8150l-wled", .data = (void *)5 },
{}
};
MODULE_DEVICE_TABLE(of, wled_match_table);
static struct platform_driver wled_driver = {
.probe = wled_probe,
.remove_new = wled_remove,
.driver = {
.name = "qcom,wled",
.of_match_table = wled_match_table,
},
};
module_platform_driver(wled_driver);
MODULE_DESCRIPTION("Qualcomm WLED driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/backlight/qcom-wled.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* lms283gf05.c -- support for Samsung LMS283GF05 LCD
*
* Copyright (c) 2009 Marek Vasut <[email protected]>
*/
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/gpio/consumer.h>
#include <linux/lcd.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
struct lms283gf05_state {
struct spi_device *spi;
struct lcd_device *ld;
struct gpio_desc *reset;
};
struct lms283gf05_seq {
unsigned char reg;
unsigned short value;
unsigned char delay;
};
/* Magic sequences supplied by manufacturer, for details refer to datasheet */
static const struct lms283gf05_seq disp_initseq[] = {
/* REG, VALUE, DELAY */
{ 0x07, 0x0000, 0 },
{ 0x13, 0x0000, 10 },
{ 0x11, 0x3004, 0 },
{ 0x14, 0x200F, 0 },
{ 0x10, 0x1a20, 0 },
{ 0x13, 0x0040, 50 },
{ 0x13, 0x0060, 0 },
{ 0x13, 0x0070, 200 },
{ 0x01, 0x0127, 0 },
{ 0x02, 0x0700, 0 },
{ 0x03, 0x1030, 0 },
{ 0x08, 0x0208, 0 },
{ 0x0B, 0x0620, 0 },
{ 0x0C, 0x0110, 0 },
{ 0x30, 0x0120, 0 },
{ 0x31, 0x0127, 0 },
{ 0x32, 0x0000, 0 },
{ 0x33, 0x0503, 0 },
{ 0x34, 0x0727, 0 },
{ 0x35, 0x0124, 0 },
{ 0x36, 0x0706, 0 },
{ 0x37, 0x0701, 0 },
{ 0x38, 0x0F00, 0 },
{ 0x39, 0x0F00, 0 },
{ 0x40, 0x0000, 0 },
{ 0x41, 0x0000, 0 },
{ 0x42, 0x013f, 0 },
{ 0x43, 0x0000, 0 },
{ 0x44, 0x013f, 0 },
{ 0x45, 0x0000, 0 },
{ 0x46, 0xef00, 0 },
{ 0x47, 0x013f, 0 },
{ 0x48, 0x0000, 0 },
{ 0x07, 0x0015, 30 },
{ 0x07, 0x0017, 0 },
{ 0x20, 0x0000, 0 },
{ 0x21, 0x0000, 0 },
{ 0x22, 0x0000, 0 }
};
static const struct lms283gf05_seq disp_pdwnseq[] = {
{ 0x07, 0x0016, 30 },
{ 0x07, 0x0004, 0 },
{ 0x10, 0x0220, 20 },
{ 0x13, 0x0060, 50 },
{ 0x13, 0x0040, 50 },
{ 0x13, 0x0000, 0 },
{ 0x10, 0x0000, 0 }
};
static void lms283gf05_reset(struct gpio_desc *gpiod)
{
gpiod_set_value(gpiod, 0); /* De-asserted */
mdelay(100);
gpiod_set_value(gpiod, 1); /* Asserted */
mdelay(20);
gpiod_set_value(gpiod, 0); /* De-asserted */
mdelay(20);
}
static void lms283gf05_toggle(struct spi_device *spi,
const struct lms283gf05_seq *seq, int sz)
{
char buf[3];
int i;
for (i = 0; i < sz; i++) {
buf[0] = 0x74;
buf[1] = 0x00;
buf[2] = seq[i].reg;
spi_write(spi, buf, 3);
buf[0] = 0x76;
buf[1] = seq[i].value >> 8;
buf[2] = seq[i].value & 0xff;
spi_write(spi, buf, 3);
mdelay(seq[i].delay);
}
}
static int lms283gf05_power_set(struct lcd_device *ld, int power)
{
struct lms283gf05_state *st = lcd_get_data(ld);
struct spi_device *spi = st->spi;
if (power <= FB_BLANK_NORMAL) {
if (st->reset)
lms283gf05_reset(st->reset);
lms283gf05_toggle(spi, disp_initseq, ARRAY_SIZE(disp_initseq));
} else {
lms283gf05_toggle(spi, disp_pdwnseq, ARRAY_SIZE(disp_pdwnseq));
if (st->reset)
gpiod_set_value(st->reset, 1); /* Asserted */
}
return 0;
}
static struct lcd_ops lms_ops = {
.set_power = lms283gf05_power_set,
.get_power = NULL,
};
static int lms283gf05_probe(struct spi_device *spi)
{
struct lms283gf05_state *st;
struct lcd_device *ld;
st = devm_kzalloc(&spi->dev, sizeof(struct lms283gf05_state),
GFP_KERNEL);
if (st == NULL)
return -ENOMEM;
st->reset = gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(st->reset))
return PTR_ERR(st->reset);
gpiod_set_consumer_name(st->reset, "LMS283GF05 RESET");
ld = devm_lcd_device_register(&spi->dev, "lms283gf05", &spi->dev, st,
&lms_ops);
if (IS_ERR(ld))
return PTR_ERR(ld);
st->spi = spi;
st->ld = ld;
spi_set_drvdata(spi, st);
/* kick in the LCD */
if (st->reset)
lms283gf05_reset(st->reset);
lms283gf05_toggle(spi, disp_initseq, ARRAY_SIZE(disp_initseq));
return 0;
}
static struct spi_driver lms283gf05_driver = {
.driver = {
.name = "lms283gf05",
},
.probe = lms283gf05_probe,
};
module_spi_driver(lms283gf05_driver);
MODULE_AUTHOR("Marek Vasut <[email protected]>");
MODULE_DESCRIPTION("LCD283GF05 LCD");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/backlight/lms283gf05.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Backlight driver for Pandora handheld.
* Pandora uses TWL4030 PWM0 -> TPS61161 combo for control backlight.
* Based on pwm_bl.c
*
* Copyright 2009,2012 Gražvydas Ignotas <[email protected]>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/backlight.h>
#include <linux/mfd/twl.h>
#include <linux/err.h>
#define TWL_PWM0_ON 0x00
#define TWL_PWM0_OFF 0x01
#define TWL_INTBR_GPBR1 0x0c
#define TWL_INTBR_PMBR1 0x0d
#define TWL_PMBR1_PWM0_MUXMASK 0x0c
#define TWL_PMBR1_PWM0 0x04
#define PWM0_CLK_ENABLE BIT(0)
#define PWM0_ENABLE BIT(2)
/* range accepted by hardware */
#define MIN_VALUE 9
#define MAX_VALUE 63
#define MAX_USER_VALUE (MAX_VALUE - MIN_VALUE)
struct pandora_private {
unsigned old_state;
#define PANDORABL_WAS_OFF 1
};
static int pandora_backlight_update_status(struct backlight_device *bl)
{
int brightness = bl->props.brightness;
struct pandora_private *priv = bl_get_data(bl);
u8 r;
if (bl->props.power != FB_BLANK_UNBLANK)
brightness = 0;
if (bl->props.state & BL_CORE_FBBLANK)
brightness = 0;
if (bl->props.state & BL_CORE_SUSPENDED)
brightness = 0;
if ((unsigned int)brightness > MAX_USER_VALUE)
brightness = MAX_USER_VALUE;
if (brightness == 0) {
if (priv->old_state == PANDORABL_WAS_OFF)
goto done;
/* first disable PWM0 output, then clock */
twl_i2c_read_u8(TWL4030_MODULE_INTBR, &r, TWL_INTBR_GPBR1);
r &= ~PWM0_ENABLE;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_GPBR1);
r &= ~PWM0_CLK_ENABLE;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_GPBR1);
goto done;
}
if (priv->old_state == PANDORABL_WAS_OFF) {
/*
* set PWM duty cycle to max. TPS61161 seems to use this
* to calibrate it's PWM sensitivity when it starts.
*/
twl_i2c_write_u8(TWL_MODULE_PWM, MAX_VALUE, TWL_PWM0_OFF);
/* first enable clock, then PWM0 out */
twl_i2c_read_u8(TWL4030_MODULE_INTBR, &r, TWL_INTBR_GPBR1);
r &= ~PWM0_ENABLE;
r |= PWM0_CLK_ENABLE;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_GPBR1);
r |= PWM0_ENABLE;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_GPBR1);
/*
* TI made it very easy to enable digital control, so easy that
* it often triggers unintentionally and disabes PWM control,
* so wait until 1 wire mode detection window ends.
*/
usleep_range(2000, 10000);
}
twl_i2c_write_u8(TWL_MODULE_PWM, MIN_VALUE + brightness, TWL_PWM0_OFF);
done:
if (brightness != 0)
priv->old_state = 0;
else
priv->old_state = PANDORABL_WAS_OFF;
return 0;
}
static const struct backlight_ops pandora_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = pandora_backlight_update_status,
};
static int pandora_backlight_probe(struct platform_device *pdev)
{
struct backlight_properties props;
struct backlight_device *bl;
struct pandora_private *priv;
u8 r;
priv = devm_kmalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv) {
dev_err(&pdev->dev, "failed to allocate driver private data\n");
return -ENOMEM;
}
memset(&props, 0, sizeof(props));
props.max_brightness = MAX_USER_VALUE;
props.type = BACKLIGHT_RAW;
bl = devm_backlight_device_register(&pdev->dev, pdev->name, &pdev->dev,
priv, &pandora_backlight_ops, &props);
if (IS_ERR(bl)) {
dev_err(&pdev->dev, "failed to register backlight\n");
return PTR_ERR(bl);
}
platform_set_drvdata(pdev, bl);
/* 64 cycle period, ON position 0 */
twl_i2c_write_u8(TWL_MODULE_PWM, 0x80, TWL_PWM0_ON);
priv->old_state = PANDORABL_WAS_OFF;
bl->props.brightness = MAX_USER_VALUE;
backlight_update_status(bl);
/* enable PWM function in pin mux */
twl_i2c_read_u8(TWL4030_MODULE_INTBR, &r, TWL_INTBR_PMBR1);
r &= ~TWL_PMBR1_PWM0_MUXMASK;
r |= TWL_PMBR1_PWM0;
twl_i2c_write_u8(TWL4030_MODULE_INTBR, r, TWL_INTBR_PMBR1);
return 0;
}
static struct platform_driver pandora_backlight_driver = {
.driver = {
.name = "pandora-backlight",
},
.probe = pandora_backlight_probe,
};
module_platform_driver(pandora_backlight_driver);
MODULE_AUTHOR("Gražvydas Ignotas <[email protected]>");
MODULE_DESCRIPTION("Pandora Backlight Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:pandora-backlight");
| linux-master | drivers/video/backlight/pandora_bl.c |
/*
* linux/drivers/video/neofb.c -- NeoMagic Framebuffer Driver
*
* Copyright (c) 2001-2002 Denis Oliver Kropp <[email protected]>
*
*
* Card specific code is based on XFree86's neomagic driver.
* Framebuffer framework code is based on code of cyber2000fb.
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
*
* 0.4.1
* - Cosmetic changes (dok)
*
* 0.4
* - Toshiba Libretto support, allow modes larger than LCD size if
* LCD is disabled, keep BIOS settings if internal/external display
* haven't been enabled explicitly
* (Thomas J. Moore <[email protected]>)
*
* 0.3.3
* - Porting over to new fbdev api. (jsimmons)
*
* 0.3.2
* - got rid of all floating point (dok)
*
* 0.3.1
* - added module license (dok)
*
* 0.3
* - hardware accelerated clear and move for 2200 and above (dok)
* - maximum allowed dotclock is handled now (dok)
*
* 0.2.1
* - correct panning after X usage (dok)
* - added module and kernel parameters (dok)
* - no stretching if external display is enabled (dok)
*
* 0.2
* - initial version (dok)
*
*
* TODO
* - ioctl for internal/external switching
* - blanking
* - 32bit depth support, maybe impossible
* - disable pan-on-sync, need specs
*
* BUGS
* - white margin on bootup like with tdfxfb (colormap problem?)
*
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#ifdef CONFIG_TOSHIBA
#include <linux/toshiba.h>
#endif
#include <asm/io.h>
#include <asm/irq.h>
#include <video/vga.h>
#include <video/neomagic.h>
#define NEOFB_VERSION "0.4.2"
/* --------------------------------------------------------------------- */
static bool internal;
static bool external;
static bool libretto;
static bool nostretch;
static bool nopciburst;
static char *mode_option = NULL;
#ifdef MODULE
MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("FBDev driver for NeoMagic PCI Chips");
module_param(internal, bool, 0);
MODULE_PARM_DESC(internal, "Enable output on internal LCD Display.");
module_param(external, bool, 0);
MODULE_PARM_DESC(external, "Enable output on external CRT.");
module_param(libretto, bool, 0);
MODULE_PARM_DESC(libretto, "Force Libretto 100/110 800x480 LCD.");
module_param(nostretch, bool, 0);
MODULE_PARM_DESC(nostretch,
"Disable stretching of modes smaller than LCD.");
module_param(nopciburst, bool, 0);
MODULE_PARM_DESC(nopciburst, "Disable PCI burst mode.");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Preferred video mode ('640x480-8@60', etc)");
#endif
/* --------------------------------------------------------------------- */
static biosMode bios8[] = {
{320, 240, 0x40},
{300, 400, 0x42},
{640, 400, 0x20},
{640, 480, 0x21},
{800, 600, 0x23},
{1024, 768, 0x25},
};
static biosMode bios16[] = {
{320, 200, 0x2e},
{320, 240, 0x41},
{300, 400, 0x43},
{640, 480, 0x31},
{800, 600, 0x34},
{1024, 768, 0x37},
};
static biosMode bios24[] = {
{640, 480, 0x32},
{800, 600, 0x35},
{1024, 768, 0x38}
};
#ifdef NO_32BIT_SUPPORT_YET
/* FIXME: guessed values, wrong */
static biosMode bios32[] = {
{640, 480, 0x33},
{800, 600, 0x36},
{1024, 768, 0x39}
};
#endif
static inline void write_le32(int regindex, u32 val, const struct neofb_par *par)
{
writel(val, par->neo2200 + par->cursorOff + regindex);
}
static int neoFindMode(int xres, int yres, int depth)
{
int xres_s;
int i, size;
biosMode *mode;
switch (depth) {
case 8:
size = ARRAY_SIZE(bios8);
mode = bios8;
break;
case 16:
size = ARRAY_SIZE(bios16);
mode = bios16;
break;
case 24:
size = ARRAY_SIZE(bios24);
mode = bios24;
break;
#ifdef NO_32BIT_SUPPORT_YET
case 32:
size = ARRAY_SIZE(bios32);
mode = bios32;
break;
#endif
default:
return 0;
}
for (i = 0; i < size; i++) {
if (xres <= mode[i].x_res) {
xres_s = mode[i].x_res;
for (; i < size; i++) {
if (mode[i].x_res != xres_s)
return mode[i - 1].mode;
if (yres <= mode[i].y_res)
return mode[i].mode;
}
}
}
return mode[size - 1].mode;
}
/*
* neoCalcVCLK --
*
* Determine the closest clock frequency to the one requested.
*/
#define MAX_N 127
#define MAX_D 31
#define MAX_F 1
static void neoCalcVCLK(const struct fb_info *info,
struct neofb_par *par, long freq)
{
int n, d, f;
int n_best = 0, d_best = 0, f_best = 0;
long f_best_diff = 0x7ffff;
for (f = 0; f <= MAX_F; f++)
for (d = 0; d <= MAX_D; d++)
for (n = 0; n <= MAX_N; n++) {
long f_out;
long f_diff;
f_out = ((14318 * (n + 1)) / (d + 1)) >> f;
f_diff = abs(f_out - freq);
if (f_diff <= f_best_diff) {
f_best_diff = f_diff;
n_best = n;
d_best = d;
f_best = f;
}
if (f_out > freq)
break;
}
if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
/* NOT_DONE: We are trying the full range of the 2200 clock.
We should be able to try n up to 2047 */
par->VCLK3NumeratorLow = n_best;
par->VCLK3NumeratorHigh = (f_best << 7);
} else
par->VCLK3NumeratorLow = n_best | (f_best << 7);
par->VCLK3Denominator = d_best;
#ifdef NEOFB_DEBUG
printk(KERN_DEBUG "neoVCLK: f:%ld NumLow=%d NumHi=%d Den=%d Df=%ld\n",
freq,
par->VCLK3NumeratorLow,
par->VCLK3NumeratorHigh,
par->VCLK3Denominator, f_best_diff);
#endif
}
/*
* vgaHWInit --
* Handle the initialization, etc. of a screen.
* Return FALSE on failure.
*/
static int vgaHWInit(const struct fb_var_screeninfo *var,
struct neofb_par *par)
{
int hsync_end = var->xres + var->right_margin + var->hsync_len;
int htotal = (hsync_end + var->left_margin) >> 3;
int vsync_start = var->yres + var->lower_margin;
int vsync_end = vsync_start + var->vsync_len;
int vtotal = vsync_end + var->upper_margin;
par->MiscOutReg = 0x23;
if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
par->MiscOutReg |= 0x40;
if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
par->MiscOutReg |= 0x80;
/*
* Time Sequencer
*/
par->Sequencer[0] = 0x00;
par->Sequencer[1] = 0x01;
par->Sequencer[2] = 0x0F;
par->Sequencer[3] = 0x00; /* Font select */
par->Sequencer[4] = 0x0E; /* Misc */
/*
* CRTC Controller
*/
par->CRTC[0] = htotal - 5;
par->CRTC[1] = (var->xres >> 3) - 1;
par->CRTC[2] = (var->xres >> 3) - 1;
par->CRTC[3] = ((htotal - 1) & 0x1F) | 0x80;
par->CRTC[4] = ((var->xres + var->right_margin) >> 3);
par->CRTC[5] = (((htotal - 1) & 0x20) << 2)
| (((hsync_end >> 3)) & 0x1F);
par->CRTC[6] = (vtotal - 2) & 0xFF;
par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8)
| (((var->yres - 1) & 0x100) >> 7)
| ((vsync_start & 0x100) >> 6)
| (((var->yres - 1) & 0x100) >> 5)
| 0x10 | (((vtotal - 2) & 0x200) >> 4)
| (((var->yres - 1) & 0x200) >> 3)
| ((vsync_start & 0x200) >> 2);
par->CRTC[8] = 0x00;
par->CRTC[9] = (((var->yres - 1) & 0x200) >> 4) | 0x40;
if (var->vmode & FB_VMODE_DOUBLE)
par->CRTC[9] |= 0x80;
par->CRTC[10] = 0x00;
par->CRTC[11] = 0x00;
par->CRTC[12] = 0x00;
par->CRTC[13] = 0x00;
par->CRTC[14] = 0x00;
par->CRTC[15] = 0x00;
par->CRTC[16] = vsync_start & 0xFF;
par->CRTC[17] = (vsync_end & 0x0F) | 0x20;
par->CRTC[18] = (var->yres - 1) & 0xFF;
par->CRTC[19] = var->xres_virtual >> 4;
par->CRTC[20] = 0x00;
par->CRTC[21] = (var->yres - 1) & 0xFF;
par->CRTC[22] = (vtotal - 1) & 0xFF;
par->CRTC[23] = 0xC3;
par->CRTC[24] = 0xFF;
/*
* are these unnecessary?
* vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
* vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
*/
/*
* Graphics Display Controller
*/
par->Graphics[0] = 0x00;
par->Graphics[1] = 0x00;
par->Graphics[2] = 0x00;
par->Graphics[3] = 0x00;
par->Graphics[4] = 0x00;
par->Graphics[5] = 0x40;
par->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
par->Graphics[7] = 0x0F;
par->Graphics[8] = 0xFF;
par->Attribute[0] = 0x00; /* standard colormap translation */
par->Attribute[1] = 0x01;
par->Attribute[2] = 0x02;
par->Attribute[3] = 0x03;
par->Attribute[4] = 0x04;
par->Attribute[5] = 0x05;
par->Attribute[6] = 0x06;
par->Attribute[7] = 0x07;
par->Attribute[8] = 0x08;
par->Attribute[9] = 0x09;
par->Attribute[10] = 0x0A;
par->Attribute[11] = 0x0B;
par->Attribute[12] = 0x0C;
par->Attribute[13] = 0x0D;
par->Attribute[14] = 0x0E;
par->Attribute[15] = 0x0F;
par->Attribute[16] = 0x41;
par->Attribute[17] = 0xFF;
par->Attribute[18] = 0x0F;
par->Attribute[19] = 0x00;
par->Attribute[20] = 0x00;
return 0;
}
static void vgaHWLock(struct vgastate *state)
{
/* Protect CRTC[0-7] */
vga_wcrt(state->vgabase, 0x11, vga_rcrt(state->vgabase, 0x11) | 0x80);
}
static void vgaHWUnlock(void)
{
/* Unprotect CRTC[0-7] */
vga_wcrt(NULL, 0x11, vga_rcrt(NULL, 0x11) & ~0x80);
}
static void neoLock(struct vgastate *state)
{
vga_wgfx(state->vgabase, 0x09, 0x00);
vgaHWLock(state);
}
static void neoUnlock(void)
{
vgaHWUnlock();
vga_wgfx(NULL, 0x09, 0x26);
}
/*
* VGA Palette management
*/
static int paletteEnabled = 0;
static inline void VGAenablePalette(void)
{
vga_r(NULL, VGA_IS1_RC);
vga_w(NULL, VGA_ATT_W, 0x00);
paletteEnabled = 1;
}
static inline void VGAdisablePalette(void)
{
vga_r(NULL, VGA_IS1_RC);
vga_w(NULL, VGA_ATT_W, 0x20);
paletteEnabled = 0;
}
static inline void VGAwATTR(u8 index, u8 value)
{
if (paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
vga_r(NULL, VGA_IS1_RC);
vga_wattr(NULL, index, value);
}
static void vgaHWProtect(int on)
{
unsigned char tmp;
tmp = vga_rseq(NULL, 0x01);
if (on) {
/*
* Turn off screen and disable sequencer.
*/
vga_wseq(NULL, 0x00, 0x01); /* Synchronous Reset */
vga_wseq(NULL, 0x01, tmp | 0x20); /* disable the display */
VGAenablePalette();
} else {
/*
* Reenable sequencer, then turn on screen.
*/
vga_wseq(NULL, 0x01, tmp & ~0x20); /* reenable display */
vga_wseq(NULL, 0x00, 0x03); /* clear synchronousreset */
VGAdisablePalette();
}
}
static void vgaHWRestore(const struct fb_info *info,
const struct neofb_par *par)
{
int i;
vga_w(NULL, VGA_MIS_W, par->MiscOutReg);
for (i = 1; i < 5; i++)
vga_wseq(NULL, i, par->Sequencer[i]);
/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or CRTC[17] */
vga_wcrt(NULL, 17, par->CRTC[17] & ~0x80);
for (i = 0; i < 25; i++)
vga_wcrt(NULL, i, par->CRTC[i]);
for (i = 0; i < 9; i++)
vga_wgfx(NULL, i, par->Graphics[i]);
VGAenablePalette();
for (i = 0; i < 21; i++)
VGAwATTR(i, par->Attribute[i]);
VGAdisablePalette();
}
/* -------------------- Hardware specific routines ------------------------- */
/*
* Hardware Acceleration for Neo2200+
*/
static inline int neo2200_sync(struct fb_info *info)
{
struct neofb_par *par = info->par;
while (readl(&par->neo2200->bltStat) & 1)
cpu_relax();
return 0;
}
static inline void neo2200_wait_fifo(struct fb_info *info,
int requested_fifo_space)
{
// ndev->neo.waitfifo_calls++;
// ndev->neo.waitfifo_sum += requested_fifo_space;
/* FIXME: does not work
if (neo_fifo_space < requested_fifo_space)
{
neo_fifo_waitcycles++;
while (1)
{
neo_fifo_space = (neo2200->bltStat >> 8);
if (neo_fifo_space >= requested_fifo_space)
break;
}
}
else
{
neo_fifo_cache_hits++;
}
neo_fifo_space -= requested_fifo_space;
*/
neo2200_sync(info);
}
static inline void neo2200_accel_init(struct fb_info *info,
struct fb_var_screeninfo *var)
{
struct neofb_par *par = info->par;
Neo2200 __iomem *neo2200 = par->neo2200;
u32 bltMod, pitch;
neo2200_sync(info);
switch (var->bits_per_pixel) {
case 8:
bltMod = NEO_MODE1_DEPTH8;
pitch = var->xres_virtual;
break;
case 15:
case 16:
bltMod = NEO_MODE1_DEPTH16;
pitch = var->xres_virtual * 2;
break;
case 24:
bltMod = NEO_MODE1_DEPTH24;
pitch = var->xres_virtual * 3;
break;
default:
printk(KERN_ERR
"neofb: neo2200_accel_init: unexpected bits per pixel!\n");
return;
}
writel(bltMod << 16, &neo2200->bltStat);
writel((pitch << 16) | pitch, &neo2200->pitch);
}
/* --------------------------------------------------------------------- */
static int
neofb_open(struct fb_info *info, int user)
{
struct neofb_par *par = info->par;
if (!par->ref_count) {
memset(&par->state, 0, sizeof(struct vgastate));
par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
save_vga(&par->state);
}
par->ref_count++;
return 0;
}
static int
neofb_release(struct fb_info *info, int user)
{
struct neofb_par *par = info->par;
if (!par->ref_count)
return -EINVAL;
if (par->ref_count == 1) {
restore_vga(&par->state);
}
par->ref_count--;
return 0;
}
static int
neofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct neofb_par *par = info->par;
int memlen, vramlen;
int mode_ok = 0;
DBG("neofb_check_var");
if (!var->pixclock || PICOS2KHZ(var->pixclock) > par->maxClock)
return -EINVAL;
/* Is the mode larger than the LCD panel? */
if (par->internal_display &&
((var->xres > par->NeoPanelWidth) ||
(var->yres > par->NeoPanelHeight))) {
printk(KERN_INFO
"Mode (%dx%d) larger than the LCD panel (%dx%d)\n",
var->xres, var->yres, par->NeoPanelWidth,
par->NeoPanelHeight);
return -EINVAL;
}
/* Is the mode one of the acceptable sizes? */
if (!par->internal_display)
mode_ok = 1;
else {
switch (var->xres) {
case 1280:
if (var->yres == 1024)
mode_ok = 1;
break;
case 1024:
if (var->yres == 768)
mode_ok = 1;
break;
case 800:
if (var->yres == (par->libretto ? 480 : 600))
mode_ok = 1;
break;
case 640:
if (var->yres == 480)
mode_ok = 1;
break;
}
}
if (!mode_ok) {
printk(KERN_INFO
"Mode (%dx%d) won't display properly on LCD\n",
var->xres, var->yres);
return -EINVAL;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
var->transp.offset = 0;
var->transp.length = 0;
switch (var->bits_per_pixel) {
case 8: /* PSEUDOCOLOUR, 256 */
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
case 16: /* DIRECTCOLOUR, 64k */
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
break;
case 24: /* TRUECOLOUR, 16m */
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
#ifdef NO_32BIT_SUPPORT_YET
case 32: /* TRUECOLOUR, 16m */
var->transp.offset = 24;
var->transp.length = 8;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
#endif
default:
printk(KERN_WARNING "neofb: no support for %dbpp\n",
var->bits_per_pixel);
return -EINVAL;
}
vramlen = info->fix.smem_len;
if (vramlen > 4 * 1024 * 1024)
vramlen = 4 * 1024 * 1024;
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
memlen = var->xres_virtual * var->bits_per_pixel * var->yres_virtual >> 3;
if (memlen > vramlen) {
var->yres_virtual = vramlen * 8 / (var->xres_virtual *
var->bits_per_pixel);
memlen = var->xres_virtual * var->bits_per_pixel *
var->yres_virtual / 8;
}
/* we must round yres/xres down, we already rounded y/xres_virtual up
if it was possible. We should return -EINVAL, but I disagree */
if (var->yres_virtual < var->yres)
var->yres = var->yres_virtual;
if (var->xoffset + var->xres > var->xres_virtual)
var->xoffset = var->xres_virtual - var->xres;
if (var->yoffset + var->yres > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
var->nonstd = 0;
var->height = -1;
var->width = -1;
if (var->bits_per_pixel >= 24 || !par->neo2200)
var->accel_flags &= ~FB_ACCELF_TEXT;
return 0;
}
static int neofb_set_par(struct fb_info *info)
{
struct neofb_par *par = info->par;
unsigned char temp;
int i, clock_hi = 0;
int lcd_stretch;
int hoffset, voffset;
int vsync_start, vtotal;
DBG("neofb_set_par");
neoUnlock();
vgaHWProtect(1); /* Blank the screen */
vsync_start = info->var.yres + info->var.lower_margin;
vtotal = vsync_start + info->var.vsync_len + info->var.upper_margin;
/*
* This will allocate the datastructure and initialize all of the
* generic VGA registers.
*/
if (vgaHWInit(&info->var, par))
return -EINVAL;
/*
* The default value assigned by vgaHW.c is 0x41, but this does
* not work for NeoMagic.
*/
par->Attribute[16] = 0x01;
switch (info->var.bits_per_pixel) {
case 8:
par->CRTC[0x13] = info->var.xres_virtual >> 3;
par->ExtCRTOffset = info->var.xres_virtual >> 11;
par->ExtColorModeSelect = 0x11;
break;
case 16:
par->CRTC[0x13] = info->var.xres_virtual >> 2;
par->ExtCRTOffset = info->var.xres_virtual >> 10;
par->ExtColorModeSelect = 0x13;
break;
case 24:
par->CRTC[0x13] = (info->var.xres_virtual * 3) >> 3;
par->ExtCRTOffset = (info->var.xres_virtual * 3) >> 11;
par->ExtColorModeSelect = 0x14;
break;
#ifdef NO_32BIT_SUPPORT_YET
case 32: /* FIXME: guessed values */
par->CRTC[0x13] = info->var.xres_virtual >> 1;
par->ExtCRTOffset = info->var.xres_virtual >> 9;
par->ExtColorModeSelect = 0x15;
break;
#endif
default:
break;
}
par->ExtCRTDispAddr = 0x10;
/* Vertical Extension */
par->VerticalExt = (((vtotal - 2) & 0x400) >> 10)
| (((info->var.yres - 1) & 0x400) >> 9)
| (((vsync_start) & 0x400) >> 8)
| (((vsync_start) & 0x400) >> 7);
/* Fast write bursts on unless disabled. */
if (par->pci_burst)
par->SysIfaceCntl1 = 0x30;
else
par->SysIfaceCntl1 = 0x00;
par->SysIfaceCntl2 = 0xc0; /* VESA Bios sets this to 0x80! */
/* Initialize: by default, we want display config register to be read */
par->PanelDispCntlRegRead = 1;
/* Enable any user specified display devices. */
par->PanelDispCntlReg1 = 0x00;
if (par->internal_display)
par->PanelDispCntlReg1 |= 0x02;
if (par->external_display)
par->PanelDispCntlReg1 |= 0x01;
/* If the user did not specify any display devices, then... */
if (par->PanelDispCntlReg1 == 0x00) {
/* Default to internal (i.e., LCD) only. */
par->PanelDispCntlReg1 = vga_rgfx(NULL, 0x20) & 0x03;
}
/* If we are using a fixed mode, then tell the chip we are. */
switch (info->var.xres) {
case 1280:
par->PanelDispCntlReg1 |= 0x60;
break;
case 1024:
par->PanelDispCntlReg1 |= 0x40;
break;
case 800:
par->PanelDispCntlReg1 |= 0x20;
break;
case 640:
default:
break;
}
/* Setup shadow register locking. */
switch (par->PanelDispCntlReg1 & 0x03) {
case 0x01: /* External CRT only mode: */
par->GeneralLockReg = 0x00;
/* We need to program the VCLK for external display only mode. */
par->ProgramVCLK = 1;
break;
case 0x02: /* Internal LCD only mode: */
case 0x03: /* Simultaneous internal/external (LCD/CRT) mode: */
par->GeneralLockReg = 0x01;
/* Don't program the VCLK when using the LCD. */
par->ProgramVCLK = 0;
break;
}
/*
* If the screen is to be stretched, turn on stretching for the
* various modes.
*
* OPTION_LCD_STRETCH means stretching should be turned off!
*/
par->PanelDispCntlReg2 = 0x00;
par->PanelDispCntlReg3 = 0x00;
if (par->lcd_stretch && (par->PanelDispCntlReg1 == 0x02) && /* LCD only */
(info->var.xres != par->NeoPanelWidth)) {
switch (info->var.xres) {
case 320: /* Needs testing. KEM -- 24 May 98 */
case 400: /* Needs testing. KEM -- 24 May 98 */
case 640:
case 800:
case 1024:
lcd_stretch = 1;
par->PanelDispCntlReg2 |= 0xC6;
break;
default:
lcd_stretch = 0;
/* No stretching in these modes. */
}
} else
lcd_stretch = 0;
/*
* If the screen is to be centerd, turn on the centering for the
* various modes.
*/
par->PanelVertCenterReg1 = 0x00;
par->PanelVertCenterReg2 = 0x00;
par->PanelVertCenterReg3 = 0x00;
par->PanelVertCenterReg4 = 0x00;
par->PanelVertCenterReg5 = 0x00;
par->PanelHorizCenterReg1 = 0x00;
par->PanelHorizCenterReg2 = 0x00;
par->PanelHorizCenterReg3 = 0x00;
par->PanelHorizCenterReg4 = 0x00;
par->PanelHorizCenterReg5 = 0x00;
if (par->PanelDispCntlReg1 & 0x02) {
if (info->var.xres == par->NeoPanelWidth) {
/*
* No centering required when the requested display width
* equals the panel width.
*/
} else {
par->PanelDispCntlReg2 |= 0x01;
par->PanelDispCntlReg3 |= 0x10;
/* Calculate the horizontal and vertical offsets. */
if (!lcd_stretch) {
hoffset =
((par->NeoPanelWidth -
info->var.xres) >> 4) - 1;
voffset =
((par->NeoPanelHeight -
info->var.yres) >> 1) - 2;
} else {
/* Stretched modes cannot be centered. */
hoffset = 0;
voffset = 0;
}
switch (info->var.xres) {
case 320: /* Needs testing. KEM -- 24 May 98 */
par->PanelHorizCenterReg3 = hoffset;
par->PanelVertCenterReg2 = voffset;
break;
case 400: /* Needs testing. KEM -- 24 May 98 */
par->PanelHorizCenterReg4 = hoffset;
par->PanelVertCenterReg1 = voffset;
break;
case 640:
par->PanelHorizCenterReg1 = hoffset;
par->PanelVertCenterReg3 = voffset;
break;
case 800:
par->PanelHorizCenterReg2 = hoffset;
par->PanelVertCenterReg4 = voffset;
break;
case 1024:
par->PanelHorizCenterReg5 = hoffset;
par->PanelVertCenterReg5 = voffset;
break;
case 1280:
default:
/* No centering in these modes. */
break;
}
}
}
par->biosMode =
neoFindMode(info->var.xres, info->var.yres,
info->var.bits_per_pixel);
/*
* Calculate the VCLK that most closely matches the requested dot
* clock.
*/
neoCalcVCLK(info, par, PICOS2KHZ(info->var.pixclock));
/* Since we program the clocks ourselves, always use VCLK3. */
par->MiscOutReg |= 0x0C;
/* alread unlocked above */
/* BOGUS vga_wgfx(NULL, 0x09, 0x26); */
/* don't know what this is, but it's 0 from bootup anyway */
vga_wgfx(NULL, 0x15, 0x00);
/* was set to 0x01 by my bios in text and vesa modes */
vga_wgfx(NULL, 0x0A, par->GeneralLockReg);
/*
* The color mode needs to be set before calling vgaHWRestore
* to ensure the DAC is initialized properly.
*
* NOTE: Make sure we don't change bits make sure we don't change
* any reserved bits.
*/
temp = vga_rgfx(NULL, 0x90);
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2070:
temp &= 0xF0; /* Save bits 7:4 */
temp |= (par->ExtColorModeSelect & ~0xF0);
break;
case FB_ACCEL_NEOMAGIC_NM2090:
case FB_ACCEL_NEOMAGIC_NM2093:
case FB_ACCEL_NEOMAGIC_NM2097:
case FB_ACCEL_NEOMAGIC_NM2160:
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
temp &= 0x70; /* Save bits 6:4 */
temp |= (par->ExtColorModeSelect & ~0x70);
break;
}
vga_wgfx(NULL, 0x90, temp);
/*
* In some rare cases a lockup might occur if we don't delay
* here. (Reported by Miles Lane)
*/
//mdelay(200);
/*
* Disable horizontal and vertical graphics and text expansions so
* that vgaHWRestore works properly.
*/
temp = vga_rgfx(NULL, 0x25);
temp &= 0x39;
vga_wgfx(NULL, 0x25, temp);
/*
* Sleep for 200ms to make sure that the two operations above have
* had time to take effect.
*/
mdelay(200);
/*
* This function handles restoring the generic VGA registers. */
vgaHWRestore(info, par);
/* linear colormap for non palettized modes */
switch (info->var.bits_per_pixel) {
case 8:
/* PseudoColor, 256 */
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
/* TrueColor, 64k */
info->fix.visual = FB_VISUAL_TRUECOLOR;
for (i = 0; i < 64; i++) {
outb(i, 0x3c8);
outb(i << 1, 0x3c9);
outb(i, 0x3c9);
outb(i << 1, 0x3c9);
}
break;
case 24:
#ifdef NO_32BIT_SUPPORT_YET
case 32:
#endif
/* TrueColor, 16m */
info->fix.visual = FB_VISUAL_TRUECOLOR;
for (i = 0; i < 256; i++) {
outb(i, 0x3c8);
outb(i, 0x3c9);
outb(i, 0x3c9);
outb(i, 0x3c9);
}
break;
}
vga_wgfx(NULL, 0x0E, par->ExtCRTDispAddr);
vga_wgfx(NULL, 0x0F, par->ExtCRTOffset);
temp = vga_rgfx(NULL, 0x10);
temp &= 0x0F; /* Save bits 3:0 */
temp |= (par->SysIfaceCntl1 & ~0x0F); /* VESA Bios sets bit 1! */
vga_wgfx(NULL, 0x10, temp);
vga_wgfx(NULL, 0x11, par->SysIfaceCntl2);
vga_wgfx(NULL, 0x15, 0 /*par->SingleAddrPage */ );
vga_wgfx(NULL, 0x16, 0 /*par->DualAddrPage */ );
temp = vga_rgfx(NULL, 0x20);
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2070:
temp &= 0xFC; /* Save bits 7:2 */
temp |= (par->PanelDispCntlReg1 & ~0xFC);
break;
case FB_ACCEL_NEOMAGIC_NM2090:
case FB_ACCEL_NEOMAGIC_NM2093:
case FB_ACCEL_NEOMAGIC_NM2097:
case FB_ACCEL_NEOMAGIC_NM2160:
temp &= 0xDC; /* Save bits 7:6,4:2 */
temp |= (par->PanelDispCntlReg1 & ~0xDC);
break;
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
temp &= 0x98; /* Save bits 7,4:3 */
temp |= (par->PanelDispCntlReg1 & ~0x98);
break;
}
vga_wgfx(NULL, 0x20, temp);
temp = vga_rgfx(NULL, 0x25);
temp &= 0x38; /* Save bits 5:3 */
temp |= (par->PanelDispCntlReg2 & ~0x38);
vga_wgfx(NULL, 0x25, temp);
if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
temp = vga_rgfx(NULL, 0x30);
temp &= 0xEF; /* Save bits 7:5 and bits 3:0 */
temp |= (par->PanelDispCntlReg3 & ~0xEF);
vga_wgfx(NULL, 0x30, temp);
}
vga_wgfx(NULL, 0x28, par->PanelVertCenterReg1);
vga_wgfx(NULL, 0x29, par->PanelVertCenterReg2);
vga_wgfx(NULL, 0x2a, par->PanelVertCenterReg3);
if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
vga_wgfx(NULL, 0x32, par->PanelVertCenterReg4);
vga_wgfx(NULL, 0x33, par->PanelHorizCenterReg1);
vga_wgfx(NULL, 0x34, par->PanelHorizCenterReg2);
vga_wgfx(NULL, 0x35, par->PanelHorizCenterReg3);
}
if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2160)
vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
vga_wgfx(NULL, 0x37, par->PanelVertCenterReg5);
vga_wgfx(NULL, 0x38, par->PanelHorizCenterReg5);
clock_hi = 1;
}
/* Program VCLK3 if needed. */
if (par->ProgramVCLK && ((vga_rgfx(NULL, 0x9B) != par->VCLK3NumeratorLow)
|| (vga_rgfx(NULL, 0x9F) != par->VCLK3Denominator)
|| (clock_hi && ((vga_rgfx(NULL, 0x8F) & ~0x0f)
!= (par->VCLK3NumeratorHigh &
~0x0F))))) {
vga_wgfx(NULL, 0x9B, par->VCLK3NumeratorLow);
if (clock_hi) {
temp = vga_rgfx(NULL, 0x8F);
temp &= 0x0F; /* Save bits 3:0 */
temp |= (par->VCLK3NumeratorHigh & ~0x0F);
vga_wgfx(NULL, 0x8F, temp);
}
vga_wgfx(NULL, 0x9F, par->VCLK3Denominator);
}
if (par->biosMode)
vga_wcrt(NULL, 0x23, par->biosMode);
vga_wgfx(NULL, 0x93, 0xc0); /* Gives 5x faster framebuffer writes !!! */
/* Program vertical extension register */
if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
vga_wcrt(NULL, 0x70, par->VerticalExt);
}
vgaHWProtect(0); /* Turn on screen */
/* Calling this also locks offset registers required in update_start */
neoLock(&par->state);
info->fix.line_length =
info->var.xres_virtual * (info->var.bits_per_pixel >> 3);
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
neo2200_accel_init(info, &info->var);
break;
default:
break;
}
return 0;
}
/*
* Pan or Wrap the Display
*/
static int neofb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct neofb_par *par = info->par;
struct vgastate *state = &par->state;
int oldExtCRTDispAddr;
int Base;
DBG("neofb_update_start");
Base = (var->yoffset * info->var.xres_virtual + var->xoffset) >> 2;
Base *= (info->var.bits_per_pixel + 7) / 8;
neoUnlock();
/*
* These are the generic starting address registers.
*/
vga_wcrt(state->vgabase, 0x0C, (Base & 0x00FF00) >> 8);
vga_wcrt(state->vgabase, 0x0D, (Base & 0x00FF));
/*
* Make sure we don't clobber some other bits that might already
* have been set. NOTE: NM2200 has a writable bit 3, but it shouldn't
* be needed.
*/
oldExtCRTDispAddr = vga_rgfx(NULL, 0x0E);
vga_wgfx(state->vgabase, 0x0E, (((Base >> 16) & 0x0f) | (oldExtCRTDispAddr & 0xf0)));
neoLock(state);
return 0;
}
static int neofb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *fb)
{
if (regno >= fb->cmap.len || regno > 255)
return -EINVAL;
if (fb->var.bits_per_pixel <= 8) {
outb(regno, 0x3c8);
outb(red >> 10, 0x3c9);
outb(green >> 10, 0x3c9);
outb(blue >> 10, 0x3c9);
} else if (regno < 16) {
switch (fb->var.bits_per_pixel) {
case 16:
((u32 *) fb->pseudo_palette)[regno] =
((red & 0xf800)) | ((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
break;
case 24:
((u32 *) fb->pseudo_palette)[regno] =
((red & 0xff00) << 8) | ((green & 0xff00)) |
((blue & 0xff00) >> 8);
break;
#ifdef NO_32BIT_SUPPORT_YET
case 32:
((u32 *) fb->pseudo_palette)[regno] =
((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
((green & 0xff00)) | ((blue & 0xff00) >> 8);
break;
#endif
default:
return 1;
}
}
return 0;
}
/*
* (Un)Blank the display.
*/
static int neofb_blank(int blank_mode, struct fb_info *info)
{
/*
* Blank the screen if blank_mode != 0, else unblank.
* Return 0 if blanking succeeded, != 0 if un-/blanking failed due to
* e.g. a video mode which doesn't support it. Implements VESA suspend
* and powerdown modes for monitors, and backlight control on LCDs.
* blank_mode == 0: unblanked (backlight on)
* blank_mode == 1: blank (backlight on)
* blank_mode == 2: suspend vsync (backlight off)
* blank_mode == 3: suspend hsync (backlight off)
* blank_mode == 4: powerdown (backlight off)
*
* wms...Enable VESA DPMS compatible powerdown mode
* run "setterm -powersave powerdown" to take advantage
*/
struct neofb_par *par = info->par;
int seqflags, lcdflags, dpmsflags, reg, tmpdisp;
/*
* Read back the register bits related to display configuration. They might
* have been changed underneath the driver via Fn key stroke.
*/
neoUnlock();
tmpdisp = vga_rgfx(NULL, 0x20) & 0x03;
neoLock(&par->state);
/* In case we blank the screen, we want to store the possibly new
* configuration in the driver. During un-blank, we re-apply this setting,
* since the LCD bit will be cleared in order to switch off the backlight.
*/
if (par->PanelDispCntlRegRead) {
par->PanelDispCntlReg1 = tmpdisp;
}
par->PanelDispCntlRegRead = !blank_mode;
switch (blank_mode) {
case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
lcdflags = 0; /* LCD off */
dpmsflags = NEO_GR01_SUPPRESS_HSYNC |
NEO_GR01_SUPPRESS_VSYNC;
#ifdef CONFIG_TOSHIBA
/* Do we still need this ? */
/* attempt to turn off backlight on toshiba; also turns off external */
{
SMMRegisters regs;
regs.eax = 0xff00; /* HCI_SET */
regs.ebx = 0x0002; /* HCI_BACKLIGHT */
regs.ecx = 0x0000; /* HCI_DISABLE */
tosh_smm(®s);
}
#endif
break;
case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
lcdflags = 0; /* LCD off */
dpmsflags = NEO_GR01_SUPPRESS_HSYNC;
break;
case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
lcdflags = 0; /* LCD off */
dpmsflags = NEO_GR01_SUPPRESS_VSYNC;
break;
case FB_BLANK_NORMAL: /* just blank screen (backlight stays on) */
seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
/*
* During a blank operation with the LID shut, we might store "LCD off"
* by mistake. Due to timing issues, the BIOS may switch the lights
* back on, and we turn it back off once we "unblank".
*
* So here is an attempt to implement ">=" - if we are in the process
* of unblanking, and the LCD bit is unset in the driver but set in the
* register, we must keep it.
*/
lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
dpmsflags = 0x00; /* no hsync/vsync suppression */
break;
case FB_BLANK_UNBLANK: /* unblank */
seqflags = 0; /* Enable sequencer */
lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
dpmsflags = 0x00; /* no hsync/vsync suppression */
#ifdef CONFIG_TOSHIBA
/* Do we still need this ? */
/* attempt to re-enable backlight/external on toshiba */
{
SMMRegisters regs;
regs.eax = 0xff00; /* HCI_SET */
regs.ebx = 0x0002; /* HCI_BACKLIGHT */
regs.ecx = 0x0001; /* HCI_ENABLE */
tosh_smm(®s);
}
#endif
break;
default: /* Anything else we don't understand; return 1 to tell
* fb_blank we didn't aactually do anything */
return 1;
}
neoUnlock();
reg = (vga_rseq(NULL, 0x01) & ~0x20) | seqflags;
vga_wseq(NULL, 0x01, reg);
reg = (vga_rgfx(NULL, 0x20) & ~0x02) | lcdflags;
vga_wgfx(NULL, 0x20, reg);
reg = (vga_rgfx(NULL, 0x01) & ~0xF0) | 0x80 | dpmsflags;
vga_wgfx(NULL, 0x01, reg);
neoLock(&par->state);
return 0;
}
static void
neo2200_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct neofb_par *par = info->par;
u_long dst, rop;
dst = rect->dx + rect->dy * info->var.xres_virtual;
rop = rect->rop ? 0x060000 : 0x0c0000;
neo2200_wait_fifo(info, 4);
/* set blt control */
writel(NEO_BC3_FIFO_EN |
NEO_BC0_SRC_IS_FG | NEO_BC3_SKIP_MAPPING |
// NEO_BC3_DST_XY_ADDR |
// NEO_BC3_SRC_XY_ADDR |
rop, &par->neo2200->bltCntl);
switch (info->var.bits_per_pixel) {
case 8:
writel(rect->color, &par->neo2200->fgColor);
break;
case 16:
case 24:
writel(((u32 *) (info->pseudo_palette))[rect->color],
&par->neo2200->fgColor);
break;
}
writel(dst * ((info->var.bits_per_pixel + 7) >> 3),
&par->neo2200->dstStart);
writel((rect->height << 16) | (rect->width & 0xffff),
&par->neo2200->xyExt);
}
static void
neo2200_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
struct neofb_par *par = info->par;
u_long src, dst, bltCntl;
bltCntl = NEO_BC3_FIFO_EN | NEO_BC3_SKIP_MAPPING | 0x0C0000;
if ((dy > sy) || ((dy == sy) && (dx > sx))) {
/* Start with the lower right corner */
sy += (area->height - 1);
dy += (area->height - 1);
sx += (area->width - 1);
dx += (area->width - 1);
bltCntl |= NEO_BC0_X_DEC | NEO_BC0_DST_Y_DEC | NEO_BC0_SRC_Y_DEC;
}
src = sx * (info->var.bits_per_pixel >> 3) + sy*info->fix.line_length;
dst = dx * (info->var.bits_per_pixel >> 3) + dy*info->fix.line_length;
neo2200_wait_fifo(info, 4);
/* set blt control */
writel(bltCntl, &par->neo2200->bltCntl);
writel(src, &par->neo2200->srcStart);
writel(dst, &par->neo2200->dstStart);
writel((area->height << 16) | (area->width & 0xffff),
&par->neo2200->xyExt);
}
static void
neo2200_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct neofb_par *par = info->par;
int s_pitch = (image->width * image->depth + 7) >> 3;
int scan_align = info->pixmap.scan_align - 1;
int buf_align = info->pixmap.buf_align - 1;
int bltCntl_flags, d_pitch, data_len;
// The data is padded for the hardware
d_pitch = (s_pitch + scan_align) & ~scan_align;
data_len = ((d_pitch * image->height) + buf_align) & ~buf_align;
neo2200_sync(info);
if (image->depth == 1) {
if (info->var.bits_per_pixel == 24 && image->width < 16) {
/* FIXME. There is a bug with accelerated color-expanded
* transfers in 24 bit mode if the image being transferred
* is less than 16 bits wide. This is due to insufficient
* padding when writing the image. We need to adjust
* struct fb_pixmap. Not yet done. */
cfb_imageblit(info, image);
return;
}
bltCntl_flags = NEO_BC0_SRC_MONO;
} else if (image->depth == info->var.bits_per_pixel) {
bltCntl_flags = 0;
} else {
/* We don't currently support hardware acceleration if image
* depth is different from display */
cfb_imageblit(info, image);
return;
}
switch (info->var.bits_per_pixel) {
case 8:
writel(image->fg_color, &par->neo2200->fgColor);
writel(image->bg_color, &par->neo2200->bgColor);
break;
case 16:
case 24:
writel(((u32 *) (info->pseudo_palette))[image->fg_color],
&par->neo2200->fgColor);
writel(((u32 *) (info->pseudo_palette))[image->bg_color],
&par->neo2200->bgColor);
break;
}
writel(NEO_BC0_SYS_TO_VID |
NEO_BC3_SKIP_MAPPING | bltCntl_flags |
// NEO_BC3_DST_XY_ADDR |
0x0c0000, &par->neo2200->bltCntl);
writel(0, &par->neo2200->srcStart);
// par->neo2200->dstStart = (image->dy << 16) | (image->dx & 0xffff);
writel(((image->dx & 0xffff) * (info->var.bits_per_pixel >> 3) +
image->dy * info->fix.line_length), &par->neo2200->dstStart);
writel((image->height << 16) | (image->width & 0xffff),
&par->neo2200->xyExt);
memcpy_toio(par->mmio_vbase + 0x100000, image->data, data_len);
}
static void
neofb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
neo2200_fillrect(info, rect);
break;
default:
cfb_fillrect(info, rect);
break;
}
}
static void
neofb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
neo2200_copyarea(info, area);
break;
default:
cfb_copyarea(info, area);
break;
}
}
static void
neofb_imageblit(struct fb_info *info, const struct fb_image *image)
{
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
neo2200_imageblit(info, image);
break;
default:
cfb_imageblit(info, image);
break;
}
}
static int
neofb_sync(struct fb_info *info)
{
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
neo2200_sync(info);
break;
default:
break;
}
return 0;
}
/*
static void
neofb_draw_cursor(struct fb_info *info, u8 *dst, u8 *src, unsigned int width)
{
//memset_io(info->sprite.addr, 0xff, 1);
}
static int
neofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct neofb_par *par = (struct neofb_par *) info->par;
* Disable cursor *
write_le32(NEOREG_CURSCNTL, ~NEO_CURS_ENABLE, par);
if (cursor->set & FB_CUR_SETPOS) {
u32 x = cursor->image.dx;
u32 y = cursor->image.dy;
info->cursor.image.dx = x;
info->cursor.image.dy = y;
write_le32(NEOREG_CURSX, x, par);
write_le32(NEOREG_CURSY, y, par);
}
if (cursor->set & FB_CUR_SETSIZE) {
info->cursor.image.height = cursor->image.height;
info->cursor.image.width = cursor->image.width;
}
if (cursor->set & FB_CUR_SETHOT)
info->cursor.hot = cursor->hot;
if (cursor->set & FB_CUR_SETCMAP) {
if (cursor->image.depth == 1) {
u32 fg = cursor->image.fg_color;
u32 bg = cursor->image.bg_color;
info->cursor.image.fg_color = fg;
info->cursor.image.bg_color = bg;
fg = ((fg & 0xff0000) >> 16) | ((fg & 0xff) << 16) | (fg & 0xff00);
bg = ((bg & 0xff0000) >> 16) | ((bg & 0xff) << 16) | (bg & 0xff00);
write_le32(NEOREG_CURSFGCOLOR, fg, par);
write_le32(NEOREG_CURSBGCOLOR, bg, par);
}
}
if (cursor->set & FB_CUR_SETSHAPE)
fb_load_cursor_image(info);
if (info->cursor.enable)
write_le32(NEOREG_CURSCNTL, NEO_CURS_ENABLE, par);
return 0;
}
*/
static const struct fb_ops neofb_ops = {
.owner = THIS_MODULE,
.fb_open = neofb_open,
.fb_release = neofb_release,
.fb_check_var = neofb_check_var,
.fb_set_par = neofb_set_par,
.fb_setcolreg = neofb_setcolreg,
.fb_pan_display = neofb_pan_display,
.fb_blank = neofb_blank,
.fb_sync = neofb_sync,
.fb_fillrect = neofb_fillrect,
.fb_copyarea = neofb_copyarea,
.fb_imageblit = neofb_imageblit,
};
/* --------------------------------------------------------------------- */
static struct fb_videomode mode800x480 = {
.xres = 800,
.yres = 480,
.pixclock = 25000,
.left_margin = 88,
.right_margin = 40,
.upper_margin = 23,
.lower_margin = 1,
.hsync_len = 128,
.vsync_len = 4,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static int neo_map_mmio(struct fb_info *info, struct pci_dev *dev)
{
struct neofb_par *par = info->par;
DBG("neo_map_mmio");
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2070:
info->fix.mmio_start = pci_resource_start(dev, 0)+
0x100000;
break;
case FB_ACCEL_NEOMAGIC_NM2090:
case FB_ACCEL_NEOMAGIC_NM2093:
info->fix.mmio_start = pci_resource_start(dev, 0)+
0x200000;
break;
case FB_ACCEL_NEOMAGIC_NM2160:
case FB_ACCEL_NEOMAGIC_NM2097:
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
info->fix.mmio_start = pci_resource_start(dev, 1);
break;
default:
info->fix.mmio_start = pci_resource_start(dev, 0);
}
info->fix.mmio_len = MMIO_SIZE;
if (!request_mem_region
(info->fix.mmio_start, MMIO_SIZE, "memory mapped I/O")) {
printk("neofb: memory mapped IO in use\n");
return -EBUSY;
}
par->mmio_vbase = ioremap(info->fix.mmio_start, MMIO_SIZE);
if (!par->mmio_vbase) {
printk("neofb: unable to map memory mapped IO\n");
release_mem_region(info->fix.mmio_start,
info->fix.mmio_len);
return -ENOMEM;
} else
printk(KERN_INFO "neofb: mapped io at %p\n",
par->mmio_vbase);
return 0;
}
static void neo_unmap_mmio(struct fb_info *info)
{
struct neofb_par *par = info->par;
DBG("neo_unmap_mmio");
iounmap(par->mmio_vbase);
par->mmio_vbase = NULL;
release_mem_region(info->fix.mmio_start,
info->fix.mmio_len);
}
static int neo_map_video(struct fb_info *info, struct pci_dev *dev,
int video_len)
{
//unsigned long addr;
struct neofb_par *par = info->par;
DBG("neo_map_video");
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = video_len;
if (!request_mem_region(info->fix.smem_start, info->fix.smem_len,
"frame buffer")) {
printk("neofb: frame buffer in use\n");
return -EBUSY;
}
info->screen_base =
ioremap_wc(info->fix.smem_start, info->fix.smem_len);
if (!info->screen_base) {
printk("neofb: unable to map screen memory\n");
release_mem_region(info->fix.smem_start,
info->fix.smem_len);
return -ENOMEM;
} else
printk(KERN_INFO "neofb: mapped framebuffer at %p\n",
info->screen_base);
par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
pci_resource_len(dev, 0));
/* Clear framebuffer, it's all white in memory after boot */
memset_io(info->screen_base, 0, info->fix.smem_len);
/* Allocate Cursor drawing pad.
info->fix.smem_len -= PAGE_SIZE;
addr = info->fix.smem_start + info->fix.smem_len;
write_le32(NEOREG_CURSMEMPOS, ((0x000f & (addr >> 10)) << 8) |
((0x0ff0 & (addr >> 10)) >> 4), par);
addr = (unsigned long) info->screen_base + info->fix.smem_len;
info->sprite.addr = (u8 *) addr; */
return 0;
}
static void neo_unmap_video(struct fb_info *info)
{
struct neofb_par *par = info->par;
DBG("neo_unmap_video");
arch_phys_wc_del(par->wc_cookie);
iounmap(info->screen_base);
info->screen_base = NULL;
release_mem_region(info->fix.smem_start,
info->fix.smem_len);
}
static int neo_scan_monitor(struct fb_info *info)
{
struct neofb_par *par = info->par;
unsigned char type, display;
int w;
// Eventually we will have i2c support.
info->monspecs.modedb = kmalloc(sizeof(struct fb_videomode), GFP_KERNEL);
if (!info->monspecs.modedb)
return -ENOMEM;
info->monspecs.modedb_len = 1;
/* Determine the panel type */
vga_wgfx(NULL, 0x09, 0x26);
type = vga_rgfx(NULL, 0x21);
display = vga_rgfx(NULL, 0x20);
if (!par->internal_display && !par->external_display) {
par->internal_display = display & 2 || !(display & 3) ? 1 : 0;
par->external_display = display & 1;
printk (KERN_INFO "Autodetected %s display\n",
par->internal_display && par->external_display ? "simultaneous" :
par->internal_display ? "internal" : "external");
}
/* Determine panel width -- used in NeoValidMode. */
w = vga_rgfx(NULL, 0x20);
vga_wgfx(NULL, 0x09, 0x00);
switch ((w & 0x18) >> 3) {
case 0x00:
// 640x480@60
par->NeoPanelWidth = 640;
par->NeoPanelHeight = 480;
memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
break;
case 0x01:
par->NeoPanelWidth = 800;
if (par->libretto) {
par->NeoPanelHeight = 480;
memcpy(info->monspecs.modedb, &mode800x480, sizeof(struct fb_videomode));
} else {
// 800x600@60
par->NeoPanelHeight = 600;
memcpy(info->monspecs.modedb, &vesa_modes[8], sizeof(struct fb_videomode));
}
break;
case 0x02:
// 1024x768@60
par->NeoPanelWidth = 1024;
par->NeoPanelHeight = 768;
memcpy(info->monspecs.modedb, &vesa_modes[13], sizeof(struct fb_videomode));
break;
case 0x03:
/* 1280x1024@60 panel support needs to be added */
#ifdef NOT_DONE
par->NeoPanelWidth = 1280;
par->NeoPanelHeight = 1024;
memcpy(info->monspecs.modedb, &vesa_modes[20], sizeof(struct fb_videomode));
break;
#else
printk(KERN_ERR
"neofb: Only 640x480, 800x600/480 and 1024x768 panels are currently supported\n");
kfree(info->monspecs.modedb);
return -1;
#endif
default:
// 640x480@60
par->NeoPanelWidth = 640;
par->NeoPanelHeight = 480;
memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
break;
}
printk(KERN_INFO "Panel is a %dx%d %s %s display\n",
par->NeoPanelWidth,
par->NeoPanelHeight,
(type & 0x02) ? "color" : "monochrome",
(type & 0x10) ? "TFT" : "dual scan");
return 0;
}
static int neo_init_hw(struct fb_info *info)
{
struct neofb_par *par = info->par;
int videoRam = 896;
int maxClock = 65000;
int CursorOff = 0x100;
DBG("neo_init_hw");
neoUnlock();
#if 0
printk(KERN_DEBUG "--- Neo extended register dump ---\n");
for (int w = 0; w < 0x85; w++)
printk(KERN_DEBUG "CR %p: %p\n", (void *) w,
(void *) vga_rcrt(NULL, w));
for (int w = 0; w < 0xC7; w++)
printk(KERN_DEBUG "GR %p: %p\n", (void *) w,
(void *) vga_rgfx(NULL, w));
#endif
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2070:
videoRam = 896;
maxClock = 65000;
break;
case FB_ACCEL_NEOMAGIC_NM2090:
case FB_ACCEL_NEOMAGIC_NM2093:
case FB_ACCEL_NEOMAGIC_NM2097:
videoRam = 1152;
maxClock = 80000;
break;
case FB_ACCEL_NEOMAGIC_NM2160:
videoRam = 2048;
maxClock = 90000;
break;
case FB_ACCEL_NEOMAGIC_NM2200:
videoRam = 2560;
maxClock = 110000;
break;
case FB_ACCEL_NEOMAGIC_NM2230:
videoRam = 3008;
maxClock = 110000;
break;
case FB_ACCEL_NEOMAGIC_NM2360:
videoRam = 4096;
maxClock = 110000;
break;
case FB_ACCEL_NEOMAGIC_NM2380:
videoRam = 6144;
maxClock = 110000;
break;
}
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2070:
case FB_ACCEL_NEOMAGIC_NM2090:
case FB_ACCEL_NEOMAGIC_NM2093:
CursorOff = 0x100;
break;
case FB_ACCEL_NEOMAGIC_NM2097:
case FB_ACCEL_NEOMAGIC_NM2160:
CursorOff = 0x100;
break;
case FB_ACCEL_NEOMAGIC_NM2200:
case FB_ACCEL_NEOMAGIC_NM2230:
case FB_ACCEL_NEOMAGIC_NM2360:
case FB_ACCEL_NEOMAGIC_NM2380:
CursorOff = 0x1000;
par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
break;
}
/*
info->sprite.size = CursorMem;
info->sprite.scan_align = 1;
info->sprite.buf_align = 1;
info->sprite.flags = FB_PIXMAP_IO;
info->sprite.outbuf = neofb_draw_cursor;
*/
par->maxClock = maxClock;
par->cursorOff = CursorOff;
return videoRam * 1024;
}
static struct fb_info *neo_alloc_fb_info(struct pci_dev *dev,
const struct pci_device_id *id)
{
struct fb_info *info;
struct neofb_par *par;
info = framebuffer_alloc(sizeof(struct neofb_par), &dev->dev);
if (!info)
return NULL;
par = info->par;
info->fix.accel = id->driver_data;
par->pci_burst = !nopciburst;
par->lcd_stretch = !nostretch;
par->libretto = libretto;
par->internal_display = internal;
par->external_display = external;
info->flags = FBINFO_HWACCEL_YPAN;
switch (info->fix.accel) {
case FB_ACCEL_NEOMAGIC_NM2070:
strscpy(info->fix.id, "MagicGraph128", sizeof(info->fix.id));
break;
case FB_ACCEL_NEOMAGIC_NM2090:
strscpy(info->fix.id, "MagicGraph128V", sizeof(info->fix.id));
break;
case FB_ACCEL_NEOMAGIC_NM2093:
strscpy(info->fix.id, "MagicGraph128ZV", sizeof(info->fix.id));
break;
case FB_ACCEL_NEOMAGIC_NM2097:
strscpy(info->fix.id, "Mag.Graph128ZV+", sizeof(info->fix.id));
break;
case FB_ACCEL_NEOMAGIC_NM2160:
strscpy(info->fix.id, "MagicGraph128XD", sizeof(info->fix.id));
break;
case FB_ACCEL_NEOMAGIC_NM2200:
strscpy(info->fix.id, "MagicGraph256AV", sizeof(info->fix.id));
info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT;
break;
case FB_ACCEL_NEOMAGIC_NM2230:
strscpy(info->fix.id, "Mag.Graph256AV+", sizeof(info->fix.id));
info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT;
break;
case FB_ACCEL_NEOMAGIC_NM2360:
strscpy(info->fix.id, "MagicGraph256ZX", sizeof(info->fix.id));
info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT;
break;
case FB_ACCEL_NEOMAGIC_NM2380:
strscpy(info->fix.id, "Mag.Graph256XL+", sizeof(info->fix.id));
info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT;
break;
}
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 4;
info->fix.ywrapstep = 0;
info->fix.accel = id->driver_data;
info->fbops = &neofb_ops;
info->pseudo_palette = par->palette;
return info;
}
static void neo_free_fb_info(struct fb_info *info)
{
if (info) {
/*
* Free the colourmap
*/
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
}
/* --------------------------------------------------------------------- */
static int neofb_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct fb_info *info;
u_int h_sync, v_sync;
int video_len, err;
DBG("neofb_probe");
err = aperture_remove_conflicting_pci_devices(dev, "neofb");
if (err)
return err;
err = pci_enable_device(dev);
if (err)
return err;
err = -ENOMEM;
info = neo_alloc_fb_info(dev, id);
if (!info)
return err;
err = neo_map_mmio(info, dev);
if (err)
goto err_map_mmio;
err = neo_scan_monitor(info);
if (err)
goto err_scan_monitor;
video_len = neo_init_hw(info);
if (video_len < 0) {
err = video_len;
goto err_init_hw;
}
err = neo_map_video(info, dev, video_len);
if (err)
goto err_init_hw;
if (!fb_find_mode(&info->var, info, mode_option, NULL, 0,
info->monspecs.modedb, 16)) {
printk(KERN_ERR "neofb: Unable to find usable video mode.\n");
err = -EINVAL;
goto err_map_video;
}
/*
* Calculate the hsync and vsync frequencies. Note that
* we split the 1e12 constant up so that we can preserve
* the precision and fit the results into 32-bit registers.
* (1953125000 * 512 = 1e12)
*/
h_sync = 1953125000 / info->var.pixclock;
h_sync =
h_sync * 512 / (info->var.xres + info->var.left_margin +
info->var.right_margin + info->var.hsync_len);
v_sync =
h_sync / (info->var.yres + info->var.upper_margin +
info->var.lower_margin + info->var.vsync_len);
printk(KERN_INFO "neofb v" NEOFB_VERSION
": %dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
info->fix.smem_len >> 10, info->var.xres,
info->var.yres, h_sync / 1000, h_sync % 1000, v_sync);
err = fb_alloc_cmap(&info->cmap, 256, 0);
if (err < 0)
goto err_map_video;
err = register_framebuffer(info);
if (err < 0)
goto err_reg_fb;
fb_info(info, "%s frame buffer device\n", info->fix.id);
/*
* Our driver data
*/
pci_set_drvdata(dev, info);
return 0;
err_reg_fb:
fb_dealloc_cmap(&info->cmap);
err_map_video:
neo_unmap_video(info);
err_init_hw:
fb_destroy_modedb(info->monspecs.modedb);
err_scan_monitor:
neo_unmap_mmio(info);
err_map_mmio:
neo_free_fb_info(info);
return err;
}
static void neofb_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
DBG("neofb_remove");
if (info) {
unregister_framebuffer(info);
neo_unmap_video(info);
fb_destroy_modedb(info->monspecs.modedb);
neo_unmap_mmio(info);
neo_free_fb_info(info);
}
}
static const struct pci_device_id neofb_devices[] = {
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2070,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2070},
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2090,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2090},
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2093,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2093},
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2097,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2097},
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2160,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2160},
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2200,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2200},
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2230,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2230},
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2360,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2360},
{PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2380,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2380},
{0, 0, 0, 0, 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, neofb_devices);
static struct pci_driver neofb_driver = {
.name = "neofb",
.id_table = neofb_devices,
.probe = neofb_probe,
.remove = neofb_remove,
};
/* ************************* init in-kernel code ************************** */
#ifndef MODULE
static int __init neofb_setup(char *options)
{
char *this_opt;
DBG("neofb_setup");
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strncmp(this_opt, "internal", 8))
internal = 1;
else if (!strncmp(this_opt, "external", 8))
external = 1;
else if (!strncmp(this_opt, "nostretch", 9))
nostretch = 1;
else if (!strncmp(this_opt, "nopciburst", 10))
nopciburst = 1;
else if (!strncmp(this_opt, "libretto", 8))
libretto = 1;
else
mode_option = this_opt;
}
return 0;
}
#endif /* MODULE */
static int __init neofb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("neofb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("neofb", &option))
return -ENODEV;
neofb_setup(option);
#endif
return pci_register_driver(&neofb_driver);
}
module_init(neofb_init);
#ifdef MODULE
static void __exit neofb_exit(void)
{
pci_unregister_driver(&neofb_driver);
}
module_exit(neofb_exit);
#endif /* MODULE */
| linux-master | drivers/video/fbdev/neofb.c |
/*
* linux/drivers/video/pxafb.c
*
* Copyright (C) 1999 Eric A. Thomas.
* Copyright (C) 2004 Jean-Frederic Clere.
* Copyright (C) 2004 Ian Campbell.
* Copyright (C) 2004 Jeff Lackey.
* Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
* which in turn is
* Based on acornfb.c Copyright (C) Russell King.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Intel PXA250/210 LCD Controller Frame Buffer Driver
*
* Please direct your questions and comments on this driver to the following
* email address:
*
* [email protected]
*
* Add support for overlay1 and overlay2 based on pxafb_overlay.c:
*
* Copyright (C) 2004, Intel Corporation
*
* 2003/08/27: <[email protected]>
* 2004/03/10: <[email protected]>
* 2004/10/28: <[email protected]>
*
* Copyright (C) 2006-2008 Marvell International Ltd.
* All Rights Reserved
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/completion.h>
#include <linux/mutex.h>
#include <linux/kthread.h>
#include <linux/freezer.h>
#include <linux/console.h>
#include <linux/of_graph.h>
#include <linux/regulator/consumer.h>
#include <linux/soc/pxa/cpu.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/div64.h>
#include <linux/platform_data/video-pxafb.h>
/*
* Complain if VAR is out of range.
*/
#define DEBUG_VAR 1
#include "pxafb.h"
#include "pxa3xx-regs.h"
/* Bits which should not be set in machine configuration structures */
#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
LCCR3_PCD | LCCR3_BPP(0xf))
static int pxafb_activate_var(struct fb_var_screeninfo *var,
struct pxafb_info *);
static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
static void setup_base_frame(struct pxafb_info *fbi,
struct fb_var_screeninfo *var, int branch);
static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
unsigned long offset, size_t size);
static unsigned long video_mem_size = 0;
static inline unsigned long
lcd_readl(struct pxafb_info *fbi, unsigned int off)
{
return __raw_readl(fbi->mmio_base + off);
}
static inline void
lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
{
__raw_writel(val, fbi->mmio_base + off);
}
static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
{
unsigned long flags;
local_irq_save(flags);
/*
* We need to handle two requests being made at the same time.
* There are two important cases:
* 1. When we are changing VT (C_REENABLE) while unblanking
* (C_ENABLE) We must perform the unblanking, which will
* do our REENABLE for us.
* 2. When we are blanking, but immediately unblank before
* we have blanked. We do the "REENABLE" thing here as
* well, just to be sure.
*/
if (fbi->task_state == C_ENABLE && state == C_REENABLE)
state = (u_int) -1;
if (fbi->task_state == C_DISABLE && state == C_ENABLE)
state = C_REENABLE;
if (state != (u_int)-1) {
fbi->task_state = state;
schedule_work(&fbi->task);
}
local_irq_restore(flags);
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int
pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
u_int val;
if (regno >= fbi->palette_size)
return 1;
if (fbi->fb.var.grayscale) {
fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
return 0;
}
switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
case LCCR4_PAL_FOR_0:
val = ((red >> 0) & 0xf800);
val |= ((green >> 5) & 0x07e0);
val |= ((blue >> 11) & 0x001f);
fbi->palette_cpu[regno] = val;
break;
case LCCR4_PAL_FOR_1:
val = ((red << 8) & 0x00f80000);
val |= ((green >> 0) & 0x0000fc00);
val |= ((blue >> 8) & 0x000000f8);
((u32 *)(fbi->palette_cpu))[regno] = val;
break;
case LCCR4_PAL_FOR_2:
val = ((red << 8) & 0x00fc0000);
val |= ((green >> 0) & 0x0000fc00);
val |= ((blue >> 8) & 0x000000fc);
((u32 *)(fbi->palette_cpu))[regno] = val;
break;
case LCCR4_PAL_FOR_3:
val = ((red << 8) & 0x00ff0000);
val |= ((green >> 0) & 0x0000ff00);
val |= ((blue >> 8) & 0x000000ff);
((u32 *)(fbi->palette_cpu))[regno] = val;
break;
}
return 0;
}
static int
pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
unsigned int val;
int ret = 1;
/*
* If inverse mode was selected, invert all the colours
* rather than the register number. The register number
* is what you poke into the framebuffer to produce the
* colour you requested.
*/
if (fbi->cmap_inverse) {
red = 0xffff - red;
green = 0xffff - green;
blue = 0xffff - blue;
}
/*
* If greyscale is true, then we convert the RGB value
* to greyscale no matter what visual we are using.
*/
if (fbi->fb.var.grayscale)
red = green = blue = (19595 * red + 38470 * green +
7471 * blue) >> 16;
switch (fbi->fb.fix.visual) {
case FB_VISUAL_TRUECOLOR:
/*
* 16-bit True Colour. We encode the RGB value
* according to the RGB bitfield information.
*/
if (regno < 16) {
u32 *pal = fbi->fb.pseudo_palette;
val = chan_to_field(red, &fbi->fb.var.red);
val |= chan_to_field(green, &fbi->fb.var.green);
val |= chan_to_field(blue, &fbi->fb.var.blue);
pal[regno] = val;
ret = 0;
}
break;
case FB_VISUAL_STATIC_PSEUDOCOLOR:
case FB_VISUAL_PSEUDOCOLOR:
ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
break;
}
return ret;
}
/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
static inline int var_to_depth(struct fb_var_screeninfo *var)
{
return var->red.length + var->green.length +
var->blue.length + var->transp.length;
}
/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
{
int bpp = -EINVAL;
switch (var->bits_per_pixel) {
case 1: bpp = 0; break;
case 2: bpp = 1; break;
case 4: bpp = 2; break;
case 8: bpp = 3; break;
case 16: bpp = 4; break;
case 24:
switch (var_to_depth(var)) {
case 18: bpp = 6; break; /* 18-bits/pixel packed */
case 19: bpp = 8; break; /* 19-bits/pixel packed */
case 24: bpp = 9; break;
}
break;
case 32:
switch (var_to_depth(var)) {
case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
case 25: bpp = 10; break;
}
break;
}
return bpp;
}
/*
* pxafb_var_to_lccr3():
* Convert a bits per pixel value to the correct bit pattern for LCCR3
*
* NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
* implication of the acutal use of transparency bit, which we handle it
* here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
* Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
*
* Transparency for palette pixel formats is not supported at the moment.
*/
static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
{
int bpp = pxafb_var_to_bpp(var);
uint32_t lccr3;
if (bpp < 0)
return 0;
lccr3 = LCCR3_BPP(bpp);
switch (var_to_depth(var)) {
case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
case 18: lccr3 |= LCCR3_PDFOR_3; break;
case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
break;
case 19:
case 25: lccr3 |= LCCR3_PDFOR_0; break;
}
return lccr3;
}
#define SET_PIXFMT(v, r, g, b, t) \
({ \
(v)->transp.offset = (t) ? (r) + (g) + (b) : 0; \
(v)->transp.length = (t) ? (t) : 0; \
(v)->blue.length = (b); (v)->blue.offset = 0; \
(v)->green.length = (g); (v)->green.offset = (b); \
(v)->red.length = (r); (v)->red.offset = (b) + (g); \
})
/* set the RGBT bitfields of fb_var_screeninf according to
* var->bits_per_pixel and given depth
*/
static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
{
if (depth == 0)
depth = var->bits_per_pixel;
if (var->bits_per_pixel < 16) {
/* indexed pixel formats */
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 8;
}
switch (depth) {
case 16: var->transp.length ?
SET_PIXFMT(var, 5, 5, 5, 1) : /* RGBT555 */
SET_PIXFMT(var, 5, 6, 5, 0); break; /* RGB565 */
case 18: SET_PIXFMT(var, 6, 6, 6, 0); break; /* RGB666 */
case 19: SET_PIXFMT(var, 6, 6, 6, 1); break; /* RGBT666 */
case 24: var->transp.length ?
SET_PIXFMT(var, 8, 8, 7, 1) : /* RGBT887 */
SET_PIXFMT(var, 8, 8, 8, 0); break; /* RGB888 */
case 25: SET_PIXFMT(var, 8, 8, 8, 1); break; /* RGBT888 */
}
}
#ifdef CONFIG_CPU_FREQ
/*
* pxafb_display_dma_period()
* Calculate the minimum period (in picoseconds) between two DMA
* requests for the LCD controller. If we hit this, it means we're
* doing nothing but LCD DMA.
*/
static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
{
/*
* Period = pixclock * bits_per_byte * bytes_per_transfer
* / memory_bits_per_pixel;
*/
return var->pixclock * 8 * 16 / var->bits_per_pixel;
}
#endif
/*
* Select the smallest mode that allows the desired resolution to be
* displayed. If desired parameters can be rounded up.
*/
static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
struct fb_var_screeninfo *var)
{
struct pxafb_mode_info *mode = NULL;
struct pxafb_mode_info *modelist = mach->modes;
unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
unsigned int i;
for (i = 0; i < mach->num_modes; i++) {
if (modelist[i].xres >= var->xres &&
modelist[i].yres >= var->yres &&
modelist[i].xres < best_x &&
modelist[i].yres < best_y &&
modelist[i].bpp >= var->bits_per_pixel) {
best_x = modelist[i].xres;
best_y = modelist[i].yres;
mode = &modelist[i];
}
}
return mode;
}
static void pxafb_setmode(struct fb_var_screeninfo *var,
struct pxafb_mode_info *mode)
{
var->xres = mode->xres;
var->yres = mode->yres;
var->bits_per_pixel = mode->bpp;
var->pixclock = mode->pixclock;
var->hsync_len = mode->hsync_len;
var->left_margin = mode->left_margin;
var->right_margin = mode->right_margin;
var->vsync_len = mode->vsync_len;
var->upper_margin = mode->upper_margin;
var->lower_margin = mode->lower_margin;
var->sync = mode->sync;
var->grayscale = mode->cmap_greyscale;
var->transp.length = mode->transparency;
/* set the initial RGBA bitfields */
pxafb_set_pixfmt(var, mode->depth);
}
static int pxafb_adjust_timing(struct pxafb_info *fbi,
struct fb_var_screeninfo *var)
{
int line_length;
var->xres = max_t(int, var->xres, MIN_XRES);
var->yres = max_t(int, var->yres, MIN_YRES);
if (!(fbi->lccr0 & LCCR0_LCDT)) {
clamp_val(var->hsync_len, 1, 64);
clamp_val(var->vsync_len, 1, 64);
clamp_val(var->left_margin, 1, 255);
clamp_val(var->right_margin, 1, 255);
clamp_val(var->upper_margin, 1, 255);
clamp_val(var->lower_margin, 1, 255);
}
/* make sure each line is aligned on word boundary */
line_length = var->xres * var->bits_per_pixel / 8;
line_length = ALIGN(line_length, 4);
var->xres = line_length * 8 / var->bits_per_pixel;
/* we don't support xpan, force xres_virtual to be equal to xres */
var->xres_virtual = var->xres;
if (var->accel_flags & FB_ACCELF_TEXT)
var->yres_virtual = fbi->fb.fix.smem_len / line_length;
else
var->yres_virtual = max(var->yres_virtual, var->yres);
/* check for limits */
if (var->xres > MAX_XRES || var->yres > MAX_YRES)
return -EINVAL;
if (var->yres > var->yres_virtual)
return -EINVAL;
return 0;
}
/*
* pxafb_check_var():
* Get the video params out of 'var'. If a value doesn't fit, round it up,
* if it's too big, return -EINVAL.
*
* Round up in the following order: bits_per_pixel, xres,
* yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
* bitfields, horizontal timing, vertical timing.
*/
static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
struct pxafb_mach_info *inf = fbi->inf;
int err;
if (inf->fixed_modes) {
struct pxafb_mode_info *mode;
mode = pxafb_getmode(inf, var);
if (!mode)
return -EINVAL;
pxafb_setmode(var, mode);
}
/* do a test conversion to BPP fields to check the color formats */
err = pxafb_var_to_bpp(var);
if (err < 0)
return err;
pxafb_set_pixfmt(var, var_to_depth(var));
err = pxafb_adjust_timing(fbi, var);
if (err)
return err;
#ifdef CONFIG_CPU_FREQ
pr_debug("pxafb: dma period = %d ps\n",
pxafb_display_dma_period(var));
#endif
return 0;
}
/*
* pxafb_set_par():
* Set the user defined part of the display for the specified console
*/
static int pxafb_set_par(struct fb_info *info)
{
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
struct fb_var_screeninfo *var = &info->var;
if (var->bits_per_pixel >= 16)
fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
else if (!fbi->cmap_static)
fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
else {
/*
* Some people have weird ideas about wanting static
* pseudocolor maps. I suspect their user space
* applications are broken.
*/
fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
}
fbi->fb.fix.line_length = var->xres_virtual *
var->bits_per_pixel / 8;
if (var->bits_per_pixel >= 16)
fbi->palette_size = 0;
else
fbi->palette_size = var->bits_per_pixel == 1 ?
4 : 1 << var->bits_per_pixel;
fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
if (fbi->fb.var.bits_per_pixel >= 16)
fb_dealloc_cmap(&fbi->fb.cmap);
else
fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
pxafb_activate_var(var, fbi);
return 0;
}
static int pxafb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
struct fb_var_screeninfo newvar;
int dma = DMA_MAX + DMA_BASE;
if (fbi->state != C_ENABLE)
return 0;
/* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
* was passed in and copy the rest from the old screeninfo.
*/
memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
newvar.xoffset = var->xoffset;
newvar.yoffset = var->yoffset;
newvar.vmode &= ~FB_VMODE_YWRAP;
newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
setup_base_frame(fbi, &newvar, 1);
if (fbi->lccr0 & LCCR0_SDS)
lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
return 0;
}
/*
* pxafb_blank():
* Blank the display by setting all palette values to zero. Note, the
* 16 bpp mode does not really use the palette, so this will not
* blank the display in all modes.
*/
static int pxafb_blank(int blank, struct fb_info *info)
{
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
int i;
switch (blank) {
case FB_BLANK_POWERDOWN:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_NORMAL:
if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
for (i = 0; i < fbi->palette_size; i++)
pxafb_setpalettereg(i, 0, 0, 0, 0, info);
pxafb_schedule_work(fbi, C_DISABLE);
/* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
break;
case FB_BLANK_UNBLANK:
/* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
fb_set_cmap(&fbi->fb.cmap, info);
pxafb_schedule_work(fbi, C_ENABLE);
}
return 0;
}
static const struct fb_ops pxafb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = pxafb_check_var,
.fb_set_par = pxafb_set_par,
.fb_pan_display = pxafb_pan_display,
.fb_setcolreg = pxafb_setcolreg,
.fb_blank = pxafb_blank,
};
#ifdef CONFIG_FB_PXA_OVERLAY
static void overlay1fb_setup(struct pxafb_layer *ofb)
{
int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
unsigned long start = ofb->video_mem_phys;
setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
}
/* Depending on the enable status of overlay1/2, the DMA should be
* updated from FDADRx (when disabled) or FBRx (when enabled).
*/
static void overlay1fb_enable(struct pxafb_layer *ofb)
{
int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
}
static void overlay1fb_disable(struct pxafb_layer *ofb)
{
uint32_t lccr5;
if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN))
return;
lccr5 = lcd_readl(ofb->fbi, LCCR5);
lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
pr_warn("%s: timeout disabling overlay1\n", __func__);
lcd_writel(ofb->fbi, LCCR5, lccr5);
}
static void overlay2fb_setup(struct pxafb_layer *ofb)
{
int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
} else {
size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
switch (pfor) {
case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
}
start[1] = start[0] + size;
start[2] = start[1] + size / div;
setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
}
}
static void overlay2fb_enable(struct pxafb_layer *ofb)
{
int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y] | (enabled ? 0x1 : 0);
uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
else {
lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
}
lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
}
static void overlay2fb_disable(struct pxafb_layer *ofb)
{
uint32_t lccr5;
if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN))
return;
lccr5 = lcd_readl(ofb->fbi, LCCR5);
lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y] | 0x3);
lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
pr_warn("%s: timeout disabling overlay2\n", __func__);
}
static struct pxafb_layer_ops ofb_ops[] = {
[0] = {
.enable = overlay1fb_enable,
.disable = overlay1fb_disable,
.setup = overlay1fb_setup,
},
[1] = {
.enable = overlay2fb_enable,
.disable = overlay2fb_disable,
.setup = overlay2fb_setup,
},
};
static int overlayfb_open(struct fb_info *info, int user)
{
struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
/* no support for framebuffer console on overlay */
if (user == 0)
return -ENODEV;
if (ofb->usage++ == 0) {
/* unblank the base framebuffer */
console_lock();
fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
console_unlock();
}
return 0;
}
static int overlayfb_release(struct fb_info *info, int user)
{
struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
if (ofb->usage == 1) {
ofb->ops->disable(ofb);
ofb->fb.var.height = -1;
ofb->fb.var.width = -1;
ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0;
ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0;
ofb->usage--;
}
return 0;
}
static int overlayfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
int xpos, ypos, pfor, bpp;
xpos = NONSTD_TO_XPOS(var->nonstd);
ypos = NONSTD_TO_YPOS(var->nonstd);
pfor = NONSTD_TO_PFOR(var->nonstd);
bpp = pxafb_var_to_bpp(var);
if (bpp < 0)
return -EINVAL;
/* no support for YUV format on overlay1 */
if (ofb->id == OVERLAY1 && pfor != 0)
return -EINVAL;
/* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
switch (pfor) {
case OVERLAY_FORMAT_RGB:
bpp = pxafb_var_to_bpp(var);
if (bpp < 0)
return -EINVAL;
pxafb_set_pixfmt(var, var_to_depth(var));
break;
case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
default:
return -EINVAL;
}
/* each line must start at a 32-bit word boundary */
if ((xpos * bpp) % 32)
return -EINVAL;
/* xres must align on 32-bit word boundary */
var->xres = roundup(var->xres * bpp, 32) / bpp;
if ((xpos + var->xres > base_var->xres) ||
(ypos + var->yres > base_var->yres))
return -EINVAL;
var->xres_virtual = var->xres;
var->yres_virtual = max(var->yres, var->yres_virtual);
return 0;
}
static int overlayfb_check_video_memory(struct pxafb_layer *ofb)
{
struct fb_var_screeninfo *var = &ofb->fb.var;
int pfor = NONSTD_TO_PFOR(var->nonstd);
int size, bpp = 0;
switch (pfor) {
case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
}
ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
if (ofb->video_mem) {
if (ofb->video_mem_size >= size)
return 0;
}
return -EINVAL;
}
static int overlayfb_set_par(struct fb_info *info)
{
struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
struct fb_var_screeninfo *var = &info->var;
int xpos, ypos, pfor, bpp, ret;
ret = overlayfb_check_video_memory(ofb);
if (ret)
return ret;
bpp = pxafb_var_to_bpp(var);
xpos = NONSTD_TO_XPOS(var->nonstd);
ypos = NONSTD_TO_YPOS(var->nonstd);
pfor = NONSTD_TO_PFOR(var->nonstd);
ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
OVLxC1_BPP(bpp);
ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
if (ofb->id == OVERLAY2)
ofb->control[1] |= OVL2C2_PFOR(pfor);
ofb->ops->setup(ofb);
ofb->ops->enable(ofb);
return 0;
}
static const struct fb_ops overlay_fb_ops = {
.owner = THIS_MODULE,
.fb_open = overlayfb_open,
.fb_release = overlayfb_release,
.fb_check_var = overlayfb_check_var,
.fb_set_par = overlayfb_set_par,
};
static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb,
int id)
{
sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
ofb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
ofb->fb.fix.xpanstep = 0;
ofb->fb.fix.ypanstep = 1;
ofb->fb.var.activate = FB_ACTIVATE_NOW;
ofb->fb.var.height = -1;
ofb->fb.var.width = -1;
ofb->fb.var.vmode = FB_VMODE_NONINTERLACED;
ofb->fb.fbops = &overlay_fb_ops;
ofb->fb.node = -1;
ofb->fb.pseudo_palette = NULL;
ofb->id = id;
ofb->ops = &ofb_ops[id];
ofb->usage = 0;
ofb->fbi = fbi;
init_completion(&ofb->branch_done);
}
static inline int pxafb_overlay_supported(void)
{
if (cpu_is_pxa27x() || cpu_is_pxa3xx())
return 1;
return 0;
}
static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb,
struct pxafb_layer *ofb)
{
/* We assume that user will use at most video_mem_size for overlay fb,
* anyway, it's useless to use 16bpp main plane and 24bpp overlay
*/
ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size),
GFP_KERNEL | __GFP_ZERO);
if (ofb->video_mem == NULL)
return -ENOMEM;
ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size);
mutex_lock(&ofb->fb.mm_lock);
ofb->fb.fix.smem_start = ofb->video_mem_phys;
ofb->fb.fix.smem_len = pxafb->video_mem_size;
mutex_unlock(&ofb->fb.mm_lock);
ofb->fb.screen_base = ofb->video_mem;
return 0;
}
static void pxafb_overlay_init(struct pxafb_info *fbi)
{
int i, ret;
if (!pxafb_overlay_supported())
return;
for (i = 0; i < 2; i++) {
struct pxafb_layer *ofb = &fbi->overlay[i];
init_pxafb_overlay(fbi, ofb, i);
ret = register_framebuffer(&ofb->fb);
if (ret) {
dev_err(fbi->dev, "failed to register overlay %d\n", i);
continue;
}
ret = pxafb_overlay_map_video_memory(fbi, ofb);
if (ret) {
dev_err(fbi->dev,
"failed to map video memory for overlay %d\n",
i);
unregister_framebuffer(&ofb->fb);
continue;
}
ofb->registered = 1;
}
/* mask all IU/BS/EOF/SOF interrupts */
lcd_writel(fbi, LCCR5, ~0);
pr_info("PXA Overlay driver loaded successfully!\n");
}
static void pxafb_overlay_exit(struct pxafb_info *fbi)
{
int i;
if (!pxafb_overlay_supported())
return;
for (i = 0; i < 2; i++) {
struct pxafb_layer *ofb = &fbi->overlay[i];
if (ofb->registered) {
if (ofb->video_mem)
free_pages_exact(ofb->video_mem,
ofb->video_mem_size);
unregister_framebuffer(&ofb->fb);
}
}
}
#else
static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
#endif /* CONFIG_FB_PXA_OVERLAY */
/*
* Calculate the PCD value from the clock rate (in picoseconds).
* We take account of the PPCR clock setting.
* From PXA Developer's Manual:
*
* PixelClock = LCLK
* -------------
* 2 ( PCD + 1 )
*
* PCD = LCLK
* ------------- - 1
* 2(PixelClock)
*
* Where:
* LCLK = LCD/Memory Clock
* PCD = LCCR3[7:0]
*
* PixelClock here is in Hz while the pixclock argument given is the
* period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
*
* The function get_lclk_frequency_10khz returns LCLK in units of
* 10khz. Calling the result of this function lclk gives us the
* following
*
* PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
* -------------------------------------- - 1
* 2
*
* Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
*/
static inline unsigned int get_pcd(struct pxafb_info *fbi,
unsigned int pixclock)
{
unsigned long long pcd;
/* FIXME: Need to take into account Double Pixel Clock mode
* (DPC) bit? or perhaps set it based on the various clock
* speeds */
pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
pcd *= pixclock;
do_div(pcd, 100000000 * 2);
/* no need for this, since we should subtract 1 anyway. they cancel */
/* pcd += 1; */ /* make up for integer math truncations */
return (unsigned int)pcd;
}
/*
* Some touchscreens need hsync information from the video driver to
* function correctly. We export it here. Note that 'hsync_time' and
* the value returned from pxafb_get_hsync_time() is the *reciprocal*
* of the hsync period in seconds.
*/
static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
{
unsigned long htime;
if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
fbi->hsync_time = 0;
return;
}
htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
fbi->hsync_time = htime;
}
unsigned long pxafb_get_hsync_time(struct device *dev)
{
struct pxafb_info *fbi = dev_get_drvdata(dev);
/* If display is blanked/suspended, hsync isn't active */
if (!fbi || (fbi->state != C_ENABLE))
return 0;
return fbi->hsync_time;
}
EXPORT_SYMBOL(pxafb_get_hsync_time);
static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
unsigned long start, size_t size)
{
struct pxafb_dma_descriptor *dma_desc, *pal_desc;
unsigned int dma_desc_off, pal_desc_off;
if (dma < 0 || dma >= DMA_MAX * 2)
return -EINVAL;
dma_desc = &fbi->dma_buff->dma_desc[dma];
dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
dma_desc->fsadr = start;
dma_desc->fidr = 0;
dma_desc->ldcmd = size;
if (pal < 0 || pal >= PAL_MAX * 2) {
dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
} else {
pal_desc = &fbi->dma_buff->pal_desc[pal];
pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
pal_desc->fidr = 0;
if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
else
pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
pal_desc->ldcmd |= LDCMD_PAL;
/* flip back and forth between palette and frame buffer */
pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
}
return 0;
}
static void setup_base_frame(struct pxafb_info *fbi,
struct fb_var_screeninfo *var,
int branch)
{
struct fb_fix_screeninfo *fix = &fbi->fb.fix;
int nbytes, dma, pal, bpp = var->bits_per_pixel;
unsigned long offset;
dma = DMA_BASE + (branch ? DMA_MAX : 0);
pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
nbytes = fix->line_length * var->yres;
offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
if (fbi->lccr0 & LCCR0_SDS) {
nbytes = nbytes / 2;
setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
}
setup_frame_dma(fbi, dma, pal, offset, nbytes);
}
#ifdef CONFIG_FB_PXA_SMARTPANEL
static int setup_smart_dma(struct pxafb_info *fbi)
{
struct pxafb_dma_descriptor *dma_desc;
unsigned long dma_desc_off, cmd_buff_off;
dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
dma_desc->fidr = 0;
dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
return 0;
}
int pxafb_smart_flush(struct fb_info *info)
{
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
uint32_t prsr;
int ret = 0;
/* disable controller until all registers are set up */
lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
/* 1. make it an even number of commands to align on 32-bit boundary
* 2. add the interrupt command to the end of the chain so we can
* keep track of the end of the transfer
*/
while (fbi->n_smart_cmds & 1)
fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
setup_smart_dma(fbi);
/* continue to execute next command */
prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
lcd_writel(fbi, PRSR, prsr);
/* stop the processor in case it executed "wait for sync" cmd */
lcd_writel(fbi, CMDCR, 0x0001);
/* don't send interrupts for fifo underruns on channel 6 */
lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
/* begin sending */
lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
pr_warn("%s: timeout waiting for command done\n", __func__);
ret = -ETIMEDOUT;
}
/* quick disable */
prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
lcd_writel(fbi, PRSR, prsr);
lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
lcd_writel(fbi, FDADR6, 0);
fbi->n_smart_cmds = 0;
return ret;
}
int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
{
int i;
struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
for (i = 0; i < n_cmds; i++, cmds++) {
/* if it is a software delay, flush and delay */
if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
pxafb_smart_flush(info);
mdelay(*cmds & 0xff);
continue;
}
/* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
pxafb_smart_flush(info);
fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
}
return 0;
}
static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
{
unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
return (t == 0) ? 1 : t;
}
static void setup_smart_timing(struct pxafb_info *fbi,
struct fb_var_screeninfo *var)
{
struct pxafb_mach_info *inf = fbi->inf;
struct pxafb_mode_info *mode = &inf->modes[0];
unsigned long lclk = clk_get_rate(fbi->clk);
unsigned t1, t2, t3, t4;
t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
t3 = mode->op_hold_time;
t4 = mode->cmd_inh_time;
fbi->reg_lccr1 =
LCCR1_DisWdth(var->xres) |
LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
/* FIXME: make this configurable */
fbi->reg_cmdcr = 1;
}
static int pxafb_smart_thread(void *arg)
{
struct pxafb_info *fbi = arg;
struct pxafb_mach_info *inf = fbi->inf;
if (!inf->smart_update) {
pr_err("%s: not properly initialized, thread terminated\n",
__func__);
return -EINVAL;
}
pr_debug("%s(): task starting\n", __func__);
set_freezable();
while (!kthread_should_stop()) {
if (try_to_freeze())
continue;
mutex_lock(&fbi->ctrlr_lock);
if (fbi->state == C_ENABLE) {
inf->smart_update(&fbi->fb);
complete(&fbi->refresh_done);
}
mutex_unlock(&fbi->ctrlr_lock);
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(msecs_to_jiffies(30));
}
pr_debug("%s(): task ending\n", __func__);
return 0;
}
static int pxafb_smart_init(struct pxafb_info *fbi)
{
if (!(fbi->lccr0 & LCCR0_LCDT))
return 0;
fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
fbi->n_smart_cmds = 0;
init_completion(&fbi->command_done);
init_completion(&fbi->refresh_done);
fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
"lcd_refresh");
if (IS_ERR(fbi->smart_thread)) {
pr_err("%s: unable to create kernel thread\n", __func__);
return PTR_ERR(fbi->smart_thread);
}
return 0;
}
#else
static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
#endif /* CONFIG_FB_PXA_SMARTPANEL */
static void setup_parallel_timing(struct pxafb_info *fbi,
struct fb_var_screeninfo *var)
{
unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
fbi->reg_lccr1 =
LCCR1_DisWdth(var->xres) +
LCCR1_HorSnchWdth(var->hsync_len) +
LCCR1_BegLnDel(var->left_margin) +
LCCR1_EndLnDel(var->right_margin);
/*
* If we have a dual scan LCD, we need to halve
* the YRES parameter.
*/
lines_per_panel = var->yres;
if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
lines_per_panel /= 2;
fbi->reg_lccr2 =
LCCR2_DisHght(lines_per_panel) +
LCCR2_VrtSnchWdth(var->vsync_len) +
LCCR2_BegFrmDel(var->upper_margin) +
LCCR2_EndFrmDel(var->lower_margin);
fbi->reg_lccr3 = fbi->lccr3 |
(var->sync & FB_SYNC_HOR_HIGH_ACT ?
LCCR3_HorSnchH : LCCR3_HorSnchL) |
(var->sync & FB_SYNC_VERT_HIGH_ACT ?
LCCR3_VrtSnchH : LCCR3_VrtSnchL);
if (pcd) {
fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
set_hsync_time(fbi, pcd);
}
}
/*
* pxafb_activate_var():
* Configures LCD Controller based on entries in var parameter.
* Settings are only written to the controller if changes were made.
*/
static int pxafb_activate_var(struct fb_var_screeninfo *var,
struct pxafb_info *fbi)
{
u_long flags;
/* Update shadow copy atomically */
local_irq_save(flags);
#ifdef CONFIG_FB_PXA_SMARTPANEL
if (fbi->lccr0 & LCCR0_LCDT)
setup_smart_timing(fbi, var);
else
#endif
setup_parallel_timing(fbi, var);
setup_base_frame(fbi, var, 0);
fbi->reg_lccr0 = fbi->lccr0 |
(LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
local_irq_restore(flags);
/*
* Only update the registers if the controller is enabled
* and something has changed.
*/
if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
(lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
(lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
(lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
(lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
(lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
((fbi->lccr0 & LCCR0_SDS) &&
(lcd_readl(fbi, FDADR1) != fbi->fdadr[1])))
pxafb_schedule_work(fbi, C_REENABLE);
return 0;
}
/*
* NOTE! The following functions are purely helpers for set_ctrlr_state.
* Do not call them directly; set_ctrlr_state does the correct serialisation
* to ensure that things happen in the right way 100% of time time.
* -- rmk
*/
static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
{
pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
if (fbi->backlight_power)
fbi->backlight_power(on);
}
static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
{
pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
if (fbi->lcd_power)
fbi->lcd_power(on, &fbi->fb.var);
if (fbi->lcd_supply && fbi->lcd_supply_enabled != on) {
int ret;
if (on)
ret = regulator_enable(fbi->lcd_supply);
else
ret = regulator_disable(fbi->lcd_supply);
if (ret < 0)
pr_warn("Unable to %s LCD supply regulator: %d\n",
on ? "enable" : "disable", ret);
else
fbi->lcd_supply_enabled = on;
}
}
static void pxafb_enable_controller(struct pxafb_info *fbi)
{
pr_debug("pxafb: Enabling LCD controller\n");
pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
/* enable LCD controller clock */
if (clk_prepare_enable(fbi->clk)) {
pr_err("%s: Failed to prepare clock\n", __func__);
return;
}
if (fbi->lccr0 & LCCR0_LCDT)
return;
/* Sequence from 11.7.10 */
lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
if (fbi->lccr0 & LCCR0_SDS)
lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
}
static void pxafb_disable_controller(struct pxafb_info *fbi)
{
uint32_t lccr0;
#ifdef CONFIG_FB_PXA_SMARTPANEL
if (fbi->lccr0 & LCCR0_LCDT) {
wait_for_completion_timeout(&fbi->refresh_done,
msecs_to_jiffies(200));
return;
}
#endif
/* Clear LCD Status Register */
lcd_writel(fbi, LCSR, 0xffffffff);
lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
lcd_writel(fbi, LCCR0, lccr0);
lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
wait_for_completion_timeout(&fbi->disable_done, msecs_to_jiffies(200));
/* disable LCD controller clock */
clk_disable_unprepare(fbi->clk);
}
/*
* pxafb_handle_irq: Handle 'LCD DONE' interrupts.
*/
static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
{
struct pxafb_info *fbi = dev_id;
unsigned int lccr0, lcsr;
lcsr = lcd_readl(fbi, LCSR);
if (lcsr & LCSR_LDD) {
lccr0 = lcd_readl(fbi, LCCR0);
lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
complete(&fbi->disable_done);
}
#ifdef CONFIG_FB_PXA_SMARTPANEL
if (lcsr & LCSR_CMD_INT)
complete(&fbi->command_done);
#endif
lcd_writel(fbi, LCSR, lcsr);
#ifdef CONFIG_FB_PXA_OVERLAY
{
unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
if (lcsr1 & LCSR1_BS(1))
complete(&fbi->overlay[0].branch_done);
if (lcsr1 & LCSR1_BS(2))
complete(&fbi->overlay[1].branch_done);
lcd_writel(fbi, LCSR1, lcsr1);
}
#endif
return IRQ_HANDLED;
}
/*
* This function must be called from task context only, since it will
* sleep when disabling the LCD controller, or if we get two contending
* processes trying to alter state.
*/
static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
{
u_int old_state;
mutex_lock(&fbi->ctrlr_lock);
old_state = fbi->state;
/*
* Hack around fbcon initialisation.
*/
if (old_state == C_STARTUP && state == C_REENABLE)
state = C_ENABLE;
switch (state) {
case C_DISABLE_CLKCHANGE:
/*
* Disable controller for clock change. If the
* controller is already disabled, then do nothing.
*/
if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
fbi->state = state;
/* TODO __pxafb_lcd_power(fbi, 0); */
pxafb_disable_controller(fbi);
}
break;
case C_DISABLE_PM:
case C_DISABLE:
/*
* Disable controller
*/
if (old_state != C_DISABLE) {
fbi->state = state;
__pxafb_backlight_power(fbi, 0);
__pxafb_lcd_power(fbi, 0);
if (old_state != C_DISABLE_CLKCHANGE)
pxafb_disable_controller(fbi);
}
break;
case C_ENABLE_CLKCHANGE:
/*
* Enable the controller after clock change. Only
* do this if we were disabled for the clock change.
*/
if (old_state == C_DISABLE_CLKCHANGE) {
fbi->state = C_ENABLE;
pxafb_enable_controller(fbi);
/* TODO __pxafb_lcd_power(fbi, 1); */
}
break;
case C_REENABLE:
/*
* Re-enable the controller only if it was already
* enabled. This is so we reprogram the control
* registers.
*/
if (old_state == C_ENABLE) {
__pxafb_lcd_power(fbi, 0);
pxafb_disable_controller(fbi);
pxafb_enable_controller(fbi);
__pxafb_lcd_power(fbi, 1);
}
break;
case C_ENABLE_PM:
/*
* Re-enable the controller after PM. This is not
* perfect - think about the case where we were doing
* a clock change, and we suspended half-way through.
*/
if (old_state != C_DISABLE_PM)
break;
fallthrough;
case C_ENABLE:
/*
* Power up the LCD screen, enable controller, and
* turn on the backlight.
*/
if (old_state != C_ENABLE) {
fbi->state = C_ENABLE;
pxafb_enable_controller(fbi);
__pxafb_lcd_power(fbi, 1);
__pxafb_backlight_power(fbi, 1);
}
break;
}
mutex_unlock(&fbi->ctrlr_lock);
}
/*
* Our LCD controller task (which is called when we blank or unblank)
* via keventd.
*/
static void pxafb_task(struct work_struct *work)
{
struct pxafb_info *fbi =
container_of(work, struct pxafb_info, task);
u_int state = xchg(&fbi->task_state, -1);
set_ctrlr_state(fbi, state);
}
#ifdef CONFIG_CPU_FREQ
/*
* CPU clock speed change handler. We need to adjust the LCD timing
* parameters when the CPU clock is adjusted by the power management
* subsystem.
*
* TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
*/
static int
pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
{
struct pxafb_info *fbi = TO_INF(nb, freq_transition);
/* TODO struct cpufreq_freqs *f = data; */
u_int pcd;
switch (val) {
case CPUFREQ_PRECHANGE:
#ifdef CONFIG_FB_PXA_OVERLAY
if (!(fbi->overlay[0].usage || fbi->overlay[1].usage))
#endif
set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
break;
case CPUFREQ_POSTCHANGE:
pcd = get_pcd(fbi, fbi->fb.var.pixclock);
set_hsync_time(fbi, pcd);
fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
LCCR3_PixClkDiv(pcd);
set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
break;
}
return 0;
}
#endif
#ifdef CONFIG_PM
/*
* Power management hooks. Note that we won't be called from IRQ context,
* unlike the blank functions above, so we may sleep.
*/
static int pxafb_suspend(struct device *dev)
{
struct pxafb_info *fbi = dev_get_drvdata(dev);
set_ctrlr_state(fbi, C_DISABLE_PM);
return 0;
}
static int pxafb_resume(struct device *dev)
{
struct pxafb_info *fbi = dev_get_drvdata(dev);
set_ctrlr_state(fbi, C_ENABLE_PM);
return 0;
}
static const struct dev_pm_ops pxafb_pm_ops = {
.suspend = pxafb_suspend,
.resume = pxafb_resume,
};
#endif
static int pxafb_init_video_memory(struct pxafb_info *fbi)
{
int size = PAGE_ALIGN(fbi->video_mem_size);
fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
if (fbi->video_mem == NULL)
return -ENOMEM;
fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
fbi->video_mem_size = size;
fbi->fb.fix.smem_start = fbi->video_mem_phys;
fbi->fb.fix.smem_len = fbi->video_mem_size;
fbi->fb.screen_base = fbi->video_mem;
return fbi->video_mem ? 0 : -ENOMEM;
}
static void pxafb_decode_mach_info(struct pxafb_info *fbi,
struct pxafb_mach_info *inf)
{
unsigned int lcd_conn = inf->lcd_conn;
struct pxafb_mode_info *m;
int i;
fbi->cmap_inverse = inf->cmap_inverse;
fbi->cmap_static = inf->cmap_static;
fbi->lccr4 = inf->lccr4;
switch (lcd_conn & LCD_TYPE_MASK) {
case LCD_TYPE_MONO_STN:
fbi->lccr0 = LCCR0_CMS;
break;
case LCD_TYPE_MONO_DSTN:
fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
break;
case LCD_TYPE_COLOR_STN:
fbi->lccr0 = 0;
break;
case LCD_TYPE_COLOR_DSTN:
fbi->lccr0 = LCCR0_SDS;
break;
case LCD_TYPE_COLOR_TFT:
fbi->lccr0 = LCCR0_PAS;
break;
case LCD_TYPE_SMART_PANEL:
fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
break;
default:
/* fall back to backward compatibility way */
fbi->lccr0 = inf->lccr0;
fbi->lccr3 = inf->lccr3;
goto decode_mode;
}
if (lcd_conn == LCD_MONO_STN_8BPP)
fbi->lccr0 |= LCCR0_DPD;
fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
decode_mode:
pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
/* decide video memory size as follows:
* 1. default to mode of maximum resolution
* 2. allow platform to override
* 3. allow module parameter to override
*/
for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
m->xres * m->yres * m->bpp / 8);
if (inf->video_mem_size > fbi->video_mem_size)
fbi->video_mem_size = inf->video_mem_size;
if (video_mem_size > fbi->video_mem_size)
fbi->video_mem_size = video_mem_size;
}
static struct pxafb_info *pxafb_init_fbinfo(struct device *dev,
struct pxafb_mach_info *inf)
{
struct pxafb_info *fbi;
void *addr;
/* Alloc the pxafb_info and pseudo_palette in one step */
fbi = devm_kzalloc(dev, sizeof(struct pxafb_info) + sizeof(u32) * 16,
GFP_KERNEL);
if (!fbi)
return ERR_PTR(-ENOMEM);
fbi->dev = dev;
fbi->inf = inf;
fbi->clk = devm_clk_get(dev, NULL);
if (IS_ERR(fbi->clk))
return ERR_CAST(fbi->clk);
strcpy(fbi->fb.fix.id, PXA_NAME);
fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fb.fix.type_aux = 0;
fbi->fb.fix.xpanstep = 0;
fbi->fb.fix.ypanstep = 1;
fbi->fb.fix.ywrapstep = 0;
fbi->fb.fix.accel = FB_ACCEL_NONE;
fbi->fb.var.nonstd = 0;
fbi->fb.var.activate = FB_ACTIVATE_NOW;
fbi->fb.var.height = -1;
fbi->fb.var.width = -1;
fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
fbi->fb.fbops = &pxafb_ops;
fbi->fb.node = -1;
addr = fbi;
addr = addr + sizeof(struct pxafb_info);
fbi->fb.pseudo_palette = addr;
fbi->state = C_STARTUP;
fbi->task_state = (u_char)-1;
pxafb_decode_mach_info(fbi, inf);
#ifdef CONFIG_FB_PXA_OVERLAY
/* place overlay(s) on top of base */
if (pxafb_overlay_supported())
fbi->lccr0 |= LCCR0_OUC;
#endif
init_waitqueue_head(&fbi->ctrlr_wait);
INIT_WORK(&fbi->task, pxafb_task);
mutex_init(&fbi->ctrlr_lock);
init_completion(&fbi->disable_done);
return fbi;
}
#ifdef CONFIG_FB_PXA_PARAMETERS
static int parse_opt_mode(struct device *dev, const char *this_opt,
struct pxafb_mach_info *inf)
{
const char *name = this_opt+5;
unsigned int namelen = strlen(name);
int res_specified = 0, bpp_specified = 0;
unsigned int xres = 0, yres = 0, bpp = 0;
int yres_specified = 0;
int i;
for (i = namelen-1; i >= 0; i--) {
switch (name[i]) {
case '-':
namelen = i;
if (!bpp_specified && !yres_specified) {
bpp = simple_strtoul(&name[i+1], NULL, 0);
bpp_specified = 1;
} else
goto done;
break;
case 'x':
if (!yres_specified) {
yres = simple_strtoul(&name[i+1], NULL, 0);
yres_specified = 1;
} else
goto done;
break;
case '0' ... '9':
break;
default:
goto done;
}
}
if (i < 0 && yres_specified) {
xres = simple_strtoul(name, NULL, 0);
res_specified = 1;
}
done:
if (res_specified) {
dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
inf->modes[0].xres = xres; inf->modes[0].yres = yres;
}
if (bpp_specified)
switch (bpp) {
case 1:
case 2:
case 4:
case 8:
case 16:
inf->modes[0].bpp = bpp;
dev_info(dev, "overriding bit depth: %d\n", bpp);
break;
default:
dev_err(dev, "Depth %d is not valid\n", bpp);
return -EINVAL;
}
return 0;
}
static int parse_opt(struct device *dev, char *this_opt,
struct pxafb_mach_info *inf)
{
struct pxafb_mode_info *mode = &inf->modes[0];
char s[64];
s[0] = '\0';
if (!strncmp(this_opt, "vmem:", 5)) {
video_mem_size = memparse(this_opt + 5, NULL);
} else if (!strncmp(this_opt, "mode:", 5)) {
return parse_opt_mode(dev, this_opt, inf);
} else if (!strncmp(this_opt, "pixclock:", 9)) {
mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
sprintf(s, "pixclock: %ld\n", mode->pixclock);
} else if (!strncmp(this_opt, "left:", 5)) {
mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
sprintf(s, "left: %u\n", mode->left_margin);
} else if (!strncmp(this_opt, "right:", 6)) {
mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
sprintf(s, "right: %u\n", mode->right_margin);
} else if (!strncmp(this_opt, "upper:", 6)) {
mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
sprintf(s, "upper: %u\n", mode->upper_margin);
} else if (!strncmp(this_opt, "lower:", 6)) {
mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
sprintf(s, "lower: %u\n", mode->lower_margin);
} else if (!strncmp(this_opt, "hsynclen:", 9)) {
mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
sprintf(s, "hsynclen: %u\n", mode->hsync_len);
} else if (!strncmp(this_opt, "vsynclen:", 9)) {
mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
sprintf(s, "vsynclen: %u\n", mode->vsync_len);
} else if (!strncmp(this_opt, "hsync:", 6)) {
if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
sprintf(s, "hsync: Active Low\n");
mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
} else {
sprintf(s, "hsync: Active High\n");
mode->sync |= FB_SYNC_HOR_HIGH_ACT;
}
} else if (!strncmp(this_opt, "vsync:", 6)) {
if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
sprintf(s, "vsync: Active Low\n");
mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
} else {
sprintf(s, "vsync: Active High\n");
mode->sync |= FB_SYNC_VERT_HIGH_ACT;
}
} else if (!strncmp(this_opt, "dpc:", 4)) {
if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
sprintf(s, "double pixel clock: false\n");
inf->lccr3 &= ~LCCR3_DPC;
} else {
sprintf(s, "double pixel clock: true\n");
inf->lccr3 |= LCCR3_DPC;
}
} else if (!strncmp(this_opt, "outputen:", 9)) {
if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
sprintf(s, "output enable: active low\n");
inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
} else {
sprintf(s, "output enable: active high\n");
inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
}
} else if (!strncmp(this_opt, "pixclockpol:", 12)) {
if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
sprintf(s, "pixel clock polarity: falling edge\n");
inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
} else {
sprintf(s, "pixel clock polarity: rising edge\n");
inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
}
} else if (!strncmp(this_opt, "color", 5)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
} else if (!strncmp(this_opt, "mono", 4)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
} else if (!strncmp(this_opt, "active", 6)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
} else if (!strncmp(this_opt, "passive", 7)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
} else if (!strncmp(this_opt, "single", 6)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
} else if (!strncmp(this_opt, "dual", 4)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
} else if (!strncmp(this_opt, "4pix", 4)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
} else if (!strncmp(this_opt, "8pix", 4)) {
inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
} else {
dev_err(dev, "unknown option: %s\n", this_opt);
return -EINVAL;
}
if (s[0] != '\0')
dev_info(dev, "override %s", s);
return 0;
}
static int pxafb_parse_options(struct device *dev, char *options,
struct pxafb_mach_info *inf)
{
char *this_opt;
int ret;
if (!options || !*options)
return 0;
dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
/* could be made table driven or similar?... */
while ((this_opt = strsep(&options, ",")) != NULL) {
ret = parse_opt(dev, this_opt, inf);
if (ret)
return ret;
}
return 0;
}
static char g_options[256] = "";
#ifndef MODULE
static int __init pxafb_setup_options(void)
{
char *options = NULL;
if (fb_get_options("pxafb", &options))
return -ENODEV;
if (options)
strscpy(g_options, options, sizeof(g_options));
return 0;
}
#else
#define pxafb_setup_options() (0)
module_param_string(options, g_options, sizeof(g_options), 0);
MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.rst)");
#endif
#else
#define pxafb_parse_options(...) (0)
#define pxafb_setup_options() (0)
#endif
#ifdef DEBUG_VAR
/* Check for various illegal bit-combinations. Currently only
* a warning is given. */
static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf)
{
if (inf->lcd_conn)
return;
if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
dev_warn(dev, "machine LCCR0 setting contains "
"illegal bits: %08x\n",
inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
dev_warn(dev, "machine LCCR3 setting contains "
"illegal bits: %08x\n",
inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
if (inf->lccr0 & LCCR0_DPD &&
((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
(inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
(inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
dev_warn(dev, "Double Pixel Data (DPD) mode is "
"only valid in passive mono"
" single panel mode\n");
if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
(inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
dev_warn(dev, "Dual panel only valid in passive mode\n");
if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
(inf->modes->upper_margin || inf->modes->lower_margin))
dev_warn(dev, "Upper and lower margins must be 0 in "
"passive mode\n");
}
#else
#define pxafb_check_options(...) do {} while (0)
#endif
#if defined(CONFIG_OF)
static const char * const lcd_types[] = {
"unknown", "mono-stn", "mono-dstn", "color-stn", "color-dstn",
"color-tft", "smart-panel", NULL
};
static int of_get_pxafb_display(struct device *dev, struct device_node *disp,
struct pxafb_mach_info *info, u32 bus_width)
{
struct display_timings *timings;
struct videomode vm;
int i, ret = -EINVAL;
const char *s;
ret = of_property_read_string(disp, "lcd-type", &s);
if (ret)
s = "color-tft";
i = match_string(lcd_types, -1, s);
if (i < 0) {
dev_err(dev, "lcd-type %s is unknown\n", s);
return i;
}
info->lcd_conn |= LCD_CONN_TYPE(i);
info->lcd_conn |= LCD_CONN_WIDTH(bus_width);
timings = of_get_display_timings(disp);
if (!timings)
return -EINVAL;
ret = -ENOMEM;
info->modes = devm_kcalloc(dev, timings->num_timings,
sizeof(info->modes[0]),
GFP_KERNEL);
if (!info->modes)
goto out;
info->num_modes = timings->num_timings;
for (i = 0; i < timings->num_timings; i++) {
ret = videomode_from_timings(timings, &vm, i);
if (ret) {
dev_err(dev, "videomode_from_timings %d failed: %d\n",
i, ret);
goto out;
}
if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
info->lcd_conn |= LCD_PCLK_EDGE_RISE;
if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
info->lcd_conn |= LCD_PCLK_EDGE_FALL;
if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
info->lcd_conn |= LCD_BIAS_ACTIVE_HIGH;
if (vm.flags & DISPLAY_FLAGS_DE_LOW)
info->lcd_conn |= LCD_BIAS_ACTIVE_LOW;
if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
info->modes[i].sync |= FB_SYNC_HOR_HIGH_ACT;
if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
info->modes[i].sync |= FB_SYNC_VERT_HIGH_ACT;
info->modes[i].pixclock = 1000000000UL / (vm.pixelclock / 1000);
info->modes[i].xres = vm.hactive;
info->modes[i].yres = vm.vactive;
info->modes[i].hsync_len = vm.hsync_len;
info->modes[i].left_margin = vm.hback_porch;
info->modes[i].right_margin = vm.hfront_porch;
info->modes[i].vsync_len = vm.vsync_len;
info->modes[i].upper_margin = vm.vback_porch;
info->modes[i].lower_margin = vm.vfront_porch;
}
ret = 0;
out:
display_timings_release(timings);
return ret;
}
static int of_get_pxafb_mode_info(struct device *dev,
struct pxafb_mach_info *info)
{
struct device_node *display, *np;
u32 bus_width;
int ret, i;
np = of_graph_get_next_endpoint(dev->of_node, NULL);
if (!np) {
dev_err(dev, "could not find endpoint\n");
return -EINVAL;
}
ret = of_property_read_u32(np, "bus-width", &bus_width);
if (ret) {
dev_err(dev, "no bus-width specified: %d\n", ret);
of_node_put(np);
return ret;
}
display = of_graph_get_remote_port_parent(np);
of_node_put(np);
if (!display) {
dev_err(dev, "no display defined\n");
return -EINVAL;
}
ret = of_get_pxafb_display(dev, display, info, bus_width);
of_node_put(display);
if (ret)
return ret;
for (i = 0; i < info->num_modes; i++)
info->modes[i].bpp = bus_width;
return 0;
}
static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
{
int ret;
struct pxafb_mach_info *info;
if (!dev->of_node)
return NULL;
info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
if (!info)
return ERR_PTR(-ENOMEM);
ret = of_get_pxafb_mode_info(dev, info);
if (ret)
return ERR_PTR(ret);
/*
* On purpose, neither lccrX registers nor video memory size can be
* specified through device-tree, they are considered more a debug hack
* available through command line.
*/
return info;
}
#else
static struct pxafb_mach_info *of_pxafb_of_mach_info(struct device *dev)
{
return NULL;
}
#endif
static int pxafb_probe(struct platform_device *dev)
{
struct pxafb_info *fbi;
struct pxafb_mach_info *inf, *pdata;
int i, irq, ret;
dev_dbg(&dev->dev, "pxafb_probe\n");
ret = -ENOMEM;
pdata = dev_get_platdata(&dev->dev);
inf = devm_kmalloc(&dev->dev, sizeof(*inf), GFP_KERNEL);
if (!inf)
goto failed;
if (pdata) {
*inf = *pdata;
inf->modes =
devm_kmalloc_array(&dev->dev, pdata->num_modes,
sizeof(inf->modes[0]), GFP_KERNEL);
if (!inf->modes)
goto failed;
for (i = 0; i < inf->num_modes; i++)
inf->modes[i] = pdata->modes[i];
} else {
inf = of_pxafb_of_mach_info(&dev->dev);
}
if (IS_ERR_OR_NULL(inf))
goto failed;
ret = pxafb_parse_options(&dev->dev, g_options, inf);
if (ret < 0)
goto failed;
pxafb_check_options(&dev->dev, inf);
dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
inf->modes->xres,
inf->modes->yres,
inf->modes->bpp);
if (inf->modes->xres == 0 ||
inf->modes->yres == 0 ||
inf->modes->bpp == 0) {
dev_err(&dev->dev, "Invalid resolution or bit depth\n");
ret = -EINVAL;
goto failed;
}
fbi = pxafb_init_fbinfo(&dev->dev, inf);
if (IS_ERR(fbi)) {
dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
ret = PTR_ERR(fbi);
goto failed;
}
if (cpu_is_pxa3xx() && inf->acceleration_enabled)
fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
fbi->backlight_power = inf->pxafb_backlight_power;
fbi->lcd_power = inf->pxafb_lcd_power;
fbi->lcd_supply = devm_regulator_get_optional(&dev->dev, "lcd");
if (IS_ERR(fbi->lcd_supply)) {
if (PTR_ERR(fbi->lcd_supply) == -EPROBE_DEFER)
return -EPROBE_DEFER;
fbi->lcd_supply = NULL;
}
fbi->mmio_base = devm_platform_ioremap_resource(dev, 0);
if (IS_ERR(fbi->mmio_base)) {
dev_err(&dev->dev, "failed to get I/O memory\n");
ret = PTR_ERR(fbi->mmio_base);
goto failed;
}
fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
&fbi->dma_buff_phys, GFP_KERNEL);
if (fbi->dma_buff == NULL) {
dev_err(&dev->dev, "failed to allocate memory for DMA\n");
ret = -ENOMEM;
goto failed;
}
ret = pxafb_init_video_memory(fbi);
if (ret) {
dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
ret = -ENOMEM;
goto failed_free_dma;
}
irq = platform_get_irq(dev, 0);
if (irq < 0) {
ret = -ENODEV;
goto failed_free_mem;
}
ret = devm_request_irq(&dev->dev, irq, pxafb_handle_irq, 0, "LCD", fbi);
if (ret) {
dev_err(&dev->dev, "request_irq failed: %d\n", ret);
ret = -EBUSY;
goto failed_free_mem;
}
ret = pxafb_smart_init(fbi);
if (ret) {
dev_err(&dev->dev, "failed to initialize smartpanel\n");
goto failed_free_mem;
}
/*
* This makes sure that our colour bitfield
* descriptors are correctly initialised.
*/
ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
if (ret) {
dev_err(&dev->dev, "failed to get suitable mode\n");
goto failed_free_mem;
}
ret = pxafb_set_par(&fbi->fb);
if (ret) {
dev_err(&dev->dev, "Failed to set parameters\n");
goto failed_free_mem;
}
platform_set_drvdata(dev, fbi);
ret = register_framebuffer(&fbi->fb);
if (ret < 0) {
dev_err(&dev->dev,
"Failed to register framebuffer device: %d\n", ret);
goto failed_free_cmap;
}
pxafb_overlay_init(fbi);
#ifdef CONFIG_CPU_FREQ
fbi->freq_transition.notifier_call = pxafb_freq_transition;
cpufreq_register_notifier(&fbi->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
#endif
/*
* Ok, now enable the LCD controller
*/
set_ctrlr_state(fbi, C_ENABLE);
return 0;
failed_free_cmap:
if (fbi->fb.cmap.len)
fb_dealloc_cmap(&fbi->fb.cmap);
failed_free_mem:
free_pages_exact(fbi->video_mem, fbi->video_mem_size);
failed_free_dma:
dma_free_coherent(&dev->dev, fbi->dma_buff_size,
fbi->dma_buff, fbi->dma_buff_phys);
failed:
return ret;
}
static void pxafb_remove(struct platform_device *dev)
{
struct pxafb_info *fbi = platform_get_drvdata(dev);
struct fb_info *info;
if (!fbi)
return;
info = &fbi->fb;
pxafb_overlay_exit(fbi);
unregister_framebuffer(info);
pxafb_disable_controller(fbi);
if (fbi->fb.cmap.len)
fb_dealloc_cmap(&fbi->fb.cmap);
free_pages_exact(fbi->video_mem, fbi->video_mem_size);
dma_free_coherent(&dev->dev, fbi->dma_buff_size, fbi->dma_buff,
fbi->dma_buff_phys);
}
static const struct of_device_id pxafb_of_dev_id[] = {
{ .compatible = "marvell,pxa270-lcdc", },
{ .compatible = "marvell,pxa300-lcdc", },
{ .compatible = "marvell,pxa2xx-lcdc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pxafb_of_dev_id);
static struct platform_driver pxafb_driver = {
.probe = pxafb_probe,
.remove_new = pxafb_remove,
.driver = {
.name = "pxa2xx-fb",
.of_match_table = pxafb_of_dev_id,
#ifdef CONFIG_PM
.pm = &pxafb_pm_ops,
#endif
},
};
static int __init pxafb_init(void)
{
if (pxafb_setup_options())
return -EINVAL;
return platform_driver_register(&pxafb_driver);
}
static void __exit pxafb_exit(void)
{
platform_driver_unregister(&pxafb_driver);
}
module_init(pxafb_init);
module_exit(pxafb_exit);
MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/pxafb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* i740fb - framebuffer driver for Intel740
* Copyright (c) 2011 Ondrej Zary
*
* Based on old i740fb driver (c) 2001-2002 Andrey Ulanov <[email protected]>
* which was partially based on:
* VGA 16-color framebuffer driver (c) 1999 Ben Pfaff <[email protected]>
* and Petr Vandrovec <[email protected]>
* i740 driver from XFree86 (c) 1998-1999 Precision Insight, Inc., Cedar Park,
* Texas.
* i740fb by Patrick LERDA, v0.9
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/console.h>
#include <video/vga.h>
#include "i740_reg.h"
static char *mode_option;
static int mtrr = 1;
struct i740fb_par {
unsigned char __iomem *regs;
bool has_sgram;
int wc_cookie;
bool ddc_registered;
struct i2c_adapter ddc_adapter;
struct i2c_algo_bit_data ddc_algo;
u32 pseudo_palette[16];
struct mutex open_lock;
unsigned int ref_count;
u8 crtc[VGA_CRT_C];
u8 atc[VGA_ATT_C];
u8 gdc[VGA_GFX_C];
u8 seq[VGA_SEQ_C];
u8 misc;
u8 vss;
/* i740 specific registers */
u8 display_cntl;
u8 pixelpipe_cfg0;
u8 pixelpipe_cfg1;
u8 pixelpipe_cfg2;
u8 video_clk2_m;
u8 video_clk2_n;
u8 video_clk2_mn_msbs;
u8 video_clk2_div_sel;
u8 pll_cntl;
u8 address_mapping;
u8 io_cntl;
u8 bitblt_cntl;
u8 ext_vert_total;
u8 ext_vert_disp_end;
u8 ext_vert_sync_start;
u8 ext_vert_blank_start;
u8 ext_horiz_total;
u8 ext_horiz_blank;
u8 ext_offset;
u8 interlace_cntl;
u32 lmi_fifo_watermark;
u8 ext_start_addr;
u8 ext_start_addr_hi;
};
#define DACSPEED8 203
#define DACSPEED16 163
#define DACSPEED24_SG 136
#define DACSPEED24_SD 128
#define DACSPEED32 86
static const struct fb_fix_screeninfo i740fb_fix = {
.id = "i740fb",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.xpanstep = 8,
.ypanstep = 1,
.accel = FB_ACCEL_NONE,
};
static inline void i740outb(struct i740fb_par *par, u16 port, u8 val)
{
vga_mm_w(par->regs, port, val);
}
static inline u8 i740inb(struct i740fb_par *par, u16 port)
{
return vga_mm_r(par->regs, port);
}
static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val)
{
vga_mm_w_fast(par->regs, port, reg, val);
}
static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg)
{
vga_mm_w(par->regs, port, reg);
return vga_mm_r(par->regs, port+1);
}
static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg,
u8 val, u8 mask)
{
vga_mm_w_fast(par->regs, port, reg, (val & mask)
| (i740inreg(par, port, reg) & ~mask));
}
#define REG_DDC_DRIVE 0x62
#define REG_DDC_STATE 0x63
#define DDC_SCL (1 << 3)
#define DDC_SDA (1 << 2)
static void i740fb_ddc_setscl(void *data, int val)
{
struct i740fb_par *par = data;
i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
}
static void i740fb_ddc_setsda(void *data, int val)
{
struct i740fb_par *par = data;
i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
}
static int i740fb_ddc_getscl(void *data)
{
struct i740fb_par *par = data;
i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
}
static int i740fb_ddc_getsda(void *data)
{
struct i740fb_par *par = data;
i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
}
static int i740fb_setup_ddc_bus(struct fb_info *info)
{
struct i740fb_par *par = info->par;
strscpy(par->ddc_adapter.name, info->fix.id,
sizeof(par->ddc_adapter.name));
par->ddc_adapter.owner = THIS_MODULE;
par->ddc_adapter.class = I2C_CLASS_DDC;
par->ddc_adapter.algo_data = &par->ddc_algo;
par->ddc_adapter.dev.parent = info->device;
par->ddc_algo.setsda = i740fb_ddc_setsda;
par->ddc_algo.setscl = i740fb_ddc_setscl;
par->ddc_algo.getsda = i740fb_ddc_getsda;
par->ddc_algo.getscl = i740fb_ddc_getscl;
par->ddc_algo.udelay = 10;
par->ddc_algo.timeout = 20;
par->ddc_algo.data = par;
i2c_set_adapdata(&par->ddc_adapter, par);
return i2c_bit_add_bus(&par->ddc_adapter);
}
static int i740fb_open(struct fb_info *info, int user)
{
struct i740fb_par *par = info->par;
mutex_lock(&(par->open_lock));
par->ref_count++;
mutex_unlock(&(par->open_lock));
return 0;
}
static int i740fb_release(struct fb_info *info, int user)
{
struct i740fb_par *par = info->par;
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
fb_err(info, "release called with zero refcount\n");
mutex_unlock(&(par->open_lock));
return -EINVAL;
}
par->ref_count--;
mutex_unlock(&(par->open_lock));
return 0;
}
static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp)
{
/*
* Would like to calculate these values automatically, but a generic
* algorithm does not seem possible. Note: These FIFO water mark
* values were tested on several cards and seem to eliminate the
* all of the snow and vertical banding, but fine adjustments will
* probably be required for other cards.
*/
u32 wm;
switch (bpp) {
case 8:
if (freq > 200)
wm = 0x18120000;
else if (freq > 175)
wm = 0x16110000;
else if (freq > 135)
wm = 0x120E0000;
else
wm = 0x100D0000;
break;
case 15:
case 16:
if (par->has_sgram) {
if (freq > 140)
wm = 0x2C1D0000;
else if (freq > 120)
wm = 0x2C180000;
else if (freq > 100)
wm = 0x24160000;
else if (freq > 90)
wm = 0x18120000;
else if (freq > 50)
wm = 0x16110000;
else if (freq > 32)
wm = 0x13100000;
else
wm = 0x120E0000;
} else {
if (freq > 160)
wm = 0x28200000;
else if (freq > 140)
wm = 0x2A1E0000;
else if (freq > 130)
wm = 0x2B1A0000;
else if (freq > 120)
wm = 0x2C180000;
else if (freq > 100)
wm = 0x24180000;
else if (freq > 90)
wm = 0x18120000;
else if (freq > 50)
wm = 0x16110000;
else if (freq > 32)
wm = 0x13100000;
else
wm = 0x120E0000;
}
break;
case 24:
if (par->has_sgram) {
if (freq > 130)
wm = 0x31200000;
else if (freq > 120)
wm = 0x2E200000;
else if (freq > 100)
wm = 0x2C1D0000;
else if (freq > 80)
wm = 0x25180000;
else if (freq > 64)
wm = 0x24160000;
else if (freq > 49)
wm = 0x18120000;
else if (freq > 32)
wm = 0x16110000;
else
wm = 0x13100000;
} else {
if (freq > 120)
wm = 0x311F0000;
else if (freq > 100)
wm = 0x2C1D0000;
else if (freq > 80)
wm = 0x25180000;
else if (freq > 64)
wm = 0x24160000;
else if (freq > 49)
wm = 0x18120000;
else if (freq > 32)
wm = 0x16110000;
else
wm = 0x13100000;
}
break;
case 32:
if (par->has_sgram) {
if (freq > 80)
wm = 0x2A200000;
else if (freq > 60)
wm = 0x281A0000;
else if (freq > 49)
wm = 0x25180000;
else if (freq > 32)
wm = 0x18120000;
else
wm = 0x16110000;
} else {
if (freq > 80)
wm = 0x29200000;
else if (freq > 60)
wm = 0x281A0000;
else if (freq > 49)
wm = 0x25180000;
else if (freq > 32)
wm = 0x18120000;
else
wm = 0x16110000;
}
break;
}
return wm;
}
/* clock calculation from i740fb by Patrick LERDA */
#define I740_RFREQ 1000000
#define TARGET_MAX_N 30
#define I740_FFIX (1 << 8)
#define I740_RFREQ_FIX (I740_RFREQ / I740_FFIX)
#define I740_REF_FREQ (6667 * I740_FFIX / 100) /* 66.67 MHz */
#define I740_MAX_VCO_FREQ (450 * I740_FFIX) /* 450 MHz */
static void i740_calc_vclk(u32 freq, struct i740fb_par *par)
{
const u32 err_max = freq / (200 * I740_RFREQ / I740_FFIX);
const u32 err_target = freq / (1000 * I740_RFREQ / I740_FFIX);
u32 err_best = 512 * I740_FFIX;
u32 f_err, f_vco;
int m_best = 0, n_best = 0, p_best = 0;
int m, n;
p_best = min(15, ilog2(I740_MAX_VCO_FREQ / (freq / I740_RFREQ_FIX)));
f_vco = (freq * (1 << p_best)) / I740_RFREQ_FIX;
freq = freq / I740_RFREQ_FIX;
n = 2;
do {
n++;
m = ((f_vco * n) / I740_REF_FREQ + 2) / 4;
if (m < 3)
m = 3;
{
u32 f_out = (((m * I740_REF_FREQ * 4)
/ n) + ((1 << p_best) / 2)) / (1 << p_best);
f_err = (freq - f_out);
if (abs(f_err) < err_max) {
m_best = m;
n_best = n;
err_best = f_err;
}
}
} while ((abs(f_err) >= err_target) &&
((n <= TARGET_MAX_N) || (abs(err_best) > err_max)));
if (abs(f_err) < err_target) {
m_best = m;
n_best = n;
}
par->video_clk2_m = (m_best - 2) & 0xFF;
par->video_clk2_n = (n_best - 2) & 0xFF;
par->video_clk2_mn_msbs = ((((n_best - 2) >> 4) & VCO_N_MSBS)
| (((m_best - 2) >> 8) & VCO_M_MSBS));
par->video_clk2_div_sel = ((p_best << 4) | REF_DIV_1);
}
static int i740fb_decode_var(const struct fb_var_screeninfo *var,
struct i740fb_par *par, struct fb_info *info)
{
/*
* Get the video params out of 'var'.
* If a value doesn't fit, round it up, if it's too big, return -EINVAL.
*/
u32 xres, right, hslen, left, xtotal;
u32 yres, lower, vslen, upper, ytotal;
u32 vxres, xoffset, vyres, yoffset;
u32 bpp, base, dacspeed24, mem, freq;
u8 r7;
int i;
dev_dbg(info->device, "decode_var: xres: %i, yres: %i, xres_v: %i, xres_v: %i\n",
var->xres, var->yres, var->xres_virtual, var->xres_virtual);
dev_dbg(info->device, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n",
var->xoffset, var->yoffset, var->bits_per_pixel,
var->grayscale);
dev_dbg(info->device, " activate: %i, nonstd: %i, vmode: %i\n",
var->activate, var->nonstd, var->vmode);
dev_dbg(info->device, " pixclock: %i, hsynclen:%i, vsynclen:%i\n",
var->pixclock, var->hsync_len, var->vsync_len);
dev_dbg(info->device, " left: %i, right: %i, up:%i, lower:%i\n",
var->left_margin, var->right_margin, var->upper_margin,
var->lower_margin);
bpp = var->bits_per_pixel;
switch (bpp) {
case 1 ... 8:
bpp = 8;
if ((1000000 / var->pixclock) > DACSPEED8) {
dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n",
1000000 / var->pixclock, DACSPEED8);
return -EINVAL;
}
break;
case 9 ... 15:
bpp = 15;
fallthrough;
case 16:
if ((1000000 / var->pixclock) > DACSPEED16) {
dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n",
1000000 / var->pixclock, DACSPEED16);
return -EINVAL;
}
break;
case 17 ... 24:
bpp = 24;
dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD;
if ((1000000 / var->pixclock) > dacspeed24) {
dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n",
1000000 / var->pixclock, dacspeed24);
return -EINVAL;
}
break;
case 25 ... 32:
bpp = 32;
if ((1000000 / var->pixclock) > DACSPEED32) {
dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n",
1000000 / var->pixclock, DACSPEED32);
return -EINVAL;
}
break;
default:
return -EINVAL;
}
xres = ALIGN(var->xres, 8);
vxres = ALIGN(var->xres_virtual, 16);
if (vxres < xres)
vxres = xres;
xoffset = ALIGN(var->xoffset, 8);
if (xres + xoffset > vxres)
xoffset = vxres - xres;
left = ALIGN(var->left_margin, 8);
right = ALIGN(var->right_margin, 8);
hslen = ALIGN(var->hsync_len, 8);
yres = var->yres;
vyres = var->yres_virtual;
if (yres > vyres)
vyres = yres;
yoffset = var->yoffset;
if (yres + yoffset > vyres)
yoffset = vyres - yres;
lower = var->lower_margin;
vslen = var->vsync_len;
upper = var->upper_margin;
mem = vxres * vyres * ((bpp + 1) / 8);
if (mem > info->screen_size) {
dev_err(info->device, "not enough video memory (%d KB requested, %ld KB available)\n",
mem >> 10, info->screen_size >> 10);
return -ENOMEM;
}
if (yoffset + yres > vyres)
yoffset = vyres - yres;
xtotal = xres + right + hslen + left;
ytotal = yres + lower + vslen + upper;
par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5;
par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1;
par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1;
par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3;
par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F)
| ((((xres + right + hslen) >> 3) & 0x20) << 2);
par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F)
| 0x80;
par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
r7 = 0x10; /* disable linecompare */
if (ytotal & 0x100)
r7 |= 0x01;
if (ytotal & 0x200)
r7 |= 0x20;
par->crtc[VGA_CRTC_PRESET_ROW] = 0;
par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */
if (var->vmode & FB_VMODE_DOUBLE)
par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
par->crtc[VGA_CRTC_CURSOR_START] = 0x00;
par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
par->crtc[VGA_CRTC_V_DISP_END] = yres-1;
if ((yres-1) & 0x100)
r7 |= 0x02;
if ((yres-1) & 0x200)
r7 |= 0x40;
par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1;
par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1;
if ((yres + lower - 1) & 0x100)
r7 |= 0x0C;
if ((yres + lower - 1) & 0x200) {
par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20;
r7 |= 0x80;
}
/* disabled IRQ */
par->crtc[VGA_CRTC_V_SYNC_END] =
((yres + lower - 1 + vslen) & 0x0F) & ~0x10;
/* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */
par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF;
par->crtc[VGA_CRTC_UNDERLINE] = 0x00;
par->crtc[VGA_CRTC_MODE] = 0xC3 ;
par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
par->crtc[VGA_CRTC_OVERFLOW] = r7;
par->vss = 0x00; /* 3DA */
for (i = 0x00; i < 0x10; i++)
par->atc[i] = i;
par->atc[VGA_ATC_MODE] = 0x81;
par->atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */
par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
par->atc[VGA_ATC_COLOR_PAGE] = 0x00;
par->misc = 0xC3;
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
par->misc &= ~0x40;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
par->misc &= ~0x80;
par->seq[VGA_SEQ_CLOCK_MODE] = 0x01;
par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
par->seq[VGA_SEQ_MEMORY_MODE] = 0x06;
par->gdc[VGA_GFX_SR_VALUE] = 0x00;
par->gdc[VGA_GFX_SR_ENABLE] = 0x00;
par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
par->gdc[VGA_GFX_DATA_ROTATE] = 0x00;
par->gdc[VGA_GFX_PLANE_READ] = 0;
par->gdc[VGA_GFX_MODE] = 0x02;
par->gdc[VGA_GFX_MISC] = 0x05;
par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
par->gdc[VGA_GFX_BIT_MASK] = 0xFF;
base = (yoffset * vxres + (xoffset & ~7)) >> 2;
switch (bpp) {
case 8:
par->crtc[VGA_CRTC_OFFSET] = vxres >> 3;
par->ext_offset = vxres >> 11;
par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE;
par->bitblt_cntl = COLEXP_8BPP;
break;
case 15: /* 0rrrrrgg gggbbbbb */
case 16: /* rrrrrggg gggbbbbb */
par->pixelpipe_cfg1 = (var->green.length == 6) ?
DISPLAY_16BPP_MODE : DISPLAY_15BPP_MODE;
par->crtc[VGA_CRTC_OFFSET] = vxres >> 2;
par->ext_offset = vxres >> 10;
par->bitblt_cntl = COLEXP_16BPP;
base *= 2;
break;
case 24:
par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3;
par->ext_offset = (vxres * 3) >> 11;
par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE;
par->bitblt_cntl = COLEXP_24BPP;
base &= 0xFFFFFFFE; /* ...ignore the last bit. */
base *= 3;
break;
case 32:
par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
par->ext_offset = vxres >> 9;
par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE;
par->bitblt_cntl = COLEXP_RESERVED; /* Unimplemented on i740 */
base *= 4;
break;
}
par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8;
par->ext_start_addr =
((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
par->pixelpipe_cfg0 = DAC_8_BIT;
par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE;
par->io_cntl = EXTENDED_CRTC_CNTL;
par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE;
par->display_cntl = HIRES_MODE;
/* Set the MCLK freq */
par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */
/* Calculate the extended CRTC regs */
par->ext_vert_total = (ytotal - 2) >> 8;
par->ext_vert_disp_end = (yres - 1) >> 8;
par->ext_vert_sync_start = (yres + lower) >> 8;
par->ext_vert_blank_start = (yres + lower) >> 8;
par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8;
par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6;
par->interlace_cntl = INTERLACE_DISABLE;
/* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */
par->atc[VGA_ATC_OVERSCAN] = 0;
/* Calculate VCLK that most closely matches the requested dot clock */
freq = (((u32)1e9) / var->pixclock) * (u32)(1e3);
if (freq < I740_RFREQ_FIX) {
fb_dbg(info, "invalid pixclock\n");
freq = I740_RFREQ_FIX;
}
i740_calc_vclk(freq, par);
/* Since we program the clocks ourselves, always use VCLK2. */
par->misc |= 0x0C;
/* Calculate the FIFO Watermark and Burst Length. */
par->lmi_fifo_watermark =
i740_calc_fifo(par, 1000000 / var->pixclock, bpp);
return 0;
}
static int i740fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (!var->pixclock)
return -EINVAL;
switch (var->bits_per_pixel) {
case 8:
var->red.offset = var->green.offset = var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = 8;
break;
case 16:
switch (var->green.length) {
default:
case 5:
var->red.offset = 10;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = 5;
var->green.length = 5;
var->blue.length = 5;
break;
case 6:
var->red.offset = 11;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = var->blue.length = 5;
break;
}
break;
case 24:
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = 8;
break;
case 32:
var->transp.offset = 24;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->transp.length = 8;
var->red.length = var->green.length = var->blue.length = 8;
break;
default:
return -EINVAL;
}
if (var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
if (info->monspecs.hfmax && info->monspecs.vfmax &&
info->monspecs.dclkmax && fb_validate_mode(var, info) < 0)
return -EINVAL;
return 0;
}
static void vga_protect(struct i740fb_par *par)
{
/* disable the display */
i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20);
i740inb(par, 0x3DA);
i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */
}
static void vga_unprotect(struct i740fb_par *par)
{
/* reenable display */
i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20);
i740inb(par, 0x3DA);
i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */
}
static int i740fb_set_par(struct fb_info *info)
{
struct i740fb_par *par = info->par;
u32 itemp;
int i;
i = i740fb_decode_var(&info->var, par, info);
if (i)
return i;
memset_io(info->screen_base, 0, info->screen_size);
vga_protect(par);
i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
mdelay(1);
i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
par->pixelpipe_cfg0 & DAC_8_BIT, 0x80);
i740inb(par, 0x3DA);
i740outb(par, 0x3C0, 0x00);
/* update misc output register */
i740outb(par, VGA_MIS_W, par->misc | 0x01);
/* synchronous reset on */
i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01);
/* write sequencer registers */
i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE,
par->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
for (i = 2; i < VGA_SEQ_C; i++)
i740outreg(par, VGA_SEQ_I, i, par->seq[i]);
/* synchronous reset off */
i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03);
/* deprotect CRT registers 0-7 */
i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END,
par->crtc[VGA_CRTC_V_SYNC_END]);
/* write CRT registers */
for (i = 0; i < VGA_CRT_C; i++)
i740outreg(par, VGA_CRT_IC, i, par->crtc[i]);
/* write graphics controller registers */
for (i = 0; i < VGA_GFX_C; i++)
i740outreg(par, VGA_GFX_I, i, par->gdc[i]);
/* write attribute controller registers */
for (i = 0; i < VGA_ATT_C; i++) {
i740inb(par, VGA_IS1_RC); /* reset flip-flop */
i740outb(par, VGA_ATT_IW, i);
i740outb(par, VGA_ATT_IW, par->atc[i]);
}
i740inb(par, VGA_IS1_RC);
i740outb(par, VGA_ATT_IW, 0x20);
i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total);
i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end);
i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START,
par->ext_vert_sync_start);
i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START,
par->ext_vert_blank_start);
i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total);
i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank);
i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset);
i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi);
i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr);
i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL,
par->interlace_cntl, INTERLACE_ENABLE);
i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
i740outreg_mask(par, XRX, DISPLAY_CNTL,
par->display_cntl, VGA_WRAP_MODE | GUI_MODE);
i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
par->pixelpipe_cfg1, DISPLAY_COLOR_MODE);
itemp = readl(par->regs + FWATER_BLC);
itemp &= ~(LMI_BURST_LENGTH | LMI_FIFO_WATERMARK);
itemp |= par->lmi_fifo_watermark;
writel(itemp, par->regs + FWATER_BLC);
i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);
i740outreg_mask(par, XRX, IO_CTNL,
par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL);
if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) {
i740outb(par, VGA_PEL_MSK, 0xFF);
i740outb(par, VGA_PEL_IW, 0x00);
for (i = 0; i < 256; i++) {
itemp = (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2;
i740outb(par, VGA_PEL_D, itemp);
i740outb(par, VGA_PEL_D, itemp);
i740outb(par, VGA_PEL_D, itemp);
}
}
/* Wait for screen to stabilize. */
mdelay(50);
vga_unprotect(par);
info->fix.line_length =
info->var.xres_virtual * info->var.bits_per_pixel / 8;
if (info->var.bits_per_pixel == 8)
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
else
info->fix.visual = FB_VISUAL_TRUECOLOR;
return 0;
}
static int i740fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
u32 r, g, b;
dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n",
regno, red, green, blue, transp, info->var.bits_per_pixel);
switch (info->fix.visual) {
case FB_VISUAL_PSEUDOCOLOR:
if (regno >= 256)
return -EINVAL;
i740outb(info->par, VGA_PEL_IW, regno);
i740outb(info->par, VGA_PEL_D, red >> 8);
i740outb(info->par, VGA_PEL_D, green >> 8);
i740outb(info->par, VGA_PEL_D, blue >> 8);
break;
case FB_VISUAL_TRUECOLOR:
if (regno >= 16)
return -EINVAL;
r = (red >> (16 - info->var.red.length))
<< info->var.red.offset;
b = (blue >> (16 - info->var.blue.length))
<< info->var.blue.offset;
g = (green >> (16 - info->var.green.length))
<< info->var.green.offset;
((u32 *) info->pseudo_palette)[regno] = r | g | b;
break;
default:
return -EINVAL;
}
return 0;
}
static int i740fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct i740fb_par *par = info->par;
u32 base = (var->yoffset * info->var.xres_virtual
+ (var->xoffset & ~7)) >> 2;
dev_dbg(info->device, "pan_display: xoffset: %i yoffset: %i base: %i\n",
var->xoffset, var->yoffset, base);
switch (info->var.bits_per_pixel) {
case 8:
break;
case 15:
case 16:
base *= 2;
break;
case 24:
/*
* The last bit does not seem to have any effect on the start
* address register in 24bpp mode, so...
*/
base &= 0xFFFFFFFE; /* ...ignore the last bit. */
base *= 3;
break;
case 32:
base *= 4;
break;
}
par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >> 8;
par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
par->ext_start_addr =
((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO, base & 0x000000FF);
i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI,
(base & 0x0000FF00) >> 8);
i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI,
(base & 0x3FC00000) >> 22);
i740outreg(par, VGA_CRT_IC, EXT_START_ADDR,
((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE);
return 0;
}
static int i740fb_blank(int blank_mode, struct fb_info *info)
{
struct i740fb_par *par = info->par;
unsigned char SEQ01;
int DPMSSyncSelect;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
SEQ01 = 0x00;
DPMSSyncSelect = HSYNC_ON | VSYNC_ON;
break;
case FB_BLANK_VSYNC_SUSPEND:
SEQ01 = 0x20;
DPMSSyncSelect = HSYNC_ON | VSYNC_OFF;
break;
case FB_BLANK_HSYNC_SUSPEND:
SEQ01 = 0x20;
DPMSSyncSelect = HSYNC_OFF | VSYNC_ON;
break;
case FB_BLANK_POWERDOWN:
SEQ01 = 0x20;
DPMSSyncSelect = HSYNC_OFF | VSYNC_OFF;
break;
default:
return -EINVAL;
}
/* Turn the screen on/off */
i740outb(par, SRX, 0x01);
SEQ01 |= i740inb(par, SRX + 1) & ~0x20;
i740outb(par, SRX, 0x01);
i740outb(par, SRX + 1, SEQ01);
/* Set the DPMS mode */
i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
/* Let fbcon do a soft blank for us */
return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
}
static const struct fb_ops i740fb_ops = {
.owner = THIS_MODULE,
.fb_open = i740fb_open,
.fb_release = i740fb_release,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = i740fb_check_var,
.fb_set_par = i740fb_set_par,
.fb_setcolreg = i740fb_setcolreg,
.fb_blank = i740fb_blank,
.fb_pan_display = i740fb_pan_display,
};
/* ------------------------------------------------------------------------- */
static int i740fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
{
struct fb_info *info;
struct i740fb_par *par;
int ret, tmp;
bool found = false;
u8 *edid;
ret = aperture_remove_conflicting_pci_devices(dev, "i740fb");
if (ret)
return ret;
info = framebuffer_alloc(sizeof(struct i740fb_par), &(dev->dev));
if (!info)
return -ENOMEM;
par = info->par;
mutex_init(&par->open_lock);
info->var.activate = FB_ACTIVATE_NOW;
info->var.bits_per_pixel = 8;
info->fbops = &i740fb_ops;
info->pseudo_palette = par->pseudo_palette;
ret = pci_enable_device(dev);
if (ret) {
dev_err(info->device, "cannot enable PCI device\n");
goto err_enable_device;
}
ret = pci_request_regions(dev, info->fix.id);
if (ret) {
dev_err(info->device, "error requesting regions\n");
goto err_request_regions;
}
info->screen_base = pci_ioremap_wc_bar(dev, 0);
if (!info->screen_base) {
dev_err(info->device, "error remapping base\n");
ret = -ENOMEM;
goto err_ioremap_1;
}
par->regs = pci_ioremap_bar(dev, 1);
if (!par->regs) {
dev_err(info->device, "error remapping MMIO\n");
ret = -ENOMEM;
goto err_ioremap_2;
}
/* detect memory size */
if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
== DRAM_ROW_1_SDRAM)
i740outb(par, XRX, DRAM_ROW_BNDRY_1);
else
i740outb(par, XRX, DRAM_ROW_BNDRY_0);
info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
/* detect memory type */
tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
par->has_sgram = !((tmp & DRAM_RAS_TIMING) ||
(tmp & DRAM_RAS_PRECHARGE));
fb_info(info, "Intel740 on %s, %ld KB %s\n",
pci_name(dev), info->screen_size >> 10,
par->has_sgram ? "SGRAM" : "SDRAM");
info->fix = i740fb_fix;
info->fix.mmio_start = pci_resource_start(dev, 1);
info->fix.mmio_len = pci_resource_len(dev, 1);
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = info->screen_size;
info->flags = FBINFO_HWACCEL_YPAN;
if (i740fb_setup_ddc_bus(info) == 0) {
par->ddc_registered = true;
edid = fb_ddc_read(&par->ddc_adapter);
if (edid) {
fb_edid_to_monspecs(edid, &info->monspecs);
kfree(edid);
if (!info->monspecs.modedb)
dev_err(info->device,
"error getting mode database\n");
else {
const struct fb_videomode *m;
fb_videomode_to_modelist(
info->monspecs.modedb,
info->monspecs.modedb_len,
&info->modelist);
m = fb_find_best_display(&info->monspecs,
&info->modelist);
if (m) {
fb_videomode_to_var(&info->var, m);
/* fill all other info->var's fields */
if (!i740fb_check_var(&info->var, info))
found = true;
}
}
}
}
if (!mode_option && !found)
mode_option = "640x480-8@60";
if (mode_option) {
ret = fb_find_mode(&info->var, info, mode_option,
info->monspecs.modedb,
info->monspecs.modedb_len,
NULL, info->var.bits_per_pixel);
if (!ret || ret == 4) {
dev_err(info->device, "mode %s not found\n",
mode_option);
ret = -EINVAL;
}
}
fb_destroy_modedb(info->monspecs.modedb);
info->monspecs.modedb = NULL;
/* maximize virtual vertical size for fast scrolling */
info->var.yres_virtual = info->fix.smem_len * 8 /
(info->var.bits_per_pixel * info->var.xres_virtual);
if (ret == -EINVAL)
goto err_find_mode;
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (ret) {
dev_err(info->device, "cannot allocate colormap\n");
goto err_alloc_cmap;
}
ret = register_framebuffer(info);
if (ret) {
dev_err(info->device, "error registering framebuffer\n");
goto err_reg_framebuffer;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
pci_set_drvdata(dev, info);
if (mtrr)
par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
info->fix.smem_len);
return 0;
err_reg_framebuffer:
fb_dealloc_cmap(&info->cmap);
err_alloc_cmap:
err_find_mode:
if (par->ddc_registered)
i2c_del_adapter(&par->ddc_adapter);
pci_iounmap(dev, par->regs);
err_ioremap_2:
pci_iounmap(dev, info->screen_base);
err_ioremap_1:
pci_release_regions(dev);
err_request_regions:
/* pci_disable_device(dev); */
err_enable_device:
framebuffer_release(info);
return ret;
}
static void i740fb_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
if (info) {
struct i740fb_par *par = info->par;
arch_phys_wc_del(par->wc_cookie);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
if (par->ddc_registered)
i2c_del_adapter(&par->ddc_adapter);
pci_iounmap(dev, par->regs);
pci_iounmap(dev, info->screen_base);
pci_release_regions(dev);
/* pci_disable_device(dev); */
framebuffer_release(info);
}
}
static int __maybe_unused i740fb_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct i740fb_par *par = info->par;
console_lock();
mutex_lock(&(par->open_lock));
/* do nothing if framebuffer is not active */
if (par->ref_count == 0) {
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
fb_set_suspend(info, 1);
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
static int __maybe_unused i740fb_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct i740fb_par *par = info->par;
console_lock();
mutex_lock(&(par->open_lock));
if (par->ref_count == 0)
goto fail;
i740fb_set_par(info);
fb_set_suspend(info, 0);
fail:
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
static const struct dev_pm_ops i740fb_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = i740fb_suspend,
.resume = i740fb_resume,
.freeze = NULL,
.thaw = i740fb_resume,
.poweroff = i740fb_suspend,
.restore = i740fb_resume,
#endif /* CONFIG_PM_SLEEP */
};
#define I740_ID_PCI 0x00d1
#define I740_ID_AGP 0x7800
static const struct pci_device_id i740fb_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) },
{ 0 }
};
MODULE_DEVICE_TABLE(pci, i740fb_id_table);
static struct pci_driver i740fb_driver = {
.name = "i740fb",
.id_table = i740fb_id_table,
.probe = i740fb_probe,
.remove = i740fb_remove,
.driver.pm = &i740fb_pm_ops,
};
#ifndef MODULE
static int __init i740fb_setup(char *options)
{
char *opt;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
else if (!strncmp(opt, "mtrr:", 5))
mtrr = simple_strtoul(opt + 5, NULL, 0);
else
mode_option = opt;
}
return 0;
}
#endif
static int __init i740fb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("i740fb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("i740fb", &option))
return -ENODEV;
i740fb_setup(option);
#endif
return pci_register_driver(&i740fb_driver);
}
static void __exit i740fb_exit(void)
{
pci_unregister_driver(&i740fb_driver);
}
module_init(i740fb_init);
module_exit(i740fb_exit);
MODULE_AUTHOR("(c) 2011 Ondrej Zary <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("fbdev driver for Intel740");
module_param(mode_option, charp, 0444);
MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
module_param(mtrr, int, 0444);
MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
| linux-master | drivers/video/fbdev/i740fb.c |
// SPDX-License-Identifier: GPL-2.0-only
/* bw2.c: BWTWO frame buffer driver
*
* Copyright (C) 2003, 2006 David S. Miller ([email protected])
* Copyright (C) 1996,1998 Jakub Jelinek ([email protected])
* Copyright (C) 1996 Miguel de Icaza ([email protected])
* Copyright (C) 1997 Eddie C. Dost ([email protected])
*
* Driver layout based loosely on tgafb.c, see that file for credits.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/fbio.h>
#include "sbuslib.h"
/*
* Local functions.
*/
static int bw2_blank(int, struct fb_info *);
static int bw2_mmap(struct fb_info *, struct vm_area_struct *);
static int bw2_ioctl(struct fb_info *, unsigned int, unsigned long);
/*
* Frame buffer operations
*/
static const struct fb_ops bw2_ops = {
.owner = THIS_MODULE,
.fb_blank = bw2_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = bw2_mmap,
.fb_ioctl = bw2_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = sbusfb_compat_ioctl,
#endif
};
/* OBio addresses for the bwtwo registers */
#define BWTWO_REGISTER_OFFSET 0x400000
struct bt_regs {
u32 addr;
u32 color_map;
u32 control;
u32 cursor;
};
struct bw2_regs {
struct bt_regs cmap;
u8 control;
u8 status;
u8 cursor_start;
u8 cursor_end;
u8 h_blank_start;
u8 h_blank_end;
u8 h_sync_start;
u8 h_sync_end;
u8 comp_sync_end;
u8 v_blank_start_high;
u8 v_blank_start_low;
u8 v_blank_end;
u8 v_sync_start;
u8 v_sync_end;
u8 xfer_holdoff_start;
u8 xfer_holdoff_end;
};
/* Status Register Constants */
#define BWTWO_SR_RES_MASK 0x70
#define BWTWO_SR_1600_1280 0x50
#define BWTWO_SR_1152_900_76_A 0x40
#define BWTWO_SR_1152_900_76_B 0x60
#define BWTWO_SR_ID_MASK 0x0f
#define BWTWO_SR_ID_MONO 0x02
#define BWTWO_SR_ID_MONO_ECL 0x03
#define BWTWO_SR_ID_MSYNC 0x04
#define BWTWO_SR_ID_NOCONN 0x0a
/* Control Register Constants */
#define BWTWO_CTL_ENABLE_INTS 0x80
#define BWTWO_CTL_ENABLE_VIDEO 0x40
#define BWTWO_CTL_ENABLE_TIMING 0x20
#define BWTWO_CTL_ENABLE_CURCMP 0x10
#define BWTWO_CTL_XTAL_MASK 0x0C
#define BWTWO_CTL_DIVISOR_MASK 0x03
/* Status Register Constants */
#define BWTWO_STAT_PENDING_INT 0x80
#define BWTWO_STAT_MSENSE_MASK 0x70
#define BWTWO_STAT_ID_MASK 0x0f
struct bw2_par {
spinlock_t lock;
struct bw2_regs __iomem *regs;
u32 flags;
#define BW2_FLAG_BLANKED 0x00000001
unsigned long which_io;
};
/**
* bw2_blank - Optional function. Blanks the display.
* @blank: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int
bw2_blank(int blank, struct fb_info *info)
{
struct bw2_par *par = (struct bw2_par *) info->par;
struct bw2_regs __iomem *regs = par->regs;
unsigned long flags;
u8 val;
spin_lock_irqsave(&par->lock, flags);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
val = sbus_readb(®s->control);
val |= BWTWO_CTL_ENABLE_VIDEO;
sbus_writeb(val, ®s->control);
par->flags &= ~BW2_FLAG_BLANKED;
break;
case FB_BLANK_NORMAL: /* Normal blanking */
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
case FB_BLANK_POWERDOWN: /* Poweroff */
val = sbus_readb(®s->control);
val &= ~BWTWO_CTL_ENABLE_VIDEO;
sbus_writeb(val, ®s->control);
par->flags |= BW2_FLAG_BLANKED;
break;
}
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
static struct sbus_mmap_map bw2_mmap_map[] = {
{
.size = SBUS_MMAP_FBSIZE(1)
},
{ .size = 0 }
};
static int bw2_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct bw2_par *par = (struct bw2_par *)info->par;
return sbusfb_mmap_helper(bw2_mmap_map,
info->fix.smem_start, info->fix.smem_len,
par->which_io,
vma);
}
static int bw2_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
return sbusfb_ioctl_helper(cmd, arg, info,
FBTYPE_SUN2BW, 1, info->fix.smem_len);
}
/*
* Initialisation
*/
static void bw2_init_fix(struct fb_info *info, int linebytes)
{
strscpy(info->fix.id, "bwtwo", sizeof(info->fix.id));
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_MONO01;
info->fix.line_length = linebytes;
info->fix.accel = FB_ACCEL_SUN_BWTWO;
}
static u8 bw2regs_1600[] = {
0x14, 0x8b, 0x15, 0x28, 0x16, 0x03, 0x17, 0x13,
0x18, 0x7b, 0x19, 0x05, 0x1a, 0x34, 0x1b, 0x2e,
0x1c, 0x00, 0x1d, 0x0a, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x21, 0
};
static u8 bw2regs_ecl[] = {
0x14, 0x65, 0x15, 0x1e, 0x16, 0x04, 0x17, 0x0c,
0x18, 0x5e, 0x19, 0x03, 0x1a, 0xa7, 0x1b, 0x23,
0x1c, 0x00, 0x1d, 0x08, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x20, 0
};
static u8 bw2regs_analog[] = {
0x14, 0xbb, 0x15, 0x2b, 0x16, 0x03, 0x17, 0x13,
0x18, 0xb0, 0x19, 0x03, 0x1a, 0xa6, 0x1b, 0x22,
0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x20, 0
};
static u8 bw2regs_76hz[] = {
0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x24, 0
};
static u8 bw2regs_66hz[] = {
0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x20, 0
};
static int bw2_do_default_mode(struct bw2_par *par, struct fb_info *info,
int *linebytes)
{
u8 status, mon;
u8 *p;
status = sbus_readb(&par->regs->status);
mon = status & BWTWO_SR_RES_MASK;
switch (status & BWTWO_SR_ID_MASK) {
case BWTWO_SR_ID_MONO_ECL:
if (mon == BWTWO_SR_1600_1280) {
p = bw2regs_1600;
info->var.xres = info->var.xres_virtual = 1600;
info->var.yres = info->var.yres_virtual = 1280;
*linebytes = 1600 / 8;
} else
p = bw2regs_ecl;
break;
case BWTWO_SR_ID_MONO:
p = bw2regs_analog;
break;
case BWTWO_SR_ID_MSYNC:
if (mon == BWTWO_SR_1152_900_76_A ||
mon == BWTWO_SR_1152_900_76_B)
p = bw2regs_76hz;
else
p = bw2regs_66hz;
break;
case BWTWO_SR_ID_NOCONN:
return 0;
default:
printk(KERN_ERR "bw2: can't handle SR %02x\n",
status);
return -EINVAL;
}
for ( ; *p; p += 2) {
u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
sbus_writeb(p[1], regp);
}
return 0;
}
static int bw2_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct fb_info *info;
struct bw2_par *par;
int linebytes, err;
info = framebuffer_alloc(sizeof(struct bw2_par), &op->dev);
err = -ENOMEM;
if (!info)
goto out_err;
par = info->par;
spin_lock_init(&par->lock);
info->fix.smem_start = op->resource[0].start;
par->which_io = op->resource[0].flags & IORESOURCE_BITS;
sbusfb_fill_var(&info->var, dp, 1);
linebytes = of_getintprop_default(dp, "linebytes",
info->var.xres);
info->var.red.length = info->var.green.length =
info->var.blue.length = info->var.bits_per_pixel;
info->var.red.offset = info->var.green.offset =
info->var.blue.offset = 0;
par->regs = of_ioremap(&op->resource[0], BWTWO_REGISTER_OFFSET,
sizeof(struct bw2_regs), "bw2 regs");
if (!par->regs)
goto out_release_fb;
if (!of_property_present(dp, "width")) {
err = bw2_do_default_mode(par, info, &linebytes);
if (err)
goto out_unmap_regs;
}
info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
info->fbops = &bw2_ops;
info->screen_base = of_ioremap(&op->resource[0], 0,
info->fix.smem_len, "bw2 ram");
if (!info->screen_base) {
err = -ENOMEM;
goto out_unmap_regs;
}
bw2_blank(FB_BLANK_UNBLANK, info);
bw2_init_fix(info, linebytes);
err = register_framebuffer(info);
if (err < 0)
goto out_unmap_screen;
dev_set_drvdata(&op->dev, info);
printk(KERN_INFO "%pOF: bwtwo at %lx:%lx\n",
dp, par->which_io, info->fix.smem_start);
return 0;
out_unmap_screen:
of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
out_unmap_regs:
of_iounmap(&op->resource[0], par->regs, sizeof(struct bw2_regs));
out_release_fb:
framebuffer_release(info);
out_err:
return err;
}
static void bw2_remove(struct platform_device *op)
{
struct fb_info *info = dev_get_drvdata(&op->dev);
struct bw2_par *par = info->par;
unregister_framebuffer(info);
of_iounmap(&op->resource[0], par->regs, sizeof(struct bw2_regs));
of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
framebuffer_release(info);
}
static const struct of_device_id bw2_match[] = {
{
.name = "bwtwo",
},
{},
};
MODULE_DEVICE_TABLE(of, bw2_match);
static struct platform_driver bw2_driver = {
.driver = {
.name = "bw2",
.of_match_table = bw2_match,
},
.probe = bw2_probe,
.remove_new = bw2_remove,
};
static int __init bw2_init(void)
{
if (fb_get_options("bw2fb", NULL))
return -ENODEV;
return platform_driver_register(&bw2_driver);
}
static void __exit bw2_exit(void)
{
platform_driver_unregister(&bw2_driver);
}
module_init(bw2_init);
module_exit(bw2_exit);
MODULE_DESCRIPTION("framebuffer driver for BWTWO chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/bw2.c |
/*
* linux/drivers/video/hgafb.c -- Hercules graphics adaptor frame buffer device
*
* Created 25 Nov 1999 by Ferenc Bakonyi ([email protected])
* Based on skeletonfb.c by Geert Uytterhoeven and
* mdacon.c by Andrew Apted
*
* History:
*
* - Revision 0.1.8 (23 Oct 2002): Ported to new framebuffer api.
*
* - Revision 0.1.7 (23 Jan 2001): fix crash resulting from MDA only cards
* being detected as Hercules. (Paul G.)
* - Revision 0.1.6 (17 Aug 2000): new style structs
* documentation
* - Revision 0.1.5 (13 Mar 2000): spinlocks instead of saveflags();cli();etc
* minor fixes
* - Revision 0.1.4 (24 Jan 2000): fixed a bug in hga_card_detect() for
* HGA-only systems
* - Revision 0.1.3 (22 Jan 2000): modified for the new fb_info structure
* screen is cleared after rmmod
* virtual resolutions
* module parameter 'nologo={0|1}'
* the most important: boot logo :)
* - Revision 0.1.0 (6 Dec 1999): faster scrolling and minor fixes
* - First release (25 Nov 1999)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/vga.h>
#if 0
#define DPRINTK(args...) printk(KERN_DEBUG __FILE__": " ##args)
#else
#define DPRINTK(args...)
#endif
#if 0
#define CHKINFO(ret) if (info != &fb_info) { printk(KERN_DEBUG __FILE__": This should never happen, line:%d \n", __LINE__); return ret; }
#else
#define CHKINFO(ret)
#endif
/* Description of the hardware layout */
static void __iomem *hga_vram; /* Base of video memory */
static unsigned long hga_vram_len; /* Size of video memory */
#define HGA_ROWADDR(row) ((row%4)*8192 + (row>>2)*90)
#define HGA_TXT 0
#define HGA_GFX 1
static inline u8 __iomem * rowaddr(struct fb_info *info, u_int row)
{
return info->screen_base + HGA_ROWADDR(row);
}
static int hga_mode = -1; /* 0 = txt, 1 = gfx mode */
static enum { TYPE_HERC, TYPE_HERCPLUS, TYPE_HERCCOLOR } hga_type;
static char *hga_type_name;
#define HGA_INDEX_PORT 0x3b4 /* Register select port */
#define HGA_VALUE_PORT 0x3b5 /* Register value port */
#define HGA_MODE_PORT 0x3b8 /* Mode control port */
#define HGA_STATUS_PORT 0x3ba /* Status and Config port */
#define HGA_GFX_PORT 0x3bf /* Graphics control port */
/* HGA register values */
#define HGA_CURSOR_BLINKING 0x00
#define HGA_CURSOR_OFF 0x20
#define HGA_CURSOR_SLOWBLINK 0x60
#define HGA_MODE_GRAPHICS 0x02
#define HGA_MODE_VIDEO_EN 0x08
#define HGA_MODE_BLINK_EN 0x20
#define HGA_MODE_GFX_PAGE1 0x80
#define HGA_STATUS_HSYNC 0x01
#define HGA_STATUS_VSYNC 0x80
#define HGA_STATUS_VIDEO 0x08
#define HGA_CONFIG_COL132 0x08
#define HGA_GFX_MODE_EN 0x01
#define HGA_GFX_PAGE_EN 0x02
/* Global locks */
static DEFINE_SPINLOCK(hga_reg_lock);
/* Framebuffer driver structures */
static const struct fb_var_screeninfo hga_default_var = {
.xres = 720,
.yres = 348,
.xres_virtual = 720,
.yres_virtual = 348,
.bits_per_pixel = 1,
.red = {0, 1, 0},
.green = {0, 1, 0},
.blue = {0, 1, 0},
.transp = {0, 0, 0},
.height = -1,
.width = -1,
};
static struct fb_fix_screeninfo hga_fix = {
.id = "HGA",
.type = FB_TYPE_PACKED_PIXELS, /* (not sure) */
.visual = FB_VISUAL_MONO10,
.xpanstep = 8,
.ypanstep = 8,
.line_length = 90,
.accel = FB_ACCEL_NONE
};
/* Don't assume that tty1 will be the initial current console. */
static int release_io_port = 0;
static int release_io_ports = 0;
static bool nologo = 0;
/* -------------------------------------------------------------------------
*
* Low level hardware functions
*
* ------------------------------------------------------------------------- */
static void write_hga_b(unsigned int val, unsigned char reg)
{
outb_p(reg, HGA_INDEX_PORT);
outb_p(val, HGA_VALUE_PORT);
}
static void write_hga_w(unsigned int val, unsigned char reg)
{
outb_p(reg, HGA_INDEX_PORT); outb_p(val >> 8, HGA_VALUE_PORT);
outb_p(reg+1, HGA_INDEX_PORT); outb_p(val & 0xff, HGA_VALUE_PORT);
}
static int test_hga_b(unsigned char val, unsigned char reg)
{
outb_p(reg, HGA_INDEX_PORT);
outb (val, HGA_VALUE_PORT);
udelay(20); val = (inb_p(HGA_VALUE_PORT) == val);
return val;
}
static void hga_clear_screen(void)
{
unsigned char fillchar = 0xbf; /* magic */
unsigned long flags;
spin_lock_irqsave(&hga_reg_lock, flags);
if (hga_mode == HGA_TXT)
fillchar = ' ';
else if (hga_mode == HGA_GFX)
fillchar = 0x00;
spin_unlock_irqrestore(&hga_reg_lock, flags);
if (fillchar != 0xbf)
memset_io(hga_vram, fillchar, hga_vram_len);
}
static void hga_txt_mode(void)
{
unsigned long flags;
spin_lock_irqsave(&hga_reg_lock, flags);
outb_p(HGA_MODE_VIDEO_EN | HGA_MODE_BLINK_EN, HGA_MODE_PORT);
outb_p(0x00, HGA_GFX_PORT);
outb_p(0x00, HGA_STATUS_PORT);
write_hga_b(0x61, 0x00); /* horizontal total */
write_hga_b(0x50, 0x01); /* horizontal displayed */
write_hga_b(0x52, 0x02); /* horizontal sync pos */
write_hga_b(0x0f, 0x03); /* horizontal sync width */
write_hga_b(0x19, 0x04); /* vertical total */
write_hga_b(0x06, 0x05); /* vertical total adjust */
write_hga_b(0x19, 0x06); /* vertical displayed */
write_hga_b(0x19, 0x07); /* vertical sync pos */
write_hga_b(0x02, 0x08); /* interlace mode */
write_hga_b(0x0d, 0x09); /* maximum scanline */
write_hga_b(0x0c, 0x0a); /* cursor start */
write_hga_b(0x0d, 0x0b); /* cursor end */
write_hga_w(0x0000, 0x0c); /* start address */
write_hga_w(0x0000, 0x0e); /* cursor location */
hga_mode = HGA_TXT;
spin_unlock_irqrestore(&hga_reg_lock, flags);
}
static void hga_gfx_mode(void)
{
unsigned long flags;
spin_lock_irqsave(&hga_reg_lock, flags);
outb_p(0x00, HGA_STATUS_PORT);
outb_p(HGA_GFX_MODE_EN, HGA_GFX_PORT);
outb_p(HGA_MODE_VIDEO_EN | HGA_MODE_GRAPHICS, HGA_MODE_PORT);
write_hga_b(0x35, 0x00); /* horizontal total */
write_hga_b(0x2d, 0x01); /* horizontal displayed */
write_hga_b(0x2e, 0x02); /* horizontal sync pos */
write_hga_b(0x07, 0x03); /* horizontal sync width */
write_hga_b(0x5b, 0x04); /* vertical total */
write_hga_b(0x02, 0x05); /* vertical total adjust */
write_hga_b(0x57, 0x06); /* vertical displayed */
write_hga_b(0x57, 0x07); /* vertical sync pos */
write_hga_b(0x02, 0x08); /* interlace mode */
write_hga_b(0x03, 0x09); /* maximum scanline */
write_hga_b(0x00, 0x0a); /* cursor start */
write_hga_b(0x00, 0x0b); /* cursor end */
write_hga_w(0x0000, 0x0c); /* start address */
write_hga_w(0x0000, 0x0e); /* cursor location */
hga_mode = HGA_GFX;
spin_unlock_irqrestore(&hga_reg_lock, flags);
}
static void hga_show_logo(struct fb_info *info)
{
/*
void __iomem *dest = hga_vram;
char *logo = linux_logo_bw;
int x, y;
for (y = 134; y < 134 + 80 ; y++) * this needs some cleanup *
for (x = 0; x < 10 ; x++)
writeb(~*(logo++),(dest + HGA_ROWADDR(y) + x + 40));
*/
}
static void hga_pan(unsigned int xoffset, unsigned int yoffset)
{
unsigned int base;
unsigned long flags;
base = (yoffset / 8) * 90 + xoffset;
spin_lock_irqsave(&hga_reg_lock, flags);
write_hga_w(base, 0x0c); /* start address */
spin_unlock_irqrestore(&hga_reg_lock, flags);
DPRINTK("hga_pan: base:%d\n", base);
}
static void hga_blank(int blank_mode)
{
unsigned long flags;
spin_lock_irqsave(&hga_reg_lock, flags);
if (blank_mode) {
outb_p(0x00, HGA_MODE_PORT); /* disable video */
} else {
outb_p(HGA_MODE_VIDEO_EN | HGA_MODE_GRAPHICS, HGA_MODE_PORT);
}
spin_unlock_irqrestore(&hga_reg_lock, flags);
}
static int hga_card_detect(void)
{
int count = 0;
void __iomem *p, *q;
unsigned short p_save, q_save;
hga_vram_len = 0x08000;
hga_vram = ioremap(0xb0000, hga_vram_len);
if (!hga_vram)
return -ENOMEM;
if (request_region(0x3b0, 12, "hgafb"))
release_io_ports = 1;
if (request_region(0x3bf, 1, "hgafb"))
release_io_port = 1;
/* do a memory check */
p = hga_vram;
q = hga_vram + 0x01000;
p_save = readw(p); q_save = readw(q);
writew(0xaa55, p); if (readw(p) == 0xaa55) count++;
writew(0x55aa, p); if (readw(p) == 0x55aa) count++;
writew(p_save, p);
if (count != 2)
goto error;
/* Ok, there is definitely a card registering at the correct
* memory location, so now we do an I/O port test.
*/
if (!test_hga_b(0x66, 0x0f)) /* cursor low register */
goto error;
if (!test_hga_b(0x99, 0x0f)) /* cursor low register */
goto error;
/* See if the card is a Hercules, by checking whether the vsync
* bit of the status register is changing. This test lasts for
* approximately 1/10th of a second.
*/
p_save = q_save = inb_p(HGA_STATUS_PORT) & HGA_STATUS_VSYNC;
for (count=0; count < 50000 && p_save == q_save; count++) {
q_save = inb(HGA_STATUS_PORT) & HGA_STATUS_VSYNC;
udelay(2);
}
if (p_save == q_save)
goto error;
switch (inb_p(HGA_STATUS_PORT) & 0x70) {
case 0x10:
hga_type = TYPE_HERCPLUS;
hga_type_name = "HerculesPlus";
break;
case 0x50:
hga_type = TYPE_HERCCOLOR;
hga_type_name = "HerculesColor";
break;
default:
hga_type = TYPE_HERC;
hga_type_name = "Hercules";
break;
}
return 0;
error:
if (release_io_ports)
release_region(0x3b0, 12);
if (release_io_port)
release_region(0x3bf, 1);
iounmap(hga_vram);
pr_err("hgafb: HGA card not detected.\n");
return -EINVAL;
}
/**
* hgafb_open - open the framebuffer device
* @info: pointer to fb_info object containing info for current hga board
* @init: open by console system or userland.
*/
static int hgafb_open(struct fb_info *info, int init)
{
hga_gfx_mode();
hga_clear_screen();
if (!nologo) hga_show_logo(info);
return 0;
}
/**
* hgafb_release - open the framebuffer device
* @info: pointer to fb_info object containing info for current hga board
* @init: open by console system or userland.
*/
static int hgafb_release(struct fb_info *info, int init)
{
hga_txt_mode();
hga_clear_screen();
return 0;
}
/**
* hgafb_setcolreg - set color registers
* @regno:register index to set
* @red:red value, unused
* @green:green value, unused
* @blue:blue value, unused
* @transp:transparency value, unused
* @info:unused
*
* This callback function is used to set the color registers of a HGA
* board. Since we have only two fixed colors only @regno is checked.
* A zero is returned on success and 1 for failure.
*/
static int hgafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
if (regno > 1)
return 1;
return 0;
}
/**
* hga_pan_display - pan or wrap the display
* @var:contains new xoffset, yoffset and vmode values
* @info:pointer to fb_info object containing info for current hga board
*
* This function looks only at xoffset, yoffset and the %FB_VMODE_YWRAP
* flag in @var. If input parameters are correct it calls hga_pan() to
* program the hardware. @info->var is updated to the new values.
* A zero is returned on success and %-EINVAL for failure.
*/
static int hgafb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if (var->vmode & FB_VMODE_YWRAP) {
if (var->yoffset >= info->var.yres_virtual ||
var->xoffset)
return -EINVAL;
} else {
if (var->xoffset + info->var.xres > info->var.xres_virtual
|| var->yoffset + info->var.yres > info->var.yres_virtual
|| var->yoffset % 8)
return -EINVAL;
}
hga_pan(var->xoffset, var->yoffset);
return 0;
}
/**
* hgafb_blank - (un)blank the screen
* @blank_mode:blanking method to use
* @info:unused
*
* Blank the screen if blank_mode != 0, else unblank.
* Implements VESA suspend and powerdown modes on hardware that supports
* disabling hsync/vsync:
* @blank_mode == 2 means suspend vsync,
* @blank_mode == 3 means suspend hsync,
* @blank_mode == 4 means powerdown.
*/
static int hgafb_blank(int blank_mode, struct fb_info *info)
{
hga_blank(blank_mode);
return 0;
}
/*
* Accel functions
*/
static void hgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
u_int rows, y;
u8 __iomem *dest;
y = rect->dy;
for (rows = rect->height; rows--; y++) {
dest = rowaddr(info, y) + (rect->dx >> 3);
switch (rect->rop) {
case ROP_COPY:
memset_io(dest, rect->color, (rect->width >> 3));
break;
case ROP_XOR:
fb_writeb(~(fb_readb(dest)), dest);
break;
}
}
}
static void hgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
u_int rows, y1, y2;
u8 __iomem *src;
u8 __iomem *dest;
if (area->dy <= area->sy) {
y1 = area->sy;
y2 = area->dy;
for (rows = area->height; rows--; ) {
src = rowaddr(info, y1) + (area->sx >> 3);
dest = rowaddr(info, y2) + (area->dx >> 3);
memmove(dest, src, (area->width >> 3));
y1++;
y2++;
}
} else {
y1 = area->sy + area->height - 1;
y2 = area->dy + area->height - 1;
for (rows = area->height; rows--;) {
src = rowaddr(info, y1) + (area->sx >> 3);
dest = rowaddr(info, y2) + (area->dx >> 3);
memmove(dest, src, (area->width >> 3));
y1--;
y2--;
}
}
}
static void hgafb_imageblit(struct fb_info *info, const struct fb_image *image)
{
u8 __iomem *dest;
u8 *cdat = (u8 *) image->data;
u_int rows, y = image->dy;
u_int x;
u8 d;
for (rows = image->height; rows--; y++) {
for (x = 0; x < image->width; x+= 8) {
d = *cdat++;
dest = rowaddr(info, y) + ((image->dx + x)>> 3);
fb_writeb(d, dest);
}
}
}
static const struct fb_ops hgafb_ops = {
.owner = THIS_MODULE,
.fb_open = hgafb_open,
.fb_release = hgafb_release,
.fb_setcolreg = hgafb_setcolreg,
.fb_pan_display = hgafb_pan_display,
.fb_blank = hgafb_blank,
.fb_fillrect = hgafb_fillrect,
.fb_copyarea = hgafb_copyarea,
.fb_imageblit = hgafb_imageblit,
};
/* ------------------------------------------------------------------------- *
*
* Functions in fb_info
*
* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
* Initialization
*/
static int hgafb_probe(struct platform_device *pdev)
{
struct fb_info *info;
int ret;
ret = hga_card_detect();
if (ret)
return ret;
printk(KERN_INFO "hgafb: %s with %ldK of memory detected.\n",
hga_type_name, hga_vram_len/1024);
info = framebuffer_alloc(0, &pdev->dev);
if (!info) {
iounmap(hga_vram);
return -ENOMEM;
}
hga_fix.smem_start = (unsigned long)hga_vram;
hga_fix.smem_len = hga_vram_len;
info->flags = FBINFO_HWACCEL_YPAN;
info->var = hga_default_var;
info->fix = hga_fix;
info->monspecs.hfmin = 0;
info->monspecs.hfmax = 0;
info->monspecs.vfmin = 10000;
info->monspecs.vfmax = 10000;
info->monspecs.dpms = 0;
info->fbops = &hgafb_ops;
info->screen_base = hga_vram;
if (register_framebuffer(info) < 0) {
framebuffer_release(info);
iounmap(hga_vram);
return -EINVAL;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
platform_set_drvdata(pdev, info);
return 0;
}
static void hgafb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
hga_txt_mode();
hga_clear_screen();
if (info) {
unregister_framebuffer(info);
framebuffer_release(info);
}
iounmap(hga_vram);
if (release_io_ports)
release_region(0x3b0, 12);
if (release_io_port)
release_region(0x3bf, 1);
}
static struct platform_driver hgafb_driver = {
.probe = hgafb_probe,
.remove_new = hgafb_remove,
.driver = {
.name = "hgafb",
},
};
static struct platform_device *hgafb_device;
static int __init hgafb_init(void)
{
int ret;
if (fb_get_options("hgafb", NULL))
return -ENODEV;
ret = platform_driver_register(&hgafb_driver);
if (!ret) {
hgafb_device = platform_device_register_simple("hgafb", 0, NULL, 0);
if (IS_ERR(hgafb_device)) {
platform_driver_unregister(&hgafb_driver);
ret = PTR_ERR(hgafb_device);
}
}
return ret;
}
static void __exit hgafb_exit(void)
{
platform_device_unregister(hgafb_device);
platform_driver_unregister(&hgafb_driver);
}
/* -------------------------------------------------------------------------
*
* Modularization
*
* ------------------------------------------------------------------------- */
MODULE_AUTHOR("Ferenc Bakonyi ([email protected])");
MODULE_DESCRIPTION("FBDev driver for Hercules Graphics Adaptor");
MODULE_LICENSE("GPL");
module_param(nologo, bool, 0);
MODULE_PARM_DESC(nologo, "Disables startup logo if != 0 (default=0)");
module_init(hgafb_init);
module_exit(hgafb_exit);
| linux-master | drivers/video/fbdev/hgafb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/ep93xx-fb.c
*
* Framebuffer support for the EP93xx series.
*
* Copyright (C) 2007 Bluewater Systems Ltd
* Author: Ryan Mallon
*
* Copyright (c) 2009 H Hartley Sweeten <[email protected]>
*
* Based on the Cirrus Logic ep93xxfb driver, and various other ep93xxfb
* drivers.
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/platform_data/video-ep93xx.h>
/* Vertical Frame Timing Registers */
#define EP93XXFB_VLINES_TOTAL 0x0000 /* SW locked */
#define EP93XXFB_VSYNC 0x0004 /* SW locked */
#define EP93XXFB_VACTIVE 0x0008 /* SW locked */
#define EP93XXFB_VBLANK 0x0228 /* SW locked */
#define EP93XXFB_VCLK 0x000c /* SW locked */
/* Horizontal Frame Timing Registers */
#define EP93XXFB_HCLKS_TOTAL 0x0010 /* SW locked */
#define EP93XXFB_HSYNC 0x0014 /* SW locked */
#define EP93XXFB_HACTIVE 0x0018 /* SW locked */
#define EP93XXFB_HBLANK 0x022c /* SW locked */
#define EP93XXFB_HCLK 0x001c /* SW locked */
/* Frame Buffer Memory Configuration Registers */
#define EP93XXFB_SCREEN_PAGE 0x0028
#define EP93XXFB_SCREEN_HPAGE 0x002c
#define EP93XXFB_SCREEN_LINES 0x0030
#define EP93XXFB_LINE_LENGTH 0x0034
#define EP93XXFB_VLINE_STEP 0x0038
#define EP93XXFB_LINE_CARRY 0x003c /* SW locked */
#define EP93XXFB_EOL_OFFSET 0x0230
/* Other Video Registers */
#define EP93XXFB_BRIGHTNESS 0x0020
#define EP93XXFB_ATTRIBS 0x0024 /* SW locked */
#define EP93XXFB_SWLOCK 0x007c /* SW locked */
#define EP93XXFB_AC_RATE 0x0214
#define EP93XXFB_FIFO_LEVEL 0x0234
#define EP93XXFB_PIXELMODE 0x0054
#define EP93XXFB_PIXELMODE_32BPP (0x7 << 0)
#define EP93XXFB_PIXELMODE_24BPP (0x6 << 0)
#define EP93XXFB_PIXELMODE_16BPP (0x4 << 0)
#define EP93XXFB_PIXELMODE_8BPP (0x2 << 0)
#define EP93XXFB_PIXELMODE_SHIFT_1P_24B (0x0 << 3)
#define EP93XXFB_PIXELMODE_SHIFT_1P_18B (0x1 << 3)
#define EP93XXFB_PIXELMODE_COLOR_LUT (0x0 << 10)
#define EP93XXFB_PIXELMODE_COLOR_888 (0x4 << 10)
#define EP93XXFB_PIXELMODE_COLOR_555 (0x5 << 10)
#define EP93XXFB_PARL_IF_OUT 0x0058
#define EP93XXFB_PARL_IF_IN 0x005c
/* Blink Control Registers */
#define EP93XXFB_BLINK_RATE 0x0040
#define EP93XXFB_BLINK_MASK 0x0044
#define EP93XXFB_BLINK_PATTRN 0x0048
#define EP93XXFB_PATTRN_MASK 0x004c
#define EP93XXFB_BKGRND_OFFSET 0x0050
/* Hardware Cursor Registers */
#define EP93XXFB_CURSOR_ADR_START 0x0060
#define EP93XXFB_CURSOR_ADR_RESET 0x0064
#define EP93XXFB_CURSOR_SIZE 0x0068
#define EP93XXFB_CURSOR_COLOR1 0x006c
#define EP93XXFB_CURSOR_COLOR2 0x0070
#define EP93XXFB_CURSOR_BLINK_COLOR1 0x021c
#define EP93XXFB_CURSOR_BLINK_COLOR2 0x0220
#define EP93XXFB_CURSOR_XY_LOC 0x0074
#define EP93XXFB_CURSOR_DSCAN_HY_LOC 0x0078
#define EP93XXFB_CURSOR_BLINK_RATE_CTRL 0x0224
/* LUT Registers */
#define EP93XXFB_GRY_SCL_LUTR 0x0080
#define EP93XXFB_GRY_SCL_LUTG 0x0280
#define EP93XXFB_GRY_SCL_LUTB 0x0300
#define EP93XXFB_LUT_SW_CONTROL 0x0218
#define EP93XXFB_LUT_SW_CONTROL_SWTCH (1 << 0)
#define EP93XXFB_LUT_SW_CONTROL_SSTAT (1 << 1)
#define EP93XXFB_COLOR_LUT 0x0400
/* Video Signature Registers */
#define EP93XXFB_VID_SIG_RSLT_VAL 0x0200
#define EP93XXFB_VID_SIG_CTRL 0x0204
#define EP93XXFB_VSIG 0x0208
#define EP93XXFB_HSIG 0x020c
#define EP93XXFB_SIG_CLR_STR 0x0210
/* Minimum / Maximum resolutions supported */
#define EP93XXFB_MIN_XRES 64
#define EP93XXFB_MIN_YRES 64
#define EP93XXFB_MAX_XRES 1024
#define EP93XXFB_MAX_YRES 768
struct ep93xx_fbi {
struct ep93xxfb_mach_info *mach_info;
struct clk *clk;
struct resource *res;
void __iomem *mmio_base;
unsigned int pseudo_palette[256];
};
static int check_screenpage_bug = 1;
module_param(check_screenpage_bug, int, 0644);
MODULE_PARM_DESC(check_screenpage_bug,
"Check for bit 27 screen page bug. Default = 1");
static inline unsigned int ep93xxfb_readl(struct ep93xx_fbi *fbi,
unsigned int off)
{
return __raw_readl(fbi->mmio_base + off);
}
static inline void ep93xxfb_writel(struct ep93xx_fbi *fbi,
unsigned int val, unsigned int off)
{
__raw_writel(val, fbi->mmio_base + off);
}
/*
* Write to one of the locked raster registers.
*/
static inline void ep93xxfb_out_locked(struct ep93xx_fbi *fbi,
unsigned int val, unsigned int reg)
{
/*
* We don't need a lock or delay here since the raster register
* block will remain unlocked until the next access.
*/
ep93xxfb_writel(fbi, 0xaa, EP93XXFB_SWLOCK);
ep93xxfb_writel(fbi, val, reg);
}
static void ep93xxfb_set_video_attribs(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int attribs;
attribs = EP93XXFB_ENABLE;
attribs |= fbi->mach_info->flags;
ep93xxfb_out_locked(fbi, attribs, EP93XXFB_ATTRIBS);
}
static int ep93xxfb_set_pixelmode(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int val;
info->var.transp.offset = 0;
info->var.transp.length = 0;
switch (info->var.bits_per_pixel) {
case 8:
val = EP93XXFB_PIXELMODE_8BPP | EP93XXFB_PIXELMODE_COLOR_LUT |
EP93XXFB_PIXELMODE_SHIFT_1P_18B;
info->var.red.offset = 0;
info->var.red.length = 8;
info->var.green.offset = 0;
info->var.green.length = 8;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
val = EP93XXFB_PIXELMODE_16BPP | EP93XXFB_PIXELMODE_COLOR_555 |
EP93XXFB_PIXELMODE_SHIFT_1P_18B;
info->var.red.offset = 11;
info->var.red.length = 5;
info->var.green.offset = 5;
info->var.green.length = 6;
info->var.blue.offset = 0;
info->var.blue.length = 5;
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 24:
val = EP93XXFB_PIXELMODE_24BPP | EP93XXFB_PIXELMODE_COLOR_888 |
EP93XXFB_PIXELMODE_SHIFT_1P_24B;
info->var.red.offset = 16;
info->var.red.length = 8;
info->var.green.offset = 8;
info->var.green.length = 8;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 32:
val = EP93XXFB_PIXELMODE_32BPP | EP93XXFB_PIXELMODE_COLOR_888 |
EP93XXFB_PIXELMODE_SHIFT_1P_24B;
info->var.red.offset = 16;
info->var.red.length = 8;
info->var.green.offset = 8;
info->var.green.length = 8;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
default:
return -EINVAL;
}
ep93xxfb_writel(fbi, val, EP93XXFB_PIXELMODE);
return 0;
}
static void ep93xxfb_set_timing(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int vlines_total, hclks_total, start, stop;
vlines_total = info->var.yres + info->var.upper_margin +
info->var.lower_margin + info->var.vsync_len - 1;
hclks_total = info->var.xres + info->var.left_margin +
info->var.right_margin + info->var.hsync_len - 1;
ep93xxfb_out_locked(fbi, vlines_total, EP93XXFB_VLINES_TOTAL);
ep93xxfb_out_locked(fbi, hclks_total, EP93XXFB_HCLKS_TOTAL);
start = vlines_total;
stop = vlines_total - info->var.vsync_len;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VSYNC);
start = vlines_total - info->var.vsync_len - info->var.upper_margin;
stop = info->var.lower_margin - 1;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VBLANK);
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VACTIVE);
start = vlines_total;
stop = vlines_total + 1;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VCLK);
start = hclks_total;
stop = hclks_total - info->var.hsync_len;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HSYNC);
start = hclks_total - info->var.hsync_len - info->var.left_margin;
stop = info->var.right_margin - 1;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HBLANK);
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HACTIVE);
start = hclks_total;
stop = hclks_total;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HCLK);
ep93xxfb_out_locked(fbi, 0x0, EP93XXFB_LINE_CARRY);
}
static int ep93xxfb_set_par(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
clk_set_rate(fbi->clk, 1000 * PICOS2KHZ(info->var.pixclock));
ep93xxfb_set_timing(info);
info->fix.line_length = info->var.xres_virtual *
info->var.bits_per_pixel / 8;
ep93xxfb_writel(fbi, info->fix.smem_start, EP93XXFB_SCREEN_PAGE);
ep93xxfb_writel(fbi, info->var.yres - 1, EP93XXFB_SCREEN_LINES);
ep93xxfb_writel(fbi, ((info->var.xres * info->var.bits_per_pixel)
/ 32) - 1, EP93XXFB_LINE_LENGTH);
ep93xxfb_writel(fbi, info->fix.line_length / 4, EP93XXFB_VLINE_STEP);
ep93xxfb_set_video_attribs(info);
return 0;
}
static int ep93xxfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int err;
err = ep93xxfb_set_pixelmode(info);
if (err)
return err;
var->xres = max_t(unsigned int, var->xres, EP93XXFB_MIN_XRES);
var->xres = min_t(unsigned int, var->xres, EP93XXFB_MAX_XRES);
var->xres_virtual = max(var->xres_virtual, var->xres);
var->yres = max_t(unsigned int, var->yres, EP93XXFB_MIN_YRES);
var->yres = min_t(unsigned int, var->yres, EP93XXFB_MAX_YRES);
var->yres_virtual = max(var->yres_virtual, var->yres);
return 0;
}
static int ep93xxfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
unsigned int offset = vma->vm_pgoff << PAGE_SHIFT;
if (offset < info->fix.smem_len) {
return dma_mmap_wc(info->device, vma, info->screen_base,
info->fix.smem_start, info->fix.smem_len);
}
return -EINVAL;
}
static int ep93xxfb_blank(int blank_mode, struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int attribs = ep93xxfb_readl(fbi, EP93XXFB_ATTRIBS);
if (blank_mode) {
if (fbi->mach_info->blank)
fbi->mach_info->blank(blank_mode, info);
ep93xxfb_out_locked(fbi, attribs & ~EP93XXFB_ENABLE,
EP93XXFB_ATTRIBS);
clk_disable(fbi->clk);
} else {
clk_enable(fbi->clk);
ep93xxfb_out_locked(fbi, attribs | EP93XXFB_ENABLE,
EP93XXFB_ATTRIBS);
if (fbi->mach_info->blank)
fbi->mach_info->blank(blank_mode, info);
}
return 0;
}
static inline int ep93xxfb_convert_color(int val, int width)
{
return ((val << width) + 0x7fff - val) >> 16;
}
static int ep93xxfb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int *pal = info->pseudo_palette;
unsigned int ctrl, i, rgb, lut_current, lut_stat;
switch (info->fix.visual) {
case FB_VISUAL_PSEUDOCOLOR:
if (regno > 255)
return 1;
rgb = ((red & 0xff00) << 8) | (green & 0xff00) |
((blue & 0xff00) >> 8);
pal[regno] = rgb;
ep93xxfb_writel(fbi, rgb, (EP93XXFB_COLOR_LUT + (regno << 2)));
ctrl = ep93xxfb_readl(fbi, EP93XXFB_LUT_SW_CONTROL);
lut_stat = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SSTAT);
lut_current = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SWTCH);
if (lut_stat == lut_current) {
for (i = 0; i < 256; i++) {
ep93xxfb_writel(fbi, pal[i],
EP93XXFB_COLOR_LUT + (i << 2));
}
ep93xxfb_writel(fbi,
ctrl ^ EP93XXFB_LUT_SW_CONTROL_SWTCH,
EP93XXFB_LUT_SW_CONTROL);
}
break;
case FB_VISUAL_TRUECOLOR:
if (regno > 16)
return 1;
red = ep93xxfb_convert_color(red, info->var.red.length);
green = ep93xxfb_convert_color(green, info->var.green.length);
blue = ep93xxfb_convert_color(blue, info->var.blue.length);
transp = ep93xxfb_convert_color(transp,
info->var.transp.length);
pal[regno] = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
break;
default:
return 1;
}
return 0;
}
static const struct fb_ops ep93xxfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = ep93xxfb_check_var,
.fb_set_par = ep93xxfb_set_par,
.fb_blank = ep93xxfb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_setcolreg = ep93xxfb_setcolreg,
.fb_mmap = ep93xxfb_mmap,
};
static int ep93xxfb_alloc_videomem(struct fb_info *info)
{
char __iomem *virt_addr;
dma_addr_t phys_addr;
unsigned int fb_size;
/* Maximum 16bpp -> used memory is maximum x*y*2 bytes */
fb_size = EP93XXFB_MAX_XRES * EP93XXFB_MAX_YRES * 2;
virt_addr = dma_alloc_wc(info->device, fb_size, &phys_addr, GFP_KERNEL);
if (!virt_addr)
return -ENOMEM;
/*
* There is a bug in the ep93xx framebuffer which causes problems
* if bit 27 of the physical address is set.
* See: https://marc.info/?l=linux-arm-kernel&m=110061245502000&w=2
* There does not seem to be any official errata for this, but I
* have confirmed the problem exists on my hardware (ep9315) at
* least.
*/
if (check_screenpage_bug && phys_addr & (1 << 27)) {
fb_err(info, "ep93xx framebuffer bug. phys addr (0x%x) "
"has bit 27 set: cannot init framebuffer\n",
phys_addr);
dma_free_coherent(info->device, fb_size, virt_addr, phys_addr);
return -ENOMEM;
}
info->fix.smem_start = phys_addr;
info->fix.smem_len = fb_size;
info->screen_base = virt_addr;
return 0;
}
static void ep93xxfb_dealloc_videomem(struct fb_info *info)
{
if (info->screen_base)
dma_free_coherent(info->device, info->fix.smem_len,
info->screen_base, info->fix.smem_start);
}
static int ep93xxfb_probe(struct platform_device *pdev)
{
struct ep93xxfb_mach_info *mach_info = dev_get_platdata(&pdev->dev);
struct fb_info *info;
struct ep93xx_fbi *fbi;
struct resource *res;
char *video_mode;
int err;
if (!mach_info)
return -EINVAL;
info = framebuffer_alloc(sizeof(struct ep93xx_fbi), &pdev->dev);
if (!info)
return -ENOMEM;
platform_set_drvdata(pdev, info);
fbi = info->par;
fbi->mach_info = mach_info;
err = fb_alloc_cmap(&info->cmap, 256, 0);
if (err)
goto failed_cmap;
err = ep93xxfb_alloc_videomem(info);
if (err)
goto failed_videomem;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
err = -ENXIO;
goto failed_resource;
}
/*
* FIXME - We don't do a request_mem_region here because we are
* sharing the register space with the backlight driver (see
* drivers/video/backlight/ep93xx_bl.c) and doing so will cause
* the second loaded driver to return -EBUSY.
*
* NOTE: No locking is required; the backlight does not touch
* any of the framebuffer registers.
*/
fbi->res = res;
fbi->mmio_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (!fbi->mmio_base) {
err = -ENXIO;
goto failed_resource;
}
strcpy(info->fix.id, pdev->name);
info->fbops = &ep93xxfb_ops;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.accel = FB_ACCEL_NONE;
info->var.activate = FB_ACTIVATE_NOW;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->node = -1;
info->state = FBINFO_STATE_RUNNING;
info->pseudo_palette = &fbi->pseudo_palette;
fb_get_options("ep93xx-fb", &video_mode);
err = fb_find_mode(&info->var, info, video_mode,
NULL, 0, NULL, 16);
if (err == 0) {
fb_err(info, "No suitable video mode found\n");
err = -EINVAL;
goto failed_resource;
}
if (mach_info->setup) {
err = mach_info->setup(pdev);
if (err)
goto failed_resource;
}
err = ep93xxfb_check_var(&info->var, info);
if (err)
goto failed_check;
fbi->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(fbi->clk)) {
err = PTR_ERR(fbi->clk);
fbi->clk = NULL;
goto failed_check;
}
ep93xxfb_set_par(info);
err = clk_prepare_enable(fbi->clk);
if (err)
goto failed_check;
err = register_framebuffer(info);
if (err)
goto failed_framebuffer;
fb_info(info, "registered. Mode = %dx%d-%d\n",
info->var.xres, info->var.yres, info->var.bits_per_pixel);
return 0;
failed_framebuffer:
clk_disable_unprepare(fbi->clk);
failed_check:
if (fbi->mach_info->teardown)
fbi->mach_info->teardown(pdev);
failed_resource:
ep93xxfb_dealloc_videomem(info);
failed_videomem:
fb_dealloc_cmap(&info->cmap);
failed_cmap:
kfree(info);
return err;
}
static void ep93xxfb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct ep93xx_fbi *fbi = info->par;
unregister_framebuffer(info);
clk_disable_unprepare(fbi->clk);
ep93xxfb_dealloc_videomem(info);
fb_dealloc_cmap(&info->cmap);
if (fbi->mach_info->teardown)
fbi->mach_info->teardown(pdev);
kfree(info);
}
static struct platform_driver ep93xxfb_driver = {
.probe = ep93xxfb_probe,
.remove_new = ep93xxfb_remove,
.driver = {
.name = "ep93xx-fb",
},
};
module_platform_driver(ep93xxfb_driver);
MODULE_DESCRIPTION("EP93XX Framebuffer Driver");
MODULE_ALIAS("platform:ep93xx-fb");
MODULE_AUTHOR("Ryan Mallon, "
"H Hartley Sweeten <[email protected]");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/ep93xx-fb.c |
// SPDX-License-Identifier: GPL-2.0-only
/* tcx.c: TCX frame buffer driver
*
* Copyright (C) 2003, 2006 David S. Miller ([email protected])
* Copyright (C) 1996,1998 Jakub Jelinek ([email protected])
* Copyright (C) 1996 Miguel de Icaza ([email protected])
* Copyright (C) 1996 Eddie C. Dost ([email protected])
*
* Driver layout based loosely on tgafb.c, see that file for credits.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/fbio.h>
#include "sbuslib.h"
/*
* Local functions.
*/
static int tcx_setcolreg(unsigned, unsigned, unsigned, unsigned,
unsigned, struct fb_info *);
static int tcx_blank(int, struct fb_info *);
static int tcx_mmap(struct fb_info *, struct vm_area_struct *);
static int tcx_ioctl(struct fb_info *, unsigned int, unsigned long);
static int tcx_pan_display(struct fb_var_screeninfo *, struct fb_info *);
/*
* Frame buffer operations
*/
static const struct fb_ops tcx_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = tcx_setcolreg,
.fb_blank = tcx_blank,
.fb_pan_display = tcx_pan_display,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = tcx_mmap,
.fb_ioctl = tcx_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = sbusfb_compat_ioctl,
#endif
};
/* THC definitions */
#define TCX_THC_MISC_REV_SHIFT 16
#define TCX_THC_MISC_REV_MASK 15
#define TCX_THC_MISC_VSYNC_DIS (1 << 25)
#define TCX_THC_MISC_HSYNC_DIS (1 << 24)
#define TCX_THC_MISC_RESET (1 << 12)
#define TCX_THC_MISC_VIDEO (1 << 10)
#define TCX_THC_MISC_SYNC (1 << 9)
#define TCX_THC_MISC_VSYNC (1 << 8)
#define TCX_THC_MISC_SYNC_ENAB (1 << 7)
#define TCX_THC_MISC_CURS_RES (1 << 6)
#define TCX_THC_MISC_INT_ENAB (1 << 5)
#define TCX_THC_MISC_INT (1 << 4)
#define TCX_THC_MISC_INIT 0x9f
#define TCX_THC_REV_REV_SHIFT 20
#define TCX_THC_REV_REV_MASK 15
#define TCX_THC_REV_MINREV_SHIFT 28
#define TCX_THC_REV_MINREV_MASK 15
/* The contents are unknown */
struct tcx_tec {
u32 tec_matrix;
u32 tec_clip;
u32 tec_vdc;
};
struct tcx_thc {
u32 thc_rev;
u32 thc_pad0[511];
u32 thc_hs; /* hsync timing */
u32 thc_hsdvs;
u32 thc_hd;
u32 thc_vs; /* vsync timing */
u32 thc_vd;
u32 thc_refresh;
u32 thc_misc;
u32 thc_pad1[56];
u32 thc_cursxy; /* cursor x,y position (16 bits each) */
u32 thc_cursmask[32]; /* cursor mask bits */
u32 thc_cursbits[32]; /* what to show where mask enabled */
};
struct bt_regs {
u32 addr;
u32 color_map;
u32 control;
u32 cursor;
};
#define TCX_MMAP_ENTRIES 14
struct tcx_par {
spinlock_t lock;
struct bt_regs __iomem *bt;
struct tcx_thc __iomem *thc;
struct tcx_tec __iomem *tec;
u32 __iomem *cplane;
u32 flags;
#define TCX_FLAG_BLANKED 0x00000001
unsigned long which_io;
struct sbus_mmap_map mmap_map[TCX_MMAP_ENTRIES];
int lowdepth;
};
/* Reset control plane so that WID is 8-bit plane. */
static void __tcx_set_control_plane(struct fb_info *info)
{
struct tcx_par *par = info->par;
u32 __iomem *p, *pend;
if (par->lowdepth)
return;
p = par->cplane;
if (p == NULL)
return;
for (pend = p + info->fix.smem_len; p < pend; p++) {
u32 tmp = sbus_readl(p);
tmp &= 0xffffff;
sbus_writel(tmp, p);
}
}
static void tcx_reset(struct fb_info *info)
{
struct tcx_par *par = (struct tcx_par *) info->par;
unsigned long flags;
spin_lock_irqsave(&par->lock, flags);
__tcx_set_control_plane(info);
spin_unlock_irqrestore(&par->lock, flags);
}
static int tcx_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
tcx_reset(info);
return 0;
}
/**
* tcx_setcolreg - Optional function. Sets a color register.
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*/
static int tcx_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct tcx_par *par = (struct tcx_par *) info->par;
struct bt_regs __iomem *bt = par->bt;
unsigned long flags;
if (regno >= 256)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
spin_lock_irqsave(&par->lock, flags);
sbus_writel(regno << 24, &bt->addr);
sbus_writel(red << 24, &bt->color_map);
sbus_writel(green << 24, &bt->color_map);
sbus_writel(blue << 24, &bt->color_map);
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
/**
* tcx_blank - Optional function. Blanks the display.
* @blank: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int
tcx_blank(int blank, struct fb_info *info)
{
struct tcx_par *par = (struct tcx_par *) info->par;
struct tcx_thc __iomem *thc = par->thc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&par->lock, flags);
val = sbus_readl(&thc->thc_misc);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
val &= ~(TCX_THC_MISC_VSYNC_DIS |
TCX_THC_MISC_HSYNC_DIS);
val |= TCX_THC_MISC_VIDEO;
par->flags &= ~TCX_FLAG_BLANKED;
break;
case FB_BLANK_NORMAL: /* Normal blanking */
val &= ~TCX_THC_MISC_VIDEO;
par->flags |= TCX_FLAG_BLANKED;
break;
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
val |= TCX_THC_MISC_VSYNC_DIS;
break;
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
val |= TCX_THC_MISC_HSYNC_DIS;
break;
case FB_BLANK_POWERDOWN: /* Poweroff */
break;
}
sbus_writel(val, &thc->thc_misc);
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
static struct sbus_mmap_map __tcx_mmap_map[TCX_MMAP_ENTRIES] = {
{
.voff = TCX_RAM8BIT,
.size = SBUS_MMAP_FBSIZE(1)
},
{
.voff = TCX_RAM24BIT,
.size = SBUS_MMAP_FBSIZE(4)
},
{
.voff = TCX_UNK3,
.size = SBUS_MMAP_FBSIZE(8)
},
{
.voff = TCX_UNK4,
.size = SBUS_MMAP_FBSIZE(8)
},
{
.voff = TCX_CONTROLPLANE,
.size = SBUS_MMAP_FBSIZE(4)
},
{
.voff = TCX_UNK6,
.size = SBUS_MMAP_FBSIZE(8)
},
{
.voff = TCX_UNK7,
.size = SBUS_MMAP_FBSIZE(8)
},
{
.voff = TCX_TEC,
.size = PAGE_SIZE
},
{
.voff = TCX_BTREGS,
.size = PAGE_SIZE
},
{
.voff = TCX_THC,
.size = PAGE_SIZE
},
{
.voff = TCX_DHC,
.size = PAGE_SIZE
},
{
.voff = TCX_ALT,
.size = PAGE_SIZE
},
{
.voff = TCX_UNK2,
.size = 0x20000
},
{ .size = 0 }
};
static int tcx_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct tcx_par *par = (struct tcx_par *)info->par;
return sbusfb_mmap_helper(par->mmap_map,
info->fix.smem_start, info->fix.smem_len,
par->which_io, vma);
}
static int tcx_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct tcx_par *par = (struct tcx_par *) info->par;
return sbusfb_ioctl_helper(cmd, arg, info,
FBTYPE_TCXCOLOR,
(par->lowdepth ? 8 : 24),
info->fix.smem_len);
}
/*
* Initialisation
*/
static void
tcx_init_fix(struct fb_info *info, int linebytes)
{
struct tcx_par *par = (struct tcx_par *)info->par;
const char *tcx_name;
if (par->lowdepth)
tcx_name = "TCX8";
else
tcx_name = "TCX24";
strscpy(info->fix.id, tcx_name, sizeof(info->fix.id));
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = linebytes;
info->fix.accel = FB_ACCEL_SUN_TCX;
}
static void tcx_unmap_regs(struct platform_device *op, struct fb_info *info,
struct tcx_par *par)
{
if (par->tec)
of_iounmap(&op->resource[7],
par->tec, sizeof(struct tcx_tec));
if (par->thc)
of_iounmap(&op->resource[9],
par->thc, sizeof(struct tcx_thc));
if (par->bt)
of_iounmap(&op->resource[8],
par->bt, sizeof(struct bt_regs));
if (par->cplane)
of_iounmap(&op->resource[4],
par->cplane, info->fix.smem_len * sizeof(u32));
if (info->screen_base)
of_iounmap(&op->resource[0],
info->screen_base, info->fix.smem_len);
}
static int tcx_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct fb_info *info;
struct tcx_par *par;
int linebytes, i, err;
info = framebuffer_alloc(sizeof(struct tcx_par), &op->dev);
err = -ENOMEM;
if (!info)
goto out_err;
par = info->par;
spin_lock_init(&par->lock);
par->lowdepth = of_property_read_bool(dp, "tcx-8-bit");
sbusfb_fill_var(&info->var, dp, 8);
info->var.red.length = 8;
info->var.green.length = 8;
info->var.blue.length = 8;
linebytes = of_getintprop_default(dp, "linebytes",
info->var.xres);
info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
par->tec = of_ioremap(&op->resource[7], 0,
sizeof(struct tcx_tec), "tcx tec");
par->thc = of_ioremap(&op->resource[9], 0,
sizeof(struct tcx_thc), "tcx thc");
par->bt = of_ioremap(&op->resource[8], 0,
sizeof(struct bt_regs), "tcx dac");
info->screen_base = of_ioremap(&op->resource[0], 0,
info->fix.smem_len, "tcx ram");
if (!par->tec || !par->thc ||
!par->bt || !info->screen_base)
goto out_unmap_regs;
memcpy(&par->mmap_map, &__tcx_mmap_map, sizeof(par->mmap_map));
if (!par->lowdepth) {
par->cplane = of_ioremap(&op->resource[4], 0,
info->fix.smem_len * sizeof(u32),
"tcx cplane");
if (!par->cplane)
goto out_unmap_regs;
} else {
par->mmap_map[1].size = SBUS_MMAP_EMPTY;
par->mmap_map[4].size = SBUS_MMAP_EMPTY;
par->mmap_map[5].size = SBUS_MMAP_EMPTY;
par->mmap_map[6].size = SBUS_MMAP_EMPTY;
}
info->fix.smem_start = op->resource[0].start;
par->which_io = op->resource[0].flags & IORESOURCE_BITS;
for (i = 0; i < TCX_MMAP_ENTRIES; i++) {
int j;
switch (i) {
case 10:
j = 12;
break;
case 11: case 12:
j = i - 1;
break;
default:
j = i;
break;
}
par->mmap_map[i].poff = op->resource[j].start;
}
info->fbops = &tcx_ops;
/* Initialize brooktree DAC. */
sbus_writel(0x04 << 24, &par->bt->addr); /* color planes */
sbus_writel(0xff << 24, &par->bt->control);
sbus_writel(0x05 << 24, &par->bt->addr);
sbus_writel(0x00 << 24, &par->bt->control);
sbus_writel(0x06 << 24, &par->bt->addr); /* overlay plane */
sbus_writel(0x73 << 24, &par->bt->control);
sbus_writel(0x07 << 24, &par->bt->addr);
sbus_writel(0x00 << 24, &par->bt->control);
tcx_reset(info);
tcx_blank(FB_BLANK_UNBLANK, info);
if (fb_alloc_cmap(&info->cmap, 256, 0))
goto out_unmap_regs;
fb_set_cmap(&info->cmap, info);
tcx_init_fix(info, linebytes);
err = register_framebuffer(info);
if (err < 0)
goto out_dealloc_cmap;
dev_set_drvdata(&op->dev, info);
printk(KERN_INFO "%pOF: TCX at %lx:%lx, %s\n",
dp,
par->which_io,
info->fix.smem_start,
par->lowdepth ? "8-bit only" : "24-bit depth");
return 0;
out_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
out_unmap_regs:
tcx_unmap_regs(op, info, par);
framebuffer_release(info);
out_err:
return err;
}
static void tcx_remove(struct platform_device *op)
{
struct fb_info *info = dev_get_drvdata(&op->dev);
struct tcx_par *par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
tcx_unmap_regs(op, info, par);
framebuffer_release(info);
}
static const struct of_device_id tcx_match[] = {
{
.name = "SUNW,tcx",
},
{},
};
MODULE_DEVICE_TABLE(of, tcx_match);
static struct platform_driver tcx_driver = {
.driver = {
.name = "tcx",
.of_match_table = tcx_match,
},
.probe = tcx_probe,
.remove_new = tcx_remove,
};
static int __init tcx_init(void)
{
if (fb_get_options("tcxfb", NULL))
return -ENODEV;
return platform_driver_register(&tcx_driver);
}
static void __exit tcx_exit(void)
{
platform_driver_unregister(&tcx_driver);
}
module_init(tcx_init);
module_exit(tcx_exit);
MODULE_DESCRIPTION("framebuffer driver for TCX chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/tcx.c |
/*
* linux/drivers/video/amifb.c -- Amiga builtin chipset frame buffer device
*
* Copyright (C) 1995-2003 Geert Uytterhoeven
*
* with work by Roman Zippel
*
*
* This file is based on the Atari frame buffer device (atafb.c):
*
* Copyright (C) 1994 Martin Schaller
* Roman Hodek
*
* with work by Andreas Schwab
* Guenther Kelleter
*
* and on the original Amiga console driver (amicon.c):
*
* Copyright (C) 1993 Hamish Macdonald
* Greg Harp
* Copyright (C) 1994 David Carter [[email protected]]
*
* with work by William Rucklidge ([email protected])
* Geert Uytterhoeven
* Jes Sorensen ([email protected])
*
*
* History:
*
* - 24 Jul 96: Copper generates now vblank interrupt and
* VESA Power Saving Protocol is fully implemented
* - 14 Jul 96: Rework and hopefully last ECS bugs fixed
* - 7 Mar 96: Hardware sprite support by Roman Zippel
* - 18 Feb 96: OCS and ECS support by Roman Zippel
* Hardware functions completely rewritten
* - 2 Dec 95: AGA version by Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <asm/irq.h>
#include <asm/amigahw.h>
#include <asm/amigaints.h>
#include <asm/setup.h>
#include "c2p.h"
#define DEBUG
#if !defined(CONFIG_FB_AMIGA_OCS) && !defined(CONFIG_FB_AMIGA_ECS) && !defined(CONFIG_FB_AMIGA_AGA)
#define CONFIG_FB_AMIGA_OCS /* define at least one fb driver, this will change later */
#endif
#if !defined(CONFIG_FB_AMIGA_OCS)
# define IS_OCS (0)
#elif defined(CONFIG_FB_AMIGA_ECS) || defined(CONFIG_FB_AMIGA_AGA)
# define IS_OCS (chipset == TAG_OCS)
#else
# define CONFIG_FB_AMIGA_OCS_ONLY
# define IS_OCS (1)
#endif
#if !defined(CONFIG_FB_AMIGA_ECS)
# define IS_ECS (0)
#elif defined(CONFIG_FB_AMIGA_OCS) || defined(CONFIG_FB_AMIGA_AGA)
# define IS_ECS (chipset == TAG_ECS)
#else
# define CONFIG_FB_AMIGA_ECS_ONLY
# define IS_ECS (1)
#endif
#if !defined(CONFIG_FB_AMIGA_AGA)
# define IS_AGA (0)
#elif defined(CONFIG_FB_AMIGA_OCS) || defined(CONFIG_FB_AMIGA_ECS)
# define IS_AGA (chipset == TAG_AGA)
#else
# define CONFIG_FB_AMIGA_AGA_ONLY
# define IS_AGA (1)
#endif
#ifdef DEBUG
# define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
#else
# define DPRINTK(fmt, args...)
#endif
/*******************************************************************************
Generic video timings
---------------------
Timings used by the frame buffer interface:
+----------+---------------------------------------------+----------+-------+
| | ^ | | |
| | |upper_margin | | |
| | v | | |
+----------###############################################----------+-------+
| # ^ # | |
| # | # | |
| # | # | |
| # | # | |
| left # | # right | hsync |
| margin # | xres # margin | len |
|<-------->#<---------------+--------------------------->#<-------->|<----->|
| # | # | |
| # | # | |
| # | # | |
| # |yres # | |
| # | # | |
| # | # | |
| # | # | |
| # | # | |
| # | # | |
| # | # | |
| # | # | |
| # | # | |
| # v # | |
+----------###############################################----------+-------+
| | ^ | | |
| | |lower_margin | | |
| | v | | |
+----------+---------------------------------------------+----------+-------+
| | ^ | | |
| | |vsync_len | | |
| | v | | |
+----------+---------------------------------------------+----------+-------+
Amiga video timings
-------------------
The Amiga native chipsets uses another timing scheme:
- hsstrt: Start of horizontal synchronization pulse
- hsstop: End of horizontal synchronization pulse
- htotal: Last value on the line (i.e. line length = htotal + 1)
- vsstrt: Start of vertical synchronization pulse
- vsstop: End of vertical synchronization pulse
- vtotal: Last line value (i.e. number of lines = vtotal + 1)
- hcenter: Start of vertical retrace for interlace
You can specify the blanking timings independently. Currently I just set
them equal to the respective synchronization values:
- hbstrt: Start of horizontal blank
- hbstop: End of horizontal blank
- vbstrt: Start of vertical blank
- vbstop: End of vertical blank
Horizontal values are in color clock cycles (280 ns), vertical values are in
scanlines.
(0, 0) is somewhere in the upper-left corner :-)
Amiga visible window definitions
--------------------------------
Currently I only have values for AGA, SHRES (28 MHz dotclock). Feel free to
make corrections and/or additions.
Within the above synchronization specifications, the visible window is
defined by the following parameters (actual register resolutions may be
different; all horizontal values are normalized with respect to the pixel
clock):
- diwstrt_h: Horizontal start of the visible window
- diwstop_h: Horizontal stop + 1(*) of the visible window
- diwstrt_v: Vertical start of the visible window
- diwstop_v: Vertical stop of the visible window
- ddfstrt: Horizontal start of display DMA
- ddfstop: Horizontal stop of display DMA
- hscroll: Horizontal display output delay
Sprite positioning:
- sprstrt_h: Horizontal start - 4 of sprite
- sprstrt_v: Vertical start of sprite
(*) Even Commodore did it wrong in the AGA monitor drivers by not adding 1.
Horizontal values are in dotclock cycles (35 ns), vertical values are in
scanlines.
(0, 0) is somewhere in the upper-left corner :-)
Dependencies (AGA, SHRES (35 ns dotclock))
-------------------------------------------
Since there are much more parameters for the Amiga display than for the
frame buffer interface, there must be some dependencies among the Amiga
display parameters. Here's what I found out:
- ddfstrt and ddfstop are best aligned to 64 pixels.
- the chipset needs 64 + 4 horizontal pixels after the DMA start before
the first pixel is output, so diwstrt_h = ddfstrt + 64 + 4 if you want
to display the first pixel on the line too. Increase diwstrt_h for
virtual screen panning.
- the display DMA always fetches 64 pixels at a time (fmode = 3).
- ddfstop is ddfstrt+#pixels - 64.
- diwstop_h = diwstrt_h + xres + 1. Because of the additional 1 this can
be 1 more than htotal.
- hscroll simply adds a delay to the display output. Smooth horizontal
panning needs an extra 64 pixels on the left to prefetch the pixels that
`fall off' on the left.
- if ddfstrt < 192, the sprite DMA cycles are all stolen by the bitplane
DMA, so it's best to make the DMA start as late as possible.
- you really don't want to make ddfstrt < 128, since this will steal DMA
cycles from the other DMA channels (audio, floppy and Chip RAM refresh).
- I make diwstop_h and diwstop_v as large as possible.
General dependencies
--------------------
- all values are SHRES pixel (35ns)
table 1:fetchstart table 2:prefetch table 3:fetchsize
------------------ ---------------- -----------------
Pixclock # SHRES|HIRES|LORES # SHRES|HIRES|LORES # SHRES|HIRES|LORES
-------------#------+-----+------#------+-----+------#------+-----+------
Bus width 1x # 16 | 32 | 64 # 16 | 32 | 64 # 64 | 64 | 64
Bus width 2x # 32 | 64 | 128 # 32 | 64 | 64 # 64 | 64 | 128
Bus width 4x # 64 | 128 | 256 # 64 | 64 | 64 # 64 | 128 | 256
- chipset needs 4 pixels before the first pixel is output
- ddfstrt must be aligned to fetchstart (table 1)
- chipset needs also prefetch (table 2) to get first pixel data, so
ddfstrt = ((diwstrt_h - 4) & -fetchstart) - prefetch
- for horizontal panning decrease diwstrt_h
- the length of a fetchline must be aligned to fetchsize (table 3)
- if fetchstart is smaller than fetchsize, then ddfstrt can a little bit
moved to optimize use of dma (useful for OCS/ECS overscan displays)
- ddfstop is ddfstrt + ddfsize - fetchsize
- If C= didn't change anything for AGA, then at following positions the
dma bus is already used:
ddfstrt < 48 -> memory refresh
< 96 -> disk dma
< 160 -> audio dma
< 192 -> sprite 0 dma
< 416 -> sprite dma (32 per sprite)
- in accordance with the hardware reference manual a hardware stop is at
192, but AGA (ECS?) can go below this.
DMA priorities
--------------
Since there are limits on the earliest start value for display DMA and the
display of sprites, I use the following policy on horizontal panning and
the hardware cursor:
- if you want to start display DMA too early, you lose the ability to
do smooth horizontal panning (xpanstep 1 -> 64).
- if you want to go even further, you lose the hardware cursor too.
IMHO a hardware cursor is more important for X than horizontal scrolling,
so that's my motivation.
Implementation
--------------
ami_decode_var() converts the frame buffer values to the Amiga values. It's
just a `straightforward' implementation of the above rules.
Standard VGA timings
--------------------
xres yres left right upper lower hsync vsync
---- ---- ---- ----- ----- ----- ----- -----
80x25 720 400 27 45 35 12 108 2
80x30 720 480 27 45 30 9 108 2
These were taken from a XFree86 configuration file, recalculated for a 28 MHz
dotclock (Amigas don't have a 25 MHz dotclock) and converted to frame buffer
generic timings.
As a comparison, graphics/monitor.h suggests the following:
xres yres left right upper lower hsync vsync
---- ---- ---- ----- ----- ----- ----- -----
VGA 640 480 52 112 24 19 112 - 2 +
VGA70 640 400 52 112 27 21 112 - 2 -
Sync polarities
---------------
VSYNC HSYNC Vertical size Vertical total
----- ----- ------------- --------------
+ + Reserved Reserved
+ - 400 414
- + 350 362
- - 480 496
Source: CL-GD542X Technical Reference Manual, Cirrus Logic, Oct 1992
Broadcast video timings
-----------------------
According to the CCIR and RETMA specifications, we have the following values:
CCIR -> PAL
-----------
- a scanline is 64 µs long, of which 52.48 µs are visible. This is about
736 visible 70 ns pixels per line.
- we have 625 scanlines, of which 575 are visible (interlaced); after
rounding this becomes 576.
RETMA -> NTSC
-------------
- a scanline is 63.5 µs long, of which 53.5 µs are visible. This is about
736 visible 70 ns pixels per line.
- we have 525 scanlines, of which 485 are visible (interlaced); after
rounding this becomes 484.
Thus if you want a PAL compatible display, you have to do the following:
- set the FB_SYNC_BROADCAST flag to indicate that standard broadcast
timings are to be used.
- make sure upper_margin + yres + lower_margin + vsync_len = 625 for an
interlaced, 312 for a non-interlaced and 156 for a doublescanned
display.
- make sure left_margin + xres + right_margin + hsync_len = 1816 for a
SHRES, 908 for a HIRES and 454 for a LORES display.
- the left visible part begins at 360 (SHRES; HIRES:180, LORES:90),
left_margin + 2 * hsync_len must be greater or equal.
- the upper visible part begins at 48 (interlaced; non-interlaced:24,
doublescanned:12), upper_margin + 2 * vsync_len must be greater or
equal.
- ami_encode_var() calculates margins with a hsync of 5320 ns and a vsync
of 4 scanlines
The settings for a NTSC compatible display are straightforward.
Note that in a strict sense the PAL and NTSC standards only define the
encoding of the color part (chrominance) of the video signal and don't say
anything about horizontal/vertical synchronization nor refresh rates.
-- Geert --
*******************************************************************************/
/*
* Custom Chipset Definitions
*/
#define CUSTOM_OFS(fld) ((long)&((struct CUSTOM*)0)->fld)
/*
* BPLCON0 -- Bitplane Control Register 0
*/
#define BPC0_HIRES (0x8000)
#define BPC0_BPU2 (0x4000) /* Bit plane used count */
#define BPC0_BPU1 (0x2000)
#define BPC0_BPU0 (0x1000)
#define BPC0_HAM (0x0800) /* HAM mode */
#define BPC0_DPF (0x0400) /* Double playfield */
#define BPC0_COLOR (0x0200) /* Enable colorburst */
#define BPC0_GAUD (0x0100) /* Genlock audio enable */
#define BPC0_UHRES (0x0080) /* Ultrahi res enable */
#define BPC0_SHRES (0x0040) /* Super hi res mode */
#define BPC0_BYPASS (0x0020) /* Bypass LUT - AGA */
#define BPC0_BPU3 (0x0010) /* AGA */
#define BPC0_LPEN (0x0008) /* Light pen enable */
#define BPC0_LACE (0x0004) /* Interlace */
#define BPC0_ERSY (0x0002) /* External resync */
#define BPC0_ECSENA (0x0001) /* ECS enable */
/*
* BPLCON2 -- Bitplane Control Register 2
*/
#define BPC2_ZDBPSEL2 (0x4000) /* Bitplane to be used for ZD - AGA */
#define BPC2_ZDBPSEL1 (0x2000)
#define BPC2_ZDBPSEL0 (0x1000)
#define BPC2_ZDBPEN (0x0800) /* Enable ZD with ZDBPSELx - AGA */
#define BPC2_ZDCTEN (0x0400) /* Enable ZD with palette bit #31 - AGA */
#define BPC2_KILLEHB (0x0200) /* Kill EHB mode - AGA */
#define BPC2_RDRAM (0x0100) /* Color table accesses read, not write - AGA */
#define BPC2_SOGEN (0x0080) /* SOG output pin high - AGA */
#define BPC2_PF2PRI (0x0040) /* PF2 priority over PF1 */
#define BPC2_PF2P2 (0x0020) /* PF2 priority wrt sprites */
#define BPC2_PF2P1 (0x0010)
#define BPC2_PF2P0 (0x0008)
#define BPC2_PF1P2 (0x0004) /* ditto PF1 */
#define BPC2_PF1P1 (0x0002)
#define BPC2_PF1P0 (0x0001)
/*
* BPLCON3 -- Bitplane Control Register 3 (AGA)
*/
#define BPC3_BANK2 (0x8000) /* Bits to select color register bank */
#define BPC3_BANK1 (0x4000)
#define BPC3_BANK0 (0x2000)
#define BPC3_PF2OF2 (0x1000) /* Bits for color table offset when PF2 */
#define BPC3_PF2OF1 (0x0800)
#define BPC3_PF2OF0 (0x0400)
#define BPC3_LOCT (0x0200) /* Color register writes go to low bits */
#define BPC3_SPRES1 (0x0080) /* Sprite resolution bits */
#define BPC3_SPRES0 (0x0040)
#define BPC3_BRDRBLNK (0x0020) /* Border blanked? */
#define BPC3_BRDRTRAN (0x0010) /* Border transparent? */
#define BPC3_ZDCLKEN (0x0004) /* ZD pin is 14 MHz (HIRES) clock output */
#define BPC3_BRDRSPRT (0x0002) /* Sprites in border? */
#define BPC3_EXTBLKEN (0x0001) /* BLANK programmable */
/*
* BPLCON4 -- Bitplane Control Register 4 (AGA)
*/
#define BPC4_BPLAM7 (0x8000) /* bitplane color XOR field */
#define BPC4_BPLAM6 (0x4000)
#define BPC4_BPLAM5 (0x2000)
#define BPC4_BPLAM4 (0x1000)
#define BPC4_BPLAM3 (0x0800)
#define BPC4_BPLAM2 (0x0400)
#define BPC4_BPLAM1 (0x0200)
#define BPC4_BPLAM0 (0x0100)
#define BPC4_ESPRM7 (0x0080) /* 4 high bits for even sprite colors */
#define BPC4_ESPRM6 (0x0040)
#define BPC4_ESPRM5 (0x0020)
#define BPC4_ESPRM4 (0x0010)
#define BPC4_OSPRM7 (0x0008) /* 4 high bits for odd sprite colors */
#define BPC4_OSPRM6 (0x0004)
#define BPC4_OSPRM5 (0x0002)
#define BPC4_OSPRM4 (0x0001)
/*
* BEAMCON0 -- Beam Control Register
*/
#define BMC0_HARDDIS (0x4000) /* Disable hardware limits */
#define BMC0_LPENDIS (0x2000) /* Disable light pen latch */
#define BMC0_VARVBEN (0x1000) /* Enable variable vertical blank */
#define BMC0_LOLDIS (0x0800) /* Disable long/short line toggle */
#define BMC0_CSCBEN (0x0400) /* Composite sync/blank */
#define BMC0_VARVSYEN (0x0200) /* Enable variable vertical sync */
#define BMC0_VARHSYEN (0x0100) /* Enable variable horizontal sync */
#define BMC0_VARBEAMEN (0x0080) /* Enable variable beam counters */
#define BMC0_DUAL (0x0040) /* Enable alternate horizontal beam counter */
#define BMC0_PAL (0x0020) /* Set decodes for PAL */
#define BMC0_VARCSYEN (0x0010) /* Enable variable composite sync */
#define BMC0_BLANKEN (0x0008) /* Blank enable (no longer used on AGA) */
#define BMC0_CSYTRUE (0x0004) /* CSY polarity */
#define BMC0_VSYTRUE (0x0002) /* VSY polarity */
#define BMC0_HSYTRUE (0x0001) /* HSY polarity */
/*
* FMODE -- Fetch Mode Control Register (AGA)
*/
#define FMODE_SSCAN2 (0x8000) /* Sprite scan-doubling */
#define FMODE_BSCAN2 (0x4000) /* Use PF2 modulus every other line */
#define FMODE_SPAGEM (0x0008) /* Sprite page mode */
#define FMODE_SPR32 (0x0004) /* Sprite 32 bit fetch */
#define FMODE_BPAGEM (0x0002) /* Bitplane page mode */
#define FMODE_BPL32 (0x0001) /* Bitplane 32 bit fetch */
/*
* Tags used to indicate a specific Pixel Clock
*
* clk_shift is the shift value to get the timings in 35 ns units
*/
enum { TAG_SHRES, TAG_HIRES, TAG_LORES };
/*
* Tags used to indicate the specific chipset
*/
enum { TAG_OCS, TAG_ECS, TAG_AGA };
/*
* Tags used to indicate the memory bandwidth
*/
enum { TAG_FMODE_1, TAG_FMODE_2, TAG_FMODE_4 };
/*
* Clock Definitions, Maximum Display Depth
*
* These depend on the E-Clock or the Chipset, so they are filled in
* dynamically
*/
static u_long pixclock[3]; /* SHRES/HIRES/LORES: index = clk_shift */
static u_short maxdepth[3]; /* SHRES/HIRES/LORES: index = clk_shift */
static u_short maxfmode, chipset;
/*
* Broadcast Video Timings
*
* Horizontal values are in 35 ns (SHRES) units
* Vertical values are in interlaced scanlines
*/
#define PAL_DIWSTRT_H (360) /* PAL Window Limits */
#define PAL_DIWSTRT_V (48)
#define PAL_HTOTAL (1816)
#define PAL_VTOTAL (625)
#define NTSC_DIWSTRT_H (360) /* NTSC Window Limits */
#define NTSC_DIWSTRT_V (40)
#define NTSC_HTOTAL (1816)
#define NTSC_VTOTAL (525)
/*
* Various macros
*/
#define up2(v) (((v) + 1) & -2)
#define down2(v) ((v) & -2)
#define div2(v) ((v)>>1)
#define mod2(v) ((v) & 1)
#define up4(v) (((v) + 3) & -4)
#define down4(v) ((v) & -4)
#define mul4(v) ((v) << 2)
#define div4(v) ((v)>>2)
#define mod4(v) ((v) & 3)
#define up8(v) (((v) + 7) & -8)
#define down8(v) ((v) & -8)
#define div8(v) ((v)>>3)
#define mod8(v) ((v) & 7)
#define up16(v) (((v) + 15) & -16)
#define down16(v) ((v) & -16)
#define div16(v) ((v)>>4)
#define mod16(v) ((v) & 15)
#define up32(v) (((v) + 31) & -32)
#define down32(v) ((v) & -32)
#define div32(v) ((v)>>5)
#define mod32(v) ((v) & 31)
#define up64(v) (((v) + 63) & -64)
#define down64(v) ((v) & -64)
#define div64(v) ((v)>>6)
#define mod64(v) ((v) & 63)
#define upx(x, v) (((v) + (x) - 1) & -(x))
#define downx(x, v) ((v) & -(x))
#define modx(x, v) ((v) & ((x) - 1))
/*
* FIXME: Use C variants of the code marked with #ifdef __mc68000__
* in the driver. It shouldn't negatively affect the performance and
* is required for APUS support (once it is re-added to the kernel).
* Needs to be tested on the hardware though..
*/
/* if x1 is not a constant, this macro won't make real sense :-) */
#ifdef __mc68000__
#define DIVUL(x1, x2) ({int res; asm("divul %1,%2,%3": "=d" (res): \
"d" (x2), "d" ((long)((x1) / 0x100000000ULL)), "0" ((long)(x1))); res;})
#else
/* We know a bit about the numbers, so we can do it this way */
#define DIVUL(x1, x2) ((((long)((unsigned long long)x1 >> 8) / x2) << 8) + \
((((long)((unsigned long long)x1 >> 8) % x2) << 8) / x2))
#endif
#define highw(x) ((u_long)(x)>>16 & 0xffff)
#define loww(x) ((u_long)(x) & 0xffff)
#define custom amiga_custom
#define VBlankOn() custom.intena = IF_SETCLR|IF_COPER
#define VBlankOff() custom.intena = IF_COPER
/*
* Chip RAM we reserve for the Frame Buffer
*
* This defines the Maximum Virtual Screen Size
* (Setable per kernel options?)
*/
#define VIDEOMEMSIZE_AGA_2M (1310720) /* AGA (2MB) : max 1280*1024*256 */
#define VIDEOMEMSIZE_AGA_1M (786432) /* AGA (1MB) : max 1024*768*256 */
#define VIDEOMEMSIZE_ECS_2M (655360) /* ECS (2MB) : max 1280*1024*16 */
#define VIDEOMEMSIZE_ECS_1M (393216) /* ECS (1MB) : max 1024*768*16 */
#define VIDEOMEMSIZE_OCS (262144) /* OCS : max ca. 800*600*16 */
#define SPRITEMEMSIZE (64 * 64 / 4) /* max 64*64*4 */
#define DUMMYSPRITEMEMSIZE (8)
static u_long spritememory;
#define CHIPRAM_SAFETY_LIMIT (16384)
static u_long videomemory;
/*
* This is the earliest allowed start of fetching display data.
* Only if you really want no hardware cursor and audio,
* set this to 128, but let it better at 192
*/
static u_long min_fstrt = 192;
#define assignchunk(name, type, ptr, size) \
{ \
(name) = (type)(ptr); \
ptr += size; \
}
/*
* Copper Instructions
*/
#define CMOVE(val, reg) (CUSTOM_OFS(reg) << 16 | (val))
#define CMOVE2(val, reg) ((CUSTOM_OFS(reg) + 2) << 16 | (val))
#define CWAIT(x, y) (((y) & 0x1fe) << 23 | ((x) & 0x7f0) << 13 | 0x0001fffe)
#define CEND (0xfffffffe)
typedef union {
u_long l;
u_short w[2];
} copins;
static struct copdisplay {
copins *init;
copins *wait;
copins *list[2][2];
copins *rebuild[2];
} copdisplay;
static u_short currentcop = 0;
/*
* Hardware Cursor API Definitions
* These used to be in linux/fb.h, but were preliminary and used by
* amifb only anyway
*/
#define FBIOGET_FCURSORINFO 0x4607
#define FBIOGET_VCURSORINFO 0x4608
#define FBIOPUT_VCURSORINFO 0x4609
#define FBIOGET_CURSORSTATE 0x460A
#define FBIOPUT_CURSORSTATE 0x460B
struct fb_fix_cursorinfo {
__u16 crsr_width; /* width and height of the cursor in */
__u16 crsr_height; /* pixels (zero if no cursor) */
__u16 crsr_xsize; /* cursor size in display pixels */
__u16 crsr_ysize;
__u16 crsr_color1; /* colormap entry for cursor color1 */
__u16 crsr_color2; /* colormap entry for cursor color2 */
};
struct fb_var_cursorinfo {
__u16 width;
__u16 height;
__u16 xspot;
__u16 yspot;
DECLARE_FLEX_ARRAY(__u8, data); /* field with [height][width] */
};
struct fb_cursorstate {
__s16 xoffset;
__s16 yoffset;
__u16 mode;
};
#define FB_CURSOR_OFF 0
#define FB_CURSOR_ON 1
#define FB_CURSOR_FLASH 2
/*
* Hardware Cursor
*/
static int cursorrate = 20; /* Number of frames/flash toggle */
static u_short cursorstate = -1;
static u_short cursormode = FB_CURSOR_OFF;
static u_short *lofsprite, *shfsprite, *dummysprite;
/*
* Current Video Mode
*/
struct amifb_par {
/* General Values */
int xres; /* vmode */
int yres; /* vmode */
int vxres; /* vmode */
int vyres; /* vmode */
int xoffset; /* vmode */
int yoffset; /* vmode */
u_short bpp; /* vmode */
u_short clk_shift; /* vmode */
u_short line_shift; /* vmode */
int vmode; /* vmode */
u_short diwstrt_h; /* vmode */
u_short diwstop_h; /* vmode */
u_short diwstrt_v; /* vmode */
u_short diwstop_v; /* vmode */
u_long next_line; /* modulo for next line */
u_long next_plane; /* modulo for next plane */
/* Cursor Values */
struct {
short crsr_x; /* movecursor */
short crsr_y; /* movecursor */
short spot_x;
short spot_y;
u_short height;
u_short width;
u_short fmode;
} crsr;
/* OCS Hardware Registers */
u_long bplpt0; /* vmode, pan (Note: physical address) */
u_long bplpt0wrap; /* vmode, pan (Note: physical address) */
u_short ddfstrt;
u_short ddfstop;
u_short bpl1mod;
u_short bpl2mod;
u_short bplcon0; /* vmode */
u_short bplcon1; /* vmode */
u_short htotal; /* vmode */
u_short vtotal; /* vmode */
/* Additional ECS Hardware Registers */
u_short bplcon3; /* vmode */
u_short beamcon0; /* vmode */
u_short hsstrt; /* vmode */
u_short hsstop; /* vmode */
u_short hbstrt; /* vmode */
u_short hbstop; /* vmode */
u_short vsstrt; /* vmode */
u_short vsstop; /* vmode */
u_short vbstrt; /* vmode */
u_short vbstop; /* vmode */
u_short hcenter; /* vmode */
/* Additional AGA Hardware Registers */
u_short fmode; /* vmode */
};
/*
* Saved color entry 0 so we can restore it when unblanking
*/
static u_char red0, green0, blue0;
#if defined(CONFIG_FB_AMIGA_ECS)
static u_short ecs_palette[32];
#endif
/*
* Latches for Display Changes during VBlank
*/
static u_short do_vmode_full = 0; /* Change the Video Mode */
static u_short do_vmode_pan = 0; /* Update the Video Mode */
static short do_blank = 0; /* (Un)Blank the Screen (±1) */
static u_short do_cursor = 0; /* Move the Cursor */
/*
* Various Flags
*/
static u_short is_blanked = 0; /* Screen is Blanked */
static u_short is_lace = 0; /* Screen is laced */
/*
* Predefined Video Modes
*
*/
static struct fb_videomode ami_modedb[] __initdata = {
/*
* AmigaOS Video Modes
*
* If you change these, make sure to update DEFMODE_* as well!
*/
{
/* 640x200, 15 kHz, 60 Hz (NTSC) */
"ntsc", 60, 640, 200, TAG_HIRES, 106, 86, 44, 16, 76, 2,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 640x400, 15 kHz, 60 Hz interlaced (NTSC) */
"ntsc-lace", 60, 640, 400, TAG_HIRES, 106, 86, 88, 33, 76, 4,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
}, {
/* 640x256, 15 kHz, 50 Hz (PAL) */
"pal", 50, 640, 256, TAG_HIRES, 106, 86, 40, 14, 76, 2,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 640x512, 15 kHz, 50 Hz interlaced (PAL) */
"pal-lace", 50, 640, 512, TAG_HIRES, 106, 86, 80, 29, 76, 4,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
}, {
/* 640x480, 29 kHz, 57 Hz */
"multiscan", 57, 640, 480, TAG_SHRES, 96, 112, 29, 8, 72, 8,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 640x960, 29 kHz, 57 Hz interlaced */
"multiscan-lace", 57, 640, 960, TAG_SHRES, 96, 112, 58, 16, 72,
16,
0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
}, {
/* 640x200, 15 kHz, 72 Hz */
"euro36", 72, 640, 200, TAG_HIRES, 92, 124, 6, 6, 52, 5,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 640x400, 15 kHz, 72 Hz interlaced */
"euro36-lace", 72, 640, 400, TAG_HIRES, 92, 124, 12, 12, 52,
10,
0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
}, {
/* 640x400, 29 kHz, 68 Hz */
"euro72", 68, 640, 400, TAG_SHRES, 164, 92, 9, 9, 80, 8,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 640x800, 29 kHz, 68 Hz interlaced */
"euro72-lace", 68, 640, 800, TAG_SHRES, 164, 92, 18, 18, 80,
16,
0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
}, {
/* 800x300, 23 kHz, 70 Hz */
"super72", 70, 800, 300, TAG_SHRES, 212, 140, 10, 11, 80, 7,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 800x600, 23 kHz, 70 Hz interlaced */
"super72-lace", 70, 800, 600, TAG_SHRES, 212, 140, 20, 22, 80,
14,
0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
}, {
/* 640x200, 27 kHz, 57 Hz doublescan */
"dblntsc", 57, 640, 200, TAG_SHRES, 196, 124, 18, 17, 80, 4,
0, FB_VMODE_DOUBLE | FB_VMODE_YWRAP
}, {
/* 640x400, 27 kHz, 57 Hz */
"dblntsc-ff", 57, 640, 400, TAG_SHRES, 196, 124, 36, 35, 80, 7,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 640x800, 27 kHz, 57 Hz interlaced */
"dblntsc-lace", 57, 640, 800, TAG_SHRES, 196, 124, 72, 70, 80,
14,
0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
}, {
/* 640x256, 27 kHz, 47 Hz doublescan */
"dblpal", 47, 640, 256, TAG_SHRES, 196, 124, 14, 13, 80, 4,
0, FB_VMODE_DOUBLE | FB_VMODE_YWRAP
}, {
/* 640x512, 27 kHz, 47 Hz */
"dblpal-ff", 47, 640, 512, TAG_SHRES, 196, 124, 28, 27, 80, 7,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 640x1024, 27 kHz, 47 Hz interlaced */
"dblpal-lace", 47, 640, 1024, TAG_SHRES, 196, 124, 56, 54, 80,
14,
0, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
},
/*
* VGA Video Modes
*/
{
/* 640x480, 31 kHz, 60 Hz (VGA) */
"vga", 60, 640, 480, TAG_SHRES, 64, 96, 30, 9, 112, 2,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 640x400, 31 kHz, 70 Hz (VGA) */
"vga70", 70, 640, 400, TAG_SHRES, 64, 96, 35, 12, 112, 2,
FB_SYNC_VERT_HIGH_ACT | FB_SYNC_COMP_HIGH_ACT,
FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
},
#if 0
/*
* A2024 video modes
* These modes don't work yet because there's no A2024 driver.
*/
{
/* 1024x800, 10 Hz */
"a2024-10", 10, 1024, 800, TAG_HIRES, 0, 0, 0, 0, 0, 0,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}, {
/* 1024x800, 15 Hz */
"a2024-15", 15, 1024, 800, TAG_HIRES, 0, 0, 0, 0, 0, 0,
0, FB_VMODE_NONINTERLACED | FB_VMODE_YWRAP
}
#endif
};
#define NUM_TOTAL_MODES ARRAY_SIZE(ami_modedb)
static char *mode_option __initdata = NULL;
static int round_down_bpp = 1; /* for mode probing */
/*
* Some default modes
*/
#define DEFMODE_PAL 2 /* "pal" for PAL OCS/ECS */
#define DEFMODE_NTSC 0 /* "ntsc" for NTSC OCS/ECS */
#define DEFMODE_AMBER_PAL 3 /* "pal-lace" for flicker fixed PAL (A3000) */
#define DEFMODE_AMBER_NTSC 1 /* "ntsc-lace" for flicker fixed NTSC (A3000) */
#define DEFMODE_AGA 19 /* "vga70" for AGA */
static int amifb_ilbm = 0; /* interleaved or normal bitplanes */
static u32 amifb_hfmin __initdata; /* monitor hfreq lower limit (Hz) */
static u32 amifb_hfmax __initdata; /* monitor hfreq upper limit (Hz) */
static u16 amifb_vfmin __initdata; /* monitor vfreq lower limit (Hz) */
static u16 amifb_vfmax __initdata; /* monitor vfreq upper limit (Hz) */
/*
* Macros for the conversion from real world values to hardware register
* values
*
* This helps us to keep our attention on the real stuff...
*
* Hardware limits for AGA:
*
* parameter min max step
* --------- --- ---- ----
* diwstrt_h 0 2047 1
* diwstrt_v 0 2047 1
* diwstop_h 0 4095 1
* diwstop_v 0 4095 1
*
* ddfstrt 0 2032 16
* ddfstop 0 2032 16
*
* htotal 8 2048 8
* hsstrt 0 2040 8
* hsstop 0 2040 8
* vtotal 1 4096 1
* vsstrt 0 4095 1
* vsstop 0 4095 1
* hcenter 0 2040 8
*
* hbstrt 0 2047 1
* hbstop 0 2047 1
* vbstrt 0 4095 1
* vbstop 0 4095 1
*
* Horizontal values are in 35 ns (SHRES) pixels
* Vertical values are in half scanlines
*/
/* bplcon1 (smooth scrolling) */
#define hscroll2hw(hscroll) \
(((hscroll) << 12 & 0x3000) | ((hscroll) << 8 & 0xc300) | \
((hscroll) << 4 & 0x0c00) | ((hscroll) << 2 & 0x00f0) | \
((hscroll)>>2 & 0x000f))
/* diwstrt/diwstop/diwhigh (visible display window) */
#define diwstrt2hw(diwstrt_h, diwstrt_v) \
(((diwstrt_v) << 7 & 0xff00) | ((diwstrt_h)>>2 & 0x00ff))
#define diwstop2hw(diwstop_h, diwstop_v) \
(((diwstop_v) << 7 & 0xff00) | ((diwstop_h)>>2 & 0x00ff))
#define diwhigh2hw(diwstrt_h, diwstrt_v, diwstop_h, diwstop_v) \
(((diwstop_h) << 3 & 0x2000) | ((diwstop_h) << 11 & 0x1800) | \
((diwstop_v)>>1 & 0x0700) | ((diwstrt_h)>>5 & 0x0020) | \
((diwstrt_h) << 3 & 0x0018) | ((diwstrt_v)>>9 & 0x0007))
/* ddfstrt/ddfstop (display DMA) */
#define ddfstrt2hw(ddfstrt) div8(ddfstrt)
#define ddfstop2hw(ddfstop) div8(ddfstop)
/* hsstrt/hsstop/htotal/vsstrt/vsstop/vtotal/hcenter (sync timings) */
#define hsstrt2hw(hsstrt) (div8(hsstrt))
#define hsstop2hw(hsstop) (div8(hsstop))
#define htotal2hw(htotal) (div8(htotal) - 1)
#define vsstrt2hw(vsstrt) (div2(vsstrt))
#define vsstop2hw(vsstop) (div2(vsstop))
#define vtotal2hw(vtotal) (div2(vtotal) - 1)
#define hcenter2hw(htotal) (div8(htotal))
/* hbstrt/hbstop/vbstrt/vbstop (blanking timings) */
#define hbstrt2hw(hbstrt) (((hbstrt) << 8 & 0x0700) | ((hbstrt)>>3 & 0x00ff))
#define hbstop2hw(hbstop) (((hbstop) << 8 & 0x0700) | ((hbstop)>>3 & 0x00ff))
#define vbstrt2hw(vbstrt) (div2(vbstrt))
#define vbstop2hw(vbstop) (div2(vbstop))
/* colour */
#define rgb2hw8_high(red, green, blue) \
(((red & 0xf0) << 4) | (green & 0xf0) | ((blue & 0xf0)>>4))
#define rgb2hw8_low(red, green, blue) \
(((red & 0x0f) << 8) | ((green & 0x0f) << 4) | (blue & 0x0f))
#define rgb2hw4(red, green, blue) \
(((red & 0xf0) << 4) | (green & 0xf0) | ((blue & 0xf0)>>4))
#define rgb2hw2(red, green, blue) \
(((red & 0xc0) << 4) | (green & 0xc0) | ((blue & 0xc0)>>4))
/* sprpos/sprctl (sprite positioning) */
#define spr2hw_pos(start_v, start_h) \
(((start_v) << 7 & 0xff00) | ((start_h)>>3 & 0x00ff))
#define spr2hw_ctl(start_v, start_h, stop_v) \
(((stop_v) << 7 & 0xff00) | ((start_v)>>4 & 0x0040) | \
((stop_v)>>5 & 0x0020) | ((start_h) << 3 & 0x0018) | \
((start_v)>>7 & 0x0004) | ((stop_v)>>8 & 0x0002) | \
((start_h)>>2 & 0x0001))
/* get current vertical position of beam */
#define get_vbpos() ((u_short)((*(u_long volatile *)&custom.vposr >> 7) & 0xffe))
/*
* Copper Initialisation List
*/
#define COPINITSIZE (sizeof(copins) * 40)
enum {
cip_bplcon0
};
/*
* Long Frame/Short Frame Copper List
* Don't change the order, build_copper()/rebuild_copper() rely on this
*/
#define COPLISTSIZE (sizeof(copins) * 64)
enum {
cop_wait, cop_bplcon0,
cop_spr0ptrh, cop_spr0ptrl,
cop_diwstrt, cop_diwstop,
cop_diwhigh,
};
/*
* Pixel modes for Bitplanes and Sprites
*/
static u_short bplpixmode[3] = {
BPC0_SHRES, /* 35 ns */
BPC0_HIRES, /* 70 ns */
0 /* 140 ns */
};
static u_short sprpixmode[3] = {
BPC3_SPRES1 | BPC3_SPRES0, /* 35 ns */
BPC3_SPRES1, /* 70 ns */
BPC3_SPRES0 /* 140 ns */
};
/*
* Fetch modes for Bitplanes and Sprites
*/
static u_short bplfetchmode[3] = {
0, /* 1x */
FMODE_BPL32, /* 2x */
FMODE_BPAGEM | FMODE_BPL32 /* 4x */
};
static u_short sprfetchmode[3] = {
0, /* 1x */
FMODE_SPR32, /* 2x */
FMODE_SPAGEM | FMODE_SPR32 /* 4x */
};
/* --------------------------- Hardware routines --------------------------- */
/*
* Get the video params out of `var'. If a value doesn't fit, round
* it up, if it's too big, return -EINVAL.
*/
static int ami_decode_var(struct fb_var_screeninfo *var, struct amifb_par *par,
const struct fb_info *info)
{
u_short clk_shift, line_shift;
u_long maxfetchstop, fstrt, fsize, fconst, xres_n, yres_n;
u_int htotal, vtotal;
/*
* Find a matching Pixel Clock
*/
for (clk_shift = TAG_SHRES; clk_shift <= TAG_LORES; clk_shift++)
if (var->pixclock <= pixclock[clk_shift])
break;
if (clk_shift > TAG_LORES) {
DPRINTK("pixclock too high\n");
return -EINVAL;
}
par->clk_shift = clk_shift;
/*
* Check the Geometry Values
*/
if ((par->xres = var->xres) < 64)
par->xres = 64;
if ((par->yres = var->yres) < 64)
par->yres = 64;
if ((par->vxres = var->xres_virtual) < par->xres)
par->vxres = par->xres;
if ((par->vyres = var->yres_virtual) < par->yres)
par->vyres = par->yres;
par->bpp = var->bits_per_pixel;
if (!var->nonstd) {
if (par->bpp < 1)
par->bpp = 1;
if (par->bpp > maxdepth[clk_shift]) {
if (round_down_bpp && maxdepth[clk_shift])
par->bpp = maxdepth[clk_shift];
else {
DPRINTK("invalid bpp\n");
return -EINVAL;
}
}
} else if (var->nonstd == FB_NONSTD_HAM) {
if (par->bpp < 6)
par->bpp = 6;
if (par->bpp != 6) {
if (par->bpp < 8)
par->bpp = 8;
if (par->bpp != 8 || !IS_AGA) {
DPRINTK("invalid bpp for ham mode\n");
return -EINVAL;
}
}
} else {
DPRINTK("unknown nonstd mode\n");
return -EINVAL;
}
/*
* FB_VMODE_SMOOTH_XPAN will be cleared, if one of the following
* checks failed and smooth scrolling is not possible
*/
par->vmode = var->vmode | FB_VMODE_SMOOTH_XPAN;
switch (par->vmode & FB_VMODE_MASK) {
case FB_VMODE_INTERLACED:
line_shift = 0;
break;
case FB_VMODE_NONINTERLACED:
line_shift = 1;
break;
case FB_VMODE_DOUBLE:
if (!IS_AGA) {
DPRINTK("double mode only possible with aga\n");
return -EINVAL;
}
line_shift = 2;
break;
default:
DPRINTK("unknown video mode\n");
return -EINVAL;
break;
}
par->line_shift = line_shift;
/*
* Vertical and Horizontal Timings
*/
xres_n = par->xres << clk_shift;
yres_n = par->yres << line_shift;
par->htotal = down8((var->left_margin + par->xres + var->right_margin +
var->hsync_len) << clk_shift);
par->vtotal =
down2(((var->upper_margin + par->yres + var->lower_margin +
var->vsync_len) << line_shift) + 1);
if (IS_AGA)
par->bplcon3 = sprpixmode[clk_shift];
else
par->bplcon3 = 0;
if (var->sync & FB_SYNC_BROADCAST) {
par->diwstop_h = par->htotal -
((var->right_margin - var->hsync_len) << clk_shift);
if (IS_AGA)
par->diwstop_h += mod4(var->hsync_len);
else
par->diwstop_h = down4(par->diwstop_h);
par->diwstrt_h = par->diwstop_h - xres_n;
par->diwstop_v = par->vtotal -
((var->lower_margin - var->vsync_len) << line_shift);
par->diwstrt_v = par->diwstop_v - yres_n;
if (par->diwstop_h >= par->htotal + 8) {
DPRINTK("invalid diwstop_h\n");
return -EINVAL;
}
if (par->diwstop_v > par->vtotal) {
DPRINTK("invalid diwstop_v\n");
return -EINVAL;
}
if (!IS_OCS) {
/* Initialize sync with some reasonable values for pwrsave */
par->hsstrt = 160;
par->hsstop = 320;
par->vsstrt = 30;
par->vsstop = 34;
} else {
par->hsstrt = 0;
par->hsstop = 0;
par->vsstrt = 0;
par->vsstop = 0;
}
if (par->vtotal > (PAL_VTOTAL + NTSC_VTOTAL) / 2) {
/* PAL video mode */
if (par->htotal != PAL_HTOTAL) {
DPRINTK("htotal invalid for pal\n");
return -EINVAL;
}
if (par->diwstrt_h < PAL_DIWSTRT_H) {
DPRINTK("diwstrt_h too low for pal\n");
return -EINVAL;
}
if (par->diwstrt_v < PAL_DIWSTRT_V) {
DPRINTK("diwstrt_v too low for pal\n");
return -EINVAL;
}
htotal = PAL_HTOTAL>>clk_shift;
vtotal = PAL_VTOTAL>>1;
if (!IS_OCS) {
par->beamcon0 = BMC0_PAL;
par->bplcon3 |= BPC3_BRDRBLNK;
} else if (AMIGAHW_PRESENT(AGNUS_HR_PAL) ||
AMIGAHW_PRESENT(AGNUS_HR_NTSC)) {
par->beamcon0 = BMC0_PAL;
par->hsstop = 1;
} else if (amiga_vblank != 50) {
DPRINTK("pal not supported by this chipset\n");
return -EINVAL;
}
} else {
/* NTSC video mode
* In the AGA chipset seems to be hardware bug with BPC3_BRDRBLNK
* and NTSC activated, so than better let diwstop_h <= 1812
*/
if (par->htotal != NTSC_HTOTAL) {
DPRINTK("htotal invalid for ntsc\n");
return -EINVAL;
}
if (par->diwstrt_h < NTSC_DIWSTRT_H) {
DPRINTK("diwstrt_h too low for ntsc\n");
return -EINVAL;
}
if (par->diwstrt_v < NTSC_DIWSTRT_V) {
DPRINTK("diwstrt_v too low for ntsc\n");
return -EINVAL;
}
htotal = NTSC_HTOTAL>>clk_shift;
vtotal = NTSC_VTOTAL>>1;
if (!IS_OCS) {
par->beamcon0 = 0;
par->bplcon3 |= BPC3_BRDRBLNK;
} else if (AMIGAHW_PRESENT(AGNUS_HR_PAL) ||
AMIGAHW_PRESENT(AGNUS_HR_NTSC)) {
par->beamcon0 = 0;
par->hsstop = 1;
} else if (amiga_vblank != 60) {
DPRINTK("ntsc not supported by this chipset\n");
return -EINVAL;
}
}
if (IS_OCS) {
if (par->diwstrt_h >= 1024 || par->diwstop_h < 1024 ||
par->diwstrt_v >= 512 || par->diwstop_v < 256) {
DPRINTK("invalid position for display on ocs\n");
return -EINVAL;
}
}
} else if (!IS_OCS) {
/* Programmable video mode */
par->hsstrt = var->right_margin << clk_shift;
par->hsstop = (var->right_margin + var->hsync_len) << clk_shift;
par->diwstop_h = par->htotal - mod8(par->hsstrt) + 8 - (1 << clk_shift);
if (!IS_AGA)
par->diwstop_h = down4(par->diwstop_h) - 16;
par->diwstrt_h = par->diwstop_h - xres_n;
par->hbstop = par->diwstrt_h + 4;
par->hbstrt = par->diwstop_h + 4;
if (par->hbstrt >= par->htotal + 8)
par->hbstrt -= par->htotal;
par->hcenter = par->hsstrt + (par->htotal >> 1);
par->vsstrt = var->lower_margin << line_shift;
par->vsstop = (var->lower_margin + var->vsync_len) << line_shift;
par->diwstop_v = par->vtotal;
if ((par->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
par->diwstop_v -= 2;
par->diwstrt_v = par->diwstop_v - yres_n;
par->vbstop = par->diwstrt_v - 2;
par->vbstrt = par->diwstop_v - 2;
if (par->vtotal > 2048) {
DPRINTK("vtotal too high\n");
return -EINVAL;
}
if (par->htotal > 2048) {
DPRINTK("htotal too high\n");
return -EINVAL;
}
par->bplcon3 |= BPC3_EXTBLKEN;
par->beamcon0 = BMC0_HARDDIS | BMC0_VARVBEN | BMC0_LOLDIS |
BMC0_VARVSYEN | BMC0_VARHSYEN | BMC0_VARBEAMEN |
BMC0_PAL | BMC0_VARCSYEN;
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
par->beamcon0 |= BMC0_HSYTRUE;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
par->beamcon0 |= BMC0_VSYTRUE;
if (var->sync & FB_SYNC_COMP_HIGH_ACT)
par->beamcon0 |= BMC0_CSYTRUE;
htotal = par->htotal>>clk_shift;
vtotal = par->vtotal>>1;
} else {
DPRINTK("only broadcast modes possible for ocs\n");
return -EINVAL;
}
/*
* Checking the DMA timing
*/
fconst = 16 << maxfmode << clk_shift;
/*
* smallest window start value without turn off other dma cycles
* than sprite1-7, unless you change min_fstrt
*/
fsize = ((maxfmode + clk_shift <= 1) ? fconst : 64);
fstrt = downx(fconst, par->diwstrt_h - 4) - fsize;
if (fstrt < min_fstrt) {
DPRINTK("fetch start too low\n");
return -EINVAL;
}
/*
* smallest window start value where smooth scrolling is possible
*/
fstrt = downx(fconst, par->diwstrt_h - fconst + (1 << clk_shift) - 4) -
fsize;
if (fstrt < min_fstrt)
par->vmode &= ~FB_VMODE_SMOOTH_XPAN;
maxfetchstop = down16(par->htotal - 80);
fstrt = downx(fconst, par->diwstrt_h - 4) - 64 - fconst;
fsize = upx(fconst, xres_n +
modx(fconst, downx(1 << clk_shift, par->diwstrt_h - 4)));
if (fstrt + fsize > maxfetchstop)
par->vmode &= ~FB_VMODE_SMOOTH_XPAN;
fsize = upx(fconst, xres_n);
if (fstrt + fsize > maxfetchstop) {
DPRINTK("fetch stop too high\n");
return -EINVAL;
}
if (maxfmode + clk_shift <= 1) {
fsize = up64(xres_n + fconst - 1);
if (min_fstrt + fsize - 64 > maxfetchstop)
par->vmode &= ~FB_VMODE_SMOOTH_XPAN;
fsize = up64(xres_n);
if (min_fstrt + fsize - 64 > maxfetchstop) {
DPRINTK("fetch size too high\n");
return -EINVAL;
}
fsize -= 64;
} else
fsize -= fconst;
/*
* Check if there is enough time to update the bitplane pointers for ywrap
*/
if (par->htotal - fsize - 64 < par->bpp * 64)
par->vmode &= ~FB_VMODE_YWRAP;
/*
* Bitplane calculations and check the Memory Requirements
*/
if (amifb_ilbm) {
par->next_plane = div8(upx(16 << maxfmode, par->vxres));
par->next_line = par->bpp * par->next_plane;
if (par->next_line * par->vyres > info->fix.smem_len) {
DPRINTK("too few video mem\n");
return -EINVAL;
}
} else {
par->next_line = div8(upx(16 << maxfmode, par->vxres));
par->next_plane = par->vyres * par->next_line;
if (par->next_plane * par->bpp > info->fix.smem_len) {
DPRINTK("too few video mem\n");
return -EINVAL;
}
}
/*
* Hardware Register Values
*/
par->bplcon0 = BPC0_COLOR | bplpixmode[clk_shift];
if (!IS_OCS)
par->bplcon0 |= BPC0_ECSENA;
if (par->bpp == 8)
par->bplcon0 |= BPC0_BPU3;
else
par->bplcon0 |= par->bpp << 12;
if (var->nonstd == FB_NONSTD_HAM)
par->bplcon0 |= BPC0_HAM;
if (var->sync & FB_SYNC_EXT)
par->bplcon0 |= BPC0_ERSY;
if (IS_AGA)
par->fmode = bplfetchmode[maxfmode];
switch (par->vmode & FB_VMODE_MASK) {
case FB_VMODE_INTERLACED:
par->bplcon0 |= BPC0_LACE;
break;
case FB_VMODE_DOUBLE:
if (IS_AGA)
par->fmode |= FMODE_SSCAN2 | FMODE_BSCAN2;
break;
}
if (!((par->vmode ^ var->vmode) & FB_VMODE_YWRAP)) {
par->xoffset = var->xoffset;
par->yoffset = var->yoffset;
if (par->vmode & FB_VMODE_YWRAP) {
if (par->yoffset >= par->vyres)
par->xoffset = par->yoffset = 0;
} else {
if (par->xoffset > upx(16 << maxfmode, par->vxres - par->xres) ||
par->yoffset > par->vyres - par->yres)
par->xoffset = par->yoffset = 0;
}
} else
par->xoffset = par->yoffset = 0;
par->crsr.crsr_x = par->crsr.crsr_y = 0;
par->crsr.spot_x = par->crsr.spot_y = 0;
par->crsr.height = par->crsr.width = 0;
return 0;
}
/*
* Fill the `var' structure based on the values in `par' and maybe
* other values read out of the hardware.
*/
static void ami_encode_var(struct fb_var_screeninfo *var,
struct amifb_par *par)
{
u_short clk_shift, line_shift;
memset(var, 0, sizeof(struct fb_var_screeninfo));
clk_shift = par->clk_shift;
line_shift = par->line_shift;
var->xres = par->xres;
var->yres = par->yres;
var->xres_virtual = par->vxres;
var->yres_virtual = par->vyres;
var->xoffset = par->xoffset;
var->yoffset = par->yoffset;
var->bits_per_pixel = par->bpp;
var->grayscale = 0;
var->red.offset = 0;
var->red.msb_right = 0;
var->red.length = par->bpp;
if (par->bplcon0 & BPC0_HAM)
var->red.length -= 2;
var->blue = var->green = var->red;
var->transp.offset = 0;
var->transp.length = 0;
var->transp.msb_right = 0;
if (par->bplcon0 & BPC0_HAM)
var->nonstd = FB_NONSTD_HAM;
else
var->nonstd = 0;
var->activate = 0;
var->height = -1;
var->width = -1;
var->pixclock = pixclock[clk_shift];
if (IS_AGA && par->fmode & FMODE_BSCAN2)
var->vmode = FB_VMODE_DOUBLE;
else if (par->bplcon0 & BPC0_LACE)
var->vmode = FB_VMODE_INTERLACED;
else
var->vmode = FB_VMODE_NONINTERLACED;
if (!IS_OCS && par->beamcon0 & BMC0_VARBEAMEN) {
var->hsync_len = (par->hsstop - par->hsstrt)>>clk_shift;
var->right_margin = par->hsstrt>>clk_shift;
var->left_margin = (par->htotal>>clk_shift) - var->xres - var->right_margin - var->hsync_len;
var->vsync_len = (par->vsstop - par->vsstrt)>>line_shift;
var->lower_margin = par->vsstrt>>line_shift;
var->upper_margin = (par->vtotal>>line_shift) - var->yres - var->lower_margin - var->vsync_len;
var->sync = 0;
if (par->beamcon0 & BMC0_HSYTRUE)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (par->beamcon0 & BMC0_VSYTRUE)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
if (par->beamcon0 & BMC0_CSYTRUE)
var->sync |= FB_SYNC_COMP_HIGH_ACT;
} else {
var->sync = FB_SYNC_BROADCAST;
var->hsync_len = (152>>clk_shift) + mod4(par->diwstop_h);
var->right_margin = ((par->htotal - down4(par->diwstop_h))>>clk_shift) + var->hsync_len;
var->left_margin = (par->htotal>>clk_shift) - var->xres - var->right_margin - var->hsync_len;
var->vsync_len = 4>>line_shift;
var->lower_margin = ((par->vtotal - par->diwstop_v)>>line_shift) + var->vsync_len;
var->upper_margin = (((par->vtotal - 2)>>line_shift) + 1) - var->yres -
var->lower_margin - var->vsync_len;
}
if (par->bplcon0 & BPC0_ERSY)
var->sync |= FB_SYNC_EXT;
if (par->vmode & FB_VMODE_YWRAP)
var->vmode |= FB_VMODE_YWRAP;
}
/*
* Update hardware
*/
static void ami_update_par(struct fb_info *info)
{
struct amifb_par *par = info->par;
short clk_shift, vshift, fstrt, fsize, fstop, fconst, shift, move, mod;
clk_shift = par->clk_shift;
if (!(par->vmode & FB_VMODE_SMOOTH_XPAN))
par->xoffset = upx(16 << maxfmode, par->xoffset);
fconst = 16 << maxfmode << clk_shift;
vshift = modx(16 << maxfmode, par->xoffset);
fstrt = par->diwstrt_h - (vshift << clk_shift) - 4;
fsize = (par->xres + vshift) << clk_shift;
shift = modx(fconst, fstrt);
move = downx(2 << maxfmode, div8(par->xoffset));
if (maxfmode + clk_shift > 1) {
fstrt = downx(fconst, fstrt) - 64;
fsize = upx(fconst, fsize);
fstop = fstrt + fsize - fconst;
} else {
mod = fstrt = downx(fconst, fstrt) - fconst;
fstop = fstrt + upx(fconst, fsize) - 64;
fsize = up64(fsize);
fstrt = fstop - fsize + 64;
if (fstrt < min_fstrt) {
fstop += min_fstrt - fstrt;
fstrt = min_fstrt;
}
move = move - div8((mod - fstrt)>>clk_shift);
}
mod = par->next_line - div8(fsize>>clk_shift);
par->ddfstrt = fstrt;
par->ddfstop = fstop;
par->bplcon1 = hscroll2hw(shift);
par->bpl2mod = mod;
if (par->bplcon0 & BPC0_LACE)
par->bpl2mod += par->next_line;
if (IS_AGA && (par->fmode & FMODE_BSCAN2))
par->bpl1mod = -div8(fsize>>clk_shift);
else
par->bpl1mod = par->bpl2mod;
if (par->yoffset) {
par->bplpt0 = info->fix.smem_start +
par->next_line * par->yoffset + move;
if (par->vmode & FB_VMODE_YWRAP) {
if (par->yoffset > par->vyres - par->yres) {
par->bplpt0wrap = info->fix.smem_start + move;
if (par->bplcon0 & BPC0_LACE &&
mod2(par->diwstrt_v + par->vyres -
par->yoffset))
par->bplpt0wrap += par->next_line;
}
}
} else
par->bplpt0 = info->fix.smem_start + move;
if (par->bplcon0 & BPC0_LACE && mod2(par->diwstrt_v))
par->bplpt0 += par->next_line;
}
/*
* Pan or Wrap the Display
*
* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
* in `var'.
*/
static void ami_pan_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct amifb_par *par = info->par;
par->xoffset = var->xoffset;
par->yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP)
par->vmode |= FB_VMODE_YWRAP;
else
par->vmode &= ~FB_VMODE_YWRAP;
do_vmode_pan = 0;
ami_update_par(info);
do_vmode_pan = 1;
}
static void ami_update_display(const struct amifb_par *par)
{
custom.bplcon1 = par->bplcon1;
custom.bpl1mod = par->bpl1mod;
custom.bpl2mod = par->bpl2mod;
custom.ddfstrt = ddfstrt2hw(par->ddfstrt);
custom.ddfstop = ddfstop2hw(par->ddfstop);
}
/*
* Change the video mode (called by VBlank interrupt)
*/
static void ami_init_display(const struct amifb_par *par)
{
int i;
custom.bplcon0 = par->bplcon0 & ~BPC0_LACE;
custom.bplcon2 = (IS_OCS ? 0 : BPC2_KILLEHB) | BPC2_PF2P2 | BPC2_PF1P2;
if (!IS_OCS) {
custom.bplcon3 = par->bplcon3;
if (IS_AGA)
custom.bplcon4 = BPC4_ESPRM4 | BPC4_OSPRM4;
if (par->beamcon0 & BMC0_VARBEAMEN) {
custom.htotal = htotal2hw(par->htotal);
custom.hbstrt = hbstrt2hw(par->hbstrt);
custom.hbstop = hbstop2hw(par->hbstop);
custom.hsstrt = hsstrt2hw(par->hsstrt);
custom.hsstop = hsstop2hw(par->hsstop);
custom.hcenter = hcenter2hw(par->hcenter);
custom.vtotal = vtotal2hw(par->vtotal);
custom.vbstrt = vbstrt2hw(par->vbstrt);
custom.vbstop = vbstop2hw(par->vbstop);
custom.vsstrt = vsstrt2hw(par->vsstrt);
custom.vsstop = vsstop2hw(par->vsstop);
}
}
if (!IS_OCS || par->hsstop)
custom.beamcon0 = par->beamcon0;
if (IS_AGA)
custom.fmode = par->fmode;
/*
* The minimum period for audio depends on htotal
*/
amiga_audio_min_period = div16(par->htotal);
is_lace = par->bplcon0 & BPC0_LACE ? 1 : 0;
#if 1
if (is_lace) {
i = custom.vposr >> 15;
} else {
custom.vposw = custom.vposr | 0x8000;
i = 1;
}
#else
i = 1;
custom.vposw = custom.vposr | 0x8000;
#endif
custom.cop2lc = (u_short *)ZTWO_PADDR(copdisplay.list[currentcop][i]);
}
/*
* (Un)Blank the screen (called by VBlank interrupt)
*/
static void ami_do_blank(const struct amifb_par *par)
{
#if defined(CONFIG_FB_AMIGA_AGA)
u_short bplcon3 = par->bplcon3;
#endif
u_char red, green, blue;
if (do_blank > 0) {
custom.dmacon = DMAF_RASTER | DMAF_SPRITE;
red = green = blue = 0;
if (!IS_OCS && do_blank > 1) {
switch (do_blank) {
case FB_BLANK_VSYNC_SUSPEND:
custom.hsstrt = hsstrt2hw(par->hsstrt);
custom.hsstop = hsstop2hw(par->hsstop);
custom.vsstrt = vsstrt2hw(par->vtotal + 4);
custom.vsstop = vsstop2hw(par->vtotal + 4);
break;
case FB_BLANK_HSYNC_SUSPEND:
custom.hsstrt = hsstrt2hw(par->htotal + 16);
custom.hsstop = hsstop2hw(par->htotal + 16);
custom.vsstrt = vsstrt2hw(par->vsstrt);
custom.vsstop = vsstrt2hw(par->vsstop);
break;
case FB_BLANK_POWERDOWN:
custom.hsstrt = hsstrt2hw(par->htotal + 16);
custom.hsstop = hsstop2hw(par->htotal + 16);
custom.vsstrt = vsstrt2hw(par->vtotal + 4);
custom.vsstop = vsstop2hw(par->vtotal + 4);
break;
}
if (!(par->beamcon0 & BMC0_VARBEAMEN)) {
custom.htotal = htotal2hw(par->htotal);
custom.vtotal = vtotal2hw(par->vtotal);
custom.beamcon0 = BMC0_HARDDIS | BMC0_VARBEAMEN |
BMC0_VARVSYEN | BMC0_VARHSYEN | BMC0_VARCSYEN;
}
}
} else {
custom.dmacon = DMAF_SETCLR | DMAF_RASTER | DMAF_SPRITE;
red = red0;
green = green0;
blue = blue0;
if (!IS_OCS) {
custom.hsstrt = hsstrt2hw(par->hsstrt);
custom.hsstop = hsstop2hw(par->hsstop);
custom.vsstrt = vsstrt2hw(par->vsstrt);
custom.vsstop = vsstop2hw(par->vsstop);
custom.beamcon0 = par->beamcon0;
}
}
#if defined(CONFIG_FB_AMIGA_AGA)
if (IS_AGA) {
custom.bplcon3 = bplcon3;
custom.color[0] = rgb2hw8_high(red, green, blue);
custom.bplcon3 = bplcon3 | BPC3_LOCT;
custom.color[0] = rgb2hw8_low(red, green, blue);
custom.bplcon3 = bplcon3;
} else
#endif
#if defined(CONFIG_FB_AMIGA_ECS)
if (par->bplcon0 & BPC0_SHRES) {
u_short color, mask;
int i;
mask = 0x3333;
color = rgb2hw2(red, green, blue);
for (i = 12; i >= 0; i -= 4)
custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color;
mask <<= 2; color >>= 2;
for (i = 3; i >= 0; i--)
custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color;
} else
#endif
custom.color[0] = rgb2hw4(red, green, blue);
is_blanked = do_blank > 0 ? do_blank : 0;
}
static int ami_get_fix_cursorinfo(struct fb_fix_cursorinfo *fix,
const struct amifb_par *par)
{
fix->crsr_width = fix->crsr_xsize = par->crsr.width;
fix->crsr_height = fix->crsr_ysize = par->crsr.height;
fix->crsr_color1 = 17;
fix->crsr_color2 = 18;
return 0;
}
static int ami_get_var_cursorinfo(struct fb_var_cursorinfo *var,
u_char __user *data,
const struct amifb_par *par)
{
register u_short *lspr, *sspr;
#ifdef __mc68000__
register u_long datawords asm ("d2");
#else
register u_long datawords;
#endif
register short delta;
register u_char color;
short height, width, bits, words;
int size, alloc;
size = par->crsr.height * par->crsr.width;
alloc = var->height * var->width;
var->height = par->crsr.height;
var->width = par->crsr.width;
var->xspot = par->crsr.spot_x;
var->yspot = par->crsr.spot_y;
if (size > var->height * var->width)
return -ENAMETOOLONG;
delta = 1 << par->crsr.fmode;
lspr = lofsprite + (delta << 1);
if (par->bplcon0 & BPC0_LACE)
sspr = shfsprite + (delta << 1);
else
sspr = NULL;
for (height = (short)var->height - 1; height >= 0; height--) {
bits = 0; words = delta; datawords = 0;
for (width = (short)var->width - 1; width >= 0; width--) {
if (bits == 0) {
bits = 16; --words;
#ifdef __mc68000__
asm volatile ("movew %1@(%3:w:2),%0 ; swap %0 ; movew %1@+,%0"
: "=d" (datawords), "=a" (lspr) : "1" (lspr), "d" (delta));
#else
datawords = (*(lspr + delta) << 16) | (*lspr++);
#endif
}
--bits;
#ifdef __mc68000__
asm volatile (
"clrb %0 ; swap %1 ; lslw #1,%1 ; roxlb #1,%0 ; "
"swap %1 ; lslw #1,%1 ; roxlb #1,%0"
: "=d" (color), "=d" (datawords) : "1" (datawords));
#else
color = (((datawords >> 30) & 2)
| ((datawords >> 15) & 1));
datawords <<= 1;
#endif
/* FIXME: check the return value + test the change */
put_user(color, data++);
}
if (bits > 0) {
--words; ++lspr;
}
while (--words >= 0)
++lspr;
#ifdef __mc68000__
asm volatile ("lea %0@(%4:w:2),%0 ; tstl %1 ; jeq 1f ; exg %0,%1\n1:"
: "=a" (lspr), "=a" (sspr) : "0" (lspr), "1" (sspr), "d" (delta));
#else
lspr += delta;
if (sspr) {
u_short *tmp = lspr;
lspr = sspr;
sspr = tmp;
}
#endif
}
return 0;
}
static int ami_set_var_cursorinfo(struct fb_var_cursorinfo *var,
u_char __user *data, struct amifb_par *par)
{
register u_short *lspr, *sspr;
#ifdef __mc68000__
register u_long datawords asm ("d2");
#else
register u_long datawords;
#endif
register short delta;
u_short fmode;
short height, width, bits, words;
if (!var->width)
return -EINVAL;
else if (var->width <= 16)
fmode = TAG_FMODE_1;
else if (var->width <= 32)
fmode = TAG_FMODE_2;
else if (var->width <= 64)
fmode = TAG_FMODE_4;
else
return -EINVAL;
if (fmode > maxfmode)
return -EINVAL;
if (!var->height)
return -EINVAL;
delta = 1 << fmode;
lofsprite = shfsprite = (u_short *)spritememory;
lspr = lofsprite + (delta << 1);
if (par->bplcon0 & BPC0_LACE) {
if (((var->height + 4) << fmode << 2) > SPRITEMEMSIZE)
return -EINVAL;
memset(lspr, 0, (var->height + 4) << fmode << 2);
shfsprite += ((var->height + 5)&-2) << fmode;
sspr = shfsprite + (delta << 1);
} else {
if (((var->height + 2) << fmode << 2) > SPRITEMEMSIZE)
return -EINVAL;
memset(lspr, 0, (var->height + 2) << fmode << 2);
sspr = NULL;
}
for (height = (short)var->height - 1; height >= 0; height--) {
bits = 16; words = delta; datawords = 0;
for (width = (short)var->width - 1; width >= 0; width--) {
unsigned long tdata = 0;
/* FIXME: check the return value + test the change */
get_user(tdata, data);
data++;
#ifdef __mc68000__
asm volatile (
"lsrb #1,%2 ; roxlw #1,%0 ; swap %0 ; "
"lsrb #1,%2 ; roxlw #1,%0 ; swap %0"
: "=d" (datawords)
: "0" (datawords), "d" (tdata));
#else
datawords = ((datawords << 1) & 0xfffefffe);
datawords |= tdata & 1;
datawords |= (tdata & 2) << (16 - 1);
#endif
if (--bits == 0) {
bits = 16; --words;
#ifdef __mc68000__
asm volatile ("swap %2 ; movew %2,%0@(%3:w:2) ; swap %2 ; movew %2,%0@+"
: "=a" (lspr) : "0" (lspr), "d" (datawords), "d" (delta));
#else
*(lspr + delta) = (u_short) (datawords >> 16);
*lspr++ = (u_short) (datawords & 0xffff);
#endif
}
}
if (bits < 16) {
--words;
#ifdef __mc68000__
asm volatile (
"swap %2 ; lslw %4,%2 ; movew %2,%0@(%3:w:2) ; "
"swap %2 ; lslw %4,%2 ; movew %2,%0@+"
: "=a" (lspr) : "0" (lspr), "d" (datawords), "d" (delta), "d" (bits));
#else
*(lspr + delta) = (u_short) (datawords >> (16 + bits));
*lspr++ = (u_short) ((datawords & 0x0000ffff) >> bits);
#endif
}
while (--words >= 0) {
#ifdef __mc68000__
asm volatile ("moveql #0,%%d0 ; movew %%d0,%0@(%2:w:2) ; movew %%d0,%0@+"
: "=a" (lspr) : "0" (lspr), "d" (delta) : "d0");
#else
*(lspr + delta) = 0;
*lspr++ = 0;
#endif
}
#ifdef __mc68000__
asm volatile ("lea %0@(%4:w:2),%0 ; tstl %1 ; jeq 1f ; exg %0,%1\n1:"
: "=a" (lspr), "=a" (sspr) : "0" (lspr), "1" (sspr), "d" (delta));
#else
lspr += delta;
if (sspr) {
u_short *tmp = lspr;
lspr = sspr;
sspr = tmp;
}
#endif
}
par->crsr.height = var->height;
par->crsr.width = var->width;
par->crsr.spot_x = var->xspot;
par->crsr.spot_y = var->yspot;
par->crsr.fmode = fmode;
if (IS_AGA) {
par->fmode &= ~(FMODE_SPAGEM | FMODE_SPR32);
par->fmode |= sprfetchmode[fmode];
custom.fmode = par->fmode;
}
return 0;
}
static int ami_get_cursorstate(struct fb_cursorstate *state,
const struct amifb_par *par)
{
state->xoffset = par->crsr.crsr_x;
state->yoffset = par->crsr.crsr_y;
state->mode = cursormode;
return 0;
}
static int ami_set_cursorstate(struct fb_cursorstate *state,
struct amifb_par *par)
{
par->crsr.crsr_x = state->xoffset;
par->crsr.crsr_y = state->yoffset;
if ((cursormode = state->mode) == FB_CURSOR_OFF)
cursorstate = -1;
do_cursor = 1;
return 0;
}
static void ami_set_sprite(const struct amifb_par *par)
{
copins *copl, *cops;
u_short hs, vs, ve;
u_long pl, ps;
short mx, my;
cops = copdisplay.list[currentcop][0];
copl = copdisplay.list[currentcop][1];
ps = pl = ZTWO_PADDR(dummysprite);
mx = par->crsr.crsr_x - par->crsr.spot_x;
my = par->crsr.crsr_y - par->crsr.spot_y;
if (!(par->vmode & FB_VMODE_YWRAP)) {
mx -= par->xoffset;
my -= par->yoffset;
}
if (!is_blanked && cursorstate > 0 && par->crsr.height > 0 &&
mx > -(short)par->crsr.width && mx < par->xres &&
my > -(short)par->crsr.height && my < par->yres) {
pl = ZTWO_PADDR(lofsprite);
hs = par->diwstrt_h + (mx << par->clk_shift) - 4;
vs = par->diwstrt_v + (my << par->line_shift);
ve = vs + (par->crsr.height << par->line_shift);
if (par->bplcon0 & BPC0_LACE) {
ps = ZTWO_PADDR(shfsprite);
lofsprite[0] = spr2hw_pos(vs, hs);
shfsprite[0] = spr2hw_pos(vs + 1, hs);
if (mod2(vs)) {
lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve);
shfsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs + 1, hs, ve + 1);
swap(pl, ps);
} else {
lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve + 1);
shfsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs + 1, hs, ve);
}
} else {
lofsprite[0] = spr2hw_pos(vs, hs) | (IS_AGA && (par->fmode & FMODE_BSCAN2) ? 0x80 : 0);
lofsprite[1 << par->crsr.fmode] = spr2hw_ctl(vs, hs, ve);
}
}
copl[cop_spr0ptrh].w[1] = highw(pl);
copl[cop_spr0ptrl].w[1] = loww(pl);
if (par->bplcon0 & BPC0_LACE) {
cops[cop_spr0ptrh].w[1] = highw(ps);
cops[cop_spr0ptrl].w[1] = loww(ps);
}
}
/*
* Initialise the Copper Initialisation List
*/
static void __init ami_init_copper(void)
{
copins *cop = copdisplay.init;
u_long p;
int i;
if (!IS_OCS) {
(cop++)->l = CMOVE(BPC0_COLOR | BPC0_SHRES | BPC0_ECSENA, bplcon0);
(cop++)->l = CMOVE(0x0181, diwstrt);
(cop++)->l = CMOVE(0x0281, diwstop);
(cop++)->l = CMOVE(0x0000, diwhigh);
} else
(cop++)->l = CMOVE(BPC0_COLOR, bplcon0);
p = ZTWO_PADDR(dummysprite);
for (i = 0; i < 8; i++) {
(cop++)->l = CMOVE(0, spr[i].pos);
(cop++)->l = CMOVE(highw(p), sprpt[i]);
(cop++)->l = CMOVE2(loww(p), sprpt[i]);
}
(cop++)->l = CMOVE(IF_SETCLR | IF_COPER, intreq);
copdisplay.wait = cop;
(cop++)->l = CEND;
(cop++)->l = CMOVE(0, copjmp2);
cop->l = CEND;
custom.cop1lc = (u_short *)ZTWO_PADDR(copdisplay.init);
custom.copjmp1 = 0;
}
static void ami_reinit_copper(const struct amifb_par *par)
{
copdisplay.init[cip_bplcon0].w[1] = ~(BPC0_BPU3 | BPC0_BPU2 | BPC0_BPU1 | BPC0_BPU0) & par->bplcon0;
copdisplay.wait->l = CWAIT(32, par->diwstrt_v - 4);
}
/*
* Rebuild the Copper List
*
* We only change the things that are not static
*/
static void ami_rebuild_copper(const struct amifb_par *par)
{
copins *copl, *cops;
u_short line, h_end1, h_end2;
short i;
u_long p;
if (IS_AGA && maxfmode + par->clk_shift == 0)
h_end1 = par->diwstrt_h - 64;
else
h_end1 = par->htotal - 32;
h_end2 = par->ddfstop + 64;
ami_set_sprite(par);
copl = copdisplay.rebuild[1];
p = par->bplpt0;
if (par->vmode & FB_VMODE_YWRAP) {
if ((par->vyres - par->yoffset) != 1 || !mod2(par->diwstrt_v)) {
if (par->yoffset > par->vyres - par->yres) {
for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) {
(copl++)->l = CMOVE(highw(p), bplpt[i]);
(copl++)->l = CMOVE2(loww(p), bplpt[i]);
}
line = par->diwstrt_v + ((par->vyres - par->yoffset) << par->line_shift) - 1;
while (line >= 512) {
(copl++)->l = CWAIT(h_end1, 510);
line -= 512;
}
if (line >= 510 && IS_AGA && maxfmode + par->clk_shift == 0)
(copl++)->l = CWAIT(h_end1, line);
else
(copl++)->l = CWAIT(h_end2, line);
p = par->bplpt0wrap;
}
} else
p = par->bplpt0wrap;
}
for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) {
(copl++)->l = CMOVE(highw(p), bplpt[i]);
(copl++)->l = CMOVE2(loww(p), bplpt[i]);
}
copl->l = CEND;
if (par->bplcon0 & BPC0_LACE) {
cops = copdisplay.rebuild[0];
p = par->bplpt0;
if (mod2(par->diwstrt_v))
p -= par->next_line;
else
p += par->next_line;
if (par->vmode & FB_VMODE_YWRAP) {
if ((par->vyres - par->yoffset) != 1 || mod2(par->diwstrt_v)) {
if (par->yoffset > par->vyres - par->yres + 1) {
for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) {
(cops++)->l = CMOVE(highw(p), bplpt[i]);
(cops++)->l = CMOVE2(loww(p), bplpt[i]);
}
line = par->diwstrt_v + ((par->vyres - par->yoffset) << par->line_shift) - 2;
while (line >= 512) {
(cops++)->l = CWAIT(h_end1, 510);
line -= 512;
}
if (line > 510 && IS_AGA && maxfmode + par->clk_shift == 0)
(cops++)->l = CWAIT(h_end1, line);
else
(cops++)->l = CWAIT(h_end2, line);
p = par->bplpt0wrap;
if (mod2(par->diwstrt_v + par->vyres -
par->yoffset))
p -= par->next_line;
else
p += par->next_line;
}
} else
p = par->bplpt0wrap - par->next_line;
}
for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) {
(cops++)->l = CMOVE(highw(p), bplpt[i]);
(cops++)->l = CMOVE2(loww(p), bplpt[i]);
}
cops->l = CEND;
}
}
/*
* Build the Copper List
*/
static void ami_build_copper(struct fb_info *info)
{
struct amifb_par *par = info->par;
copins *copl, *cops;
u_long p;
currentcop = 1 - currentcop;
copl = copdisplay.list[currentcop][1];
(copl++)->l = CWAIT(0, 10);
(copl++)->l = CMOVE(par->bplcon0, bplcon0);
(copl++)->l = CMOVE(0, sprpt[0]);
(copl++)->l = CMOVE2(0, sprpt[0]);
if (par->bplcon0 & BPC0_LACE) {
cops = copdisplay.list[currentcop][0];
(cops++)->l = CWAIT(0, 10);
(cops++)->l = CMOVE(par->bplcon0, bplcon0);
(cops++)->l = CMOVE(0, sprpt[0]);
(cops++)->l = CMOVE2(0, sprpt[0]);
(copl++)->l = CMOVE(diwstrt2hw(par->diwstrt_h, par->diwstrt_v + 1), diwstrt);
(copl++)->l = CMOVE(diwstop2hw(par->diwstop_h, par->diwstop_v + 1), diwstop);
(cops++)->l = CMOVE(diwstrt2hw(par->diwstrt_h, par->diwstrt_v), diwstrt);
(cops++)->l = CMOVE(diwstop2hw(par->diwstop_h, par->diwstop_v), diwstop);
if (!IS_OCS) {
(copl++)->l = CMOVE(diwhigh2hw(par->diwstrt_h, par->diwstrt_v + 1,
par->diwstop_h, par->diwstop_v + 1), diwhigh);
(cops++)->l = CMOVE(diwhigh2hw(par->diwstrt_h, par->diwstrt_v,
par->diwstop_h, par->diwstop_v), diwhigh);
#if 0
if (par->beamcon0 & BMC0_VARBEAMEN) {
(copl++)->l = CMOVE(vtotal2hw(par->vtotal), vtotal);
(copl++)->l = CMOVE(vbstrt2hw(par->vbstrt + 1), vbstrt);
(copl++)->l = CMOVE(vbstop2hw(par->vbstop + 1), vbstop);
(cops++)->l = CMOVE(vtotal2hw(par->vtotal), vtotal);
(cops++)->l = CMOVE(vbstrt2hw(par->vbstrt), vbstrt);
(cops++)->l = CMOVE(vbstop2hw(par->vbstop), vbstop);
}
#endif
}
p = ZTWO_PADDR(copdisplay.list[currentcop][0]);
(copl++)->l = CMOVE(highw(p), cop2lc);
(copl++)->l = CMOVE2(loww(p), cop2lc);
p = ZTWO_PADDR(copdisplay.list[currentcop][1]);
(cops++)->l = CMOVE(highw(p), cop2lc);
(cops++)->l = CMOVE2(loww(p), cop2lc);
copdisplay.rebuild[0] = cops;
} else {
(copl++)->l = CMOVE(diwstrt2hw(par->diwstrt_h, par->diwstrt_v), diwstrt);
(copl++)->l = CMOVE(diwstop2hw(par->diwstop_h, par->diwstop_v), diwstop);
if (!IS_OCS) {
(copl++)->l = CMOVE(diwhigh2hw(par->diwstrt_h, par->diwstrt_v,
par->diwstop_h, par->diwstop_v), diwhigh);
#if 0
if (par->beamcon0 & BMC0_VARBEAMEN) {
(copl++)->l = CMOVE(vtotal2hw(par->vtotal), vtotal);
(copl++)->l = CMOVE(vbstrt2hw(par->vbstrt), vbstrt);
(copl++)->l = CMOVE(vbstop2hw(par->vbstop), vbstop);
}
#endif
}
}
copdisplay.rebuild[1] = copl;
ami_update_par(info);
ami_rebuild_copper(info->par);
}
#ifndef MODULE
static void __init amifb_setup_mcap(char *spec)
{
char *p;
int vmin, vmax, hmin, hmax;
/* Format for monitor capabilities is: <Vmin>;<Vmax>;<Hmin>;<Hmax>
* <V*> vertical freq. in Hz
* <H*> horizontal freq. in kHz
*/
if (!(p = strsep(&spec, ";")) || !*p)
return;
vmin = simple_strtoul(p, NULL, 10);
if (vmin <= 0)
return;
if (!(p = strsep(&spec, ";")) || !*p)
return;
vmax = simple_strtoul(p, NULL, 10);
if (vmax <= 0 || vmax <= vmin)
return;
if (!(p = strsep(&spec, ";")) || !*p)
return;
hmin = 1000 * simple_strtoul(p, NULL, 10);
if (hmin <= 0)
return;
if (!(p = strsep(&spec, "")) || !*p)
return;
hmax = 1000 * simple_strtoul(p, NULL, 10);
if (hmax <= 0 || hmax <= hmin)
return;
amifb_hfmin = hmin;
amifb_hfmax = hmax;
amifb_vfmin = vmin;
amifb_vfmax = vmax;
}
static int __init amifb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strcmp(this_opt, "inverse")) {
fb_invert_cmaps();
} else if (!strcmp(this_opt, "ilbm"))
amifb_ilbm = 1;
else if (!strncmp(this_opt, "monitorcap:", 11))
amifb_setup_mcap(this_opt + 11);
else if (!strncmp(this_opt, "fstart:", 7))
min_fstrt = simple_strtoul(this_opt + 7, NULL, 0);
else
mode_option = this_opt;
}
if (min_fstrt < 48)
min_fstrt = 48;
return 0;
}
#endif
static int amifb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int err;
struct amifb_par par;
/* Validate wanted screen parameters */
err = ami_decode_var(var, &par, info);
if (err)
return err;
/* Encode (possibly rounded) screen parameters */
ami_encode_var(var, &par);
return 0;
}
static int amifb_set_par(struct fb_info *info)
{
struct amifb_par *par = info->par;
int error;
do_vmode_pan = 0;
do_vmode_full = 0;
/* Decode wanted screen parameters */
error = ami_decode_var(&info->var, par, info);
if (error)
return error;
/* Set new videomode */
ami_build_copper(info);
/* Set VBlank trigger */
do_vmode_full = 1;
/* Update fix for new screen parameters */
if (par->bpp == 1) {
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
} else if (amifb_ilbm) {
info->fix.type = FB_TYPE_INTERLEAVED_PLANES;
info->fix.type_aux = par->next_line;
} else {
info->fix.type = FB_TYPE_PLANES;
info->fix.type_aux = 0;
}
info->fix.line_length = div8(upx(16 << maxfmode, par->vxres));
if (par->vmode & FB_VMODE_YWRAP) {
info->fix.ywrapstep = 1;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->flags = FBINFO_HWACCEL_YWRAP |
FBINFO_READS_FAST; /* override SCROLL_REDRAW */
} else {
info->fix.ywrapstep = 0;
if (par->vmode & FB_VMODE_SMOOTH_XPAN)
info->fix.xpanstep = 1;
else
info->fix.xpanstep = 16 << maxfmode;
info->fix.ypanstep = 1;
info->flags = FBINFO_HWACCEL_YPAN;
}
return 0;
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int amifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
const struct amifb_par *par = info->par;
if (IS_AGA) {
if (regno > 255)
return 1;
} else if (par->bplcon0 & BPC0_SHRES) {
if (regno > 3)
return 1;
} else {
if (regno > 31)
return 1;
}
red >>= 8;
green >>= 8;
blue >>= 8;
if (!regno) {
red0 = red;
green0 = green;
blue0 = blue;
}
/*
* Update the corresponding Hardware Color Register, unless it's Color
* Register 0 and the screen is blanked.
*
* VBlank is switched off to protect bplcon3 or ecs_palette[] from
* being changed by ami_do_blank() during the VBlank.
*/
if (regno || !is_blanked) {
#if defined(CONFIG_FB_AMIGA_AGA)
if (IS_AGA) {
u_short bplcon3 = par->bplcon3;
VBlankOff();
custom.bplcon3 = bplcon3 | (regno << 8 & 0xe000);
custom.color[regno & 31] = rgb2hw8_high(red, green,
blue);
custom.bplcon3 = bplcon3 | (regno << 8 & 0xe000) |
BPC3_LOCT;
custom.color[regno & 31] = rgb2hw8_low(red, green,
blue);
custom.bplcon3 = bplcon3;
VBlankOn();
} else
#endif
#if defined(CONFIG_FB_AMIGA_ECS)
if (par->bplcon0 & BPC0_SHRES) {
u_short color, mask;
int i;
mask = 0x3333;
color = rgb2hw2(red, green, blue);
VBlankOff();
for (i = regno + 12; i >= (int)regno; i -= 4)
custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color;
mask <<= 2; color >>= 2;
regno = down16(regno) + mul4(mod4(regno));
for (i = regno + 3; i >= (int)regno; i--)
custom.color[i] = ecs_palette[i] = (ecs_palette[i] & mask) | color;
VBlankOn();
} else
#endif
custom.color[regno] = rgb2hw4(red, green, blue);
}
return 0;
}
/*
* Blank the display.
*/
static int amifb_blank(int blank, struct fb_info *info)
{
do_blank = blank ? blank : -1;
return 0;
}
/*
* Pan or Wrap the Display
*
* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
*/
static int amifb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if (!(var->vmode & FB_VMODE_YWRAP)) {
/*
* TODO: There will be problems when xpan!=1, so some columns
* on the right side will never be seen
*/
if (var->xoffset + info->var.xres >
upx(16 << maxfmode, info->var.xres_virtual))
return -EINVAL;
}
ami_pan_var(var, info);
return 0;
}
#if BITS_PER_LONG == 32
#define BYTES_PER_LONG 4
#define SHIFT_PER_LONG 5
#elif BITS_PER_LONG == 64
#define BYTES_PER_LONG 8
#define SHIFT_PER_LONG 6
#else
#define Please update me
#endif
/*
* Compose two values, using a bitmask as decision value
* This is equivalent to (a & mask) | (b & ~mask)
*/
static inline unsigned long comp(unsigned long a, unsigned long b,
unsigned long mask)
{
return ((a ^ b) & mask) ^ b;
}
static inline unsigned long xor(unsigned long a, unsigned long b,
unsigned long mask)
{
return (a & mask) ^ b;
}
/*
* Unaligned forward bit copy using 32-bit or 64-bit memory accesses
*/
static void bitcpy(unsigned long *dst, int dst_idx, const unsigned long *src,
int src_idx, u32 n)
{
unsigned long first, last;
int shift = dst_idx - src_idx, left, right;
unsigned long d0, d1;
int m;
if (!n)
return;
shift = dst_idx - src_idx;
first = ~0UL >> dst_idx;
last = ~(~0UL >> ((dst_idx + n) % BITS_PER_LONG));
if (!shift) {
// Same alignment for source and dest
if (dst_idx + n <= BITS_PER_LONG) {
// Single word
if (last)
first &= last;
*dst = comp(*src, *dst, first);
} else {
// Multiple destination words
// Leading bits
if (first) {
*dst = comp(*src, *dst, first);
dst++;
src++;
n -= BITS_PER_LONG - dst_idx;
}
// Main chunk
n /= BITS_PER_LONG;
while (n >= 8) {
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
n -= 8;
}
while (n--)
*dst++ = *src++;
// Trailing bits
if (last)
*dst = comp(*src, *dst, last);
}
} else {
// Different alignment for source and dest
right = shift & (BITS_PER_LONG - 1);
left = -shift & (BITS_PER_LONG - 1);
if (dst_idx + n <= BITS_PER_LONG) {
// Single destination word
if (last)
first &= last;
if (shift > 0) {
// Single source word
*dst = comp(*src >> right, *dst, first);
} else if (src_idx + n <= BITS_PER_LONG) {
// Single source word
*dst = comp(*src << left, *dst, first);
} else {
// 2 source words
d0 = *src++;
d1 = *src;
*dst = comp(d0 << left | d1 >> right, *dst,
first);
}
} else {
// Multiple destination words
d0 = *src++;
// Leading bits
if (shift > 0) {
// Single source word
*dst = comp(d0 >> right, *dst, first);
dst++;
n -= BITS_PER_LONG - dst_idx;
} else {
// 2 source words
d1 = *src++;
*dst = comp(d0 << left | d1 >> right, *dst,
first);
d0 = d1;
dst++;
n -= BITS_PER_LONG - dst_idx;
}
// Main chunk
m = n % BITS_PER_LONG;
n /= BITS_PER_LONG;
while (n >= 4) {
d1 = *src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
d1 = *src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
d1 = *src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
d1 = *src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
n -= 4;
}
while (n--) {
d1 = *src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
}
// Trailing bits
if (last) {
if (m <= right) {
// Single source word
*dst = comp(d0 << left, *dst, last);
} else {
// 2 source words
d1 = *src;
*dst = comp(d0 << left | d1 >> right,
*dst, last);
}
}
}
}
}
/*
* Unaligned reverse bit copy using 32-bit or 64-bit memory accesses
*/
static void bitcpy_rev(unsigned long *dst, int dst_idx,
const unsigned long *src, int src_idx, u32 n)
{
unsigned long first, last;
int shift = dst_idx - src_idx, left, right;
unsigned long d0, d1;
int m;
if (!n)
return;
dst += (n - 1) / BITS_PER_LONG;
src += (n - 1) / BITS_PER_LONG;
if ((n - 1) % BITS_PER_LONG) {
dst_idx += (n - 1) % BITS_PER_LONG;
dst += dst_idx >> SHIFT_PER_LONG;
dst_idx &= BITS_PER_LONG - 1;
src_idx += (n - 1) % BITS_PER_LONG;
src += src_idx >> SHIFT_PER_LONG;
src_idx &= BITS_PER_LONG - 1;
}
shift = dst_idx - src_idx;
first = ~0UL << (BITS_PER_LONG - 1 - dst_idx);
last = ~(~0UL << (BITS_PER_LONG - 1 - ((dst_idx - n) % BITS_PER_LONG)));
if (!shift) {
// Same alignment for source and dest
if ((unsigned long)dst_idx + 1 >= n) {
// Single word
if (last)
first &= last;
*dst = comp(*src, *dst, first);
} else {
// Multiple destination words
// Leading bits
if (first) {
*dst = comp(*src, *dst, first);
dst--;
src--;
n -= dst_idx + 1;
}
// Main chunk
n /= BITS_PER_LONG;
while (n >= 8) {
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
n -= 8;
}
while (n--)
*dst-- = *src--;
// Trailing bits
if (last)
*dst = comp(*src, *dst, last);
}
} else {
// Different alignment for source and dest
right = shift & (BITS_PER_LONG - 1);
left = -shift & (BITS_PER_LONG - 1);
if ((unsigned long)dst_idx + 1 >= n) {
// Single destination word
if (last)
first &= last;
if (shift < 0) {
// Single source word
*dst = comp(*src << left, *dst, first);
} else if (1 + (unsigned long)src_idx >= n) {
// Single source word
*dst = comp(*src >> right, *dst, first);
} else {
// 2 source words
d0 = *src--;
d1 = *src;
*dst = comp(d0 >> right | d1 << left, *dst,
first);
}
} else {
// Multiple destination words
d0 = *src--;
// Leading bits
if (shift < 0) {
// Single source word
*dst = comp(d0 << left, *dst, first);
dst--;
n -= dst_idx + 1;
} else {
// 2 source words
d1 = *src--;
*dst = comp(d0 >> right | d1 << left, *dst,
first);
d0 = d1;
dst--;
n -= dst_idx + 1;
}
// Main chunk
m = n % BITS_PER_LONG;
n /= BITS_PER_LONG;
while (n >= 4) {
d1 = *src--;
*dst-- = d0 >> right | d1 << left;
d0 = d1;
d1 = *src--;
*dst-- = d0 >> right | d1 << left;
d0 = d1;
d1 = *src--;
*dst-- = d0 >> right | d1 << left;
d0 = d1;
d1 = *src--;
*dst-- = d0 >> right | d1 << left;
d0 = d1;
n -= 4;
}
while (n--) {
d1 = *src--;
*dst-- = d0 >> right | d1 << left;
d0 = d1;
}
// Trailing bits
if (last) {
if (m <= left) {
// Single source word
*dst = comp(d0 >> right, *dst, last);
} else {
// 2 source words
d1 = *src;
*dst = comp(d0 >> right | d1 << left,
*dst, last);
}
}
}
}
}
/*
* Unaligned forward inverting bit copy using 32-bit or 64-bit memory
* accesses
*/
static void bitcpy_not(unsigned long *dst, int dst_idx,
const unsigned long *src, int src_idx, u32 n)
{
unsigned long first, last;
int shift = dst_idx - src_idx, left, right;
unsigned long d0, d1;
int m;
if (!n)
return;
shift = dst_idx - src_idx;
first = ~0UL >> dst_idx;
last = ~(~0UL >> ((dst_idx + n) % BITS_PER_LONG));
if (!shift) {
// Same alignment for source and dest
if (dst_idx + n <= BITS_PER_LONG) {
// Single word
if (last)
first &= last;
*dst = comp(~*src, *dst, first);
} else {
// Multiple destination words
// Leading bits
if (first) {
*dst = comp(~*src, *dst, first);
dst++;
src++;
n -= BITS_PER_LONG - dst_idx;
}
// Main chunk
n /= BITS_PER_LONG;
while (n >= 8) {
*dst++ = ~*src++;
*dst++ = ~*src++;
*dst++ = ~*src++;
*dst++ = ~*src++;
*dst++ = ~*src++;
*dst++ = ~*src++;
*dst++ = ~*src++;
*dst++ = ~*src++;
n -= 8;
}
while (n--)
*dst++ = ~*src++;
// Trailing bits
if (last)
*dst = comp(~*src, *dst, last);
}
} else {
// Different alignment for source and dest
right = shift & (BITS_PER_LONG - 1);
left = -shift & (BITS_PER_LONG - 1);
if (dst_idx + n <= BITS_PER_LONG) {
// Single destination word
if (last)
first &= last;
if (shift > 0) {
// Single source word
*dst = comp(~*src >> right, *dst, first);
} else if (src_idx + n <= BITS_PER_LONG) {
// Single source word
*dst = comp(~*src << left, *dst, first);
} else {
// 2 source words
d0 = ~*src++;
d1 = ~*src;
*dst = comp(d0 << left | d1 >> right, *dst,
first);
}
} else {
// Multiple destination words
d0 = ~*src++;
// Leading bits
if (shift > 0) {
// Single source word
*dst = comp(d0 >> right, *dst, first);
dst++;
n -= BITS_PER_LONG - dst_idx;
} else {
// 2 source words
d1 = ~*src++;
*dst = comp(d0 << left | d1 >> right, *dst,
first);
d0 = d1;
dst++;
n -= BITS_PER_LONG - dst_idx;
}
// Main chunk
m = n % BITS_PER_LONG;
n /= BITS_PER_LONG;
while (n >= 4) {
d1 = ~*src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
d1 = ~*src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
d1 = ~*src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
d1 = ~*src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
n -= 4;
}
while (n--) {
d1 = ~*src++;
*dst++ = d0 << left | d1 >> right;
d0 = d1;
}
// Trailing bits
if (last) {
if (m <= right) {
// Single source word
*dst = comp(d0 << left, *dst, last);
} else {
// 2 source words
d1 = ~*src;
*dst = comp(d0 << left | d1 >> right,
*dst, last);
}
}
}
}
}
/*
* Unaligned 32-bit pattern fill using 32/64-bit memory accesses
*/
static void bitfill32(unsigned long *dst, int dst_idx, u32 pat, u32 n)
{
unsigned long val = pat;
unsigned long first, last;
if (!n)
return;
#if BITS_PER_LONG == 64
val |= val << 32;
#endif
first = ~0UL >> dst_idx;
last = ~(~0UL >> ((dst_idx + n) % BITS_PER_LONG));
if (dst_idx + n <= BITS_PER_LONG) {
// Single word
if (last)
first &= last;
*dst = comp(val, *dst, first);
} else {
// Multiple destination words
// Leading bits
if (first) {
*dst = comp(val, *dst, first);
dst++;
n -= BITS_PER_LONG - dst_idx;
}
// Main chunk
n /= BITS_PER_LONG;
while (n >= 8) {
*dst++ = val;
*dst++ = val;
*dst++ = val;
*dst++ = val;
*dst++ = val;
*dst++ = val;
*dst++ = val;
*dst++ = val;
n -= 8;
}
while (n--)
*dst++ = val;
// Trailing bits
if (last)
*dst = comp(val, *dst, last);
}
}
/*
* Unaligned 32-bit pattern xor using 32/64-bit memory accesses
*/
static void bitxor32(unsigned long *dst, int dst_idx, u32 pat, u32 n)
{
unsigned long val = pat;
unsigned long first, last;
if (!n)
return;
#if BITS_PER_LONG == 64
val |= val << 32;
#endif
first = ~0UL >> dst_idx;
last = ~(~0UL >> ((dst_idx + n) % BITS_PER_LONG));
if (dst_idx + n <= BITS_PER_LONG) {
// Single word
if (last)
first &= last;
*dst = xor(val, *dst, first);
} else {
// Multiple destination words
// Leading bits
if (first) {
*dst = xor(val, *dst, first);
dst++;
n -= BITS_PER_LONG - dst_idx;
}
// Main chunk
n /= BITS_PER_LONG;
while (n >= 4) {
*dst++ ^= val;
*dst++ ^= val;
*dst++ ^= val;
*dst++ ^= val;
n -= 4;
}
while (n--)
*dst++ ^= val;
// Trailing bits
if (last)
*dst = xor(val, *dst, last);
}
}
static inline void fill_one_line(int bpp, unsigned long next_plane,
unsigned long *dst, int dst_idx, u32 n,
u32 color)
{
while (1) {
dst += dst_idx >> SHIFT_PER_LONG;
dst_idx &= (BITS_PER_LONG - 1);
bitfill32(dst, dst_idx, color & 1 ? ~0 : 0, n);
if (!--bpp)
break;
color >>= 1;
dst_idx += next_plane * 8;
}
}
static inline void xor_one_line(int bpp, unsigned long next_plane,
unsigned long *dst, int dst_idx, u32 n,
u32 color)
{
while (color) {
dst += dst_idx >> SHIFT_PER_LONG;
dst_idx &= (BITS_PER_LONG - 1);
bitxor32(dst, dst_idx, color & 1 ? ~0 : 0, n);
if (!--bpp)
break;
color >>= 1;
dst_idx += next_plane * 8;
}
}
static void amifb_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
struct amifb_par *par = info->par;
int dst_idx, x2, y2;
unsigned long *dst;
u32 width, height;
if (!rect->width || !rect->height)
return;
/*
* We could use hardware clipping but on many cards you get around
* hardware clipping by writing to framebuffer directly.
* */
x2 = rect->dx + rect->width;
y2 = rect->dy + rect->height;
x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
width = x2 - rect->dx;
height = y2 - rect->dy;
dst = (unsigned long *)
((unsigned long)info->screen_base & ~(BYTES_PER_LONG - 1));
dst_idx = ((unsigned long)info->screen_base & (BYTES_PER_LONG - 1)) * 8;
dst_idx += rect->dy * par->next_line * 8 + rect->dx;
while (height--) {
switch (rect->rop) {
case ROP_COPY:
fill_one_line(info->var.bits_per_pixel,
par->next_plane, dst, dst_idx, width,
rect->color);
break;
case ROP_XOR:
xor_one_line(info->var.bits_per_pixel, par->next_plane,
dst, dst_idx, width, rect->color);
break;
}
dst_idx += par->next_line * 8;
}
}
static inline void copy_one_line(int bpp, unsigned long next_plane,
unsigned long *dst, int dst_idx,
unsigned long *src, int src_idx, u32 n)
{
while (1) {
dst += dst_idx >> SHIFT_PER_LONG;
dst_idx &= (BITS_PER_LONG - 1);
src += src_idx >> SHIFT_PER_LONG;
src_idx &= (BITS_PER_LONG - 1);
bitcpy(dst, dst_idx, src, src_idx, n);
if (!--bpp)
break;
dst_idx += next_plane * 8;
src_idx += next_plane * 8;
}
}
static inline void copy_one_line_rev(int bpp, unsigned long next_plane,
unsigned long *dst, int dst_idx,
unsigned long *src, int src_idx, u32 n)
{
while (1) {
dst += dst_idx >> SHIFT_PER_LONG;
dst_idx &= (BITS_PER_LONG - 1);
src += src_idx >> SHIFT_PER_LONG;
src_idx &= (BITS_PER_LONG - 1);
bitcpy_rev(dst, dst_idx, src, src_idx, n);
if (!--bpp)
break;
dst_idx += next_plane * 8;
src_idx += next_plane * 8;
}
}
static void amifb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct amifb_par *par = info->par;
int x2, y2;
u32 dx, dy, sx, sy, width, height;
unsigned long *dst, *src;
int dst_idx, src_idx;
int rev_copy = 0;
/* clip the destination */
x2 = area->dx + area->width;
y2 = area->dy + area->height;
dx = area->dx > 0 ? area->dx : 0;
dy = area->dy > 0 ? area->dy : 0;
x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
width = x2 - dx;
height = y2 - dy;
if (area->sx + dx < area->dx || area->sy + dy < area->dy)
return;
/* update sx,sy */
sx = area->sx + (dx - area->dx);
sy = area->sy + (dy - area->dy);
/* the source must be completely inside the virtual screen */
if (sx + width > info->var.xres_virtual ||
sy + height > info->var.yres_virtual)
return;
if (dy > sy || (dy == sy && dx > sx)) {
dy += height;
sy += height;
rev_copy = 1;
}
dst = (unsigned long *)
((unsigned long)info->screen_base & ~(BYTES_PER_LONG - 1));
src = dst;
dst_idx = ((unsigned long)info->screen_base & (BYTES_PER_LONG - 1)) * 8;
src_idx = dst_idx;
dst_idx += dy * par->next_line * 8 + dx;
src_idx += sy * par->next_line * 8 + sx;
if (rev_copy) {
while (height--) {
dst_idx -= par->next_line * 8;
src_idx -= par->next_line * 8;
copy_one_line_rev(info->var.bits_per_pixel,
par->next_plane, dst, dst_idx, src,
src_idx, width);
}
} else {
while (height--) {
copy_one_line(info->var.bits_per_pixel,
par->next_plane, dst, dst_idx, src,
src_idx, width);
dst_idx += par->next_line * 8;
src_idx += par->next_line * 8;
}
}
}
static inline void expand_one_line(int bpp, unsigned long next_plane,
unsigned long *dst, int dst_idx, u32 n,
const u8 *data, u32 bgcolor, u32 fgcolor)
{
const unsigned long *src;
int src_idx;
while (1) {
dst += dst_idx >> SHIFT_PER_LONG;
dst_idx &= (BITS_PER_LONG - 1);
if ((bgcolor ^ fgcolor) & 1) {
src = (unsigned long *)
((unsigned long)data & ~(BYTES_PER_LONG - 1));
src_idx = ((unsigned long)data & (BYTES_PER_LONG - 1)) * 8;
if (fgcolor & 1)
bitcpy(dst, dst_idx, src, src_idx, n);
else
bitcpy_not(dst, dst_idx, src, src_idx, n);
/* set or clear */
} else
bitfill32(dst, dst_idx, fgcolor & 1 ? ~0 : 0, n);
if (!--bpp)
break;
bgcolor >>= 1;
fgcolor >>= 1;
dst_idx += next_plane * 8;
}
}
static void amifb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct amifb_par *par = info->par;
int x2, y2;
unsigned long *dst;
int dst_idx;
const char *src;
u32 dx, dy, width, height, pitch;
/*
* We could use hardware clipping but on many cards you get around
* hardware clipping by writing to framebuffer directly like we are
* doing here.
*/
x2 = image->dx + image->width;
y2 = image->dy + image->height;
dx = image->dx;
dy = image->dy;
x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
width = x2 - dx;
height = y2 - dy;
if (image->depth == 1) {
dst = (unsigned long *)
((unsigned long)info->screen_base & ~(BYTES_PER_LONG - 1));
dst_idx = ((unsigned long)info->screen_base & (BYTES_PER_LONG - 1)) * 8;
dst_idx += dy * par->next_line * 8 + dx;
src = image->data;
pitch = (image->width + 7) / 8;
while (height--) {
expand_one_line(info->var.bits_per_pixel,
par->next_plane, dst, dst_idx, width,
src, image->bg_color,
image->fg_color);
dst_idx += par->next_line * 8;
src += pitch;
}
} else {
c2p_planar(info->screen_base, image->data, dx, dy, width,
height, par->next_line, par->next_plane,
image->width, info->var.bits_per_pixel);
}
}
/*
* Amiga Frame Buffer Specific ioctls
*/
static int amifb_ioctl(struct fb_info *info,
unsigned int cmd, unsigned long arg)
{
union {
struct fb_fix_cursorinfo fix;
struct fb_var_cursorinfo var;
struct fb_cursorstate state;
} crsr;
void __user *argp = (void __user *)arg;
int i;
switch (cmd) {
case FBIOGET_FCURSORINFO:
i = ami_get_fix_cursorinfo(&crsr.fix, info->par);
if (i)
return i;
return copy_to_user(argp, &crsr.fix,
sizeof(crsr.fix)) ? -EFAULT : 0;
case FBIOGET_VCURSORINFO:
i = ami_get_var_cursorinfo(&crsr.var,
((struct fb_var_cursorinfo __user *)arg)->data,
info->par);
if (i)
return i;
return copy_to_user(argp, &crsr.var,
sizeof(crsr.var)) ? -EFAULT : 0;
case FBIOPUT_VCURSORINFO:
if (copy_from_user(&crsr.var, argp, sizeof(crsr.var)))
return -EFAULT;
return ami_set_var_cursorinfo(&crsr.var,
((struct fb_var_cursorinfo __user *)arg)->data,
info->par);
case FBIOGET_CURSORSTATE:
i = ami_get_cursorstate(&crsr.state, info->par);
if (i)
return i;
return copy_to_user(argp, &crsr.state,
sizeof(crsr.state)) ? -EFAULT : 0;
case FBIOPUT_CURSORSTATE:
if (copy_from_user(&crsr.state, argp, sizeof(crsr.state)))
return -EFAULT;
return ami_set_cursorstate(&crsr.state, info->par);
}
return -EINVAL;
}
/*
* Flash the cursor (called by VBlank interrupt)
*/
static int flash_cursor(void)
{
static int cursorcount = 1;
if (cursormode == FB_CURSOR_FLASH) {
if (!--cursorcount) {
cursorstate = -cursorstate;
cursorcount = cursorrate;
if (!is_blanked)
return 1;
}
}
return 0;
}
/*
* VBlank Display Interrupt
*/
static irqreturn_t amifb_interrupt(int irq, void *dev_id)
{
struct amifb_par *par = dev_id;
if (do_vmode_pan || do_vmode_full)
ami_update_display(par);
if (do_vmode_full)
ami_init_display(par);
if (do_vmode_pan) {
flash_cursor();
ami_rebuild_copper(par);
do_cursor = do_vmode_pan = 0;
} else if (do_cursor) {
flash_cursor();
ami_set_sprite(par);
do_cursor = 0;
} else {
if (flash_cursor())
ami_set_sprite(par);
}
if (do_blank) {
ami_do_blank(par);
do_blank = 0;
}
if (do_vmode_full) {
ami_reinit_copper(par);
do_vmode_full = 0;
}
return IRQ_HANDLED;
}
static const struct fb_ops amifb_ops = {
.owner = THIS_MODULE,
.fb_check_var = amifb_check_var,
.fb_set_par = amifb_set_par,
.fb_setcolreg = amifb_setcolreg,
.fb_blank = amifb_blank,
.fb_pan_display = amifb_pan_display,
.fb_fillrect = amifb_fillrect,
.fb_copyarea = amifb_copyarea,
.fb_imageblit = amifb_imageblit,
.fb_ioctl = amifb_ioctl,
};
/*
* Allocate, Clear and Align a Block of Chip Memory
*/
static void *aligned_chipptr;
static inline u_long __init chipalloc(u_long size)
{
aligned_chipptr = amiga_chip_alloc(size, "amifb [RAM]");
if (!aligned_chipptr) {
pr_err("amifb: No Chip RAM for frame buffer");
return 0;
}
memset(aligned_chipptr, 0, size);
return (u_long)aligned_chipptr;
}
static inline void chipfree(void)
{
if (aligned_chipptr)
amiga_chip_free(aligned_chipptr);
}
/*
* Initialisation
*/
static int __init amifb_probe(struct platform_device *pdev)
{
struct fb_info *info;
int tag, i, err = 0;
u_long chipptr;
u_int defmode;
#ifndef MODULE
char *option = NULL;
if (fb_get_options("amifb", &option)) {
amifb_video_off();
return -ENODEV;
}
amifb_setup(option);
#endif
custom.dmacon = DMAF_ALL | DMAF_MASTER;
info = framebuffer_alloc(sizeof(struct amifb_par), &pdev->dev);
if (!info)
return -ENOMEM;
strcpy(info->fix.id, "Amiga ");
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.accel = FB_ACCEL_AMIGABLITT;
switch (amiga_chipset) {
#ifdef CONFIG_FB_AMIGA_OCS
case CS_OCS:
strcat(info->fix.id, "OCS");
default_chipset:
chipset = TAG_OCS;
maxdepth[TAG_SHRES] = 0; /* OCS means no SHRES */
maxdepth[TAG_HIRES] = 4;
maxdepth[TAG_LORES] = 6;
maxfmode = TAG_FMODE_1;
defmode = amiga_vblank == 50 ? DEFMODE_PAL : DEFMODE_NTSC;
info->fix.smem_len = VIDEOMEMSIZE_OCS;
break;
#endif /* CONFIG_FB_AMIGA_OCS */
#ifdef CONFIG_FB_AMIGA_ECS
case CS_ECS:
strcat(info->fix.id, "ECS");
chipset = TAG_ECS;
maxdepth[TAG_SHRES] = 2;
maxdepth[TAG_HIRES] = 4;
maxdepth[TAG_LORES] = 6;
maxfmode = TAG_FMODE_1;
if (AMIGAHW_PRESENT(AMBER_FF))
defmode = amiga_vblank == 50 ? DEFMODE_AMBER_PAL
: DEFMODE_AMBER_NTSC;
else
defmode = amiga_vblank == 50 ? DEFMODE_PAL
: DEFMODE_NTSC;
if (amiga_chip_avail() - CHIPRAM_SAFETY_LIMIT >
VIDEOMEMSIZE_ECS_2M)
info->fix.smem_len = VIDEOMEMSIZE_ECS_2M;
else
info->fix.smem_len = VIDEOMEMSIZE_ECS_1M;
break;
#endif /* CONFIG_FB_AMIGA_ECS */
#ifdef CONFIG_FB_AMIGA_AGA
case CS_AGA:
strcat(info->fix.id, "AGA");
chipset = TAG_AGA;
maxdepth[TAG_SHRES] = 8;
maxdepth[TAG_HIRES] = 8;
maxdepth[TAG_LORES] = 8;
maxfmode = TAG_FMODE_4;
defmode = DEFMODE_AGA;
if (amiga_chip_avail() - CHIPRAM_SAFETY_LIMIT >
VIDEOMEMSIZE_AGA_2M)
info->fix.smem_len = VIDEOMEMSIZE_AGA_2M;
else
info->fix.smem_len = VIDEOMEMSIZE_AGA_1M;
break;
#endif /* CONFIG_FB_AMIGA_AGA */
default:
#ifdef CONFIG_FB_AMIGA_OCS
printk("Unknown graphics chipset, defaulting to OCS\n");
strcat(info->fix.id, "Unknown");
goto default_chipset;
#else /* CONFIG_FB_AMIGA_OCS */
err = -ENODEV;
goto release;
#endif /* CONFIG_FB_AMIGA_OCS */
break;
}
/*
* Calculate the Pixel Clock Values for this Machine
*/
{
u_long tmp = DIVUL(200000000000ULL, amiga_eclock);
pixclock[TAG_SHRES] = (tmp + 4) / 8; /* SHRES: 35 ns / 28 MHz */
pixclock[TAG_HIRES] = (tmp + 2) / 4; /* HIRES: 70 ns / 14 MHz */
pixclock[TAG_LORES] = (tmp + 1) / 2; /* LORES: 140 ns / 7 MHz */
}
/*
* Replace the Tag Values with the Real Pixel Clock Values
*/
for (i = 0; i < NUM_TOTAL_MODES; i++) {
struct fb_videomode *mode = &ami_modedb[i];
tag = mode->pixclock;
if (tag == TAG_SHRES || tag == TAG_HIRES || tag == TAG_LORES) {
mode->pixclock = pixclock[tag];
}
}
if (amifb_hfmin) {
info->monspecs.hfmin = amifb_hfmin;
info->monspecs.hfmax = amifb_hfmax;
info->monspecs.vfmin = amifb_vfmin;
info->monspecs.vfmax = amifb_vfmax;
} else {
/*
* These are for a typical Amiga monitor (e.g. A1960)
*/
info->monspecs.hfmin = 15000;
info->monspecs.hfmax = 38000;
info->monspecs.vfmin = 49;
info->monspecs.vfmax = 90;
}
info->fbops = &amifb_ops;
info->device = &pdev->dev;
if (!fb_find_mode(&info->var, info, mode_option, ami_modedb,
NUM_TOTAL_MODES, &ami_modedb[defmode], 4)) {
err = -EINVAL;
goto release;
}
fb_videomode_to_modelist(ami_modedb, NUM_TOTAL_MODES,
&info->modelist);
round_down_bpp = 0;
chipptr = chipalloc(info->fix.smem_len + SPRITEMEMSIZE +
DUMMYSPRITEMEMSIZE + COPINITSIZE +
4 * COPLISTSIZE);
if (!chipptr) {
err = -ENOMEM;
goto release;
}
assignchunk(videomemory, u_long, chipptr, info->fix.smem_len);
assignchunk(spritememory, u_long, chipptr, SPRITEMEMSIZE);
assignchunk(dummysprite, u_short *, chipptr, DUMMYSPRITEMEMSIZE);
assignchunk(copdisplay.init, copins *, chipptr, COPINITSIZE);
assignchunk(copdisplay.list[0][0], copins *, chipptr, COPLISTSIZE);
assignchunk(copdisplay.list[0][1], copins *, chipptr, COPLISTSIZE);
assignchunk(copdisplay.list[1][0], copins *, chipptr, COPLISTSIZE);
assignchunk(copdisplay.list[1][1], copins *, chipptr, COPLISTSIZE);
/*
* access the videomem with writethrough cache
*/
info->fix.smem_start = (u_long)ZTWO_PADDR(videomemory);
videomemory = (u_long)ioremap_wt(info->fix.smem_start,
info->fix.smem_len);
if (!videomemory) {
dev_warn(&pdev->dev,
"Unable to map videomem cached writethrough\n");
info->screen_base = ZTWO_VADDR(info->fix.smem_start);
} else
info->screen_base = (char *)videomemory;
memset(dummysprite, 0, DUMMYSPRITEMEMSIZE);
/*
* Make sure the Copper has something to do
*/
ami_init_copper();
/*
* Enable Display DMA
*/
custom.dmacon = DMAF_SETCLR | DMAF_MASTER | DMAF_RASTER | DMAF_COPPER |
DMAF_BLITTER | DMAF_SPRITE;
err = request_irq(IRQ_AMIGA_COPPER, amifb_interrupt, 0,
"fb vertb handler", info->par);
if (err)
goto disable_dma;
err = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
if (err)
goto free_irq;
platform_set_drvdata(pdev, info);
err = register_framebuffer(info);
if (err)
goto unset_drvdata;
fb_info(info, "%s frame buffer device, using %dK of video memory\n",
info->fix.id, info->fix.smem_len>>10);
return 0;
unset_drvdata:
fb_dealloc_cmap(&info->cmap);
free_irq:
free_irq(IRQ_AMIGA_COPPER, info->par);
disable_dma:
custom.dmacon = DMAF_ALL | DMAF_MASTER;
if (videomemory)
iounmap((void *)videomemory);
chipfree();
release:
framebuffer_release(info);
return err;
}
static int __exit amifb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
free_irq(IRQ_AMIGA_COPPER, info->par);
custom.dmacon = DMAF_ALL | DMAF_MASTER;
if (videomemory)
iounmap((void *)videomemory);
chipfree();
framebuffer_release(info);
amifb_video_off();
return 0;
}
static struct platform_driver amifb_driver = {
.remove = __exit_p(amifb_remove),
.driver = {
.name = "amiga-video",
},
};
module_platform_driver_probe(amifb_driver, amifb_probe);
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:amiga-video");
| linux-master | drivers/video/fbdev/amifb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* WonderMedia WM8505 Frame Buffer device driver
*
* Copyright (C) 2010 Ed Spiridonov <[email protected]>
* Based on vt8500lcdfb.c
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/fb.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/memblock.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/wait.h>
#include <video/of_display_timing.h>
#include "wm8505fb_regs.h"
#include "wmt_ge_rops.h"
#define DRIVER_NAME "wm8505-fb"
#define to_wm8505fb_info(__info) container_of(__info, \
struct wm8505fb_info, fb)
struct wm8505fb_info {
struct fb_info fb;
void __iomem *regbase;
unsigned int contrast;
};
static int wm8505fb_init_hw(struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
int i;
/* I know the purpose only of few registers, so clear unknown */
for (i = 0; i < 0x200; i += 4)
writel(0, fbi->regbase + i);
/* Set frame buffer address */
writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
/*
* Set in-memory picture format to RGB
* 0x31C sets the correct color mode (RGB565) for WM8650
* Bit 8+9 (0x300) are ignored on WM8505 as reserved
*/
writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE);
writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1);
/* Virtual buffer size */
writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES);
writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL);
/* black magic ;) */
writel(0xf, fbi->regbase + WMT_GOVR_FHI);
writel(4, fbi->regbase + WMT_GOVR_DVO_SET);
writel(1, fbi->regbase + WMT_GOVR_MIF_ENABLE);
writel(1, fbi->regbase + WMT_GOVR_REG_UPDATE);
return 0;
}
static int wm8505fb_set_timing(struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
int h_start = info->var.left_margin;
int h_end = h_start + info->var.xres;
int h_all = h_end + info->var.right_margin;
int h_sync = info->var.hsync_len;
int v_start = info->var.upper_margin;
int v_end = v_start + info->var.yres;
int v_all = v_end + info->var.lower_margin;
int v_sync = info->var.vsync_len;
writel(0, fbi->regbase + WMT_GOVR_TG);
writel(h_start, fbi->regbase + WMT_GOVR_TIMING_H_START);
writel(h_end, fbi->regbase + WMT_GOVR_TIMING_H_END);
writel(h_all, fbi->regbase + WMT_GOVR_TIMING_H_ALL);
writel(h_sync, fbi->regbase + WMT_GOVR_TIMING_H_SYNC);
writel(v_start, fbi->regbase + WMT_GOVR_TIMING_V_START);
writel(v_end, fbi->regbase + WMT_GOVR_TIMING_V_END);
writel(v_all, fbi->regbase + WMT_GOVR_TIMING_V_ALL);
writel(v_sync, fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
writel(1, fbi->regbase + WMT_GOVR_TG);
return 0;
}
static int wm8505fb_set_par(struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
if (!fbi)
return -EINVAL;
if (info->var.bits_per_pixel == 32) {
info->var.red.offset = 16;
info->var.red.length = 8;
info->var.red.msb_right = 0;
info->var.green.offset = 8;
info->var.green.length = 8;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->var.blue.msb_right = 0;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = info->var.xres_virtual << 2;
} else if (info->var.bits_per_pixel == 16) {
info->var.red.offset = 11;
info->var.red.length = 5;
info->var.red.msb_right = 0;
info->var.green.offset = 5;
info->var.green.length = 6;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = 5;
info->var.blue.msb_right = 0;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = info->var.xres_virtual << 1;
}
wm8505fb_set_timing(info);
writel(fbi->contrast<<16 | fbi->contrast<<8 | fbi->contrast,
fbi->regbase + WMT_GOVR_CONTRAST);
return 0;
}
static ssize_t contrast_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
return sprintf(buf, "%u\n", fbi->contrast);
}
static ssize_t contrast_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(dev);
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
unsigned long tmp;
if (kstrtoul(buf, 10, &tmp) || (tmp > 0xff))
return -EINVAL;
fbi->contrast = tmp;
wm8505fb_set_par(info);
return count;
}
static DEVICE_ATTR_RW(contrast);
static struct attribute *wm8505fb_attrs[] = {
&dev_attr_contrast.attr,
NULL,
};
ATTRIBUTE_GROUPS(wm8505fb);
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int wm8505fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info) {
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
int ret = 1;
unsigned int val;
if (regno >= 256)
return -EINVAL;
if (info->var.grayscale)
red = green = blue =
(19595 * red + 38470 * green + 7471 * blue) >> 16;
switch (fbi->fb.fix.visual) {
case FB_VISUAL_TRUECOLOR:
if (regno < 16) {
u32 *pal = info->pseudo_palette;
val = chan_to_field(red, &fbi->fb.var.red);
val |= chan_to_field(green, &fbi->fb.var.green);
val |= chan_to_field(blue, &fbi->fb.var.blue);
pal[regno] = val;
ret = 0;
}
break;
}
return ret;
}
static int wm8505fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
writel(var->xoffset, fbi->regbase + WMT_GOVR_XPAN);
writel(var->yoffset, fbi->regbase + WMT_GOVR_YPAN);
return 0;
}
static int wm8505fb_blank(int blank, struct fb_info *info)
{
struct wm8505fb_info *fbi = to_wm8505fb_info(info);
switch (blank) {
case FB_BLANK_UNBLANK:
wm8505fb_set_timing(info);
break;
default:
writel(0, fbi->regbase + WMT_GOVR_TIMING_V_SYNC);
break;
}
return 0;
}
static const struct fb_ops wm8505fb_ops = {
.owner = THIS_MODULE,
.fb_set_par = wm8505fb_set_par,
.fb_setcolreg = wm8505fb_setcolreg,
.fb_fillrect = wmt_ge_fillrect,
.fb_copyarea = wmt_ge_copyarea,
.fb_imageblit = sys_imageblit,
.fb_sync = wmt_ge_sync,
.fb_pan_display = wm8505fb_pan_display,
.fb_blank = wm8505fb_blank,
};
static int wm8505fb_probe(struct platform_device *pdev)
{
struct wm8505fb_info *fbi;
struct display_timings *disp_timing;
void *addr;
int ret;
struct fb_videomode mode;
u32 bpp;
dma_addr_t fb_mem_phys;
unsigned long fb_mem_len;
void *fb_mem_virt;
fbi = devm_kzalloc(&pdev->dev, sizeof(struct wm8505fb_info) +
sizeof(u32) * 16, GFP_KERNEL);
if (!fbi)
return -ENOMEM;
strcpy(fbi->fb.fix.id, DRIVER_NAME);
fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fb.fix.xpanstep = 1;
fbi->fb.fix.ypanstep = 1;
fbi->fb.fix.ywrapstep = 0;
fbi->fb.fix.accel = FB_ACCEL_NONE;
fbi->fb.fbops = &wm8505fb_ops;
fbi->fb.flags = FBINFO_HWACCEL_COPYAREA
| FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_XPAN
| FBINFO_HWACCEL_YPAN
| FBINFO_VIRTFB
| FBINFO_PARTIAL_PAN_OK;
fbi->fb.node = -1;
addr = fbi;
addr = addr + sizeof(struct wm8505fb_info);
fbi->fb.pseudo_palette = addr;
fbi->regbase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(fbi->regbase))
return PTR_ERR(fbi->regbase);
disp_timing = of_get_display_timings(pdev->dev.of_node);
if (!disp_timing)
return -EINVAL;
ret = of_get_fb_videomode(pdev->dev.of_node, &mode, OF_USE_NATIVE_MODE);
if (ret)
return ret;
ret = of_property_read_u32(pdev->dev.of_node, "bits-per-pixel", &bpp);
if (ret)
return ret;
fb_videomode_to_var(&fbi->fb.var, &mode);
fbi->fb.var.nonstd = 0;
fbi->fb.var.activate = FB_ACTIVATE_NOW;
fbi->fb.var.height = -1;
fbi->fb.var.width = -1;
/* try allocating the framebuffer */
fb_mem_len = mode.xres * mode.yres * 2 * (bpp / 8);
fb_mem_virt = dmam_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
GFP_KERNEL);
if (!fb_mem_virt) {
pr_err("%s: Failed to allocate framebuffer\n", __func__);
return -ENOMEM;
}
fbi->fb.var.xres_virtual = mode.xres;
fbi->fb.var.yres_virtual = mode.yres * 2;
fbi->fb.var.bits_per_pixel = bpp;
fbi->fb.fix.smem_start = fb_mem_phys;
fbi->fb.fix.smem_len = fb_mem_len;
fbi->fb.screen_buffer = fb_mem_virt;
fbi->fb.screen_size = fb_mem_len;
fbi->contrast = 0x10;
ret = wm8505fb_set_par(&fbi->fb);
if (ret) {
dev_err(&pdev->dev, "Failed to set parameters\n");
return ret;
}
if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
dev_err(&pdev->dev, "Failed to allocate color map\n");
return -ENOMEM;
}
wm8505fb_init_hw(&fbi->fb);
platform_set_drvdata(pdev, fbi);
ret = register_framebuffer(&fbi->fb);
if (ret < 0) {
dev_err(&pdev->dev,
"Failed to register framebuffer device: %d\n", ret);
if (fbi->fb.cmap.len)
fb_dealloc_cmap(&fbi->fb.cmap);
return ret;
}
fb_info(&fbi->fb, "%s frame buffer at 0x%lx-0x%lx\n",
fbi->fb.fix.id, fbi->fb.fix.smem_start,
fbi->fb.fix.smem_start + fbi->fb.fix.smem_len - 1);
return 0;
}
static void wm8505fb_remove(struct platform_device *pdev)
{
struct wm8505fb_info *fbi = platform_get_drvdata(pdev);
unregister_framebuffer(&fbi->fb);
writel(0, fbi->regbase);
if (fbi->fb.cmap.len)
fb_dealloc_cmap(&fbi->fb.cmap);
}
static const struct of_device_id wmt_dt_ids[] = {
{ .compatible = "wm,wm8505-fb", },
{}
};
static struct platform_driver wm8505fb_driver = {
.probe = wm8505fb_probe,
.remove_new = wm8505fb_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = wmt_dt_ids,
.dev_groups = wm8505fb_groups,
},
};
module_platform_driver(wm8505fb_driver);
MODULE_AUTHOR("Ed Spiridonov <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for WMT WM8505");
MODULE_DEVICE_TABLE(of, wmt_dt_ids);
| linux-master | drivers/video/fbdev/wm8505fb.c |
/*
* drivers/video/chipsfb.c -- frame buffer device for
* Chips & Technologies 65550 chip.
*
* Copyright (C) 1998-2002 Paul Mackerras
*
* This file is derived from the Powermac "chips" driver:
* Copyright (C) 1997 Fabio Riccardi.
* And from the frame buffer device for Open Firmware-initialized devices:
* Copyright (C) 1997 Geert Uytterhoeven.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/pm.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/console.h>
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
/*
* Since we access the display with inb/outb to fixed port numbers,
* we can only handle one 6555x chip. -- paulus
*/
#define write_ind(num, val, ap, dp) do { \
outb((num), (ap)); outb((val), (dp)); \
} while (0)
#define read_ind(num, var, ap, dp) do { \
outb((num), (ap)); var = inb((dp)); \
} while (0)
/* extension registers */
#define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7)
#define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7)
/* flat panel registers */
#define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1)
#define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1)
/* CRTC registers */
#define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5)
#define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5)
/* graphics registers */
#define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf)
#define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf)
/* sequencer registers */
#define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5)
#define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5)
/* attribute registers - slightly strange */
#define write_ar(num, val) do { \
inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
} while (0)
#define read_ar(num, var) do { \
inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
} while (0)
/*
* Exported functions
*/
int chips_init(void);
static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
static int chipsfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info);
static int chipsfb_set_par(struct fb_info *info);
static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int chipsfb_blank(int blank, struct fb_info *info);
static const struct fb_ops chipsfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = chipsfb_check_var,
.fb_set_par = chipsfb_set_par,
.fb_setcolreg = chipsfb_setcolreg,
.fb_blank = chipsfb_blank,
};
static int chipsfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if (var->xres > 800 || var->yres > 600
|| var->xres_virtual > 800 || var->yres_virtual > 600
|| (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
|| var->nonstd
|| (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
return -EINVAL;
var->xres = var->xres_virtual = 800;
var->yres = var->yres_virtual = 600;
return 0;
}
static int chipsfb_set_par(struct fb_info *info)
{
if (info->var.bits_per_pixel == 16) {
write_cr(0x13, 200); // Set line length (doublewords)
write_xr(0x81, 0x14); // 15 bit (555) color mode
write_xr(0x82, 0x00); // Disable palettes
write_xr(0x20, 0x10); // 16 bit blitter mode
info->fix.line_length = 800*2;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->var.red.offset = 10;
info->var.green.offset = 5;
info->var.blue.offset = 0;
info->var.red.length = info->var.green.length =
info->var.blue.length = 5;
} else {
/* p->var.bits_per_pixel == 8 */
write_cr(0x13, 100); // Set line length (doublewords)
write_xr(0x81, 0x12); // 8 bit color mode
write_xr(0x82, 0x08); // Graphics gamma enable
write_xr(0x20, 0x00); // 8 bit blitter mode
info->fix.line_length = 800;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->var.red.offset = info->var.green.offset =
info->var.blue.offset = 0;
info->var.red.length = info->var.green.length =
info->var.blue.length = 8;
}
return 0;
}
static int chipsfb_blank(int blank, struct fb_info *info)
{
return 1; /* get fb_blank to set the colormap to all black */
}
static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
outb(regno, 0x3c8);
udelay(1);
outb(red, 0x3c9);
outb(green, 0x3c9);
outb(blue, 0x3c9);
return 0;
}
struct chips_init_reg {
unsigned char addr;
unsigned char data;
};
static struct chips_init_reg chips_init_sr[] = {
{ 0x00, 0x03 },
{ 0x01, 0x01 },
{ 0x02, 0x0f },
{ 0x04, 0x0e }
};
static struct chips_init_reg chips_init_gr[] = {
{ 0x05, 0x00 },
{ 0x06, 0x0d },
{ 0x08, 0xff }
};
static struct chips_init_reg chips_init_ar[] = {
{ 0x10, 0x01 },
{ 0x12, 0x0f },
{ 0x13, 0x00 }
};
static struct chips_init_reg chips_init_cr[] = {
{ 0x00, 0x7f },
{ 0x01, 0x63 },
{ 0x02, 0x63 },
{ 0x03, 0x83 },
{ 0x04, 0x66 },
{ 0x05, 0x10 },
{ 0x06, 0x72 },
{ 0x07, 0x3e },
{ 0x08, 0x00 },
{ 0x09, 0x40 },
{ 0x0c, 0x00 },
{ 0x0d, 0x00 },
{ 0x10, 0x59 },
{ 0x11, 0x0d },
{ 0x12, 0x57 },
{ 0x13, 0x64 },
{ 0x14, 0x00 },
{ 0x15, 0x57 },
{ 0x16, 0x73 },
{ 0x17, 0xe3 },
{ 0x18, 0xff },
{ 0x30, 0x02 },
{ 0x31, 0x02 },
{ 0x32, 0x02 },
{ 0x33, 0x02 },
{ 0x40, 0x00 },
{ 0x41, 0x00 },
{ 0x40, 0x80 }
};
static struct chips_init_reg chips_init_fr[] = {
{ 0x01, 0x02 },
{ 0x03, 0x08 },
{ 0x04, 0x81 },
{ 0x05, 0x21 },
{ 0x08, 0x0c },
{ 0x0a, 0x74 },
{ 0x0b, 0x11 },
{ 0x10, 0x0c },
{ 0x11, 0xe0 },
/* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
{ 0x20, 0x63 },
{ 0x21, 0x68 },
{ 0x22, 0x19 },
{ 0x23, 0x7f },
{ 0x24, 0x68 },
{ 0x26, 0x00 },
{ 0x27, 0x0f },
{ 0x30, 0x57 },
{ 0x31, 0x58 },
{ 0x32, 0x0d },
{ 0x33, 0x72 },
{ 0x34, 0x02 },
{ 0x35, 0x22 },
{ 0x36, 0x02 },
{ 0x37, 0x00 }
};
static struct chips_init_reg chips_init_xr[] = {
{ 0xce, 0x00 }, /* set default memory clock */
{ 0xcc, 0x43 }, /* memory clock ratio */
{ 0xcd, 0x18 },
{ 0xce, 0xa1 },
{ 0xc8, 0x84 },
{ 0xc9, 0x0a },
{ 0xca, 0x00 },
{ 0xcb, 0x20 },
{ 0xcf, 0x06 },
{ 0xd0, 0x0e },
{ 0x09, 0x01 },
{ 0x0a, 0x02 },
{ 0x0b, 0x01 },
{ 0x20, 0x00 },
{ 0x40, 0x03 },
{ 0x41, 0x01 },
{ 0x42, 0x00 },
{ 0x80, 0x82 },
{ 0x81, 0x12 },
{ 0x82, 0x08 },
{ 0xa0, 0x00 },
{ 0xa8, 0x00 }
};
static void chips_hw_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
outb(0x29, 0x3c2); /* set misc output reg */
for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
}
static const struct fb_fix_screeninfo chipsfb_fix = {
.id = "C&T 65550",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.accel = FB_ACCEL_NONE,
.line_length = 800,
// FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
// * "3500" PowerBook G3 (the original PB G3) has 2MB.
// * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
// Motherboard actually supports 2MB -- there are two blank locations
// for a second pair of DRAMs. (Thanks, Apple!)
// * 3400 has 1MB (I think). Don't know if it's expandable.
// -- Tim Seufert
.smem_len = 0x100000, /* 1MB */
};
static const struct fb_var_screeninfo chipsfb_var = {
.xres = 800,
.yres = 600,
.xres_virtual = 800,
.yres_virtual = 600,
.bits_per_pixel = 8,
.red = { .length = 8 },
.green = { .length = 8 },
.blue = { .length = 8 },
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
.pixclock = 10000,
.left_margin = 16,
.right_margin = 16,
.upper_margin = 16,
.lower_margin = 16,
.hsync_len = 8,
.vsync_len = 8,
};
static void init_chips(struct fb_info *p, unsigned long addr)
{
fb_memset_io(p->screen_base, 0, 0x100000);
p->fix = chipsfb_fix;
p->fix.smem_start = addr;
p->var = chipsfb_var;
p->fbops = &chipsfb_ops;
fb_alloc_cmap(&p->cmap, 256, 0);
chips_hw_init();
}
static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
{
struct fb_info *p;
unsigned long addr;
unsigned short cmd;
int rc;
rc = aperture_remove_conflicting_pci_devices(dp, "chipsfb");
if (rc)
return rc;
rc = pci_enable_device(dp);
if (rc < 0) {
dev_err(&dp->dev, "Cannot enable PCI device\n");
goto err_out;
}
if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) {
rc = -ENODEV;
goto err_disable;
}
addr = pci_resource_start(dp, 0);
if (addr == 0) {
rc = -ENODEV;
goto err_disable;
}
p = framebuffer_alloc(0, &dp->dev);
if (p == NULL) {
rc = -ENOMEM;
goto err_disable;
}
if (pci_request_region(dp, 0, "chipsfb") != 0) {
dev_err(&dp->dev, "Cannot request framebuffer\n");
rc = -EBUSY;
goto err_release_fb;
}
#ifdef __BIG_ENDIAN
addr += 0x800000; // Use big-endian aperture
#endif
/* we should use pci_enable_device here, but,
the device doesn't declare its I/O ports in its BARs
so pci_enable_device won't turn on I/O responses */
pci_read_config_word(dp, PCI_COMMAND, &cmd);
cmd |= 3; /* enable memory and IO space */
pci_write_config_word(dp, PCI_COMMAND, cmd);
#ifdef CONFIG_PMAC_BACKLIGHT
/* turn on the backlight */
mutex_lock(&pmac_backlight_mutex);
if (pmac_backlight) {
pmac_backlight->props.power = FB_BLANK_UNBLANK;
backlight_update_status(pmac_backlight);
}
mutex_unlock(&pmac_backlight_mutex);
#endif /* CONFIG_PMAC_BACKLIGHT */
#ifdef CONFIG_PPC
p->screen_base = ioremap_wc(addr, 0x200000);
#else
p->screen_base = ioremap(addr, 0x200000);
#endif
if (p->screen_base == NULL) {
dev_err(&dp->dev, "Cannot map framebuffer\n");
rc = -ENOMEM;
goto err_release_pci;
}
pci_set_drvdata(dp, p);
init_chips(p, addr);
rc = register_framebuffer(p);
if (rc < 0) {
dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
goto err_unmap;
}
dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
" (%dK RAM detected)\n",
p->node, p->fix.smem_len / 1024);
return 0;
err_unmap:
iounmap(p->screen_base);
err_release_pci:
pci_release_region(dp, 0);
err_release_fb:
framebuffer_release(p);
err_disable:
pci_disable_device(dp);
err_out:
return rc;
}
static void chipsfb_remove(struct pci_dev *dp)
{
struct fb_info *p = pci_get_drvdata(dp);
if (p->screen_base == NULL)
return;
unregister_framebuffer(p);
iounmap(p->screen_base);
p->screen_base = NULL;
pci_release_region(dp, 0);
}
#ifdef CONFIG_PM
static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct fb_info *p = pci_get_drvdata(pdev);
if (state.event == pdev->dev.power.power_state.event)
return 0;
if (!(state.event & PM_EVENT_SLEEP))
goto done;
console_lock();
chipsfb_blank(1, p);
fb_set_suspend(p, 1);
console_unlock();
done:
pdev->dev.power.power_state = state;
return 0;
}
static int chipsfb_pci_resume(struct pci_dev *pdev)
{
struct fb_info *p = pci_get_drvdata(pdev);
console_lock();
fb_set_suspend(p, 0);
chipsfb_blank(0, p);
console_unlock();
pdev->dev.power.power_state = PMSG_ON;
return 0;
}
#endif /* CONFIG_PM */
static struct pci_device_id chipsfb_pci_tbl[] = {
{ PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
{ 0 }
};
MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
static struct pci_driver chipsfb_driver = {
.name = "chipsfb",
.id_table = chipsfb_pci_tbl,
.probe = chipsfb_pci_init,
.remove = chipsfb_remove,
#ifdef CONFIG_PM
.suspend = chipsfb_pci_suspend,
.resume = chipsfb_pci_resume,
#endif
};
int __init chips_init(void)
{
if (fb_modesetting_disabled("chipsfb"))
return -ENODEV;
if (fb_get_options("chipsfb", NULL))
return -ENODEV;
return pci_register_driver(&chipsfb_driver);
}
module_init(chips_init);
static void __exit chipsfb_exit(void)
{
pci_unregister_driver(&chipsfb_driver);
}
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/chipsfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/cyber2000fb.c
*
* Copyright (C) 1998-2002 Russell King
*
* MIPS and 50xx clock support
* Copyright (C) 2001 Bradley D. LaRonde <[email protected]>
*
* 32 bit support, text color and panning fixes for modes != 8 bit
* Copyright (C) 2002 Denis Oliver Kropp <[email protected]>
*
* Integraphics CyberPro 2000, 2010 and 5000 frame buffer device
*
* Based on cyberfb.c.
*
* Note that we now use the new fbcon fix, var and cmap scheme. We do
* still have to check which console is the currently displayed one
* however, especially for the colourmap stuff.
*
* We also use the new hotplug PCI subsystem. I'm not sure if there
* are any such cards, but I'm erring on the side of caution. We don't
* want to go pop just because someone does have one.
*
* Note that this doesn't work fully in the case of multiple CyberPro
* cards with grabbers. We currently can only attach to the first
* CyberPro card found.
*
* When we're in truecolour mode, we power down the LUT RAM as a power
* saving feature. Also, when we enter any of the powersaving modes
* (except soft blanking) we power down the RAMDACs. This saves about
* 1W, which is roughly 8% of the power consumption of a NetWinder
* (which, incidentally, is about the same saving as a 2.5in hard disk
* entering standby mode.)
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#ifdef __arm__
#include <asm/mach-types.h>
#endif
#include "cyber2000fb.h"
struct cfb_info {
struct fb_info fb;
struct display_switch *dispsw;
unsigned char __iomem *region;
unsigned char __iomem *regs;
u_int id;
u_int irq;
int func_use_count;
u_long ref_ps;
/*
* Clock divisors
*/
u_int divisors[4];
struct {
u8 red, green, blue;
} palette[NR_PALETTE];
u_char mem_ctl1;
u_char mem_ctl2;
u_char mclk_mult;
u_char mclk_div;
/*
* RAMDAC control register is both of these or'ed together
*/
u_char ramdac_ctrl;
u_char ramdac_powerdown;
u32 pseudo_palette[16];
spinlock_t reg_b0_lock;
#ifdef CONFIG_FB_CYBER2000_DDC
bool ddc_registered;
struct i2c_adapter ddc_adapter;
struct i2c_algo_bit_data ddc_algo;
#endif
#ifdef CONFIG_FB_CYBER2000_I2C
struct i2c_adapter i2c_adapter;
struct i2c_algo_bit_data i2c_algo;
#endif
};
static char *default_font = "Acorn8x8";
module_param(default_font, charp, 0);
MODULE_PARM_DESC(default_font, "Default font name");
/*
* Our access methods.
*/
#define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg))
#define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg))
#define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg))
#define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg))
static inline void
cyber2000_crtcw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
{
cyber2000fb_writew((reg & 255) | val << 8, 0x3d4, cfb);
}
static inline void
cyber2000_grphw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
{
cyber2000fb_writew((reg & 255) | val << 8, 0x3ce, cfb);
}
static inline unsigned int
cyber2000_grphr(unsigned int reg, struct cfb_info *cfb)
{
cyber2000fb_writeb(reg, 0x3ce, cfb);
return cyber2000fb_readb(0x3cf, cfb);
}
static inline void
cyber2000_attrw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
{
cyber2000fb_readb(0x3da, cfb);
cyber2000fb_writeb(reg, 0x3c0, cfb);
cyber2000fb_readb(0x3c1, cfb);
cyber2000fb_writeb(val, 0x3c0, cfb);
}
static inline void
cyber2000_seqw(unsigned int reg, unsigned int val, struct cfb_info *cfb)
{
cyber2000fb_writew((reg & 255) | val << 8, 0x3c4, cfb);
}
/* -------------------- Hardware specific routines ------------------------- */
/*
* Hardware Cyber2000 Acceleration
*/
static void
cyber2000fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
unsigned long dst, col;
if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
cfb_fillrect(info, rect);
return;
}
cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
cyber2000fb_writew(rect->width - 1, CO_REG_PIXWIDTH, cfb);
cyber2000fb_writew(rect->height - 1, CO_REG_PIXHEIGHT, cfb);
col = rect->color;
if (cfb->fb.var.bits_per_pixel > 8)
col = ((u32 *)cfb->fb.pseudo_palette)[col];
cyber2000fb_writel(col, CO_REG_FGCOLOUR, cfb);
dst = rect->dx + rect->dy * cfb->fb.var.xres_virtual;
if (cfb->fb.var.bits_per_pixel == 24) {
cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
dst *= 3;
}
cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
cyber2000fb_writeb(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
cyber2000fb_writew(CO_CMD_L_PATTERN_FGCOL, CO_REG_CMD_L, cfb);
cyber2000fb_writew(CO_CMD_H_BLITTER, CO_REG_CMD_H, cfb);
}
static void
cyber2000fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
unsigned int cmd = CO_CMD_L_PATTERN_FGCOL;
unsigned long src, dst;
if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) {
cfb_copyarea(info, region);
return;
}
cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
cyber2000fb_writew(region->width - 1, CO_REG_PIXWIDTH, cfb);
cyber2000fb_writew(region->height - 1, CO_REG_PIXHEIGHT, cfb);
src = region->sx + region->sy * cfb->fb.var.xres_virtual;
dst = region->dx + region->dy * cfb->fb.var.xres_virtual;
if (region->sx < region->dx) {
src += region->width - 1;
dst += region->width - 1;
cmd |= CO_CMD_L_INC_LEFT;
}
if (region->sy < region->dy) {
src += (region->height - 1) * cfb->fb.var.xres_virtual;
dst += (region->height - 1) * cfb->fb.var.xres_virtual;
cmd |= CO_CMD_L_INC_UP;
}
if (cfb->fb.var.bits_per_pixel == 24) {
cyber2000fb_writeb(dst, CO_REG_X_PHASE, cfb);
src *= 3;
dst *= 3;
}
cyber2000fb_writel(src, CO_REG_SRC1_PTR, cfb);
cyber2000fb_writel(dst, CO_REG_DEST_PTR, cfb);
cyber2000fb_writew(CO_FG_MIX_SRC, CO_REG_FGMIX, cfb);
cyber2000fb_writew(cmd, CO_REG_CMD_L, cfb);
cyber2000fb_writew(CO_CMD_H_FGSRCMAP | CO_CMD_H_BLITTER,
CO_REG_CMD_H, cfb);
}
static void
cyber2000fb_imageblit(struct fb_info *info, const struct fb_image *image)
{
cfb_imageblit(info, image);
return;
}
static int cyber2000fb_sync(struct fb_info *info)
{
struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
int count = 100000;
if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT))
return 0;
while (cyber2000fb_readb(CO_REG_CONTROL, cfb) & CO_CTRL_BUSY) {
if (!count--) {
debug_printf("accel_wait timed out\n");
cyber2000fb_writeb(0, CO_REG_CONTROL, cfb);
break;
}
udelay(1);
}
return 0;
}
/*
* ===========================================================================
*/
static inline u32 convert_bitfield(u_int val, struct fb_bitfield *bf)
{
u_int mask = (1 << bf->length) - 1;
return (val >> (16 - bf->length) & mask) << bf->offset;
}
/*
* Set a single color register. Return != 0 for invalid regno.
*/
static int
cyber2000fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
struct fb_var_screeninfo *var = &cfb->fb.var;
u32 pseudo_val;
int ret = 1;
switch (cfb->fb.fix.visual) {
default:
return 1;
/*
* Pseudocolour:
* 8 8
* pixel --/--+--/--> red lut --> red dac
* | 8
* +--/--> green lut --> green dac
* | 8
* +--/--> blue lut --> blue dac
*/
case FB_VISUAL_PSEUDOCOLOR:
if (regno >= NR_PALETTE)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
cfb->palette[regno].red = red;
cfb->palette[regno].green = green;
cfb->palette[regno].blue = blue;
cyber2000fb_writeb(regno, 0x3c8, cfb);
cyber2000fb_writeb(red, 0x3c9, cfb);
cyber2000fb_writeb(green, 0x3c9, cfb);
cyber2000fb_writeb(blue, 0x3c9, cfb);
return 0;
/*
* Direct colour:
* n rl
* pixel --/--+--/--> red lut --> red dac
* | gl
* +--/--> green lut --> green dac
* | bl
* +--/--> blue lut --> blue dac
* n = bpp, rl = red length, gl = green length, bl = blue length
*/
case FB_VISUAL_DIRECTCOLOR:
red >>= 8;
green >>= 8;
blue >>= 8;
if (var->green.length == 6 && regno < 64) {
cfb->palette[regno << 2].green = green;
/*
* The 6 bits of the green component are applied
* to the high 6 bits of the LUT.
*/
cyber2000fb_writeb(regno << 2, 0x3c8, cfb);
cyber2000fb_writeb(cfb->palette[regno >> 1].red,
0x3c9, cfb);
cyber2000fb_writeb(green, 0x3c9, cfb);
cyber2000fb_writeb(cfb->palette[regno >> 1].blue,
0x3c9, cfb);
green = cfb->palette[regno << 3].green;
ret = 0;
}
if (var->green.length >= 5 && regno < 32) {
cfb->palette[regno << 3].red = red;
cfb->palette[regno << 3].green = green;
cfb->palette[regno << 3].blue = blue;
/*
* The 5 bits of each colour component are
* applied to the high 5 bits of the LUT.
*/
cyber2000fb_writeb(regno << 3, 0x3c8, cfb);
cyber2000fb_writeb(red, 0x3c9, cfb);
cyber2000fb_writeb(green, 0x3c9, cfb);
cyber2000fb_writeb(blue, 0x3c9, cfb);
ret = 0;
}
if (var->green.length == 4 && regno < 16) {
cfb->palette[regno << 4].red = red;
cfb->palette[regno << 4].green = green;
cfb->palette[regno << 4].blue = blue;
/*
* The 5 bits of each colour component are
* applied to the high 5 bits of the LUT.
*/
cyber2000fb_writeb(regno << 4, 0x3c8, cfb);
cyber2000fb_writeb(red, 0x3c9, cfb);
cyber2000fb_writeb(green, 0x3c9, cfb);
cyber2000fb_writeb(blue, 0x3c9, cfb);
ret = 0;
}
/*
* Since this is only used for the first 16 colours, we
* don't have to care about overflowing for regno >= 32
*/
pseudo_val = regno << var->red.offset |
regno << var->green.offset |
regno << var->blue.offset;
break;
/*
* True colour:
* n rl
* pixel --/--+--/--> red dac
* | gl
* +--/--> green dac
* | bl
* +--/--> blue dac
* n = bpp, rl = red length, gl = green length, bl = blue length
*/
case FB_VISUAL_TRUECOLOR:
pseudo_val = convert_bitfield(transp ^ 0xffff, &var->transp);
pseudo_val |= convert_bitfield(red, &var->red);
pseudo_val |= convert_bitfield(green, &var->green);
pseudo_val |= convert_bitfield(blue, &var->blue);
ret = 0;
break;
}
/*
* Now set our pseudo palette for the CFB16/24/32 drivers.
*/
if (regno < 16)
((u32 *)cfb->fb.pseudo_palette)[regno] = pseudo_val;
return ret;
}
struct par_info {
/*
* Hardware
*/
u_char clock_mult;
u_char clock_div;
u_char extseqmisc;
u_char co_pixfmt;
u_char crtc_ofl;
u_char crtc[19];
u_int width;
u_int pitch;
u_int fetch;
/*
* Other
*/
u_char ramdac;
};
static const u_char crtc_idx[] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18
};
static void cyber2000fb_write_ramdac_ctrl(struct cfb_info *cfb)
{
unsigned int i;
unsigned int val = cfb->ramdac_ctrl | cfb->ramdac_powerdown;
cyber2000fb_writeb(0x56, 0x3ce, cfb);
i = cyber2000fb_readb(0x3cf, cfb);
cyber2000fb_writeb(i | 4, 0x3cf, cfb);
cyber2000fb_writeb(val, 0x3c6, cfb);
cyber2000fb_writeb(i, 0x3cf, cfb);
/* prevent card lock-up observed on x86 with CyberPro 2000 */
cyber2000fb_readb(0x3cf, cfb);
}
static void cyber2000fb_set_timing(struct cfb_info *cfb, struct par_info *hw)
{
u_int i;
/*
* Blank palette
*/
for (i = 0; i < NR_PALETTE; i++) {
cyber2000fb_writeb(i, 0x3c8, cfb);
cyber2000fb_writeb(0, 0x3c9, cfb);
cyber2000fb_writeb(0, 0x3c9, cfb);
cyber2000fb_writeb(0, 0x3c9, cfb);
}
cyber2000fb_writeb(0xef, 0x3c2, cfb);
cyber2000_crtcw(0x11, 0x0b, cfb);
cyber2000_attrw(0x11, 0x00, cfb);
cyber2000_seqw(0x00, 0x01, cfb);
cyber2000_seqw(0x01, 0x01, cfb);
cyber2000_seqw(0x02, 0x0f, cfb);
cyber2000_seqw(0x03, 0x00, cfb);
cyber2000_seqw(0x04, 0x0e, cfb);
cyber2000_seqw(0x00, 0x03, cfb);
for (i = 0; i < sizeof(crtc_idx); i++)
cyber2000_crtcw(crtc_idx[i], hw->crtc[i], cfb);
for (i = 0x0a; i < 0x10; i++)
cyber2000_crtcw(i, 0, cfb);
cyber2000_grphw(EXT_CRT_VRTOFL, hw->crtc_ofl, cfb);
cyber2000_grphw(0x00, 0x00, cfb);
cyber2000_grphw(0x01, 0x00, cfb);
cyber2000_grphw(0x02, 0x00, cfb);
cyber2000_grphw(0x03, 0x00, cfb);
cyber2000_grphw(0x04, 0x00, cfb);
cyber2000_grphw(0x05, 0x60, cfb);
cyber2000_grphw(0x06, 0x05, cfb);
cyber2000_grphw(0x07, 0x0f, cfb);
cyber2000_grphw(0x08, 0xff, cfb);
/* Attribute controller registers */
for (i = 0; i < 16; i++)
cyber2000_attrw(i, i, cfb);
cyber2000_attrw(0x10, 0x01, cfb);
cyber2000_attrw(0x11, 0x00, cfb);
cyber2000_attrw(0x12, 0x0f, cfb);
cyber2000_attrw(0x13, 0x00, cfb);
cyber2000_attrw(0x14, 0x00, cfb);
/* PLL registers */
spin_lock(&cfb->reg_b0_lock);
cyber2000_grphw(EXT_DCLK_MULT, hw->clock_mult, cfb);
cyber2000_grphw(EXT_DCLK_DIV, hw->clock_div, cfb);
cyber2000_grphw(EXT_MCLK_MULT, cfb->mclk_mult, cfb);
cyber2000_grphw(EXT_MCLK_DIV, cfb->mclk_div, cfb);
cyber2000_grphw(0x90, 0x01, cfb);
cyber2000_grphw(0xb9, 0x80, cfb);
cyber2000_grphw(0xb9, 0x00, cfb);
spin_unlock(&cfb->reg_b0_lock);
cfb->ramdac_ctrl = hw->ramdac;
cyber2000fb_write_ramdac_ctrl(cfb);
cyber2000fb_writeb(0x20, 0x3c0, cfb);
cyber2000fb_writeb(0xff, 0x3c6, cfb);
cyber2000_grphw(0x14, hw->fetch, cfb);
cyber2000_grphw(0x15, ((hw->fetch >> 8) & 0x03) |
((hw->pitch >> 4) & 0x30), cfb);
cyber2000_grphw(EXT_SEQ_MISC, hw->extseqmisc, cfb);
/*
* Set up accelerator registers
*/
cyber2000fb_writew(hw->width, CO_REG_SRC_WIDTH, cfb);
cyber2000fb_writew(hw->width, CO_REG_DEST_WIDTH, cfb);
cyber2000fb_writeb(hw->co_pixfmt, CO_REG_PIXFMT, cfb);
}
static inline int
cyber2000fb_update_start(struct cfb_info *cfb, struct fb_var_screeninfo *var)
{
u_int base = var->yoffset * var->xres_virtual + var->xoffset;
base *= var->bits_per_pixel;
/*
* Convert to bytes and shift two extra bits because DAC
* can only start on 4 byte aligned data.
*/
base >>= 5;
if (base >= 1 << 20)
return -EINVAL;
cyber2000_grphw(0x10, base >> 16 | 0x10, cfb);
cyber2000_crtcw(0x0c, base >> 8, cfb);
cyber2000_crtcw(0x0d, base, cfb);
return 0;
}
static int
cyber2000fb_decode_crtc(struct par_info *hw, struct cfb_info *cfb,
struct fb_var_screeninfo *var)
{
u_int Htotal, Hblankend, Hsyncend;
u_int Vtotal, Vdispend, Vblankstart, Vblankend, Vsyncstart, Vsyncend;
#define ENCODE_BIT(v, b1, m, b2) ((((v) >> (b1)) & (m)) << (b2))
hw->crtc[13] = hw->pitch;
hw->crtc[17] = 0xe3;
hw->crtc[14] = 0;
hw->crtc[8] = 0;
Htotal = var->xres + var->right_margin +
var->hsync_len + var->left_margin;
if (Htotal > 2080)
return -EINVAL;
hw->crtc[0] = (Htotal >> 3) - 5;
hw->crtc[1] = (var->xres >> 3) - 1;
hw->crtc[2] = var->xres >> 3;
hw->crtc[4] = (var->xres + var->right_margin) >> 3;
Hblankend = (Htotal - 4 * 8) >> 3;
hw->crtc[3] = ENCODE_BIT(Hblankend, 0, 0x1f, 0) |
ENCODE_BIT(1, 0, 0x01, 7);
Hsyncend = (var->xres + var->right_margin + var->hsync_len) >> 3;
hw->crtc[5] = ENCODE_BIT(Hsyncend, 0, 0x1f, 0) |
ENCODE_BIT(Hblankend, 5, 0x01, 7);
Vdispend = var->yres - 1;
Vsyncstart = var->yres + var->lower_margin;
Vsyncend = var->yres + var->lower_margin + var->vsync_len;
Vtotal = var->yres + var->lower_margin + var->vsync_len +
var->upper_margin - 2;
if (Vtotal > 2047)
return -EINVAL;
Vblankstart = var->yres + 6;
Vblankend = Vtotal - 10;
hw->crtc[6] = Vtotal;
hw->crtc[7] = ENCODE_BIT(Vtotal, 8, 0x01, 0) |
ENCODE_BIT(Vdispend, 8, 0x01, 1) |
ENCODE_BIT(Vsyncstart, 8, 0x01, 2) |
ENCODE_BIT(Vblankstart, 8, 0x01, 3) |
ENCODE_BIT(1, 0, 0x01, 4) |
ENCODE_BIT(Vtotal, 9, 0x01, 5) |
ENCODE_BIT(Vdispend, 9, 0x01, 6) |
ENCODE_BIT(Vsyncstart, 9, 0x01, 7);
hw->crtc[9] = ENCODE_BIT(0, 0, 0x1f, 0) |
ENCODE_BIT(Vblankstart, 9, 0x01, 5) |
ENCODE_BIT(1, 0, 0x01, 6);
hw->crtc[10] = Vsyncstart;
hw->crtc[11] = ENCODE_BIT(Vsyncend, 0, 0x0f, 0) |
ENCODE_BIT(1, 0, 0x01, 7);
hw->crtc[12] = Vdispend;
hw->crtc[15] = Vblankstart;
hw->crtc[16] = Vblankend;
hw->crtc[18] = 0xff;
/*
* overflow - graphics reg 0x11
* 0=VTOTAL:10 1=VDEND:10 2=VRSTART:10 3=VBSTART:10
* 4=LINECOMP:10 5-IVIDEO 6=FIXCNT
*/
hw->crtc_ofl =
ENCODE_BIT(Vtotal, 10, 0x01, 0) |
ENCODE_BIT(Vdispend, 10, 0x01, 1) |
ENCODE_BIT(Vsyncstart, 10, 0x01, 2) |
ENCODE_BIT(Vblankstart, 10, 0x01, 3) |
EXT_CRT_VRTOFL_LINECOMP10;
/* woody: set the interlaced bit... */
/* FIXME: what about doublescan? */
if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
hw->crtc_ofl |= EXT_CRT_VRTOFL_INTERLACE;
return 0;
}
/*
* The following was discovered by a good monitor, bit twiddling, theorising
* and but mostly luck. Strangely, it looks like everyone elses' PLL!
*
* Clock registers:
* fclock = fpll / div2
* fpll = fref * mult / div1
* where:
* fref = 14.318MHz (69842ps)
* mult = reg0xb0.7:0
* div1 = (reg0xb1.5:0 + 1)
* div2 = 2^(reg0xb1.7:6)
* fpll should be between 115 and 260 MHz
* (8696ps and 3846ps)
*/
static int
cyber2000fb_decode_clock(struct par_info *hw, struct cfb_info *cfb,
struct fb_var_screeninfo *var)
{
u_long pll_ps = var->pixclock;
const u_long ref_ps = cfb->ref_ps;
u_int div2, t_div1, best_div1, best_mult;
int best_diff;
int vco;
/*
* Step 1:
* find div2 such that 115MHz < fpll < 260MHz
* and 0 <= div2 < 4
*/
for (div2 = 0; div2 < 4; div2++) {
u_long new_pll;
new_pll = pll_ps / cfb->divisors[div2];
if (8696 > new_pll && new_pll > 3846) {
pll_ps = new_pll;
break;
}
}
if (div2 == 4)
return -EINVAL;
/*
* Step 2:
* Given pll_ps and ref_ps, find:
* pll_ps * 0.995 < pll_ps_calc < pll_ps * 1.005
* where { 1 < best_div1 < 32, 1 < best_mult < 256 }
* pll_ps_calc = best_div1 / (ref_ps * best_mult)
*/
best_diff = 0x7fffffff;
best_mult = 2;
best_div1 = 32;
for (t_div1 = 2; t_div1 < 32; t_div1 += 1) {
u_int rr, t_mult, t_pll_ps;
int diff;
/*
* Find the multiplier for this divisor
*/
rr = ref_ps * t_div1;
t_mult = (rr + pll_ps / 2) / pll_ps;
/*
* Is the multiplier within the correct range?
*/
if (t_mult > 256 || t_mult < 2)
continue;
/*
* Calculate the actual clock period from this multiplier
* and divisor, and estimate the error.
*/
t_pll_ps = (rr + t_mult / 2) / t_mult;
diff = pll_ps - t_pll_ps;
if (diff < 0)
diff = -diff;
if (diff < best_diff) {
best_diff = diff;
best_mult = t_mult;
best_div1 = t_div1;
}
/*
* If we hit an exact value, there is no point in continuing.
*/
if (diff == 0)
break;
}
/*
* Step 3:
* combine values
*/
hw->clock_mult = best_mult - 1;
hw->clock_div = div2 << 6 | (best_div1 - 1);
vco = ref_ps * best_div1 / best_mult;
if ((ref_ps == 40690) && (vco < 5556))
/* Set VFSEL when VCO > 180MHz (5.556 ps). */
hw->clock_div |= EXT_DCLK_DIV_VFSEL;
return 0;
}
/*
* Set the User Defined Part of the Display
*/
static int
cyber2000fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
struct par_info hw;
unsigned int mem;
int err;
var->transp.msb_right = 0;
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.offset = 0;
var->transp.length = 0;
switch (var->bits_per_pixel) {
case 8: /* PSEUDOCOLOUR, 256 */
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
case 16:/* DIRECTCOLOUR, 64k or 32k */
switch (var->green.length) {
case 6: /* RGB565, 64k */
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
break;
default:
case 5: /* RGB555, 32k */
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 0;
var->blue.length = 5;
break;
case 4: /* RGB444, 4k + transparency? */
var->transp.offset = 12;
var->transp.length = 4;
var->red.offset = 8;
var->red.length = 4;
var->green.offset = 4;
var->green.length = 4;
var->blue.offset = 0;
var->blue.length = 4;
break;
}
break;
case 24:/* TRUECOLOUR, 16m */
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
case 32:/* TRUECOLOUR, 16m */
var->transp.offset = 24;
var->transp.length = 8;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
default:
return -EINVAL;
}
mem = var->xres_virtual * var->yres_virtual * (var->bits_per_pixel / 8);
if (mem > cfb->fb.fix.smem_len)
var->yres_virtual = cfb->fb.fix.smem_len * 8 /
(var->bits_per_pixel * var->xres_virtual);
if (var->yres > var->yres_virtual)
var->yres = var->yres_virtual;
if (var->xres > var->xres_virtual)
var->xres = var->xres_virtual;
err = cyber2000fb_decode_clock(&hw, cfb, var);
if (err)
return err;
err = cyber2000fb_decode_crtc(&hw, cfb, var);
if (err)
return err;
return 0;
}
static int cyber2000fb_set_par(struct fb_info *info)
{
struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
struct fb_var_screeninfo *var = &cfb->fb.var;
struct par_info hw;
unsigned int mem;
hw.width = var->xres_virtual;
hw.ramdac = RAMDAC_VREFEN | RAMDAC_DAC8BIT;
switch (var->bits_per_pixel) {
case 8:
hw.co_pixfmt = CO_PIXFMT_8BPP;
hw.pitch = hw.width >> 3;
hw.extseqmisc = EXT_SEQ_MISC_8;
break;
case 16:
hw.co_pixfmt = CO_PIXFMT_16BPP;
hw.pitch = hw.width >> 2;
switch (var->green.length) {
case 6: /* RGB565, 64k */
hw.extseqmisc = EXT_SEQ_MISC_16_RGB565;
break;
case 5: /* RGB555, 32k */
hw.extseqmisc = EXT_SEQ_MISC_16_RGB555;
break;
case 4: /* RGB444, 4k + transparency? */
hw.extseqmisc = EXT_SEQ_MISC_16_RGB444;
break;
default:
BUG();
}
break;
case 24:/* TRUECOLOUR, 16m */
hw.co_pixfmt = CO_PIXFMT_24BPP;
hw.width *= 3;
hw.pitch = hw.width >> 3;
hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
hw.extseqmisc = EXT_SEQ_MISC_24_RGB888;
break;
case 32:/* TRUECOLOUR, 16m */
hw.co_pixfmt = CO_PIXFMT_32BPP;
hw.pitch = hw.width >> 1;
hw.ramdac |= (RAMDAC_BYPASS | RAMDAC_RAMPWRDN);
hw.extseqmisc = EXT_SEQ_MISC_32;
break;
default:
BUG();
}
/*
* Sigh, this is absolutely disgusting, but caused by
* the way the fbcon developers want to separate out
* the "checking" and the "setting" of the video mode.
*
* If the mode is not suitable for the hardware here,
* we can't prevent it being set by returning an error.
*
* In theory, since NetWinders contain just one VGA card,
* we should never end up hitting this problem.
*/
BUG_ON(cyber2000fb_decode_clock(&hw, cfb, var) != 0);
BUG_ON(cyber2000fb_decode_crtc(&hw, cfb, var) != 0);
hw.width -= 1;
hw.fetch = hw.pitch;
if (!(cfb->mem_ctl2 & MEM_CTL2_64BIT))
hw.fetch <<= 1;
hw.fetch += 1;
cfb->fb.fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
/*
* Same here - if the size of the video mode exceeds the
* available RAM, we can't prevent this mode being set.
*
* In theory, since NetWinders contain just one VGA card,
* we should never end up hitting this problem.
*/
mem = cfb->fb.fix.line_length * var->yres_virtual;
BUG_ON(mem > cfb->fb.fix.smem_len);
/*
* 8bpp displays are always pseudo colour. 16bpp and above
* are direct colour or true colour, depending on whether
* the RAMDAC palettes are bypassed. (Direct colour has
* palettes, true colour does not.)
*/
if (var->bits_per_pixel == 8)
cfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
else if (hw.ramdac & RAMDAC_BYPASS)
cfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
else
cfb->fb.fix.visual = FB_VISUAL_DIRECTCOLOR;
cyber2000fb_set_timing(cfb, &hw);
cyber2000fb_update_start(cfb, var);
return 0;
}
/*
* Pan or Wrap the Display
*/
static int
cyber2000fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
if (cyber2000fb_update_start(cfb, var))
return -EINVAL;
cfb->fb.var.xoffset = var->xoffset;
cfb->fb.var.yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP) {
cfb->fb.var.vmode |= FB_VMODE_YWRAP;
} else {
cfb->fb.var.vmode &= ~FB_VMODE_YWRAP;
}
return 0;
}
/*
* (Un)Blank the display.
*
* Blank the screen if blank_mode != 0, else unblank. If
* blank == NULL then the caller blanks by setting the CLUT
* (Color Look Up Table) to all black. Return 0 if blanking
* succeeded, != 0 if un-/blanking failed due to e.g. a
* video mode which doesn't support it. Implements VESA
* suspend and powerdown modes on hardware that supports
* disabling hsync/vsync:
* blank_mode == 2: suspend vsync
* blank_mode == 3: suspend hsync
* blank_mode == 4: powerdown
*
* wms...Enable VESA DMPS compatible powerdown mode
* run "setterm -powersave powerdown" to take advantage
*/
static int cyber2000fb_blank(int blank, struct fb_info *info)
{
struct cfb_info *cfb = container_of(info, struct cfb_info, fb);
unsigned int sync = 0;
int i;
switch (blank) {
case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_0;
break;
case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
sync = EXT_SYNC_CTL_VS_NORMAL | EXT_SYNC_CTL_HS_0;
break;
case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
sync = EXT_SYNC_CTL_VS_0 | EXT_SYNC_CTL_HS_NORMAL;
break;
case FB_BLANK_NORMAL: /* soft blank */
default: /* unblank */
break;
}
cyber2000_grphw(EXT_SYNC_CTL, sync, cfb);
if (blank <= 1) {
/* turn on ramdacs */
cfb->ramdac_powerdown &= ~(RAMDAC_DACPWRDN | RAMDAC_BYPASS |
RAMDAC_RAMPWRDN);
cyber2000fb_write_ramdac_ctrl(cfb);
}
/*
* Soft blank/unblank the display.
*/
if (blank) { /* soft blank */
for (i = 0; i < NR_PALETTE; i++) {
cyber2000fb_writeb(i, 0x3c8, cfb);
cyber2000fb_writeb(0, 0x3c9, cfb);
cyber2000fb_writeb(0, 0x3c9, cfb);
cyber2000fb_writeb(0, 0x3c9, cfb);
}
} else { /* unblank */
for (i = 0; i < NR_PALETTE; i++) {
cyber2000fb_writeb(i, 0x3c8, cfb);
cyber2000fb_writeb(cfb->palette[i].red, 0x3c9, cfb);
cyber2000fb_writeb(cfb->palette[i].green, 0x3c9, cfb);
cyber2000fb_writeb(cfb->palette[i].blue, 0x3c9, cfb);
}
}
if (blank >= 2) {
/* turn off ramdacs */
cfb->ramdac_powerdown |= RAMDAC_DACPWRDN | RAMDAC_BYPASS |
RAMDAC_RAMPWRDN;
cyber2000fb_write_ramdac_ctrl(cfb);
}
return 0;
}
static const struct fb_ops cyber2000fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = cyber2000fb_check_var,
.fb_set_par = cyber2000fb_set_par,
.fb_setcolreg = cyber2000fb_setcolreg,
.fb_blank = cyber2000fb_blank,
.fb_pan_display = cyber2000fb_pan_display,
.fb_fillrect = cyber2000fb_fillrect,
.fb_copyarea = cyber2000fb_copyarea,
.fb_imageblit = cyber2000fb_imageblit,
.fb_sync = cyber2000fb_sync,
};
/*
* This is the only "static" reference to the internal data structures
* of this driver. It is here solely at the moment to support the other
* CyberPro modules external to this driver.
*/
static struct cfb_info *int_cfb_info;
/*
* Enable access to the extended registers
*/
void cyber2000fb_enable_extregs(struct cfb_info *cfb)
{
cfb->func_use_count += 1;
if (cfb->func_use_count == 1) {
int old;
old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
old |= EXT_FUNC_CTL_EXTREGENBL;
cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
}
}
EXPORT_SYMBOL(cyber2000fb_enable_extregs);
/*
* Disable access to the extended registers
*/
void cyber2000fb_disable_extregs(struct cfb_info *cfb)
{
if (cfb->func_use_count == 1) {
int old;
old = cyber2000_grphr(EXT_FUNC_CTL, cfb);
old &= ~EXT_FUNC_CTL_EXTREGENBL;
cyber2000_grphw(EXT_FUNC_CTL, old, cfb);
}
if (cfb->func_use_count == 0)
printk(KERN_ERR "disable_extregs: count = 0\n");
else
cfb->func_use_count -= 1;
}
EXPORT_SYMBOL(cyber2000fb_disable_extregs);
/*
* Attach a capture/tv driver to the core CyberX0X0 driver.
*/
int cyber2000fb_attach(struct cyberpro_info *info, int idx)
{
if (int_cfb_info != NULL) {
info->dev = int_cfb_info->fb.device;
#ifdef CONFIG_FB_CYBER2000_I2C
info->i2c = &int_cfb_info->i2c_adapter;
#else
info->i2c = NULL;
#endif
info->regs = int_cfb_info->regs;
info->irq = int_cfb_info->irq;
info->fb = int_cfb_info->fb.screen_base;
info->fb_size = int_cfb_info->fb.fix.smem_len;
info->info = int_cfb_info;
strscpy(info->dev_name, int_cfb_info->fb.fix.id,
sizeof(info->dev_name));
}
return int_cfb_info != NULL;
}
EXPORT_SYMBOL(cyber2000fb_attach);
/*
* Detach a capture/tv driver from the core CyberX0X0 driver.
*/
void cyber2000fb_detach(int idx)
{
}
EXPORT_SYMBOL(cyber2000fb_detach);
#ifdef CONFIG_FB_CYBER2000_DDC
#define DDC_REG 0xb0
#define DDC_SCL_OUT (1 << 0)
#define DDC_SDA_OUT (1 << 4)
#define DDC_SCL_IN (1 << 2)
#define DDC_SDA_IN (1 << 6)
static void cyber2000fb_enable_ddc(struct cfb_info *cfb)
__acquires(&cfb->reg_b0_lock)
{
spin_lock(&cfb->reg_b0_lock);
cyber2000fb_writew(0x1bf, 0x3ce, cfb);
}
static void cyber2000fb_disable_ddc(struct cfb_info *cfb)
__releases(&cfb->reg_b0_lock)
{
cyber2000fb_writew(0x0bf, 0x3ce, cfb);
spin_unlock(&cfb->reg_b0_lock);
}
static void cyber2000fb_ddc_setscl(void *data, int val)
{
struct cfb_info *cfb = data;
unsigned char reg;
cyber2000fb_enable_ddc(cfb);
reg = cyber2000_grphr(DDC_REG, cfb);
if (!val) /* bit is inverted */
reg |= DDC_SCL_OUT;
else
reg &= ~DDC_SCL_OUT;
cyber2000_grphw(DDC_REG, reg, cfb);
cyber2000fb_disable_ddc(cfb);
}
static void cyber2000fb_ddc_setsda(void *data, int val)
{
struct cfb_info *cfb = data;
unsigned char reg;
cyber2000fb_enable_ddc(cfb);
reg = cyber2000_grphr(DDC_REG, cfb);
if (!val) /* bit is inverted */
reg |= DDC_SDA_OUT;
else
reg &= ~DDC_SDA_OUT;
cyber2000_grphw(DDC_REG, reg, cfb);
cyber2000fb_disable_ddc(cfb);
}
static int cyber2000fb_ddc_getscl(void *data)
{
struct cfb_info *cfb = data;
int retval;
cyber2000fb_enable_ddc(cfb);
retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SCL_IN);
cyber2000fb_disable_ddc(cfb);
return retval;
}
static int cyber2000fb_ddc_getsda(void *data)
{
struct cfb_info *cfb = data;
int retval;
cyber2000fb_enable_ddc(cfb);
retval = !!(cyber2000_grphr(DDC_REG, cfb) & DDC_SDA_IN);
cyber2000fb_disable_ddc(cfb);
return retval;
}
static int cyber2000fb_setup_ddc_bus(struct cfb_info *cfb)
{
strscpy(cfb->ddc_adapter.name, cfb->fb.fix.id,
sizeof(cfb->ddc_adapter.name));
cfb->ddc_adapter.owner = THIS_MODULE;
cfb->ddc_adapter.class = I2C_CLASS_DDC;
cfb->ddc_adapter.algo_data = &cfb->ddc_algo;
cfb->ddc_adapter.dev.parent = cfb->fb.device;
cfb->ddc_algo.setsda = cyber2000fb_ddc_setsda;
cfb->ddc_algo.setscl = cyber2000fb_ddc_setscl;
cfb->ddc_algo.getsda = cyber2000fb_ddc_getsda;
cfb->ddc_algo.getscl = cyber2000fb_ddc_getscl;
cfb->ddc_algo.udelay = 10;
cfb->ddc_algo.timeout = 20;
cfb->ddc_algo.data = cfb;
i2c_set_adapdata(&cfb->ddc_adapter, cfb);
return i2c_bit_add_bus(&cfb->ddc_adapter);
}
#endif /* CONFIG_FB_CYBER2000_DDC */
#ifdef CONFIG_FB_CYBER2000_I2C
static void cyber2000fb_i2c_setsda(void *data, int state)
{
struct cfb_info *cfb = data;
unsigned int latch2;
spin_lock(&cfb->reg_b0_lock);
latch2 = cyber2000_grphr(EXT_LATCH2, cfb);
latch2 &= EXT_LATCH2_I2C_CLKEN;
if (state)
latch2 |= EXT_LATCH2_I2C_DATEN;
cyber2000_grphw(EXT_LATCH2, latch2, cfb);
spin_unlock(&cfb->reg_b0_lock);
}
static void cyber2000fb_i2c_setscl(void *data, int state)
{
struct cfb_info *cfb = data;
unsigned int latch2;
spin_lock(&cfb->reg_b0_lock);
latch2 = cyber2000_grphr(EXT_LATCH2, cfb);
latch2 &= EXT_LATCH2_I2C_DATEN;
if (state)
latch2 |= EXT_LATCH2_I2C_CLKEN;
cyber2000_grphw(EXT_LATCH2, latch2, cfb);
spin_unlock(&cfb->reg_b0_lock);
}
static int cyber2000fb_i2c_getsda(void *data)
{
struct cfb_info *cfb = data;
int ret;
spin_lock(&cfb->reg_b0_lock);
ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_DAT);
spin_unlock(&cfb->reg_b0_lock);
return ret;
}
static int cyber2000fb_i2c_getscl(void *data)
{
struct cfb_info *cfb = data;
int ret;
spin_lock(&cfb->reg_b0_lock);
ret = !!(cyber2000_grphr(EXT_LATCH2, cfb) & EXT_LATCH2_I2C_CLK);
spin_unlock(&cfb->reg_b0_lock);
return ret;
}
static int cyber2000fb_i2c_register(struct cfb_info *cfb)
{
strscpy(cfb->i2c_adapter.name, cfb->fb.fix.id,
sizeof(cfb->i2c_adapter.name));
cfb->i2c_adapter.owner = THIS_MODULE;
cfb->i2c_adapter.algo_data = &cfb->i2c_algo;
cfb->i2c_adapter.dev.parent = cfb->fb.device;
cfb->i2c_algo.setsda = cyber2000fb_i2c_setsda;
cfb->i2c_algo.setscl = cyber2000fb_i2c_setscl;
cfb->i2c_algo.getsda = cyber2000fb_i2c_getsda;
cfb->i2c_algo.getscl = cyber2000fb_i2c_getscl;
cfb->i2c_algo.udelay = 5;
cfb->i2c_algo.timeout = msecs_to_jiffies(100);
cfb->i2c_algo.data = cfb;
return i2c_bit_add_bus(&cfb->i2c_adapter);
}
static void cyber2000fb_i2c_unregister(struct cfb_info *cfb)
{
i2c_del_adapter(&cfb->i2c_adapter);
}
#else
#define cyber2000fb_i2c_register(cfb) (0)
#define cyber2000fb_i2c_unregister(cfb) do { } while (0)
#endif
/*
* These parameters give
* 640x480, hsync 31.5kHz, vsync 60Hz
*/
static const struct fb_videomode cyber2000fb_default_mode = {
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39722,
.left_margin = 56,
.right_margin = 16,
.upper_margin = 34,
.lower_margin = 9,
.hsync_len = 88,
.vsync_len = 2,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static char igs_regs[] = {
EXT_CRT_IRQ, 0,
EXT_CRT_TEST, 0,
EXT_SYNC_CTL, 0,
EXT_SEG_WRITE_PTR, 0,
EXT_SEG_READ_PTR, 0,
EXT_BIU_MISC, EXT_BIU_MISC_LIN_ENABLE |
EXT_BIU_MISC_COP_ENABLE |
EXT_BIU_MISC_COP_BFC,
EXT_FUNC_CTL, 0,
CURS_H_START, 0,
CURS_H_START + 1, 0,
CURS_H_PRESET, 0,
CURS_V_START, 0,
CURS_V_START + 1, 0,
CURS_V_PRESET, 0,
CURS_CTL, 0,
EXT_ATTRIB_CTL, EXT_ATTRIB_CTL_EXT,
EXT_OVERSCAN_RED, 0,
EXT_OVERSCAN_GREEN, 0,
EXT_OVERSCAN_BLUE, 0,
/* some of these are questionable when we have a BIOS */
EXT_MEM_CTL0, EXT_MEM_CTL0_7CLK |
EXT_MEM_CTL0_RAS_1 |
EXT_MEM_CTL0_MULTCAS,
EXT_HIDDEN_CTL1, 0x30,
EXT_FIFO_CTL, 0x0b,
EXT_FIFO_CTL + 1, 0x17,
0x76, 0x00,
EXT_HIDDEN_CTL4, 0xc8
};
/*
* Initialise the CyberPro hardware. On the CyberPro5XXXX,
* ensure that we're using the correct PLL (5XXX's may be
* programmed to use an additional set of PLLs.)
*/
static void cyberpro_init_hw(struct cfb_info *cfb)
{
int i;
for (i = 0; i < sizeof(igs_regs); i += 2)
cyber2000_grphw(igs_regs[i], igs_regs[i + 1], cfb);
if (cfb->id == ID_CYBERPRO_5000) {
unsigned char val;
cyber2000fb_writeb(0xba, 0x3ce, cfb);
val = cyber2000fb_readb(0x3cf, cfb) & 0x80;
cyber2000fb_writeb(val, 0x3cf, cfb);
}
}
static struct cfb_info *cyberpro_alloc_fb_info(unsigned int id, char *name)
{
struct cfb_info *cfb;
cfb = kzalloc(sizeof(struct cfb_info), GFP_KERNEL);
if (!cfb)
return NULL;
cfb->id = id;
if (id == ID_CYBERPRO_5000)
cfb->ref_ps = 40690; /* 24.576 MHz */
else
cfb->ref_ps = 69842; /* 14.31818 MHz (69841?) */
cfb->divisors[0] = 1;
cfb->divisors[1] = 2;
cfb->divisors[2] = 4;
if (id == ID_CYBERPRO_2000)
cfb->divisors[3] = 8;
else
cfb->divisors[3] = 6;
strcpy(cfb->fb.fix.id, name);
cfb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
cfb->fb.fix.type_aux = 0;
cfb->fb.fix.xpanstep = 0;
cfb->fb.fix.ypanstep = 1;
cfb->fb.fix.ywrapstep = 0;
switch (id) {
case ID_IGA_1682:
cfb->fb.fix.accel = 0;
break;
case ID_CYBERPRO_2000:
cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2000;
break;
case ID_CYBERPRO_2010:
cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER2010;
break;
case ID_CYBERPRO_5000:
cfb->fb.fix.accel = FB_ACCEL_IGS_CYBER5000;
break;
}
cfb->fb.var.nonstd = 0;
cfb->fb.var.activate = FB_ACTIVATE_NOW;
cfb->fb.var.height = -1;
cfb->fb.var.width = -1;
cfb->fb.var.accel_flags = FB_ACCELF_TEXT;
cfb->fb.fbops = &cyber2000fb_ops;
cfb->fb.flags = FBINFO_HWACCEL_YPAN;
cfb->fb.pseudo_palette = cfb->pseudo_palette;
spin_lock_init(&cfb->reg_b0_lock);
fb_alloc_cmap(&cfb->fb.cmap, NR_PALETTE, 0);
return cfb;
}
static void cyberpro_free_fb_info(struct cfb_info *cfb)
{
if (cfb) {
/*
* Free the colourmap
*/
fb_alloc_cmap(&cfb->fb.cmap, 0, 0);
kfree(cfb);
}
}
/*
* Parse Cyber2000fb options. Usage:
* video=cyber2000:font:fontname
*/
#ifndef MODULE
static int cyber2000fb_setup(char *options)
{
char *opt;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
if (strncmp(opt, "font:", 5) == 0) {
static char default_font_storage[40];
strscpy(default_font_storage, opt + 5,
sizeof(default_font_storage));
default_font = default_font_storage;
continue;
}
printk(KERN_ERR "CyberPro20x0: unknown parameter: %s\n", opt);
}
return 0;
}
#endif /* MODULE */
/*
* The CyberPro chips can be placed on many different bus types.
* This probe function is common to all bus types. The bus-specific
* probe function is expected to have:
* - enabled access to the linear memory region
* - memory mapped access to the registers
* - initialised mem_ctl1 and mem_ctl2 appropriately.
*/
static int cyberpro_common_probe(struct cfb_info *cfb)
{
u_long smem_size;
u_int h_sync, v_sync;
int err;
cyberpro_init_hw(cfb);
/*
* Get the video RAM size and width from the VGA register.
* This should have been already initialised by the BIOS,
* but if it's garbage, claim default 1MB VRAM (woody)
*/
cfb->mem_ctl1 = cyber2000_grphr(EXT_MEM_CTL1, cfb);
cfb->mem_ctl2 = cyber2000_grphr(EXT_MEM_CTL2, cfb);
/*
* Determine the size of the memory.
*/
switch (cfb->mem_ctl2 & MEM_CTL2_SIZE_MASK) {
case MEM_CTL2_SIZE_4MB:
smem_size = 0x00400000;
break;
case MEM_CTL2_SIZE_2MB:
smem_size = 0x00200000;
break;
case MEM_CTL2_SIZE_1MB:
smem_size = 0x00100000;
break;
default:
smem_size = 0x00100000;
break;
}
cfb->fb.fix.smem_len = smem_size;
cfb->fb.fix.mmio_len = MMIO_SIZE;
cfb->fb.screen_base = cfb->region;
#ifdef CONFIG_FB_CYBER2000_DDC
if (cyber2000fb_setup_ddc_bus(cfb) == 0)
cfb->ddc_registered = true;
#endif
err = -EINVAL;
if (!fb_find_mode(&cfb->fb.var, &cfb->fb, NULL, NULL, 0,
&cyber2000fb_default_mode, 8)) {
printk(KERN_ERR "%s: no valid mode found\n", cfb->fb.fix.id);
goto failed;
}
cfb->fb.var.yres_virtual = cfb->fb.fix.smem_len * 8 /
(cfb->fb.var.bits_per_pixel * cfb->fb.var.xres_virtual);
if (cfb->fb.var.yres_virtual < cfb->fb.var.yres)
cfb->fb.var.yres_virtual = cfb->fb.var.yres;
/* fb_set_var(&cfb->fb.var, -1, &cfb->fb); */
/*
* Calculate the hsync and vsync frequencies. Note that
* we split the 1e12 constant up so that we can preserve
* the precision and fit the results into 32-bit registers.
* (1953125000 * 512 = 1e12)
*/
h_sync = 1953125000 / cfb->fb.var.pixclock;
h_sync = h_sync * 512 / (cfb->fb.var.xres + cfb->fb.var.left_margin +
cfb->fb.var.right_margin + cfb->fb.var.hsync_len);
v_sync = h_sync / (cfb->fb.var.yres + cfb->fb.var.upper_margin +
cfb->fb.var.lower_margin + cfb->fb.var.vsync_len);
printk(KERN_INFO "%s: %dKiB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
cfb->fb.fix.id, cfb->fb.fix.smem_len >> 10,
cfb->fb.var.xres, cfb->fb.var.yres,
h_sync / 1000, h_sync % 1000, v_sync);
err = cyber2000fb_i2c_register(cfb);
if (err)
goto failed;
err = register_framebuffer(&cfb->fb);
if (err)
cyber2000fb_i2c_unregister(cfb);
failed:
#ifdef CONFIG_FB_CYBER2000_DDC
if (err && cfb->ddc_registered)
i2c_del_adapter(&cfb->ddc_adapter);
#endif
return err;
}
static void cyberpro_common_remove(struct cfb_info *cfb)
{
unregister_framebuffer(&cfb->fb);
#ifdef CONFIG_FB_CYBER2000_DDC
if (cfb->ddc_registered)
i2c_del_adapter(&cfb->ddc_adapter);
#endif
cyber2000fb_i2c_unregister(cfb);
}
static void cyberpro_common_resume(struct cfb_info *cfb)
{
cyberpro_init_hw(cfb);
/*
* Reprogram the MEM_CTL1 and MEM_CTL2 registers
*/
cyber2000_grphw(EXT_MEM_CTL1, cfb->mem_ctl1, cfb);
cyber2000_grphw(EXT_MEM_CTL2, cfb->mem_ctl2, cfb);
/*
* Restore the old video mode and the palette.
* We also need to tell fbcon to redraw the console.
*/
cyber2000fb_set_par(&cfb->fb);
}
/*
* We need to wake up the CyberPro, and make sure its in linear memory
* mode. Unfortunately, this is specific to the platform and card that
* we are running on.
*
* On x86 and ARM, should we be initialising the CyberPro first via the
* IO registers, and then the MMIO registers to catch all cases? Can we
* end up in the situation where the chip is in MMIO mode, but not awake
* on an x86 system?
*/
static int cyberpro_pci_enable_mmio(struct cfb_info *cfb)
{
unsigned char val;
#if defined(__sparc_v9__)
#error "You lose, consult DaveM."
#elif defined(__sparc__)
/*
* SPARC does not have an "outb" instruction, so we generate
* I/O cycles storing into a reserved memory space at
* physical address 0x3000000
*/
unsigned char __iomem *iop;
iop = ioremap(0x3000000, 0x5000);
if (iop == NULL) {
printk(KERN_ERR "iga5000: cannot map I/O\n");
return -ENOMEM;
}
writeb(0x18, iop + 0x46e8);
writeb(0x01, iop + 0x102);
writeb(0x08, iop + 0x46e8);
writeb(EXT_BIU_MISC, iop + 0x3ce);
writeb(EXT_BIU_MISC_LIN_ENABLE, iop + 0x3cf);
iounmap(iop);
#else
/*
* Most other machine types are "normal", so
* we use the standard IO-based wakeup.
*/
outb(0x18, 0x46e8);
outb(0x01, 0x102);
outb(0x08, 0x46e8);
outb(EXT_BIU_MISC, 0x3ce);
outb(EXT_BIU_MISC_LIN_ENABLE, 0x3cf);
#endif
/*
* Allow the CyberPro to accept PCI burst accesses
*/
if (cfb->id == ID_CYBERPRO_2010) {
printk(KERN_INFO "%s: NOT enabling PCI bursts\n",
cfb->fb.fix.id);
} else {
val = cyber2000_grphr(EXT_BUS_CTL, cfb);
if (!(val & EXT_BUS_CTL_PCIBURST_WRITE)) {
printk(KERN_INFO "%s: enabling PCI bursts\n",
cfb->fb.fix.id);
val |= EXT_BUS_CTL_PCIBURST_WRITE;
if (cfb->id == ID_CYBERPRO_5000)
val |= EXT_BUS_CTL_PCIBURST_READ;
cyber2000_grphw(EXT_BUS_CTL, val, cfb);
}
}
return 0;
}
static int cyberpro_pci_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
struct cfb_info *cfb;
char name[16];
int err;
sprintf(name, "CyberPro%4X", id->device);
err = aperture_remove_conflicting_pci_devices(dev, name);
if (err)
return err;
err = pci_enable_device(dev);
if (err)
return err;
err = -ENOMEM;
cfb = cyberpro_alloc_fb_info(id->driver_data, name);
if (!cfb)
goto failed_release;
err = pci_request_regions(dev, cfb->fb.fix.id);
if (err)
goto failed_regions;
cfb->irq = dev->irq;
cfb->region = pci_ioremap_bar(dev, 0);
if (!cfb->region) {
err = -ENOMEM;
goto failed_ioremap;
}
cfb->regs = cfb->region + MMIO_OFFSET;
cfb->fb.device = &dev->dev;
cfb->fb.fix.mmio_start = pci_resource_start(dev, 0) + MMIO_OFFSET;
cfb->fb.fix.smem_start = pci_resource_start(dev, 0);
/*
* Bring up the hardware. This is expected to enable access
* to the linear memory region, and allow access to the memory
* mapped registers. Also, mem_ctl1 and mem_ctl2 must be
* initialised.
*/
err = cyberpro_pci_enable_mmio(cfb);
if (err)
goto failed;
/*
* Use MCLK from BIOS. FIXME: what about hotplug?
*/
cfb->mclk_mult = cyber2000_grphr(EXT_MCLK_MULT, cfb);
cfb->mclk_div = cyber2000_grphr(EXT_MCLK_DIV, cfb);
#ifdef __arm__
/*
* MCLK on the NetWinder and the Shark is fixed at 75MHz
*/
if (machine_is_netwinder()) {
cfb->mclk_mult = 0xdb;
cfb->mclk_div = 0x54;
}
#endif
err = cyberpro_common_probe(cfb);
if (err)
goto failed;
/*
* Our driver data
*/
pci_set_drvdata(dev, cfb);
if (int_cfb_info == NULL)
int_cfb_info = cfb;
return 0;
failed:
iounmap(cfb->region);
failed_ioremap:
pci_release_regions(dev);
failed_regions:
cyberpro_free_fb_info(cfb);
failed_release:
pci_disable_device(dev);
return err;
}
static void cyberpro_pci_remove(struct pci_dev *dev)
{
struct cfb_info *cfb = pci_get_drvdata(dev);
if (cfb) {
cyberpro_common_remove(cfb);
iounmap(cfb->region);
cyberpro_free_fb_info(cfb);
if (cfb == int_cfb_info)
int_cfb_info = NULL;
pci_release_regions(dev);
pci_disable_device(dev);
}
}
static int __maybe_unused cyberpro_pci_suspend(struct device *dev)
{
return 0;
}
/*
* Re-initialise the CyberPro hardware
*/
static int __maybe_unused cyberpro_pci_resume(struct device *dev)
{
struct cfb_info *cfb = dev_get_drvdata(dev);
if (cfb) {
cyberpro_pci_enable_mmio(cfb);
cyberpro_common_resume(cfb);
}
return 0;
}
static struct pci_device_id cyberpro_pci_table[] = {
/* Not yet
* { PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_1682,
* PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_IGA_1682 },
*/
{ PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2000,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2000 },
{ PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_2010,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_2010 },
{ PCI_VENDOR_ID_INTERG, PCI_DEVICE_ID_INTERG_5000,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, ID_CYBERPRO_5000 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, cyberpro_pci_table);
static SIMPLE_DEV_PM_OPS(cyberpro_pci_pm_ops,
cyberpro_pci_suspend,
cyberpro_pci_resume);
static struct pci_driver cyberpro_driver = {
.name = "CyberPro",
.probe = cyberpro_pci_probe,
.remove = cyberpro_pci_remove,
.driver.pm = &cyberpro_pci_pm_ops,
.id_table = cyberpro_pci_table
};
/*
* I don't think we can use the "module_init" stuff here because
* the fbcon stuff may not be initialised yet. Hence the #ifdef
* around module_init.
*
* Tony: "module_init" is now required
*/
static int __init cyber2000fb_init(void)
{
int ret = -1, err;
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("CyberPro"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("cyber2000fb", &option))
return -ENODEV;
cyber2000fb_setup(option);
#endif
err = pci_register_driver(&cyberpro_driver);
if (!err)
ret = 0;
return ret ? err : 0;
}
module_init(cyber2000fb_init);
static void __exit cyberpro_exit(void)
{
pci_unregister_driver(&cyberpro_driver);
}
module_exit(cyberpro_exit);
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("CyberPro 2000, 2010 and 5000 framebuffer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/cyber2000fb.c |
/*
* controlfb.c -- frame buffer device for the PowerMac 'control' display
*
* Created 12 July 1998 by Dan Jacobowitz <[email protected]>
* Copyright (C) 1998 Dan Jacobowitz
* Copyright (C) 2001 Takashi Oe
*
* Mmap code by Michel Lanners <[email protected]>
*
* Frame buffer structure from:
* drivers/video/chipsfb.c -- frame buffer device for
* Chips & Technologies 65550 chip.
*
* Copyright (C) 1998 Paul Mackerras
*
* This file is derived from the Powermac "chips" driver:
* Copyright (C) 1997 Fabio Riccardi.
* And from the frame buffer device for Open Firmware-initialized devices:
* Copyright (C) 1997 Geert Uytterhoeven.
*
* Hardware information from:
* control.c: Console support for PowerMac "control" display adaptor.
* Copyright (C) 1996 Paul Mackerras
*
* Updated to 2.5 framebuffer API by Ben Herrenschmidt
* <[email protected]>, Paul Mackerras <[email protected]>,
* and James Simmons <[email protected]>.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/nvram.h>
#include <linux/adb.h>
#include <linux/cuda.h>
#ifdef CONFIG_BOOTX_TEXT
#include <asm/btext.h>
#endif
#include "macmodes.h"
#include "controlfb.h"
#if !defined(CONFIG_PPC_PMAC) || !defined(CONFIG_PPC32)
#define invalid_vram_cache(addr)
#undef in_8
#undef out_8
#undef in_le32
#undef out_le32
#define in_8(addr) 0
#define out_8(addr, val) (void)(val)
#define in_le32(addr) 0
#define out_le32(addr, val) (void)(val)
#ifndef pgprot_cached_wthru
#define pgprot_cached_wthru(prot) (prot)
#endif
#else
static void invalid_vram_cache(void __force *addr)
{
eieio();
dcbf(addr);
mb();
eieio();
dcbf(addr);
mb();
}
#endif
struct fb_par_control {
int vmode, cmode;
int xres, yres;
int vxres, vyres;
int xoffset, yoffset;
int pitch;
struct control_regvals regvals;
unsigned long sync;
unsigned char ctrl;
};
#define DIRTY(z) ((x)->z != (y)->z)
#define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z)))
static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y)
{
int i, results;
results = 1;
for (i = 0; i < 3; i++)
results &= !DIRTY(regvals.clock_params[i]);
if (!results)
return 0;
for (i = 0; i < 16; i++)
results &= !DIRTY(regvals.regs[i]);
if (!results)
return 0;
return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres)
&& !DIRTY(vxres) && !DIRTY(vyres));
}
struct fb_info_control {
struct fb_info info;
struct fb_par_control par;
u32 pseudo_palette[16];
struct cmap_regs __iomem *cmap_regs;
unsigned long cmap_regs_phys;
struct control_regs __iomem *control_regs;
unsigned long control_regs_phys;
unsigned long control_regs_size;
__u8 __iomem *frame_buffer;
unsigned long frame_buffer_phys;
unsigned long fb_orig_base;
unsigned long fb_orig_size;
int control_use_bank2;
unsigned long total_vram;
unsigned char vram_attr;
};
/* control register access macro */
#define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
/************************** Internal variables *******************************/
static struct fb_info_control *control_fb;
static int default_vmode __initdata = VMODE_NVRAM;
static int default_cmode __initdata = CMODE_NVRAM;
static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct fb_info_control *p =
container_of(info, struct fb_info_control, info);
__u8 r, g, b;
if (regno > 255)
return 1;
r = red >> 8;
g = green >> 8;
b = blue >> 8;
out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */
out_8(&p->cmap_regs->lut, r); /* send one color channel at */
out_8(&p->cmap_regs->lut, g); /* a time... */
out_8(&p->cmap_regs->lut, b);
if (regno < 16) {
int i;
switch (p->par.cmode) {
case CMODE_16:
p->pseudo_palette[regno] =
(regno << 10) | (regno << 5) | regno;
break;
case CMODE_32:
i = (regno << 8) | regno;
p->pseudo_palette[regno] = (i << 16) | i;
break;
}
}
return 0;
}
/******************** End of controlfb_ops implementation ******************/
static void set_control_clock(unsigned char *params)
{
#ifdef CONFIG_ADB_CUDA
struct adb_request req;
int i;
for (i = 0; i < 3; ++i) {
cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
0x50, i + 1, params[i]);
while (!req.complete)
cuda_poll();
}
#endif
}
/*
* Set screen start address according to var offset values
*/
static inline void set_screen_start(int xoffset, int yoffset,
struct fb_info_control *p)
{
struct fb_par_control *par = &p->par;
par->xoffset = xoffset;
par->yoffset = yoffset;
out_le32(CNTRL_REG(p,start_addr),
par->yoffset * par->pitch + (par->xoffset << par->cmode));
}
#define RADACAL_WRITE(a,d) \
out_8(&p->cmap_regs->addr, (a)); \
out_8(&p->cmap_regs->dat, (d))
/* Now how about actually saying, Make it so! */
/* Some things in here probably don't need to be done each time. */
static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par)
{
struct control_regvals *r;
volatile struct preg __iomem *rp;
int i, cmode;
if (PAR_EQUAL(&p->par, par)) {
/*
* check if only xoffset or yoffset differs.
* this prevents flickers in typical VT switch case.
*/
if (p->par.xoffset != par->xoffset ||
p->par.yoffset != par->yoffset)
set_screen_start(par->xoffset, par->yoffset, p);
return;
}
p->par = *par;
cmode = p->par.cmode;
r = &par->regvals;
/* Turn off display */
out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl);
set_control_clock(r->clock_params);
RADACAL_WRITE(0x20, r->radacal_ctrl);
RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1);
RADACAL_WRITE(0x10, 0);
RADACAL_WRITE(0x11, 0);
rp = &p->control_regs->vswin;
for (i = 0; i < 16; ++i, ++rp)
out_le32(&rp->r, r->regs[i]);
out_le32(CNTRL_REG(p,pitch), par->pitch);
out_le32(CNTRL_REG(p,mode), r->mode);
out_le32(CNTRL_REG(p,vram_attr), p->vram_attr);
out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch
+ (par->xoffset << cmode));
out_le32(CNTRL_REG(p,rfrcnt), 0x1e5);
out_le32(CNTRL_REG(p,intr_ena), 0);
/* Turn on display */
out_le32(CNTRL_REG(p,ctrl), par->ctrl);
#ifdef CONFIG_BOOTX_TEXT
btext_update_display(p->frame_buffer_phys + CTRLFB_OFF,
p->par.xres, p->par.yres,
(cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8),
p->par.pitch);
#endif /* CONFIG_BOOTX_TEXT */
}
/* Work out which banks of VRAM we have installed. */
/* danj: I guess the card just ignores writes to nonexistant VRAM... */
static void __init find_vram_size(struct fb_info_control *p)
{
int bank1, bank2;
/*
* Set VRAM in 2MB (bank 1) mode
* VRAM Bank 2 will be accessible through offset 0x600000 if present
* and VRAM Bank 1 will not respond at that offset even if present
*/
out_le32(CNTRL_REG(p,vram_attr), 0x31);
out_8(&p->frame_buffer[0x600000], 0xb3);
out_8(&p->frame_buffer[0x600001], 0x71);
invalid_vram_cache(&p->frame_buffer[0x600000]);
bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3)
&& (in_8(&p->frame_buffer[0x600001]) == 0x71);
/*
* Set VRAM in 2MB (bank 2) mode
* VRAM Bank 1 will be accessible through offset 0x000000 if present
* and VRAM Bank 2 will not respond at that offset even if present
*/
out_le32(CNTRL_REG(p,vram_attr), 0x39);
out_8(&p->frame_buffer[0], 0x5a);
out_8(&p->frame_buffer[1], 0xc7);
invalid_vram_cache(&p->frame_buffer[0]);
bank1 = (in_8(&p->frame_buffer[0]) == 0x5a)
&& (in_8(&p->frame_buffer[1]) == 0xc7);
if (bank2) {
if (!bank1) {
/*
* vram bank 2 only
*/
p->control_use_bank2 = 1;
p->vram_attr = 0x39;
p->frame_buffer += 0x600000;
p->frame_buffer_phys += 0x600000;
} else {
/*
* 4 MB vram
*/
p->vram_attr = 0x51;
}
} else {
/*
* vram bank 1 only
*/
p->vram_attr = 0x31;
}
p->total_vram = (bank1 + bank2) * 0x200000;
printk(KERN_INFO "controlfb: VRAM Total = %dMB "
"(%dMB @ bank 1, %dMB @ bank 2)\n",
(bank1 + bank2) << 1, bank1 << 1, bank2 << 1);
}
/*
* Get the monitor sense value.
* Note that this can be called before calibrate_delay,
* so we can't use udelay.
*/
static int read_control_sense(struct fb_info_control *p)
{
int sense;
out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */
__delay(200);
out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
__delay(2000);
sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
/* drive each sense line low in turn and collect the other 2 */
out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */
__delay(2000);
sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */
__delay(2000);
sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
| ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */
__delay(2000);
sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
return sense;
}
/********************** Various translation functions **********************/
#define CONTROL_PIXCLOCK_BASE 256016
#define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */
/*
* calculate the clock parameters to be sent to CUDA according to given
* pixclock in pico second.
*/
static int calc_clock_params(unsigned long clk, unsigned char *param)
{
unsigned long p0, p1, p2, k, l, m, n, min;
if (clk > (CONTROL_PIXCLOCK_BASE << 3))
return 1;
p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2;
l = clk << p2;
p0 = 0;
p1 = 0;
for (k = 1, min = l; k < 32; k++) {
unsigned long rem;
m = CONTROL_PIXCLOCK_BASE * k;
n = m / l;
rem = m % l;
if (n && (n < 128) && rem < min) {
p0 = k;
p1 = n;
min = rem;
}
}
if (!p0 || !p1)
return 1;
param[0] = p0;
param[1] = p1;
param[2] = p2;
return 0;
}
/*
* This routine takes a user-supplied var, and picks the best vmode/cmode
* from it.
*/
static int control_var_to_par(struct fb_var_screeninfo *var,
struct fb_par_control *par, const struct fb_info *fb_info)
{
int cmode, piped_diff, hstep;
unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln,
hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin;
unsigned long pixclock;
struct fb_info_control *p =
container_of(fb_info, struct fb_info_control, info);
struct control_regvals *r = &par->regvals;
switch (var->bits_per_pixel) {
case 8:
par->cmode = CMODE_8;
if (p->total_vram > 0x200000) {
r->mode = 3;
r->radacal_ctrl = 0x20;
piped_diff = 13;
} else {
r->mode = 2;
r->radacal_ctrl = 0x10;
piped_diff = 9;
}
break;
case 15:
case 16:
par->cmode = CMODE_16;
if (p->total_vram > 0x200000) {
r->mode = 2;
r->radacal_ctrl = 0x24;
piped_diff = 5;
} else {
r->mode = 1;
r->radacal_ctrl = 0x14;
piped_diff = 3;
}
break;
case 32:
par->cmode = CMODE_32;
if (p->total_vram > 0x200000) {
r->mode = 1;
r->radacal_ctrl = 0x28;
} else {
r->mode = 0;
r->radacal_ctrl = 0x18;
}
piped_diff = 1;
break;
default:
return -EINVAL;
}
/*
* adjust xres and vxres so that the corresponding memory widths are
* 32-byte aligned
*/
hstep = 31 >> par->cmode;
par->xres = (var->xres + hstep) & ~hstep;
par->vxres = (var->xres_virtual + hstep) & ~hstep;
par->xoffset = (var->xoffset + hstep) & ~hstep;
if (par->vxres < par->xres)
par->vxres = par->xres;
par->pitch = par->vxres << par->cmode;
par->yres = var->yres;
par->vyres = var->yres_virtual;
par->yoffset = var->yoffset;
if (par->vyres < par->yres)
par->vyres = par->yres;
par->sync = var->sync;
if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram)
return -EINVAL;
if (par->xoffset + par->xres > par->vxres)
par->xoffset = par->vxres - par->xres;
if (par->yoffset + par->yres > par->vyres)
par->yoffset = par->vyres - par->yres;
pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN:
var->pixclock;
if (calc_clock_params(pixclock, r->clock_params))
return -EINVAL;
hperiod = ((var->left_margin + par->xres + var->right_margin
+ var->hsync_len) >> 1) - 2;
hssync = hperiod + 1;
hsblank = hssync - (var->right_margin >> 1);
hesync = (var->hsync_len >> 1) - 1;
heblank = (var->left_margin >> 1) + hesync;
piped = heblank - piped_diff;
heq = var->hsync_len >> 2;
hlfln = (hperiod+2) >> 1;
hserr = hssync-hesync;
vperiod = (var->vsync_len + var->lower_margin + par->yres
+ var->upper_margin) << 1;
vssync = vperiod - 2;
vesync = (var->vsync_len << 1) - vperiod + vssync;
veblank = (var->upper_margin << 1) + vesync;
vsblank = vssync - (var->lower_margin << 1);
vswin = (vsblank+vssync) >> 1;
vewin = (vesync+veblank) >> 1;
r->regs[0] = vswin;
r->regs[1] = vsblank;
r->regs[2] = veblank;
r->regs[3] = vewin;
r->regs[4] = vesync;
r->regs[5] = vssync;
r->regs[6] = vperiod;
r->regs[7] = piped;
r->regs[8] = hperiod;
r->regs[9] = hsblank;
r->regs[10] = heblank;
r->regs[11] = hesync;
r->regs[12] = hssync;
r->regs[13] = heq;
r->regs[14] = hlfln;
r->regs[15] = hserr;
if (par->xres >= 1280 && par->cmode >= CMODE_16)
par->ctrl = 0x7f;
else
par->ctrl = 0x3b;
if (mac_var_to_vmode(var, &par->vmode, &cmode))
par->vmode = 0;
return 0;
}
/*
* Convert hardware data in par to an fb_var_screeninfo
*/
static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var)
{
struct control_regints *rv;
rv = (struct control_regints *) par->regvals.regs;
memset(var, 0, sizeof(*var));
var->xres = par->xres;
var->yres = par->yres;
var->xres_virtual = par->vxres;
var->yres_virtual = par->vyres;
var->xoffset = par->xoffset;
var->yoffset = par->yoffset;
switch(par->cmode) {
default:
case CMODE_8:
var->bits_per_pixel = 8;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
case CMODE_16: /* RGB 555 */
var->bits_per_pixel = 16;
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.length = 5;
break;
case CMODE_32: /* RGB 888 */
var->bits_per_pixel = 32;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
}
var->height = -1;
var->width = -1;
var->vmode = FB_VMODE_NONINTERLACED;
var->left_margin = (rv->heblank - rv->hesync) << 1;
var->right_margin = (rv->hssync - rv->hsblank) << 1;
var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1;
var->upper_margin = (rv->veblank - rv->vesync) >> 1;
var->lower_margin = (rv->vssync - rv->vsblank) >> 1;
var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1;
var->sync = par->sync;
/*
* 10^12 * clock_params[0] / (3906400 * clock_params[1]
* * 2^clock_params[2])
* (10^12 * clock_params[0] / (3906400 * clock_params[1]))
* >> clock_params[2]
*/
/* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */
var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0];
var->pixclock /= par->regvals.clock_params[1];
var->pixclock >>= par->regvals.clock_params[2];
}
/******************** The functions for controlfb_ops ********************/
/*
* Checks a var structure
*/
static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
{
struct fb_par_control par;
int err;
err = control_var_to_par(var, &par, info);
if (err)
return err;
control_par_to_var(&par, var);
return 0;
}
/*
* Applies current var to display
*/
static int controlfb_set_par (struct fb_info *info)
{
struct fb_info_control *p =
container_of(info, struct fb_info_control, info);
struct fb_par_control par;
int err;
if((err = control_var_to_par(&info->var, &par, info))) {
printk (KERN_ERR "controlfb_set_par: error calling"
" control_var_to_par: %d.\n", err);
return err;
}
control_set_hardware(p, &par);
info->fix.visual = (p->par.cmode == CMODE_8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
info->fix.line_length = p->par.pitch;
info->fix.xpanstep = 32 >> p->par.cmode;
info->fix.ypanstep = 1;
return 0;
}
static int controlfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
unsigned int xoffset, hstep;
struct fb_info_control *p =
container_of(info, struct fb_info_control, info);
struct fb_par_control *par = &p->par;
/*
* make sure start addr will be 32-byte aligned
*/
hstep = 0x1f >> par->cmode;
xoffset = (var->xoffset + hstep) & ~hstep;
if (xoffset+par->xres > par->vxres ||
var->yoffset+par->yres > par->vyres)
return -EINVAL;
set_screen_start(xoffset, var->yoffset, p);
return 0;
}
static int controlfb_blank(int blank_mode, struct fb_info *info)
{
struct fb_info_control __maybe_unused *p =
container_of(info, struct fb_info_control, info);
unsigned ctrl;
ctrl = in_le32(CNTRL_REG(p, ctrl));
if (blank_mode > 0)
switch (blank_mode) {
case FB_BLANK_VSYNC_SUSPEND:
ctrl &= ~3;
break;
case FB_BLANK_HSYNC_SUSPEND:
ctrl &= ~0x30;
break;
case FB_BLANK_POWERDOWN:
ctrl &= ~0x33;
fallthrough;
case FB_BLANK_NORMAL:
ctrl |= 0x400;
break;
default:
break;
}
else {
ctrl &= ~0x400;
ctrl |= 0x33;
}
out_le32(CNTRL_REG(p,ctrl), ctrl);
return 0;
}
/*
* Private mmap since we want to have a different caching on the framebuffer
* for controlfb.
* Note there's no locking in here; it's done in fb_mmap() in fbmem.c.
*/
static int controlfb_mmap(struct fb_info *info,
struct vm_area_struct *vma)
{
unsigned long mmio_pgoff;
unsigned long start;
u32 len;
start = info->fix.smem_start;
len = info->fix.smem_len;
mmio_pgoff = PAGE_ALIGN((start & ~PAGE_MASK) + len) >> PAGE_SHIFT;
if (vma->vm_pgoff >= mmio_pgoff) {
if (info->var.accel_flags)
return -EINVAL;
vma->vm_pgoff -= mmio_pgoff;
start = info->fix.mmio_start;
len = info->fix.mmio_len;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
} else {
/* framebuffer */
vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot);
}
return vm_iomap_memory(vma, start, len);
}
static const struct fb_ops controlfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = controlfb_check_var,
.fb_set_par = controlfb_set_par,
.fb_setcolreg = controlfb_setcolreg,
.fb_pan_display = controlfb_pan_display,
.fb_blank = controlfb_blank,
.fb_mmap = controlfb_mmap,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
/*
* Set misc info vars for this driver
*/
static void __init control_init_info(struct fb_info *info, struct fb_info_control *p)
{
/* Fill fb_info */
info->par = &p->par;
info->fbops = &controlfb_ops;
info->pseudo_palette = p->pseudo_palette;
info->flags = FBINFO_HWACCEL_YPAN;
info->screen_base = p->frame_buffer + CTRLFB_OFF;
fb_alloc_cmap(&info->cmap, 256, 0);
/* Fill fix common fields */
strcpy(info->fix.id, "control");
info->fix.mmio_start = p->control_regs_phys;
info->fix.mmio_len = sizeof(struct control_regs);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF;
info->fix.smem_len = p->total_vram - CTRLFB_OFF;
info->fix.ywrapstep = 0;
info->fix.type_aux = 0;
info->fix.accel = FB_ACCEL_NONE;
}
/*
* Parse user specified options (`video=controlfb:')
*/
static void __init control_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "vmode:", 6)) {
int vmode = simple_strtoul(this_opt+6, NULL, 0);
if (vmode > 0 && vmode <= VMODE_MAX &&
control_mac_modes[vmode - 1].m[1] >= 0)
default_vmode = vmode;
} else if (!strncmp(this_opt, "cmode:", 6)) {
int depth = simple_strtoul(this_opt+6, NULL, 0);
switch (depth) {
case CMODE_8:
case CMODE_16:
case CMODE_32:
default_cmode = depth;
break;
case 8:
default_cmode = CMODE_8;
break;
case 15:
case 16:
default_cmode = CMODE_16;
break;
case 24:
case 32:
default_cmode = CMODE_32;
break;
}
}
}
}
/*
* finish off the driver initialization and register
*/
static int __init init_control(struct fb_info_control *p)
{
int full, sense, vmode, cmode, vyres;
struct fb_var_screeninfo var;
int rc;
printk(KERN_INFO "controlfb: ");
full = p->total_vram == 0x400000;
/* Try to pick a video mode out of NVRAM if we have one. */
cmode = default_cmode;
if (IS_REACHABLE(CONFIG_NVRAM) && cmode == CMODE_NVRAM)
cmode = nvram_read_byte(NV_CMODE);
if (cmode < CMODE_8 || cmode > CMODE_32)
cmode = CMODE_8;
vmode = default_vmode;
if (IS_REACHABLE(CONFIG_NVRAM) && vmode == VMODE_NVRAM)
vmode = nvram_read_byte(NV_VMODE);
if (vmode < 1 || vmode > VMODE_MAX ||
control_mac_modes[vmode - 1].m[full] < cmode) {
sense = read_control_sense(p);
printk(KERN_CONT "Monitor sense value = 0x%x, ", sense);
vmode = mac_map_monitor_sense(sense);
if (control_mac_modes[vmode - 1].m[full] < 0)
vmode = VMODE_640_480_60;
cmode = min(cmode, control_mac_modes[vmode - 1].m[full]);
}
/* Initialize info structure */
control_init_info(&p->info, p);
/* Setup default var */
if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
/* This shouldn't happen! */
printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode);
try_again:
vmode = VMODE_640_480_60;
cmode = CMODE_8;
if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n");
return -ENXIO;
}
printk(KERN_INFO "controlfb: ");
}
printk("using video mode %d and color mode %d.\n", vmode, cmode);
vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode);
if (vyres > var.yres)
var.yres_virtual = vyres;
/* Apply default var */
var.activate = FB_ACTIVATE_NOW;
rc = fb_set_var(&p->info, &var);
if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8))
goto try_again;
/* Register with fbdev layer */
if (register_framebuffer(&p->info) < 0)
return -ENXIO;
fb_info(&p->info, "control display adapter\n");
return 0;
}
static void control_cleanup(void)
{
struct fb_info_control *p = control_fb;
if (!p)
return;
if (p->cmap_regs)
iounmap(p->cmap_regs);
if (p->control_regs)
iounmap(p->control_regs);
if (p->frame_buffer) {
if (p->control_use_bank2)
p->frame_buffer -= 0x600000;
iounmap(p->frame_buffer);
}
if (p->cmap_regs_phys)
release_mem_region(p->cmap_regs_phys, 0x1000);
if (p->control_regs_phys)
release_mem_region(p->control_regs_phys, p->control_regs_size);
if (p->fb_orig_base)
release_mem_region(p->fb_orig_base, p->fb_orig_size);
kfree(p);
}
/*
* find "control" and initialize
*/
static int __init control_of_init(struct device_node *dp)
{
struct fb_info_control *p;
struct resource fb_res, reg_res;
if (control_fb) {
printk(KERN_ERR "controlfb: only one control is supported\n");
return -ENXIO;
}
if (of_pci_address_to_resource(dp, 2, &fb_res) ||
of_pci_address_to_resource(dp, 1, ®_res)) {
printk(KERN_ERR "can't get 2 addresses for control\n");
return -ENXIO;
}
p = kzalloc(sizeof(*p), GFP_KERNEL);
if (!p)
return -ENOMEM;
control_fb = p; /* save it for cleanups */
/* Map in frame buffer and registers */
p->fb_orig_base = fb_res.start;
p->fb_orig_size = resource_size(&fb_res);
/* use the big-endian aperture (??) */
p->frame_buffer_phys = fb_res.start + 0x800000;
p->control_regs_phys = reg_res.start;
p->control_regs_size = resource_size(®_res);
if (!p->fb_orig_base ||
!request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) {
p->fb_orig_base = 0;
goto error_out;
}
/* map at most 8MB for the frame buffer */
p->frame_buffer = ioremap_wt(p->frame_buffer_phys, 0x800000);
if (!p->control_regs_phys ||
!request_mem_region(p->control_regs_phys, p->control_regs_size,
"controlfb regs")) {
p->control_regs_phys = 0;
goto error_out;
}
p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size);
p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) {
p->cmap_regs_phys = 0;
goto error_out;
}
p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
if (!p->cmap_regs || !p->control_regs || !p->frame_buffer)
goto error_out;
find_vram_size(p);
if (!p->total_vram)
goto error_out;
if (init_control(p) < 0)
goto error_out;
return 0;
error_out:
control_cleanup();
return -ENXIO;
}
static int __init control_init(void)
{
struct device_node *dp;
char *option = NULL;
int ret = -ENXIO;
if (fb_get_options("controlfb", &option))
return -ENODEV;
control_setup(option);
dp = of_find_node_by_name(NULL, "control");
if (dp && !control_of_init(dp))
ret = 0;
of_node_put(dp);
return ret;
}
device_initcall(control_init);
| linux-master | drivers/video/fbdev/controlfb.c |
/*
* linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
*
* Copyright (c) 2006-2007 Ondrej Zajicek <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
* which is based on the code of neofb.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/svga.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
#include <video/vga.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
struct s3fb_info {
int chip, rev, mclk_freq;
int wc_cookie;
struct vgastate state;
struct mutex open_lock;
unsigned int ref_count;
u32 pseudo_palette[16];
#ifdef CONFIG_FB_S3_DDC
u8 __iomem *mmio;
bool ddc_registered;
struct i2c_adapter ddc_adapter;
struct i2c_algo_bit_data ddc_algo;
#endif
};
/* ------------------------------------------------------------------------- */
static const struct svga_fb_format s3fb_formats[] = {
{ 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
{ 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
{ 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
{ 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
{16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
{16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
{24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
{32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
SVGA_FORMAT_END
};
static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
35000, 240000, 14318};
static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
230000, 460000, 14318};
static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
"S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
"S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
"S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
"S3 Virge/GX2", "S3 Virge/GX2+", "",
"S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
"S3 Trio3D", "S3 Virge/MX"};
#define CHIP_UNKNOWN 0x00
#define CHIP_732_TRIO32 0x01
#define CHIP_764_TRIO64 0x02
#define CHIP_765_TRIO64VP 0x03
#define CHIP_767_TRIO64UVP 0x04
#define CHIP_775_TRIO64V2_DX 0x05
#define CHIP_785_TRIO64V2_GX 0x06
#define CHIP_551_PLATO_PX 0x07
#define CHIP_M65_AURORA64VP 0x08
#define CHIP_325_VIRGE 0x09
#define CHIP_988_VIRGE_VX 0x0A
#define CHIP_375_VIRGE_DX 0x0B
#define CHIP_385_VIRGE_GX 0x0C
#define CHIP_357_VIRGE_GX2 0x0D
#define CHIP_359_VIRGE_GX2P 0x0E
#define CHIP_360_TRIO3D_1X 0x10
#define CHIP_362_TRIO3D_2X 0x11
#define CHIP_368_TRIO3D_2X 0x12
#define CHIP_365_TRIO3D 0x13
#define CHIP_260_VIRGE_MX 0x14
#define CHIP_XXX_TRIO 0x80
#define CHIP_XXX_TRIO64V2_DXGX 0x81
#define CHIP_XXX_VIRGE_DXGX 0x82
#define CHIP_36X_TRIO3D_1X_2X 0x83
#define CHIP_UNDECIDED_FLAG 0x80
#define CHIP_MASK 0xFF
#define MMIO_OFFSET 0x1000000
#define MMIO_SIZE 0x10000
/* CRT timing register sets */
static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
static const struct svga_timing_regs s3_timing_regs = {
s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
};
/* ------------------------------------------------------------------------- */
/* Module parameters */
static char *mode_option;
static int mtrr = 1;
static int fasttext = 1;
MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
module_param(mode_option, charp, 0444);
MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
module_param_named(mode, mode_option, charp, 0444);
MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
module_param(mtrr, int, 0444);
MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
module_param(fasttext, int, 0644);
MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_FB_S3_DDC
#define DDC_REG 0xaa /* Trio 3D/1X/2X */
#define DDC_MMIO_REG 0xff20 /* all other chips */
#define DDC_SCL_OUT (1 << 0)
#define DDC_SDA_OUT (1 << 1)
#define DDC_SCL_IN (1 << 2)
#define DDC_SDA_IN (1 << 3)
#define DDC_DRIVE_EN (1 << 4)
static bool s3fb_ddc_needs_mmio(int chip)
{
return !(chip == CHIP_360_TRIO3D_1X ||
chip == CHIP_362_TRIO3D_2X ||
chip == CHIP_368_TRIO3D_2X);
}
static u8 s3fb_ddc_read(struct s3fb_info *par)
{
if (s3fb_ddc_needs_mmio(par->chip))
return readb(par->mmio + DDC_MMIO_REG);
else
return vga_rcrt(par->state.vgabase, DDC_REG);
}
static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
{
if (s3fb_ddc_needs_mmio(par->chip))
writeb(val, par->mmio + DDC_MMIO_REG);
else
vga_wcrt(par->state.vgabase, DDC_REG, val);
}
static void s3fb_ddc_setscl(void *data, int val)
{
struct s3fb_info *par = data;
unsigned char reg;
reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
if (val)
reg |= DDC_SCL_OUT;
else
reg &= ~DDC_SCL_OUT;
s3fb_ddc_write(par, reg);
}
static void s3fb_ddc_setsda(void *data, int val)
{
struct s3fb_info *par = data;
unsigned char reg;
reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
if (val)
reg |= DDC_SDA_OUT;
else
reg &= ~DDC_SDA_OUT;
s3fb_ddc_write(par, reg);
}
static int s3fb_ddc_getscl(void *data)
{
struct s3fb_info *par = data;
return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
}
static int s3fb_ddc_getsda(void *data)
{
struct s3fb_info *par = data;
return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
}
static int s3fb_setup_ddc_bus(struct fb_info *info)
{
struct s3fb_info *par = info->par;
strscpy(par->ddc_adapter.name, info->fix.id,
sizeof(par->ddc_adapter.name));
par->ddc_adapter.owner = THIS_MODULE;
par->ddc_adapter.class = I2C_CLASS_DDC;
par->ddc_adapter.algo_data = &par->ddc_algo;
par->ddc_adapter.dev.parent = info->device;
par->ddc_algo.setsda = s3fb_ddc_setsda;
par->ddc_algo.setscl = s3fb_ddc_setscl;
par->ddc_algo.getsda = s3fb_ddc_getsda;
par->ddc_algo.getscl = s3fb_ddc_getscl;
par->ddc_algo.udelay = 10;
par->ddc_algo.timeout = 20;
par->ddc_algo.data = par;
i2c_set_adapdata(&par->ddc_adapter, par);
/*
* some Virge cards have external MUX to switch chip I2C bus between
* DDC and extension pins - switch it do DDC
*/
/* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
if (par->chip == CHIP_357_VIRGE_GX2 ||
par->chip == CHIP_359_VIRGE_GX2P ||
par->chip == CHIP_260_VIRGE_MX)
svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
else
svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
/* some Virge need this or the DDC is ignored */
svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
return i2c_bit_add_bus(&par->ddc_adapter);
}
#endif /* CONFIG_FB_S3_DDC */
/* ------------------------------------------------------------------------- */
/* Set font in S3 fast text mode */
static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
{
const u8 *font = map->data;
u8 __iomem *fb = (u8 __iomem *) info->screen_base;
int i, c;
if ((map->width != 8) || (map->height != 16) ||
(map->depth != 1) || (map->length != 256)) {
fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
map->width, map->height, map->depth, map->length);
return;
}
fb += 2;
for (i = 0; i < map->height; i++) {
for (c = 0; c < map->length; c++) {
fb_writeb(font[c * map->height + i], fb + c * 4);
}
fb += 1024;
}
}
static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
{
struct s3fb_info *par = info->par;
svga_tilecursor(par->state.vgabase, info, cursor);
}
static struct fb_tile_ops s3fb_tile_ops = {
.fb_settile = svga_settile,
.fb_tilecopy = svga_tilecopy,
.fb_tilefill = svga_tilefill,
.fb_tileblit = svga_tileblit,
.fb_tilecursor = s3fb_tilecursor,
.fb_get_tilemax = svga_get_tilemax,
};
static struct fb_tile_ops s3fb_fast_tile_ops = {
.fb_settile = s3fb_settile_fast,
.fb_tilecopy = svga_tilecopy,
.fb_tilefill = svga_tilefill,
.fb_tileblit = svga_tileblit,
.fb_tilecursor = s3fb_tilecursor,
.fb_get_tilemax = svga_get_tilemax,
};
/* ------------------------------------------------------------------------- */
/* image data is MSB-first, fb structure is MSB-first too */
static inline u32 expand_color(u32 c)
{
return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
}
/* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
{
u32 fg = expand_color(image->fg_color);
u32 bg = expand_color(image->bg_color);
const u8 *src1, *src;
u8 __iomem *dst1;
u32 __iomem *dst;
u32 val;
int x, y;
src1 = image->data;
dst1 = info->screen_base + (image->dy * info->fix.line_length)
+ ((image->dx / 8) * 4);
for (y = 0; y < image->height; y++) {
src = src1;
dst = (u32 __iomem *) dst1;
for (x = 0; x < image->width; x += 8) {
val = *(src++) * 0x01010101;
val = (val & fg) | (~val & bg);
fb_writel(val, dst++);
}
src1 += image->width / 8;
dst1 += info->fix.line_length;
}
}
/* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
u32 fg = expand_color(rect->color);
u8 __iomem *dst1;
u32 __iomem *dst;
int x, y;
dst1 = info->screen_base + (rect->dy * info->fix.line_length)
+ ((rect->dx / 8) * 4);
for (y = 0; y < rect->height; y++) {
dst = (u32 __iomem *) dst1;
for (x = 0; x < rect->width; x += 8) {
fb_writel(fg, dst++);
}
dst1 += info->fix.line_length;
}
}
/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
static inline u32 expand_pixel(u32 c)
{
return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
}
/* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
{
u32 fg = image->fg_color * 0x11111111;
u32 bg = image->bg_color * 0x11111111;
const u8 *src1, *src;
u8 __iomem *dst1;
u32 __iomem *dst;
u32 val;
int x, y;
src1 = image->data;
dst1 = info->screen_base + (image->dy * info->fix.line_length)
+ ((image->dx / 8) * 4);
for (y = 0; y < image->height; y++) {
src = src1;
dst = (u32 __iomem *) dst1;
for (x = 0; x < image->width; x += 8) {
val = expand_pixel(*(src++));
val = (val & fg) | (~val & bg);
fb_writel(val, dst++);
}
src1 += image->width / 8;
dst1 += info->fix.line_length;
}
}
static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
{
if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
&& ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
s3fb_iplan_imageblit(info, image);
else
s3fb_cfb4_imageblit(info, image);
} else
cfb_imageblit(info, image);
}
static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
if ((info->var.bits_per_pixel == 4)
&& ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
&& (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
s3fb_iplan_fillrect(info, rect);
else
cfb_fillrect(info, rect);
}
/* ------------------------------------------------------------------------- */
static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
{
struct s3fb_info *par = info->par;
u16 m, n, r;
u8 regval;
int rv;
rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
1000000000 / pixclock, &m, &n, &r, info->node);
if (rv < 0) {
fb_err(info, "cannot set requested pixclock, keeping old value\n");
return;
}
/* Set VGA misc register */
regval = vga_r(par->state.vgabase, VGA_MIS_R);
vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
/* Set S3 clock registers */
if (par->chip == CHIP_357_VIRGE_GX2 ||
par->chip == CHIP_359_VIRGE_GX2P ||
par->chip == CHIP_360_TRIO3D_1X ||
par->chip == CHIP_362_TRIO3D_2X ||
par->chip == CHIP_368_TRIO3D_2X ||
par->chip == CHIP_260_VIRGE_MX) {
vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
} else
vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
vga_wseq(par->state.vgabase, 0x13, m - 2);
udelay(1000);
/* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
}
/* Open framebuffer */
static int s3fb_open(struct fb_info *info, int user)
{
struct s3fb_info *par = info->par;
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
void __iomem *vgabase = par->state.vgabase;
memset(&(par->state), 0, sizeof(struct vgastate));
par->state.vgabase = vgabase;
par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
par->state.num_crtc = 0x70;
par->state.num_seq = 0x20;
save_vga(&(par->state));
}
par->ref_count++;
mutex_unlock(&(par->open_lock));
return 0;
}
/* Close framebuffer */
static int s3fb_release(struct fb_info *info, int user)
{
struct s3fb_info *par = info->par;
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
mutex_unlock(&(par->open_lock));
return -EINVAL;
}
if (par->ref_count == 1)
restore_vga(&(par->state));
par->ref_count--;
mutex_unlock(&(par->open_lock));
return 0;
}
/* Validate passed in var */
static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct s3fb_info *par = info->par;
int rv, mem, step;
u16 m, n, r;
if (!var->pixclock)
return -EINVAL;
/* Find appropriate format */
rv = svga_match_format (s3fb_formats, var, NULL);
/* 32bpp mode is not supported on VIRGE VX,
24bpp is not supported on others */
if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
rv = -EINVAL;
if (rv < 0) {
fb_err(info, "unsupported mode requested\n");
return rv;
}
/* Do not allow to have real resoulution larger than virtual */
if (var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
/* Round up xres_virtual to have proper alignment of lines */
step = s3fb_formats[rv].xresstep - 1;
var->xres_virtual = (var->xres_virtual+step) & ~step;
/* Check whether have enough memory */
mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
if (mem > info->screen_size) {
fb_err(info, "not enough framebuffer memory (%d kB requested , %u kB available)\n",
mem >> 10, (unsigned int) (info->screen_size >> 10));
return -EINVAL;
}
rv = svga_check_timings (&s3_timing_regs, var, info->node);
if (rv < 0) {
fb_err(info, "invalid timings requested\n");
return rv;
}
rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
info->node);
if (rv < 0) {
fb_err(info, "invalid pixclock value requested\n");
return rv;
}
return 0;
}
/* Set video mode from par */
static int s3fb_set_par(struct fb_info *info)
{
struct s3fb_info *par = info->par;
u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
u32 bpp = info->var.bits_per_pixel;
u32 htotal, hsstart;
if (bpp != 0) {
info->fix.ypanstep = 1;
info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
info->flags &= ~FBINFO_MISC_TILEBLITTING;
info->tileops = NULL;
/* in 4bpp supports 8p wide tiles only, any tiles otherwise */
info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
info->pixmap.blit_y = ~(u32)0;
offset_value = (info->var.xres_virtual * bpp) / 64;
screen_size = info->var.yres_virtual * info->fix.line_length;
} else {
info->fix.ypanstep = 16;
info->fix.line_length = 0;
info->flags |= FBINFO_MISC_TILEBLITTING;
info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
/* supports 8x16 tiles only */
info->pixmap.blit_x = 1 << (8 - 1);
info->pixmap.blit_y = 1 << (16 - 1);
offset_value = info->var.xres_virtual / 16;
screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
}
info->var.xoffset = 0;
info->var.yoffset = 0;
info->var.activate = FB_ACTIVATE_NOW;
/* Unlock registers */
vga_wcrt(par->state.vgabase, 0x38, 0x48);
vga_wcrt(par->state.vgabase, 0x39, 0xA5);
vga_wseq(par->state.vgabase, 0x08, 0x06);
svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
/* Blank screen and turn off sync */
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
/* Set default values */
svga_set_default_gfx_regs(par->state.vgabase);
svga_set_default_atc_regs(par->state.vgabase);
svga_set_default_seq_regs(par->state.vgabase);
svga_set_default_crt_regs(par->state.vgabase);
svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
/* S3 specific initialization */
svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
/* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
/* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
/* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
/* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
/* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
/* Set the offset register */
fb_dbg(info, "offset register : %d\n", offset_value);
svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
if (par->chip != CHIP_357_VIRGE_GX2 &&
par->chip != CHIP_359_VIRGE_GX2P &&
par->chip != CHIP_360_TRIO3D_1X &&
par->chip != CHIP_362_TRIO3D_2X &&
par->chip != CHIP_368_TRIO3D_2X &&
par->chip != CHIP_260_VIRGE_MX) {
vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
}
vga_wcrt(par->state.vgabase, 0x3A, 0x35);
svga_wattr(par->state.vgabase, 0x33, 0x00);
if (info->var.vmode & FB_VMODE_DOUBLE)
svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
else
svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
if (info->var.vmode & FB_VMODE_INTERLACED)
svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
else
svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
/* Disable hardware graphics cursor */
svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
/* Disable Streams engine */
svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
/* S3 virge DX hack */
if (par->chip == CHIP_375_VIRGE_DX) {
vga_wcrt(par->state.vgabase, 0x86, 0x80);
vga_wcrt(par->state.vgabase, 0x90, 0x00);
}
/* S3 virge VX hack */
if (par->chip == CHIP_988_VIRGE_VX) {
vga_wcrt(par->state.vgabase, 0x50, 0x00);
vga_wcrt(par->state.vgabase, 0x67, 0x50);
msleep(10); /* screen remains blank sometimes without this */
vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
vga_wcrt(par->state.vgabase, 0x66, 0x90);
}
if (par->chip == CHIP_357_VIRGE_GX2 ||
par->chip == CHIP_359_VIRGE_GX2P ||
par->chip == CHIP_360_TRIO3D_1X ||
par->chip == CHIP_362_TRIO3D_2X ||
par->chip == CHIP_368_TRIO3D_2X ||
par->chip == CHIP_365_TRIO3D ||
par->chip == CHIP_375_VIRGE_DX ||
par->chip == CHIP_385_VIRGE_GX ||
par->chip == CHIP_260_VIRGE_MX) {
dbytes = info->var.xres * ((bpp+7)/8);
vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
vga_wcrt(par->state.vgabase, 0x66, 0x81);
}
if (par->chip == CHIP_357_VIRGE_GX2 ||
par->chip == CHIP_359_VIRGE_GX2P ||
par->chip == CHIP_360_TRIO3D_1X ||
par->chip == CHIP_362_TRIO3D_2X ||
par->chip == CHIP_368_TRIO3D_2X ||
par->chip == CHIP_260_VIRGE_MX)
vga_wcrt(par->state.vgabase, 0x34, 0x00);
else /* enable Data Transfer Position Control (DTPC) */
vga_wcrt(par->state.vgabase, 0x34, 0x10);
svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
multiplex = 0;
hmul = 1;
/* Set mode-specific register values */
switch (mode) {
case 0:
fb_dbg(info, "text mode\n");
svga_set_textmode_vga_regs(par->state.vgabase);
/* Set additional registers like in 8-bit mode */
svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
/* Disable enhanced mode */
svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
if (fasttext) {
fb_dbg(info, "high speed text mode set\n");
svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
}
break;
case 1:
fb_dbg(info, "4 bit pseudocolor\n");
vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
/* Set additional registers like in 8-bit mode */
svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
/* disable enhanced mode */
svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
break;
case 2:
fb_dbg(info, "4 bit pseudocolor, planar\n");
/* Set additional registers like in 8-bit mode */
svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
/* disable enhanced mode */
svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
break;
case 3:
fb_dbg(info, "8 bit pseudocolor\n");
svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
if (info->var.pixclock > 20000 ||
par->chip == CHIP_357_VIRGE_GX2 ||
par->chip == CHIP_359_VIRGE_GX2P ||
par->chip == CHIP_360_TRIO3D_1X ||
par->chip == CHIP_362_TRIO3D_2X ||
par->chip == CHIP_368_TRIO3D_2X ||
par->chip == CHIP_260_VIRGE_MX)
svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
else {
svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
multiplex = 1;
}
break;
case 4:
fb_dbg(info, "5/5/5 truecolor\n");
if (par->chip == CHIP_988_VIRGE_VX) {
if (info->var.pixclock > 20000)
svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
else
svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
} else if (par->chip == CHIP_365_TRIO3D) {
svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
if (info->var.pixclock > 8695) {
svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
hmul = 2;
} else {
svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
multiplex = 1;
}
} else {
svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
if (par->chip != CHIP_357_VIRGE_GX2 &&
par->chip != CHIP_359_VIRGE_GX2P &&
par->chip != CHIP_360_TRIO3D_1X &&
par->chip != CHIP_362_TRIO3D_2X &&
par->chip != CHIP_368_TRIO3D_2X &&
par->chip != CHIP_260_VIRGE_MX)
hmul = 2;
}
break;
case 5:
fb_dbg(info, "5/6/5 truecolor\n");
if (par->chip == CHIP_988_VIRGE_VX) {
if (info->var.pixclock > 20000)
svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
else
svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
} else if (par->chip == CHIP_365_TRIO3D) {
svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
if (info->var.pixclock > 8695) {
svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
hmul = 2;
} else {
svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
multiplex = 1;
}
} else {
svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
if (par->chip != CHIP_357_VIRGE_GX2 &&
par->chip != CHIP_359_VIRGE_GX2P &&
par->chip != CHIP_360_TRIO3D_1X &&
par->chip != CHIP_362_TRIO3D_2X &&
par->chip != CHIP_368_TRIO3D_2X &&
par->chip != CHIP_260_VIRGE_MX)
hmul = 2;
}
break;
case 6:
/* VIRGE VX case */
fb_dbg(info, "8/8/8 truecolor\n");
svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
break;
case 7:
fb_dbg(info, "8/8/8/8 truecolor\n");
svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
break;
default:
fb_err(info, "unsupported mode - bug\n");
return -EINVAL;
}
if (par->chip != CHIP_988_VIRGE_VX) {
svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
}
s3_set_pixclock(info, info->var.pixclock);
svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
(info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
(info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
hmul, info->node);
/* Set interlaced mode start/end register */
htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
htotal = ((htotal * hmul) / 8) - 5;
vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
/* Set Data Transfer Position */
hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
/* + 2 is needed for Virge/VX, does no harm on other cards */
value = clamp((htotal + hsstart + 1) / 2 + 2, hsstart + 4, htotal + 1);
svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
if (screen_size > info->screen_size)
screen_size = info->screen_size;
memset_io(info->screen_base, 0x00, screen_size);
/* Device and screen back on */
svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
return 0;
}
/* Set a colour register */
static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *fb)
{
switch (fb->var.bits_per_pixel) {
case 0:
case 4:
if (regno >= 16)
return -EINVAL;
if ((fb->var.bits_per_pixel == 4) &&
(fb->var.nonstd == 0)) {
outb(0xF0, VGA_PEL_MSK);
outb(regno*16, VGA_PEL_IW);
} else {
outb(0x0F, VGA_PEL_MSK);
outb(regno, VGA_PEL_IW);
}
outb(red >> 10, VGA_PEL_D);
outb(green >> 10, VGA_PEL_D);
outb(blue >> 10, VGA_PEL_D);
break;
case 8:
if (regno >= 256)
return -EINVAL;
outb(0xFF, VGA_PEL_MSK);
outb(regno, VGA_PEL_IW);
outb(red >> 10, VGA_PEL_D);
outb(green >> 10, VGA_PEL_D);
outb(blue >> 10, VGA_PEL_D);
break;
case 16:
if (regno >= 16)
return 0;
if (fb->var.green.length == 5)
((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
else if (fb->var.green.length == 6)
((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
else return -EINVAL;
break;
case 24:
case 32:
if (regno >= 16)
return 0;
((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
(green & 0xFF00) | ((blue & 0xFF00) >> 8);
break;
default:
return -EINVAL;
}
return 0;
}
/* Set the display blanking state */
static int s3fb_blank(int blank_mode, struct fb_info *info)
{
struct s3fb_info *par = info->par;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
fb_dbg(info, "unblank\n");
svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
break;
case FB_BLANK_NORMAL:
fb_dbg(info, "blank\n");
svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
break;
case FB_BLANK_HSYNC_SUSPEND:
fb_dbg(info, "hsync\n");
svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
break;
case FB_BLANK_VSYNC_SUSPEND:
fb_dbg(info, "vsync\n");
svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
break;
case FB_BLANK_POWERDOWN:
fb_dbg(info, "sync down\n");
svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
break;
}
return 0;
}
/* Pan the display */
static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct s3fb_info *par = info->par;
unsigned int offset;
/* Calculate the offset */
if (info->var.bits_per_pixel == 0) {
offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
+ (var->xoffset / 2);
offset = offset >> 2;
} else {
offset = (var->yoffset * info->fix.line_length) +
(var->xoffset * info->var.bits_per_pixel / 8);
offset = offset >> 2;
}
/* Set the offset */
svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
return 0;
}
/* ------------------------------------------------------------------------- */
/* Frame buffer operations */
static const struct fb_ops s3fb_ops = {
.owner = THIS_MODULE,
.fb_open = s3fb_open,
.fb_release = s3fb_release,
.fb_check_var = s3fb_check_var,
.fb_set_par = s3fb_set_par,
.fb_setcolreg = s3fb_setcolreg,
.fb_blank = s3fb_blank,
.fb_pan_display = s3fb_pan_display,
.fb_fillrect = s3fb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = s3fb_imageblit,
.fb_get_caps = svga_get_caps,
};
/* ------------------------------------------------------------------------- */
static int s3_identification(struct s3fb_info *par)
{
int chip = par->chip;
if (chip == CHIP_XXX_TRIO) {
u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
if (cr2e == 0x10)
return CHIP_732_TRIO32;
if (cr2e == 0x11) {
if (! (cr2f & 0x40))
return CHIP_764_TRIO64;
else
return CHIP_765_TRIO64VP;
}
}
}
if (chip == CHIP_XXX_TRIO64V2_DXGX) {
u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
if (! (cr6f & 0x01))
return CHIP_775_TRIO64V2_DX;
else
return CHIP_785_TRIO64V2_GX;
}
if (chip == CHIP_XXX_VIRGE_DXGX) {
u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
if (! (cr6f & 0x01))
return CHIP_375_VIRGE_DX;
else
return CHIP_385_VIRGE_GX;
}
if (chip == CHIP_36X_TRIO3D_1X_2X) {
switch (vga_rcrt(par->state.vgabase, 0x2f)) {
case 0x00:
return CHIP_360_TRIO3D_1X;
case 0x01:
return CHIP_362_TRIO3D_2X;
case 0x02:
return CHIP_368_TRIO3D_2X;
}
}
return CHIP_UNKNOWN;
}
/* PCI probe */
static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct pci_bus_region bus_reg;
struct resource vga_res;
struct fb_info *info;
struct s3fb_info *par;
int rc;
u8 regval, cr38, cr39;
bool found = false;
/* Ignore secondary VGA device because there is no VGA arbitration */
if (! svga_primary_device(dev)) {
dev_info(&(dev->dev), "ignoring secondary device\n");
return -ENODEV;
}
rc = aperture_remove_conflicting_pci_devices(dev, "s3fb");
if (rc)
return rc;
/* Allocate and fill driver data structure */
info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
if (!info)
return -ENOMEM;
par = info->par;
mutex_init(&par->open_lock);
info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
info->fbops = &s3fb_ops;
/* Prepare PCI device */
rc = pci_enable_device(dev);
if (rc < 0) {
dev_err(info->device, "cannot enable PCI device\n");
goto err_enable_device;
}
rc = pci_request_regions(dev, "s3fb");
if (rc < 0) {
dev_err(info->device, "cannot reserve framebuffer region\n");
goto err_request_regions;
}
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = pci_resource_len(dev, 0);
/* Map physical IO memory address into kernel space */
info->screen_base = pci_iomap_wc(dev, 0, 0);
if (! info->screen_base) {
rc = -ENOMEM;
dev_err(info->device, "iomap for framebuffer failed\n");
goto err_iomap;
}
bus_reg.start = 0;
bus_reg.end = 64 * 1024;
vga_res.flags = IORESOURCE_IO;
pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
/* Unlock regs */
cr38 = vga_rcrt(par->state.vgabase, 0x38);
cr39 = vga_rcrt(par->state.vgabase, 0x39);
vga_wseq(par->state.vgabase, 0x08, 0x06);
vga_wcrt(par->state.vgabase, 0x38, 0x48);
vga_wcrt(par->state.vgabase, 0x39, 0xA5);
/* Identify chip type */
par->chip = id->driver_data & CHIP_MASK;
par->rev = vga_rcrt(par->state.vgabase, 0x2f);
if (par->chip & CHIP_UNDECIDED_FLAG)
par->chip = s3_identification(par);
/* Find how many physical memory there is on card */
/* 0x36 register is accessible even if other registers are locked */
regval = vga_rcrt(par->state.vgabase, 0x36);
if (par->chip == CHIP_360_TRIO3D_1X ||
par->chip == CHIP_362_TRIO3D_2X ||
par->chip == CHIP_368_TRIO3D_2X ||
par->chip == CHIP_365_TRIO3D) {
switch ((regval & 0xE0) >> 5) {
case 0: /* 8MB -- only 4MB usable for display */
case 1: /* 4MB with 32-bit bus */
case 2: /* 4MB */
info->screen_size = 4 << 20;
break;
case 4: /* 2MB on 365 Trio3D */
case 6: /* 2MB */
info->screen_size = 2 << 20;
break;
}
} else if (par->chip == CHIP_357_VIRGE_GX2 ||
par->chip == CHIP_359_VIRGE_GX2P ||
par->chip == CHIP_260_VIRGE_MX) {
switch ((regval & 0xC0) >> 6) {
case 1: /* 4MB */
info->screen_size = 4 << 20;
break;
case 3: /* 2MB */
info->screen_size = 2 << 20;
break;
}
} else if (par->chip == CHIP_988_VIRGE_VX) {
switch ((regval & 0x60) >> 5) {
case 0: /* 2MB */
info->screen_size = 2 << 20;
break;
case 1: /* 4MB */
info->screen_size = 4 << 20;
break;
case 2: /* 6MB */
info->screen_size = 6 << 20;
break;
case 3: /* 8MB */
info->screen_size = 8 << 20;
break;
}
/* off-screen memory */
regval = vga_rcrt(par->state.vgabase, 0x37);
switch ((regval & 0x60) >> 5) {
case 1: /* 4MB */
info->screen_size -= 4 << 20;
break;
case 2: /* 2MB */
info->screen_size -= 2 << 20;
break;
}
} else
info->screen_size = s3_memsizes[regval >> 5] << 10;
info->fix.smem_len = info->screen_size;
/* Find MCLK frequency */
regval = vga_rseq(par->state.vgabase, 0x10);
par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
par->mclk_freq = par->mclk_freq >> (regval >> 5);
/* Restore locks */
vga_wcrt(par->state.vgabase, 0x38, cr38);
vga_wcrt(par->state.vgabase, 0x39, cr39);
strcpy(info->fix.id, s3_names [par->chip]);
info->fix.mmio_start = 0;
info->fix.mmio_len = 0;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.ypanstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->pseudo_palette = (void*) (par->pseudo_palette);
info->var.bits_per_pixel = 8;
#ifdef CONFIG_FB_S3_DDC
/* Enable MMIO if needed */
if (s3fb_ddc_needs_mmio(par->chip)) {
par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
if (par->mmio)
svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
else
dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC",
info->fix.smem_start + MMIO_OFFSET);
}
if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
if (s3fb_setup_ddc_bus(info) == 0) {
u8 *edid = fb_ddc_read(&par->ddc_adapter);
par->ddc_registered = true;
if (edid) {
fb_edid_to_monspecs(edid, &info->monspecs);
kfree(edid);
if (!info->monspecs.modedb)
dev_err(info->device, "error getting mode database\n");
else {
const struct fb_videomode *m;
fb_videomode_to_modelist(info->monspecs.modedb,
info->monspecs.modedb_len,
&info->modelist);
m = fb_find_best_display(&info->monspecs, &info->modelist);
if (m) {
fb_videomode_to_var(&info->var, m);
/* fill all other info->var's fields */
if (s3fb_check_var(&info->var, info) == 0)
found = true;
}
}
}
}
#endif
if (!mode_option && !found)
mode_option = "640x480-8@60";
/* Prepare startup mode */
if (mode_option) {
rc = fb_find_mode(&info->var, info, mode_option,
info->monspecs.modedb, info->monspecs.modedb_len,
NULL, info->var.bits_per_pixel);
if (!rc || rc == 4) {
rc = -EINVAL;
dev_err(info->device, "mode %s not found\n", mode_option);
fb_destroy_modedb(info->monspecs.modedb);
info->monspecs.modedb = NULL;
goto err_find_mode;
}
}
fb_destroy_modedb(info->monspecs.modedb);
info->monspecs.modedb = NULL;
/* maximize virtual vertical size for fast scrolling */
info->var.yres_virtual = info->fix.smem_len * 8 /
(info->var.bits_per_pixel * info->var.xres_virtual);
if (info->var.yres_virtual < info->var.yres) {
dev_err(info->device, "virtual vertical size smaller than real\n");
rc = -EINVAL;
goto err_find_mode;
}
rc = fb_alloc_cmap(&info->cmap, 256, 0);
if (rc < 0) {
dev_err(info->device, "cannot allocate colormap\n");
goto err_alloc_cmap;
}
rc = register_framebuffer(info);
if (rc < 0) {
dev_err(info->device, "cannot register framebuffer\n");
goto err_reg_fb;
}
fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n",
info->fix.id, pci_name(dev),
info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
if (par->chip == CHIP_UNKNOWN)
fb_info(info, "unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
vga_rcrt(par->state.vgabase, 0x2d),
vga_rcrt(par->state.vgabase, 0x2e),
vga_rcrt(par->state.vgabase, 0x2f),
vga_rcrt(par->state.vgabase, 0x30));
/* Record a reference to the driver data */
pci_set_drvdata(dev, info);
if (mtrr)
par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
info->fix.smem_len);
return 0;
/* Error handling */
err_reg_fb:
fb_dealloc_cmap(&info->cmap);
err_alloc_cmap:
err_find_mode:
#ifdef CONFIG_FB_S3_DDC
if (par->ddc_registered)
i2c_del_adapter(&par->ddc_adapter);
if (par->mmio)
iounmap(par->mmio);
#endif
pci_iounmap(dev, info->screen_base);
err_iomap:
pci_release_regions(dev);
err_request_regions:
/* pci_disable_device(dev); */
err_enable_device:
framebuffer_release(info);
return rc;
}
/* PCI remove */
static void s3_pci_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
struct s3fb_info __maybe_unused *par;
if (info) {
par = info->par;
arch_phys_wc_del(par->wc_cookie);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
#ifdef CONFIG_FB_S3_DDC
if (par->ddc_registered)
i2c_del_adapter(&par->ddc_adapter);
if (par->mmio)
iounmap(par->mmio);
#endif
pci_iounmap(dev, info->screen_base);
pci_release_regions(dev);
/* pci_disable_device(dev); */
framebuffer_release(info);
}
}
/* PCI suspend */
static int __maybe_unused s3_pci_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct s3fb_info *par = info->par;
dev_info(info->device, "suspend\n");
console_lock();
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
fb_set_suspend(info, 1);
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
/* PCI resume */
static int __maybe_unused s3_pci_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct s3fb_info *par = info->par;
dev_info(info->device, "resume\n");
console_lock();
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
s3fb_set_par(info);
fb_set_suspend(info, 0);
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
static const struct dev_pm_ops s3_pci_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = s3_pci_suspend,
.resume = s3_pci_resume,
.freeze = NULL,
.thaw = s3_pci_resume,
.poweroff = s3_pci_suspend,
.restore = s3_pci_resume,
#endif
};
/* List of boards that we are trying to support */
static const struct pci_device_id s3_devices[] = {
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
{PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX},
{0, 0, 0, 0, 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, s3_devices);
static struct pci_driver s3fb_pci_driver = {
.name = "s3fb",
.id_table = s3_devices,
.probe = s3_pci_probe,
.remove = s3_pci_remove,
.driver.pm = &s3_pci_pm_ops,
};
/* Parse user specified options */
#ifndef MODULE
static int __init s3fb_setup(char *options)
{
char *opt;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
else if (!strncmp(opt, "mtrr:", 5))
mtrr = simple_strtoul(opt + 5, NULL, 0);
else if (!strncmp(opt, "fasttext:", 9))
fasttext = simple_strtoul(opt + 9, NULL, 0);
else
mode_option = opt;
}
return 0;
}
#endif
/* Cleanup */
static void __exit s3fb_cleanup(void)
{
pr_debug("s3fb: cleaning up\n");
pci_unregister_driver(&s3fb_pci_driver);
}
/* Driver Initialisation */
static int __init s3fb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("s3fb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("s3fb", &option))
return -ENODEV;
s3fb_setup(option);
#endif
pr_debug("s3fb: initializing\n");
return pci_register_driver(&s3fb_pci_driver);
}
/* ------------------------------------------------------------------------- */
/* Modularization */
module_init(s3fb_init);
module_exit(s3fb_cleanup);
| linux-master | drivers/video/fbdev/s3fb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* macfb.c: Generic framebuffer for Macs whose colourmaps/modes we
* don't know how to set.
*
* (c) 1999 David Huggins-Daines <[email protected]>
*
* Primarily based on vesafb.c, by Gerd Knorr
* (c) 1998 Gerd Knorr <[email protected]>
*
* Also uses information and code from:
*
* The original macfb.c from Linux/mac68k 2.0, by Alan Cox, Juergen
* Mellinger, Mikael Forselius, Michael Schmitz, and others.
*
* valkyriefb.c, by Martin Costabel, Kevin Schoedel, Barry Nathan, Dan
* Jacobowitz, Paul Mackerras, Fabio Riccardi, and Geert Uytterhoeven.
*
* The VideoToolbox "Bugs" web page at
* http://rajsky.psych.nyu.edu/Tips/VideoBugs.html
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/nubus.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <asm/setup.h>
#include <asm/macintosh.h>
#include <asm/io.h>
/* Common DAC base address for the LC, RBV, Valkyrie, and IIvx */
#define DAC_BASE 0x50f24000
/* Some addresses for the DAFB */
#define DAFB_BASE 0xf9800200
/* Address for the built-in Civic framebuffer in Quadra AVs */
#define CIVIC_BASE 0x50f30800
/* GSC (Gray Scale Controller) base address */
#define GSC_BASE 0x50F20000
/* CSC (Color Screen Controller) base address */
#define CSC_BASE 0x50F20000
static int (*macfb_setpalette)(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info);
static struct {
unsigned char addr;
unsigned char lut;
} __iomem *v8_brazil_cmap_regs;
static struct {
unsigned char addr;
char pad1[3]; /* word aligned */
unsigned char lut;
char pad2[3]; /* word aligned */
unsigned char cntl; /* a guess as to purpose */
} __iomem *rbv_cmap_regs;
static struct {
unsigned long reset;
unsigned long pad1[3];
unsigned char pad2[3];
unsigned char lut;
} __iomem *dafb_cmap_regs;
static struct {
unsigned char addr; /* OFFSET: 0x00 */
unsigned char pad1[15];
unsigned char lut; /* OFFSET: 0x10 */
unsigned char pad2[15];
unsigned char status; /* OFFSET: 0x20 */
unsigned char pad3[7];
unsigned long vbl_addr; /* OFFSET: 0x28 */
unsigned int status2; /* OFFSET: 0x2C */
} __iomem *civic_cmap_regs;
static struct {
char pad1[0x40];
unsigned char clut_waddr; /* 0x40 */
char pad2;
unsigned char clut_data; /* 0x42 */
char pad3[0x3];
unsigned char clut_raddr; /* 0x46 */
} __iomem *csc_cmap_regs;
/* The registers in these structs are in NuBus slot space */
struct mdc_cmap_regs {
char pad1[0x200200];
unsigned char addr;
char pad2[6];
unsigned char lut;
};
struct toby_cmap_regs {
char pad1[0x90018];
unsigned char lut; /* TFBClutWDataReg, offset 0x90018 */
char pad2[3];
unsigned char addr; /* TFBClutAddrReg, offset 0x9001C */
};
struct jet_cmap_regs {
char pad1[0xe0e000];
unsigned char addr;
unsigned char lut;
};
#define PIXEL_TO_MM(a) (((a)*10)/28) /* width in mm at 72 dpi */
static struct fb_var_screeninfo macfb_defined = {
.activate = FB_ACTIVATE_NOW,
.right_margin = 32,
.upper_margin = 16,
.lower_margin = 4,
.vsync_len = 4,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_fix_screeninfo macfb_fix = {
.type = FB_TYPE_PACKED_PIXELS,
.accel = FB_ACCEL_NONE,
};
static void *slot_addr;
static struct fb_info fb_info;
static u32 pseudo_palette[16];
static int vidtest;
/*
* Unlike the Valkyrie, the DAFB cannot set individual colormap
* registers. Therefore, we do what the MacOS driver does (no
* kidding!) and simply set them one by one until we hit the one we
* want.
*/
static int dafb_setpalette(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info)
{
static int lastreg = -2;
unsigned long flags;
local_irq_save(flags);
/*
* fbdev will set an entire colourmap, but X won't. Hopefully
* this should accommodate both of them
*/
if (regno != lastreg + 1) {
int i;
/* Stab in the dark trying to reset the CLUT pointer */
nubus_writel(0, &dafb_cmap_regs->reset);
nop();
/* Loop until we get to the register we want */
for (i = 0; i < regno; i++) {
nubus_writeb(info->cmap.red[i] >> 8,
&dafb_cmap_regs->lut);
nop();
nubus_writeb(info->cmap.green[i] >> 8,
&dafb_cmap_regs->lut);
nop();
nubus_writeb(info->cmap.blue[i] >> 8,
&dafb_cmap_regs->lut);
nop();
}
}
nubus_writeb(red, &dafb_cmap_regs->lut);
nop();
nubus_writeb(green, &dafb_cmap_regs->lut);
nop();
nubus_writeb(blue, &dafb_cmap_regs->lut);
local_irq_restore(flags);
lastreg = regno;
return 0;
}
/* V8 and Brazil seem to use the same DAC. Sonora does as well. */
static int v8_brazil_setpalette(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info)
{
unsigned int bpp = info->var.bits_per_pixel;
unsigned long flags;
local_irq_save(flags);
/* On these chips, the CLUT register numbers are spread out
* across the register space. Thus:
* In 8bpp, all regnos are valid.
* In 4bpp, the regnos are 0x0f, 0x1f, 0x2f, etc, etc
* In 2bpp, the regnos are 0x3f, 0x7f, 0xbf, 0xff
*/
regno = (regno << (8 - bpp)) | (0xFF >> bpp);
nubus_writeb(regno, &v8_brazil_cmap_regs->addr);
nop();
/* send one color channel at a time */
nubus_writeb(red, &v8_brazil_cmap_regs->lut);
nop();
nubus_writeb(green, &v8_brazil_cmap_regs->lut);
nop();
nubus_writeb(blue, &v8_brazil_cmap_regs->lut);
local_irq_restore(flags);
return 0;
}
/* RAM-Based Video */
static int rbv_setpalette(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info)
{
unsigned long flags;
local_irq_save(flags);
/* From the VideoToolbox driver. Seems to be saying that
* regno #254 and #255 are the important ones for 1-bit color,
* regno #252-255 are the important ones for 2-bit color, etc.
*/
regno += 256 - (1 << info->var.bits_per_pixel);
/* reset clut? (VideoToolbox sez "not necessary") */
nubus_writeb(0xFF, &rbv_cmap_regs->cntl);
nop();
/* tell clut which address to use. */
nubus_writeb(regno, &rbv_cmap_regs->addr);
nop();
/* send one color channel at a time. */
nubus_writeb(red, &rbv_cmap_regs->lut);
nop();
nubus_writeb(green, &rbv_cmap_regs->lut);
nop();
nubus_writeb(blue, &rbv_cmap_regs->lut);
local_irq_restore(flags);
return 0;
}
/* Macintosh Display Card (8*24) */
static int mdc_setpalette(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info)
{
struct mdc_cmap_regs *cmap_regs = slot_addr;
unsigned long flags;
local_irq_save(flags);
/* the nop's are there to order writes. */
nubus_writeb(regno, &cmap_regs->addr);
nop();
nubus_writeb(red, &cmap_regs->lut);
nop();
nubus_writeb(green, &cmap_regs->lut);
nop();
nubus_writeb(blue, &cmap_regs->lut);
local_irq_restore(flags);
return 0;
}
/* Toby frame buffer */
static int toby_setpalette(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info)
{
struct toby_cmap_regs *cmap_regs = slot_addr;
unsigned int bpp = info->var.bits_per_pixel;
unsigned long flags;
red = ~red;
green = ~green;
blue = ~blue;
regno = (regno << (8 - bpp)) | (0xFF >> bpp);
local_irq_save(flags);
nubus_writeb(regno, &cmap_regs->addr);
nop();
nubus_writeb(red, &cmap_regs->lut);
nop();
nubus_writeb(green, &cmap_regs->lut);
nop();
nubus_writeb(blue, &cmap_regs->lut);
local_irq_restore(flags);
return 0;
}
/* Jet frame buffer */
static int jet_setpalette(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info)
{
struct jet_cmap_regs *cmap_regs = slot_addr;
unsigned long flags;
local_irq_save(flags);
nubus_writeb(regno, &cmap_regs->addr);
nop();
nubus_writeb(red, &cmap_regs->lut);
nop();
nubus_writeb(green, &cmap_regs->lut);
nop();
nubus_writeb(blue, &cmap_regs->lut);
local_irq_restore(flags);
return 0;
}
/*
* Civic framebuffer -- Quadra AV built-in video. A chip
* called Sebastian holds the actual color palettes, and
* apparently, there are two different banks of 512K RAM
* which can act as separate framebuffers for doing video
* input and viewing the screen at the same time! The 840AV
* Can add another 1MB RAM to give the two framebuffers
* 1MB RAM apiece.
*/
static int civic_setpalette(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info)
{
unsigned long flags;
int clut_status;
local_irq_save(flags);
/* Set the register address */
nubus_writeb(regno, &civic_cmap_regs->addr);
nop();
/*
* Grab a status word and do some checking;
* Then finally write the clut!
*/
clut_status = nubus_readb(&civic_cmap_regs->status2);
if ((clut_status & 0x0008) == 0)
{
#if 0
if ((clut_status & 0x000D) != 0)
{
nubus_writeb(0x00, &civic_cmap_regs->lut);
nop();
nubus_writeb(0x00, &civic_cmap_regs->lut);
nop();
}
#endif
nubus_writeb(red, &civic_cmap_regs->lut);
nop();
nubus_writeb(green, &civic_cmap_regs->lut);
nop();
nubus_writeb(blue, &civic_cmap_regs->lut);
nop();
nubus_writeb(0x00, &civic_cmap_regs->lut);
}
else
{
unsigned char junk;
junk = nubus_readb(&civic_cmap_regs->lut);
nop();
junk = nubus_readb(&civic_cmap_regs->lut);
nop();
junk = nubus_readb(&civic_cmap_regs->lut);
nop();
junk = nubus_readb(&civic_cmap_regs->lut);
nop();
if ((clut_status & 0x000D) != 0)
{
nubus_writeb(0x00, &civic_cmap_regs->lut);
nop();
nubus_writeb(0x00, &civic_cmap_regs->lut);
nop();
}
nubus_writeb(red, &civic_cmap_regs->lut);
nop();
nubus_writeb(green, &civic_cmap_regs->lut);
nop();
nubus_writeb(blue, &civic_cmap_regs->lut);
nop();
nubus_writeb(junk, &civic_cmap_regs->lut);
}
local_irq_restore(flags);
return 0;
}
/*
* The CSC is the framebuffer on the PowerBook 190 series
* (and the 5300 too, but that's a PowerMac). This function
* brought to you in part by the ECSC driver for MkLinux.
*/
static int csc_setpalette(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
struct fb_info *info)
{
unsigned long flags;
local_irq_save(flags);
udelay(1); /* mklinux on PB 5300 waits for 260 ns */
nubus_writeb(regno, &csc_cmap_regs->clut_waddr);
nubus_writeb(red, &csc_cmap_regs->clut_data);
nubus_writeb(green, &csc_cmap_regs->clut_data);
nubus_writeb(blue, &csc_cmap_regs->clut_data);
local_irq_restore(flags);
return 0;
}
static int macfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *fb_info)
{
/*
* Set a single color register. The values supplied are
* already rounded down to the hardware's capabilities
* (according to the entries in the `var' structure).
* Return non-zero for invalid regno.
*/
if (regno >= fb_info->cmap.len)
return 1;
if (fb_info->var.bits_per_pixel <= 8) {
switch (fb_info->var.bits_per_pixel) {
case 1:
/* We shouldn't get here */
break;
case 2:
case 4:
case 8:
if (macfb_setpalette)
macfb_setpalette(regno, red >> 8, green >> 8,
blue >> 8, fb_info);
else
return 1;
break;
}
} else if (regno < 16) {
switch (fb_info->var.bits_per_pixel) {
case 16:
if (fb_info->var.red.offset == 10) {
/* 1:5:5:5 */
((u32*) (fb_info->pseudo_palette))[regno] =
((red & 0xf800) >> 1) |
((green & 0xf800) >> 6) |
((blue & 0xf800) >> 11) |
((transp != 0) << 15);
} else {
/* 0:5:6:5 */
((u32*) (fb_info->pseudo_palette))[regno] =
((red & 0xf800) >> 0) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
}
break;
/*
* 24-bit colour almost doesn't exist on 68k Macs --
* https://support.apple.com/kb/TA28634 (Old Article: 10992)
*/
case 24:
case 32:
red >>= 8;
green >>= 8;
blue >>= 8;
((u32 *)(fb_info->pseudo_palette))[regno] =
(red << fb_info->var.red.offset) |
(green << fb_info->var.green.offset) |
(blue << fb_info->var.blue.offset);
break;
}
}
return 0;
}
static const struct fb_ops macfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = macfb_setcolreg,
};
static void __init macfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strcmp(this_opt, "inverse"))
fb_invert_cmaps();
else
if (!strcmp(this_opt, "vidtest"))
vidtest = 1; /* enable experimental CLUT code */
}
}
static void __init iounmap_macfb(void)
{
if (dafb_cmap_regs)
iounmap(dafb_cmap_regs);
if (v8_brazil_cmap_regs)
iounmap(v8_brazil_cmap_regs);
if (rbv_cmap_regs)
iounmap(rbv_cmap_regs);
if (civic_cmap_regs)
iounmap(civic_cmap_regs);
if (csc_cmap_regs)
iounmap(csc_cmap_regs);
}
static int __init macfb_init(void)
{
int video_cmap_len, video_is_nubus = 0;
struct nubus_rsrc *ndev = NULL;
char *option = NULL;
int err;
if (fb_get_options("macfb", &option))
return -ENODEV;
macfb_setup(option);
if (!MACH_IS_MAC)
return -ENODEV;
if (mac_bi_data.id == MAC_MODEL_Q630 ||
mac_bi_data.id == MAC_MODEL_P588)
return -ENODEV; /* See valkyriefb.c */
macfb_defined.xres = mac_bi_data.dimensions & 0xFFFF;
macfb_defined.yres = mac_bi_data.dimensions >> 16;
macfb_defined.bits_per_pixel = mac_bi_data.videodepth;
macfb_fix.line_length = mac_bi_data.videorow;
macfb_fix.smem_len = macfb_fix.line_length * macfb_defined.yres;
/* Note: physical address (since 2.1.127) */
macfb_fix.smem_start = mac_bi_data.videoaddr;
/*
* This is actually redundant with the initial mappings.
* However, there are some non-obvious aspects to the way
* those mappings are set up, so this is in fact the safest
* way to ensure that this driver will work on every possible Mac
*/
fb_info.screen_base = ioremap(mac_bi_data.videoaddr,
macfb_fix.smem_len);
if (!fb_info.screen_base)
return -ENODEV;
pr_info("macfb: framebuffer at 0x%08lx, mapped to 0x%p, size %dk\n",
macfb_fix.smem_start, fb_info.screen_base,
macfb_fix.smem_len / 1024);
pr_info("macfb: mode is %dx%dx%d, linelength=%d\n",
macfb_defined.xres, macfb_defined.yres,
macfb_defined.bits_per_pixel, macfb_fix.line_length);
/* Fill in the available video resolution */
macfb_defined.xres_virtual = macfb_defined.xres;
macfb_defined.yres_virtual = macfb_defined.yres;
macfb_defined.height = PIXEL_TO_MM(macfb_defined.yres);
macfb_defined.width = PIXEL_TO_MM(macfb_defined.xres);
/* Some dummy values for timing to make fbset happy */
macfb_defined.pixclock = 10000000 / macfb_defined.xres *
1000 / macfb_defined.yres;
macfb_defined.left_margin = (macfb_defined.xres / 8) & 0xf8;
macfb_defined.hsync_len = (macfb_defined.xres / 8) & 0xf8;
switch (macfb_defined.bits_per_pixel) {
case 1:
macfb_defined.red.length = macfb_defined.bits_per_pixel;
macfb_defined.green.length = macfb_defined.bits_per_pixel;
macfb_defined.blue.length = macfb_defined.bits_per_pixel;
video_cmap_len = 2;
macfb_fix.visual = FB_VISUAL_MONO01;
break;
case 2:
case 4:
case 8:
macfb_defined.red.length = macfb_defined.bits_per_pixel;
macfb_defined.green.length = macfb_defined.bits_per_pixel;
macfb_defined.blue.length = macfb_defined.bits_per_pixel;
video_cmap_len = 1 << macfb_defined.bits_per_pixel;
macfb_fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
macfb_defined.transp.offset = 15;
macfb_defined.transp.length = 1;
macfb_defined.red.offset = 10;
macfb_defined.red.length = 5;
macfb_defined.green.offset = 5;
macfb_defined.green.length = 5;
macfb_defined.blue.offset = 0;
macfb_defined.blue.length = 5;
video_cmap_len = 16;
/*
* Should actually be FB_VISUAL_DIRECTCOLOR, but this
* works too
*/
macfb_fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 24:
case 32:
macfb_defined.red.offset = 16;
macfb_defined.red.length = 8;
macfb_defined.green.offset = 8;
macfb_defined.green.length = 8;
macfb_defined.blue.offset = 0;
macfb_defined.blue.length = 8;
video_cmap_len = 16;
macfb_fix.visual = FB_VISUAL_TRUECOLOR;
break;
default:
pr_err("macfb: unknown or unsupported bit depth: %d\n",
macfb_defined.bits_per_pixel);
err = -EINVAL;
goto fail_unmap;
}
/*
* We take a wild guess that if the video physical address is
* in nubus slot space, that the nubus card is driving video.
* Penguin really ought to tell us whether we are using internal
* video or not.
* Hopefully we only find one of them. Otherwise our NuBus
* code is really broken :-)
*/
for_each_func_rsrc(ndev) {
unsigned long base = ndev->board->slot_addr;
if (mac_bi_data.videoaddr < base ||
mac_bi_data.videoaddr - base > 0xFFFFFF)
continue;
if (ndev->category != NUBUS_CAT_DISPLAY ||
ndev->type != NUBUS_TYPE_VIDEO)
continue;
video_is_nubus = 1;
slot_addr = (unsigned char *)base;
switch(ndev->dr_hw) {
case NUBUS_DRHW_APPLE_MDC:
strcpy(macfb_fix.id, "Mac Disp. Card");
macfb_setpalette = mdc_setpalette;
break;
case NUBUS_DRHW_APPLE_TFB:
strcpy(macfb_fix.id, "Toby");
macfb_setpalette = toby_setpalette;
break;
case NUBUS_DRHW_APPLE_JET:
strcpy(macfb_fix.id, "Jet");
macfb_setpalette = jet_setpalette;
break;
default:
strcpy(macfb_fix.id, "Generic NuBus");
break;
}
}
/* If it's not a NuBus card, it must be internal video */
if (!video_is_nubus)
switch (mac_bi_data.id) {
/*
* DAFB Quadras
* Note: these first four have the v7 DAFB, which is
* known to be rather unlike the ones used in the
* other models
*/
case MAC_MODEL_P475:
case MAC_MODEL_P475F:
case MAC_MODEL_P575:
case MAC_MODEL_Q605:
case MAC_MODEL_Q800:
case MAC_MODEL_Q650:
case MAC_MODEL_Q610:
case MAC_MODEL_C650:
case MAC_MODEL_C610:
case MAC_MODEL_Q700:
case MAC_MODEL_Q900:
case MAC_MODEL_Q950:
strcpy(macfb_fix.id, "DAFB");
macfb_setpalette = dafb_setpalette;
dafb_cmap_regs = ioremap(DAFB_BASE, 0x1000);
break;
/*
* LC II uses the V8 framebuffer
*/
case MAC_MODEL_LCII:
strcpy(macfb_fix.id, "V8");
macfb_setpalette = v8_brazil_setpalette;
v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
break;
/*
* IIvi, IIvx use the "Brazil" framebuffer (which is
* very much like the V8, it seems, and probably uses
* the same DAC)
*/
case MAC_MODEL_IIVI:
case MAC_MODEL_IIVX:
case MAC_MODEL_P600:
strcpy(macfb_fix.id, "Brazil");
macfb_setpalette = v8_brazil_setpalette;
v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
break;
/*
* LC III (and friends) use the Sonora framebuffer
* Incidentally this is also used in the non-AV models
* of the x100 PowerMacs
* These do in fact seem to use the same DAC interface
* as the LC II.
*/
case MAC_MODEL_LCIII:
case MAC_MODEL_P520:
case MAC_MODEL_P550:
case MAC_MODEL_P460:
strcpy(macfb_fix.id, "Sonora");
macfb_setpalette = v8_brazil_setpalette;
v8_brazil_cmap_regs = ioremap(DAC_BASE, 0x1000);
break;
/*
* IIci and IIsi use the infamous RBV chip
* (the IIsi is just a rebadged and crippled
* IIci in a different case, BTW)
*/
case MAC_MODEL_IICI:
case MAC_MODEL_IISI:
strcpy(macfb_fix.id, "RBV");
macfb_setpalette = rbv_setpalette;
rbv_cmap_regs = ioremap(DAC_BASE, 0x1000);
break;
/*
* AVs use the Civic framebuffer
*/
case MAC_MODEL_Q840:
case MAC_MODEL_C660:
strcpy(macfb_fix.id, "Civic");
macfb_setpalette = civic_setpalette;
civic_cmap_regs = ioremap(CIVIC_BASE, 0x1000);
break;
/*
* Assorted weirdos
* We think this may be like the LC II
*/
case MAC_MODEL_LC:
strcpy(macfb_fix.id, "LC");
if (vidtest) {
macfb_setpalette = v8_brazil_setpalette;
v8_brazil_cmap_regs =
ioremap(DAC_BASE, 0x1000);
}
break;
/*
* We think this may be like the LC II
*/
case MAC_MODEL_CCL:
strcpy(macfb_fix.id, "Color Classic");
if (vidtest) {
macfb_setpalette = v8_brazil_setpalette;
v8_brazil_cmap_regs =
ioremap(DAC_BASE, 0x1000);
}
break;
/*
* And we *do* mean "weirdos"
*/
case MAC_MODEL_TV:
strcpy(macfb_fix.id, "Mac TV");
break;
/*
* These don't have colour, so no need to worry
*/
case MAC_MODEL_SE30:
case MAC_MODEL_CLII:
strcpy(macfb_fix.id, "Monochrome");
break;
/*
* Powerbooks are particularly difficult. Many of
* them have separate framebuffers for external and
* internal video, which is admittedly pretty cool,
* but will be a bit of a headache to support here.
* Also, many of them are grayscale, and we don't
* really support that.
*/
/*
* Slot 0 ROM says TIM. No external video. B&W.
*/
case MAC_MODEL_PB140:
case MAC_MODEL_PB145:
case MAC_MODEL_PB170:
strcpy(macfb_fix.id, "DDC");
break;
/*
* Internal is GSC, External (if present) is ViSC
*/
case MAC_MODEL_PB150: /* no external video */
case MAC_MODEL_PB160:
case MAC_MODEL_PB165:
case MAC_MODEL_PB180:
case MAC_MODEL_PB210:
case MAC_MODEL_PB230:
strcpy(macfb_fix.id, "GSC");
break;
/*
* Internal is TIM, External is ViSC
*/
case MAC_MODEL_PB165C:
case MAC_MODEL_PB180C:
strcpy(macfb_fix.id, "TIM");
break;
/*
* Internal is CSC, External is Keystone+Ariel.
*/
case MAC_MODEL_PB190: /* external video is optional */
case MAC_MODEL_PB520:
case MAC_MODEL_PB250:
case MAC_MODEL_PB270C:
case MAC_MODEL_PB280:
case MAC_MODEL_PB280C:
strcpy(macfb_fix.id, "CSC");
macfb_setpalette = csc_setpalette;
csc_cmap_regs = ioremap(CSC_BASE, 0x1000);
break;
default:
strcpy(macfb_fix.id, "Unknown");
break;
}
fb_info.fbops = &macfb_ops;
fb_info.var = macfb_defined;
fb_info.fix = macfb_fix;
fb_info.pseudo_palette = pseudo_palette;
err = fb_alloc_cmap(&fb_info.cmap, video_cmap_len, 0);
if (err)
goto fail_unmap;
err = register_framebuffer(&fb_info);
if (err)
goto fail_dealloc;
fb_info(&fb_info, "%s frame buffer device\n", fb_info.fix.id);
return 0;
fail_dealloc:
fb_dealloc_cmap(&fb_info.cmap);
fail_unmap:
iounmap(fb_info.screen_base);
iounmap_macfb();
return err;
}
module_init(macfb_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/macfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* A framebuffer driver for VBE 2.0+ compliant video cards
*
* (c) 2007 Michal Januszewski <[email protected]>
* Loosely based upon the vesafb driver.
*
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/init.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/skbuff.h>
#include <linux/timer.h>
#include <linux/completion.h>
#include <linux/connector.h>
#include <linux/random.h>
#include <linux/platform_device.h>
#include <linux/limits.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <video/edid.h>
#include <video/uvesafb.h>
#ifdef CONFIG_X86
#include <video/vga.h>
#endif
#include "edid.h"
static struct cb_id uvesafb_cn_id = {
.idx = CN_IDX_V86D,
.val = CN_VAL_V86D_UVESAFB
};
static char v86d_path[PATH_MAX] = "/sbin/v86d";
static char v86d_started; /* has v86d been started by uvesafb? */
static const struct fb_fix_screeninfo uvesafb_fix = {
.id = "VESA VGA",
.type = FB_TYPE_PACKED_PIXELS,
.accel = FB_ACCEL_NONE,
.visual = FB_VISUAL_TRUECOLOR,
};
static int mtrr = 3; /* enable mtrr by default */
static bool blank = true; /* enable blanking by default */
static int ypan = 1; /* 0: scroll, 1: ypan, 2: ywrap */
static bool pmi_setpal = true; /* use PMI for palette changes */
static bool nocrtc; /* ignore CRTC settings */
static bool noedid; /* don't try DDC transfers */
static int vram_remap; /* set amt. of memory to be used */
static int vram_total; /* set total amount of memory */
static u16 maxclk; /* maximum pixel clock */
static u16 maxvf; /* maximum vertical frequency */
static u16 maxhf; /* maximum horizontal frequency */
static u16 vbemode; /* force use of a specific VBE mode */
static char *mode_option;
static u8 dac_width = 6;
static struct uvesafb_ktask *uvfb_tasks[UVESAFB_TASKS_MAX];
static DEFINE_MUTEX(uvfb_lock);
/*
* A handler for replies from userspace.
*
* Make sure each message passes consistency checks and if it does,
* find the kernel part of the task struct, copy the registers and
* the buffer contents and then complete the task.
*/
static void uvesafb_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp)
{
struct uvesafb_task *utask;
struct uvesafb_ktask *task;
if (!capable(CAP_SYS_ADMIN))
return;
if (msg->seq >= UVESAFB_TASKS_MAX)
return;
mutex_lock(&uvfb_lock);
task = uvfb_tasks[msg->seq];
if (!task || msg->ack != task->ack) {
mutex_unlock(&uvfb_lock);
return;
}
utask = (struct uvesafb_task *)msg->data;
/* Sanity checks for the buffer length. */
if (task->t.buf_len < utask->buf_len ||
utask->buf_len > msg->len - sizeof(*utask)) {
mutex_unlock(&uvfb_lock);
return;
}
uvfb_tasks[msg->seq] = NULL;
mutex_unlock(&uvfb_lock);
memcpy(&task->t, utask, sizeof(*utask));
if (task->t.buf_len && task->buf)
memcpy(task->buf, utask + 1, task->t.buf_len);
complete(task->done);
return;
}
static int uvesafb_helper_start(void)
{
char *envp[] = {
"HOME=/",
"PATH=/sbin:/bin",
NULL,
};
char *argv[] = {
v86d_path,
NULL,
};
return call_usermodehelper(v86d_path, argv, envp, UMH_WAIT_PROC);
}
/*
* Execute a uvesafb task.
*
* Returns 0 if the task is executed successfully.
*
* A message sent to the userspace consists of the uvesafb_task
* struct and (optionally) a buffer. The uvesafb_task struct is
* a simplified version of uvesafb_ktask (its kernel counterpart)
* containing only the register values, flags and the length of
* the buffer.
*
* Each message is assigned a sequence number (increased linearly)
* and a random ack number. The sequence number is used as a key
* for the uvfb_tasks array which holds pointers to uvesafb_ktask
* structs for all requests.
*/
static int uvesafb_exec(struct uvesafb_ktask *task)
{
static int seq;
struct cn_msg *m;
int err;
int len = sizeof(task->t) + task->t.buf_len;
/*
* Check whether the message isn't longer than the maximum
* allowed by connector.
*/
if (sizeof(*m) + len > CONNECTOR_MAX_MSG_SIZE) {
pr_warn("message too long (%d), can't execute task\n",
(int)(sizeof(*m) + len));
return -E2BIG;
}
m = kzalloc(sizeof(*m) + len, GFP_KERNEL);
if (!m)
return -ENOMEM;
init_completion(task->done);
memcpy(&m->id, &uvesafb_cn_id, sizeof(m->id));
m->seq = seq;
m->len = len;
m->ack = get_random_u32();
/* uvesafb_task structure */
memcpy(m + 1, &task->t, sizeof(task->t));
/* Buffer */
memcpy((u8 *)(m + 1) + sizeof(task->t), task->buf, task->t.buf_len);
/*
* Save the message ack number so that we can find the kernel
* part of this task when a reply is received from userspace.
*/
task->ack = m->ack;
mutex_lock(&uvfb_lock);
/* If all slots are taken -- bail out. */
if (uvfb_tasks[seq]) {
mutex_unlock(&uvfb_lock);
err = -EBUSY;
goto out;
}
/* Save a pointer to the kernel part of the task struct. */
uvfb_tasks[seq] = task;
mutex_unlock(&uvfb_lock);
err = cn_netlink_send(m, 0, 0, GFP_KERNEL);
if (err == -ESRCH) {
/*
* Try to start the userspace helper if sending
* the request failed the first time.
*/
err = uvesafb_helper_start();
if (err) {
pr_err("failed to execute %s\n", v86d_path);
pr_err("make sure that the v86d helper is installed and executable\n");
} else {
v86d_started = 1;
err = cn_netlink_send(m, 0, 0, gfp_any());
if (err == -ENOBUFS)
err = 0;
}
} else if (err == -ENOBUFS)
err = 0;
if (!err && !(task->t.flags & TF_EXIT))
err = !wait_for_completion_timeout(task->done,
msecs_to_jiffies(UVESAFB_TIMEOUT));
mutex_lock(&uvfb_lock);
uvfb_tasks[seq] = NULL;
mutex_unlock(&uvfb_lock);
seq++;
if (seq >= UVESAFB_TASKS_MAX)
seq = 0;
out:
kfree(m);
return err;
}
/*
* Free a uvesafb_ktask struct.
*/
static void uvesafb_free(struct uvesafb_ktask *task)
{
if (task) {
kfree(task->done);
kfree(task);
}
}
/*
* Prepare a uvesafb_ktask struct to be used again.
*/
static void uvesafb_reset(struct uvesafb_ktask *task)
{
struct completion *cpl = task->done;
memset(task, 0, sizeof(*task));
task->done = cpl;
}
/*
* Allocate and prepare a uvesafb_ktask struct.
*/
static struct uvesafb_ktask *uvesafb_prep(void)
{
struct uvesafb_ktask *task;
task = kzalloc(sizeof(*task), GFP_KERNEL);
if (task) {
task->done = kzalloc(sizeof(*task->done), GFP_KERNEL);
if (!task->done) {
kfree(task);
task = NULL;
}
}
return task;
}
static void uvesafb_setup_var(struct fb_var_screeninfo *var,
struct fb_info *info, struct vbe_mode_ib *mode)
{
struct uvesafb_par *par = info->par;
var->vmode = FB_VMODE_NONINTERLACED;
var->sync = FB_SYNC_VERT_HIGH_ACT;
var->xres = mode->x_res;
var->yres = mode->y_res;
var->xres_virtual = mode->x_res;
var->yres_virtual = (par->ypan) ?
info->fix.smem_len / mode->bytes_per_scan_line :
mode->y_res;
var->xoffset = 0;
var->yoffset = 0;
var->bits_per_pixel = mode->bits_per_pixel;
if (var->bits_per_pixel == 15)
var->bits_per_pixel = 16;
if (var->bits_per_pixel > 8) {
var->red.offset = mode->red_off;
var->red.length = mode->red_len;
var->green.offset = mode->green_off;
var->green.length = mode->green_len;
var->blue.offset = mode->blue_off;
var->blue.length = mode->blue_len;
var->transp.offset = mode->rsvd_off;
var->transp.length = mode->rsvd_len;
} else {
var->red.offset = 0;
var->green.offset = 0;
var->blue.offset = 0;
var->transp.offset = 0;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.length = 0;
}
}
static int uvesafb_vbe_find_mode(struct uvesafb_par *par,
int xres, int yres, int depth, unsigned char flags)
{
int i, match = -1, h = 0, d = 0x7fffffff;
for (i = 0; i < par->vbe_modes_cnt; i++) {
h = abs(par->vbe_modes[i].x_res - xres) +
abs(par->vbe_modes[i].y_res - yres) +
abs(depth - par->vbe_modes[i].depth);
/*
* We have an exact match in terms of resolution
* and depth.
*/
if (h == 0)
return i;
if (h < d || (h == d && par->vbe_modes[i].depth > depth)) {
d = h;
match = i;
}
}
i = 1;
if (flags & UVESAFB_EXACT_DEPTH &&
par->vbe_modes[match].depth != depth)
i = 0;
if (flags & UVESAFB_EXACT_RES && d > 24)
i = 0;
if (i != 0)
return match;
else
return -1;
}
static u8 *uvesafb_vbe_state_save(struct uvesafb_par *par)
{
struct uvesafb_ktask *task;
u8 *state;
int err;
if (!par->vbe_state_size)
return NULL;
state = kmalloc(par->vbe_state_size, GFP_KERNEL);
if (!state)
return ERR_PTR(-ENOMEM);
task = uvesafb_prep();
if (!task) {
kfree(state);
return NULL;
}
task->t.regs.eax = 0x4f04;
task->t.regs.ecx = 0x000f;
task->t.regs.edx = 0x0001;
task->t.flags = TF_BUF_RET | TF_BUF_ESBX;
task->t.buf_len = par->vbe_state_size;
task->buf = state;
err = uvesafb_exec(task);
if (err || (task->t.regs.eax & 0xffff) != 0x004f) {
pr_warn("VBE get state call failed (eax=0x%x, err=%d)\n",
task->t.regs.eax, err);
kfree(state);
state = NULL;
}
uvesafb_free(task);
return state;
}
static void uvesafb_vbe_state_restore(struct uvesafb_par *par, u8 *state_buf)
{
struct uvesafb_ktask *task;
int err;
if (!state_buf)
return;
task = uvesafb_prep();
if (!task)
return;
task->t.regs.eax = 0x4f04;
task->t.regs.ecx = 0x000f;
task->t.regs.edx = 0x0002;
task->t.buf_len = par->vbe_state_size;
task->t.flags = TF_BUF_ESBX;
task->buf = state_buf;
err = uvesafb_exec(task);
if (err || (task->t.regs.eax & 0xffff) != 0x004f)
pr_warn("VBE state restore call failed (eax=0x%x, err=%d)\n",
task->t.regs.eax, err);
uvesafb_free(task);
}
static int uvesafb_vbe_getinfo(struct uvesafb_ktask *task,
struct uvesafb_par *par)
{
int err;
task->t.regs.eax = 0x4f00;
task->t.flags = TF_VBEIB;
task->t.buf_len = sizeof(struct vbe_ib);
task->buf = &par->vbe_ib;
memcpy(par->vbe_ib.vbe_signature, "VBE2", 4);
err = uvesafb_exec(task);
if (err || (task->t.regs.eax & 0xffff) != 0x004f) {
pr_err("Getting VBE info block failed (eax=0x%x, err=%d)\n",
(u32)task->t.regs.eax, err);
return -EINVAL;
}
if (par->vbe_ib.vbe_version < 0x0200) {
pr_err("Sorry, pre-VBE 2.0 cards are not supported\n");
return -EINVAL;
}
if (!par->vbe_ib.mode_list_ptr) {
pr_err("Missing mode list!\n");
return -EINVAL;
}
pr_info("");
/*
* Convert string pointers and the mode list pointer into
* usable addresses. Print informational messages about the
* video adapter and its vendor.
*/
if (par->vbe_ib.oem_vendor_name_ptr)
pr_cont("%s, ",
((char *)task->buf) + par->vbe_ib.oem_vendor_name_ptr);
if (par->vbe_ib.oem_product_name_ptr)
pr_cont("%s, ",
((char *)task->buf) + par->vbe_ib.oem_product_name_ptr);
if (par->vbe_ib.oem_product_rev_ptr)
pr_cont("%s, ",
((char *)task->buf) + par->vbe_ib.oem_product_rev_ptr);
if (par->vbe_ib.oem_string_ptr)
pr_cont("OEM: %s, ",
((char *)task->buf) + par->vbe_ib.oem_string_ptr);
pr_cont("VBE v%d.%d\n",
(par->vbe_ib.vbe_version & 0xff00) >> 8,
par->vbe_ib.vbe_version & 0xff);
return 0;
}
static int uvesafb_vbe_getmodes(struct uvesafb_ktask *task,
struct uvesafb_par *par)
{
int off = 0, err;
u16 *mode;
par->vbe_modes_cnt = 0;
/* Count available modes. */
mode = (u16 *) (((u8 *)&par->vbe_ib) + par->vbe_ib.mode_list_ptr);
while (*mode != 0xffff) {
par->vbe_modes_cnt++;
mode++;
}
par->vbe_modes = kcalloc(par->vbe_modes_cnt,
sizeof(struct vbe_mode_ib),
GFP_KERNEL);
if (!par->vbe_modes)
return -ENOMEM;
/* Get info about all available modes. */
mode = (u16 *) (((u8 *)&par->vbe_ib) + par->vbe_ib.mode_list_ptr);
while (*mode != 0xffff) {
struct vbe_mode_ib *mib;
uvesafb_reset(task);
task->t.regs.eax = 0x4f01;
task->t.regs.ecx = (u32) *mode;
task->t.flags = TF_BUF_RET | TF_BUF_ESDI;
task->t.buf_len = sizeof(struct vbe_mode_ib);
task->buf = par->vbe_modes + off;
err = uvesafb_exec(task);
if (err || (task->t.regs.eax & 0xffff) != 0x004f) {
pr_warn("Getting mode info block for mode 0x%x failed (eax=0x%x, err=%d)\n",
*mode, (u32)task->t.regs.eax, err);
mode++;
par->vbe_modes_cnt--;
continue;
}
mib = task->buf;
mib->mode_id = *mode;
/*
* We only want modes that are supported with the current
* hardware configuration, color, graphics and that have
* support for the LFB.
*/
if ((mib->mode_attr & VBE_MODE_MASK) == VBE_MODE_MASK &&
mib->bits_per_pixel >= 8)
off++;
else
par->vbe_modes_cnt--;
mode++;
mib->depth = mib->red_len + mib->green_len + mib->blue_len;
/*
* Handle 8bpp modes and modes with broken color component
* lengths.
*/
if (mib->depth == 0 || (mib->depth == 24 &&
mib->bits_per_pixel == 32))
mib->depth = mib->bits_per_pixel;
}
if (par->vbe_modes_cnt > 0)
return 0;
else
return -EINVAL;
}
/*
* The Protected Mode Interface is 32-bit x86 code, so we only run it on
* x86 and not x86_64.
*/
#ifdef CONFIG_X86_32
static int uvesafb_vbe_getpmi(struct uvesafb_ktask *task,
struct uvesafb_par *par)
{
int i, err;
uvesafb_reset(task);
task->t.regs.eax = 0x4f0a;
task->t.regs.ebx = 0x0;
err = uvesafb_exec(task);
if (err)
return err;
if ((task->t.regs.eax & 0xffff) != 0x4f || task->t.regs.es < 0xc000) {
par->pmi_setpal = par->ypan = 0;
} else {
par->pmi_base = (u16 *)phys_to_virt(((u32)task->t.regs.es << 4)
+ task->t.regs.edi);
par->pmi_start = (u8 *)par->pmi_base + par->pmi_base[1];
par->pmi_pal = (u8 *)par->pmi_base + par->pmi_base[2];
pr_info("protected mode interface info at %04x:%04x\n",
(u16)task->t.regs.es, (u16)task->t.regs.edi);
pr_info("pmi: set display start = %p, set palette = %p\n",
par->pmi_start, par->pmi_pal);
if (par->pmi_base[3]) {
pr_info("pmi: ports =");
for (i = par->pmi_base[3]/2;
par->pmi_base[i] != 0xffff; i++)
pr_cont(" %x", par->pmi_base[i]);
pr_cont("\n");
if (par->pmi_base[i] != 0xffff) {
pr_info("can't handle memory requests, pmi disabled\n");
par->ypan = par->pmi_setpal = 0;
}
}
}
return 0;
}
#endif /* CONFIG_X86_32 */
/*
* Check whether a video mode is supported by the Video BIOS and is
* compatible with the monitor limits.
*/
static int uvesafb_is_valid_mode(struct fb_videomode *mode,
struct fb_info *info)
{
if (info->monspecs.gtf) {
fb_videomode_to_var(&info->var, mode);
if (fb_validate_mode(&info->var, info))
return 0;
}
if (uvesafb_vbe_find_mode(info->par, mode->xres, mode->yres, 8,
UVESAFB_EXACT_RES) == -1)
return 0;
return 1;
}
static int uvesafb_vbe_getedid(struct uvesafb_ktask *task, struct fb_info *info)
{
struct uvesafb_par *par = info->par;
int err = 0;
if (noedid || par->vbe_ib.vbe_version < 0x0300)
return -EINVAL;
task->t.regs.eax = 0x4f15;
task->t.regs.ebx = 0;
task->t.regs.ecx = 0;
task->t.buf_len = 0;
task->t.flags = 0;
err = uvesafb_exec(task);
if ((task->t.regs.eax & 0xffff) != 0x004f || err)
return -EINVAL;
if ((task->t.regs.ebx & 0x3) == 3) {
pr_info("VBIOS/hardware supports both DDC1 and DDC2 transfers\n");
} else if ((task->t.regs.ebx & 0x3) == 2) {
pr_info("VBIOS/hardware supports DDC2 transfers\n");
} else if ((task->t.regs.ebx & 0x3) == 1) {
pr_info("VBIOS/hardware supports DDC1 transfers\n");
} else {
pr_info("VBIOS/hardware doesn't support DDC transfers\n");
return -EINVAL;
}
task->t.regs.eax = 0x4f15;
task->t.regs.ebx = 1;
task->t.regs.ecx = task->t.regs.edx = 0;
task->t.flags = TF_BUF_RET | TF_BUF_ESDI;
task->t.buf_len = EDID_LENGTH;
task->buf = kzalloc(EDID_LENGTH, GFP_KERNEL);
if (!task->buf)
return -ENOMEM;
err = uvesafb_exec(task);
if ((task->t.regs.eax & 0xffff) == 0x004f && !err) {
fb_edid_to_monspecs(task->buf, &info->monspecs);
if (info->monspecs.vfmax && info->monspecs.hfmax) {
/*
* If the maximum pixel clock wasn't specified in
* the EDID block, set it to 300 MHz.
*/
if (info->monspecs.dclkmax == 0)
info->monspecs.dclkmax = 300 * 1000000;
info->monspecs.gtf = 1;
}
} else {
err = -EINVAL;
}
kfree(task->buf);
return err;
}
static void uvesafb_vbe_getmonspecs(struct uvesafb_ktask *task,
struct fb_info *info)
{
struct uvesafb_par *par = info->par;
int i;
memset(&info->monspecs, 0, sizeof(info->monspecs));
/*
* If we don't get all necessary data from the EDID block,
* mark it as incompatible with the GTF and set nocrtc so
* that we always use the default BIOS refresh rate.
*/
if (uvesafb_vbe_getedid(task, info)) {
info->monspecs.gtf = 0;
par->nocrtc = 1;
}
/* Kernel command line overrides. */
if (maxclk)
info->monspecs.dclkmax = maxclk * 1000000;
if (maxvf)
info->monspecs.vfmax = maxvf;
if (maxhf)
info->monspecs.hfmax = maxhf * 1000;
/*
* In case DDC transfers are not supported, the user can provide
* monitor limits manually. Lower limits are set to "safe" values.
*/
if (info->monspecs.gtf == 0 && maxclk && maxvf && maxhf) {
info->monspecs.dclkmin = 0;
info->monspecs.vfmin = 60;
info->monspecs.hfmin = 29000;
info->monspecs.gtf = 1;
par->nocrtc = 0;
}
if (info->monspecs.gtf)
pr_info("monitor limits: vf = %d Hz, hf = %d kHz, clk = %d MHz\n",
info->monspecs.vfmax,
(int)(info->monspecs.hfmax / 1000),
(int)(info->monspecs.dclkmax / 1000000));
else
pr_info("no monitor limits have been set, default refresh rate will be used\n");
/* Add VBE modes to the modelist. */
for (i = 0; i < par->vbe_modes_cnt; i++) {
struct fb_var_screeninfo var;
struct vbe_mode_ib *mode;
struct fb_videomode vmode;
mode = &par->vbe_modes[i];
memset(&var, 0, sizeof(var));
var.xres = mode->x_res;
var.yres = mode->y_res;
fb_get_mode(FB_VSYNCTIMINGS | FB_IGNOREMON, 60, &var, info);
fb_var_to_videomode(&vmode, &var);
fb_add_videomode(&vmode, &info->modelist);
}
/* Add valid VESA modes to our modelist. */
for (i = 0; i < VESA_MODEDB_SIZE; i++) {
if (uvesafb_is_valid_mode((struct fb_videomode *)
&vesa_modes[i], info))
fb_add_videomode(&vesa_modes[i], &info->modelist);
}
for (i = 0; i < info->monspecs.modedb_len; i++) {
if (uvesafb_is_valid_mode(&info->monspecs.modedb[i], info))
fb_add_videomode(&info->monspecs.modedb[i],
&info->modelist);
}
return;
}
static void uvesafb_vbe_getstatesize(struct uvesafb_ktask *task,
struct uvesafb_par *par)
{
int err;
uvesafb_reset(task);
/*
* Get the VBE state buffer size. We want all available
* hardware state data (CL = 0x0f).
*/
task->t.regs.eax = 0x4f04;
task->t.regs.ecx = 0x000f;
task->t.regs.edx = 0x0000;
task->t.flags = 0;
err = uvesafb_exec(task);
if (err || (task->t.regs.eax & 0xffff) != 0x004f) {
pr_warn("VBE state buffer size cannot be determined (eax=0x%x, err=%d)\n",
task->t.regs.eax, err);
par->vbe_state_size = 0;
return;
}
par->vbe_state_size = 64 * (task->t.regs.ebx & 0xffff);
}
static int uvesafb_vbe_init(struct fb_info *info)
{
struct uvesafb_ktask *task = NULL;
struct uvesafb_par *par = info->par;
int err;
task = uvesafb_prep();
if (!task)
return -ENOMEM;
err = uvesafb_vbe_getinfo(task, par);
if (err)
goto out;
err = uvesafb_vbe_getmodes(task, par);
if (err)
goto out;
par->nocrtc = nocrtc;
#ifdef CONFIG_X86_32
par->pmi_setpal = pmi_setpal;
par->ypan = ypan;
if (par->pmi_setpal || par->ypan) {
if (__supported_pte_mask & _PAGE_NX) {
par->pmi_setpal = par->ypan = 0;
pr_warn("NX protection is active, better not use the PMI\n");
} else {
uvesafb_vbe_getpmi(task, par);
}
}
#else
/* The protected mode interface is not available on non-x86. */
par->pmi_setpal = par->ypan = 0;
#endif
INIT_LIST_HEAD(&info->modelist);
uvesafb_vbe_getmonspecs(task, info);
uvesafb_vbe_getstatesize(task, par);
out: uvesafb_free(task);
return err;
}
static int uvesafb_vbe_init_mode(struct fb_info *info)
{
struct list_head *pos;
struct fb_modelist *modelist;
struct fb_videomode *mode;
struct uvesafb_par *par = info->par;
int i, modeid;
/* Has the user requested a specific VESA mode? */
if (vbemode) {
for (i = 0; i < par->vbe_modes_cnt; i++) {
if (par->vbe_modes[i].mode_id == vbemode) {
modeid = i;
uvesafb_setup_var(&info->var, info,
&par->vbe_modes[modeid]);
fb_get_mode(FB_VSYNCTIMINGS | FB_IGNOREMON, 60,
&info->var, info);
/*
* With pixclock set to 0, the default BIOS
* timings will be used in set_par().
*/
info->var.pixclock = 0;
goto gotmode;
}
}
pr_info("requested VBE mode 0x%x is unavailable\n", vbemode);
vbemode = 0;
}
/* Count the modes in the modelist */
i = 0;
list_for_each(pos, &info->modelist)
i++;
/*
* Convert the modelist into a modedb so that we can use it with
* fb_find_mode().
*/
mode = kcalloc(i, sizeof(*mode), GFP_KERNEL);
if (mode) {
i = 0;
list_for_each(pos, &info->modelist) {
modelist = list_entry(pos, struct fb_modelist, list);
mode[i] = modelist->mode;
i++;
}
if (!mode_option)
mode_option = UVESAFB_DEFAULT_MODE;
i = fb_find_mode(&info->var, info, mode_option, mode, i,
NULL, 8);
kfree(mode);
}
/* fb_find_mode() failed */
if (i == 0) {
info->var.xres = 640;
info->var.yres = 480;
mode = (struct fb_videomode *)
fb_find_best_mode(&info->var, &info->modelist);
if (mode) {
fb_videomode_to_var(&info->var, mode);
} else {
modeid = par->vbe_modes[0].mode_id;
uvesafb_setup_var(&info->var, info,
&par->vbe_modes[modeid]);
fb_get_mode(FB_VSYNCTIMINGS | FB_IGNOREMON, 60,
&info->var, info);
goto gotmode;
}
}
/* Look for a matching VBE mode. */
modeid = uvesafb_vbe_find_mode(par, info->var.xres, info->var.yres,
info->var.bits_per_pixel, UVESAFB_EXACT_RES);
if (modeid == -1)
return -EINVAL;
uvesafb_setup_var(&info->var, info, &par->vbe_modes[modeid]);
gotmode:
/*
* If we are not VBE3.0+ compliant, we're done -- the BIOS will
* ignore our timings anyway.
*/
if (par->vbe_ib.vbe_version < 0x0300 || par->nocrtc)
fb_get_mode(FB_VSYNCTIMINGS | FB_IGNOREMON, 60,
&info->var, info);
return modeid;
}
static int uvesafb_setpalette(struct uvesafb_pal_entry *entries, int count,
int start, struct fb_info *info)
{
struct uvesafb_ktask *task;
#ifdef CONFIG_X86
struct uvesafb_par *par = info->par;
int i = par->mode_idx;
#endif
int err = 0;
/*
* We support palette modifications for 8 bpp modes only, so
* there can never be more than 256 entries.
*/
if (start + count > 256)
return -EINVAL;
#ifdef CONFIG_X86
/* Use VGA registers if mode is VGA-compatible. */
if (i >= 0 && i < par->vbe_modes_cnt &&
par->vbe_modes[i].mode_attr & VBE_MODE_VGACOMPAT) {
for (i = 0; i < count; i++) {
outb_p(start + i, dac_reg);
outb_p(entries[i].red, dac_val);
outb_p(entries[i].green, dac_val);
outb_p(entries[i].blue, dac_val);
}
}
#ifdef CONFIG_X86_32
else if (par->pmi_setpal) {
__asm__ __volatile__(
"call *(%%esi)"
: /* no return value */
: "a" (0x4f09), /* EAX */
"b" (0), /* EBX */
"c" (count), /* ECX */
"d" (start), /* EDX */
"D" (entries), /* EDI */
"S" (&par->pmi_pal)); /* ESI */
}
#endif /* CONFIG_X86_32 */
else
#endif /* CONFIG_X86 */
{
task = uvesafb_prep();
if (!task)
return -ENOMEM;
task->t.regs.eax = 0x4f09;
task->t.regs.ebx = 0x0;
task->t.regs.ecx = count;
task->t.regs.edx = start;
task->t.flags = TF_BUF_ESDI;
task->t.buf_len = sizeof(struct uvesafb_pal_entry) * count;
task->buf = entries;
err = uvesafb_exec(task);
if ((task->t.regs.eax & 0xffff) != 0x004f)
err = 1;
uvesafb_free(task);
}
return err;
}
static int uvesafb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct uvesafb_pal_entry entry;
int shift = 16 - dac_width;
int err = 0;
if (regno >= info->cmap.len)
return -EINVAL;
if (info->var.bits_per_pixel == 8) {
entry.red = red >> shift;
entry.green = green >> shift;
entry.blue = blue >> shift;
entry.pad = 0;
err = uvesafb_setpalette(&entry, 1, regno, info);
} else if (regno < 16) {
switch (info->var.bits_per_pixel) {
case 16:
if (info->var.red.offset == 10) {
/* 1:5:5:5 */
((u32 *) (info->pseudo_palette))[regno] =
((red & 0xf800) >> 1) |
((green & 0xf800) >> 6) |
((blue & 0xf800) >> 11);
} else {
/* 0:5:6:5 */
((u32 *) (info->pseudo_palette))[regno] =
((red & 0xf800) ) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
}
break;
case 24:
case 32:
red >>= 8;
green >>= 8;
blue >>= 8;
((u32 *)(info->pseudo_palette))[regno] =
(red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
break;
}
}
return err;
}
static int uvesafb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
{
struct uvesafb_pal_entry *entries;
int shift = 16 - dac_width;
int i, err = 0;
if (info->var.bits_per_pixel == 8) {
if (cmap->start + cmap->len > info->cmap.start +
info->cmap.len || cmap->start < info->cmap.start)
return -EINVAL;
entries = kmalloc_array(cmap->len, sizeof(*entries),
GFP_KERNEL);
if (!entries)
return -ENOMEM;
for (i = 0; i < cmap->len; i++) {
entries[i].red = cmap->red[i] >> shift;
entries[i].green = cmap->green[i] >> shift;
entries[i].blue = cmap->blue[i] >> shift;
entries[i].pad = 0;
}
err = uvesafb_setpalette(entries, cmap->len, cmap->start, info);
kfree(entries);
} else {
/*
* For modes with bpp > 8, we only set the pseudo palette in
* the fb_info struct. We rely on uvesafb_setcolreg to do all
* sanity checking.
*/
for (i = 0; i < cmap->len; i++) {
err |= uvesafb_setcolreg(cmap->start + i, cmap->red[i],
cmap->green[i], cmap->blue[i],
0, info);
}
}
return err;
}
static int uvesafb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
#ifdef CONFIG_X86_32
int offset;
struct uvesafb_par *par = info->par;
offset = (var->yoffset * info->fix.line_length + var->xoffset) / 4;
/*
* It turns out it's not the best idea to do panning via vm86,
* so we only allow it if we have a PMI.
*/
if (par->pmi_start) {
__asm__ __volatile__(
"call *(%%edi)"
: /* no return value */
: "a" (0x4f07), /* EAX */
"b" (0), /* EBX */
"c" (offset), /* ECX */
"d" (offset >> 16), /* EDX */
"D" (&par->pmi_start)); /* EDI */
}
#endif
return 0;
}
static int uvesafb_blank(int blank, struct fb_info *info)
{
struct uvesafb_ktask *task;
int err = 1;
#ifdef CONFIG_X86
struct uvesafb_par *par = info->par;
if (par->vbe_ib.capabilities & VBE_CAP_VGACOMPAT) {
int loop = 10000;
u8 seq = 0, crtc17 = 0;
if (blank == FB_BLANK_POWERDOWN) {
seq = 0x20;
crtc17 = 0x00;
err = 0;
} else {
seq = 0x00;
crtc17 = 0x80;
err = (blank == FB_BLANK_UNBLANK) ? 0 : -EINVAL;
}
vga_wseq(NULL, 0x00, 0x01);
seq |= vga_rseq(NULL, 0x01) & ~0x20;
vga_wseq(NULL, 0x00, seq);
crtc17 |= vga_rcrt(NULL, 0x17) & ~0x80;
while (loop--);
vga_wcrt(NULL, 0x17, crtc17);
vga_wseq(NULL, 0x00, 0x03);
} else
#endif /* CONFIG_X86 */
{
task = uvesafb_prep();
if (!task)
return -ENOMEM;
task->t.regs.eax = 0x4f10;
switch (blank) {
case FB_BLANK_UNBLANK:
task->t.regs.ebx = 0x0001;
break;
case FB_BLANK_NORMAL:
task->t.regs.ebx = 0x0101; /* standby */
break;
case FB_BLANK_POWERDOWN:
task->t.regs.ebx = 0x0401; /* powerdown */
break;
default:
goto out;
}
err = uvesafb_exec(task);
if (err || (task->t.regs.eax & 0xffff) != 0x004f)
err = 1;
out: uvesafb_free(task);
}
return err;
}
static int uvesafb_open(struct fb_info *info, int user)
{
struct uvesafb_par *par = info->par;
int cnt = atomic_read(&par->ref_count);
u8 *buf = NULL;
if (!cnt && par->vbe_state_size) {
buf = uvesafb_vbe_state_save(par);
if (IS_ERR(buf)) {
pr_warn("save hardware state failed, error code is %ld!\n",
PTR_ERR(buf));
} else {
par->vbe_state_orig = buf;
}
}
atomic_inc(&par->ref_count);
return 0;
}
static int uvesafb_release(struct fb_info *info, int user)
{
struct uvesafb_ktask *task = NULL;
struct uvesafb_par *par = info->par;
int cnt = atomic_read(&par->ref_count);
if (!cnt)
return -EINVAL;
if (cnt != 1)
goto out;
task = uvesafb_prep();
if (!task)
goto out;
/* First, try to set the standard 80x25 text mode. */
task->t.regs.eax = 0x0003;
uvesafb_exec(task);
/*
* Now try to restore whatever hardware state we might have
* saved when the fb device was first opened.
*/
uvesafb_vbe_state_restore(par, par->vbe_state_orig);
out:
atomic_dec(&par->ref_count);
uvesafb_free(task);
return 0;
}
static int uvesafb_set_par(struct fb_info *info)
{
struct uvesafb_par *par = info->par;
struct uvesafb_ktask *task = NULL;
struct vbe_crtc_ib *crtc = NULL;
struct vbe_mode_ib *mode = NULL;
int i, err = 0, depth = info->var.bits_per_pixel;
if (depth > 8 && depth != 32)
depth = info->var.red.length + info->var.green.length +
info->var.blue.length;
i = uvesafb_vbe_find_mode(par, info->var.xres, info->var.yres, depth,
UVESAFB_EXACT_RES | UVESAFB_EXACT_DEPTH);
if (i >= 0)
mode = &par->vbe_modes[i];
else
return -EINVAL;
task = uvesafb_prep();
if (!task)
return -ENOMEM;
setmode:
task->t.regs.eax = 0x4f02;
task->t.regs.ebx = mode->mode_id | 0x4000; /* use LFB */
if (par->vbe_ib.vbe_version >= 0x0300 && !par->nocrtc &&
info->var.pixclock != 0) {
task->t.regs.ebx |= 0x0800; /* use CRTC data */
task->t.flags = TF_BUF_ESDI;
crtc = kzalloc(sizeof(struct vbe_crtc_ib), GFP_KERNEL);
if (!crtc) {
err = -ENOMEM;
goto out;
}
crtc->horiz_start = info->var.xres + info->var.right_margin;
crtc->horiz_end = crtc->horiz_start + info->var.hsync_len;
crtc->horiz_total = crtc->horiz_end + info->var.left_margin;
crtc->vert_start = info->var.yres + info->var.lower_margin;
crtc->vert_end = crtc->vert_start + info->var.vsync_len;
crtc->vert_total = crtc->vert_end + info->var.upper_margin;
crtc->pixel_clock = PICOS2KHZ(info->var.pixclock) * 1000;
crtc->refresh_rate = (u16)(100 * (crtc->pixel_clock /
(crtc->vert_total * crtc->horiz_total)));
if (info->var.vmode & FB_VMODE_DOUBLE)
crtc->flags |= 0x1;
if (info->var.vmode & FB_VMODE_INTERLACED)
crtc->flags |= 0x2;
if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
crtc->flags |= 0x4;
if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
crtc->flags |= 0x8;
memcpy(&par->crtc, crtc, sizeof(*crtc));
} else {
memset(&par->crtc, 0, sizeof(*crtc));
}
task->t.buf_len = sizeof(struct vbe_crtc_ib);
task->buf = &par->crtc;
err = uvesafb_exec(task);
if (err || (task->t.regs.eax & 0xffff) != 0x004f) {
/*
* The mode switch might have failed because we tried to
* use our own timings. Try again with the default timings.
*/
if (crtc != NULL) {
pr_warn("mode switch failed (eax=0x%x, err=%d) - trying again with default timings\n",
task->t.regs.eax, err);
uvesafb_reset(task);
kfree(crtc);
crtc = NULL;
info->var.pixclock = 0;
goto setmode;
} else {
pr_err("mode switch failed (eax=0x%x, err=%d)\n",
task->t.regs.eax, err);
err = -EINVAL;
goto out;
}
}
par->mode_idx = i;
/* For 8bpp modes, always try to set the DAC to 8 bits. */
if (par->vbe_ib.capabilities & VBE_CAP_CAN_SWITCH_DAC &&
mode->bits_per_pixel <= 8) {
uvesafb_reset(task);
task->t.regs.eax = 0x4f08;
task->t.regs.ebx = 0x0800;
err = uvesafb_exec(task);
if (err || (task->t.regs.eax & 0xffff) != 0x004f ||
((task->t.regs.ebx & 0xff00) >> 8) != 8) {
dac_width = 6;
} else {
dac_width = 8;
}
}
info->fix.visual = (info->var.bits_per_pixel == 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
info->fix.line_length = mode->bytes_per_scan_line;
out:
kfree(crtc);
uvesafb_free(task);
return err;
}
static void uvesafb_check_limits(struct fb_var_screeninfo *var,
struct fb_info *info)
{
const struct fb_videomode *mode;
struct uvesafb_par *par = info->par;
/*
* If pixclock is set to 0, then we're using default BIOS timings
* and thus don't have to perform any checks here.
*/
if (!var->pixclock)
return;
if (par->vbe_ib.vbe_version < 0x0300) {
fb_get_mode(FB_VSYNCTIMINGS | FB_IGNOREMON, 60, var, info);
return;
}
if (!fb_validate_mode(var, info))
return;
mode = fb_find_best_mode(var, &info->modelist);
if (mode) {
if (mode->xres == var->xres && mode->yres == var->yres &&
!(mode->vmode & (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE))) {
fb_videomode_to_var(var, mode);
return;
}
}
if (info->monspecs.gtf && !fb_get_mode(FB_MAXTIMINGS, 0, var, info))
return;
/* Use default refresh rate */
var->pixclock = 0;
}
static int uvesafb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct uvesafb_par *par = info->par;
struct vbe_mode_ib *mode = NULL;
int match = -1;
int depth = var->red.length + var->green.length + var->blue.length;
/*
* Various apps will use bits_per_pixel to set the color depth,
* which is theoretically incorrect, but which we'll try to handle
* here.
*/
if (depth == 0 || abs(depth - var->bits_per_pixel) >= 8)
depth = var->bits_per_pixel;
match = uvesafb_vbe_find_mode(par, var->xres, var->yres, depth,
UVESAFB_EXACT_RES);
if (match == -1)
return -EINVAL;
mode = &par->vbe_modes[match];
uvesafb_setup_var(var, info, mode);
/*
* Check whether we have remapped enough memory for this mode.
* We might be called at an early stage, when we haven't remapped
* any memory yet, in which case we simply skip the check.
*/
if (var->yres * mode->bytes_per_scan_line > info->fix.smem_len
&& info->fix.smem_len)
return -EINVAL;
if ((var->vmode & FB_VMODE_DOUBLE) &&
!(par->vbe_modes[match].mode_attr & 0x100))
var->vmode &= ~FB_VMODE_DOUBLE;
if ((var->vmode & FB_VMODE_INTERLACED) &&
!(par->vbe_modes[match].mode_attr & 0x200))
var->vmode &= ~FB_VMODE_INTERLACED;
uvesafb_check_limits(var, info);
var->xres_virtual = var->xres;
var->yres_virtual = (par->ypan) ?
info->fix.smem_len / mode->bytes_per_scan_line :
var->yres;
return 0;
}
static struct fb_ops uvesafb_ops = {
.owner = THIS_MODULE,
.fb_open = uvesafb_open,
.fb_release = uvesafb_release,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = uvesafb_setcolreg,
.fb_setcmap = uvesafb_setcmap,
.fb_pan_display = uvesafb_pan_display,
.fb_blank = uvesafb_blank,
.fb_check_var = uvesafb_check_var,
.fb_set_par = uvesafb_set_par,
};
static void uvesafb_init_info(struct fb_info *info, struct vbe_mode_ib *mode)
{
unsigned int size_vmode;
unsigned int size_remap;
unsigned int size_total;
struct uvesafb_par *par = info->par;
int i, h;
info->pseudo_palette = ((u8 *)info->par + sizeof(struct uvesafb_par));
info->fix = uvesafb_fix;
info->fix.ypanstep = par->ypan ? 1 : 0;
info->fix.ywrapstep = (par->ypan > 1) ? 1 : 0;
/* Disable blanking if the user requested so. */
if (!blank)
uvesafb_ops.fb_blank = NULL;
/*
* Find out how much IO memory is required for the mode with
* the highest resolution.
*/
size_remap = 0;
for (i = 0; i < par->vbe_modes_cnt; i++) {
h = par->vbe_modes[i].bytes_per_scan_line *
par->vbe_modes[i].y_res;
if (h > size_remap)
size_remap = h;
}
size_remap *= 2;
/*
* size_vmode -- that is the amount of memory needed for the
* used video mode, i.e. the minimum amount of
* memory we need.
*/
size_vmode = info->var.yres * mode->bytes_per_scan_line;
/*
* size_total -- all video memory we have. Used for mtrr
* entries, resource allocation and bounds
* checking.
*/
size_total = par->vbe_ib.total_memory * 65536;
if (vram_total)
size_total = vram_total * 1024 * 1024;
if (size_total < size_vmode)
size_total = size_vmode;
/*
* size_remap -- the amount of video memory we are going to
* use for vesafb. With modern cards it is no
* option to simply use size_total as th
* wastes plenty of kernel address space.
*/
if (vram_remap)
size_remap = vram_remap * 1024 * 1024;
if (size_remap < size_vmode)
size_remap = size_vmode;
if (size_remap > size_total)
size_remap = size_total;
info->fix.smem_len = size_remap;
info->fix.smem_start = mode->phys_base_ptr;
/*
* We have to set yres_virtual here because when setup_var() was
* called, smem_len wasn't defined yet.
*/
info->var.yres_virtual = info->fix.smem_len /
mode->bytes_per_scan_line;
if (par->ypan && info->var.yres_virtual > info->var.yres) {
pr_info("scrolling: %s using protected mode interface, yres_virtual=%d\n",
(par->ypan > 1) ? "ywrap" : "ypan",
info->var.yres_virtual);
} else {
pr_info("scrolling: redraw\n");
info->var.yres_virtual = info->var.yres;
par->ypan = 0;
}
info->flags = (par->ypan ? FBINFO_HWACCEL_YPAN : 0);
if (!par->ypan)
uvesafb_ops.fb_pan_display = NULL;
}
static void uvesafb_init_mtrr(struct fb_info *info)
{
struct uvesafb_par *par = info->par;
if (mtrr && !(info->fix.smem_start & (PAGE_SIZE - 1))) {
int temp_size = info->fix.smem_len;
int rc;
/* Find the largest power-of-two */
temp_size = roundup_pow_of_two(temp_size);
/* Try and find a power of two to add */
do {
rc = arch_phys_wc_add(info->fix.smem_start, temp_size);
temp_size >>= 1;
} while (temp_size >= PAGE_SIZE && rc == -EINVAL);
if (rc >= 0)
par->mtrr_handle = rc;
}
}
static void uvesafb_ioremap(struct fb_info *info)
{
info->screen_base = ioremap_wc(info->fix.smem_start, info->fix.smem_len);
}
static ssize_t uvesafb_show_vbe_ver(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct uvesafb_par *par = info->par;
return snprintf(buf, PAGE_SIZE, "%.4x\n", par->vbe_ib.vbe_version);
}
static DEVICE_ATTR(vbe_version, S_IRUGO, uvesafb_show_vbe_ver, NULL);
static ssize_t uvesafb_show_vbe_modes(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct uvesafb_par *par = info->par;
int ret = 0, i;
for (i = 0; i < par->vbe_modes_cnt && ret < PAGE_SIZE; i++) {
ret += scnprintf(buf + ret, PAGE_SIZE - ret,
"%dx%d-%d, 0x%.4x\n",
par->vbe_modes[i].x_res, par->vbe_modes[i].y_res,
par->vbe_modes[i].depth, par->vbe_modes[i].mode_id);
}
return ret;
}
static DEVICE_ATTR(vbe_modes, S_IRUGO, uvesafb_show_vbe_modes, NULL);
static ssize_t uvesafb_show_vendor(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct uvesafb_par *par = info->par;
if (par->vbe_ib.oem_vendor_name_ptr)
return sysfs_emit(buf, "%s\n", (char *)
(&par->vbe_ib) + par->vbe_ib.oem_vendor_name_ptr);
else
return 0;
}
static DEVICE_ATTR(oem_vendor, S_IRUGO, uvesafb_show_vendor, NULL);
static ssize_t uvesafb_show_product_name(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct uvesafb_par *par = info->par;
if (par->vbe_ib.oem_product_name_ptr)
return sysfs_emit(buf, "%s\n", (char *)
(&par->vbe_ib) + par->vbe_ib.oem_product_name_ptr);
else
return 0;
}
static DEVICE_ATTR(oem_product_name, S_IRUGO, uvesafb_show_product_name, NULL);
static ssize_t uvesafb_show_product_rev(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct uvesafb_par *par = info->par;
if (par->vbe_ib.oem_product_rev_ptr)
return sysfs_emit(buf, "%s\n", (char *)
(&par->vbe_ib) + par->vbe_ib.oem_product_rev_ptr);
else
return 0;
}
static DEVICE_ATTR(oem_product_rev, S_IRUGO, uvesafb_show_product_rev, NULL);
static ssize_t uvesafb_show_oem_string(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct uvesafb_par *par = info->par;
if (par->vbe_ib.oem_string_ptr)
return sysfs_emit(buf, "%s\n",
(char *)(&par->vbe_ib) + par->vbe_ib.oem_string_ptr);
else
return 0;
}
static DEVICE_ATTR(oem_string, S_IRUGO, uvesafb_show_oem_string, NULL);
static ssize_t uvesafb_show_nocrtc(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct uvesafb_par *par = info->par;
return sysfs_emit(buf, "%d\n", par->nocrtc);
}
static ssize_t uvesafb_store_nocrtc(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(dev);
struct uvesafb_par *par = info->par;
if (count > 0) {
if (buf[0] == '0')
par->nocrtc = 0;
else
par->nocrtc = 1;
}
return count;
}
static DEVICE_ATTR(nocrtc, S_IRUGO | S_IWUSR, uvesafb_show_nocrtc,
uvesafb_store_nocrtc);
static struct attribute *uvesafb_dev_attrs[] = {
&dev_attr_vbe_version.attr,
&dev_attr_vbe_modes.attr,
&dev_attr_oem_vendor.attr,
&dev_attr_oem_product_name.attr,
&dev_attr_oem_product_rev.attr,
&dev_attr_oem_string.attr,
&dev_attr_nocrtc.attr,
NULL,
};
static const struct attribute_group uvesafb_dev_attgrp = {
.name = NULL,
.attrs = uvesafb_dev_attrs,
};
static int uvesafb_probe(struct platform_device *dev)
{
struct fb_info *info;
struct vbe_mode_ib *mode = NULL;
struct uvesafb_par *par;
int err = 0, i;
info = framebuffer_alloc(sizeof(*par) + sizeof(u32) * 256, &dev->dev);
if (!info)
return -ENOMEM;
par = info->par;
err = uvesafb_vbe_init(info);
if (err) {
pr_err("vbe_init() failed with %d\n", err);
goto out;
}
info->fbops = &uvesafb_ops;
i = uvesafb_vbe_init_mode(info);
if (i < 0) {
err = -EINVAL;
goto out;
} else {
mode = &par->vbe_modes[i];
}
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
err = -ENXIO;
goto out;
}
uvesafb_init_info(info, mode);
if (!request_region(0x3c0, 32, "uvesafb")) {
pr_err("request region 0x3c0-0x3e0 failed\n");
err = -EIO;
goto out_mode;
}
if (!request_mem_region(info->fix.smem_start, info->fix.smem_len,
"uvesafb")) {
pr_err("cannot reserve video memory at 0x%lx\n",
info->fix.smem_start);
err = -EIO;
goto out_reg;
}
uvesafb_init_mtrr(info);
uvesafb_ioremap(info);
if (!info->screen_base) {
pr_err("abort, cannot ioremap 0x%x bytes of video memory at 0x%lx\n",
info->fix.smem_len, info->fix.smem_start);
err = -EIO;
goto out_mem;
}
platform_set_drvdata(dev, info);
if (register_framebuffer(info) < 0) {
pr_err("failed to register framebuffer device\n");
err = -EINVAL;
goto out_unmap;
}
pr_info("framebuffer at 0x%lx, mapped to 0x%p, using %dk, total %dk\n",
info->fix.smem_start, info->screen_base,
info->fix.smem_len / 1024, par->vbe_ib.total_memory * 64);
fb_info(info, "%s frame buffer device\n", info->fix.id);
err = sysfs_create_group(&dev->dev.kobj, &uvesafb_dev_attgrp);
if (err != 0)
fb_warn(info, "failed to register attributes\n");
return 0;
out_unmap:
iounmap(info->screen_base);
out_mem:
arch_phys_wc_del(par->mtrr_handle);
release_mem_region(info->fix.smem_start, info->fix.smem_len);
out_reg:
release_region(0x3c0, 32);
out_mode:
if (!list_empty(&info->modelist))
fb_destroy_modelist(&info->modelist);
fb_destroy_modedb(info->monspecs.modedb);
fb_dealloc_cmap(&info->cmap);
out:
kfree(par->vbe_modes);
framebuffer_release(info);
return err;
}
static void uvesafb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
struct uvesafb_par *par = info->par;
sysfs_remove_group(&dev->dev.kobj, &uvesafb_dev_attgrp);
unregister_framebuffer(info);
release_region(0x3c0, 32);
iounmap(info->screen_base);
arch_phys_wc_del(par->mtrr_handle);
release_mem_region(info->fix.smem_start, info->fix.smem_len);
fb_destroy_modedb(info->monspecs.modedb);
fb_dealloc_cmap(&info->cmap);
kfree(par->vbe_modes);
kfree(par->vbe_state_orig);
kfree(par->vbe_state_saved);
framebuffer_release(info);
}
static struct platform_driver uvesafb_driver = {
.probe = uvesafb_probe,
.remove_new = uvesafb_remove,
.driver = {
.name = "uvesafb",
},
};
static struct platform_device *uvesafb_device;
#ifndef MODULE
static int uvesafb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt) continue;
if (!strcmp(this_opt, "redraw"))
ypan = 0;
else if (!strcmp(this_opt, "ypan"))
ypan = 1;
else if (!strcmp(this_opt, "ywrap"))
ypan = 2;
else if (!strcmp(this_opt, "vgapal"))
pmi_setpal = false;
else if (!strcmp(this_opt, "pmipal"))
pmi_setpal = true;
else if (!strncmp(this_opt, "mtrr:", 5))
mtrr = simple_strtoul(this_opt+5, NULL, 0);
else if (!strcmp(this_opt, "nomtrr"))
mtrr = 0;
else if (!strcmp(this_opt, "nocrtc"))
nocrtc = true;
else if (!strcmp(this_opt, "noedid"))
noedid = true;
else if (!strcmp(this_opt, "noblank"))
blank = false;
else if (!strncmp(this_opt, "vtotal:", 7))
vram_total = simple_strtoul(this_opt + 7, NULL, 0);
else if (!strncmp(this_opt, "vremap:", 7))
vram_remap = simple_strtoul(this_opt + 7, NULL, 0);
else if (!strncmp(this_opt, "maxhf:", 6))
maxhf = simple_strtoul(this_opt + 6, NULL, 0);
else if (!strncmp(this_opt, "maxvf:", 6))
maxvf = simple_strtoul(this_opt + 6, NULL, 0);
else if (!strncmp(this_opt, "maxclk:", 7))
maxclk = simple_strtoul(this_opt + 7, NULL, 0);
else if (!strncmp(this_opt, "vbemode:", 8))
vbemode = simple_strtoul(this_opt + 8, NULL, 0);
else if (this_opt[0] >= '0' && this_opt[0] <= '9') {
mode_option = this_opt;
} else {
pr_warn("unrecognized option %s\n", this_opt);
}
}
if (mtrr != 3 && mtrr != 0)
pr_warn("uvesafb: mtrr should be set to 0 or 3; %d is unsupported", mtrr);
return 0;
}
#endif /* !MODULE */
static ssize_t v86d_show(struct device_driver *dev, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%s\n", v86d_path);
}
static ssize_t v86d_store(struct device_driver *dev, const char *buf,
size_t count)
{
strncpy(v86d_path, buf, PATH_MAX - 1);
return count;
}
static DRIVER_ATTR_RW(v86d);
static int uvesafb_init(void)
{
int err;
#ifndef MODULE
char *option = NULL;
if (fb_get_options("uvesafb", &option))
return -ENODEV;
uvesafb_setup(option);
#endif
err = cn_add_callback(&uvesafb_cn_id, "uvesafb", uvesafb_cn_callback);
if (err)
return err;
err = platform_driver_register(&uvesafb_driver);
if (!err) {
uvesafb_device = platform_device_alloc("uvesafb", 0);
if (uvesafb_device)
err = platform_device_add(uvesafb_device);
else
err = -ENOMEM;
if (err) {
platform_device_put(uvesafb_device);
platform_driver_unregister(&uvesafb_driver);
cn_del_callback(&uvesafb_cn_id);
return err;
}
err = driver_create_file(&uvesafb_driver.driver,
&driver_attr_v86d);
if (err) {
pr_warn("failed to register attributes\n");
err = 0;
}
}
return err;
}
module_init(uvesafb_init);
static void uvesafb_exit(void)
{
struct uvesafb_ktask *task;
if (v86d_started) {
task = uvesafb_prep();
if (task) {
task->t.flags = TF_EXIT;
uvesafb_exec(task);
uvesafb_free(task);
}
}
cn_del_callback(&uvesafb_cn_id);
driver_remove_file(&uvesafb_driver.driver, &driver_attr_v86d);
platform_device_unregister(uvesafb_device);
platform_driver_unregister(&uvesafb_driver);
}
module_exit(uvesafb_exit);
static int param_set_scroll(const char *val, const struct kernel_param *kp)
{
ypan = 0;
if (!strcmp(val, "redraw"))
ypan = 0;
else if (!strcmp(val, "ypan"))
ypan = 1;
else if (!strcmp(val, "ywrap"))
ypan = 2;
else
return -EINVAL;
return 0;
}
static const struct kernel_param_ops param_ops_scroll = {
.set = param_set_scroll,
};
#define param_check_scroll(name, p) __param_check(name, p, void)
module_param_named(scroll, ypan, scroll, 0);
MODULE_PARM_DESC(scroll,
"Scrolling mode, set to 'redraw', 'ypan', or 'ywrap'");
module_param_named(vgapal, pmi_setpal, invbool, 0);
MODULE_PARM_DESC(vgapal, "Set palette using VGA registers");
module_param_named(pmipal, pmi_setpal, bool, 0);
MODULE_PARM_DESC(pmipal, "Set palette using PMI calls");
module_param(mtrr, uint, 0);
MODULE_PARM_DESC(mtrr,
"Memory Type Range Registers setting. Use 0 to disable.");
module_param(blank, bool, 0);
MODULE_PARM_DESC(blank, "Enable hardware blanking");
module_param(nocrtc, bool, 0);
MODULE_PARM_DESC(nocrtc, "Ignore CRTC timings when setting modes");
module_param(noedid, bool, 0);
MODULE_PARM_DESC(noedid,
"Ignore EDID-provided monitor limits when setting modes");
module_param(vram_remap, uint, 0);
MODULE_PARM_DESC(vram_remap, "Set amount of video memory to be used [MiB]");
module_param(vram_total, uint, 0);
MODULE_PARM_DESC(vram_total, "Set total amount of video memory [MiB]");
module_param(maxclk, ushort, 0);
MODULE_PARM_DESC(maxclk, "Maximum pixelclock [MHz], overrides EDID data");
module_param(maxhf, ushort, 0);
MODULE_PARM_DESC(maxhf,
"Maximum horizontal frequency [kHz], overrides EDID data");
module_param(maxvf, ushort, 0);
MODULE_PARM_DESC(maxvf,
"Maximum vertical frequency [Hz], overrides EDID data");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option,
"Specify initial video mode as \"<xres>x<yres>[-<bpp>][@<refresh>]\"");
module_param(vbemode, ushort, 0);
MODULE_PARM_DESC(vbemode,
"VBE mode number to set, overrides the 'mode' option");
module_param_string(v86d, v86d_path, PATH_MAX, 0660);
MODULE_PARM_DESC(v86d, "Path to the v86d userspace helper.");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Michal Januszewski <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for VBE2.0+ compliant graphics boards");
| linux-master | drivers/video/fbdev/uvesafb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
*
* Copyright (c) 2000-2002 Ghozlane Toumi <[email protected]>
*
* Created 15 Jan 2000 by Ghozlane Toumi
*
* Contributions (and many thanks) :
*
* 03/2001 James Simmons <[email protected]>
* 04/2001 Paul Mundt <[email protected]>
* 05/2001 Urs Ganse <[email protected]>
* (initial work on voodoo2 port, interlace)
* 09/2002 Helge Deller <[email protected]>
* (enable driver on big-endian machines (hppa), ioctl fixes)
* 12/2002 Helge Deller <[email protected]>
* (port driver to new frambuffer infrastructure)
* 01/2003 Helge Deller <[email protected]>
* (initial work on fb hardware acceleration for voodoo2)
* 08/2006 Alan Cox <[email protected]>
* Remove never finished and bogus 24/32bit support
* Clean up macro abuse
* Minor tidying for format.
* 12/2006 Helge Deller <[email protected]>
* add /sys/class/graphics/fbX/vgapass sysfs-interface
* add module option "mode_option" to set initial screen mode
* use fbdev default videomode database
* remove debug functions from ioctl
*/
/*
* The voodoo1 has the following memory mapped address space:
* 0x000000 - 0x3fffff : registers (4MB)
* 0x400000 - 0x7fffff : linear frame buffer (4MB)
* 0x800000 - 0xffffff : texture memory (8MB)
*/
/*
* misc notes, TODOs, toASKs, and deep thoughts
-TODO: at one time or another test that the mode is acceptable by the monitor
-ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
which one should i use ? is there any preferred one ? It seems ARGB is
the one ...
-TODO: in set_var check the validity of timings (hsync vsync)...
-TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
a nop command. so it's ok as long as the commands we pass don't go
through the fifo. warning: issuing a nop command seems to need pci_fifo
-FIXME: in case of failure in the init sequence, be sure we return to a safe
state.
- FIXME: Use accelerator for 2D scroll
-FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
*/
/*
* debug info
* SST_DEBUG : enable debugging
* SST_DEBUG_REG : debug registers
* 0 : no debug
* 1 : dac calls, [un]set_bits, FbiInit
* 2 : insane debug level (log every register read/write)
* SST_DEBUG_FUNC : functions
* 0 : no debug
* 1 : function call / debug ioctl
* 2 : variables
* 3 : flood . you don't want to do that. trust me.
* SST_DEBUG_VAR : debug display/var structs
* 0 : no debug
* 1 : dumps display, fb_var
*
* sstfb specific ioctls:
* toggle vga (0x46db) : toggle vga_pass_through
*/
#undef SST_DEBUG
/*
* Includes
*/
#include <linux/aperture.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <video/sstfb.h>
/* initialized by setup */
static bool vgapass; /* enable VGA passthrough cable */
static int mem; /* mem size in MB, 0 = autodetect */
static bool clipping = 1; /* use clipping (slower, safer) */
static int gfxclk; /* force FBI freq in Mhz . Dangerous */
static bool slowpci; /* slow PCI settings */
/*
Possible default video modes: 800x600@60, 640x480@75, 1024x768@76, 640x480@60
*/
#define DEFAULT_VIDEO_MODE "640x480@60"
static char *mode_option = DEFAULT_VIDEO_MODE;
enum {
ID_VOODOO1 = 0,
ID_VOODOO2 = 1,
};
#define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
static struct sst_spec voodoo_spec[] = {
{ .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
{ .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 },
};
/*
* debug functions
*/
#if (SST_DEBUG_REG > 0)
static void sst_dbg_print_read_reg(u32 reg, u32 val) {
const char *regname;
switch (reg) {
case FBIINIT0: regname = "FbiInit0"; break;
case FBIINIT1: regname = "FbiInit1"; break;
case FBIINIT2: regname = "FbiInit2"; break;
case FBIINIT3: regname = "FbiInit3"; break;
case FBIINIT4: regname = "FbiInit4"; break;
case FBIINIT5: regname = "FbiInit5"; break;
case FBIINIT6: regname = "FbiInit6"; break;
default: regname = NULL; break;
}
if (regname == NULL)
r_ddprintk("sst_read(%#x): %#x\n", reg, val);
else
r_dprintk(" sst_read(%s): %#x\n", regname, val);
}
static void sst_dbg_print_write_reg(u32 reg, u32 val) {
const char *regname;
switch (reg) {
case FBIINIT0: regname = "FbiInit0"; break;
case FBIINIT1: regname = "FbiInit1"; break;
case FBIINIT2: regname = "FbiInit2"; break;
case FBIINIT3: regname = "FbiInit3"; break;
case FBIINIT4: regname = "FbiInit4"; break;
case FBIINIT5: regname = "FbiInit5"; break;
case FBIINIT6: regname = "FbiInit6"; break;
default: regname = NULL; break;
}
if (regname == NULL)
r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
else
r_dprintk(" sst_write(%s, %#x)\n", regname, val);
}
#else /* (SST_DEBUG_REG > 0) */
# define sst_dbg_print_read_reg(reg, val) do {} while(0)
# define sst_dbg_print_write_reg(reg, val) do {} while(0)
#endif /* (SST_DEBUG_REG > 0) */
/*
* hardware access functions
*/
/* register access */
#define sst_read(reg) __sst_read(par->mmio_vbase, reg)
#define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val)
#define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val)
#define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val)
#define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg)
#define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val)
#define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
#define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
{
u32 ret = readl(vbase + reg);
sst_dbg_print_read_reg(reg, ret);
return ret;
}
static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
{
sst_dbg_print_write_reg(reg, val);
writel(val, vbase + reg);
}
static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
{
r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
__sst_write(vbase, reg, __sst_read(vbase, reg) | val);
}
static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
{
r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
__sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
}
/*
* wait for the fbi chip. ASK: what happens if the fbi is stuck ?
*
* the FBI is supposed to be ready if we receive 5 time
* in a row a "idle" answer to our requests
*/
#define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
static int __sst_wait_idle(u8 __iomem *vbase)
{
int count = 0;
/* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
while(1) {
if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
f_dddprintk("status: busy\n");
/* FIXME basically, this is a busy wait. maybe not that good. oh well;
* this is a small loop after all.
* Or maybe we should use mdelay() or udelay() here instead ? */
count = 0;
} else {
count++;
f_dddprintk("status: idle(%d)\n", count);
}
if (count >= 5) return 1;
/* XXX do something to avoid hanging the machine if the voodoo is out */
}
}
/* dac access */
/* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
{
u8 ret;
reg &= 0x07;
__sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
__sst_wait_idle(vbase);
/* udelay(10); */
ret = __sst_read(vbase, DAC_READ) & 0xff;
r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
return ret;
}
static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
{
r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
reg &= 0x07;
__sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
__sst_wait_idle(vbase);
}
/* indexed access to ti/att dacs */
static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
{
u32 ret;
__sst_dac_write(vbase, DACREG_ADDR_I, reg);
ret = __sst_dac_read(vbase, DACREG_DATA_I);
r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
return ret;
}
static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
{
r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
__sst_dac_write(vbase, DACREG_ADDR_I, reg);
__sst_dac_write(vbase, DACREG_DATA_I, val);
}
/* compute the m,n,p , returns the real freq
* (ics datasheet : N <-> N1 , P <-> N2)
*
* Fout= Fref * (M+2)/( 2^P * (N+2))
* we try to get close to the asked freq
* with P as high, and M as low as possible
* range:
* ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
* ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
* we'll use the lowest limitation, should be precise enouth
*/
static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
{
int m, m2, n, p, best_err, fout;
int best_n = -1;
int best_m = -1;
best_err = freq;
p = 3;
/* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
while (((1 << p) * freq > VCO_MAX) && (p >= 0))
p--;
if (p == -1)
return -EINVAL;
for (n = 1; n < 32; n++) {
/* calc 2 * m so we can round it later*/
m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
if (m >= 128)
break;
fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
if ((abs(fout - freq) < best_err) && (m > 0)) {
best_n = n;
best_m = m;
best_err = abs(fout - freq);
/* we get the lowest m , allowing 0.5% error in freq*/
if (200*best_err < freq) break;
}
}
if (best_n == -1) /* unlikely, but who knows ? */
return -EINVAL;
t->p = p;
t->n = best_n;
t->m = best_m;
*freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
t->m, t->n, t->p, *freq_out);
return 0;
}
/*
* clear lfb screen
*/
static void sstfb_clear_screen(struct fb_info *info)
{
/* clear screen */
fb_memset_io(info->screen_base, 0, info->fix.smem_len);
}
/**
* sstfb_check_var - Optional function. Validates a var passed in.
* @var: frame buffer variable screen structure
* @info: frame buffer structure that represents a single frame buffer
*
* Limit to the abilities of a single chip as SLI is not supported
* by this driver.
*/
static int sstfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sstfb_par *par = info->par;
int hSyncOff = var->xres + var->right_margin + var->left_margin;
int vSyncOff = var->yres + var->lower_margin + var->upper_margin;
int vBackPorch = var->left_margin, yDim = var->yres;
int vSyncOn = var->vsync_len;
int tiles_in_X, real_length;
unsigned int freq;
if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n",
PICOS2KHZ(var->pixclock));
return -EINVAL;
}
var->pixclock = KHZ2PICOS(freq);
if (var->vmode & FB_VMODE_INTERLACED)
vBackPorch += (vBackPorch % 2);
if (var->vmode & FB_VMODE_DOUBLE) {
vBackPorch <<= 1;
yDim <<=1;
vSyncOn <<=1;
vSyncOff <<=1;
}
switch (var->bits_per_pixel) {
case 0 ... 16 :
var->bits_per_pixel = 16;
break;
default :
printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel);
return -EINVAL;
}
/* validity tests */
if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1 ||
hSyncOff <= 1 || var->left_margin <= 2 || vSyncOn <= 0 ||
vSyncOff <= 0 || vBackPorch <= 0) {
return -EINVAL;
}
if (IS_VOODOO2(par)) {
/* Voodoo 2 limits */
tiles_in_X = (var->xres + 63 ) / 64 * 2;
if (var->xres > POW2(11) || yDim >= POW2(11)) {
printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
var->xres, var->yres);
return -EINVAL;
}
if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) ||
var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) ||
vSyncOff >= POW2(13) || vBackPorch >= POW2(9) ||
tiles_in_X >= POW2(6) || tiles_in_X <= 0) {
printk(KERN_ERR "sstfb: Unsupported timings\n");
return -EINVAL;
}
} else {
/* Voodoo limits */
tiles_in_X = (var->xres + 63 ) / 64;
if (var->vmode) {
printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n",
var->vmode);
return -EINVAL;
}
if (var->xres > POW2(10) || var->yres >= POW2(10)) {
printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
var->xres, var->yres);
return -EINVAL;
}
if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) ||
var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) ||
vSyncOff >= POW2(12) || vBackPorch >= POW2(8) ||
tiles_in_X >= POW2(4) || tiles_in_X <= 0) {
printk(KERN_ERR "sstfb: Unsupported timings\n");
return -EINVAL;
}
}
/* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
/* FIXME: i don't like this... looks wrong */
real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 )
* ((var->bits_per_pixel == 16) ? 2 : 4);
if (real_length * yDim > info->fix.smem_len) {
printk(KERN_ERR "sstfb: Not enough video memory\n");
return -ENOMEM;
}
var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
var->xoffset = 0;
var->yoffset = 0;
var->height = -1;
var->width = -1;
/*
* correct the color bit fields
*/
/* var->{red|green|blue}.msb_right = 0; */
switch (var->bits_per_pixel) {
case 16: /* RGB 565 LfbMode 0 */
var->red.length = 5;
var->green.length = 6;
var->blue.length = 5;
var->transp.length = 0;
var->red.offset = 11;
var->green.offset = 5;
var->blue.offset = 0;
var->transp.offset = 0;
break;
default:
return -EINVAL;
}
return 0;
}
/**
* sstfb_set_par - Optional function. Alters the hardware state.
* @info: frame buffer structure that represents a single frame buffer
*/
static int sstfb_set_par(struct fb_info *info)
{
struct sstfb_par *par = info->par;
u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
struct pci_dev *sst_dev = par->dev;
unsigned int freq;
int ntiles;
par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin;
par->yDim = info->var.yres;
par->vSyncOn = info->var.vsync_len;
par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin;
par->vBackPorch = info->var.upper_margin;
/* We need par->pll */
sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
if (info->var.vmode & FB_VMODE_INTERLACED)
par->vBackPorch += (par->vBackPorch % 2);
if (info->var.vmode & FB_VMODE_DOUBLE) {
par->vBackPorch <<= 1;
par->yDim <<=1;
par->vSyncOn <<=1;
par->vSyncOff <<=1;
}
if (IS_VOODOO2(par)) {
/* voodoo2 has 32 pixel wide tiles , BUT strange things
happen with odd number of tiles */
par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
} else {
/* voodoo1 has 64 pixels wide tiles. */
par->tiles_in_X = (info->var.xres + 63 ) / 64;
}
f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
f_ddprintk("%-7d %-8d %-7d %-8d\n",
info->var.hsync_len, par->hSyncOff,
par->vSyncOn, par->vSyncOff);
f_ddprintk("left_margin upper_margin xres yres Freq\n");
f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
info->var.left_margin, info->var.upper_margin,
info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
sst_write(NOPCMD, 0);
sst_wait_idle();
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
sst_set_bits(FBIINIT1, VIDEO_RESET);
sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
sst_wait_idle();
/*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn);
fbiinit2 = sst_read(FBIINIT2);
fbiinit3 = sst_read(FBIINIT3);
/* everything is reset. we enable fbiinit2/3 remap : dac access ok */
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
PCI_EN_INIT_WR | PCI_REMAP_DAC );
par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
/* set video clock */
par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
/* disable fbiinit2/3 remap */
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
PCI_EN_INIT_WR);
/* restore fbiinit2/3 */
sst_write(FBIINIT2,fbiinit2);
sst_write(FBIINIT3,fbiinit3);
fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
| EN_DATA_OE
| EN_BLANK_OE
| EN_HVSYNC_OE
| EN_DCLK_OE
/* | (15 << TILES_IN_X_SHIFT) */
| SEL_INPUT_VCLK_2X
/* | (2 << VCLK_2X_SEL_DEL_SHIFT)
| (2 << VCLK_DEL_SHIFT) */;
/* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
in (near) future set them accordingly to revision + resolution (cf glide)
first understand what it stands for :)
FIXME: there are some artefacts... check for the vclk_in_delay
lets try with 6ns delay in both vclk_out & in...
doh... they're still there :\
*/
ntiles = par->tiles_in_X;
if (IS_VOODOO2(par)) {
fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
| ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
/* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
write our value. BTW due to the dac unable to read odd number of tiles, this
field is always null ... */
fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
}
else
fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
switch (info->var.bits_per_pixel) {
case 16:
fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL;
break;
default:
return -EINVAL;
}
sst_write(FBIINIT1, fbiinit1);
if (IS_VOODOO2(par)) {
sst_write(FBIINIT6, fbiinit6);
fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
if (info->var.vmode & FB_VMODE_INTERLACED)
fbiinit5 |= INTERLACE;
if (info->var.vmode & FB_VMODE_DOUBLE)
fbiinit5 |= VDOUBLESCAN;
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
fbiinit5 |= HSYNC_HIGH;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
fbiinit5 |= VSYNC_HIGH;
sst_write(FBIINIT5, fbiinit5);
}
sst_wait_idle();
sst_unset_bits(FBIINIT1, VIDEO_RESET);
sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
/* disables fbiinit writes */
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
/* set lfbmode : set mode + front buffer for reads/writes
+ disable pipeline */
switch (info->var.bits_per_pixel) {
case 16:
lfbmode = LFB_565;
break;
default:
return -EINVAL;
}
#if defined(__BIG_ENDIAN)
/* Enable byte-swizzle functionality in hardware.
* With this enabled, all our read- and write-accesses to
* the voodoo framebuffer can be done in native format, and
* the hardware will automatically convert it to little-endian.
* - tested on HP-PARISC, Helge Deller <[email protected]> */
lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
#endif
if (clipping) {
sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
/*
* Set "clipping" dimensions. If clipping is disabled and
* writes to offscreen areas of the framebuffer are performed,
* the "behaviour is undefined" (_very_ undefined) - Urs
*/
/* btw, it requires enabling pixel pipeline in LFBMODE .
off screen read/writes will just wrap and read/print pixels
on screen. Ugly but not that dangerous */
f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
info->var.xres - 1, par->yDim - 1);
sst_write(CLIP_LEFT_RIGHT, info->var.xres);
sst_write(CLIP_LOWY_HIGHY, par->yDim);
sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
} else {
/* no clipping : direct access, no pipeline */
sst_write(LFBMODE, lfbmode);
}
return 0;
}
/**
* sstfb_setcolreg - Optional function. Sets a color register.
* @regno: hardware colormap register
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*/
static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct sstfb_par *par = info->par;
u32 col;
f_dddprintk("sstfb_setcolreg\n");
f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
regno, red, green, blue, transp);
if (regno > 15)
return 0;
red >>= (16 - info->var.red.length);
green >>= (16 - info->var.green.length);
blue >>= (16 - info->var.blue.length);
transp >>= (16 - info->var.transp.length);
col = (red << info->var.red.offset)
| (green << info->var.green.offset)
| (blue << info->var.blue.offset)
| (transp << info->var.transp.offset);
par->palette[regno] = col;
return 0;
}
static void sstfb_setvgapass( struct fb_info *info, int enable )
{
struct sstfb_par *par = info->par;
struct pci_dev *sst_dev = par->dev;
u32 fbiinit0, tmp;
enable = enable ? 1:0;
if (par->vgapass == enable)
return;
par->vgapass = enable;
pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
tmp | PCI_EN_INIT_WR );
fbiinit0 = sst_read (FBIINIT0);
if (par->vgapass) {
sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH);
fb_info(info, "Enabling VGA pass-through\n");
} else {
sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH);
fb_info(info, "Disabling VGA pass-through\n");
}
pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
}
static ssize_t store_vgapass(struct device *device, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(device);
char ** last = NULL;
int val;
val = simple_strtoul(buf, last, 0);
sstfb_setvgapass(info, val);
return count;
}
static ssize_t show_vgapass(struct device *device, struct device_attribute *attr,
char *buf)
{
struct fb_info *info = dev_get_drvdata(device);
struct sstfb_par *par = info->par;
return sprintf(buf, "%d\n", par->vgapass);
}
static struct device_attribute device_attrs[] = {
__ATTR(vgapass, S_IRUGO|S_IWUSR, show_vgapass, store_vgapass)
};
static int sstfb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct sstfb_par *par;
u32 val;
switch (cmd) {
/* set/get VGA pass_through mode */
case SSTFB_SET_VGAPASS:
if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
return -EFAULT;
sstfb_setvgapass(info, val);
return 0;
case SSTFB_GET_VGAPASS:
par = info->par;
val = par->vgapass;
if (copy_to_user((void __user *)arg, &val, sizeof(val)))
return -EFAULT;
return 0;
}
return -EINVAL;
}
/*
* Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
*/
#if 0
static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct sstfb_par *par = info->par;
u32 stride = info->fix.line_length;
if (!IS_VOODOO2(par))
return;
sst_write(BLTSRCBASEADDR, 0);
sst_write(BLTDSTBASEADDR, 0);
sst_write(BLTROP, BLTROP_COPY);
sst_write(BLTXYSTRIDES, stride | (stride << 16));
sst_write(BLTSRCXY, area->sx | (area->sy << 16));
sst_write(BLTDSTXY, area->dx | (area->dy << 16));
sst_write(BLTSIZE, area->width | (area->height << 16));
sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
(BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
sst_wait_idle();
}
#endif
/*
* FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
*/
#if 0
static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct sstfb_par *par = info->par;
u32 stride = info->fix.line_length;
if (!IS_VOODOO2(par))
return;
sst_write(BLTCLIPX, info->var.xres);
sst_write(BLTCLIPY, info->var.yres);
sst_write(BLTDSTBASEADDR, 0);
sst_write(BLTCOLOR, rect->color);
sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
sst_write(BLTXYSTRIDES, stride | (stride << 16));
sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
sst_write(BLTSIZE, rect->width | (rect->height << 16));
sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
| (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
sst_wait_idle();
}
#endif
/*
* get lfb size
*/
static int sst_get_memsize(struct fb_info *info, __u32 *memsize)
{
u8 __iomem *fbbase_virt = info->screen_base;
/* force memsize */
if (mem >= 1 && mem <= 4) {
*memsize = (mem * 0x100000);
printk(KERN_INFO "supplied memsize: %#x\n", *memsize);
return 1;
}
writel(0xdeadbeef, fbbase_virt);
writel(0xdeadbeef, fbbase_virt+0x100000);
writel(0xdeadbeef, fbbase_virt+0x200000);
f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
readl(fbbase_virt), readl(fbbase_virt + 0x100000),
readl(fbbase_virt + 0x200000));
writel(0xabcdef01, fbbase_virt);
f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
readl(fbbase_virt), readl(fbbase_virt + 0x100000),
readl(fbbase_virt + 0x200000));
/* checks for 4mb lfb, then 2, then defaults to 1 */
if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
*memsize = 0x400000;
else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
*memsize = 0x200000;
else
*memsize = 0x100000;
f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
return 1;
}
/*
* DAC detection routines
*/
/* fbi should be idle, and fifo emty and mem disabled */
/* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
static int sst_detect_att(struct fb_info *info)
{
struct sstfb_par *par = info->par;
int i, mir, dir;
for (i = 0; i < 3; i++) {
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_read(DACREG_RMR); /* read 4 times RMR */
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
/* the fifth time, CR0 is read */
sst_dac_read(DACREG_RMR);
/* the 6th, manufacturer id register */
mir = sst_dac_read(DACREG_RMR);
/*the 7th, device ID register */
dir = sst_dac_read(DACREG_RMR);
f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) {
return 1;
}
}
return 0;
}
static int sst_detect_ti(struct fb_info *info)
{
struct sstfb_par *par = info->par;
int i, mir, dir;
for (i = 0; i<3; i++) {
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_read(DACREG_RMR); /* read 4 times RMR */
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
/* the fifth time, CR0 is read */
sst_dac_read(DACREG_RMR);
/* the 6th, manufacturer id register */
mir = sst_dac_read(DACREG_RMR);
/*the 7th, device ID register */
dir = sst_dac_read(DACREG_RMR);
f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
return 1;
}
}
return 0;
}
/*
* try to detect ICS5342 ramdac
* we get the 1st byte (M value) of preset f1,f7 and fB
* why those 3 ? mmmh... for now, i'll do it the glide way...
* and ask questions later. anyway, it seems that all the freq registers are
* really at their default state (cf specs) so i ask again, why those 3 regs ?
* mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
* pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
* touched...
* is it really safe ? how can i reset this ramdac ? geee...
*/
static int sst_detect_ics(struct fb_info *info)
{
struct sstfb_par *par = info->par;
int m_clk0_1, m_clk0_7, m_clk1_b;
int n_clk0_1, n_clk0_7, n_clk1_b;
int i;
for (i = 0; i<5; i++ ) {
sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
m_clk0_1, m_clk0_7, m_clk1_b);
f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
n_clk0_1, n_clk0_7, n_clk1_b);
if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
&& (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
&& (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
return 1;
}
}
return 0;
}
/*
* gfx, video, pci fifo should be reset, dram refresh disabled
* see detect_dac
*/
static int sst_set_pll_att_ti(struct fb_info *info,
const struct pll_timing *t, const int clock)
{
struct sstfb_par *par = info->par;
u8 cr0, cc;
/* enable indexed mode */
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_read(DACREG_RMR); /* 1 time: RMR */
sst_dac_read(DACREG_RMR); /* 2 RMR */
sst_dac_read(DACREG_RMR); /* 3 // */
sst_dac_read(DACREG_RMR); /* 4 // */
cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
sst_dac_write(DACREG_WMA, 0);
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
| DACREG_CR0_EN_INDEXED
| DACREG_CR0_8BIT
| DACREG_CR0_PWDOWN );
/* so, now we are in indexed mode . dunno if its common, but
i find this way of doing things a little bit weird :p */
udelay(300);
cc = dac_i_read(DACREG_CC_I);
switch (clock) {
case VID_CLOCK:
dac_i_write(DACREG_AC0_I, t->m);
dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
dac_i_write(DACREG_CC_I,
(cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
break;
case GFX_CLOCK:
dac_i_write(DACREG_BD0_I, t->m);
dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
dac_i_write(DACREG_CC_I,
(cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
break;
default:
dprintk("%s: wrong clock code '%d'\n",
__func__, clock);
return 0;
}
udelay(300);
/* power up the dac & return to "normal" non-indexed mode */
dac_i_write(DACREG_CR0_I,
cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
return 1;
}
static int sst_set_pll_ics(struct fb_info *info,
const struct pll_timing *t, const int clock)
{
struct sstfb_par *par = info->par;
u8 pll_ctrl;
sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
switch(clock) {
case VID_CLOCK:
sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
sst_dac_write(DACREG_ICS_PLLDATA, t->m);
sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
/* selects freq f0 for clock 0 */
sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
sst_dac_write(DACREG_ICS_PLLDATA,
(pll_ctrl & 0xd8)
| DACREG_ICS_CLK0
| DACREG_ICS_CLK0_0);
break;
case GFX_CLOCK :
sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
sst_dac_write(DACREG_ICS_PLLDATA, t->m);
sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
/* selects freq fA for clock 1 */
sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
sst_dac_write(DACREG_ICS_PLLDATA,
(pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
break;
default:
dprintk("%s: wrong clock code '%d'\n",
__func__, clock);
return 0;
}
udelay(300);
return 1;
}
static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
{
struct sstfb_par *par = info->par;
u8 cr0;
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_read(DACREG_RMR); /* read 4 times RMR */
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
/* the fifth time, CR0 is read */
cr0 = sst_dac_read(DACREG_RMR);
sst_dac_write(DACREG_WMA, 0); /* backdoor */
sst_dac_read(DACREG_RMR); /* read 4 times RMR */
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
sst_dac_read(DACREG_RMR);
/* cr0 */
switch(bpp) {
case 16:
sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
break;
default:
dprintk("%s: bad depth '%u'\n", __func__, bpp);
break;
}
}
static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
{
struct sstfb_par *par = info->par;
switch(bpp) {
case 16:
sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
break;
default:
dprintk("%s: bad depth '%u'\n", __func__, bpp);
break;
}
}
/*
* detect dac type
* prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
* dram refresh disabled, FbiInit remaped.
* TODO: mmh.. maybe i should put the "prerequisite" in the func ...
*/
static struct dac_switch dacs[] = {
{ .name = "TI TVP3409",
.detect = sst_detect_ti,
.set_pll = sst_set_pll_att_ti,
.set_vidmod = sst_set_vidmod_att_ti },
{ .name = "AT&T ATT20C409",
.detect = sst_detect_att,
.set_pll = sst_set_pll_att_ti,
.set_vidmod = sst_set_vidmod_att_ti },
{ .name = "ICS ICS5342",
.detect = sst_detect_ics,
.set_pll = sst_set_pll_ics,
.set_vidmod = sst_set_vidmod_ics },
};
static int sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
{
int i, ret = 0;
for (i = 0; i < ARRAY_SIZE(dacs); i++) {
ret = dacs[i].detect(info);
if (ret)
break;
}
if (!ret)
return 0;
f_dprintk("%s found %s\n", __func__, dacs[i].name);
par->dac_sw = dacs[i];
return 1;
}
/*
* Internal Routines
*/
static int sst_init(struct fb_info *info, struct sstfb_par *par)
{
u32 fbiinit0, fbiinit1, fbiinit4;
struct pci_dev *dev = par->dev;
struct pll_timing gfx_timings;
struct sst_spec *spec;
int Fout;
int gfx_clock;
spec = &voodoo_spec[par->type];
f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 "
" fbiinit6\n");
f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
/* disable video clock */
pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
/* enable writing to init registers, disable pci fifo */
pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
/* reset video */
sst_set_bits(FBIINIT1, VIDEO_RESET);
sst_wait_idle();
/* reset gfx + pci fifo */
sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
sst_wait_idle();
/* unreset fifo */
/*sst_unset_bits(FBIINIT0, FIFO_RESET);
sst_wait_idle();*/
/* unreset FBI */
/*sst_unset_bits(FBIINIT0, FBI_RESET);
sst_wait_idle();*/
/* disable dram refresh */
sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
sst_wait_idle();
/* remap fbinit2/3 to dac */
pci_write_config_dword(dev, PCI_INIT_ENABLE,
PCI_EN_INIT_WR | PCI_REMAP_DAC );
/* detect dac type */
if (!sst_detect_dactype(info, par)) {
printk(KERN_ERR "sstfb: unknown dac type.\n");
//FIXME watch it: we are not in a safe state, bad bad bad.
return 0;
}
/* set graphic clock */
gfx_clock = spec->default_gfx_clock;
if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk);
gfx_clock = gfxclk *1000;
} else if (gfxclk) {
printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk);
}
sst_calc_pll(gfx_clock, &Fout, &gfx_timings);
par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
/* disable fbiinit remap */
pci_write_config_dword(dev, PCI_INIT_ENABLE,
PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
/* defaults init registers */
/* FbiInit0: unreset gfx, unreset fifo */
fbiinit0 = FBIINIT0_DEFAULT;
fbiinit1 = FBIINIT1_DEFAULT;
fbiinit4 = FBIINIT4_DEFAULT;
par->vgapass = vgapass;
if (par->vgapass)
fbiinit0 &= ~DIS_VGA_PASSTHROUGH;
else
fbiinit0 |= DIS_VGA_PASSTHROUGH;
if (slowpci) {
fbiinit1 |= SLOW_PCI_WRITES;
fbiinit4 |= SLOW_PCI_READS;
} else {
fbiinit1 &= ~SLOW_PCI_WRITES;
fbiinit4 &= ~SLOW_PCI_READS;
}
sst_write(FBIINIT0, fbiinit0);
sst_wait_idle();
sst_write(FBIINIT1, fbiinit1);
sst_wait_idle();
sst_write(FBIINIT2, FBIINIT2_DEFAULT);
sst_wait_idle();
sst_write(FBIINIT3, FBIINIT3_DEFAULT);
sst_wait_idle();
sst_write(FBIINIT4, fbiinit4);
sst_wait_idle();
if (IS_VOODOO2(par)) {
sst_write(FBIINIT6, FBIINIT6_DEFAULT);
sst_wait_idle();
}
pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
return 1;
}
static void sst_shutdown(struct fb_info *info)
{
struct sstfb_par *par = info->par;
struct pci_dev *dev = par->dev;
struct pll_timing gfx_timings;
int Fout;
/* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
sst_wait_idle();
pci_write_config_dword(dev, PCI_INIT_ENABLE,
PCI_EN_INIT_WR | PCI_REMAP_DAC);
/* set 20Mhz gfx clock */
sst_calc_pll(20000, &Fout, &gfx_timings);
par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
/* TODO maybe shutdown the dac, vrefresh and so on... */
pci_write_config_dword(dev, PCI_INIT_ENABLE,
PCI_EN_INIT_WR);
sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH);
pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
/* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
* from start ? */
pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
}
/*
* Interface to the world
*/
static int sstfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt) continue;
f_ddprintk("option %s\n", this_opt);
if (!strcmp(this_opt, "vganopass"))
vgapass = 0;
else if (!strcmp(this_opt, "vgapass"))
vgapass = 1;
else if (!strcmp(this_opt, "clipping"))
clipping = 1;
else if (!strcmp(this_opt, "noclipping"))
clipping = 0;
else if (!strcmp(this_opt, "fastpci"))
slowpci = 0;
else if (!strcmp(this_opt, "slowpci"))
slowpci = 1;
else if (!strncmp(this_opt, "mem:",4))
mem = simple_strtoul (this_opt+4, NULL, 0);
else if (!strncmp(this_opt, "gfxclk:",7))
gfxclk = simple_strtoul (this_opt+7, NULL, 0);
else
mode_option = this_opt;
}
return 0;
}
static const struct fb_ops sstfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = sstfb_check_var,
.fb_set_par = sstfb_set_par,
.fb_setcolreg = sstfb_setcolreg,
.fb_ioctl = sstfb_ioctl,
};
static int sstfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct fb_info *info;
struct fb_fix_screeninfo *fix;
struct sstfb_par *par;
struct sst_spec *spec;
int err;
err = aperture_remove_conflicting_pci_devices(pdev, "sstfb");
if (err)
return err;
/* Enable device in PCI config. */
if ((err=pci_enable_device(pdev))) {
printk(KERN_ERR "cannot enable device\n");
return err;
}
/* Allocate the fb and par structures. */
info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev);
if (!info)
return -ENOMEM;
pci_set_drvdata(pdev, info);
par = info->par;
fix = &info->fix;
par->type = id->driver_data;
spec = &voodoo_spec[par->type];
f_ddprintk("found device : %s\n", spec->name);
par->dev = pdev;
par->revision = pdev->revision;
fix->mmio_start = pci_resource_start(pdev,0);
fix->mmio_len = 0x400000;
fix->smem_start = fix->mmio_start + 0x400000;
if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
printk(KERN_ERR "sstfb: cannot reserve mmio memory\n");
goto fail_mmio_mem;
}
if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
printk(KERN_ERR "sstfb: cannot reserve fb memory\n");
goto fail_fb_mem;
}
par->mmio_vbase = ioremap(fix->mmio_start,
fix->mmio_len);
if (!par->mmio_vbase) {
printk(KERN_ERR "sstfb: cannot remap register area %#lx\n",
fix->mmio_start);
goto fail_mmio_remap;
}
info->screen_base = ioremap(fix->smem_start, 0x400000);
if (!info->screen_base) {
printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n",
fix->smem_start);
goto fail_fb_remap;
}
if (!sst_init(info, par)) {
printk(KERN_ERR "sstfb: Init failed\n");
goto fail;
}
sst_get_memsize(info, &fix->smem_len);
strscpy(fix->id, spec->name, sizeof(fix->id));
printk(KERN_INFO "%s (revision %d) with %s dac\n",
fix->id, par->revision, par->dac_sw.name);
printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
fix->smem_start, info->screen_base,
fix->smem_len >> 20);
f_ddprintk("regbase_virt: %p\n", par->mmio_vbase);
f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
f_ddprintk("fbbase_virt: %p\n", info->screen_base);
info->fbops = &sstfb_ops;
info->pseudo_palette = par->palette;
fix->type = FB_TYPE_PACKED_PIXELS;
fix->visual = FB_VISUAL_TRUECOLOR;
fix->accel = FB_ACCEL_NONE; /* FIXME */
/*
* According to the specs, the linelength must be of 1024 *pixels*
* and the 24bpp mode is in fact a 32 bpp mode (and both are in
* fact dithered to 16bit).
*/
fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16);
if (sstfb_check_var(&info->var, info)) {
printk(KERN_ERR "sstfb: invalid video mode.\n");
goto fail;
}
if (sstfb_set_par(info)) {
printk(KERN_ERR "sstfb: can't set default video mode.\n");
goto fail;
}
if (fb_alloc_cmap(&info->cmap, 256, 0)) {
printk(KERN_ERR "sstfb: can't alloc cmap memory.\n");
goto fail;
}
/* register fb */
info->device = &pdev->dev;
if (register_framebuffer(info) < 0) {
printk(KERN_ERR "sstfb: can't register framebuffer.\n");
goto fail_register;
}
sstfb_clear_screen(info);
if (device_create_file(info->dev, &device_attrs[0]))
printk(KERN_WARNING "sstfb: can't create sysfs entry.\n");
fb_info(info, "%s frame buffer device at 0x%p\n",
fix->id, info->screen_base);
return 0;
fail_register:
fb_dealloc_cmap(&info->cmap);
fail:
iounmap(info->screen_base);
fail_fb_remap:
iounmap(par->mmio_vbase);
fail_mmio_remap:
release_mem_region(fix->smem_start, 0x400000);
fail_fb_mem:
release_mem_region(fix->mmio_start, info->fix.mmio_len);
fail_mmio_mem:
framebuffer_release(info);
return -ENXIO; /* no voodoo detected */
}
static void sstfb_remove(struct pci_dev *pdev)
{
struct sstfb_par *par;
struct fb_info *info;
info = pci_get_drvdata(pdev);
par = info->par;
device_remove_file(info->dev, &device_attrs[0]);
sst_shutdown(info);
iounmap(info->screen_base);
iounmap(par->mmio_vbase);
release_mem_region(info->fix.smem_start, 0x400000);
release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
fb_dealloc_cmap(&info->cmap);
unregister_framebuffer(info);
framebuffer_release(info);
}
static const struct pci_device_id sstfb_id_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO ),
.driver_data = ID_VOODOO1, },
{ PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2),
.driver_data = ID_VOODOO2, },
{ 0 },
};
static struct pci_driver sstfb_driver = {
.name = "sstfb",
.id_table = sstfb_id_tbl,
.probe = sstfb_probe,
.remove = sstfb_remove,
};
static int sstfb_init(void)
{
char *option = NULL;
if (fb_modesetting_disabled("sstfb"))
return -ENODEV;
if (fb_get_options("sstfb", &option))
return -ENODEV;
sstfb_setup(option);
return pci_register_driver(&sstfb_driver);
}
static void sstfb_exit(void)
{
pci_unregister_driver(&sstfb_driver);
}
module_init(sstfb_init);
module_exit(sstfb_exit);
MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <[email protected]>");
MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
MODULE_LICENSE("GPL");
module_param(mem, int, 0);
MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
module_param(vgapass, bool, 0);
MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
module_param(clipping, bool, 0);
MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
module_param(gfxclk, int, 0);
MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
module_param(slowpci, bool, 0);
MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Initial video mode (default=" DEFAULT_VIDEO_MODE ")");
| linux-master | drivers/video/fbdev/sstfb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* pxa3xx-gcu.c - Linux kernel module for PXA3xx graphics controllers
*
* This driver needs a DirectFB counterpart in user space, communication
* is handled via mmap()ed memory areas and an ioctl.
*
* Copyright (c) 2009 Daniel Mack <[email protected]>
* Copyright (c) 2009 Janine Kropp <[email protected]>
* Copyright (c) 2009 Denis Oliver Kropp <[email protected]>
*/
/*
* WARNING: This controller is attached to System Bus 2 of the PXA which
* needs its arbiter to be enabled explicitly (CKENB & 1<<9).
* There is currently no way to do this from Linux, so you need to teach
* your bootloader for now.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/miscdevice.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/ioctl.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/fs.h>
#include <linux/io.h>
#include <linux/of.h>
#include "pxa3xx-gcu.h"
#define DRV_NAME "pxa3xx-gcu"
#define REG_GCCR 0x00
#define GCCR_SYNC_CLR (1 << 9)
#define GCCR_BP_RST (1 << 8)
#define GCCR_ABORT (1 << 6)
#define GCCR_STOP (1 << 4)
#define REG_GCISCR 0x04
#define REG_GCIECR 0x08
#define REG_GCRBBR 0x20
#define REG_GCRBLR 0x24
#define REG_GCRBHR 0x28
#define REG_GCRBTR 0x2C
#define REG_GCRBEXHR 0x30
#define IE_EOB (1 << 0)
#define IE_EEOB (1 << 5)
#define IE_ALL 0xff
#define SHARED_SIZE PAGE_ALIGN(sizeof(struct pxa3xx_gcu_shared))
/* #define PXA3XX_GCU_DEBUG */
/* #define PXA3XX_GCU_DEBUG_TIMER */
#ifdef PXA3XX_GCU_DEBUG
#define QDUMP(msg) \
do { \
QPRINT(priv, KERN_DEBUG, msg); \
} while (0)
#else
#define QDUMP(msg) do {} while (0)
#endif
#define QERROR(msg) \
do { \
QPRINT(priv, KERN_ERR, msg); \
} while (0)
struct pxa3xx_gcu_batch {
struct pxa3xx_gcu_batch *next;
u32 *ptr;
dma_addr_t phys;
unsigned long length;
};
struct pxa3xx_gcu_priv {
struct device *dev;
void __iomem *mmio_base;
struct clk *clk;
struct pxa3xx_gcu_shared *shared;
dma_addr_t shared_phys;
struct resource *resource_mem;
struct miscdevice misc_dev;
wait_queue_head_t wait_idle;
wait_queue_head_t wait_free;
spinlock_t spinlock;
struct timespec64 base_time;
struct pxa3xx_gcu_batch *free;
struct pxa3xx_gcu_batch *ready;
struct pxa3xx_gcu_batch *ready_last;
struct pxa3xx_gcu_batch *running;
};
static inline unsigned long
gc_readl(struct pxa3xx_gcu_priv *priv, unsigned int off)
{
return __raw_readl(priv->mmio_base + off);
}
static inline void
gc_writel(struct pxa3xx_gcu_priv *priv, unsigned int off, unsigned long val)
{
__raw_writel(val, priv->mmio_base + off);
}
#define QPRINT(priv, level, msg) \
do { \
struct timespec64 ts; \
struct pxa3xx_gcu_shared *shared = priv->shared; \
u32 base = gc_readl(priv, REG_GCRBBR); \
\
ktime_get_ts64(&ts); \
ts = timespec64_sub(ts, priv->base_time); \
\
printk(level "%lld.%03ld.%03ld - %-17s: %-21s (%s, " \
"STATUS " \
"0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, " \
"T %5ld)\n", \
(s64)(ts.tv_sec), \
ts.tv_nsec / NSEC_PER_MSEC, \
(ts.tv_nsec % NSEC_PER_MSEC) / USEC_PER_MSEC, \
__func__, msg, \
shared->hw_running ? "running" : " idle", \
gc_readl(priv, REG_GCISCR), \
gc_readl(priv, REG_GCRBBR), \
gc_readl(priv, REG_GCRBLR), \
(gc_readl(priv, REG_GCRBEXHR) - base) / 4, \
(gc_readl(priv, REG_GCRBHR) - base) / 4, \
(gc_readl(priv, REG_GCRBTR) - base) / 4); \
} while (0)
static void
pxa3xx_gcu_reset(struct pxa3xx_gcu_priv *priv)
{
QDUMP("RESET");
/* disable interrupts */
gc_writel(priv, REG_GCIECR, 0);
/* reset hardware */
gc_writel(priv, REG_GCCR, GCCR_ABORT);
gc_writel(priv, REG_GCCR, 0);
memset(priv->shared, 0, SHARED_SIZE);
priv->shared->buffer_phys = priv->shared_phys;
priv->shared->magic = PXA3XX_GCU_SHARED_MAGIC;
ktime_get_ts64(&priv->base_time);
/* set up the ring buffer pointers */
gc_writel(priv, REG_GCRBLR, 0);
gc_writel(priv, REG_GCRBBR, priv->shared_phys);
gc_writel(priv, REG_GCRBTR, priv->shared_phys);
/* enable all IRQs except EOB */
gc_writel(priv, REG_GCIECR, IE_ALL & ~IE_EOB);
}
static void
dump_whole_state(struct pxa3xx_gcu_priv *priv)
{
struct pxa3xx_gcu_shared *sh = priv->shared;
u32 base = gc_readl(priv, REG_GCRBBR);
QDUMP("DUMP");
printk(KERN_DEBUG "== PXA3XX-GCU DUMP ==\n"
"%s, STATUS 0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, T %5ld\n",
sh->hw_running ? "running" : "idle ",
gc_readl(priv, REG_GCISCR),
gc_readl(priv, REG_GCRBBR),
gc_readl(priv, REG_GCRBLR),
(gc_readl(priv, REG_GCRBEXHR) - base) / 4,
(gc_readl(priv, REG_GCRBHR) - base) / 4,
(gc_readl(priv, REG_GCRBTR) - base) / 4);
}
static void
flush_running(struct pxa3xx_gcu_priv *priv)
{
struct pxa3xx_gcu_batch *running = priv->running;
struct pxa3xx_gcu_batch *next;
while (running) {
next = running->next;
running->next = priv->free;
priv->free = running;
running = next;
}
priv->running = NULL;
}
static void
run_ready(struct pxa3xx_gcu_priv *priv)
{
unsigned int num = 0;
struct pxa3xx_gcu_shared *shared = priv->shared;
struct pxa3xx_gcu_batch *ready = priv->ready;
QDUMP("Start");
BUG_ON(!ready);
shared->buffer[num++] = 0x05000000;
while (ready) {
shared->buffer[num++] = 0x00000001;
shared->buffer[num++] = ready->phys;
ready = ready->next;
}
shared->buffer[num++] = 0x05000000;
priv->running = priv->ready;
priv->ready = priv->ready_last = NULL;
gc_writel(priv, REG_GCRBLR, 0);
shared->hw_running = 1;
/* ring base address */
gc_writel(priv, REG_GCRBBR, shared->buffer_phys);
/* ring tail address */
gc_writel(priv, REG_GCRBTR, shared->buffer_phys + num * 4);
/* ring length */
gc_writel(priv, REG_GCRBLR, ((num + 63) & ~63) * 4);
}
static irqreturn_t
pxa3xx_gcu_handle_irq(int irq, void *ctx)
{
struct pxa3xx_gcu_priv *priv = ctx;
struct pxa3xx_gcu_shared *shared = priv->shared;
u32 status = gc_readl(priv, REG_GCISCR) & IE_ALL;
QDUMP("-Interrupt");
if (!status)
return IRQ_NONE;
spin_lock(&priv->spinlock);
shared->num_interrupts++;
if (status & IE_EEOB) {
QDUMP(" [EEOB]");
flush_running(priv);
wake_up_all(&priv->wait_free);
if (priv->ready) {
run_ready(priv);
} else {
/* There is no more data prepared by the userspace.
* Set hw_running = 0 and wait for the next userspace
* kick-off */
shared->num_idle++;
shared->hw_running = 0;
QDUMP(" '-> Idle.");
/* set ring buffer length to zero */
gc_writel(priv, REG_GCRBLR, 0);
wake_up_all(&priv->wait_idle);
}
shared->num_done++;
} else {
QERROR(" [???]");
dump_whole_state(priv);
}
/* Clear the interrupt */
gc_writel(priv, REG_GCISCR, status);
spin_unlock(&priv->spinlock);
return IRQ_HANDLED;
}
static int
pxa3xx_gcu_wait_idle(struct pxa3xx_gcu_priv *priv)
{
int ret = 0;
QDUMP("Waiting for idle...");
/* Does not need to be atomic. There's a lock in user space,
* but anyhow, this is just for statistics. */
priv->shared->num_wait_idle++;
while (priv->shared->hw_running) {
int num = priv->shared->num_interrupts;
u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);
ret = wait_event_interruptible_timeout(priv->wait_idle,
!priv->shared->hw_running, HZ*4);
if (ret != 0)
break;
if (gc_readl(priv, REG_GCRBEXHR) == rbexhr &&
priv->shared->num_interrupts == num) {
QERROR("TIMEOUT");
ret = -ETIMEDOUT;
break;
}
}
QDUMP("done");
return ret;
}
static int
pxa3xx_gcu_wait_free(struct pxa3xx_gcu_priv *priv)
{
int ret = 0;
QDUMP("Waiting for free...");
/* Does not need to be atomic. There's a lock in user space,
* but anyhow, this is just for statistics. */
priv->shared->num_wait_free++;
while (!priv->free) {
u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);
ret = wait_event_interruptible_timeout(priv->wait_free,
priv->free, HZ*4);
if (ret < 0)
break;
if (ret > 0)
continue;
if (gc_readl(priv, REG_GCRBEXHR) == rbexhr) {
QERROR("TIMEOUT");
ret = -ETIMEDOUT;
break;
}
}
QDUMP("done");
return ret;
}
/* Misc device layer */
static inline struct pxa3xx_gcu_priv *to_pxa3xx_gcu_priv(struct file *file)
{
struct miscdevice *dev = file->private_data;
return container_of(dev, struct pxa3xx_gcu_priv, misc_dev);
}
/*
* provide an empty .open callback, so the core sets file->private_data
* for us.
*/
static int pxa3xx_gcu_open(struct inode *inode, struct file *file)
{
return 0;
}
static ssize_t
pxa3xx_gcu_write(struct file *file, const char *buff,
size_t count, loff_t *offp)
{
int ret;
unsigned long flags;
struct pxa3xx_gcu_batch *buffer;
struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
size_t words = count / 4;
/* Does not need to be atomic. There's a lock in user space,
* but anyhow, this is just for statistics. */
priv->shared->num_writes++;
priv->shared->num_words += words;
/* Last word reserved for batch buffer end command */
if (words >= PXA3XX_GCU_BATCH_WORDS)
return -E2BIG;
/* Wait for a free buffer */
if (!priv->free) {
ret = pxa3xx_gcu_wait_free(priv);
if (ret < 0)
return ret;
}
/*
* Get buffer from free list
*/
spin_lock_irqsave(&priv->spinlock, flags);
buffer = priv->free;
priv->free = buffer->next;
spin_unlock_irqrestore(&priv->spinlock, flags);
/* Copy data from user into buffer */
ret = copy_from_user(buffer->ptr, buff, words * 4);
if (ret) {
spin_lock_irqsave(&priv->spinlock, flags);
buffer->next = priv->free;
priv->free = buffer;
spin_unlock_irqrestore(&priv->spinlock, flags);
return -EFAULT;
}
buffer->length = words;
/* Append batch buffer end command */
buffer->ptr[words] = 0x01000000;
/*
* Add buffer to ready list
*/
spin_lock_irqsave(&priv->spinlock, flags);
buffer->next = NULL;
if (priv->ready) {
BUG_ON(priv->ready_last == NULL);
priv->ready_last->next = buffer;
} else
priv->ready = buffer;
priv->ready_last = buffer;
if (!priv->shared->hw_running)
run_ready(priv);
spin_unlock_irqrestore(&priv->spinlock, flags);
return words * 4;
}
static long
pxa3xx_gcu_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
unsigned long flags;
struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
switch (cmd) {
case PXA3XX_GCU_IOCTL_RESET:
spin_lock_irqsave(&priv->spinlock, flags);
pxa3xx_gcu_reset(priv);
spin_unlock_irqrestore(&priv->spinlock, flags);
return 0;
case PXA3XX_GCU_IOCTL_WAIT_IDLE:
return pxa3xx_gcu_wait_idle(priv);
}
return -ENOSYS;
}
static int
pxa3xx_gcu_mmap(struct file *file, struct vm_area_struct *vma)
{
unsigned int size = vma->vm_end - vma->vm_start;
struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
switch (vma->vm_pgoff) {
case 0:
/* hand out the shared data area */
if (size != SHARED_SIZE)
return -EINVAL;
return dma_mmap_coherent(priv->dev, vma,
priv->shared, priv->shared_phys, size);
case SHARED_SIZE >> PAGE_SHIFT:
/* hand out the MMIO base for direct register access
* from userspace */
if (size != resource_size(priv->resource_mem))
return -EINVAL;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
return io_remap_pfn_range(vma, vma->vm_start,
priv->resource_mem->start >> PAGE_SHIFT,
size, vma->vm_page_prot);
}
return -EINVAL;
}
#ifdef PXA3XX_GCU_DEBUG_TIMER
static struct timer_list pxa3xx_gcu_debug_timer;
static struct pxa3xx_gcu_priv *debug_timer_priv;
static void pxa3xx_gcu_debug_timedout(struct timer_list *unused)
{
struct pxa3xx_gcu_priv *priv = debug_timer_priv;
QERROR("Timer DUMP");
mod_timer(&pxa3xx_gcu_debug_timer, jiffies + 5 * HZ);
}
static void pxa3xx_gcu_init_debug_timer(struct pxa3xx_gcu_priv *priv)
{
/* init the timer structure */
debug_timer_priv = priv;
timer_setup(&pxa3xx_gcu_debug_timer, pxa3xx_gcu_debug_timedout, 0);
pxa3xx_gcu_debug_timedout(NULL);
}
#else
static inline void pxa3xx_gcu_init_debug_timer(struct pxa3xx_gcu_priv *priv) {}
#endif
static int
pxa3xx_gcu_add_buffer(struct device *dev,
struct pxa3xx_gcu_priv *priv)
{
struct pxa3xx_gcu_batch *buffer;
buffer = kzalloc(sizeof(struct pxa3xx_gcu_batch), GFP_KERNEL);
if (!buffer)
return -ENOMEM;
buffer->ptr = dma_alloc_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4,
&buffer->phys, GFP_KERNEL);
if (!buffer->ptr) {
kfree(buffer);
return -ENOMEM;
}
buffer->next = priv->free;
priv->free = buffer;
return 0;
}
static void
pxa3xx_gcu_free_buffers(struct device *dev,
struct pxa3xx_gcu_priv *priv)
{
struct pxa3xx_gcu_batch *next, *buffer = priv->free;
while (buffer) {
next = buffer->next;
dma_free_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4,
buffer->ptr, buffer->phys);
kfree(buffer);
buffer = next;
}
priv->free = NULL;
}
static const struct file_operations pxa3xx_gcu_miscdev_fops = {
.owner = THIS_MODULE,
.open = pxa3xx_gcu_open,
.write = pxa3xx_gcu_write,
.unlocked_ioctl = pxa3xx_gcu_ioctl,
.mmap = pxa3xx_gcu_mmap,
};
static int pxa3xx_gcu_probe(struct platform_device *pdev)
{
int i, ret, irq;
struct resource *r;
struct pxa3xx_gcu_priv *priv;
struct device *dev = &pdev->dev;
priv = devm_kzalloc(dev, sizeof(struct pxa3xx_gcu_priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
init_waitqueue_head(&priv->wait_idle);
init_waitqueue_head(&priv->wait_free);
spin_lock_init(&priv->spinlock);
/* we allocate the misc device structure as part of our own allocation,
* so we can get a pointer to our priv structure later on with
* container_of(). This isn't really necessary as we have a fixed minor
* number anyway, but this is to avoid statics. */
priv->misc_dev.minor = PXA3XX_GCU_MINOR,
priv->misc_dev.name = DRV_NAME,
priv->misc_dev.fops = &pxa3xx_gcu_miscdev_fops;
/* handle IO resources */
priv->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
if (IS_ERR(priv->mmio_base))
return PTR_ERR(priv->mmio_base);
/* enable the clock */
priv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->clk))
return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to get clock\n");
/* request the IRQ */
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
ret = devm_request_irq(dev, irq, pxa3xx_gcu_handle_irq,
0, DRV_NAME, priv);
if (ret < 0) {
dev_err(dev, "request_irq failed\n");
return ret;
}
/* allocate dma memory */
priv->shared = dma_alloc_coherent(dev, SHARED_SIZE,
&priv->shared_phys, GFP_KERNEL);
if (!priv->shared) {
dev_err(dev, "failed to allocate DMA memory\n");
return -ENOMEM;
}
/* register misc device */
ret = misc_register(&priv->misc_dev);
if (ret < 0) {
dev_err(dev, "misc_register() for minor %d failed\n",
PXA3XX_GCU_MINOR);
goto err_free_dma;
}
ret = clk_prepare_enable(priv->clk);
if (ret < 0) {
dev_err(dev, "failed to enable clock\n");
goto err_misc_deregister;
}
for (i = 0; i < 8; i++) {
ret = pxa3xx_gcu_add_buffer(dev, priv);
if (ret) {
pxa3xx_gcu_free_buffers(dev, priv);
dev_err(dev, "failed to allocate DMA memory\n");
goto err_disable_clk;
}
}
platform_set_drvdata(pdev, priv);
priv->resource_mem = r;
priv->dev = dev;
pxa3xx_gcu_reset(priv);
pxa3xx_gcu_init_debug_timer(priv);
dev_info(dev, "registered @0x%p, DMA 0x%p (%d bytes), IRQ %d\n",
(void *) r->start, (void *) priv->shared_phys,
SHARED_SIZE, irq);
return 0;
err_disable_clk:
clk_disable_unprepare(priv->clk);
err_misc_deregister:
misc_deregister(&priv->misc_dev);
err_free_dma:
dma_free_coherent(dev, SHARED_SIZE,
priv->shared, priv->shared_phys);
return ret;
}
static void pxa3xx_gcu_remove(struct platform_device *pdev)
{
struct pxa3xx_gcu_priv *priv = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
pxa3xx_gcu_wait_idle(priv);
misc_deregister(&priv->misc_dev);
dma_free_coherent(dev, SHARED_SIZE, priv->shared, priv->shared_phys);
clk_disable_unprepare(priv->clk);
pxa3xx_gcu_free_buffers(dev, priv);
}
#ifdef CONFIG_OF
static const struct of_device_id pxa3xx_gcu_of_match[] = {
{ .compatible = "marvell,pxa300-gcu", },
{ }
};
MODULE_DEVICE_TABLE(of, pxa3xx_gcu_of_match);
#endif
static struct platform_driver pxa3xx_gcu_driver = {
.probe = pxa3xx_gcu_probe,
.remove_new = pxa3xx_gcu_remove,
.driver = {
.name = DRV_NAME,
.of_match_table = of_match_ptr(pxa3xx_gcu_of_match),
},
};
module_platform_driver(pxa3xx_gcu_driver);
MODULE_DESCRIPTION("PXA3xx graphics controller unit driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(PXA3XX_GCU_MINOR);
MODULE_AUTHOR("Janine Kropp <[email protected]>, "
"Denis Oliver Kropp <[email protected]>, "
"Daniel Mack <[email protected]>");
| linux-master | drivers/video/fbdev/pxa3xx-gcu.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* udlfb.c -- Framebuffer driver for DisplayLink USB controller
*
* Copyright (C) 2009 Roberto De Ioris <[email protected]>
* Copyright (C) 2009 Jaya Kumar <[email protected]>
* Copyright (C) 2009 Bernie Thompson <[email protected]>
*
* Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven,
* usb-skeleton by GregKH.
*
* Device-specific portions based on information from Displaylink, with work
* from Florian Echtler, Henrik Bjerregaard Pedersen, and others.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/usb.h>
#include <linux/uaccess.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/vmalloc.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <asm/unaligned.h>
#include <video/udlfb.h>
#include "edid.h"
#define OUT_EP_NUM 1 /* The endpoint number we will use */
static const struct fb_fix_screeninfo dlfb_fix = {
.id = "udlfb",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static const u32 udlfb_info_flags = FBINFO_READS_FAST |
FBINFO_VIRTFB |
FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR;
/*
* There are many DisplayLink-based graphics products, all with unique PIDs.
* So we match on DisplayLink's VID + Vendor-Defined Interface Class (0xff)
* We also require a match on SubClass (0x00) and Protocol (0x00),
* which is compatible with all known USB 2.0 era graphics chips and firmware,
* but allows DisplayLink to increment those for any future incompatible chips
*/
static const struct usb_device_id id_table[] = {
{.idVendor = 0x17e9,
.bInterfaceClass = 0xff,
.bInterfaceSubClass = 0x00,
.bInterfaceProtocol = 0x00,
.match_flags = USB_DEVICE_ID_MATCH_VENDOR |
USB_DEVICE_ID_MATCH_INT_CLASS |
USB_DEVICE_ID_MATCH_INT_SUBCLASS |
USB_DEVICE_ID_MATCH_INT_PROTOCOL,
},
{},
};
MODULE_DEVICE_TABLE(usb, id_table);
/* module options */
static bool console = true; /* Allow fbcon to open framebuffer */
static bool fb_defio = true; /* Detect mmap writes using page faults */
static bool shadow = true; /* Optionally disable shadow framebuffer */
static int pixel_limit; /* Optionally force a pixel resolution limit */
struct dlfb_deferred_free {
struct list_head list;
void *mem;
};
static int dlfb_realloc_framebuffer(struct dlfb_data *dlfb, struct fb_info *info, u32 new_len);
/* dlfb keeps a list of urbs for efficient bulk transfers */
static void dlfb_urb_completion(struct urb *urb);
static struct urb *dlfb_get_urb(struct dlfb_data *dlfb);
static int dlfb_submit_urb(struct dlfb_data *dlfb, struct urb * urb, size_t len);
static int dlfb_alloc_urb_list(struct dlfb_data *dlfb, int count, size_t size);
static void dlfb_free_urb_list(struct dlfb_data *dlfb);
/*
* All DisplayLink bulk operations start with 0xAF, followed by specific code
* All operations are written to buffers which then later get sent to device
*/
static char *dlfb_set_register(char *buf, u8 reg, u8 val)
{
*buf++ = 0xAF;
*buf++ = 0x20;
*buf++ = reg;
*buf++ = val;
return buf;
}
static char *dlfb_vidreg_lock(char *buf)
{
return dlfb_set_register(buf, 0xFF, 0x00);
}
static char *dlfb_vidreg_unlock(char *buf)
{
return dlfb_set_register(buf, 0xFF, 0xFF);
}
/*
* Map FB_BLANK_* to DisplayLink register
* DLReg FB_BLANK_*
* ----- -----------------------------
* 0x00 FB_BLANK_UNBLANK (0)
* 0x01 FB_BLANK (1)
* 0x03 FB_BLANK_VSYNC_SUSPEND (2)
* 0x05 FB_BLANK_HSYNC_SUSPEND (3)
* 0x07 FB_BLANK_POWERDOWN (4) Note: requires modeset to come back
*/
static char *dlfb_blanking(char *buf, int fb_blank)
{
u8 reg;
switch (fb_blank) {
case FB_BLANK_POWERDOWN:
reg = 0x07;
break;
case FB_BLANK_HSYNC_SUSPEND:
reg = 0x05;
break;
case FB_BLANK_VSYNC_SUSPEND:
reg = 0x03;
break;
case FB_BLANK_NORMAL:
reg = 0x01;
break;
default:
reg = 0x00;
}
buf = dlfb_set_register(buf, 0x1F, reg);
return buf;
}
static char *dlfb_set_color_depth(char *buf, u8 selection)
{
return dlfb_set_register(buf, 0x00, selection);
}
static char *dlfb_set_base16bpp(char *wrptr, u32 base)
{
/* the base pointer is 16 bits wide, 0x20 is hi byte. */
wrptr = dlfb_set_register(wrptr, 0x20, base >> 16);
wrptr = dlfb_set_register(wrptr, 0x21, base >> 8);
return dlfb_set_register(wrptr, 0x22, base);
}
/*
* DisplayLink HW has separate 16bpp and 8bpp framebuffers.
* In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
*/
static char *dlfb_set_base8bpp(char *wrptr, u32 base)
{
wrptr = dlfb_set_register(wrptr, 0x26, base >> 16);
wrptr = dlfb_set_register(wrptr, 0x27, base >> 8);
return dlfb_set_register(wrptr, 0x28, base);
}
static char *dlfb_set_register_16(char *wrptr, u8 reg, u16 value)
{
wrptr = dlfb_set_register(wrptr, reg, value >> 8);
return dlfb_set_register(wrptr, reg+1, value);
}
/*
* This is kind of weird because the controller takes some
* register values in a different byte order than other registers.
*/
static char *dlfb_set_register_16be(char *wrptr, u8 reg, u16 value)
{
wrptr = dlfb_set_register(wrptr, reg, value);
return dlfb_set_register(wrptr, reg+1, value >> 8);
}
/*
* LFSR is linear feedback shift register. The reason we have this is
* because the display controller needs to minimize the clock depth of
* various counters used in the display path. So this code reverses the
* provided value into the lfsr16 value by counting backwards to get
* the value that needs to be set in the hardware comparator to get the
* same actual count. This makes sense once you read above a couple of
* times and think about it from a hardware perspective.
*/
static u16 dlfb_lfsr16(u16 actual_count)
{
u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */
while (actual_count--) {
lv = ((lv << 1) |
(((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1))
& 0xFFFF;
}
return (u16) lv;
}
/*
* This does LFSR conversion on the value that is to be written.
* See LFSR explanation above for more detail.
*/
static char *dlfb_set_register_lfsr16(char *wrptr, u8 reg, u16 value)
{
return dlfb_set_register_16(wrptr, reg, dlfb_lfsr16(value));
}
/*
* This takes a standard fbdev screeninfo struct and all of its monitor mode
* details and converts them into the DisplayLink equivalent register commands.
*/
static char *dlfb_set_vid_cmds(char *wrptr, struct fb_var_screeninfo *var)
{
u16 xds, yds;
u16 xde, yde;
u16 yec;
/* x display start */
xds = var->left_margin + var->hsync_len;
wrptr = dlfb_set_register_lfsr16(wrptr, 0x01, xds);
/* x display end */
xde = xds + var->xres;
wrptr = dlfb_set_register_lfsr16(wrptr, 0x03, xde);
/* y display start */
yds = var->upper_margin + var->vsync_len;
wrptr = dlfb_set_register_lfsr16(wrptr, 0x05, yds);
/* y display end */
yde = yds + var->yres;
wrptr = dlfb_set_register_lfsr16(wrptr, 0x07, yde);
/* x end count is active + blanking - 1 */
wrptr = dlfb_set_register_lfsr16(wrptr, 0x09,
xde + var->right_margin - 1);
/* libdlo hardcodes hsync start to 1 */
wrptr = dlfb_set_register_lfsr16(wrptr, 0x0B, 1);
/* hsync end is width of sync pulse + 1 */
wrptr = dlfb_set_register_lfsr16(wrptr, 0x0D, var->hsync_len + 1);
/* hpixels is active pixels */
wrptr = dlfb_set_register_16(wrptr, 0x0F, var->xres);
/* yendcount is vertical active + vertical blanking */
yec = var->yres + var->upper_margin + var->lower_margin +
var->vsync_len;
wrptr = dlfb_set_register_lfsr16(wrptr, 0x11, yec);
/* libdlo hardcodes vsync start to 0 */
wrptr = dlfb_set_register_lfsr16(wrptr, 0x13, 0);
/* vsync end is width of vsync pulse */
wrptr = dlfb_set_register_lfsr16(wrptr, 0x15, var->vsync_len);
/* vpixels is active pixels */
wrptr = dlfb_set_register_16(wrptr, 0x17, var->yres);
/* convert picoseconds to 5kHz multiple for pclk5k = x * 1E12/5k */
wrptr = dlfb_set_register_16be(wrptr, 0x1B,
200*1000*1000/var->pixclock);
return wrptr;
}
/*
* This takes a standard fbdev screeninfo struct that was fetched or prepared
* and then generates the appropriate command sequence that then drives the
* display controller.
*/
static int dlfb_set_video_mode(struct dlfb_data *dlfb,
struct fb_var_screeninfo *var)
{
char *buf;
char *wrptr;
int retval;
int writesize;
struct urb *urb;
if (!atomic_read(&dlfb->usb_active))
return -EPERM;
urb = dlfb_get_urb(dlfb);
if (!urb)
return -ENOMEM;
buf = (char *) urb->transfer_buffer;
/*
* This first section has to do with setting the base address on the
* controller * associated with the display. There are 2 base
* pointers, currently, we only * use the 16 bpp segment.
*/
wrptr = dlfb_vidreg_lock(buf);
wrptr = dlfb_set_color_depth(wrptr, 0x00);
/* set base for 16bpp segment to 0 */
wrptr = dlfb_set_base16bpp(wrptr, 0);
/* set base for 8bpp segment to end of fb */
wrptr = dlfb_set_base8bpp(wrptr, dlfb->info->fix.smem_len);
wrptr = dlfb_set_vid_cmds(wrptr, var);
wrptr = dlfb_blanking(wrptr, FB_BLANK_UNBLANK);
wrptr = dlfb_vidreg_unlock(wrptr);
writesize = wrptr - buf;
retval = dlfb_submit_urb(dlfb, urb, writesize);
dlfb->blank_mode = FB_BLANK_UNBLANK;
return retval;
}
static int dlfb_ops_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
unsigned long start = vma->vm_start;
unsigned long size = vma->vm_end - vma->vm_start;
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
unsigned long page, pos;
if (info->fbdefio)
return fb_deferred_io_mmap(info, vma);
if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
return -EINVAL;
if (size > info->fix.smem_len)
return -EINVAL;
if (offset > info->fix.smem_len - size)
return -EINVAL;
pos = (unsigned long)info->fix.smem_start + offset;
dev_dbg(info->dev, "mmap() framebuffer addr:%lu size:%lu\n",
pos, size);
while (size > 0) {
page = vmalloc_to_pfn((void *)pos);
if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED))
return -EAGAIN;
start += PAGE_SIZE;
pos += PAGE_SIZE;
if (size > PAGE_SIZE)
size -= PAGE_SIZE;
else
size = 0;
}
return 0;
}
/*
* Trims identical data from front and back of line
* Sets new front buffer address and width
* And returns byte count of identical pixels
* Assumes CPU natural alignment (unsigned long)
* for back and front buffer ptrs and width
*/
static int dlfb_trim_hline(const u8 *bback, const u8 **bfront, int *width_bytes)
{
int j, k;
const unsigned long *back = (const unsigned long *) bback;
const unsigned long *front = (const unsigned long *) *bfront;
const int width = *width_bytes / sizeof(unsigned long);
int identical;
int start = width;
int end = width;
for (j = 0; j < width; j++) {
if (back[j] != front[j]) {
start = j;
break;
}
}
for (k = width - 1; k > j; k--) {
if (back[k] != front[k]) {
end = k+1;
break;
}
}
identical = start + (width - end);
*bfront = (u8 *) &front[start];
*width_bytes = (end - start) * sizeof(unsigned long);
return identical * sizeof(unsigned long);
}
/*
* Render a command stream for an encoded horizontal line segment of pixels.
*
* A command buffer holds several commands.
* It always begins with a fresh command header
* (the protocol doesn't require this, but we enforce it to allow
* multiple buffers to be potentially encoded and sent in parallel).
* A single command encodes one contiguous horizontal line of pixels
*
* The function relies on the client to do all allocation, so that
* rendering can be done directly to output buffers (e.g. USB URBs).
* The function fills the supplied command buffer, providing information
* on where it left off, so the client may call in again with additional
* buffers if the line will take several buffers to complete.
*
* A single command can transmit a maximum of 256 pixels,
* regardless of the compression ratio (protocol design limit).
* To the hardware, 0 for a size byte means 256
*
* Rather than 256 pixel commands which are either rl or raw encoded,
* the rlx command simply assumes alternating raw and rl spans within one cmd.
* This has a slightly larger header overhead, but produces more even results.
* It also processes all data (read and write) in a single pass.
* Performance benchmarks of common cases show it having just slightly better
* compression than 256 pixel raw or rle commands, with similar CPU consumpion.
* But for very rl friendly data, will compress not quite as well.
*/
static void dlfb_compress_hline(
const uint16_t **pixel_start_ptr,
const uint16_t *const pixel_end,
uint32_t *device_address_ptr,
uint8_t **command_buffer_ptr,
const uint8_t *const cmd_buffer_end,
unsigned long back_buffer_offset,
int *ident_ptr)
{
const uint16_t *pixel = *pixel_start_ptr;
uint32_t dev_addr = *device_address_ptr;
uint8_t *cmd = *command_buffer_ptr;
while ((pixel_end > pixel) &&
(cmd_buffer_end - MIN_RLX_CMD_BYTES > cmd)) {
uint8_t *raw_pixels_count_byte = NULL;
uint8_t *cmd_pixels_count_byte = NULL;
const uint16_t *raw_pixel_start = NULL;
const uint16_t *cmd_pixel_start, *cmd_pixel_end = NULL;
if (back_buffer_offset &&
*pixel == *(u16 *)((u8 *)pixel + back_buffer_offset)) {
pixel++;
dev_addr += BPP;
(*ident_ptr)++;
continue;
}
*cmd++ = 0xAF;
*cmd++ = 0x6B;
*cmd++ = dev_addr >> 16;
*cmd++ = dev_addr >> 8;
*cmd++ = dev_addr;
cmd_pixels_count_byte = cmd++; /* we'll know this later */
cmd_pixel_start = pixel;
raw_pixels_count_byte = cmd++; /* we'll know this later */
raw_pixel_start = pixel;
cmd_pixel_end = pixel + min3(MAX_CMD_PIXELS + 1UL,
(unsigned long)(pixel_end - pixel),
(unsigned long)(cmd_buffer_end - 1 - cmd) / BPP);
if (back_buffer_offset) {
/* note: the framebuffer may change under us, so we must test for underflow */
while (cmd_pixel_end - 1 > pixel &&
*(cmd_pixel_end - 1) == *(u16 *)((u8 *)(cmd_pixel_end - 1) + back_buffer_offset))
cmd_pixel_end--;
}
while (pixel < cmd_pixel_end) {
const uint16_t * const repeating_pixel = pixel;
u16 pixel_value = *pixel;
put_unaligned_be16(pixel_value, cmd);
if (back_buffer_offset)
*(u16 *)((u8 *)pixel + back_buffer_offset) = pixel_value;
cmd += 2;
pixel++;
if (unlikely((pixel < cmd_pixel_end) &&
(*pixel == pixel_value))) {
/* go back and fill in raw pixel count */
*raw_pixels_count_byte = ((repeating_pixel -
raw_pixel_start) + 1) & 0xFF;
do {
if (back_buffer_offset)
*(u16 *)((u8 *)pixel + back_buffer_offset) = pixel_value;
pixel++;
} while ((pixel < cmd_pixel_end) &&
(*pixel == pixel_value));
/* immediately after raw data is repeat byte */
*cmd++ = ((pixel - repeating_pixel) - 1) & 0xFF;
/* Then start another raw pixel span */
raw_pixel_start = pixel;
raw_pixels_count_byte = cmd++;
}
}
if (pixel > raw_pixel_start) {
/* finalize last RAW span */
*raw_pixels_count_byte = (pixel-raw_pixel_start) & 0xFF;
} else {
/* undo unused byte */
cmd--;
}
*cmd_pixels_count_byte = (pixel - cmd_pixel_start) & 0xFF;
dev_addr += (u8 *)pixel - (u8 *)cmd_pixel_start;
}
if (cmd_buffer_end - MIN_RLX_CMD_BYTES <= cmd) {
/* Fill leftover bytes with no-ops */
if (cmd_buffer_end > cmd)
memset(cmd, 0xAF, cmd_buffer_end - cmd);
cmd = (uint8_t *) cmd_buffer_end;
}
*command_buffer_ptr = cmd;
*pixel_start_ptr = pixel;
*device_address_ptr = dev_addr;
}
/*
* There are 3 copies of every pixel: The front buffer that the fbdev
* client renders to, the actual framebuffer across the USB bus in hardware
* (that we can only write to, slowly, and can never read), and (optionally)
* our shadow copy that tracks what's been sent to that hardware buffer.
*/
static int dlfb_render_hline(struct dlfb_data *dlfb, struct urb **urb_ptr,
const char *front, char **urb_buf_ptr,
u32 byte_offset, u32 byte_width,
int *ident_ptr, int *sent_ptr)
{
const u8 *line_start, *line_end, *next_pixel;
u32 dev_addr = dlfb->base16 + byte_offset;
struct urb *urb = *urb_ptr;
u8 *cmd = *urb_buf_ptr;
u8 *cmd_end = (u8 *) urb->transfer_buffer + urb->transfer_buffer_length;
unsigned long back_buffer_offset = 0;
line_start = (u8 *) (front + byte_offset);
next_pixel = line_start;
line_end = next_pixel + byte_width;
if (dlfb->backing_buffer) {
int offset;
const u8 *back_start = (u8 *) (dlfb->backing_buffer
+ byte_offset);
back_buffer_offset = (unsigned long)back_start - (unsigned long)line_start;
*ident_ptr += dlfb_trim_hline(back_start, &next_pixel,
&byte_width);
offset = next_pixel - line_start;
line_end = next_pixel + byte_width;
dev_addr += offset;
back_start += offset;
line_start += offset;
}
while (next_pixel < line_end) {
dlfb_compress_hline((const uint16_t **) &next_pixel,
(const uint16_t *) line_end, &dev_addr,
(u8 **) &cmd, (u8 *) cmd_end, back_buffer_offset,
ident_ptr);
if (cmd >= cmd_end) {
int len = cmd - (u8 *) urb->transfer_buffer;
if (dlfb_submit_urb(dlfb, urb, len))
return 1; /* lost pixels is set */
*sent_ptr += len;
urb = dlfb_get_urb(dlfb);
if (!urb)
return 1; /* lost_pixels is set */
*urb_ptr = urb;
cmd = urb->transfer_buffer;
cmd_end = &cmd[urb->transfer_buffer_length];
}
}
*urb_buf_ptr = cmd;
return 0;
}
static int dlfb_handle_damage(struct dlfb_data *dlfb, int x, int y, int width, int height)
{
int i, ret;
char *cmd;
cycles_t start_cycles, end_cycles;
int bytes_sent = 0;
int bytes_identical = 0;
struct urb *urb;
int aligned_x;
start_cycles = get_cycles();
mutex_lock(&dlfb->render_mutex);
aligned_x = DL_ALIGN_DOWN(x, sizeof(unsigned long));
width = DL_ALIGN_UP(width + (x-aligned_x), sizeof(unsigned long));
x = aligned_x;
if ((width <= 0) ||
(x + width > dlfb->info->var.xres) ||
(y + height > dlfb->info->var.yres)) {
ret = -EINVAL;
goto unlock_ret;
}
if (!atomic_read(&dlfb->usb_active)) {
ret = 0;
goto unlock_ret;
}
urb = dlfb_get_urb(dlfb);
if (!urb) {
ret = 0;
goto unlock_ret;
}
cmd = urb->transfer_buffer;
for (i = y; i < y + height ; i++) {
const int line_offset = dlfb->info->fix.line_length * i;
const int byte_offset = line_offset + (x * BPP);
if (dlfb_render_hline(dlfb, &urb,
(char *) dlfb->info->fix.smem_start,
&cmd, byte_offset, width * BPP,
&bytes_identical, &bytes_sent))
goto error;
}
if (cmd > (char *) urb->transfer_buffer) {
int len;
if (cmd < (char *) urb->transfer_buffer + urb->transfer_buffer_length)
*cmd++ = 0xAF;
/* Send partial buffer remaining before exiting */
len = cmd - (char *) urb->transfer_buffer;
dlfb_submit_urb(dlfb, urb, len);
bytes_sent += len;
} else
dlfb_urb_completion(urb);
error:
atomic_add(bytes_sent, &dlfb->bytes_sent);
atomic_add(bytes_identical, &dlfb->bytes_identical);
atomic_add(width*height*2, &dlfb->bytes_rendered);
end_cycles = get_cycles();
atomic_add(((unsigned int) ((end_cycles - start_cycles)
>> 10)), /* Kcycles */
&dlfb->cpu_kcycles_used);
ret = 0;
unlock_ret:
mutex_unlock(&dlfb->render_mutex);
return ret;
}
static void dlfb_init_damage(struct dlfb_data *dlfb)
{
dlfb->damage_x = INT_MAX;
dlfb->damage_x2 = 0;
dlfb->damage_y = INT_MAX;
dlfb->damage_y2 = 0;
}
static void dlfb_damage_work(struct work_struct *w)
{
struct dlfb_data *dlfb = container_of(w, struct dlfb_data, damage_work);
int x, x2, y, y2;
spin_lock_irq(&dlfb->damage_lock);
x = dlfb->damage_x;
x2 = dlfb->damage_x2;
y = dlfb->damage_y;
y2 = dlfb->damage_y2;
dlfb_init_damage(dlfb);
spin_unlock_irq(&dlfb->damage_lock);
if (x < x2 && y < y2)
dlfb_handle_damage(dlfb, x, y, x2 - x, y2 - y);
}
static void dlfb_offload_damage(struct dlfb_data *dlfb, int x, int y, int width, int height)
{
unsigned long flags;
int x2 = x + width;
int y2 = y + height;
if (x >= x2 || y >= y2)
return;
spin_lock_irqsave(&dlfb->damage_lock, flags);
dlfb->damage_x = min(x, dlfb->damage_x);
dlfb->damage_x2 = max(x2, dlfb->damage_x2);
dlfb->damage_y = min(y, dlfb->damage_y);
dlfb->damage_y2 = max(y2, dlfb->damage_y2);
spin_unlock_irqrestore(&dlfb->damage_lock, flags);
schedule_work(&dlfb->damage_work);
}
/*
* Path triggered by usermode clients who write to filesystem
* e.g. cat filename > /dev/fb1
* Not used by X Windows or text-mode console. But useful for testing.
* Slow because of extra copy and we must assume all pixels dirty.
*/
static ssize_t dlfb_ops_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos)
{
ssize_t result;
struct dlfb_data *dlfb = info->par;
u32 offset = (u32) *ppos;
result = fb_sys_write(info, buf, count, ppos);
if (result > 0) {
int start = max((int)(offset / info->fix.line_length), 0);
int lines = min((u32)((result / info->fix.line_length) + 1),
(u32)info->var.yres);
dlfb_handle_damage(dlfb, 0, start, info->var.xres,
lines);
}
return result;
}
/* hardware has native COPY command (see libdlo), but not worth it for fbcon */
static void dlfb_ops_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct dlfb_data *dlfb = info->par;
sys_copyarea(info, area);
dlfb_offload_damage(dlfb, area->dx, area->dy,
area->width, area->height);
}
static void dlfb_ops_imageblit(struct fb_info *info,
const struct fb_image *image)
{
struct dlfb_data *dlfb = info->par;
sys_imageblit(info, image);
dlfb_offload_damage(dlfb, image->dx, image->dy,
image->width, image->height);
}
static void dlfb_ops_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
struct dlfb_data *dlfb = info->par;
sys_fillrect(info, rect);
dlfb_offload_damage(dlfb, rect->dx, rect->dy, rect->width,
rect->height);
}
/*
* NOTE: fb_defio.c is holding info->fbdefio.mutex
* Touching ANY framebuffer memory that triggers a page fault
* in fb_defio will cause a deadlock, when it also tries to
* grab the same mutex.
*/
static void dlfb_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist)
{
struct fb_deferred_io_pageref *pageref;
struct dlfb_data *dlfb = info->par;
struct urb *urb;
char *cmd;
cycles_t start_cycles, end_cycles;
int bytes_sent = 0;
int bytes_identical = 0;
int bytes_rendered = 0;
mutex_lock(&dlfb->render_mutex);
if (!fb_defio)
goto unlock_ret;
if (!atomic_read(&dlfb->usb_active))
goto unlock_ret;
start_cycles = get_cycles();
urb = dlfb_get_urb(dlfb);
if (!urb)
goto unlock_ret;
cmd = urb->transfer_buffer;
/* walk the written page list and render each to device */
list_for_each_entry(pageref, pagereflist, list) {
if (dlfb_render_hline(dlfb, &urb, (char *) info->fix.smem_start,
&cmd, pageref->offset, PAGE_SIZE,
&bytes_identical, &bytes_sent))
goto error;
bytes_rendered += PAGE_SIZE;
}
if (cmd > (char *) urb->transfer_buffer) {
int len;
if (cmd < (char *) urb->transfer_buffer + urb->transfer_buffer_length)
*cmd++ = 0xAF;
/* Send partial buffer remaining before exiting */
len = cmd - (char *) urb->transfer_buffer;
dlfb_submit_urb(dlfb, urb, len);
bytes_sent += len;
} else
dlfb_urb_completion(urb);
error:
atomic_add(bytes_sent, &dlfb->bytes_sent);
atomic_add(bytes_identical, &dlfb->bytes_identical);
atomic_add(bytes_rendered, &dlfb->bytes_rendered);
end_cycles = get_cycles();
atomic_add(((unsigned int) ((end_cycles - start_cycles)
>> 10)), /* Kcycles */
&dlfb->cpu_kcycles_used);
unlock_ret:
mutex_unlock(&dlfb->render_mutex);
}
static int dlfb_get_edid(struct dlfb_data *dlfb, char *edid, int len)
{
int i, ret;
char *rbuf;
rbuf = kmalloc(2, GFP_KERNEL);
if (!rbuf)
return 0;
for (i = 0; i < len; i++) {
ret = usb_control_msg(dlfb->udev,
usb_rcvctrlpipe(dlfb->udev, 0), 0x02,
(0x80 | (0x02 << 5)), i << 8, 0xA1,
rbuf, 2, USB_CTRL_GET_TIMEOUT);
if (ret < 2) {
dev_err(&dlfb->udev->dev,
"Read EDID byte %d failed: %d\n", i, ret);
i--;
break;
}
edid[i] = rbuf[1];
}
kfree(rbuf);
return i;
}
static int dlfb_ops_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct dlfb_data *dlfb = info->par;
if (!atomic_read(&dlfb->usb_active))
return 0;
/* TODO: Update X server to get this from sysfs instead */
if (cmd == DLFB_IOCTL_RETURN_EDID) {
void __user *edid = (void __user *)arg;
if (copy_to_user(edid, dlfb->edid, dlfb->edid_size))
return -EFAULT;
return 0;
}
/* TODO: Help propose a standard fb.h ioctl to report mmap damage */
if (cmd == DLFB_IOCTL_REPORT_DAMAGE) {
struct dloarea area;
if (copy_from_user(&area, (void __user *)arg,
sizeof(struct dloarea)))
return -EFAULT;
/*
* If we have a damage-aware client, turn fb_defio "off"
* To avoid perf imact of unnecessary page fault handling.
* Done by resetting the delay for this fb_info to a very
* long period. Pages will become writable and stay that way.
* Reset to normal value when all clients have closed this fb.
*/
if (info->fbdefio)
info->fbdefio->delay = DL_DEFIO_WRITE_DISABLE;
if (area.x < 0)
area.x = 0;
if (area.x > info->var.xres)
area.x = info->var.xres;
if (area.y < 0)
area.y = 0;
if (area.y > info->var.yres)
area.y = info->var.yres;
dlfb_handle_damage(dlfb, area.x, area.y, area.w, area.h);
}
return 0;
}
/* taken from vesafb */
static int
dlfb_ops_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
int err = 0;
if (regno >= info->cmap.len)
return 1;
if (regno < 16) {
if (info->var.red.offset == 10) {
/* 1:5:5:5 */
((u32 *) (info->pseudo_palette))[regno] =
((red & 0xf800) >> 1) |
((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11);
} else {
/* 0:5:6:5 */
((u32 *) (info->pseudo_palette))[regno] =
((red & 0xf800)) |
((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
}
}
return err;
}
/*
* It's common for several clients to have framebuffer open simultaneously.
* e.g. both fbcon and X. Makes things interesting.
* Assumes caller is holding info->lock (for open and release at least)
*/
static int dlfb_ops_open(struct fb_info *info, int user)
{
struct dlfb_data *dlfb = info->par;
/*
* fbcon aggressively connects to first framebuffer it finds,
* preventing other clients (X) from working properly. Usually
* not what the user wants. Fail by default with option to enable.
*/
if ((user == 0) && (!console))
return -EBUSY;
/* If the USB device is gone, we don't accept new opens */
if (dlfb->virtualized)
return -ENODEV;
dlfb->fb_count++;
if (fb_defio && (info->fbdefio == NULL)) {
/* enable defio at last moment if not disabled by client */
struct fb_deferred_io *fbdefio;
fbdefio = kzalloc(sizeof(struct fb_deferred_io), GFP_KERNEL);
if (fbdefio) {
fbdefio->delay = DL_DEFIO_WRITE_DELAY;
fbdefio->sort_pagereflist = true;
fbdefio->deferred_io = dlfb_dpy_deferred_io;
}
info->fbdefio = fbdefio;
fb_deferred_io_init(info);
}
dev_dbg(info->dev, "open, user=%d fb_info=%p count=%d\n",
user, info, dlfb->fb_count);
return 0;
}
static void dlfb_ops_destroy(struct fb_info *info)
{
struct dlfb_data *dlfb = info->par;
cancel_work_sync(&dlfb->damage_work);
mutex_destroy(&dlfb->render_mutex);
if (info->cmap.len != 0)
fb_dealloc_cmap(&info->cmap);
if (info->monspecs.modedb)
fb_destroy_modedb(info->monspecs.modedb);
vfree(info->screen_buffer);
fb_destroy_modelist(&info->modelist);
while (!list_empty(&dlfb->deferred_free)) {
struct dlfb_deferred_free *d = list_entry(dlfb->deferred_free.next, struct dlfb_deferred_free, list);
list_del(&d->list);
vfree(d->mem);
kfree(d);
}
vfree(dlfb->backing_buffer);
kfree(dlfb->edid);
dlfb_free_urb_list(dlfb);
usb_put_dev(dlfb->udev);
kfree(dlfb);
/* Assume info structure is freed after this point */
framebuffer_release(info);
}
/*
* Assumes caller is holding info->lock mutex (for open and release at least)
*/
static int dlfb_ops_release(struct fb_info *info, int user)
{
struct dlfb_data *dlfb = info->par;
dlfb->fb_count--;
if ((dlfb->fb_count == 0) && (info->fbdefio)) {
fb_deferred_io_cleanup(info);
kfree(info->fbdefio);
info->fbdefio = NULL;
}
dev_dbg(info->dev, "release, user=%d count=%d\n", user, dlfb->fb_count);
return 0;
}
/*
* Check whether a video mode is supported by the DisplayLink chip
* We start from monitor's modes, so don't need to filter that here
*/
static int dlfb_is_valid_mode(struct fb_videomode *mode, struct dlfb_data *dlfb)
{
if (mode->xres * mode->yres > dlfb->sku_pixel_limit)
return 0;
return 1;
}
static void dlfb_var_color_format(struct fb_var_screeninfo *var)
{
const struct fb_bitfield red = { 11, 5, 0 };
const struct fb_bitfield green = { 5, 6, 0 };
const struct fb_bitfield blue = { 0, 5, 0 };
var->bits_per_pixel = 16;
var->red = red;
var->green = green;
var->blue = blue;
}
static int dlfb_ops_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct fb_videomode mode;
struct dlfb_data *dlfb = info->par;
/* set device-specific elements of var unrelated to mode */
dlfb_var_color_format(var);
fb_var_to_videomode(&mode, var);
if (!dlfb_is_valid_mode(&mode, dlfb))
return -EINVAL;
return 0;
}
static int dlfb_ops_set_par(struct fb_info *info)
{
struct dlfb_data *dlfb = info->par;
int result;
u16 *pix_framebuffer;
int i;
struct fb_var_screeninfo fvs;
u32 line_length = info->var.xres * (info->var.bits_per_pixel / 8);
/* clear the activate field because it causes spurious miscompares */
fvs = info->var;
fvs.activate = 0;
fvs.vmode &= ~FB_VMODE_SMOOTH_XPAN;
if (!memcmp(&dlfb->current_mode, &fvs, sizeof(struct fb_var_screeninfo)))
return 0;
result = dlfb_realloc_framebuffer(dlfb, info, info->var.yres * line_length);
if (result)
return result;
result = dlfb_set_video_mode(dlfb, &info->var);
if (result)
return result;
dlfb->current_mode = fvs;
info->fix.line_length = line_length;
if (dlfb->fb_count == 0) {
/* paint greenscreen */
pix_framebuffer = (u16 *)info->screen_buffer;
for (i = 0; i < info->fix.smem_len / 2; i++)
pix_framebuffer[i] = 0x37e6;
}
dlfb_handle_damage(dlfb, 0, 0, info->var.xres, info->var.yres);
return 0;
}
/* To fonzi the jukebox (e.g. make blanking changes take effect) */
static char *dlfb_dummy_render(char *buf)
{
*buf++ = 0xAF;
*buf++ = 0x6A; /* copy */
*buf++ = 0x00; /* from address*/
*buf++ = 0x00;
*buf++ = 0x00;
*buf++ = 0x01; /* one pixel */
*buf++ = 0x00; /* to address */
*buf++ = 0x00;
*buf++ = 0x00;
return buf;
}
/*
* In order to come back from full DPMS off, we need to set the mode again
*/
static int dlfb_ops_blank(int blank_mode, struct fb_info *info)
{
struct dlfb_data *dlfb = info->par;
char *bufptr;
struct urb *urb;
dev_dbg(info->dev, "blank, mode %d --> %d\n",
dlfb->blank_mode, blank_mode);
if ((dlfb->blank_mode == FB_BLANK_POWERDOWN) &&
(blank_mode != FB_BLANK_POWERDOWN)) {
/* returning from powerdown requires a fresh modeset */
dlfb_set_video_mode(dlfb, &info->var);
}
urb = dlfb_get_urb(dlfb);
if (!urb)
return 0;
bufptr = (char *) urb->transfer_buffer;
bufptr = dlfb_vidreg_lock(bufptr);
bufptr = dlfb_blanking(bufptr, blank_mode);
bufptr = dlfb_vidreg_unlock(bufptr);
/* seems like a render op is needed to have blank change take effect */
bufptr = dlfb_dummy_render(bufptr);
dlfb_submit_urb(dlfb, urb, bufptr -
(char *) urb->transfer_buffer);
dlfb->blank_mode = blank_mode;
return 0;
}
static const struct fb_ops dlfb_ops = {
.owner = THIS_MODULE,
.fb_read = fb_sys_read,
.fb_write = dlfb_ops_write,
.fb_setcolreg = dlfb_ops_setcolreg,
.fb_fillrect = dlfb_ops_fillrect,
.fb_copyarea = dlfb_ops_copyarea,
.fb_imageblit = dlfb_ops_imageblit,
.fb_mmap = dlfb_ops_mmap,
.fb_ioctl = dlfb_ops_ioctl,
.fb_open = dlfb_ops_open,
.fb_release = dlfb_ops_release,
.fb_blank = dlfb_ops_blank,
.fb_check_var = dlfb_ops_check_var,
.fb_set_par = dlfb_ops_set_par,
.fb_destroy = dlfb_ops_destroy,
};
static void dlfb_deferred_vfree(struct dlfb_data *dlfb, void *mem)
{
struct dlfb_deferred_free *d = kmalloc(sizeof(struct dlfb_deferred_free), GFP_KERNEL);
if (!d)
return;
d->mem = mem;
list_add(&d->list, &dlfb->deferred_free);
}
/*
* Assumes &info->lock held by caller
* Assumes no active clients have framebuffer open
*/
static int dlfb_realloc_framebuffer(struct dlfb_data *dlfb, struct fb_info *info, u32 new_len)
{
u32 old_len = info->fix.smem_len;
const void *old_fb = info->screen_buffer;
unsigned char *new_fb;
unsigned char *new_back = NULL;
new_len = PAGE_ALIGN(new_len);
if (new_len > old_len) {
/*
* Alloc system memory for virtual framebuffer
*/
new_fb = vmalloc(new_len);
if (!new_fb) {
dev_err(info->dev, "Virtual framebuffer alloc failed\n");
return -ENOMEM;
}
memset(new_fb, 0xff, new_len);
if (info->screen_buffer) {
memcpy(new_fb, old_fb, old_len);
dlfb_deferred_vfree(dlfb, info->screen_buffer);
}
info->screen_buffer = new_fb;
info->fix.smem_len = new_len;
info->fix.smem_start = (unsigned long) new_fb;
info->flags = udlfb_info_flags;
/*
* Second framebuffer copy to mirror the framebuffer state
* on the physical USB device. We can function without this.
* But with imperfect damage info we may send pixels over USB
* that were, in fact, unchanged - wasting limited USB bandwidth
*/
if (shadow)
new_back = vzalloc(new_len);
if (!new_back)
dev_info(info->dev,
"No shadow/backing buffer allocated\n");
else {
dlfb_deferred_vfree(dlfb, dlfb->backing_buffer);
dlfb->backing_buffer = new_back;
}
}
return 0;
}
/*
* 1) Get EDID from hw, or use sw default
* 2) Parse into various fb_info structs
* 3) Allocate virtual framebuffer memory to back highest res mode
*
* Parses EDID into three places used by various parts of fbdev:
* fb_var_screeninfo contains the timing of the monitor's preferred mode
* fb_info.monspecs is full parsed EDID info, including monspecs.modedb
* fb_info.modelist is a linked list of all monitor & VESA modes which work
*
* If EDID is not readable/valid, then modelist is all VESA modes,
* monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode
* Returns 0 if successful
*/
static int dlfb_setup_modes(struct dlfb_data *dlfb,
struct fb_info *info,
char *default_edid, size_t default_edid_size)
{
char *edid;
int i, result = 0, tries = 3;
struct device *dev = info->device;
struct fb_videomode *mode;
const struct fb_videomode *default_vmode = NULL;
if (info->dev) {
/* only use mutex if info has been registered */
mutex_lock(&info->lock);
/* parent device is used otherwise */
dev = info->dev;
}
edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
if (!edid) {
result = -ENOMEM;
goto error;
}
fb_destroy_modelist(&info->modelist);
memset(&info->monspecs, 0, sizeof(info->monspecs));
/*
* Try to (re)read EDID from hardware first
* EDID data may return, but not parse as valid
* Try again a few times, in case of e.g. analog cable noise
*/
while (tries--) {
i = dlfb_get_edid(dlfb, edid, EDID_LENGTH);
if (i >= EDID_LENGTH)
fb_edid_to_monspecs(edid, &info->monspecs);
if (info->monspecs.modedb_len > 0) {
dlfb->edid = edid;
dlfb->edid_size = i;
break;
}
}
/* If that fails, use a previously returned EDID if available */
if (info->monspecs.modedb_len == 0) {
dev_err(dev, "Unable to get valid EDID from device/display\n");
if (dlfb->edid) {
fb_edid_to_monspecs(dlfb->edid, &info->monspecs);
if (info->monspecs.modedb_len > 0)
dev_err(dev, "Using previously queried EDID\n");
}
}
/* If that fails, use the default EDID we were handed */
if (info->monspecs.modedb_len == 0) {
if (default_edid_size >= EDID_LENGTH) {
fb_edid_to_monspecs(default_edid, &info->monspecs);
if (info->monspecs.modedb_len > 0) {
memcpy(edid, default_edid, default_edid_size);
dlfb->edid = edid;
dlfb->edid_size = default_edid_size;
dev_err(dev, "Using default/backup EDID\n");
}
}
}
/* If we've got modes, let's pick a best default mode */
if (info->monspecs.modedb_len > 0) {
for (i = 0; i < info->monspecs.modedb_len; i++) {
mode = &info->monspecs.modedb[i];
if (dlfb_is_valid_mode(mode, dlfb)) {
fb_add_videomode(mode, &info->modelist);
} else {
dev_dbg(dev, "Specified mode %dx%d too big\n",
mode->xres, mode->yres);
if (i == 0)
/* if we've removed top/best mode */
info->monspecs.misc
&= ~FB_MISC_1ST_DETAIL;
}
}
default_vmode = fb_find_best_display(&info->monspecs,
&info->modelist);
}
/* If everything else has failed, fall back to safe default mode */
if (default_vmode == NULL) {
struct fb_videomode fb_vmode = {0};
/*
* Add the standard VESA modes to our modelist
* Since we don't have EDID, there may be modes that
* overspec monitor and/or are incorrect aspect ratio, etc.
* But at least the user has a chance to choose
*/
for (i = 0; i < VESA_MODEDB_SIZE; i++) {
mode = (struct fb_videomode *)&vesa_modes[i];
if (dlfb_is_valid_mode(mode, dlfb))
fb_add_videomode(mode, &info->modelist);
else
dev_dbg(dev, "VESA mode %dx%d too big\n",
mode->xres, mode->yres);
}
/*
* default to resolution safe for projectors
* (since they are most common case without EDID)
*/
fb_vmode.xres = 800;
fb_vmode.yres = 600;
fb_vmode.refresh = 60;
default_vmode = fb_find_nearest_mode(&fb_vmode,
&info->modelist);
}
/* If we have good mode and no active clients*/
if ((default_vmode != NULL) && (dlfb->fb_count == 0)) {
fb_videomode_to_var(&info->var, default_vmode);
dlfb_var_color_format(&info->var);
/*
* with mode size info, we can now alloc our framebuffer.
*/
memcpy(&info->fix, &dlfb_fix, sizeof(dlfb_fix));
} else
result = -EINVAL;
error:
if (edid && (dlfb->edid != edid))
kfree(edid);
if (info->dev)
mutex_unlock(&info->lock);
return result;
}
static ssize_t metrics_bytes_rendered_show(struct device *fbdev,
struct device_attribute *a, char *buf) {
struct fb_info *fb_info = dev_get_drvdata(fbdev);
struct dlfb_data *dlfb = fb_info->par;
return sysfs_emit(buf, "%u\n",
atomic_read(&dlfb->bytes_rendered));
}
static ssize_t metrics_bytes_identical_show(struct device *fbdev,
struct device_attribute *a, char *buf) {
struct fb_info *fb_info = dev_get_drvdata(fbdev);
struct dlfb_data *dlfb = fb_info->par;
return sysfs_emit(buf, "%u\n",
atomic_read(&dlfb->bytes_identical));
}
static ssize_t metrics_bytes_sent_show(struct device *fbdev,
struct device_attribute *a, char *buf) {
struct fb_info *fb_info = dev_get_drvdata(fbdev);
struct dlfb_data *dlfb = fb_info->par;
return sysfs_emit(buf, "%u\n",
atomic_read(&dlfb->bytes_sent));
}
static ssize_t metrics_cpu_kcycles_used_show(struct device *fbdev,
struct device_attribute *a, char *buf) {
struct fb_info *fb_info = dev_get_drvdata(fbdev);
struct dlfb_data *dlfb = fb_info->par;
return sysfs_emit(buf, "%u\n",
atomic_read(&dlfb->cpu_kcycles_used));
}
static ssize_t edid_show(
struct file *filp,
struct kobject *kobj, struct bin_attribute *a,
char *buf, loff_t off, size_t count) {
struct device *fbdev = kobj_to_dev(kobj);
struct fb_info *fb_info = dev_get_drvdata(fbdev);
struct dlfb_data *dlfb = fb_info->par;
if (dlfb->edid == NULL)
return 0;
if ((off >= dlfb->edid_size) || (count > dlfb->edid_size))
return 0;
if (off + count > dlfb->edid_size)
count = dlfb->edid_size - off;
memcpy(buf, dlfb->edid, count);
return count;
}
static ssize_t edid_store(
struct file *filp,
struct kobject *kobj, struct bin_attribute *a,
char *src, loff_t src_off, size_t src_size) {
struct device *fbdev = kobj_to_dev(kobj);
struct fb_info *fb_info = dev_get_drvdata(fbdev);
struct dlfb_data *dlfb = fb_info->par;
int ret;
/* We only support write of entire EDID at once, no offset*/
if ((src_size != EDID_LENGTH) || (src_off != 0))
return -EINVAL;
ret = dlfb_setup_modes(dlfb, fb_info, src, src_size);
if (ret)
return ret;
if (!dlfb->edid || memcmp(src, dlfb->edid, src_size))
return -EINVAL;
ret = dlfb_ops_set_par(fb_info);
if (ret)
return ret;
return src_size;
}
static ssize_t metrics_reset_store(struct device *fbdev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(fbdev);
struct dlfb_data *dlfb = fb_info->par;
atomic_set(&dlfb->bytes_rendered, 0);
atomic_set(&dlfb->bytes_identical, 0);
atomic_set(&dlfb->bytes_sent, 0);
atomic_set(&dlfb->cpu_kcycles_used, 0);
return count;
}
static const struct bin_attribute edid_attr = {
.attr.name = "edid",
.attr.mode = 0666,
.size = EDID_LENGTH,
.read = edid_show,
.write = edid_store
};
static const struct device_attribute fb_device_attrs[] = {
__ATTR_RO(metrics_bytes_rendered),
__ATTR_RO(metrics_bytes_identical),
__ATTR_RO(metrics_bytes_sent),
__ATTR_RO(metrics_cpu_kcycles_used),
__ATTR(metrics_reset, S_IWUSR, NULL, metrics_reset_store),
};
/*
* This is necessary before we can communicate with the display controller.
*/
static int dlfb_select_std_channel(struct dlfb_data *dlfb)
{
int ret;
static const u8 set_def_chn[] = {
0x57, 0xCD, 0xDC, 0xA7,
0x1C, 0x88, 0x5E, 0x15,
0x60, 0xFE, 0xC6, 0x97,
0x16, 0x3D, 0x47, 0xF2 };
ret = usb_control_msg_send(dlfb->udev, 0, NR_USB_REQUEST_CHANNEL,
(USB_DIR_OUT | USB_TYPE_VENDOR), 0, 0,
&set_def_chn, sizeof(set_def_chn), USB_CTRL_SET_TIMEOUT,
GFP_KERNEL);
return ret;
}
static int dlfb_parse_vendor_descriptor(struct dlfb_data *dlfb,
struct usb_interface *intf)
{
char *desc;
char *buf;
char *desc_end;
int total_len;
buf = kzalloc(MAX_VENDOR_DESCRIPTOR_SIZE, GFP_KERNEL);
if (!buf)
return false;
desc = buf;
total_len = usb_get_descriptor(interface_to_usbdev(intf),
0x5f, /* vendor specific */
0, desc, MAX_VENDOR_DESCRIPTOR_SIZE);
/* if not found, look in configuration descriptor */
if (total_len < 0) {
if (0 == usb_get_extra_descriptor(intf->cur_altsetting,
0x5f, &desc))
total_len = (int) desc[0];
}
if (total_len > 5) {
dev_info(&intf->dev,
"vendor descriptor length: %d data: %11ph\n",
total_len, desc);
if ((desc[0] != total_len) || /* descriptor length */
(desc[1] != 0x5f) || /* vendor descriptor type */
(desc[2] != 0x01) || /* version (2 bytes) */
(desc[3] != 0x00) ||
(desc[4] != total_len - 2)) /* length after type */
goto unrecognized;
desc_end = desc + total_len;
desc += 5; /* the fixed header we've already parsed */
while (desc < desc_end) {
u8 length;
u16 key;
key = *desc++;
key |= (u16)*desc++ << 8;
length = *desc++;
switch (key) {
case 0x0200: { /* max_area */
u32 max_area = *desc++;
max_area |= (u32)*desc++ << 8;
max_area |= (u32)*desc++ << 16;
max_area |= (u32)*desc++ << 24;
dev_warn(&intf->dev,
"DL chip limited to %d pixel modes\n",
max_area);
dlfb->sku_pixel_limit = max_area;
break;
}
default:
break;
}
desc += length;
}
} else {
dev_info(&intf->dev, "vendor descriptor not available (%d)\n",
total_len);
}
goto success;
unrecognized:
/* allow udlfb to load for now even if firmware unrecognized */
dev_err(&intf->dev, "Unrecognized vendor firmware descriptor\n");
success:
kfree(buf);
return true;
}
static int dlfb_usb_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
int i;
const struct device_attribute *attr;
struct dlfb_data *dlfb;
struct fb_info *info;
int retval;
struct usb_device *usbdev = interface_to_usbdev(intf);
static u8 out_ep[] = {OUT_EP_NUM + USB_DIR_OUT, 0};
/* usb initialization */
dlfb = kzalloc(sizeof(*dlfb), GFP_KERNEL);
if (!dlfb) {
dev_err(&intf->dev, "%s: failed to allocate dlfb\n", __func__);
return -ENOMEM;
}
INIT_LIST_HEAD(&dlfb->deferred_free);
dlfb->udev = usb_get_dev(usbdev);
usb_set_intfdata(intf, dlfb);
if (!usb_check_bulk_endpoints(intf, out_ep)) {
dev_err(&intf->dev, "Invalid DisplayLink device!\n");
retval = -EINVAL;
goto error;
}
dev_dbg(&intf->dev, "console enable=%d\n", console);
dev_dbg(&intf->dev, "fb_defio enable=%d\n", fb_defio);
dev_dbg(&intf->dev, "shadow enable=%d\n", shadow);
dlfb->sku_pixel_limit = 2048 * 1152; /* default to maximum */
if (!dlfb_parse_vendor_descriptor(dlfb, intf)) {
dev_err(&intf->dev,
"firmware not recognized, incompatible device?\n");
retval = -ENODEV;
goto error;
}
if (pixel_limit) {
dev_warn(&intf->dev,
"DL chip limit of %d overridden to %d\n",
dlfb->sku_pixel_limit, pixel_limit);
dlfb->sku_pixel_limit = pixel_limit;
}
/* allocates framebuffer driver structure, not framebuffer memory */
info = framebuffer_alloc(0, &dlfb->udev->dev);
if (!info) {
retval = -ENOMEM;
goto error;
}
dlfb->info = info;
info->par = dlfb;
info->pseudo_palette = dlfb->pseudo_palette;
dlfb->ops = dlfb_ops;
info->fbops = &dlfb->ops;
mutex_init(&dlfb->render_mutex);
dlfb_init_damage(dlfb);
spin_lock_init(&dlfb->damage_lock);
INIT_WORK(&dlfb->damage_work, dlfb_damage_work);
INIT_LIST_HEAD(&info->modelist);
if (!dlfb_alloc_urb_list(dlfb, WRITES_IN_FLIGHT, MAX_TRANSFER)) {
retval = -ENOMEM;
dev_err(&intf->dev, "unable to allocate urb list\n");
goto error;
}
/* We don't register a new USB class. Our client interface is dlfbev */
retval = fb_alloc_cmap(&info->cmap, 256, 0);
if (retval < 0) {
dev_err(info->device, "cmap allocation failed: %d\n", retval);
goto error;
}
retval = dlfb_setup_modes(dlfb, info, NULL, 0);
if (retval != 0) {
dev_err(info->device,
"unable to find common mode for display and adapter\n");
goto error;
}
/* ready to begin using device */
atomic_set(&dlfb->usb_active, 1);
dlfb_select_std_channel(dlfb);
dlfb_ops_check_var(&info->var, info);
retval = dlfb_ops_set_par(info);
if (retval)
goto error;
retval = register_framebuffer(info);
if (retval < 0) {
dev_err(info->device, "unable to register framebuffer: %d\n",
retval);
goto error;
}
for (i = 0; i < ARRAY_SIZE(fb_device_attrs); i++) {
attr = &fb_device_attrs[i];
retval = device_create_file(info->dev, attr);
if (retval)
dev_warn(info->device,
"failed to create '%s' attribute: %d\n",
attr->attr.name, retval);
}
retval = device_create_bin_file(info->dev, &edid_attr);
if (retval)
dev_warn(info->device, "failed to create '%s' attribute: %d\n",
edid_attr.attr.name, retval);
dev_info(info->device,
"%s is DisplayLink USB device (%dx%d, %dK framebuffer memory)\n",
dev_name(info->dev), info->var.xres, info->var.yres,
((dlfb->backing_buffer) ?
info->fix.smem_len * 2 : info->fix.smem_len) >> 10);
return 0;
error:
if (dlfb->info) {
dlfb_ops_destroy(dlfb->info);
} else {
usb_put_dev(dlfb->udev);
kfree(dlfb);
}
return retval;
}
static void dlfb_usb_disconnect(struct usb_interface *intf)
{
struct dlfb_data *dlfb;
struct fb_info *info;
int i;
dlfb = usb_get_intfdata(intf);
info = dlfb->info;
dev_dbg(&intf->dev, "USB disconnect starting\n");
/* we virtualize until all fb clients release. Then we free */
dlfb->virtualized = true;
/* When non-active we'll update virtual framebuffer, but no new urbs */
atomic_set(&dlfb->usb_active, 0);
/* this function will wait for all in-flight urbs to complete */
dlfb_free_urb_list(dlfb);
/* remove udlfb's sysfs interfaces */
for (i = 0; i < ARRAY_SIZE(fb_device_attrs); i++)
device_remove_file(info->dev, &fb_device_attrs[i]);
device_remove_bin_file(info->dev, &edid_attr);
unregister_framebuffer(info);
}
static struct usb_driver dlfb_driver = {
.name = "udlfb",
.probe = dlfb_usb_probe,
.disconnect = dlfb_usb_disconnect,
.id_table = id_table,
};
module_usb_driver(dlfb_driver);
static void dlfb_urb_completion(struct urb *urb)
{
struct urb_node *unode = urb->context;
struct dlfb_data *dlfb = unode->dlfb;
unsigned long flags;
switch (urb->status) {
case 0:
/* success */
break;
case -ECONNRESET:
case -ENOENT:
case -ESHUTDOWN:
/* sync/async unlink faults aren't errors */
break;
default:
dev_err(&dlfb->udev->dev,
"%s - nonzero write bulk status received: %d\n",
__func__, urb->status);
atomic_set(&dlfb->lost_pixels, 1);
break;
}
urb->transfer_buffer_length = dlfb->urbs.size; /* reset to actual */
spin_lock_irqsave(&dlfb->urbs.lock, flags);
list_add_tail(&unode->entry, &dlfb->urbs.list);
dlfb->urbs.available++;
spin_unlock_irqrestore(&dlfb->urbs.lock, flags);
up(&dlfb->urbs.limit_sem);
}
static void dlfb_free_urb_list(struct dlfb_data *dlfb)
{
int count = dlfb->urbs.count;
struct list_head *node;
struct urb_node *unode;
struct urb *urb;
/* keep waiting and freeing, until we've got 'em all */
while (count--) {
down(&dlfb->urbs.limit_sem);
spin_lock_irq(&dlfb->urbs.lock);
node = dlfb->urbs.list.next; /* have reserved one with sem */
list_del_init(node);
spin_unlock_irq(&dlfb->urbs.lock);
unode = list_entry(node, struct urb_node, entry);
urb = unode->urb;
/* Free each separately allocated piece */
usb_free_coherent(urb->dev, dlfb->urbs.size,
urb->transfer_buffer, urb->transfer_dma);
usb_free_urb(urb);
kfree(node);
}
dlfb->urbs.count = 0;
}
static int dlfb_alloc_urb_list(struct dlfb_data *dlfb, int count, size_t size)
{
struct urb *urb;
struct urb_node *unode;
char *buf;
size_t wanted_size = count * size;
spin_lock_init(&dlfb->urbs.lock);
retry:
dlfb->urbs.size = size;
INIT_LIST_HEAD(&dlfb->urbs.list);
sema_init(&dlfb->urbs.limit_sem, 0);
dlfb->urbs.count = 0;
dlfb->urbs.available = 0;
while (dlfb->urbs.count * size < wanted_size) {
unode = kzalloc(sizeof(*unode), GFP_KERNEL);
if (!unode)
break;
unode->dlfb = dlfb;
urb = usb_alloc_urb(0, GFP_KERNEL);
if (!urb) {
kfree(unode);
break;
}
unode->urb = urb;
buf = usb_alloc_coherent(dlfb->udev, size, GFP_KERNEL,
&urb->transfer_dma);
if (!buf) {
kfree(unode);
usb_free_urb(urb);
if (size > PAGE_SIZE) {
size /= 2;
dlfb_free_urb_list(dlfb);
goto retry;
}
break;
}
/* urb->transfer_buffer_length set to actual before submit */
usb_fill_bulk_urb(urb, dlfb->udev,
usb_sndbulkpipe(dlfb->udev, OUT_EP_NUM),
buf, size, dlfb_urb_completion, unode);
urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
list_add_tail(&unode->entry, &dlfb->urbs.list);
up(&dlfb->urbs.limit_sem);
dlfb->urbs.count++;
dlfb->urbs.available++;
}
return dlfb->urbs.count;
}
static struct urb *dlfb_get_urb(struct dlfb_data *dlfb)
{
int ret;
struct list_head *entry;
struct urb_node *unode;
/* Wait for an in-flight buffer to complete and get re-queued */
ret = down_timeout(&dlfb->urbs.limit_sem, GET_URB_TIMEOUT);
if (ret) {
atomic_set(&dlfb->lost_pixels, 1);
dev_warn(&dlfb->udev->dev,
"wait for urb interrupted: %d available: %d\n",
ret, dlfb->urbs.available);
return NULL;
}
spin_lock_irq(&dlfb->urbs.lock);
BUG_ON(list_empty(&dlfb->urbs.list)); /* reserved one with limit_sem */
entry = dlfb->urbs.list.next;
list_del_init(entry);
dlfb->urbs.available--;
spin_unlock_irq(&dlfb->urbs.lock);
unode = list_entry(entry, struct urb_node, entry);
return unode->urb;
}
static int dlfb_submit_urb(struct dlfb_data *dlfb, struct urb *urb, size_t len)
{
int ret;
BUG_ON(len > dlfb->urbs.size);
urb->transfer_buffer_length = len; /* set to actual payload len */
ret = usb_submit_urb(urb, GFP_KERNEL);
if (ret) {
dlfb_urb_completion(urb); /* because no one else will */
atomic_set(&dlfb->lost_pixels, 1);
dev_err(&dlfb->udev->dev, "submit urb error: %d\n", ret);
}
return ret;
}
module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
MODULE_PARM_DESC(console, "Allow fbcon to open framebuffer");
module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
MODULE_PARM_DESC(fb_defio, "Page fault detection of mmap writes");
module_param(shadow, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
MODULE_PARM_DESC(shadow, "Shadow vid mem. Disable to save mem but lose perf");
module_param(pixel_limit, int, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
MODULE_PARM_DESC(pixel_limit, "Force limit on max mode (in x*y pixels)");
MODULE_AUTHOR("Roberto De Ioris <[email protected]>, "
"Jaya Kumar <[email protected]>, "
"Bernie Thompson <[email protected]>");
MODULE_DESCRIPTION("DisplayLink kernel framebuffer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/udlfb.c |
/*
* SGI GBE frame buffer driver
*
* Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
* Copyright (C) 2002 Vivien Chappelier <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/gfp.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/io.h>
#ifdef CONFIG_MIPS
#include <asm/addrspace.h>
#endif
#include <asm/byteorder.h>
#include <asm/tlbflush.h>
#include <video/gbe.h>
static struct sgi_gbe *gbe;
struct gbefb_par {
struct fb_var_screeninfo var;
struct gbe_timing_info timing;
int wc_cookie;
int valid;
};
#define GBE_BASE 0x16000000 /* SGI O2 */
/* macro for fastest write-though access to the framebuffer */
#ifdef CONFIG_MIPS
#ifdef CONFIG_CPU_R10000
#define pgprot_fb(_prot) (((_prot) & (~_CACHE_MASK)) | _CACHE_UNCACHED_ACCELERATED)
#else
#define pgprot_fb(_prot) (((_prot) & (~_CACHE_MASK)) | _CACHE_CACHABLE_NO_WA)
#endif
#endif
/*
* RAM we reserve for the frame buffer. This defines the maximum screen
* size
*/
#if CONFIG_FB_GBE_MEM > 8
#error GBE Framebuffer cannot use more than 8MB of memory
#endif
#define TILE_SHIFT 16
#define TILE_SIZE (1 << TILE_SHIFT)
#define TILE_MASK (TILE_SIZE - 1)
static unsigned int gbe_mem_size = CONFIG_FB_GBE_MEM * 1024*1024;
static void *gbe_mem;
static dma_addr_t gbe_dma_addr;
static unsigned long gbe_mem_phys;
static struct {
uint16_t *cpu;
dma_addr_t dma;
} gbe_tiles;
static int gbe_revision;
static int ypan, ywrap;
static uint32_t pseudo_palette[16];
static uint32_t gbe_cmap[256];
static int gbe_turned_on; /* 0 turned off, 1 turned on */
static char *mode_option = NULL;
/* default CRT mode */
static struct fb_var_screeninfo default_var_CRT = {
/* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.xoffset = 0,
.yoffset = 0,
.bits_per_pixel = 8,
.grayscale = 0,
.red = { 0, 8, 0 },
.green = { 0, 8, 0 },
.blue = { 0, 8, 0 },
.transp = { 0, 0, 0 },
.nonstd = 0,
.activate = 0,
.height = -1,
.width = -1,
.accel_flags = 0,
.pixclock = 39722, /* picoseconds */
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
};
/* default LCD mode */
static struct fb_var_screeninfo default_var_LCD = {
/* 1600x1024, 8 bpp */
.xres = 1600,
.yres = 1024,
.xres_virtual = 1600,
.yres_virtual = 1024,
.xoffset = 0,
.yoffset = 0,
.bits_per_pixel = 8,
.grayscale = 0,
.red = { 0, 8, 0 },
.green = { 0, 8, 0 },
.blue = { 0, 8, 0 },
.transp = { 0, 0, 0 },
.nonstd = 0,
.activate = 0,
.height = -1,
.width = -1,
.accel_flags = 0,
.pixclock = 9353,
.left_margin = 20,
.right_margin = 30,
.upper_margin = 37,
.lower_margin = 3,
.hsync_len = 20,
.vsync_len = 3,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
/* default modedb mode */
/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
static struct fb_videomode default_mode_CRT = {
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39722,
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
};
/* 1600x1024 SGI flatpanel 1600sw */
static struct fb_videomode default_mode_LCD = {
/* 1600x1024, 8 bpp */
.xres = 1600,
.yres = 1024,
.pixclock = 9353,
.left_margin = 20,
.right_margin = 30,
.upper_margin = 37,
.lower_margin = 3,
.hsync_len = 20,
.vsync_len = 3,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_videomode *default_mode = &default_mode_CRT;
static struct fb_var_screeninfo *default_var = &default_var_CRT;
static int flat_panel_enabled = 0;
static void gbe_reset(void)
{
/* Turn on dotclock PLL */
gbe->ctrlstat = 0x300aa000;
}
/*
* Function: gbe_turn_off
* Parameters: (None)
* Description: This should turn off the monitor and gbe. This is used
* when switching between the serial console and the graphics
* console.
*/
static void gbe_turn_off(void)
{
int i;
unsigned int val, y, vpixen_off;
gbe_turned_on = 0;
/* check if pixel counter is on */
val = gbe->vt_xy;
if (GET_GBE_FIELD(VT_XY, FREEZE, val) == 1)
return;
/* turn off DMA */
val = gbe->ovr_control;
SET_GBE_FIELD(OVR_CONTROL, OVR_DMA_ENABLE, val, 0);
gbe->ovr_control = val;
udelay(1000);
val = gbe->frm_control;
SET_GBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, val, 0);
gbe->frm_control = val;
udelay(1000);
val = gbe->did_control;
SET_GBE_FIELD(DID_CONTROL, DID_DMA_ENABLE, val, 0);
gbe->did_control = val;
udelay(1000);
/* We have to wait through two vertical retrace periods before
* the pixel DMA is turned off for sure. */
for (i = 0; i < 10000; i++) {
val = gbe->frm_inhwctrl;
if (GET_GBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, val)) {
udelay(10);
} else {
val = gbe->ovr_inhwctrl;
if (GET_GBE_FIELD(OVR_INHWCTRL, OVR_DMA_ENABLE, val)) {
udelay(10);
} else {
val = gbe->did_inhwctrl;
if (GET_GBE_FIELD(DID_INHWCTRL, DID_DMA_ENABLE, val)) {
udelay(10);
} else
break;
}
}
}
if (i == 10000)
printk(KERN_ERR "gbefb: turn off DMA timed out\n");
/* wait for vpixen_off */
val = gbe->vt_vpixen;
vpixen_off = GET_GBE_FIELD(VT_VPIXEN, VPIXEN_OFF, val);
for (i = 0; i < 100000; i++) {
val = gbe->vt_xy;
y = GET_GBE_FIELD(VT_XY, Y, val);
if (y < vpixen_off)
break;
udelay(1);
}
if (i == 100000)
printk(KERN_ERR
"gbefb: wait for vpixen_off timed out\n");
for (i = 0; i < 10000; i++) {
val = gbe->vt_xy;
y = GET_GBE_FIELD(VT_XY, Y, val);
if (y > vpixen_off)
break;
udelay(1);
}
if (i == 10000)
printk(KERN_ERR "gbefb: wait for vpixen_off timed out\n");
/* turn off pixel counter */
val = 0;
SET_GBE_FIELD(VT_XY, FREEZE, val, 1);
gbe->vt_xy = val;
mdelay(10);
for (i = 0; i < 10000; i++) {
val = gbe->vt_xy;
if (GET_GBE_FIELD(VT_XY, FREEZE, val) != 1)
udelay(10);
else
break;
}
if (i == 10000)
printk(KERN_ERR "gbefb: turn off pixel clock timed out\n");
/* turn off dot clock */
val = gbe->dotclock;
SET_GBE_FIELD(DOTCLK, RUN, val, 0);
gbe->dotclock = val;
mdelay(10);
for (i = 0; i < 10000; i++) {
val = gbe->dotclock;
if (GET_GBE_FIELD(DOTCLK, RUN, val))
udelay(10);
else
break;
}
if (i == 10000)
printk(KERN_ERR "gbefb: turn off dotclock timed out\n");
/* reset the frame DMA FIFO */
val = gbe->frm_size_tile;
SET_GBE_FIELD(FRM_SIZE_TILE, FRM_FIFO_RESET, val, 1);
gbe->frm_size_tile = val;
SET_GBE_FIELD(FRM_SIZE_TILE, FRM_FIFO_RESET, val, 0);
gbe->frm_size_tile = val;
}
static void gbe_turn_on(void)
{
unsigned int val, i;
/*
* Check if pixel counter is off, for unknown reason this
* code hangs Visual Workstations
*/
if (gbe_revision < 2) {
val = gbe->vt_xy;
if (GET_GBE_FIELD(VT_XY, FREEZE, val) == 0)
return;
}
/* turn on dot clock */
val = gbe->dotclock;
SET_GBE_FIELD(DOTCLK, RUN, val, 1);
gbe->dotclock = val;
mdelay(10);
for (i = 0; i < 10000; i++) {
val = gbe->dotclock;
if (GET_GBE_FIELD(DOTCLK, RUN, val) != 1)
udelay(10);
else
break;
}
if (i == 10000)
printk(KERN_ERR "gbefb: turn on dotclock timed out\n");
/* turn on pixel counter */
val = 0;
SET_GBE_FIELD(VT_XY, FREEZE, val, 0);
gbe->vt_xy = val;
mdelay(10);
for (i = 0; i < 10000; i++) {
val = gbe->vt_xy;
if (GET_GBE_FIELD(VT_XY, FREEZE, val))
udelay(10);
else
break;
}
if (i == 10000)
printk(KERN_ERR "gbefb: turn on pixel clock timed out\n");
/* turn on DMA */
val = gbe->frm_control;
SET_GBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, val, 1);
gbe->frm_control = val;
udelay(1000);
for (i = 0; i < 10000; i++) {
val = gbe->frm_inhwctrl;
if (GET_GBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, val) != 1)
udelay(10);
else
break;
}
if (i == 10000)
printk(KERN_ERR "gbefb: turn on DMA timed out\n");
gbe_turned_on = 1;
}
static void gbe_loadcmap(void)
{
int i, j;
for (i = 0; i < 256; i++) {
for (j = 0; j < 1000 && gbe->cm_fifo >= 63; j++)
udelay(10);
if (j == 1000)
printk(KERN_ERR "gbefb: cmap FIFO timeout\n");
gbe->cmap[i] = gbe_cmap[i];
}
}
/*
* Blank the display.
*/
static int gbefb_blank(int blank, struct fb_info *info)
{
/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
switch (blank) {
case FB_BLANK_UNBLANK: /* unblank */
gbe_turn_on();
gbe_loadcmap();
break;
case FB_BLANK_NORMAL: /* blank */
gbe_turn_off();
break;
default:
/* Nothing */
break;
}
return 0;
}
/*
* Setup flatpanel related registers.
*/
static void gbefb_setup_flatpanel(struct gbe_timing_info *timing)
{
int fp_wid, fp_hgt, fp_vbs, fp_vbe;
u32 outputVal = 0;
SET_GBE_FIELD(VT_FLAGS, HDRV_INVERT, outputVal,
(timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1);
SET_GBE_FIELD(VT_FLAGS, VDRV_INVERT, outputVal,
(timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1);
gbe->vt_flags = outputVal;
/* Turn on the flat panel */
fp_wid = 1600;
fp_hgt = 1024;
fp_vbs = 0;
fp_vbe = 1600;
timing->pll_m = 4;
timing->pll_n = 1;
timing->pll_p = 0;
outputVal = 0;
SET_GBE_FIELD(FP_DE, ON, outputVal, fp_vbs);
SET_GBE_FIELD(FP_DE, OFF, outputVal, fp_vbe);
gbe->fp_de = outputVal;
outputVal = 0;
SET_GBE_FIELD(FP_HDRV, OFF, outputVal, fp_wid);
gbe->fp_hdrv = outputVal;
outputVal = 0;
SET_GBE_FIELD(FP_VDRV, ON, outputVal, 1);
SET_GBE_FIELD(FP_VDRV, OFF, outputVal, fp_hgt + 1);
gbe->fp_vdrv = outputVal;
}
struct gbe_pll_info {
int clock_rate;
int fvco_min;
int fvco_max;
};
static struct gbe_pll_info gbe_pll_table[2] = {
{ 20, 80, 220 },
{ 27, 80, 220 },
};
static int compute_gbe_timing(struct fb_var_screeninfo *var,
struct gbe_timing_info *timing)
{
int pll_m, pll_n, pll_p, error, best_m, best_n, best_p, best_error;
int pixclock;
struct gbe_pll_info *gbe_pll;
if (gbe_revision < 2)
gbe_pll = &gbe_pll_table[0];
else
gbe_pll = &gbe_pll_table[1];
/* Determine valid resolution and timing
* GBE crystal runs at 20Mhz or 27Mhz
* pll_m, pll_n, pll_p define the following frequencies
* fvco = pll_m * 20Mhz / pll_n
* fout = fvco / (2**pll_p) */
best_error = 1000000000;
best_n = best_m = best_p = 0;
for (pll_p = 0; pll_p < 4; pll_p++)
for (pll_m = 1; pll_m < 256; pll_m++)
for (pll_n = 1; pll_n < 64; pll_n++) {
pixclock = (1000000 / gbe_pll->clock_rate) *
(pll_n << pll_p) / pll_m;
error = var->pixclock - pixclock;
if (error < 0)
error = -error;
if (error < best_error &&
pll_m / pll_n >
gbe_pll->fvco_min / gbe_pll->clock_rate &&
pll_m / pll_n <
gbe_pll->fvco_max / gbe_pll->clock_rate) {
best_error = error;
best_m = pll_m;
best_n = pll_n;
best_p = pll_p;
}
}
if (!best_n || !best_m)
return -EINVAL; /* Resolution to high */
pixclock = (1000000 / gbe_pll->clock_rate) *
(best_n << best_p) / best_m;
/* set video timing information */
if (timing) {
timing->width = var->xres;
timing->height = var->yres;
timing->pll_m = best_m;
timing->pll_n = best_n;
timing->pll_p = best_p;
timing->cfreq = gbe_pll->clock_rate * 1000 * timing->pll_m /
(timing->pll_n << timing->pll_p);
timing->htotal = var->left_margin + var->xres +
var->right_margin + var->hsync_len;
timing->vtotal = var->upper_margin + var->yres +
var->lower_margin + var->vsync_len;
timing->fields_sec = 1000 * timing->cfreq / timing->htotal *
1000 / timing->vtotal;
timing->hblank_start = var->xres;
timing->vblank_start = var->yres;
timing->hblank_end = timing->htotal;
timing->hsync_start = var->xres + var->right_margin + 1;
timing->hsync_end = timing->hsync_start + var->hsync_len;
timing->vblank_end = timing->vtotal;
timing->vsync_start = var->yres + var->lower_margin + 1;
timing->vsync_end = timing->vsync_start + var->vsync_len;
}
return pixclock;
}
static void gbe_set_timing_info(struct gbe_timing_info *timing)
{
int temp;
unsigned int val;
/* setup dot clock PLL */
val = 0;
SET_GBE_FIELD(DOTCLK, M, val, timing->pll_m - 1);
SET_GBE_FIELD(DOTCLK, N, val, timing->pll_n - 1);
SET_GBE_FIELD(DOTCLK, P, val, timing->pll_p);
SET_GBE_FIELD(DOTCLK, RUN, val, 0); /* do not start yet */
gbe->dotclock = val;
mdelay(10);
/* setup pixel counter */
val = 0;
SET_GBE_FIELD(VT_XYMAX, MAXX, val, timing->htotal);
SET_GBE_FIELD(VT_XYMAX, MAXY, val, timing->vtotal);
gbe->vt_xymax = val;
/* setup video timing signals */
val = 0;
SET_GBE_FIELD(VT_VSYNC, VSYNC_ON, val, timing->vsync_start);
SET_GBE_FIELD(VT_VSYNC, VSYNC_OFF, val, timing->vsync_end);
gbe->vt_vsync = val;
val = 0;
SET_GBE_FIELD(VT_HSYNC, HSYNC_ON, val, timing->hsync_start);
SET_GBE_FIELD(VT_HSYNC, HSYNC_OFF, val, timing->hsync_end);
gbe->vt_hsync = val;
val = 0;
SET_GBE_FIELD(VT_VBLANK, VBLANK_ON, val, timing->vblank_start);
SET_GBE_FIELD(VT_VBLANK, VBLANK_OFF, val, timing->vblank_end);
gbe->vt_vblank = val;
val = 0;
SET_GBE_FIELD(VT_HBLANK, HBLANK_ON, val,
timing->hblank_start - 5);
SET_GBE_FIELD(VT_HBLANK, HBLANK_OFF, val,
timing->hblank_end - 3);
gbe->vt_hblank = val;
/* setup internal timing signals */
val = 0;
SET_GBE_FIELD(VT_VCMAP, VCMAP_ON, val, timing->vblank_start);
SET_GBE_FIELD(VT_VCMAP, VCMAP_OFF, val, timing->vblank_end);
gbe->vt_vcmap = val;
val = 0;
SET_GBE_FIELD(VT_HCMAP, HCMAP_ON, val, timing->hblank_start);
SET_GBE_FIELD(VT_HCMAP, HCMAP_OFF, val, timing->hblank_end);
gbe->vt_hcmap = val;
val = 0;
temp = timing->vblank_start - timing->vblank_end - 1;
if (temp > 0)
temp = -temp;
if (flat_panel_enabled)
gbefb_setup_flatpanel(timing);
SET_GBE_FIELD(DID_START_XY, DID_STARTY, val, (u32) temp);
if (timing->hblank_end >= 20)
SET_GBE_FIELD(DID_START_XY, DID_STARTX, val,
timing->hblank_end - 20);
else
SET_GBE_FIELD(DID_START_XY, DID_STARTX, val,
timing->htotal - (20 - timing->hblank_end));
gbe->did_start_xy = val;
val = 0;
SET_GBE_FIELD(CRS_START_XY, CRS_STARTY, val, (u32) (temp + 1));
if (timing->hblank_end >= GBE_CRS_MAGIC)
SET_GBE_FIELD(CRS_START_XY, CRS_STARTX, val,
timing->hblank_end - GBE_CRS_MAGIC);
else
SET_GBE_FIELD(CRS_START_XY, CRS_STARTX, val,
timing->htotal - (GBE_CRS_MAGIC -
timing->hblank_end));
gbe->crs_start_xy = val;
val = 0;
SET_GBE_FIELD(VC_START_XY, VC_STARTY, val, (u32) temp);
SET_GBE_FIELD(VC_START_XY, VC_STARTX, val, timing->hblank_end - 4);
gbe->vc_start_xy = val;
val = 0;
temp = timing->hblank_end - GBE_PIXEN_MAGIC_ON;
if (temp < 0)
temp += timing->htotal; /* allow blank to wrap around */
SET_GBE_FIELD(VT_HPIXEN, HPIXEN_ON, val, temp);
SET_GBE_FIELD(VT_HPIXEN, HPIXEN_OFF, val,
((temp + timing->width -
GBE_PIXEN_MAGIC_OFF) % timing->htotal));
gbe->vt_hpixen = val;
val = 0;
SET_GBE_FIELD(VT_VPIXEN, VPIXEN_ON, val, timing->vblank_end);
SET_GBE_FIELD(VT_VPIXEN, VPIXEN_OFF, val, timing->vblank_start);
gbe->vt_vpixen = val;
/* turn off sync on green */
val = 0;
SET_GBE_FIELD(VT_FLAGS, SYNC_LOW, val, 1);
gbe->vt_flags = val;
}
/*
* Set the hardware according to 'par'.
*/
static int gbefb_set_par(struct fb_info *info)
{
int i;
unsigned int val;
int wholeTilesX, partTilesX, maxPixelsPerTileX;
int height_pix;
int xpmax, ypmax; /* Monitor resolution */
int bytesPerPixel; /* Bytes per pixel */
struct gbefb_par *par = (struct gbefb_par *) info->par;
compute_gbe_timing(&info->var, &par->timing);
bytesPerPixel = info->var.bits_per_pixel / 8;
info->fix.line_length = info->var.xres_virtual * bytesPerPixel;
xpmax = par->timing.width;
ypmax = par->timing.height;
/* turn off GBE */
gbe_turn_off();
/* set timing info */
gbe_set_timing_info(&par->timing);
/* initialize DIDs */
val = 0;
switch (bytesPerPixel) {
case 1:
SET_GBE_FIELD(WID, TYP, val, GBE_CMODE_I8);
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 2:
SET_GBE_FIELD(WID, TYP, val, GBE_CMODE_ARGB5);
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 4:
SET_GBE_FIELD(WID, TYP, val, GBE_CMODE_RGB8);
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
}
SET_GBE_FIELD(WID, BUF, val, GBE_BMODE_BOTH);
for (i = 0; i < 32; i++)
gbe->mode_regs[i] = val;
/* Initialize interrupts */
gbe->vt_intr01 = 0xffffffff;
gbe->vt_intr23 = 0xffffffff;
/* HACK:
The GBE hardware uses a tiled memory to screen mapping. Tiles are
blocks of 512x128, 256x128 or 128x128 pixels, respectively for 8bit,
16bit and 32 bit modes (64 kB). They cover the screen with partial
tiles on the right and/or bottom of the screen if needed.
For example in 640x480 8 bit mode the mapping is:
<-------- 640 ----->
<---- 512 ----><128|384 offscreen>
^ ^
| 128 [tile 0] [tile 1]
| v
^
4 128 [tile 2] [tile 3]
8 v
0 ^
128 [tile 4] [tile 5]
| v
| ^
v 96 [tile 6] [tile 7]
32 offscreen
Tiles have the advantage that they can be allocated individually in
memory. However, this mapping is not linear at all, which is not
really convenient. In order to support linear addressing, the GBE
DMA hardware is fooled into thinking the screen is only one tile
large and but has a greater height, so that the DMA transfer covers
the same region.
Tiles are still allocated as independent chunks of 64KB of
continuous physical memory and remapped so that the kernel sees the
framebuffer as a continuous virtual memory. The GBE tile table is
set up so that each tile references one of these 64k blocks:
GBE -> tile list framebuffer TLB <------------ CPU
[ tile 0 ] -> [ 64KB ] <- [ 16x 4KB page entries ] ^
... ... ... linear virtual FB
[ tile n ] -> [ 64KB ] <- [ 16x 4KB page entries ] v
The GBE hardware is then told that the buffer is 512*tweaked_height,
with tweaked_height = real_width*real_height/pixels_per_tile.
Thus the GBE hardware will scan the first tile, filing the first 64k
covered region of the screen, and then will proceed to the next
tile, until the whole screen is covered.
Here is what would happen at 640x480 8bit:
normal tiling linear
^ 11111111111111112222 11111111111111111111 ^
128 11111111111111112222 11111111111111111111 102 lines
11111111111111112222 11111111111111111111 v
V 11111111111111112222 11111111222222222222
33333333333333334444 22222222222222222222
33333333333333334444 22222222222222222222
< 512 > < 256 > 102*640+256 = 64k
NOTE: The only mode for which this is not working is 800x600 8bit,
as 800*600/512 = 937.5 which is not integer and thus causes
flickering.
I guess this is not so important as one can use 640x480 8bit or
800x600 16bit anyway.
*/
/* Tell gbe about the tiles table location */
/* tile_ptr -> [ tile 1 ] -> FB mem */
/* [ tile 2 ] -> FB mem */
/* ... */
val = 0;
SET_GBE_FIELD(FRM_CONTROL, FRM_TILE_PTR, val, gbe_tiles.dma >> 9);
SET_GBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, val, 0); /* do not start */
SET_GBE_FIELD(FRM_CONTROL, FRM_LINEAR, val, 0);
gbe->frm_control = val;
maxPixelsPerTileX = 512 / bytesPerPixel;
wholeTilesX = 1;
partTilesX = 0;
/* Initialize the framebuffer */
val = 0;
SET_GBE_FIELD(FRM_SIZE_TILE, FRM_WIDTH_TILE, val, wholeTilesX);
SET_GBE_FIELD(FRM_SIZE_TILE, FRM_RHS, val, partTilesX);
switch (bytesPerPixel) {
case 1:
SET_GBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, val,
GBE_FRM_DEPTH_8);
break;
case 2:
SET_GBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, val,
GBE_FRM_DEPTH_16);
break;
case 4:
SET_GBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, val,
GBE_FRM_DEPTH_32);
break;
}
gbe->frm_size_tile = val;
/* compute tweaked height */
height_pix = xpmax * ypmax / maxPixelsPerTileX;
val = 0;
SET_GBE_FIELD(FRM_SIZE_PIXEL, FB_HEIGHT_PIX, val, height_pix);
gbe->frm_size_pixel = val;
/* turn off DID and overlay DMA */
gbe->did_control = 0;
gbe->ovr_width_tile = 0;
/* Turn off mouse cursor */
gbe->crs_ctl = 0;
/* Turn on GBE */
gbe_turn_on();
/* Initialize the gamma map */
udelay(10);
for (i = 0; i < 256; i++)
gbe->gmap[i] = (i << 24) | (i << 16) | (i << 8);
/* Initialize the color map */
for (i = 0; i < 256; i++)
gbe_cmap[i] = (i << 8) | (i << 16) | (i << 24);
gbe_loadcmap();
return 0;
}
static void gbefb_encode_fix(struct fb_fix_screeninfo *fix,
struct fb_var_screeninfo *var)
{
memset(fix, 0, sizeof(struct fb_fix_screeninfo));
strcpy(fix->id, "SGI GBE");
fix->smem_start = (unsigned long) gbe_mem;
fix->smem_len = gbe_mem_size;
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
fix->accel = FB_ACCEL_NONE;
switch (var->bits_per_pixel) {
case 8:
fix->visual = FB_VISUAL_PSEUDOCOLOR;
break;
default:
fix->visual = FB_VISUAL_TRUECOLOR;
break;
}
fix->ywrapstep = 0;
fix->xpanstep = 0;
fix->ypanstep = 0;
fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
fix->mmio_start = GBE_BASE;
fix->mmio_len = sizeof(struct sgi_gbe);
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int gbefb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
int i;
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
if (info->var.bits_per_pixel <= 8) {
gbe_cmap[regno] = (red << 24) | (green << 16) | (blue << 8);
if (gbe_turned_on) {
/* wait for the color map FIFO to have a free entry */
for (i = 0; i < 1000 && gbe->cm_fifo >= 63; i++)
udelay(10);
if (i == 1000) {
printk(KERN_ERR "gbefb: cmap FIFO timeout\n");
return 1;
}
gbe->cmap[regno] = gbe_cmap[regno];
}
} else if (regno < 16) {
switch (info->var.bits_per_pixel) {
case 15:
case 16:
red >>= 3;
green >>= 3;
blue >>= 3;
pseudo_palette[regno] =
(red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
break;
case 32:
pseudo_palette[regno] =
(red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
break;
}
}
return 0;
}
/*
* Check video mode validity, eventually modify var to best match.
*/
static int gbefb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
unsigned int line_length;
struct gbe_timing_info timing;
int ret;
/* Limit bpp to 8, 16, and 32 */
if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel <= 32)
var->bits_per_pixel = 32;
else
return -EINVAL;
/* Check the mode can be mapped linearly with the tile table trick. */
/* This requires width x height x bytes/pixel be a multiple of 512 */
if ((var->xres * var->yres * var->bits_per_pixel) & 4095)
return -EINVAL;
var->grayscale = 0; /* No grayscale for now */
ret = compute_gbe_timing(var, &timing);
var->pixclock = ret;
if (ret < 0)
return -EINVAL;
/* Adjust virtual resolution, if necessary */
if (var->xres > var->xres_virtual || (!ywrap && !ypan))
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual || (!ywrap && !ypan))
var->yres_virtual = var->yres;
if (var->vmode & FB_VMODE_CONUPDATE) {
var->vmode |= FB_VMODE_YWRAP;
var->xoffset = info->var.xoffset;
var->yoffset = info->var.yoffset;
}
/* No grayscale for now */
var->grayscale = 0;
/* Memory limit */
line_length = var->xres_virtual * var->bits_per_pixel / 8;
if (line_length * var->yres_virtual > gbe_mem_size)
return -ENOMEM; /* Virtual resolution too high */
switch (var->bits_per_pixel) {
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16: /* RGB 1555 */
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 32: /* RGB 8888 */
var->red.offset = 24;
var->red.length = 8;
var->green.offset = 16;
var->green.length = 8;
var->blue.offset = 8;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 8;
break;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
var->left_margin = timing.htotal - timing.hsync_end;
var->right_margin = timing.hsync_start - timing.width;
var->upper_margin = timing.vtotal - timing.vsync_end;
var->lower_margin = timing.vsync_start - timing.height;
var->hsync_len = timing.hsync_end - timing.hsync_start;
var->vsync_len = timing.vsync_end - timing.vsync_start;
return 0;
}
static int gbefb_mmap(struct fb_info *info,
struct vm_area_struct *vma)
{
unsigned long size = vma->vm_end - vma->vm_start;
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
unsigned long addr;
unsigned long phys_addr, phys_size;
u16 *tile;
/* check range */
if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
return -EINVAL;
if (size > gbe_mem_size)
return -EINVAL;
if (offset > gbe_mem_size - size)
return -EINVAL;
/* remap using the fastest write-through mode on architecture */
/* try not polluting the cache when possible */
#ifdef CONFIG_MIPS
pgprot_val(vma->vm_page_prot) =
pgprot_fb(pgprot_val(vma->vm_page_prot));
#endif
/* VM_IO | VM_DONTEXPAND | VM_DONTDUMP are set by remap_pfn_range() */
/* look for the starting tile */
tile = &gbe_tiles.cpu[offset >> TILE_SHIFT];
addr = vma->vm_start;
offset &= TILE_MASK;
/* remap each tile separately */
do {
phys_addr = (((unsigned long) (*tile)) << TILE_SHIFT) + offset;
if ((offset + size) < TILE_SIZE)
phys_size = size;
else
phys_size = TILE_SIZE - offset;
if (remap_pfn_range(vma, addr, phys_addr >> PAGE_SHIFT,
phys_size, vma->vm_page_prot))
return -EAGAIN;
offset = 0;
size -= phys_size;
addr += phys_size;
tile++;
} while (size);
return 0;
}
static const struct fb_ops gbefb_ops = {
.owner = THIS_MODULE,
.fb_check_var = gbefb_check_var,
.fb_set_par = gbefb_set_par,
.fb_setcolreg = gbefb_setcolreg,
.fb_mmap = gbefb_mmap,
.fb_blank = gbefb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
/*
* sysfs
*/
static ssize_t gbefb_show_memsize(struct device *dev, struct device_attribute *attr, char *buf)
{
return sysfs_emit(buf, "%u\n", gbe_mem_size);
}
static DEVICE_ATTR(size, S_IRUGO, gbefb_show_memsize, NULL);
static ssize_t gbefb_show_rev(struct device *device, struct device_attribute *attr, char *buf)
{
return sysfs_emit(buf, "%d\n", gbe_revision);
}
static DEVICE_ATTR(revision, S_IRUGO, gbefb_show_rev, NULL);
static struct attribute *gbefb_attrs[] = {
&dev_attr_size.attr,
&dev_attr_revision.attr,
NULL,
};
ATTRIBUTE_GROUPS(gbefb);
/*
* Initialization
*/
static int gbefb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "monitor:", 8)) {
if (!strncmp(this_opt + 8, "crt", 3)) {
flat_panel_enabled = 0;
default_var = &default_var_CRT;
default_mode = &default_mode_CRT;
} else if (!strncmp(this_opt + 8, "1600sw", 6) ||
!strncmp(this_opt + 8, "lcd", 3)) {
flat_panel_enabled = 1;
default_var = &default_var_LCD;
default_mode = &default_mode_LCD;
}
} else if (!strncmp(this_opt, "mem:", 4)) {
gbe_mem_size = memparse(this_opt + 4, &this_opt);
if (gbe_mem_size > CONFIG_FB_GBE_MEM * 1024 * 1024)
gbe_mem_size = CONFIG_FB_GBE_MEM * 1024 * 1024;
if (gbe_mem_size < TILE_SIZE)
gbe_mem_size = TILE_SIZE;
} else
mode_option = this_opt;
}
return 0;
}
static int gbefb_probe(struct platform_device *p_dev)
{
int i, ret = 0;
struct fb_info *info;
struct gbefb_par *par;
#ifndef MODULE
char *options = NULL;
#endif
info = framebuffer_alloc(sizeof(struct gbefb_par), &p_dev->dev);
if (!info)
return -ENOMEM;
#ifndef MODULE
if (fb_get_options("gbefb", &options)) {
ret = -ENODEV;
goto out_release_framebuffer;
}
gbefb_setup(options);
#endif
if (!request_mem_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) {
printk(KERN_ERR "gbefb: couldn't reserve mmio region\n");
ret = -EBUSY;
goto out_release_framebuffer;
}
gbe = (struct sgi_gbe *) devm_ioremap(&p_dev->dev, GBE_BASE,
sizeof(struct sgi_gbe));
if (!gbe) {
printk(KERN_ERR "gbefb: couldn't map mmio region\n");
ret = -ENXIO;
goto out_release_mem_region;
}
gbe_revision = gbe->ctrlstat & 15;
gbe_tiles.cpu = dmam_alloc_coherent(&p_dev->dev,
GBE_TLB_SIZE * sizeof(uint16_t),
&gbe_tiles.dma, GFP_KERNEL);
if (!gbe_tiles.cpu) {
printk(KERN_ERR "gbefb: couldn't allocate tiles table\n");
ret = -ENOMEM;
goto out_release_mem_region;
}
if (gbe_mem_phys) {
/* memory was allocated at boot time */
gbe_mem = devm_ioremap_wc(&p_dev->dev, gbe_mem_phys,
gbe_mem_size);
if (!gbe_mem) {
printk(KERN_ERR "gbefb: couldn't map framebuffer\n");
ret = -ENOMEM;
goto out_release_mem_region;
}
gbe_dma_addr = 0;
} else {
/* try to allocate memory with the classical allocator
* this has high chance to fail on low memory machines */
gbe_mem = dmam_alloc_attrs(&p_dev->dev, gbe_mem_size,
&gbe_dma_addr, GFP_KERNEL,
DMA_ATTR_WRITE_COMBINE);
if (!gbe_mem) {
printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n");
ret = -ENOMEM;
goto out_release_mem_region;
}
gbe_mem_phys = (unsigned long) gbe_dma_addr;
}
par = info->par;
par->wc_cookie = arch_phys_wc_add(gbe_mem_phys, gbe_mem_size);
/* map framebuffer memory into tiles table */
for (i = 0; i < (gbe_mem_size >> TILE_SHIFT); i++)
gbe_tiles.cpu[i] = (gbe_mem_phys >> TILE_SHIFT) + i;
info->fbops = &gbefb_ops;
info->pseudo_palette = pseudo_palette;
info->screen_base = gbe_mem;
fb_alloc_cmap(&info->cmap, 256, 0);
/* reset GBE */
gbe_reset();
/* turn on default video mode */
if (fb_find_mode(&par->var, info, mode_option, NULL, 0,
default_mode, 8) == 0)
par->var = *default_var;
info->var = par->var;
gbefb_check_var(&par->var, info);
gbefb_encode_fix(&info->fix, &info->var);
if (register_framebuffer(info) < 0) {
printk(KERN_ERR "gbefb: couldn't register framebuffer\n");
ret = -ENXIO;
goto out_gbe_unmap;
}
platform_set_drvdata(p_dev, info);
fb_info(info, "%s rev %d @ 0x%08x using %dkB memory\n",
info->fix.id, gbe_revision, (unsigned)GBE_BASE,
gbe_mem_size >> 10);
return 0;
out_gbe_unmap:
arch_phys_wc_del(par->wc_cookie);
out_release_mem_region:
release_mem_region(GBE_BASE, sizeof(struct sgi_gbe));
out_release_framebuffer:
framebuffer_release(info);
return ret;
}
static void gbefb_remove(struct platform_device* p_dev)
{
struct fb_info *info = platform_get_drvdata(p_dev);
struct gbefb_par *par = info->par;
unregister_framebuffer(info);
gbe_turn_off();
arch_phys_wc_del(par->wc_cookie);
release_mem_region(GBE_BASE, sizeof(struct sgi_gbe));
framebuffer_release(info);
}
static struct platform_driver gbefb_driver = {
.probe = gbefb_probe,
.remove_new = gbefb_remove,
.driver = {
.name = "gbefb",
.dev_groups = gbefb_groups,
},
};
static struct platform_device *gbefb_device;
static int __init gbefb_init(void)
{
int ret = platform_driver_register(&gbefb_driver);
if (IS_ENABLED(CONFIG_SGI_IP32) && !ret) {
gbefb_device = platform_device_alloc("gbefb", 0);
if (gbefb_device) {
ret = platform_device_add(gbefb_device);
} else {
ret = -ENOMEM;
}
if (ret) {
platform_device_put(gbefb_device);
platform_driver_unregister(&gbefb_driver);
}
}
return ret;
}
static void __exit gbefb_exit(void)
{
platform_device_unregister(gbefb_device);
platform_driver_unregister(&gbefb_driver);
}
module_init(gbefb_init);
module_exit(gbefb_exit);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/gbefb.c |
/*
* linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
*
* Copyright (C) 2001 Romain Dolbeau <[email protected]>.
*
* Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <[email protected]>
* based on pm2fb.c
*
* Based on code written by:
* Sven Luther, <[email protected]>
* Alan Hourihane, <[email protected]>
* Russell King, <[email protected]>
* Based on linux/drivers/video/skeletonfb.c:
* Copyright (C) 1997 Geert Uytterhoeven
* Based on linux/driver/video/pm2fb.c:
* Copyright (C) 1998-1999 Ilario Nardinocchi ([email protected])
* Copyright (C) 1999 Jakub Jelinek ([email protected])
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <video/pm3fb.h>
#if !defined(CONFIG_PCI)
#error "Only generic PCI cards supported."
#endif
#undef PM3FB_MASTER_DEBUG
#ifdef PM3FB_MASTER_DEBUG
#define DPRINTK(a, b...) \
printk(KERN_DEBUG "pm3fb: %s: " a, __func__ , ## b)
#else
#define DPRINTK(a, b...) no_printk(a, ##b)
#endif
#define PM3_PIXMAP_SIZE (2048 * 4)
/*
* Driver data
*/
static int hwcursor = 1;
static char *mode_option;
static bool noaccel;
static bool nomtrr;
/*
* This structure defines the hardware state of the graphics card. Normally
* you place this in a header file in linux/include/video. This file usually
* also includes register information. That allows other driver subsystems
* and userland applications the ability to use the same header file to
* avoid duplicate work and easy porting of software.
*/
struct pm3_par {
unsigned char __iomem *v_regs;/* virtual address of p_regs */
u32 video; /* video flags before blanking */
u32 base; /* screen base in 128 bits unit */
u32 palette[16];
int wc_cookie;
};
/*
* Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
* if we don't use modedb. If we do use modedb see pm3fb_init how to use it
* to get a fb_var_screeninfo. Otherwise define a default var as well.
*/
static struct fb_fix_screeninfo pm3fb_fix = {
.id = "Permedia3",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 1,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_3DLABS_PERMEDIA3,
};
/*
* Utility functions
*/
static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
{
return fb_readl(par->v_regs + off);
}
static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
{
fb_writel(v, par->v_regs + off);
}
static inline void PM3_WAIT(struct pm3_par *par, u32 n)
{
while (PM3_READ_REG(par, PM3InFIFOSpace) < n)
cpu_relax();
}
static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
{
PM3_WAIT(par, 3);
PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
wmb();
PM3_WRITE_REG(par, PM3RD_IndexedData, v);
wmb();
}
static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
unsigned char r, unsigned char g, unsigned char b)
{
PM3_WAIT(par, 4);
PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
wmb();
PM3_WRITE_REG(par, PM3RD_PaletteData, r);
wmb();
PM3_WRITE_REG(par, PM3RD_PaletteData, g);
wmb();
PM3_WRITE_REG(par, PM3RD_PaletteData, b);
wmb();
}
static void pm3fb_clear_colormap(struct pm3_par *par,
unsigned char r, unsigned char g, unsigned char b)
{
int i;
for (i = 0; i < 256 ; i++)
pm3fb_set_color(par, i, r, g, b);
}
/* Calculating various clock parameters */
static void pm3fb_calculate_clock(unsigned long reqclock,
unsigned char *prescale,
unsigned char *feedback,
unsigned char *postscale)
{
int f, pre, post;
unsigned long freq;
long freqerr = 1000;
long currerr;
for (f = 1; f < 256; f++) {
for (pre = 1; pre < 256; pre++) {
for (post = 0; post < 5; post++) {
freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
currerr = (reqclock > freq)
? reqclock - freq
: freq - reqclock;
if (currerr < freqerr) {
freqerr = currerr;
*feedback = f;
*prescale = pre;
*postscale = post;
}
}
}
}
}
static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
{
if (var->bits_per_pixel == 16)
return var->red.length + var->green.length
+ var->blue.length;
return var->bits_per_pixel;
}
static inline int pm3fb_shift_bpp(unsigned bpp, int v)
{
switch (bpp) {
case 8:
return (v >> 4);
case 16:
return (v >> 3);
case 32:
return (v >> 2);
}
DPRINTK("Unsupported depth %u\n", bpp);
return 0;
}
/* acceleration */
static int pm3fb_sync(struct fb_info *info)
{
struct pm3_par *par = info->par;
PM3_WAIT(par, 2);
PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
PM3_WRITE_REG(par, PM3Sync, 0);
mb();
do {
while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0)
cpu_relax();
} while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
return 0;
}
static void pm3fb_init_engine(struct fb_info *info)
{
struct pm3_par *par = info->par;
const u32 width = (info->var.xres_virtual + 7) & ~7;
PM3_WAIT(par, 50);
PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
PM3_WRITE_REG(par, PM3GIDMode, 0x0);
PM3_WRITE_REG(par, PM3DepthMode, 0x0);
PM3_WRITE_REG(par, PM3StencilMode, 0x0);
PM3_WRITE_REG(par, PM3StencilData, 0x0);
PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
PM3_WRITE_REG(par, PM3LUTMode, 0x0);
PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
PM3_WRITE_REG(par, PM3FogMode, 0x0);
PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
PM3_WRITE_REG(par, PM3YUVMode, 0x0);
PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
PM3_WRITE_REG(par, PM3DitherMode, 0x0);
PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
PM3_WRITE_REG(par, PM3RouterMode, 0x0);
PM3_WRITE_REG(par, PM3Window, 0x0);
PM3_WRITE_REG(par, PM3Config2D, 0x0);
PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
PM3_WRITE_REG(par, PM3XBias, 0x0);
PM3_WRITE_REG(par, PM3YBias, 0x0);
PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
PM3_WRITE_REG(par, PM3FBDestReadEnables,
PM3FBDestReadEnables_E(0xff) |
PM3FBDestReadEnables_R(0xff) |
PM3FBDestReadEnables_ReferenceAlpha(0xff));
PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
PM3FBDestReadBufferWidth_Width(width));
PM3_WRITE_REG(par, PM3FBDestReadMode,
PM3FBDestReadMode_ReadEnable |
PM3FBDestReadMode_Enable0);
PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
PM3FBSourceReadBufferWidth_Width(width));
PM3_WRITE_REG(par, PM3FBSourceReadMode,
PM3FBSourceReadMode_Blocking |
PM3FBSourceReadMode_ReadEnable);
PM3_WAIT(par, 2);
{
/* invert bits in bitmask */
unsigned long rm = 1 | (3 << 7);
switch (info->var.bits_per_pixel) {
case 8:
PM3_WRITE_REG(par, PM3PixelSize,
PM3PixelSize_GLOBAL_8BIT);
#ifdef __BIG_ENDIAN
rm |= 3 << 15;
#endif
break;
case 16:
PM3_WRITE_REG(par, PM3PixelSize,
PM3PixelSize_GLOBAL_16BIT);
#ifdef __BIG_ENDIAN
rm |= 2 << 15;
#endif
break;
case 32:
PM3_WRITE_REG(par, PM3PixelSize,
PM3PixelSize_GLOBAL_32BIT);
break;
default:
DPRINTK("Unsupported depth %d\n",
info->var.bits_per_pixel);
break;
}
PM3_WRITE_REG(par, PM3RasterizerMode, rm);
}
PM3_WAIT(par, 20);
PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
PM3_WRITE_REG(par, PM3FBWriteMode,
PM3FBWriteMode_WriteEnable |
PM3FBWriteMode_OpaqueSpan |
PM3FBWriteMode_Enable0);
PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
PM3FBWriteBufferWidth_Width(width));
PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
{
/* size in lines of FB */
unsigned long sofb = info->screen_size /
info->fix.line_length;
if (sofb > 4095)
PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
else
PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
switch (info->var.bits_per_pixel) {
case 8:
PM3_WRITE_REG(par, PM3DitherMode,
(1 << 10) | (2 << 3));
break;
case 16:
PM3_WRITE_REG(par, PM3DitherMode,
(1 << 10) | (1 << 3));
break;
case 32:
PM3_WRITE_REG(par, PM3DitherMode,
(1 << 10) | (0 << 3));
break;
default:
DPRINTK("Unsupported depth %d\n",
info->var.bits_per_pixel);
break;
}
}
PM3_WRITE_REG(par, PM3dXDom, 0x0);
PM3_WRITE_REG(par, PM3dXSub, 0x0);
PM3_WRITE_REG(par, PM3dY, 1 << 16);
PM3_WRITE_REG(par, PM3StartXDom, 0x0);
PM3_WRITE_REG(par, PM3StartXSub, 0x0);
PM3_WRITE_REG(par, PM3StartY, 0x0);
PM3_WRITE_REG(par, PM3Count, 0x0);
/* Disable LocalBuffer. better safe than sorry */
PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
pm3fb_sync(info);
}
static void pm3fb_fillrect(struct fb_info *info,
const struct fb_fillrect *region)
{
struct pm3_par *par = info->par;
struct fb_fillrect modded;
int vxres, vyres;
int rop;
u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
((u32 *)info->pseudo_palette)[region->color] : region->color;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_fillrect(info, region);
return;
}
if (region->rop == ROP_COPY )
rop = PM3Config2D_ForegroundROP(0x3); /* GXcopy */
else
rop = PM3Config2D_ForegroundROP(0x6) | /* GXxor */
PM3Config2D_FBDestReadEnable;
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
memcpy(&modded, region, sizeof(struct fb_fillrect));
if (!modded.width || !modded.height ||
modded.dx >= vxres || modded.dy >= vyres)
return;
if (modded.dx + modded.width > vxres)
modded.width = vxres - modded.dx;
if (modded.dy + modded.height > vyres)
modded.height = vyres - modded.dy;
if (info->var.bits_per_pixel == 8)
color |= color << 8;
if (info->var.bits_per_pixel <= 16)
color |= color << 16;
PM3_WAIT(par, 4);
/* ROP Ox3 is GXcopy */
PM3_WRITE_REG(par, PM3Config2D,
PM3Config2D_UseConstantSource |
PM3Config2D_ForegroundROPEnable |
rop |
PM3Config2D_FBWriteEnable);
PM3_WRITE_REG(par, PM3ForegroundColor, color);
PM3_WRITE_REG(par, PM3RectanglePosition,
PM3RectanglePosition_XOffset(modded.dx) |
PM3RectanglePosition_YOffset(modded.dy));
PM3_WRITE_REG(par, PM3Render2D,
PM3Render2D_XPositive |
PM3Render2D_YPositive |
PM3Render2D_Operation_Normal |
PM3Render2D_SpanOperation |
PM3Render2D_Width(modded.width) |
PM3Render2D_Height(modded.height));
}
static void pm3fb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct pm3_par *par = info->par;
struct fb_copyarea modded;
u32 vxres, vyres;
int x_align, o_x, o_y;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_copyarea(info, area);
return;
}
memcpy(&modded, area, sizeof(struct fb_copyarea));
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
if (!modded.width || !modded.height ||
modded.sx >= vxres || modded.sy >= vyres ||
modded.dx >= vxres || modded.dy >= vyres)
return;
if (modded.sx + modded.width > vxres)
modded.width = vxres - modded.sx;
if (modded.dx + modded.width > vxres)
modded.width = vxres - modded.dx;
if (modded.sy + modded.height > vyres)
modded.height = vyres - modded.sy;
if (modded.dy + modded.height > vyres)
modded.height = vyres - modded.dy;
o_x = modded.sx - modded.dx; /*(sx > dx ) ? (sx - dx) : (dx - sx); */
o_y = modded.sy - modded.dy; /*(sy > dy ) ? (sy - dy) : (dy - sy); */
x_align = (modded.sx & 0x1f);
PM3_WAIT(par, 6);
PM3_WRITE_REG(par, PM3Config2D,
PM3Config2D_UserScissorEnable |
PM3Config2D_ForegroundROPEnable |
PM3Config2D_Blocking |
PM3Config2D_ForegroundROP(0x3) | /* Ox3 is GXcopy */
PM3Config2D_FBWriteEnable);
PM3_WRITE_REG(par, PM3ScissorMinXY,
((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
PM3_WRITE_REG(par, PM3ScissorMaxXY,
(((modded.dy + modded.height) & 0x0fff) << 16) |
((modded.dx + modded.width) & 0x0fff));
PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
PM3FBSourceReadBufferOffset_XOffset(o_x) |
PM3FBSourceReadBufferOffset_YOffset(o_y));
PM3_WRITE_REG(par, PM3RectanglePosition,
PM3RectanglePosition_XOffset(modded.dx - x_align) |
PM3RectanglePosition_YOffset(modded.dy));
PM3_WRITE_REG(par, PM3Render2D,
((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
PM3Render2D_Operation_Normal |
PM3Render2D_SpanOperation |
PM3Render2D_FBSourceReadEnable |
PM3Render2D_Width(modded.width + x_align) |
PM3Render2D_Height(modded.height));
}
static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct pm3_par *par = info->par;
u32 height = image->height;
u32 fgx, bgx;
const u32 *src = (const u32 *)image->data;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_imageblit(info, image);
return;
}
switch (info->fix.visual) {
case FB_VISUAL_PSEUDOCOLOR:
fgx = image->fg_color;
bgx = image->bg_color;
break;
case FB_VISUAL_TRUECOLOR:
default:
fgx = par->palette[image->fg_color];
bgx = par->palette[image->bg_color];
break;
}
if (image->depth != 1) {
cfb_imageblit(info, image);
return;
}
if (info->var.bits_per_pixel == 8) {
fgx |= fgx << 8;
bgx |= bgx << 8;
}
if (info->var.bits_per_pixel <= 16) {
fgx |= fgx << 16;
bgx |= bgx << 16;
}
PM3_WAIT(par, 7);
PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
/* ROP Ox3 is GXcopy */
PM3_WRITE_REG(par, PM3Config2D,
PM3Config2D_UserScissorEnable |
PM3Config2D_UseConstantSource |
PM3Config2D_ForegroundROPEnable |
PM3Config2D_ForegroundROP(0x3) |
PM3Config2D_OpaqueSpan |
PM3Config2D_FBWriteEnable);
PM3_WRITE_REG(par, PM3ScissorMinXY,
((image->dy & 0x0fff) << 16) | (image->dx & 0x0fff));
PM3_WRITE_REG(par, PM3ScissorMaxXY,
(((image->dy + image->height) & 0x0fff) << 16) |
((image->dx + image->width) & 0x0fff));
PM3_WRITE_REG(par, PM3RectanglePosition,
PM3RectanglePosition_XOffset(image->dx) |
PM3RectanglePosition_YOffset(image->dy));
PM3_WRITE_REG(par, PM3Render2D,
PM3Render2D_XPositive |
PM3Render2D_YPositive |
PM3Render2D_Operation_SyncOnBitMask |
PM3Render2D_SpanOperation |
PM3Render2D_Width(image->width) |
PM3Render2D_Height(image->height));
while (height--) {
int width = ((image->width + 7) >> 3)
+ info->pixmap.scan_align - 1;
width >>= 2;
while (width >= PM3_FIFO_SIZE) {
int i = PM3_FIFO_SIZE - 1;
PM3_WAIT(par, PM3_FIFO_SIZE);
while (i--) {
PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
src++;
}
width -= PM3_FIFO_SIZE - 1;
}
PM3_WAIT(par, width + 1);
while (width--) {
PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
src++;
}
}
}
/* end of acceleration functions */
/*
* Hardware Cursor support.
*/
static const u8 cursor_bits_lookup[16] = {
0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
};
static int pm3fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct pm3_par *par = info->par;
u8 mode;
if (!hwcursor)
return -EINVAL; /* just to force soft_cursor() call */
/* Too large of a cursor or wrong bpp :-( */
if (cursor->image.width > 64 ||
cursor->image.height > 64 ||
cursor->image.depth > 1)
return -EINVAL;
mode = PM3RD_CursorMode_TYPE_X;
if (cursor->enable)
mode |= PM3RD_CursorMode_CURSOR_ENABLE;
PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, mode);
/*
* If the cursor is not be changed this means either we want the
* current cursor state (if enable is set) or we want to query what
* we can do with the cursor (if enable is not set)
*/
if (!cursor->set)
return 0;
if (cursor->set & FB_CUR_SETPOS) {
int x = cursor->image.dx - info->var.xoffset;
int y = cursor->image.dy - info->var.yoffset;
PM3_WRITE_DAC_REG(par, PM3RD_CursorXLow, x & 0xff);
PM3_WRITE_DAC_REG(par, PM3RD_CursorXHigh, (x >> 8) & 0xf);
PM3_WRITE_DAC_REG(par, PM3RD_CursorYLow, y & 0xff);
PM3_WRITE_DAC_REG(par, PM3RD_CursorYHigh, (y >> 8) & 0xf);
}
if (cursor->set & FB_CUR_SETHOT) {
PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotX,
cursor->hot.x & 0x3f);
PM3_WRITE_DAC_REG(par, PM3RD_CursorHotSpotY,
cursor->hot.y & 0x3f);
}
if (cursor->set & FB_CUR_SETCMAP) {
u32 fg_idx = cursor->image.fg_color;
u32 bg_idx = cursor->image.bg_color;
struct fb_cmap cmap = info->cmap;
/* the X11 driver says one should use these color registers */
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(39),
cmap.red[fg_idx] >> 8 );
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(40),
cmap.green[fg_idx] >> 8 );
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(41),
cmap.blue[fg_idx] >> 8 );
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(42),
cmap.red[bg_idx] >> 8 );
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(43),
cmap.green[bg_idx] >> 8 );
PM3_WRITE_DAC_REG(par, PM3RD_CursorPalette(44),
cmap.blue[bg_idx] >> 8 );
}
if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
u8 *bitmap = (u8 *)cursor->image.data;
u8 *mask = (u8 *)cursor->mask;
int i;
int pos = PM3RD_CursorPattern(0);
for (i = 0; i < cursor->image.height; i++) {
int j = (cursor->image.width + 7) >> 3;
int k = 8 - j;
for (; j > 0; j--) {
u8 data = *bitmap ^ *mask;
if (cursor->rop == ROP_COPY)
data = *mask & *bitmap;
/* Upper 4 bits of bitmap data */
PM3_WRITE_DAC_REG(par, pos++,
cursor_bits_lookup[data >> 4] |
(cursor_bits_lookup[*mask >> 4] << 1));
/* Lower 4 bits of bitmap */
PM3_WRITE_DAC_REG(par, pos++,
cursor_bits_lookup[data & 0xf] |
(cursor_bits_lookup[*mask & 0xf] << 1));
bitmap++;
mask++;
}
for (; k > 0; k--) {
PM3_WRITE_DAC_REG(par, pos++, 0);
PM3_WRITE_DAC_REG(par, pos++, 0);
}
}
while (pos < PM3RD_CursorPattern(1024))
PM3_WRITE_DAC_REG(par, pos++, 0);
}
return 0;
}
/* write the mode to registers */
static void pm3fb_write_mode(struct fb_info *info)
{
struct pm3_par *par = info->par;
char tempsync = 0x00;
char tempmisc = 0x00;
const u32 hsstart = info->var.right_margin;
const u32 hsend = hsstart + info->var.hsync_len;
const u32 hbend = hsend + info->var.left_margin;
const u32 xres = (info->var.xres + 31) & ~31;
const u32 htotal = xres + hbend;
const u32 vsstart = info->var.lower_margin;
const u32 vsend = vsstart + info->var.vsync_len;
const u32 vbend = vsend + info->var.upper_margin;
const u32 vtotal = info->var.yres + vbend;
const u32 width = (info->var.xres_virtual + 7) & ~7;
const unsigned bpp = info->var.bits_per_pixel;
PM3_WAIT(par, 20);
PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
PM3_WRITE_REG(par, PM3HTotal,
pm3fb_shift_bpp(bpp, htotal - 1));
PM3_WRITE_REG(par, PM3HsEnd,
pm3fb_shift_bpp(bpp, hsend));
PM3_WRITE_REG(par, PM3HsStart,
pm3fb_shift_bpp(bpp, hsstart));
PM3_WRITE_REG(par, PM3HbEnd,
pm3fb_shift_bpp(bpp, hbend));
PM3_WRITE_REG(par, PM3HgEnd,
pm3fb_shift_bpp(bpp, hbend));
PM3_WRITE_REG(par, PM3ScreenStride,
pm3fb_shift_bpp(bpp, width));
PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
PM3_WRITE_REG(par, PM3VbEnd, vbend);
switch (bpp) {
case 8:
PM3_WRITE_REG(par, PM3ByAperture1Mode,
PM3ByApertureMode_PIXELSIZE_8BIT);
PM3_WRITE_REG(par, PM3ByAperture2Mode,
PM3ByApertureMode_PIXELSIZE_8BIT);
break;
case 16:
#ifndef __BIG_ENDIAN
PM3_WRITE_REG(par, PM3ByAperture1Mode,
PM3ByApertureMode_PIXELSIZE_16BIT);
PM3_WRITE_REG(par, PM3ByAperture2Mode,
PM3ByApertureMode_PIXELSIZE_16BIT);
#else
PM3_WRITE_REG(par, PM3ByAperture1Mode,
PM3ByApertureMode_PIXELSIZE_16BIT |
PM3ByApertureMode_BYTESWAP_BADC);
PM3_WRITE_REG(par, PM3ByAperture2Mode,
PM3ByApertureMode_PIXELSIZE_16BIT |
PM3ByApertureMode_BYTESWAP_BADC);
#endif /* ! __BIG_ENDIAN */
break;
case 32:
#ifndef __BIG_ENDIAN
PM3_WRITE_REG(par, PM3ByAperture1Mode,
PM3ByApertureMode_PIXELSIZE_32BIT);
PM3_WRITE_REG(par, PM3ByAperture2Mode,
PM3ByApertureMode_PIXELSIZE_32BIT);
#else
PM3_WRITE_REG(par, PM3ByAperture1Mode,
PM3ByApertureMode_PIXELSIZE_32BIT |
PM3ByApertureMode_BYTESWAP_DCBA);
PM3_WRITE_REG(par, PM3ByAperture2Mode,
PM3ByApertureMode_PIXELSIZE_32BIT |
PM3ByApertureMode_BYTESWAP_DCBA);
#endif /* ! __BIG_ENDIAN */
break;
default:
DPRINTK("Unsupported depth %d\n", bpp);
break;
}
/*
* Oxygen VX1 - it appears that setting PM3VideoControl and
* then PM3RD_SyncControl to the same SYNC settings undoes
* any net change - they seem to xor together. Only set the
* sync options in PM3RD_SyncControl. --rmk
*/
{
unsigned int video = par->video;
video &= ~(PM3VideoControl_HSYNC_MASK |
PM3VideoControl_VSYNC_MASK);
video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
PM3VideoControl_VSYNC_ACTIVE_HIGH;
PM3_WRITE_REG(par, PM3VideoControl, video);
}
PM3_WRITE_REG(par, PM3VClkCtl,
(PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
PM3_WRITE_REG(par, PM3ScreenBase, par->base);
PM3_WRITE_REG(par, PM3ChipConfig,
(PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
wmb();
{
unsigned char m; /* ClkPreScale */
unsigned char n; /* ClkFeedBackScale */
unsigned char p; /* ClkPostScale */
unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
(void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
pixclock, (int) m, (int) n, (int) p);
PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
}
/*
PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
*/
/*
PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
*/
if ((par->video & PM3VideoControl_HSYNC_MASK) ==
PM3VideoControl_HSYNC_ACTIVE_HIGH)
tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
if ((par->video & PM3VideoControl_VSYNC_MASK) ==
PM3VideoControl_VSYNC_ACTIVE_HIGH)
tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
switch (pm3fb_depth(&info->var)) {
case 8:
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
PM3RD_PixelSize_8_BIT_PIXELS);
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
PM3RD_ColorFormat_CI8_COLOR |
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
break;
case 12:
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
PM3RD_PixelSize_16_BIT_PIXELS);
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
PM3RD_ColorFormat_4444_COLOR |
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
break;
case 15:
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
PM3RD_PixelSize_16_BIT_PIXELS);
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
PM3RD_ColorFormat_5551_FRONT_COLOR |
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
break;
case 16:
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
PM3RD_PixelSize_16_BIT_PIXELS);
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
PM3RD_ColorFormat_565_FRONT_COLOR |
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
break;
case 32:
PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
PM3RD_PixelSize_32_BIT_PIXELS);
PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
PM3RD_ColorFormat_8888_COLOR |
PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
break;
}
PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
}
/*
* hardware independent functions
*/
static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
u32 lpitch;
unsigned bpp = var->red.length + var->green.length
+ var->blue.length + var->transp.length;
if (bpp != var->bits_per_pixel) {
/* set predefined mode for bits_per_pixel settings */
switch (var->bits_per_pixel) {
case 8:
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->red.offset = 0;
var->green.offset = 0;
var->blue.offset = 0;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16:
var->red.length = 5;
var->blue.length = 5;
var->green.length = 6;
var->transp.length = 0;
break;
case 32:
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.length = 8;
break;
default:
DPRINTK("depth not supported: %u\n",
var->bits_per_pixel);
return -EINVAL;
}
}
/* it is assumed BGRA order */
if (var->bits_per_pixel > 8 ) {
var->blue.offset = 0;
var->green.offset = var->blue.length;
var->red.offset = var->green.offset + var->green.length;
var->transp.offset = var->red.offset + var->red.length;
}
var->height = -1;
var->width = -1;
if (var->xres != var->xres_virtual) {
DPRINTK("virtual x resolution != "
"physical x resolution not supported\n");
return -EINVAL;
}
if (var->yres > var->yres_virtual) {
DPRINTK("virtual y resolution < "
"physical y resolution not possible\n");
return -EINVAL;
}
if (var->xoffset) {
DPRINTK("xoffset not supported\n");
return -EINVAL;
}
if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
DPRINTK("interlace not supported\n");
return -EINVAL;
}
var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
if (var->xres < 200 || var->xres > 2048) {
DPRINTK("width not supported: %u\n", var->xres);
return -EINVAL;
}
if (var->yres < 200 || var->yres > 4095) {
DPRINTK("height not supported: %u\n", var->yres);
return -EINVAL;
}
if (lpitch * var->yres_virtual > info->fix.smem_len) {
DPRINTK("no memory for screen (%ux%ux%u)\n",
var->xres, var->yres_virtual, var->bits_per_pixel);
return -EINVAL;
}
if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
DPRINTK("pixclock too high (%ldKHz)\n",
PICOS2KHZ(var->pixclock));
return -EINVAL;
}
var->accel_flags = 0; /* Can't mmap if this is on */
DPRINTK("Checking graphics mode at %dx%d depth %d\n",
var->xres, var->yres, var->bits_per_pixel);
return 0;
}
static int pm3fb_set_par(struct fb_info *info)
{
struct pm3_par *par = info->par;
const u32 xres = (info->var.xres + 31) & ~31;
const unsigned bpp = info->var.bits_per_pixel;
par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres)
+ info->var.xoffset);
par->video = 0;
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
else
par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
else
par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
par->video |= PM3VideoControl_LINE_DOUBLE_ON;
if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
par->video |= PM3VideoControl_ENABLE;
else
DPRINTK("PM3Video disabled\n");
switch (bpp) {
case 8:
par->video |= PM3VideoControl_PIXELSIZE_8BIT;
break;
case 16:
par->video |= PM3VideoControl_PIXELSIZE_16BIT;
break;
case 32:
par->video |= PM3VideoControl_PIXELSIZE_32BIT;
break;
default:
DPRINTK("Unsupported depth\n");
break;
}
info->fix.visual =
(bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
info->fix.line_length = ((info->var.xres_virtual + 7) >> 3) * bpp;
/* pm3fb_clear_memory(info, 0);*/
pm3fb_clear_colormap(par, 0, 0, 0);
PM3_WRITE_DAC_REG(par, PM3RD_CursorMode, 0);
pm3fb_init_engine(info);
pm3fb_write_mode(info);
return 0;
}
static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct pm3_par *par = info->par;
if (regno >= 256) /* no. of hw registers */
return -EINVAL;
/* grayscale works only partially under directcolor */
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
if (info->var.grayscale)
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
/* Directcolor:
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* {hardwarespecific} contains width of DAC
* pseudo_palette[X] is programmed to (X << red.offset) |
* (X << green.offset) |
* (X << blue.offset)
* RAMDAC[X] is programmed to (red, green, blue)
* color depth = SUM(var->{color}.length)
*
* Pseudocolor:
* var->{color}.offset is 0
* var->{color}.length contains width of DAC or the number
* of unique colors available (color depth)
* pseudo_palette is not used
* RAMDAC[X] is programmed to (red, green, blue)
* color depth = var->{color}.length
*/
/*
* This is the point where the color is converted to something that
* is acceptable by the hardware.
*/
#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
transp = CNVT_TOHW(transp, info->var.transp.length);
#undef CNVT_TOHW
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
u32 v;
if (regno >= 16)
return -EINVAL;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
switch (info->var.bits_per_pixel) {
case 8:
break;
case 16:
case 32:
((u32 *)(info->pseudo_palette))[regno] = v;
break;
}
return 0;
} else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
pm3fb_set_color(par, regno, red, green, blue);
return 0;
}
static int pm3fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct pm3_par *par = info->par;
const u32 xres = (info->var.xres + 31) & ~31;
par->base = pm3fb_shift_bpp(info->var.bits_per_pixel,
(var->yoffset * xres)
+ var->xoffset);
PM3_WAIT(par, 1);
PM3_WRITE_REG(par, PM3ScreenBase, par->base);
return 0;
}
static int pm3fb_blank(int blank_mode, struct fb_info *info)
{
struct pm3_par *par = info->par;
u32 video = par->video;
/*
* Oxygen VX1 - it appears that setting PM3VideoControl and
* then PM3RD_SyncControl to the same SYNC settings undoes
* any net change - they seem to xor together. Only set the
* sync options in PM3RD_SyncControl. --rmk
*/
video &= ~(PM3VideoControl_HSYNC_MASK |
PM3VideoControl_VSYNC_MASK);
video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
PM3VideoControl_VSYNC_ACTIVE_HIGH;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
video |= PM3VideoControl_ENABLE;
break;
case FB_BLANK_NORMAL:
video &= ~PM3VideoControl_ENABLE;
break;
case FB_BLANK_HSYNC_SUSPEND:
video &= ~(PM3VideoControl_HSYNC_MASK |
PM3VideoControl_BLANK_ACTIVE_LOW);
break;
case FB_BLANK_VSYNC_SUSPEND:
video &= ~(PM3VideoControl_VSYNC_MASK |
PM3VideoControl_BLANK_ACTIVE_LOW);
break;
case FB_BLANK_POWERDOWN:
video &= ~(PM3VideoControl_HSYNC_MASK |
PM3VideoControl_VSYNC_MASK |
PM3VideoControl_BLANK_ACTIVE_LOW);
break;
default:
DPRINTK("Unsupported blanking %d\n", blank_mode);
return 1;
}
PM3_WAIT(par, 1);
PM3_WRITE_REG(par, PM3VideoControl, video);
return 0;
}
/*
* Frame buffer operations
*/
static const struct fb_ops pm3fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = pm3fb_check_var,
.fb_set_par = pm3fb_set_par,
.fb_setcolreg = pm3fb_setcolreg,
.fb_pan_display = pm3fb_pan_display,
.fb_fillrect = pm3fb_fillrect,
.fb_copyarea = pm3fb_copyarea,
.fb_imageblit = pm3fb_imageblit,
.fb_blank = pm3fb_blank,
.fb_sync = pm3fb_sync,
.fb_cursor = pm3fb_cursor,
};
/* ------------------------------------------------------------------------- */
/*
* Initialization
*/
/* mmio register are already mapped when this function is called */
/* the pm3fb_fix.smem_start is also set */
static unsigned long pm3fb_size_memory(struct pm3_par *par)
{
unsigned long memsize = 0;
unsigned long tempBypass, i, temp1, temp2;
unsigned char __iomem *screen_mem;
pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
/* Linear frame buffer - request region and map it. */
if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
"pm3fb smem")) {
printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
return 0;
}
screen_mem =
ioremap(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
if (!screen_mem) {
printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
return 0;
}
/* TODO: card-specific stuff, *before* accessing *any* FB memory */
/* For Appian Jeronimo 2000 board second head */
tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
PM3_WAIT(par, 1);
PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
/* pm3 split up memory, replicates, and do a lot of
* nasty stuff IMHO ;-)
*/
for (i = 0; i < 32; i++) {
fb_writel(i * 0x00345678,
(screen_mem + (i * 1048576)));
mb();
temp1 = fb_readl((screen_mem + (i * 1048576)));
/* Let's check for wrapover, write will fail at 16MB boundary */
if (temp1 == (i * 0x00345678))
memsize = i;
else
break;
}
DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
if (memsize + 1 == i) {
for (i = 0; i < 32; i++) {
/* Clear first 32MB ; 0 is 0, no need to byteswap */
writel(0x0000000, (screen_mem + (i * 1048576)));
}
wmb();
for (i = 32; i < 64; i++) {
fb_writel(i * 0x00345678,
(screen_mem + (i * 1048576)));
mb();
temp1 =
fb_readl((screen_mem + (i * 1048576)));
temp2 =
fb_readl((screen_mem + ((i - 32) * 1048576)));
/* different value, different RAM... */
if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
memsize = i;
else
break;
}
}
DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
PM3_WAIT(par, 1);
PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
iounmap(screen_mem);
release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
memsize = 1048576 * (memsize + 1);
DPRINTK("Returning 0x%08lx bytes\n", memsize);
return memsize;
}
static int pm3fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
{
struct fb_info *info;
struct pm3_par *par;
struct device *device = &dev->dev; /* for pci drivers */
int err;
int retval = -ENXIO;
err = aperture_remove_conflicting_pci_devices(dev, "pm3fb");
if (err)
return err;
err = pci_enable_device(dev);
if (err) {
printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
return err;
}
/*
* Dynamically allocate info and par
*/
info = framebuffer_alloc(sizeof(struct pm3_par), device);
if (!info)
return -ENOMEM;
par = info->par;
/*
* Here we set the screen_base to the virtual memory address
* for the framebuffer.
*/
pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
pm3fb_fix.mmio_len = PM3_REGS_SIZE;
#if defined(__BIG_ENDIAN)
pm3fb_fix.mmio_start += PM3_REGS_SIZE;
DPRINTK("Adjusting register base for big-endian.\n");
#endif
/* Registers - request region and map it. */
if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
"pm3fb regbase")) {
printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
goto err_exit_neither;
}
par->v_regs =
ioremap(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
if (!par->v_regs) {
printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
pm3fb_fix.id);
release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
goto err_exit_neither;
}
/* Linear frame buffer - request region and map it. */
pm3fb_fix.smem_start = pci_resource_start(dev, 1);
pm3fb_fix.smem_len = pm3fb_size_memory(par);
if (!pm3fb_fix.smem_len) {
printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
goto err_exit_mmio;
}
if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
"pm3fb smem")) {
printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
goto err_exit_mmio;
}
info->screen_base = ioremap_wc(pm3fb_fix.smem_start,
pm3fb_fix.smem_len);
if (!info->screen_base) {
printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
goto err_exit_mmio;
}
info->screen_size = pm3fb_fix.smem_len;
if (!nomtrr)
par->wc_cookie = arch_phys_wc_add(pm3fb_fix.smem_start,
pm3fb_fix.smem_len);
info->fbops = &pm3fb_ops;
par->video = PM3_READ_REG(par, PM3VideoControl);
info->fix = pm3fb_fix;
info->pseudo_palette = par->palette;
info->flags = FBINFO_HWACCEL_XPAN |
FBINFO_HWACCEL_YPAN |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_HWACCEL_FILLRECT;
if (noaccel) {
printk(KERN_DEBUG "disabling acceleration\n");
info->flags |= FBINFO_HWACCEL_DISABLED;
}
info->pixmap.addr = kmalloc(PM3_PIXMAP_SIZE, GFP_KERNEL);
if (!info->pixmap.addr) {
retval = -ENOMEM;
goto err_exit_pixmap;
}
info->pixmap.size = PM3_PIXMAP_SIZE;
info->pixmap.buf_align = 4;
info->pixmap.scan_align = 4;
info->pixmap.access_align = 32;
info->pixmap.flags = FB_PIXMAP_SYSTEM;
/*
* This should give a reasonable default video mode. The following is
* done when we can set a video mode.
*/
if (!mode_option)
mode_option = "640x480@60";
retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
if (!retval || retval == 4) {
retval = -EINVAL;
goto err_exit_both;
}
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
retval = -ENOMEM;
goto err_exit_both;
}
/*
* For drivers that can...
*/
pm3fb_check_var(&info->var, info);
if (register_framebuffer(info) < 0) {
retval = -EINVAL;
goto err_exit_all;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
pci_set_drvdata(dev, info);
return 0;
err_exit_all:
fb_dealloc_cmap(&info->cmap);
err_exit_both:
kfree(info->pixmap.addr);
err_exit_pixmap:
iounmap(info->screen_base);
release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
err_exit_mmio:
iounmap(par->v_regs);
release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
err_exit_neither:
framebuffer_release(info);
return retval;
}
/*
* Cleanup
*/
static void pm3fb_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
if (info) {
struct fb_fix_screeninfo *fix = &info->fix;
struct pm3_par *par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
arch_phys_wc_del(par->wc_cookie);
iounmap(info->screen_base);
release_mem_region(fix->smem_start, fix->smem_len);
iounmap(par->v_regs);
release_mem_region(fix->mmio_start, fix->mmio_len);
kfree(info->pixmap.addr);
framebuffer_release(info);
}
}
static const struct pci_device_id pm3fb_id_table[] = {
{ PCI_VENDOR_ID_3DLABS, 0x0a,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ 0, }
};
/* For PCI drivers */
static struct pci_driver pm3fb_driver = {
.name = "pm3fb",
.id_table = pm3fb_id_table,
.probe = pm3fb_probe,
.remove = pm3fb_remove,
};
MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
#ifndef MODULE
/*
* Setup
*/
/*
* Only necessary if your driver takes special options,
* otherwise we fall back on the generic fb_setup().
*/
static int __init pm3fb_setup(char *options)
{
char *this_opt;
/* Parse user specified options (`video=pm3fb:') */
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
else if (!strncmp(this_opt, "noaccel", 7))
noaccel = 1;
else if (!strncmp(this_opt, "hwcursor=", 9))
hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
else if (!strncmp(this_opt, "nomtrr", 6))
nomtrr = 1;
else
mode_option = this_opt;
}
return 0;
}
#endif /* MODULE */
static int __init pm3fb_init(void)
{
/*
* For kernel boot options (in 'video=pm3fb:<options>' format)
*/
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("pm3fb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("pm3fb", &option))
return -ENODEV;
pm3fb_setup(option);
#endif
return pci_register_driver(&pm3fb_driver);
}
#ifdef MODULE
static void __exit pm3fb_exit(void)
{
pci_unregister_driver(&pm3fb_driver);
}
module_exit(pm3fb_exit);
#endif
module_init(pm3fb_init);
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
module_param(noaccel, bool, 0);
MODULE_PARM_DESC(noaccel, "Disable acceleration");
module_param(hwcursor, int, 0644);
MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
"(1=enable, 0=disable, default=1)");
module_param(nomtrr, bool, 0);
MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
MODULE_DESCRIPTION("Permedia3 framebuffer device driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/pm3fb.c |
/*
* linux/drivers/video/pxa168fb.c -- Marvell PXA168 LCD Controller
*
* Copyright (C) 2008 Marvell International Ltd.
* All rights reserved.
*
* 2009-02-16 adapted from original version for PXA168/910
* Jun Nie <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/uaccess.h>
#include <video/pxa168fb.h>
#include "pxa168fb.h"
#define DEFAULT_REFRESH 60 /* Hz */
static int determine_best_pix_fmt(struct fb_var_screeninfo *var)
{
/*
* Pseudocolor mode?
*/
if (var->bits_per_pixel == 8)
return PIX_FMT_PSEUDOCOLOR;
/*
* Check for 565/1555.
*/
if (var->bits_per_pixel == 16 && var->red.length <= 5 &&
var->green.length <= 6 && var->blue.length <= 5) {
if (var->transp.length == 0) {
if (var->red.offset >= var->blue.offset)
return PIX_FMT_RGB565;
else
return PIX_FMT_BGR565;
}
if (var->transp.length == 1 && var->green.length <= 5) {
if (var->red.offset >= var->blue.offset)
return PIX_FMT_RGB1555;
else
return PIX_FMT_BGR1555;
}
}
/*
* Check for 888/A888.
*/
if (var->bits_per_pixel <= 32 && var->red.length <= 8 &&
var->green.length <= 8 && var->blue.length <= 8) {
if (var->bits_per_pixel == 24 && var->transp.length == 0) {
if (var->red.offset >= var->blue.offset)
return PIX_FMT_RGB888PACK;
else
return PIX_FMT_BGR888PACK;
}
if (var->bits_per_pixel == 32 && var->transp.length == 8) {
if (var->red.offset >= var->blue.offset)
return PIX_FMT_RGBA888;
else
return PIX_FMT_BGRA888;
} else {
if (var->red.offset >= var->blue.offset)
return PIX_FMT_RGB888UNPACK;
else
return PIX_FMT_BGR888UNPACK;
}
}
return -EINVAL;
}
static void set_pix_fmt(struct fb_var_screeninfo *var, int pix_fmt)
{
switch (pix_fmt) {
case PIX_FMT_RGB565:
var->bits_per_pixel = 16;
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIX_FMT_BGR565:
var->bits_per_pixel = 16;
var->red.offset = 0; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 11; var->blue.length = 5;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIX_FMT_RGB1555:
var->bits_per_pixel = 16;
var->red.offset = 10; var->red.length = 5;
var->green.offset = 5; var->green.length = 5;
var->blue.offset = 0; var->blue.length = 5;
var->transp.offset = 15; var->transp.length = 1;
break;
case PIX_FMT_BGR1555:
var->bits_per_pixel = 16;
var->red.offset = 0; var->red.length = 5;
var->green.offset = 5; var->green.length = 5;
var->blue.offset = 10; var->blue.length = 5;
var->transp.offset = 15; var->transp.length = 1;
break;
case PIX_FMT_RGB888PACK:
var->bits_per_pixel = 24;
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIX_FMT_BGR888PACK:
var->bits_per_pixel = 24;
var->red.offset = 0; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 16; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIX_FMT_RGBA888:
var->bits_per_pixel = 32;
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 24; var->transp.length = 8;
break;
case PIX_FMT_BGRA888:
var->bits_per_pixel = 32;
var->red.offset = 0; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 16; var->blue.length = 8;
var->transp.offset = 24; var->transp.length = 8;
break;
case PIX_FMT_PSEUDOCOLOR:
var->bits_per_pixel = 8;
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
}
}
static void set_mode(struct pxa168fb_info *fbi, struct fb_var_screeninfo *var,
struct fb_videomode *mode, int pix_fmt, int ystretch)
{
struct fb_info *info = fbi->info;
set_pix_fmt(var, pix_fmt);
var->xres = mode->xres;
var->yres = mode->yres;
var->xres_virtual = max(var->xres, var->xres_virtual);
if (ystretch)
var->yres_virtual = info->fix.smem_len /
(var->xres_virtual * (var->bits_per_pixel >> 3));
else
var->yres_virtual = max(var->yres, var->yres_virtual);
var->grayscale = 0;
var->accel_flags = FB_ACCEL_NONE;
var->pixclock = mode->pixclock;
var->left_margin = mode->left_margin;
var->right_margin = mode->right_margin;
var->upper_margin = mode->upper_margin;
var->lower_margin = mode->lower_margin;
var->hsync_len = mode->hsync_len;
var->vsync_len = mode->vsync_len;
var->sync = mode->sync;
var->vmode = FB_VMODE_NONINTERLACED;
var->rotate = FB_ROTATE_UR;
}
static int pxa168fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct pxa168fb_info *fbi = info->par;
int pix_fmt;
/*
* Determine which pixel format we're going to use.
*/
pix_fmt = determine_best_pix_fmt(var);
if (pix_fmt < 0)
return pix_fmt;
set_pix_fmt(var, pix_fmt);
fbi->pix_fmt = pix_fmt;
/*
* Basic geometry sanity checks.
*/
if (var->xoffset + var->xres > var->xres_virtual)
return -EINVAL;
if (var->yoffset + var->yres > var->yres_virtual)
return -EINVAL;
if (var->xres + var->right_margin +
var->hsync_len + var->left_margin > 2048)
return -EINVAL;
if (var->yres + var->lower_margin +
var->vsync_len + var->upper_margin > 2048)
return -EINVAL;
/*
* Check size of framebuffer.
*/
if (var->xres_virtual * var->yres_virtual *
(var->bits_per_pixel >> 3) > info->fix.smem_len)
return -EINVAL;
return 0;
}
/*
* The hardware clock divider has an integer and a fractional
* stage:
*
* clk2 = clk_in / integer_divider
* clk_out = clk2 * (1 - (fractional_divider >> 12))
*
* Calculate integer and fractional divider for given clk_in
* and clk_out.
*/
static void set_clock_divider(struct pxa168fb_info *fbi,
const struct fb_videomode *m)
{
int divider_int;
int needed_pixclk;
u64 div_result;
u32 x = 0;
/*
* Notice: The field pixclock is used by linux fb
* is in pixel second. E.g. struct fb_videomode &
* struct fb_var_screeninfo
*/
/*
* Check input values.
*/
if (!m || !m->pixclock || !m->refresh) {
dev_err(fbi->dev, "Input refresh or pixclock is wrong.\n");
return;
}
/*
* Using PLL/AXI clock.
*/
x = 0x80000000;
/*
* Calc divider according to refresh rate.
*/
div_result = 1000000000000ll;
do_div(div_result, m->pixclock);
needed_pixclk = (u32)div_result;
divider_int = clk_get_rate(fbi->clk) / needed_pixclk;
/* check whether divisor is too small. */
if (divider_int < 2) {
dev_warn(fbi->dev, "Warning: clock source is too slow. "
"Try smaller resolution\n");
divider_int = 2;
}
/*
* Set setting to reg.
*/
x |= divider_int;
writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV);
}
static void set_dma_control0(struct pxa168fb_info *fbi)
{
u32 x;
/*
* Set bit to enable graphics DMA.
*/
x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
x &= ~CFG_GRA_ENA_MASK;
x |= fbi->active ? CFG_GRA_ENA(1) : CFG_GRA_ENA(0);
/*
* If we are in a pseudo-color mode, we need to enable
* palette lookup.
*/
if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR)
x |= 0x10000000;
/*
* Configure hardware pixel format.
*/
x &= ~(0xF << 16);
x |= (fbi->pix_fmt >> 1) << 16;
/*
* Check red and blue pixel swap.
* 1. source data swap
* 2. panel output data swap
*/
x &= ~(1 << 12);
x |= ((fbi->pix_fmt & 1) ^ (fbi->panel_rbswap)) << 12;
writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);
}
static void set_dma_control1(struct pxa168fb_info *fbi, int sync)
{
u32 x;
/*
* Configure default bits: vsync triggers DMA, gated clock
* enable, power save enable, configure alpha registers to
* display 100% graphics, and set pixel command.
*/
x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1);
x |= 0x2032ff81;
/*
* We trigger DMA on the falling edge of vsync if vsync is
* active low, or on the rising edge if vsync is active high.
*/
if (!(sync & FB_SYNC_VERT_HIGH_ACT))
x |= 0x08000000;
writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1);
}
static void set_graphics_start(struct fb_info *info, int xoffset, int yoffset)
{
struct pxa168fb_info *fbi = info->par;
struct fb_var_screeninfo *var = &info->var;
int pixel_offset;
unsigned long addr;
pixel_offset = (yoffset * var->xres_virtual) + xoffset;
addr = fbi->fb_start_dma + (pixel_offset * (var->bits_per_pixel >> 3));
writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0);
}
static void set_dumb_panel_control(struct fb_info *info)
{
struct pxa168fb_info *fbi = info->par;
struct pxa168fb_mach_info *mi = dev_get_platdata(fbi->dev);
u32 x;
/*
* Preserve enable flag.
*/
x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001;
x |= (fbi->is_blanked ? 0x7 : mi->dumb_mode) << 28;
x |= mi->gpio_output_data << 20;
x |= mi->gpio_output_mask << 12;
x |= mi->panel_rgb_reverse_lanes ? 0x00000080 : 0;
x |= mi->invert_composite_blank ? 0x00000040 : 0;
x |= (info->var.sync & FB_SYNC_COMP_HIGH_ACT) ? 0x00000020 : 0;
x |= mi->invert_pix_val_ena ? 0x00000010 : 0;
x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x00000008;
x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x00000004;
x |= mi->invert_pixclock ? 0x00000002 : 0;
writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL);
}
static void set_dumb_screen_dimensions(struct fb_info *info)
{
struct pxa168fb_info *fbi = info->par;
struct fb_var_screeninfo *v = &info->var;
int x;
int y;
x = v->xres + v->right_margin + v->hsync_len + v->left_margin;
y = v->yres + v->lower_margin + v->vsync_len + v->upper_margin;
writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL);
}
static int pxa168fb_set_par(struct fb_info *info)
{
struct pxa168fb_info *fbi = info->par;
struct fb_var_screeninfo *var = &info->var;
struct fb_videomode mode;
u32 x;
/*
* Set additional mode info.
*/
if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR)
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
else
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
info->fix.ypanstep = var->yres;
/*
* Disable panel output while we setup the display.
*/
x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);
writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL);
/*
* Configure global panel parameters.
*/
writel((var->yres << 16) | var->xres,
fbi->reg_base + LCD_SPU_V_H_ACTIVE);
/*
* convet var to video mode
*/
fb_var_to_videomode(&mode, &info->var);
/* Calculate clock divisor. */
set_clock_divider(fbi, &mode);
/* Configure dma ctrl regs. */
set_dma_control0(fbi);
set_dma_control1(fbi, info->var.sync);
/*
* Configure graphics DMA parameters.
*/
x = readl(fbi->reg_base + LCD_CFG_GRA_PITCH);
x = (x & ~0xFFFF) | ((var->xres_virtual * var->bits_per_pixel) >> 3);
writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH);
writel((var->yres << 16) | var->xres,
fbi->reg_base + LCD_SPU_GRA_HPXL_VLN);
writel((var->yres << 16) | var->xres,
fbi->reg_base + LCD_SPU_GZM_HPXL_VLN);
/*
* Configure dumb panel ctrl regs & timings.
*/
set_dumb_panel_control(info);
set_dumb_screen_dimensions(info);
writel((var->left_margin << 16) | var->right_margin,
fbi->reg_base + LCD_SPU_H_PORCH);
writel((var->upper_margin << 16) | var->lower_margin,
fbi->reg_base + LCD_SPU_V_PORCH);
/*
* Re-enable panel output.
*/
x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL);
writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL);
return 0;
}
static unsigned int chan_to_field(unsigned int chan, struct fb_bitfield *bf)
{
return ((chan & 0xffff) >> (16 - bf->length)) << bf->offset;
}
static u32 to_rgb(u16 red, u16 green, u16 blue)
{
red >>= 8;
green >>= 8;
blue >>= 8;
return (red << 16) | (green << 8) | blue;
}
static int
pxa168fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
unsigned int blue, unsigned int trans, struct fb_info *info)
{
struct pxa168fb_info *fbi = info->par;
u32 val;
if (info->var.grayscale)
red = green = blue = (19595 * red + 38470 * green +
7471 * blue) >> 16;
if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) {
val = chan_to_field(red, &info->var.red);
val |= chan_to_field(green, &info->var.green);
val |= chan_to_field(blue , &info->var.blue);
fbi->pseudo_palette[regno] = val;
}
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
val = to_rgb(red, green, blue);
writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT);
writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL);
}
return 0;
}
static int pxa168fb_blank(int blank, struct fb_info *info)
{
struct pxa168fb_info *fbi = info->par;
fbi->is_blanked = (blank == FB_BLANK_UNBLANK) ? 0 : 1;
set_dumb_panel_control(info);
return 0;
}
static int pxa168fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
set_graphics_start(info, var->xoffset, var->yoffset);
return 0;
}
static irqreturn_t pxa168fb_handle_irq(int irq, void *dev_id)
{
struct pxa168fb_info *fbi = dev_id;
u32 isr = readl(fbi->reg_base + SPU_IRQ_ISR);
if ((isr & GRA_FRAME_IRQ0_ENA_MASK)) {
writel(isr & (~GRA_FRAME_IRQ0_ENA_MASK),
fbi->reg_base + SPU_IRQ_ISR);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static const struct fb_ops pxa168fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = pxa168fb_check_var,
.fb_set_par = pxa168fb_set_par,
.fb_setcolreg = pxa168fb_setcolreg,
.fb_blank = pxa168fb_blank,
.fb_pan_display = pxa168fb_pan_display,
};
static void pxa168fb_init_mode(struct fb_info *info,
struct pxa168fb_mach_info *mi)
{
struct pxa168fb_info *fbi = info->par;
struct fb_var_screeninfo *var = &info->var;
u32 total_w, total_h, refresh;
u64 div_result;
const struct fb_videomode *m;
/*
* Set default value
*/
refresh = DEFAULT_REFRESH;
/* try to find best video mode. */
m = fb_find_best_mode(&info->var, &info->modelist);
if (m)
fb_videomode_to_var(&info->var, m);
/* Init settings. */
var->xres_virtual = var->xres;
var->yres_virtual = info->fix.smem_len /
(var->xres_virtual * (var->bits_per_pixel >> 3));
dev_dbg(fbi->dev, "pxa168fb: find best mode: res = %dx%d\n",
var->xres, var->yres);
/* correct pixclock. */
total_w = var->xres + var->left_margin + var->right_margin +
var->hsync_len;
total_h = var->yres + var->upper_margin + var->lower_margin +
var->vsync_len;
div_result = 1000000000000ll;
do_div(div_result, total_w * total_h * refresh);
var->pixclock = (u32)div_result;
}
static int pxa168fb_probe(struct platform_device *pdev)
{
struct pxa168fb_mach_info *mi;
struct fb_info *info = NULL;
struct pxa168fb_info *fbi = NULL;
struct resource *res;
struct clk *clk;
int irq, ret;
mi = dev_get_platdata(&pdev->dev);
if (mi == NULL) {
dev_err(&pdev->dev, "no platform data defined\n");
return -EINVAL;
}
clk = devm_clk_get(&pdev->dev, "LCDCLK");
if (IS_ERR(clk))
return dev_err_probe(&pdev->dev, PTR_ERR(clk),
"unable to get LCDCLK");
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "no IO memory defined\n");
return -ENOENT;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -ENOENT;
info = framebuffer_alloc(sizeof(struct pxa168fb_info), &pdev->dev);
if (info == NULL) {
return -ENOMEM;
}
/* Initialize private data */
fbi = info->par;
fbi->info = info;
fbi->clk = clk;
fbi->dev = &pdev->dev;
fbi->panel_rbswap = mi->panel_rbswap;
fbi->is_blanked = 0;
fbi->active = mi->active;
/*
* Initialise static fb parameters.
*/
info->flags = FBINFO_PARTIAL_PAN_OK |
FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
info->node = -1;
strscpy(info->fix.id, mi->id, 16);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.mmio_start = res->start;
info->fix.mmio_len = resource_size(res);
info->fix.accel = FB_ACCEL_NONE;
info->fbops = &pxa168fb_ops;
info->pseudo_palette = fbi->pseudo_palette;
/*
* Map LCD controller registers.
*/
fbi->reg_base = devm_ioremap(&pdev->dev, res->start,
resource_size(res));
if (fbi->reg_base == NULL) {
ret = -ENOMEM;
goto failed_free_info;
}
/*
* Allocate framebuffer memory.
*/
info->fix.smem_len = PAGE_ALIGN(DEFAULT_FB_SIZE);
info->screen_base = dma_alloc_wc(fbi->dev, info->fix.smem_len,
&fbi->fb_start_dma, GFP_KERNEL);
if (info->screen_base == NULL) {
ret = -ENOMEM;
goto failed_free_info;
}
info->fix.smem_start = (unsigned long)fbi->fb_start_dma;
set_graphics_start(info, 0, 0);
/*
* Set video mode according to platform data.
*/
set_mode(fbi, &info->var, mi->modes, mi->pix_fmt, 1);
fb_videomode_to_modelist(mi->modes, mi->num_modes, &info->modelist);
/*
* init video mode data.
*/
pxa168fb_init_mode(info, mi);
/*
* Fill in sane defaults.
*/
ret = pxa168fb_check_var(&info->var, info);
if (ret)
goto failed_free_fbmem;
/*
* enable controller clock
*/
clk_prepare_enable(fbi->clk);
pxa168fb_set_par(info);
/*
* Configure default register values.
*/
writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR);
writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL);
writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1);
writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN);
writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0);
writel(CFG_CSB_256x32(0x1)|CFG_CSB_256x24(0x1)|CFG_CSB_256x8(0x1),
fbi->reg_base + LCD_SPU_SRAM_PARA1);
/*
* Allocate color map.
*/
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
ret = -ENOMEM;
goto failed_free_clk;
}
/*
* Register irq handler.
*/
ret = devm_request_irq(&pdev->dev, irq, pxa168fb_handle_irq,
IRQF_SHARED, info->fix.id, fbi);
if (ret < 0) {
dev_err(&pdev->dev, "unable to request IRQ\n");
ret = -ENXIO;
goto failed_free_cmap;
}
/*
* Enable GFX interrupt
*/
writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA);
/*
* Register framebuffer.
*/
ret = register_framebuffer(info);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register pxa168-fb: %d\n", ret);
ret = -ENXIO;
goto failed_free_cmap;
}
platform_set_drvdata(pdev, fbi);
return 0;
failed_free_cmap:
fb_dealloc_cmap(&info->cmap);
failed_free_clk:
clk_disable_unprepare(fbi->clk);
failed_free_fbmem:
dma_free_wc(fbi->dev, info->fix.smem_len,
info->screen_base, fbi->fb_start_dma);
failed_free_info:
framebuffer_release(info);
dev_err(&pdev->dev, "frame buffer device init failed with %d\n", ret);
return ret;
}
static void pxa168fb_remove(struct platform_device *pdev)
{
struct pxa168fb_info *fbi = platform_get_drvdata(pdev);
struct fb_info *info;
unsigned int data;
if (!fbi)
return;
/* disable DMA transfer */
data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
data &= ~CFG_GRA_ENA_MASK;
writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0);
info = fbi->info;
unregister_framebuffer(info);
writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA);
if (info->cmap.len)
fb_dealloc_cmap(&info->cmap);
dma_free_wc(fbi->dev, info->fix.smem_len,
info->screen_base, info->fix.smem_start);
clk_disable_unprepare(fbi->clk);
framebuffer_release(info);
}
static struct platform_driver pxa168fb_driver = {
.driver = {
.name = "pxa168-fb",
},
.probe = pxa168fb_probe,
.remove_new = pxa168fb_remove,
};
module_platform_driver(pxa168fb_driver);
MODULE_AUTHOR("Lennert Buytenhek <[email protected]> "
"Green Wan <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for PXA168/910");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/pxa168fb.c |
/*
* valkyriefb.c -- frame buffer device for the PowerMac 'valkyrie' display
*
* Created 8 August 1998 by
* Martin Costabel <[email protected]> and Kevin Schoedel
*
* Vmode-switching changes and vmode 15/17 modifications created 29 August
* 1998 by Barry K. Nathan <[email protected]>.
*
* Ported to m68k Macintosh by David Huggins-Daines <[email protected]>
*
* Derived directly from:
*
* controlfb.c -- frame buffer device for the PowerMac 'control' display
* Copyright (C) 1998 Dan Jacobowitz <[email protected]>
*
* pmc-valkyrie.c -- Console support for PowerMac "valkyrie" display adaptor.
* Copyright (C) 1997 Paul Mackerras.
*
* and indirectly:
*
* Frame buffer structure from:
* drivers/video/chipsfb.c -- frame buffer device for
* Chips & Technologies 65550 chip.
*
* Copyright (C) 1998 Paul Mackerras
*
* This file is derived from the Powermac "chips" driver:
* Copyright (C) 1997 Fabio Riccardi.
* And from the frame buffer device for Open Firmware-initialized devices:
* Copyright (C) 1997 Geert Uytterhoeven.
*
* Hardware information from:
* control.c: Console support for PowerMac "control" display adaptor.
* Copyright (C) 1996 Paul Mackerras
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/selection.h>
#include <linux/init.h>
#include <linux/nvram.h>
#include <linux/adb.h>
#include <linux/cuda.h>
#include <linux/of_address.h>
#ifdef CONFIG_MAC
#include <asm/macintosh.h>
#endif
#include "macmodes.h"
#include "valkyriefb.h"
static int default_vmode = VMODE_NVRAM;
static int default_cmode = CMODE_NVRAM;
struct fb_par_valkyrie {
int vmode, cmode;
int xres, yres;
int vxres, vyres;
struct valkyrie_regvals *init;
};
struct fb_info_valkyrie {
struct fb_info info;
struct fb_par_valkyrie par;
struct cmap_regs __iomem *cmap_regs;
unsigned long cmap_regs_phys;
struct valkyrie_regs __iomem *valkyrie_regs;
unsigned long valkyrie_regs_phys;
__u8 __iomem *frame_buffer;
unsigned long frame_buffer_phys;
int sense;
unsigned long total_vram;
u32 pseudo_palette[16];
};
static int valkyriefb_setup(char*);
static int valkyriefb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info);
static int valkyriefb_set_par(struct fb_info *info);
static int valkyriefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int valkyriefb_blank(int blank_mode, struct fb_info *info);
static int read_valkyrie_sense(struct fb_info_valkyrie *p);
static void set_valkyrie_clock(unsigned char *params);
static int valkyrie_var_to_par(struct fb_var_screeninfo *var,
struct fb_par_valkyrie *par, const struct fb_info *fb_info);
static int valkyrie_init_info(struct fb_info *info, struct fb_info_valkyrie *p);
static void valkyrie_par_to_fix(struct fb_par_valkyrie *par, struct fb_fix_screeninfo *fix);
static void valkyrie_init_fix(struct fb_fix_screeninfo *fix, struct fb_info_valkyrie *p);
static const struct fb_ops valkyriefb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = valkyriefb_check_var,
.fb_set_par = valkyriefb_set_par,
.fb_setcolreg = valkyriefb_setcolreg,
.fb_blank = valkyriefb_blank,
};
/* Sets the video mode according to info->var */
static int valkyriefb_set_par(struct fb_info *info)
{
struct fb_info_valkyrie *p =
container_of(info, struct fb_info_valkyrie, info);
volatile struct valkyrie_regs __iomem *valkyrie_regs = p->valkyrie_regs;
struct fb_par_valkyrie *par = info->par;
struct valkyrie_regvals *init;
int err;
if ((err = valkyrie_var_to_par(&info->var, par, info)))
return err;
valkyrie_par_to_fix(par, &info->fix);
/* Reset the valkyrie */
out_8(&valkyrie_regs->status.r, 0);
udelay(100);
/* Initialize display timing registers */
init = par->init;
out_8(&valkyrie_regs->mode.r, init->mode | 0x80);
out_8(&valkyrie_regs->depth.r, par->cmode + 3);
set_valkyrie_clock(init->clock_params);
udelay(100);
/* Turn on display */
out_8(&valkyrie_regs->mode.r, init->mode);
return 0;
}
static inline int valkyrie_par_to_var(struct fb_par_valkyrie *par,
struct fb_var_screeninfo *var)
{
return mac_vmode_to_var(par->vmode, par->cmode, var);
}
static int
valkyriefb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
int err;
struct fb_par_valkyrie par;
if ((err = valkyrie_var_to_par(var, &par, info)))
return err;
valkyrie_par_to_var(&par, var);
return 0;
}
/*
* Blank the screen if blank_mode != 0, else unblank. If blank_mode == NULL
* then the caller blanks by setting the CLUT (Color Look Up Table) to all
* black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
* to e.g. a video mode which doesn't support it. Implements VESA suspend
* and powerdown modes on hardware that supports disabling hsync/vsync:
* blank_mode == 2: suspend vsync
* blank_mode == 3: suspend hsync
* blank_mode == 4: powerdown
*/
static int valkyriefb_blank(int blank_mode, struct fb_info *info)
{
struct fb_info_valkyrie *p =
container_of(info, struct fb_info_valkyrie, info);
struct fb_par_valkyrie *par = info->par;
struct valkyrie_regvals *init = par->init;
if (init == NULL)
return 1;
switch (blank_mode) {
case FB_BLANK_UNBLANK: /* unblank */
out_8(&p->valkyrie_regs->mode.r, init->mode);
break;
case FB_BLANK_NORMAL:
return 1; /* get caller to set CLUT to all black */
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
/*
* [kps] Value extracted from MacOS. I don't know
* whether this bit disables hsync or vsync, or
* whether the hardware can do the other as well.
*/
out_8(&p->valkyrie_regs->mode.r, init->mode | 0x40);
break;
case FB_BLANK_POWERDOWN:
out_8(&p->valkyrie_regs->mode.r, 0x66);
break;
}
return 0;
}
static int valkyriefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct fb_info_valkyrie *p =
container_of(info, struct fb_info_valkyrie, info);
volatile struct cmap_regs __iomem *cmap_regs = p->cmap_regs;
struct fb_par_valkyrie *par = info->par;
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
/* tell clut which address to fill */
out_8(&p->cmap_regs->addr, regno);
udelay(1);
/* send one color channel at a time */
out_8(&cmap_regs->lut, red);
out_8(&cmap_regs->lut, green);
out_8(&cmap_regs->lut, blue);
if (regno < 16 && par->cmode == CMODE_16)
((u32 *)info->pseudo_palette)[regno] =
(regno << 10) | (regno << 5) | regno;
return 0;
}
static inline int valkyrie_vram_reqd(int video_mode, int color_mode)
{
int pitch;
struct valkyrie_regvals *init = valkyrie_reg_init[video_mode-1];
if ((pitch = init->pitch[color_mode]) == 0)
pitch = 2 * init->pitch[0];
return init->vres * pitch;
}
static void set_valkyrie_clock(unsigned char *params)
{
#ifdef CONFIG_ADB_CUDA
struct adb_request req;
int i;
for (i = 0; i < 3; ++i) {
cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
0x50, i + 1, params[i]);
while (!req.complete)
cuda_poll();
}
#endif
}
static void __init valkyrie_choose_mode(struct fb_info_valkyrie *p)
{
p->sense = read_valkyrie_sense(p);
printk(KERN_INFO "Monitor sense value = 0x%x\n", p->sense);
/* Try to pick a video mode out of NVRAM if we have one. */
#ifdef CONFIG_PPC_PMAC
if (IS_REACHABLE(CONFIG_NVRAM) && default_vmode == VMODE_NVRAM)
default_vmode = nvram_read_byte(NV_VMODE);
#endif
if (default_vmode <= 0 || default_vmode > VMODE_MAX ||
!valkyrie_reg_init[default_vmode - 1]) {
default_vmode = mac_map_monitor_sense(p->sense);
if (!valkyrie_reg_init[default_vmode - 1])
default_vmode = VMODE_640_480_67;
}
#ifdef CONFIG_PPC_PMAC
if (IS_REACHABLE(CONFIG_NVRAM) && default_cmode == CMODE_NVRAM)
default_cmode = nvram_read_byte(NV_CMODE);
#endif
/*
* Reduce the pixel size if we don't have enough VRAM or bandwidth.
*/
if (default_cmode < CMODE_8 || default_cmode > CMODE_16
|| valkyrie_reg_init[default_vmode-1]->pitch[default_cmode] == 0
|| valkyrie_vram_reqd(default_vmode, default_cmode) > p->total_vram)
default_cmode = CMODE_8;
printk(KERN_INFO "using video mode %d and color mode %d.\n",
default_vmode, default_cmode);
}
static int __init valkyriefb_init(void)
{
struct fb_info_valkyrie *p;
unsigned long frame_buffer_phys, cmap_regs_phys;
int err;
char *option = NULL;
if (fb_get_options("valkyriefb", &option))
return -ENODEV;
valkyriefb_setup(option);
#ifdef CONFIG_MAC
if (!MACH_IS_MAC)
return -ENODEV;
if (!(mac_bi_data.id == MAC_MODEL_Q630
/* I'm not sure about this one */
|| mac_bi_data.id == MAC_MODEL_P588))
return -ENODEV;
/* Hardcoded addresses... welcome to 68k Macintosh country :-) */
frame_buffer_phys = 0xf9000000;
cmap_regs_phys = 0x50f24000;
#else /* ppc (!CONFIG_MAC) */
{
struct device_node *dp;
struct resource r;
dp = of_find_node_by_name(NULL, "valkyrie");
if (!dp)
return 0;
if (of_address_to_resource(dp, 0, &r)) {
printk(KERN_ERR "can't find address for valkyrie\n");
return 0;
}
frame_buffer_phys = r.start;
cmap_regs_phys = r.start + 0x304000;
}
#endif /* ppc (!CONFIG_MAC) */
p = kzalloc(sizeof(*p), GFP_ATOMIC);
if (!p)
return -ENOMEM;
/* Map in frame buffer and registers */
if (!request_mem_region(frame_buffer_phys, 0x100000, "valkyriefb")) {
kfree(p);
return 0;
}
p->total_vram = 0x100000;
p->frame_buffer_phys = frame_buffer_phys;
#ifdef CONFIG_MAC
p->frame_buffer = ioremap(frame_buffer_phys, p->total_vram);
#else
p->frame_buffer = ioremap_wt(frame_buffer_phys, p->total_vram);
#endif
p->cmap_regs_phys = cmap_regs_phys;
p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
p->valkyrie_regs_phys = cmap_regs_phys+0x6000;
p->valkyrie_regs = ioremap(p->valkyrie_regs_phys, 0x1000);
err = -ENOMEM;
if (p->frame_buffer == NULL || p->cmap_regs == NULL
|| p->valkyrie_regs == NULL) {
printk(KERN_ERR "valkyriefb: couldn't map resources\n");
goto out_free;
}
valkyrie_choose_mode(p);
mac_vmode_to_var(default_vmode, default_cmode, &p->info.var);
err = valkyrie_init_info(&p->info, p);
if (err < 0)
goto out_free;
valkyrie_init_fix(&p->info.fix, p);
if (valkyriefb_set_par(&p->info))
/* "can't happen" */
printk(KERN_ERR "valkyriefb: can't set default video mode\n");
if ((err = register_framebuffer(&p->info)) != 0)
goto out_cmap_free;
fb_info(&p->info, "valkyrie frame buffer device\n");
return 0;
out_cmap_free:
fb_dealloc_cmap(&p->info.cmap);
out_free:
if (p->frame_buffer)
iounmap(p->frame_buffer);
if (p->cmap_regs)
iounmap(p->cmap_regs);
if (p->valkyrie_regs)
iounmap(p->valkyrie_regs);
kfree(p);
return err;
}
/*
* Get the monitor sense value.
*/
static int read_valkyrie_sense(struct fb_info_valkyrie *p)
{
int sense, in;
out_8(&p->valkyrie_regs->msense.r, 0); /* release all lines */
__delay(20000);
sense = ((in = in_8(&p->valkyrie_regs->msense.r)) & 0x70) << 4;
/* drive each sense line low in turn and collect the other 2 */
out_8(&p->valkyrie_regs->msense.r, 4); /* drive A low */
__delay(20000);
sense |= ((in = in_8(&p->valkyrie_regs->msense.r)) & 0x30);
out_8(&p->valkyrie_regs->msense.r, 2); /* drive B low */
__delay(20000);
sense |= ((in = in_8(&p->valkyrie_regs->msense.r)) & 0x40) >> 3;
sense |= (in & 0x10) >> 2;
out_8(&p->valkyrie_regs->msense.r, 1); /* drive C low */
__delay(20000);
sense |= ((in = in_8(&p->valkyrie_regs->msense.r)) & 0x60) >> 5;
out_8(&p->valkyrie_regs->msense.r, 7);
return sense;
}
/*
* This routine takes a user-supplied var,
* and picks the best vmode/cmode from it.
*/
/* [bkn] I did a major overhaul of this function.
*
* Much of the old code was "swiped by jonh from atyfb.c". Because
* macmodes has mac_var_to_vmode, I felt that it would be better to
* rework this function to use that, instead of reinventing the wheel to
* add support for vmode 17. This was reinforced by the fact that
* the previously swiped atyfb.c code is no longer there.
*
* So, I swiped and adapted platinum_var_to_par (from platinumfb.c), replacing
* most, but not all, of the old code in the process. One side benefit of
* swiping the platinumfb code is that we now have more comprehensible error
* messages when a vmode/cmode switch fails. (Most of the error messages are
* platinumfb.c, but I added two of my own, and I also changed some commas
* into colons to make the messages more consistent with other Linux error
* messages.) In addition, I think the new code *might* fix some vmode-
* switching oddities, but I'm not sure.
*
* There may be some more opportunities for cleanup in here, but this is a
* good start...
*/
static int valkyrie_var_to_par(struct fb_var_screeninfo *var,
struct fb_par_valkyrie *par, const struct fb_info *fb_info)
{
int vmode, cmode;
struct valkyrie_regvals *init;
struct fb_info_valkyrie *p =
container_of(fb_info, struct fb_info_valkyrie, info);
if (mac_var_to_vmode(var, &vmode, &cmode) != 0) {
printk(KERN_ERR "valkyriefb: can't do %dx%dx%d.\n",
var->xres, var->yres, var->bits_per_pixel);
return -EINVAL;
}
/* Check if we know about the wanted video mode */
if (vmode < 1 || vmode > VMODE_MAX || !valkyrie_reg_init[vmode-1]) {
printk(KERN_ERR "valkyriefb: vmode %d not valid.\n", vmode);
return -EINVAL;
}
if (cmode != CMODE_8 && cmode != CMODE_16) {
printk(KERN_ERR "valkyriefb: cmode %d not valid.\n", cmode);
return -EINVAL;
}
if (var->xres_virtual > var->xres || var->yres_virtual > var->yres
|| var->xoffset != 0 || var->yoffset != 0) {
return -EINVAL;
}
init = valkyrie_reg_init[vmode-1];
if (init->pitch[cmode] == 0) {
printk(KERN_ERR "valkyriefb: vmode %d does not support "
"cmode %d.\n", vmode, cmode);
return -EINVAL;
}
if (valkyrie_vram_reqd(vmode, cmode) > p->total_vram) {
printk(KERN_ERR "valkyriefb: not enough ram for vmode %d, "
"cmode %d.\n", vmode, cmode);
return -EINVAL;
}
par->vmode = vmode;
par->cmode = cmode;
par->init = init;
par->xres = var->xres;
par->yres = var->yres;
par->vxres = par->xres;
par->vyres = par->yres;
return 0;
}
static void valkyrie_init_fix(struct fb_fix_screeninfo *fix, struct fb_info_valkyrie *p)
{
memset(fix, 0, sizeof(*fix));
strcpy(fix->id, "valkyrie");
fix->mmio_start = p->valkyrie_regs_phys;
fix->mmio_len = sizeof(struct valkyrie_regs);
fix->type = FB_TYPE_PACKED_PIXELS;
fix->smem_start = p->frame_buffer_phys + 0x1000;
fix->smem_len = p->total_vram;
fix->type_aux = 0;
fix->ywrapstep = 0;
fix->ypanstep = 0;
fix->xpanstep = 0;
}
/* Fix must already be inited above */
static void valkyrie_par_to_fix(struct fb_par_valkyrie *par,
struct fb_fix_screeninfo *fix)
{
fix->smem_len = valkyrie_vram_reqd(par->vmode, par->cmode);
fix->visual = (par->cmode == CMODE_8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
fix->line_length = par->vxres << par->cmode;
/* ywrapstep, xpanstep, ypanstep */
}
static int __init valkyrie_init_info(struct fb_info *info,
struct fb_info_valkyrie *p)
{
info->fbops = &valkyriefb_ops;
info->screen_base = p->frame_buffer + 0x1000;
info->pseudo_palette = p->pseudo_palette;
info->par = &p->par;
return fb_alloc_cmap(&info->cmap, 256, 0);
}
/*
* Parse user specified options (`video=valkyriefb:')
*/
static int __init valkyriefb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "vmode:", 6)) {
int vmode = simple_strtoul(this_opt+6, NULL, 0);
if (vmode > 0 && vmode <= VMODE_MAX)
default_vmode = vmode;
}
else if (!strncmp(this_opt, "cmode:", 6)) {
int depth = simple_strtoul(this_opt+6, NULL, 0);
switch (depth) {
case 8:
default_cmode = CMODE_8;
break;
case 15:
case 16:
default_cmode = CMODE_16;
break;
}
}
}
return 0;
}
module_init(valkyriefb_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/valkyriefb.c |
// SPDX-License-Identifier: GPL-2.0-only
/* cg14.c: CGFOURTEEN frame buffer driver
*
* Copyright (C) 2003, 2006 David S. Miller ([email protected])
* Copyright (C) 1996,1998 Jakub Jelinek ([email protected])
* Copyright (C) 1995 Miguel de Icaza ([email protected])
*
* Driver layout based loosely on tgafb.c, see that file for credits.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/uaccess.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/fbio.h>
#include "sbuslib.h"
/*
* Local functions.
*/
static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
unsigned, struct fb_info *);
static int cg14_mmap(struct fb_info *, struct vm_area_struct *);
static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);
/*
* Frame buffer operations
*/
static const struct fb_ops cg14_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = cg14_setcolreg,
.fb_pan_display = cg14_pan_display,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = cg14_mmap,
.fb_ioctl = cg14_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = sbusfb_compat_ioctl,
#endif
};
#define CG14_MCR_INTENABLE_SHIFT 7
#define CG14_MCR_INTENABLE_MASK 0x80
#define CG14_MCR_VIDENABLE_SHIFT 6
#define CG14_MCR_VIDENABLE_MASK 0x40
#define CG14_MCR_PIXMODE_SHIFT 4
#define CG14_MCR_PIXMODE_MASK 0x30
#define CG14_MCR_TMR_SHIFT 2
#define CG14_MCR_TMR_MASK 0x0c
#define CG14_MCR_TMENABLE_SHIFT 1
#define CG14_MCR_TMENABLE_MASK 0x02
#define CG14_MCR_RESET_SHIFT 0
#define CG14_MCR_RESET_MASK 0x01
#define CG14_REV_REVISION_SHIFT 4
#define CG14_REV_REVISION_MASK 0xf0
#define CG14_REV_IMPL_SHIFT 0
#define CG14_REV_IMPL_MASK 0x0f
#define CG14_VBR_FRAMEBASE_SHIFT 12
#define CG14_VBR_FRAMEBASE_MASK 0x00fff000
#define CG14_VMCR1_SETUP_SHIFT 0
#define CG14_VMCR1_SETUP_MASK 0x000001ff
#define CG14_VMCR1_VCONFIG_SHIFT 9
#define CG14_VMCR1_VCONFIG_MASK 0x00000e00
#define CG14_VMCR2_REFRESH_SHIFT 0
#define CG14_VMCR2_REFRESH_MASK 0x00000001
#define CG14_VMCR2_TESTROWCNT_SHIFT 1
#define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
#define CG14_VMCR2_FBCONFIG_SHIFT 2
#define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
#define CG14_VCR_REFRESHREQ_SHIFT 0
#define CG14_VCR_REFRESHREQ_MASK 0x000003ff
#define CG14_VCR1_REFRESHENA_SHIFT 10
#define CG14_VCR1_REFRESHENA_MASK 0x00000400
#define CG14_VCA_CAD_SHIFT 0
#define CG14_VCA_CAD_MASK 0x000003ff
#define CG14_VCA_VERS_SHIFT 10
#define CG14_VCA_VERS_MASK 0x00000c00
#define CG14_VCA_RAMSPEED_SHIFT 12
#define CG14_VCA_RAMSPEED_MASK 0x00001000
#define CG14_VCA_8MB_SHIFT 13
#define CG14_VCA_8MB_MASK 0x00002000
#define CG14_MCR_PIXMODE_8 0
#define CG14_MCR_PIXMODE_16 2
#define CG14_MCR_PIXMODE_32 3
struct cg14_regs{
u8 mcr; /* Master Control Reg */
u8 ppr; /* Packed Pixel Reg */
u8 tms[2]; /* Test Mode Status Regs */
u8 msr; /* Master Status Reg */
u8 fsr; /* Fault Status Reg */
u8 rev; /* Revision & Impl */
u8 ccr; /* Clock Control Reg */
u32 tmr; /* Test Mode Read Back */
u8 mod; /* Monitor Operation Data Reg */
u8 acr; /* Aux Control */
u8 xxx0[6];
u16 hct; /* Hor Counter */
u16 vct; /* Vert Counter */
u16 hbs; /* Hor Blank Start */
u16 hbc; /* Hor Blank Clear */
u16 hss; /* Hor Sync Start */
u16 hsc; /* Hor Sync Clear */
u16 csc; /* Composite Sync Clear */
u16 vbs; /* Vert Blank Start */
u16 vbc; /* Vert Blank Clear */
u16 vss; /* Vert Sync Start */
u16 vsc; /* Vert Sync Clear */
u16 xcs;
u16 xcc;
u16 fsa; /* Fault Status Address */
u16 adr; /* Address Registers */
u8 xxx1[0xce];
u8 pcg[0x100]; /* Pixel Clock Generator */
u32 vbr; /* Frame Base Row */
u32 vmcr; /* VBC Master Control */
u32 vcr; /* VBC refresh */
u32 vca; /* VBC Config */
};
#define CG14_CCR_ENABLE 0x04
#define CG14_CCR_SELECT 0x02 /* HW/Full screen */
struct cg14_cursor {
u32 cpl0[32]; /* Enable plane 0 */
u32 cpl1[32]; /* Color selection plane */
u8 ccr; /* Cursor Control Reg */
u8 xxx0[3];
u16 cursx; /* Cursor x,y position */
u16 cursy; /* Cursor x,y position */
u32 color0;
u32 color1;
u32 xxx1[0x1bc];
u32 cpl0i[32]; /* Enable plane 0 autoinc */
u32 cpl1i[32]; /* Color selection autoinc */
};
struct cg14_dac {
u8 addr; /* Address Register */
u8 xxx0[255];
u8 glut; /* Gamma table */
u8 xxx1[255];
u8 select; /* Register Select */
u8 xxx2[255];
u8 mode; /* Mode Register */
};
struct cg14_xlut{
u8 x_xlut [256];
u8 x_xlutd [256];
u8 xxx0[0x600];
u8 x_xlut_inc [256];
u8 x_xlutd_inc [256];
};
/* Color look up table (clut) */
/* Each one of these arrays hold the color lookup table (for 256
* colors) for each MDI page (I assume then there should be 4 MDI
* pages, I still wonder what they are. I have seen NeXTStep split
* the screen in four parts, while operating in 24 bits mode. Each
* integer holds 4 values: alpha value (transparency channel, thanks
* go to John Stone ([email protected]) from OpenBSD), red, green and blue
*
* I currently use the clut instead of the Xlut
*/
struct cg14_clut {
u32 c_clut [256];
u32 c_clutd [256]; /* i wonder what the 'd' is for */
u32 c_clut_inc [256];
u32 c_clutd_inc [256];
};
#define CG14_MMAP_ENTRIES 16
struct cg14_par {
spinlock_t lock;
struct cg14_regs __iomem *regs;
struct cg14_clut __iomem *clut;
struct cg14_cursor __iomem *cursor;
u32 flags;
#define CG14_FLAG_BLANKED 0x00000001
unsigned long iospace;
struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
int mode;
int ramsize;
};
static void __cg14_reset(struct cg14_par *par)
{
struct cg14_regs __iomem *regs = par->regs;
u8 val;
val = sbus_readb(®s->mcr);
val &= ~(CG14_MCR_PIXMODE_MASK);
sbus_writeb(val, ®s->mcr);
}
static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct cg14_par *par = (struct cg14_par *) info->par;
unsigned long flags;
/* We just use this to catch switches out of
* graphics mode.
*/
spin_lock_irqsave(&par->lock, flags);
__cg14_reset(par);
spin_unlock_irqrestore(&par->lock, flags);
if (var->xoffset || var->yoffset || var->vmode)
return -EINVAL;
return 0;
}
/**
* cg14_setcolreg - Optional function. Sets a color register.
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*/
static int cg14_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct cg14_par *par = (struct cg14_par *) info->par;
struct cg14_clut __iomem *clut = par->clut;
unsigned long flags;
u32 val;
if (regno >= 256)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
val = (red | (green << 8) | (blue << 16));
spin_lock_irqsave(&par->lock, flags);
sbus_writel(val, &clut->c_clut[regno]);
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct cg14_par *par = (struct cg14_par *) info->par;
return sbusfb_mmap_helper(par->mmap_map,
info->fix.smem_start, info->fix.smem_len,
par->iospace, vma);
}
static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
struct cg14_par *par = (struct cg14_par *) info->par;
struct cg14_regs __iomem *regs = par->regs;
struct mdi_cfginfo kmdi, __user *mdii;
unsigned long flags;
int cur_mode, mode, ret = 0;
switch (cmd) {
case MDI_RESET:
spin_lock_irqsave(&par->lock, flags);
__cg14_reset(par);
spin_unlock_irqrestore(&par->lock, flags);
break;
case MDI_GET_CFGINFO:
memset(&kmdi, 0, sizeof(kmdi));
spin_lock_irqsave(&par->lock, flags);
kmdi.mdi_type = FBTYPE_MDICOLOR;
kmdi.mdi_height = info->var.yres;
kmdi.mdi_width = info->var.xres;
kmdi.mdi_mode = par->mode;
kmdi.mdi_pixfreq = 72; /* FIXME */
kmdi.mdi_size = par->ramsize;
spin_unlock_irqrestore(&par->lock, flags);
mdii = (struct mdi_cfginfo __user *) arg;
if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
ret = -EFAULT;
break;
case MDI_SET_PIXELMODE:
if (get_user(mode, (int __user *) arg)) {
ret = -EFAULT;
break;
}
spin_lock_irqsave(&par->lock, flags);
cur_mode = sbus_readb(®s->mcr);
cur_mode &= ~CG14_MCR_PIXMODE_MASK;
switch(mode) {
case MDI_32_PIX:
cur_mode |= (CG14_MCR_PIXMODE_32 <<
CG14_MCR_PIXMODE_SHIFT);
break;
case MDI_16_PIX:
cur_mode |= (CG14_MCR_PIXMODE_16 <<
CG14_MCR_PIXMODE_SHIFT);
break;
case MDI_8_PIX:
break;
default:
ret = -ENOSYS;
break;
}
if (!ret) {
sbus_writeb(cur_mode, ®s->mcr);
par->mode = mode;
}
spin_unlock_irqrestore(&par->lock, flags);
break;
default:
ret = sbusfb_ioctl_helper(cmd, arg, info,
FBTYPE_MDICOLOR, 8,
info->fix.smem_len);
break;
}
return ret;
}
/*
* Initialisation
*/
static void cg14_init_fix(struct fb_info *info, int linebytes,
struct device_node *dp)
{
snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = linebytes;
info->fix.accel = FB_ACCEL_SUN_CG14;
}
static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] = {
{
.voff = CG14_REGS,
.poff = 0x80000000,
.size = 0x1000
},
{
.voff = CG14_XLUT,
.poff = 0x80003000,
.size = 0x1000
},
{
.voff = CG14_CLUT1,
.poff = 0x80004000,
.size = 0x1000
},
{
.voff = CG14_CLUT2,
.poff = 0x80005000,
.size = 0x1000
},
{
.voff = CG14_CLUT3,
.poff = 0x80006000,
.size = 0x1000
},
{
.voff = CG3_MMAP_OFFSET - 0x7000,
.poff = 0x80000000,
.size = 0x7000
},
{
.voff = CG3_MMAP_OFFSET,
.poff = 0x00000000,
.size = SBUS_MMAP_FBSIZE(1)
},
{
.voff = MDI_CURSOR_MAP,
.poff = 0x80001000,
.size = 0x1000
},
{
.voff = MDI_CHUNKY_BGR_MAP,
.poff = 0x01000000,
.size = 0x400000
},
{
.voff = MDI_PLANAR_X16_MAP,
.poff = 0x02000000,
.size = 0x200000
},
{
.voff = MDI_PLANAR_C16_MAP,
.poff = 0x02800000,
.size = 0x200000
},
{
.voff = MDI_PLANAR_X32_MAP,
.poff = 0x03000000,
.size = 0x100000
},
{
.voff = MDI_PLANAR_B32_MAP,
.poff = 0x03400000,
.size = 0x100000
},
{
.voff = MDI_PLANAR_G32_MAP,
.poff = 0x03800000,
.size = 0x100000
},
{
.voff = MDI_PLANAR_R32_MAP,
.poff = 0x03c00000,
.size = 0x100000
},
{ .size = 0 }
};
static void cg14_unmap_regs(struct platform_device *op, struct fb_info *info,
struct cg14_par *par)
{
if (par->regs)
of_iounmap(&op->resource[0],
par->regs, sizeof(struct cg14_regs));
if (par->clut)
of_iounmap(&op->resource[0],
par->clut, sizeof(struct cg14_clut));
if (par->cursor)
of_iounmap(&op->resource[0],
par->cursor, sizeof(struct cg14_cursor));
if (info->screen_base)
of_iounmap(&op->resource[1],
info->screen_base, info->fix.smem_len);
}
static int cg14_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct fb_info *info;
struct cg14_par *par;
int is_8mb, linebytes, i, err;
info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);
err = -ENOMEM;
if (!info)
goto out_err;
par = info->par;
spin_lock_init(&par->lock);
sbusfb_fill_var(&info->var, dp, 8);
info->var.red.length = 8;
info->var.green.length = 8;
info->var.blue.length = 8;
linebytes = of_getintprop_default(dp, "linebytes",
info->var.xres);
info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
if (of_node_name_eq(dp->parent, "sbus") ||
of_node_name_eq(dp->parent, "sbi")) {
info->fix.smem_start = op->resource[0].start;
par->iospace = op->resource[0].flags & IORESOURCE_BITS;
} else {
info->fix.smem_start = op->resource[1].start;
par->iospace = op->resource[0].flags & IORESOURCE_BITS;
}
par->regs = of_ioremap(&op->resource[0], 0,
sizeof(struct cg14_regs), "cg14 regs");
par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
sizeof(struct cg14_clut), "cg14 clut");
par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
sizeof(struct cg14_cursor), "cg14 cursor");
info->screen_base = of_ioremap(&op->resource[1], 0,
info->fix.smem_len, "cg14 ram");
if (!par->regs || !par->clut || !par->cursor || !info->screen_base)
goto out_unmap_regs;
is_8mb = (resource_size(&op->resource[1]) == (8 * 1024 * 1024));
BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));
for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
struct sbus_mmap_map *map = &par->mmap_map[i];
if (!map->size)
break;
if (map->poff & 0x80000000)
map->poff = (map->poff & 0x7fffffff) +
(op->resource[0].start -
op->resource[1].start);
if (is_8mb &&
map->size >= 0x100000 &&
map->size <= 0x400000)
map->size *= 2;
}
par->mode = MDI_8_PIX;
par->ramsize = (is_8mb ? 0x800000 : 0x400000);
info->flags = FBINFO_HWACCEL_YPAN;
info->fbops = &cg14_ops;
__cg14_reset(par);
if (fb_alloc_cmap(&info->cmap, 256, 0))
goto out_unmap_regs;
fb_set_cmap(&info->cmap, info);
cg14_init_fix(info, linebytes, dp);
err = register_framebuffer(info);
if (err < 0)
goto out_dealloc_cmap;
dev_set_drvdata(&op->dev, info);
printk(KERN_INFO "%pOF: cgfourteen at %lx:%lx, %dMB\n",
dp,
par->iospace, info->fix.smem_start,
par->ramsize >> 20);
return 0;
out_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
out_unmap_regs:
cg14_unmap_regs(op, info, par);
framebuffer_release(info);
out_err:
return err;
}
static void cg14_remove(struct platform_device *op)
{
struct fb_info *info = dev_get_drvdata(&op->dev);
struct cg14_par *par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
cg14_unmap_regs(op, info, par);
framebuffer_release(info);
}
static const struct of_device_id cg14_match[] = {
{
.name = "cgfourteen",
},
{},
};
MODULE_DEVICE_TABLE(of, cg14_match);
static struct platform_driver cg14_driver = {
.driver = {
.name = "cg14",
.of_match_table = cg14_match,
},
.probe = cg14_probe,
.remove_new = cg14_remove,
};
static int __init cg14_init(void)
{
if (fb_get_options("cg14fb", NULL))
return -ENODEV;
return platform_driver_register(&cg14_driver);
}
static void __exit cg14_exit(void)
{
platform_driver_unregister(&cg14_driver);
}
module_init(cg14_init);
module_exit(cg14_exit);
MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/cg14.c |
/*
* linux/drivers/video/pmagb-b-fb.c
*
* PMAGB-B TURBOchannel Smart Frame Buffer (SFB) card support,
* derived from:
* "HP300 Topcat framebuffer support (derived from macfb of all things)
* Phil Blundell <[email protected]> 1998", the original code can be
* found in the file hpfb.c in the same directory.
*
* DECstation related code Copyright (C) 1999, 2000, 2001 by
* Michael Engel <[email protected]>,
* Karsten Merker <[email protected]> and
* Harald Koerfgen.
* Copyright (c) 2005, 2006 Maciej W. Rozycki
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*/
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/tc.h>
#include <linux/types.h>
#include <asm/io.h>
#include <video/pmagb-b-fb.h>
struct pmagbbfb_par {
volatile void __iomem *mmio;
volatile void __iomem *smem;
volatile u32 __iomem *sfb;
volatile u32 __iomem *dac;
unsigned int osc0;
unsigned int osc1;
int slot;
};
static const struct fb_var_screeninfo pmagbbfb_defined = {
.bits_per_pixel = 8,
.red.length = 8,
.green.length = 8,
.blue.length = 8,
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.accel_flags = FB_ACCEL_NONE,
.sync = FB_SYNC_ON_GREEN,
.vmode = FB_VMODE_NONINTERLACED,
};
static const struct fb_fix_screeninfo pmagbbfb_fix = {
.id = "PMAGB-BA",
.smem_len = (2048 * 1024),
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.mmio_len = PMAGB_B_FBMEM,
};
static inline void sfb_write(struct pmagbbfb_par *par, unsigned int reg, u32 v)
{
writel(v, par->sfb + reg / 4);
}
static inline u32 sfb_read(struct pmagbbfb_par *par, unsigned int reg)
{
return readl(par->sfb + reg / 4);
}
static inline void dac_write(struct pmagbbfb_par *par, unsigned int reg, u8 v)
{
writeb(v, par->dac + reg / 4);
}
static inline u8 dac_read(struct pmagbbfb_par *par, unsigned int reg)
{
return readb(par->dac + reg / 4);
}
static inline void gp0_write(struct pmagbbfb_par *par, u32 v)
{
writel(v, par->mmio + PMAGB_B_GP0);
}
/*
* Set the palette.
*/
static int pmagbbfb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
struct pmagbbfb_par *par = info->par;
if (regno >= info->cmap.len)
return 1;
red >>= 8; /* The cmap fields are 16 bits */
green >>= 8; /* wide, but the hardware colormap */
blue >>= 8; /* registers are only 8 bits wide */
mb();
dac_write(par, BT459_ADDR_LO, regno);
dac_write(par, BT459_ADDR_HI, 0x00);
wmb();
dac_write(par, BT459_CMAP, red);
wmb();
dac_write(par, BT459_CMAP, green);
wmb();
dac_write(par, BT459_CMAP, blue);
return 0;
}
static const struct fb_ops pmagbbfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = pmagbbfb_setcolreg,
};
/*
* Turn the hardware cursor off.
*/
static void pmagbbfb_erase_cursor(struct fb_info *info)
{
struct pmagbbfb_par *par = info->par;
mb();
dac_write(par, BT459_ADDR_LO, 0x00);
dac_write(par, BT459_ADDR_HI, 0x03);
wmb();
dac_write(par, BT459_DATA, 0x00);
}
/*
* Set up screen parameters.
*/
static void pmagbbfb_screen_setup(struct fb_info *info)
{
struct pmagbbfb_par *par = info->par;
info->var.xres = ((sfb_read(par, SFB_REG_VID_HOR) >>
SFB_VID_HOR_PIX_SHIFT) & SFB_VID_HOR_PIX_MASK) * 4;
info->var.xres_virtual = info->var.xres;
info->var.yres = (sfb_read(par, SFB_REG_VID_VER) >>
SFB_VID_VER_SL_SHIFT) & SFB_VID_VER_SL_MASK;
info->var.yres_virtual = info->var.yres;
info->var.left_margin = ((sfb_read(par, SFB_REG_VID_HOR) >>
SFB_VID_HOR_BP_SHIFT) &
SFB_VID_HOR_BP_MASK) * 4;
info->var.right_margin = ((sfb_read(par, SFB_REG_VID_HOR) >>
SFB_VID_HOR_FP_SHIFT) &
SFB_VID_HOR_FP_MASK) * 4;
info->var.upper_margin = (sfb_read(par, SFB_REG_VID_VER) >>
SFB_VID_VER_BP_SHIFT) & SFB_VID_VER_BP_MASK;
info->var.lower_margin = (sfb_read(par, SFB_REG_VID_VER) >>
SFB_VID_VER_FP_SHIFT) & SFB_VID_VER_FP_MASK;
info->var.hsync_len = ((sfb_read(par, SFB_REG_VID_HOR) >>
SFB_VID_HOR_SYN_SHIFT) &
SFB_VID_HOR_SYN_MASK) * 4;
info->var.vsync_len = (sfb_read(par, SFB_REG_VID_VER) >>
SFB_VID_VER_SYN_SHIFT) & SFB_VID_VER_SYN_MASK;
info->fix.line_length = info->var.xres;
};
/*
* Determine oscillator configuration.
*/
static void pmagbbfb_osc_setup(struct fb_info *info)
{
static unsigned int pmagbbfb_freqs[] = {
130808, 119843, 104000, 92980, 74370, 72800,
69197, 66000, 65000, 50350, 36000, 32000, 25175
};
struct pmagbbfb_par *par = info->par;
struct tc_bus *tbus = to_tc_dev(info->device)->bus;
u32 count0 = 8, count1 = 8, counttc = 16 * 256 + 8;
u32 freq0, freq1, freqtc = tc_get_speed(tbus) / 250;
int i, j;
gp0_write(par, 0); /* select Osc0 */
for (j = 0; j < 16; j++) {
mb();
sfb_write(par, SFB_REG_TCCLK_COUNT, 0);
mb();
for (i = 0; i < 100; i++) { /* nominally max. 20.5us */
if (sfb_read(par, SFB_REG_TCCLK_COUNT) == 0)
break;
udelay(1);
}
count0 += sfb_read(par, SFB_REG_VIDCLK_COUNT);
}
gp0_write(par, 1); /* select Osc1 */
for (j = 0; j < 16; j++) {
mb();
sfb_write(par, SFB_REG_TCCLK_COUNT, 0);
for (i = 0; i < 100; i++) { /* nominally max. 20.5us */
if (sfb_read(par, SFB_REG_TCCLK_COUNT) == 0)
break;
udelay(1);
}
count1 += sfb_read(par, SFB_REG_VIDCLK_COUNT);
}
freq0 = (freqtc * count0 + counttc / 2) / counttc;
par->osc0 = freq0;
if (freq0 >= pmagbbfb_freqs[0] - (pmagbbfb_freqs[0] + 32) / 64 &&
freq0 <= pmagbbfb_freqs[0] + (pmagbbfb_freqs[0] + 32) / 64)
par->osc0 = pmagbbfb_freqs[0];
freq1 = (par->osc0 * count1 + count0 / 2) / count0;
par->osc1 = freq1;
for (i = 0; i < ARRAY_SIZE(pmagbbfb_freqs); i++)
if (freq1 >= pmagbbfb_freqs[i] -
(pmagbbfb_freqs[i] + 128) / 256 &&
freq1 <= pmagbbfb_freqs[i] +
(pmagbbfb_freqs[i] + 128) / 256) {
par->osc1 = pmagbbfb_freqs[i];
break;
}
if (par->osc0 - par->osc1 <= (par->osc0 + par->osc1 + 256) / 512 ||
par->osc1 - par->osc0 <= (par->osc0 + par->osc1 + 256) / 512)
par->osc1 = 0;
gp0_write(par, par->osc1 != 0); /* reselect OscX */
info->var.pixclock = par->osc1 ?
(1000000000 + par->osc1 / 2) / par->osc1 :
(1000000000 + par->osc0 / 2) / par->osc0;
};
static int pmagbbfb_probe(struct device *dev)
{
struct tc_dev *tdev = to_tc_dev(dev);
resource_size_t start, len;
struct fb_info *info;
struct pmagbbfb_par *par;
char freq0[12], freq1[12];
u32 vid_base;
int err;
info = framebuffer_alloc(sizeof(struct pmagbbfb_par), dev);
if (!info)
return -ENOMEM;
par = info->par;
dev_set_drvdata(dev, info);
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
printk(KERN_ERR "%s: Cannot allocate color map\n",
dev_name(dev));
err = -ENOMEM;
goto err_alloc;
}
info->fbops = &pmagbbfb_ops;
info->fix = pmagbbfb_fix;
info->var = pmagbbfb_defined;
/* Request the I/O MEM resource. */
start = tdev->resource.start;
len = tdev->resource.end - start + 1;
if (!request_mem_region(start, len, dev_name(dev))) {
printk(KERN_ERR "%s: Cannot reserve FB region\n",
dev_name(dev));
err = -EBUSY;
goto err_cmap;
}
/* MMIO mapping setup. */
info->fix.mmio_start = start;
par->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
if (!par->mmio) {
printk(KERN_ERR "%s: Cannot map MMIO\n", dev_name(dev));
err = -ENOMEM;
goto err_resource;
}
par->sfb = par->mmio + PMAGB_B_SFB;
par->dac = par->mmio + PMAGB_B_BT459;
/* Frame buffer mapping setup. */
info->fix.smem_start = start + PMAGB_B_FBMEM;
par->smem = ioremap(info->fix.smem_start, info->fix.smem_len);
if (!par->smem) {
printk(KERN_ERR "%s: Cannot map FB\n", dev_name(dev));
err = -ENOMEM;
goto err_mmio_map;
}
vid_base = sfb_read(par, SFB_REG_VID_BASE);
info->screen_base = (void __iomem *)par->smem + vid_base * 0x1000;
info->screen_size = info->fix.smem_len - 2 * vid_base * 0x1000;
pmagbbfb_erase_cursor(info);
pmagbbfb_screen_setup(info);
pmagbbfb_osc_setup(info);
err = register_framebuffer(info);
if (err < 0) {
printk(KERN_ERR "%s: Cannot register framebuffer\n",
dev_name(dev));
goto err_smem_map;
}
get_device(dev);
snprintf(freq0, sizeof(freq0), "%u.%03uMHz",
par->osc0 / 1000, par->osc0 % 1000);
snprintf(freq1, sizeof(freq1), "%u.%03uMHz",
par->osc1 / 1000, par->osc1 % 1000);
fb_info(info, "%s frame buffer device at %s\n",
info->fix.id, dev_name(dev));
fb_info(info, "Osc0: %s, Osc1: %s, Osc%u selected\n",
freq0, par->osc1 ? freq1 : "disabled", par->osc1 != 0);
return 0;
err_smem_map:
iounmap(par->smem);
err_mmio_map:
iounmap(par->mmio);
err_resource:
release_mem_region(start, len);
err_cmap:
fb_dealloc_cmap(&info->cmap);
err_alloc:
framebuffer_release(info);
return err;
}
static int pmagbbfb_remove(struct device *dev)
{
struct tc_dev *tdev = to_tc_dev(dev);
struct fb_info *info = dev_get_drvdata(dev);
struct pmagbbfb_par *par = info->par;
resource_size_t start, len;
put_device(dev);
unregister_framebuffer(info);
iounmap(par->smem);
iounmap(par->mmio);
start = tdev->resource.start;
len = tdev->resource.end - start + 1;
release_mem_region(start, len);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
return 0;
}
/*
* Initialize the framebuffer.
*/
static const struct tc_device_id pmagbbfb_tc_table[] = {
{ "DEC ", "PMAGB-BA" },
{ }
};
MODULE_DEVICE_TABLE(tc, pmagbbfb_tc_table);
static struct tc_driver pmagbbfb_driver = {
.id_table = pmagbbfb_tc_table,
.driver = {
.name = "pmagbbfb",
.bus = &tc_bus_type,
.probe = pmagbbfb_probe,
.remove = pmagbbfb_remove,
},
};
static int __init pmagbbfb_init(void)
{
#ifndef MODULE
if (fb_get_options("pmagbbfb", NULL))
return -ENXIO;
#endif
return tc_register_driver(&pmagbbfb_driver);
}
static void __exit pmagbbfb_exit(void)
{
tc_unregister_driver(&pmagbbfb_driver);
}
module_init(pmagbbfb_init);
module_exit(pmagbbfb_exit);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/pmagb-b-fb.c |
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/amigahw.h>
#include <asm/amigaints.h>
#include <asm/apollohw.h>
#include <linux/fb.h>
#include <linux/module.h>
/* apollo video HW definitions */
/*
* Control Registers. IOBASE + $x
*
* Note: these are the Memory/IO BASE definitions for a mono card set to the
* alternate address
*
* Control 3A and 3B serve identical functions except that 3A
* deals with control 1 and 3b deals with Color LUT reg.
*/
#define AP_IOBASE 0x3b0 /* Base address of 1 plane board. */
#define AP_STATUS isaIO2mem(AP_IOBASE+0) /* Status register. Read */
#define AP_WRITE_ENABLE isaIO2mem(AP_IOBASE+0) /* Write Enable Register Write */
#define AP_DEVICE_ID isaIO2mem(AP_IOBASE+1) /* Device ID Register. Read */
#define AP_ROP_1 isaIO2mem(AP_IOBASE+2) /* Raster Operation reg. Write Word */
#define AP_DIAG_MEM_REQ isaIO2mem(AP_IOBASE+4) /* Diagnostic Memory Request. Write Word */
#define AP_CONTROL_0 isaIO2mem(AP_IOBASE+8) /* Control Register 0. Read/Write */
#define AP_CONTROL_1 isaIO2mem(AP_IOBASE+0xa) /* Control Register 1. Read/Write */
#define AP_CONTROL_3A isaIO2mem(AP_IOBASE+0xe) /* Control Register 3a. Read/Write */
#define AP_CONTROL_2 isaIO2mem(AP_IOBASE+0xc) /* Control Register 2. Read/Write */
#define FRAME_BUFFER_START 0x0FA0000
#define FRAME_BUFFER_LEN 0x40000
/* CREG 0 */
#define VECTOR_MODE 0x40 /* 010x.xxxx */
#define DBLT_MODE 0x80 /* 100x.xxxx */
#define NORMAL_MODE 0xE0 /* 111x.xxxx */
#define SHIFT_BITS 0x1F /* xxx1.1111 */
/* other bits are Shift value */
/* CREG 1 */
#define AD_BLT 0x80 /* 1xxx.xxxx */
#define NORMAL 0x80 /* 1xxx.xxxx */ /* What is happening here ?? */
#define INVERSE 0x00 /* 0xxx.xxxx */ /* Clearing this reverses the screen */
#define PIX_BLT 0x00 /* 0xxx.xxxx */
#define AD_HIBIT 0x40 /* xIxx.xxxx */
#define ROP_EN 0x10 /* xxx1.xxxx */
#define DST_EQ_SRC 0x00 /* xxx0.xxxx */
#define nRESET_SYNC 0x08 /* xxxx.1xxx */
#define SYNC_ENAB 0x02 /* xxxx.xx1x */
#define BLANK_DISP 0x00 /* xxxx.xxx0 */
#define ENAB_DISP 0x01 /* xxxx.xxx1 */
#define NORM_CREG1 (nRESET_SYNC | SYNC_ENAB | ENAB_DISP) /* no reset sync */
/* CREG 2 */
/*
* Following 3 defines are common to 1, 4 and 8 plane.
*/
#define S_DATA_1s 0x00 /* 00xx.xxxx */ /* set source to all 1's -- vector drawing */
#define S_DATA_PIX 0x40 /* 01xx.xxxx */ /* takes source from ls-bits and replicates over 16 bits */
#define S_DATA_PLN 0xC0 /* 11xx.xxxx */ /* normal, each data access =16-bits in
one plane of image mem */
/* CREG 3A/CREG 3B */
# define RESET_CREG 0x80 /* 1000.0000 */
/* ROP REG - all one nibble */
/* ********* NOTE : this is used r0,r1,r2,r3 *********** */
#define ROP(r2,r3,r0,r1) ( (U_SHORT)((r0)|((r1)<<4)|((r2)<<8)|((r3)<<12)) )
#define DEST_ZERO 0x0
#define SRC_AND_DEST 0x1
#define SRC_AND_nDEST 0x2
#define SRC 0x3
#define nSRC_AND_DEST 0x4
#define DEST 0x5
#define SRC_XOR_DEST 0x6
#define SRC_OR_DEST 0x7
#define SRC_NOR_DEST 0x8
#define SRC_XNOR_DEST 0x9
#define nDEST 0xA
#define SRC_OR_nDEST 0xB
#define nSRC 0xC
#define nSRC_OR_DEST 0xD
#define SRC_NAND_DEST 0xE
#define DEST_ONE 0xF
#define SWAP(A) ((A>>8) | ((A&0xff) <<8))
/* frame buffer operations */
static int dnfb_blank(int blank, struct fb_info *info);
static void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
static const struct fb_ops dn_fb_ops = {
.owner = THIS_MODULE,
.fb_blank = dnfb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = dnfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static const struct fb_var_screeninfo dnfb_var = {
.xres = 1280,
.yres = 1024,
.xres_virtual = 2048,
.yres_virtual = 1024,
.bits_per_pixel = 1,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
};
static const struct fb_fix_screeninfo dnfb_fix = {
.id = "Apollo Mono",
.smem_start = (FRAME_BUFFER_START + IO_BASE),
.smem_len = FRAME_BUFFER_LEN,
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_MONO10,
.line_length = 256,
};
static int dnfb_blank(int blank, struct fb_info *info)
{
if (blank)
out_8(AP_CONTROL_3A, 0x0);
else
out_8(AP_CONTROL_3A, 0x1);
return 0;
}
static
void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
int incr, y_delta, pre_read = 0, x_end, x_word_count;
uint start_mask, end_mask, dest;
ushort *src, dummy;
short i, j;
incr = (area->dy <= area->sy) ? 1 : -1;
src = (ushort *)(info->screen_base + area->sy * info->fix.line_length +
(area->sx >> 4));
dest = area->dy * (info->fix.line_length >> 1) + (area->dx >> 4);
if (incr > 0) {
y_delta = (info->fix.line_length * 8) - area->sx - area->width;
x_end = area->dx + area->width - 1;
x_word_count = (x_end >> 4) - (area->dx >> 4) + 1;
start_mask = 0xffff0000 >> (area->dx & 0xf);
end_mask = 0x7ffff >> (x_end & 0xf);
out_8(AP_CONTROL_0,
(((area->dx & 0xf) - (area->sx & 0xf)) % 16) | (0x4 << 5));
if ((area->dx & 0xf) < (area->sx & 0xf))
pre_read = 1;
} else {
y_delta = -((info->fix.line_length * 8) - area->sx - area->width);
x_end = area->dx - area->width + 1;
x_word_count = (area->dx >> 4) - (x_end >> 4) + 1;
start_mask = 0x7ffff >> (area->dx & 0xf);
end_mask = 0xffff0000 >> (x_end & 0xf);
out_8(AP_CONTROL_0,
((-((area->sx & 0xf) - (area->dx & 0xf))) % 16) |
(0x4 << 5));
if ((area->dx & 0xf) > (area->sx & 0xf))
pre_read = 1;
}
for (i = 0; i < area->height; i++) {
out_8(AP_CONTROL_3A, 0xc | (dest >> 16));
if (pre_read) {
dummy = *src;
src += incr;
}
if (x_word_count) {
out_8(AP_WRITE_ENABLE, start_mask);
*src = dest;
src += incr;
dest += incr;
out_8(AP_WRITE_ENABLE, 0);
for (j = 1; j < (x_word_count - 1); j++) {
*src = dest;
src += incr;
dest += incr;
}
out_8(AP_WRITE_ENABLE, start_mask);
*src = dest;
dest += incr;
src += incr;
} else {
out_8(AP_WRITE_ENABLE, start_mask | end_mask);
*src = dest;
dest += incr;
src += incr;
}
src += (y_delta / 16);
dest += (y_delta / 16);
}
out_8(AP_CONTROL_0, NORMAL_MODE);
}
/*
* Initialization
*/
static int dnfb_probe(struct platform_device *dev)
{
struct fb_info *info;
int err = 0;
info = framebuffer_alloc(0, &dev->dev);
if (!info)
return -ENOMEM;
info->fbops = &dn_fb_ops;
info->fix = dnfb_fix;
info->var = dnfb_var;
info->var.red.length = 1;
info->var.red.offset = 0;
info->var.green = info->var.blue = info->var.red;
info->screen_base = (u_char *) info->fix.smem_start;
err = fb_alloc_cmap(&info->cmap, 2, 0);
if (err < 0)
goto release_framebuffer;
err = register_framebuffer(info);
if (err < 0) {
fb_dealloc_cmap(&info->cmap);
goto release_framebuffer;
}
platform_set_drvdata(dev, info);
/* now we have registered we can safely setup the hardware */
out_8(AP_CONTROL_3A, RESET_CREG);
out_be16(AP_WRITE_ENABLE, 0x0);
out_8(AP_CONTROL_0, NORMAL_MODE);
out_8(AP_CONTROL_1, (AD_BLT | DST_EQ_SRC | NORM_CREG1));
out_8(AP_CONTROL_2, S_DATA_PLN);
out_be16(AP_ROP_1, SWAP(0x3));
printk("apollo frame buffer alive and kicking !\n");
return err;
release_framebuffer:
framebuffer_release(info);
return err;
}
static struct platform_driver dnfb_driver = {
.probe = dnfb_probe,
.driver = {
.name = "dnfb",
},
};
static struct platform_device dnfb_device = {
.name = "dnfb",
};
static int __init dnfb_init(void)
{
int ret;
if (!MACH_IS_APOLLO)
return -ENODEV;
if (fb_get_options("dnfb", NULL))
return -ENODEV;
ret = platform_driver_register(&dnfb_driver);
if (!ret) {
ret = platform_device_register(&dnfb_device);
if (ret)
platform_driver_unregister(&dnfb_driver);
}
return ret;
}
module_init(dnfb_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/dnfb.c |
/*
* Permedia2 framebuffer driver.
*
* 2.5/2.6 driver:
* Copyright (c) 2003 Jim Hague ([email protected])
*
* based on 2.4 driver:
* Copyright (c) 1998-2000 Ilario Nardinocchi ([email protected])
* Copyright (c) 1999 Jakub Jelinek ([email protected])
*
* and additional input from James Simmon's port of Hannu Mallat's tdfx
* driver.
*
* I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
* have no access to other pm2fb implementations. Sparc (and thus
* hopefully other big-endian) devices now work, thanks to a lot of
* testing work by Ron Murray. I have no access to CVision hardware,
* and therefore for now I am omitting the CVision code.
*
* Multiple boards support has been on the TODO list for ages.
* Don't expect this to change.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <video/permedia2.h>
#include <video/cvisionppc.h>
#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
#error "The endianness of the target host has not been defined."
#endif
#if !defined(CONFIG_PCI)
#error "Only generic PCI cards supported."
#endif
#undef PM2FB_MASTER_DEBUG
#ifdef PM2FB_MASTER_DEBUG
#define DPRINTK(a, b...) \
printk(KERN_DEBUG "pm2fb: %s: " a, __func__ , ## b)
#else
#define DPRINTK(a, b...) no_printk(a, ##b)
#endif
#define PM2_PIXMAP_SIZE (1600 * 4)
/*
* Driver data
*/
static int hwcursor = 1;
static char *mode_option;
/*
* The XFree GLINT driver will (I think to implement hardware cursor
* support on TVP4010 and similar where there is no RAMDAC - see
* comment in set_video) always request +ve sync regardless of what
* the mode requires. This screws me because I have a Sun
* fixed-frequency monitor which absolutely has to have -ve sync. So
* these flags allow the user to specify that requests for +ve sync
* should be silently turned in -ve sync.
*/
static bool lowhsync;
static bool lowvsync;
static bool noaccel;
static bool nomtrr;
/*
* The hardware state of the graphics card that isn't part of the
* screeninfo.
*/
struct pm2fb_par
{
pm2type_t type; /* Board type */
unsigned char __iomem *v_regs;/* virtual address of p_regs */
u32 memclock; /* memclock */
u32 video; /* video flags before blanking */
u32 mem_config; /* MemConfig reg at probe */
u32 mem_control; /* MemControl reg at probe */
u32 boot_address; /* BootAddress reg at probe */
u32 palette[16];
int wc_cookie;
};
/*
* Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
* if we don't use modedb.
*/
static struct fb_fix_screeninfo pm2fb_fix = {
.id = "",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 1,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_3DLABS_PERMEDIA2,
};
/*
* Default video mode. In case the modedb doesn't work.
*/
static const struct fb_var_screeninfo pm2fb_var = {
/* "640x480, 8 bpp @ 60 Hz */
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel = 8,
.red = {0, 8, 0},
.blue = {0, 8, 0},
.green = {0, 8, 0},
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.accel_flags = 0,
.pixclock = 39721,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* Utility functions
*/
static inline u32 pm2_RD(struct pm2fb_par *p, s32 off)
{
return fb_readl(p->v_regs + off);
}
static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v)
{
fb_writel(v, p->v_regs + off);
}
static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx)
{
pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
mb();
return pm2_RD(p, PM2R_RD_INDEXED_DATA);
}
static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx)
{
pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
mb();
return pm2_RD(p, PM2VR_RD_INDEXED_DATA);
}
static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
{
pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
wmb();
pm2_WR(p, PM2R_RD_INDEXED_DATA, v);
wmb();
}
static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
{
pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
wmb();
pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
wmb();
}
#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
#define WAIT_FIFO(p, a)
#else
static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a)
{
while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a)
cpu_relax();
}
#endif
/*
* partial products for the supported horizontal resolutions.
*/
#define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
static const struct {
u16 width;
u16 pp;
} pp_table[] = {
{ 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
{ 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
{ 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
{ 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
{ 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
{ 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
{ 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
{ 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
{ 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
{ 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
{ 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
{ 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
{ 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
{ 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
{ 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
{ 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
{ 0, 0 } };
static u32 partprod(u32 xres)
{
int i;
for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
;
if (pp_table[i].width == 0)
DPRINTK("invalid width %u\n", xres);
return pp_table[i].pp;
}
static u32 to3264(u32 timing, int bpp, int is64)
{
switch (bpp) {
case 24:
timing *= 3;
fallthrough;
case 8:
timing >>= 1;
fallthrough;
case 16:
timing >>= 1;
fallthrough;
case 32:
break;
}
if (is64)
timing >>= 1;
return timing;
}
static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
unsigned char *pp)
{
unsigned char m;
unsigned char n;
unsigned char p;
u32 f;
s32 curr;
s32 delta = 100000;
*mm = *nn = *pp = 0;
for (n = 2; n < 15; n++) {
for (m = 2; m; m++) {
f = PM2_REFERENCE_CLOCK * m / n;
if (f >= 150000 && f <= 300000) {
for (p = 0; p < 5; p++, f >>= 1) {
curr = (clk > f) ? clk - f : f - clk;
if (curr < delta) {
delta = curr;
*mm = m;
*nn = n;
*pp = p;
}
}
}
}
}
}
static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
unsigned char *pp)
{
unsigned char m;
unsigned char n;
unsigned char p;
u32 f;
s32 delta = 1000;
*mm = *nn = *pp = 0;
for (m = 1; m < 128; m++) {
for (n = 2 * m + 1; n; n++) {
for (p = 0; p < 2; p++) {
f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m;
if (clk > f - delta && clk < f + delta) {
delta = (clk > f) ? clk - f : f - clk;
*mm = m;
*nn = n;
*pp = p;
}
}
}
}
}
static void clear_palette(struct pm2fb_par *p)
{
int i = 256;
WAIT_FIFO(p, 1);
pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
wmb();
while (i--) {
WAIT_FIFO(p, 3);
pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
}
}
static void reset_card(struct pm2fb_par *p)
{
if (p->type == PM2_TYPE_PERMEDIA2V)
pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
pm2_WR(p, PM2R_RESET_STATUS, 0);
mb();
while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
cpu_relax();
mb();
#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
DPRINTK("FIFO disconnect enabled\n");
pm2_WR(p, PM2R_FIFO_DISCON, 1);
mb();
#endif
/* Restore stashed memory config information from probe */
WAIT_FIFO(p, 3);
pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
wmb();
pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
}
static void reset_config(struct pm2fb_par *p)
{
WAIT_FIFO(p, 53);
pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
pm2_WR(p, PM2R_FIFO_CONTROL, 0);
pm2_WR(p, PM2R_APERTURE_ONE, 0);
pm2_WR(p, PM2R_APERTURE_TWO, 0);
pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
pm2_WR(p, PM2R_LB_READ_MODE, 0);
pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
pm2_WR(p, PM2R_DITHER_MODE, 0);
pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
pm2_WR(p, PM2R_DEPTH_MODE, 0);
pm2_WR(p, PM2R_STENCIL_MODE, 0);
pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
pm2_WR(p, PM2R_YUV_MODE, 0);
pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
pm2_WR(p, PM2R_FOG_MODE, 0);
pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
pm2_WR(p, PM2R_STATISTICS_MODE, 0);
pm2_WR(p, PM2R_SCISSOR_MODE, 0);
pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
switch (p->type) {
case PM2_TYPE_PERMEDIA2:
pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
break;
case PM2_TYPE_PERMEDIA2V:
pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
break;
}
}
static void set_aperture(struct pm2fb_par *p, u32 depth)
{
/*
* The hardware is little-endian. When used in big-endian
* hosts, the on-chip aperture settings are used where
* possible to translate from host to card byte order.
*/
WAIT_FIFO(p, 2);
#ifdef __LITTLE_ENDIAN
pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
#else
switch (depth) {
case 24: /* RGB->BGR */
/*
* We can't use the aperture to translate host to
* card byte order here, so we switch to BGR mode
* in pm2fb_set_par().
*/
case 8: /* B->B */
pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
break;
case 16: /* HL->LH */
pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
break;
case 32: /* RGBA->ABGR */
pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
break;
}
#endif
/* We don't use aperture two, so this may be superflous */
pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
}
static void set_color(struct pm2fb_par *p, unsigned char regno,
unsigned char r, unsigned char g, unsigned char b)
{
WAIT_FIFO(p, 4);
pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
wmb();
pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
wmb();
pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
wmb();
pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
}
static void set_memclock(struct pm2fb_par *par, u32 clk)
{
int i;
unsigned char m, n, p;
switch (par->type) {
case PM2_TYPE_PERMEDIA2V:
pm2v_mnp(clk/2, &m, &n, &p);
WAIT_FIFO(par, 12);
pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
rmb();
for (i = 256; i; i--)
if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2)
break;
pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
break;
case PM2_TYPE_PERMEDIA2:
pm2_mnp(clk, &m, &n, &p);
WAIT_FIFO(par, 10);
pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
rmb();
for (i = 256; i; i--)
if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
break;
break;
}
}
static void set_pixclock(struct pm2fb_par *par, u32 clk)
{
int i;
unsigned char m, n, p;
switch (par->type) {
case PM2_TYPE_PERMEDIA2:
pm2_mnp(clk, &m, &n, &p);
WAIT_FIFO(par, 10);
pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
rmb();
for (i = 256; i; i--)
if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
break;
break;
case PM2_TYPE_PERMEDIA2V:
pm2v_mnp(clk/2, &m, &n, &p);
WAIT_FIFO(par, 8);
pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
break;
}
}
static void set_video(struct pm2fb_par *p, u32 video)
{
u32 tmp;
u32 vsync = video;
DPRINTK("video = 0x%x\n", video);
/*
* The hardware cursor needs +vsync to recognise vert retrace.
* We may not be using the hardware cursor, but the X Glint
* driver may well. So always set +hsync/+vsync and then set
* the RAMDAC to invert the sync if necessary.
*/
vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
WAIT_FIFO(p, 3);
pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
switch (p->type) {
case PM2_TYPE_PERMEDIA2:
tmp = PM2F_RD_PALETTE_WIDTH_8;
if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
tmp |= 4; /* invert hsync */
if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
tmp |= 8; /* invert vsync */
pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
break;
case PM2_TYPE_PERMEDIA2V:
tmp = 0;
if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
tmp |= 1; /* invert hsync */
if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
tmp |= 4; /* invert vsync */
pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
break;
}
}
/*
* pm2fb_check_var - Optional function. Validates a var passed in.
* @var: frame buffer variable screen structure
* @info: frame buffer structure that represents a single frame buffer
*
* Checks to see if the hardware supports the state requested by
* var passed in.
*
* Returns negative errno on error, or zero on success.
*/
static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
u32 lpitch;
if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
return -EINVAL;
}
if (var->xres != var->xres_virtual) {
DPRINTK("virtual x resolution != "
"physical x resolution not supported\n");
return -EINVAL;
}
if (var->yres > var->yres_virtual) {
DPRINTK("virtual y resolution < "
"physical y resolution not possible\n");
return -EINVAL;
}
/* permedia cannot blit over 2048 */
if (var->yres_virtual > 2047) {
var->yres_virtual = 2047;
}
if (var->xoffset) {
DPRINTK("xoffset not supported\n");
return -EINVAL;
}
if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
DPRINTK("interlace not supported\n");
return -EINVAL;
}
var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
if (var->xres < 320 || var->xres > 1600) {
DPRINTK("width not supported: %u\n", var->xres);
return -EINVAL;
}
if (var->yres < 200 || var->yres > 1200) {
DPRINTK("height not supported: %u\n", var->yres);
return -EINVAL;
}
if (lpitch * var->yres_virtual > info->fix.smem_len) {
DPRINTK("no memory for screen (%ux%ux%u)\n",
var->xres, var->yres_virtual, var->bits_per_pixel);
return -EINVAL;
}
if (!var->pixclock) {
DPRINTK("pixclock is zero\n");
return -EINVAL;
}
if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
DPRINTK("pixclock too high (%ldKHz)\n",
PICOS2KHZ(var->pixclock));
return -EINVAL;
}
var->transp.offset = 0;
var->transp.length = 0;
switch (var->bits_per_pixel) {
case 8:
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
case 16:
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
break;
case 32:
var->transp.offset = 24;
var->transp.length = 8;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
case 24:
#ifdef __BIG_ENDIAN
var->red.offset = 0;
var->blue.offset = 16;
#else
var->red.offset = 16;
var->blue.offset = 0;
#endif
var->green.offset = 8;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
}
var->height = -1;
var->width = -1;
var->accel_flags = 0; /* Can't mmap if this is on */
DPRINTK("Checking graphics mode at %dx%d depth %d\n",
var->xres, var->yres, var->bits_per_pixel);
return 0;
}
/**
* pm2fb_set_par - Alters the hardware state.
* @info: frame buffer structure that represents a single frame buffer
*
* Using the fb_var_screeninfo in fb_info we set the resolution of the
* this particular framebuffer.
*/
static int pm2fb_set_par(struct fb_info *info)
{
struct pm2fb_par *par = info->par;
u32 pixclock;
u32 width = (info->var.xres_virtual + 7) & ~7;
u32 height = info->var.yres_virtual;
u32 depth = (info->var.bits_per_pixel + 7) & ~7;
u32 hsstart, hsend, hbend, htotal;
u32 vsstart, vsend, vbend, vtotal;
u32 stride;
u32 base;
u32 video = 0;
u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
u32 txtmap = 0;
u32 pixsize = 0;
u32 clrformat = 0;
u32 misc = 1; /* 8-bit DAC */
u32 xres = (info->var.xres + 31) & ~31;
int data64;
reset_card(par);
reset_config(par);
clear_palette(par);
if (par->memclock)
set_memclock(par, par->memclock);
depth = (depth > 32) ? 32 : depth;
data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
pixclock = PICOS2KHZ(info->var.pixclock);
if (pixclock > PM2_MAX_PIXCLOCK) {
DPRINTK("pixclock too high (%uKHz)\n", pixclock);
return -EINVAL;
}
hsstart = to3264(info->var.right_margin, depth, data64);
hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
hbend = hsend + to3264(info->var.left_margin, depth, data64);
htotal = to3264(xres, depth, data64) + hbend - 1;
vsstart = (info->var.lower_margin)
? info->var.lower_margin - 1
: 0; /* FIXME! */
vsend = info->var.lower_margin + info->var.vsync_len - 1;
vbend = info->var.lower_margin + info->var.vsync_len +
info->var.upper_margin;
vtotal = info->var.yres + vbend - 1;
stride = to3264(width, depth, 1);
base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
if (data64)
video |= PM2F_DATA_64_ENABLE;
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
if (lowhsync) {
DPRINTK("ignoring +hsync, using -hsync.\n");
video |= PM2F_HSYNC_ACT_LOW;
} else
video |= PM2F_HSYNC_ACT_HIGH;
} else
video |= PM2F_HSYNC_ACT_LOW;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
if (lowvsync) {
DPRINTK("ignoring +vsync, using -vsync.\n");
video |= PM2F_VSYNC_ACT_LOW;
} else
video |= PM2F_VSYNC_ACT_HIGH;
} else
video |= PM2F_VSYNC_ACT_LOW;
if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
DPRINTK("interlaced not supported\n");
return -EINVAL;
}
if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
video |= PM2F_LINE_DOUBLE;
if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
video |= PM2F_VIDEO_ENABLE;
par->video = video;
info->fix.visual =
(depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
info->fix.line_length = info->var.xres * depth / 8;
info->cmap.len = 256;
/*
* Settings calculated. Now write them out.
*/
if (par->type == PM2_TYPE_PERMEDIA2V) {
WAIT_FIFO(par, 1);
pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
}
set_aperture(par, depth);
mb();
WAIT_FIFO(par, 19);
switch (depth) {
case 8:
pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
clrformat = 0x2e;
break;
case 16:
pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
txtmap = PM2F_TEXTEL_SIZE_16;
pixsize = 1;
clrformat = 0x70;
misc |= 8;
break;
case 32:
pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
txtmap = PM2F_TEXTEL_SIZE_32;
pixsize = 2;
clrformat = 0x20;
misc |= 8;
break;
case 24:
pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
txtmap = PM2F_TEXTEL_SIZE_24;
pixsize = 4;
clrformat = 0x20;
misc |= 8;
break;
}
pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
pm2_WR(par, PM2R_H_TOTAL, htotal);
pm2_WR(par, PM2R_HS_START, hsstart);
pm2_WR(par, PM2R_HS_END, hsend);
pm2_WR(par, PM2R_HG_END, hbend);
pm2_WR(par, PM2R_HB_END, hbend);
pm2_WR(par, PM2R_V_TOTAL, vtotal);
pm2_WR(par, PM2R_VS_START, vsstart);
pm2_WR(par, PM2R_VS_END, vsend);
pm2_WR(par, PM2R_VB_END, vbend);
pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
wmb();
pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
wmb();
pm2_WR(par, PM2R_SCREEN_BASE, base);
wmb();
set_video(par, video);
WAIT_FIFO(par, 10);
switch (par->type) {
case PM2_TYPE_PERMEDIA2:
pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
(depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
break;
case PM2_TYPE_PERMEDIA2V:
pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
break;
}
set_pixclock(par, pixclock);
DPRINTK("Setting graphics mode at %dx%d depth %d\n",
info->var.xres, info->var.yres, info->var.bits_per_pixel);
return 0;
}
/**
* pm2fb_setcolreg - Sets a color register.
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*
* Set a single color register. The values supplied have a 16 bit
* magnitude which needs to be scaled in this function for the hardware.
* Pretty much a direct lift from tdfxfb.c.
*
* Returns negative errno on error, or zero on success.
*/
static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct pm2fb_par *par = info->par;
if (regno >= info->cmap.len) /* no. of hw registers */
return -EINVAL;
/*
* Program hardware... do anything you want with transp
*/
/* grayscale works only partially under directcolor */
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
if (info->var.grayscale)
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
/* Directcolor:
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* {hardwarespecific} contains width of DAC
* cmap[X] is programmed to
* (X << red.offset) | (X << green.offset) | (X << blue.offset)
* RAMDAC[X] is programmed to (red, green, blue)
*
* Pseudocolor:
* uses offset = 0 && length = DAC register width.
* var->{color}.offset is 0
* var->{color}.length contains width of DAC
* cmap is not used
* DAC[X] is programmed to (red, green, blue)
* Truecolor:
* does not use RAMDAC (usually has 3 of them).
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* cmap is programmed to
* (red << red.offset) | (green << green.offset) |
* (blue << blue.offset) | (transp << transp.offset)
* RAMDAC does not exist
*/
#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
case FB_VISUAL_PSEUDOCOLOR:
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
transp = CNVT_TOHW(transp, info->var.transp.length);
break;
case FB_VISUAL_DIRECTCOLOR:
/* example here assumes 8 bit DAC. Might be different
* for your hardware */
red = CNVT_TOHW(red, 8);
green = CNVT_TOHW(green, 8);
blue = CNVT_TOHW(blue, 8);
/* hey, there is bug in transp handling... */
transp = CNVT_TOHW(transp, 8);
break;
}
#undef CNVT_TOHW
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 v;
if (regno >= 16)
return -EINVAL;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
switch (info->var.bits_per_pixel) {
case 8:
break;
case 16:
case 24:
case 32:
par->palette[regno] = v;
break;
}
return 0;
} else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
set_color(par, regno, red, green, blue);
return 0;
}
/**
* pm2fb_pan_display - Pans the display.
* @var: frame buffer variable screen structure
* @info: frame buffer structure that represents a single frame buffer
*
* Pan (or wrap, depending on the `vmode' field) the display using the
* `xoffset' and `yoffset' fields of the `var' structure.
* If the values don't fit, return -EINVAL.
*
* Returns negative errno on error, or zero on success.
*
*/
static int pm2fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct pm2fb_par *p = info->par;
u32 base;
u32 depth = (info->var.bits_per_pixel + 7) & ~7;
u32 xres = (info->var.xres + 31) & ~31;
depth = (depth > 32) ? 32 : depth;
base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
WAIT_FIFO(p, 1);
pm2_WR(p, PM2R_SCREEN_BASE, base);
return 0;
}
/**
* pm2fb_blank - Blanks the display.
* @blank_mode: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*
* Blank the screen if blank_mode != 0, else unblank. Return 0 if
* blanking succeeded, != 0 if un-/blanking failed due to e.g. a
* video mode which doesn't support it. Implements VESA suspend
* and powerdown modes on hardware that supports disabling hsync/vsync:
* blank_mode == 2: suspend vsync
* blank_mode == 3: suspend hsync
* blank_mode == 4: powerdown
*
* Returns negative errno on error, or zero on success.
*
*/
static int pm2fb_blank(int blank_mode, struct fb_info *info)
{
struct pm2fb_par *par = info->par;
u32 video = par->video;
DPRINTK("blank_mode %d\n", blank_mode);
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* Screen: On */
video |= PM2F_VIDEO_ENABLE;
break;
case FB_BLANK_NORMAL:
/* Screen: Off */
video &= ~PM2F_VIDEO_ENABLE;
break;
case FB_BLANK_VSYNC_SUSPEND:
/* VSync: Off */
video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW);
break;
case FB_BLANK_HSYNC_SUSPEND:
/* HSync: Off */
video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
break;
case FB_BLANK_POWERDOWN:
/* HSync: Off, VSync: Off */
video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
break;
}
set_video(par, video);
return 0;
}
static int pm2fb_sync(struct fb_info *info)
{
struct pm2fb_par *par = info->par;
WAIT_FIFO(par, 1);
pm2_WR(par, PM2R_SYNC, 0);
mb();
do {
while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
cpu_relax();
} while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
return 0;
}
static void pm2fb_fillrect(struct fb_info *info,
const struct fb_fillrect *region)
{
struct pm2fb_par *par = info->par;
struct fb_fillrect modded;
int vxres, vyres;
u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
((u32 *)info->pseudo_palette)[region->color] : region->color;
if (info->state != FBINFO_STATE_RUNNING)
return;
if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
region->rop != ROP_COPY ) {
cfb_fillrect(info, region);
return;
}
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
memcpy(&modded, region, sizeof(struct fb_fillrect));
if (!modded.width || !modded.height ||
modded.dx >= vxres || modded.dy >= vyres)
return;
if (modded.dx + modded.width > vxres)
modded.width = vxres - modded.dx;
if (modded.dy + modded.height > vyres)
modded.height = vyres - modded.dy;
if (info->var.bits_per_pixel == 8)
color |= color << 8;
if (info->var.bits_per_pixel <= 16)
color |= color << 16;
WAIT_FIFO(par, 3);
pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE);
pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
if (info->var.bits_per_pixel != 24) {
WAIT_FIFO(par, 2);
pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
wmb();
pm2_WR(par, PM2R_RENDER,
PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL);
} else {
WAIT_FIFO(par, 4);
pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
pm2_WR(par, PM2R_CONSTANT_COLOR, color);
wmb();
pm2_WR(par, PM2R_RENDER,
PM2F_RENDER_RECTANGLE |
PM2F_INCREASE_X | PM2F_INCREASE_Y );
pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
}
}
static void pm2fb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct pm2fb_par *par = info->par;
struct fb_copyarea modded;
u32 vxres, vyres;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_copyarea(info, area);
return;
}
memcpy(&modded, area, sizeof(struct fb_copyarea));
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
if (!modded.width || !modded.height ||
modded.sx >= vxres || modded.sy >= vyres ||
modded.dx >= vxres || modded.dy >= vyres)
return;
if (modded.sx + modded.width > vxres)
modded.width = vxres - modded.sx;
if (modded.dx + modded.width > vxres)
modded.width = vxres - modded.dx;
if (modded.sy + modded.height > vyres)
modded.height = vyres - modded.sy;
if (modded.dy + modded.height > vyres)
modded.height = vyres - modded.dy;
WAIT_FIFO(par, 5);
pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
pm2_WR(par, PM2R_FB_SOURCE_DELTA,
((modded.sy - modded.dy) & 0xfff) << 16 |
((modded.sx - modded.dx) & 0xfff));
pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
wmb();
pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
(modded.dx < modded.sx ? PM2F_INCREASE_X : 0) |
(modded.dy < modded.sy ? PM2F_INCREASE_Y : 0));
}
static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct pm2fb_par *par = info->par;
u32 height = image->height;
u32 fgx, bgx;
const u32 *src = (const u32 *)image->data;
u32 xres = (info->var.xres + 31) & ~31;
int raster_mode = 1; /* invert bits */
#ifdef __LITTLE_ENDIAN
raster_mode |= 3 << 7; /* reverse byte order */
#endif
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) {
cfb_imageblit(info, image);
return;
}
switch (info->fix.visual) {
case FB_VISUAL_PSEUDOCOLOR:
fgx = image->fg_color;
bgx = image->bg_color;
break;
case FB_VISUAL_TRUECOLOR:
default:
fgx = par->palette[image->fg_color];
bgx = par->palette[image->bg_color];
break;
}
if (info->var.bits_per_pixel == 8) {
fgx |= fgx << 8;
bgx |= bgx << 8;
}
if (info->var.bits_per_pixel <= 16) {
fgx |= fgx << 16;
bgx |= bgx << 16;
}
WAIT_FIFO(par, 13);
pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
pm2_WR(par, PM2R_SCISSOR_MIN_XY,
((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
pm2_WR(par, PM2R_SCISSOR_MAX_XY,
(((image->dy + image->height) & 0x0fff) << 16) |
((image->dx + image->width) & 0x0fff));
pm2_WR(par, PM2R_SCISSOR_MODE, 1);
/* GXcopy & UNIT_ENABLE */
pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1);
pm2_WR(par, PM2R_RECTANGLE_ORIGIN,
((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
pm2_WR(par, PM2R_RECTANGLE_SIZE,
((image->height & 0x0fff) << 16) |
((image->width) & 0x0fff));
if (info->var.bits_per_pixel == 24) {
pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
/* clear area */
pm2_WR(par, PM2R_CONSTANT_COLOR, bgx);
pm2_WR(par, PM2R_RENDER,
PM2F_RENDER_RECTANGLE |
PM2F_INCREASE_X | PM2F_INCREASE_Y);
/* BitMapPackEachScanline */
pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode | (1 << 9));
pm2_WR(par, PM2R_CONSTANT_COLOR, fgx);
pm2_WR(par, PM2R_RENDER,
PM2F_RENDER_RECTANGLE |
PM2F_INCREASE_X | PM2F_INCREASE_Y |
PM2F_RENDER_SYNC_ON_BIT_MASK);
} else {
pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
/* clear area */
pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx);
pm2_WR(par, PM2R_RENDER,
PM2F_RENDER_RECTANGLE |
PM2F_RENDER_FASTFILL |
PM2F_INCREASE_X | PM2F_INCREASE_Y);
pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode);
pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx);
pm2_WR(par, PM2R_RENDER,
PM2F_RENDER_RECTANGLE |
PM2F_INCREASE_X | PM2F_INCREASE_Y |
PM2F_RENDER_FASTFILL |
PM2F_RENDER_SYNC_ON_BIT_MASK);
}
while (height--) {
int width = ((image->width + 7) >> 3)
+ info->pixmap.scan_align - 1;
width >>= 2;
WAIT_FIFO(par, width);
while (width--) {
pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src);
src++;
}
}
WAIT_FIFO(par, 3);
pm2_WR(par, PM2R_RASTERIZER_MODE, 0);
pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
pm2_WR(par, PM2R_SCISSOR_MODE, 0);
}
/*
* Hardware cursor support.
*/
static const u8 cursor_bits_lookup[16] = {
0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
};
static int pm2vfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct pm2fb_par *par = info->par;
u8 mode = PM2F_CURSORMODE_TYPE_X;
int x = cursor->image.dx - info->var.xoffset;
int y = cursor->image.dy - info->var.yoffset;
if (cursor->enable)
mode |= PM2F_CURSORMODE_CURSOR_ENABLE;
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_MODE, mode);
if (!cursor->enable)
x = 2047; /* push it outside display */
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_LOW, x & 0xff);
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HIGH, (x >> 8) & 0xf);
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_LOW, y & 0xff);
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HIGH, (y >> 8) & 0xf);
/*
* If the cursor is not be changed this means either we want the
* current cursor state (if enable is set) or we want to query what
* we can do with the cursor (if enable is not set)
*/
if (!cursor->set)
return 0;
if (cursor->set & FB_CUR_SETHOT) {
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HOT,
cursor->hot.x & 0x3f);
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HOT,
cursor->hot.y & 0x3f);
}
if (cursor->set & FB_CUR_SETCMAP) {
u32 fg_idx = cursor->image.fg_color;
u32 bg_idx = cursor->image.bg_color;
struct fb_cmap cmap = info->cmap;
/* the X11 driver says one should use these color registers */
pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CURSOR_PALETTE >> 8);
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 0,
cmap.red[bg_idx] >> 8 );
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 1,
cmap.green[bg_idx] >> 8 );
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 2,
cmap.blue[bg_idx] >> 8 );
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 3,
cmap.red[fg_idx] >> 8 );
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 4,
cmap.green[fg_idx] >> 8 );
pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 5,
cmap.blue[fg_idx] >> 8 );
pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
}
if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
u8 *bitmap = (u8 *)cursor->image.data;
u8 *mask = (u8 *)cursor->mask;
int i;
int pos = PM2VI_RD_CURSOR_PATTERN;
for (i = 0; i < cursor->image.height; i++) {
int j = (cursor->image.width + 7) >> 3;
int k = 8 - j;
pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
for (; j > 0; j--) {
u8 data = *bitmap ^ *mask;
if (cursor->rop == ROP_COPY)
data = *mask & *bitmap;
/* Upper 4 bits of bitmap data */
pm2v_RDAC_WR(par, pos++,
cursor_bits_lookup[data >> 4] |
(cursor_bits_lookup[*mask >> 4] << 1));
/* Lower 4 bits of bitmap */
pm2v_RDAC_WR(par, pos++,
cursor_bits_lookup[data & 0xf] |
(cursor_bits_lookup[*mask & 0xf] << 1));
bitmap++;
mask++;
}
for (; k > 0; k--) {
pm2v_RDAC_WR(par, pos++, 0);
pm2v_RDAC_WR(par, pos++, 0);
}
}
while (pos < (1024 + PM2VI_RD_CURSOR_PATTERN)) {
pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
pm2v_RDAC_WR(par, pos++, 0);
}
pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
}
return 0;
}
static int pm2fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct pm2fb_par *par = info->par;
u8 mode;
if (!hwcursor)
return -EINVAL; /* just to force soft_cursor() call */
/* Too large of a cursor or wrong bpp :-( */
if (cursor->image.width > 64 ||
cursor->image.height > 64 ||
cursor->image.depth > 1)
return -EINVAL;
if (par->type == PM2_TYPE_PERMEDIA2V)
return pm2vfb_cursor(info, cursor);
mode = 0x40;
if (cursor->enable)
mode = 0x43;
pm2_RDAC_WR(par, PM2I_RD_CURSOR_CONTROL, mode);
/*
* If the cursor is not be changed this means either we want the
* current cursor state (if enable is set) or we want to query what
* we can do with the cursor (if enable is not set)
*/
if (!cursor->set)
return 0;
if (cursor->set & FB_CUR_SETPOS) {
int x = cursor->image.dx - info->var.xoffset + 63;
int y = cursor->image.dy - info->var.yoffset + 63;
WAIT_FIFO(par, 4);
pm2_WR(par, PM2R_RD_CURSOR_X_LSB, x & 0xff);
pm2_WR(par, PM2R_RD_CURSOR_X_MSB, (x >> 8) & 0x7);
pm2_WR(par, PM2R_RD_CURSOR_Y_LSB, y & 0xff);
pm2_WR(par, PM2R_RD_CURSOR_Y_MSB, (y >> 8) & 0x7);
}
if (cursor->set & FB_CUR_SETCMAP) {
u32 fg_idx = cursor->image.fg_color;
u32 bg_idx = cursor->image.bg_color;
WAIT_FIFO(par, 7);
pm2_WR(par, PM2R_RD_CURSOR_COLOR_ADDRESS, 1);
pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
info->cmap.red[bg_idx] >> 8);
pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
info->cmap.green[bg_idx] >> 8);
pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
info->cmap.blue[bg_idx] >> 8);
pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
info->cmap.red[fg_idx] >> 8);
pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
info->cmap.green[fg_idx] >> 8);
pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
info->cmap.blue[fg_idx] >> 8);
}
if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
u8 *bitmap = (u8 *)cursor->image.data;
u8 *mask = (u8 *)cursor->mask;
int i;
WAIT_FIFO(par, 1);
pm2_WR(par, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
for (i = 0; i < cursor->image.height; i++) {
int j = (cursor->image.width + 7) >> 3;
int k = 8 - j;
WAIT_FIFO(par, 8);
for (; j > 0; j--) {
u8 data = *bitmap ^ *mask;
if (cursor->rop == ROP_COPY)
data = *mask & *bitmap;
/* bitmap data */
pm2_WR(par, PM2R_RD_CURSOR_DATA, data);
bitmap++;
mask++;
}
for (; k > 0; k--)
pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
}
for (; i < 64; i++) {
int j = 8;
WAIT_FIFO(par, 8);
while (j-- > 0)
pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
}
mask = (u8 *)cursor->mask;
for (i = 0; i < cursor->image.height; i++) {
int j = (cursor->image.width + 7) >> 3;
int k = 8 - j;
WAIT_FIFO(par, 8);
for (; j > 0; j--) {
/* mask */
pm2_WR(par, PM2R_RD_CURSOR_DATA, *mask);
mask++;
}
for (; k > 0; k--)
pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
}
for (; i < 64; i++) {
int j = 8;
WAIT_FIFO(par, 8);
while (j-- > 0)
pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
}
}
return 0;
}
/* ------------ Hardware Independent Functions ------------ */
/*
* Frame buffer operations
*/
static const struct fb_ops pm2fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = pm2fb_check_var,
.fb_set_par = pm2fb_set_par,
.fb_setcolreg = pm2fb_setcolreg,
.fb_blank = pm2fb_blank,
.fb_pan_display = pm2fb_pan_display,
.fb_fillrect = pm2fb_fillrect,
.fb_copyarea = pm2fb_copyarea,
.fb_imageblit = pm2fb_imageblit,
.fb_sync = pm2fb_sync,
.fb_cursor = pm2fb_cursor,
};
/*
* PCI stuff
*/
/**
* pm2fb_probe - Initialise and allocate resource for PCI device.
*
* @pdev: PCI device.
* @id: PCI device ID.
*/
static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct pm2fb_par *default_par;
struct fb_info *info;
int err;
int retval = -ENXIO;
err = aperture_remove_conflicting_pci_devices(pdev, "pm2fb");
if (err)
return err;
err = pci_enable_device(pdev);
if (err) {
printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
return err;
}
info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
if (!info) {
err = -ENOMEM;
goto err_exit_disable;
}
default_par = info->par;
switch (pdev->device) {
case PCI_DEVICE_ID_TI_TVP4020:
strcpy(pm2fb_fix.id, "TVP4020");
default_par->type = PM2_TYPE_PERMEDIA2;
break;
case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
strcpy(pm2fb_fix.id, "Permedia2");
default_par->type = PM2_TYPE_PERMEDIA2;
break;
case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
strcpy(pm2fb_fix.id, "Permedia2v");
default_par->type = PM2_TYPE_PERMEDIA2V;
break;
}
pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
pm2fb_fix.mmio_len = PM2_REGS_SIZE;
#if defined(__BIG_ENDIAN)
/*
* PM2 has a 64k register file, mapped twice in 128k. Lower
* map is little-endian, upper map is big-endian.
*/
pm2fb_fix.mmio_start += PM2_REGS_SIZE;
DPRINTK("Adjusting register base for big-endian.\n");
#endif
DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
/* Registers - request region and map it. */
if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
"pm2fb regbase")) {
printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
goto err_exit_neither;
}
default_par->v_regs =
ioremap(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
if (!default_par->v_regs) {
printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
pm2fb_fix.id);
release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
goto err_exit_neither;
}
/* Stash away memory register info for use when we reset the board */
default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
default_par->mem_control, default_par->boot_address,
default_par->mem_config);
if (default_par->mem_control == 0 &&
default_par->boot_address == 0x31 &&
default_par->mem_config == 0x259fffff) {
default_par->memclock = CVPPC_MEMCLOCK;
default_par->mem_control = 0;
default_par->boot_address = 0x20;
default_par->mem_config = 0xe6002021;
if (pdev->subsystem_vendor == 0x1048 &&
pdev->subsystem_device == 0x0a31) {
DPRINTK("subsystem_vendor: %04x, "
"subsystem_device: %04x\n",
pdev->subsystem_vendor, pdev->subsystem_device);
DPRINTK("We have not been initialized by VGA BIOS and "
"are running on an Elsa Winner 2000 Office\n");
DPRINTK("Initializing card timings manually...\n");
default_par->memclock = 100000;
}
if (pdev->subsystem_vendor == 0x3d3d &&
pdev->subsystem_device == 0x0100) {
DPRINTK("subsystem_vendor: %04x, "
"subsystem_device: %04x\n",
pdev->subsystem_vendor, pdev->subsystem_device);
DPRINTK("We have not been initialized by VGA BIOS and "
"are running on an 3dlabs reference board\n");
DPRINTK("Initializing card timings manually...\n");
default_par->memclock = 74894;
}
}
/* Now work out how big lfb is going to be. */
switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
case PM2F_MEM_BANKS_1:
pm2fb_fix.smem_len = 0x200000;
break;
case PM2F_MEM_BANKS_2:
pm2fb_fix.smem_len = 0x400000;
break;
case PM2F_MEM_BANKS_3:
pm2fb_fix.smem_len = 0x600000;
break;
case PM2F_MEM_BANKS_4:
pm2fb_fix.smem_len = 0x800000;
break;
}
pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
/* Linear frame buffer - request region and map it. */
if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
"pm2fb smem")) {
printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
goto err_exit_mmio;
}
info->screen_base =
ioremap_wc(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
if (!info->screen_base) {
printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
goto err_exit_mmio;
}
if (!nomtrr)
default_par->wc_cookie = arch_phys_wc_add(pm2fb_fix.smem_start,
pm2fb_fix.smem_len);
info->fbops = &pm2fb_ops;
info->fix = pm2fb_fix;
info->pseudo_palette = default_par->palette;
info->flags = FBINFO_HWACCEL_YPAN |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_HWACCEL_FILLRECT;
info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL);
if (!info->pixmap.addr) {
retval = -ENOMEM;
goto err_exit_pixmap;
}
info->pixmap.size = PM2_PIXMAP_SIZE;
info->pixmap.buf_align = 4;
info->pixmap.scan_align = 4;
info->pixmap.access_align = 32;
info->pixmap.flags = FB_PIXMAP_SYSTEM;
if (noaccel) {
printk(KERN_DEBUG "disabling acceleration\n");
info->flags |= FBINFO_HWACCEL_DISABLED;
info->pixmap.scan_align = 1;
}
if (!mode_option)
mode_option = "640x480@60";
err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
if (!err || err == 4)
info->var = pm2fb_var;
retval = fb_alloc_cmap(&info->cmap, 256, 0);
if (retval < 0)
goto err_exit_both;
retval = register_framebuffer(info);
if (retval < 0)
goto err_exit_all;
fb_info(info, "%s frame buffer device, memory = %dK\n",
info->fix.id, pm2fb_fix.smem_len / 1024);
/*
* Our driver data
*/
pci_set_drvdata(pdev, info);
return 0;
err_exit_all:
fb_dealloc_cmap(&info->cmap);
err_exit_both:
kfree(info->pixmap.addr);
err_exit_pixmap:
iounmap(info->screen_base);
release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
err_exit_mmio:
iounmap(default_par->v_regs);
release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
err_exit_neither:
framebuffer_release(info);
err_exit_disable:
pci_disable_device(pdev);
return retval;
}
/**
* pm2fb_remove - Release all device resources.
*
* @pdev: PCI device to clean up.
*/
static void pm2fb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct fb_fix_screeninfo *fix = &info->fix;
struct pm2fb_par *par = info->par;
unregister_framebuffer(info);
arch_phys_wc_del(par->wc_cookie);
iounmap(info->screen_base);
release_mem_region(fix->smem_start, fix->smem_len);
iounmap(par->v_regs);
release_mem_region(fix->mmio_start, fix->mmio_len);
fb_dealloc_cmap(&info->cmap);
kfree(info->pixmap.addr);
framebuffer_release(info);
pci_disable_device(pdev);
}
static const struct pci_device_id pm2fb_id_table[] = {
{ PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ 0, }
};
static struct pci_driver pm2fb_driver = {
.name = "pm2fb",
.id_table = pm2fb_id_table,
.probe = pm2fb_probe,
.remove = pm2fb_remove,
};
MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
#ifndef MODULE
/*
* Parse user specified options.
*
* This is, comma-separated options following `video=pm2fb:'.
*/
static int __init pm2fb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strcmp(this_opt, "lowhsync"))
lowhsync = 1;
else if (!strcmp(this_opt, "lowvsync"))
lowvsync = 1;
else if (!strncmp(this_opt, "hwcursor=", 9))
hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
else if (!strncmp(this_opt, "nomtrr", 6))
nomtrr = 1;
else if (!strncmp(this_opt, "noaccel", 7))
noaccel = 1;
else
mode_option = this_opt;
}
return 0;
}
#endif
static int __init pm2fb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("pm2fb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("pm2fb", &option))
return -ENODEV;
pm2fb_setup(option);
#endif
return pci_register_driver(&pm2fb_driver);
}
module_init(pm2fb_init);
#ifdef MODULE
/*
* Cleanup
*/
static void __exit pm2fb_exit(void)
{
pci_unregister_driver(&pm2fb_driver);
}
#endif
#ifdef MODULE
module_exit(pm2fb_exit);
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
module_param_named(mode, mode_option, charp, 0);
MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
module_param(lowhsync, bool, 0);
MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
module_param(lowvsync, bool, 0);
MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
module_param(noaccel, bool, 0);
MODULE_PARM_DESC(noaccel, "Disable acceleration");
module_param(hwcursor, int, 0644);
MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
"(1=enable, 0=disable, default=1)");
module_param(nomtrr, bool, 0);
MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
MODULE_AUTHOR("Jim Hague <[email protected]>");
MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
MODULE_LICENSE("GPL");
#endif
| linux-master | drivers/video/fbdev/pm2fb.c |
/* drivers/video/s1d13xxxfb.c
*
* (c) 2004 Simtec Electronics
* (c) 2005 Thibaut VARENE <[email protected]>
* (c) 2009 Kristoffer Ericson <[email protected]>
*
* Driver for Epson S1D13xxx series framebuffer chips
*
* Adapted from
* linux/drivers/video/skeletonfb.c
* linux/drivers/video/epson1355fb.c
* linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
*
* TODO: - handle dual screen display (CRT and LCD at the same time).
* - check_var(), mode change, etc.
* - probably not SMP safe :)
* - support all bitblt operations on all cards
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/mm.h>
#include <linux/mman.h>
#include <linux/fb.h>
#include <linux/spinlock_types.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <video/s1d13xxxfb.h>
#define PFX "s1d13xxxfb: "
#define BLIT "s1d13xxxfb_bitblt: "
/*
* set this to enable debugging on general functions
*/
#if 0
#define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
#else
#define dbg(fmt, args...) do { no_printk(KERN_INFO fmt, ## args); } while (0)
#endif
/*
* set this to enable debugging on 2D acceleration
*/
#if 0
#define dbg_blit(fmt, args...) do { printk(KERN_INFO BLIT fmt, ## args); } while (0)
#else
#define dbg_blit(fmt, args...) do { } while (0)
#endif
/*
* we make sure only one bitblt operation is running
*/
static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock);
/*
* list of card production ids
*/
static const int s1d13xxxfb_prod_ids[] = {
S1D13505_PROD_ID,
S1D13506_PROD_ID,
S1D13806_PROD_ID,
};
/*
* List of card strings
*/
static const char *s1d13xxxfb_prod_names[] = {
"S1D13505",
"S1D13506",
"S1D13806",
};
/*
* here we define the default struct fb_fix_screeninfo
*/
static const struct fb_fix_screeninfo s1d13xxxfb_fix = {
.id = S1D_FBID,
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static inline u8
s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno)
{
return readb(par->regs + regno);
}
static inline void
s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value)
{
writeb(value, par->regs + regno);
}
static inline void
s1d13xxxfb_runinit(struct s1d13xxxfb_par *par,
const struct s1d13xxxfb_regval *initregs,
const unsigned int size)
{
int i;
for (i = 0; i < size; i++) {
if ((initregs[i].addr == S1DREG_DELAYOFF) ||
(initregs[i].addr == S1DREG_DELAYON))
mdelay((int)initregs[i].value);
else {
s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value);
}
}
/* make sure the hardware can cope with us */
mdelay(1);
}
static inline void
lcd_enable(struct s1d13xxxfb_par *par, int enable)
{
u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
if (enable)
mode |= 0x01;
else
mode &= ~0x01;
s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
}
static inline void
crt_enable(struct s1d13xxxfb_par *par, int enable)
{
u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
if (enable)
mode |= 0x02;
else
mode &= ~0x02;
s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
}
/*************************************************************
framebuffer control functions
*************************************************************/
static inline void
s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
{
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->var.red.length = 4;
info->var.green.length = 4;
info->var.blue.length = 4;
}
static inline void
s1d13xxxfb_setup_truecolour(struct fb_info *info)
{
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->var.bits_per_pixel = 16;
info->var.red.length = 5;
info->var.red.offset = 11;
info->var.green.length = 6;
info->var.green.offset = 5;
info->var.blue.length = 5;
info->var.blue.offset = 0;
}
/**
* s1d13xxxfb_set_par - Alters the hardware state.
* @info: frame buffer structure
*
* Using the fb_var_screeninfo in fb_info we set the depth of the
* framebuffer. This function alters the par AND the
* fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
* fb_info since we are using that data. This means we depend on the
* data in var inside fb_info to be supported by the hardware.
* xxxfb_check_var is always called before xxxfb_set_par to ensure this.
*
* XXX TODO: write proper s1d13xxxfb_check_var(), without which that
* function is quite useless.
*/
static int
s1d13xxxfb_set_par(struct fb_info *info)
{
struct s1d13xxxfb_par *s1dfb = info->par;
unsigned int val;
dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel);
if ((s1dfb->display & 0x01)) /* LCD */
val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */
else /* CRT */
val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */
val &= ~0x07;
switch (info->var.bits_per_pixel) {
case 4:
dbg("pseudo colour 4\n");
s1d13xxxfb_setup_pseudocolour(info);
val |= 2;
break;
case 8:
dbg("pseudo colour 8\n");
s1d13xxxfb_setup_pseudocolour(info);
val |= 3;
break;
case 16:
dbg("true colour\n");
s1d13xxxfb_setup_truecolour(info);
val |= 5;
break;
default:
dbg("bpp not supported!\n");
return -EINVAL;
}
dbg("writing %02x to display mode register\n", val);
if ((s1dfb->display & 0x01)) /* LCD */
s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val);
else /* CRT */
s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val);
info->fix.line_length = info->var.xres * info->var.bits_per_pixel;
info->fix.line_length /= 8;
dbg("setting line_length to %d\n", info->fix.line_length);
dbg("done setup\n");
return 0;
}
/**
* s1d13xxxfb_setcolreg - sets a color register.
* @regno: Which register in the CLUT we are programming
* @red: The red value which can be up to 16 bits wide
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*
* Returns negative errno on error, or zero on success.
*/
static int
s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct s1d13xxxfb_par *s1dfb = info->par;
unsigned int pseudo_val;
if (regno >= S1D_PALETTE_SIZE)
return -EINVAL;
dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n",
regno, red, green, blue, transp);
if (info->var.grayscale)
red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16;
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
if (regno >= 16)
return -EINVAL;
/* deal with creating pseudo-palette entries */
pseudo_val = (red >> 11) << info->var.red.offset;
pseudo_val |= (green >> 10) << info->var.green.offset;
pseudo_val |= (blue >> 11) << info->var.blue.offset;
dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
regno, pseudo_val);
((u32 *)info->pseudo_palette)[regno] = pseudo_val;
break;
case FB_VISUAL_PSEUDOCOLOR:
s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno);
s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red);
s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green);
s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue);
break;
default:
return -ENOSYS;
}
dbg("s1d13xxxfb_setcolreg: done\n");
return 0;
}
/**
* s1d13xxxfb_blank - blanks the display.
* @blank_mode: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*
* Blank the screen if blank_mode != 0, else unblank. Return 0 if
* blanking succeeded, != 0 if un-/blanking failed due to e.g. a
* video mode which doesn't support it. Implements VESA suspend
* and powerdown modes on hardware that supports disabling hsync/vsync:
* blank_mode == 2: suspend vsync
* blank_mode == 3: suspend hsync
* blank_mode == 4: powerdown
*
* Returns negative errno on error, or zero on success.
*/
static int
s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
{
struct s1d13xxxfb_par *par = info->par;
dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info);
switch (blank_mode) {
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
if ((par->display & 0x01) != 0)
lcd_enable(par, 1);
if ((par->display & 0x02) != 0)
crt_enable(par, 1);
break;
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
break;
case FB_BLANK_POWERDOWN:
lcd_enable(par, 0);
crt_enable(par, 0);
break;
default:
return -EINVAL;
}
/* let fbcon do a soft blank for us */
return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
}
/**
* s1d13xxxfb_pan_display - Pans the display.
* @var: frame buffer variable screen structure
* @info: frame buffer structure that represents a single frame buffer
*
* Pan (or wrap, depending on the `vmode' field) the display using the
* `yoffset' field of the `var' structure (`xoffset' not yet supported).
* If the values don't fit, return -EINVAL.
*
* Returns negative errno on error, or zero on success.
*/
static int
s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct s1d13xxxfb_par *par = info->par;
u32 start;
if (var->xoffset != 0) /* not yet ... */
return -EINVAL;
if (var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
start = (info->fix.line_length >> 1) * var->yoffset;
if ((par->display & 0x01)) {
/* LCD */
s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff));
s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff));
s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f));
} else {
/* CRT */
s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff));
s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff));
s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f));
}
return 0;
}
/************************************************************
functions to handle bitblt acceleration
************************************************************/
/**
* bltbit_wait_bitclear - waits for change in register value
* @info : frambuffer structure
* @bit : value currently in register
* @timeout : ...
*
* waits until value changes FROM bit
*
*/
static u8
bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout)
{
while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) {
udelay(10);
if (!--timeout) {
dbg_blit("wait_bitclear timeout\n");
break;
}
}
return timeout;
}
/*
* s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
* @info : framebuffer structure
* @area : fb_copyarea structure
*
* supports (atleast) S1D13506
*
*/
static void
s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
u32 dst, src;
u32 stride;
u16 reverse = 0;
u16 sx = area->sx, sy = area->sy;
u16 dx = area->dx, dy = area->dy;
u16 width = area->width, height = area->height;
u16 bpp;
spin_lock(&s1d13xxxfb_bitblt_lock);
/* bytes per xres line */
bpp = (info->var.bits_per_pixel >> 3);
stride = bpp * info->var.xres;
/* reverse, calculate the last pixel in rectangle */
if ((dy > sy) || ((dy == sy) && (dx >= sx))) {
dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1)));
src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1)));
reverse = 1;
/* not reverse, calculate the first pixel in rectangle */
} else { /* (y * xres) + (bpp * x) */
dst = (dy * stride) + (bpp * dx);
src = (sy * stride) + (bpp * sx);
}
/* set source address */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff));
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff);
/* set destination address */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff));
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff);
/* program height and width */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8));
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8));
/* negative direction ROP */
if (reverse == 1) {
dbg_blit("(copyarea) negative rop\n");
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03);
} else /* positive direction ROP */ {
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02);
dbg_blit("(copyarea) positive rop\n");
}
/* set for rectangel mode and not linear */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
/* setup the bpp 1 = 16bpp, 0 = 8bpp*/
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1));
/* set words per xres */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9));
dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy);
dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy);
dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1);
dbg_blit("(copyarea) stride=%d\n", stride);
dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1),
(stride >> 1) & 0xff, stride >> 9);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c);
/* initialize the engine */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
/* wait to complete */
bltbit_wait_bitclear(info, 0x80, 8000);
spin_unlock(&s1d13xxxfb_bitblt_lock);
}
/**
* s1d13xxxfb_bitblt_solidfill - accelerated solidfill function
* @info : framebuffer structure
* @rect : fb_fillrect structure
*
* supports (atleast 13506)
*
**/
static void
s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect)
{
u32 screen_stride, dest;
u32 fg;
u16 bpp = (info->var.bits_per_pixel >> 3);
/* grab spinlock */
spin_lock(&s1d13xxxfb_bitblt_lock);
/* bytes per x width */
screen_stride = (bpp * info->var.xres);
/* bytes to starting point */
dest = ((rect->dy * screen_stride) + (bpp * rect->dx));
dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n"
"(solidfill) : rect_width=%d, rect_height=%d\n",
rect->dx, rect->dy, screen_stride, dest,
rect->width - 1, rect->height - 1);
dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n",
info->var.xres, info->var.yres,
info->var.bits_per_pixel);
dbg_blit("(solidfill) : rop=%d\n", rect->rop);
/* We split the destination into the three registers */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff));
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff));
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff));
/* give information regarding rectangel width */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8));
/* give information regarding rectangel height */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8));
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
fg = ((u32 *)info->pseudo_palette)[rect->color];
dbg_blit("(solidfill) truecolor/directcolor\n");
dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg);
} else {
fg = rect->color;
dbg_blit("(solidfill) color = %d\n", rect->color);
}
/* set foreground color */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff));
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff);
/* set rectangual region of memory (rectangle and not linear) */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
/* set operation mode SOLID_FILL */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL);
/* set bits per pixel (1 = 16bpp, 0 = 8bpp) */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4));
/* set the memory offset for the bblt in word sizes */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff);
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9));
/* and away we go.... */
s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
/* wait until its done */
bltbit_wait_bitclear(info, 0x80, 8000);
/* let others play */
spin_unlock(&s1d13xxxfb_bitblt_lock);
}
/* framebuffer information structures */
static struct fb_ops s1d13xxxfb_fbops = {
.owner = THIS_MODULE,
.fb_set_par = s1d13xxxfb_set_par,
.fb_setcolreg = s1d13xxxfb_setcolreg,
.fb_blank = s1d13xxxfb_blank,
.fb_pan_display = s1d13xxxfb_pan_display,
/* gets replaced at chip detection time */
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static int s1d13xxxfb_width_tab[2][4] = {
{4, 8, 16, -1},
{9, 12, 18, -1},
};
/**
* s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
* hardware setup.
* @info: frame buffer structure
*
* We setup the framebuffer structures according to the current
* hardware setup. On some machines, the BIOS will have filled
* the chip registers with such info, on others, these values will
* have been written in some init procedure. In any case, the
* software values needs to match the hardware ones. This is what
* this function ensures.
*
* Note: some of the hardcoded values here might need some love to
* work on various chips, and might need to no longer be hardcoded.
*/
static void s1d13xxxfb_fetch_hw_state(struct fb_info *info)
{
struct fb_var_screeninfo *var = &info->var;
struct fb_fix_screeninfo *fix = &info->fix;
struct s1d13xxxfb_par *par = info->par;
u8 panel, display;
u16 offset;
u32 xres, yres;
u32 xres_virtual, yres_virtual;
int bpp, lcd_bpp;
int is_color, is_dual, is_tft;
int lcd_enabled, crt_enabled;
fix->type = FB_TYPE_PACKED_PIXELS;
/* general info */
par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
crt_enabled = (par->display & 0x02) != 0;
lcd_enabled = (par->display & 0x01) != 0;
if (lcd_enabled && crt_enabled)
printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n");
if (lcd_enabled)
display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
else /* CRT */
display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);
bpp = display & 0x07;
switch (bpp) {
case 2: /* 4 bpp */
case 3: /* 8 bpp */
var->bits_per_pixel = 8;
var->red.offset = var->green.offset = var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = 8;
break;
case 5: /* 16 bpp */
s1d13xxxfb_setup_truecolour(info);
break;
default:
dbg("bpp: %i\n", bpp);
}
fb_alloc_cmap(&info->cmap, 256, 0);
/* LCD info */
panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE);
is_color = (panel & 0x04) != 0;
is_dual = (panel & 0x02) != 0;
is_tft = (panel & 0x01) != 0;
lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3];
if (lcd_enabled) {
xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8;
yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) +
((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1);
offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) +
((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8));
} else { /* crt */
xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8;
yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) +
((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1);
offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) +
((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8));
}
xres_virtual = offset * 16 / var->bits_per_pixel;
yres_virtual = fix->smem_len / (offset * 2);
var->xres = xres;
var->yres = yres;
var->xres_virtual = xres_virtual;
var->yres_virtual = yres_virtual;
var->xoffset = var->yoffset = 0;
fix->line_length = offset * 2;
var->grayscale = !is_color;
var->activate = FB_ACTIVATE_NOW;
dbg(PFX "bpp=%d, lcd_bpp=%d, "
"crt_enabled=%d, lcd_enabled=%d\n",
var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled);
dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d "
"is_color=%d, is_dual=%d, is_tft=%d\n",
xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft);
}
static void __s1d13xxxfb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct s1d13xxxfb_par *par = NULL;
if (info) {
par = info->par;
if (par && par->regs) {
/* disable output & enable powersave */
s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00);
s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11);
iounmap(par->regs);
}
fb_dealloc_cmap(&info->cmap);
if (info->screen_base)
iounmap(info->screen_base);
framebuffer_release(info);
}
release_mem_region(pdev->resource[0].start,
resource_size(&pdev->resource[0]));
release_mem_region(pdev->resource[1].start,
resource_size(&pdev->resource[1]));
}
static void s1d13xxxfb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
unregister_framebuffer(info);
__s1d13xxxfb_remove(pdev);
}
static int s1d13xxxfb_probe(struct platform_device *pdev)
{
struct s1d13xxxfb_par *default_par;
struct fb_info *info;
struct s1d13xxxfb_pdata *pdata = NULL;
int ret = 0;
int i;
u8 revision, prod_id;
dbg("probe called: device is %p\n", pdev);
printk(KERN_INFO "Epson S1D13XXX FB Driver\n");
/* enable platform-dependent hardware glue, if any */
if (dev_get_platdata(&pdev->dev))
pdata = dev_get_platdata(&pdev->dev);
if (pdata && pdata->platform_init_video)
pdata->platform_init_video();
if (pdev->num_resources != 2) {
dev_err(&pdev->dev, "invalid num_resources: %i\n",
pdev->num_resources);
ret = -ENODEV;
goto bail;
}
/* resource[0] is VRAM, resource[1] is registers */
if (pdev->resource[0].flags != IORESOURCE_MEM
|| pdev->resource[1].flags != IORESOURCE_MEM) {
dev_err(&pdev->dev, "invalid resource type\n");
ret = -ENODEV;
goto bail;
}
if (!request_mem_region(pdev->resource[0].start,
resource_size(&pdev->resource[0]), "s1d13xxxfb mem")) {
dev_dbg(&pdev->dev, "request_mem_region failed\n");
ret = -EBUSY;
goto bail;
}
if (!request_mem_region(pdev->resource[1].start,
resource_size(&pdev->resource[1]), "s1d13xxxfb regs")) {
dev_dbg(&pdev->dev, "request_mem_region failed\n");
ret = -EBUSY;
goto bail;
}
info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev);
if (!info) {
ret = -ENOMEM;
goto bail;
}
platform_set_drvdata(pdev, info);
default_par = info->par;
default_par->regs = ioremap(pdev->resource[1].start,
resource_size(&pdev->resource[1]));
if (!default_par->regs) {
printk(KERN_ERR PFX "unable to map registers\n");
ret = -ENOMEM;
goto bail;
}
info->pseudo_palette = default_par->pseudo_palette;
info->screen_base = ioremap(pdev->resource[0].start,
resource_size(&pdev->resource[0]));
if (!info->screen_base) {
printk(KERN_ERR PFX "unable to map framebuffer\n");
ret = -ENOMEM;
goto bail;
}
/* production id is top 6 bits */
prod_id = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) >> 2;
/* revision id is lower 2 bits */
revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE) & 0x3;
ret = -ENODEV;
for (i = 0; i < ARRAY_SIZE(s1d13xxxfb_prod_ids); i++) {
if (prod_id == s1d13xxxfb_prod_ids[i]) {
/* looks like we got it in our list */
default_par->prod_id = prod_id;
default_par->revision = revision;
ret = 0;
break;
}
}
if (!ret) {
printk(KERN_INFO PFX "chip production id %i = %s\n",
prod_id, s1d13xxxfb_prod_names[i]);
printk(KERN_INFO PFX "chip revision %i\n", revision);
} else {
printk(KERN_INFO PFX
"unknown chip production id %i, revision %i\n",
prod_id, revision);
printk(KERN_INFO PFX "please contact maintainer\n");
goto bail;
}
info->fix = s1d13xxxfb_fix;
info->fix.mmio_start = pdev->resource[1].start;
info->fix.mmio_len = resource_size(&pdev->resource[1]);
info->fix.smem_start = pdev->resource[0].start;
info->fix.smem_len = resource_size(&pdev->resource[0]);
printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
default_par->regs, info->fix.smem_len / 1024, info->screen_base);
info->par = default_par;
info->flags = FBINFO_HWACCEL_YPAN;
info->fbops = &s1d13xxxfb_fbops;
switch(prod_id) {
case S1D13506_PROD_ID: /* activate acceleration */
s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill;
s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea;
info->flags = FBINFO_HWACCEL_YPAN |
FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
break;
default:
break;
}
/* perform "manual" chip initialization, if needed */
if (pdata && pdata->initregs)
s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize);
s1d13xxxfb_fetch_hw_state(info);
if (register_framebuffer(info) < 0) {
ret = -EINVAL;
goto bail;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
bail:
__s1d13xxxfb_remove(pdev);
return ret;
}
#ifdef CONFIG_PM
static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state)
{
struct fb_info *info = platform_get_drvdata(dev);
struct s1d13xxxfb_par *s1dfb = info->par;
struct s1d13xxxfb_pdata *pdata = NULL;
/* disable display */
lcd_enable(s1dfb, 0);
crt_enable(s1dfb, 0);
if (dev_get_platdata(&dev->dev))
pdata = dev_get_platdata(&dev->dev);
#if 0
if (!s1dfb->disp_save)
s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL);
if (!s1dfb->disp_save) {
printk(KERN_ERR PFX "no memory to save screen\n");
return -ENOMEM;
}
memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len);
#else
s1dfb->disp_save = NULL;
#endif
if (!s1dfb->regs_save)
s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL);
if (!s1dfb->regs_save) {
printk(KERN_ERR PFX "no memory to save registers");
return -ENOMEM;
}
/* backup all registers */
memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len);
/* now activate power save mode */
s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11);
if (pdata && pdata->platform_suspend_video)
return pdata->platform_suspend_video();
else
return 0;
}
static int s1d13xxxfb_resume(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
struct s1d13xxxfb_par *s1dfb = info->par;
struct s1d13xxxfb_pdata *pdata = NULL;
/* awaken the chip */
s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10);
/* do not let go until SDRAM "wakes up" */
while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01))
udelay(10);
if (dev_get_platdata(&dev->dev))
pdata = dev_get_platdata(&dev->dev);
if (s1dfb->regs_save) {
/* will write RO regs, *should* get away with it :) */
memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len);
kfree(s1dfb->regs_save);
}
if (s1dfb->disp_save) {
memcpy_toio(info->screen_base, s1dfb->disp_save,
info->fix.smem_len);
kfree(s1dfb->disp_save); /* XXX kmalloc()'d when? */
}
if ((s1dfb->display & 0x01) != 0)
lcd_enable(s1dfb, 1);
if ((s1dfb->display & 0x02) != 0)
crt_enable(s1dfb, 1);
if (pdata && pdata->platform_resume_video)
return pdata->platform_resume_video();
else
return 0;
}
#endif /* CONFIG_PM */
static struct platform_driver s1d13xxxfb_driver = {
.probe = s1d13xxxfb_probe,
.remove_new = s1d13xxxfb_remove,
#ifdef CONFIG_PM
.suspend = s1d13xxxfb_suspend,
.resume = s1d13xxxfb_resume,
#endif
.driver = {
.name = S1D_DEVICENAME,
},
};
static int __init
s1d13xxxfb_init(void)
{
#ifndef MODULE
if (fb_get_options("s1d13xxxfb", NULL))
return -ENODEV;
#endif
return platform_driver_register(&s1d13xxxfb_driver);
}
static void __exit
s1d13xxxfb_exit(void)
{
platform_driver_unregister(&s1d13xxxfb_driver);
}
module_init(s1d13xxxfb_init);
module_exit(s1d13xxxfb_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices");
MODULE_AUTHOR("Ben Dooks <[email protected]>, Thibaut VARENE <[email protected]>");
| linux-master | drivers/video/fbdev/s1d13xxxfb.c |
/*
* linux/drivers/video/ps3fb.c -- PS3 GPU frame buffer device
*
* Copyright (C) 2006 Sony Computer Entertainment Inc.
* Copyright 2006, 2007 Sony Corporation
*
* This file is based on :
*
* linux/drivers/video/vfb.c -- Virtual frame buffer device
*
* Copyright (C) 2002 James Simmons
*
* Copyright (C) 1997 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/console.h>
#include <linux/ioctl.h>
#include <linux/kthread.h>
#include <linux/freezer.h>
#include <linux/uaccess.h>
#include <linux/fb.h>
#include <linux/fbcon.h>
#include <linux/init.h>
#include <asm/cell-regs.h>
#include <asm/lv1call.h>
#include <asm/ps3av.h>
#include <asm/ps3fb.h>
#include <asm/ps3.h>
#include <asm/ps3gpu.h>
#define DEVICE_NAME "ps3fb"
#define GPU_CMD_BUF_SIZE (2 * 1024 * 1024)
#define GPU_FB_START (64 * 1024)
#define GPU_IOIF (0x0d000000UL)
#define GPU_ALIGN_UP(x) ALIGN((x), 64)
#define GPU_MAX_LINE_LENGTH (65536 - 64)
#define GPU_INTR_STATUS_VSYNC_0 0 /* vsync on head A */
#define GPU_INTR_STATUS_VSYNC_1 1 /* vsync on head B */
#define GPU_INTR_STATUS_FLIP_0 3 /* flip head A */
#define GPU_INTR_STATUS_FLIP_1 4 /* flip head B */
#define GPU_INTR_STATUS_QUEUE_0 5 /* queue head A */
#define GPU_INTR_STATUS_QUEUE_1 6 /* queue head B */
#define GPU_DRIVER_INFO_VERSION 0x211
/* gpu internals */
struct display_head {
u64 be_time_stamp;
u32 status;
u32 offset;
u32 res1;
u32 res2;
u32 field;
u32 reserved1;
u64 res3;
u32 raster;
u64 vblank_count;
u32 field_vsync;
u32 reserved2;
};
struct gpu_irq {
u32 irq_outlet;
u32 status;
u32 mask;
u32 video_cause;
u32 graph_cause;
u32 user_cause;
u32 res1;
u64 res2;
u32 reserved[4];
};
struct gpu_driver_info {
u32 version_driver;
u32 version_gpu;
u32 memory_size;
u32 hardware_channel;
u32 nvcore_frequency;
u32 memory_frequency;
u32 reserved[1063];
struct display_head display_head[8];
struct gpu_irq irq;
};
struct ps3fb_priv {
unsigned int irq_no;
u64 context_handle, memory_handle;
struct gpu_driver_info *dinfo;
u64 vblank_count; /* frame count */
wait_queue_head_t wait_vsync;
atomic_t ext_flip; /* on/off flip with vsync */
atomic_t f_count; /* fb_open count */
int is_blanked;
int is_kicked;
struct task_struct *task;
};
static struct ps3fb_priv ps3fb;
struct ps3fb_par {
u32 pseudo_palette[16];
int mode_id, new_mode_id;
unsigned int num_frames; /* num of frame buffers */
unsigned int width;
unsigned int height;
unsigned int ddr_line_length;
unsigned int ddr_frame_size;
unsigned int xdr_frame_size;
unsigned int full_offset; /* start of fullscreen DDR fb */
unsigned int fb_offset; /* start of actual DDR fb */
unsigned int pan_offset;
};
#define FIRST_NATIVE_MODE_INDEX 10
static const struct fb_videomode ps3fb_modedb[] = {
/* 60 Hz broadcast modes (modes "1" to "5") */
{
/* 480i */
"480i", 60, 576, 384, 74074, 130, 89, 78, 57, 63, 6,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED
}, {
/* 480p */
"480p", 60, 576, 384, 37037, 130, 89, 78, 57, 63, 6,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
}, {
/* 720p */
"720p", 60, 1124, 644, 13481, 298, 148, 57, 44, 80, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
}, {
/* 1080i */
"1080i", 60, 1688, 964, 13481, 264, 160, 94, 62, 88, 5,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED
}, {
/* 1080p */
"1080p", 60, 1688, 964, 6741, 264, 160, 94, 62, 88, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
},
/* 50 Hz broadcast modes (modes "6" to "10") */
{
/* 576i */
"576i", 50, 576, 460, 74074, 142, 83, 97, 63, 63, 5,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED
}, {
/* 576p */
"576p", 50, 576, 460, 37037, 142, 83, 97, 63, 63, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
}, {
/* 720p */
"720p", 50, 1124, 644, 13468, 298, 478, 57, 44, 80, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
}, {
/* 1080i */
"1080i", 50, 1688, 964, 13468, 264, 600, 94, 62, 88, 5,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED
}, {
/* 1080p */
"1080p", 50, 1688, 964, 6734, 264, 600, 94, 62, 88, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
},
[FIRST_NATIVE_MODE_INDEX] =
/* 60 Hz broadcast modes (full resolution versions of modes "1" to "5") */
{
/* 480if */
"480if", 60, 720, 480, 74074, 58, 17, 30, 9, 63, 6,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED
}, {
/* 480pf */
"480pf", 60, 720, 480, 37037, 58, 17, 30, 9, 63, 6,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
}, {
/* 720pf */
"720pf", 60, 1280, 720, 13481, 220, 70, 19, 6, 80, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
}, {
/* 1080if */
"1080if", 60, 1920, 1080, 13481, 148, 44, 36, 4, 88, 5,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED
}, {
/* 1080pf */
"1080pf", 60, 1920, 1080, 6741, 148, 44, 36, 4, 88, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
},
/* 50 Hz broadcast modes (full resolution versions of modes "6" to "10") */
{
/* 576if */
"576if", 50, 720, 576, 74074, 70, 11, 39, 5, 63, 5,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED
}, {
/* 576pf */
"576pf", 50, 720, 576, 37037, 70, 11, 39, 5, 63, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
}, {
/* 720pf */
"720pf", 50, 1280, 720, 13468, 220, 400, 19, 6, 80, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
}, {
/* 1080if */
"1080if", 50, 1920, 1080, 13468, 148, 484, 36, 4, 88, 5,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED
}, {
/* 1080pf */
"1080pf", 50, 1920, 1080, 6734, 148, 484, 36, 4, 88, 5,
FB_SYNC_BROADCAST, FB_VMODE_NONINTERLACED
},
/* VESA modes (modes "11" to "13") */
{
/* WXGA */
"wxga", 60, 1280, 768, 12924, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED,
FB_MODE_IS_VESA
}, {
/* SXGA */
"sxga", 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED,
FB_MODE_IS_VESA
}, {
/* WUXGA */
"wuxga", 60, 1920, 1200, 6494, 80, 48, 26, 3, 32, 6,
FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED,
FB_MODE_IS_VESA
}
};
#define HEAD_A
#define HEAD_B
#define BPP 4 /* number of bytes per pixel */
static int ps3fb_mode;
module_param(ps3fb_mode, int, 0);
static char *mode_option;
static int ps3fb_cmp_mode(const struct fb_videomode *vmode,
const struct fb_var_screeninfo *var)
{
long xres, yres, left_margin, right_margin, upper_margin, lower_margin;
long dx, dy;
/* maximum values */
if (var->xres > vmode->xres || var->yres > vmode->yres ||
var->pixclock > vmode->pixclock ||
var->hsync_len > vmode->hsync_len ||
var->vsync_len > vmode->vsync_len)
return -1;
/* progressive/interlaced must match */
if ((var->vmode & FB_VMODE_MASK) != vmode->vmode)
return -1;
/* minimum resolution */
xres = max(var->xres, 1U);
yres = max(var->yres, 1U);
/* minimum margins */
left_margin = max(var->left_margin, vmode->left_margin);
right_margin = max(var->right_margin, vmode->right_margin);
upper_margin = max(var->upper_margin, vmode->upper_margin);
lower_margin = max(var->lower_margin, vmode->lower_margin);
/* resolution + margins may not exceed native parameters */
dx = ((long)vmode->left_margin + (long)vmode->xres +
(long)vmode->right_margin) -
(left_margin + xres + right_margin);
if (dx < 0)
return -1;
dy = ((long)vmode->upper_margin + (long)vmode->yres +
(long)vmode->lower_margin) -
(upper_margin + yres + lower_margin);
if (dy < 0)
return -1;
/* exact match */
if (!dx && !dy)
return 0;
/* resolution difference */
return (vmode->xres - xres) * (vmode->yres - yres);
}
static const struct fb_videomode *ps3fb_native_vmode(enum ps3av_mode_num id)
{
return &ps3fb_modedb[FIRST_NATIVE_MODE_INDEX + id - 1];
}
static const struct fb_videomode *ps3fb_vmode(int id)
{
u32 mode = id & PS3AV_MODE_MASK;
if (mode < PS3AV_MODE_480I || mode > PS3AV_MODE_WUXGA)
return NULL;
if (mode <= PS3AV_MODE_1080P50 && !(id & PS3AV_MODE_FULL)) {
/* Non-fullscreen broadcast mode */
return &ps3fb_modedb[mode - 1];
}
return ps3fb_native_vmode(mode);
}
static unsigned int ps3fb_find_mode(struct fb_var_screeninfo *var,
u32 *ddr_line_length, u32 *xdr_line_length)
{
unsigned int id, best_id;
int diff, best_diff;
const struct fb_videomode *vmode;
long gap;
best_id = 0;
best_diff = INT_MAX;
pr_debug("%s: wanted %u [%u] %u x %u [%u] %u\n", __func__,
var->left_margin, var->xres, var->right_margin,
var->upper_margin, var->yres, var->lower_margin);
for (id = PS3AV_MODE_480I; id <= PS3AV_MODE_WUXGA; id++) {
vmode = ps3fb_native_vmode(id);
diff = ps3fb_cmp_mode(vmode, var);
pr_debug("%s: mode %u: %u [%u] %u x %u [%u] %u: diff = %d\n",
__func__, id, vmode->left_margin, vmode->xres,
vmode->right_margin, vmode->upper_margin,
vmode->yres, vmode->lower_margin, diff);
if (diff < 0)
continue;
if (diff < best_diff) {
best_id = id;
if (!diff)
break;
best_diff = diff;
}
}
if (!best_id) {
pr_debug("%s: no suitable mode found\n", __func__);
return 0;
}
id = best_id;
vmode = ps3fb_native_vmode(id);
*ddr_line_length = vmode->xres * BPP;
/* minimum resolution */
if (!var->xres)
var->xres = 1;
if (!var->yres)
var->yres = 1;
/* minimum virtual resolution */
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
/* minimum margins */
if (var->left_margin < vmode->left_margin)
var->left_margin = vmode->left_margin;
if (var->right_margin < vmode->right_margin)
var->right_margin = vmode->right_margin;
if (var->upper_margin < vmode->upper_margin)
var->upper_margin = vmode->upper_margin;
if (var->lower_margin < vmode->lower_margin)
var->lower_margin = vmode->lower_margin;
/* extra margins */
gap = ((long)vmode->left_margin + (long)vmode->xres +
(long)vmode->right_margin) -
((long)var->left_margin + (long)var->xres +
(long)var->right_margin);
if (gap > 0) {
var->left_margin += gap/2;
var->right_margin += (gap+1)/2;
pr_debug("%s: rounded up H to %u [%u] %u\n", __func__,
var->left_margin, var->xres, var->right_margin);
}
gap = ((long)vmode->upper_margin + (long)vmode->yres +
(long)vmode->lower_margin) -
((long)var->upper_margin + (long)var->yres +
(long)var->lower_margin);
if (gap > 0) {
var->upper_margin += gap/2;
var->lower_margin += (gap+1)/2;
pr_debug("%s: rounded up V to %u [%u] %u\n", __func__,
var->upper_margin, var->yres, var->lower_margin);
}
/* fixed fields */
var->pixclock = vmode->pixclock;
var->hsync_len = vmode->hsync_len;
var->vsync_len = vmode->vsync_len;
var->sync = vmode->sync;
if (ps3_compare_firmware_version(1, 9, 0) >= 0) {
*xdr_line_length = GPU_ALIGN_UP(var->xres_virtual * BPP);
if (*xdr_line_length > GPU_MAX_LINE_LENGTH)
*xdr_line_length = GPU_MAX_LINE_LENGTH;
} else
*xdr_line_length = *ddr_line_length;
if (vmode->sync & FB_SYNC_BROADCAST) {
/* Full broadcast modes have the full mode bit set */
if (vmode->xres == var->xres && vmode->yres == var->yres)
id |= PS3AV_MODE_FULL;
}
pr_debug("%s: mode %u\n", __func__, id);
return id;
}
static void ps3fb_sync_image(struct device *dev, u64 frame_offset,
u64 dst_offset, u64 src_offset, u32 width,
u32 height, u32 dst_line_length,
u32 src_line_length)
{
int status;
u64 line_length;
line_length = dst_line_length;
if (src_line_length != dst_line_length)
line_length |= (u64)src_line_length << 32;
src_offset += GPU_FB_START;
mutex_lock(&ps3_gpu_mutex);
status = lv1_gpu_fb_blit(ps3fb.context_handle, dst_offset,
GPU_IOIF + src_offset,
L1GPU_FB_BLIT_WAIT_FOR_COMPLETION |
(width << 16) | height,
line_length);
mutex_unlock(&ps3_gpu_mutex);
if (status)
dev_err(dev, "%s: lv1_gpu_fb_blit failed: %d\n", __func__,
status);
#ifdef HEAD_A
status = lv1_gpu_display_flip(ps3fb.context_handle, 0, frame_offset);
if (status)
dev_err(dev, "%s: lv1_gpu_display_flip failed: %d\n", __func__,
status);
#endif
#ifdef HEAD_B
status = lv1_gpu_display_flip(ps3fb.context_handle, 1, frame_offset);
if (status)
dev_err(dev, "%s: lv1_gpu_display_flip failed: %d\n", __func__,
status);
#endif
}
static int ps3fb_sync(struct fb_info *info, u32 frame)
{
struct ps3fb_par *par = info->par;
int error = 0;
u64 ddr_base, xdr_base;
if (frame > par->num_frames - 1) {
dev_dbg(info->device, "%s: invalid frame number (%u)\n",
__func__, frame);
error = -EINVAL;
goto out;
}
xdr_base = frame * par->xdr_frame_size;
ddr_base = frame * par->ddr_frame_size;
ps3fb_sync_image(info->device, ddr_base + par->full_offset,
ddr_base + par->fb_offset, xdr_base + par->pan_offset,
par->width, par->height, par->ddr_line_length,
info->fix.line_length);
out:
return error;
}
static int ps3fb_open(struct fb_info *info, int user)
{
atomic_inc(&ps3fb.f_count);
return 0;
}
static int ps3fb_release(struct fb_info *info, int user)
{
if (atomic_dec_and_test(&ps3fb.f_count)) {
if (atomic_read(&ps3fb.ext_flip)) {
atomic_set(&ps3fb.ext_flip, 0);
if (console_trylock()) {
ps3fb_sync(info, 0); /* single buffer */
console_unlock();
}
}
}
return 0;
}
/*
* Setting the video mode has been split into two parts.
* First part, xxxfb_check_var, must not write anything
* to hardware, it should only verify and adjust var.
* This means it doesn't alter par but it does use hardware
* data from it to check this var.
*/
static int ps3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
u32 xdr_line_length, ddr_line_length;
int mode;
mode = ps3fb_find_mode(var, &ddr_line_length, &xdr_line_length);
if (!mode)
return -EINVAL;
/* Virtual screen */
if (var->xres_virtual > xdr_line_length / BPP) {
dev_dbg(info->device,
"Horizontal virtual screen size too large\n");
return -EINVAL;
}
if (var->xoffset + var->xres > var->xres_virtual ||
var->yoffset + var->yres > var->yres_virtual) {
dev_dbg(info->device, "panning out-of-range\n");
return -EINVAL;
}
/* We support ARGB8888 only */
if (var->bits_per_pixel > 32 || var->grayscale ||
var->red.offset > 16 || var->green.offset > 8 ||
var->blue.offset > 0 || var->transp.offset > 24 ||
var->red.length > 8 || var->green.length > 8 ||
var->blue.length > 8 || var->transp.length > 8 ||
var->red.msb_right || var->green.msb_right ||
var->blue.msb_right || var->transp.msb_right || var->nonstd) {
dev_dbg(info->device, "We support ARGB8888 only\n");
return -EINVAL;
}
var->bits_per_pixel = 32;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->transp.offset = 24;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.length = 8;
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
/* Rotation is not supported */
if (var->rotate) {
dev_dbg(info->device, "Rotation is not supported\n");
return -EINVAL;
}
/* Memory limit */
if (var->yres_virtual * xdr_line_length > info->fix.smem_len) {
dev_dbg(info->device, "Not enough memory\n");
return -ENOMEM;
}
var->height = -1;
var->width = -1;
return 0;
}
/*
* This routine actually sets the video mode.
*/
static int ps3fb_set_par(struct fb_info *info)
{
struct ps3fb_par *par = info->par;
unsigned int mode, ddr_line_length, xdr_line_length, lines, maxlines;
unsigned int ddr_xoff, ddr_yoff, offset;
const struct fb_videomode *vmode;
u64 dst;
mode = ps3fb_find_mode(&info->var, &ddr_line_length, &xdr_line_length);
if (!mode)
return -EINVAL;
vmode = ps3fb_native_vmode(mode & PS3AV_MODE_MASK);
info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
info->fix.line_length = xdr_line_length;
par->ddr_line_length = ddr_line_length;
par->ddr_frame_size = vmode->yres * ddr_line_length;
par->xdr_frame_size = info->var.yres_virtual * xdr_line_length;
par->num_frames = info->fix.smem_len /
max(par->ddr_frame_size, par->xdr_frame_size);
/* Keep the special bits we cannot set using fb_var_screeninfo */
par->new_mode_id = (par->new_mode_id & ~PS3AV_MODE_MASK) | mode;
par->width = info->var.xres;
par->height = info->var.yres;
/* Start of the virtual frame buffer (relative to fullscreen) */
ddr_xoff = info->var.left_margin - vmode->left_margin;
ddr_yoff = info->var.upper_margin - vmode->upper_margin;
offset = ddr_yoff * ddr_line_length + ddr_xoff * BPP;
par->fb_offset = GPU_ALIGN_UP(offset);
par->full_offset = par->fb_offset - offset;
par->pan_offset = info->var.yoffset * xdr_line_length +
info->var.xoffset * BPP;
if (par->new_mode_id != par->mode_id) {
if (ps3av_set_video_mode(par->new_mode_id)) {
par->new_mode_id = par->mode_id;
return -EINVAL;
}
par->mode_id = par->new_mode_id;
}
/* Clear XDR frame buffer memory */
memset(info->screen_buffer, 0, info->fix.smem_len);
/* Clear DDR frame buffer memory */
lines = vmode->yres * par->num_frames;
if (par->full_offset)
lines++;
maxlines = info->fix.smem_len / ddr_line_length;
for (dst = 0; lines; dst += maxlines * ddr_line_length) {
unsigned int l = min(lines, maxlines);
ps3fb_sync_image(info->device, 0, dst, 0, vmode->xres, l,
ddr_line_length, ddr_line_length);
lines -= l;
}
return 0;
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int ps3fb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
if (regno >= 16)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
transp >>= 8;
((u32 *)info->pseudo_palette)[regno] = transp << 24 | red << 16 |
green << 8 | blue;
return 0;
}
static int ps3fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct ps3fb_par *par = info->par;
par->pan_offset = var->yoffset * info->fix.line_length +
var->xoffset * BPP;
return 0;
}
/*
* As we have a virtual frame buffer, we need our own mmap function
*/
static int ps3fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
int r;
r = vm_iomap_memory(vma, info->fix.smem_start, info->fix.smem_len);
dev_dbg(info->device, "ps3fb: mmap framebuffer P(%lx)->V(%lx)\n",
info->fix.smem_start + (vma->vm_pgoff << PAGE_SHIFT),
vma->vm_start);
return r;
}
/*
* Blank the display
*/
static int ps3fb_blank(int blank, struct fb_info *info)
{
int retval;
dev_dbg(info->device, "%s: blank:%d\n", __func__, blank);
switch (blank) {
case FB_BLANK_POWERDOWN:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_NORMAL:
retval = ps3av_video_mute(1); /* mute on */
if (!retval)
ps3fb.is_blanked = 1;
break;
default: /* unblank */
retval = ps3av_video_mute(0); /* mute off */
if (!retval)
ps3fb.is_blanked = 0;
break;
}
return retval;
}
static int ps3fb_get_vblank(struct fb_vblank *vblank)
{
memset(vblank, 0, sizeof(*vblank));
vblank->flags = FB_VBLANK_HAVE_VSYNC;
return 0;
}
static int ps3fb_wait_for_vsync(u32 crtc)
{
int ret;
u64 count;
count = ps3fb.vblank_count;
ret = wait_event_interruptible_timeout(ps3fb.wait_vsync,
count != ps3fb.vblank_count,
HZ / 10);
if (!ret)
return -ETIMEDOUT;
return 0;
}
/*
* ioctl
*/
static int ps3fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
void __user *argp = (void __user *)arg;
u32 val;
int retval = -EFAULT;
switch (cmd) {
case FBIOGET_VBLANK:
{
struct fb_vblank vblank;
dev_dbg(info->device, "FBIOGET_VBLANK:\n");
retval = ps3fb_get_vblank(&vblank);
if (retval)
break;
if (copy_to_user(argp, &vblank, sizeof(vblank)))
retval = -EFAULT;
break;
}
case FBIO_WAITFORVSYNC:
{
u32 crt;
dev_dbg(info->device, "FBIO_WAITFORVSYNC:\n");
if (get_user(crt, (u32 __user *) arg))
break;
retval = ps3fb_wait_for_vsync(crt);
break;
}
case PS3FB_IOCTL_SETMODE:
{
struct ps3fb_par *par = info->par;
const struct fb_videomode *vmode;
struct fb_var_screeninfo var;
if (copy_from_user(&val, argp, sizeof(val)))
break;
if (!(val & PS3AV_MODE_MASK)) {
u32 id = ps3av_get_auto_mode();
if (id > 0)
val = (val & ~PS3AV_MODE_MASK) | id;
}
dev_dbg(info->device, "PS3FB_IOCTL_SETMODE:%x\n", val);
retval = -EINVAL;
vmode = ps3fb_vmode(val);
if (vmode) {
var = info->var;
fb_videomode_to_var(&var, vmode);
console_lock();
/* Force, in case only special bits changed */
var.activate |= FB_ACTIVATE_FORCE;
par->new_mode_id = val;
retval = fb_set_var(info, &var);
if (!retval)
fbcon_update_vcs(info, var.activate & FB_ACTIVATE_ALL);
console_unlock();
}
break;
}
case PS3FB_IOCTL_GETMODE:
val = ps3av_get_mode();
dev_dbg(info->device, "PS3FB_IOCTL_GETMODE:%x\n", val);
if (!copy_to_user(argp, &val, sizeof(val)))
retval = 0;
break;
case PS3FB_IOCTL_SCREENINFO:
{
struct ps3fb_par *par = info->par;
struct ps3fb_ioctl_res res;
dev_dbg(info->device, "PS3FB_IOCTL_SCREENINFO:\n");
res.xres = info->fix.line_length / BPP;
res.yres = info->var.yres_virtual;
res.xoff = (res.xres - info->var.xres) / 2;
res.yoff = (res.yres - info->var.yres) / 2;
res.num_frames = par->num_frames;
if (!copy_to_user(argp, &res, sizeof(res)))
retval = 0;
break;
}
case PS3FB_IOCTL_ON:
dev_dbg(info->device, "PS3FB_IOCTL_ON:\n");
atomic_inc(&ps3fb.ext_flip);
retval = 0;
break;
case PS3FB_IOCTL_OFF:
dev_dbg(info->device, "PS3FB_IOCTL_OFF:\n");
atomic_dec_if_positive(&ps3fb.ext_flip);
retval = 0;
break;
case PS3FB_IOCTL_FSEL:
if (copy_from_user(&val, argp, sizeof(val)))
break;
dev_dbg(info->device, "PS3FB_IOCTL_FSEL:%d\n", val);
console_lock();
retval = ps3fb_sync(info, val);
console_unlock();
break;
default:
retval = -ENOIOCTLCMD;
break;
}
return retval;
}
static int ps3fbd(void *arg)
{
struct fb_info *info = arg;
set_freezable();
while (!kthread_should_stop()) {
try_to_freeze();
set_current_state(TASK_INTERRUPTIBLE);
if (ps3fb.is_kicked) {
ps3fb.is_kicked = 0;
console_lock();
ps3fb_sync(info, 0); /* single buffer */
console_unlock();
}
schedule();
}
return 0;
}
static irqreturn_t ps3fb_vsync_interrupt(int irq, void *ptr)
{
struct device *dev = ptr;
u64 v1;
int status;
struct display_head *head = &ps3fb.dinfo->display_head[1];
status = lv1_gpu_context_intr(ps3fb.context_handle, &v1);
if (status) {
dev_err(dev, "%s: lv1_gpu_context_intr failed: %d\n", __func__,
status);
return IRQ_NONE;
}
if (v1 & (1 << GPU_INTR_STATUS_VSYNC_1)) {
/* VSYNC */
ps3fb.vblank_count = head->vblank_count;
if (ps3fb.task && !ps3fb.is_blanked &&
!atomic_read(&ps3fb.ext_flip)) {
ps3fb.is_kicked = 1;
wake_up_process(ps3fb.task);
}
wake_up_interruptible(&ps3fb.wait_vsync);
}
return IRQ_HANDLED;
}
static const struct fb_ops ps3fb_ops = {
.owner = THIS_MODULE,
.fb_open = ps3fb_open,
.fb_release = ps3fb_release,
.fb_read = fb_sys_read,
.fb_write = fb_sys_write,
.fb_check_var = ps3fb_check_var,
.fb_set_par = ps3fb_set_par,
.fb_setcolreg = ps3fb_setcolreg,
.fb_pan_display = ps3fb_pan_display,
.fb_fillrect = sys_fillrect,
.fb_copyarea = sys_copyarea,
.fb_imageblit = sys_imageblit,
.fb_mmap = ps3fb_mmap,
.fb_blank = ps3fb_blank,
.fb_ioctl = ps3fb_ioctl,
.fb_compat_ioctl = ps3fb_ioctl
};
static const struct fb_fix_screeninfo ps3fb_fix = {
.id = DEVICE_NAME,
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.accel = FB_ACCEL_NONE,
};
static int ps3fb_probe(struct ps3_system_bus_device *dev)
{
struct fb_info *info;
struct ps3fb_par *par;
int retval;
u64 ddr_lpar = 0;
u64 lpar_dma_control = 0;
u64 lpar_driver_info = 0;
u64 lpar_reports = 0;
u64 lpar_reports_size = 0;
u64 xdr_lpar;
struct gpu_driver_info *dinfo;
void *fb_start;
int status;
struct task_struct *task;
unsigned long max_ps3fb_size;
if (ps3fb_videomemory.size < GPU_CMD_BUF_SIZE) {
dev_err(&dev->core, "%s: Not enough video memory\n", __func__);
return -ENOMEM;
}
retval = ps3_open_hv_device(dev);
if (retval) {
dev_err(&dev->core, "%s: ps3_open_hv_device failed\n",
__func__);
goto err;
}
if (!ps3fb_mode)
ps3fb_mode = ps3av_get_mode();
dev_dbg(&dev->core, "ps3fb_mode: %d\n", ps3fb_mode);
atomic_set(&ps3fb.f_count, -1); /* fbcon opens ps3fb */
atomic_set(&ps3fb.ext_flip, 0); /* for flip with vsync */
init_waitqueue_head(&ps3fb.wait_vsync);
#ifdef HEAD_A
status = lv1_gpu_display_sync(0x0, 0, L1GPU_DISPLAY_SYNC_VSYNC);
if (status) {
dev_err(&dev->core, "%s: lv1_gpu_display_sync failed: %d\n",
__func__, status);
retval = -ENODEV;
goto err_close_device;
}
#endif
#ifdef HEAD_B
status = lv1_gpu_display_sync(0x0, 1, L1GPU_DISPLAY_SYNC_VSYNC);
if (status) {
dev_err(&dev->core, "%s: lv1_gpu_display_sync failed: %d\n",
__func__, status);
retval = -ENODEV;
goto err_close_device;
}
#endif
max_ps3fb_size = ALIGN(GPU_IOIF, 256*1024*1024) - GPU_IOIF;
if (ps3fb_videomemory.size > max_ps3fb_size) {
dev_info(&dev->core, "Limiting ps3fb mem size to %lu bytes\n",
max_ps3fb_size);
ps3fb_videomemory.size = max_ps3fb_size;
}
/* get gpu context handle */
status = lv1_gpu_memory_allocate(ps3fb_videomemory.size, 0, 0, 0, 0,
&ps3fb.memory_handle, &ddr_lpar);
if (status) {
dev_err(&dev->core, "%s: lv1_gpu_memory_allocate failed: %d\n",
__func__, status);
retval = -ENOMEM;
goto err_close_device;
}
dev_dbg(&dev->core, "ddr:lpar:0x%llx\n", ddr_lpar);
status = lv1_gpu_context_allocate(ps3fb.memory_handle, 0,
&ps3fb.context_handle,
&lpar_dma_control, &lpar_driver_info,
&lpar_reports, &lpar_reports_size);
if (status) {
dev_err(&dev->core,
"%s: lv1_gpu_context_allocate failed: %d\n", __func__,
status);
retval = -ENOMEM;
goto err_gpu_memory_free;
}
/* vsync interrupt */
dinfo = (void __force *)ioremap(lpar_driver_info, 128 * 1024);
if (!dinfo) {
dev_err(&dev->core, "%s: ioremap failed\n", __func__);
retval = -ENOMEM;
goto err_gpu_context_free;
}
ps3fb.dinfo = dinfo;
dev_dbg(&dev->core, "version_driver:%x\n", dinfo->version_driver);
dev_dbg(&dev->core, "irq outlet:%x\n", dinfo->irq.irq_outlet);
dev_dbg(&dev->core, "version_gpu: %x memory_size: %x ch: %x "
"core_freq: %d mem_freq:%d\n", dinfo->version_gpu,
dinfo->memory_size, dinfo->hardware_channel,
dinfo->nvcore_frequency/1000000,
dinfo->memory_frequency/1000000);
if (dinfo->version_driver != GPU_DRIVER_INFO_VERSION) {
dev_err(&dev->core, "%s: version_driver err:%x\n", __func__,
dinfo->version_driver);
retval = -EINVAL;
goto err_iounmap_dinfo;
}
retval = ps3_irq_plug_setup(PS3_BINDING_CPU_ANY, dinfo->irq.irq_outlet,
&ps3fb.irq_no);
if (retval) {
dev_err(&dev->core, "%s: ps3_alloc_irq failed %d\n", __func__,
retval);
goto err_iounmap_dinfo;
}
retval = request_irq(ps3fb.irq_no, ps3fb_vsync_interrupt,
0, DEVICE_NAME, &dev->core);
if (retval) {
dev_err(&dev->core, "%s: request_irq failed %d\n", __func__,
retval);
goto err_destroy_plug;
}
dinfo->irq.mask = (1 << GPU_INTR_STATUS_VSYNC_1) |
(1 << GPU_INTR_STATUS_FLIP_1);
/* Clear memory to prevent kernel info leakage into userspace */
memset(ps3fb_videomemory.address, 0, ps3fb_videomemory.size);
xdr_lpar = ps3_mm_phys_to_lpar(__pa(ps3fb_videomemory.address));
status = lv1_gpu_context_iomap(ps3fb.context_handle, GPU_IOIF,
xdr_lpar, ps3fb_videomemory.size,
CBE_IOPTE_PP_W | CBE_IOPTE_PP_R |
CBE_IOPTE_M);
if (status) {
dev_err(&dev->core, "%s: lv1_gpu_context_iomap failed: %d\n",
__func__, status);
retval = -ENXIO;
goto err_free_irq;
}
dev_dbg(&dev->core, "video:%p ioif:%lx lpar:%llx size:%lx\n",
ps3fb_videomemory.address, GPU_IOIF, xdr_lpar,
ps3fb_videomemory.size);
status = lv1_gpu_fb_setup(ps3fb.context_handle, xdr_lpar,
GPU_CMD_BUF_SIZE, GPU_IOIF);
if (status) {
dev_err(&dev->core, "%s: lv1_gpu_fb_setup failed: %d\n",
__func__, status);
retval = -ENXIO;
goto err_context_unmap;
}
info = framebuffer_alloc(sizeof(struct ps3fb_par), &dev->core);
if (!info) {
retval = -ENOMEM;
goto err_context_fb_close;
}
par = info->par;
par->mode_id = ~ps3fb_mode; /* != ps3fb_mode, to trigger change */
par->new_mode_id = ps3fb_mode;
par->num_frames = 1;
info->fbops = &ps3fb_ops;
info->fix = ps3fb_fix;
/*
* The GPU command buffer is at the start of video memory
* As we don't use the full command buffer, we can put the actual
* frame buffer at offset GPU_FB_START and save some precious XDR
* memory
*/
fb_start = ps3fb_videomemory.address + GPU_FB_START;
info->screen_buffer = fb_start;
info->fix.smem_start = __pa(fb_start);
info->fix.smem_len = ps3fb_videomemory.size - GPU_FB_START;
info->pseudo_palette = par->pseudo_palette;
info->flags = FBINFO_READS_FAST |
FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
retval = fb_alloc_cmap(&info->cmap, 256, 0);
if (retval < 0)
goto err_framebuffer_release;
if (!fb_find_mode(&info->var, info, mode_option, ps3fb_modedb,
ARRAY_SIZE(ps3fb_modedb),
ps3fb_vmode(par->new_mode_id), 32)) {
retval = -EINVAL;
goto err_fb_dealloc;
}
fb_videomode_to_modelist(ps3fb_modedb, ARRAY_SIZE(ps3fb_modedb),
&info->modelist);
retval = register_framebuffer(info);
if (retval < 0)
goto err_fb_dealloc;
ps3_system_bus_set_drvdata(dev, info);
fb_info(info, "using %u KiB of video memory\n", info->fix.smem_len >> 10);
task = kthread_run(ps3fbd, info, DEVICE_NAME);
if (IS_ERR(task)) {
retval = PTR_ERR(task);
goto err_unregister_framebuffer;
}
ps3fb.task = task;
return 0;
err_unregister_framebuffer:
unregister_framebuffer(info);
err_fb_dealloc:
fb_dealloc_cmap(&info->cmap);
err_framebuffer_release:
framebuffer_release(info);
err_context_fb_close:
lv1_gpu_fb_close(ps3fb.context_handle);
err_context_unmap:
lv1_gpu_context_iomap(ps3fb.context_handle, GPU_IOIF, xdr_lpar,
ps3fb_videomemory.size, CBE_IOPTE_M);
err_free_irq:
free_irq(ps3fb.irq_no, &dev->core);
err_destroy_plug:
ps3_irq_plug_destroy(ps3fb.irq_no);
err_iounmap_dinfo:
iounmap((u8 __force __iomem *)ps3fb.dinfo);
err_gpu_context_free:
lv1_gpu_context_free(ps3fb.context_handle);
err_gpu_memory_free:
lv1_gpu_memory_free(ps3fb.memory_handle);
err_close_device:
ps3_close_hv_device(dev);
err:
return retval;
}
static void ps3fb_shutdown(struct ps3_system_bus_device *dev)
{
struct fb_info *info = ps3_system_bus_get_drvdata(dev);
u64 xdr_lpar = ps3_mm_phys_to_lpar(__pa(ps3fb_videomemory.address));
dev_dbg(&dev->core, " -> %s:%d\n", __func__, __LINE__);
atomic_inc(&ps3fb.ext_flip); /* flip off */
ps3fb.dinfo->irq.mask = 0;
if (ps3fb.task) {
struct task_struct *task = ps3fb.task;
ps3fb.task = NULL;
kthread_stop(task);
}
if (ps3fb.irq_no) {
free_irq(ps3fb.irq_no, &dev->core);
ps3_irq_plug_destroy(ps3fb.irq_no);
}
if (info) {
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
ps3_system_bus_set_drvdata(dev, NULL);
}
iounmap((u8 __force __iomem *)ps3fb.dinfo);
lv1_gpu_fb_close(ps3fb.context_handle);
lv1_gpu_context_iomap(ps3fb.context_handle, GPU_IOIF, xdr_lpar,
ps3fb_videomemory.size, CBE_IOPTE_M);
lv1_gpu_context_free(ps3fb.context_handle);
lv1_gpu_memory_free(ps3fb.memory_handle);
ps3_close_hv_device(dev);
dev_dbg(&dev->core, " <- %s:%d\n", __func__, __LINE__);
}
static struct ps3_system_bus_driver ps3fb_driver = {
.match_id = PS3_MATCH_ID_GPU,
.match_sub_id = PS3_MATCH_SUB_ID_GPU_FB,
.core.name = DEVICE_NAME,
.core.owner = THIS_MODULE,
.probe = ps3fb_probe,
.remove = ps3fb_shutdown,
.shutdown = ps3fb_shutdown,
};
static int __init ps3fb_setup(void)
{
char *options;
#ifdef MODULE
return 0;
#endif
if (fb_get_options(DEVICE_NAME, &options))
return -ENXIO;
if (!options || !*options)
return 0;
while (1) {
char *this_opt = strsep(&options, ",");
if (!this_opt)
break;
if (!*this_opt)
continue;
if (!strncmp(this_opt, "mode:", 5))
ps3fb_mode = simple_strtoul(this_opt + 5, NULL, 0);
else
mode_option = this_opt;
}
return 0;
}
static int __init ps3fb_init(void)
{
if (!ps3fb_videomemory.address || ps3fb_setup())
return -ENXIO;
return ps3_system_bus_driver_register(&ps3fb_driver);
}
static void __exit ps3fb_exit(void)
{
pr_debug(" -> %s:%d\n", __func__, __LINE__);
ps3_system_bus_driver_unregister(&ps3fb_driver);
pr_debug(" <- %s:%d\n", __func__, __LINE__);
}
module_init(ps3fb_init);
module_exit(ps3fb_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("PS3 GPU Frame Buffer Driver");
MODULE_AUTHOR("Sony Computer Entertainment Inc.");
MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_FB);
| linux-master | drivers/video/fbdev/ps3fb.c |
// SPDX-License-Identifier: GPL-2.0-only
/* p9100.c: P9100 frame buffer driver
*
* Copyright (C) 2003, 2006 David S. Miller ([email protected])
* Copyright 1999 Derrick J Brashear ([email protected])
*
* Driver layout based loosely on tgafb.c, see that file for credits.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/fbio.h>
#include "sbuslib.h"
/*
* Local functions.
*/
static int p9100_setcolreg(unsigned, unsigned, unsigned, unsigned,
unsigned, struct fb_info *);
static int p9100_blank(int, struct fb_info *);
static int p9100_mmap(struct fb_info *, struct vm_area_struct *);
static int p9100_ioctl(struct fb_info *, unsigned int, unsigned long);
/*
* Frame buffer operations
*/
static const struct fb_ops p9100_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = p9100_setcolreg,
.fb_blank = p9100_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = p9100_mmap,
.fb_ioctl = p9100_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = sbusfb_compat_ioctl,
#endif
};
/* P9100 control registers */
#define P9100_SYSCTL_OFF 0x0UL
#define P9100_VIDEOCTL_OFF 0x100UL
#define P9100_VRAMCTL_OFF 0x180UL
#define P9100_RAMDAC_OFF 0x200UL
#define P9100_VIDEOCOPROC_OFF 0x400UL
/* P9100 command registers */
#define P9100_CMD_OFF 0x0UL
/* P9100 framebuffer memory */
#define P9100_FB_OFF 0x0UL
/* 3 bits: 2=8bpp 3=16bpp 5=32bpp 7=24bpp */
#define SYS_CONFIG_PIXELSIZE_SHIFT 26
#define SCREENPAINT_TIMECTL1_ENABLE_VIDEO 0x20 /* 0 = off, 1 = on */
struct p9100_regs {
/* Registers for the system control */
u32 sys_base;
u32 sys_config;
u32 sys_intr;
u32 sys_int_ena;
u32 sys_alt_rd;
u32 sys_alt_wr;
u32 sys_xxx[58];
/* Registers for the video control */
u32 vid_base;
u32 vid_hcnt;
u32 vid_htotal;
u32 vid_hsync_rise;
u32 vid_hblank_rise;
u32 vid_hblank_fall;
u32 vid_hcnt_preload;
u32 vid_vcnt;
u32 vid_vlen;
u32 vid_vsync_rise;
u32 vid_vblank_rise;
u32 vid_vblank_fall;
u32 vid_vcnt_preload;
u32 vid_screenpaint_addr;
u32 vid_screenpaint_timectl1;
u32 vid_screenpaint_qsfcnt;
u32 vid_screenpaint_timectl2;
u32 vid_xxx[15];
/* Registers for the video control */
u32 vram_base;
u32 vram_memcfg;
u32 vram_refresh_pd;
u32 vram_refresh_cnt;
u32 vram_raslo_max;
u32 vram_raslo_cur;
u32 pwrup_cfg;
u32 vram_xxx[25];
/* Registers for IBM RGB528 Palette */
u32 ramdac_cmap_wridx;
u32 ramdac_palette_data;
u32 ramdac_pixel_mask;
u32 ramdac_palette_rdaddr;
u32 ramdac_idx_lo;
u32 ramdac_idx_hi;
u32 ramdac_idx_data;
u32 ramdac_idx_ctl;
u32 ramdac_xxx[1784];
};
struct p9100_cmd_parameng {
u32 parameng_status;
u32 parameng_bltcmd;
u32 parameng_quadcmd;
};
struct p9100_par {
spinlock_t lock;
struct p9100_regs __iomem *regs;
u32 flags;
#define P9100_FLAG_BLANKED 0x00000001
unsigned long which_io;
};
/**
* p9100_setcolreg - Optional function. Sets a color register.
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*/
static int p9100_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct p9100_par *par = (struct p9100_par *) info->par;
struct p9100_regs __iomem *regs = par->regs;
unsigned long flags;
if (regno >= 256)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
spin_lock_irqsave(&par->lock, flags);
sbus_writel((regno << 16), ®s->ramdac_cmap_wridx);
sbus_writel((red << 16), ®s->ramdac_palette_data);
sbus_writel((green << 16), ®s->ramdac_palette_data);
sbus_writel((blue << 16), ®s->ramdac_palette_data);
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
/**
* p9100_blank - Optional function. Blanks the display.
* @blank: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int
p9100_blank(int blank, struct fb_info *info)
{
struct p9100_par *par = (struct p9100_par *) info->par;
struct p9100_regs __iomem *regs = par->regs;
unsigned long flags;
u32 val;
spin_lock_irqsave(&par->lock, flags);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
val = sbus_readl(®s->vid_screenpaint_timectl1);
val |= SCREENPAINT_TIMECTL1_ENABLE_VIDEO;
sbus_writel(val, ®s->vid_screenpaint_timectl1);
par->flags &= ~P9100_FLAG_BLANKED;
break;
case FB_BLANK_NORMAL: /* Normal blanking */
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
case FB_BLANK_POWERDOWN: /* Poweroff */
val = sbus_readl(®s->vid_screenpaint_timectl1);
val &= ~SCREENPAINT_TIMECTL1_ENABLE_VIDEO;
sbus_writel(val, ®s->vid_screenpaint_timectl1);
par->flags |= P9100_FLAG_BLANKED;
break;
}
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
static struct sbus_mmap_map p9100_mmap_map[] = {
{ CG3_MMAP_OFFSET, 0, SBUS_MMAP_FBSIZE(1) },
{ 0, 0, 0 }
};
static int p9100_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct p9100_par *par = (struct p9100_par *)info->par;
return sbusfb_mmap_helper(p9100_mmap_map,
info->fix.smem_start, info->fix.smem_len,
par->which_io, vma);
}
static int p9100_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
/* Make it look like a cg3. */
return sbusfb_ioctl_helper(cmd, arg, info,
FBTYPE_SUN3COLOR, 8, info->fix.smem_len);
}
/*
* Initialisation
*/
static void p9100_init_fix(struct fb_info *info, int linebytes, struct device_node *dp)
{
snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = linebytes;
info->fix.accel = FB_ACCEL_SUN_CGTHREE;
}
static int p9100_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct fb_info *info;
struct p9100_par *par;
int linebytes, err;
info = framebuffer_alloc(sizeof(struct p9100_par), &op->dev);
err = -ENOMEM;
if (!info)
goto out_err;
par = info->par;
spin_lock_init(&par->lock);
/* This is the framebuffer and the only resource apps can mmap. */
info->fix.smem_start = op->resource[2].start;
par->which_io = op->resource[2].flags & IORESOURCE_BITS;
sbusfb_fill_var(&info->var, dp, 8);
info->var.red.length = 8;
info->var.green.length = 8;
info->var.blue.length = 8;
linebytes = of_getintprop_default(dp, "linebytes", info->var.xres);
info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
par->regs = of_ioremap(&op->resource[0], 0,
sizeof(struct p9100_regs), "p9100 regs");
if (!par->regs)
goto out_release_fb;
info->fbops = &p9100_ops;
info->screen_base = of_ioremap(&op->resource[2], 0,
info->fix.smem_len, "p9100 ram");
if (!info->screen_base)
goto out_unmap_regs;
p9100_blank(FB_BLANK_UNBLANK, info);
if (fb_alloc_cmap(&info->cmap, 256, 0))
goto out_unmap_screen;
p9100_init_fix(info, linebytes, dp);
err = register_framebuffer(info);
if (err < 0)
goto out_dealloc_cmap;
fb_set_cmap(&info->cmap, info);
dev_set_drvdata(&op->dev, info);
printk(KERN_INFO "%pOF: p9100 at %lx:%lx\n",
dp,
par->which_io, info->fix.smem_start);
return 0;
out_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
out_unmap_screen:
of_iounmap(&op->resource[2], info->screen_base, info->fix.smem_len);
out_unmap_regs:
of_iounmap(&op->resource[0], par->regs, sizeof(struct p9100_regs));
out_release_fb:
framebuffer_release(info);
out_err:
return err;
}
static void p9100_remove(struct platform_device *op)
{
struct fb_info *info = dev_get_drvdata(&op->dev);
struct p9100_par *par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
of_iounmap(&op->resource[0], par->regs, sizeof(struct p9100_regs));
of_iounmap(&op->resource[2], info->screen_base, info->fix.smem_len);
framebuffer_release(info);
}
static const struct of_device_id p9100_match[] = {
{
.name = "p9100",
},
{},
};
MODULE_DEVICE_TABLE(of, p9100_match);
static struct platform_driver p9100_driver = {
.driver = {
.name = "p9100",
.of_match_table = p9100_match,
},
.probe = p9100_probe,
.remove_new = p9100_remove,
};
static int __init p9100_init(void)
{
if (fb_get_options("p9100fb", NULL))
return -ENODEV;
return platform_driver_register(&p9100_driver);
}
static void __exit p9100_exit(void)
{
platform_driver_unregister(&p9100_driver);
}
module_init(p9100_init);
module_exit(p9100_exit);
MODULE_DESCRIPTION("framebuffer driver for P9100 chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/p9100.c |
/*
* linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV
* with ICS 5342 dac (it is easy to add support for different dacs).
*
* Copyright (c) 2007 Ondrej Zajicek <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Code is based on s3fb
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/svga.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
#include <video/vga.h>
struct arkfb_info {
int mclk_freq;
int wc_cookie;
struct dac_info *dac;
struct vgastate state;
struct mutex open_lock;
unsigned int ref_count;
u32 pseudo_palette[16];
};
/* ------------------------------------------------------------------------- */
static const struct svga_fb_format arkfb_formats[] = {
{ 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8},
{ 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
{ 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
{ 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
{16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
{16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
{24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8},
{32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
SVGA_FORMAT_END
};
/* CRT timing register sets */
static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END};
static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END};
static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END};
static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END};
static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END};
static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END};
static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END};
static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END};
// const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END};
static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END};
static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END};
static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END};
static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END};
static const struct svga_timing_regs ark_timing_regs = {
ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs,
ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs,
ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs,
ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs,
};
/* ------------------------------------------------------------------------- */
/* Module parameters */
static char *mode_option = "640x480-8@60";
MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("fbdev driver for ARK 2000PV");
module_param(mode_option, charp, 0444);
MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
module_param_named(mode, mode_option, charp, 0444);
MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
static int threshold = 4;
module_param(threshold, int, 0644);
MODULE_PARM_DESC(threshold, "FIFO threshold");
/* ------------------------------------------------------------------------- */
static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map)
{
const u8 *font = map->data;
u8 __iomem *fb = (u8 __iomem *)info->screen_base;
int i, c;
if ((map->width != 8) || (map->height != 16) ||
(map->depth != 1) || (map->length != 256)) {
fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
map->width, map->height, map->depth, map->length);
return;
}
fb += 2;
for (c = 0; c < map->length; c++) {
for (i = 0; i < map->height; i++) {
fb_writeb(font[i], &fb[i * 4]);
fb_writeb(font[i], &fb[i * 4 + (128 * 8)]);
}
fb += 128;
if ((c % 8) == 7)
fb += 128*8;
font += map->height;
}
}
static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
{
struct arkfb_info *par = info->par;
svga_tilecursor(par->state.vgabase, info, cursor);
}
static struct fb_tile_ops arkfb_tile_ops = {
.fb_settile = arkfb_settile,
.fb_tilecopy = svga_tilecopy,
.fb_tilefill = svga_tilefill,
.fb_tileblit = svga_tileblit,
.fb_tilecursor = arkfb_tilecursor,
.fb_get_tilemax = svga_get_tilemax,
};
/* ------------------------------------------------------------------------- */
/* image data is MSB-first, fb structure is MSB-first too */
static inline u32 expand_color(u32 c)
{
return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
}
/* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
{
u32 fg = expand_color(image->fg_color);
u32 bg = expand_color(image->bg_color);
const u8 *src1, *src;
u8 __iomem *dst1;
u32 __iomem *dst;
u32 val;
int x, y;
src1 = image->data;
dst1 = info->screen_base + (image->dy * info->fix.line_length)
+ ((image->dx / 8) * 4);
for (y = 0; y < image->height; y++) {
src = src1;
dst = (u32 __iomem *) dst1;
for (x = 0; x < image->width; x += 8) {
val = *(src++) * 0x01010101;
val = (val & fg) | (~val & bg);
fb_writel(val, dst++);
}
src1 += image->width / 8;
dst1 += info->fix.line_length;
}
}
/* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
u32 fg = expand_color(rect->color);
u8 __iomem *dst1;
u32 __iomem *dst;
int x, y;
dst1 = info->screen_base + (rect->dy * info->fix.line_length)
+ ((rect->dx / 8) * 4);
for (y = 0; y < rect->height; y++) {
dst = (u32 __iomem *) dst1;
for (x = 0; x < rect->width; x += 8) {
fb_writel(fg, dst++);
}
dst1 += info->fix.line_length;
}
}
/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
static inline u32 expand_pixel(u32 c)
{
return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
}
/* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
{
u32 fg = image->fg_color * 0x11111111;
u32 bg = image->bg_color * 0x11111111;
const u8 *src1, *src;
u8 __iomem *dst1;
u32 __iomem *dst;
u32 val;
int x, y;
src1 = image->data;
dst1 = info->screen_base + (image->dy * info->fix.line_length)
+ ((image->dx / 8) * 4);
for (y = 0; y < image->height; y++) {
src = src1;
dst = (u32 __iomem *) dst1;
for (x = 0; x < image->width; x += 8) {
val = expand_pixel(*(src++));
val = (val & fg) | (~val & bg);
fb_writel(val, dst++);
}
src1 += image->width / 8;
dst1 += info->fix.line_length;
}
}
static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image)
{
if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
&& ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
arkfb_iplan_imageblit(info, image);
else
arkfb_cfb4_imageblit(info, image);
} else
cfb_imageblit(info, image);
}
static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
if ((info->var.bits_per_pixel == 4)
&& ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
&& (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
arkfb_iplan_fillrect(info, rect);
else
cfb_fillrect(info, rect);
}
/* ------------------------------------------------------------------------- */
enum
{
DAC_PSEUDO8_8,
DAC_RGB1555_8,
DAC_RGB0565_8,
DAC_RGB0888_8,
DAC_RGB8888_8,
DAC_PSEUDO8_16,
DAC_RGB1555_16,
DAC_RGB0565_16,
DAC_RGB0888_16,
DAC_RGB8888_16,
DAC_MAX
};
struct dac_ops {
int (*dac_get_mode)(struct dac_info *info);
int (*dac_set_mode)(struct dac_info *info, int mode);
int (*dac_get_freq)(struct dac_info *info, int channel);
int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq);
void (*dac_release)(struct dac_info *info);
};
typedef void (*dac_read_regs_t)(void *data, u8 *code, int count);
typedef void (*dac_write_regs_t)(void *data, u8 *code, int count);
struct dac_info
{
struct dac_ops *dacops;
dac_read_regs_t dac_read_regs;
dac_write_regs_t dac_write_regs;
void *data;
};
static inline void dac_read_regs(struct dac_info *info, u8 *code, int count)
{
info->dac_read_regs(info->data, code, count);
}
static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val)
{
u8 code[2] = {reg, val};
info->dac_write_regs(info->data, code, 1);
}
static inline void dac_write_regs(struct dac_info *info, u8 *code, int count)
{
info->dac_write_regs(info->data, code, count);
}
static inline int dac_set_mode(struct dac_info *info, int mode)
{
return info->dacops->dac_set_mode(info, mode);
}
static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq)
{
return info->dacops->dac_set_freq(info, channel, freq);
}
static inline void dac_release(struct dac_info *info)
{
info->dacops->dac_release(info);
}
/* ------------------------------------------------------------------------- */
/* ICS5342 DAC */
struct ics5342_info
{
struct dac_info dac;
u8 mode;
};
#define DAC_PAR(info) ((struct ics5342_info *) info)
/* LSB is set to distinguish unused slots */
static const u8 ics5342_mode_table[DAC_MAX] = {
[DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61,
[DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31,
[DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71
};
static int ics5342_set_mode(struct dac_info *info, int mode)
{
u8 code;
if (mode >= DAC_MAX)
return -EINVAL;
code = ics5342_mode_table[mode];
if (! code)
return -EINVAL;
dac_write_reg(info, 6, code & 0xF0);
DAC_PAR(info)->mode = mode;
return 0;
}
static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3,
60000, 250000, 14318};
/* pd4 - allow only posdivider 4 (r=2) */
static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2,
60000, 335000, 14318};
/* 270 MHz should be upper bound for VCO clock according to specs,
but that is too restrictive in pd4 case */
static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq)
{
u16 m, n, r;
/* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */
int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16)
? &ics5342_pll_pd4 : &ics5342_pll,
freq, &m, &n, &r, 0);
if (rv < 0) {
return -EINVAL;
} else {
u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)};
dac_write_regs(info, code, 3);
return 0;
}
}
static void ics5342_release(struct dac_info *info)
{
ics5342_set_mode(info, DAC_PSEUDO8_8);
kfree(info);
}
static struct dac_ops ics5342_ops = {
.dac_set_mode = ics5342_set_mode,
.dac_set_freq = ics5342_set_freq,
.dac_release = ics5342_release
};
static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data)
{
struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL);
if (! info)
return NULL;
info->dacops = &ics5342_ops;
info->dac_read_regs = drr;
info->dac_write_regs = dwr;
info->data = data;
DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */
return info;
}
/* ------------------------------------------------------------------------- */
static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7};
static void ark_dac_read_regs(void *data, u8 *code, int count)
{
struct fb_info *info = data;
struct arkfb_info *par;
u8 regval;
par = info->par;
regval = vga_rseq(par->state.vgabase, 0x1C);
while (count != 0)
{
vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
count--;
code += 2;
}
vga_wseq(par->state.vgabase, 0x1C, regval);
}
static void ark_dac_write_regs(void *data, u8 *code, int count)
{
struct fb_info *info = data;
struct arkfb_info *par;
u8 regval;
par = info->par;
regval = vga_rseq(par->state.vgabase, 0x1C);
while (count != 0)
{
vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
count--;
code += 2;
}
vga_wseq(par->state.vgabase, 0x1C, regval);
}
static void ark_set_pixclock(struct fb_info *info, u32 pixclock)
{
struct arkfb_info *par = info->par;
u8 regval;
int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock);
if (rv < 0) {
fb_err(info, "cannot set requested pixclock, keeping old value\n");
return;
}
/* Set VGA misc register */
regval = vga_r(par->state.vgabase, VGA_MIS_R);
vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
}
/* Open framebuffer */
static int arkfb_open(struct fb_info *info, int user)
{
struct arkfb_info *par = info->par;
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
void __iomem *vgabase = par->state.vgabase;
memset(&(par->state), 0, sizeof(struct vgastate));
par->state.vgabase = vgabase;
par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
par->state.num_crtc = 0x60;
par->state.num_seq = 0x30;
save_vga(&(par->state));
}
par->ref_count++;
mutex_unlock(&(par->open_lock));
return 0;
}
/* Close framebuffer */
static int arkfb_release(struct fb_info *info, int user)
{
struct arkfb_info *par = info->par;
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
mutex_unlock(&(par->open_lock));
return -EINVAL;
}
if (par->ref_count == 1) {
restore_vga(&(par->state));
dac_set_mode(par->dac, DAC_PSEUDO8_8);
}
par->ref_count--;
mutex_unlock(&(par->open_lock));
return 0;
}
/* Validate passed in var */
static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
int rv, mem, step;
if (!var->pixclock)
return -EINVAL;
/* Find appropriate format */
rv = svga_match_format (arkfb_formats, var, NULL);
if (rv < 0)
{
fb_err(info, "unsupported mode requested\n");
return rv;
}
/* Do not allow to have real resoulution larger than virtual */
if (var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
/* Round up xres_virtual to have proper alignment of lines */
step = arkfb_formats[rv].xresstep - 1;
var->xres_virtual = (var->xres_virtual+step) & ~step;
/* Check whether have enough memory */
mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
if (mem > info->screen_size)
{
fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n",
mem >> 10, (unsigned int) (info->screen_size >> 10));
return -EINVAL;
}
rv = svga_check_timings (&ark_timing_regs, var, info->node);
if (rv < 0)
{
fb_err(info, "invalid timings requested\n");
return rv;
}
/* Interlaced mode is broken */
if (var->vmode & FB_VMODE_INTERLACED)
return -EINVAL;
return 0;
}
/* Set video mode from par */
static int arkfb_set_par(struct fb_info *info)
{
struct arkfb_info *par = info->par;
u32 value, mode, hmul, hdiv, offset_value, screen_size;
u32 bpp = info->var.bits_per_pixel;
u8 regval;
if (bpp != 0) {
info->fix.ypanstep = 1;
info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
info->flags &= ~FBINFO_MISC_TILEBLITTING;
info->tileops = NULL;
/* in 4bpp supports 8p wide tiles only, any tiles otherwise */
info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
info->pixmap.blit_y = ~(u32)0;
offset_value = (info->var.xres_virtual * bpp) / 64;
screen_size = info->var.yres_virtual * info->fix.line_length;
} else {
info->fix.ypanstep = 16;
info->fix.line_length = 0;
info->flags |= FBINFO_MISC_TILEBLITTING;
info->tileops = &arkfb_tile_ops;
/* supports 8x16 tiles only */
info->pixmap.blit_x = 1 << (8 - 1);
info->pixmap.blit_y = 1 << (16 - 1);
offset_value = info->var.xres_virtual / 16;
screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
}
info->var.xoffset = 0;
info->var.yoffset = 0;
info->var.activate = FB_ACTIVATE_NOW;
/* Unlock registers */
svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
/* Blank screen and turn off sync */
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
/* Set default values */
svga_set_default_gfx_regs(par->state.vgabase);
svga_set_default_atc_regs(par->state.vgabase);
svga_set_default_seq_regs(par->state.vgabase);
svga_set_default_crt_regs(par->state.vgabase);
svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
/* ARK specific initialization */
svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
vga_wseq(par->state.vgabase, 0x15, 0);
vga_wseq(par->state.vgabase, 0x16, 0);
/* Set the FIFO threshold register */
/* It is fascinating way to store 5-bit value in 8-bit register */
regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1;
vga_wseq(par->state.vgabase, 0x18, regval);
/* Set the offset register */
fb_dbg(info, "offset register : %d\n", offset_value);
svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
/* fix for hi-res textmode */
svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
if (info->var.vmode & FB_VMODE_DOUBLE)
svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
else
svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
if (info->var.vmode & FB_VMODE_INTERLACED)
svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
else
svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
hmul = 1;
hdiv = 1;
mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix));
/* Set mode-specific register values */
switch (mode) {
case 0:
fb_dbg(info, "text mode\n");
svga_set_textmode_vga_regs(par->state.vgabase);
vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
dac_set_mode(par->dac, DAC_PSEUDO8_8);
break;
case 1:
fb_dbg(info, "4 bit pseudocolor\n");
vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
dac_set_mode(par->dac, DAC_PSEUDO8_8);
break;
case 2:
fb_dbg(info, "4 bit pseudocolor, planar\n");
vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
dac_set_mode(par->dac, DAC_PSEUDO8_8);
break;
case 3:
fb_dbg(info, "8 bit pseudocolor\n");
vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
if (info->var.pixclock > 20000) {
fb_dbg(info, "not using multiplex\n");
svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
dac_set_mode(par->dac, DAC_PSEUDO8_8);
} else {
fb_dbg(info, "using multiplex\n");
svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
dac_set_mode(par->dac, DAC_PSEUDO8_16);
hdiv = 2;
}
break;
case 4:
fb_dbg(info, "5/5/5 truecolor\n");
vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
dac_set_mode(par->dac, DAC_RGB1555_16);
break;
case 5:
fb_dbg(info, "5/6/5 truecolor\n");
vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
dac_set_mode(par->dac, DAC_RGB0565_16);
break;
case 6:
fb_dbg(info, "8/8/8 truecolor\n");
vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
dac_set_mode(par->dac, DAC_RGB0888_16);
hmul = 3;
hdiv = 2;
break;
case 7:
fb_dbg(info, "8/8/8/8 truecolor\n");
vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
dac_set_mode(par->dac, DAC_RGB8888_16);
hmul = 2;
break;
default:
fb_err(info, "unsupported mode - bug\n");
return -EINVAL;
}
value = (hdiv * info->var.pixclock) / hmul;
if (!value) {
fb_dbg(info, "invalid pixclock\n");
value = 1;
}
ark_set_pixclock(info, value);
svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
(info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
(info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
hmul, info->node);
/* Set interlaced mode start/end register */
value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
value = ((value * hmul / hdiv) / 8) - 5;
vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
if (screen_size > info->screen_size)
screen_size = info->screen_size;
memset_io(info->screen_base, 0x00, screen_size);
/* Device and screen back on */
svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
return 0;
}
/* Set a colour register */
static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *fb)
{
switch (fb->var.bits_per_pixel) {
case 0:
case 4:
if (regno >= 16)
return -EINVAL;
if ((fb->var.bits_per_pixel == 4) &&
(fb->var.nonstd == 0)) {
outb(0xF0, VGA_PEL_MSK);
outb(regno*16, VGA_PEL_IW);
} else {
outb(0x0F, VGA_PEL_MSK);
outb(regno, VGA_PEL_IW);
}
outb(red >> 10, VGA_PEL_D);
outb(green >> 10, VGA_PEL_D);
outb(blue >> 10, VGA_PEL_D);
break;
case 8:
if (regno >= 256)
return -EINVAL;
outb(0xFF, VGA_PEL_MSK);
outb(regno, VGA_PEL_IW);
outb(red >> 10, VGA_PEL_D);
outb(green >> 10, VGA_PEL_D);
outb(blue >> 10, VGA_PEL_D);
break;
case 16:
if (regno >= 16)
return 0;
if (fb->var.green.length == 5)
((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
else if (fb->var.green.length == 6)
((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
else
return -EINVAL;
break;
case 24:
case 32:
if (regno >= 16)
return 0;
((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
(green & 0xFF00) | ((blue & 0xFF00) >> 8);
break;
default:
return -EINVAL;
}
return 0;
}
/* Set the display blanking state */
static int arkfb_blank(int blank_mode, struct fb_info *info)
{
struct arkfb_info *par = info->par;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
fb_dbg(info, "unblank\n");
svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
break;
case FB_BLANK_NORMAL:
fb_dbg(info, "blank\n");
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
break;
case FB_BLANK_POWERDOWN:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_VSYNC_SUSPEND:
fb_dbg(info, "sync down\n");
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
break;
}
return 0;
}
/* Pan the display */
static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct arkfb_info *par = info->par;
unsigned int offset;
/* Calculate the offset */
if (info->var.bits_per_pixel == 0) {
offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
+ (var->xoffset / 2);
offset = offset >> 2;
} else {
offset = (var->yoffset * info->fix.line_length) +
(var->xoffset * info->var.bits_per_pixel / 8);
offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 3);
}
/* Set the offset */
svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
return 0;
}
/* ------------------------------------------------------------------------- */
/* Frame buffer operations */
static const struct fb_ops arkfb_ops = {
.owner = THIS_MODULE,
.fb_open = arkfb_open,
.fb_release = arkfb_release,
.fb_check_var = arkfb_check_var,
.fb_set_par = arkfb_set_par,
.fb_setcolreg = arkfb_setcolreg,
.fb_blank = arkfb_blank,
.fb_pan_display = arkfb_pan_display,
.fb_fillrect = arkfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = arkfb_imageblit,
.fb_get_caps = svga_get_caps,
};
/* ------------------------------------------------------------------------- */
/* PCI probe */
static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct pci_bus_region bus_reg;
struct resource vga_res;
struct fb_info *info;
struct arkfb_info *par;
int rc;
u8 regval;
rc = aperture_remove_conflicting_pci_devices(dev, "arkfb");
if (rc < 0)
return rc;
/* Ignore secondary VGA device because there is no VGA arbitration */
if (! svga_primary_device(dev)) {
dev_info(&(dev->dev), "ignoring secondary device\n");
return -ENODEV;
}
/* Allocate and fill driver data structure */
info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev));
if (!info)
return -ENOMEM;
par = info->par;
mutex_init(&par->open_lock);
info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
info->fbops = &arkfb_ops;
/* Prepare PCI device */
rc = pci_enable_device(dev);
if (rc < 0) {
dev_err(info->device, "cannot enable PCI device\n");
goto err_enable_device;
}
rc = pci_request_regions(dev, "arkfb");
if (rc < 0) {
dev_err(info->device, "cannot reserve framebuffer region\n");
goto err_request_regions;
}
par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info);
if (! par->dac) {
rc = -ENOMEM;
dev_err(info->device, "RAMDAC initialization failed\n");
goto err_dac;
}
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = pci_resource_len(dev, 0);
/* Map physical IO memory address into kernel space */
info->screen_base = pci_iomap_wc(dev, 0, 0);
if (! info->screen_base) {
rc = -ENOMEM;
dev_err(info->device, "iomap for framebuffer failed\n");
goto err_iomap;
}
bus_reg.start = 0;
bus_reg.end = 64 * 1024;
vga_res.flags = IORESOURCE_IO;
pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
/* FIXME get memsize */
regval = vga_rseq(par->state.vgabase, 0x10);
info->screen_size = (1 << (regval >> 6)) << 20;
info->fix.smem_len = info->screen_size;
strcpy(info->fix.id, "ARK 2000PV");
info->fix.mmio_start = 0;
info->fix.mmio_len = 0;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.ypanstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->pseudo_palette = (void*) (par->pseudo_palette);
/* Prepare startup mode */
rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
if (! ((rc == 1) || (rc == 2))) {
rc = -EINVAL;
dev_err(info->device, "mode %s not found\n", mode_option);
goto err_find_mode;
}
rc = fb_alloc_cmap(&info->cmap, 256, 0);
if (rc < 0) {
dev_err(info->device, "cannot allocate colormap\n");
goto err_alloc_cmap;
}
rc = register_framebuffer(info);
if (rc < 0) {
dev_err(info->device, "cannot register framebuffer\n");
goto err_reg_fb;
}
fb_info(info, "%s on %s, %d MB RAM\n",
info->fix.id, pci_name(dev), info->fix.smem_len >> 20);
/* Record a reference to the driver data */
pci_set_drvdata(dev, info);
par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
info->fix.smem_len);
return 0;
/* Error handling */
err_reg_fb:
fb_dealloc_cmap(&info->cmap);
err_alloc_cmap:
err_find_mode:
pci_iounmap(dev, info->screen_base);
err_iomap:
dac_release(par->dac);
err_dac:
pci_release_regions(dev);
err_request_regions:
/* pci_disable_device(dev); */
err_enable_device:
framebuffer_release(info);
return rc;
}
/* PCI remove */
static void ark_pci_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
if (info) {
struct arkfb_info *par = info->par;
arch_phys_wc_del(par->wc_cookie);
dac_release(par->dac);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
pci_iounmap(dev, info->screen_base);
pci_release_regions(dev);
/* pci_disable_device(dev); */
framebuffer_release(info);
}
}
/* PCI suspend */
static int __maybe_unused ark_pci_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct arkfb_info *par = info->par;
dev_info(info->device, "suspend\n");
console_lock();
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
fb_set_suspend(info, 1);
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
/* PCI resume */
static int __maybe_unused ark_pci_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct arkfb_info *par = info->par;
dev_info(info->device, "resume\n");
console_lock();
mutex_lock(&(par->open_lock));
if (par->ref_count == 0)
goto fail;
arkfb_set_par(info);
fb_set_suspend(info, 0);
fail:
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
static const struct dev_pm_ops ark_pci_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = ark_pci_suspend,
.resume = ark_pci_resume,
.freeze = NULL,
.thaw = ark_pci_resume,
.poweroff = ark_pci_suspend,
.restore = ark_pci_resume,
#endif
};
/* List of boards that we are trying to support */
static const struct pci_device_id ark_devices[] = {
{PCI_DEVICE(0xEDD8, 0xA099)},
{0, 0, 0, 0, 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, ark_devices);
static struct pci_driver arkfb_pci_driver = {
.name = "arkfb",
.id_table = ark_devices,
.probe = ark_pci_probe,
.remove = ark_pci_remove,
.driver.pm = &ark_pci_pm_ops,
};
/* Cleanup */
static void __exit arkfb_cleanup(void)
{
pr_debug("arkfb: cleaning up\n");
pci_unregister_driver(&arkfb_pci_driver);
}
/* Driver Initialisation */
static int __init arkfb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("arkfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("arkfb", &option))
return -ENODEV;
if (option && *option)
mode_option = option;
#endif
pr_debug("arkfb: initializing\n");
return pci_register_driver(&arkfb_pci_driver);
}
module_init(arkfb_init);
module_exit(arkfb_cleanup);
| linux-master | drivers/video/fbdev/arkfb.c |
/*
* drivers/video/imsttfb.c -- frame buffer device for IMS TwinTurbo
*
* This file is derived from the powermac console "imstt" driver:
* Copyright (C) 1997 Sigurdur Asgeirsson
* With additional hacking by Jeffrey Kuskin ([email protected])
* Modified by Danilo Beuche 1998
* Some register values added by Damien Doligez, INRIA Rocquencourt
* Various cleanups by Paul Mundt ([email protected])
*
* This file was written by Ryan Nielsen ([email protected])
* Most of the frame buffer device stuff was copied from atyfb.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#if defined(CONFIG_PPC_PMAC)
#include <linux/nvram.h>
#include "macmodes.h"
#endif
#ifndef __powerpc__
#define eieio() /* Enforce In-order Execution of I/O */
#endif
/* TwinTurbo (Cosmo) registers */
enum {
S1SA = 0, /* 0x00 */
S2SA = 1, /* 0x04 */
SP = 2, /* 0x08 */
DSA = 3, /* 0x0C */
CNT = 4, /* 0x10 */
DP_OCTL = 5, /* 0x14 */
CLR = 6, /* 0x18 */
BI = 8, /* 0x20 */
MBC = 9, /* 0x24 */
BLTCTL = 10, /* 0x28 */
/* Scan Timing Generator Registers */
HES = 12, /* 0x30 */
HEB = 13, /* 0x34 */
HSB = 14, /* 0x38 */
HT = 15, /* 0x3C */
VES = 16, /* 0x40 */
VEB = 17, /* 0x44 */
VSB = 18, /* 0x48 */
VT = 19, /* 0x4C */
HCIV = 20, /* 0x50 */
VCIV = 21, /* 0x54 */
TCDR = 22, /* 0x58 */
VIL = 23, /* 0x5C */
STGCTL = 24, /* 0x60 */
/* Screen Refresh Generator Registers */
SSR = 25, /* 0x64 */
HRIR = 26, /* 0x68 */
SPR = 27, /* 0x6C */
CMR = 28, /* 0x70 */
SRGCTL = 29, /* 0x74 */
/* RAM Refresh Generator Registers */
RRCIV = 30, /* 0x78 */
RRSC = 31, /* 0x7C */
RRCR = 34, /* 0x88 */
/* System Registers */
GIOE = 32, /* 0x80 */
GIO = 33, /* 0x84 */
SCR = 35, /* 0x8C */
SSTATUS = 36, /* 0x90 */
PRC = 37, /* 0x94 */
#if 0
/* PCI Registers */
DVID = 0x00000000L,
SC = 0x00000004L,
CCR = 0x00000008L,
OG = 0x0000000CL,
BARM = 0x00000010L,
BARER = 0x00000030L,
#endif
};
/* IBM 624 RAMDAC Direct Registers */
enum {
PADDRW = 0x00,
PDATA = 0x04,
PPMASK = 0x08,
PADDRR = 0x0c,
PIDXLO = 0x10,
PIDXHI = 0x14,
PIDXDATA= 0x18,
PIDXCTL = 0x1c
};
/* IBM 624 RAMDAC Indirect Registers */
enum {
CLKCTL = 0x02, /* (0x01) Miscellaneous Clock Control */
SYNCCTL = 0x03, /* (0x00) Sync Control */
HSYNCPOS = 0x04, /* (0x00) Horizontal Sync Position */
PWRMNGMT = 0x05, /* (0x00) Power Management */
DACOP = 0x06, /* (0x02) DAC Operation */
PALETCTL = 0x07, /* (0x00) Palette Control */
SYSCLKCTL = 0x08, /* (0x01) System Clock Control */
PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
BPP8 = 0x0b, /* () 8 Bits/Pixel Control */
BPP16 = 0x0c, /* () 16 Bits/Pixel Control [bit 1=1 for 565] */
BPP24 = 0x0d, /* () 24 Bits/Pixel Control */
BPP32 = 0x0e, /* () 32 Bits/Pixel Control */
PIXCTL1 = 0x10, /* (0x05) Pixel PLL Control 1 */
PIXCTL2 = 0x11, /* (0x00) Pixel PLL Control 2 */
SYSCLKN = 0x15, /* () System Clock N (System PLL Reference Divider) */
SYSCLKM = 0x16, /* () System Clock M (System PLL VCO Divider) */
SYSCLKP = 0x17, /* () System Clock P */
SYSCLKC = 0x18, /* () System Clock C */
/*
* Dot clock rate is 20MHz * (m + 1) / ((n + 1) * (p ? 2 * p : 1)
* c is charge pump bias which depends on the VCO frequency
*/
PIXM0 = 0x20, /* () Pixel M 0 */
PIXN0 = 0x21, /* () Pixel N 0 */
PIXP0 = 0x22, /* () Pixel P 0 */
PIXC0 = 0x23, /* () Pixel C 0 */
CURSCTL = 0x30, /* (0x00) Cursor Control */
CURSXLO = 0x31, /* () Cursor X position, low 8 bits */
CURSXHI = 0x32, /* () Cursor X position, high 8 bits */
CURSYLO = 0x33, /* () Cursor Y position, low 8 bits */
CURSYHI = 0x34, /* () Cursor Y position, high 8 bits */
CURSHOTX = 0x35, /* () Cursor Hot Spot X */
CURSHOTY = 0x36, /* () Cursor Hot Spot Y */
CURSACCTL = 0x37, /* () Advanced Cursor Control Enable */
CURSACATTR = 0x38, /* () Advanced Cursor Attribute */
CURS1R = 0x40, /* () Cursor 1 Red */
CURS1G = 0x41, /* () Cursor 1 Green */
CURS1B = 0x42, /* () Cursor 1 Blue */
CURS2R = 0x43, /* () Cursor 2 Red */
CURS2G = 0x44, /* () Cursor 2 Green */
CURS2B = 0x45, /* () Cursor 2 Blue */
CURS3R = 0x46, /* () Cursor 3 Red */
CURS3G = 0x47, /* () Cursor 3 Green */
CURS3B = 0x48, /* () Cursor 3 Blue */
BORDR = 0x60, /* () Border Color Red */
BORDG = 0x61, /* () Border Color Green */
BORDB = 0x62, /* () Border Color Blue */
MISCTL1 = 0x70, /* (0x00) Miscellaneous Control 1 */
MISCTL2 = 0x71, /* (0x00) Miscellaneous Control 2 */
MISCTL3 = 0x72, /* (0x00) Miscellaneous Control 3 */
KEYCTL = 0x78 /* (0x00) Key Control/DB Operation */
};
/* TI TVP 3030 RAMDAC Direct Registers */
enum {
TVPADDRW = 0x00, /* 0 Palette/Cursor RAM Write Address/Index */
TVPPDATA = 0x04, /* 1 Palette Data RAM Data */
TVPPMASK = 0x08, /* 2 Pixel Read-Mask */
TVPPADRR = 0x0c, /* 3 Palette/Cursor RAM Read Address */
TVPCADRW = 0x10, /* 4 Cursor/Overscan Color Write Address */
TVPCDATA = 0x14, /* 5 Cursor/Overscan Color Data */
/* 6 reserved */
TVPCADRR = 0x1c, /* 7 Cursor/Overscan Color Read Address */
/* 8 reserved */
TVPDCCTL = 0x24, /* 9 Direct Cursor Control */
TVPIDATA = 0x28, /* 10 Index Data */
TVPCRDAT = 0x2c, /* 11 Cursor RAM Data */
TVPCXPOL = 0x30, /* 12 Cursor-Position X LSB */
TVPCXPOH = 0x34, /* 13 Cursor-Position X MSB */
TVPCYPOL = 0x38, /* 14 Cursor-Position Y LSB */
TVPCYPOH = 0x3c, /* 15 Cursor-Position Y MSB */
};
/* TI TVP 3030 RAMDAC Indirect Registers */
enum {
TVPIRREV = 0x01, /* Silicon Revision [RO] */
TVPIRICC = 0x06, /* Indirect Cursor Control (0x00) */
TVPIRBRC = 0x07, /* Byte Router Control (0xe4) */
TVPIRLAC = 0x0f, /* Latch Control (0x06) */
TVPIRTCC = 0x18, /* True Color Control (0x80) */
TVPIRMXC = 0x19, /* Multiplex Control (0x98) */
TVPIRCLS = 0x1a, /* Clock Selection (0x07) */
TVPIRPPG = 0x1c, /* Palette Page (0x00) */
TVPIRGEC = 0x1d, /* General Control (0x00) */
TVPIRMIC = 0x1e, /* Miscellaneous Control (0x00) */
TVPIRPLA = 0x2c, /* PLL Address */
TVPIRPPD = 0x2d, /* Pixel Clock PLL Data */
TVPIRMPD = 0x2e, /* Memory Clock PLL Data */
TVPIRLPD = 0x2f, /* Loop Clock PLL Data */
TVPIRCKL = 0x30, /* Color-Key Overlay Low */
TVPIRCKH = 0x31, /* Color-Key Overlay High */
TVPIRCRL = 0x32, /* Color-Key Red Low */
TVPIRCRH = 0x33, /* Color-Key Red High */
TVPIRCGL = 0x34, /* Color-Key Green Low */
TVPIRCGH = 0x35, /* Color-Key Green High */
TVPIRCBL = 0x36, /* Color-Key Blue Low */
TVPIRCBH = 0x37, /* Color-Key Blue High */
TVPIRCKC = 0x38, /* Color-Key Control (0x00) */
TVPIRMLC = 0x39, /* MCLK/Loop Clock Control (0x18) */
TVPIRSEN = 0x3a, /* Sense Test (0x00) */
TVPIRTMD = 0x3b, /* Test Mode Data */
TVPIRRML = 0x3c, /* CRC Remainder LSB [RO] */
TVPIRRMM = 0x3d, /* CRC Remainder MSB [RO] */
TVPIRRMS = 0x3e, /* CRC Bit Select [WO] */
TVPIRDID = 0x3f, /* Device ID [RO] (0x30) */
TVPIRRES = 0xff /* Software Reset [WO] */
};
struct initvalues {
__u8 addr, value;
};
static struct initvalues ibm_initregs[] = {
{ CLKCTL, 0x21 },
{ SYNCCTL, 0x00 },
{ HSYNCPOS, 0x00 },
{ PWRMNGMT, 0x00 },
{ DACOP, 0x02 },
{ PALETCTL, 0x00 },
{ SYSCLKCTL, 0x01 },
/*
* Note that colors in X are correct only if all video data is
* passed through the palette in the DAC. That is, "indirect
* color" must be configured. This is the case for the IBM DAC
* used in the 2MB and 4MB cards, at least.
*/
{ BPP8, 0x00 },
{ BPP16, 0x01 },
{ BPP24, 0x00 },
{ BPP32, 0x00 },
{ PIXCTL1, 0x05 },
{ PIXCTL2, 0x00 },
{ SYSCLKN, 0x08 },
{ SYSCLKM, 0x4f },
{ SYSCLKP, 0x00 },
{ SYSCLKC, 0x00 },
{ CURSCTL, 0x00 },
{ CURSACCTL, 0x01 },
{ CURSACATTR, 0xa8 },
{ CURS1R, 0xff },
{ CURS1G, 0xff },
{ CURS1B, 0xff },
{ CURS2R, 0xff },
{ CURS2G, 0xff },
{ CURS2B, 0xff },
{ CURS3R, 0xff },
{ CURS3G, 0xff },
{ CURS3B, 0xff },
{ BORDR, 0xff },
{ BORDG, 0xff },
{ BORDB, 0xff },
{ MISCTL1, 0x01 },
{ MISCTL2, 0x45 },
{ MISCTL3, 0x00 },
{ KEYCTL, 0x00 }
};
static struct initvalues tvp_initregs[] = {
{ TVPIRICC, 0x00 },
{ TVPIRBRC, 0xe4 },
{ TVPIRLAC, 0x06 },
{ TVPIRTCC, 0x80 },
{ TVPIRMXC, 0x4d },
{ TVPIRCLS, 0x05 },
{ TVPIRPPG, 0x00 },
{ TVPIRGEC, 0x00 },
{ TVPIRMIC, 0x08 },
{ TVPIRCKL, 0xff },
{ TVPIRCKH, 0xff },
{ TVPIRCRL, 0xff },
{ TVPIRCRH, 0xff },
{ TVPIRCGL, 0xff },
{ TVPIRCGH, 0xff },
{ TVPIRCBL, 0xff },
{ TVPIRCBH, 0xff },
{ TVPIRCKC, 0x00 },
{ TVPIRPLA, 0x00 },
{ TVPIRPPD, 0xc0 },
{ TVPIRPPD, 0xd5 },
{ TVPIRPPD, 0xea },
{ TVPIRPLA, 0x00 },
{ TVPIRMPD, 0xb9 },
{ TVPIRMPD, 0x3a },
{ TVPIRMPD, 0xb1 },
{ TVPIRPLA, 0x00 },
{ TVPIRLPD, 0xc1 },
{ TVPIRLPD, 0x3d },
{ TVPIRLPD, 0xf3 },
};
struct imstt_regvals {
__u32 pitch;
__u16 hes, heb, hsb, ht, ves, veb, vsb, vt, vil;
__u8 pclk_m, pclk_n, pclk_p;
/* Values of the tvp which change depending on colormode x resolution */
__u8 mlc[3]; /* Memory Loop Config 0x39 */
__u8 lckl_p[3]; /* P value of LCKL PLL */
};
struct imstt_par {
struct imstt_regvals init;
__u32 __iomem *dc_regs;
unsigned long cmap_regs_phys;
__u8 *cmap_regs;
__u32 ramdac;
__u32 palette[16];
};
enum {
IBM = 0,
TVP = 1
};
#define INIT_BPP 8
#define INIT_XRES 640
#define INIT_YRES 480
static int inverse = 0;
static char fontname[40] __initdata = { 0 };
#if defined(CONFIG_PPC_PMAC)
static signed char init_vmode = -1, init_cmode = -1;
#endif
static struct imstt_regvals tvp_reg_init_2 = {
512,
0x0002, 0x0006, 0x0026, 0x0028, 0x0003, 0x0016, 0x0196, 0x0197, 0x0196,
0xec, 0x2a, 0xf3,
{ 0x3c, 0x3b, 0x39 }, { 0xf3, 0xf3, 0xf3 }
};
static struct imstt_regvals tvp_reg_init_6 = {
640,
0x0004, 0x0009, 0x0031, 0x0036, 0x0003, 0x002a, 0x020a, 0x020d, 0x020a,
0xef, 0x2e, 0xb2,
{ 0x39, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
};
static struct imstt_regvals tvp_reg_init_12 = {
800,
0x0005, 0x000e, 0x0040, 0x0042, 0x0003, 0x018, 0x270, 0x271, 0x270,
0xf6, 0x2e, 0xf2,
{ 0x3a, 0x39, 0x38 }, { 0xf3, 0xf3, 0xf3 }
};
static struct imstt_regvals tvp_reg_init_13 = {
832,
0x0004, 0x0011, 0x0045, 0x0048, 0x0003, 0x002a, 0x029a, 0x029b, 0x0000,
0xfe, 0x3e, 0xf1,
{ 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
};
static struct imstt_regvals tvp_reg_init_17 = {
1024,
0x0006, 0x0210, 0x0250, 0x0053, 0x1003, 0x0021, 0x0321, 0x0324, 0x0000,
0xfc, 0x3a, 0xf1,
{ 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
};
static struct imstt_regvals tvp_reg_init_18 = {
1152,
0x0009, 0x0011, 0x059, 0x5b, 0x0003, 0x0031, 0x0397, 0x039a, 0x0000,
0xfd, 0x3a, 0xf1,
{ 0x39, 0x38, 0x38 }, { 0xf3, 0xf3, 0xf2 }
};
static struct imstt_regvals tvp_reg_init_19 = {
1280,
0x0009, 0x0016, 0x0066, 0x0069, 0x0003, 0x0027, 0x03e7, 0x03e8, 0x03e7,
0xf7, 0x36, 0xf0,
{ 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
};
static struct imstt_regvals tvp_reg_init_20 = {
1280,
0x0009, 0x0018, 0x0068, 0x006a, 0x0003, 0x0029, 0x0429, 0x042a, 0x0000,
0xf0, 0x2d, 0xf0,
{ 0x38, 0x38, 0x38 }, { 0xf3, 0xf2, 0xf1 }
};
/*
* PCI driver prototypes
*/
static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
static void imsttfb_remove(struct pci_dev *pdev);
/*
* Register access
*/
static inline u32 read_reg_le32(volatile u32 __iomem *base, int regindex)
{
#ifdef __powerpc__
return in_le32(base + regindex);
#else
return readl(base + regindex);
#endif
}
static inline void write_reg_le32(volatile u32 __iomem *base, int regindex, u32 val)
{
#ifdef __powerpc__
out_le32(base + regindex, val);
#else
writel(val, base + regindex);
#endif
}
static __u32
getclkMHz(struct imstt_par *par)
{
__u32 clk_m, clk_n, clk_p;
clk_m = par->init.pclk_m;
clk_n = par->init.pclk_n;
clk_p = par->init.pclk_p;
return 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
}
static void
setclkMHz(struct imstt_par *par, __u32 MHz)
{
__u32 clk_m, clk_n, x, stage, spilled;
clk_m = clk_n = 0;
stage = spilled = 0;
for (;;) {
switch (stage) {
case 0:
clk_m++;
break;
case 1:
clk_n++;
break;
}
x = 20 * (clk_m + 1) / (clk_n + 1);
if (x == MHz)
break;
if (x > MHz) {
spilled = 1;
stage = 1;
} else if (spilled && x < MHz) {
stage = 0;
}
}
par->init.pclk_m = clk_m;
par->init.pclk_n = clk_n;
par->init.pclk_p = 0;
}
static struct imstt_regvals *
compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres)
{
struct imstt_regvals *init = &par->init;
__u32 MHz, hes, heb, veb, htp, vtp;
switch (xres) {
case 640:
hes = 0x0008; heb = 0x0012; veb = 0x002a; htp = 10; vtp = 2;
MHz = 30 /* .25 */ ;
break;
case 832:
hes = 0x0005; heb = 0x0020; veb = 0x0028; htp = 8; vtp = 3;
MHz = 57 /* .27_ */ ;
break;
case 1024:
hes = 0x000a; heb = 0x001c; veb = 0x0020; htp = 8; vtp = 3;
MHz = 80;
break;
case 1152:
hes = 0x0012; heb = 0x0022; veb = 0x0031; htp = 4; vtp = 3;
MHz = 101 /* .6_ */ ;
break;
case 1280:
hes = 0x0012; heb = 0x002f; veb = 0x0029; htp = 4; vtp = 1;
MHz = yres == 960 ? 126 : 135;
break;
case 1600:
hes = 0x0018; heb = 0x0040; veb = 0x002a; htp = 4; vtp = 3;
MHz = 200;
break;
default:
return NULL;
}
setclkMHz(par, MHz);
init->hes = hes;
init->heb = heb;
init->hsb = init->heb + (xres >> 3);
init->ht = init->hsb + htp;
init->ves = 0x0003;
init->veb = veb;
init->vsb = init->veb + yres;
init->vt = init->vsb + vtp;
init->vil = init->vsb;
init->pitch = xres;
return init;
}
static struct imstt_regvals *
compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres)
{
struct imstt_regvals *init;
switch (xres) {
case 512:
init = &tvp_reg_init_2;
break;
case 640:
init = &tvp_reg_init_6;
break;
case 800:
init = &tvp_reg_init_12;
break;
case 832:
init = &tvp_reg_init_13;
break;
case 1024:
init = &tvp_reg_init_17;
break;
case 1152:
init = &tvp_reg_init_18;
break;
case 1280:
init = yres == 960 ? &tvp_reg_init_19 : &tvp_reg_init_20;
break;
default:
return NULL;
}
par->init = *init;
return init;
}
static struct imstt_regvals *
compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres)
{
if (par->ramdac == IBM)
return compute_imstt_regvals_ibm(par, xres, yres);
else
return compute_imstt_regvals_tvp(par, xres, yres);
}
static void
set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp)
{
struct imstt_regvals *init = &par->init;
__u8 pformat = (bpp >> 3) + 2;
par->cmap_regs[PIDXHI] = 0; eieio();
par->cmap_regs[PIDXLO] = PIXM0; eieio();
par->cmap_regs[PIDXDATA] = init->pclk_m;eieio();
par->cmap_regs[PIDXLO] = PIXN0; eieio();
par->cmap_regs[PIDXDATA] = init->pclk_n;eieio();
par->cmap_regs[PIDXLO] = PIXP0; eieio();
par->cmap_regs[PIDXDATA] = init->pclk_p;eieio();
par->cmap_regs[PIDXLO] = PIXC0; eieio();
par->cmap_regs[PIDXDATA] = 0x02; eieio();
par->cmap_regs[PIDXLO] = PIXFMT; eieio();
par->cmap_regs[PIDXDATA] = pformat; eieio();
}
static void
set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp)
{
struct imstt_regvals *init = &par->init;
__u8 tcc, mxc, lckl_n, mic;
__u8 mlc, lckl_p;
switch (bpp) {
default:
case 8:
tcc = 0x80;
mxc = 0x4d;
lckl_n = 0xc1;
mlc = init->mlc[0];
lckl_p = init->lckl_p[0];
break;
case 16:
tcc = 0x44;
mxc = 0x55;
lckl_n = 0xe1;
mlc = init->mlc[1];
lckl_p = init->lckl_p[1];
break;
case 24:
tcc = 0x5e;
mxc = 0x5d;
lckl_n = 0xf1;
mlc = init->mlc[2];
lckl_p = init->lckl_p[2];
break;
case 32:
tcc = 0x46;
mxc = 0x5d;
lckl_n = 0xf1;
mlc = init->mlc[2];
lckl_p = init->lckl_p[2];
break;
}
mic = 0x08;
par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
par->cmap_regs[TVPIDATA] = 0x00; eieio();
par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
par->cmap_regs[TVPIDATA] = init->pclk_m; eieio();
par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
par->cmap_regs[TVPIDATA] = init->pclk_n; eieio();
par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
par->cmap_regs[TVPIDATA] = init->pclk_p; eieio();
par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
par->cmap_regs[TVPIDATA] = tcc; eieio();
par->cmap_regs[TVPADDRW] = TVPIRMXC; eieio();
par->cmap_regs[TVPIDATA] = mxc; eieio();
par->cmap_regs[TVPADDRW] = TVPIRMIC; eieio();
par->cmap_regs[TVPIDATA] = mic; eieio();
par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
par->cmap_regs[TVPIDATA] = 0x00; eieio();
par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
par->cmap_regs[TVPIDATA] = lckl_n; eieio();
par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
par->cmap_regs[TVPIDATA] = 0x15; eieio();
par->cmap_regs[TVPADDRW] = TVPIRMLC; eieio();
par->cmap_regs[TVPIDATA] = mlc; eieio();
par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
par->cmap_regs[TVPIDATA] = 0x2a; eieio();
par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
par->cmap_regs[TVPIDATA] = lckl_p; eieio();
}
static void
set_imstt_regvals (struct fb_info *info, u_int bpp)
{
struct imstt_par *par = info->par;
struct imstt_regvals *init = &par->init;
__u32 ctl, pitch, byteswap, scr;
if (par->ramdac == IBM)
set_imstt_regvals_ibm(par, bpp);
else
set_imstt_regvals_tvp(par, bpp);
/*
* From what I (jsk) can gather poking around with MacsBug,
* bits 8 and 9 in the SCR register control endianness
* correction (byte swapping). These bits must be set according
* to the color depth as follows:
* Color depth Bit 9 Bit 8
* ========== ===== =====
* 8bpp 0 0
* 16bpp 0 1
* 32bpp 1 1
*/
switch (bpp) {
default:
case 8:
ctl = 0x17b1;
pitch = init->pitch >> 2;
byteswap = 0x000;
break;
case 16:
ctl = 0x17b3;
pitch = init->pitch >> 1;
byteswap = 0x100;
break;
case 24:
ctl = 0x17b9;
pitch = init->pitch - (init->pitch >> 2);
byteswap = 0x200;
break;
case 32:
ctl = 0x17b5;
pitch = init->pitch;
byteswap = 0x300;
break;
}
if (par->ramdac == TVP)
ctl -= 0x30;
write_reg_le32(par->dc_regs, HES, init->hes);
write_reg_le32(par->dc_regs, HEB, init->heb);
write_reg_le32(par->dc_regs, HSB, init->hsb);
write_reg_le32(par->dc_regs, HT, init->ht);
write_reg_le32(par->dc_regs, VES, init->ves);
write_reg_le32(par->dc_regs, VEB, init->veb);
write_reg_le32(par->dc_regs, VSB, init->vsb);
write_reg_le32(par->dc_regs, VT, init->vt);
write_reg_le32(par->dc_regs, VIL, init->vil);
write_reg_le32(par->dc_regs, HCIV, 1);
write_reg_le32(par->dc_regs, VCIV, 1);
write_reg_le32(par->dc_regs, TCDR, 4);
write_reg_le32(par->dc_regs, RRCIV, 1);
write_reg_le32(par->dc_regs, RRSC, 0x980);
write_reg_le32(par->dc_regs, RRCR, 0x11);
if (par->ramdac == IBM) {
write_reg_le32(par->dc_regs, HRIR, 0x0100);
write_reg_le32(par->dc_regs, CMR, 0x00ff);
write_reg_le32(par->dc_regs, SRGCTL, 0x0073);
} else {
write_reg_le32(par->dc_regs, HRIR, 0x0200);
write_reg_le32(par->dc_regs, CMR, 0x01ff);
write_reg_le32(par->dc_regs, SRGCTL, 0x0003);
}
switch (info->fix.smem_len) {
case 0x200000:
scr = 0x059d | byteswap;
break;
/* case 0x400000:
case 0x800000: */
default:
pitch >>= 1;
scr = 0x150dd | byteswap;
break;
}
write_reg_le32(par->dc_regs, SCR, scr);
write_reg_le32(par->dc_regs, SPR, pitch);
write_reg_le32(par->dc_regs, STGCTL, ctl);
}
static inline void
set_offset (struct fb_var_screeninfo *var, struct fb_info *info)
{
struct imstt_par *par = info->par;
__u32 off = var->yoffset * (info->fix.line_length >> 3)
+ ((var->xoffset * (info->var.bits_per_pixel >> 3)) >> 3);
write_reg_le32(par->dc_regs, SSR, off);
}
static inline void
set_555 (struct imstt_par *par)
{
if (par->ramdac == IBM) {
par->cmap_regs[PIDXHI] = 0; eieio();
par->cmap_regs[PIDXLO] = BPP16; eieio();
par->cmap_regs[PIDXDATA] = 0x01; eieio();
} else {
par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
par->cmap_regs[TVPIDATA] = 0x44; eieio();
}
}
static inline void
set_565 (struct imstt_par *par)
{
if (par->ramdac == IBM) {
par->cmap_regs[PIDXHI] = 0; eieio();
par->cmap_regs[PIDXLO] = BPP16; eieio();
par->cmap_regs[PIDXDATA] = 0x03; eieio();
} else {
par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
par->cmap_regs[TVPIDATA] = 0x45; eieio();
}
}
static int
imsttfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if ((var->bits_per_pixel != 8 && var->bits_per_pixel != 16
&& var->bits_per_pixel != 24 && var->bits_per_pixel != 32)
|| var->xres_virtual < var->xres || var->yres_virtual < var->yres
|| var->nonstd
|| (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
return -EINVAL;
if ((var->xres * var->yres) * (var->bits_per_pixel >> 3) > info->fix.smem_len
|| (var->xres_virtual * var->yres_virtual) * (var->bits_per_pixel >> 3) > info->fix.smem_len)
return -EINVAL;
switch (var->bits_per_pixel) {
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16: /* RGB 555 or 565 */
if (var->green.length != 6)
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
if (var->green.length != 6)
var->green.length = 5;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 24: /* RGB 888 */
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 32: /* RGBA 8888 */
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
}
if (var->yres == var->yres_virtual) {
__u32 vram = (info->fix.smem_len - (PAGE_SIZE << 2));
var->yres_virtual = ((vram << 3) / var->bits_per_pixel) / var->xres_virtual;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
var->height = -1;
var->width = -1;
var->vmode = FB_VMODE_NONINTERLACED;
var->left_margin = var->right_margin = 16;
var->upper_margin = var->lower_margin = 16;
var->hsync_len = var->vsync_len = 8;
return 0;
}
static int
imsttfb_set_par(struct fb_info *info)
{
struct imstt_par *par = info->par;
if (!compute_imstt_regvals(par, info->var.xres, info->var.yres))
return -EINVAL;
if (info->var.green.length == 6)
set_565(par);
else
set_555(par);
set_imstt_regvals(info, info->var.bits_per_pixel);
info->var.pixclock = 1000000 / getclkMHz(par);
return 0;
}
static int
imsttfb_setcolreg (u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct imstt_par *par = info->par;
u_int bpp = info->var.bits_per_pixel;
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
/* PADDRW/PDATA are the same as TVPPADDRW/TVPPDATA */
if (0 && bpp == 16) /* screws up X */
par->cmap_regs[PADDRW] = regno << 3;
else
par->cmap_regs[PADDRW] = regno;
eieio();
par->cmap_regs[PDATA] = red; eieio();
par->cmap_regs[PDATA] = green; eieio();
par->cmap_regs[PDATA] = blue; eieio();
if (regno < 16)
switch (bpp) {
case 16:
par->palette[regno] =
(regno << (info->var.green.length ==
5 ? 10 : 11)) | (regno << 5) | regno;
break;
case 24:
par->palette[regno] =
(regno << 16) | (regno << 8) | regno;
break;
case 32: {
int i = (regno << 8) | regno;
par->palette[regno] = (i << 16) |i;
break;
}
}
return 0;
}
static int
imsttfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (var->xoffset + info->var.xres > info->var.xres_virtual
|| var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
set_offset(var, info);
return 0;
}
static int
imsttfb_blank(int blank, struct fb_info *info)
{
struct imstt_par *par = info->par;
__u32 ctrl;
ctrl = read_reg_le32(par->dc_regs, STGCTL);
if (blank > 0) {
switch (blank) {
case FB_BLANK_NORMAL:
case FB_BLANK_POWERDOWN:
ctrl &= ~0x00000380;
if (par->ramdac == IBM) {
par->cmap_regs[PIDXHI] = 0; eieio();
par->cmap_regs[PIDXLO] = MISCTL2; eieio();
par->cmap_regs[PIDXDATA] = 0x55; eieio();
par->cmap_regs[PIDXLO] = MISCTL1; eieio();
par->cmap_regs[PIDXDATA] = 0x11; eieio();
par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
par->cmap_regs[PIDXDATA] = 0x0f; eieio();
par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
par->cmap_regs[PIDXDATA] = 0x1f; eieio();
par->cmap_regs[PIDXLO] = CLKCTL; eieio();
par->cmap_regs[PIDXDATA] = 0xc0;
}
break;
case FB_BLANK_VSYNC_SUSPEND:
ctrl &= ~0x00000020;
break;
case FB_BLANK_HSYNC_SUSPEND:
ctrl &= ~0x00000010;
break;
}
} else {
if (par->ramdac == IBM) {
ctrl |= 0x000017b0;
par->cmap_regs[PIDXHI] = 0; eieio();
par->cmap_regs[PIDXLO] = CLKCTL; eieio();
par->cmap_regs[PIDXDATA] = 0x01; eieio();
par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
par->cmap_regs[PIDXDATA] = 0x00; eieio();
par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
par->cmap_regs[PIDXDATA] = 0x00; eieio();
par->cmap_regs[PIDXLO] = MISCTL1; eieio();
par->cmap_regs[PIDXDATA] = 0x01; eieio();
par->cmap_regs[PIDXLO] = MISCTL2; eieio();
par->cmap_regs[PIDXDATA] = 0x45; eieio();
} else
ctrl |= 0x00001780;
}
write_reg_le32(par->dc_regs, STGCTL, ctrl);
return 0;
}
static void
imsttfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct imstt_par *par = info->par;
__u32 Bpp, line_pitch, bgc, dx, dy, width, height;
bgc = rect->color;
bgc |= (bgc << 8);
bgc |= (bgc << 16);
Bpp = info->var.bits_per_pixel >> 3,
line_pitch = info->fix.line_length;
dy = rect->dy * line_pitch;
dx = rect->dx * Bpp;
height = rect->height;
height--;
width = rect->width * Bpp;
width--;
if (rect->rop == ROP_COPY) {
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
write_reg_le32(par->dc_regs, DSA, dy + dx);
write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
write_reg_le32(par->dc_regs, BI, 0xffffffff);
write_reg_le32(par->dc_regs, MBC, 0xffffffff);
write_reg_le32(par->dc_regs, CLR, bgc);
write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
} else {
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
write_reg_le32(par->dc_regs, DSA, dy + dx);
write_reg_le32(par->dc_regs, S1SA, dy + dx);
write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
write_reg_le32(par->dc_regs, SP, line_pitch);
write_reg_le32(par->dc_regs, BLTCTL, 0x40005);
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
}
}
static void
imsttfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct imstt_par *par = info->par;
__u32 Bpp, line_pitch, fb_offset_old, fb_offset_new, sp, dp_octl;
__u32 cnt, bltctl, sx, sy, dx, dy, height, width;
Bpp = info->var.bits_per_pixel >> 3,
sx = area->sx * Bpp;
sy = area->sy;
dx = area->dx * Bpp;
dy = area->dy;
height = area->height;
height--;
width = area->width * Bpp;
width--;
line_pitch = info->fix.line_length;
bltctl = 0x05;
sp = line_pitch << 16;
cnt = height << 16;
if (sy < dy) {
sy += height;
dy += height;
sp |= -(line_pitch) & 0xffff;
dp_octl = -(line_pitch) & 0xffff;
} else {
sp |= line_pitch;
dp_octl = line_pitch;
}
if (sx < dx) {
sx += width;
dx += width;
bltctl |= 0x80;
cnt |= -(width) & 0xffff;
} else {
cnt |= width;
}
fb_offset_old = sy * line_pitch + sx;
fb_offset_new = dy * line_pitch + dx;
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
write_reg_le32(par->dc_regs, S1SA, fb_offset_old);
write_reg_le32(par->dc_regs, SP, sp);
write_reg_le32(par->dc_regs, DSA, fb_offset_new);
write_reg_le32(par->dc_regs, CNT, cnt);
write_reg_le32(par->dc_regs, DP_OCTL, dp_octl);
write_reg_le32(par->dc_regs, BLTCTL, bltctl);
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
}
#if 0
static int
imsttfb_load_cursor_image(struct imstt_par *par, int width, int height, __u8 fgc)
{
u_int x, y;
if (width > 32 || height > 32)
return -EINVAL;
if (par->ramdac == IBM) {
par->cmap_regs[PIDXHI] = 1; eieio();
for (x = 0; x < 0x100; x++) {
par->cmap_regs[PIDXLO] = x; eieio();
par->cmap_regs[PIDXDATA] = 0x00; eieio();
}
par->cmap_regs[PIDXHI] = 1; eieio();
for (y = 0; y < height; y++)
for (x = 0; x < width >> 2; x++) {
par->cmap_regs[PIDXLO] = x + y * 8; eieio();
par->cmap_regs[PIDXDATA] = 0xff; eieio();
}
par->cmap_regs[PIDXHI] = 0; eieio();
par->cmap_regs[PIDXLO] = CURS1R; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
par->cmap_regs[PIDXLO] = CURS1G; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
par->cmap_regs[PIDXLO] = CURS1B; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
par->cmap_regs[PIDXLO] = CURS2R; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
par->cmap_regs[PIDXLO] = CURS2G; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
par->cmap_regs[PIDXLO] = CURS2B; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
par->cmap_regs[PIDXLO] = CURS3R; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
par->cmap_regs[PIDXLO] = CURS3G; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
par->cmap_regs[PIDXLO] = CURS3B; eieio();
par->cmap_regs[PIDXDATA] = fgc; eieio();
} else {
par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
par->cmap_regs[TVPIDATA] &= 0x03; eieio();
par->cmap_regs[TVPADDRW] = 0; eieio();
for (x = 0; x < 0x200; x++) {
par->cmap_regs[TVPCRDAT] = 0x00; eieio();
}
for (x = 0; x < 0x200; x++) {
par->cmap_regs[TVPCRDAT] = 0xff; eieio();
}
par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
par->cmap_regs[TVPIDATA] &= 0x03; eieio();
for (y = 0; y < height; y++)
for (x = 0; x < width >> 3; x++) {
par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
par->cmap_regs[TVPCRDAT] = 0xff; eieio();
}
par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
par->cmap_regs[TVPIDATA] |= 0x08; eieio();
for (y = 0; y < height; y++)
for (x = 0; x < width >> 3; x++) {
par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
par->cmap_regs[TVPCRDAT] = 0xff; eieio();
}
par->cmap_regs[TVPCADRW] = 0x00; eieio();
for (x = 0; x < 12; x++) {
par->cmap_regs[TVPCDATA] = fgc;
eieio();
}
}
return 1;
}
static void
imstt_set_cursor(struct imstt_par *par, struct fb_image *d, int on)
{
if (par->ramdac == IBM) {
par->cmap_regs[PIDXHI] = 0; eieio();
if (!on) {
par->cmap_regs[PIDXLO] = CURSCTL; eieio();
par->cmap_regs[PIDXDATA] = 0x00; eieio();
} else {
par->cmap_regs[PIDXLO] = CURSXHI; eieio();
par->cmap_regs[PIDXDATA] = d->dx >> 8; eieio();
par->cmap_regs[PIDXLO] = CURSXLO; eieio();
par->cmap_regs[PIDXDATA] = d->dx & 0xff;eieio();
par->cmap_regs[PIDXLO] = CURSYHI; eieio();
par->cmap_regs[PIDXDATA] = d->dy >> 8; eieio();
par->cmap_regs[PIDXLO] = CURSYLO; eieio();
par->cmap_regs[PIDXDATA] = d->dy & 0xff;eieio();
par->cmap_regs[PIDXLO] = CURSCTL; eieio();
par->cmap_regs[PIDXDATA] = 0x02; eieio();
}
} else {
if (!on) {
par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
par->cmap_regs[TVPIDATA] = 0x00; eieio();
} else {
__u16 x = d->dx + 0x40, y = d->dy + 0x40;
par->cmap_regs[TVPCXPOH] = x >> 8; eieio();
par->cmap_regs[TVPCXPOL] = x & 0xff; eieio();
par->cmap_regs[TVPCYPOH] = y >> 8; eieio();
par->cmap_regs[TVPCYPOL] = y & 0xff; eieio();
par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
par->cmap_regs[TVPIDATA] = 0x02; eieio();
}
}
}
static int
imsttfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct imstt_par *par = info->par;
u32 flags = cursor->set, fg, bg, xx, yy;
if (cursor->dest == NULL && cursor->rop == ROP_XOR)
return 1;
imstt_set_cursor(info, cursor, 0);
if (flags & FB_CUR_SETPOS) {
xx = cursor->image.dx - info->var.xoffset;
yy = cursor->image.dy - info->var.yoffset;
}
if (flags & FB_CUR_SETSIZE) {
}
if (flags & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP)) {
int fg_idx = cursor->image.fg_color;
int width = (cursor->image.width+7)/8;
u8 *dat = (u8 *) cursor->image.data;
u8 *dst = (u8 *) cursor->dest;
u8 *msk = (u8 *) cursor->mask;
switch (cursor->rop) {
case ROP_XOR:
for (i = 0; i < cursor->image.height; i++) {
for (j = 0; j < width; j++) {
d_idx = i * MAX_CURS/8 + j;
data[d_idx] = byte_rev[dat[s_idx] ^
dst[s_idx]];
mask[d_idx] = byte_rev[msk[s_idx]];
s_idx++;
}
}
break;
case ROP_COPY:
default:
for (i = 0; i < cursor->image.height; i++) {
for (j = 0; j < width; j++) {
d_idx = i * MAX_CURS/8 + j;
data[d_idx] = byte_rev[dat[s_idx]];
mask[d_idx] = byte_rev[msk[s_idx]];
s_idx++;
}
}
break;
}
fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
((info->cmap.green[fg_idx] & 0xf8) << 2) |
((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
imsttfb_load_cursor_image(par, xx, yy, fgc);
}
if (cursor->enable)
imstt_set_cursor(info, cursor, 1);
return 0;
}
#endif
#define FBIMSTT_SETREG 0x545401
#define FBIMSTT_GETREG 0x545402
#define FBIMSTT_SETCMAPREG 0x545403
#define FBIMSTT_GETCMAPREG 0x545404
#define FBIMSTT_SETIDXREG 0x545405
#define FBIMSTT_GETIDXREG 0x545406
static int
imsttfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
{
struct imstt_par *par = info->par;
void __user *argp = (void __user *)arg;
__u32 reg[2];
__u8 idx[2];
switch (cmd) {
case FBIMSTT_SETREG:
if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
return -EFAULT;
write_reg_le32(par->dc_regs, reg[0], reg[1]);
return 0;
case FBIMSTT_GETREG:
if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
return -EFAULT;
reg[1] = read_reg_le32(par->dc_regs, reg[0]);
if (copy_to_user((void __user *)(arg + 4), ®[1], 4))
return -EFAULT;
return 0;
case FBIMSTT_SETCMAPREG:
if (copy_from_user(reg, argp, 8) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
return -EFAULT;
write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]);
return 0;
case FBIMSTT_GETCMAPREG:
if (copy_from_user(reg, argp, 4) || reg[0] > (0x1000 - sizeof(reg[0])) / sizeof(reg[0]))
return -EFAULT;
reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]);
if (copy_to_user((void __user *)(arg + 4), ®[1], 4))
return -EFAULT;
return 0;
case FBIMSTT_SETIDXREG:
if (copy_from_user(idx, argp, 2))
return -EFAULT;
par->cmap_regs[PIDXHI] = 0; eieio();
par->cmap_regs[PIDXLO] = idx[0]; eieio();
par->cmap_regs[PIDXDATA] = idx[1]; eieio();
return 0;
case FBIMSTT_GETIDXREG:
if (copy_from_user(idx, argp, 1))
return -EFAULT;
par->cmap_regs[PIDXHI] = 0; eieio();
par->cmap_regs[PIDXLO] = idx[0]; eieio();
idx[1] = par->cmap_regs[PIDXDATA];
if (copy_to_user((void __user *)(arg + 1), &idx[1], 1))
return -EFAULT;
return 0;
default:
return -ENOIOCTLCMD;
}
}
static const struct pci_device_id imsttfb_pci_tbl[] = {
{ PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT128,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, IBM },
{ PCI_VENDOR_ID_IMS, PCI_DEVICE_ID_IMS_TT3D,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, TVP },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, imsttfb_pci_tbl);
static struct pci_driver imsttfb_pci_driver = {
.name = "imsttfb",
.id_table = imsttfb_pci_tbl,
.probe = imsttfb_probe,
.remove = imsttfb_remove,
};
static const struct fb_ops imsttfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = imsttfb_check_var,
.fb_set_par = imsttfb_set_par,
.fb_setcolreg = imsttfb_setcolreg,
.fb_pan_display = imsttfb_pan_display,
.fb_blank = imsttfb_blank,
.fb_fillrect = imsttfb_fillrect,
.fb_copyarea = imsttfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_ioctl = imsttfb_ioctl,
};
static int init_imstt(struct fb_info *info)
{
struct imstt_par *par = info->par;
__u32 i, tmp, *ip, *end;
tmp = read_reg_le32(par->dc_regs, PRC);
if (par->ramdac == IBM)
info->fix.smem_len = (tmp & 0x0004) ? 0x400000 : 0x200000;
else
info->fix.smem_len = 0x800000;
ip = (__u32 *)info->screen_base;
end = (__u32 *)(info->screen_base + info->fix.smem_len);
while (ip < end)
*ip++ = 0;
/* initialize the card */
tmp = read_reg_le32(par->dc_regs, STGCTL);
write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
write_reg_le32(par->dc_regs, SSR, 0);
/* set default values for DAC registers */
if (par->ramdac == IBM) {
par->cmap_regs[PPMASK] = 0xff;
eieio();
par->cmap_regs[PIDXHI] = 0;
eieio();
for (i = 0; i < ARRAY_SIZE(ibm_initregs); i++) {
par->cmap_regs[PIDXLO] = ibm_initregs[i].addr;
eieio();
par->cmap_regs[PIDXDATA] = ibm_initregs[i].value;
eieio();
}
} else {
for (i = 0; i < ARRAY_SIZE(tvp_initregs); i++) {
par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;
eieio();
par->cmap_regs[TVPIDATA] = tvp_initregs[i].value;
eieio();
}
}
#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
if (IS_REACHABLE(CONFIG_NVRAM) && machine_is(powermac)) {
int vmode = init_vmode, cmode = init_cmode;
if (vmode == -1) {
vmode = nvram_read_byte(NV_VMODE);
if (vmode <= 0 || vmode > VMODE_MAX)
vmode = VMODE_640_480_67;
}
if (cmode == -1) {
cmode = nvram_read_byte(NV_CMODE);
if (cmode < CMODE_8 || cmode > CMODE_32)
cmode = CMODE_8;
}
if (mac_vmode_to_var(vmode, cmode, &info->var)) {
info->var.xres = info->var.xres_virtual = INIT_XRES;
info->var.yres = info->var.yres_virtual = INIT_YRES;
info->var.bits_per_pixel = INIT_BPP;
}
} else
#endif
{
info->var.xres = info->var.xres_virtual = INIT_XRES;
info->var.yres = info->var.yres_virtual = INIT_YRES;
info->var.bits_per_pixel = INIT_BPP;
}
if ((info->var.xres * info->var.yres) * (info->var.bits_per_pixel >> 3) > info->fix.smem_len
|| !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) {
printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
framebuffer_release(info);
return -ENODEV;
}
sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP");
info->fix.mmio_len = 0x1000;
info->fix.accel = FB_ACCEL_IMS_TWINTURBO;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = info->var.bits_per_pixel == 8 ? FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_DIRECTCOLOR;
info->fix.line_length = info->var.xres * (info->var.bits_per_pixel >> 3);
info->fix.xpanstep = 8;
info->fix.ypanstep = 1;
info->fix.ywrapstep = 0;
info->var.accel_flags = FB_ACCELF_TEXT;
// if (par->ramdac == IBM)
// imstt_cursor_init(info);
if (info->var.green.length == 6)
set_565(par);
else
set_555(par);
set_imstt_regvals(info, info->var.bits_per_pixel);
info->var.pixclock = 1000000 / getclkMHz(par);
info->fbops = &imsttfb_ops;
info->flags = FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_YPAN;
if (fb_alloc_cmap(&info->cmap, 0, 0)) {
framebuffer_release(info);
return -ENODEV;
}
if (register_framebuffer(info) < 0) {
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
return -ENODEV;
}
tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8;
fb_info(info, "%s frame buffer; %uMB vram; chip version %u\n",
info->fix.id, info->fix.smem_len >> 20, tmp);
return 0;
}
static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
unsigned long addr, size;
struct imstt_par *par;
struct fb_info *info;
struct device_node *dp;
int ret;
ret = aperture_remove_conflicting_pci_devices(pdev, "imsttfb");
if (ret)
return ret;
ret = -ENOMEM;
dp = pci_device_to_OF_node(pdev);
if(dp)
printk(KERN_INFO "%s: OF name %pOFn\n",__func__, dp);
else if (IS_ENABLED(CONFIG_OF))
printk(KERN_ERR "imsttfb: no OF node for pci device\n");
info = framebuffer_alloc(sizeof(struct imstt_par), &pdev->dev);
if (!info)
return -ENOMEM;
par = info->par;
addr = pci_resource_start (pdev, 0);
size = pci_resource_len (pdev, 0);
if (!request_mem_region(addr, size, "imsttfb")) {
printk(KERN_ERR "imsttfb: Can't reserve memory region\n");
framebuffer_release(info);
return -ENODEV;
}
switch (pdev->device) {
case PCI_DEVICE_ID_IMS_TT128: /* IMS,tt128mbA */
par->ramdac = IBM;
if (of_node_name_eq(dp, "IMS,tt128mb8") ||
of_node_name_eq(dp, "IMS,tt128mb8A"))
par->ramdac = TVP;
break;
case PCI_DEVICE_ID_IMS_TT3D: /* IMS,tt3d */
par->ramdac = TVP;
break;
default:
printk(KERN_INFO "imsttfb: Device 0x%x unknown, "
"contact maintainer.\n", pdev->device);
ret = -ENODEV;
goto error;
}
info->fix.smem_start = addr;
info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ?
0x400000 : 0x800000);
if (!info->screen_base)
goto error;
info->fix.mmio_start = addr + 0x800000;
par->dc_regs = ioremap(addr + 0x800000, 0x1000);
if (!par->dc_regs)
goto error;
par->cmap_regs_phys = addr + 0x840000;
par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
if (!par->cmap_regs)
goto error;
info->pseudo_palette = par->palette;
ret = init_imstt(info);
if (ret)
goto error;
pci_set_drvdata(pdev, info);
return ret;
error:
if (par->dc_regs)
iounmap(par->dc_regs);
if (info->screen_base)
iounmap(info->screen_base);
release_mem_region(addr, size);
framebuffer_release(info);
return ret;
}
static void imsttfb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct imstt_par *par = info->par;
int size = pci_resource_len(pdev, 0);
unregister_framebuffer(info);
iounmap(par->cmap_regs);
iounmap(par->dc_regs);
iounmap(info->screen_base);
release_mem_region(info->fix.smem_start, size);
framebuffer_release(info);
}
#ifndef MODULE
static int __init
imsttfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "font:", 5)) {
char *p;
int i;
p = this_opt + 5;
for (i = 0; i < sizeof(fontname) - 1; i++)
if (!*p || *p == ' ' || *p == ',')
break;
memcpy(fontname, this_opt + 5, i);
fontname[i] = 0;
} else if (!strncmp(this_opt, "inverse", 7)) {
inverse = 1;
fb_invert_cmaps();
}
#if defined(CONFIG_PPC_PMAC)
else if (!strncmp(this_opt, "vmode:", 6)) {
int vmode = simple_strtoul(this_opt+6, NULL, 0);
if (vmode > 0 && vmode <= VMODE_MAX)
init_vmode = vmode;
} else if (!strncmp(this_opt, "cmode:", 6)) {
int cmode = simple_strtoul(this_opt+6, NULL, 0);
switch (cmode) {
case CMODE_8:
case 8:
init_cmode = CMODE_8;
break;
case CMODE_16:
case 15:
case 16:
init_cmode = CMODE_16;
break;
case CMODE_32:
case 24:
case 32:
init_cmode = CMODE_32;
break;
}
}
#endif
}
return 0;
}
#endif /* MODULE */
static int __init imsttfb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("imsttfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("imsttfb", &option))
return -ENODEV;
imsttfb_setup(option);
#endif
return pci_register_driver(&imsttfb_pci_driver);
}
static void __exit imsttfb_exit(void)
{
pci_unregister_driver(&imsttfb_pci_driver);
}
MODULE_LICENSE("GPL");
module_init(imsttfb_init);
module_exit(imsttfb_exit);
| linux-master | drivers/video/fbdev/imsttfb.c |
/*
* Xilinx TFT frame buffer driver
*
* Author: MontaVista Software, Inc.
* [email protected]
*
* 2002-2007 (c) MontaVista Software, Inc.
* 2007 (c) Secret Lab Technologies, Ltd.
* 2009 (c) Xilinx Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/*
* This driver was based on au1100fb.c by MontaVista rewritten for 2.6
* by Embedded Alley Solutions <[email protected]>, which in turn
* was based on skeletonfb.c, Skeleton for a frame buffer device by
* Geert Uytterhoeven.
*/
#include <linux/device.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>
#include <linux/io.h>
#include <linux/slab.h>
#ifdef CONFIG_PPC_DCR
#include <asm/dcr.h>
#endif
#define DRIVER_NAME "xilinxfb"
/*
* Xilinx calls it "TFT LCD Controller" though it can also be used for
* the VGA port on the Xilinx ML40x board. This is a hardware display
* controller for a 640x480 resolution TFT or VGA screen.
*
* The interface to the framebuffer is nice and simple. There are two
* control registers. The first tells the LCD interface where in memory
* the frame buffer is (only the 11 most significant bits are used, so
* don't start thinking about scrolling). The second allows the LCD to
* be turned on or off as well as rotated 180 degrees.
*
* In case of direct BUS access the second control register will be at
* an offset of 4 as compared to the DCR access where the offset is 1
* i.e. REG_CTRL. So this is taken care in the function
* xilinx_fb_out32 where it left shifts the offset 2 times in case of
* direct BUS access.
*/
#define NUM_REGS 2
#define REG_FB_ADDR 0
#define REG_CTRL 1
#define REG_CTRL_ENABLE 0x0001
#define REG_CTRL_ROTATE 0x0002
/*
* The hardware only handles a single mode: 640x480 24 bit true
* color. Each pixel gets a word (32 bits) of memory. Within each word,
* the 8 most significant bits are ignored, the next 8 bits are the red
* level, the next 8 bits are the green level and the 8 least
* significant bits are the blue level. Each row of the LCD uses 1024
* words, but only the first 640 pixels are displayed with the other 384
* words being ignored. There are 480 rows.
*/
#define BYTES_PER_PIXEL 4
#define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
#define RED_SHIFT 16
#define GREEN_SHIFT 8
#define BLUE_SHIFT 0
#define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
/* ML300/403 reference design framebuffer driver platform data struct */
struct xilinxfb_platform_data {
u32 rotate_screen; /* Flag to rotate display 180 degrees */
u32 screen_height_mm; /* Physical dimensions of screen in mm */
u32 screen_width_mm;
u32 xres, yres; /* resolution of screen in pixels */
u32 xvirt, yvirt; /* resolution of memory buffer */
/* Physical address of framebuffer memory; If non-zero, driver
* will use provided memory address instead of allocating one from
* the consistent pool.
*/
u32 fb_phys;
};
/*
* Default xilinxfb configuration
*/
static const struct xilinxfb_platform_data xilinx_fb_default_pdata = {
.xres = 640,
.yres = 480,
.xvirt = 1024,
.yvirt = 480,
};
/*
* Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
*/
static const struct fb_fix_screeninfo xilinx_fb_fix = {
.id = "Xilinx",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.accel = FB_ACCEL_NONE
};
static const struct fb_var_screeninfo xilinx_fb_var = {
.bits_per_pixel = BITS_PER_PIXEL,
.red = { RED_SHIFT, 8, 0 },
.green = { GREEN_SHIFT, 8, 0 },
.blue = { BLUE_SHIFT, 8, 0 },
.transp = { 0, 0, 0 },
.activate = FB_ACTIVATE_NOW
};
#define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */
#define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */
struct xilinxfb_drvdata {
struct fb_info info; /* FB driver info record */
phys_addr_t regs_phys; /* phys. address of the control
* registers
*/
void __iomem *regs; /* virt. address of the control
* registers
*/
#ifdef CONFIG_PPC_DCR
dcr_host_t dcr_host;
unsigned int dcr_len;
#endif
void *fb_virt; /* virt. address of the frame buffer */
dma_addr_t fb_phys; /* phys. address of the frame buffer */
int fb_alloced; /* Flag, was the fb memory alloced? */
u8 flags; /* features of the driver */
u32 reg_ctrl_default;
u32 pseudo_palette[PALETTE_ENTRIES_NO];
/* Fake palette of 16 colors */
};
#define to_xilinxfb_drvdata(_info) \
container_of(_info, struct xilinxfb_drvdata, info)
/*
* The XPS TFT Controller can be accessed through BUS or DCR interface.
* To perform the read/write on the registers we need to check on
* which bus its connected and call the appropriate write API.
*/
static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
u32 val)
{
if (drvdata->flags & BUS_ACCESS_FLAG) {
if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
iowrite32(val, drvdata->regs + (offset << 2));
else
iowrite32be(val, drvdata->regs + (offset << 2));
}
#ifdef CONFIG_PPC_DCR
else
dcr_write(drvdata->dcr_host, offset, val);
#endif
}
static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset)
{
if (drvdata->flags & BUS_ACCESS_FLAG) {
if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
return ioread32(drvdata->regs + (offset << 2));
else
return ioread32be(drvdata->regs + (offset << 2));
}
#ifdef CONFIG_PPC_DCR
else
return dcr_read(drvdata->dcr_host, offset);
#endif
return 0;
}
static int
xilinx_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
unsigned int blue, unsigned int transp, struct fb_info *fbi)
{
u32 *palette = fbi->pseudo_palette;
if (regno >= PALETTE_ENTRIES_NO)
return -EINVAL;
if (fbi->var.grayscale) {
/* Convert color to grayscale.
* grayscale = 0.30*R + 0.59*G + 0.11*B
*/
blue = (red * 77 + green * 151 + blue * 28 + 127) >> 8;
green = blue;
red = green;
}
/* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
/* We only handle 8 bits of each color. */
red >>= 8;
green >>= 8;
blue >>= 8;
palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
(blue << BLUE_SHIFT);
return 0;
}
static int
xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
{
struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* turn on panel */
xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
break;
case FB_BLANK_NORMAL:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
/* turn off panel */
xilinx_fb_out32(drvdata, REG_CTRL, 0);
break;
default:
break;
}
return 0; /* success */
}
static const struct fb_ops xilinxfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = xilinx_fb_setcolreg,
.fb_blank = xilinx_fb_blank,
};
/* ---------------------------------------------------------------------
* Bus independent setup/teardown
*/
static int xilinxfb_assign(struct platform_device *pdev,
struct xilinxfb_drvdata *drvdata,
struct xilinxfb_platform_data *pdata)
{
int rc;
struct device *dev = &pdev->dev;
int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
if (drvdata->flags & BUS_ACCESS_FLAG) {
struct resource *res;
drvdata->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(drvdata->regs))
return PTR_ERR(drvdata->regs);
drvdata->regs_phys = res->start;
}
/* Allocate the framebuffer memory */
if (pdata->fb_phys) {
drvdata->fb_phys = pdata->fb_phys;
drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
} else {
drvdata->fb_alloced = 1;
drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
&drvdata->fb_phys,
GFP_KERNEL);
}
if (!drvdata->fb_virt) {
dev_err(dev, "Could not allocate frame buffer memory\n");
return -ENOMEM;
}
/* Clear (turn to black) the framebuffer */
memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
/* Tell the hardware where the frame buffer is */
xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
rc = xilinx_fb_in32(drvdata, REG_FB_ADDR);
/* Endianness detection */
if (rc != drvdata->fb_phys) {
drvdata->flags |= LITTLE_ENDIAN_ACCESS;
xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
}
/* Turn on the display */
drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
if (pdata->rotate_screen)
drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
/* Fill struct fb_info */
drvdata->info.device = dev;
drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
drvdata->info.fbops = &xilinxfb_ops;
drvdata->info.fix = xilinx_fb_fix;
drvdata->info.fix.smem_start = drvdata->fb_phys;
drvdata->info.fix.smem_len = fbsize;
drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
drvdata->info.pseudo_palette = drvdata->pseudo_palette;
drvdata->info.var = xilinx_fb_var;
drvdata->info.var.height = pdata->screen_height_mm;
drvdata->info.var.width = pdata->screen_width_mm;
drvdata->info.var.xres = pdata->xres;
drvdata->info.var.yres = pdata->yres;
drvdata->info.var.xres_virtual = pdata->xvirt;
drvdata->info.var.yres_virtual = pdata->yvirt;
/* Allocate a colour map */
rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
if (rc) {
dev_err(dev, "Fail to allocate colormap (%d entries)\n",
PALETTE_ENTRIES_NO);
goto err_cmap;
}
/* Register new frame buffer */
rc = register_framebuffer(&drvdata->info);
if (rc) {
dev_err(dev, "Could not register frame buffer\n");
goto err_regfb;
}
if (drvdata->flags & BUS_ACCESS_FLAG) {
/* Put a banner in the log (for DEBUG) */
dev_dbg(dev, "regs: phys=%pa, virt=%p\n",
&drvdata->regs_phys, drvdata->regs);
}
/* Put a banner in the log (for DEBUG) */
dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
(unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
return 0; /* success */
err_regfb:
fb_dealloc_cmap(&drvdata->info.cmap);
err_cmap:
if (drvdata->fb_alloced)
dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
drvdata->fb_phys);
else
iounmap(drvdata->fb_virt);
/* Turn off the display */
xilinx_fb_out32(drvdata, REG_CTRL, 0);
return rc;
}
static void xilinxfb_release(struct device *dev)
{
struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
#endif
unregister_framebuffer(&drvdata->info);
fb_dealloc_cmap(&drvdata->info.cmap);
if (drvdata->fb_alloced)
dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
drvdata->fb_virt, drvdata->fb_phys);
else
iounmap(drvdata->fb_virt);
/* Turn off the display */
xilinx_fb_out32(drvdata, REG_CTRL, 0);
#ifdef CONFIG_PPC_DCR
/* Release the resources, as allocated based on interface */
if (!(drvdata->flags & BUS_ACCESS_FLAG))
dcr_unmap(drvdata->dcr_host, drvdata->dcr_len);
#endif
}
/* ---------------------------------------------------------------------
* OF bus binding
*/
static int xilinxfb_of_probe(struct platform_device *pdev)
{
const u32 *prop;
u32 tft_access = 0;
struct xilinxfb_platform_data pdata;
int size;
struct xilinxfb_drvdata *drvdata;
/* Copy with the default pdata (not a ptr reference!) */
pdata = xilinx_fb_default_pdata;
/* Allocate the driver data region */
drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
/*
* To check whether the core is connected directly to DCR or BUS
* interface and initialize the tft_access accordingly.
*/
of_property_read_u32(pdev->dev.of_node, "xlnx,dcr-splb-slave-if",
&tft_access);
/*
* Fill the resource structure if its direct BUS interface
* otherwise fill the dcr_host structure.
*/
if (tft_access)
drvdata->flags |= BUS_ACCESS_FLAG;
#ifdef CONFIG_PPC_DCR
else {
int start;
start = dcr_resource_start(pdev->dev.of_node, 0);
drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0);
drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len);
if (!DCR_MAP_OK(drvdata->dcr_host)) {
dev_err(&pdev->dev, "invalid DCR address\n");
return -ENODEV;
}
}
#endif
prop = of_get_property(pdev->dev.of_node, "phys-size", &size);
if ((prop) && (size >= sizeof(u32) * 2)) {
pdata.screen_width_mm = prop[0];
pdata.screen_height_mm = prop[1];
}
prop = of_get_property(pdev->dev.of_node, "resolution", &size);
if ((prop) && (size >= sizeof(u32) * 2)) {
pdata.xres = prop[0];
pdata.yres = prop[1];
}
prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size);
if ((prop) && (size >= sizeof(u32) * 2)) {
pdata.xvirt = prop[0];
pdata.yvirt = prop[1];
}
pdata.rotate_screen = of_property_read_bool(pdev->dev.of_node, "rotate-display");
platform_set_drvdata(pdev, drvdata);
return xilinxfb_assign(pdev, drvdata, &pdata);
}
static void xilinxfb_of_remove(struct platform_device *op)
{
xilinxfb_release(&op->dev);
}
/* Match table for of_platform binding */
static const struct of_device_id xilinxfb_of_match[] = {
{ .compatible = "xlnx,xps-tft-1.00.a", },
{ .compatible = "xlnx,xps-tft-2.00.a", },
{ .compatible = "xlnx,xps-tft-2.01.a", },
{ .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
{ .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
{},
};
MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
static struct platform_driver xilinxfb_of_driver = {
.probe = xilinxfb_of_probe,
.remove_new = xilinxfb_of_remove,
.driver = {
.name = DRIVER_NAME,
.of_match_table = xilinxfb_of_match,
},
};
module_platform_driver(xilinxfb_of_driver);
MODULE_AUTHOR("MontaVista Software, Inc. <[email protected]>");
MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/xilinxfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2012, Microsoft Corporation.
*
* Author:
* Haiyang Zhang <[email protected]>
*/
/*
* Hyper-V Synthetic Video Frame Buffer Driver
*
* This is the driver for the Hyper-V Synthetic Video, which supports
* screen resolution up to Full HD 1920x1080 with 32 bit color on Windows
* Server 2012, and 1600x1200 with 16 bit color on Windows Server 2008 R2
* or earlier.
*
* It also solves the double mouse cursor issue of the emulated video mode.
*
* The default screen resolution is 1152x864, which may be changed by a
* kernel parameter:
* video=hyperv_fb:<width>x<height>
* For example: video=hyperv_fb:1280x1024
*
* Portrait orientation is also supported:
* For example: video=hyperv_fb:864x1152
*
* When a Windows 10 RS5+ host is used, the virtual machine screen
* resolution is obtained from the host. The "video=hyperv_fb" option is
* not needed, but still can be used to overwrite what the host specifies.
* The VM resolution on the host could be set by executing the powershell
* "set-vmvideo" command. For example
* set-vmvideo -vmname name -horizontalresolution:1920 \
* -verticalresolution:1200 -resolutiontype single
*
* Gen 1 VMs also support direct using VM's physical memory for framebuffer.
* It could improve the efficiency and performance for framebuffer and VM.
* This requires to allocate contiguous physical memory from Linux kernel's
* CMA memory allocator. To enable this, supply a kernel parameter to give
* enough memory space to CMA allocator for framebuffer. For example:
* cma=130m
* This gives 130MB memory to CMA allocator that can be allocated to
* framebuffer. For reference, 8K resolution (7680x4320) takes about
* 127MB memory.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/screen_info.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/completion.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/panic_notifier.h>
#include <linux/efi.h>
#include <linux/console.h>
#include <linux/hyperv.h>
/* Hyper-V Synthetic Video Protocol definitions and structures */
#define MAX_VMBUS_PKT_SIZE 0x4000
#define SYNTHVID_VERSION(major, minor) ((minor) << 16 | (major))
/* Support for VERSION_WIN7 is removed. #define is retained for reference. */
#define SYNTHVID_VERSION_WIN7 SYNTHVID_VERSION(3, 0)
#define SYNTHVID_VERSION_WIN8 SYNTHVID_VERSION(3, 2)
#define SYNTHVID_VERSION_WIN10 SYNTHVID_VERSION(3, 5)
#define SYNTHVID_VER_GET_MAJOR(ver) (ver & 0x0000ffff)
#define SYNTHVID_VER_GET_MINOR(ver) ((ver & 0xffff0000) >> 16)
#define SYNTHVID_DEPTH_WIN8 32
#define SYNTHVID_FB_SIZE_WIN8 (8 * 1024 * 1024)
enum pipe_msg_type {
PIPE_MSG_INVALID,
PIPE_MSG_DATA,
PIPE_MSG_MAX
};
struct pipe_msg_hdr {
u32 type;
u32 size; /* size of message after this field */
} __packed;
enum synthvid_msg_type {
SYNTHVID_ERROR = 0,
SYNTHVID_VERSION_REQUEST = 1,
SYNTHVID_VERSION_RESPONSE = 2,
SYNTHVID_VRAM_LOCATION = 3,
SYNTHVID_VRAM_LOCATION_ACK = 4,
SYNTHVID_SITUATION_UPDATE = 5,
SYNTHVID_SITUATION_UPDATE_ACK = 6,
SYNTHVID_POINTER_POSITION = 7,
SYNTHVID_POINTER_SHAPE = 8,
SYNTHVID_FEATURE_CHANGE = 9,
SYNTHVID_DIRT = 10,
SYNTHVID_RESOLUTION_REQUEST = 13,
SYNTHVID_RESOLUTION_RESPONSE = 14,
SYNTHVID_MAX = 15
};
#define SYNTHVID_EDID_BLOCK_SIZE 128
#define SYNTHVID_MAX_RESOLUTION_COUNT 64
struct hvd_screen_info {
u16 width;
u16 height;
} __packed;
struct synthvid_msg_hdr {
u32 type;
u32 size; /* size of this header + payload after this field*/
} __packed;
struct synthvid_version_req {
u32 version;
} __packed;
struct synthvid_version_resp {
u32 version;
u8 is_accepted;
u8 max_video_outputs;
} __packed;
struct synthvid_supported_resolution_req {
u8 maximum_resolution_count;
} __packed;
struct synthvid_supported_resolution_resp {
u8 edid_block[SYNTHVID_EDID_BLOCK_SIZE];
u8 resolution_count;
u8 default_resolution_index;
u8 is_standard;
struct hvd_screen_info
supported_resolution[SYNTHVID_MAX_RESOLUTION_COUNT];
} __packed;
struct synthvid_vram_location {
u64 user_ctx;
u8 is_vram_gpa_specified;
u64 vram_gpa;
} __packed;
struct synthvid_vram_location_ack {
u64 user_ctx;
} __packed;
struct video_output_situation {
u8 active;
u32 vram_offset;
u8 depth_bits;
u32 width_pixels;
u32 height_pixels;
u32 pitch_bytes;
} __packed;
struct synthvid_situation_update {
u64 user_ctx;
u8 video_output_count;
struct video_output_situation video_output[1];
} __packed;
struct synthvid_situation_update_ack {
u64 user_ctx;
} __packed;
struct synthvid_pointer_position {
u8 is_visible;
u8 video_output;
s32 image_x;
s32 image_y;
} __packed;
#define CURSOR_MAX_X 96
#define CURSOR_MAX_Y 96
#define CURSOR_ARGB_PIXEL_SIZE 4
#define CURSOR_MAX_SIZE (CURSOR_MAX_X * CURSOR_MAX_Y * CURSOR_ARGB_PIXEL_SIZE)
#define CURSOR_COMPLETE (-1)
struct synthvid_pointer_shape {
u8 part_idx;
u8 is_argb;
u32 width; /* CURSOR_MAX_X at most */
u32 height; /* CURSOR_MAX_Y at most */
u32 hot_x; /* hotspot relative to upper-left of pointer image */
u32 hot_y;
u8 data[4];
} __packed;
struct synthvid_feature_change {
u8 is_dirt_needed;
u8 is_ptr_pos_needed;
u8 is_ptr_shape_needed;
u8 is_situ_needed;
} __packed;
struct rect {
s32 x1, y1; /* top left corner */
s32 x2, y2; /* bottom right corner, exclusive */
} __packed;
struct synthvid_dirt {
u8 video_output;
u8 dirt_count;
struct rect rect[1];
} __packed;
struct synthvid_msg {
struct pipe_msg_hdr pipe_hdr;
struct synthvid_msg_hdr vid_hdr;
union {
struct synthvid_version_req ver_req;
struct synthvid_version_resp ver_resp;
struct synthvid_vram_location vram;
struct synthvid_vram_location_ack vram_ack;
struct synthvid_situation_update situ;
struct synthvid_situation_update_ack situ_ack;
struct synthvid_pointer_position ptr_pos;
struct synthvid_pointer_shape ptr_shape;
struct synthvid_feature_change feature_chg;
struct synthvid_dirt dirt;
struct synthvid_supported_resolution_req resolution_req;
struct synthvid_supported_resolution_resp resolution_resp;
};
} __packed;
/* FB driver definitions and structures */
#define HVFB_WIDTH 1152 /* default screen width */
#define HVFB_HEIGHT 864 /* default screen height */
#define HVFB_WIDTH_MIN 640
#define HVFB_HEIGHT_MIN 480
#define RING_BUFSIZE (256 * 1024)
#define VSP_TIMEOUT (10 * HZ)
#define HVFB_UPDATE_DELAY (HZ / 20)
#define HVFB_ONDEMAND_THROTTLE (HZ / 20)
struct hvfb_par {
struct fb_info *info;
struct resource *mem;
bool fb_ready; /* fb device is ready */
struct completion wait;
u32 synthvid_version;
struct delayed_work dwork;
bool update;
bool update_saved; /* The value of 'update' before hibernation */
u32 pseudo_palette[16];
u8 init_buf[MAX_VMBUS_PKT_SIZE];
u8 recv_buf[MAX_VMBUS_PKT_SIZE];
/* If true, the VSC notifies the VSP on every framebuffer change */
bool synchronous_fb;
/* If true, need to copy from deferred IO mem to framebuffer mem */
bool need_docopy;
struct notifier_block hvfb_panic_nb;
/* Memory for deferred IO and frame buffer itself */
unsigned char *dio_vp;
unsigned char *mmio_vp;
phys_addr_t mmio_pp;
/* Dirty rectangle, protected by delayed_refresh_lock */
int x1, y1, x2, y2;
bool delayed_refresh;
spinlock_t delayed_refresh_lock;
};
static uint screen_width = HVFB_WIDTH;
static uint screen_height = HVFB_HEIGHT;
static uint screen_depth;
static uint screen_fb_size;
static uint dio_fb_size; /* FB size for deferred IO */
/* Send message to Hyper-V host */
static inline int synthvid_send(struct hv_device *hdev,
struct synthvid_msg *msg)
{
static atomic64_t request_id = ATOMIC64_INIT(0);
int ret;
msg->pipe_hdr.type = PIPE_MSG_DATA;
msg->pipe_hdr.size = msg->vid_hdr.size;
ret = vmbus_sendpacket(hdev->channel, msg,
msg->vid_hdr.size + sizeof(struct pipe_msg_hdr),
atomic64_inc_return(&request_id),
VM_PKT_DATA_INBAND, 0);
if (ret)
pr_err_ratelimited("Unable to send packet via vmbus; error %d\n", ret);
return ret;
}
/* Send screen resolution info to host */
static int synthvid_send_situ(struct hv_device *hdev)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct synthvid_msg msg;
if (!info)
return -ENODEV;
memset(&msg, 0, sizeof(struct synthvid_msg));
msg.vid_hdr.type = SYNTHVID_SITUATION_UPDATE;
msg.vid_hdr.size = sizeof(struct synthvid_msg_hdr) +
sizeof(struct synthvid_situation_update);
msg.situ.user_ctx = 0;
msg.situ.video_output_count = 1;
msg.situ.video_output[0].active = 1;
msg.situ.video_output[0].vram_offset = 0;
msg.situ.video_output[0].depth_bits = info->var.bits_per_pixel;
msg.situ.video_output[0].width_pixels = info->var.xres;
msg.situ.video_output[0].height_pixels = info->var.yres;
msg.situ.video_output[0].pitch_bytes = info->fix.line_length;
synthvid_send(hdev, &msg);
return 0;
}
/* Send mouse pointer info to host */
static int synthvid_send_ptr(struct hv_device *hdev)
{
struct synthvid_msg msg;
memset(&msg, 0, sizeof(struct synthvid_msg));
msg.vid_hdr.type = SYNTHVID_POINTER_POSITION;
msg.vid_hdr.size = sizeof(struct synthvid_msg_hdr) +
sizeof(struct synthvid_pointer_position);
msg.ptr_pos.is_visible = 1;
msg.ptr_pos.video_output = 0;
msg.ptr_pos.image_x = 0;
msg.ptr_pos.image_y = 0;
synthvid_send(hdev, &msg);
memset(&msg, 0, sizeof(struct synthvid_msg));
msg.vid_hdr.type = SYNTHVID_POINTER_SHAPE;
msg.vid_hdr.size = sizeof(struct synthvid_msg_hdr) +
sizeof(struct synthvid_pointer_shape);
msg.ptr_shape.part_idx = CURSOR_COMPLETE;
msg.ptr_shape.is_argb = 1;
msg.ptr_shape.width = 1;
msg.ptr_shape.height = 1;
msg.ptr_shape.hot_x = 0;
msg.ptr_shape.hot_y = 0;
msg.ptr_shape.data[0] = 0;
msg.ptr_shape.data[1] = 1;
msg.ptr_shape.data[2] = 1;
msg.ptr_shape.data[3] = 1;
synthvid_send(hdev, &msg);
return 0;
}
/* Send updated screen area (dirty rectangle) location to host */
static int
synthvid_update(struct fb_info *info, int x1, int y1, int x2, int y2)
{
struct hv_device *hdev = device_to_hv_device(info->device);
struct synthvid_msg msg;
memset(&msg, 0, sizeof(struct synthvid_msg));
if (x2 == INT_MAX)
x2 = info->var.xres;
if (y2 == INT_MAX)
y2 = info->var.yres;
msg.vid_hdr.type = SYNTHVID_DIRT;
msg.vid_hdr.size = sizeof(struct synthvid_msg_hdr) +
sizeof(struct synthvid_dirt);
msg.dirt.video_output = 0;
msg.dirt.dirt_count = 1;
msg.dirt.rect[0].x1 = (x1 > x2) ? 0 : x1;
msg.dirt.rect[0].y1 = (y1 > y2) ? 0 : y1;
msg.dirt.rect[0].x2 =
(x2 < x1 || x2 > info->var.xres) ? info->var.xres : x2;
msg.dirt.rect[0].y2 =
(y2 < y1 || y2 > info->var.yres) ? info->var.yres : y2;
synthvid_send(hdev, &msg);
return 0;
}
static void hvfb_docopy(struct hvfb_par *par,
unsigned long offset,
unsigned long size)
{
if (!par || !par->mmio_vp || !par->dio_vp || !par->fb_ready ||
size == 0 || offset >= dio_fb_size)
return;
if (offset + size > dio_fb_size)
size = dio_fb_size - offset;
memcpy(par->mmio_vp + offset, par->dio_vp + offset, size);
}
/* Deferred IO callback */
static void synthvid_deferred_io(struct fb_info *p, struct list_head *pagereflist)
{
struct hvfb_par *par = p->par;
struct fb_deferred_io_pageref *pageref;
unsigned long start, end;
int y1, y2, miny, maxy;
miny = INT_MAX;
maxy = 0;
/*
* Merge dirty pages. It is possible that last page cross
* over the end of frame buffer row yres. This is taken care of
* in synthvid_update function by clamping the y2
* value to yres.
*/
list_for_each_entry(pageref, pagereflist, list) {
start = pageref->offset;
end = start + PAGE_SIZE - 1;
y1 = start / p->fix.line_length;
y2 = end / p->fix.line_length;
miny = min_t(int, miny, y1);
maxy = max_t(int, maxy, y2);
/* Copy from dio space to mmio address */
if (par->fb_ready && par->need_docopy)
hvfb_docopy(par, start, PAGE_SIZE);
}
if (par->fb_ready && par->update)
synthvid_update(p, 0, miny, p->var.xres, maxy + 1);
}
static struct fb_deferred_io synthvid_defio = {
.delay = HZ / 20,
.deferred_io = synthvid_deferred_io,
};
/*
* Actions on received messages from host:
* Complete the wait event.
* Or, reply with screen and cursor info.
*/
static void synthvid_recv_sub(struct hv_device *hdev)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par;
struct synthvid_msg *msg;
if (!info)
return;
par = info->par;
msg = (struct synthvid_msg *)par->recv_buf;
/* Complete the wait event */
if (msg->vid_hdr.type == SYNTHVID_VERSION_RESPONSE ||
msg->vid_hdr.type == SYNTHVID_RESOLUTION_RESPONSE ||
msg->vid_hdr.type == SYNTHVID_VRAM_LOCATION_ACK) {
memcpy(par->init_buf, msg, MAX_VMBUS_PKT_SIZE);
complete(&par->wait);
return;
}
/* Reply with screen and cursor info */
if (msg->vid_hdr.type == SYNTHVID_FEATURE_CHANGE) {
if (par->fb_ready) {
synthvid_send_ptr(hdev);
synthvid_send_situ(hdev);
}
par->update = msg->feature_chg.is_dirt_needed;
if (par->update)
schedule_delayed_work(&par->dwork, HVFB_UPDATE_DELAY);
}
}
/* Receive callback for messages from the host */
static void synthvid_receive(void *ctx)
{
struct hv_device *hdev = ctx;
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par;
struct synthvid_msg *recv_buf;
u32 bytes_recvd;
u64 req_id;
int ret;
if (!info)
return;
par = info->par;
recv_buf = (struct synthvid_msg *)par->recv_buf;
do {
ret = vmbus_recvpacket(hdev->channel, recv_buf,
MAX_VMBUS_PKT_SIZE,
&bytes_recvd, &req_id);
if (bytes_recvd > 0 &&
recv_buf->pipe_hdr.type == PIPE_MSG_DATA)
synthvid_recv_sub(hdev);
} while (bytes_recvd > 0 && ret == 0);
}
/* Check if the ver1 version is equal or greater than ver2 */
static inline bool synthvid_ver_ge(u32 ver1, u32 ver2)
{
if (SYNTHVID_VER_GET_MAJOR(ver1) > SYNTHVID_VER_GET_MAJOR(ver2) ||
(SYNTHVID_VER_GET_MAJOR(ver1) == SYNTHVID_VER_GET_MAJOR(ver2) &&
SYNTHVID_VER_GET_MINOR(ver1) >= SYNTHVID_VER_GET_MINOR(ver2)))
return true;
return false;
}
/* Check synthetic video protocol version with the host */
static int synthvid_negotiate_ver(struct hv_device *hdev, u32 ver)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par = info->par;
struct synthvid_msg *msg = (struct synthvid_msg *)par->init_buf;
int ret = 0;
unsigned long t;
memset(msg, 0, sizeof(struct synthvid_msg));
msg->vid_hdr.type = SYNTHVID_VERSION_REQUEST;
msg->vid_hdr.size = sizeof(struct synthvid_msg_hdr) +
sizeof(struct synthvid_version_req);
msg->ver_req.version = ver;
synthvid_send(hdev, msg);
t = wait_for_completion_timeout(&par->wait, VSP_TIMEOUT);
if (!t) {
pr_err("Time out on waiting version response\n");
ret = -ETIMEDOUT;
goto out;
}
if (!msg->ver_resp.is_accepted) {
ret = -ENODEV;
goto out;
}
par->synthvid_version = ver;
pr_info("Synthvid Version major %d, minor %d\n",
SYNTHVID_VER_GET_MAJOR(ver), SYNTHVID_VER_GET_MINOR(ver));
out:
return ret;
}
/* Get current resolution from the host */
static int synthvid_get_supported_resolution(struct hv_device *hdev)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par = info->par;
struct synthvid_msg *msg = (struct synthvid_msg *)par->init_buf;
int ret = 0;
unsigned long t;
u8 index;
memset(msg, 0, sizeof(struct synthvid_msg));
msg->vid_hdr.type = SYNTHVID_RESOLUTION_REQUEST;
msg->vid_hdr.size = sizeof(struct synthvid_msg_hdr) +
sizeof(struct synthvid_supported_resolution_req);
msg->resolution_req.maximum_resolution_count =
SYNTHVID_MAX_RESOLUTION_COUNT;
synthvid_send(hdev, msg);
t = wait_for_completion_timeout(&par->wait, VSP_TIMEOUT);
if (!t) {
pr_err("Time out on waiting resolution response\n");
ret = -ETIMEDOUT;
goto out;
}
if (msg->resolution_resp.resolution_count == 0) {
pr_err("No supported resolutions\n");
ret = -ENODEV;
goto out;
}
index = msg->resolution_resp.default_resolution_index;
if (index >= msg->resolution_resp.resolution_count) {
pr_err("Invalid resolution index: %d\n", index);
ret = -ENODEV;
goto out;
}
screen_width =
msg->resolution_resp.supported_resolution[index].width;
screen_height =
msg->resolution_resp.supported_resolution[index].height;
out:
return ret;
}
/* Connect to VSP (Virtual Service Provider) on host */
static int synthvid_connect_vsp(struct hv_device *hdev)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par = info->par;
int ret;
ret = vmbus_open(hdev->channel, RING_BUFSIZE, RING_BUFSIZE,
NULL, 0, synthvid_receive, hdev);
if (ret) {
pr_err("Unable to open vmbus channel\n");
return ret;
}
/* Negotiate the protocol version with host */
switch (vmbus_proto_version) {
case VERSION_WIN10:
case VERSION_WIN10_V5:
ret = synthvid_negotiate_ver(hdev, SYNTHVID_VERSION_WIN10);
if (!ret)
break;
fallthrough;
case VERSION_WIN8:
case VERSION_WIN8_1:
ret = synthvid_negotiate_ver(hdev, SYNTHVID_VERSION_WIN8);
break;
default:
ret = synthvid_negotiate_ver(hdev, SYNTHVID_VERSION_WIN10);
break;
}
if (ret) {
pr_err("Synthetic video device version not accepted\n");
goto error;
}
screen_depth = SYNTHVID_DEPTH_WIN8;
if (synthvid_ver_ge(par->synthvid_version, SYNTHVID_VERSION_WIN10)) {
ret = synthvid_get_supported_resolution(hdev);
if (ret)
pr_info("Failed to get supported resolution from host, use default\n");
}
screen_fb_size = hdev->channel->offermsg.offer.
mmio_megabytes * 1024 * 1024;
return 0;
error:
vmbus_close(hdev->channel);
return ret;
}
/* Send VRAM and Situation messages to the host */
static int synthvid_send_config(struct hv_device *hdev)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par = info->par;
struct synthvid_msg *msg = (struct synthvid_msg *)par->init_buf;
int ret = 0;
unsigned long t;
/* Send VRAM location */
memset(msg, 0, sizeof(struct synthvid_msg));
msg->vid_hdr.type = SYNTHVID_VRAM_LOCATION;
msg->vid_hdr.size = sizeof(struct synthvid_msg_hdr) +
sizeof(struct synthvid_vram_location);
msg->vram.user_ctx = msg->vram.vram_gpa = par->mmio_pp;
msg->vram.is_vram_gpa_specified = 1;
synthvid_send(hdev, msg);
t = wait_for_completion_timeout(&par->wait, VSP_TIMEOUT);
if (!t) {
pr_err("Time out on waiting vram location ack\n");
ret = -ETIMEDOUT;
goto out;
}
if (msg->vram_ack.user_ctx != par->mmio_pp) {
pr_err("Unable to set VRAM location\n");
ret = -ENODEV;
goto out;
}
/* Send pointer and situation update */
synthvid_send_ptr(hdev);
synthvid_send_situ(hdev);
out:
return ret;
}
/*
* Delayed work callback:
* It is scheduled to call whenever update request is received and it has
* not been called in last HVFB_ONDEMAND_THROTTLE time interval.
*/
static void hvfb_update_work(struct work_struct *w)
{
struct hvfb_par *par = container_of(w, struct hvfb_par, dwork.work);
struct fb_info *info = par->info;
unsigned long flags;
int x1, x2, y1, y2;
int j;
spin_lock_irqsave(&par->delayed_refresh_lock, flags);
/* Reset the request flag */
par->delayed_refresh = false;
/* Store the dirty rectangle to local variables */
x1 = par->x1;
x2 = par->x2;
y1 = par->y1;
y2 = par->y2;
/* Clear dirty rectangle */
par->x1 = par->y1 = INT_MAX;
par->x2 = par->y2 = 0;
spin_unlock_irqrestore(&par->delayed_refresh_lock, flags);
if (x1 > info->var.xres || x2 > info->var.xres ||
y1 > info->var.yres || y2 > info->var.yres || x2 <= x1)
return;
/* Copy the dirty rectangle to frame buffer memory */
if (par->need_docopy)
for (j = y1; j < y2; j++)
hvfb_docopy(par,
j * info->fix.line_length +
(x1 * screen_depth / 8),
(x2 - x1) * screen_depth / 8);
/* Refresh */
if (par->fb_ready && par->update)
synthvid_update(info, x1, y1, x2, y2);
}
/*
* Control the on-demand refresh frequency. It schedules a delayed
* screen update if it has not yet.
*/
static void hvfb_ondemand_refresh_throttle(struct hvfb_par *par,
int x1, int y1, int w, int h)
{
unsigned long flags;
int x2 = x1 + w;
int y2 = y1 + h;
spin_lock_irqsave(&par->delayed_refresh_lock, flags);
/* Merge dirty rectangle */
par->x1 = min_t(int, par->x1, x1);
par->y1 = min_t(int, par->y1, y1);
par->x2 = max_t(int, par->x2, x2);
par->y2 = max_t(int, par->y2, y2);
/* Schedule a delayed screen update if not yet */
if (par->delayed_refresh == false) {
schedule_delayed_work(&par->dwork,
HVFB_ONDEMAND_THROTTLE);
par->delayed_refresh = true;
}
spin_unlock_irqrestore(&par->delayed_refresh_lock, flags);
}
static int hvfb_on_panic(struct notifier_block *nb,
unsigned long e, void *p)
{
struct hv_device *hdev;
struct hvfb_par *par;
struct fb_info *info;
par = container_of(nb, struct hvfb_par, hvfb_panic_nb);
info = par->info;
hdev = device_to_hv_device(info->device);
if (hv_ringbuffer_spinlock_busy(hdev->channel))
return NOTIFY_DONE;
par->synchronous_fb = true;
if (par->need_docopy)
hvfb_docopy(par, 0, dio_fb_size);
synthvid_update(info, 0, 0, INT_MAX, INT_MAX);
return NOTIFY_DONE;
}
/* Framebuffer operation handlers */
static int hvfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (var->xres < HVFB_WIDTH_MIN || var->yres < HVFB_HEIGHT_MIN ||
var->xres > screen_width || var->yres > screen_height ||
var->bits_per_pixel != screen_depth)
return -EINVAL;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
return 0;
}
static int hvfb_set_par(struct fb_info *info)
{
struct hv_device *hdev = device_to_hv_device(info->device);
return synthvid_send_situ(hdev);
}
static inline u32 chan_to_field(u32 chan, struct fb_bitfield *bf)
{
return ((chan & 0xffff) >> (16 - bf->length)) << bf->offset;
}
static int hvfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
u32 *pal = info->pseudo_palette;
if (regno > 15)
return -EINVAL;
pal[regno] = chan_to_field(red, &info->var.red)
| chan_to_field(green, &info->var.green)
| chan_to_field(blue, &info->var.blue)
| chan_to_field(transp, &info->var.transp);
return 0;
}
static int hvfb_blank(int blank, struct fb_info *info)
{
return 1; /* get fb_blank to set the colormap to all black */
}
static void hvfb_cfb_fillrect(struct fb_info *p,
const struct fb_fillrect *rect)
{
struct hvfb_par *par = p->par;
cfb_fillrect(p, rect);
if (par->synchronous_fb)
synthvid_update(p, 0, 0, INT_MAX, INT_MAX);
else
hvfb_ondemand_refresh_throttle(par, rect->dx, rect->dy,
rect->width, rect->height);
}
static void hvfb_cfb_copyarea(struct fb_info *p,
const struct fb_copyarea *area)
{
struct hvfb_par *par = p->par;
cfb_copyarea(p, area);
if (par->synchronous_fb)
synthvid_update(p, 0, 0, INT_MAX, INT_MAX);
else
hvfb_ondemand_refresh_throttle(par, area->dx, area->dy,
area->width, area->height);
}
static void hvfb_cfb_imageblit(struct fb_info *p,
const struct fb_image *image)
{
struct hvfb_par *par = p->par;
cfb_imageblit(p, image);
if (par->synchronous_fb)
synthvid_update(p, 0, 0, INT_MAX, INT_MAX);
else
hvfb_ondemand_refresh_throttle(par, image->dx, image->dy,
image->width, image->height);
}
static const struct fb_ops hvfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = hvfb_check_var,
.fb_set_par = hvfb_set_par,
.fb_setcolreg = hvfb_setcolreg,
.fb_fillrect = hvfb_cfb_fillrect,
.fb_copyarea = hvfb_cfb_copyarea,
.fb_imageblit = hvfb_cfb_imageblit,
.fb_blank = hvfb_blank,
.fb_mmap = fb_deferred_io_mmap,
};
/* Get options from kernel paramenter "video=" */
static void hvfb_get_option(struct fb_info *info)
{
struct hvfb_par *par = info->par;
char *opt = NULL, *p;
uint x = 0, y = 0;
if (fb_get_options(KBUILD_MODNAME, &opt) || !opt || !*opt)
return;
p = strsep(&opt, "x");
if (!*p || kstrtouint(p, 0, &x) ||
!opt || !*opt || kstrtouint(opt, 0, &y)) {
pr_err("Screen option is invalid: skipped\n");
return;
}
if (x < HVFB_WIDTH_MIN || y < HVFB_HEIGHT_MIN ||
(synthvid_ver_ge(par->synthvid_version, SYNTHVID_VERSION_WIN10) &&
(x * y * screen_depth / 8 > screen_fb_size)) ||
(par->synthvid_version == SYNTHVID_VERSION_WIN8 &&
x * y * screen_depth / 8 > SYNTHVID_FB_SIZE_WIN8)) {
pr_err("Screen resolution option is out of range: skipped\n");
return;
}
screen_width = x;
screen_height = y;
return;
}
/*
* Allocate enough contiguous physical memory.
* Return physical address if succeeded or -1 if failed.
*/
static phys_addr_t hvfb_get_phymem(struct hv_device *hdev,
unsigned int request_size)
{
struct page *page = NULL;
dma_addr_t dma_handle;
void *vmem;
phys_addr_t paddr = 0;
unsigned int order = get_order(request_size);
if (request_size == 0)
return -1;
if (order <= MAX_ORDER) {
/* Call alloc_pages if the size is less than 2^MAX_ORDER */
page = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
if (!page)
return -1;
paddr = (page_to_pfn(page) << PAGE_SHIFT);
} else {
/* Allocate from CMA */
hdev->device.coherent_dma_mask = DMA_BIT_MASK(64);
vmem = dma_alloc_coherent(&hdev->device,
round_up(request_size, PAGE_SIZE),
&dma_handle,
GFP_KERNEL | __GFP_NOWARN);
if (!vmem)
return -1;
paddr = virt_to_phys(vmem);
}
return paddr;
}
/* Release contiguous physical memory */
static void hvfb_release_phymem(struct hv_device *hdev,
phys_addr_t paddr, unsigned int size)
{
unsigned int order = get_order(size);
if (order <= MAX_ORDER)
__free_pages(pfn_to_page(paddr >> PAGE_SHIFT), order);
else
dma_free_coherent(&hdev->device,
round_up(size, PAGE_SIZE),
phys_to_virt(paddr),
paddr);
}
/* Get framebuffer memory from Hyper-V video pci space */
static int hvfb_getmem(struct hv_device *hdev, struct fb_info *info)
{
struct hvfb_par *par = info->par;
struct pci_dev *pdev = NULL;
void __iomem *fb_virt;
int gen2vm = efi_enabled(EFI_BOOT);
resource_size_t base, size;
phys_addr_t paddr;
int ret;
if (!gen2vm) {
pdev = pci_get_device(PCI_VENDOR_ID_MICROSOFT,
PCI_DEVICE_ID_HYPERV_VIDEO, NULL);
if (!pdev) {
pr_err("Unable to find PCI Hyper-V video\n");
return -ENODEV;
}
base = pci_resource_start(pdev, 0);
size = pci_resource_len(pdev, 0);
/*
* For Gen 1 VM, we can directly use the contiguous memory
* from VM. If we succeed, deferred IO happens directly
* on this allocated framebuffer memory, avoiding extra
* memory copy.
*/
paddr = hvfb_get_phymem(hdev, screen_fb_size);
if (paddr != (phys_addr_t) -1) {
par->mmio_pp = paddr;
par->mmio_vp = par->dio_vp = __va(paddr);
info->fix.smem_start = paddr;
info->fix.smem_len = screen_fb_size;
info->screen_base = par->mmio_vp;
info->screen_size = screen_fb_size;
par->need_docopy = false;
goto getmem_done;
}
pr_info("Unable to allocate enough contiguous physical memory on Gen 1 VM. Using MMIO instead.\n");
} else {
base = screen_info.lfb_base;
size = screen_info.lfb_size;
}
/*
* Cannot use the contiguous physical memory.
* Allocate mmio space for framebuffer.
*/
dio_fb_size =
screen_width * screen_height * screen_depth / 8;
ret = vmbus_allocate_mmio(&par->mem, hdev, 0, -1,
screen_fb_size, 0x100000, true);
if (ret != 0) {
pr_err("Unable to allocate framebuffer memory\n");
goto err1;
}
/*
* Map the VRAM cacheable for performance. This is also required for
* VM Connect to display properly for ARM64 Linux VM, as the host also
* maps the VRAM cacheable.
*/
fb_virt = ioremap_cache(par->mem->start, screen_fb_size);
if (!fb_virt)
goto err2;
/* Allocate memory for deferred IO */
par->dio_vp = vzalloc(round_up(dio_fb_size, PAGE_SIZE));
if (par->dio_vp == NULL)
goto err3;
/* Physical address of FB device */
par->mmio_pp = par->mem->start;
/* Virtual address of FB device */
par->mmio_vp = (unsigned char *) fb_virt;
info->fix.smem_start = par->mem->start;
info->fix.smem_len = dio_fb_size;
info->screen_base = par->dio_vp;
info->screen_size = dio_fb_size;
getmem_done:
aperture_remove_conflicting_devices(base, size, KBUILD_MODNAME);
if (gen2vm) {
/* framebuffer is reallocated, clear screen_info to avoid misuse from kexec */
screen_info.lfb_size = 0;
screen_info.lfb_base = 0;
screen_info.orig_video_isVGA = 0;
} else {
pci_dev_put(pdev);
}
return 0;
err3:
iounmap(fb_virt);
err2:
vmbus_free_mmio(par->mem->start, screen_fb_size);
par->mem = NULL;
err1:
if (!gen2vm)
pci_dev_put(pdev);
return -ENOMEM;
}
/* Release the framebuffer */
static void hvfb_putmem(struct hv_device *hdev, struct fb_info *info)
{
struct hvfb_par *par = info->par;
if (par->need_docopy) {
vfree(par->dio_vp);
iounmap(info->screen_base);
vmbus_free_mmio(par->mem->start, screen_fb_size);
} else {
hvfb_release_phymem(hdev, info->fix.smem_start,
screen_fb_size);
}
par->mem = NULL;
}
static int hvfb_probe(struct hv_device *hdev,
const struct hv_vmbus_device_id *dev_id)
{
struct fb_info *info;
struct hvfb_par *par;
int ret;
info = framebuffer_alloc(sizeof(struct hvfb_par), &hdev->device);
if (!info)
return -ENOMEM;
par = info->par;
par->info = info;
par->fb_ready = false;
par->need_docopy = true;
init_completion(&par->wait);
INIT_DELAYED_WORK(&par->dwork, hvfb_update_work);
par->delayed_refresh = false;
spin_lock_init(&par->delayed_refresh_lock);
par->x1 = par->y1 = INT_MAX;
par->x2 = par->y2 = 0;
/* Connect to VSP */
hv_set_drvdata(hdev, info);
ret = synthvid_connect_vsp(hdev);
if (ret) {
pr_err("Unable to connect to VSP\n");
goto error1;
}
hvfb_get_option(info);
pr_info("Screen resolution: %dx%d, Color depth: %d, Frame buffer size: %d\n",
screen_width, screen_height, screen_depth, screen_fb_size);
ret = hvfb_getmem(hdev, info);
if (ret) {
pr_err("No memory for framebuffer\n");
goto error2;
}
/* Set up fb_info */
info->var.xres_virtual = info->var.xres = screen_width;
info->var.yres_virtual = info->var.yres = screen_height;
info->var.bits_per_pixel = screen_depth;
if (info->var.bits_per_pixel == 16) {
info->var.red = (struct fb_bitfield){11, 5, 0};
info->var.green = (struct fb_bitfield){5, 6, 0};
info->var.blue = (struct fb_bitfield){0, 5, 0};
info->var.transp = (struct fb_bitfield){0, 0, 0};
} else {
info->var.red = (struct fb_bitfield){16, 8, 0};
info->var.green = (struct fb_bitfield){8, 8, 0};
info->var.blue = (struct fb_bitfield){0, 8, 0};
info->var.transp = (struct fb_bitfield){24, 8, 0};
}
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.vmode = FB_VMODE_NONINTERLACED;
strcpy(info->fix.id, KBUILD_MODNAME);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = screen_width * screen_depth / 8;
info->fix.accel = FB_ACCEL_NONE;
info->fbops = &hvfb_ops;
info->pseudo_palette = par->pseudo_palette;
/* Initialize deferred IO */
info->fbdefio = &synthvid_defio;
fb_deferred_io_init(info);
/* Send config to host */
ret = synthvid_send_config(hdev);
if (ret)
goto error;
ret = register_framebuffer(info);
if (ret) {
pr_err("Unable to register framebuffer\n");
goto error;
}
par->fb_ready = true;
par->synchronous_fb = false;
/*
* We need to be sure this panic notifier runs _before_ the
* vmbus disconnect, so order it by priority. It must execute
* before the function hv_panic_vmbus_unload() [drivers/hv/vmbus_drv.c],
* which is almost at the end of list, with priority = INT_MIN + 1.
*/
par->hvfb_panic_nb.notifier_call = hvfb_on_panic;
par->hvfb_panic_nb.priority = INT_MIN + 10,
atomic_notifier_chain_register(&panic_notifier_list,
&par->hvfb_panic_nb);
return 0;
error:
fb_deferred_io_cleanup(info);
hvfb_putmem(hdev, info);
error2:
vmbus_close(hdev->channel);
error1:
cancel_delayed_work_sync(&par->dwork);
hv_set_drvdata(hdev, NULL);
framebuffer_release(info);
return ret;
}
static void hvfb_remove(struct hv_device *hdev)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par = info->par;
atomic_notifier_chain_unregister(&panic_notifier_list,
&par->hvfb_panic_nb);
par->update = false;
par->fb_ready = false;
fb_deferred_io_cleanup(info);
unregister_framebuffer(info);
cancel_delayed_work_sync(&par->dwork);
vmbus_close(hdev->channel);
hv_set_drvdata(hdev, NULL);
hvfb_putmem(hdev, info);
framebuffer_release(info);
}
static int hvfb_suspend(struct hv_device *hdev)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par = info->par;
console_lock();
/* 1 means do suspend */
fb_set_suspend(info, 1);
cancel_delayed_work_sync(&par->dwork);
cancel_delayed_work_sync(&info->deferred_work);
par->update_saved = par->update;
par->update = false;
par->fb_ready = false;
vmbus_close(hdev->channel);
console_unlock();
return 0;
}
static int hvfb_resume(struct hv_device *hdev)
{
struct fb_info *info = hv_get_drvdata(hdev);
struct hvfb_par *par = info->par;
int ret;
console_lock();
ret = synthvid_connect_vsp(hdev);
if (ret != 0)
goto out;
ret = synthvid_send_config(hdev);
if (ret != 0) {
vmbus_close(hdev->channel);
goto out;
}
par->fb_ready = true;
par->update = par->update_saved;
schedule_delayed_work(&info->deferred_work, info->fbdefio->delay);
schedule_delayed_work(&par->dwork, HVFB_UPDATE_DELAY);
/* 0 means do resume */
fb_set_suspend(info, 0);
out:
console_unlock();
return ret;
}
static const struct pci_device_id pci_stub_id_table[] = {
{
.vendor = PCI_VENDOR_ID_MICROSOFT,
.device = PCI_DEVICE_ID_HYPERV_VIDEO,
},
{ /* end of list */ }
};
static const struct hv_vmbus_device_id id_table[] = {
/* Synthetic Video Device GUID */
{HV_SYNTHVID_GUID},
{}
};
MODULE_DEVICE_TABLE(pci, pci_stub_id_table);
MODULE_DEVICE_TABLE(vmbus, id_table);
static struct hv_driver hvfb_drv = {
.name = KBUILD_MODNAME,
.id_table = id_table,
.probe = hvfb_probe,
.remove = hvfb_remove,
.suspend = hvfb_suspend,
.resume = hvfb_resume,
.driver = {
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
};
static int hvfb_pci_stub_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
return 0;
}
static void hvfb_pci_stub_remove(struct pci_dev *pdev)
{
}
static struct pci_driver hvfb_pci_stub_driver = {
.name = KBUILD_MODNAME,
.id_table = pci_stub_id_table,
.probe = hvfb_pci_stub_probe,
.remove = hvfb_pci_stub_remove,
.driver = {
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
}
};
static int __init hvfb_drv_init(void)
{
int ret;
if (fb_modesetting_disabled("hyper_fb"))
return -ENODEV;
ret = vmbus_driver_register(&hvfb_drv);
if (ret != 0)
return ret;
ret = pci_register_driver(&hvfb_pci_stub_driver);
if (ret != 0) {
vmbus_driver_unregister(&hvfb_drv);
return ret;
}
return 0;
}
static void __exit hvfb_drv_exit(void)
{
pci_unregister_driver(&hvfb_pci_stub_driver);
vmbus_driver_unregister(&hvfb_drv);
}
module_init(hvfb_drv_init);
module_exit(hvfb_drv_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Microsoft Hyper-V Synthetic Video Frame Buffer Driver");
| linux-master | drivers/video/fbdev/hyperv_fb.c |
/*
* linux/drivers/video/vt8623fb.c - fbdev driver for
* integrated graphic core in VIA VT8623 [CLE266] chipset
*
* Copyright (c) 2006-2007 Ondrej Zajicek <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Code is based on s3fb, some parts are from David Boucher's viafb
* (http://davesdomain.org.uk/viafb/)
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/svga.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
#include <video/vga.h>
struct vt8623fb_info {
char __iomem *mmio_base;
int wc_cookie;
struct vgastate state;
struct mutex open_lock;
unsigned int ref_count;
u32 pseudo_palette[16];
};
/* ------------------------------------------------------------------------- */
static const struct svga_fb_format vt8623fb_formats[] = {
{ 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP8, FB_VISUAL_PSEUDOCOLOR, 16, 16},
{ 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 16, 16},
{ 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 16, 16},
{ 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8},
/* {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, */
{16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4},
{32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2},
SVGA_FORMAT_END
};
static const struct svga_pll vt8623_pll = {2, 127, 2, 7, 0, 3,
60000, 300000, 14318};
/* CRT timing register sets */
static const struct vga_regset vt8623_h_total_regs[] = {{0x00, 0, 7}, {0x36, 3, 3}, VGA_REGSET_END};
static const struct vga_regset vt8623_h_display_regs[] = {{0x01, 0, 7}, VGA_REGSET_END};
static const struct vga_regset vt8623_h_blank_start_regs[] = {{0x02, 0, 7}, VGA_REGSET_END};
static const struct vga_regset vt8623_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, {0x33, 5, 5}, VGA_REGSET_END};
static const struct vga_regset vt8623_h_sync_start_regs[] = {{0x04, 0, 7}, {0x33, 4, 4}, VGA_REGSET_END};
static const struct vga_regset vt8623_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
static const struct vga_regset vt8623_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x35, 0, 0}, VGA_REGSET_END};
static const struct vga_regset vt8623_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x35, 2, 2}, VGA_REGSET_END};
static const struct vga_regset vt8623_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x35, 3, 3}, VGA_REGSET_END};
static const struct vga_regset vt8623_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
static const struct vga_regset vt8623_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x35, 1, 1}, VGA_REGSET_END};
static const struct vga_regset vt8623_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
static const struct vga_regset vt8623_offset_regs[] = {{0x13, 0, 7}, {0x35, 5, 7}, VGA_REGSET_END};
static const struct vga_regset vt8623_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x33, 0, 2}, {0x35, 4, 4}, VGA_REGSET_END};
static const struct vga_regset vt8623_fetch_count_regs[] = {{0x1C, 0, 7}, {0x1D, 0, 1}, VGA_REGSET_END};
static const struct vga_regset vt8623_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x34, 0, 7}, {0x48, 0, 1}, VGA_REGSET_END};
static const struct svga_timing_regs vt8623_timing_regs = {
vt8623_h_total_regs, vt8623_h_display_regs, vt8623_h_blank_start_regs,
vt8623_h_blank_end_regs, vt8623_h_sync_start_regs, vt8623_h_sync_end_regs,
vt8623_v_total_regs, vt8623_v_display_regs, vt8623_v_blank_start_regs,
vt8623_v_blank_end_regs, vt8623_v_sync_start_regs, vt8623_v_sync_end_regs,
};
/* ------------------------------------------------------------------------- */
/* Module parameters */
static char *mode_option = "640x480-8@60";
static int mtrr = 1;
MODULE_AUTHOR("(c) 2006 Ondrej Zajicek <[email protected]>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("fbdev driver for integrated graphics core in VIA VT8623 [CLE266]");
module_param(mode_option, charp, 0644);
MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
module_param_named(mode, mode_option, charp, 0);
MODULE_PARM_DESC(mode, "Default video mode e.g. '648x480-8@60' (deprecated)");
module_param(mtrr, int, 0444);
MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
/* ------------------------------------------------------------------------- */
static void vt8623fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
{
struct vt8623fb_info *par = info->par;
svga_tilecursor(par->state.vgabase, info, cursor);
}
static struct fb_tile_ops vt8623fb_tile_ops = {
.fb_settile = svga_settile,
.fb_tilecopy = svga_tilecopy,
.fb_tilefill = svga_tilefill,
.fb_tileblit = svga_tileblit,
.fb_tilecursor = vt8623fb_tilecursor,
.fb_get_tilemax = svga_get_tilemax,
};
/* ------------------------------------------------------------------------- */
/* image data is MSB-first, fb structure is MSB-first too */
static inline u32 expand_color(u32 c)
{
return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
}
/* vt8623fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
static void vt8623fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
{
u32 fg = expand_color(image->fg_color);
u32 bg = expand_color(image->bg_color);
const u8 *src1, *src;
u8 __iomem *dst1;
u32 __iomem *dst;
u32 val;
int x, y;
src1 = image->data;
dst1 = info->screen_base + (image->dy * info->fix.line_length)
+ ((image->dx / 8) * 4);
for (y = 0; y < image->height; y++) {
src = src1;
dst = (u32 __iomem *) dst1;
for (x = 0; x < image->width; x += 8) {
val = *(src++) * 0x01010101;
val = (val & fg) | (~val & bg);
fb_writel(val, dst++);
}
src1 += image->width / 8;
dst1 += info->fix.line_length;
}
}
/* vt8623fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
static void vt8623fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
u32 fg = expand_color(rect->color);
u8 __iomem *dst1;
u32 __iomem *dst;
int x, y;
dst1 = info->screen_base + (rect->dy * info->fix.line_length)
+ ((rect->dx / 8) * 4);
for (y = 0; y < rect->height; y++) {
dst = (u32 __iomem *) dst1;
for (x = 0; x < rect->width; x += 8) {
fb_writel(fg, dst++);
}
dst1 += info->fix.line_length;
}
}
/* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
static inline u32 expand_pixel(u32 c)
{
return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
}
/* vt8623fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
static void vt8623fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
{
u32 fg = image->fg_color * 0x11111111;
u32 bg = image->bg_color * 0x11111111;
const u8 *src1, *src;
u8 __iomem *dst1;
u32 __iomem *dst;
u32 val;
int x, y;
src1 = image->data;
dst1 = info->screen_base + (image->dy * info->fix.line_length)
+ ((image->dx / 8) * 4);
for (y = 0; y < image->height; y++) {
src = src1;
dst = (u32 __iomem *) dst1;
for (x = 0; x < image->width; x += 8) {
val = expand_pixel(*(src++));
val = (val & fg) | (~val & bg);
fb_writel(val, dst++);
}
src1 += image->width / 8;
dst1 += info->fix.line_length;
}
}
static void vt8623fb_imageblit(struct fb_info *info, const struct fb_image *image)
{
if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
&& ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
vt8623fb_iplan_imageblit(info, image);
else
vt8623fb_cfb4_imageblit(info, image);
} else
cfb_imageblit(info, image);
}
static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
if ((info->var.bits_per_pixel == 4)
&& ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
&& (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
vt8623fb_iplan_fillrect(info, rect);
else
cfb_fillrect(info, rect);
}
/* ------------------------------------------------------------------------- */
static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
{
struct vt8623fb_info *par = info->par;
u16 m, n, r;
u8 regval;
int rv;
rv = svga_compute_pll(&vt8623_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
if (rv < 0) {
fb_err(info, "cannot set requested pixclock, keeping old value\n");
return;
}
/* Set VGA misc register */
regval = vga_r(par->state.vgabase, VGA_MIS_R);
vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
/* Set clock registers */
vga_wseq(par->state.vgabase, 0x46, (n | (r << 6)));
vga_wseq(par->state.vgabase, 0x47, m);
udelay(1000);
/* PLL reset */
svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02);
svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02);
}
static int vt8623fb_open(struct fb_info *info, int user)
{
struct vt8623fb_info *par = info->par;
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
void __iomem *vgabase = par->state.vgabase;
memset(&(par->state), 0, sizeof(struct vgastate));
par->state.vgabase = vgabase;
par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
par->state.num_crtc = 0xA2;
par->state.num_seq = 0x50;
save_vga(&(par->state));
}
par->ref_count++;
mutex_unlock(&(par->open_lock));
return 0;
}
static int vt8623fb_release(struct fb_info *info, int user)
{
struct vt8623fb_info *par = info->par;
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
mutex_unlock(&(par->open_lock));
return -EINVAL;
}
if (par->ref_count == 1)
restore_vga(&(par->state));
par->ref_count--;
mutex_unlock(&(par->open_lock));
return 0;
}
static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
int rv, mem, step;
if (!var->pixclock)
return -EINVAL;
/* Find appropriate format */
rv = svga_match_format (vt8623fb_formats, var, NULL);
if (rv < 0)
{
fb_err(info, "unsupported mode requested\n");
return rv;
}
/* Do not allow to have real resoulution larger than virtual */
if (var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
/* Round up xres_virtual to have proper alignment of lines */
step = vt8623fb_formats[rv].xresstep - 1;
var->xres_virtual = (var->xres_virtual+step) & ~step;
/* Check whether have enough memory */
mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
if (mem > info->screen_size)
{
fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n",
mem >> 10, (unsigned int) (info->screen_size >> 10));
return -EINVAL;
}
/* Text mode is limited to 256 kB of memory */
if ((var->bits_per_pixel == 0) && (mem > (256*1024)))
{
fb_err(info, "text framebuffer size too large (%d kB requested, 256 kB possible)\n",
mem >> 10);
return -EINVAL;
}
rv = svga_check_timings (&vt8623_timing_regs, var, info->node);
if (rv < 0)
{
fb_err(info, "invalid timings requested\n");
return rv;
}
/* Interlaced mode not supported */
if (var->vmode & FB_VMODE_INTERLACED)
return -EINVAL;
return 0;
}
static int vt8623fb_set_par(struct fb_info *info)
{
u32 mode, offset_value, fetch_value, screen_size;
struct vt8623fb_info *par = info->par;
u32 bpp = info->var.bits_per_pixel;
if (bpp != 0) {
info->fix.ypanstep = 1;
info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
info->flags &= ~FBINFO_MISC_TILEBLITTING;
info->tileops = NULL;
/* in 4bpp supports 8p wide tiles only, any tiles otherwise */
info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0);
info->pixmap.blit_y = ~(u32)0;
offset_value = (info->var.xres_virtual * bpp) / 64;
fetch_value = ((info->var.xres * bpp) / 128) + 4;
if (bpp == 4)
fetch_value = (info->var.xres / 8) + 8; /* + 0 is OK */
screen_size = info->var.yres_virtual * info->fix.line_length;
} else {
info->fix.ypanstep = 16;
info->fix.line_length = 0;
info->flags |= FBINFO_MISC_TILEBLITTING;
info->tileops = &vt8623fb_tile_ops;
/* supports 8x16 tiles only */
info->pixmap.blit_x = 1 << (8 - 1);
info->pixmap.blit_y = 1 << (16 - 1);
offset_value = info->var.xres_virtual / 16;
fetch_value = (info->var.xres / 8) + 8;
screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
}
info->var.xoffset = 0;
info->var.yoffset = 0;
info->var.activate = FB_ACTIVATE_NOW;
/* Unlock registers */
svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01);
/* Device, screen and sync off */
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
/* Set default values */
svga_set_default_gfx_regs(par->state.vgabase);
svga_set_default_atc_regs(par->state.vgabase);
svga_set_default_seq_regs(par->state.vgabase);
svga_set_default_crt_regs(par->state.vgabase);
svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF);
svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0);
svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value);
svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value);
/* Clear H/V Skew */
svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60);
svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60);
if (info->var.vmode & FB_VMODE_DOUBLE)
svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
else
svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold
vga_wseq(par->state.vgabase, 0x17, 0x1F); // FIFO depth
vga_wseq(par->state.vgabase, 0x18, 0x4E);
svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ?
vga_wcrt(par->state.vgabase, 0x32, 0x00);
vga_wcrt(par->state.vgabase, 0x34, 0x00);
vga_wcrt(par->state.vgabase, 0x6A, 0x80);
vga_wcrt(par->state.vgabase, 0x6A, 0xC0);
vga_wgfx(par->state.vgabase, 0x20, 0x00);
vga_wgfx(par->state.vgabase, 0x21, 0x00);
vga_wgfx(par->state.vgabase, 0x22, 0x00);
/* Set SR15 according to number of bits per pixel */
mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix));
switch (mode) {
case 0:
fb_dbg(info, "text mode\n");
svga_set_textmode_vga_regs(par->state.vgabase);
svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70);
break;
case 1:
fb_dbg(info, "4 bit pseudocolor\n");
vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
break;
case 2:
fb_dbg(info, "4 bit pseudocolor, planar\n");
svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
break;
case 3:
fb_dbg(info, "8 bit pseudocolor\n");
svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE);
break;
case 4:
fb_dbg(info, "5/6/5 truecolor\n");
svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE);
break;
case 5:
fb_dbg(info, "8/8/8 truecolor\n");
svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE);
break;
default:
printk(KERN_ERR "vt8623fb: unsupported mode - bug\n");
return (-EINVAL);
}
vt8623_set_pixclock(info, info->var.pixclock);
svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1,
(info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1,
1, info->node);
if (screen_size > info->screen_size)
screen_size = info->screen_size;
memset_io(info->screen_base, 0x00, screen_size);
/* Device and screen back on */
svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
return 0;
}
static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *fb)
{
switch (fb->var.bits_per_pixel) {
case 0:
case 4:
if (regno >= 16)
return -EINVAL;
outb(0x0F, VGA_PEL_MSK);
outb(regno, VGA_PEL_IW);
outb(red >> 10, VGA_PEL_D);
outb(green >> 10, VGA_PEL_D);
outb(blue >> 10, VGA_PEL_D);
break;
case 8:
if (regno >= 256)
return -EINVAL;
outb(0xFF, VGA_PEL_MSK);
outb(regno, VGA_PEL_IW);
outb(red >> 10, VGA_PEL_D);
outb(green >> 10, VGA_PEL_D);
outb(blue >> 10, VGA_PEL_D);
break;
case 16:
if (regno >= 16)
return 0;
if (fb->var.green.length == 5)
((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
else if (fb->var.green.length == 6)
((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
else
return -EINVAL;
break;
case 24:
case 32:
if (regno >= 16)
return 0;
/* ((transp & 0xFF00) << 16) */
((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
(green & 0xFF00) | ((blue & 0xFF00) >> 8);
break;
default:
return -EINVAL;
}
return 0;
}
static int vt8623fb_blank(int blank_mode, struct fb_info *info)
{
struct vt8623fb_info *par = info->par;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
fb_dbg(info, "unblank\n");
svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
break;
case FB_BLANK_NORMAL:
fb_dbg(info, "blank\n");
svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
break;
case FB_BLANK_HSYNC_SUSPEND:
fb_dbg(info, "DPMS standby (hsync off)\n");
svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30);
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
break;
case FB_BLANK_VSYNC_SUSPEND:
fb_dbg(info, "DPMS suspend (vsync off)\n");
svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30);
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
break;
case FB_BLANK_POWERDOWN:
fb_dbg(info, "DPMS off (no sync)\n");
svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
break;
}
return 0;
}
static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct vt8623fb_info *par = info->par;
unsigned int offset;
/* Calculate the offset */
if (info->var.bits_per_pixel == 0) {
offset = (var->yoffset / 16) * info->var.xres_virtual
+ var->xoffset;
offset = offset >> 3;
} else {
offset = (var->yoffset * info->fix.line_length) +
(var->xoffset * info->var.bits_per_pixel / 8);
offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 1);
}
/* Set the offset */
svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset);
return 0;
}
/* ------------------------------------------------------------------------- */
/* Frame buffer operations */
static const struct fb_ops vt8623fb_ops = {
.owner = THIS_MODULE,
.fb_open = vt8623fb_open,
.fb_release = vt8623fb_release,
.fb_check_var = vt8623fb_check_var,
.fb_set_par = vt8623fb_set_par,
.fb_setcolreg = vt8623fb_setcolreg,
.fb_blank = vt8623fb_blank,
.fb_pan_display = vt8623fb_pan_display,
.fb_fillrect = vt8623fb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = vt8623fb_imageblit,
.fb_get_caps = svga_get_caps,
};
/* PCI probe */
static int vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct pci_bus_region bus_reg;
struct resource vga_res;
struct fb_info *info;
struct vt8623fb_info *par;
unsigned int memsize1, memsize2;
int rc;
/* Ignore secondary VGA device because there is no VGA arbitration */
if (! svga_primary_device(dev)) {
dev_info(&(dev->dev), "ignoring secondary device\n");
return -ENODEV;
}
rc = aperture_remove_conflicting_pci_devices(dev, "vt8623fb");
if (rc)
return rc;
/* Allocate and fill driver data structure */
info = framebuffer_alloc(sizeof(struct vt8623fb_info), &(dev->dev));
if (!info)
return -ENOMEM;
par = info->par;
mutex_init(&par->open_lock);
info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
info->fbops = &vt8623fb_ops;
/* Prepare PCI device */
rc = pci_enable_device(dev);
if (rc < 0) {
dev_err(info->device, "cannot enable PCI device\n");
goto err_enable_device;
}
rc = pci_request_regions(dev, "vt8623fb");
if (rc < 0) {
dev_err(info->device, "cannot reserve framebuffer region\n");
goto err_request_regions;
}
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = pci_resource_len(dev, 0);
info->fix.mmio_start = pci_resource_start(dev, 1);
info->fix.mmio_len = pci_resource_len(dev, 1);
/* Map physical IO memory address into kernel space */
info->screen_base = pci_iomap_wc(dev, 0, 0);
if (! info->screen_base) {
rc = -ENOMEM;
dev_err(info->device, "iomap for framebuffer failed\n");
goto err_iomap_1;
}
par->mmio_base = pci_iomap(dev, 1, 0);
if (! par->mmio_base) {
rc = -ENOMEM;
dev_err(info->device, "iomap for MMIO failed\n");
goto err_iomap_2;
}
bus_reg.start = 0;
bus_reg.end = 64 * 1024;
vga_res.flags = IORESOURCE_IO;
pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
/* Find how many physical memory there is on card */
memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1;
memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2;
if ((16 <= memsize1) && (memsize1 <= 64) && (memsize1 == memsize2))
info->screen_size = memsize1 << 20;
else {
dev_err(info->device, "memory size detection failed (%x %x), suppose 16 MB\n", memsize1, memsize2);
info->screen_size = 16 << 20;
}
info->fix.smem_len = info->screen_size;
strcpy(info->fix.id, "VIA VT8623");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.ypanstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->pseudo_palette = (void*)par->pseudo_palette;
/* Prepare startup mode */
kernel_param_lock(THIS_MODULE);
rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
kernel_param_unlock(THIS_MODULE);
if (! ((rc == 1) || (rc == 2))) {
rc = -EINVAL;
dev_err(info->device, "mode %s not found\n", mode_option);
goto err_find_mode;
}
rc = fb_alloc_cmap(&info->cmap, 256, 0);
if (rc < 0) {
dev_err(info->device, "cannot allocate colormap\n");
goto err_alloc_cmap;
}
rc = register_framebuffer(info);
if (rc < 0) {
dev_err(info->device, "cannot register framebuffer\n");
goto err_reg_fb;
}
fb_info(info, "%s on %s, %d MB RAM\n",
info->fix.id, pci_name(dev), info->fix.smem_len >> 20);
/* Record a reference to the driver data */
pci_set_drvdata(dev, info);
if (mtrr)
par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
info->fix.smem_len);
return 0;
/* Error handling */
err_reg_fb:
fb_dealloc_cmap(&info->cmap);
err_alloc_cmap:
err_find_mode:
pci_iounmap(dev, par->mmio_base);
err_iomap_2:
pci_iounmap(dev, info->screen_base);
err_iomap_1:
pci_release_regions(dev);
err_request_regions:
/* pci_disable_device(dev); */
err_enable_device:
framebuffer_release(info);
return rc;
}
/* PCI remove */
static void vt8623_pci_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
if (info) {
struct vt8623fb_info *par = info->par;
arch_phys_wc_del(par->wc_cookie);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
pci_iounmap(dev, info->screen_base);
pci_iounmap(dev, par->mmio_base);
pci_release_regions(dev);
/* pci_disable_device(dev); */
framebuffer_release(info);
}
}
/* PCI suspend */
static int __maybe_unused vt8623_pci_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct vt8623fb_info *par = info->par;
dev_info(info->device, "suspend\n");
console_lock();
mutex_lock(&(par->open_lock));
if (par->ref_count == 0) {
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
fb_set_suspend(info, 1);
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
/* PCI resume */
static int __maybe_unused vt8623_pci_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct vt8623fb_info *par = info->par;
dev_info(info->device, "resume\n");
console_lock();
mutex_lock(&(par->open_lock));
if (par->ref_count == 0)
goto fail;
vt8623fb_set_par(info);
fb_set_suspend(info, 0);
fail:
mutex_unlock(&(par->open_lock));
console_unlock();
return 0;
}
static const struct dev_pm_ops vt8623_pci_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = vt8623_pci_suspend,
.resume = vt8623_pci_resume,
.freeze = NULL,
.thaw = vt8623_pci_resume,
.poweroff = vt8623_pci_suspend,
.restore = vt8623_pci_resume,
#endif /* CONFIG_PM_SLEEP */
};
/* List of boards that we are trying to support */
static const struct pci_device_id vt8623_devices[] = {
{PCI_DEVICE(PCI_VENDOR_ID_VIA, 0x3122)},
{0, 0, 0, 0, 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, vt8623_devices);
static struct pci_driver vt8623fb_pci_driver = {
.name = "vt8623fb",
.id_table = vt8623_devices,
.probe = vt8623_pci_probe,
.remove = vt8623_pci_remove,
.driver.pm = &vt8623_pci_pm_ops,
};
/* Cleanup */
static void __exit vt8623fb_cleanup(void)
{
pr_debug("vt8623fb: cleaning up\n");
pci_unregister_driver(&vt8623fb_pci_driver);
}
/* Driver Initialisation */
static int __init vt8623fb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("vt8623fb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("vt8623fb", &option))
return -ENODEV;
if (option && *option)
mode_option = option;
#endif
pr_debug("vt8623fb: initializing\n");
return pci_register_driver(&vt8623fb_pci_driver);
}
/* ------------------------------------------------------------------------- */
/* Modularization */
module_init(vt8623fb_init);
module_exit(vt8623fb_cleanup);
| linux-master | drivers/video/fbdev/vt8623fb.c |
/* sunxvr2500.c: Sun 3DLABS XVR-2500 et al. fb driver for sparc64 systems
*
* License: GPL
*
* Copyright (C) 2007 David S. Miller ([email protected])
*/
#include <linux/aperture.h>
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/of.h>
#include <asm/io.h>
struct s3d_info {
struct fb_info *info;
struct pci_dev *pdev;
char __iomem *fb_base;
unsigned long fb_base_phys;
struct device_node *of_node;
unsigned int width;
unsigned int height;
unsigned int depth;
unsigned int fb_size;
u32 pseudo_palette[16];
};
static int s3d_get_props(struct s3d_info *sp)
{
sp->width = of_getintprop_default(sp->of_node, "width", 0);
sp->height = of_getintprop_default(sp->of_node, "height", 0);
sp->depth = of_getintprop_default(sp->of_node, "depth", 8);
if (!sp->width || !sp->height) {
printk(KERN_ERR "s3d: Critical properties missing for %s\n",
pci_name(sp->pdev));
return -EINVAL;
}
return 0;
}
static int s3d_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
u32 value;
if (regno < 16) {
red >>= 8;
green >>= 8;
blue >>= 8;
value = (blue << 24) | (green << 16) | (red << 8);
((u32 *)info->pseudo_palette)[regno] = value;
}
return 0;
}
static const struct fb_ops s3d_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = s3d_setcolreg,
};
static int s3d_set_fbinfo(struct s3d_info *sp)
{
struct fb_info *info = sp->info;
struct fb_var_screeninfo *var = &info->var;
info->fbops = &s3d_ops;
info->screen_base = sp->fb_base;
info->screen_size = sp->fb_size;
info->pseudo_palette = sp->pseudo_palette;
/* Fill fix common fields */
strscpy(info->fix.id, "s3d", sizeof(info->fix.id));
info->fix.smem_start = sp->fb_base_phys;
info->fix.smem_len = sp->fb_size;
info->fix.type = FB_TYPE_PACKED_PIXELS;
if (sp->depth == 32 || sp->depth == 24)
info->fix.visual = FB_VISUAL_TRUECOLOR;
else
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
var->xres = sp->width;
var->yres = sp->height;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->bits_per_pixel = sp->depth;
var->red.offset = 8;
var->red.length = 8;
var->green.offset = 16;
var->green.length = 8;
var->blue.offset = 24;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
if (fb_alloc_cmap(&info->cmap, 256, 0)) {
printk(KERN_ERR "s3d: Cannot allocate color map.\n");
return -ENOMEM;
}
return 0;
}
static int s3d_pci_register(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct fb_info *info;
struct s3d_info *sp;
int err;
err = aperture_remove_conflicting_pci_devices(pdev, "s3dfb");
if (err)
return err;
err = pci_enable_device(pdev);
if (err < 0) {
printk(KERN_ERR "s3d: Cannot enable PCI device %s\n",
pci_name(pdev));
goto err_out;
}
info = framebuffer_alloc(sizeof(struct s3d_info), &pdev->dev);
if (!info) {
err = -ENOMEM;
goto err_disable;
}
sp = info->par;
sp->info = info;
sp->pdev = pdev;
sp->of_node = pci_device_to_OF_node(pdev);
if (!sp->of_node) {
printk(KERN_ERR "s3d: Cannot find OF node of %s\n",
pci_name(pdev));
err = -ENODEV;
goto err_release_fb;
}
sp->fb_base_phys = pci_resource_start (pdev, 1);
err = pci_request_region(pdev, 1, "s3d framebuffer");
if (err < 0) {
printk("s3d: Cannot request region 1 for %s\n",
pci_name(pdev));
goto err_release_fb;
}
err = s3d_get_props(sp);
if (err)
goto err_release_pci;
/* XXX 'linebytes' is often wrong, it is equal to the width
* XXX with depth of 32 on my XVR-2500 which is clearly not
* XXX right. So we don't try to use it.
*/
switch (sp->depth) {
case 8:
info->fix.line_length = sp->width;
break;
case 16:
info->fix.line_length = sp->width * 2;
break;
case 24:
info->fix.line_length = sp->width * 3;
break;
case 32:
info->fix.line_length = sp->width * 4;
break;
}
sp->fb_size = info->fix.line_length * sp->height;
sp->fb_base = ioremap(sp->fb_base_phys, sp->fb_size);
if (!sp->fb_base) {
err = -ENOMEM;
goto err_release_pci;
}
err = s3d_set_fbinfo(sp);
if (err)
goto err_unmap_fb;
pci_set_drvdata(pdev, info);
printk("s3d: Found device at %s\n", pci_name(pdev));
err = register_framebuffer(info);
if (err < 0) {
printk(KERN_ERR "s3d: Could not register framebuffer %s\n",
pci_name(pdev));
goto err_unmap_fb;
}
return 0;
err_unmap_fb:
iounmap(sp->fb_base);
err_release_pci:
pci_release_region(pdev, 1);
err_release_fb:
framebuffer_release(info);
err_disable:
pci_disable_device(pdev);
err_out:
return err;
}
static const struct pci_device_id s3d_pci_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x002c), },
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x002d), },
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x002e), },
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x002f), },
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x0030), },
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x0031), },
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x0032), },
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x0033), },
{ 0, }
};
static struct pci_driver s3d_driver = {
.driver = {
.suppress_bind_attrs = true,
},
.name = "s3d",
.id_table = s3d_pci_table,
.probe = s3d_pci_register,
};
static int __init s3d_init(void)
{
if (fb_modesetting_disabled("s3d"))
return -ENODEV;
if (fb_get_options("s3d", NULL))
return -ENODEV;
return pci_register_driver(&s3d_driver);
}
device_initcall(s3d_init);
| linux-master | drivers/video/fbdev/sunxvr2500.c |
/*
* linux/drivers/video/mfb.c -- Low level frame buffer operations for
* monochrome
*
* Created 5 Apr 1997 by Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/string.h>
#include <linux/fb.h>
#include "atafb.h"
#include "atafb_utils.h"
/*
* Monochrome
*/
void atafb_mfb_copyarea(struct fb_info *info, u_long next_line,
int sy, int sx, int dy, int dx,
int height, int width)
{
u8 *src, *dest;
u_int rows;
if (sx == 0 && dx == 0 && width == next_line) {
src = (u8 *)info->screen_base + sy * (width >> 3);
dest = (u8 *)info->screen_base + dy * (width >> 3);
fb_memmove(dest, src, height * (width >> 3));
} else if (dy <= sy) {
src = (u8 *)info->screen_base + sy * next_line + (sx >> 3);
dest = (u8 *)info->screen_base + dy * next_line + (dx >> 3);
for (rows = height; rows--;) {
fb_memmove(dest, src, width >> 3);
src += next_line;
dest += next_line;
}
} else {
src = (u8 *)info->screen_base + (sy + height - 1) * next_line + (sx >> 3);
dest = (u8 *)info->screen_base + (dy + height - 1) * next_line + (dx >> 3);
for (rows = height; rows--;) {
fb_memmove(dest, src, width >> 3);
src -= next_line;
dest -= next_line;
}
}
}
void atafb_mfb_fillrect(struct fb_info *info, u_long next_line, u32 color,
int sy, int sx, int height, int width)
{
u8 *dest;
u_int rows;
dest = (u8 *)info->screen_base + sy * next_line + (sx >> 3);
if (sx == 0 && width == next_line) {
if (color)
fb_memset255(dest, height * (width >> 3));
else
fb_memclear(dest, height * (width >> 3));
} else {
for (rows = height; rows--; dest += next_line) {
if (color)
fb_memset255(dest, width >> 3);
else
fb_memclear_small(dest, width >> 3);
}
}
}
void atafb_mfb_linefill(struct fb_info *info, u_long next_line,
int dy, int dx, u32 width,
const u8 *data, u32 bgcolor, u32 fgcolor)
{
u8 *dest;
u_int rows;
dest = (u8 *)info->screen_base + dy * next_line + (dx >> 3);
for (rows = width / 8; rows--; /* check margins */ ) {
// use fast_memmove or fb_memmove
*dest++ = *data++;
}
}
| linux-master | drivers/video/fbdev/atafb_mfb.c |
/*
* Driver for AT91 LCD Controller
*
* Copyright (C) 2007 Atmel Corporation
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/backlight.h>
#include <linux/gfp.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <video/of_videomode.h>
#include <video/of_display_timing.h>
#include <linux/regulator/consumer.h>
#include <video/videomode.h>
#include <video/atmel_lcdc.h>
struct atmel_lcdfb_config {
bool have_alt_pixclock;
bool have_hozval;
bool have_intensity_bit;
};
/* LCD Controller info data structure, stored in device platform_data */
struct atmel_lcdfb_info {
spinlock_t lock;
struct fb_info *info;
void __iomem *mmio;
int irq_base;
struct work_struct task;
unsigned int smem_len;
struct platform_device *pdev;
struct clk *bus_clk;
struct clk *lcdc_clk;
struct backlight_device *backlight;
u8 saved_lcdcon;
u32 pseudo_palette[16];
bool have_intensity_bit;
struct atmel_lcdfb_pdata pdata;
struct atmel_lcdfb_config *config;
struct regulator *reg_lcd;
};
struct atmel_lcdfb_power_ctrl_gpio {
struct gpio_desc *gpiod;
struct list_head list;
};
#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
/* configurable parameters */
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
#define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */
#define ATMEL_LCDC_FIFO_SIZE 512 /* words */
static struct atmel_lcdfb_config at91sam9261_config = {
.have_hozval = true,
.have_intensity_bit = true,
};
static struct atmel_lcdfb_config at91sam9263_config = {
.have_intensity_bit = true,
};
static struct atmel_lcdfb_config at91sam9g10_config = {
.have_hozval = true,
};
static struct atmel_lcdfb_config at91sam9g45_config = {
.have_alt_pixclock = true,
};
static struct atmel_lcdfb_config at91sam9g45es_config = {
};
static struct atmel_lcdfb_config at91sam9rl_config = {
.have_intensity_bit = true,
};
static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
| ATMEL_LCDC_POL_POSITIVE
| ATMEL_LCDC_ENA_PWMENABLE;
#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
/* some bl->props field just changed */
static int atmel_bl_update_status(struct backlight_device *bl)
{
struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
int brightness = backlight_get_brightness(bl);
lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
if (contrast_ctr & ATMEL_LCDC_POL_POSITIVE)
lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
brightness ? contrast_ctr : 0);
else
lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
return 0;
}
static int atmel_bl_get_brightness(struct backlight_device *bl)
{
struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
}
static const struct backlight_ops atmel_lcdc_bl_ops = {
.update_status = atmel_bl_update_status,
.get_brightness = atmel_bl_get_brightness,
};
static void init_backlight(struct atmel_lcdfb_info *sinfo)
{
struct backlight_properties props;
struct backlight_device *bl;
if (sinfo->backlight)
return;
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = 0xff;
bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
&atmel_lcdc_bl_ops, &props);
if (IS_ERR(bl)) {
dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
PTR_ERR(bl));
return;
}
sinfo->backlight = bl;
bl->props.power = FB_BLANK_UNBLANK;
bl->props.fb_blank = FB_BLANK_UNBLANK;
bl->props.brightness = atmel_bl_get_brightness(bl);
}
static void exit_backlight(struct atmel_lcdfb_info *sinfo)
{
if (!sinfo->backlight)
return;
if (sinfo->backlight->ops) {
sinfo->backlight->props.power = FB_BLANK_POWERDOWN;
sinfo->backlight->ops->update_status(sinfo->backlight);
}
backlight_device_unregister(sinfo->backlight);
}
#else
static void init_backlight(struct atmel_lcdfb_info *sinfo)
{
dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
}
static void exit_backlight(struct atmel_lcdfb_info *sinfo)
{
}
#endif
static void init_contrast(struct atmel_lcdfb_info *sinfo)
{
struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
/* contrast pwm can be 'inverted' */
if (pdata->lcdcon_pol_negative)
contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
/* have some default contrast/backlight settings */
lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
if (pdata->lcdcon_is_backlight)
init_backlight(sinfo);
}
static inline void atmel_lcdfb_power_control(struct atmel_lcdfb_info *sinfo, int on)
{
int ret;
struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
if (pdata->atmel_lcdfb_power_control)
pdata->atmel_lcdfb_power_control(pdata, on);
else if (sinfo->reg_lcd) {
if (on) {
ret = regulator_enable(sinfo->reg_lcd);
if (ret)
dev_err(&sinfo->pdev->dev,
"lcd regulator enable failed: %d\n", ret);
} else {
ret = regulator_disable(sinfo->reg_lcd);
if (ret)
dev_err(&sinfo->pdev->dev,
"lcd regulator disable failed: %d\n", ret);
}
}
}
static const struct fb_fix_screeninfo atmel_lcdfb_fix __initconst = {
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static unsigned long compute_hozval(struct atmel_lcdfb_info *sinfo,
unsigned long xres)
{
unsigned long lcdcon2;
unsigned long value;
if (!sinfo->config->have_hozval)
return xres;
lcdcon2 = lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2);
value = xres;
if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
/* STN display */
if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
value *= 3;
}
if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
|| ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
&& (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
value = DIV_ROUND_UP(value, 4);
else
value = DIV_ROUND_UP(value, 8);
}
return value;
}
static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
{
struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
/* Turn off the LCD controller and the DMA controller */
lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
/* Wait for the LCDC core to become idle */
while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
msleep(10);
lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
}
static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
{
atmel_lcdfb_stop_nowait(sinfo);
/* Wait for DMA engine to become idle... */
while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
msleep(10);
}
static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
{
struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
lcdc_writel(sinfo, ATMEL_LCDC_DMACON, pdata->default_dmacon);
lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
(pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
| ATMEL_LCDC_PWR);
}
static void atmel_lcdfb_update_dma(struct fb_info *info,
struct fb_var_screeninfo *var)
{
struct atmel_lcdfb_info *sinfo = info->par;
struct fb_fix_screeninfo *fix = &info->fix;
unsigned long dma_addr;
dma_addr = (fix->smem_start + var->yoffset * fix->line_length
+ var->xoffset * info->var.bits_per_pixel / 8);
dma_addr &= ~3UL;
/* Set framebuffer DMA base address and pixel offset */
lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
}
static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
{
struct fb_info *info = sinfo->info;
dma_free_wc(info->device, info->fix.smem_len, info->screen_base,
info->fix.smem_start);
}
/**
* atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
* @sinfo: the frame buffer to allocate memory for
*
* This function is called only from the atmel_lcdfb_probe()
* so no locking by fb_info->mm_lock around smem_len setting is needed.
*/
static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
{
struct fb_info *info = sinfo->info;
struct fb_var_screeninfo *var = &info->var;
unsigned int smem_len;
smem_len = (var->xres_virtual * var->yres_virtual
* ((var->bits_per_pixel + 7) / 8));
info->fix.smem_len = max(smem_len, sinfo->smem_len);
info->screen_base = dma_alloc_wc(info->device, info->fix.smem_len,
(dma_addr_t *)&info->fix.smem_start,
GFP_KERNEL);
if (!info->screen_base) {
return -ENOMEM;
}
memset(info->screen_base, 0, info->fix.smem_len);
return 0;
}
static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct fb_videomode varfbmode;
const struct fb_videomode *fbmode = NULL;
fb_var_to_videomode(&varfbmode, var);
fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
if (fbmode)
fb_videomode_to_var(var, fbmode);
return fbmode;
}
/**
* atmel_lcdfb_check_var - Validates a var passed in.
* @var: frame buffer variable screen structure
* @info: frame buffer structure that represents a single frame buffer
*
* Checks to see if the hardware supports the state requested by
* var passed in. This function does not alter the hardware
* state!!! This means the data stored in struct fb_info and
* struct atmel_lcdfb_info do not change. This includes the var
* inside of struct fb_info. Do NOT change these. This function
* can be called on its own if we intent to only test a mode and
* not actually set it. The stuff in modedb.c is a example of
* this. If the var passed in is slightly off by what the
* hardware can support then we alter the var PASSED in to what
* we can do. If the hardware doesn't support mode change a
* -EINVAL will be returned by the upper layers. You don't need
* to implement this function then. If you hardware doesn't
* support changing the resolution then this function is not
* needed. In this case the driver would just provide a var that
* represents the static state the screen is in.
*
* Returns negative errno on error, or zero on success.
*/
static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct device *dev = info->device;
struct atmel_lcdfb_info *sinfo = info->par;
struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
unsigned long clk_value_khz;
clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
dev_dbg(dev, "%s:\n", __func__);
if (!(var->pixclock && var->bits_per_pixel)) {
/* choose a suitable mode if possible */
if (!atmel_lcdfb_choose_mode(var, info)) {
dev_err(dev, "needed value not specified\n");
return -EINVAL;
}
}
dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
return -EINVAL;
}
/* Do not allow to have real resoulution larger than virtual */
if (var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
/* Force same alignment for each line */
var->xres = (var->xres + 3) & ~3UL;
var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
var->transp.msb_right = 0;
var->transp.offset = var->transp.length = 0;
var->xoffset = var->yoffset = 0;
if (info->fix.smem_len) {
unsigned int smem_len = (var->xres_virtual * var->yres_virtual
* ((var->bits_per_pixel + 7) / 8));
if (smem_len > info->fix.smem_len) {
dev_err(dev, "Frame buffer is too small (%u) for screen size (need at least %u)\n",
info->fix.smem_len, smem_len);
return -EINVAL;
}
}
/* Saturate vertical and horizontal timings at maximum values */
var->vsync_len = min_t(u32, var->vsync_len,
(ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
var->upper_margin = min_t(u32, var->upper_margin,
ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
var->lower_margin = min_t(u32, var->lower_margin,
ATMEL_LCDC_VFP);
var->right_margin = min_t(u32, var->right_margin,
(ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
var->hsync_len = min_t(u32, var->hsync_len,
(ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
var->left_margin = min_t(u32, var->left_margin,
ATMEL_LCDC_HBP + 1);
/* Some parameters can't be zero */
var->vsync_len = max_t(u32, var->vsync_len, 1);
var->right_margin = max_t(u32, var->right_margin, 1);
var->hsync_len = max_t(u32, var->hsync_len, 1);
var->left_margin = max_t(u32, var->left_margin, 1);
switch (var->bits_per_pixel) {
case 1:
case 2:
case 4:
case 8:
var->red.offset = var->green.offset = var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length
= var->bits_per_pixel;
break;
case 16:
/* Older SOCs use IBGR:555 rather than BGR:565. */
if (sinfo->config->have_intensity_bit)
var->green.length = 5;
else
var->green.length = 6;
if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
/* RGB:5X5 mode */
var->red.offset = var->green.length + 5;
var->blue.offset = 0;
} else {
/* BGR:5X5 mode */
var->red.offset = 0;
var->blue.offset = var->green.length + 5;
}
var->green.offset = 5;
var->red.length = var->blue.length = 5;
break;
case 32:
var->transp.offset = 24;
var->transp.length = 8;
fallthrough;
case 24:
if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
/* RGB:888 mode */
var->red.offset = 16;
var->blue.offset = 0;
} else {
/* BGR:888 mode */
var->red.offset = 0;
var->blue.offset = 16;
}
var->green.offset = 8;
var->red.length = var->green.length = var->blue.length = 8;
break;
default:
dev_err(dev, "color depth %d not supported\n",
var->bits_per_pixel);
return -EINVAL;
}
return 0;
}
/*
* LCD reset sequence
*/
static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
{
might_sleep();
atmel_lcdfb_stop(sinfo);
atmel_lcdfb_start(sinfo);
}
/**
* atmel_lcdfb_set_par - Alters the hardware state.
* @info: frame buffer structure that represents a single frame buffer
*
* Using the fb_var_screeninfo in fb_info we set the resolution
* of the this particular framebuffer. This function alters the
* par AND the fb_fix_screeninfo stored in fb_info. It doesn't
* not alter var in fb_info since we are using that data. This
* means we depend on the data in var inside fb_info to be
* supported by the hardware. atmel_lcdfb_check_var is always called
* before atmel_lcdfb_set_par to ensure this. Again if you can't
* change the resolution you don't need this function.
*
*/
static int atmel_lcdfb_set_par(struct fb_info *info)
{
struct atmel_lcdfb_info *sinfo = info->par;
struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
unsigned long hozval_linesz;
unsigned long value;
unsigned long clk_value_khz;
unsigned long bits_per_line;
unsigned long pix_factor = 2;
might_sleep();
dev_dbg(info->device, "%s:\n", __func__);
dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
info->var.xres, info->var.yres,
info->var.xres_virtual, info->var.yres_virtual);
atmel_lcdfb_stop_nowait(sinfo);
if (info->var.bits_per_pixel == 1)
info->fix.visual = FB_VISUAL_MONO01;
else if (info->var.bits_per_pixel <= 8)
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
else
info->fix.visual = FB_VISUAL_TRUECOLOR;
bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
/* Re-initialize the DMA engine... */
dev_dbg(info->device, " * update DMA engine\n");
atmel_lcdfb_update_dma(info, &info->var);
/* ...set frame size and burst length = 8 words (?) */
value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
/* Now, the LCDC core... */
/* Set pixel clock */
if (sinfo->config->have_alt_pixclock)
pix_factor = 1;
clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
if (value < pix_factor) {
dev_notice(info->device, "Bypassing pixel clock divider\n");
lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
} else {
value = (value / pix_factor) - 1;
dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n",
value);
lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
value << ATMEL_LCDC_CLKVAL_OFFSET);
info->var.pixclock =
KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
dev_dbg(info->device, " updated pixclk: %lu KHz\n",
PICOS2KHZ(info->var.pixclock));
}
/* Initialize control register 2 */
value = pdata->default_lcdcon2;
if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
value |= ATMEL_LCDC_INVLINE_INVERTED;
if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
value |= ATMEL_LCDC_INVFRAME_INVERTED;
switch (info->var.bits_per_pixel) {
case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
case 15: fallthrough;
case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
default: BUG(); break;
}
dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
/* Vertical timing */
value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
value |= info->var.lower_margin;
dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
/* Horizontal timing */
value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
value |= (info->var.left_margin - 1);
dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
/* Horizontal value (aka line size) */
hozval_linesz = compute_hozval(sinfo, info->var.xres);
/* Display size */
value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
value |= info->var.yres - 1;
dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
/* FIFO Threshold: Use formula from data sheet */
value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
/* Toggle LCD_MODE every frame */
lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
/* Disable all interrupts */
lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0U);
/* Enable FIFO & DMA errors */
lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
/* ...wait for DMA engine to become idle... */
while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
msleep(10);
atmel_lcdfb_start(sinfo);
dev_dbg(info->device, " * DONE\n");
return 0;
}
static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
/**
* atmel_lcdfb_setcolreg - Optional function. Sets a color register.
* @regno: Which register in the CLUT we are programming
* @red: The red value which can be up to 16 bits wide
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*
* Set a single color register. The values supplied have a 16 bit
* magnitude which needs to be scaled in this function for the hardware.
* Things to take into consideration are how many color registers, if
* any, are supported with the current color visual. With truecolor mode
* no color palettes are supported. Here a pseudo palette is created
* which we store the value in pseudo_palette in struct fb_info. For
* pseudocolor mode we have a limited color palette. To deal with this
* we can program what color is displayed for a particular pixel value.
* DirectColor is similar in that we can program each color field. If
* we have a static colormap we don't need to implement this function.
*
* Returns negative errno on error, or zero on success. In an
* ideal world, this would have been the case, but as it turns
* out, the other drivers return 1 on failure, so that's what
* we're going to do.
*/
static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
struct atmel_lcdfb_info *sinfo = info->par;
struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
unsigned int val;
u32 *pal;
int ret = 1;
if (info->var.grayscale)
red = green = blue = (19595 * red + 38470 * green
+ 7471 * blue) >> 16;
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
if (regno < 16) {
pal = info->pseudo_palette;
val = chan_to_field(red, &info->var.red);
val |= chan_to_field(green, &info->var.green);
val |= chan_to_field(blue, &info->var.blue);
pal[regno] = val;
ret = 0;
}
break;
case FB_VISUAL_PSEUDOCOLOR:
if (regno < 256) {
if (sinfo->config->have_intensity_bit) {
/* old style I+BGR:555 */
val = ((red >> 11) & 0x001f);
val |= ((green >> 6) & 0x03e0);
val |= ((blue >> 1) & 0x7c00);
/*
* TODO: intensity bit. Maybe something like
* ~(red[10] ^ green[10] ^ blue[10]) & 1
*/
} else {
/* new style BGR:565 / RGB:565 */
if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
val = ((blue >> 11) & 0x001f);
val |= ((red >> 0) & 0xf800);
} else {
val = ((red >> 11) & 0x001f);
val |= ((blue >> 0) & 0xf800);
}
val |= ((green >> 5) & 0x07e0);
}
lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
ret = 0;
}
break;
case FB_VISUAL_MONO01:
if (regno < 2) {
val = (regno == 0) ? 0x00 : 0x1F;
lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
ret = 0;
}
break;
}
return ret;
}
static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
dev_dbg(info->device, "%s\n", __func__);
atmel_lcdfb_update_dma(info, var);
return 0;
}
static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
{
struct atmel_lcdfb_info *sinfo = info->par;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
atmel_lcdfb_start(sinfo);
break;
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
break;
case FB_BLANK_POWERDOWN:
atmel_lcdfb_stop(sinfo);
break;
default:
return -EINVAL;
}
/* let fbcon do a soft blank for us */
return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
}
static const struct fb_ops atmel_lcdfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = atmel_lcdfb_check_var,
.fb_set_par = atmel_lcdfb_set_par,
.fb_setcolreg = atmel_lcdfb_setcolreg,
.fb_blank = atmel_lcdfb_blank,
.fb_pan_display = atmel_lcdfb_pan_display,
};
static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
{
struct fb_info *info = dev_id;
struct atmel_lcdfb_info *sinfo = info->par;
u32 status;
status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
if (status & ATMEL_LCDC_UFLWI) {
dev_warn(info->device, "FIFO underflow %#x\n", status);
/* reset DMA and FIFO to avoid screen shifting */
schedule_work(&sinfo->task);
}
lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
return IRQ_HANDLED;
}
/*
* LCD controller task (to reset the LCD)
*/
static void atmel_lcdfb_task(struct work_struct *work)
{
struct atmel_lcdfb_info *sinfo =
container_of(work, struct atmel_lcdfb_info, task);
atmel_lcdfb_reset(sinfo);
}
static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
{
struct fb_info *info = sinfo->info;
int ret = 0;
info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
dev_info(info->device,
"%luKiB frame buffer at %08lx (mapped at %p)\n",
(unsigned long)info->fix.smem_len / 1024,
(unsigned long)info->fix.smem_start,
info->screen_base);
/* Allocate colormap */
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (ret < 0)
dev_err(info->device, "Alloc color map failed\n");
return ret;
}
static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
{
clk_prepare_enable(sinfo->bus_clk);
clk_prepare_enable(sinfo->lcdc_clk);
}
static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
{
clk_disable_unprepare(sinfo->bus_clk);
clk_disable_unprepare(sinfo->lcdc_clk);
}
static const struct of_device_id atmel_lcdfb_dt_ids[] = {
{ .compatible = "atmel,at91sam9261-lcdc" , .data = &at91sam9261_config, },
{ .compatible = "atmel,at91sam9263-lcdc" , .data = &at91sam9263_config, },
{ .compatible = "atmel,at91sam9g10-lcdc" , .data = &at91sam9g10_config, },
{ .compatible = "atmel,at91sam9g45-lcdc" , .data = &at91sam9g45_config, },
{ .compatible = "atmel,at91sam9g45es-lcdc" , .data = &at91sam9g45es_config, },
{ .compatible = "atmel,at91sam9rl-lcdc" , .data = &at91sam9rl_config, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, atmel_lcdfb_dt_ids);
static const char *atmel_lcdfb_wiring_modes[] = {
[ATMEL_LCDC_WIRING_BGR] = "BRG",
[ATMEL_LCDC_WIRING_RGB] = "RGB",
};
static int atmel_lcdfb_get_of_wiring_modes(struct device_node *np)
{
const char *mode;
int err, i;
err = of_property_read_string(np, "atmel,lcd-wiring-mode", &mode);
if (err < 0)
return ATMEL_LCDC_WIRING_BGR;
for (i = 0; i < ARRAY_SIZE(atmel_lcdfb_wiring_modes); i++)
if (!strcasecmp(mode, atmel_lcdfb_wiring_modes[i]))
return i;
return -ENODEV;
}
static void atmel_lcdfb_power_control_gpio(struct atmel_lcdfb_pdata *pdata, int on)
{
struct atmel_lcdfb_power_ctrl_gpio *og;
list_for_each_entry(og, &pdata->pwr_gpios, list)
gpiod_set_value(og->gpiod, on);
}
static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo)
{
struct fb_info *info = sinfo->info;
struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
struct fb_var_screeninfo *var = &info->var;
struct device *dev = &sinfo->pdev->dev;
struct device_node *np =dev->of_node;
struct device_node *display_np;
struct atmel_lcdfb_power_ctrl_gpio *og;
bool is_gpio_power = false;
struct fb_videomode fb_vm;
struct gpio_desc *gpiod;
struct videomode vm;
int ret;
int i;
sinfo->config = (struct atmel_lcdfb_config*)
of_match_device(atmel_lcdfb_dt_ids, dev)->data;
display_np = of_parse_phandle(np, "display", 0);
if (!display_np) {
dev_err(dev, "failed to find display phandle\n");
return -ENOENT;
}
ret = of_property_read_u32(display_np, "bits-per-pixel", &var->bits_per_pixel);
if (ret < 0) {
dev_err(dev, "failed to get property bits-per-pixel\n");
goto put_display_node;
}
ret = of_property_read_u32(display_np, "atmel,guard-time", &pdata->guard_time);
if (ret < 0) {
dev_err(dev, "failed to get property atmel,guard-time\n");
goto put_display_node;
}
ret = of_property_read_u32(display_np, "atmel,lcdcon2", &pdata->default_lcdcon2);
if (ret < 0) {
dev_err(dev, "failed to get property atmel,lcdcon2\n");
goto put_display_node;
}
ret = of_property_read_u32(display_np, "atmel,dmacon", &pdata->default_dmacon);
if (ret < 0) {
dev_err(dev, "failed to get property bits-per-pixel\n");
goto put_display_node;
}
INIT_LIST_HEAD(&pdata->pwr_gpios);
for (i = 0; i < gpiod_count(dev, "atmel,power-control"); i++) {
ret = -ENOMEM;
gpiod = devm_gpiod_get_index(dev, "atmel,power-control",
i, GPIOD_ASIS);
if (IS_ERR(gpiod))
continue;
og = devm_kzalloc(dev, sizeof(*og), GFP_KERNEL);
if (!og)
goto put_display_node;
og->gpiod = gpiod;
is_gpio_power = true;
ret = gpiod_direction_output(gpiod, gpiod_is_active_low(gpiod));
if (ret) {
dev_err(dev, "set direction output gpio atmel,power-control[%d] failed\n", i);
goto put_display_node;
}
list_add(&og->list, &pdata->pwr_gpios);
}
if (is_gpio_power)
pdata->atmel_lcdfb_power_control = atmel_lcdfb_power_control_gpio;
ret = atmel_lcdfb_get_of_wiring_modes(display_np);
if (ret < 0) {
dev_err(dev, "invalid atmel,lcd-wiring-mode\n");
goto put_display_node;
}
pdata->lcd_wiring_mode = ret;
pdata->lcdcon_is_backlight = of_property_read_bool(display_np, "atmel,lcdcon-backlight");
pdata->lcdcon_pol_negative = of_property_read_bool(display_np, "atmel,lcdcon-backlight-inverted");
ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE);
if (ret) {
dev_err(dev, "failed to get videomode from DT\n");
goto put_display_node;
}
ret = fb_videomode_from_videomode(&vm, &fb_vm);
if (ret < 0)
goto put_display_node;
fb_add_videomode(&fb_vm, &info->modelist);
put_display_node:
of_node_put(display_np);
return ret;
}
static int __init atmel_lcdfb_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct fb_info *info;
struct atmel_lcdfb_info *sinfo;
struct resource *regs = NULL;
struct resource *map = NULL;
struct fb_modelist *modelist;
int ret;
dev_dbg(dev, "%s BEGIN\n", __func__);
ret = -ENOMEM;
info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
if (!info)
goto out;
sinfo = info->par;
sinfo->pdev = pdev;
sinfo->info = info;
INIT_LIST_HEAD(&info->modelist);
if (!pdev->dev.of_node) {
dev_err(dev, "cannot get default configuration\n");
goto free_info;
}
ret = atmel_lcdfb_of_init(sinfo);
if (ret)
goto free_info;
ret = -ENODEV;
if (!sinfo->config)
goto free_info;
sinfo->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
if (IS_ERR(sinfo->reg_lcd))
sinfo->reg_lcd = NULL;
info->flags = FBINFO_PARTIAL_PAN_OK |
FBINFO_HWACCEL_YPAN;
info->pseudo_palette = sinfo->pseudo_palette;
info->fbops = &atmel_lcdfb_ops;
info->fix = atmel_lcdfb_fix;
strcpy(info->fix.id, sinfo->pdev->name);
/* Enable LCDC Clocks */
sinfo->bus_clk = clk_get(dev, "hclk");
if (IS_ERR(sinfo->bus_clk)) {
ret = PTR_ERR(sinfo->bus_clk);
goto free_info;
}
sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
if (IS_ERR(sinfo->lcdc_clk)) {
ret = PTR_ERR(sinfo->lcdc_clk);
goto put_bus_clk;
}
atmel_lcdfb_start_clock(sinfo);
modelist = list_first_entry(&info->modelist,
struct fb_modelist, list);
fb_videomode_to_var(&info->var, &modelist->mode);
atmel_lcdfb_check_var(&info->var, info);
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!regs) {
dev_err(dev, "resources unusable\n");
ret = -ENXIO;
goto stop_clk;
}
sinfo->irq_base = platform_get_irq(pdev, 0);
if (sinfo->irq_base < 0) {
ret = sinfo->irq_base;
goto stop_clk;
}
/* Initialize video memory */
map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (map) {
/* use a pre-allocated memory buffer */
info->fix.smem_start = map->start;
info->fix.smem_len = resource_size(map);
if (!request_mem_region(info->fix.smem_start,
info->fix.smem_len, pdev->name)) {
ret = -EBUSY;
goto stop_clk;
}
info->screen_base = ioremap_wc(info->fix.smem_start,
info->fix.smem_len);
if (!info->screen_base) {
ret = -ENOMEM;
goto release_intmem;
}
/*
* Don't clear the framebuffer -- someone may have set
* up a splash image.
*/
} else {
/* allocate memory buffer */
ret = atmel_lcdfb_alloc_video_memory(sinfo);
if (ret < 0) {
dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
goto stop_clk;
}
}
/* LCDC registers */
info->fix.mmio_start = regs->start;
info->fix.mmio_len = resource_size(regs);
if (!request_mem_region(info->fix.mmio_start,
info->fix.mmio_len, pdev->name)) {
ret = -EBUSY;
goto free_fb;
}
sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
if (!sinfo->mmio) {
dev_err(dev, "cannot map LCDC registers\n");
ret = -ENOMEM;
goto release_mem;
}
/* Initialize PWM for contrast or backlight ("off") */
init_contrast(sinfo);
/* interrupt */
ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
if (ret) {
dev_err(dev, "request_irq failed: %d\n", ret);
goto unmap_mmio;
}
/* Some operations on the LCDC might sleep and
* require a preemptible task context */
INIT_WORK(&sinfo->task, atmel_lcdfb_task);
ret = atmel_lcdfb_init_fbinfo(sinfo);
if (ret < 0) {
dev_err(dev, "init fbinfo failed: %d\n", ret);
goto unregister_irqs;
}
ret = atmel_lcdfb_set_par(info);
if (ret < 0) {
dev_err(dev, "set par failed: %d\n", ret);
goto unregister_irqs;
}
dev_set_drvdata(dev, info);
/*
* Tell the world that we're ready to go
*/
ret = register_framebuffer(info);
if (ret < 0) {
dev_err(dev, "failed to register framebuffer device: %d\n", ret);
goto reset_drvdata;
}
/* Power up the LCDC screen */
atmel_lcdfb_power_control(sinfo, 1);
dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n",
info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
return 0;
reset_drvdata:
dev_set_drvdata(dev, NULL);
fb_dealloc_cmap(&info->cmap);
unregister_irqs:
cancel_work_sync(&sinfo->task);
free_irq(sinfo->irq_base, info);
unmap_mmio:
exit_backlight(sinfo);
iounmap(sinfo->mmio);
release_mem:
release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
free_fb:
if (map)
iounmap(info->screen_base);
else
atmel_lcdfb_free_video_memory(sinfo);
release_intmem:
if (map)
release_mem_region(info->fix.smem_start, info->fix.smem_len);
stop_clk:
atmel_lcdfb_stop_clock(sinfo);
clk_put(sinfo->lcdc_clk);
put_bus_clk:
clk_put(sinfo->bus_clk);
free_info:
framebuffer_release(info);
out:
dev_dbg(dev, "%s FAILED\n", __func__);
return ret;
}
static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct fb_info *info = dev_get_drvdata(dev);
struct atmel_lcdfb_info *sinfo;
if (!info || !info->par)
return 0;
sinfo = info->par;
cancel_work_sync(&sinfo->task);
exit_backlight(sinfo);
atmel_lcdfb_power_control(sinfo, 0);
unregister_framebuffer(info);
atmel_lcdfb_stop_clock(sinfo);
clk_put(sinfo->lcdc_clk);
clk_put(sinfo->bus_clk);
fb_dealloc_cmap(&info->cmap);
free_irq(sinfo->irq_base, info);
iounmap(sinfo->mmio);
release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
iounmap(info->screen_base);
release_mem_region(info->fix.smem_start, info->fix.smem_len);
} else {
atmel_lcdfb_free_video_memory(sinfo);
}
framebuffer_release(info);
return 0;
}
#ifdef CONFIG_PM
static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct atmel_lcdfb_info *sinfo = info->par;
/*
* We don't want to handle interrupts while the clock is
* stopped. It may take forever.
*/
lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0U);
sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_CTR);
lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
atmel_lcdfb_power_control(sinfo, 0);
atmel_lcdfb_stop(sinfo);
atmel_lcdfb_stop_clock(sinfo);
return 0;
}
static int atmel_lcdfb_resume(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct atmel_lcdfb_info *sinfo = info->par;
atmel_lcdfb_start_clock(sinfo);
atmel_lcdfb_start(sinfo);
atmel_lcdfb_power_control(sinfo, 1);
lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
/* Enable FIFO & DMA errors */
lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
| ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
return 0;
}
#else
#define atmel_lcdfb_suspend NULL
#define atmel_lcdfb_resume NULL
#endif
static struct platform_driver atmel_lcdfb_driver = {
.remove = __exit_p(atmel_lcdfb_remove),
.suspend = atmel_lcdfb_suspend,
.resume = atmel_lcdfb_resume,
.driver = {
.name = "atmel_lcdfb",
.of_match_table = atmel_lcdfb_dt_ids,
},
};
module_platform_driver_probe(atmel_lcdfb_driver, atmel_lcdfb_probe);
MODULE_DESCRIPTION("AT91 LCD Controller framebuffer driver");
MODULE_AUTHOR("Nicolas Ferre <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/atmel_lcdfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/* cg3.c: CGTHREE frame buffer driver
*
* Copyright (C) 2003, 2006 David S. Miller ([email protected])
* Copyright (C) 1996,1998 Jakub Jelinek ([email protected])
* Copyright (C) 1996 Miguel de Icaza ([email protected])
* Copyright (C) 1997 Eddie C. Dost ([email protected])
*
* Driver layout based loosely on tgafb.c, see that file for credits.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/fbio.h>
#include "sbuslib.h"
/*
* Local functions.
*/
static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
unsigned, struct fb_info *);
static int cg3_blank(int, struct fb_info *);
static int cg3_mmap(struct fb_info *, struct vm_area_struct *);
static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);
/*
* Frame buffer operations
*/
static const struct fb_ops cg3_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = cg3_setcolreg,
.fb_blank = cg3_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = cg3_mmap,
.fb_ioctl = cg3_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = sbusfb_compat_ioctl,
#endif
};
/* Control Register Constants */
#define CG3_CR_ENABLE_INTS 0x80
#define CG3_CR_ENABLE_VIDEO 0x40
#define CG3_CR_ENABLE_TIMING 0x20
#define CG3_CR_ENABLE_CURCMP 0x10
#define CG3_CR_XTAL_MASK 0x0c
#define CG3_CR_DIVISOR_MASK 0x03
/* Status Register Constants */
#define CG3_SR_PENDING_INT 0x80
#define CG3_SR_RES_MASK 0x70
#define CG3_SR_1152_900_76_A 0x40
#define CG3_SR_1152_900_76_B 0x60
#define CG3_SR_ID_MASK 0x0f
#define CG3_SR_ID_COLOR 0x01
#define CG3_SR_ID_MONO 0x02
#define CG3_SR_ID_MONO_ECL 0x03
enum cg3_type {
CG3_AT_66HZ = 0,
CG3_AT_76HZ,
CG3_RDI
};
struct bt_regs {
u32 addr;
u32 color_map;
u32 control;
u32 cursor;
};
struct cg3_regs {
struct bt_regs cmap;
u8 control;
u8 status;
u8 cursor_start;
u8 cursor_end;
u8 h_blank_start;
u8 h_blank_end;
u8 h_sync_start;
u8 h_sync_end;
u8 comp_sync_end;
u8 v_blank_start_high;
u8 v_blank_start_low;
u8 v_blank_end;
u8 v_sync_start;
u8 v_sync_end;
u8 xfer_holdoff_start;
u8 xfer_holdoff_end;
};
/* Offset of interesting structures in the OBIO space */
#define CG3_REGS_OFFSET 0x400000UL
#define CG3_RAM_OFFSET 0x800000UL
struct cg3_par {
spinlock_t lock;
struct cg3_regs __iomem *regs;
u32 sw_cmap[((256 * 3) + 3) / 4];
u32 flags;
#define CG3_FLAG_BLANKED 0x00000001
#define CG3_FLAG_RDI 0x00000002
unsigned long which_io;
};
/**
* cg3_setcolreg - Optional function. Sets a color register.
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*
* The cg3 palette is loaded with 4 color values at each time
* so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
* We keep a sw copy of the hw cmap to assist us in this esoteric
* loading procedure.
*/
static int cg3_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct cg3_par *par = (struct cg3_par *) info->par;
struct bt_regs __iomem *bt = &par->regs->cmap;
unsigned long flags;
u32 *p32;
u8 *p8;
int count;
if (regno >= 256)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
spin_lock_irqsave(&par->lock, flags);
p8 = (u8 *)par->sw_cmap + (regno * 3);
p8[0] = red;
p8[1] = green;
p8[2] = blue;
#define D4M3(x) ((((x)>>2)<<1) + ((x)>>2)) /* (x/4)*3 */
#define D4M4(x) ((x)&~0x3) /* (x/4)*4 */
count = 3;
p32 = &par->sw_cmap[D4M3(regno)];
sbus_writel(D4M4(regno), &bt->addr);
while (count--)
sbus_writel(*p32++, &bt->color_map);
#undef D4M3
#undef D4M4
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
/**
* cg3_blank - Optional function. Blanks the display.
* @blank: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int cg3_blank(int blank, struct fb_info *info)
{
struct cg3_par *par = (struct cg3_par *) info->par;
struct cg3_regs __iomem *regs = par->regs;
unsigned long flags;
u8 val;
spin_lock_irqsave(&par->lock, flags);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
val = sbus_readb(®s->control);
val |= CG3_CR_ENABLE_VIDEO;
sbus_writeb(val, ®s->control);
par->flags &= ~CG3_FLAG_BLANKED;
break;
case FB_BLANK_NORMAL: /* Normal blanking */
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
case FB_BLANK_POWERDOWN: /* Poweroff */
val = sbus_readb(®s->control);
val &= ~CG3_CR_ENABLE_VIDEO;
sbus_writeb(val, ®s->control);
par->flags |= CG3_FLAG_BLANKED;
break;
}
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
static struct sbus_mmap_map cg3_mmap_map[] = {
{
.voff = CG3_MMAP_OFFSET,
.poff = CG3_RAM_OFFSET,
.size = SBUS_MMAP_FBSIZE(1)
},
{ .size = 0 }
};
static int cg3_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct cg3_par *par = (struct cg3_par *)info->par;
return sbusfb_mmap_helper(cg3_mmap_map,
info->fix.smem_start, info->fix.smem_len,
par->which_io,
vma);
}
static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
return sbusfb_ioctl_helper(cmd, arg, info,
FBTYPE_SUN3COLOR, 8, info->fix.smem_len);
}
/*
* Initialisation
*/
static void cg3_init_fix(struct fb_info *info, int linebytes,
struct device_node *dp)
{
snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = linebytes;
info->fix.accel = FB_ACCEL_SUN_CGTHREE;
}
static void cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
struct device_node *dp)
{
const char *params;
char *p;
int ww, hh;
params = of_get_property(dp, "params", NULL);
if (params) {
ww = simple_strtoul(params, &p, 10);
if (ww && *p == 'x') {
hh = simple_strtoul(p + 1, &p, 10);
if (hh && *p == '-') {
if (var->xres != ww ||
var->yres != hh) {
var->xres = var->xres_virtual = ww;
var->yres = var->yres_virtual = hh;
}
}
}
}
}
static u8 cg3regvals_66hz[] = { /* 1152 x 900, 66 Hz */
0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x20, 0
};
static u8 cg3regvals_76hz[] = { /* 1152 x 900, 76 Hz */
0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x24, 0
};
static u8 cg3regvals_rdi[] = { /* 640 x 480, cgRDI */
0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10,
0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51,
0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
0x10, 0x22, 0
};
static u8 *cg3_regvals[] = {
cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
};
static u_char cg3_dacvals[] = {
4, 0xff, 5, 0x00, 6, 0x70, 7, 0x00, 0
};
static int cg3_do_default_mode(struct cg3_par *par)
{
enum cg3_type type;
u8 *p;
if (par->flags & CG3_FLAG_RDI)
type = CG3_RDI;
else {
u8 status = sbus_readb(&par->regs->status), mon;
if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
mon = status & CG3_SR_RES_MASK;
if (mon == CG3_SR_1152_900_76_A ||
mon == CG3_SR_1152_900_76_B)
type = CG3_AT_76HZ;
else
type = CG3_AT_66HZ;
} else {
printk(KERN_ERR "cgthree: can't handle SR %02x\n",
status);
return -EINVAL;
}
}
for (p = cg3_regvals[type]; *p; p += 2) {
u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
sbus_writeb(p[1], regp);
}
for (p = cg3_dacvals; *p; p += 2) {
u8 __iomem *regp;
regp = (u8 __iomem *)&par->regs->cmap.addr;
sbus_writeb(p[0], regp);
regp = (u8 __iomem *)&par->regs->cmap.control;
sbus_writeb(p[1], regp);
}
return 0;
}
static int cg3_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct fb_info *info;
struct cg3_par *par;
int linebytes, err;
info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev);
err = -ENOMEM;
if (!info)
goto out_err;
par = info->par;
spin_lock_init(&par->lock);
info->fix.smem_start = op->resource[0].start;
par->which_io = op->resource[0].flags & IORESOURCE_BITS;
sbusfb_fill_var(&info->var, dp, 8);
info->var.red.length = 8;
info->var.green.length = 8;
info->var.blue.length = 8;
if (of_node_name_eq(dp, "cgRDI"))
par->flags |= CG3_FLAG_RDI;
if (par->flags & CG3_FLAG_RDI)
cg3_rdi_maybe_fixup_var(&info->var, dp);
linebytes = of_getintprop_default(dp, "linebytes",
info->var.xres);
info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,
sizeof(struct cg3_regs), "cg3 regs");
if (!par->regs)
goto out_release_fb;
info->fbops = &cg3_ops;
info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET,
info->fix.smem_len, "cg3 ram");
if (!info->screen_base)
goto out_unmap_regs;
cg3_blank(FB_BLANK_UNBLANK, info);
if (!of_property_present(dp, "width")) {
err = cg3_do_default_mode(par);
if (err)
goto out_unmap_screen;
}
err = fb_alloc_cmap(&info->cmap, 256, 0);
if (err)
goto out_unmap_screen;
fb_set_cmap(&info->cmap, info);
cg3_init_fix(info, linebytes, dp);
err = register_framebuffer(info);
if (err < 0)
goto out_dealloc_cmap;
dev_set_drvdata(&op->dev, info);
printk(KERN_INFO "%pOF: cg3 at %lx:%lx\n",
dp, par->which_io, info->fix.smem_start);
return 0;
out_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
out_unmap_screen:
of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
out_unmap_regs:
of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
out_release_fb:
framebuffer_release(info);
out_err:
return err;
}
static void cg3_remove(struct platform_device *op)
{
struct fb_info *info = dev_get_drvdata(&op->dev);
struct cg3_par *par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
of_iounmap(&op->resource[0], info->screen_base, info->fix.smem_len);
framebuffer_release(info);
}
static const struct of_device_id cg3_match[] = {
{
.name = "cgthree",
},
{
.name = "cgRDI",
},
{},
};
MODULE_DEVICE_TABLE(of, cg3_match);
static struct platform_driver cg3_driver = {
.driver = {
.name = "cg3",
.of_match_table = cg3_match,
},
.probe = cg3_probe,
.remove_new = cg3_remove,
};
static int __init cg3_init(void)
{
if (fb_get_options("cg3fb", NULL))
return -ENODEV;
return platform_driver_register(&cg3_driver);
}
static void __exit cg3_exit(void)
{
platform_driver_unregister(&cg3_driver);
}
module_init(cg3_init);
module_exit(cg3_exit);
MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/cg3.c |
/*
* broadsheetfb.c -- FB driver for E-Ink Broadsheet controller
*
* Copyright (C) 2008, Jaya Kumar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
*
* This driver is written to be used with the Broadsheet display controller.
*
* It is intended to be architecture independent. A board specific driver
* must be used to perform all the physical IO interactions.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/firmware.h>
#include <linux/uaccess.h>
#include <video/broadsheetfb.h>
/* track panel specific parameters */
struct panel_info {
int w;
int h;
u16 sdcfg;
u16 gdcfg;
u16 lutfmt;
u16 fsynclen;
u16 fendfbegin;
u16 lsynclen;
u16 lendlbegin;
u16 pixclk;
};
/* table of panel specific parameters to be indexed into by the board drivers */
static struct panel_info panel_table[] = {
{ /* standard 6" on TFT backplane */
.w = 800,
.h = 600,
.sdcfg = (100 | (1 << 8) | (1 << 9)),
.gdcfg = 2,
.lutfmt = (4 | (1 << 7)),
.fsynclen = 4,
.fendfbegin = (10 << 8) | 4,
.lsynclen = 10,
.lendlbegin = (100 << 8) | 4,
.pixclk = 6,
},
{ /* custom 3.7" flexible on PET or steel */
.w = 320,
.h = 240,
.sdcfg = (67 | (0 << 8) | (0 << 9) | (0 << 10) | (0 << 12)),
.gdcfg = 3,
.lutfmt = (4 | (1 << 7)),
.fsynclen = 0,
.fendfbegin = (80 << 8) | 4,
.lsynclen = 10,
.lendlbegin = (80 << 8) | 20,
.pixclk = 14,
},
{ /* standard 9.7" on TFT backplane */
.w = 1200,
.h = 825,
.sdcfg = (100 | (1 << 8) | (1 << 9) | (0 << 10) | (0 << 12)),
.gdcfg = 2,
.lutfmt = (4 | (1 << 7)),
.fsynclen = 0,
.fendfbegin = (4 << 8) | 4,
.lsynclen = 4,
.lendlbegin = (60 << 8) | 10,
.pixclk = 3,
},
};
#define DPY_W 800
#define DPY_H 600
static struct fb_fix_screeninfo broadsheetfb_fix = {
.id = "broadsheetfb",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_STATIC_PSEUDOCOLOR,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
.line_length = DPY_W,
.accel = FB_ACCEL_NONE,
};
static struct fb_var_screeninfo broadsheetfb_var = {
.xres = DPY_W,
.yres = DPY_H,
.xres_virtual = DPY_W,
.yres_virtual = DPY_H,
.bits_per_pixel = 8,
.grayscale = 1,
.red = { 0, 4, 0 },
.green = { 0, 4, 0 },
.blue = { 0, 4, 0 },
.transp = { 0, 0, 0 },
};
/* main broadsheetfb functions */
static void broadsheet_gpio_issue_data(struct broadsheetfb_par *par, u16 data)
{
par->board->set_ctl(par, BS_WR, 0);
par->board->set_hdb(par, data);
par->board->set_ctl(par, BS_WR, 1);
}
static void broadsheet_gpio_issue_cmd(struct broadsheetfb_par *par, u16 data)
{
par->board->set_ctl(par, BS_DC, 0);
broadsheet_gpio_issue_data(par, data);
}
static void broadsheet_gpio_send_command(struct broadsheetfb_par *par, u16 data)
{
par->board->wait_for_rdy(par);
par->board->set_ctl(par, BS_CS, 0);
broadsheet_gpio_issue_cmd(par, data);
par->board->set_ctl(par, BS_DC, 1);
par->board->set_ctl(par, BS_CS, 1);
}
static void broadsheet_gpio_send_cmdargs(struct broadsheetfb_par *par, u16 cmd,
int argc, u16 *argv)
{
int i;
par->board->wait_for_rdy(par);
par->board->set_ctl(par, BS_CS, 0);
broadsheet_gpio_issue_cmd(par, cmd);
par->board->set_ctl(par, BS_DC, 1);
for (i = 0; i < argc; i++)
broadsheet_gpio_issue_data(par, argv[i]);
par->board->set_ctl(par, BS_CS, 1);
}
static void broadsheet_mmio_send_cmdargs(struct broadsheetfb_par *par, u16 cmd,
int argc, u16 *argv)
{
int i;
par->board->mmio_write(par, BS_MMIO_CMD, cmd);
for (i = 0; i < argc; i++)
par->board->mmio_write(par, BS_MMIO_DATA, argv[i]);
}
static void broadsheet_send_command(struct broadsheetfb_par *par, u16 data)
{
if (par->board->mmio_write)
par->board->mmio_write(par, BS_MMIO_CMD, data);
else
broadsheet_gpio_send_command(par, data);
}
static void broadsheet_send_cmdargs(struct broadsheetfb_par *par, u16 cmd,
int argc, u16 *argv)
{
if (par->board->mmio_write)
broadsheet_mmio_send_cmdargs(par, cmd, argc, argv);
else
broadsheet_gpio_send_cmdargs(par, cmd, argc, argv);
}
static void broadsheet_gpio_burst_write(struct broadsheetfb_par *par, int size,
u16 *data)
{
int i;
u16 tmp;
par->board->set_ctl(par, BS_CS, 0);
par->board->set_ctl(par, BS_DC, 1);
for (i = 0; i < size; i++) {
par->board->set_ctl(par, BS_WR, 0);
tmp = (data[i] & 0x0F) << 4;
tmp |= (data[i] & 0x0F00) << 4;
par->board->set_hdb(par, tmp);
par->board->set_ctl(par, BS_WR, 1);
}
par->board->set_ctl(par, BS_CS, 1);
}
static void broadsheet_mmio_burst_write(struct broadsheetfb_par *par, int size,
u16 *data)
{
int i;
u16 tmp;
for (i = 0; i < size; i++) {
tmp = (data[i] & 0x0F) << 4;
tmp |= (data[i] & 0x0F00) << 4;
par->board->mmio_write(par, BS_MMIO_DATA, tmp);
}
}
static void broadsheet_burst_write(struct broadsheetfb_par *par, int size,
u16 *data)
{
if (par->board->mmio_write)
broadsheet_mmio_burst_write(par, size, data);
else
broadsheet_gpio_burst_write(par, size, data);
}
static u16 broadsheet_gpio_get_data(struct broadsheetfb_par *par)
{
u16 res;
/* wait for ready to go hi. (lo is busy) */
par->board->wait_for_rdy(par);
/* cs lo, dc lo for cmd, we lo for each data, db as usual */
par->board->set_ctl(par, BS_DC, 1);
par->board->set_ctl(par, BS_CS, 0);
par->board->set_ctl(par, BS_WR, 0);
res = par->board->get_hdb(par);
/* strobe wr */
par->board->set_ctl(par, BS_WR, 1);
par->board->set_ctl(par, BS_CS, 1);
return res;
}
static u16 broadsheet_get_data(struct broadsheetfb_par *par)
{
if (par->board->mmio_read)
return par->board->mmio_read(par);
else
return broadsheet_gpio_get_data(par);
}
static void broadsheet_gpio_write_reg(struct broadsheetfb_par *par, u16 reg,
u16 data)
{
/* wait for ready to go hi. (lo is busy) */
par->board->wait_for_rdy(par);
/* cs lo, dc lo for cmd, we lo for each data, db as usual */
par->board->set_ctl(par, BS_CS, 0);
broadsheet_gpio_issue_cmd(par, BS_CMD_WR_REG);
par->board->set_ctl(par, BS_DC, 1);
broadsheet_gpio_issue_data(par, reg);
broadsheet_gpio_issue_data(par, data);
par->board->set_ctl(par, BS_CS, 1);
}
static void broadsheet_mmio_write_reg(struct broadsheetfb_par *par, u16 reg,
u16 data)
{
par->board->mmio_write(par, BS_MMIO_CMD, BS_CMD_WR_REG);
par->board->mmio_write(par, BS_MMIO_DATA, reg);
par->board->mmio_write(par, BS_MMIO_DATA, data);
}
static void broadsheet_write_reg(struct broadsheetfb_par *par, u16 reg,
u16 data)
{
if (par->board->mmio_write)
broadsheet_mmio_write_reg(par, reg, data);
else
broadsheet_gpio_write_reg(par, reg, data);
}
static void broadsheet_write_reg32(struct broadsheetfb_par *par, u16 reg,
u32 data)
{
broadsheet_write_reg(par, reg, cpu_to_le32(data) & 0xFFFF);
broadsheet_write_reg(par, reg + 2, (cpu_to_le32(data) >> 16) & 0xFFFF);
}
static u16 broadsheet_read_reg(struct broadsheetfb_par *par, u16 reg)
{
broadsheet_send_cmdargs(par, BS_CMD_RD_REG, 1, ®);
par->board->wait_for_rdy(par);
return broadsheet_get_data(par);
}
/* functions for waveform manipulation */
static int is_broadsheet_pll_locked(struct broadsheetfb_par *par)
{
return broadsheet_read_reg(par, 0x000A) & 0x0001;
}
static int broadsheet_setup_plls(struct broadsheetfb_par *par)
{
int retry_count = 0;
u16 tmp;
/* disable arral saemipu mode */
broadsheet_write_reg(par, 0x0006, 0x0000);
broadsheet_write_reg(par, 0x0010, 0x0004);
broadsheet_write_reg(par, 0x0012, 0x5949);
broadsheet_write_reg(par, 0x0014, 0x0040);
broadsheet_write_reg(par, 0x0016, 0x0000);
do {
if (retry_count++ > 100)
return -ETIMEDOUT;
mdelay(1);
} while (!is_broadsheet_pll_locked(par));
tmp = broadsheet_read_reg(par, 0x0006);
tmp &= ~0x1;
broadsheet_write_reg(par, 0x0006, tmp);
return 0;
}
static int broadsheet_setup_spi(struct broadsheetfb_par *par)
{
broadsheet_write_reg(par, 0x0204, ((3 << 3) | 1));
broadsheet_write_reg(par, 0x0208, 0x0001);
return 0;
}
static int broadsheet_setup_spiflash(struct broadsheetfb_par *par,
u16 *orig_sfmcd)
{
*orig_sfmcd = broadsheet_read_reg(par, 0x0204);
broadsheet_write_reg(par, 0x0208, 0);
broadsheet_write_reg(par, 0x0204, 0);
broadsheet_write_reg(par, 0x0204, ((3 << 3) | 1));
return 0;
}
static int broadsheet_spiflash_wait_for_bit(struct broadsheetfb_par *par,
u16 reg, int bitnum, int val,
int timeout)
{
u16 tmp;
do {
tmp = broadsheet_read_reg(par, reg);
if (((tmp >> bitnum) & 1) == val)
return 0;
mdelay(1);
} while (timeout--);
return -ETIMEDOUT;
}
static int broadsheet_spiflash_write_byte(struct broadsheetfb_par *par, u8 data)
{
broadsheet_write_reg(par, 0x0202, (data | 0x100));
return broadsheet_spiflash_wait_for_bit(par, 0x0206, 3, 0, 100);
}
static int broadsheet_spiflash_read_byte(struct broadsheetfb_par *par, u8 *data)
{
int err;
u16 tmp;
broadsheet_write_reg(par, 0x0202, 0);
err = broadsheet_spiflash_wait_for_bit(par, 0x0206, 3, 0, 100);
if (err)
return err;
tmp = broadsheet_read_reg(par, 0x200);
*data = tmp & 0xFF;
return 0;
}
static int broadsheet_spiflash_wait_for_status(struct broadsheetfb_par *par,
int timeout)
{
u8 tmp;
int err;
do {
broadsheet_write_reg(par, 0x0208, 1);
err = broadsheet_spiflash_write_byte(par, 0x05);
if (err)
goto failout;
err = broadsheet_spiflash_read_byte(par, &tmp);
if (err)
goto failout;
broadsheet_write_reg(par, 0x0208, 0);
if (!(tmp & 0x1))
return 0;
mdelay(5);
} while (timeout--);
dev_err(par->info->device, "Timed out waiting for spiflash status\n");
return -ETIMEDOUT;
failout:
broadsheet_write_reg(par, 0x0208, 0);
return err;
}
static int broadsheet_spiflash_op_on_address(struct broadsheetfb_par *par,
u8 op, u32 addr)
{
int i;
u8 tmp;
int err;
broadsheet_write_reg(par, 0x0208, 1);
err = broadsheet_spiflash_write_byte(par, op);
if (err)
return err;
for (i = 2; i >= 0; i--) {
tmp = ((addr >> (i * 8)) & 0xFF);
err = broadsheet_spiflash_write_byte(par, tmp);
if (err)
return err;
}
return err;
}
static int broadsheet_verify_spiflash(struct broadsheetfb_par *par,
int *flash_type)
{
int err = 0;
u8 sig;
err = broadsheet_spiflash_op_on_address(par, 0xAB, 0x00000000);
if (err)
goto failout;
err = broadsheet_spiflash_read_byte(par, &sig);
if (err)
goto failout;
if ((sig != 0x10) && (sig != 0x11)) {
dev_err(par->info->device, "Unexpected flash type\n");
err = -EINVAL;
goto failout;
}
*flash_type = sig;
failout:
broadsheet_write_reg(par, 0x0208, 0);
return err;
}
static int broadsheet_setup_for_wfm_write(struct broadsheetfb_par *par,
u16 *initial_sfmcd, int *flash_type)
{
int err;
err = broadsheet_setup_plls(par);
if (err)
return err;
broadsheet_write_reg(par, 0x0106, 0x0203);
err = broadsheet_setup_spi(par);
if (err)
return err;
err = broadsheet_setup_spiflash(par, initial_sfmcd);
if (err)
return err;
return broadsheet_verify_spiflash(par, flash_type);
}
static int broadsheet_spiflash_write_control(struct broadsheetfb_par *par,
int mode)
{
int err;
broadsheet_write_reg(par, 0x0208, 1);
if (mode)
err = broadsheet_spiflash_write_byte(par, 0x06);
else
err = broadsheet_spiflash_write_byte(par, 0x04);
broadsheet_write_reg(par, 0x0208, 0);
return err;
}
static int broadsheet_spiflash_erase_sector(struct broadsheetfb_par *par,
int addr)
{
int err;
broadsheet_spiflash_write_control(par, 1);
err = broadsheet_spiflash_op_on_address(par, 0xD8, addr);
broadsheet_write_reg(par, 0x0208, 0);
if (err)
return err;
err = broadsheet_spiflash_wait_for_status(par, 1000);
return err;
}
static int broadsheet_spiflash_read_range(struct broadsheetfb_par *par,
int addr, int size, char *data)
{
int err;
int i;
err = broadsheet_spiflash_op_on_address(par, 0x03, addr);
if (err)
goto failout;
for (i = 0; i < size; i++) {
err = broadsheet_spiflash_read_byte(par, &data[i]);
if (err)
goto failout;
}
failout:
broadsheet_write_reg(par, 0x0208, 0);
return err;
}
#define BS_SPIFLASH_PAGE_SIZE 256
static int broadsheet_spiflash_write_page(struct broadsheetfb_par *par,
int addr, const char *data)
{
int err;
int i;
broadsheet_spiflash_write_control(par, 1);
err = broadsheet_spiflash_op_on_address(par, 0x02, addr);
if (err)
goto failout;
for (i = 0; i < BS_SPIFLASH_PAGE_SIZE; i++) {
err = broadsheet_spiflash_write_byte(par, data[i]);
if (err)
goto failout;
}
broadsheet_write_reg(par, 0x0208, 0);
err = broadsheet_spiflash_wait_for_status(par, 100);
failout:
return err;
}
static int broadsheet_spiflash_write_sector(struct broadsheetfb_par *par,
int addr, const char *data, int sector_size)
{
int i;
int err;
for (i = 0; i < sector_size; i += BS_SPIFLASH_PAGE_SIZE) {
err = broadsheet_spiflash_write_page(par, addr + i, &data[i]);
if (err)
return err;
}
return 0;
}
/*
* The caller must guarantee that the data to be rewritten is entirely
* contained within this sector. That is, data_start_addr + data_len
* must be less than sector_start_addr + sector_size.
*/
static int broadsheet_spiflash_rewrite_sector(struct broadsheetfb_par *par,
int sector_size, int data_start_addr,
int data_len, const char *data)
{
int err;
char *sector_buffer;
int tail_start_addr;
int start_sector_addr;
sector_buffer = kzalloc(sector_size, GFP_KERNEL);
if (!sector_buffer)
return -ENOMEM;
/* the start address of the sector is the 0th byte of that sector */
start_sector_addr = (data_start_addr / sector_size) * sector_size;
/*
* check if there is head data that we need to readback into our sector
* buffer first
*/
if (data_start_addr != start_sector_addr) {
/*
* we need to read every byte up till the start address of our
* data and we put it into our sector buffer.
*/
err = broadsheet_spiflash_read_range(par, start_sector_addr,
data_start_addr, sector_buffer);
if (err)
goto out;
}
/* now we copy our data into the right place in the sector buffer */
memcpy(sector_buffer + data_start_addr, data, data_len);
/*
* now we check if there is a tail section of the sector that we need to
* readback.
*/
tail_start_addr = (data_start_addr + data_len) % sector_size;
if (tail_start_addr) {
int tail_len;
tail_len = sector_size - tail_start_addr;
/* now we read this tail into our sector buffer */
err = broadsheet_spiflash_read_range(par, tail_start_addr,
tail_len, sector_buffer + tail_start_addr);
if (err)
goto out;
}
/* if we got here we have the full sector that we want to rewrite. */
/* first erase the sector */
err = broadsheet_spiflash_erase_sector(par, start_sector_addr);
if (err)
goto out;
/* now write it */
err = broadsheet_spiflash_write_sector(par, start_sector_addr,
sector_buffer, sector_size);
out:
kfree(sector_buffer);
return err;
}
static int broadsheet_write_spiflash(struct broadsheetfb_par *par, u32 wfm_addr,
const u8 *wfm, int bytecount, int flash_type)
{
int sector_size;
int err;
int cur_addr;
int writecount;
int maxlen;
int offset = 0;
switch (flash_type) {
case 0x10:
sector_size = 32*1024;
break;
case 0x11:
default:
sector_size = 64*1024;
break;
}
while (bytecount) {
cur_addr = wfm_addr + offset;
maxlen = roundup(cur_addr, sector_size) - cur_addr;
writecount = min(bytecount, maxlen);
err = broadsheet_spiflash_rewrite_sector(par, sector_size,
cur_addr, writecount, wfm + offset);
if (err)
return err;
offset += writecount;
bytecount -= writecount;
}
return 0;
}
static int broadsheet_store_waveform_to_spiflash(struct broadsheetfb_par *par,
const u8 *wfm, size_t wfm_size)
{
int err = 0;
u16 initial_sfmcd = 0;
int flash_type = 0;
err = broadsheet_setup_for_wfm_write(par, &initial_sfmcd, &flash_type);
if (err)
goto failout;
err = broadsheet_write_spiflash(par, 0x886, wfm, wfm_size, flash_type);
failout:
broadsheet_write_reg(par, 0x0204, initial_sfmcd);
return err;
}
static ssize_t broadsheet_loadstore_waveform(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
int err;
struct fb_info *info = dev_get_drvdata(dev);
struct broadsheetfb_par *par = info->par;
const struct firmware *fw_entry;
if (len < 1)
return -EINVAL;
err = request_firmware(&fw_entry, "broadsheet.wbf", dev);
if (err < 0) {
dev_err(dev, "Failed to get broadsheet waveform\n");
goto err_failed;
}
/* try to enforce reasonable min max on waveform */
if ((fw_entry->size < 8*1024) || (fw_entry->size > 64*1024)) {
dev_err(dev, "Invalid waveform\n");
err = -EINVAL;
goto err_fw;
}
mutex_lock(&(par->io_lock));
err = broadsheet_store_waveform_to_spiflash(par, fw_entry->data,
fw_entry->size);
mutex_unlock(&(par->io_lock));
if (err < 0) {
dev_err(dev, "Failed to store broadsheet waveform\n");
goto err_fw;
}
dev_info(dev, "Stored broadsheet waveform, size %zd\n", fw_entry->size);
err = len;
err_fw:
release_firmware(fw_entry);
err_failed:
return err;
}
static DEVICE_ATTR(loadstore_waveform, S_IWUSR, NULL,
broadsheet_loadstore_waveform);
/* upper level functions that manipulate the display and other stuff */
static void broadsheet_init_display(struct broadsheetfb_par *par)
{
u16 args[5];
int xres = par->info->var.xres;
int yres = par->info->var.yres;
args[0] = panel_table[par->panel_index].w;
args[1] = panel_table[par->panel_index].h;
args[2] = panel_table[par->panel_index].sdcfg;
args[3] = panel_table[par->panel_index].gdcfg;
args[4] = panel_table[par->panel_index].lutfmt;
broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_CFG, 5, args);
/* did the controller really set it? */
broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_CFG, 5, args);
args[0] = panel_table[par->panel_index].fsynclen;
args[1] = panel_table[par->panel_index].fendfbegin;
args[2] = panel_table[par->panel_index].lsynclen;
args[3] = panel_table[par->panel_index].lendlbegin;
args[4] = panel_table[par->panel_index].pixclk;
broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_TMG, 5, args);
broadsheet_write_reg32(par, 0x310, xres*yres*2);
/* setup waveform */
args[0] = 0x886;
args[1] = 0;
broadsheet_send_cmdargs(par, BS_CMD_RD_WFM_INFO, 2, args);
broadsheet_send_command(par, BS_CMD_UPD_GDRV_CLR);
broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG);
broadsheet_write_reg(par, 0x330, 0x84);
broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG);
args[0] = (0x3 << 4);
broadsheet_send_cmdargs(par, BS_CMD_LD_IMG, 1, args);
args[0] = 0x154;
broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args);
broadsheet_burst_write(par, (panel_table[par->panel_index].w *
panel_table[par->panel_index].h)/2,
(u16 *)par->info->screen_buffer);
broadsheet_send_command(par, BS_CMD_LD_IMG_END);
args[0] = 0x4300;
broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args);
broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG);
broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND);
par->board->wait_for_rdy(par);
}
static void broadsheet_identify(struct broadsheetfb_par *par)
{
u16 rev, prc;
struct device *dev = par->info->device;
rev = broadsheet_read_reg(par, BS_REG_REV);
prc = broadsheet_read_reg(par, BS_REG_PRC);
dev_info(dev, "Broadsheet Rev 0x%x, Product Code 0x%x\n", rev, prc);
if (prc != 0x0047)
dev_warn(dev, "Unrecognized Broadsheet Product Code\n");
if (rev != 0x0100)
dev_warn(dev, "Unrecognized Broadsheet Revision\n");
}
static void broadsheet_init(struct broadsheetfb_par *par)
{
broadsheet_send_command(par, BS_CMD_INIT_SYS_RUN);
/* the controller needs a second */
msleep(1000);
broadsheet_init_display(par);
}
static void broadsheetfb_dpy_update_pages(struct broadsheetfb_par *par,
u16 y1, u16 y2)
{
u16 args[5];
unsigned char *buf = par->info->screen_buffer;
mutex_lock(&(par->io_lock));
/* y1 must be a multiple of 4 so drop the lower bits */
y1 &= 0xFFFC;
/* y2 must be a multiple of 4 , but - 1 so up the lower bits */
y2 |= 0x0003;
args[0] = 0x3 << 4;
args[1] = 0;
args[2] = y1;
args[3] = cpu_to_le16(par->info->var.xres);
args[4] = y2;
broadsheet_send_cmdargs(par, BS_CMD_LD_IMG_AREA, 5, args);
args[0] = 0x154;
broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args);
buf += y1 * par->info->var.xres;
broadsheet_burst_write(par, ((1 + y2 - y1) * par->info->var.xres)/2,
(u16 *) buf);
broadsheet_send_command(par, BS_CMD_LD_IMG_END);
args[0] = 0x4300;
broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args);
broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG);
broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND);
par->board->wait_for_rdy(par);
mutex_unlock(&(par->io_lock));
}
static void broadsheetfb_dpy_update(struct broadsheetfb_par *par)
{
u16 args[5];
mutex_lock(&(par->io_lock));
args[0] = 0x3 << 4;
broadsheet_send_cmdargs(par, BS_CMD_LD_IMG, 1, args);
args[0] = 0x154;
broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args);
broadsheet_burst_write(par, (panel_table[par->panel_index].w *
panel_table[par->panel_index].h)/2,
(u16 *)par->info->screen_buffer);
broadsheet_send_command(par, BS_CMD_LD_IMG_END);
args[0] = 0x4300;
broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args);
broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG);
broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND);
par->board->wait_for_rdy(par);
mutex_unlock(&(par->io_lock));
}
/* this is called back from the deferred io workqueue */
static void broadsheetfb_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist)
{
u16 y1 = 0, h = 0;
unsigned long prev_offset = ULONG_MAX;
struct fb_deferred_io_pageref *pageref;
int h_inc;
u16 yres = info->var.yres;
u16 xres = info->var.xres;
/* height increment is fixed per page */
h_inc = DIV_ROUND_UP(PAGE_SIZE , xres);
/* walk the written page list and swizzle the data */
list_for_each_entry(pageref, pagereflist, list) {
if (prev_offset == ULONG_MAX) {
/* just starting so assign first page */
y1 = pageref->offset / xres;
h = h_inc;
} else if ((prev_offset + PAGE_SIZE) == pageref->offset) {
/* this page is consecutive so increase our height */
h += h_inc;
} else {
/* page not consecutive, issue previous update first */
broadsheetfb_dpy_update_pages(info->par, y1, y1 + h);
/* start over with our non consecutive page */
y1 = pageref->offset / xres;
h = h_inc;
}
prev_offset = pageref->offset;
}
/* if we still have any pages to update we do so now */
if (h >= yres) {
/* its a full screen update, just do it */
broadsheetfb_dpy_update(info->par);
} else {
broadsheetfb_dpy_update_pages(info->par, y1,
min((u16) (y1 + h), yres));
}
}
static void broadsheetfb_defio_damage_range(struct fb_info *info, off_t off, size_t len)
{
struct broadsheetfb_par *par = info->par;
broadsheetfb_dpy_update(par);
}
static void broadsheetfb_defio_damage_area(struct fb_info *info, u32 x, u32 y,
u32 width, u32 height)
{
struct broadsheetfb_par *par = info->par;
broadsheetfb_dpy_update(par);
}
FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(broadsheetfb,
broadsheetfb_defio_damage_range,
broadsheetfb_defio_damage_area)
static const struct fb_ops broadsheetfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_DEFERRED_OPS(broadsheetfb),
};
static struct fb_deferred_io broadsheetfb_defio = {
.delay = HZ/4,
.sort_pagereflist = true,
.deferred_io = broadsheetfb_dpy_deferred_io,
};
static int broadsheetfb_probe(struct platform_device *dev)
{
struct fb_info *info;
struct broadsheet_board *board;
int retval = -ENOMEM;
int videomemorysize;
unsigned char *videomemory;
struct broadsheetfb_par *par;
int i;
int dpyw, dpyh;
int panel_index;
/* pick up board specific routines */
board = dev->dev.platform_data;
if (!board)
return -EINVAL;
/* try to count device specific driver, if can't, platform recalls */
if (!try_module_get(board->owner))
return -ENODEV;
info = framebuffer_alloc(sizeof(struct broadsheetfb_par), &dev->dev);
if (!info)
goto err;
switch (board->get_panel_type()) {
case 37:
panel_index = 1;
break;
case 97:
panel_index = 2;
break;
case 6:
default:
panel_index = 0;
break;
}
dpyw = panel_table[panel_index].w;
dpyh = panel_table[panel_index].h;
videomemorysize = roundup((dpyw*dpyh), PAGE_SIZE);
videomemory = vzalloc(videomemorysize);
if (!videomemory)
goto err_fb_rel;
info->screen_buffer = videomemory;
info->fbops = &broadsheetfb_ops;
broadsheetfb_var.xres = dpyw;
broadsheetfb_var.yres = dpyh;
broadsheetfb_var.xres_virtual = dpyw;
broadsheetfb_var.yres_virtual = dpyh;
info->var = broadsheetfb_var;
broadsheetfb_fix.line_length = dpyw;
info->fix = broadsheetfb_fix;
info->fix.smem_len = videomemorysize;
par = info->par;
par->panel_index = panel_index;
par->info = info;
par->board = board;
par->write_reg = broadsheet_write_reg;
par->read_reg = broadsheet_read_reg;
init_waitqueue_head(&par->waitq);
mutex_init(&par->io_lock);
info->flags = FBINFO_VIRTFB;
info->fbdefio = &broadsheetfb_defio;
fb_deferred_io_init(info);
retval = fb_alloc_cmap(&info->cmap, 16, 0);
if (retval < 0) {
dev_err(&dev->dev, "Failed to allocate colormap\n");
goto err_vfree;
}
/* set cmap */
for (i = 0; i < 16; i++)
info->cmap.red[i] = (((2*i)+1)*(0xFFFF))/32;
memcpy(info->cmap.green, info->cmap.red, sizeof(u16)*16);
memcpy(info->cmap.blue, info->cmap.red, sizeof(u16)*16);
retval = par->board->setup_irq(info);
if (retval < 0)
goto err_cmap;
/* this inits the dpy */
retval = board->init(par);
if (retval < 0)
goto err_free_irq;
broadsheet_identify(par);
broadsheet_init(par);
retval = register_framebuffer(info);
if (retval < 0)
goto err_free_irq;
platform_set_drvdata(dev, info);
retval = device_create_file(&dev->dev, &dev_attr_loadstore_waveform);
if (retval < 0)
goto err_unreg_fb;
fb_info(info, "Broadsheet frame buffer, using %dK of video memory\n",
videomemorysize >> 10);
return 0;
err_unreg_fb:
unregister_framebuffer(info);
err_free_irq:
board->cleanup(par);
err_cmap:
fb_dealloc_cmap(&info->cmap);
err_vfree:
vfree(videomemory);
err_fb_rel:
framebuffer_release(info);
err:
module_put(board->owner);
return retval;
}
static void broadsheetfb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
if (info) {
struct broadsheetfb_par *par = info->par;
device_remove_file(info->device, &dev_attr_loadstore_waveform);
unregister_framebuffer(info);
fb_deferred_io_cleanup(info);
par->board->cleanup(par);
fb_dealloc_cmap(&info->cmap);
vfree(info->screen_buffer);
module_put(par->board->owner);
framebuffer_release(info);
}
}
static struct platform_driver broadsheetfb_driver = {
.probe = broadsheetfb_probe,
.remove_new = broadsheetfb_remove,
.driver = {
.name = "broadsheetfb",
},
};
module_platform_driver(broadsheetfb_driver);
MODULE_DESCRIPTION("fbdev driver for Broadsheet controller");
MODULE_AUTHOR("Jaya Kumar");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE("broadsheet.wbf");
| linux-master | drivers/video/fbdev/broadsheetfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/wmt_ge_rops.c
*
* Accelerators for raster operations using WonderMedia Graphics Engine
*
* Copyright (C) 2010 Alexey Charkov <[email protected]>
*/
#include <linux/module.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include "core/fb_draw.h"
#include "wmt_ge_rops.h"
#define GE_COMMAND_OFF 0x00
#define GE_DEPTH_OFF 0x04
#define GE_HIGHCOLOR_OFF 0x08
#define GE_ROPCODE_OFF 0x14
#define GE_FIRE_OFF 0x18
#define GE_SRCBASE_OFF 0x20
#define GE_SRCDISPW_OFF 0x24
#define GE_SRCDISPH_OFF 0x28
#define GE_SRCAREAX_OFF 0x2c
#define GE_SRCAREAY_OFF 0x30
#define GE_SRCAREAW_OFF 0x34
#define GE_SRCAREAH_OFF 0x38
#define GE_DESTBASE_OFF 0x3c
#define GE_DESTDISPW_OFF 0x40
#define GE_DESTDISPH_OFF 0x44
#define GE_DESTAREAX_OFF 0x48
#define GE_DESTAREAY_OFF 0x4c
#define GE_DESTAREAW_OFF 0x50
#define GE_DESTAREAH_OFF 0x54
#define GE_PAT0C_OFF 0x88 /* Pattern 0 color */
#define GE_ENABLE_OFF 0xec
#define GE_INTEN_OFF 0xf0
#define GE_STATUS_OFF 0xf8
static void __iomem *regbase;
void wmt_ge_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
{
unsigned long fg, pat;
if (p->state != FBINFO_STATE_RUNNING)
return;
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR)
fg = ((u32 *) (p->pseudo_palette))[rect->color];
else
fg = rect->color;
pat = pixel_to_pat(p->var.bits_per_pixel, fg);
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
writel(p->var.bits_per_pixel == 32 ? 3 :
(p->var.bits_per_pixel == 8 ? 0 : 1), regbase + GE_DEPTH_OFF);
writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF);
writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
writel(rect->dx, regbase + GE_DESTAREAX_OFF);
writel(rect->dy, regbase + GE_DESTAREAY_OFF);
writel(rect->width - 1, regbase + GE_DESTAREAW_OFF);
writel(rect->height - 1, regbase + GE_DESTAREAH_OFF);
writel(pat, regbase + GE_PAT0C_OFF);
writel(1, regbase + GE_COMMAND_OFF);
writel(rect->rop == ROP_XOR ? 0x5a : 0xf0, regbase + GE_ROPCODE_OFF);
writel(1, regbase + GE_FIRE_OFF);
}
EXPORT_SYMBOL_GPL(wmt_ge_fillrect);
void wmt_ge_copyarea(struct fb_info *p, const struct fb_copyarea *area)
{
if (p->state != FBINFO_STATE_RUNNING)
return;
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
writel(p->var.bits_per_pixel > 16 ? 3 :
(p->var.bits_per_pixel > 8 ? 1 : 0), regbase + GE_DEPTH_OFF);
writel(p->fix.smem_start, regbase + GE_SRCBASE_OFF);
writel(p->var.xres_virtual - 1, regbase + GE_SRCDISPW_OFF);
writel(p->var.yres_virtual - 1, regbase + GE_SRCDISPH_OFF);
writel(area->sx, regbase + GE_SRCAREAX_OFF);
writel(area->sy, regbase + GE_SRCAREAY_OFF);
writel(area->width - 1, regbase + GE_SRCAREAW_OFF);
writel(area->height - 1, regbase + GE_SRCAREAH_OFF);
writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF);
writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF);
writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF);
writel(area->dx, regbase + GE_DESTAREAX_OFF);
writel(area->dy, regbase + GE_DESTAREAY_OFF);
writel(area->width - 1, regbase + GE_DESTAREAW_OFF);
writel(area->height - 1, regbase + GE_DESTAREAH_OFF);
writel(0xcc, regbase + GE_ROPCODE_OFF);
writel(1, regbase + GE_COMMAND_OFF);
writel(1, regbase + GE_FIRE_OFF);
}
EXPORT_SYMBOL_GPL(wmt_ge_copyarea);
int wmt_ge_sync(struct fb_info *p)
{
int loops = 5000000;
while ((readl(regbase + GE_STATUS_OFF) & 4) && --loops)
cpu_relax();
return loops > 0 ? 0 : -EBUSY;
}
EXPORT_SYMBOL_GPL(wmt_ge_sync);
static int wmt_ge_rops_probe(struct platform_device *pdev)
{
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "no I/O memory resource defined\n");
return -ENODEV;
}
/* Only one ROP engine is presently supported. */
if (unlikely(regbase)) {
WARN_ON(1);
return -EBUSY;
}
regbase = ioremap(res->start, resource_size(res));
if (regbase == NULL) {
dev_err(&pdev->dev, "failed to map I/O memory\n");
return -EBUSY;
}
writel(1, regbase + GE_ENABLE_OFF);
printk(KERN_INFO "Enabled support for WMT GE raster acceleration\n");
return 0;
}
static void wmt_ge_rops_remove(struct platform_device *pdev)
{
iounmap(regbase);
}
static const struct of_device_id wmt_dt_ids[] = {
{ .compatible = "wm,prizm-ge-rops", },
{ /* sentinel */ }
};
static struct platform_driver wmt_ge_rops_driver = {
.probe = wmt_ge_rops_probe,
.remove_new = wmt_ge_rops_remove,
.driver = {
.name = "wmt_ge_rops",
.of_match_table = wmt_dt_ids,
},
};
module_platform_driver(wmt_ge_rops_driver);
MODULE_AUTHOR("Alexey Charkov <[email protected]>");
MODULE_DESCRIPTION("Accelerators for raster operations using "
"WonderMedia Graphics Engine");
MODULE_DEVICE_TABLE(of, wmt_dt_ids);
| linux-master | drivers/video/fbdev/wmt_ge_rops.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Cirrus Logic CLPS711X FB driver
*
* Copyright (C) 2014 Alexander Shiyan <[email protected]>
* Based on driver by Russell King <[email protected]>
*/
#include <linux/clk.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/lcd.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/clps711x.h>
#include <linux/regulator/consumer.h>
#include <video/of_display_timing.h>
#define CLPS711X_FB_NAME "clps711x-fb"
#define CLPS711X_FB_BPP_MAX (4)
/* Registers relative to LCDCON */
#define CLPS711X_LCDCON (0x0000)
# define LCDCON_GSEN BIT(30)
# define LCDCON_GSMD BIT(31)
#define CLPS711X_PALLSW (0x0280)
#define CLPS711X_PALMSW (0x02c0)
#define CLPS711X_FBADDR (0x0d40)
struct clps711x_fb_info {
struct clk *clk;
void __iomem *base;
struct regmap *syscon;
resource_size_t buffsize;
struct fb_videomode mode;
struct regulator *lcd_pwr;
u32 ac_prescale;
bool cmap_invert;
};
static int clps711x_fb_setcolreg(u_int regno, u_int red, u_int green,
u_int blue, u_int transp, struct fb_info *info)
{
struct clps711x_fb_info *cfb = info->par;
u32 level, mask, shift;
if (regno >= BIT(info->var.bits_per_pixel))
return -EINVAL;
shift = 4 * (regno & 7);
mask = 0xf << shift;
/* gray = 0.30*R + 0.58*G + 0.11*B */
level = (((red * 77 + green * 151 + blue * 28) >> 20) << shift) & mask;
if (cfb->cmap_invert)
level = 0xf - level;
regno = (regno < 8) ? CLPS711X_PALLSW : CLPS711X_PALMSW;
writel((readl(cfb->base + regno) & ~mask) | level, cfb->base + regno);
return 0;
}
static int clps711x_fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
u32 val;
if (var->bits_per_pixel < 1 ||
var->bits_per_pixel > CLPS711X_FB_BPP_MAX)
return -EINVAL;
if (!var->pixclock)
return -EINVAL;
val = DIV_ROUND_UP(var->xres, 16) - 1;
if (val < 0x01 || val > 0x3f)
return -EINVAL;
val = DIV_ROUND_UP(var->yres * var->xres * var->bits_per_pixel, 128);
val--;
if (val < 0x001 || val > 0x1fff)
return -EINVAL;
var->transp.msb_right = 0;
var->transp.offset = 0;
var->transp.length = 0;
var->red.msb_right = 0;
var->red.offset = 0;
var->red.length = var->bits_per_pixel;
var->green = var->red;
var->blue = var->red;
var->grayscale = var->bits_per_pixel > 1;
return 0;
}
static int clps711x_fb_set_par(struct fb_info *info)
{
struct clps711x_fb_info *cfb = info->par;
resource_size_t size;
u32 lcdcon, pps;
size = (info->var.xres * info->var.yres * info->var.bits_per_pixel) / 8;
if (size > cfb->buffsize)
return -EINVAL;
switch (info->var.bits_per_pixel) {
case 1:
info->fix.visual = FB_VISUAL_MONO01;
break;
case 2:
case 4:
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
default:
return -EINVAL;
}
info->fix.line_length = info->var.xres * info->var.bits_per_pixel / 8;
info->fix.smem_len = size;
lcdcon = (info->var.xres * info->var.yres *
info->var.bits_per_pixel) / 128 - 1;
lcdcon |= ((info->var.xres / 16) - 1) << 13;
lcdcon |= (cfb->ac_prescale & 0x1f) << 25;
pps = clk_get_rate(cfb->clk) / (PICOS2KHZ(info->var.pixclock) * 1000);
if (pps)
pps--;
lcdcon |= (pps & 0x3f) << 19;
if (info->var.bits_per_pixel == 4)
lcdcon |= LCDCON_GSMD;
if (info->var.bits_per_pixel >= 2)
lcdcon |= LCDCON_GSEN;
/* LCDCON must only be changed while the LCD is disabled */
regmap_update_bits(cfb->syscon, SYSCON_OFFSET, SYSCON1_LCDEN, 0);
writel(lcdcon, cfb->base + CLPS711X_LCDCON);
regmap_update_bits(cfb->syscon, SYSCON_OFFSET,
SYSCON1_LCDEN, SYSCON1_LCDEN);
return 0;
}
static int clps711x_fb_blank(int blank, struct fb_info *info)
{
/* Return happy */
return 0;
}
static const struct fb_ops clps711x_fb_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = clps711x_fb_setcolreg,
.fb_check_var = clps711x_fb_check_var,
.fb_set_par = clps711x_fb_set_par,
.fb_blank = clps711x_fb_blank,
.fb_fillrect = sys_fillrect,
.fb_copyarea = sys_copyarea,
.fb_imageblit = sys_imageblit,
};
static int clps711x_lcd_check_fb(struct lcd_device *lcddev, struct fb_info *fi)
{
struct clps711x_fb_info *cfb = dev_get_drvdata(&lcddev->dev);
return (!fi || fi->par == cfb) ? 1 : 0;
}
static int clps711x_lcd_get_power(struct lcd_device *lcddev)
{
struct clps711x_fb_info *cfb = dev_get_drvdata(&lcddev->dev);
if (!IS_ERR_OR_NULL(cfb->lcd_pwr))
if (!regulator_is_enabled(cfb->lcd_pwr))
return FB_BLANK_NORMAL;
return FB_BLANK_UNBLANK;
}
static int clps711x_lcd_set_power(struct lcd_device *lcddev, int blank)
{
struct clps711x_fb_info *cfb = dev_get_drvdata(&lcddev->dev);
if (!IS_ERR_OR_NULL(cfb->lcd_pwr)) {
if (blank == FB_BLANK_UNBLANK) {
if (!regulator_is_enabled(cfb->lcd_pwr))
return regulator_enable(cfb->lcd_pwr);
} else {
if (regulator_is_enabled(cfb->lcd_pwr))
return regulator_disable(cfb->lcd_pwr);
}
}
return 0;
}
static struct lcd_ops clps711x_lcd_ops = {
.check_fb = clps711x_lcd_check_fb,
.get_power = clps711x_lcd_get_power,
.set_power = clps711x_lcd_set_power,
};
static int clps711x_fb_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *disp, *np = dev->of_node;
struct clps711x_fb_info *cfb;
struct lcd_device *lcd;
struct fb_info *info;
struct resource *res;
int ret = -ENOENT;
u32 val;
if (fb_get_options(CLPS711X_FB_NAME, NULL))
return -ENODEV;
info = framebuffer_alloc(sizeof(*cfb), dev);
if (!info)
return -ENOMEM;
cfb = info->par;
platform_set_drvdata(pdev, info);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
goto out_fb_release;
cfb->base = devm_ioremap(dev, res->start, resource_size(res));
if (!cfb->base) {
ret = -ENOMEM;
goto out_fb_release;
}
info->fix.mmio_start = res->start;
info->fix.mmio_len = resource_size(res);
info->screen_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
if (IS_ERR(info->screen_base)) {
ret = PTR_ERR(info->screen_base);
goto out_fb_release;
}
/* Physical address should be aligned to 256 MiB */
if (res->start & 0x0fffffff) {
ret = -EINVAL;
goto out_fb_release;
}
cfb->buffsize = resource_size(res);
info->fix.smem_start = res->start;
cfb->clk = devm_clk_get(dev, NULL);
if (IS_ERR(cfb->clk)) {
ret = PTR_ERR(cfb->clk);
goto out_fb_release;
}
cfb->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
if (IS_ERR(cfb->syscon)) {
ret = PTR_ERR(cfb->syscon);
goto out_fb_release;
}
disp = of_parse_phandle(np, "display", 0);
if (!disp) {
dev_err(&pdev->dev, "No display defined\n");
ret = -ENODATA;
goto out_fb_release;
}
ret = of_get_fb_videomode(disp, &cfb->mode, OF_USE_NATIVE_MODE);
if (ret) {
of_node_put(disp);
goto out_fb_release;
}
of_property_read_u32(disp, "ac-prescale", &cfb->ac_prescale);
cfb->cmap_invert = of_property_read_bool(disp, "cmap-invert");
ret = of_property_read_u32(disp, "bits-per-pixel",
&info->var.bits_per_pixel);
of_node_put(disp);
if (ret)
goto out_fb_release;
/* Force disable LCD on any mismatch */
if (info->fix.smem_start != (readb(cfb->base + CLPS711X_FBADDR) << 28))
regmap_update_bits(cfb->syscon, SYSCON_OFFSET,
SYSCON1_LCDEN, 0);
ret = regmap_read(cfb->syscon, SYSCON_OFFSET, &val);
if (ret)
goto out_fb_release;
if (!(val & SYSCON1_LCDEN)) {
/* Setup start FB address */
writeb(info->fix.smem_start >> 28, cfb->base + CLPS711X_FBADDR);
/* Clean FB memory */
memset_io(info->screen_base, 0, cfb->buffsize);
}
cfb->lcd_pwr = devm_regulator_get(dev, "lcd");
if (PTR_ERR(cfb->lcd_pwr) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto out_fb_release;
}
info->fbops = &clps711x_fb_ops;
info->var.activate = FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.accel = FB_ACCEL_NONE;
strscpy(info->fix.id, CLPS711X_FB_NAME, sizeof(info->fix.id));
fb_videomode_to_var(&info->var, &cfb->mode);
ret = fb_alloc_cmap(&info->cmap, BIT(CLPS711X_FB_BPP_MAX), 0);
if (ret)
goto out_fb_release;
ret = fb_set_var(info, &info->var);
if (ret)
goto out_fb_dealloc_cmap;
ret = register_framebuffer(info);
if (ret)
goto out_fb_dealloc_cmap;
lcd = devm_lcd_device_register(dev, "clps711x-lcd", dev, cfb,
&clps711x_lcd_ops);
if (!IS_ERR(lcd))
return 0;
ret = PTR_ERR(lcd);
unregister_framebuffer(info);
out_fb_dealloc_cmap:
regmap_update_bits(cfb->syscon, SYSCON_OFFSET, SYSCON1_LCDEN, 0);
fb_dealloc_cmap(&info->cmap);
out_fb_release:
framebuffer_release(info);
return ret;
}
static void clps711x_fb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct clps711x_fb_info *cfb = info->par;
regmap_update_bits(cfb->syscon, SYSCON_OFFSET, SYSCON1_LCDEN, 0);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
static const struct of_device_id clps711x_fb_dt_ids[] = {
{ .compatible = "cirrus,ep7209-fb", },
{ }
};
MODULE_DEVICE_TABLE(of, clps711x_fb_dt_ids);
static struct platform_driver clps711x_fb_driver = {
.driver = {
.name = CLPS711X_FB_NAME,
.of_match_table = clps711x_fb_dt_ids,
},
.probe = clps711x_fb_probe,
.remove_new = clps711x_fb_remove,
};
module_platform_driver(clps711x_fb_driver);
MODULE_AUTHOR("Alexander Shiyan <[email protected]>");
MODULE_DESCRIPTION("Cirrus Logic CLPS711X FB driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/clps711x-fb.c |
// SPDX-License-Identifier: GPL-2.0
/*
* Framebuffer driver for EFI/UEFI based system
*
* (c) 2006 Edgar Hucek <[email protected]>
* Original efi driver written by Gerd Knorr <[email protected]>
*
*/
#include <linux/aperture.h>
#include <linux/kernel.h>
#include <linux/efi.h>
#include <linux/efi-bgrt.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/printk.h>
#include <linux/screen_info.h>
#include <linux/pm_runtime.h>
#include <video/vga.h>
#include <asm/efi.h>
#include <drm/drm_utils.h> /* For drm_get_panel_orientation_quirk */
#include <drm/drm_connector.h> /* For DRM_MODE_PANEL_ORIENTATION_* */
struct bmp_file_header {
u16 id;
u32 file_size;
u32 reserved;
u32 bitmap_offset;
} __packed;
struct bmp_dib_header {
u32 dib_header_size;
s32 width;
s32 height;
u16 planes;
u16 bpp;
u32 compression;
u32 bitmap_size;
u32 horz_resolution;
u32 vert_resolution;
u32 colors_used;
u32 colors_important;
} __packed;
static bool use_bgrt = true;
static bool request_mem_succeeded = false;
static u64 mem_flags = EFI_MEMORY_WC | EFI_MEMORY_UC;
static struct pci_dev *efifb_pci_dev; /* dev with BAR covering the efifb */
struct efifb_par {
u32 pseudo_palette[16];
resource_size_t base;
resource_size_t size;
};
static struct fb_var_screeninfo efifb_defined = {
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.right_margin = 32,
.upper_margin = 16,
.lower_margin = 4,
.vsync_len = 4,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_fix_screeninfo efifb_fix = {
.id = "EFI VGA",
.type = FB_TYPE_PACKED_PIXELS,
.accel = FB_ACCEL_NONE,
.visual = FB_VISUAL_TRUECOLOR,
};
static int efifb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
/*
* Set a single color register. The values supplied are
* already rounded down to the hardware's capabilities
* (according to the entries in the `var' structure). Return
* != 0 for invalid regno.
*/
if (regno >= info->cmap.len)
return 1;
if (regno < 16) {
red >>= 16 - info->var.red.length;
green >>= 16 - info->var.green.length;
blue >>= 16 - info->var.blue.length;
((u32 *)(info->pseudo_palette))[regno] =
(red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
}
return 0;
}
/*
* If fbcon deffered console takeover is configured, the intent is for the
* framebuffer to show the boot graphics (e.g. vendor logo) until there is some
* (error) message to display. But the boot graphics may have been destroyed by
* e.g. option ROM output, detect this and restore the boot graphics.
*/
#if defined CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER && \
defined CONFIG_ACPI_BGRT
static void efifb_copy_bmp(u8 *src, u32 *dst, int width, struct screen_info *si)
{
u8 r, g, b;
while (width--) {
b = *src++;
g = *src++;
r = *src++;
*dst++ = (r << si->red_pos) |
(g << si->green_pos) |
(b << si->blue_pos);
}
}
#ifdef CONFIG_X86
/*
* On x86 some firmwares use a low non native resolution for the display when
* they have shown some text messages. While keeping the bgrt filled with info
* for the native resolution. If the bgrt image intended for the native
* resolution still fits, it will be displayed very close to the right edge of
* the display looking quite bad. This function checks for this.
*/
static bool efifb_bgrt_sanity_check(struct screen_info *si, u32 bmp_width)
{
/*
* All x86 firmwares horizontally center the image (the yoffset
* calculations differ between boards, but xoffset is predictable).
*/
u32 expected_xoffset = (si->lfb_width - bmp_width) / 2;
return bgrt_tab.image_offset_x == expected_xoffset;
}
#else
static bool efifb_bgrt_sanity_check(struct screen_info *si, u32 bmp_width)
{
return true;
}
#endif
static void efifb_show_boot_graphics(struct fb_info *info)
{
u32 bmp_width, bmp_height, bmp_pitch, dst_x, y, src_y;
struct screen_info *si = &screen_info;
struct bmp_file_header *file_header;
struct bmp_dib_header *dib_header;
void *bgrt_image = NULL;
u8 *dst = info->screen_base;
if (!use_bgrt)
return;
if (!bgrt_tab.image_address) {
pr_info("efifb: No BGRT, not showing boot graphics\n");
return;
}
if (bgrt_tab.status & 0x06) {
pr_info("efifb: BGRT rotation bits set, not showing boot graphics\n");
return;
}
/* Avoid flashing the logo if we're going to print std probe messages */
if (console_loglevel > CONSOLE_LOGLEVEL_QUIET)
return;
/* bgrt_tab.status is unreliable, so we don't check it */
if (si->lfb_depth != 32) {
pr_info("efifb: not 32 bits, not showing boot graphics\n");
return;
}
bgrt_image = memremap(bgrt_tab.image_address, bgrt_image_size,
MEMREMAP_WB);
if (!bgrt_image) {
pr_warn("efifb: Ignoring BGRT: failed to map image memory\n");
return;
}
if (bgrt_image_size < (sizeof(*file_header) + sizeof(*dib_header)))
goto error;
file_header = bgrt_image;
if (file_header->id != 0x4d42 || file_header->reserved != 0)
goto error;
dib_header = bgrt_image + sizeof(*file_header);
if (dib_header->dib_header_size != 40 || dib_header->width < 0 ||
dib_header->planes != 1 || dib_header->bpp != 24 ||
dib_header->compression != 0)
goto error;
bmp_width = dib_header->width;
bmp_height = abs(dib_header->height);
bmp_pitch = round_up(3 * bmp_width, 4);
if ((file_header->bitmap_offset + bmp_pitch * bmp_height) >
bgrt_image_size)
goto error;
if ((bgrt_tab.image_offset_x + bmp_width) > si->lfb_width ||
(bgrt_tab.image_offset_y + bmp_height) > si->lfb_height)
goto error;
if (!efifb_bgrt_sanity_check(si, bmp_width))
goto error;
pr_info("efifb: showing boot graphics\n");
for (y = 0; y < si->lfb_height; y++, dst += si->lfb_linelength) {
/* Only background? */
if (y < bgrt_tab.image_offset_y ||
y >= (bgrt_tab.image_offset_y + bmp_height)) {
memset(dst, 0, 4 * si->lfb_width);
continue;
}
src_y = y - bgrt_tab.image_offset_y;
/* Positive header height means upside down row order */
if (dib_header->height > 0)
src_y = (bmp_height - 1) - src_y;
memset(dst, 0, bgrt_tab.image_offset_x * 4);
dst_x = bgrt_tab.image_offset_x;
efifb_copy_bmp(bgrt_image + file_header->bitmap_offset +
src_y * bmp_pitch,
(u32 *)dst + dst_x, bmp_width, si);
dst_x += bmp_width;
memset((u32 *)dst + dst_x, 0, (si->lfb_width - dst_x) * 4);
}
memunmap(bgrt_image);
return;
error:
memunmap(bgrt_image);
pr_warn("efifb: Ignoring BGRT: unexpected or invalid BMP data\n");
}
#else
static inline void efifb_show_boot_graphics(struct fb_info *info) {}
#endif
/*
* fb_ops.fb_destroy is called by the last put_fb_info() call at the end
* of unregister_framebuffer() or fb_release(). Do any cleanup here.
*/
static void efifb_destroy(struct fb_info *info)
{
struct efifb_par *par = info->par;
if (efifb_pci_dev)
pm_runtime_put(&efifb_pci_dev->dev);
if (info->screen_base) {
if (mem_flags & (EFI_MEMORY_UC | EFI_MEMORY_WC))
iounmap(info->screen_base);
else
memunmap(info->screen_base);
}
if (request_mem_succeeded)
release_mem_region(par->base, par->size);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
static const struct fb_ops efifb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_destroy = efifb_destroy,
.fb_setcolreg = efifb_setcolreg,
};
static int efifb_setup(char *options)
{
char *this_opt;
if (options && *options) {
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt) continue;
efifb_setup_from_dmi(&screen_info, this_opt);
if (!strncmp(this_opt, "base:", 5))
screen_info.lfb_base = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "stride:", 7))
screen_info.lfb_linelength = simple_strtoul(this_opt+7, NULL, 0) * 4;
else if (!strncmp(this_opt, "height:", 7))
screen_info.lfb_height = simple_strtoul(this_opt+7, NULL, 0);
else if (!strncmp(this_opt, "width:", 6))
screen_info.lfb_width = simple_strtoul(this_opt+6, NULL, 0);
else if (!strcmp(this_opt, "nowc"))
mem_flags &= ~EFI_MEMORY_WC;
else if (!strcmp(this_opt, "nobgrt"))
use_bgrt = false;
}
}
return 0;
}
static inline bool fb_base_is_valid(void)
{
if (screen_info.lfb_base)
return true;
if (!(screen_info.capabilities & VIDEO_CAPABILITY_64BIT_BASE))
return false;
if (screen_info.ext_lfb_base)
return true;
return false;
}
#define efifb_attr_decl(name, fmt) \
static ssize_t name##_show(struct device *dev, \
struct device_attribute *attr, \
char *buf) \
{ \
return sprintf(buf, fmt "\n", (screen_info.lfb_##name)); \
} \
static DEVICE_ATTR_RO(name)
efifb_attr_decl(base, "0x%x");
efifb_attr_decl(linelength, "%u");
efifb_attr_decl(height, "%u");
efifb_attr_decl(width, "%u");
efifb_attr_decl(depth, "%u");
static struct attribute *efifb_attrs[] = {
&dev_attr_base.attr,
&dev_attr_linelength.attr,
&dev_attr_width.attr,
&dev_attr_height.attr,
&dev_attr_depth.attr,
NULL
};
ATTRIBUTE_GROUPS(efifb);
static bool pci_dev_disabled; /* FB base matches BAR of a disabled device */
static struct resource *bar_resource;
static u64 bar_offset;
static int efifb_probe(struct platform_device *dev)
{
struct fb_info *info;
struct efifb_par *par;
int err, orientation;
unsigned int size_vmode;
unsigned int size_remap;
unsigned int size_total;
char *option = NULL;
efi_memory_desc_t md;
if (screen_info.orig_video_isVGA != VIDEO_TYPE_EFI || pci_dev_disabled)
return -ENODEV;
if (fb_get_options("efifb", &option))
return -ENODEV;
efifb_setup(option);
/* We don't get linelength from UGA Draw Protocol, only from
* EFI Graphics Protocol. So if it's not in DMI, and it's not
* passed in from the user, we really can't use the framebuffer.
*/
if (!screen_info.lfb_linelength)
return -ENODEV;
if (!screen_info.lfb_depth)
screen_info.lfb_depth = 32;
if (!screen_info.pages)
screen_info.pages = 1;
if (!fb_base_is_valid()) {
printk(KERN_DEBUG "efifb: invalid framebuffer address\n");
return -ENODEV;
}
printk(KERN_INFO "efifb: probing for efifb\n");
/* just assume they're all unset if any are */
if (!screen_info.blue_size) {
screen_info.blue_size = 8;
screen_info.blue_pos = 0;
screen_info.green_size = 8;
screen_info.green_pos = 8;
screen_info.red_size = 8;
screen_info.red_pos = 16;
screen_info.rsvd_size = 8;
screen_info.rsvd_pos = 24;
}
efifb_fix.smem_start = screen_info.lfb_base;
if (screen_info.capabilities & VIDEO_CAPABILITY_64BIT_BASE) {
u64 ext_lfb_base;
ext_lfb_base = (u64)(unsigned long)screen_info.ext_lfb_base << 32;
efifb_fix.smem_start |= ext_lfb_base;
}
if (bar_resource &&
bar_resource->start + bar_offset != efifb_fix.smem_start) {
dev_info(&efifb_pci_dev->dev,
"BAR has moved, updating efifb address\n");
efifb_fix.smem_start = bar_resource->start + bar_offset;
}
efifb_defined.bits_per_pixel = screen_info.lfb_depth;
efifb_defined.xres = screen_info.lfb_width;
efifb_defined.yres = screen_info.lfb_height;
efifb_fix.line_length = screen_info.lfb_linelength;
/* size_vmode -- that is the amount of memory needed for the
* used video mode, i.e. the minimum amount of
* memory we need. */
size_vmode = efifb_defined.yres * efifb_fix.line_length;
/* size_total -- all video memory we have. Used for
* entries, ressource allocation and bounds
* checking. */
size_total = screen_info.lfb_size;
if (size_total < size_vmode)
size_total = size_vmode;
/* size_remap -- the amount of video memory we are going to
* use for efifb. With modern cards it is no
* option to simply use size_total as that
* wastes plenty of kernel address space. */
size_remap = size_vmode * 2;
if (size_remap > size_total)
size_remap = size_total;
if (size_remap % PAGE_SIZE)
size_remap += PAGE_SIZE - (size_remap % PAGE_SIZE);
efifb_fix.smem_len = size_remap;
if (request_mem_region(efifb_fix.smem_start, size_remap, "efifb")) {
request_mem_succeeded = true;
} else {
/* We cannot make this fatal. Sometimes this comes from magic
spaces our resource handlers simply don't know about */
pr_warn("efifb: cannot reserve video memory at 0x%lx\n",
efifb_fix.smem_start);
}
info = framebuffer_alloc(sizeof(*par), &dev->dev);
if (!info) {
err = -ENOMEM;
goto err_release_mem;
}
platform_set_drvdata(dev, info);
par = info->par;
info->pseudo_palette = par->pseudo_palette;
par->base = efifb_fix.smem_start;
par->size = size_remap;
if (efi_enabled(EFI_MEMMAP) &&
!efi_mem_desc_lookup(efifb_fix.smem_start, &md)) {
if ((efifb_fix.smem_start + efifb_fix.smem_len) >
(md.phys_addr + (md.num_pages << EFI_PAGE_SHIFT))) {
pr_err("efifb: video memory @ 0x%lx spans multiple EFI memory regions\n",
efifb_fix.smem_start);
err = -EIO;
goto err_release_fb;
}
/*
* If the UEFI memory map covers the efifb region, we may only
* remap it using the attributes the memory map prescribes.
*/
md.attribute &= EFI_MEMORY_UC | EFI_MEMORY_WC |
EFI_MEMORY_WT | EFI_MEMORY_WB;
if (md.attribute) {
mem_flags |= EFI_MEMORY_WT | EFI_MEMORY_WB;
mem_flags &= md.attribute;
}
}
if (mem_flags & EFI_MEMORY_WC)
info->screen_base = ioremap_wc(efifb_fix.smem_start,
efifb_fix.smem_len);
else if (mem_flags & EFI_MEMORY_UC)
info->screen_base = ioremap(efifb_fix.smem_start,
efifb_fix.smem_len);
else if (mem_flags & EFI_MEMORY_WT)
info->screen_base = memremap(efifb_fix.smem_start,
efifb_fix.smem_len, MEMREMAP_WT);
else if (mem_flags & EFI_MEMORY_WB)
info->screen_base = memremap(efifb_fix.smem_start,
efifb_fix.smem_len, MEMREMAP_WB);
if (!info->screen_base) {
pr_err("efifb: abort, cannot remap video memory 0x%x @ 0x%lx\n",
efifb_fix.smem_len, efifb_fix.smem_start);
err = -EIO;
goto err_release_fb;
}
efifb_show_boot_graphics(info);
pr_info("efifb: framebuffer at 0x%lx, using %dk, total %dk\n",
efifb_fix.smem_start, size_remap/1024, size_total/1024);
pr_info("efifb: mode is %dx%dx%d, linelength=%d, pages=%d\n",
efifb_defined.xres, efifb_defined.yres,
efifb_defined.bits_per_pixel, efifb_fix.line_length,
screen_info.pages);
efifb_defined.xres_virtual = efifb_defined.xres;
efifb_defined.yres_virtual = efifb_fix.smem_len /
efifb_fix.line_length;
pr_info("efifb: scrolling: redraw\n");
efifb_defined.yres_virtual = efifb_defined.yres;
/* some dummy values for timing to make fbset happy */
efifb_defined.pixclock = 10000000 / efifb_defined.xres *
1000 / efifb_defined.yres;
efifb_defined.left_margin = (efifb_defined.xres / 8) & 0xf8;
efifb_defined.hsync_len = (efifb_defined.xres / 8) & 0xf8;
efifb_defined.red.offset = screen_info.red_pos;
efifb_defined.red.length = screen_info.red_size;
efifb_defined.green.offset = screen_info.green_pos;
efifb_defined.green.length = screen_info.green_size;
efifb_defined.blue.offset = screen_info.blue_pos;
efifb_defined.blue.length = screen_info.blue_size;
efifb_defined.transp.offset = screen_info.rsvd_pos;
efifb_defined.transp.length = screen_info.rsvd_size;
pr_info("efifb: %s: "
"size=%d:%d:%d:%d, shift=%d:%d:%d:%d\n",
"Truecolor",
screen_info.rsvd_size,
screen_info.red_size,
screen_info.green_size,
screen_info.blue_size,
screen_info.rsvd_pos,
screen_info.red_pos,
screen_info.green_pos,
screen_info.blue_pos);
efifb_fix.ypanstep = 0;
efifb_fix.ywrapstep = 0;
info->fbops = &efifb_ops;
info->var = efifb_defined;
info->fix = efifb_fix;
orientation = drm_get_panel_orientation_quirk(efifb_defined.xres,
efifb_defined.yres);
switch (orientation) {
default:
info->fbcon_rotate_hint = FB_ROTATE_UR;
break;
case DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP:
info->fbcon_rotate_hint = FB_ROTATE_UD;
break;
case DRM_MODE_PANEL_ORIENTATION_LEFT_UP:
info->fbcon_rotate_hint = FB_ROTATE_CCW;
break;
case DRM_MODE_PANEL_ORIENTATION_RIGHT_UP:
info->fbcon_rotate_hint = FB_ROTATE_CW;
break;
}
err = sysfs_create_groups(&dev->dev.kobj, efifb_groups);
if (err) {
pr_err("efifb: cannot add sysfs attrs\n");
goto err_unmap;
}
err = fb_alloc_cmap(&info->cmap, 256, 0);
if (err < 0) {
pr_err("efifb: cannot allocate colormap\n");
goto err_groups;
}
if (efifb_pci_dev)
WARN_ON(pm_runtime_get_sync(&efifb_pci_dev->dev) < 0);
err = devm_aperture_acquire_for_platform_device(dev, par->base, par->size);
if (err) {
pr_err("efifb: cannot acquire aperture\n");
goto err_put_rpm_ref;
}
err = register_framebuffer(info);
if (err < 0) {
pr_err("efifb: cannot register framebuffer\n");
goto err_put_rpm_ref;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
err_put_rpm_ref:
if (efifb_pci_dev)
pm_runtime_put(&efifb_pci_dev->dev);
fb_dealloc_cmap(&info->cmap);
err_groups:
sysfs_remove_groups(&dev->dev.kobj, efifb_groups);
err_unmap:
if (mem_flags & (EFI_MEMORY_UC | EFI_MEMORY_WC))
iounmap(info->screen_base);
else
memunmap(info->screen_base);
err_release_fb:
framebuffer_release(info);
err_release_mem:
if (request_mem_succeeded)
release_mem_region(efifb_fix.smem_start, size_total);
return err;
}
static void efifb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
/* efifb_destroy takes care of info cleanup */
unregister_framebuffer(info);
sysfs_remove_groups(&pdev->dev.kobj, efifb_groups);
}
static struct platform_driver efifb_driver = {
.driver = {
.name = "efi-framebuffer",
},
.probe = efifb_probe,
.remove_new = efifb_remove,
};
builtin_platform_driver(efifb_driver);
#if defined(CONFIG_PCI)
static void record_efifb_bar_resource(struct pci_dev *dev, int idx, u64 offset)
{
u16 word;
efifb_pci_dev = dev;
pci_read_config_word(dev, PCI_COMMAND, &word);
if (!(word & PCI_COMMAND_MEMORY)) {
pci_dev_disabled = true;
dev_err(&dev->dev,
"BAR %d: assigned to efifb but device is disabled!\n",
idx);
return;
}
bar_resource = &dev->resource[idx];
bar_offset = offset;
dev_info(&dev->dev, "BAR %d: assigned to efifb\n", idx);
}
static void efifb_fixup_resources(struct pci_dev *dev)
{
u64 base = screen_info.lfb_base;
u64 size = screen_info.lfb_size;
int i;
if (efifb_pci_dev || screen_info.orig_video_isVGA != VIDEO_TYPE_EFI)
return;
if (screen_info.capabilities & VIDEO_CAPABILITY_64BIT_BASE)
base |= (u64)screen_info.ext_lfb_base << 32;
if (!base)
return;
for (i = 0; i < PCI_STD_NUM_BARS; i++) {
struct resource *res = &dev->resource[i];
if (!(res->flags & IORESOURCE_MEM))
continue;
if (res->start <= base && res->end >= base + size - 1) {
record_efifb_bar_resource(dev, i, base - res->start);
break;
}
}
}
DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY,
16, efifb_fixup_resources);
#endif
| linux-master | drivers/video/fbdev/efifb.c |
/*
* linux/drivers/video/68328fb.c -- Low level implementation of the
* mc68x328 LCD frame buffer device
*
* Copyright (C) 2003 Georges Menie
*
* This driver assumes an already configured controller (e.g. from config.c)
* Keep the code clean of board specific initialization.
*
* This code has not been tested with colors, colormap management functions
* are minimal (no colormap data written to the 68328 registers...)
*
* initial version of this driver:
* Copyright (C) 1998,1999 Kenneth Albanowski <[email protected]>,
* The Silver Hammer Group, Ltd.
*
* this version is based on :
*
* linux/drivers/video/vfb.c -- Virtual frame buffer device
*
* Copyright (C) 2002 James Simmons
*
* Copyright (C) 1997 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <linux/fb.h>
#include <linux/init.h>
#if defined(CONFIG_M68VZ328)
#include <asm/MC68VZ328.h>
#elif defined(CONFIG_M68EZ328)
#include <asm/MC68EZ328.h>
#elif defined(CONFIG_M68328)
#include <asm/MC68328.h>
#else
#error wrong architecture for the MC68x328 frame buffer device
#endif
static u_long videomemory;
static u_long videomemorysize;
static struct fb_info fb_info;
static u32 mc68x328fb_pseudo_palette[16];
static struct fb_var_screeninfo mc68x328fb_default __initdata = {
.red = { 0, 8, 0 },
.green = { 0, 8, 0 },
.blue = { 0, 8, 0 },
.activate = FB_ACTIVATE_TEST,
.height = -1,
.width = -1,
.pixclock = 20000,
.left_margin = 64,
.right_margin = 64,
.upper_margin = 32,
.lower_margin = 32,
.hsync_len = 64,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED,
};
static const struct fb_fix_screeninfo mc68x328fb_fix __initconst = {
.id = "68328fb",
.type = FB_TYPE_PACKED_PIXELS,
.xpanstep = 1,
.ypanstep = 1,
.ywrapstep = 1,
.accel = FB_ACCEL_NONE,
};
/*
* Interface used by the world
*/
static int mc68x328fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info);
static int mc68x328fb_set_par(struct fb_info *info);
static int mc68x328fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int mc68x328fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info);
static int mc68x328fb_mmap(struct fb_info *info, struct vm_area_struct *vma);
static const struct fb_ops mc68x328fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = mc68x328fb_check_var,
.fb_set_par = mc68x328fb_set_par,
.fb_setcolreg = mc68x328fb_setcolreg,
.fb_pan_display = mc68x328fb_pan_display,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = mc68x328fb_mmap,
};
/*
* Internal routines
*/
static u_long get_line_length(int xres_virtual, int bpp)
{
u_long length;
length = xres_virtual * bpp;
length = (length + 31) & ~31;
length >>= 3;
return (length);
}
/*
* Setting the video mode has been split into two parts.
* First part, xxxfb_check_var, must not write anything
* to hardware, it should only verify and adjust var.
* This means it doesn't alter par but it does use hardware
* data from it to check this var.
*/
static int mc68x328fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
u_long line_length;
/*
* FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
* as FB_VMODE_SMOOTH_XPAN is only used internally
*/
if (var->vmode & FB_VMODE_CONUPDATE) {
var->vmode |= FB_VMODE_YWRAP;
var->xoffset = info->var.xoffset;
var->yoffset = info->var.yoffset;
}
/*
* Some very basic checks
*/
if (!var->xres)
var->xres = 1;
if (!var->yres)
var->yres = 1;
if (var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
if (var->bits_per_pixel <= 1)
var->bits_per_pixel = 1;
else if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel <= 24)
var->bits_per_pixel = 24;
else if (var->bits_per_pixel <= 32)
var->bits_per_pixel = 32;
else
return -EINVAL;
if (var->xres_virtual < var->xoffset + var->xres)
var->xres_virtual = var->xoffset + var->xres;
if (var->yres_virtual < var->yoffset + var->yres)
var->yres_virtual = var->yoffset + var->yres;
/*
* Memory limit
*/
line_length =
get_line_length(var->xres_virtual, var->bits_per_pixel);
if (line_length * var->yres_virtual > videomemorysize)
return -ENOMEM;
/*
* Now that we checked it we alter var. The reason being is that the video
* mode passed in might not work but slight changes to it might make it
* work. This way we let the user know what is acceptable.
*/
switch (var->bits_per_pixel) {
case 1:
var->red.offset = 0;
var->red.length = 1;
var->green.offset = 0;
var->green.length = 1;
var->blue.offset = 0;
var->blue.length = 1;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16: /* RGBA 5551 */
if (var->transp.length) {
var->red.offset = 0;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 10;
var->blue.length = 5;
var->transp.offset = 15;
var->transp.length = 1;
} else { /* RGB 565 */
var->red.offset = 0;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 11;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
}
break;
case 24: /* RGB 888 */
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 32: /* RGBA 8888 */
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
return 0;
}
/* This routine actually sets the video mode. It's in here where we
* the hardware state info->par and fix which can be affected by the
* change in par. For this driver it doesn't do much.
*/
static int mc68x328fb_set_par(struct fb_info *info)
{
info->fix.line_length = get_line_length(info->var.xres_virtual,
info->var.bits_per_pixel);
return 0;
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int mc68x328fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
if (regno >= 256) /* no. of hw registers */
return 1;
/*
* Program hardware... do anything you want with transp
*/
/* grayscale works only partially under directcolor */
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue =
(red * 77 + green * 151 + blue * 28) >> 8;
}
/* Directcolor:
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* {hardwarespecific} contains width of RAMDAC
* cmap[X] is programmed to (X << red.offset) | (X << green.offset) | (X << blue.offset)
* RAMDAC[X] is programmed to (red, green, blue)
*
* Pseudocolor:
* uses offset = 0 && length = RAMDAC register width.
* var->{color}.offset is 0
* var->{color}.length contains width of DAC
* cmap is not used
* RAMDAC[X] is programmed to (red, green, blue)
* Truecolor:
* does not use DAC. Usually 3 are present.
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* cmap is programmed to (red << red.offset) | (green << green.offset) |
* (blue << blue.offset) | (transp << transp.offset)
* RAMDAC does not exist
*/
#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
case FB_VISUAL_PSEUDOCOLOR:
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
transp = CNVT_TOHW(transp, info->var.transp.length);
break;
case FB_VISUAL_DIRECTCOLOR:
red = CNVT_TOHW(red, 8); /* expect 8 bit DAC */
green = CNVT_TOHW(green, 8);
blue = CNVT_TOHW(blue, 8);
/* hey, there is bug in transp handling... */
transp = CNVT_TOHW(transp, 8);
break;
}
#undef CNVT_TOHW
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 v;
if (regno >= 16)
return 1;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
switch (info->var.bits_per_pixel) {
case 8:
break;
case 16:
((u32 *) (info->pseudo_palette))[regno] = v;
break;
case 24:
case 32:
((u32 *) (info->pseudo_palette))[regno] = v;
break;
}
return 0;
}
return 0;
}
/*
* Pan or Wrap the Display
*
* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
*/
static int mc68x328fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if (var->vmode & FB_VMODE_YWRAP) {
if (var->yoffset < 0
|| var->yoffset >= info->var.yres_virtual
|| var->xoffset)
return -EINVAL;
} else {
if (var->xoffset + info->var.xres > info->var.xres_virtual ||
var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
}
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP)
info->var.vmode |= FB_VMODE_YWRAP;
else
info->var.vmode &= ~FB_VMODE_YWRAP;
return 0;
}
/*
* Most drivers don't need their own mmap function
*/
static int mc68x328fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
#ifndef MMU
/* this is uClinux (no MMU) specific code */
vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP);
vma->vm_start = videomemory;
return 0;
#else
return -EINVAL;
#endif
}
static int __init mc68x328fb_setup(char *options)
{
if (!options || !*options)
return 1;
return 1;
}
/*
* Initialisation
*/
static int __init mc68x328fb_init(void)
{
#ifndef MODULE
char *option = NULL;
if (fb_get_options("68328fb", &option))
return -ENODEV;
mc68x328fb_setup(option);
#endif
/*
* initialize the default mode from the LCD controller registers
*/
mc68x328fb_default.xres = LXMAX;
mc68x328fb_default.yres = LYMAX+1;
mc68x328fb_default.xres_virtual = mc68x328fb_default.xres;
mc68x328fb_default.yres_virtual = mc68x328fb_default.yres;
mc68x328fb_default.bits_per_pixel = 1 + (LPICF & 0x01);
videomemory = LSSA;
videomemorysize = (mc68x328fb_default.xres_virtual+7) / 8 *
mc68x328fb_default.yres_virtual * mc68x328fb_default.bits_per_pixel;
fb_info.screen_base = (void *)videomemory;
fb_info.fbops = &mc68x328fb_ops;
fb_info.var = mc68x328fb_default;
fb_info.fix = mc68x328fb_fix;
fb_info.fix.smem_start = videomemory;
fb_info.fix.smem_len = videomemorysize;
fb_info.fix.line_length =
get_line_length(mc68x328fb_default.xres_virtual, mc68x328fb_default.bits_per_pixel);
fb_info.fix.visual = (mc68x328fb_default.bits_per_pixel) == 1 ?
FB_VISUAL_MONO10 : FB_VISUAL_PSEUDOCOLOR;
if (fb_info.var.bits_per_pixel == 1) {
fb_info.var.red.length = fb_info.var.green.length = fb_info.var.blue.length = 1;
fb_info.var.red.offset = fb_info.var.green.offset = fb_info.var.blue.offset = 0;
}
fb_info.pseudo_palette = &mc68x328fb_pseudo_palette;
fb_info.flags = FBINFO_HWACCEL_YPAN;
if (fb_alloc_cmap(&fb_info.cmap, 256, 0))
return -ENOMEM;
if (register_framebuffer(&fb_info) < 0) {
fb_dealloc_cmap(&fb_info.cmap);
return -EINVAL;
}
fb_info(&fb_info, "%s frame buffer device\n", fb_info.fix.id);
fb_info(&fb_info, "%dx%dx%d at 0x%08lx\n",
mc68x328fb_default.xres_virtual,
mc68x328fb_default.yres_virtual,
1 << mc68x328fb_default.bits_per_pixel, videomemory);
return 0;
}
module_init(mc68x328fb_init);
#ifdef MODULE
static void __exit mc68x328fb_cleanup(void)
{
unregister_framebuffer(&fb_info);
fb_dealloc_cmap(&fb_info.cmap);
}
module_exit(mc68x328fb_cleanup);
MODULE_LICENSE("GPL");
#endif /* MODULE */
| linux-master | drivers/video/fbdev/68328fb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/video/pvr2fb.c
*
* Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
* Dreamcast.
*
* Copyright (c) 2001 M. R. Brown <[email protected]>
* Copyright (c) 2001 - 2008 Paul Mundt <[email protected]>
*
* This driver is mostly based on the excellent amifb and vfb sources. It uses
* an odd scheme for converting hardware values to/from framebuffer values,
* here are some hacked-up formulas:
*
* The Dreamcast has screen offsets from each side of its four borders and
* the start offsets of the display window. I used these values to calculate
* 'pseudo' values (think of them as placeholders) for the fb video mode, so
* that when it came time to convert these values back into their hardware
* values, I could just add mode- specific offsets to get the correct mode
* settings:
*
* left_margin = diwstart_h - borderstart_h;
* right_margin = borderstop_h - (diwstart_h + xres);
* upper_margin = diwstart_v - borderstart_v;
* lower_margin = borderstop_v - (diwstart_h + yres);
*
* hsync_len = borderstart_h + (hsync_total - borderstop_h);
* vsync_len = borderstart_v + (vsync_total - borderstop_v);
*
* Then, when it's time to convert back to hardware settings, the only
* constants are the borderstart_* offsets, all other values are derived from
* the fb video mode:
*
* // PAL
* borderstart_h = 116;
* borderstart_v = 44;
* ...
* borderstop_h = borderstart_h + hsync_total - hsync_len;
* ...
* diwstart_v = borderstart_v - upper_margin;
*
* However, in the current implementation, the borderstart values haven't had
* the benefit of being fully researched, so some modes may be broken.
*/
#undef DEBUG
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#ifdef CONFIG_SH_DREAMCAST
#include <asm/machvec.h>
#include <mach-dreamcast/mach/sysasic.h>
#endif
#ifdef CONFIG_PVR2_DMA
#include <linux/pagemap.h>
#include <mach/dma.h>
#include <asm/dma.h>
#endif
#ifdef CONFIG_SH_STORE_QUEUES
#include <linux/uaccess.h>
#include <cpu/sq.h>
#endif
#ifndef PCI_DEVICE_ID_NEC_NEON250
# define PCI_DEVICE_ID_NEC_NEON250 0x0067
#endif
/* 2D video registers */
#define DISP_BASE par->mmio_base
#define DISP_BRDRCOLR (DISP_BASE + 0x40)
#define DISP_DIWMODE (DISP_BASE + 0x44)
#define DISP_DIWADDRL (DISP_BASE + 0x50)
#define DISP_DIWADDRS (DISP_BASE + 0x54)
#define DISP_DIWSIZE (DISP_BASE + 0x5c)
#define DISP_SYNCCONF (DISP_BASE + 0xd0)
#define DISP_BRDRHORZ (DISP_BASE + 0xd4)
#define DISP_SYNCSIZE (DISP_BASE + 0xd8)
#define DISP_BRDRVERT (DISP_BASE + 0xdc)
#define DISP_DIWCONF (DISP_BASE + 0xe8)
#define DISP_DIWHSTRT (DISP_BASE + 0xec)
#define DISP_DIWVSTRT (DISP_BASE + 0xf0)
#define DISP_PIXDEPTH (DISP_BASE + 0x108)
/* Pixel clocks, one for TV output, doubled for VGA output */
#define TV_CLK 74239
#define VGA_CLK 37119
/* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
#define PAL_HTOTAL 863
#define PAL_VTOTAL 312
#define NTSC_HTOTAL 857
#define NTSC_VTOTAL 262
/* Supported cable types */
enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
/* Supported video output types */
enum { VO_PAL, VO_NTSC, VO_VGA };
/* Supported palette types */
enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
struct pvr2_params { unsigned int val; char *name; };
static struct pvr2_params cables[] = {
{ CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
};
static struct pvr2_params outputs[] = {
{ VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
};
/*
* This describes the current video mode
*/
static struct pvr2fb_par {
unsigned int hsync_total; /* Clocks/line */
unsigned int vsync_total; /* Lines/field */
unsigned int borderstart_h;
unsigned int borderstop_h;
unsigned int borderstart_v;
unsigned int borderstop_v;
unsigned int diwstart_h; /* Horizontal offset of the display field */
unsigned int diwstart_v; /* Vertical offset of the display field, for
interlaced modes, this is the long field */
unsigned long disp_start; /* Address of image within VRAM */
unsigned char is_interlaced; /* Is the display interlaced? */
unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
void __iomem *mmio_base; /* MMIO base */
u32 palette[16];
} *currentpar;
static struct fb_info *fb_info;
static struct fb_fix_screeninfo pvr2_fix = {
.id = "NEC PowerVR2",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.ypanstep = 1,
.ywrapstep = 1,
.accel = FB_ACCEL_NONE,
};
static const struct fb_var_screeninfo pvr2_var = {
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel =16,
.red = { 11, 5, 0 },
.green = { 5, 6, 0 },
.blue = { 0, 5, 0 },
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
};
static int cable_type = CT_VGA;
static int video_output = VO_VGA;
static int nopan = 0;
static int nowrap = 1;
/*
* We do all updating, blanking, etc. during the vertical retrace period
*/
static unsigned int do_vmode_full = 0; /* Change the video mode */
static unsigned int do_vmode_pan = 0; /* Update the video mode */
static short do_blank = 0; /* (Un)Blank the screen */
static unsigned int is_blanked = 0; /* Is the screen blanked? */
#ifdef CONFIG_SH_STORE_QUEUES
static unsigned long pvr2fb_map;
#endif
#ifdef CONFIG_PVR2_DMA
static unsigned int shdma = PVR2_CASCADE_CHAN;
static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
#endif
static struct fb_videomode pvr2_modedb[] = {
/*
* Broadcast video modes (PAL and NTSC). I'm unfamiliar with
* PAL-M and PAL-N, but from what I've read both modes parallel PAL and
* NTSC, so it shouldn't be a problem (I hope).
*/
{
/* 640x480 @ 60Hz interlaced (NTSC) */
"ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
}, {
/* 640x240 @ 60Hz (NTSC) */
/* XXX: Broken! Don't use... */
"ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
FB_SYNC_BROADCAST, FB_VMODE_YWRAP
}, {
/* 640x480 @ 60hz (VGA) */
"vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
0, FB_VMODE_YWRAP
},
};
#define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
#define DEFMODE_NTSC 0
#define DEFMODE_PAL 0
#define DEFMODE_VGA 2
static int defmode = DEFMODE_NTSC;
static char *mode_option = NULL;
static inline void pvr2fb_set_pal_type(unsigned int type)
{
struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
fb_writel(type, par->mmio_base + 0x108);
}
static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
unsigned int regno,
unsigned int val)
{
fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
}
static int pvr2fb_blank(int blank, struct fb_info *info)
{
do_blank = blank ? blank : -1;
return 0;
}
static inline unsigned long get_line_length(int xres_virtual, int bpp)
{
return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
}
static void set_color_bitfields(struct fb_var_screeninfo *var)
{
switch (var->bits_per_pixel) {
case 16: /* RGB 565 */
pvr2fb_set_pal_type(PAL_RGB565);
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
var->transp.offset = 0; var->transp.length = 0;
break;
case 24: /* RGB 888 */
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
case 32: /* ARGB 8888 */
pvr2fb_set_pal_type(PAL_ARGB8888);
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 24; var->transp.length = 8;
break;
}
}
static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
unsigned int tmp;
if (regno > info->cmap.len)
return 1;
/*
* We only support the hardware palette for 16 and 32bpp. It's also
* expected that the palette format has been set by the time we get
* here, so we don't waste time setting it again.
*/
switch (info->var.bits_per_pixel) {
case 16: /* RGB 565 */
tmp = (red & 0xf800) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
pvr2fb_set_pal_entry(par, regno, tmp);
break;
case 24: /* RGB 888 */
red >>= 8; green >>= 8; blue >>= 8;
tmp = (red << 16) | (green << 8) | blue;
break;
case 32: /* ARGB 8888 */
red >>= 8; green >>= 8; blue >>= 8;
tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
pvr2fb_set_pal_entry(par, regno, tmp);
break;
default:
pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
return 1;
}
if (regno < 16)
((u32*)(info->pseudo_palette))[regno] = tmp;
return 0;
}
/*
* Determine the cable type and initialize the cable output format. Don't do
* anything if the cable type has been overidden (via "cable:XX").
*/
#define PCTRA ((void __iomem *)0xff80002c)
#define PDTRA ((void __iomem *)0xff800030)
#define VOUTC ((void __iomem *)0xa0702c00)
static int pvr2_init_cable(void)
{
if (cable_type < 0) {
fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
PCTRA);
cable_type = (fb_readw(PDTRA) >> 8) & 3;
}
/* Now select the output format (either composite or other) */
/* XXX: Save the previous val first, as this reg is also AICA
related */
if (cable_type == CT_COMPOSITE)
fb_writel(3 << 8, VOUTC);
else if (cable_type == CT_RGB)
fb_writel(1 << 9, VOUTC);
else
fb_writel(0, VOUTC);
return cable_type;
}
static int pvr2fb_set_par(struct fb_info *info)
{
struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
struct fb_var_screeninfo *var = &info->var;
unsigned long line_length;
unsigned int vtotal;
/*
* XXX: It's possible that a user could use a VGA box, change the cable
* type in hardware (i.e. switch from VGA<->composite), then change
* modes (i.e. switching to another VT). If that happens we should
* automagically change the output format to cope, but currently I
* don't have a VGA box to make sure this works properly.
*/
cable_type = pvr2_init_cable();
if (cable_type == CT_VGA && video_output != VO_VGA)
video_output = VO_VGA;
var->vmode &= FB_VMODE_MASK;
if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
par->is_interlaced = 1;
/*
* XXX: Need to be more creative with this (i.e. allow doublecan for
* PAL/NTSC output).
*/
if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
par->is_doublescan = 1;
par->hsync_total = var->left_margin + var->xres + var->right_margin +
var->hsync_len;
par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
var->vsync_len;
if (var->sync & FB_SYNC_BROADCAST) {
vtotal = par->vsync_total;
if (par->is_interlaced)
vtotal /= 2;
if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
/* XXX: Check for start values here... */
/* XXX: Check hardware for PAL-compatibility */
par->borderstart_h = 116;
par->borderstart_v = 44;
} else {
/* NTSC video output */
par->borderstart_h = 126;
par->borderstart_v = 18;
}
} else {
/* VGA mode */
/* XXX: What else needs to be checked? */
/*
* XXX: We have a little freedom in VGA modes, what ranges
* should be here (i.e. hsync/vsync totals, etc.)?
*/
par->borderstart_h = 126;
par->borderstart_v = 40;
}
/* Calculate the remainding offsets */
par->diwstart_h = par->borderstart_h + var->left_margin;
par->diwstart_v = par->borderstart_v + var->upper_margin;
par->borderstop_h = par->diwstart_h + var->xres +
var->right_margin;
par->borderstop_v = par->diwstart_v + var->yres +
var->lower_margin;
if (!par->is_interlaced)
par->borderstop_v /= 2;
if (info->var.xres < 640)
par->is_lowres = 1;
line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
info->fix.line_length = line_length;
return 0;
}
static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
unsigned int vtotal, hsync_total;
unsigned long line_length;
if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
pr_debug("Invalid pixclock value %d\n", var->pixclock);
return -EINVAL;
}
if (var->xres < 320)
var->xres = 320;
if (var->yres < 240)
var->yres = 240;
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel <= 24)
var->bits_per_pixel = 24;
else if (var->bits_per_pixel <= 32)
var->bits_per_pixel = 32;
set_color_bitfields(var);
if (var->vmode & FB_VMODE_YWRAP) {
if (var->xoffset || var->yoffset >= var->yres_virtual) {
var->xoffset = var->yoffset = 0;
} else {
if (var->xoffset > var->xres_virtual - var->xres ||
var->yoffset > var->yres_virtual - var->yres)
var->xoffset = var->yoffset = 0;
}
} else {
var->xoffset = var->yoffset = 0;
}
/*
* XXX: Need to be more creative with this (i.e. allow doublecan for
* PAL/NTSC output).
*/
if (var->yres < 480 && video_output == VO_VGA)
var->vmode |= FB_VMODE_DOUBLE;
if (video_output != VO_VGA) {
var->sync |= FB_SYNC_BROADCAST;
var->vmode |= FB_VMODE_INTERLACED;
} else {
var->sync &= ~FB_SYNC_BROADCAST;
var->vmode &= ~FB_VMODE_INTERLACED;
var->vmode |= FB_VMODE_NONINTERLACED;
}
if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
var->right_margin = par->borderstop_h -
(par->diwstart_h + var->xres);
var->left_margin = par->diwstart_h - par->borderstart_h;
var->hsync_len = par->borderstart_h +
(par->hsync_total - par->borderstop_h);
var->upper_margin = par->diwstart_v - par->borderstart_v;
var->lower_margin = par->borderstop_v -
(par->diwstart_v + var->yres);
var->vsync_len = par->borderstop_v +
(par->vsync_total - par->borderstop_v);
}
hsync_total = var->left_margin + var->xres + var->right_margin +
var->hsync_len;
vtotal = var->upper_margin + var->yres + var->lower_margin +
var->vsync_len;
if (var->sync & FB_SYNC_BROADCAST) {
if (var->vmode & FB_VMODE_INTERLACED)
vtotal /= 2;
if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
/* PAL video output */
/* XXX: Should be using a range here ... ? */
if (hsync_total != PAL_HTOTAL) {
pr_debug("invalid hsync total for PAL\n");
return -EINVAL;
}
} else {
/* NTSC video output */
if (hsync_total != NTSC_HTOTAL) {
pr_debug("invalid hsync total for NTSC\n");
return -EINVAL;
}
}
}
/* Check memory sizes */
line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
if (line_length * var->yres_virtual > info->fix.smem_len)
return -ENOMEM;
return 0;
}
static void pvr2_update_display(struct fb_info *info)
{
struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
struct fb_var_screeninfo *var = &info->var;
/* Update the start address of the display image */
fb_writel(par->disp_start, DISP_DIWADDRL);
fb_writel(par->disp_start +
get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
DISP_DIWADDRS);
}
/*
* Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
* very stable. It's probably due to the fact that a lot of the 2D video
* registers are still undocumented.
*/
static void pvr2_init_display(struct fb_info *info)
{
struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
struct fb_var_screeninfo *var = &info->var;
unsigned int diw_height, diw_width, diw_modulo = 1;
unsigned int bytesperpixel = var->bits_per_pixel >> 3;
/* hsync and vsync totals */
fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
/* column height, modulo, row width */
/* since we're "panning" within vram, we need to offset things based
* on the offset from the virtual x start to our real gfx. */
if (video_output != VO_VGA && par->is_interlaced)
diw_modulo += info->fix.line_length / 4;
diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
DISP_DIWSIZE);
/* display address, long and short fields */
fb_writel(par->disp_start, DISP_DIWADDRL);
fb_writel(par->disp_start +
get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
DISP_DIWADDRS);
/* border horizontal, border vertical, border color */
fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
fb_writel(0, DISP_BRDRCOLR);
/* display window start position */
fb_writel(par->diwstart_h, DISP_DIWHSTRT);
fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
/* misc. settings */
fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
/* clock doubler (for VGA), scan doubler, display enable */
fb_writel(((video_output == VO_VGA) << 23) |
(par->is_doublescan << 1) | 1, DISP_DIWMODE);
/* bits per pixel */
fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
fb_writel(bytesperpixel << 2, DISP_PIXDEPTH);
/* video enable, color sync, interlace,
* hsync and vsync polarity (currently unused) */
fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
}
/* Simulate blanking by making the border cover the entire screen */
#define BLANK_BIT (1<<3)
static void pvr2_do_blank(void)
{
struct pvr2fb_par *par = currentpar;
unsigned long diwconf;
diwconf = fb_readl(DISP_DIWCONF);
if (do_blank > 0)
fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
else
fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
is_blanked = do_blank > 0 ? do_blank : 0;
}
static irqreturn_t __maybe_unused pvr2fb_interrupt(int irq, void *dev_id)
{
struct fb_info *info = dev_id;
if (do_vmode_pan || do_vmode_full)
pvr2_update_display(info);
if (do_vmode_full)
pvr2_init_display(info);
if (do_vmode_pan)
do_vmode_pan = 0;
if (do_vmode_full)
do_vmode_full = 0;
if (do_blank) {
pvr2_do_blank();
do_blank = 0;
}
return IRQ_HANDLED;
}
#ifdef CONFIG_PVR2_DMA
static ssize_t pvr2fb_write(struct fb_info *info, const char *buf,
size_t count, loff_t *ppos)
{
unsigned long dst, start, end, len;
unsigned int nr_pages;
struct page **pages;
int ret, i;
if (!info->screen_base)
return -ENODEV;
nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
if (!pages)
return -ENOMEM;
ret = pin_user_pages_fast((unsigned long)buf, nr_pages, FOLL_WRITE, pages);
if (ret < nr_pages) {
if (ret < 0) {
/*
* Clamp the unsigned nr_pages to zero so that the
* error handling works. And leave ret at whatever
* -errno value was returned from GUP.
*/
nr_pages = 0;
} else {
nr_pages = ret;
/*
* Use -EINVAL to represent a mildly desperate guess at
* why we got fewer pages (maybe even zero pages) than
* requested.
*/
ret = -EINVAL;
}
goto out_unmap;
}
dma_configure_channel(shdma, 0x12c1);
dst = (unsigned long)fb_info->screen_base + *ppos;
start = (unsigned long)page_address(pages[0]);
end = (unsigned long)page_address(pages[nr_pages]);
len = nr_pages << PAGE_SHIFT;
/* Half-assed contig check */
if (start + len == end) {
/* As we do this in one shot, it's either all or nothing.. */
if ((*ppos + len) > fb_info->fix.smem_len) {
ret = -ENOSPC;
goto out_unmap;
}
dma_write(shdma, start, 0, len);
dma_write(pvr2dma, 0, dst, len);
dma_wait_for_completion(pvr2dma);
goto out;
}
/* Not contiguous, writeout per-page instead.. */
for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
ret = -ENOSPC;
goto out_unmap;
}
dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
dma_write_page(pvr2dma, 0, dst);
dma_wait_for_completion(pvr2dma);
}
out:
*ppos += count;
ret = count;
out_unmap:
unpin_user_pages(pages, nr_pages);
kfree(pages);
return ret;
}
#endif /* CONFIG_PVR2_DMA */
static const struct fb_ops pvr2fb_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = pvr2fb_setcolreg,
.fb_blank = pvr2fb_blank,
.fb_check_var = pvr2fb_check_var,
.fb_set_par = pvr2fb_set_par,
#ifdef CONFIG_PVR2_DMA
.fb_write = pvr2fb_write,
#endif
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
#ifndef MODULE
static int pvr2_get_param_val(const struct pvr2_params *p, const char *s,
int size)
{
int i;
for (i = 0; i < size; i++) {
if (!strncasecmp(p[i].name, s, strlen(s)))
return p[i].val;
}
return -1;
}
#endif
static char *pvr2_get_param_name(const struct pvr2_params *p, int val,
int size)
{
int i;
for (i = 0; i < size; i++) {
if (p[i].val == val)
return p[i].name;
}
return NULL;
}
/**
* pvr2fb_common_init
*
* Common init code for the PVR2 chips.
*
* This mostly takes care of the common aspects of the fb setup and
* registration. It's expected that the board-specific init code has
* already setup pvr2_fix with something meaningful at this point.
*
* Device info reporting is also done here, as well as picking a sane
* default from the modedb. For board-specific modelines, simply define
* a per-board modedb.
*
* Also worth noting is that the cable and video output types are likely
* always going to be VGA for the PCI-based PVR2 boards, but we leave this
* in for flexibility anyways. Who knows, maybe someone has tv-out on a
* PCI-based version of these things ;-)
*/
static int __maybe_unused pvr2fb_common_init(void)
{
struct pvr2fb_par *par = currentpar;
unsigned long modememused, rev;
fb_info->screen_base = ioremap(pvr2_fix.smem_start,
pvr2_fix.smem_len);
if (!fb_info->screen_base) {
printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
goto out_err;
}
par->mmio_base = ioremap(pvr2_fix.mmio_start,
pvr2_fix.mmio_len);
if (!par->mmio_base) {
printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
goto out_err;
}
fb_memset_io(fb_info->screen_base, 0, pvr2_fix.smem_len);
pvr2_fix.ypanstep = nopan ? 0 : 1;
pvr2_fix.ywrapstep = nowrap ? 0 : 1;
fb_info->fbops = &pvr2fb_ops;
fb_info->fix = pvr2_fix;
fb_info->par = currentpar;
fb_info->pseudo_palette = currentpar->palette;
fb_info->flags = FBINFO_HWACCEL_YPAN;
if (video_output == VO_VGA)
defmode = DEFMODE_VGA;
if (!mode_option)
mode_option = "640x480@60";
if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
fb_info->var = pvr2_var;
fb_alloc_cmap(&fb_info->cmap, 256, 0);
if (register_framebuffer(fb_info) < 0)
goto out_err;
/*Must write PIXDEPTH to register before anything is displayed - so force init */
pvr2_init_display(fb_info);
modememused = get_line_length(fb_info->var.xres_virtual,
fb_info->var.bits_per_pixel);
modememused *= fb_info->var.yres_virtual;
rev = fb_readl(par->mmio_base + 0x04);
fb_info(fb_info, "%s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
modememused >> 10,
(unsigned long)(fb_info->fix.smem_len >> 10));
fb_info(fb_info, "Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
fb_info->var.xres, fb_info->var.yres,
fb_info->var.bits_per_pixel,
get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
pvr2_get_param_name(cables, cable_type, 3),
pvr2_get_param_name(outputs, video_output, 3));
#ifdef CONFIG_SH_STORE_QUEUES
fb_notice(fb_info, "registering with SQ API\n");
pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
fb_info->fix.id, PAGE_SHARED);
fb_notice(fb_info, "Mapped video memory to SQ addr 0x%lx\n",
pvr2fb_map);
#endif
return 0;
out_err:
if (fb_info->screen_base)
iounmap(fb_info->screen_base);
if (par->mmio_base)
iounmap(par->mmio_base);
return -ENXIO;
}
#ifdef CONFIG_SH_DREAMCAST
static int __init pvr2fb_dc_init(void)
{
if (!mach_is_dreamcast())
return -ENXIO;
/* Make a guess at the monitor based on the attached cable */
if (pvr2_init_cable() == CT_VGA) {
fb_info->monspecs.hfmin = 30000;
fb_info->monspecs.hfmax = 70000;
fb_info->monspecs.vfmin = 60;
fb_info->monspecs.vfmax = 60;
} else {
/* Not VGA, using a TV (taken from acornfb) */
fb_info->monspecs.hfmin = 15469;
fb_info->monspecs.hfmax = 15781;
fb_info->monspecs.vfmin = 49;
fb_info->monspecs.vfmax = 51;
}
/*
* XXX: This needs to pull default video output via BIOS or other means
*/
if (video_output < 0) {
if (cable_type == CT_VGA) {
video_output = VO_VGA;
} else {
video_output = VO_NTSC;
}
}
/*
* Nothing exciting about the DC PVR2 .. only a measly 8MiB.
*/
pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
pvr2_fix.smem_len = 8 << 20;
pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
pvr2_fix.mmio_len = 0x2000;
if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, IRQF_SHARED,
"pvr2 VBL handler", fb_info)) {
return -EBUSY;
}
#ifdef CONFIG_PVR2_DMA
if (request_dma(pvr2dma, "pvr2") != 0) {
free_irq(HW_EVENT_VSYNC, fb_info);
return -EBUSY;
}
#endif
return pvr2fb_common_init();
}
static void pvr2fb_dc_exit(void)
{
if (fb_info->screen_base) {
iounmap(fb_info->screen_base);
fb_info->screen_base = NULL;
}
if (currentpar->mmio_base) {
iounmap(currentpar->mmio_base);
currentpar->mmio_base = NULL;
}
free_irq(HW_EVENT_VSYNC, fb_info);
#ifdef CONFIG_PVR2_DMA
free_dma(pvr2dma);
#endif
}
#endif /* CONFIG_SH_DREAMCAST */
#ifdef CONFIG_PCI
static int pvr2fb_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int ret;
ret = aperture_remove_conflicting_pci_devices(pdev, "pvrfb");
if (ret)
return ret;
ret = pci_enable_device(pdev);
if (ret) {
printk(KERN_ERR "pvr2fb: PCI enable failed\n");
return ret;
}
ret = pci_request_regions(pdev, "pvr2fb");
if (ret) {
printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
return ret;
}
/*
* Slightly more exciting than the DC PVR2 .. 16MiB!
*/
pvr2_fix.smem_start = pci_resource_start(pdev, 0);
pvr2_fix.smem_len = pci_resource_len(pdev, 0);
pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
fb_info->device = &pdev->dev;
return pvr2fb_common_init();
}
static void pvr2fb_pci_remove(struct pci_dev *pdev)
{
if (fb_info->screen_base) {
iounmap(fb_info->screen_base);
fb_info->screen_base = NULL;
}
if (currentpar->mmio_base) {
iounmap(currentpar->mmio_base);
currentpar->mmio_base = NULL;
}
pci_release_regions(pdev);
}
static const struct pci_device_id pvr2fb_pci_tbl[] = {
{ PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
static struct pci_driver pvr2fb_pci_driver = {
.name = "pvr2fb",
.id_table = pvr2fb_pci_tbl,
.probe = pvr2fb_pci_probe,
.remove = pvr2fb_pci_remove,
};
static int __init pvr2fb_pci_init(void)
{
return pci_register_driver(&pvr2fb_pci_driver);
}
static void pvr2fb_pci_exit(void)
{
pci_unregister_driver(&pvr2fb_pci_driver);
}
#endif /* CONFIG_PCI */
/*
* Parse command arguments. Supported arguments are:
* inverse Use inverse color maps
* cable:composite|rgb|vga Override the video cable type
* output:NTSC|PAL|VGA Override the video output format
*
* <xres>x<yres>[-<bpp>][@<refresh>] or,
* <name>[-<bpp>][@<refresh>] Startup using this video mode
*/
#ifndef MODULE
static int __init pvr2fb_setup(char *options)
{
char *this_opt;
char cable_arg[80];
char output_arg[80];
if (!options || !*options)
return 0;
cable_arg[0] = output_arg[0] = 0;
while ((this_opt = strsep(&options, ","))) {
if (!*this_opt)
continue;
if (!strcmp(this_opt, "inverse")) {
fb_invert_cmaps();
} else if (!strncmp(this_opt, "cable:", 6)) {
strcpy(cable_arg, this_opt + 6);
} else if (!strncmp(this_opt, "output:", 7)) {
strcpy(output_arg, this_opt + 7);
} else if (!strncmp(this_opt, "nopan", 5)) {
nopan = 1;
} else if (!strncmp(this_opt, "nowrap", 6)) {
nowrap = 1;
} else {
mode_option = this_opt;
}
}
if (*cable_arg)
cable_type = pvr2_get_param_val(cables, cable_arg, 3);
if (*output_arg)
video_output = pvr2_get_param_val(outputs, output_arg, 3);
return 0;
}
#endif
static struct pvr2_board {
int (*init)(void);
void (*exit)(void);
char name[16];
} board_driver[] __refdata = {
#ifdef CONFIG_SH_DREAMCAST
{ pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
#endif
#ifdef CONFIG_PCI
{ pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
#endif
{ 0, },
};
static int __init pvr2fb_init(void)
{
int i, ret = -ENODEV;
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("pvr2fb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("pvr2fb", &option))
return -ENODEV;
pvr2fb_setup(option);
#endif
fb_info = framebuffer_alloc(sizeof(struct pvr2fb_par), NULL);
if (!fb_info)
return -ENOMEM;
currentpar = fb_info->par;
for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
struct pvr2_board *pvr_board = board_driver + i;
if (!pvr_board->init)
continue;
ret = pvr_board->init();
if (ret != 0) {
printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
pvr_board->name);
framebuffer_release(fb_info);
break;
}
}
return ret;
}
static void __exit pvr2fb_exit(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(board_driver); i++) {
struct pvr2_board *pvr_board = board_driver + i;
if (pvr_board->exit)
pvr_board->exit();
}
#ifdef CONFIG_SH_STORE_QUEUES
sq_unmap(pvr2fb_map);
#endif
unregister_framebuffer(fb_info);
framebuffer_release(fb_info);
}
module_init(pvr2fb_init);
module_exit(pvr2fb_exit);
MODULE_AUTHOR("Paul Mundt <[email protected]>, M. R. Brown <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/pvr2fb.c |
/*
* Fast C2P (Chunky-to-Planar) Conversion
*
* Copyright (C) 2003-2008 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/string.h>
#include <asm/unaligned.h>
#include "c2p.h"
#include "c2p_core.h"
/*
* Perform a full C2P step on 16 8-bit pixels, stored in 4 32-bit words
* containing
* - 16 8-bit chunky pixels on input
* - permutated planar data (2 planes per 32-bit word) on output
*/
static void c2p_16x8(u32 d[4])
{
transp4(d, 8, 2);
transp4(d, 1, 2);
transp4x(d, 16, 2);
transp4x(d, 2, 2);
transp4(d, 4, 1);
}
/*
* Array containing the permutation indices of the planar data after c2p
*/
static const int perm_c2p_16x8[4] = { 1, 3, 0, 2 };
/*
* Store a full block of iplan2 data after c2p conversion
*/
static inline void store_iplan2(void *dst, u32 bpp, u32 d[4])
{
int i;
for (i = 0; i < bpp/2; i++, dst += 4)
put_unaligned_be32(d[perm_c2p_16x8[i]], dst);
}
/*
* Store a partial block of iplan2 data after c2p conversion
*/
static inline void store_iplan2_masked(void *dst, u32 bpp, u32 d[4], u32 mask)
{
int i;
for (i = 0; i < bpp/2; i++, dst += 4)
put_unaligned_be32(comp(d[perm_c2p_16x8[i]],
get_unaligned_be32(dst), mask),
dst);
}
/*
* c2p_iplan2 - Copy 8-bit chunky image data to an interleaved planar
* frame buffer with 2 bytes of interleave
* @dst: Starting address of the planar frame buffer
* @dx: Horizontal destination offset (in pixels)
* @dy: Vertical destination offset (in pixels)
* @width: Image width (in pixels)
* @height: Image height (in pixels)
* @dst_nextline: Frame buffer offset to the next line (in bytes)
* @src_nextline: Image offset to the next line (in bytes)
* @bpp: Bits per pixel of the planar frame buffer (2, 4, or 8)
*/
void c2p_iplan2(void *dst, const void *src, u32 dx, u32 dy, u32 width,
u32 height, u32 dst_nextline, u32 src_nextline, u32 bpp)
{
union {
u8 pixels[16];
u32 words[4];
} d;
u32 dst_idx, first, last, w;
const u8 *c;
void *p;
dst += dy*dst_nextline+(dx & ~15)*bpp;
dst_idx = dx % 16;
first = 0xffffU >> dst_idx;
first |= first << 16;
last = 0xffffU ^ (0xffffU >> ((dst_idx+width) % 16));
last |= last << 16;
while (height--) {
c = src;
p = dst;
w = width;
if (dst_idx+width <= 16) {
/* Single destination word */
first &= last;
memset(d.pixels, 0, sizeof(d));
memcpy(d.pixels+dst_idx, c, width);
c += width;
c2p_16x8(d.words);
store_iplan2_masked(p, bpp, d.words, first);
p += bpp*2;
} else {
/* Multiple destination words */
w = width;
/* Leading bits */
if (dst_idx) {
w = 16 - dst_idx;
memset(d.pixels, 0, dst_idx);
memcpy(d.pixels+dst_idx, c, w);
c += w;
c2p_16x8(d.words);
store_iplan2_masked(p, bpp, d.words, first);
p += bpp*2;
w = width-w;
}
/* Main chunk */
while (w >= 16) {
memcpy(d.pixels, c, 16);
c += 16;
c2p_16x8(d.words);
store_iplan2(p, bpp, d.words);
p += bpp*2;
w -= 16;
}
/* Trailing bits */
w %= 16;
if (w > 0) {
memcpy(d.pixels, c, w);
memset(d.pixels+w, 0, 16-w);
c2p_16x8(d.words);
store_iplan2_masked(p, bpp, d.words, last);
}
}
src += src_nextline;
dst += dst_nextline;
}
}
EXPORT_SYMBOL_GPL(c2p_iplan2);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/c2p_iplan2.c |
/*
* linux/drivers/video/iplan2p4.c -- Low level frame buffer operations for
* interleaved bitplanes à la Atari (4
* planes, 2 bytes interleave)
*
* Created 5 Apr 1997 by Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/setup.h>
#include "atafb.h"
#define BPL 4
#include "atafb_utils.h"
void atafb_iplan2p4_copyarea(struct fb_info *info, u_long next_line,
int sy, int sx, int dy, int dx,
int height, int width)
{
/* bmove() has to distinguish two major cases: If both, source and
* destination, start at even addresses or both are at odd
* addresses, just the first odd and last even column (if present)
* require special treatment (memmove_col()). The rest between
* then can be copied by normal operations, because all adjacent
* bytes are affected and are to be stored in the same order.
* The pathological case is when the move should go from an odd
* address to an even or vice versa. Since the bytes in the plane
* words must be assembled in new order, it seems wisest to make
* all movements by memmove_col().
*/
u8 *src, *dst;
u32 *s, *d;
int w, l , i, j;
u_int colsize;
u_int upwards = (dy < sy) || (dy == sy && dx < sx);
colsize = height;
if (!((sx ^ dx) & 15)) {
/* odd->odd or even->even */
if (upwards) {
src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL);
if (sx & 15) {
memmove32_col(dst, src, 0xff00ff, height, next_line - BPL * 2);
src += BPL * 2;
dst += BPL * 2;
width -= 8;
}
w = width >> 4;
if (w) {
s = (u32 *)src;
d = (u32 *)dst;
w *= BPL / 2;
l = next_line - w * 4;
for (j = height; j > 0; j--) {
for (i = w; i > 0; i--)
*d++ = *s++;
s = (u32 *)((u8 *)s + l);
d = (u32 *)((u8 *)d + l);
}
}
if (width & 15)
memmove32_col(dst + width / (8 / BPL), src + width / (8 / BPL),
0xff00ff00, height, next_line - BPL * 2);
} else {
src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL);
if ((sx + width) & 15) {
src -= BPL * 2;
dst -= BPL * 2;
memmove32_col(dst, src, 0xff00ff00, colsize, -next_line - BPL * 2);
width -= 8;
}
w = width >> 4;
if (w) {
s = (u32 *)src;
d = (u32 *)dst;
w *= BPL / 2;
l = next_line - w * 4;
for (j = height; j > 0; j--) {
for (i = w; i > 0; i--)
*--d = *--s;
s = (u32 *)((u8 *)s - l);
d = (u32 *)((u8 *)d - l);
}
}
if (sx & 15)
memmove32_col(dst - (width - 16) / (8 / BPL),
src - (width - 16) / (8 / BPL),
0xff00ff, colsize, -next_line - BPL * 2);
}
} else {
/* odd->even or even->odd */
if (upwards) {
u32 *src32, *dst32;
u32 pval[4], v, v1, mask;
int i, j, w, f;
src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL);
mask = 0xff00ff00;
f = 0;
w = width;
if (sx & 15) {
f = 1;
w += 8;
}
if ((sx + width) & 15)
f |= 2;
w >>= 4;
for (i = height; i; i--) {
src32 = (u32 *)src;
dst32 = (u32 *)dst;
if (f & 1) {
pval[0] = (*src32++ << 8) & mask;
pval[1] = (*src32++ << 8) & mask;
} else {
pval[0] = dst32[0] & mask;
pval[1] = dst32[1] & mask;
}
for (j = w; j > 0; j--) {
v = *src32++;
v1 = v & mask;
*dst32++ = pval[0] | (v1 >> 8);
pval[0] = (v ^ v1) << 8;
v = *src32++;
v1 = v & mask;
*dst32++ = pval[1] | (v1 >> 8);
pval[1] = (v ^ v1) << 8;
}
if (f & 2) {
dst32[0] = (dst32[0] & mask) | pval[0];
dst32[1] = (dst32[1] & mask) | pval[1];
}
src += next_line;
dst += next_line;
}
} else {
u32 *src32, *dst32;
u32 pval[4], v, v1, mask;
int i, j, w, f;
src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL);
mask = 0xff00ff;
f = 0;
w = width;
if ((dx + width) & 15)
f = 1;
if (sx & 15) {
f |= 2;
w += 8;
}
w >>= 4;
for (i = height; i; i--) {
src32 = (u32 *)src;
dst32 = (u32 *)dst;
if (f & 1) {
pval[0] = dst32[-1] & mask;
pval[1] = dst32[-2] & mask;
} else {
pval[0] = (*--src32 >> 8) & mask;
pval[1] = (*--src32 >> 8) & mask;
}
for (j = w; j > 0; j--) {
v = *--src32;
v1 = v & mask;
*--dst32 = pval[0] | (v1 << 8);
pval[0] = (v ^ v1) >> 8;
v = *--src32;
v1 = v & mask;
*--dst32 = pval[1] | (v1 << 8);
pval[1] = (v ^ v1) >> 8;
}
if (!(f & 2)) {
dst32[-1] = (dst32[-1] & mask) | pval[0];
dst32[-2] = (dst32[-2] & mask) | pval[1];
}
src -= next_line;
dst -= next_line;
}
}
}
}
void atafb_iplan2p4_fillrect(struct fb_info *info, u_long next_line, u32 color,
int sy, int sx, int height, int width)
{
u32 *dest;
int rows, i;
u32 cval[4];
dest = (u32 *)(info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL));
if (sx & 15) {
u8 *dest8 = (u8 *)dest + 1;
expand8_col2mask(color, cval);
for (i = height; i; i--) {
fill8_col(dest8, cval);
dest8 += next_line;
}
dest += BPL / 2;
width -= 8;
}
expand16_col2mask(color, cval);
rows = width >> 4;
if (rows) {
u32 *d = dest;
u32 off = next_line - rows * BPL * 2;
for (i = height; i; i--) {
d = fill16_col(d, rows, cval);
d = (u32 *)((long)d + off);
}
dest += rows * BPL / 2;
width &= 15;
}
if (width) {
u8 *dest8 = (u8 *)dest;
expand8_col2mask(color, cval);
for (i = height; i; i--) {
fill8_col(dest8, cval);
dest8 += next_line;
}
}
}
void atafb_iplan2p4_linefill(struct fb_info *info, u_long next_line,
int dy, int dx, u32 width,
const u8 *data, u32 bgcolor, u32 fgcolor)
{
u32 *dest;
const u16 *data16;
int rows;
u32 fgm[4], bgm[4], m;
dest = (u32 *)(info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL));
if (dx & 15) {
fill8_2col((u8 *)dest + 1, fgcolor, bgcolor, *data++);
dest += BPL / 2;
width -= 8;
}
if (width >= 16) {
data16 = (const u16 *)data;
expand16_2col2mask(fgcolor, bgcolor, fgm, bgm);
for (rows = width / 16; rows; rows--) {
u16 d = *data16++;
m = d | ((u32)d << 16);
*dest++ = (m & fgm[0]) ^ bgm[0];
*dest++ = (m & fgm[1]) ^ bgm[1];
}
data = (const u8 *)data16;
width &= 15;
}
if (width)
fill8_2col((u8 *)dest, fgcolor, bgcolor, *data);
}
| linux-master | drivers/video/fbdev/atafb_iplan2p4.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* tdfxfb.c
*
* Author: Hannu Mallat <[email protected]>
*
* Copyright © 1999 Hannu Mallat
* All rights reserved
*
* Created : Thu Sep 23 18:17:43 1999, hmallat
* Last modified: Tue Nov 2 21:19:47 1999, hmallat
*
* I2C part copied from the i2c-voodoo3.c driver by:
* Frodo Looijaard <[email protected]>,
* Philip Edelbrock <[email protected]>,
* Ralph Metzler <[email protected]>, and
* Mark D. Studebaker <[email protected]>
*
* Lots of the information here comes from the Daryll Strauss' Banshee
* patches to the XF86 server, and the rest comes from the 3dfx
* Banshee specification. I'm very much indebted to Daryll for his
* work on the X server.
*
* Voodoo3 support was contributed Harold Oga. Lots of additions
* (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
* Kesmarki. Thanks guys!
*
* Voodoo1 and Voodoo2 support aren't relevant to this driver as they
* behave very differently from the Voodoo3/4/5. For anyone wanting to
* use frame buffer on the Voodoo1/2, see the sstfb driver (which is
* located at http://www.sourceforge.net/projects/sstfb).
*
* While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
* I do wish the next version is a bit more complete. Without the XF86
* patches I couldn't have gotten even this far... for instance, the
* extensions to the VGA register set go completely unmentioned in the
* spec! Also, lots of references are made to the 'SST core', but no
* spec is publicly available, AFAIK.
*
* The structure of this driver comes pretty much from the Permedia
* driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
*
* TODO:
* - multihead support (basically need to support an array of fb_infos)
* - support other architectures (PPC, Alpha); does the fact that the VGA
* core can be accessed only thru I/O (not memory mapped) complicate
* things?
*
* Version history:
*
* 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
*
* 0.1.3 (released 1999-11-02) added Attila's panning support, code
* reorg, hwcursor address page size alignment
* (for mmapping both frame buffer and regs),
* and my changes to get rid of hardcoded
* VGA i/o register locations (uses PCI
* configuration info now)
* 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
* improvements
* 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
* 0.1.0 (released 1999-10-06) initial version
*
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <video/tdfx.h>
#define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b)
#define BANSHEE_MAX_PIXCLOCK 270000
#define VOODOO3_MAX_PIXCLOCK 300000
#define VOODOO5_MAX_PIXCLOCK 350000
static const struct fb_fix_screeninfo tdfx_fix = {
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.ypanstep = 1,
.ywrapstep = 1,
.accel = FB_ACCEL_3DFX_BANSHEE
};
static const struct fb_var_screeninfo tdfx_var = {
/* "640x480, 8 bpp @ 60 Hz */
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 1024,
.bits_per_pixel = 8,
.red = {0, 8, 0},
.blue = {0, 8, 0},
.green = {0, 8, 0},
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.accel_flags = FB_ACCELF_TEXT,
.pixclock = 39722,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* PCI driver prototypes
*/
static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id);
static void tdfxfb_remove(struct pci_dev *pdev);
static const struct pci_device_id tdfxfb_id_table[] = {
{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
0xff0000, 0 },
{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
0xff0000, 0 },
{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
0xff0000, 0 },
{ 0, }
};
static struct pci_driver tdfxfb_driver = {
.name = "tdfxfb",
.id_table = tdfxfb_id_table,
.probe = tdfxfb_probe,
.remove = tdfxfb_remove,
};
MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
/*
* Driver data
*/
static int nopan;
static int nowrap = 1; /* not implemented (yet) */
static int hwcursor = 1;
static char *mode_option;
static bool nomtrr;
/* -------------------------------------------------------------------------
* Hardware-specific funcions
* ------------------------------------------------------------------------- */
static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
{
return inb(par->iobase + reg - 0x300);
}
static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
{
outb(val, par->iobase + reg - 0x300);
}
static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
{
vga_outb(par, GRA_I, idx);
wmb();
vga_outb(par, GRA_D, val);
wmb();
}
static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
{
vga_outb(par, SEQ_I, idx);
wmb();
vga_outb(par, SEQ_D, val);
wmb();
}
static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
{
vga_outb(par, SEQ_I, idx);
mb();
return vga_inb(par, SEQ_D);
}
static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
{
vga_outb(par, CRT_I, idx);
wmb();
vga_outb(par, CRT_D, val);
wmb();
}
static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
{
vga_outb(par, CRT_I, idx);
mb();
return vga_inb(par, CRT_D);
}
static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
{
vga_inb(par, IS1_R);
vga_outb(par, ATT_IW, idx);
vga_outb(par, ATT_IW, val);
}
static inline void vga_disable_video(struct tdfx_par *par)
{
unsigned char s;
s = seq_inb(par, 0x01) | 0x20;
seq_outb(par, 0x00, 0x01);
seq_outb(par, 0x01, s);
seq_outb(par, 0x00, 0x03);
}
static inline void vga_enable_video(struct tdfx_par *par)
{
unsigned char s;
s = seq_inb(par, 0x01) & 0xdf;
seq_outb(par, 0x00, 0x01);
seq_outb(par, 0x01, s);
seq_outb(par, 0x00, 0x03);
}
static inline void vga_enable_palette(struct tdfx_par *par)
{
vga_inb(par, IS1_R);
mb();
vga_outb(par, ATT_IW, 0x20);
}
static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
{
return readl(par->regbase_virt + reg);
}
static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
{
writel(val, par->regbase_virt + reg);
}
static inline void banshee_make_room(struct tdfx_par *par, int size)
{
/* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
* won't quit if you ask for more. */
while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
cpu_relax();
}
static int banshee_wait_idle(struct fb_info *info)
{
struct tdfx_par *par = info->par;
int i = 0;
banshee_make_room(par, 1);
tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
do {
if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
i++;
} while (i < 3);
return 0;
}
/*
* Set the color of a palette entry in 8bpp mode
*/
static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
{
banshee_make_room(par, 2);
tdfx_outl(par, DACADDR, regno);
/* read after write makes it working */
tdfx_inl(par, DACADDR);
tdfx_outl(par, DACDATA, c);
}
static u32 do_calc_pll(int freq, int *freq_out)
{
int m, n, k, best_m, best_n, best_k, best_error;
int fref = 14318;
best_error = freq;
best_n = best_m = best_k = 0;
for (k = 3; k >= 0; k--) {
for (m = 63; m >= 0; m--) {
/*
* Estimate value of n that produces target frequency
* with current m and k
*/
int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
/* Search neighborhood of estimated n */
for (n = max(0, n_estimated);
n <= min(255, n_estimated + 1);
n++) {
/*
* Calculate PLL freqency with current m, k and
* estimated n
*/
int f = (fref * (n + 2) / (m + 2)) >> k;
int error = abs(f - freq);
/*
* If this is the closest we've come to the
* target frequency then remember n, m and k
*/
if (error < best_error) {
best_error = error;
best_n = n;
best_m = m;
best_k = k;
}
}
}
}
n = best_n;
m = best_m;
k = best_k;
*freq_out = (fref * (n + 2) / (m + 2)) >> k;
return (n << 8) | (m << 2) | k;
}
static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
{
struct tdfx_par *par = info->par;
int i;
banshee_wait_idle(info);
tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
banshee_make_room(par, 3);
tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
#if 0
tdfx_outl(par, PLLCTRL1, reg->mempll);
tdfx_outl(par, PLLCTRL2, reg->gfxpll);
#endif
tdfx_outl(par, PLLCTRL0, reg->vidpll);
vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
for (i = 0; i < 5; i++)
seq_outb(par, i, reg->seq[i]);
for (i = 0; i < 25; i++)
crt_outb(par, i, reg->crt[i]);
for (i = 0; i < 9; i++)
gra_outb(par, i, reg->gra[i]);
for (i = 0; i < 21; i++)
att_outb(par, i, reg->att[i]);
crt_outb(par, 0x1a, reg->ext[0]);
crt_outb(par, 0x1b, reg->ext[1]);
vga_enable_palette(par);
vga_enable_video(par);
banshee_make_room(par, 9);
tdfx_outl(par, VGAINIT0, reg->vgainit0);
tdfx_outl(par, DACMODE, reg->dacmode);
tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
tdfx_outl(par, VIDDESKSTART, reg->startaddr);
tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
tdfx_outl(par, VGAINIT1, reg->vgainit1);
tdfx_outl(par, MISCINIT0, reg->miscinit0);
banshee_make_room(par, 8);
tdfx_outl(par, SRCBASE, reg->startaddr);
tdfx_outl(par, DSTBASE, reg->startaddr);
tdfx_outl(par, COMMANDEXTRA_2D, 0);
tdfx_outl(par, CLIP0MIN, 0);
tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
tdfx_outl(par, CLIP1MIN, 0);
tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
tdfx_outl(par, SRCXY, 0);
banshee_wait_idle(info);
}
static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
{
u32 draminit0 = tdfx_inl(par, DRAMINIT0);
u32 draminit1 = tdfx_inl(par, DRAMINIT1);
u32 miscinit1;
int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
int chip_size; /* in MB */
int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
/* Banshee/Voodoo3 */
chip_size = 2;
if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE))
chip_size = 1;
} else {
/* Voodoo4/5 */
has_sgram = 0;
chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK;
chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT);
}
/* disable block writes for SDRAM */
miscinit1 = tdfx_inl(par, MISCINIT1);
miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
miscinit1 |= MISCINIT1_CLUT_INV;
banshee_make_room(par, 1);
tdfx_outl(par, MISCINIT1, miscinit1);
return num_chips * chip_size * 1024l * 1024;
}
/* ------------------------------------------------------------------------- */
static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct tdfx_par *par = info->par;
u32 lpitch;
if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
return -EINVAL;
}
if (var->xres != var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
if (var->xoffset) {
DPRINTK("xoffset not supported\n");
return -EINVAL;
}
var->yoffset = 0;
/*
* Banshee doesn't support interlace, but Voodoo4/5 and probably
* Voodoo3 do.
* no direct information about device id now?
* use max_pixclock for this...
*/
if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
(par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
DPRINTK("interlace not supported\n");
return -EINVAL;
}
if (info->monspecs.hfmax && info->monspecs.vfmax &&
info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) {
DPRINTK("mode outside monitor's specs\n");
return -EINVAL;
}
var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
if (var->xres < 320 || var->xres > 2048) {
DPRINTK("width not supported: %u\n", var->xres);
return -EINVAL;
}
if (var->yres < 200 || var->yres > 2048) {
DPRINTK("height not supported: %u\n", var->yres);
return -EINVAL;
}
if (lpitch * var->yres_virtual > info->fix.smem_len) {
var->yres_virtual = info->fix.smem_len / lpitch;
if (var->yres_virtual < var->yres) {
DPRINTK("no memory for screen (%ux%ux%u)\n",
var->xres, var->yres_virtual,
var->bits_per_pixel);
return -EINVAL;
}
}
if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
DPRINTK("pixclock too high (%ldKHz)\n",
PICOS2KHZ(var->pixclock));
return -EINVAL;
}
var->transp.offset = 0;
var->transp.length = 0;
switch (var->bits_per_pixel) {
case 8:
var->red.length = 8;
var->red.offset = 0;
var->green = var->red;
var->blue = var->red;
break;
case 16:
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
break;
case 32:
var->transp.offset = 24;
var->transp.length = 8;
fallthrough;
case 24:
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = 8;
break;
}
var->width = -1;
var->height = -1;
var->accel_flags = FB_ACCELF_TEXT;
DPRINTK("Checking graphics mode at %dx%d depth %d\n",
var->xres, var->yres, var->bits_per_pixel);
return 0;
}
static int tdfxfb_set_par(struct fb_info *info)
{
struct tdfx_par *par = info->par;
u32 hdispend = info->var.xres;
u32 hsyncsta = hdispend + info->var.right_margin;
u32 hsyncend = hsyncsta + info->var.hsync_len;
u32 htotal = hsyncend + info->var.left_margin;
u32 hd, hs, he, ht, hbs, hbe;
u32 vd, vs, ve, vt, vbs, vbe;
struct banshee_reg reg;
int fout, freq;
u32 wd;
u32 cpp = (info->var.bits_per_pixel + 7) >> 3;
memset(®, 0, sizeof(reg));
reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
VIDCFG_CURS_X11 |
((cpp - 1) << VIDCFG_PIXFMT_SHIFT) |
(cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
/* PLL settings */
freq = PICOS2KHZ(info->var.pixclock);
reg.vidcfg &= ~VIDCFG_2X;
if (freq > par->max_pixclock / 2) {
freq = freq > par->max_pixclock ? par->max_pixclock : freq;
reg.dacmode |= DACMODE_2X;
reg.vidcfg |= VIDCFG_2X;
hdispend >>= 1;
hsyncsta >>= 1;
hsyncend >>= 1;
htotal >>= 1;
}
wd = (hdispend >> 3) - 1;
hd = wd;
hs = (hsyncsta >> 3) - 1;
he = (hsyncend >> 3) - 1;
ht = (htotal >> 3) - 1;
hbs = hd;
hbe = ht;
if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
vd = (info->var.yres << 1) - 1;
vs = vd + (info->var.lower_margin << 1);
ve = vs + (info->var.vsync_len << 1);
vt = ve + (info->var.upper_margin << 1) - 1;
reg.screensize = info->var.xres | (info->var.yres << 13);
reg.vidcfg |= VIDCFG_HALF_MODE;
reg.crt[0x09] = 0x80;
} else {
vd = info->var.yres - 1;
vs = vd + info->var.lower_margin;
ve = vs + info->var.vsync_len;
vt = ve + info->var.upper_margin - 1;
reg.screensize = info->var.xres | (info->var.yres << 12);
reg.vidcfg &= ~VIDCFG_HALF_MODE;
}
vbs = vd;
vbe = vt;
/* this is all pretty standard VGA register stuffing */
reg.misc[0x00] = 0x0f |
(info->var.xres < 400 ? 0xa0 :
info->var.xres < 480 ? 0x60 :
info->var.xres < 768 ? 0xe0 : 0x20);
reg.gra[0x05] = 0x40;
reg.gra[0x06] = 0x05;
reg.gra[0x07] = 0x0f;
reg.gra[0x08] = 0xff;
reg.att[0x00] = 0x00;
reg.att[0x01] = 0x01;
reg.att[0x02] = 0x02;
reg.att[0x03] = 0x03;
reg.att[0x04] = 0x04;
reg.att[0x05] = 0x05;
reg.att[0x06] = 0x06;
reg.att[0x07] = 0x07;
reg.att[0x08] = 0x08;
reg.att[0x09] = 0x09;
reg.att[0x0a] = 0x0a;
reg.att[0x0b] = 0x0b;
reg.att[0x0c] = 0x0c;
reg.att[0x0d] = 0x0d;
reg.att[0x0e] = 0x0e;
reg.att[0x0f] = 0x0f;
reg.att[0x10] = 0x41;
reg.att[0x12] = 0x0f;
reg.seq[0x00] = 0x03;
reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
reg.seq[0x02] = 0x0f;
reg.seq[0x03] = 0x00;
reg.seq[0x04] = 0x0e;
reg.crt[0x00] = ht - 4;
reg.crt[0x01] = hd;
reg.crt[0x02] = hbs;
reg.crt[0x03] = 0x80 | (hbe & 0x1f);
reg.crt[0x04] = hs;
reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
reg.crt[0x06] = vt;
reg.crt[0x07] = ((vs & 0x200) >> 2) |
((vd & 0x200) >> 3) |
((vt & 0x200) >> 4) | 0x10 |
((vbs & 0x100) >> 5) |
((vs & 0x100) >> 6) |
((vd & 0x100) >> 7) |
((vt & 0x100) >> 8);
reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
reg.crt[0x10] = vs;
reg.crt[0x11] = (ve & 0x0f) | 0x20;
reg.crt[0x12] = vd;
reg.crt[0x13] = wd;
reg.crt[0x15] = vbs;
reg.crt[0x16] = vbe + 1;
reg.crt[0x17] = 0xc3;
reg.crt[0x18] = 0xff;
/* Banshee's nonvga stuff */
reg.ext[0x00] = (((ht & 0x100) >> 8) |
((hd & 0x100) >> 6) |
((hbs & 0x100) >> 4) |
((hbe & 0x40) >> 1) |
((hs & 0x100) >> 2) |
((he & 0x20) << 2));
reg.ext[0x01] = (((vt & 0x400) >> 10) |
((vd & 0x400) >> 8) |
((vbs & 0x400) >> 6) |
((vbe & 0x400) >> 4));
reg.vgainit0 = VGAINIT0_8BIT_DAC |
VGAINIT0_EXT_ENABLE |
VGAINIT0_WAKEUP_3C3 |
VGAINIT0_ALT_READBACK |
VGAINIT0_EXTSHIFTOUT;
reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
if (hwcursor)
reg.curspataddr = info->fix.smem_len;
reg.cursloc = 0;
reg.cursc0 = 0;
reg.cursc1 = 0xffffff;
reg.stride = info->var.xres * cpp;
reg.startaddr = info->var.yoffset * reg.stride
+ info->var.xoffset * cpp;
reg.vidpll = do_calc_pll(freq, &fout);
#if 0
reg.mempll = do_calc_pll(..., &fout);
reg.gfxpll = do_calc_pll(..., &fout);
#endif
if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
reg.vidcfg |= VIDCFG_INTERLACE;
reg.miscinit0 = tdfx_inl(par, MISCINIT0);
#if defined(__BIG_ENDIAN)
switch (info->var.bits_per_pixel) {
case 8:
case 24:
reg.miscinit0 &= ~(1 << 30);
reg.miscinit0 &= ~(1 << 31);
break;
case 16:
reg.miscinit0 |= (1 << 30);
reg.miscinit0 |= (1 << 31);
break;
case 32:
reg.miscinit0 |= (1 << 30);
reg.miscinit0 &= ~(1 << 31);
break;
}
#endif
do_write_regs(info, ®);
/* Now change fb_fix_screeninfo according to changes in par */
info->fix.line_length = reg.stride;
info->fix.visual = (info->var.bits_per_pixel == 8)
? FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_TRUECOLOR;
DPRINTK("Graphics mode is now set at %dx%d depth %d\n",
info->var.xres, info->var.yres, info->var.bits_per_pixel);
return 0;
}
/* A handy macro shamelessly pinched from matroxfb */
#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct tdfx_par *par = info->par;
u32 rgbcol;
if (regno >= info->cmap.len || regno > 255)
return 1;
/* grayscale works only partially under directcolor */
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
blue = (red * 77 + green * 151 + blue * 28) >> 8;
green = blue;
red = blue;
}
switch (info->fix.visual) {
case FB_VISUAL_PSEUDOCOLOR:
rgbcol = (((u32)red & 0xff00) << 8) |
(((u32)green & 0xff00) << 0) |
(((u32)blue & 0xff00) >> 8);
do_setpalentry(par, regno, rgbcol);
break;
/* Truecolor has no hardware color palettes. */
case FB_VISUAL_TRUECOLOR:
if (regno < 16) {
rgbcol = (CNVT_TOHW(red, info->var.red.length) <<
info->var.red.offset) |
(CNVT_TOHW(green, info->var.green.length) <<
info->var.green.offset) |
(CNVT_TOHW(blue, info->var.blue.length) <<
info->var.blue.offset) |
(CNVT_TOHW(transp, info->var.transp.length) <<
info->var.transp.offset);
par->palette[regno] = rgbcol;
}
break;
default:
DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
break;
}
return 0;
}
/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
static int tdfxfb_blank(int blank, struct fb_info *info)
{
struct tdfx_par *par = info->par;
int vgablank = 1;
u32 dacmode = tdfx_inl(par, DACMODE);
dacmode &= ~(BIT(1) | BIT(3));
switch (blank) {
case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
vgablank = 0;
break;
case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
break;
case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
dacmode |= BIT(3);
break;
case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
dacmode |= BIT(1);
break;
case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
dacmode |= BIT(1) | BIT(3);
break;
}
banshee_make_room(par, 1);
tdfx_outl(par, DACMODE, dacmode);
if (vgablank)
vga_disable_video(par);
else
vga_enable_video(par);
return 0;
}
/*
* Set the starting position of the visible screen to var->yoffset
*/
static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct tdfx_par *par = info->par;
u32 addr = var->yoffset * info->fix.line_length;
if (nopan || var->xoffset)
return -EINVAL;
banshee_make_room(par, 1);
tdfx_outl(par, VIDDESKSTART, addr);
return 0;
}
#ifdef CONFIG_FB_3DFX_ACCEL
/*
* FillRect 2D command (solidfill or invert (via ROP_XOR))
*/
static void tdfxfb_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
struct tdfx_par *par = info->par;
u32 bpp = info->var.bits_per_pixel;
u32 stride = info->fix.line_length;
u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
int tdfx_rop;
u32 dx = rect->dx;
u32 dy = rect->dy;
u32 dstbase = 0;
if (rect->rop == ROP_COPY)
tdfx_rop = TDFX_ROP_COPY;
else
tdfx_rop = TDFX_ROP_XOR;
/* assume always rect->height < 4096 */
if (dy + rect->height > 4095) {
dstbase = stride * dy;
dy = 0;
}
/* assume always rect->width < 4096 */
if (dx + rect->width > 4095) {
dstbase += dx * bpp >> 3;
dx = 0;
}
banshee_make_room(par, 6);
tdfx_outl(par, DSTFORMAT, fmt);
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
tdfx_outl(par, COLORFORE, rect->color);
} else { /* FB_VISUAL_TRUECOLOR */
tdfx_outl(par, COLORFORE, par->palette[rect->color]);
}
tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
tdfx_outl(par, DSTBASE, dstbase);
tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
}
/*
* Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
*/
static void tdfxfb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct tdfx_par *par = info->par;
u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
u32 bpp = info->var.bits_per_pixel;
u32 stride = info->fix.line_length;
u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
u32 dstbase = 0;
u32 srcbase = 0;
/* assume always area->height < 4096 */
if (sy + area->height > 4095) {
srcbase = stride * sy;
sy = 0;
}
/* assume always area->width < 4096 */
if (sx + area->width > 4095) {
srcbase += sx * bpp >> 3;
sx = 0;
}
/* assume always area->height < 4096 */
if (dy + area->height > 4095) {
dstbase = stride * dy;
dy = 0;
}
/* assume always area->width < 4096 */
if (dx + area->width > 4095) {
dstbase += dx * bpp >> 3;
dx = 0;
}
if (area->sx <= area->dx) {
/* -X */
blitcmd |= BIT(14);
sx += area->width - 1;
dx += area->width - 1;
}
if (area->sy <= area->dy) {
/* -Y */
blitcmd |= BIT(15);
sy += area->height - 1;
dy += area->height - 1;
}
banshee_make_room(par, 8);
tdfx_outl(par, SRCFORMAT, fmt);
tdfx_outl(par, DSTFORMAT, fmt);
tdfx_outl(par, COMMAND_2D, blitcmd);
tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
tdfx_outl(par, DSTXY, dx | (dy << 16));
tdfx_outl(par, SRCBASE, srcbase);
tdfx_outl(par, DSTBASE, dstbase);
tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
}
static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct tdfx_par *par = info->par;
int size = image->height * ((image->width * image->depth + 7) >> 3);
int fifo_free;
int i, stride = info->fix.line_length;
u32 bpp = info->var.bits_per_pixel;
u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
u8 *chardata = (u8 *) image->data;
u32 srcfmt;
u32 dx = image->dx;
u32 dy = image->dy;
u32 dstbase = 0;
if (image->depth != 1) {
#ifdef BROKEN_CODE
banshee_make_room(par, 6 + ((size + 3) >> 2));
srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) |
0x400000;
#else
cfb_imageblit(info, image);
#endif
return;
}
banshee_make_room(par, 9);
switch (info->fix.visual) {
case FB_VISUAL_PSEUDOCOLOR:
tdfx_outl(par, COLORFORE, image->fg_color);
tdfx_outl(par, COLORBACK, image->bg_color);
break;
case FB_VISUAL_TRUECOLOR:
default:
tdfx_outl(par, COLORFORE,
par->palette[image->fg_color]);
tdfx_outl(par, COLORBACK,
par->palette[image->bg_color]);
}
#ifdef __BIG_ENDIAN
srcfmt = 0x400000 | BIT(20);
#else
srcfmt = 0x400000;
#endif
/* assume always image->height < 4096 */
if (dy + image->height > 4095) {
dstbase = stride * dy;
dy = 0;
}
/* assume always image->width < 4096 */
if (dx + image->width > 4095) {
dstbase += dx * bpp >> 3;
dx = 0;
}
tdfx_outl(par, DSTBASE, dstbase);
tdfx_outl(par, SRCXY, 0);
tdfx_outl(par, DSTXY, dx | (dy << 16));
tdfx_outl(par, COMMAND_2D,
COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
tdfx_outl(par, SRCFORMAT, srcfmt);
tdfx_outl(par, DSTFORMAT, dstfmt);
tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
/* A count of how many free FIFO entries we've requested.
* When this goes negative, we need to request more. */
fifo_free = 0;
/* Send four bytes at a time of data */
for (i = (size >> 2); i > 0; i--) {
if (--fifo_free < 0) {
fifo_free = 31;
banshee_make_room(par, fifo_free);
}
tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
chardata += 4;
}
/* Send the leftovers now */
banshee_make_room(par, 3);
switch (size % 4) {
case 0:
break;
case 1:
tdfx_outl(par, LAUNCH_2D, *chardata);
break;
case 2:
tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
break;
case 3:
tdfx_outl(par, LAUNCH_2D,
*(u16 *)chardata | (chardata[3] << 24));
break;
}
}
#endif /* CONFIG_FB_3DFX_ACCEL */
static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct tdfx_par *par = info->par;
u32 vidcfg;
if (!hwcursor)
return -EINVAL; /* just to force soft_cursor() call */
/* Too large of a cursor or wrong bpp :-( */
if (cursor->image.width > 64 ||
cursor->image.height > 64 ||
cursor->image.depth > 1)
return -EINVAL;
vidcfg = tdfx_inl(par, VIDPROCCFG);
if (cursor->enable)
tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
else
tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
/*
* If the cursor is not be changed this means either we want the
* current cursor state (if enable is set) or we want to query what
* we can do with the cursor (if enable is not set)
*/
if (!cursor->set)
return 0;
/* fix cursor color - XFree86 forgets to restore it properly */
if (cursor->set & FB_CUR_SETCMAP) {
struct fb_cmap cmap = info->cmap;
u32 bg_idx = cursor->image.bg_color;
u32 fg_idx = cursor->image.fg_color;
unsigned long bg_color, fg_color;
fg_color = (((u32)cmap.red[fg_idx] & 0xff00) << 8) |
(((u32)cmap.green[fg_idx] & 0xff00) << 0) |
(((u32)cmap.blue[fg_idx] & 0xff00) >> 8);
bg_color = (((u32)cmap.red[bg_idx] & 0xff00) << 8) |
(((u32)cmap.green[bg_idx] & 0xff00) << 0) |
(((u32)cmap.blue[bg_idx] & 0xff00) >> 8);
banshee_make_room(par, 2);
tdfx_outl(par, HWCURC0, bg_color);
tdfx_outl(par, HWCURC1, fg_color);
}
if (cursor->set & FB_CUR_SETPOS) {
int x = cursor->image.dx;
int y = cursor->image.dy - info->var.yoffset;
x += 63;
y += 63;
banshee_make_room(par, 1);
tdfx_outl(par, HWCURLOC, (y << 16) + x);
}
if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
/*
* Voodoo 3 and above cards use 2 monochrome cursor patterns.
* The reason is so the card can fetch 8 words at a time
* and are stored on chip for use for the next 8 scanlines.
* This reduces the number of times for access to draw the
* cursor for each screen refresh.
* Each pattern is a bitmap of 64 bit wide and 64 bit high
* (total of 8192 bits or 1024 bytes). The two patterns are
* stored in such a way that pattern 0 always resides in the
* lower half (least significant 64 bits) of a 128 bit word
* and pattern 1 the upper half. If you examine the data of
* the cursor image the graphics card uses then from the
* beginning you see line one of pattern 0, line one of
* pattern 1, line two of pattern 0, line two of pattern 1,
* etc etc. The linear stride for the cursor is always 16 bytes
* (128 bits) which is the maximum cursor width times two for
* the two monochrome patterns.
*/
u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len;
u8 *bitmap = (u8 *)cursor->image.data;
u8 *mask = (u8 *)cursor->mask;
int i;
fb_memset_io(cursorbase, 0, 1024);
for (i = 0; i < cursor->image.height; i++) {
int h = 0;
int j = (cursor->image.width + 7) >> 3;
for (; j > 0; j--) {
u8 data = *mask ^ *bitmap;
if (cursor->rop == ROP_COPY)
data = *mask & *bitmap;
/* Pattern 0. Copy the cursor mask to it */
fb_writeb(*mask, cursorbase + h);
mask++;
/* Pattern 1. Copy the cursor bitmap to it */
fb_writeb(data, cursorbase + h + 8);
bitmap++;
h++;
}
cursorbase += 16;
}
}
return 0;
}
static const struct fb_ops tdfxfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = tdfxfb_check_var,
.fb_set_par = tdfxfb_set_par,
.fb_setcolreg = tdfxfb_setcolreg,
.fb_blank = tdfxfb_blank,
.fb_pan_display = tdfxfb_pan_display,
.fb_sync = banshee_wait_idle,
.fb_cursor = tdfxfb_cursor,
#ifdef CONFIG_FB_3DFX_ACCEL
.fb_fillrect = tdfxfb_fillrect,
.fb_copyarea = tdfxfb_copyarea,
.fb_imageblit = tdfxfb_imageblit,
#else
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
#endif
};
#ifdef CONFIG_FB_3DFX_I2C
/* The voo GPIO registers don't have individual masks for each bit
so we always have to read before writing. */
static void tdfxfb_i2c_setscl(void *data, int val)
{
struct tdfxfb_i2c_chan *chan = data;
struct tdfx_par *par = chan->par;
unsigned int r;
r = tdfx_inl(par, VIDSERPARPORT);
if (val)
r |= I2C_SCL_OUT;
else
r &= ~I2C_SCL_OUT;
tdfx_outl(par, VIDSERPARPORT, r);
tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
}
static void tdfxfb_i2c_setsda(void *data, int val)
{
struct tdfxfb_i2c_chan *chan = data;
struct tdfx_par *par = chan->par;
unsigned int r;
r = tdfx_inl(par, VIDSERPARPORT);
if (val)
r |= I2C_SDA_OUT;
else
r &= ~I2C_SDA_OUT;
tdfx_outl(par, VIDSERPARPORT, r);
tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
}
/* The GPIO pins are open drain, so the pins always remain outputs.
We rely on the i2c-algo-bit routines to set the pins high before
reading the input from other chips. */
static int tdfxfb_i2c_getscl(void *data)
{
struct tdfxfb_i2c_chan *chan = data;
struct tdfx_par *par = chan->par;
return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
}
static int tdfxfb_i2c_getsda(void *data)
{
struct tdfxfb_i2c_chan *chan = data;
struct tdfx_par *par = chan->par;
return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
}
static void tdfxfb_ddc_setscl(void *data, int val)
{
struct tdfxfb_i2c_chan *chan = data;
struct tdfx_par *par = chan->par;
unsigned int r;
r = tdfx_inl(par, VIDSERPARPORT);
if (val)
r |= DDC_SCL_OUT;
else
r &= ~DDC_SCL_OUT;
tdfx_outl(par, VIDSERPARPORT, r);
tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
}
static void tdfxfb_ddc_setsda(void *data, int val)
{
struct tdfxfb_i2c_chan *chan = data;
struct tdfx_par *par = chan->par;
unsigned int r;
r = tdfx_inl(par, VIDSERPARPORT);
if (val)
r |= DDC_SDA_OUT;
else
r &= ~DDC_SDA_OUT;
tdfx_outl(par, VIDSERPARPORT, r);
tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
}
static int tdfxfb_ddc_getscl(void *data)
{
struct tdfxfb_i2c_chan *chan = data;
struct tdfx_par *par = chan->par;
return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
}
static int tdfxfb_ddc_getsda(void *data)
{
struct tdfxfb_i2c_chan *chan = data;
struct tdfx_par *par = chan->par;
return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));
}
static int tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan, const char *name,
struct device *dev)
{
int rc;
strscpy(chan->adapter.name, name, sizeof(chan->adapter.name));
chan->adapter.owner = THIS_MODULE;
chan->adapter.class = I2C_CLASS_DDC;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = dev;
chan->algo.setsda = tdfxfb_ddc_setsda;
chan->algo.setscl = tdfxfb_ddc_setscl;
chan->algo.getsda = tdfxfb_ddc_getsda;
chan->algo.getscl = tdfxfb_ddc_getscl;
chan->algo.udelay = 10;
chan->algo.timeout = msecs_to_jiffies(500);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
DPRINTK("I2C bus %s registered.\n", name);
else
chan->par = NULL;
return rc;
}
static int tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan, const char *name,
struct device *dev)
{
int rc;
strscpy(chan->adapter.name, name, sizeof(chan->adapter.name));
chan->adapter.owner = THIS_MODULE;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = dev;
chan->algo.setsda = tdfxfb_i2c_setsda;
chan->algo.setscl = tdfxfb_i2c_setscl;
chan->algo.getsda = tdfxfb_i2c_getsda;
chan->algo.getscl = tdfxfb_i2c_getscl;
chan->algo.udelay = 10;
chan->algo.timeout = msecs_to_jiffies(500);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
DPRINTK("I2C bus %s registered.\n", name);
else
chan->par = NULL;
return rc;
}
static void tdfxfb_create_i2c_busses(struct fb_info *info)
{
struct tdfx_par *par = info->par;
tdfx_outl(par, VIDINFORMAT, 0x8160);
tdfx_outl(par, VIDSERPARPORT, 0xcffc0020);
par->chan[0].par = par;
par->chan[1].par = par;
tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->device);
tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->device);
}
static void tdfxfb_delete_i2c_busses(struct tdfx_par *par)
{
if (par->chan[0].par)
i2c_del_adapter(&par->chan[0].adapter);
par->chan[0].par = NULL;
if (par->chan[1].par)
i2c_del_adapter(&par->chan[1].adapter);
par->chan[1].par = NULL;
}
static int tdfxfb_probe_i2c_connector(struct tdfx_par *par,
struct fb_monspecs *specs)
{
u8 *edid = NULL;
DPRINTK("Probe DDC Bus\n");
if (par->chan[0].par)
edid = fb_ddc_read(&par->chan[0].adapter);
if (edid) {
fb_edid_to_monspecs(edid, specs);
kfree(edid);
return 0;
}
return 1;
}
#endif /* CONFIG_FB_3DFX_I2C */
/**
* tdfxfb_probe - Device Initializiation
*
* @pdev: PCI Device to initialize
* @id: PCI Device ID
*
* Initializes and allocates resources for PCI device @pdev.
*
*/
static int tdfxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct tdfx_par *default_par;
struct fb_info *info;
int err, lpitch;
struct fb_monspecs *specs;
bool found;
err = aperture_remove_conflicting_pci_devices(pdev, "tdfxfb");
if (err)
return err;
err = pci_enable_device(pdev);
if (err) {
printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err);
return err;
}
info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
if (!info)
return -ENOMEM;
default_par = info->par;
info->fix = tdfx_fix;
/* Configure the default fb_fix_screeninfo first */
switch (pdev->device) {
case PCI_DEVICE_ID_3DFX_BANSHEE:
strcpy(info->fix.id, "3Dfx Banshee");
default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
break;
case PCI_DEVICE_ID_3DFX_VOODOO3:
strcpy(info->fix.id, "3Dfx Voodoo3");
default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
break;
case PCI_DEVICE_ID_3DFX_VOODOO5:
strcpy(info->fix.id, "3Dfx Voodoo5");
default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
break;
}
info->fix.mmio_start = pci_resource_start(pdev, 0);
info->fix.mmio_len = pci_resource_len(pdev, 0);
if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len,
"tdfx regbase")) {
printk(KERN_ERR "tdfxfb: Can't reserve regbase\n");
goto out_err;
}
default_par->regbase_virt =
ioremap(info->fix.mmio_start, info->fix.mmio_len);
if (!default_par->regbase_virt) {
printk(KERN_ERR "fb: Can't remap %s register area.\n",
info->fix.id);
goto out_err_regbase;
}
info->fix.smem_start = pci_resource_start(pdev, 1);
info->fix.smem_len = do_lfb_size(default_par, pdev->device);
if (!info->fix.smem_len) {
printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id);
goto out_err_regbase;
}
if (!request_mem_region(info->fix.smem_start,
pci_resource_len(pdev, 1), "tdfx smem")) {
printk(KERN_ERR "tdfxfb: Can't reserve smem\n");
goto out_err_regbase;
}
info->screen_base = ioremap_wc(info->fix.smem_start,
info->fix.smem_len);
if (!info->screen_base) {
printk(KERN_ERR "fb: Can't remap %s framebuffer.\n",
info->fix.id);
goto out_err_screenbase;
}
default_par->iobase = pci_resource_start(pdev, 2);
if (!request_region(pci_resource_start(pdev, 2),
pci_resource_len(pdev, 2), "tdfx iobase")) {
printk(KERN_ERR "tdfxfb: Can't reserve iobase\n");
goto out_err_screenbase;
}
printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id,
info->fix.smem_len >> 10);
if (!nomtrr)
default_par->wc_cookie= arch_phys_wc_add(info->fix.smem_start,
info->fix.smem_len);
info->fix.ypanstep = nopan ? 0 : 1;
info->fix.ywrapstep = nowrap ? 0 : 1;
info->fbops = &tdfxfb_ops;
info->pseudo_palette = default_par->palette;
info->flags = FBINFO_HWACCEL_YPAN;
#ifdef CONFIG_FB_3DFX_ACCEL
info->flags |= FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_READS_FAST;
#endif
/* reserve 8192 bits for cursor */
/* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */
if (hwcursor)
info->fix.smem_len = (info->fix.smem_len - 1024) &
(PAGE_MASK << 1);
specs = &info->monspecs;
found = false;
info->var.bits_per_pixel = 8;
#ifdef CONFIG_FB_3DFX_I2C
tdfxfb_create_i2c_busses(info);
err = tdfxfb_probe_i2c_connector(default_par, specs);
if (!err) {
if (specs->modedb == NULL)
DPRINTK("Unable to get Mode Database\n");
else {
const struct fb_videomode *m;
fb_videomode_to_modelist(specs->modedb,
specs->modedb_len,
&info->modelist);
m = fb_find_best_display(specs, &info->modelist);
if (m) {
fb_videomode_to_var(&info->var, m);
/* fill all other info->var's fields */
if (tdfxfb_check_var(&info->var, info) < 0)
info->var = tdfx_var;
else
found = true;
}
}
}
#endif
if (!mode_option && !found)
mode_option = "640x480@60";
if (mode_option) {
err = fb_find_mode(&info->var, info, mode_option,
specs->modedb, specs->modedb_len,
NULL, info->var.bits_per_pixel);
if (!err || err == 4)
info->var = tdfx_var;
}
if (found) {
fb_destroy_modedb(specs->modedb);
specs->modedb = NULL;
}
/* maximize virtual vertical length */
lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
info->var.yres_virtual = info->fix.smem_len / lpitch;
if (info->var.yres_virtual < info->var.yres)
goto out_err_iobase;
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
printk(KERN_ERR "tdfxfb: Can't allocate color map\n");
goto out_err_iobase;
}
if (register_framebuffer(info) < 0) {
printk(KERN_ERR "tdfxfb: can't register framebuffer\n");
fb_dealloc_cmap(&info->cmap);
goto out_err_iobase;
}
/*
* Our driver data
*/
pci_set_drvdata(pdev, info);
return 0;
out_err_iobase:
#ifdef CONFIG_FB_3DFX_I2C
tdfxfb_delete_i2c_busses(default_par);
#endif
arch_phys_wc_del(default_par->wc_cookie);
release_region(pci_resource_start(pdev, 2),
pci_resource_len(pdev, 2));
out_err_screenbase:
if (info->screen_base)
iounmap(info->screen_base);
release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1));
out_err_regbase:
/*
* Cleanup after anything that was remapped/allocated.
*/
if (default_par->regbase_virt)
iounmap(default_par->regbase_virt);
release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
out_err:
framebuffer_release(info);
return -ENXIO;
}
#ifndef MODULE
static void __init tdfxfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strcmp(this_opt, "nopan")) {
nopan = 1;
} else if (!strcmp(this_opt, "nowrap")) {
nowrap = 1;
} else if (!strncmp(this_opt, "hwcursor=", 9)) {
hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
} else if (!strncmp(this_opt, "nomtrr", 6)) {
nomtrr = 1;
} else {
mode_option = this_opt;
}
}
}
#endif
/**
* tdfxfb_remove - Device removal
*
* @pdev: PCI Device to cleanup
*
* Releases all resources allocated during the course of the driver's
* lifetime for the PCI device @pdev.
*
*/
static void tdfxfb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct tdfx_par *par = info->par;
unregister_framebuffer(info);
#ifdef CONFIG_FB_3DFX_I2C
tdfxfb_delete_i2c_busses(par);
#endif
arch_phys_wc_del(par->wc_cookie);
iounmap(par->regbase_virt);
iounmap(info->screen_base);
/* Clean up after reserved regions */
release_region(pci_resource_start(pdev, 2),
pci_resource_len(pdev, 2));
release_mem_region(pci_resource_start(pdev, 1),
pci_resource_len(pdev, 1));
release_mem_region(pci_resource_start(pdev, 0),
pci_resource_len(pdev, 0));
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
static int __init tdfxfb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("tdfxfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("tdfxfb", &option))
return -ENODEV;
tdfxfb_setup(option);
#endif
return pci_register_driver(&tdfxfb_driver);
}
static void __exit tdfxfb_exit(void)
{
pci_unregister_driver(&tdfxfb_driver);
}
MODULE_AUTHOR("Hannu Mallat <[email protected]>");
MODULE_DESCRIPTION("3Dfx framebuffer device driver");
MODULE_LICENSE("GPL");
module_param(hwcursor, int, 0644);
MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
"(1=enable, 0=disable, default=1)");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
module_param(nomtrr, bool, 0);
MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)");
module_init(tdfxfb_init);
module_exit(tdfxfb_exit);
| linux-master | drivers/video/fbdev/tdfxfb.c |
/*
* linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
*
* Copyright (C) 1995 Jay Estabrook
* Copyright (C) 1997 Geert Uytterhoeven
* Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
* Copyright (C) 2002 Richard Henderson
* Copyright (C) 2006, 2007 Maciej W. Rozycki
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/aperture.h>
#include <linux/bitrev.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/selection.h>
#include <linux/string.h>
#include <linux/tc.h>
#include <asm/io.h>
#include <video/tgafb.h>
#ifdef CONFIG_TC
#define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
#else
#define TGA_BUS_TC(dev) 0
#endif
/*
* Local functions.
*/
static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
static int tgafb_set_par(struct fb_info *);
static void tgafb_set_pll(struct tga_par *, int);
static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
unsigned, struct fb_info *);
static int tgafb_blank(int, struct fb_info *);
static void tgafb_init_fix(struct fb_info *);
static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
static int tgafb_register(struct device *dev);
static void tgafb_unregister(struct device *dev);
static const char *mode_option;
static const char *mode_option_pci = "640x480@60";
static const char *mode_option_tc = "1280x1024@72";
static struct pci_driver tgafb_pci_driver;
static struct tc_driver tgafb_tc_driver;
/*
* Frame buffer operations
*/
static const struct fb_ops tgafb_ops = {
.owner = THIS_MODULE,
.fb_check_var = tgafb_check_var,
.fb_set_par = tgafb_set_par,
.fb_setcolreg = tgafb_setcolreg,
.fb_blank = tgafb_blank,
.fb_pan_display = tgafb_pan_display,
.fb_fillrect = tgafb_fillrect,
.fb_copyarea = tgafb_copyarea,
.fb_imageblit = tgafb_imageblit,
};
#ifdef CONFIG_PCI
/*
* PCI registration operations
*/
static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
static void tgafb_pci_unregister(struct pci_dev *);
static struct pci_device_id const tgafb_pci_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) },
{ }
};
MODULE_DEVICE_TABLE(pci, tgafb_pci_table);
static struct pci_driver tgafb_pci_driver = {
.name = "tgafb",
.id_table = tgafb_pci_table,
.probe = tgafb_pci_register,
.remove = tgafb_pci_unregister,
};
static int tgafb_pci_register(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int ret;
ret = aperture_remove_conflicting_pci_devices(pdev, "tgafb");
if (ret)
return ret;
return tgafb_register(&pdev->dev);
}
static void tgafb_pci_unregister(struct pci_dev *pdev)
{
tgafb_unregister(&pdev->dev);
}
#endif /* CONFIG_PCI */
#ifdef CONFIG_TC
/*
* TC registration operations
*/
static int tgafb_tc_register(struct device *);
static int tgafb_tc_unregister(struct device *);
static struct tc_device_id const tgafb_tc_table[] = {
{ "DEC ", "PMAGD-AA" },
{ "DEC ", "PMAGD " },
{ }
};
MODULE_DEVICE_TABLE(tc, tgafb_tc_table);
static struct tc_driver tgafb_tc_driver = {
.id_table = tgafb_tc_table,
.driver = {
.name = "tgafb",
.bus = &tc_bus_type,
.probe = tgafb_tc_register,
.remove = tgafb_tc_unregister,
},
};
static int tgafb_tc_register(struct device *dev)
{
int status = tgafb_register(dev);
if (!status)
get_device(dev);
return status;
}
static int tgafb_tc_unregister(struct device *dev)
{
put_device(dev);
tgafb_unregister(dev);
return 0;
}
#endif /* CONFIG_TC */
/**
* tgafb_check_var - Optional function. Validates a var passed in.
* @var: frame buffer variable screen structure
* @info: frame buffer structure that represents a single frame buffer
*/
static int
tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct tga_par *par = (struct tga_par *)info->par;
if (!var->pixclock)
return -EINVAL;
if (par->tga_type == TGA_TYPE_8PLANE) {
if (var->bits_per_pixel != 8)
return -EINVAL;
} else {
if (var->bits_per_pixel != 32)
return -EINVAL;
}
var->red.length = var->green.length = var->blue.length = 8;
if (var->bits_per_pixel == 32) {
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
}
if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
return -EINVAL;
if (var->xres * var->yres * (var->bits_per_pixel >> 3) > info->fix.smem_len)
return -EINVAL;
if (var->nonstd)
return -EINVAL;
if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
return -EINVAL;
if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
return -EINVAL;
/* Some of the acceleration routines assume the line width is
a multiple of 8 bytes. */
if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 8)
return -EINVAL;
return 0;
}
/**
* tgafb_set_par - Optional function. Alters the hardware state.
* @info: frame buffer structure that represents a single frame buffer
*/
static int
tgafb_set_par(struct fb_info *info)
{
static unsigned int const deep_presets[4] = {
0x00004000,
0x0000440d,
0xffffffff,
0x0000441d
};
static unsigned int const rasterop_presets[4] = {
0x00000003,
0x00000303,
0xffffffff,
0x00000303
};
static unsigned int const mode_presets[4] = {
0x00000000,
0x00000300,
0xffffffff,
0x00000300
};
static unsigned int const base_addr_presets[4] = {
0x00000000,
0x00000001,
0xffffffff,
0x00000001
};
struct tga_par *par = (struct tga_par *) info->par;
int tga_bus_pci = dev_is_pci(par->dev);
int tga_bus_tc = TGA_BUS_TC(par->dev);
u32 htimings, vtimings, pll_freq;
u8 tga_type;
int i;
/* Encode video timings. */
htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
| (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
vtimings = (info->var.yres & TGA_VERT_ACTIVE);
htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
htimings |= TGA_HORIZ_POLARITY;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
vtimings |= TGA_VERT_POLARITY;
par->htimings = htimings;
par->vtimings = vtimings;
par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
/* Store other useful values in par. */
par->xres = info->var.xres;
par->yres = info->var.yres;
par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
par->bits_per_pixel = info->var.bits_per_pixel;
info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
tga_type = par->tga_type;
/* First, disable video. */
TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
/* Write the DEEP register. */
while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
continue;
mb();
TGA_WRITE_REG(par, deep_presets[tga_type] |
(par->sync_on_green ? 0x0 : 0x00010000),
TGA_DEEP_REG);
while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
continue;
mb();
/* Write some more registers. */
TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
/* Calculate & write the PLL. */
tgafb_set_pll(par, pll_freq);
/* Write some more registers. */
TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
/* Init video timing regs. */
TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
/* Initialise RAMDAC. */
if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
/* Init BT485 RAMDAC registers. */
BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
BT485_CMD_0);
BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
BT485_WRITE(par, 0x40, BT485_CMD_1);
BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
/* Fill palette registers. */
BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
for (i = 0; i < 256 * 3; i += 4) {
TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
TGA_RAMDAC_REG);
}
} else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
/* Init BT459 RAMDAC registers. */
BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
(par->sync_on_green ? 0xc0 : 0x40));
BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
/* Fill the palette. */
BT459_LOAD_ADDR(par, 0x0000);
TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
for (i = 0; i < 256 * 3; i += 4) {
TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
}
} else { /* 24-plane or 24plusZ */
/* Init BT463 RAMDAC registers. */
BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
(par->sync_on_green ? 0xc0 : 0x40));
BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
/* Fill the palette. */
BT463_LOAD_ADDR(par, 0x0000);
TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
#ifdef CONFIG_HW_CONSOLE
for (i = 0; i < 16; i++) {
int j = color_table[i];
TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
}
for (i = 0; i < 512 * 3; i += 4) {
#else
for (i = 0; i < 528 * 3; i += 4) {
#endif
TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
}
/* Fill window type table after start of vertical retrace. */
while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
continue;
TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
mb();
while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
continue;
TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
for (i = 0; i < 16; i++) {
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
}
}
/* Finally, enable video scan (and pray for the monitor... :-) */
TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
return 0;
}
#define DIFFCHECK(X) \
do { \
if (m <= 0x3f) { \
int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
if (delta < 0) \
delta = -delta; \
if (delta < min_diff) \
min_diff = delta, vm = m, va = a, vr = r; \
} \
} while (0)
static void
tgafb_set_pll(struct tga_par *par, int f)
{
int n, shift, base, min_diff, target;
int r,a,m,vm = 34, va = 1, vr = 30;
for (r = 0 ; r < 12 ; r++)
TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
if (f > TGA_PLL_MAX_FREQ)
f = TGA_PLL_MAX_FREQ;
if (f >= TGA_PLL_MAX_FREQ / 2)
shift = 0;
else if (f >= TGA_PLL_MAX_FREQ / 4)
shift = 1;
else
shift = 2;
TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
for (r = 0 ; r < 10 ; r++)
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
if (f <= 120000) {
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
}
else if (f <= 200000) {
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
}
else {
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
}
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
target = (f << shift) / TGA_PLL_BASE_FREQ;
min_diff = TGA_PLL_MAX_FREQ;
r = 7 / target;
if (!r) r = 1;
base = target * r;
while (base < 449) {
for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
m = ((n + 3) / 7) - 1;
a = 0;
DIFFCHECK((m + 1) * 7);
m++;
DIFFCHECK((m + 1) * 7);
m = (n / 6) - 1;
if ((a = n % 6))
DIFFCHECK(n);
}
r++;
base += target;
}
vr--;
for (r = 0; r < 8; r++)
TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
for (r = 0; r < 8 ; r++)
TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
for (r = 0; r < 7 ; r++)
TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
}
/**
* tgafb_setcolreg - Optional function. Sets a color register.
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*/
static int
tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct tga_par *par = (struct tga_par *) info->par;
int tga_bus_pci = dev_is_pci(par->dev);
int tga_bus_tc = TGA_BUS_TC(par->dev);
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
} else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
BT459_LOAD_ADDR(par, regno);
TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
} else {
if (regno < 16) {
u32 value = (regno << 16) | (regno << 8) | regno;
((u32 *)info->pseudo_palette)[regno] = value;
}
BT463_LOAD_ADDR(par, regno);
TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
}
return 0;
}
/**
* tgafb_blank - Optional function. Blanks the display.
* @blank: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int
tgafb_blank(int blank, struct fb_info *info)
{
struct tga_par *par = (struct tga_par *) info->par;
u32 vhcr, vvcr, vvvr;
unsigned long flags;
local_irq_save(flags);
vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
vvcr = TGA_READ_REG(par, TGA_VERT_REG);
vvvr = TGA_READ_REG(par, TGA_VALID_REG);
vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
if (par->vesa_blanked) {
TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
par->vesa_blanked = 0;
}
TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
break;
case FB_BLANK_NORMAL: /* Normal blanking */
TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
TGA_VALID_REG);
break;
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
par->vesa_blanked = 1;
break;
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
par->vesa_blanked = 1;
break;
case FB_BLANK_POWERDOWN: /* Poweroff */
TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
par->vesa_blanked = 1;
break;
}
local_irq_restore(flags);
return 0;
}
/*
* Acceleration.
*/
static void
tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct tga_par *par = (struct tga_par *) info->par;
u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
unsigned long rincr, line_length, shift, pos, is8bpp;
unsigned long i, j;
const unsigned char *data;
void __iomem *regs_base;
void __iomem *fb_base;
is8bpp = info->var.bits_per_pixel == 8;
dx = image->dx;
dy = image->dy;
width = image->width;
height = image->height;
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
line_length = info->fix.line_length;
rincr = (width + 7) / 8;
/* A shift below cannot cope with. */
if (unlikely(width == 0))
return;
/* Crop the image to the screen. */
if (dx > vxres || dy > vyres)
return;
if (dx + width > vxres)
width = vxres - dx;
if (dy + height > vyres)
height = vyres - dy;
regs_base = par->tga_regs_base;
fb_base = par->tga_fb_base;
/* Expand the color values to fill 32-bits. */
/* ??? Would be nice to notice colour changes elsewhere, so
that we can do this only when necessary. */
fgcolor = image->fg_color;
bgcolor = image->bg_color;
if (is8bpp) {
fgcolor |= fgcolor << 8;
fgcolor |= fgcolor << 16;
bgcolor |= bgcolor << 8;
bgcolor |= bgcolor << 16;
} else {
if (fgcolor < 16)
fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
if (bgcolor < 16)
bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
}
__raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
__raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
/* Acquire proper alignment; set up the PIXELMASK register
so that we only write the proper character cell. */
pos = dy * line_length;
if (is8bpp) {
pos += dx;
shift = pos & 3;
pos &= -4;
} else {
pos += dx * 4;
shift = (pos & 7) >> 2;
pos &= -8;
}
data = (const unsigned char *) image->data;
/* Enable opaque stipple mode. */
__raw_writel((is8bpp
? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
: TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
regs_base + TGA_MODE_REG);
if (width + shift <= 32) {
unsigned long bwidth;
/* Handle common case of imaging a single character, in
a font less than or 32 pixels wide. */
/* Avoid a shift by 32; width > 0 implied. */
pixelmask = (2ul << (width - 1)) - 1;
pixelmask <<= shift;
__raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
wmb();
bwidth = (width + 7) / 8;
for (i = 0; i < height; ++i) {
u32 mask = 0;
/* The image data is bit big endian; we need
little endian. */
for (j = 0; j < bwidth; ++j)
mask |= bitrev8(data[j]) << (j * 8);
__raw_writel(mask << shift, fb_base + pos);
pos += line_length;
data += rincr;
}
wmb();
__raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
} else if (shift == 0) {
unsigned long pos0 = pos;
const unsigned char *data0 = data;
unsigned long bincr = (is8bpp ? 8 : 8*4);
unsigned long bwidth;
/* Handle another common case in which accel_putcs
generates a large bitmap, which happens to be aligned.
Allow the tail to be misaligned. This case is
interesting because we've not got to hold partial
bytes across the words being written. */
wmb();
bwidth = (width / 8) & -4;
for (i = 0; i < height; ++i) {
for (j = 0; j < bwidth; j += 4) {
u32 mask = 0;
mask |= bitrev8(data[j+0]) << (0 * 8);
mask |= bitrev8(data[j+1]) << (1 * 8);
mask |= bitrev8(data[j+2]) << (2 * 8);
mask |= bitrev8(data[j+3]) << (3 * 8);
__raw_writel(mask, fb_base + pos + j*bincr);
}
pos += line_length;
data += rincr;
}
wmb();
pixelmask = (1ul << (width & 31)) - 1;
if (pixelmask) {
__raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
wmb();
pos = pos0 + bwidth*bincr;
data = data0 + bwidth;
bwidth = ((width & 31) + 7) / 8;
for (i = 0; i < height; ++i) {
u32 mask = 0;
for (j = 0; j < bwidth; ++j)
mask |= bitrev8(data[j]) << (j * 8);
__raw_writel(mask, fb_base + pos);
pos += line_length;
data += rincr;
}
wmb();
__raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
}
} else {
unsigned long pos0 = pos;
const unsigned char *data0 = data;
unsigned long bincr = (is8bpp ? 8 : 8*4);
unsigned long bwidth;
/* Finally, handle the generic case of misaligned start.
Here we split the write into 16-bit spans. This allows
us to use only one pixel mask, instead of four as would
be required by writing 24-bit spans. */
pixelmask = 0xffff << shift;
__raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
wmb();
bwidth = (width / 8) & -2;
for (i = 0; i < height; ++i) {
for (j = 0; j < bwidth; j += 2) {
u32 mask = 0;
mask |= bitrev8(data[j+0]) << (0 * 8);
mask |= bitrev8(data[j+1]) << (1 * 8);
mask <<= shift;
__raw_writel(mask, fb_base + pos + j*bincr);
}
pos += line_length;
data += rincr;
}
wmb();
pixelmask = ((1ul << (width & 15)) - 1) << shift;
if (pixelmask) {
__raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
wmb();
pos = pos0 + bwidth*bincr;
data = data0 + bwidth;
bwidth = (width & 15) > 8;
for (i = 0; i < height; ++i) {
u32 mask = bitrev8(data[0]);
if (bwidth)
mask |= bitrev8(data[1]) << 8;
mask <<= shift;
__raw_writel(mask, fb_base + pos);
pos += line_length;
data += rincr;
}
wmb();
}
__raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
}
/* Disable opaque stipple mode. */
__raw_writel((is8bpp
? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
: TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
regs_base + TGA_MODE_REG);
}
static void
tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct tga_par *par = (struct tga_par *) info->par;
u32 color, dx, dy, width, height, vxres, vyres;
u32 *palette = ((u32 *)info->pseudo_palette);
unsigned long pos, line_length, i, j;
const unsigned char *data;
void __iomem *fb_base;
dx = image->dx;
dy = image->dy;
width = image->width;
height = image->height;
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
line_length = info->fix.line_length;
/* Crop the image to the screen. */
if (dx > vxres || dy > vyres)
return;
if (dx + width > vxres)
width = vxres - dx;
if (dy + height > vyres)
height = vyres - dy;
fb_base = par->tga_fb_base;
pos = dy * line_length + (dx * 4);
data = image->data;
/* Now copy the image, color_expanding via the palette. */
for (i = 0; i < height; i++) {
for (j = 0; j < width; j++) {
color = palette[*data++];
__raw_writel(color, fb_base + pos + j*4);
}
pos += line_length;
}
}
/**
* tgafb_imageblit - REQUIRED function. Can use generic routines if
* non acclerated hardware and packed pixel based.
* Copies a image from system memory to the screen.
*
* @info: frame buffer structure that represents a single frame buffer
* @image: structure defining the image.
*/
static void
tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
{
unsigned int is8bpp = info->var.bits_per_pixel == 8;
/* If a mono image, regardless of FB depth, go do it. */
if (image->depth == 1) {
tgafb_mono_imageblit(info, image);
return;
}
/* For copies that aren't pixel expansion, there's little we
can do better than the generic code. */
/* ??? There is a DMA write mode; I wonder if that could be
made to pull the data from the image buffer... */
if (image->depth == info->var.bits_per_pixel) {
cfb_imageblit(info, image);
return;
}
/* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
if (!is8bpp && image->depth == 8) {
tgafb_clut_imageblit(info, image);
return;
}
/* Silently return... */
}
/**
* tgafb_fillrect - REQUIRED function. Can use generic routines if
* non acclerated hardware and packed pixel based.
* Draws a rectangle on the screen.
*
* @info: frame buffer structure that represents a single frame buffer
* @rect: structure defining the rectagle and operation.
*/
static void
tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct tga_par *par = (struct tga_par *) info->par;
int is8bpp = info->var.bits_per_pixel == 8;
u32 dx, dy, width, height, vxres, vyres, color;
unsigned long pos, align, line_length, i, j;
void __iomem *regs_base;
void __iomem *fb_base;
dx = rect->dx;
dy = rect->dy;
width = rect->width;
height = rect->height;
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
line_length = info->fix.line_length;
regs_base = par->tga_regs_base;
fb_base = par->tga_fb_base;
/* Crop the rectangle to the screen. */
if (dx > vxres || dy > vyres || !width || !height)
return;
if (dx + width > vxres)
width = vxres - dx;
if (dy + height > vyres)
height = vyres - dy;
pos = dy * line_length + dx * (is8bpp ? 1 : 4);
/* ??? We could implement ROP_XOR with opaque fill mode
and a RasterOp setting of GXxor, but as far as I can
tell, this mode is not actually used in the kernel.
Thus I am ignoring it for now. */
if (rect->rop != ROP_COPY) {
cfb_fillrect(info, rect);
return;
}
/* Expand the color value to fill 8 pixels. */
color = rect->color;
if (is8bpp) {
color |= color << 8;
color |= color << 16;
__raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
__raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
} else {
if (color < 16)
color = ((u32 *)info->pseudo_palette)[color];
__raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
__raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
__raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
__raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
__raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
__raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
__raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
__raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
}
/* The DATA register holds the fill mask for block fill mode.
Since we're not stippling, this is all ones. */
__raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
/* Enable block fill mode. */
__raw_writel((is8bpp
? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
: TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
regs_base + TGA_MODE_REG);
wmb();
/* We can fill 2k pixels per operation. Notice blocks that fit
the width of the screen so that we can take advantage of this
and fill more than one line per write. */
if (width == line_length) {
width *= height;
height = 1;
}
/* The write into the frame buffer must be aligned to 4 bytes,
but we are allowed to encode the offset within the word in
the data word written. */
align = (pos & 3) << 16;
pos &= -4;
if (width <= 2048) {
u32 data;
data = (width - 1) | align;
for (i = 0; i < height; ++i) {
__raw_writel(data, fb_base + pos);
pos += line_length;
}
} else {
unsigned long Bpp = (is8bpp ? 1 : 4);
unsigned long nwidth = width & -2048;
u32 fdata, ldata;
fdata = (2048 - 1) | align;
ldata = ((width & 2047) - 1) | align;
for (i = 0; i < height; ++i) {
for (j = 0; j < nwidth; j += 2048)
__raw_writel(fdata, fb_base + pos + j*Bpp);
if (j < width)
__raw_writel(ldata, fb_base + pos + j*Bpp);
pos += line_length;
}
}
wmb();
/* Disable block fill mode. */
__raw_writel((is8bpp
? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
: TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
regs_base + TGA_MODE_REG);
}
/*
* tgafb_copyarea - REQUIRED function. Can use generic routines if
* non acclerated hardware and packed pixel based.
* Copies on area of the screen to another area.
*
* @info: frame buffer structure that represents a single frame buffer
* @area: structure defining the source and destination.
*/
/* Handle the special case of copying entire lines, e.g. during scrolling.
We can avoid a lot of needless computation in this case. In the 8bpp
case we need to use the COPY64 registers instead of mask writes into
the frame buffer to achieve maximum performance. */
static inline void
copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
u32 height, u32 width)
{
struct tga_par *par = (struct tga_par *) info->par;
void __iomem *tga_regs = par->tga_regs_base;
unsigned long dpos, spos, i, n64;
/* Set up the MODE and PIXELSHIFT registers. */
__raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
__raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
wmb();
n64 = (height * width) / 64;
if (sy < dy) {
spos = (sy + height) * width;
dpos = (dy + height) * width;
for (i = 0; i < n64; ++i) {
spos -= 64;
dpos -= 64;
__raw_writel(spos, tga_regs+TGA_COPY64_SRC);
wmb();
__raw_writel(dpos, tga_regs+TGA_COPY64_DST);
wmb();
}
} else {
spos = sy * width;
dpos = dy * width;
for (i = 0; i < n64; ++i) {
__raw_writel(spos, tga_regs+TGA_COPY64_SRC);
wmb();
__raw_writel(dpos, tga_regs+TGA_COPY64_DST);
wmb();
spos += 64;
dpos += 64;
}
}
/* Reset the MODE register to normal. */
__raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
}
static inline void
copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
u32 height, u32 width)
{
struct tga_par *par = (struct tga_par *) info->par;
void __iomem *tga_regs = par->tga_regs_base;
void __iomem *tga_fb = par->tga_fb_base;
void __iomem *src;
void __iomem *dst;
unsigned long i, n16;
/* Set up the MODE and PIXELSHIFT registers. */
__raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
__raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
wmb();
n16 = (height * width) / 16;
if (sy < dy) {
src = tga_fb + (sy + height) * width * 4;
dst = tga_fb + (dy + height) * width * 4;
for (i = 0; i < n16; ++i) {
src -= 64;
dst -= 64;
__raw_writel(0xffff, src);
wmb();
__raw_writel(0xffff, dst);
wmb();
}
} else {
src = tga_fb + sy * width * 4;
dst = tga_fb + dy * width * 4;
for (i = 0; i < n16; ++i) {
__raw_writel(0xffff, src);
wmb();
__raw_writel(0xffff, dst);
wmb();
src += 64;
dst += 64;
}
}
/* Reset the MODE register to normal. */
__raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
}
/* The (almost) general case of backward copy in 8bpp mode. */
static inline void
copyarea_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
u32 height, u32 width, u32 line_length,
const struct fb_copyarea *area)
{
struct tga_par *par = (struct tga_par *) info->par;
unsigned i, yincr;
int depos, sepos, backward, last_step, step;
u32 mask_last;
unsigned n32;
void __iomem *tga_regs;
void __iomem *tga_fb;
/* Do acceleration only if we are aligned on 8 pixels */
if ((dx | sx | width) & 7) {
cfb_copyarea(info, area);
return;
}
yincr = line_length;
if (dy > sy) {
dy += height - 1;
sy += height - 1;
yincr = -yincr;
}
backward = dy == sy && dx > sx && dx < sx + width;
/* Compute the offsets and alignments in the frame buffer.
More than anything else, these control how we do copies. */
depos = dy * line_length + dx;
sepos = sy * line_length + sx;
if (backward) {
depos += width;
sepos += width;
}
/* Next copy full words at a time. */
n32 = width / 32;
last_step = width % 32;
/* Finally copy the unaligned head of the span. */
mask_last = (1ul << last_step) - 1;
if (!backward) {
step = 32;
last_step = 32;
} else {
step = -32;
last_step = -last_step;
sepos -= 32;
depos -= 32;
}
tga_regs = par->tga_regs_base;
tga_fb = par->tga_fb_base;
/* Set up the MODE and PIXELSHIFT registers. */
__raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
__raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
wmb();
for (i = 0; i < height; ++i) {
unsigned long j;
void __iomem *sfb;
void __iomem *dfb;
sfb = tga_fb + sepos;
dfb = tga_fb + depos;
for (j = 0; j < n32; j++) {
if (j < 2 && j + 1 < n32 && !backward &&
!(((unsigned long)sfb | (unsigned long)dfb) & 63)) {
do {
__raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
wmb();
__raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
wmb();
sfb += 64;
dfb += 64;
j += 2;
} while (j + 1 < n32);
j--;
continue;
}
__raw_writel(0xffffffff, sfb);
wmb();
__raw_writel(0xffffffff, dfb);
wmb();
sfb += step;
dfb += step;
}
if (mask_last) {
sfb += last_step - step;
dfb += last_step - step;
__raw_writel(mask_last, sfb);
wmb();
__raw_writel(mask_last, dfb);
wmb();
}
sepos += yincr;
depos += yincr;
}
/* Reset the MODE register to normal. */
__raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
}
static void
tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
unsigned long line_length, bpp;
dx = area->dx;
dy = area->dy;
width = area->width;
height = area->height;
sx = area->sx;
sy = area->sy;
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
line_length = info->fix.line_length;
/* The top left corners must be in the virtual screen. */
if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
return;
/* Clip the destination. */
if (dx + width > vxres)
width = vxres - dx;
if (dy + height > vyres)
height = vyres - dy;
/* The source must be completely inside the virtual screen. */
if (sx + width > vxres || sy + height > vyres)
return;
bpp = info->var.bits_per_pixel;
/* Detect copies of the entire line. */
if (!(line_length & 63) && width * (bpp >> 3) == line_length) {
if (bpp == 8)
copyarea_line_8bpp(info, dy, sy, height, width);
else
copyarea_line_32bpp(info, dy, sy, height, width);
}
/* ??? The documentation is unclear to me exactly how the pixelshift
register works in 32bpp mode. Since I don't have hardware to test,
give up for now and fall back on the generic routines. */
else if (bpp == 32)
cfb_copyarea(info, area);
else
copyarea_8bpp(info, dx, dy, sx, sy, height,
width, line_length, area);
}
/*
* Initialisation
*/
static void
tgafb_init_fix(struct fb_info *info)
{
struct tga_par *par = (struct tga_par *)info->par;
int tga_bus_pci = dev_is_pci(par->dev);
int tga_bus_tc = TGA_BUS_TC(par->dev);
u8 tga_type = par->tga_type;
const char *tga_type_name = NULL;
unsigned memory_size;
switch (tga_type) {
case TGA_TYPE_8PLANE:
if (tga_bus_pci)
tga_type_name = "Digital ZLXp-E1";
if (tga_bus_tc)
tga_type_name = "Digital ZLX-E1";
memory_size = 2097152;
break;
case TGA_TYPE_24PLANE:
if (tga_bus_pci)
tga_type_name = "Digital ZLXp-E2";
if (tga_bus_tc)
tga_type_name = "Digital ZLX-E2";
memory_size = 8388608;
break;
case TGA_TYPE_24PLUSZ:
if (tga_bus_pci)
tga_type_name = "Digital ZLXp-E3";
if (tga_bus_tc)
tga_type_name = "Digital ZLX-E3";
memory_size = 16777216;
break;
}
if (!tga_type_name) {
tga_type_name = "Unknown";
memory_size = 16777216;
}
strscpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.visual = (tga_type == TGA_TYPE_8PLANE
? FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_DIRECTCOLOR);
info->fix.smem_start = (size_t) par->tga_fb_base;
info->fix.smem_len = memory_size;
info->fix.mmio_start = (size_t) par->tga_regs_base;
info->fix.mmio_len = 512;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_DEC_TGA;
/*
* These are needed by fb_set_logo_truepalette(), so we
* set them here for 24-plane cards.
*/
if (tga_type != TGA_TYPE_8PLANE) {
info->var.red.length = 8;
info->var.green.length = 8;
info->var.blue.length = 8;
info->var.red.offset = 16;
info->var.green.offset = 8;
info->var.blue.offset = 0;
}
}
static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
/* We just use this to catch switches out of graphics mode. */
tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
return 0;
}
static int tgafb_register(struct device *dev)
{
static const struct fb_videomode modedb_tc = {
/* 1280x1024 @ 72 Hz, 76.8 kHz hsync */
"1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3,
FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED
};
static unsigned int const fb_offset_presets[4] = {
TGA_8PLANE_FB_OFFSET,
TGA_24PLANE_FB_OFFSET,
0xffffffff,
TGA_24PLUSZ_FB_OFFSET
};
const struct fb_videomode *modedb_tga = NULL;
resource_size_t bar0_start = 0, bar0_len = 0;
const char *mode_option_tga = NULL;
int tga_bus_pci = dev_is_pci(dev);
int tga_bus_tc = TGA_BUS_TC(dev);
unsigned int modedbsize_tga = 0;
void __iomem *mem_base;
struct fb_info *info;
struct tga_par *par;
u8 tga_type;
int ret = 0;
/* Enable device in PCI config. */
if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) {
printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
return -ENODEV;
}
/* Allocate the fb and par structures. */
info = framebuffer_alloc(sizeof(struct tga_par), dev);
if (!info)
return -ENOMEM;
par = info->par;
dev_set_drvdata(dev, info);
/* Request the mem regions. */
ret = -ENODEV;
if (tga_bus_pci) {
bar0_start = pci_resource_start(to_pci_dev(dev), 0);
bar0_len = pci_resource_len(to_pci_dev(dev), 0);
}
if (tga_bus_tc) {
bar0_start = to_tc_dev(dev)->resource.start;
bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
}
if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
printk(KERN_ERR "tgafb: cannot reserve FB region\n");
goto err0;
}
/* Map the framebuffer. */
mem_base = ioremap(bar0_start, bar0_len);
if (!mem_base) {
printk(KERN_ERR "tgafb: Cannot map MMIO\n");
goto err1;
}
/* Grab info about the card. */
tga_type = (readl(mem_base) >> 12) & 0x0f;
par->dev = dev;
par->tga_mem_base = mem_base;
par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
par->tga_type = tga_type;
if (tga_bus_pci)
par->tga_chip_rev = (to_pci_dev(dev))->revision;
if (tga_bus_tc)
par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
/* Setup framebuffer. */
info->flags = FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
info->fbops = &tgafb_ops;
info->screen_base = par->tga_fb_base;
info->pseudo_palette = par->palette;
/* This should give a reasonable default video mode. */
if (tga_bus_pci) {
mode_option_tga = mode_option_pci;
}
if (tga_bus_tc) {
mode_option_tga = mode_option_tc;
modedb_tga = &modedb_tc;
modedbsize_tga = 1;
}
tgafb_init_fix(info);
ret = fb_find_mode(&info->var, info,
mode_option ? mode_option : mode_option_tga,
modedb_tga, modedbsize_tga, NULL,
tga_type == TGA_TYPE_8PLANE ? 8 : 32);
if (ret == 0 || ret == 4) {
printk(KERN_ERR "tgafb: Could not find valid video mode\n");
ret = -EINVAL;
goto err1;
}
if (fb_alloc_cmap(&info->cmap, 256, 0)) {
printk(KERN_ERR "tgafb: Could not allocate color map\n");
ret = -ENOMEM;
goto err1;
}
tgafb_set_par(info);
if (register_framebuffer(info) < 0) {
printk(KERN_ERR "tgafb: Could not register framebuffer\n");
ret = -EINVAL;
goto err2;
}
if (tga_bus_pci) {
pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
par->tga_chip_rev);
pr_info("tgafb: at PCI bus %d, device %d, function %d\n",
to_pci_dev(dev)->bus->number,
PCI_SLOT(to_pci_dev(dev)->devfn),
PCI_FUNC(to_pci_dev(dev)->devfn));
}
if (tga_bus_tc)
pr_info("tgafb: SFB+ detected, rev=0x%02x\n",
par->tga_chip_rev);
fb_info(info, "%s frame buffer device at 0x%lx\n",
info->fix.id, (long)bar0_start);
return 0;
err2:
fb_dealloc_cmap(&info->cmap);
err1:
if (mem_base)
iounmap(mem_base);
release_mem_region(bar0_start, bar0_len);
err0:
framebuffer_release(info);
return ret;
}
static void tgafb_unregister(struct device *dev)
{
resource_size_t bar0_start = 0, bar0_len = 0;
int tga_bus_pci = dev_is_pci(dev);
int tga_bus_tc = TGA_BUS_TC(dev);
struct fb_info *info = NULL;
struct tga_par *par;
info = dev_get_drvdata(dev);
if (!info)
return;
par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
iounmap(par->tga_mem_base);
if (tga_bus_pci) {
bar0_start = pci_resource_start(to_pci_dev(dev), 0);
bar0_len = pci_resource_len(to_pci_dev(dev), 0);
}
if (tga_bus_tc) {
bar0_start = to_tc_dev(dev)->resource.start;
bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
}
release_mem_region(bar0_start, bar0_len);
framebuffer_release(info);
}
static void tgafb_exit(void)
{
tc_unregister_driver(&tgafb_tc_driver);
pci_unregister_driver(&tgafb_pci_driver);
}
#ifndef MODULE
static int tgafb_setup(char *arg)
{
char *this_opt;
if (arg && *arg) {
while ((this_opt = strsep(&arg, ","))) {
if (!*this_opt)
continue;
if (!strncmp(this_opt, "mode:", 5))
mode_option = this_opt+5;
else
printk(KERN_ERR
"tgafb: unknown parameter %s\n",
this_opt);
}
}
return 0;
}
#endif /* !MODULE */
static int tgafb_init(void)
{
int status;
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("tgafb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("tgafb", &option))
return -ENODEV;
tgafb_setup(option);
#endif
status = pci_register_driver(&tgafb_pci_driver);
if (!status)
status = tc_register_driver(&tgafb_tc_driver);
return status;
}
/*
* Modularisation
*/
module_init(tgafb_init);
module_exit(tgafb_exit);
MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/tgafb.c |
/*
* linux/drivers/video/hecubafb.c -- FB driver for Hecuba/Apollo controller
*
* Copyright (C) 2006, Jaya Kumar
* This work was sponsored by CIS(M) Sdn Bhd
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
* This work was possible because of apollo display code from E-Ink's website
* http://support.eink.com/community
* All information used to write this code is from public material made
* available by E-Ink on its support site. Some commands such as 0xA4
* were found by looping through cmd=0x00 thru 0xFF and supplying random
* values. There are other commands that the display is capable of,
* beyond the 5 used here but they are more complex.
*
* This driver is written to be used with the Hecuba display architecture.
* The actual display chip is called Apollo and the interface electronics
* it needs is called Hecuba.
*
* It is intended to be architecture independent. A board specific driver
* must be used to perform all the physical IO interactions. An example
* is provided as n411.c
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/uaccess.h>
#include <video/hecubafb.h>
/* Display specific information */
#define DPY_W 600
#define DPY_H 800
static const struct fb_fix_screeninfo hecubafb_fix = {
.id = "hecubafb",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_MONO01,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
.line_length = DPY_W,
.accel = FB_ACCEL_NONE,
};
static const struct fb_var_screeninfo hecubafb_var = {
.xres = DPY_W,
.yres = DPY_H,
.xres_virtual = DPY_W,
.yres_virtual = DPY_H,
.bits_per_pixel = 1,
.nonstd = 1,
};
/* main hecubafb functions */
static void apollo_send_data(struct hecubafb_par *par, unsigned char data)
{
/* set data */
par->board->set_data(par, data);
/* set DS low */
par->board->set_ctl(par, HCB_DS_BIT, 0);
/* wait for ack */
par->board->wait_for_ack(par, 0);
/* set DS hi */
par->board->set_ctl(par, HCB_DS_BIT, 1);
/* wait for ack to clear */
par->board->wait_for_ack(par, 1);
}
static void apollo_send_command(struct hecubafb_par *par, unsigned char data)
{
/* command so set CD to high */
par->board->set_ctl(par, HCB_CD_BIT, 1);
/* actually strobe with command */
apollo_send_data(par, data);
/* clear CD back to low */
par->board->set_ctl(par, HCB_CD_BIT, 0);
}
static void hecubafb_dpy_update(struct hecubafb_par *par)
{
int i;
unsigned char *buf = par->info->screen_buffer;
apollo_send_command(par, APOLLO_START_NEW_IMG);
for (i=0; i < (DPY_W*DPY_H/8); i++) {
apollo_send_data(par, *(buf++));
}
apollo_send_command(par, APOLLO_STOP_IMG_DATA);
apollo_send_command(par, APOLLO_DISPLAY_IMG);
}
/* this is called back from the deferred io workqueue */
static void hecubafb_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist)
{
hecubafb_dpy_update(info->par);
}
static void hecubafb_defio_damage_range(struct fb_info *info, off_t off, size_t len)
{
struct hecubafb_par *par = info->par;
hecubafb_dpy_update(par);
}
static void hecubafb_defio_damage_area(struct fb_info *info, u32 x, u32 y,
u32 width, u32 height)
{
struct hecubafb_par *par = info->par;
hecubafb_dpy_update(par);
}
FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(hecubafb,
hecubafb_defio_damage_range,
hecubafb_defio_damage_area)
static const struct fb_ops hecubafb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_DEFERRED_OPS(hecubafb),
};
static struct fb_deferred_io hecubafb_defio = {
.delay = HZ,
.deferred_io = hecubafb_dpy_deferred_io,
};
static int hecubafb_probe(struct platform_device *dev)
{
struct fb_info *info;
struct hecuba_board *board;
int retval = -ENOMEM;
int videomemorysize;
unsigned char *videomemory;
struct hecubafb_par *par;
/* pick up board specific routines */
board = dev->dev.platform_data;
if (!board)
return -EINVAL;
/* try to count device specific driver, if can't, platform recalls */
if (!try_module_get(board->owner))
return -ENODEV;
videomemorysize = (DPY_W*DPY_H)/8;
videomemory = vzalloc(videomemorysize);
if (!videomemory)
goto err_videomem_alloc;
info = framebuffer_alloc(sizeof(struct hecubafb_par), &dev->dev);
if (!info)
goto err_fballoc;
info->screen_buffer = videomemory;
info->fbops = &hecubafb_ops;
info->var = hecubafb_var;
info->fix = hecubafb_fix;
info->fix.smem_len = videomemorysize;
par = info->par;
par->info = info;
par->board = board;
par->send_command = apollo_send_command;
par->send_data = apollo_send_data;
info->flags = FBINFO_VIRTFB;
info->fbdefio = &hecubafb_defio;
fb_deferred_io_init(info);
retval = register_framebuffer(info);
if (retval < 0)
goto err_fbreg;
platform_set_drvdata(dev, info);
fb_info(info, "Hecuba frame buffer device, using %dK of video memory\n",
videomemorysize >> 10);
/* this inits the dpy */
retval = par->board->init(par);
if (retval < 0)
goto err_fbreg;
return 0;
err_fbreg:
framebuffer_release(info);
err_fballoc:
vfree(videomemory);
err_videomem_alloc:
module_put(board->owner);
return retval;
}
static void hecubafb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
if (info) {
struct hecubafb_par *par = info->par;
fb_deferred_io_cleanup(info);
unregister_framebuffer(info);
vfree(info->screen_buffer);
if (par->board->remove)
par->board->remove(par);
module_put(par->board->owner);
framebuffer_release(info);
}
}
static struct platform_driver hecubafb_driver = {
.probe = hecubafb_probe,
.remove_new = hecubafb_remove,
.driver = {
.name = "hecubafb",
},
};
module_platform_driver(hecubafb_driver);
MODULE_DESCRIPTION("fbdev driver for Hecuba/Apollo controller");
MODULE_AUTHOR("Jaya Kumar");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/hecubafb.c |
/*
* drivers/video/asiliantfb.c
* frame buffer driver for Asiliant 69000 chip
* Copyright (C) 2001-2003 Saito.K & Jeanne
*
* from driver/video/chipsfb.c and,
*
* drivers/video/asiliantfb.c -- frame buffer device for
* Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies)
* Author: [email protected]
* Copyright (C) 2000 AG Electronics
* Note: the data sheets don't seem to be available from Asiliant.
* They are available by searching developer.intel.com, but are not otherwise
* linked to.
*
* This driver should be portable with minimal effort to the 69000 display
* chip, and to the twin-display mode of the 69030.
* Contains code from Thomas Hhenleitner <[email protected]> (thanks)
*
* Derived from the CT65550 driver chipsfb.c:
* Copyright (C) 1998 Paul Mackerras
* ...which was derived from the Powermac "chips" driver:
* Copyright (C) 1997 Fabio Riccardi.
* And from the frame buffer device for Open Firmware-initialized devices:
* Copyright (C) 1997 Geert Uytterhoeven.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/io.h>
/* Built in clock of the 69030 */
static const unsigned Fref = 14318180;
#define mmio_base (p->screen_base + 0x400000)
#define mm_write_ind(num, val, ap, dp) do { \
writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \
} while (0)
static void mm_write_xr(struct fb_info *p, u8 reg, u8 data)
{
mm_write_ind(reg, data, 0x7ac, 0x7ad);
}
#define write_xr(num, val) mm_write_xr(p, num, val)
static void mm_write_fr(struct fb_info *p, u8 reg, u8 data)
{
mm_write_ind(reg, data, 0x7a0, 0x7a1);
}
#define write_fr(num, val) mm_write_fr(p, num, val)
static void mm_write_cr(struct fb_info *p, u8 reg, u8 data)
{
mm_write_ind(reg, data, 0x7a8, 0x7a9);
}
#define write_cr(num, val) mm_write_cr(p, num, val)
static void mm_write_gr(struct fb_info *p, u8 reg, u8 data)
{
mm_write_ind(reg, data, 0x79c, 0x79d);
}
#define write_gr(num, val) mm_write_gr(p, num, val)
static void mm_write_sr(struct fb_info *p, u8 reg, u8 data)
{
mm_write_ind(reg, data, 0x788, 0x789);
}
#define write_sr(num, val) mm_write_sr(p, num, val)
static void mm_write_ar(struct fb_info *p, u8 reg, u8 data)
{
readb(mmio_base + 0x7b4);
mm_write_ind(reg, data, 0x780, 0x780);
}
#define write_ar(num, val) mm_write_ar(p, num, val)
static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
static int asiliantfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info);
static int asiliantfb_set_par(struct fb_info *info);
static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static const struct fb_ops asiliantfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = asiliantfb_check_var,
.fb_set_par = asiliantfb_set_par,
.fb_setcolreg = asiliantfb_setcolreg,
};
/* Calculate the ratios for the dot clocks without using a single long long
* value */
static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div)
{
unsigned pixclock = *ppixclock;
unsigned Ftarget;
unsigned n;
unsigned best_error = 0xffffffff;
unsigned best_m = 0xffffffff,
best_n = 0xffffffff;
unsigned ratio;
unsigned remainder;
unsigned char divisor = 0;
/* Calculate the frequency required. This is hard enough. */
ratio = 1000000 / pixclock;
remainder = 1000000 % pixclock;
Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock;
while (Ftarget < 100000000) {
divisor += 0x10;
Ftarget <<= 1;
}
ratio = Ftarget / Fref;
remainder = Ftarget % Fref;
/* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz,
* together with 3 <= n <= 257. */
for (n = 3; n <= 257; n++) {
unsigned m = n * ratio + (n * remainder) / Fref;
/* 3 <= m <= 257 */
if (m >= 3 && m <= 257) {
unsigned new_error = Ftarget * n >= Fref * m ?
((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n));
if (new_error < best_error) {
best_n = n;
best_m = m;
best_error = new_error;
}
}
/* But if VLD = 4, then 4m <= 1028 */
else if (m <= 1028) {
/* remember there are still only 8-bits of precision in m, so
* avoid over-optimistic error calculations */
unsigned new_error = Ftarget * n >= Fref * (m & ~3) ?
((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n));
if (new_error < best_error) {
best_n = n;
best_m = m;
best_error = new_error;
}
}
}
if (best_m > 257)
best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */
else
divisor |= 4; /* or set VCO loop divide to 1 */
*dclk2_m = best_m - 2;
*dclk2_n = best_n - 2;
*dclk2_div = divisor;
*ppixclock = pixclock;
return;
}
static void asiliant_set_timing(struct fb_info *p)
{
unsigned hd = p->var.xres / 8;
unsigned hs = (p->var.xres + p->var.right_margin) / 8;
unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8;
unsigned vd = p->var.yres;
unsigned vs = p->var.yres + p->var.lower_margin;
unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len;
unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len;
unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8;
if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) {
write_fr(0x01, 0x02); /* LCD */
} else {
write_fr(0x01, 0x01); /* CRT */
}
write_cr(0x11, (ve - 1) & 0x0f);
write_cr(0x00, (ht - 5) & 0xff);
write_cr(0x01, hd - 1);
write_cr(0x02, hd);
write_cr(0x03, ((ht - 1) & 0x1f) | 0x80);
write_cr(0x04, hs);
write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f));
write_cr(0x3c, (ht - 1) & 0xc0);
write_cr(0x06, (vt - 2) & 0xff);
write_cr(0x30, (vt - 2) >> 8);
write_cr(0x07, 0x00);
write_cr(0x08, 0x00);
write_cr(0x09, 0x00);
write_cr(0x10, (vs - 1) & 0xff);
write_cr(0x32, ((vs - 1) >> 8) & 0xf);
write_cr(0x11, ((ve - 1) & 0x0f) | 0x80);
write_cr(0x12, (vd - 1) & 0xff);
write_cr(0x31, ((vd - 1) & 0xf00) >> 8);
write_cr(0x13, wd & 0xff);
write_cr(0x41, (wd & 0xf00) >> 8);
write_cr(0x15, (vs - 1) & 0xff);
write_cr(0x33, ((vs - 1) >> 8) & 0xf);
write_cr(0x38, ((ht - 5) & 0x100) >> 8);
write_cr(0x16, (vt - 1) & 0xff);
write_cr(0x18, 0x00);
if (p->var.xres == 640) {
writeb(0xc7, mmio_base + 0x784); /* set misc output reg */
} else {
writeb(0x07, mmio_base + 0x784); /* set misc output reg */
}
}
static int asiliantfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *p)
{
unsigned long Ftarget, ratio, remainder;
if (!var->pixclock)
return -EINVAL;
ratio = 1000000 / var->pixclock;
remainder = 1000000 % var->pixclock;
Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock;
/* First check the constraint that the maximum post-VCO divisor is 32,
* and the maximum Fvco is 220MHz */
if (Ftarget > 220000000 || Ftarget < 3125000) {
printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n");
return -ENXIO;
}
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
if (var->bits_per_pixel == 24) {
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->red.length = var->blue.length = var->green.length = 8;
} else if (var->bits_per_pixel == 16) {
switch (var->red.offset) {
case 11:
var->green.length = 6;
break;
case 10:
var->green.length = 5;
break;
default:
return -EINVAL;
}
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = var->blue.length = 5;
} else if (var->bits_per_pixel == 8) {
var->red.offset = var->green.offset = var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = 8;
}
return 0;
}
static int asiliantfb_set_par(struct fb_info *p)
{
u8 dclk2_m; /* Holds m-2 value for register */
u8 dclk2_n; /* Holds n-2 value for register */
u8 dclk2_div; /* Holds divisor bitmask */
/* Set pixclock */
asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div);
/* Set color depth */
if (p->var.bits_per_pixel == 24) {
write_xr(0x81, 0x16); /* 24 bit packed color mode */
write_xr(0x82, 0x00); /* Disable palettes */
write_xr(0x20, 0x20); /* 24 bit blitter mode */
} else if (p->var.bits_per_pixel == 16) {
if (p->var.red.offset == 11)
write_xr(0x81, 0x15); /* 16 bit color mode */
else
write_xr(0x81, 0x14); /* 15 bit color mode */
write_xr(0x82, 0x00); /* Disable palettes */
write_xr(0x20, 0x10); /* 16 bit blitter mode */
} else if (p->var.bits_per_pixel == 8) {
write_xr(0x0a, 0x02); /* Linear */
write_xr(0x81, 0x12); /* 8 bit color mode */
write_xr(0x82, 0x00); /* Graphics gamma enable */
write_xr(0x20, 0x00); /* 8 bit blitter mode */
}
p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3);
p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
write_xr(0xc4, dclk2_m);
write_xr(0xc5, dclk2_n);
write_xr(0xc7, dclk2_div);
/* Set up the CR registers */
asiliant_set_timing(p);
return 0;
}
static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *p)
{
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
/* Set hardware palete */
writeb(regno, mmio_base + 0x790);
udelay(1);
writeb(red, mmio_base + 0x791);
writeb(green, mmio_base + 0x791);
writeb(blue, mmio_base + 0x791);
if (regno < 16) {
switch(p->var.red.offset) {
case 10: /* RGB 555 */
((u32 *)(p->pseudo_palette))[regno] =
((red & 0xf8) << 7) |
((green & 0xf8) << 2) |
((blue & 0xf8) >> 3);
break;
case 11: /* RGB 565 */
((u32 *)(p->pseudo_palette))[regno] =
((red & 0xf8) << 8) |
((green & 0xfc) << 3) |
((blue & 0xf8) >> 3);
break;
case 16: /* RGB 888 */
((u32 *)(p->pseudo_palette))[regno] =
(red << 16) |
(green << 8) |
(blue);
break;
}
}
return 0;
}
struct chips_init_reg {
unsigned char addr;
unsigned char data;
};
static struct chips_init_reg chips_init_sr[] =
{
{0x00, 0x03}, /* Reset register */
{0x01, 0x01}, /* Clocking mode */
{0x02, 0x0f}, /* Plane mask */
{0x04, 0x0e} /* Memory mode */
};
static struct chips_init_reg chips_init_gr[] =
{
{0x03, 0x00}, /* Data rotate */
{0x05, 0x00}, /* Graphics mode */
{0x06, 0x01}, /* Miscellaneous */
{0x08, 0x00} /* Bit mask */
};
static struct chips_init_reg chips_init_ar[] =
{
{0x10, 0x01}, /* Mode control */
{0x11, 0x00}, /* Overscan */
{0x12, 0x0f}, /* Memory plane enable */
{0x13, 0x00} /* Horizontal pixel panning */
};
static struct chips_init_reg chips_init_cr[] =
{
{0x0c, 0x00}, /* Start address high */
{0x0d, 0x00}, /* Start address low */
{0x40, 0x00}, /* Extended Start Address */
{0x41, 0x00}, /* Extended Start Address */
{0x14, 0x00}, /* Underline location */
{0x17, 0xe3}, /* CRT mode control */
{0x70, 0x00} /* Interlace control */
};
static struct chips_init_reg chips_init_fr[] =
{
{0x01, 0x02},
{0x03, 0x08},
{0x08, 0xcc},
{0x0a, 0x08},
{0x18, 0x00},
{0x1e, 0x80},
{0x40, 0x83},
{0x41, 0x00},
{0x48, 0x13},
{0x4d, 0x60},
{0x4e, 0x0f},
{0x0b, 0x01},
{0x21, 0x51},
{0x22, 0x1d},
{0x23, 0x5f},
{0x20, 0x4f},
{0x34, 0x00},
{0x24, 0x51},
{0x25, 0x00},
{0x27, 0x0b},
{0x26, 0x00},
{0x37, 0x80},
{0x33, 0x0b},
{0x35, 0x11},
{0x36, 0x02},
{0x31, 0xea},
{0x32, 0x0c},
{0x30, 0xdf},
{0x10, 0x0c},
{0x11, 0xe0},
{0x12, 0x50},
{0x13, 0x00},
{0x16, 0x03},
{0x17, 0xbd},
{0x1a, 0x00},
};
static struct chips_init_reg chips_init_xr[] =
{
{0xce, 0x00}, /* set default memory clock */
{0xcc, 200 }, /* MCLK ratio M */
{0xcd, 18 }, /* MCLK ratio N */
{0xce, 0x90}, /* MCLK divisor = 2 */
{0xc4, 209 },
{0xc5, 118 },
{0xc7, 32 },
{0xcf, 0x06},
{0x09, 0x01}, /* IO Control - CRT controller extensions */
{0x0a, 0x02}, /* Frame buffer mapping */
{0x0b, 0x01}, /* PCI burst write */
{0x40, 0x03}, /* Memory access control */
{0x80, 0x82}, /* Pixel pipeline configuration 0 */
{0x81, 0x12}, /* Pixel pipeline configuration 1 */
{0x82, 0x08}, /* Pixel pipeline configuration 2 */
{0xd0, 0x0f},
{0xd1, 0x01},
};
static void chips_hw_init(struct fb_info *p)
{
int i;
for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
write_xr(0x81, 0x12);
write_xr(0x82, 0x08);
write_xr(0x20, 0x00);
for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
/* Enable video output in attribute index register */
writeb(0x20, mmio_base + 0x780);
for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
}
static const struct fb_fix_screeninfo asiliantfb_fix = {
.id = "Asiliant 69000",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.accel = FB_ACCEL_NONE,
.line_length = 640,
.smem_len = 0x200000, /* 2MB */
};
static const struct fb_var_screeninfo asiliantfb_var = {
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel = 8,
.red = { .length = 8 },
.green = { .length = 8 },
.blue = { .length = 8 },
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
.pixclock = 39722,
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
};
static int init_asiliant(struct fb_info *p, unsigned long addr)
{
int err;
p->fix = asiliantfb_fix;
p->fix.smem_start = addr;
p->var = asiliantfb_var;
p->fbops = &asiliantfb_ops;
err = fb_alloc_cmap(&p->cmap, 256, 0);
if (err) {
printk(KERN_ERR "C&T 69000 fb failed to alloc cmap memory\n");
return err;
}
err = register_framebuffer(p);
if (err < 0) {
printk(KERN_ERR "C&T 69000 framebuffer failed to register\n");
fb_dealloc_cmap(&p->cmap);
return err;
}
fb_info(p, "Asiliant 69000 frame buffer (%dK RAM detected)\n",
p->fix.smem_len / 1024);
writeb(0xff, mmio_base + 0x78c);
chips_hw_init(p);
return 0;
}
static int asiliantfb_pci_init(struct pci_dev *dp,
const struct pci_device_id *ent)
{
unsigned long addr, size;
struct fb_info *p;
int err;
err = aperture_remove_conflicting_pci_devices(dp, "asiliantfb");
if (err)
return err;
if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
return -ENODEV;
addr = pci_resource_start(dp, 0);
size = pci_resource_len(dp, 0);
if (addr == 0)
return -ENODEV;
if (!request_mem_region(addr, size, "asiliantfb"))
return -EBUSY;
p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev);
if (!p) {
release_mem_region(addr, size);
return -ENOMEM;
}
p->pseudo_palette = p->par;
p->par = NULL;
p->screen_base = ioremap(addr, 0x800000);
if (p->screen_base == NULL) {
release_mem_region(addr, size);
framebuffer_release(p);
return -ENOMEM;
}
pci_write_config_dword(dp, 4, 0x02800083);
writeb(3, p->screen_base + 0x400784);
err = init_asiliant(p, addr);
if (err) {
iounmap(p->screen_base);
release_mem_region(addr, size);
framebuffer_release(p);
return err;
}
pci_set_drvdata(dp, p);
return 0;
}
static void asiliantfb_remove(struct pci_dev *dp)
{
struct fb_info *p = pci_get_drvdata(dp);
unregister_framebuffer(p);
fb_dealloc_cmap(&p->cmap);
iounmap(p->screen_base);
release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0));
framebuffer_release(p);
}
static const struct pci_device_id asiliantfb_pci_tbl[] = {
{ PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID },
{ 0 }
};
MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl);
static struct pci_driver asiliantfb_driver = {
.name = "asiliantfb",
.id_table = asiliantfb_pci_tbl,
.probe = asiliantfb_pci_init,
.remove = asiliantfb_remove,
};
static int __init asiliantfb_init(void)
{
if (fb_modesetting_disabled("asiliantfb"))
return -ENODEV;
if (fb_get_options("asiliantfb", NULL))
return -ENODEV;
return pci_register_driver(&asiliantfb_driver);
}
module_init(asiliantfb_init);
static void __exit asiliantfb_exit(void)
{
pci_unregister_driver(&asiliantfb_driver);
}
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/asiliantfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Frame buffer device for IBM GXT4500P/6500P and GXT4000P/6000P
* display adaptors
*
* Copyright (C) 2006 Paul Mackerras, IBM Corp. <[email protected]>
*/
#include <linux/aperture.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/fb.h>
#include <linux/console.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/delay.h>
#include <linux/string.h>
#define PCI_DEVICE_ID_IBM_GXT4500P 0x21c
#define PCI_DEVICE_ID_IBM_GXT6500P 0x21b
#define PCI_DEVICE_ID_IBM_GXT4000P 0x16e
#define PCI_DEVICE_ID_IBM_GXT6000P 0x170
/* GXT4500P registers */
/* Registers in PCI config space */
#define CFG_ENDIAN0 0x40
/* Misc control/status registers */
#define STATUS 0x1000
#define CTRL_REG0 0x1004
#define CR0_HALT_DMA 0x4
#define CR0_RASTER_RESET 0x8
#define CR0_GEOM_RESET 0x10
#define CR0_MEM_CTRLER_RESET 0x20
/* Framebuffer control registers */
#define FB_AB_CTRL 0x1100
#define FB_CD_CTRL 0x1104
#define FB_WID_CTRL 0x1108
#define FB_Z_CTRL 0x110c
#define FB_VGA_CTRL 0x1110
#define REFRESH_AB_CTRL 0x1114
#define REFRESH_CD_CTRL 0x1118
#define FB_OVL_CTRL 0x111c
#define FB_CTRL_TYPE 0x80000000
#define FB_CTRL_WIDTH_MASK 0x007f0000
#define FB_CTRL_WIDTH_SHIFT 16
#define FB_CTRL_START_SEG_MASK 0x00003fff
#define REFRESH_START 0x1098
#define REFRESH_SIZE 0x109c
/* "Direct" framebuffer access registers */
#define DFA_FB_A 0x11e0
#define DFA_FB_B 0x11e4
#define DFA_FB_C 0x11e8
#define DFA_FB_D 0x11ec
#define DFA_FB_ENABLE 0x80000000
#define DFA_FB_BASE_MASK 0x03f00000
#define DFA_FB_STRIDE_1k 0x00000000
#define DFA_FB_STRIDE_2k 0x00000010
#define DFA_FB_STRIDE_4k 0x00000020
#define DFA_PIX_8BIT 0x00000000
#define DFA_PIX_16BIT_565 0x00000001
#define DFA_PIX_16BIT_1555 0x00000002
#define DFA_PIX_24BIT 0x00000004
#define DFA_PIX_32BIT 0x00000005
/* maps DFA_PIX_* to pixel size in bytes */
static const unsigned char pixsize[] = {
1, 2, 2, 2, 4, 4
};
/* Display timing generator registers */
#define DTG_CONTROL 0x1900
#define DTG_CTL_SCREEN_REFRESH 2
#define DTG_CTL_ENABLE 1
#define DTG_HORIZ_EXTENT 0x1904
#define DTG_HORIZ_DISPLAY 0x1908
#define DTG_HSYNC_START 0x190c
#define DTG_HSYNC_END 0x1910
#define DTG_HSYNC_END_COMP 0x1914
#define DTG_VERT_EXTENT 0x1918
#define DTG_VERT_DISPLAY 0x191c
#define DTG_VSYNC_START 0x1920
#define DTG_VSYNC_END 0x1924
#define DTG_VERT_SHORT 0x1928
/* PLL/RAMDAC registers */
#define DISP_CTL 0x402c
#define DISP_CTL_OFF 2
#define SYNC_CTL 0x4034
#define SYNC_CTL_SYNC_ON_RGB 1
#define SYNC_CTL_SYNC_OFF 2
#define SYNC_CTL_HSYNC_INV 8
#define SYNC_CTL_VSYNC_INV 0x10
#define SYNC_CTL_HSYNC_OFF 0x20
#define SYNC_CTL_VSYNC_OFF 0x40
#define PLL_M 0x4040
#define PLL_N 0x4044
#define PLL_POSTDIV 0x4048
#define PLL_C 0x404c
/* Hardware cursor */
#define CURSOR_X 0x4078
#define CURSOR_Y 0x407c
#define CURSOR_HOTSPOT 0x4080
#define CURSOR_MODE 0x4084
#define CURSOR_MODE_OFF 0
#define CURSOR_MODE_4BPP 1
#define CURSOR_PIXMAP 0x5000
#define CURSOR_CMAP 0x7400
/* Window attribute table */
#define WAT_FMT 0x4100
#define WAT_FMT_24BIT 0
#define WAT_FMT_16BIT_565 1
#define WAT_FMT_16BIT_1555 2
#define WAT_FMT_32BIT 3 /* 0 vs. 3 is a guess */
#define WAT_FMT_8BIT_332 9
#define WAT_FMT_8BIT 0xa
#define WAT_FMT_NO_CMAP 4 /* ORd in to other values */
#define WAT_CMAP_OFFSET 0x4104 /* 4-bit value gets << 6 */
#define WAT_CTRL 0x4108
#define WAT_CTRL_SEL_B 1 /* select B buffer if 1 */
#define WAT_CTRL_NO_INC 2
#define WAT_GAMMA_CTRL 0x410c
#define WAT_GAMMA_DISABLE 1 /* disables gamma cmap */
#define WAT_OVL_CTRL 0x430c /* controls overlay */
/* Indexed by DFA_PIX_* values */
static const unsigned char watfmt[] = {
WAT_FMT_8BIT, WAT_FMT_16BIT_565, WAT_FMT_16BIT_1555, 0,
WAT_FMT_24BIT, WAT_FMT_32BIT
};
/* Colormap array; 1k entries of 4 bytes each */
#define CMAP 0x6000
#define readreg(par, reg) readl((par)->regs + (reg))
#define writereg(par, reg, val) writel((val), (par)->regs + (reg))
struct gxt4500_par {
void __iomem *regs;
int wc_cookie;
int pixfmt; /* pixel format, see DFA_PIX_* values */
/* PLL parameters */
int refclk_ps; /* ref clock period in picoseconds */
int pll_m; /* ref clock divisor */
int pll_n; /* VCO divisor */
int pll_pd1; /* first post-divisor */
int pll_pd2; /* second post-divisor */
u32 pseudo_palette[16]; /* used in color blits */
};
/* mode requested by user */
static char *mode_option;
/* default mode: 1280x1024 @ 60 Hz, 8 bpp */
static const struct fb_videomode defaultmode = {
.refresh = 60,
.xres = 1280,
.yres = 1024,
.pixclock = 9295,
.left_margin = 248,
.right_margin = 48,
.upper_margin = 38,
.lower_margin = 1,
.hsync_len = 112,
.vsync_len = 3,
.vmode = FB_VMODE_NONINTERLACED
};
/* List of supported cards */
enum gxt_cards {
GXT4500P,
GXT6500P,
GXT4000P,
GXT6000P
};
/* Card-specific information */
static const struct cardinfo {
int refclk_ps; /* period of PLL reference clock in ps */
const char *cardname;
} cardinfo[] = {
[GXT4500P] = { .refclk_ps = 9259, .cardname = "IBM GXT4500P" },
[GXT6500P] = { .refclk_ps = 9259, .cardname = "IBM GXT6500P" },
[GXT4000P] = { .refclk_ps = 40000, .cardname = "IBM GXT4000P" },
[GXT6000P] = { .refclk_ps = 40000, .cardname = "IBM GXT6000P" },
};
/*
* The refclk and VCO dividers appear to use a linear feedback shift
* register, which gets reloaded when it reaches a terminal value, at
* which point the divider output is toggled. Thus one can obtain
* whatever divisor is required by putting the appropriate value into
* the reload register. For a divisor of N, one puts the value from
* the LFSR sequence that comes N-1 places before the terminal value
* into the reload register.
*/
static const unsigned char mdivtab[] = {
/* 1 */ 0x3f, 0x00, 0x20, 0x10, 0x28, 0x14, 0x2a, 0x15, 0x0a,
/* 10 */ 0x25, 0x32, 0x19, 0x0c, 0x26, 0x13, 0x09, 0x04, 0x22, 0x11,
/* 20 */ 0x08, 0x24, 0x12, 0x29, 0x34, 0x1a, 0x2d, 0x36, 0x1b, 0x0d,
/* 30 */ 0x06, 0x23, 0x31, 0x38, 0x1c, 0x2e, 0x17, 0x0b, 0x05, 0x02,
/* 40 */ 0x21, 0x30, 0x18, 0x2c, 0x16, 0x2b, 0x35, 0x3a, 0x1d, 0x0e,
/* 50 */ 0x27, 0x33, 0x39, 0x3c, 0x1e, 0x2f, 0x37, 0x3b, 0x3d, 0x3e,
/* 60 */ 0x1f, 0x0f, 0x07, 0x03, 0x01,
};
static const unsigned char ndivtab[] = {
/* 2 */ 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0x78, 0xbc, 0x5e,
/* 10 */ 0x2f, 0x17, 0x0b, 0x85, 0xc2, 0xe1, 0x70, 0x38, 0x9c, 0x4e,
/* 20 */ 0xa7, 0xd3, 0xe9, 0xf4, 0xfa, 0xfd, 0xfe, 0x7f, 0xbf, 0xdf,
/* 30 */ 0xef, 0x77, 0x3b, 0x1d, 0x8e, 0xc7, 0xe3, 0x71, 0xb8, 0xdc,
/* 40 */ 0x6e, 0xb7, 0x5b, 0x2d, 0x16, 0x8b, 0xc5, 0xe2, 0xf1, 0xf8,
/* 50 */ 0xfc, 0x7e, 0x3f, 0x9f, 0xcf, 0x67, 0xb3, 0xd9, 0x6c, 0xb6,
/* 60 */ 0xdb, 0x6d, 0x36, 0x9b, 0x4d, 0x26, 0x13, 0x89, 0xc4, 0x62,
/* 70 */ 0xb1, 0xd8, 0xec, 0xf6, 0xfb, 0x7d, 0xbe, 0x5f, 0xaf, 0x57,
/* 80 */ 0x2b, 0x95, 0x4a, 0x25, 0x92, 0x49, 0xa4, 0x52, 0x29, 0x94,
/* 90 */ 0xca, 0x65, 0xb2, 0x59, 0x2c, 0x96, 0xcb, 0xe5, 0xf2, 0x79,
/* 100 */ 0x3c, 0x1e, 0x0f, 0x07, 0x83, 0x41, 0x20, 0x90, 0x48, 0x24,
/* 110 */ 0x12, 0x09, 0x84, 0x42, 0xa1, 0x50, 0x28, 0x14, 0x8a, 0x45,
/* 120 */ 0xa2, 0xd1, 0xe8, 0x74, 0xba, 0xdd, 0xee, 0xf7, 0x7b, 0x3d,
/* 130 */ 0x9e, 0x4f, 0x27, 0x93, 0xc9, 0xe4, 0x72, 0x39, 0x1c, 0x0e,
/* 140 */ 0x87, 0xc3, 0x61, 0x30, 0x18, 0x8c, 0xc6, 0x63, 0x31, 0x98,
/* 150 */ 0xcc, 0xe6, 0x73, 0xb9, 0x5c, 0x2e, 0x97, 0x4b, 0xa5, 0xd2,
/* 160 */ 0x69,
};
static int calc_pll(int period_ps, struct gxt4500_par *par)
{
int m, n, pdiv1, pdiv2, postdiv;
int pll_period, best_error, t, intf;
/* only deal with range 5MHz - 300MHz */
if (period_ps < 3333 || period_ps > 200000)
return -1;
best_error = 1000000;
for (pdiv1 = 1; pdiv1 <= 8; ++pdiv1) {
for (pdiv2 = 1; pdiv2 <= pdiv1; ++pdiv2) {
postdiv = pdiv1 * pdiv2;
pll_period = DIV_ROUND_UP(period_ps, postdiv);
/* keep pll in range 350..600 MHz */
if (pll_period < 1666 || pll_period > 2857)
continue;
for (m = 1; m <= 64; ++m) {
intf = m * par->refclk_ps;
if (intf > 500000)
break;
n = intf * postdiv / period_ps;
if (n < 3 || n > 160)
continue;
t = par->refclk_ps * m * postdiv / n;
t -= period_ps;
if (t >= 0 && t < best_error) {
par->pll_m = m;
par->pll_n = n;
par->pll_pd1 = pdiv1;
par->pll_pd2 = pdiv2;
best_error = t;
}
}
}
}
if (best_error == 1000000)
return -1;
return 0;
}
static int calc_pixclock(struct gxt4500_par *par)
{
return par->refclk_ps * par->pll_m * par->pll_pd1 * par->pll_pd2
/ par->pll_n;
}
static int gxt4500_var_to_par(struct fb_var_screeninfo *var,
struct gxt4500_par *par)
{
if (var->xres + var->xoffset > var->xres_virtual ||
var->yres + var->yoffset > var->yres_virtual ||
var->xres_virtual > 4096)
return -EINVAL;
if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
return -EINVAL;
if (calc_pll(var->pixclock, par) < 0)
return -EINVAL;
switch (var->bits_per_pixel) {
case 32:
if (var->transp.length)
par->pixfmt = DFA_PIX_32BIT;
else
par->pixfmt = DFA_PIX_24BIT;
break;
case 24:
par->pixfmt = DFA_PIX_24BIT;
break;
case 16:
if (var->green.length == 5)
par->pixfmt = DFA_PIX_16BIT_1555;
else
par->pixfmt = DFA_PIX_16BIT_565;
break;
case 8:
par->pixfmt = DFA_PIX_8BIT;
break;
default:
return -EINVAL;
}
return 0;
}
static const struct fb_bitfield eightbits = {0, 8};
static const struct fb_bitfield nobits = {0, 0};
static void gxt4500_unpack_pixfmt(struct fb_var_screeninfo *var,
int pixfmt)
{
var->bits_per_pixel = pixsize[pixfmt] * 8;
var->red = eightbits;
var->green = eightbits;
var->blue = eightbits;
var->transp = nobits;
switch (pixfmt) {
case DFA_PIX_16BIT_565:
var->red.length = 5;
var->green.length = 6;
var->blue.length = 5;
break;
case DFA_PIX_16BIT_1555:
var->red.length = 5;
var->green.length = 5;
var->blue.length = 5;
var->transp.length = 1;
break;
case DFA_PIX_32BIT:
var->transp.length = 8;
break;
}
if (pixfmt != DFA_PIX_8BIT) {
var->blue.offset = 0;
var->green.offset = var->blue.length;
var->red.offset = var->green.offset + var->green.length;
if (var->transp.length)
var->transp.offset =
var->red.offset + var->red.length;
}
}
static int gxt4500_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct gxt4500_par par;
int err;
par = *(struct gxt4500_par *)info->par;
err = gxt4500_var_to_par(var, &par);
if (!err) {
var->pixclock = calc_pixclock(&par);
gxt4500_unpack_pixfmt(var, par.pixfmt);
}
return err;
}
static int gxt4500_set_par(struct fb_info *info)
{
struct gxt4500_par *par = info->par;
struct fb_var_screeninfo *var = &info->var;
int err;
u32 ctrlreg, tmp;
unsigned int dfa_ctl, pixfmt, stride;
unsigned int wid_tiles, i;
unsigned int prefetch_pix, htot;
struct gxt4500_par save_par;
save_par = *par;
err = gxt4500_var_to_par(var, par);
if (err) {
*par = save_par;
return err;
}
/* turn off DTG for now */
ctrlreg = readreg(par, DTG_CONTROL);
ctrlreg &= ~(DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH);
writereg(par, DTG_CONTROL, ctrlreg);
/* set PLL registers */
tmp = readreg(par, PLL_C) & ~0x7f;
if (par->pll_n < 38)
tmp |= 0x29;
if (par->pll_n < 69)
tmp |= 0x35;
else if (par->pll_n < 100)
tmp |= 0x76;
else
tmp |= 0x7e;
writereg(par, PLL_C, tmp);
writereg(par, PLL_M, mdivtab[par->pll_m - 1]);
writereg(par, PLL_N, ndivtab[par->pll_n - 2]);
tmp = ((8 - par->pll_pd2) << 3) | (8 - par->pll_pd1);
if (par->pll_pd1 == 8 || par->pll_pd2 == 8) {
/* work around erratum */
writereg(par, PLL_POSTDIV, tmp | 0x9);
udelay(1);
}
writereg(par, PLL_POSTDIV, tmp);
msleep(20);
/* turn off hardware cursor */
writereg(par, CURSOR_MODE, CURSOR_MODE_OFF);
/* reset raster engine */
writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16));
udelay(10);
writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16);
/* set display timing generator registers */
htot = var->xres + var->left_margin + var->right_margin +
var->hsync_len;
writereg(par, DTG_HORIZ_EXTENT, htot - 1);
writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1);
writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1);
writereg(par, DTG_HSYNC_END,
var->xres + var->right_margin + var->hsync_len - 1);
writereg(par, DTG_HSYNC_END_COMP,
var->xres + var->right_margin + var->hsync_len - 1);
writereg(par, DTG_VERT_EXTENT,
var->yres + var->upper_margin + var->lower_margin +
var->vsync_len - 1);
writereg(par, DTG_VERT_DISPLAY, var->yres - 1);
writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1);
writereg(par, DTG_VSYNC_END,
var->yres + var->lower_margin + var->vsync_len - 1);
prefetch_pix = 3300000 / var->pixclock;
if (prefetch_pix >= htot)
prefetch_pix = htot - 1;
writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1);
ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH;
writereg(par, DTG_CONTROL, ctrlreg);
/* calculate stride in DFA aperture */
if (var->xres_virtual > 2048) {
stride = 4096;
dfa_ctl = DFA_FB_STRIDE_4k;
} else if (var->xres_virtual > 1024) {
stride = 2048;
dfa_ctl = DFA_FB_STRIDE_2k;
} else {
stride = 1024;
dfa_ctl = DFA_FB_STRIDE_1k;
}
/* Set up framebuffer definition */
wid_tiles = (var->xres_virtual + 63) >> 6;
/* XXX add proper FB allocation here someday */
writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0);
writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres);
/* Set up framebuffer access by CPU */
pixfmt = par->pixfmt;
dfa_ctl |= DFA_FB_ENABLE | pixfmt;
writereg(par, DFA_FB_A, dfa_ctl);
/*
* Set up window attribute table.
* We set all WAT entries the same so it doesn't matter what the
* window ID (WID) plane contains.
*/
for (i = 0; i < 32; ++i) {
writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]);
writereg(par, WAT_CMAP_OFFSET + (i << 4), 0);
writereg(par, WAT_CTRL + (i << 4), 0);
writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE);
}
/* Set sync polarity etc. */
ctrlreg = readreg(par, SYNC_CTL) &
~(SYNC_CTL_SYNC_ON_RGB | SYNC_CTL_HSYNC_INV |
SYNC_CTL_VSYNC_INV);
if (var->sync & FB_SYNC_ON_GREEN)
ctrlreg |= SYNC_CTL_SYNC_ON_RGB;
if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
ctrlreg |= SYNC_CTL_HSYNC_INV;
if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
ctrlreg |= SYNC_CTL_VSYNC_INV;
writereg(par, SYNC_CTL, ctrlreg);
info->fix.line_length = stride * pixsize[pixfmt];
info->fix.visual = (pixfmt == DFA_PIX_8BIT)? FB_VISUAL_PSEUDOCOLOR:
FB_VISUAL_DIRECTCOLOR;
return 0;
}
static int gxt4500_setcolreg(unsigned int reg, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
u32 cmap_entry;
struct gxt4500_par *par = info->par;
if (reg > 1023)
return 1;
cmap_entry = ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
(green & 0xff00) | (blue >> 8);
writereg(par, CMAP + reg * 4, cmap_entry);
if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) {
u32 *pal = info->pseudo_palette;
u32 val = reg;
switch (par->pixfmt) {
case DFA_PIX_16BIT_565:
val |= (reg << 11) | (reg << 5);
break;
case DFA_PIX_16BIT_1555:
val |= (reg << 10) | (reg << 5);
break;
case DFA_PIX_32BIT:
val |= (reg << 24);
fallthrough;
case DFA_PIX_24BIT:
val |= (reg << 16) | (reg << 8);
break;
}
pal[reg] = val;
}
return 0;
}
static int gxt4500_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct gxt4500_par *par = info->par;
if (var->xoffset & 7)
return -EINVAL;
if (var->xoffset + info->var.xres > info->var.xres_virtual ||
var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset);
return 0;
}
static int gxt4500_blank(int blank, struct fb_info *info)
{
struct gxt4500_par *par = info->par;
int ctrl, dctl;
ctrl = readreg(par, SYNC_CTL);
ctrl &= ~(SYNC_CTL_SYNC_OFF | SYNC_CTL_HSYNC_OFF | SYNC_CTL_VSYNC_OFF);
dctl = readreg(par, DISP_CTL);
dctl |= DISP_CTL_OFF;
switch (blank) {
case FB_BLANK_UNBLANK:
dctl &= ~DISP_CTL_OFF;
break;
case FB_BLANK_POWERDOWN:
ctrl |= SYNC_CTL_SYNC_OFF;
break;
case FB_BLANK_HSYNC_SUSPEND:
ctrl |= SYNC_CTL_HSYNC_OFF;
break;
case FB_BLANK_VSYNC_SUSPEND:
ctrl |= SYNC_CTL_VSYNC_OFF;
break;
default: ;
}
writereg(par, SYNC_CTL, ctrl);
writereg(par, DISP_CTL, dctl);
return 0;
}
static const struct fb_fix_screeninfo gxt4500_fix = {
.id = "IBM GXT4500P",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 8,
.ypanstep = 1,
.mmio_len = 0x20000,
};
static const struct fb_ops gxt4500_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = gxt4500_check_var,
.fb_set_par = gxt4500_set_par,
.fb_setcolreg = gxt4500_setcolreg,
.fb_pan_display = gxt4500_pan_display,
.fb_blank = gxt4500_blank,
};
/* PCI functions */
static int gxt4500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
int err;
unsigned long reg_phys, fb_phys;
struct gxt4500_par *par;
struct fb_info *info;
struct fb_var_screeninfo var;
enum gxt_cards cardtype;
err = aperture_remove_conflicting_pci_devices(pdev, "gxt4500fb");
if (err)
return err;
err = pci_enable_device(pdev);
if (err) {
dev_err(&pdev->dev, "gxt4500: cannot enable PCI device: %d\n",
err);
return err;
}
reg_phys = pci_resource_start(pdev, 0);
if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0),
"gxt4500 regs")) {
dev_err(&pdev->dev, "gxt4500: cannot get registers\n");
goto err_nodev;
}
fb_phys = pci_resource_start(pdev, 1);
if (!request_mem_region(fb_phys, pci_resource_len(pdev, 1),
"gxt4500 FB")) {
dev_err(&pdev->dev, "gxt4500: cannot get framebuffer\n");
goto err_free_regs;
}
info = framebuffer_alloc(sizeof(struct gxt4500_par), &pdev->dev);
if (!info)
goto err_free_fb;
par = info->par;
cardtype = ent->driver_data;
par->refclk_ps = cardinfo[cardtype].refclk_ps;
info->fix = gxt4500_fix;
strscpy(info->fix.id, cardinfo[cardtype].cardname,
sizeof(info->fix.id));
info->pseudo_palette = par->pseudo_palette;
info->fix.mmio_start = reg_phys;
par->regs = pci_ioremap_bar(pdev, 0);
if (!par->regs) {
dev_err(&pdev->dev, "gxt4500: cannot map registers\n");
goto err_free_all;
}
info->fix.smem_start = fb_phys;
info->fix.smem_len = pci_resource_len(pdev, 1);
info->screen_base = pci_ioremap_wc_bar(pdev, 1);
if (!info->screen_base) {
dev_err(&pdev->dev, "gxt4500: cannot map framebuffer\n");
goto err_unmap_regs;
}
pci_set_drvdata(pdev, info);
par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
info->fix.smem_len);
#ifdef __BIG_ENDIAN
/* Set byte-swapping for DFA aperture for all pixel sizes */
pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300);
#else /* __LITTLE_ENDIAN */
/* not sure what this means but fgl23 driver does that */
pci_write_config_dword(pdev, CFG_ENDIAN0, 0x2300);
/* pci_write_config_dword(pdev, CFG_ENDIAN0 + 4, 0x400000);*/
pci_write_config_dword(pdev, CFG_ENDIAN0 + 8, 0x98530000);
#endif
info->fbops = &gxt4500_ops;
info->flags = FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
err = fb_alloc_cmap(&info->cmap, 256, 0);
if (err) {
dev_err(&pdev->dev, "gxt4500: cannot allocate cmap\n");
goto err_unmap_all;
}
gxt4500_blank(FB_BLANK_UNBLANK, info);
if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) {
dev_err(&pdev->dev, "gxt4500: cannot find valid video mode\n");
goto err_free_cmap;
}
info->var = var;
if (gxt4500_set_par(info)) {
printk(KERN_ERR "gxt4500: cannot set video mode\n");
goto err_free_cmap;
}
if (register_framebuffer(info) < 0) {
dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n");
goto err_free_cmap;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
err_free_cmap:
fb_dealloc_cmap(&info->cmap);
err_unmap_all:
iounmap(info->screen_base);
err_unmap_regs:
iounmap(par->regs);
err_free_all:
framebuffer_release(info);
err_free_fb:
release_mem_region(fb_phys, pci_resource_len(pdev, 1));
err_free_regs:
release_mem_region(reg_phys, pci_resource_len(pdev, 0));
err_nodev:
return -ENODEV;
}
static void gxt4500_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct gxt4500_par *par;
if (!info)
return;
par = info->par;
unregister_framebuffer(info);
arch_phys_wc_del(par->wc_cookie);
fb_dealloc_cmap(&info->cmap);
iounmap(par->regs);
iounmap(info->screen_base);
release_mem_region(pci_resource_start(pdev, 0),
pci_resource_len(pdev, 0));
release_mem_region(pci_resource_start(pdev, 1),
pci_resource_len(pdev, 1));
framebuffer_release(info);
}
/* supported chipsets */
static const struct pci_device_id gxt4500_pci_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4500P),
.driver_data = GXT4500P },
{ PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6500P),
.driver_data = GXT6500P },
{ PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4000P),
.driver_data = GXT4000P },
{ PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6000P),
.driver_data = GXT6000P },
{ 0 }
};
MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl);
static struct pci_driver gxt4500_driver = {
.name = "gxt4500",
.id_table = gxt4500_pci_tbl,
.probe = gxt4500_probe,
.remove = gxt4500_remove,
};
static int gxt4500_init(void)
{
if (fb_modesetting_disabled("gxt4500"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("gxt4500", &mode_option))
return -ENODEV;
#endif
return pci_register_driver(&gxt4500_driver);
}
module_init(gxt4500_init);
static void __exit gxt4500_exit(void)
{
pci_unregister_driver(&gxt4500_driver);
}
module_exit(gxt4500_exit);
MODULE_AUTHOR("Paul Mackerras <[email protected]>");
MODULE_DESCRIPTION("FBDev driver for IBM GXT4500P/6500P and GXT4000P/6000P");
MODULE_LICENSE("GPL");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\"");
| linux-master | drivers/video/fbdev/gxt4500.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
*
* Freescale DIU Frame Buffer device driver
*
* Authors: Hongjun Chen <[email protected]>
* Paul Widmer <[email protected]>
* Srikanth Srinivasan <[email protected]>
* York Sun <[email protected]>
*
* Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <linux/uaccess.h>
#include <linux/vmalloc.h>
#include <linux/spinlock.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <sysdev/fsl_soc.h>
#include <linux/fsl-diu-fb.h>
#include "edid.h"
#define NUM_AOIS 5 /* 1 for plane 0, 2 for planes 1 & 2 each */
/* HW cursor parameters */
#define MAX_CURS 32
/* INT_STATUS/INT_MASK field descriptions */
#define INT_VSYNC 0x01 /* Vsync interrupt */
#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
#define INT_UNDRUN 0x04 /* Under run exception interrupt */
#define INT_PARERR 0x08 /* Display parameters error interrupt */
#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
/*
* List of supported video modes
*
* The first entry is the default video mode. The remain entries are in
* order if increasing resolution and frequency. The 320x240-60 mode is
* the initial AOI for the second and third planes.
*/
static struct fb_videomode fsl_diu_mode_db[] = {
{
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 160,
.right_margin = 24,
.upper_margin = 29,
.lower_margin = 3,
.hsync_len = 136,
.vsync_len = 6,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 320,
.yres = 240,
.pixclock = 79440,
.left_margin = 16,
.right_margin = 16,
.upper_margin = 16,
.lower_margin = 5,
.hsync_len = 48,
.vsync_len = 1,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39722,
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 72,
.xres = 640,
.yres = 480,
.pixclock = 32052,
.left_margin = 128,
.right_margin = 24,
.upper_margin = 28,
.lower_margin = 9,
.hsync_len = 40,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 75,
.xres = 640,
.yres = 480,
.pixclock = 31747,
.left_margin = 120,
.right_margin = 16,
.upper_margin = 16,
.lower_margin = 1,
.hsync_len = 64,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 90,
.xres = 640,
.yres = 480,
.pixclock = 25057,
.left_margin = 120,
.right_margin = 32,
.upper_margin = 14,
.lower_margin = 25,
.hsync_len = 40,
.vsync_len = 14,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 100,
.xres = 640,
.yres = 480,
.pixclock = 22272,
.left_margin = 48,
.right_margin = 32,
.upper_margin = 17,
.lower_margin = 22,
.hsync_len = 128,
.vsync_len = 12,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 33805,
.left_margin = 96,
.right_margin = 24,
.upper_margin = 10,
.lower_margin = 3,
.hsync_len = 72,
.vsync_len = 7,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.left_margin = 88,
.right_margin = 40,
.upper_margin = 23,
.lower_margin = 1,
.hsync_len = 128,
.vsync_len = 4,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 854,
.yres = 480,
.pixclock = 31518,
.left_margin = 104,
.right_margin = 16,
.upper_margin = 13,
.lower_margin = 1,
.hsync_len = 88,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 70,
.xres = 1024,
.yres = 768,
.pixclock = 16886,
.left_margin = 3,
.right_margin = 3,
.upper_margin = 2,
.lower_margin = 2,
.hsync_len = 40,
.vsync_len = 18,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 75,
.xres = 1024,
.yres = 768,
.pixclock = 15009,
.left_margin = 3,
.right_margin = 3,
.upper_margin = 2,
.lower_margin = 2,
.hsync_len = 80,
.vsync_len = 32,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 1280,
.yres = 480,
.pixclock = 18939,
.left_margin = 353,
.right_margin = 47,
.upper_margin = 39,
.lower_margin = 4,
.hsync_len = 8,
.vsync_len = 2,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 1280,
.yres = 720,
.pixclock = 13426,
.left_margin = 192,
.right_margin = 64,
.upper_margin = 22,
.lower_margin = 1,
.hsync_len = 136,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 1280,
.yres = 1024,
.pixclock = 9375,
.left_margin = 38,
.right_margin = 128,
.upper_margin = 2,
.lower_margin = 7,
.hsync_len = 216,
.vsync_len = 37,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 70,
.xres = 1280,
.yres = 1024,
.pixclock = 9380,
.left_margin = 6,
.right_margin = 6,
.upper_margin = 4,
.lower_margin = 4,
.hsync_len = 60,
.vsync_len = 94,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 75,
.xres = 1280,
.yres = 1024,
.pixclock = 9380,
.left_margin = 6,
.right_margin = 6,
.upper_margin = 4,
.lower_margin = 4,
.hsync_len = 60,
.vsync_len = 15,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
{
.refresh = 60,
.xres = 1920,
.yres = 1080,
.pixclock = 5787,
.left_margin = 328,
.right_margin = 120,
.upper_margin = 34,
.lower_margin = 1,
.hsync_len = 208,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
},
};
static char *fb_mode;
static unsigned long default_bpp = 32;
static enum fsl_diu_monitor_port monitor_port;
static char *monitor_string;
#if defined(CONFIG_NOT_COHERENT_CACHE)
static u8 *coherence_data;
static size_t coherence_data_size;
static unsigned int d_cache_line_size;
#endif
static DEFINE_SPINLOCK(diu_lock);
enum mfb_index {
PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */
PLANE1_AOI0, /* Plane 1, first AOI */
PLANE1_AOI1, /* Plane 1, second AOI */
PLANE2_AOI0, /* Plane 2, first AOI */
PLANE2_AOI1, /* Plane 2, second AOI */
};
struct mfb_info {
enum mfb_index index;
char *id;
int registered;
unsigned long pseudo_palette[16];
struct diu_ad *ad;
unsigned char g_alpha;
unsigned int count;
int x_aoi_d; /* aoi display x offset to physical screen */
int y_aoi_d; /* aoi display y offset to physical screen */
struct fsl_diu_data *parent;
};
/**
* struct fsl_diu_data - per-DIU data structure
* @dma_addr: DMA address of this structure
* @fsl_diu_info: fb_info objects, one per AOI
* @dev_attr: sysfs structure
* @irq: IRQ
* @monitor_port: the monitor port this DIU is connected to
* @diu_reg: pointer to the DIU hardware registers
* @reg_lock: spinlock for register access
* @dummy_aoi: video buffer for the 4x4 32-bit dummy AOI
* dummy_ad: DIU Area Descriptor for the dummy AOI
* @ad[]: Area Descriptors for each real AOI
* @gamma: gamma color table
* @cursor: hardware cursor data
* @blank_cursor: blank cursor for hiding cursor
* @next_cursor: scratch space to build load cursor
* @edid_data: EDID information buffer
* @has_edid: whether or not the EDID buffer is valid
*
* This data structure must be allocated with 32-byte alignment, so that the
* internal fields can be aligned properly.
*/
struct fsl_diu_data {
dma_addr_t dma_addr;
struct fb_info fsl_diu_info[NUM_AOIS];
struct mfb_info mfb[NUM_AOIS];
struct device_attribute dev_attr;
unsigned int irq;
enum fsl_diu_monitor_port monitor_port;
struct diu __iomem *diu_reg;
spinlock_t reg_lock;
u8 dummy_aoi[4 * 4 * 4];
struct diu_ad dummy_ad __aligned(8);
struct diu_ad ad[NUM_AOIS] __aligned(8);
u8 gamma[256 * 3] __aligned(32);
/* It's easier to parse the cursor data as little-endian */
__le16 cursor[MAX_CURS * MAX_CURS] __aligned(32);
/* Blank cursor data -- used to hide the cursor */
__le16 blank_cursor[MAX_CURS * MAX_CURS] __aligned(32);
/* Scratch cursor data -- used to build new cursor */
__le16 next_cursor[MAX_CURS * MAX_CURS] __aligned(32);
uint8_t edid_data[EDID_LENGTH];
bool has_edid;
} __aligned(32);
/* Determine the DMA address of a member of the fsl_diu_data structure */
#define DMA_ADDR(p, f) ((p)->dma_addr + offsetof(struct fsl_diu_data, f))
static const struct mfb_info mfb_template[] = {
{
.index = PLANE0,
.id = "Panel0",
.registered = 0,
.count = 0,
.x_aoi_d = 0,
.y_aoi_d = 0,
},
{
.index = PLANE1_AOI0,
.id = "Panel1 AOI0",
.registered = 0,
.g_alpha = 0xff,
.count = 0,
.x_aoi_d = 0,
.y_aoi_d = 0,
},
{
.index = PLANE1_AOI1,
.id = "Panel1 AOI1",
.registered = 0,
.g_alpha = 0xff,
.count = 0,
.x_aoi_d = 0,
.y_aoi_d = 480,
},
{
.index = PLANE2_AOI0,
.id = "Panel2 AOI0",
.registered = 0,
.g_alpha = 0xff,
.count = 0,
.x_aoi_d = 640,
.y_aoi_d = 0,
},
{
.index = PLANE2_AOI1,
.id = "Panel2 AOI1",
.registered = 0,
.g_alpha = 0xff,
.count = 0,
.x_aoi_d = 640,
.y_aoi_d = 480,
},
};
#ifdef DEBUG
static void __attribute__ ((unused)) fsl_diu_dump(struct diu __iomem *hw)
{
mb();
pr_debug("DIU: desc=%08x,%08x,%08x, gamma=%08x palette=%08x "
"cursor=%08x curs_pos=%08x diu_mode=%08x bgnd=%08x "
"disp_size=%08x hsyn_para=%08x vsyn_para=%08x syn_pol=%08x "
"thresholds=%08x int_mask=%08x plut=%08x\n",
hw->desc[0], hw->desc[1], hw->desc[2], hw->gamma,
hw->palette, hw->cursor, hw->curs_pos, hw->diu_mode,
hw->bgnd, hw->disp_size, hw->hsyn_para, hw->vsyn_para,
hw->syn_pol, hw->thresholds, hw->int_mask, hw->plut);
rmb();
}
#endif
/**
* fsl_diu_name_to_port - convert a port name to a monitor port enum
*
* Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
* the enum fsl_diu_monitor_port that corresponds to that string.
*
* For compatibility with older versions, a number ("0", "1", or "2") is also
* supported.
*
* If the string is unknown, DVI is assumed.
*
* If the particular port is not supported by the platform, another port
* (platform-specific) is chosen instead.
*/
static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s)
{
enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI;
unsigned long val;
if (s) {
if (!kstrtoul(s, 10, &val) && (val <= 2))
port = (enum fsl_diu_monitor_port) val;
else if (strncmp(s, "lvds", 4) == 0)
port = FSL_DIU_PORT_LVDS;
else if (strncmp(s, "dlvds", 5) == 0)
port = FSL_DIU_PORT_DLVDS;
}
if (diu_ops.valid_monitor_port)
port = diu_ops.valid_monitor_port(port);
return port;
}
/*
* Workaround for failed writing desc register of planes.
* Needed with MPC5121 DIU rev 2.0 silicon.
*/
void wr_reg_wa(u32 *reg, u32 val)
{
do {
out_be32(reg, val);
} while (in_be32(reg) != val);
}
static void fsl_diu_enable_panel(struct fb_info *info)
{
struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
struct diu_ad *ad = mfbi->ad;
struct fsl_diu_data *data = mfbi->parent;
struct diu __iomem *hw = data->diu_reg;
switch (mfbi->index) {
case PLANE0:
wr_reg_wa(&hw->desc[0], ad->paddr);
break;
case PLANE1_AOI0:
cmfbi = &data->mfb[2];
if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
if (cmfbi->count > 0) /* AOI1 open */
ad->next_ad =
cpu_to_le32(cmfbi->ad->paddr);
else
ad->next_ad = 0;
wr_reg_wa(&hw->desc[1], ad->paddr);
}
break;
case PLANE2_AOI0:
cmfbi = &data->mfb[4];
if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
if (cmfbi->count > 0) /* AOI1 open */
ad->next_ad =
cpu_to_le32(cmfbi->ad->paddr);
else
ad->next_ad = 0;
wr_reg_wa(&hw->desc[2], ad->paddr);
}
break;
case PLANE1_AOI1:
pmfbi = &data->mfb[1];
ad->next_ad = 0;
if (hw->desc[1] == data->dummy_ad.paddr)
wr_reg_wa(&hw->desc[1], ad->paddr);
else /* AOI0 open */
pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
break;
case PLANE2_AOI1:
pmfbi = &data->mfb[3];
ad->next_ad = 0;
if (hw->desc[2] == data->dummy_ad.paddr)
wr_reg_wa(&hw->desc[2], ad->paddr);
else /* AOI0 was open */
pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
break;
}
}
static void fsl_diu_disable_panel(struct fb_info *info)
{
struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
struct diu_ad *ad = mfbi->ad;
struct fsl_diu_data *data = mfbi->parent;
struct diu __iomem *hw = data->diu_reg;
switch (mfbi->index) {
case PLANE0:
wr_reg_wa(&hw->desc[0], 0);
break;
case PLANE1_AOI0:
cmfbi = &data->mfb[2];
if (cmfbi->count > 0) /* AOI1 is open */
wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
/* move AOI1 to the first */
else /* AOI1 was closed */
wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
/* close AOI 0 */
break;
case PLANE2_AOI0:
cmfbi = &data->mfb[4];
if (cmfbi->count > 0) /* AOI1 is open */
wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
/* move AOI1 to the first */
else /* AOI1 was closed */
wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
/* close AOI 0 */
break;
case PLANE1_AOI1:
pmfbi = &data->mfb[1];
if (hw->desc[1] != ad->paddr) {
/* AOI1 is not the first in the chain */
if (pmfbi->count > 0)
/* AOI0 is open, must be the first */
pmfbi->ad->next_ad = 0;
} else /* AOI1 is the first in the chain */
wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
/* close AOI 1 */
break;
case PLANE2_AOI1:
pmfbi = &data->mfb[3];
if (hw->desc[2] != ad->paddr) {
/* AOI1 is not the first in the chain */
if (pmfbi->count > 0)
/* AOI0 is open, must be the first */
pmfbi->ad->next_ad = 0;
} else /* AOI1 is the first in the chain */
wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
/* close AOI 1 */
break;
}
}
static void enable_lcdc(struct fb_info *info)
{
struct mfb_info *mfbi = info->par;
struct fsl_diu_data *data = mfbi->parent;
struct diu __iomem *hw = data->diu_reg;
out_be32(&hw->diu_mode, MFB_MODE1);
}
static void disable_lcdc(struct fb_info *info)
{
struct mfb_info *mfbi = info->par;
struct fsl_diu_data *data = mfbi->parent;
struct diu __iomem *hw = data->diu_reg;
out_be32(&hw->diu_mode, 0);
}
static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
struct fsl_diu_data *data = mfbi->parent;
int available_height, upper_aoi_bottom;
enum mfb_index index = mfbi->index;
int lower_aoi_is_open, upper_aoi_is_open;
__u32 base_plane_width, base_plane_height, upper_aoi_height;
base_plane_width = data->fsl_diu_info[0].var.xres;
base_plane_height = data->fsl_diu_info[0].var.yres;
if (mfbi->x_aoi_d < 0)
mfbi->x_aoi_d = 0;
if (mfbi->y_aoi_d < 0)
mfbi->y_aoi_d = 0;
switch (index) {
case PLANE0:
if (mfbi->x_aoi_d != 0)
mfbi->x_aoi_d = 0;
if (mfbi->y_aoi_d != 0)
mfbi->y_aoi_d = 0;
break;
case PLANE1_AOI0:
case PLANE2_AOI0:
lower_aoi_mfbi = data->fsl_diu_info[index+1].par;
lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
if (var->xres > base_plane_width)
var->xres = base_plane_width;
if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
mfbi->x_aoi_d = base_plane_width - var->xres;
if (lower_aoi_is_open)
available_height = lower_aoi_mfbi->y_aoi_d;
else
available_height = base_plane_height;
if (var->yres > available_height)
var->yres = available_height;
if ((mfbi->y_aoi_d + var->yres) > available_height)
mfbi->y_aoi_d = available_height - var->yres;
break;
case PLANE1_AOI1:
case PLANE2_AOI1:
upper_aoi_mfbi = data->fsl_diu_info[index-1].par;
upper_aoi_height = data->fsl_diu_info[index-1].var.yres;
upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
if (var->xres > base_plane_width)
var->xres = base_plane_width;
if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
mfbi->x_aoi_d = base_plane_width - var->xres;
if (mfbi->y_aoi_d < 0)
mfbi->y_aoi_d = 0;
if (upper_aoi_is_open) {
if (mfbi->y_aoi_d < upper_aoi_bottom)
mfbi->y_aoi_d = upper_aoi_bottom;
available_height = base_plane_height
- upper_aoi_bottom;
} else
available_height = base_plane_height;
if (var->yres > available_height)
var->yres = available_height;
if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
mfbi->y_aoi_d = base_plane_height - var->yres;
break;
}
}
/*
* Checks to see if the hardware supports the state requested by var passed
* in. This function does not alter the hardware state! If the var passed in
* is slightly off by what the hardware can support then we alter the var
* PASSED in to what we can do. If the hardware doesn't support mode change
* a -EINVAL will be returned by the upper layers.
*/
static int fsl_diu_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
if (var->xoffset + info->var.xres > info->var.xres_virtual)
var->xoffset = info->var.xres_virtual - info->var.xres;
if (var->yoffset + info->var.yres > info->var.yres_virtual)
var->yoffset = info->var.yres_virtual - info->var.yres;
if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
(var->bits_per_pixel != 16))
var->bits_per_pixel = default_bpp;
switch (var->bits_per_pixel) {
case 16:
var->red.length = 5;
var->red.offset = 11;
var->red.msb_right = 0;
var->green.length = 6;
var->green.offset = 5;
var->green.msb_right = 0;
var->blue.length = 5;
var->blue.offset = 0;
var->blue.msb_right = 0;
var->transp.length = 0;
var->transp.offset = 0;
var->transp.msb_right = 0;
break;
case 24:
var->red.length = 8;
var->red.offset = 0;
var->red.msb_right = 0;
var->green.length = 8;
var->green.offset = 8;
var->green.msb_right = 0;
var->blue.length = 8;
var->blue.offset = 16;
var->blue.msb_right = 0;
var->transp.length = 0;
var->transp.offset = 0;
var->transp.msb_right = 0;
break;
case 32:
var->red.length = 8;
var->red.offset = 16;
var->red.msb_right = 0;
var->green.length = 8;
var->green.offset = 8;
var->green.msb_right = 0;
var->blue.length = 8;
var->blue.offset = 0;
var->blue.msb_right = 0;
var->transp.length = 8;
var->transp.offset = 24;
var->transp.msb_right = 0;
break;
}
var->height = -1;
var->width = -1;
var->grayscale = 0;
/* Copy nonstd field to/from sync for fbset usage */
var->sync |= var->nonstd;
var->nonstd |= var->sync;
adjust_aoi_size_position(var, info);
return 0;
}
static void set_fix(struct fb_info *info)
{
struct fb_fix_screeninfo *fix = &info->fix;
struct fb_var_screeninfo *var = &info->var;
struct mfb_info *mfbi = info->par;
strncpy(fix->id, mfbi->id, sizeof(fix->id));
fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
fix->type = FB_TYPE_PACKED_PIXELS;
fix->accel = FB_ACCEL_NONE;
fix->visual = FB_VISUAL_TRUECOLOR;
fix->xpanstep = 1;
fix->ypanstep = 1;
}
static void update_lcdc(struct fb_info *info)
{
struct fb_var_screeninfo *var = &info->var;
struct mfb_info *mfbi = info->par;
struct fsl_diu_data *data = mfbi->parent;
struct diu __iomem *hw;
int i, j;
u8 *gamma_table_base;
u32 temp;
hw = data->diu_reg;
if (diu_ops.set_monitor_port)
diu_ops.set_monitor_port(data->monitor_port);
gamma_table_base = data->gamma;
/* Prep for DIU init - gamma table, cursor table */
for (i = 0; i <= 2; i++)
for (j = 0; j <= 255; j++)
*gamma_table_base++ = j;
if (diu_ops.set_gamma_table)
diu_ops.set_gamma_table(data->monitor_port, data->gamma);
disable_lcdc(info);
/* Program DIU registers */
out_be32(&hw->gamma, DMA_ADDR(data, gamma));
out_be32(&hw->bgnd, 0x007F7F7F); /* Set background to grey */
out_be32(&hw->disp_size, (var->yres << 16) | var->xres);
/* Horizontal and vertical configuration register */
temp = var->left_margin << 22 | /* BP_H */
var->hsync_len << 11 | /* PW_H */
var->right_margin; /* FP_H */
out_be32(&hw->hsyn_para, temp);
temp = var->upper_margin << 22 | /* BP_V */
var->vsync_len << 11 | /* PW_V */
var->lower_margin; /* FP_V */
out_be32(&hw->vsyn_para, temp);
diu_ops.set_pixel_clock(var->pixclock);
#ifndef CONFIG_PPC_MPC512x
/*
* The PLUT register is defined differently on the MPC5121 than it
* is on other SOCs. Unfortunately, there's no documentation that
* explains how it's supposed to be programmed, so for now, we leave
* it at the default value on the MPC5121.
*
* For other SOCs, program it for the highest priority, which will
* reduce the chance of underrun. Technically, we should scale the
* priority to match the screen resolution, but doing that properly
* requires delicate fine-tuning for each use-case.
*/
out_be32(&hw->plut, 0x01F5F666);
#endif
/* Enable the DIU */
enable_lcdc(info);
}
static int map_video_memory(struct fb_info *info)
{
u32 smem_len = info->fix.line_length * info->var.yres_virtual;
void *p;
p = alloc_pages_exact(smem_len, GFP_DMA | __GFP_ZERO);
if (!p) {
fb_err(info, "unable to allocate fb memory\n");
return -ENOMEM;
}
mutex_lock(&info->mm_lock);
info->screen_base = p;
info->fix.smem_start = virt_to_phys(info->screen_base);
info->fix.smem_len = smem_len;
mutex_unlock(&info->mm_lock);
info->screen_size = info->fix.smem_len;
return 0;
}
static void unmap_video_memory(struct fb_info *info)
{
void *p = info->screen_base;
size_t l = info->fix.smem_len;
mutex_lock(&info->mm_lock);
info->screen_base = NULL;
info->fix.smem_start = 0;
info->fix.smem_len = 0;
mutex_unlock(&info->mm_lock);
if (p)
free_pages_exact(p, l);
}
/*
* Using the fb_var_screeninfo in fb_info we set the aoi of this
* particular framebuffer. It is a light version of fsl_diu_set_par.
*/
static int fsl_diu_set_aoi(struct fb_info *info)
{
struct fb_var_screeninfo *var = &info->var;
struct mfb_info *mfbi = info->par;
struct diu_ad *ad = mfbi->ad;
/* AOI should not be greater than display size */
ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
return 0;
}
/**
* fsl_diu_get_pixel_format: return the pixel format for a given color depth
*
* The pixel format is a 32-bit value that determine which bits in each
* pixel are to be used for each color. This is the default function used
* if the platform does not define its own version.
*/
static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
{
#define PF_BYTE_F 0x10000000
#define PF_ALPHA_C_MASK 0x0E000000
#define PF_ALPHA_C_SHIFT 25
#define PF_BLUE_C_MASK 0x01800000
#define PF_BLUE_C_SHIFT 23
#define PF_GREEN_C_MASK 0x00600000
#define PF_GREEN_C_SHIFT 21
#define PF_RED_C_MASK 0x00180000
#define PF_RED_C_SHIFT 19
#define PF_PALETTE 0x00040000
#define PF_PIXEL_S_MASK 0x00030000
#define PF_PIXEL_S_SHIFT 16
#define PF_COMP_3_MASK 0x0000F000
#define PF_COMP_3_SHIFT 12
#define PF_COMP_2_MASK 0x00000F00
#define PF_COMP_2_SHIFT 8
#define PF_COMP_1_MASK 0x000000F0
#define PF_COMP_1_SHIFT 4
#define PF_COMP_0_MASK 0x0000000F
#define PF_COMP_0_SHIFT 0
#define MAKE_PF(alpha, red, green, blue, size, c0, c1, c2, c3) \
cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \
(blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \
(red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \
(c2 << PF_COMP_2_SHIFT) | (c1 << PF_COMP_1_SHIFT) | \
(c0 << PF_COMP_0_SHIFT) | (size << PF_PIXEL_S_SHIFT))
switch (bits_per_pixel) {
case 32:
/* 0x88883316 */
return MAKE_PF(3, 2, 1, 0, 3, 8, 8, 8, 8);
case 24:
/* 0x88082219 */
return MAKE_PF(4, 0, 1, 2, 2, 8, 8, 8, 0);
case 16:
/* 0x65053118 */
return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0);
default:
pr_err("fsl-diu: unsupported color depth %u\n", bits_per_pixel);
return 0;
}
}
/*
* Copies a cursor image from user space to the proper place in driver
* memory so that the hardware can display the cursor image.
*
* Cursor data is represented as a sequence of 'width' bits packed into bytes.
* That is, the first 8 bits are in the first byte, the second 8 bits in the
* second byte, and so on. Therefore, the each row of the cursor is (width +
* 7) / 8 bytes of 'data'
*
* The DIU only supports cursors up to 32x32 (MAX_CURS). We reject cursors
* larger than this, so we already know that 'width' <= 32. Therefore, we can
* simplify our code by using a 32-bit big-endian integer ("line") to read in
* a single line of pixels, and only look at the top 'width' bits of that
* integer.
*
* This could result in an unaligned 32-bit read. For example, if the cursor
* is 24x24, then the first three bytes of 'image' contain the pixel data for
* the top line of the cursor. We do a 32-bit read of 'image', but we look
* only at the top 24 bits. Then we increment 'image' by 3 bytes. The next
* read is unaligned. The only problem is that we might read past the end of
* 'image' by 1-3 bytes, but that should not cause any problems.
*/
static void fsl_diu_load_cursor_image(struct fb_info *info,
const void *image, uint16_t bg, uint16_t fg,
unsigned int width, unsigned int height)
{
struct mfb_info *mfbi = info->par;
struct fsl_diu_data *data = mfbi->parent;
__le16 *cursor = data->cursor;
__le16 _fg = cpu_to_le16(fg);
__le16 _bg = cpu_to_le16(bg);
unsigned int h, w;
for (h = 0; h < height; h++) {
uint32_t mask = 1 << 31;
uint32_t line = be32_to_cpup(image);
for (w = 0; w < width; w++) {
cursor[w] = (line & mask) ? _fg : _bg;
mask >>= 1;
}
cursor += MAX_CURS;
image += DIV_ROUND_UP(width, 8);
}
}
/*
* Set a hardware cursor. The image data for the cursor is passed via the
* fb_cursor object.
*/
static int fsl_diu_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct mfb_info *mfbi = info->par;
struct fsl_diu_data *data = mfbi->parent;
struct diu __iomem *hw = data->diu_reg;
if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
return -EINVAL;
/* The cursor size has changed */
if (cursor->set & FB_CUR_SETSIZE) {
/*
* The DIU cursor is a fixed size, so when we get this
* message, instead of resizing the cursor, we just clear
* all the image data, in expectation of new data. However,
* in tests this control does not appear to be normally
* called.
*/
memset(data->cursor, 0, sizeof(data->cursor));
}
/* The cursor position has changed (cursor->image.dx|dy) */
if (cursor->set & FB_CUR_SETPOS) {
uint32_t xx, yy;
yy = (cursor->image.dy - info->var.yoffset) & 0x7ff;
xx = (cursor->image.dx - info->var.xoffset) & 0x7ff;
out_be32(&hw->curs_pos, yy << 16 | xx);
}
/*
* FB_CUR_SETIMAGE - the cursor image has changed
* FB_CUR_SETCMAP - the cursor colors has changed
* FB_CUR_SETSHAPE - the cursor bitmask has changed
*/
if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
/*
* Determine the size of the cursor image data. Normally,
* it's 8x16.
*/
unsigned int image_size =
DIV_ROUND_UP(cursor->image.width, 8) *
cursor->image.height;
unsigned int image_words =
DIV_ROUND_UP(image_size, sizeof(uint32_t));
unsigned int bg_idx = cursor->image.bg_color;
unsigned int fg_idx = cursor->image.fg_color;
uint32_t *image, *source, *mask;
uint16_t fg, bg;
unsigned int i;
if (info->state != FBINFO_STATE_RUNNING)
return 0;
bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
((info->cmap.green[bg_idx] & 0xf8) << 2) |
((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1 << 15;
fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
((info->cmap.green[fg_idx] & 0xf8) << 2) |
((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1 << 15;
/* Use 32-bit operations on the data to improve performance */
image = (uint32_t *)data->next_cursor;
source = (uint32_t *)cursor->image.data;
mask = (uint32_t *)cursor->mask;
if (cursor->rop == ROP_XOR)
for (i = 0; i < image_words; i++)
image[i] = source[i] ^ mask[i];
else
for (i = 0; i < image_words; i++)
image[i] = source[i] & mask[i];
fsl_diu_load_cursor_image(info, image, bg, fg,
cursor->image.width, cursor->image.height);
}
/*
* Show or hide the cursor. The cursor data is always stored in the
* 'cursor' memory block, and the actual cursor position is always in
* the DIU's CURS_POS register. To hide the cursor, we redirect the
* CURSOR register to a blank cursor. The show the cursor, we
* redirect the CURSOR register to the real cursor data.
*/
if (cursor->enable)
out_be32(&hw->cursor, DMA_ADDR(data, cursor));
else
out_be32(&hw->cursor, DMA_ADDR(data, blank_cursor));
return 0;
}
/*
* Using the fb_var_screeninfo in fb_info we set the resolution of this
* particular framebuffer. This function alters the fb_fix_screeninfo stored
* in fb_info. It does not alter var in fb_info since we are using that
* data. This means we depend on the data in var inside fb_info to be
* supported by the hardware. fsl_diu_check_var is always called before
* fsl_diu_set_par to ensure this.
*/
static int fsl_diu_set_par(struct fb_info *info)
{
unsigned long len;
struct fb_var_screeninfo *var = &info->var;
struct mfb_info *mfbi = info->par;
struct fsl_diu_data *data = mfbi->parent;
struct diu_ad *ad = mfbi->ad;
struct diu __iomem *hw;
hw = data->diu_reg;
set_fix(info);
len = info->var.yres_virtual * info->fix.line_length;
/* Alloc & dealloc each time resolution/bpp change */
if (len != info->fix.smem_len) {
if (info->fix.smem_start)
unmap_video_memory(info);
/* Memory allocation for framebuffer */
if (map_video_memory(info)) {
fb_err(info, "unable to allocate fb memory 1\n");
return -ENOMEM;
}
}
if (diu_ops.get_pixel_format)
ad->pix_fmt = diu_ops.get_pixel_format(data->monitor_port,
var->bits_per_pixel);
else
ad->pix_fmt = fsl_diu_get_pixel_format(var->bits_per_pixel);
ad->addr = cpu_to_le32(info->fix.smem_start);
ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
var->xres_virtual) | mfbi->g_alpha;
/* AOI should not be greater than display size */
ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
/* Disable chroma keying function */
ad->ckmax_r = 0;
ad->ckmax_g = 0;
ad->ckmax_b = 0;
ad->ckmin_r = 255;
ad->ckmin_g = 255;
ad->ckmin_b = 255;
if (mfbi->index == PLANE0)
update_lcdc(info);
return 0;
}
static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
{
return ((val << width) + 0x7FFF - val) >> 16;
}
/*
* Set a single color register. The values supplied have a 16 bit magnitude
* which needs to be scaled in this function for the hardware. Things to take
* into consideration are how many color registers, if any, are supported with
* the current color visual. With truecolor mode no color palettes are
* supported. Here a pseudo palette is created which we store the value in
* pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
* color palette.
*/
static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
int ret = 1;
/*
* If greyscale is true, then we convert the RGB value
* to greyscale no matter what visual we are using.
*/
if (info->var.grayscale)
red = green = blue = (19595 * red + 38470 * green +
7471 * blue) >> 16;
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
/*
* 16-bit True Colour. We encode the RGB value
* according to the RGB bitfield information.
*/
if (regno < 16) {
u32 *pal = info->pseudo_palette;
u32 v;
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
transp = CNVT_TOHW(transp, info->var.transp.length);
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
pal[regno] = v;
ret = 0;
}
break;
}
return ret;
}
/*
* Pan (or wrap, depending on the `vmode' field) the display using the
* 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
* don't fit, return -EINVAL.
*/
static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if ((info->var.xoffset == var->xoffset) &&
(info->var.yoffset == var->yoffset))
return 0; /* No change, do nothing */
if (var->xoffset + info->var.xres > info->var.xres_virtual
|| var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP)
info->var.vmode |= FB_VMODE_YWRAP;
else
info->var.vmode &= ~FB_VMODE_YWRAP;
fsl_diu_set_aoi(info);
return 0;
}
static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct mfb_info *mfbi = info->par;
struct diu_ad *ad = mfbi->ad;
struct mfb_chroma_key ck;
unsigned char global_alpha;
struct aoi_display_offset aoi_d;
__u32 pix_fmt;
void __user *buf = (void __user *)arg;
if (!arg)
return -EINVAL;
fb_dbg(info, "ioctl %08x (dir=%s%s type=%u nr=%u size=%u)\n", cmd,
_IOC_DIR(cmd) & _IOC_READ ? "R" : "",
_IOC_DIR(cmd) & _IOC_WRITE ? "W" : "",
_IOC_TYPE(cmd), _IOC_NR(cmd), _IOC_SIZE(cmd));
switch (cmd) {
case MFB_SET_PIXFMT_OLD:
fb_warn(info,
"MFB_SET_PIXFMT value of 0x%08x is deprecated.\n",
MFB_SET_PIXFMT_OLD);
fallthrough;
case MFB_SET_PIXFMT:
if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
return -EFAULT;
ad->pix_fmt = pix_fmt;
break;
case MFB_GET_PIXFMT_OLD:
fb_warn(info,
"MFB_GET_PIXFMT value of 0x%08x is deprecated.\n",
MFB_GET_PIXFMT_OLD);
fallthrough;
case MFB_GET_PIXFMT:
pix_fmt = ad->pix_fmt;
if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
return -EFAULT;
break;
case MFB_SET_AOID:
if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
return -EFAULT;
mfbi->x_aoi_d = aoi_d.x_aoi_d;
mfbi->y_aoi_d = aoi_d.y_aoi_d;
fsl_diu_check_var(&info->var, info);
fsl_diu_set_aoi(info);
break;
case MFB_GET_AOID:
aoi_d.x_aoi_d = mfbi->x_aoi_d;
aoi_d.y_aoi_d = mfbi->y_aoi_d;
if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
return -EFAULT;
break;
case MFB_GET_ALPHA:
global_alpha = mfbi->g_alpha;
if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
return -EFAULT;
break;
case MFB_SET_ALPHA:
/* set panel information */
if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
return -EFAULT;
ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
(global_alpha & 0xff);
mfbi->g_alpha = global_alpha;
break;
case MFB_SET_CHROMA_KEY:
/* set panel winformation */
if (copy_from_user(&ck, buf, sizeof(ck)))
return -EFAULT;
if (ck.enable &&
(ck.red_max < ck.red_min ||
ck.green_max < ck.green_min ||
ck.blue_max < ck.blue_min))
return -EINVAL;
if (!ck.enable) {
ad->ckmax_r = 0;
ad->ckmax_g = 0;
ad->ckmax_b = 0;
ad->ckmin_r = 255;
ad->ckmin_g = 255;
ad->ckmin_b = 255;
} else {
ad->ckmax_r = ck.red_max;
ad->ckmax_g = ck.green_max;
ad->ckmax_b = ck.blue_max;
ad->ckmin_r = ck.red_min;
ad->ckmin_g = ck.green_min;
ad->ckmin_b = ck.blue_min;
}
break;
#ifdef CONFIG_PPC_MPC512x
case MFB_SET_GAMMA: {
struct fsl_diu_data *data = mfbi->parent;
if (copy_from_user(data->gamma, buf, sizeof(data->gamma)))
return -EFAULT;
setbits32(&data->diu_reg->gamma, 0); /* Force table reload */
break;
}
case MFB_GET_GAMMA: {
struct fsl_diu_data *data = mfbi->parent;
if (copy_to_user(buf, data->gamma, sizeof(data->gamma)))
return -EFAULT;
break;
}
#endif
default:
fb_err(info, "unknown ioctl command (0x%08X)\n", cmd);
return -ENOIOCTLCMD;
}
return 0;
}
static inline void fsl_diu_enable_interrupts(struct fsl_diu_data *data)
{
u32 int_mask = INT_UNDRUN; /* enable underrun detection */
if (IS_ENABLED(CONFIG_NOT_COHERENT_CACHE))
int_mask |= INT_VSYNC; /* enable vertical sync */
clrbits32(&data->diu_reg->int_mask, int_mask);
}
/* turn on fb if count == 1
*/
static int fsl_diu_open(struct fb_info *info, int user)
{
struct mfb_info *mfbi = info->par;
int res = 0;
/* free boot splash memory on first /dev/fb0 open */
if ((mfbi->index == PLANE0) && diu_ops.release_bootmem)
diu_ops.release_bootmem();
spin_lock(&diu_lock);
mfbi->count++;
if (mfbi->count == 1) {
fsl_diu_check_var(&info->var, info);
res = fsl_diu_set_par(info);
if (res < 0)
mfbi->count--;
else {
fsl_diu_enable_interrupts(mfbi->parent);
fsl_diu_enable_panel(info);
}
}
spin_unlock(&diu_lock);
return res;
}
/* turn off fb if count == 0
*/
static int fsl_diu_release(struct fb_info *info, int user)
{
struct mfb_info *mfbi = info->par;
spin_lock(&diu_lock);
mfbi->count--;
if (mfbi->count == 0) {
struct fsl_diu_data *data = mfbi->parent;
bool disable = true;
int i;
/* Disable interrupts only if all AOIs are closed */
for (i = 0; i < NUM_AOIS; i++) {
struct mfb_info *mi = data->fsl_diu_info[i].par;
if (mi->count)
disable = false;
}
if (disable)
out_be32(&data->diu_reg->int_mask, 0xffffffff);
fsl_diu_disable_panel(info);
}
spin_unlock(&diu_lock);
return 0;
}
static const struct fb_ops fsl_diu_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = fsl_diu_check_var,
.fb_set_par = fsl_diu_set_par,
.fb_setcolreg = fsl_diu_setcolreg,
.fb_pan_display = fsl_diu_pan_display,
.fb_ioctl = fsl_diu_ioctl,
.fb_open = fsl_diu_open,
.fb_release = fsl_diu_release,
.fb_cursor = fsl_diu_cursor,
};
static int install_fb(struct fb_info *info)
{
int rc;
struct mfb_info *mfbi = info->par;
struct fsl_diu_data *data = mfbi->parent;
const char *aoi_mode, *init_aoi_mode = "320x240";
struct fb_videomode *db = fsl_diu_mode_db;
unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
int has_default_mode = 1;
info->var.activate = FB_ACTIVATE_NOW;
info->fbops = &fsl_diu_ops;
info->flags = FBINFO_VIRTFB | FBINFO_PARTIAL_PAN_OK |
FBINFO_READS_FAST;
info->pseudo_palette = mfbi->pseudo_palette;
rc = fb_alloc_cmap(&info->cmap, 16, 0);
if (rc)
return rc;
if (mfbi->index == PLANE0) {
if (data->has_edid) {
/* Now build modedb from EDID */
fb_edid_to_monspecs(data->edid_data, &info->monspecs);
fb_videomode_to_modelist(info->monspecs.modedb,
info->monspecs.modedb_len,
&info->modelist);
db = info->monspecs.modedb;
dbsize = info->monspecs.modedb_len;
}
aoi_mode = fb_mode;
} else {
aoi_mode = init_aoi_mode;
}
rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL,
default_bpp);
if (!rc) {
/*
* For plane 0 we continue and look into
* driver's internal modedb.
*/
if ((mfbi->index == PLANE0) && data->has_edid)
has_default_mode = 0;
else
return -EINVAL;
}
if (!has_default_mode) {
rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp);
if (rc)
has_default_mode = 1;
}
/* Still not found, use preferred mode from database if any */
if (!has_default_mode && info->monspecs.modedb) {
struct fb_monspecs *specs = &info->monspecs;
struct fb_videomode *modedb = &specs->modedb[0];
/*
* Get preferred timing. If not found,
* first mode in database will be used.
*/
if (specs->misc & FB_MISC_1ST_DETAIL) {
int i;
for (i = 0; i < specs->modedb_len; i++) {
if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
modedb = &specs->modedb[i];
break;
}
}
}
info->var.bits_per_pixel = default_bpp;
fb_videomode_to_var(&info->var, modedb);
}
if (fsl_diu_check_var(&info->var, info)) {
fb_err(info, "fsl_diu_check_var failed\n");
unmap_video_memory(info);
fb_dealloc_cmap(&info->cmap);
return -EINVAL;
}
if (register_framebuffer(info) < 0) {
fb_err(info, "register_framebuffer failed\n");
unmap_video_memory(info);
fb_dealloc_cmap(&info->cmap);
return -EINVAL;
}
mfbi->registered = 1;
fb_info(info, "%s registered successfully\n", mfbi->id);
return 0;
}
static void uninstall_fb(struct fb_info *info)
{
struct mfb_info *mfbi = info->par;
if (!mfbi->registered)
return;
unregister_framebuffer(info);
unmap_video_memory(info);
fb_dealloc_cmap(&info->cmap);
mfbi->registered = 0;
}
static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
{
struct diu __iomem *hw = dev_id;
uint32_t status = in_be32(&hw->int_status);
if (status) {
/* This is the workaround for underrun */
if (status & INT_UNDRUN) {
out_be32(&hw->diu_mode, 0);
udelay(1);
out_be32(&hw->diu_mode, 1);
}
#if defined(CONFIG_NOT_COHERENT_CACHE)
else if (status & INT_VSYNC) {
unsigned int i;
for (i = 0; i < coherence_data_size;
i += d_cache_line_size)
__asm__ __volatile__ (
"dcbz 0, %[input]"
::[input]"r"(&coherence_data[i]));
}
#endif
return IRQ_HANDLED;
}
return IRQ_NONE;
}
#ifdef CONFIG_PM
/*
* Power management hooks. Note that we won't be called from IRQ context,
* unlike the blank functions above, so we may sleep.
*/
static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state)
{
struct fsl_diu_data *data;
data = dev_get_drvdata(&ofdev->dev);
disable_lcdc(data->fsl_diu_info);
return 0;
}
static int fsl_diu_resume(struct platform_device *ofdev)
{
struct fsl_diu_data *data;
unsigned int i;
data = dev_get_drvdata(&ofdev->dev);
fsl_diu_enable_interrupts(data);
update_lcdc(data->fsl_diu_info);
for (i = 0; i < NUM_AOIS; i++) {
if (data->mfb[i].count)
fsl_diu_enable_panel(&data->fsl_diu_info[i]);
}
return 0;
}
#else
#define fsl_diu_suspend NULL
#define fsl_diu_resume NULL
#endif /* CONFIG_PM */
static ssize_t store_monitor(struct device *device,
struct device_attribute *attr, const char *buf, size_t count)
{
enum fsl_diu_monitor_port old_monitor_port;
struct fsl_diu_data *data =
container_of(attr, struct fsl_diu_data, dev_attr);
old_monitor_port = data->monitor_port;
data->monitor_port = fsl_diu_name_to_port(buf);
if (old_monitor_port != data->monitor_port) {
/* All AOIs need adjust pixel format
* fsl_diu_set_par only change the pixsel format here
* unlikely to fail. */
unsigned int i;
for (i=0; i < NUM_AOIS; i++)
fsl_diu_set_par(&data->fsl_diu_info[i]);
}
return count;
}
static ssize_t show_monitor(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fsl_diu_data *data =
container_of(attr, struct fsl_diu_data, dev_attr);
switch (data->monitor_port) {
case FSL_DIU_PORT_DVI:
return sprintf(buf, "DVI\n");
case FSL_DIU_PORT_LVDS:
return sprintf(buf, "Single-link LVDS\n");
case FSL_DIU_PORT_DLVDS:
return sprintf(buf, "Dual-link LVDS\n");
}
return 0;
}
static int fsl_diu_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct mfb_info *mfbi;
struct fsl_diu_data *data;
dma_addr_t dma_addr; /* DMA addr of fsl_diu_data struct */
const void *prop;
unsigned int i;
int ret;
data = dmam_alloc_coherent(&pdev->dev, sizeof(struct fsl_diu_data),
&dma_addr, GFP_DMA | __GFP_ZERO);
if (!data)
return -ENOMEM;
data->dma_addr = dma_addr;
/*
* dma_alloc_coherent() uses a page allocator, so the address is
* always page-aligned. We need the memory to be 32-byte aligned,
* so that's good. However, if one day the allocator changes, we
* need to catch that. It's not worth the effort to handle unaligned
* alloctions now because it's highly unlikely to ever be a problem.
*/
if ((unsigned long)data & 31) {
dev_err(&pdev->dev, "misaligned allocation");
ret = -ENOMEM;
goto error;
}
spin_lock_init(&data->reg_lock);
for (i = 0; i < NUM_AOIS; i++) {
struct fb_info *info = &data->fsl_diu_info[i];
info->device = &pdev->dev;
info->par = &data->mfb[i];
/*
* We store the physical address of the AD in the reserved
* 'paddr' field of the AD itself.
*/
data->ad[i].paddr = DMA_ADDR(data, ad[i]);
info->fix.smem_start = 0;
/* Initialize the AOI data structure */
mfbi = info->par;
memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
mfbi->parent = data;
mfbi->ad = &data->ad[i];
}
/* Get the EDID data from the device tree, if present */
prop = of_get_property(np, "edid", &ret);
if (prop && ret == EDID_LENGTH) {
memcpy(data->edid_data, prop, EDID_LENGTH);
data->has_edid = true;
}
data->diu_reg = of_iomap(np, 0);
if (!data->diu_reg) {
dev_err(&pdev->dev, "cannot map DIU registers\n");
ret = -EFAULT;
goto error;
}
/* Get the IRQ of the DIU */
data->irq = irq_of_parse_and_map(np, 0);
if (!data->irq) {
dev_err(&pdev->dev, "could not get DIU IRQ\n");
ret = -EINVAL;
goto error;
}
data->monitor_port = monitor_port;
/* Initialize the dummy Area Descriptor */
data->dummy_ad.addr = cpu_to_le32(DMA_ADDR(data, dummy_aoi));
data->dummy_ad.pix_fmt = 0x88882317;
data->dummy_ad.src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
data->dummy_ad.aoi_size = cpu_to_le32((4 << 16) | 2);
data->dummy_ad.offset_xyi = 0;
data->dummy_ad.offset_xyd = 0;
data->dummy_ad.next_ad = 0;
data->dummy_ad.paddr = DMA_ADDR(data, dummy_ad);
/*
* Let DIU continue to display splash screen if it was pre-initialized
* by the bootloader; otherwise, clear the display.
*/
if (in_be32(&data->diu_reg->diu_mode) == MFB_MODE0)
out_be32(&data->diu_reg->desc[0], 0);
out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr);
out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr);
/*
* Older versions of U-Boot leave interrupts enabled, so disable
* all of them and clear the status register.
*/
out_be32(&data->diu_reg->int_mask, 0xffffffff);
in_be32(&data->diu_reg->int_status);
ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb",
data->diu_reg);
if (ret) {
dev_err(&pdev->dev, "could not claim irq\n");
goto error;
}
for (i = 0; i < NUM_AOIS; i++) {
ret = install_fb(&data->fsl_diu_info[i]);
if (ret) {
dev_err(&pdev->dev, "could not register fb %d\n", i);
free_irq(data->irq, data->diu_reg);
goto error;
}
}
sysfs_attr_init(&data->dev_attr.attr);
data->dev_attr.attr.name = "monitor";
data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
data->dev_attr.show = show_monitor;
data->dev_attr.store = store_monitor;
ret = device_create_file(&pdev->dev, &data->dev_attr);
if (ret) {
dev_err(&pdev->dev, "could not create sysfs file %s\n",
data->dev_attr.attr.name);
}
dev_set_drvdata(&pdev->dev, data);
return 0;
error:
for (i = 0; i < NUM_AOIS; i++)
uninstall_fb(&data->fsl_diu_info[i]);
iounmap(data->diu_reg);
return ret;
}
static void fsl_diu_remove(struct platform_device *pdev)
{
struct fsl_diu_data *data;
int i;
data = dev_get_drvdata(&pdev->dev);
disable_lcdc(&data->fsl_diu_info[0]);
free_irq(data->irq, data->diu_reg);
for (i = 0; i < NUM_AOIS; i++)
uninstall_fb(&data->fsl_diu_info[i]);
iounmap(data->diu_reg);
}
#ifndef MODULE
static int __init fsl_diu_setup(char *options)
{
char *opt;
unsigned long val;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
if (!strncmp(opt, "monitor=", 8)) {
monitor_port = fsl_diu_name_to_port(opt + 8);
} else if (!strncmp(opt, "bpp=", 4)) {
if (!kstrtoul(opt + 4, 10, &val))
default_bpp = val;
} else
fb_mode = opt;
}
return 0;
}
#endif
static const struct of_device_id fsl_diu_match[] = {
#ifdef CONFIG_PPC_MPC512x
{
.compatible = "fsl,mpc5121-diu",
},
#endif
{
.compatible = "fsl,diu",
},
{}
};
MODULE_DEVICE_TABLE(of, fsl_diu_match);
static struct platform_driver fsl_diu_driver = {
.driver = {
.name = "fsl-diu-fb",
.of_match_table = fsl_diu_match,
},
.probe = fsl_diu_probe,
.remove_new = fsl_diu_remove,
.suspend = fsl_diu_suspend,
.resume = fsl_diu_resume,
};
static int __init fsl_diu_init(void)
{
#ifdef CONFIG_NOT_COHERENT_CACHE
struct device_node *np;
const u32 *prop;
#endif
int ret;
#ifndef MODULE
char *option;
/*
* For kernel boot options (in 'video=xxxfb:<options>' format)
*/
if (fb_get_options("fslfb", &option))
return -ENODEV;
fsl_diu_setup(option);
#else
monitor_port = fsl_diu_name_to_port(monitor_string);
#endif
/*
* Must to verify set_pixel_clock. If not implement on platform,
* then that means that there is no platform support for the DIU.
*/
if (!diu_ops.set_pixel_clock)
return -ENODEV;
pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
#ifdef CONFIG_NOT_COHERENT_CACHE
np = of_get_cpu_node(0, NULL);
if (!np) {
pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
return -ENODEV;
}
prop = of_get_property(np, "d-cache-size", NULL);
if (prop == NULL) {
pr_err("fsl-diu-fb: missing 'd-cache-size' property' "
"in 'cpu' node\n");
of_node_put(np);
return -ENODEV;
}
/*
* Freescale PLRU requires 13/8 times the cache size to do a proper
* displacement flush
*/
coherence_data_size = be32_to_cpup(prop) * 13;
coherence_data_size /= 8;
pr_debug("fsl-diu-fb: coherence data size is %zu bytes\n",
coherence_data_size);
prop = of_get_property(np, "d-cache-line-size", NULL);
if (prop == NULL) {
pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' "
"in 'cpu' node\n");
of_node_put(np);
return -ENODEV;
}
d_cache_line_size = be32_to_cpup(prop);
pr_debug("fsl-diu-fb: cache lines size is %u bytes\n",
d_cache_line_size);
of_node_put(np);
coherence_data = vmalloc(coherence_data_size);
if (!coherence_data)
return -ENOMEM;
#endif
ret = platform_driver_register(&fsl_diu_driver);
if (ret) {
pr_err("fsl-diu-fb: failed to register platform driver\n");
#if defined(CONFIG_NOT_COHERENT_CACHE)
vfree(coherence_data);
#endif
}
return ret;
}
static void __exit fsl_diu_exit(void)
{
platform_driver_unregister(&fsl_diu_driver);
#if defined(CONFIG_NOT_COHERENT_CACHE)
vfree(coherence_data);
#endif
}
module_init(fsl_diu_init);
module_exit(fsl_diu_exit);
MODULE_AUTHOR("York Sun <[email protected]>");
MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
MODULE_LICENSE("GPL");
module_param_named(mode, fb_mode, charp, 0);
MODULE_PARM_DESC(mode,
"Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
module_param_named(bpp, default_bpp, ulong, 0);
MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'");
module_param_named(monitor, monitor_string, charp, 0);
MODULE_PARM_DESC(monitor, "Specify the monitor port "
"(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
| linux-master | drivers/video/fbdev/fsl-diu-fb.c |
/*
* linux/drivers/video/arcfb.c -- FB driver for Arc monochrome LCD board
*
* Copyright (C) 2005, Jaya Kumar <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
*
* This driver was written to be used with the Arc LCD board. Arc uses a
* set of KS108 chips that control individual 64x64 LCD matrices. The board
* can be paneled in a variety of setups such as 2x1=128x64, 4x4=256x256 and
* so on. The interface between the board and the host is TTL based GPIO. The
* GPIO requirements are 8 writable data lines and 4+n lines for control. On a
* GPIO-less system, the board can be tested by connecting the respective sigs
* up to a parallel port connector. The driver requires the IO addresses for
* data and control GPIO at load time. It is unable to probe for the
* existence of the LCD so it must be told at load time whether it should
* be enabled or not.
*
* Todo:
* - testing with 4x4
* - testing with interrupt hw
*
* General notes:
* - User must set tuhold. It's in microseconds. According to the 108 spec,
* the hold time is supposed to be at least 1 microsecond.
* - User must set num_cols=x num_rows=y, eg: x=2 means 128
* - User must set arcfb_enable=1 to enable it
* - User must set dio_addr=0xIOADDR cio_addr=0xIOADDR
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/arcfb.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#define floor8(a) (a&(~0x07))
#define floorXres(a,xres) (a&(~(xres - 1)))
#define iceil8(a) (((int)((a+7)/8))*8)
#define ceil64(a) (a|0x3F)
#define ceilXres(a,xres) (a|(xres - 1))
/* ks108 chipset specific defines and code */
#define KS_SET_DPY_START_LINE 0xC0
#define KS_SET_PAGE_NUM 0xB8
#define KS_SET_X 0x40
#define KS_CEHI 0x01
#define KS_CELO 0x00
#define KS_SEL_CMD 0x08
#define KS_SEL_DATA 0x00
#define KS_DPY_ON 0x3F
#define KS_DPY_OFF 0x3E
#define KS_INTACK 0x40
#define KS_CLRINT 0x02
struct arcfb_par {
unsigned long dio_addr;
unsigned long cio_addr;
unsigned long c2io_addr;
atomic_t ref_count;
unsigned char cslut[9];
struct fb_info *info;
unsigned int irq;
spinlock_t lock;
};
static const struct fb_fix_screeninfo arcfb_fix = {
.id = "arcfb",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_MONO01,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static const struct fb_var_screeninfo arcfb_var = {
.xres = 128,
.yres = 64,
.xres_virtual = 128,
.yres_virtual = 64,
.bits_per_pixel = 1,
.nonstd = 1,
};
static unsigned long num_cols;
static unsigned long num_rows;
static unsigned long dio_addr;
static unsigned long cio_addr;
static unsigned long c2io_addr;
static unsigned long splashval;
static unsigned long tuhold;
static unsigned int nosplash;
static unsigned int arcfb_enable;
static unsigned int irq;
static DECLARE_WAIT_QUEUE_HEAD(arcfb_waitq);
static void ks108_writeb_ctl(struct arcfb_par *par,
unsigned int chipindex, unsigned char value)
{
unsigned char chipselval = par->cslut[chipindex];
outb(chipselval|KS_CEHI|KS_SEL_CMD, par->cio_addr);
outb(value, par->dio_addr);
udelay(tuhold);
outb(chipselval|KS_CELO|KS_SEL_CMD, par->cio_addr);
}
static void ks108_writeb_mainctl(struct arcfb_par *par, unsigned char value)
{
outb(value, par->cio_addr);
udelay(tuhold);
}
static unsigned char ks108_readb_ctl2(struct arcfb_par *par)
{
return inb(par->c2io_addr);
}
static void ks108_writeb_data(struct arcfb_par *par,
unsigned int chipindex, unsigned char value)
{
unsigned char chipselval = par->cslut[chipindex];
outb(chipselval|KS_CEHI|KS_SEL_DATA, par->cio_addr);
outb(value, par->dio_addr);
udelay(tuhold);
outb(chipselval|KS_CELO|KS_SEL_DATA, par->cio_addr);
}
static void ks108_set_start_line(struct arcfb_par *par,
unsigned int chipindex, unsigned char y)
{
ks108_writeb_ctl(par, chipindex, KS_SET_DPY_START_LINE|y);
}
static void ks108_set_yaddr(struct arcfb_par *par,
unsigned int chipindex, unsigned char y)
{
ks108_writeb_ctl(par, chipindex, KS_SET_PAGE_NUM|y);
}
static void ks108_set_xaddr(struct arcfb_par *par,
unsigned int chipindex, unsigned char x)
{
ks108_writeb_ctl(par, chipindex, KS_SET_X|x);
}
static void ks108_clear_lcd(struct arcfb_par *par, unsigned int chipindex)
{
int i,j;
for (i = 0; i <= 8; i++) {
ks108_set_yaddr(par, chipindex, i);
ks108_set_xaddr(par, chipindex, 0);
for (j = 0; j < 64; j++) {
ks108_writeb_data(par, chipindex,
(unsigned char) splashval);
}
}
}
/* main arcfb functions */
static int arcfb_open(struct fb_info *info, int user)
{
struct arcfb_par *par = info->par;
atomic_inc(&par->ref_count);
return 0;
}
static int arcfb_release(struct fb_info *info, int user)
{
struct arcfb_par *par = info->par;
int count = atomic_read(&par->ref_count);
if (!count)
return -EINVAL;
atomic_dec(&par->ref_count);
return 0;
}
static int arcfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int i;
struct arcfb_par *par = info->par;
if ((var->vmode & FB_VMODE_YWRAP) && (var->yoffset < 64)
&& (info->var.yres <= 64)) {
for (i = 0; i < num_cols; i++) {
ks108_set_start_line(par, i, var->yoffset);
}
info->var.yoffset = var->yoffset;
return 0;
}
return -EINVAL;
}
static irqreturn_t arcfb_interrupt(int vec, void *dev_instance)
{
struct fb_info *info = dev_instance;
unsigned char ctl2status;
struct arcfb_par *par = info->par;
ctl2status = ks108_readb_ctl2(par);
if (!(ctl2status & KS_INTACK)) /* not arc generated interrupt */
return IRQ_NONE;
ks108_writeb_mainctl(par, KS_CLRINT);
spin_lock(&par->lock);
if (waitqueue_active(&arcfb_waitq)) {
wake_up(&arcfb_waitq);
}
spin_unlock(&par->lock);
return IRQ_HANDLED;
}
/*
* here we handle a specific page on the lcd. the complexity comes from
* the fact that the fb is laidout in 8xX vertical columns. we extract
* each write of 8 vertical pixels. then we shift out as we move along
* X. That's what rightshift does. bitmask selects the desired input bit.
*/
static void arcfb_lcd_update_page(struct arcfb_par *par, unsigned int upper,
unsigned int left, unsigned int right, unsigned int distance)
{
unsigned char *src;
unsigned int xindex, yindex, chipindex, linesize;
int i;
unsigned char val;
unsigned char bitmask, rightshift;
xindex = left >> 6;
yindex = upper >> 6;
chipindex = (xindex + (yindex*num_cols));
ks108_set_yaddr(par, chipindex, upper/8);
linesize = par->info->var.xres/8;
src = (unsigned char *)par->info->screen_buffer + (left/8) +
(upper * linesize);
ks108_set_xaddr(par, chipindex, left);
bitmask=1;
rightshift=0;
while (left <= right) {
val = 0;
for (i = 0; i < 8; i++) {
if ( i > rightshift) {
val |= (*(src + (i*linesize)) & bitmask)
<< (i - rightshift);
} else {
val |= (*(src + (i*linesize)) & bitmask)
>> (rightshift - i);
}
}
ks108_writeb_data(par, chipindex, val);
left++;
if (bitmask == 0x80) {
bitmask = 1;
src++;
rightshift=0;
} else {
bitmask <<= 1;
rightshift++;
}
}
}
/*
* here we handle the entire vertical page of the update. we write across
* lcd chips. update_page uses the upper/left values to decide which
* chip to select for the right. upper is needed for setting the page
* desired for the write.
*/
static void arcfb_lcd_update_vert(struct arcfb_par *par, unsigned int top,
unsigned int bottom, unsigned int left, unsigned int right)
{
unsigned int distance, upper, lower;
distance = (bottom - top) + 1;
upper = top;
lower = top + 7;
while (distance > 0) {
distance -= 8;
arcfb_lcd_update_page(par, upper, left, right, 8);
upper = lower + 1;
lower = upper + 7;
}
}
/*
* here we handle horizontal blocks for the update. update_vert will
* handle spaning multiple pages. we break out each horizontal
* block in to individual blocks no taller than 64 pixels.
*/
static void arcfb_lcd_update_horiz(struct arcfb_par *par, unsigned int left,
unsigned int right, unsigned int top, unsigned int h)
{
unsigned int distance, upper, lower;
distance = h;
upper = floor8(top);
lower = min(upper + distance - 1, ceil64(upper));
while (distance > 0) {
distance -= ((lower - upper) + 1 );
arcfb_lcd_update_vert(par, upper, lower, left, right);
upper = lower + 1;
lower = min(upper + distance - 1, ceil64(upper));
}
}
/*
* here we start the process of splitting out the fb update into
* individual blocks of pixels. we end up splitting into 64x64 blocks
* and finally down to 64x8 pages.
*/
static void arcfb_lcd_update(struct arcfb_par *par, unsigned int dx,
unsigned int dy, unsigned int w, unsigned int h)
{
unsigned int left, right, distance, y;
/* align the request first */
y = floor8(dy);
h += dy - y;
h = iceil8(h);
distance = w;
left = dx;
right = min(left + w - 1, ceil64(left));
while (distance > 0) {
arcfb_lcd_update_horiz(par, left, right, y, h);
distance -= ((right - left) + 1);
left = right + 1;
right = min(left + distance - 1, ceil64(left));
}
}
static void arcfb_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
struct arcfb_par *par = info->par;
sys_fillrect(info, rect);
/* update the physical lcd */
arcfb_lcd_update(par, rect->dx, rect->dy, rect->width, rect->height);
}
static void arcfb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct arcfb_par *par = info->par;
sys_copyarea(info, area);
/* update the physical lcd */
arcfb_lcd_update(par, area->dx, area->dy, area->width, area->height);
}
static void arcfb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct arcfb_par *par = info->par;
sys_imageblit(info, image);
/* update the physical lcd */
arcfb_lcd_update(par, image->dx, image->dy, image->width,
image->height);
}
static int arcfb_ioctl(struct fb_info *info,
unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
struct arcfb_par *par = info->par;
unsigned long flags;
switch (cmd) {
case FBIO_WAITEVENT:
{
DEFINE_WAIT(wait);
/* illegal to wait on arc if no irq will occur */
if (!par->irq)
return -EINVAL;
/* wait until the Arc has generated an interrupt
* which will wake us up */
spin_lock_irqsave(&par->lock, flags);
prepare_to_wait(&arcfb_waitq, &wait,
TASK_INTERRUPTIBLE);
spin_unlock_irqrestore(&par->lock, flags);
schedule();
finish_wait(&arcfb_waitq, &wait);
}
fallthrough;
case FBIO_GETCONTROL2:
{
unsigned char ctl2;
ctl2 = ks108_readb_ctl2(info->par);
if (copy_to_user(argp, &ctl2, sizeof(ctl2)))
return -EFAULT;
return 0;
}
default:
return -EINVAL;
}
}
/*
* this is the access path from userspace. they can seek and write to
* the fb. it's inefficient for them to do anything less than 64*8
* writes since we update the lcd in each write() anyway.
*/
static ssize_t arcfb_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos)
{
/* modded from epson 1355 */
unsigned long p;
int err;
unsigned int fbmemlength,x,y,w,h, bitppos, startpos, endpos, bitcount;
struct arcfb_par *par;
unsigned int xres;
if (!info->screen_buffer)
return -ENODEV;
p = *ppos;
par = info->par;
xres = info->var.xres;
fbmemlength = (xres * info->var.yres)/8;
if (p > fbmemlength)
return -ENOSPC;
err = 0;
if ((count + p) > fbmemlength) {
count = fbmemlength - p;
err = -ENOSPC;
}
if (count) {
char *base_addr;
base_addr = info->screen_buffer;
count -= copy_from_user(base_addr + p, buf, count);
*ppos += count;
err = -EFAULT;
}
bitppos = p*8;
startpos = floorXres(bitppos, xres);
endpos = ceilXres((bitppos + (count*8)), xres);
bitcount = endpos - startpos;
x = startpos % xres;
y = startpos / xres;
w = xres;
h = bitcount / xres;
arcfb_lcd_update(par, x, y, w, h);
if (count)
return count;
return err;
}
static const struct fb_ops arcfb_ops = {
.owner = THIS_MODULE,
.fb_open = arcfb_open,
.fb_read = fb_sys_read,
.fb_write = arcfb_write,
.fb_release = arcfb_release,
.fb_pan_display = arcfb_pan_display,
.fb_fillrect = arcfb_fillrect,
.fb_copyarea = arcfb_copyarea,
.fb_imageblit = arcfb_imageblit,
.fb_ioctl = arcfb_ioctl,
};
static int arcfb_probe(struct platform_device *dev)
{
struct fb_info *info;
int retval = -ENOMEM;
int videomemorysize;
unsigned char *videomemory;
struct arcfb_par *par;
int i;
videomemorysize = (((64*64)*num_cols)*num_rows)/8;
/* We need a flat backing store for the Arc's
less-flat actual paged framebuffer */
videomemory = vzalloc(videomemorysize);
if (!videomemory)
return retval;
info = framebuffer_alloc(sizeof(struct arcfb_par), &dev->dev);
if (!info)
goto err_fb_alloc;
info->screen_buffer = videomemory;
info->fbops = &arcfb_ops;
info->var = arcfb_var;
info->fix = arcfb_fix;
par = info->par;
par->info = info;
if (!dio_addr || !cio_addr || !c2io_addr) {
printk(KERN_WARNING "no IO addresses supplied\n");
goto err_addr;
}
par->dio_addr = dio_addr;
par->cio_addr = cio_addr;
par->c2io_addr = c2io_addr;
par->cslut[0] = 0x00;
par->cslut[1] = 0x06;
spin_lock_init(&par->lock);
if (irq) {
par->irq = irq;
if (request_irq(par->irq, &arcfb_interrupt, IRQF_SHARED,
"arcfb", info)) {
printk(KERN_INFO
"arcfb: Failed req IRQ %d\n", par->irq);
retval = -EBUSY;
goto err_addr;
}
}
retval = register_framebuffer(info);
if (retval < 0)
goto err_register_fb;
platform_set_drvdata(dev, info);
fb_info(info, "Arc frame buffer device, using %dK of video memory\n",
videomemorysize >> 10);
/* this inits the lcd but doesn't clear dirty pixels */
for (i = 0; i < num_cols * num_rows; i++) {
ks108_writeb_ctl(par, i, KS_DPY_OFF);
ks108_set_start_line(par, i, 0);
ks108_set_yaddr(par, i, 0);
ks108_set_xaddr(par, i, 0);
ks108_writeb_ctl(par, i, KS_DPY_ON);
}
/* if we were told to splash the screen, we just clear it */
if (!nosplash) {
for (i = 0; i < num_cols * num_rows; i++) {
fb_info(info, "splashing lcd %d\n", i);
ks108_set_start_line(par, i, 0);
ks108_clear_lcd(par, i);
}
}
return 0;
err_register_fb:
free_irq(par->irq, info);
err_addr:
framebuffer_release(info);
err_fb_alloc:
vfree(videomemory);
return retval;
}
static void arcfb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
if (info) {
unregister_framebuffer(info);
if (irq)
free_irq(((struct arcfb_par *)(info->par))->irq, info);
vfree(info->screen_buffer);
framebuffer_release(info);
}
}
static struct platform_driver arcfb_driver = {
.probe = arcfb_probe,
.remove_new = arcfb_remove,
.driver = {
.name = "arcfb",
},
};
static struct platform_device *arcfb_device;
static int __init arcfb_init(void)
{
int ret;
if (!arcfb_enable)
return -ENXIO;
ret = platform_driver_register(&arcfb_driver);
if (!ret) {
arcfb_device = platform_device_alloc("arcfb", 0);
if (arcfb_device) {
ret = platform_device_add(arcfb_device);
} else {
ret = -ENOMEM;
}
if (ret) {
platform_device_put(arcfb_device);
platform_driver_unregister(&arcfb_driver);
}
}
return ret;
}
static void __exit arcfb_exit(void)
{
platform_device_unregister(arcfb_device);
platform_driver_unregister(&arcfb_driver);
}
module_param(num_cols, ulong, 0);
MODULE_PARM_DESC(num_cols, "Num horiz panels, eg: 2 = 128 bit wide");
module_param(num_rows, ulong, 0);
MODULE_PARM_DESC(num_rows, "Num vert panels, eg: 1 = 64 bit high");
module_param(nosplash, uint, 0);
MODULE_PARM_DESC(nosplash, "Disable doing the splash screen");
module_param(arcfb_enable, uint, 0);
MODULE_PARM_DESC(arcfb_enable, "Enable communication with Arc board");
module_param_hw(dio_addr, ulong, ioport, 0);
MODULE_PARM_DESC(dio_addr, "IO address for data, eg: 0x480");
module_param_hw(cio_addr, ulong, ioport, 0);
MODULE_PARM_DESC(cio_addr, "IO address for control, eg: 0x400");
module_param_hw(c2io_addr, ulong, ioport, 0);
MODULE_PARM_DESC(c2io_addr, "IO address for secondary control, eg: 0x408");
module_param(splashval, ulong, 0);
MODULE_PARM_DESC(splashval, "Splash pattern: 0xFF is black, 0x00 is green");
module_param(tuhold, ulong, 0);
MODULE_PARM_DESC(tuhold, "Time to hold between strobing data to Arc board");
module_param_hw(irq, uint, irq, 0);
MODULE_PARM_DESC(irq, "IRQ for the Arc board");
module_init(arcfb_init);
module_exit(arcfb_exit);
MODULE_DESCRIPTION("fbdev driver for Arc monochrome LCD board");
MODULE_AUTHOR("Jaya Kumar");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/arcfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/acornfb.c
*
* Copyright (C) 1998-2001 Russell King
*
* Frame buffer code for Acorn platforms
*
* NOTE: Most of the modes with X!=640 will disappear shortly.
* NOTE: Startup setting of HS & VS polarity not supported.
* (do we need to support it if we're coming up in 640x480?)
*
* FIXME: (things broken by the "new improved" FBCON API)
* - Blanking 8bpp displays with VIDC
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/gfp.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include "acornfb.h"
/*
* Default resolution.
* NOTE that it has to be supported in the table towards
* the end of this file.
*/
#define DEFAULT_XRES 640
#define DEFAULT_YRES 480
#define DEFAULT_BPP 4
/*
* define this to debug the video mode selection
*/
#undef DEBUG_MODE_SELECTION
/*
* Translation from RISC OS monitor types to actual
* HSYNC and VSYNC frequency ranges. These are
* probably not right, but they're the best info I
* have. Allow 1% either way on the nominal for TVs.
*/
#define NR_MONTYPES 6
static struct fb_monspecs monspecs[NR_MONTYPES] = {
{ /* TV */
.hfmin = 15469,
.hfmax = 15781,
.vfmin = 49,
.vfmax = 51,
}, { /* Multi Freq */
.hfmin = 0,
.hfmax = 99999,
.vfmin = 0,
.vfmax = 199,
}, { /* Hi-res mono */
.hfmin = 58608,
.hfmax = 58608,
.vfmin = 64,
.vfmax = 64,
}, { /* VGA */
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
}, { /* SVGA */
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 56,
.vfmax = 75,
}, {
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
}
};
static struct fb_info fb_info;
static struct acornfb_par current_par;
static struct vidc_timing current_vidc;
extern unsigned int vram_size; /* set by setup.c */
#ifdef HAS_VIDC20
#include <mach/acornfb.h>
#define MAX_SIZE (2*1024*1024)
/* VIDC20 has a different set of rules from the VIDC:
* hcr : must be multiple of 4
* hswr : must be even
* hdsr : must be even
* hder : must be even
* vcr : >= 2, (interlace, must be odd)
* vswr : >= 1
* vdsr : >= 1
* vder : >= vdsr
*/
static void acornfb_set_timing(struct fb_info *info)
{
struct fb_var_screeninfo *var = &info->var;
struct vidc_timing vidc;
u_int vcr, fsize;
u_int ext_ctl, dat_ctl;
u_int words_per_line;
memset(&vidc, 0, sizeof(vidc));
vidc.h_sync_width = var->hsync_len - 8;
vidc.h_border_start = vidc.h_sync_width + var->left_margin + 8 - 12;
vidc.h_display_start = vidc.h_border_start + 12 - 18;
vidc.h_display_end = vidc.h_display_start + var->xres;
vidc.h_border_end = vidc.h_display_end + 18 - 12;
vidc.h_cycle = vidc.h_border_end + var->right_margin + 12 - 8;
vidc.h_interlace = vidc.h_cycle / 2;
vidc.v_sync_width = var->vsync_len - 1;
vidc.v_border_start = vidc.v_sync_width + var->upper_margin;
vidc.v_display_start = vidc.v_border_start;
vidc.v_display_end = vidc.v_display_start + var->yres;
vidc.v_border_end = vidc.v_display_end;
vidc.control = acornfb_default_control();
vcr = var->vsync_len + var->upper_margin + var->yres +
var->lower_margin;
if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
vidc.v_cycle = (vcr - 3) / 2;
vidc.control |= VIDC20_CTRL_INT;
} else
vidc.v_cycle = vcr - 2;
switch (var->bits_per_pixel) {
case 1: vidc.control |= VIDC20_CTRL_1BPP; break;
case 2: vidc.control |= VIDC20_CTRL_2BPP; break;
case 4: vidc.control |= VIDC20_CTRL_4BPP; break;
default:
case 8: vidc.control |= VIDC20_CTRL_8BPP; break;
case 16: vidc.control |= VIDC20_CTRL_16BPP; break;
case 32: vidc.control |= VIDC20_CTRL_32BPP; break;
}
acornfb_vidc20_find_rates(&vidc, var);
fsize = var->vsync_len + var->upper_margin + var->lower_margin - 1;
if (memcmp(¤t_vidc, &vidc, sizeof(vidc))) {
current_vidc = vidc;
vidc_writel(VIDC20_CTRL | vidc.control);
vidc_writel(0xd0000000 | vidc.pll_ctl);
vidc_writel(0x80000000 | vidc.h_cycle);
vidc_writel(0x81000000 | vidc.h_sync_width);
vidc_writel(0x82000000 | vidc.h_border_start);
vidc_writel(0x83000000 | vidc.h_display_start);
vidc_writel(0x84000000 | vidc.h_display_end);
vidc_writel(0x85000000 | vidc.h_border_end);
vidc_writel(0x86000000);
vidc_writel(0x87000000 | vidc.h_interlace);
vidc_writel(0x90000000 | vidc.v_cycle);
vidc_writel(0x91000000 | vidc.v_sync_width);
vidc_writel(0x92000000 | vidc.v_border_start);
vidc_writel(0x93000000 | vidc.v_display_start);
vidc_writel(0x94000000 | vidc.v_display_end);
vidc_writel(0x95000000 | vidc.v_border_end);
vidc_writel(0x96000000);
vidc_writel(0x97000000);
}
iomd_writel(fsize, IOMD_FSIZE);
ext_ctl = acornfb_default_econtrol();
if (var->sync & FB_SYNC_COMP_HIGH_ACT) /* should be FB_SYNC_COMP */
ext_ctl |= VIDC20_ECTL_HS_NCSYNC | VIDC20_ECTL_VS_NCSYNC;
else {
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
ext_ctl |= VIDC20_ECTL_HS_HSYNC;
else
ext_ctl |= VIDC20_ECTL_HS_NHSYNC;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
ext_ctl |= VIDC20_ECTL_VS_VSYNC;
else
ext_ctl |= VIDC20_ECTL_VS_NVSYNC;
}
vidc_writel(VIDC20_ECTL | ext_ctl);
words_per_line = var->xres * var->bits_per_pixel / 32;
if (current_par.using_vram && info->fix.smem_len == 2048*1024)
words_per_line /= 2;
/* RiscPC doesn't use the VIDC's VRAM control. */
dat_ctl = VIDC20_DCTL_VRAM_DIS | VIDC20_DCTL_SNA | words_per_line;
/* The data bus width is dependent on both the type
* and amount of video memory.
* DRAM 32bit low
* 1MB VRAM 32bit
* 2MB VRAM 64bit
*/
if (current_par.using_vram && current_par.vram_half_sam == 2048)
dat_ctl |= VIDC20_DCTL_BUS_D63_0;
else
dat_ctl |= VIDC20_DCTL_BUS_D31_0;
vidc_writel(VIDC20_DCTL | dat_ctl);
#ifdef DEBUG_MODE_SELECTION
printk(KERN_DEBUG "VIDC registers for %dx%dx%d:\n", var->xres,
var->yres, var->bits_per_pixel);
printk(KERN_DEBUG " H-cycle : %d\n", vidc.h_cycle);
printk(KERN_DEBUG " H-sync-width : %d\n", vidc.h_sync_width);
printk(KERN_DEBUG " H-border-start : %d\n", vidc.h_border_start);
printk(KERN_DEBUG " H-display-start : %d\n", vidc.h_display_start);
printk(KERN_DEBUG " H-display-end : %d\n", vidc.h_display_end);
printk(KERN_DEBUG " H-border-end : %d\n", vidc.h_border_end);
printk(KERN_DEBUG " H-interlace : %d\n", vidc.h_interlace);
printk(KERN_DEBUG " V-cycle : %d\n", vidc.v_cycle);
printk(KERN_DEBUG " V-sync-width : %d\n", vidc.v_sync_width);
printk(KERN_DEBUG " V-border-start : %d\n", vidc.v_border_start);
printk(KERN_DEBUG " V-display-start : %d\n", vidc.v_display_start);
printk(KERN_DEBUG " V-display-end : %d\n", vidc.v_display_end);
printk(KERN_DEBUG " V-border-end : %d\n", vidc.v_border_end);
printk(KERN_DEBUG " Ext Ctrl (C) : 0x%08X\n", ext_ctl);
printk(KERN_DEBUG " PLL Ctrl (D) : 0x%08X\n", vidc.pll_ctl);
printk(KERN_DEBUG " Ctrl (E) : 0x%08X\n", vidc.control);
printk(KERN_DEBUG " Data Ctrl (F) : 0x%08X\n", dat_ctl);
printk(KERN_DEBUG " Fsize : 0x%08X\n", fsize);
#endif
}
/*
* We have to take note of the VIDC20's 16-bit palette here.
* The VIDC20 looks up a 16 bit pixel as follows:
*
* bits 111111
* 5432109876543210
* red ++++++++ (8 bits, 7 to 0)
* green ++++++++ (8 bits, 11 to 4)
* blue ++++++++ (8 bits, 15 to 8)
*
* We use a pixel which looks like:
*
* bits 111111
* 5432109876543210
* red +++++ (5 bits, 4 to 0)
* green +++++ (5 bits, 9 to 5)
* blue +++++ (5 bits, 14 to 10)
*/
static int
acornfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
union palette pal;
if (regno >= current_par.palette_size)
return 1;
if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
u32 pseudo_val;
pseudo_val = regno << info->var.red.offset;
pseudo_val |= regno << info->var.green.offset;
pseudo_val |= regno << info->var.blue.offset;
((u32 *)info->pseudo_palette)[regno] = pseudo_val;
}
pal.p = 0;
pal.vidc20.red = red >> 8;
pal.vidc20.green = green >> 8;
pal.vidc20.blue = blue >> 8;
current_par.palette[regno] = pal;
if (info->var.bits_per_pixel == 16) {
int i;
pal.p = 0;
vidc_writel(0x10000000);
for (i = 0; i < 256; i += 1) {
pal.vidc20.red = current_par.palette[i & 31].vidc20.red;
pal.vidc20.green = current_par.palette[(i >> 1) & 31].vidc20.green;
pal.vidc20.blue = current_par.palette[(i >> 2) & 31].vidc20.blue;
vidc_writel(pal.p);
/* Palette register pointer auto-increments */
}
} else {
vidc_writel(0x10000000 | regno);
vidc_writel(pal.p);
}
return 0;
}
#endif
/*
* Before selecting the timing parameters, adjust
* the resolution to fit the rules.
*/
static int
acornfb_adjust_timing(struct fb_info *info, struct fb_var_screeninfo *var, u_int fontht)
{
u_int font_line_len, sam_size, min_size, size, nr_y;
/* xres must be even */
var->xres = (var->xres + 1) & ~1;
/*
* We don't allow xres_virtual to differ from xres
*/
var->xres_virtual = var->xres;
var->xoffset = 0;
if (current_par.using_vram)
sam_size = current_par.vram_half_sam * 2;
else
sam_size = 16;
/*
* Now, find a value for yres_virtual which allows
* us to do ywrap scrolling. The value of
* yres_virtual must be such that the end of the
* displayable frame buffer must be aligned with
* the start of a font line.
*/
font_line_len = var->xres * var->bits_per_pixel * fontht / 8;
min_size = var->xres * var->yres * var->bits_per_pixel / 8;
/*
* If minimum screen size is greater than that we have
* available, reject it.
*/
if (min_size > info->fix.smem_len)
return -EINVAL;
/* Find int 'y', such that y * fll == s * sam < maxsize
* y = s * sam / fll; s = maxsize / sam
*/
for (size = info->fix.smem_len;
nr_y = size / font_line_len, min_size <= size;
size -= sam_size) {
if (nr_y * font_line_len == size)
break;
}
nr_y *= fontht;
if (var->accel_flags & FB_ACCELF_TEXT) {
if (min_size > size) {
/*
* failed, use ypan
*/
size = info->fix.smem_len;
var->yres_virtual = size / (font_line_len / fontht);
} else
var->yres_virtual = nr_y;
} else if (var->yres_virtual > nr_y)
var->yres_virtual = nr_y;
current_par.screen_end = info->fix.smem_start + size;
/*
* Fix yres & yoffset if needed.
*/
if (var->yres > var->yres_virtual)
var->yres = var->yres_virtual;
if (var->vmode & FB_VMODE_YWRAP) {
if (var->yoffset > var->yres_virtual)
var->yoffset = var->yres_virtual;
} else {
if (var->yoffset + var->yres > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
}
/* hsync_len must be even */
var->hsync_len = (var->hsync_len + 1) & ~1;
#if defined(HAS_VIDC20)
/* left_margin must be even */
if (var->left_margin & 1) {
var->left_margin += 1;
var->right_margin -= 1;
}
/* right_margin must be even */
if (var->right_margin & 1)
var->right_margin += 1;
#endif
if (var->vsync_len < 1)
var->vsync_len = 1;
return 0;
}
static int
acornfb_validate_timing(struct fb_var_screeninfo *var,
struct fb_monspecs *monspecs)
{
unsigned long hs, vs;
/*
* hs(Hz) = 10^12 / (pixclock * xtotal)
* vs(Hz) = hs(Hz) / ytotal
*
* No need to do long long divisions or anything
* like that if you factor it correctly
*/
hs = 1953125000 / var->pixclock;
hs = hs * 512 /
(var->xres + var->left_margin + var->right_margin + var->hsync_len);
vs = hs /
(var->yres + var->upper_margin + var->lower_margin + var->vsync_len);
return (vs >= monspecs->vfmin && vs <= monspecs->vfmax &&
hs >= monspecs->hfmin && hs <= monspecs->hfmax) ? 0 : -EINVAL;
}
static inline void
acornfb_update_dma(struct fb_info *info, struct fb_var_screeninfo *var)
{
u_int off = var->yoffset * info->fix.line_length;
#if defined(HAS_MEMC)
memc_write(VDMA_INIT, off >> 2);
#elif defined(HAS_IOMD)
iomd_writel(info->fix.smem_start + off, IOMD_VIDINIT);
#endif
}
static int
acornfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
u_int fontht;
int err;
/*
* FIXME: Find the font height
*/
fontht = 8;
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
switch (var->bits_per_pixel) {
case 1: case 2: case 4: case 8:
var->red.offset = 0;
var->red.length = var->bits_per_pixel;
var->green = var->red;
var->blue = var->red;
var->transp.offset = 0;
var->transp.length = 0;
break;
#ifdef HAS_VIDC20
case 16:
var->red.offset = 0;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 10;
var->blue.length = 5;
var->transp.offset = 15;
var->transp.length = 1;
break;
case 32:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 4;
break;
#endif
default:
return -EINVAL;
}
/*
* Check to see if the pixel rate is valid.
*/
if (!acornfb_valid_pixrate(var))
return -EINVAL;
/*
* Validate and adjust the resolution to
* match the video generator hardware.
*/
err = acornfb_adjust_timing(info, var, fontht);
if (err)
return err;
/*
* Validate the timing against the
* monitor hardware.
*/
return acornfb_validate_timing(var, &info->monspecs);
}
static int acornfb_set_par(struct fb_info *info)
{
switch (info->var.bits_per_pixel) {
case 1:
current_par.palette_size = 2;
info->fix.visual = FB_VISUAL_MONO10;
break;
case 2:
current_par.palette_size = 4;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 4:
current_par.palette_size = 16;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 8:
current_par.palette_size = VIDC_PALETTE_SIZE;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
#ifdef HAS_VIDC20
case 16:
current_par.palette_size = 32;
info->fix.visual = FB_VISUAL_DIRECTCOLOR;
break;
case 32:
current_par.palette_size = VIDC_PALETTE_SIZE;
info->fix.visual = FB_VISUAL_DIRECTCOLOR;
break;
#endif
default:
BUG();
}
info->fix.line_length = (info->var.xres * info->var.bits_per_pixel) / 8;
#if defined(HAS_MEMC)
{
unsigned long size = info->fix.smem_len - VDMA_XFERSIZE;
memc_write(VDMA_START, 0);
memc_write(VDMA_END, size >> 2);
}
#elif defined(HAS_IOMD)
{
unsigned long start, size;
u_int control;
start = info->fix.smem_start;
size = current_par.screen_end;
if (current_par.using_vram) {
size -= current_par.vram_half_sam;
control = DMA_CR_E | (current_par.vram_half_sam / 256);
} else {
size -= 16;
control = DMA_CR_E | DMA_CR_D | 16;
}
iomd_writel(start, IOMD_VIDSTART);
iomd_writel(size, IOMD_VIDEND);
iomd_writel(control, IOMD_VIDCR);
}
#endif
acornfb_update_dma(info, &info->var);
acornfb_set_timing(info);
return 0;
}
static int
acornfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
u_int y_bottom = var->yoffset;
if (!(var->vmode & FB_VMODE_YWRAP))
y_bottom += info->var.yres;
if (y_bottom > info->var.yres_virtual)
return -EINVAL;
acornfb_update_dma(info, var);
return 0;
}
static const struct fb_ops acornfb_ops = {
.owner = THIS_MODULE,
FB_IOMEM_DEFAULT_OPS,
.fb_check_var = acornfb_check_var,
.fb_set_par = acornfb_set_par,
.fb_setcolreg = acornfb_setcolreg,
.fb_pan_display = acornfb_pan_display,
};
/*
* Everything after here is initialisation!!!
*/
static struct fb_videomode modedb[] = {
{ /* 320x256 @ 50Hz */
NULL, 50, 320, 256, 125000, 92, 62, 35, 19, 38, 2,
FB_SYNC_COMP_HIGH_ACT,
FB_VMODE_NONINTERLACED
}, { /* 640x250 @ 50Hz, 15.6 kHz hsync */
NULL, 50, 640, 250, 62500, 185, 123, 38, 21, 76, 3,
0,
FB_VMODE_NONINTERLACED
}, { /* 640x256 @ 50Hz, 15.6 kHz hsync */
NULL, 50, 640, 256, 62500, 185, 123, 35, 18, 76, 3,
0,
FB_VMODE_NONINTERLACED
}, { /* 640x512 @ 50Hz, 26.8 kHz hsync */
NULL, 50, 640, 512, 41667, 113, 87, 18, 1, 56, 3,
0,
FB_VMODE_NONINTERLACED
}, { /* 640x250 @ 70Hz, 31.5 kHz hsync */
NULL, 70, 640, 250, 39722, 48, 16, 109, 88, 96, 2,
0,
FB_VMODE_NONINTERLACED
}, { /* 640x256 @ 70Hz, 31.5 kHz hsync */
NULL, 70, 640, 256, 39722, 48, 16, 106, 85, 96, 2,
0,
FB_VMODE_NONINTERLACED
}, { /* 640x352 @ 70Hz, 31.5 kHz hsync */
NULL, 70, 640, 352, 39722, 48, 16, 58, 37, 96, 2,
0,
FB_VMODE_NONINTERLACED
}, { /* 640x480 @ 60Hz, 31.5 kHz hsync */
NULL, 60, 640, 480, 39722, 48, 16, 32, 11, 96, 2,
0,
FB_VMODE_NONINTERLACED
}, { /* 800x600 @ 56Hz, 35.2 kHz hsync */
NULL, 56, 800, 600, 27778, 101, 23, 22, 1, 100, 2,
0,
FB_VMODE_NONINTERLACED
}, { /* 896x352 @ 60Hz, 21.8 kHz hsync */
NULL, 60, 896, 352, 41667, 59, 27, 9, 0, 118, 3,
0,
FB_VMODE_NONINTERLACED
}, { /* 1024x 768 @ 60Hz, 48.4 kHz hsync */
NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
0,
FB_VMODE_NONINTERLACED
}, { /* 1280x1024 @ 60Hz, 63.8 kHz hsync */
NULL, 60, 1280, 1024, 9090, 186, 96, 38, 1, 160, 3,
0,
FB_VMODE_NONINTERLACED
}
};
static struct fb_videomode acornfb_default_mode = {
.name = NULL,
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39722,
.left_margin = 56,
.right_margin = 16,
.upper_margin = 34,
.lower_margin = 9,
.hsync_len = 88,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
static void acornfb_init_fbinfo(void)
{
static int first = 1;
if (!first)
return;
first = 0;
fb_info.fbops = &acornfb_ops;
fb_info.flags = FBINFO_HWACCEL_YPAN;
fb_info.pseudo_palette = current_par.pseudo_palette;
strcpy(fb_info.fix.id, "Acorn");
fb_info.fix.type = FB_TYPE_PACKED_PIXELS;
fb_info.fix.type_aux = 0;
fb_info.fix.xpanstep = 0;
fb_info.fix.ypanstep = 1;
fb_info.fix.ywrapstep = 1;
fb_info.fix.line_length = 0;
fb_info.fix.accel = FB_ACCEL_NONE;
/*
* setup initial parameters
*/
memset(&fb_info.var, 0, sizeof(fb_info.var));
#if defined(HAS_VIDC20)
fb_info.var.red.length = 8;
fb_info.var.transp.length = 4;
#endif
fb_info.var.green = fb_info.var.red;
fb_info.var.blue = fb_info.var.red;
fb_info.var.nonstd = 0;
fb_info.var.activate = FB_ACTIVATE_NOW;
fb_info.var.height = -1;
fb_info.var.width = -1;
fb_info.var.vmode = FB_VMODE_NONINTERLACED;
fb_info.var.accel_flags = FB_ACCELF_TEXT;
current_par.dram_size = 0;
current_par.montype = -1;
current_par.dpms = 0;
}
/*
* setup acornfb options:
*
* mon:hmin-hmax:vmin-vmax:dpms:width:height
* Set monitor parameters:
* hmin = horizontal minimum frequency (Hz)
* hmax = horizontal maximum frequency (Hz) (optional)
* vmin = vertical minimum frequency (Hz)
* vmax = vertical maximum frequency (Hz) (optional)
* dpms = DPMS supported? (optional)
* width = width of picture in mm. (optional)
* height = height of picture in mm. (optional)
*
* montype:type
* Set RISC-OS style monitor type:
* 0 (or tv) - TV frequency
* 1 (or multi) - Multi frequency
* 2 (or hires) - Hi-res monochrome
* 3 (or vga) - VGA
* 4 (or svga) - SVGA
* auto, or option missing
* - try hardware detect
*
* dram:size
* Set the amount of DRAM to use for the frame buffer
* (even if you have VRAM).
* size can optionally be followed by 'M' or 'K' for
* MB or KB respectively.
*/
static void acornfb_parse_mon(char *opt)
{
char *p = opt;
current_par.montype = -2;
fb_info.monspecs.hfmin = simple_strtoul(p, &p, 0);
if (*p == '-')
fb_info.monspecs.hfmax = simple_strtoul(p + 1, &p, 0);
else
fb_info.monspecs.hfmax = fb_info.monspecs.hfmin;
if (*p != ':')
goto bad;
fb_info.monspecs.vfmin = simple_strtoul(p + 1, &p, 0);
if (*p == '-')
fb_info.monspecs.vfmax = simple_strtoul(p + 1, &p, 0);
else
fb_info.monspecs.vfmax = fb_info.monspecs.vfmin;
if (*p != ':')
goto check_values;
fb_info.monspecs.dpms = simple_strtoul(p + 1, &p, 0);
if (*p != ':')
goto check_values;
fb_info.var.width = simple_strtoul(p + 1, &p, 0);
if (*p != ':')
goto check_values;
fb_info.var.height = simple_strtoul(p + 1, NULL, 0);
check_values:
if (fb_info.monspecs.hfmax < fb_info.monspecs.hfmin ||
fb_info.monspecs.vfmax < fb_info.monspecs.vfmin)
goto bad;
return;
bad:
printk(KERN_ERR "Acornfb: bad monitor settings: %s\n", opt);
current_par.montype = -1;
}
static void acornfb_parse_montype(char *opt)
{
current_par.montype = -2;
if (strncmp(opt, "tv", 2) == 0) {
opt += 2;
current_par.montype = 0;
} else if (strncmp(opt, "multi", 5) == 0) {
opt += 5;
current_par.montype = 1;
} else if (strncmp(opt, "hires", 5) == 0) {
opt += 5;
current_par.montype = 2;
} else if (strncmp(opt, "vga", 3) == 0) {
opt += 3;
current_par.montype = 3;
} else if (strncmp(opt, "svga", 4) == 0) {
opt += 4;
current_par.montype = 4;
} else if (strncmp(opt, "auto", 4) == 0) {
opt += 4;
current_par.montype = -1;
} else if (isdigit(*opt))
current_par.montype = simple_strtoul(opt, &opt, 0);
if (current_par.montype == -2 ||
current_par.montype > NR_MONTYPES) {
printk(KERN_ERR "acornfb: unknown monitor type: %s\n",
opt);
current_par.montype = -1;
} else
if (opt && *opt) {
if (strcmp(opt, ",dpms") == 0)
current_par.dpms = 1;
else
printk(KERN_ERR
"acornfb: unknown monitor option: %s\n",
opt);
}
}
static void acornfb_parse_dram(char *opt)
{
unsigned int size;
size = simple_strtoul(opt, &opt, 0);
if (opt) {
switch (*opt) {
case 'M':
case 'm':
size *= 1024;
fallthrough;
case 'K':
case 'k':
size *= 1024;
default:
break;
}
}
current_par.dram_size = size;
}
static struct options {
char *name;
void (*parse)(char *opt);
} opt_table[] = {
{ "mon", acornfb_parse_mon },
{ "montype", acornfb_parse_montype },
{ "dram", acornfb_parse_dram },
{ NULL, NULL }
};
static int acornfb_setup(char *options)
{
struct options *optp;
char *opt;
if (!options || !*options)
return 0;
acornfb_init_fbinfo();
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
for (optp = opt_table; optp->name; optp++) {
int optlen;
optlen = strlen(optp->name);
if (strncmp(opt, optp->name, optlen) == 0 &&
opt[optlen] == ':') {
optp->parse(opt + optlen + 1);
break;
}
}
if (!optp->name)
printk(KERN_ERR "acornfb: unknown parameter: %s\n",
opt);
}
return 0;
}
/*
* Detect type of monitor connected
* For now, we just assume SVGA
*/
static int acornfb_detect_monitortype(void)
{
return 4;
}
static int acornfb_probe(struct platform_device *dev)
{
unsigned long size;
u_int h_sync, v_sync;
int rc, i;
char *option = NULL;
if (fb_get_options("acornfb", &option))
return -ENODEV;
acornfb_setup(option);
acornfb_init_fbinfo();
current_par.dev = &dev->dev;
if (current_par.montype == -1)
current_par.montype = acornfb_detect_monitortype();
if (current_par.montype == -1 || current_par.montype > NR_MONTYPES)
current_par.montype = 4;
if (current_par.montype >= 0) {
fb_info.monspecs = monspecs[current_par.montype];
fb_info.monspecs.dpms = current_par.dpms;
}
/*
* Try to select a suitable default mode
*/
for (i = 0; i < ARRAY_SIZE(modedb); i++) {
unsigned long hs;
hs = modedb[i].refresh *
(modedb[i].yres + modedb[i].upper_margin +
modedb[i].lower_margin + modedb[i].vsync_len);
if (modedb[i].xres == DEFAULT_XRES &&
modedb[i].yres == DEFAULT_YRES &&
modedb[i].refresh >= fb_info.monspecs.vfmin &&
modedb[i].refresh <= fb_info.monspecs.vfmax &&
hs >= fb_info.monspecs.hfmin &&
hs <= fb_info.monspecs.hfmax) {
acornfb_default_mode = modedb[i];
break;
}
}
fb_info.screen_base = (char *)SCREEN_BASE;
fb_info.fix.smem_start = SCREEN_START;
current_par.using_vram = 0;
/*
* If vram_size is set, we are using VRAM in
* a Risc PC. However, if the user has specified
* an amount of DRAM then use that instead.
*/
if (vram_size && !current_par.dram_size) {
size = vram_size;
current_par.vram_half_sam = vram_size / 1024;
current_par.using_vram = 1;
} else if (current_par.dram_size)
size = current_par.dram_size;
else
size = MAX_SIZE;
/*
* Limit maximum screen size.
*/
if (size > MAX_SIZE)
size = MAX_SIZE;
size = PAGE_ALIGN(size);
#if defined(HAS_VIDC20)
if (!current_par.using_vram) {
dma_addr_t handle;
void *base;
/*
* RiscPC needs to allocate the DRAM memory
* for the framebuffer if we are not using
* VRAM.
*/
base = dma_alloc_wc(current_par.dev, size, &handle,
GFP_KERNEL);
if (base == NULL) {
printk(KERN_ERR "acornfb: unable to allocate screen memory\n");
return -ENOMEM;
}
fb_info.screen_base = base;
fb_info.fix.smem_start = handle;
}
#endif
fb_info.fix.smem_len = size;
current_par.palette_size = VIDC_PALETTE_SIZE;
/*
* Lookup the timing for this resolution. If we can't
* find it, then we can't restore it if we change
* the resolution, so we disable this feature.
*/
do {
rc = fb_find_mode(&fb_info.var, &fb_info, NULL, modedb,
ARRAY_SIZE(modedb),
&acornfb_default_mode, DEFAULT_BPP);
/*
* If we found an exact match, all ok.
*/
if (rc == 1)
break;
rc = fb_find_mode(&fb_info.var, &fb_info, NULL, NULL, 0,
&acornfb_default_mode, DEFAULT_BPP);
/*
* If we found an exact match, all ok.
*/
if (rc == 1)
break;
rc = fb_find_mode(&fb_info.var, &fb_info, NULL, modedb,
ARRAY_SIZE(modedb),
&acornfb_default_mode, DEFAULT_BPP);
if (rc)
break;
rc = fb_find_mode(&fb_info.var, &fb_info, NULL, NULL, 0,
&acornfb_default_mode, DEFAULT_BPP);
} while (0);
/*
* If we didn't find an exact match, try the
* generic database.
*/
if (rc == 0) {
printk("Acornfb: no valid mode found\n");
return -EINVAL;
}
h_sync = 1953125000 / fb_info.var.pixclock;
h_sync = h_sync * 512 / (fb_info.var.xres + fb_info.var.left_margin +
fb_info.var.right_margin + fb_info.var.hsync_len);
v_sync = h_sync / (fb_info.var.yres + fb_info.var.upper_margin +
fb_info.var.lower_margin + fb_info.var.vsync_len);
printk(KERN_INFO "Acornfb: %dkB %cRAM, %s, using %dx%d, %d.%03dkHz, %dHz\n",
fb_info.fix.smem_len / 1024,
current_par.using_vram ? 'V' : 'D',
VIDC_NAME, fb_info.var.xres, fb_info.var.yres,
h_sync / 1000, h_sync % 1000, v_sync);
printk(KERN_INFO "Acornfb: Monitor: %d.%03d-%d.%03dkHz, %d-%dHz%s\n",
fb_info.monspecs.hfmin / 1000, fb_info.monspecs.hfmin % 1000,
fb_info.monspecs.hfmax / 1000, fb_info.monspecs.hfmax % 1000,
fb_info.monspecs.vfmin, fb_info.monspecs.vfmax,
fb_info.monspecs.dpms ? ", DPMS" : "");
if (fb_set_var(&fb_info, &fb_info.var))
printk(KERN_ERR "Acornfb: unable to set display parameters\n");
if (register_framebuffer(&fb_info) < 0)
return -EINVAL;
return 0;
}
static struct platform_driver acornfb_driver = {
.probe = acornfb_probe,
.driver = {
.name = "acornfb",
},
};
static int __init acornfb_init(void)
{
return platform_driver_register(&acornfb_driver);
}
module_init(acornfb_init);
MODULE_AUTHOR("Russell King");
MODULE_DESCRIPTION("VIDC 1/1a/20 framebuffer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/acornfb.c |
/*
* linux/drivers/video/vfb.c -- Virtual frame buffer device
*
* Copyright (C) 2002 James Simmons
*
* Copyright (C) 1997 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <linux/init.h>
/*
* RAM we reserve for the frame buffer. This defines the maximum screen
* size
*
* The default can be overridden if the driver is compiled as a module
*/
#define VIDEOMEMSIZE (1*1024*1024) /* 1 MB */
static void *videomemory;
static u_long videomemorysize = VIDEOMEMSIZE;
module_param(videomemorysize, ulong, 0);
MODULE_PARM_DESC(videomemorysize, "RAM available to frame buffer (in bytes)");
static char *mode_option = NULL;
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Preferred video mode (e.g. 640x480-8@60)");
static const struct fb_videomode vfb_default = {
.xres = 640,
.yres = 480,
.pixclock = 20000,
.left_margin = 64,
.right_margin = 64,
.upper_margin = 32,
.lower_margin = 32,
.hsync_len = 64,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_fix_screeninfo vfb_fix = {
.id = "Virtual FB",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 1,
.ypanstep = 1,
.ywrapstep = 1,
.accel = FB_ACCEL_NONE,
};
static bool vfb_enable __initdata = 0; /* disabled by default */
module_param(vfb_enable, bool, 0);
MODULE_PARM_DESC(vfb_enable, "Enable Virtual FB driver");
static int vfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info);
static int vfb_set_par(struct fb_info *info);
static int vfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int vfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info);
static int vfb_mmap(struct fb_info *info,
struct vm_area_struct *vma);
static const struct fb_ops vfb_ops = {
.owner = THIS_MODULE,
.fb_read = fb_sys_read,
.fb_write = fb_sys_write,
.fb_check_var = vfb_check_var,
.fb_set_par = vfb_set_par,
.fb_setcolreg = vfb_setcolreg,
.fb_pan_display = vfb_pan_display,
.fb_fillrect = sys_fillrect,
.fb_copyarea = sys_copyarea,
.fb_imageblit = sys_imageblit,
.fb_mmap = vfb_mmap,
};
/*
* Internal routines
*/
static u_long get_line_length(int xres_virtual, int bpp)
{
u_long length;
length = xres_virtual * bpp;
length = (length + 31) & ~31;
length >>= 3;
return (length);
}
/*
* Setting the video mode has been split into two parts.
* First part, xxxfb_check_var, must not write anything
* to hardware, it should only verify and adjust var.
* This means it doesn't alter par but it does use hardware
* data from it to check this var.
*/
static int vfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
u_long line_length;
/*
* FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
* as FB_VMODE_SMOOTH_XPAN is only used internally
*/
if (var->vmode & FB_VMODE_CONUPDATE) {
var->vmode |= FB_VMODE_YWRAP;
var->xoffset = info->var.xoffset;
var->yoffset = info->var.yoffset;
}
/*
* Some very basic checks
*/
if (!var->xres)
var->xres = 1;
if (!var->yres)
var->yres = 1;
if (var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
if (var->bits_per_pixel <= 1)
var->bits_per_pixel = 1;
else if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel <= 24)
var->bits_per_pixel = 24;
else if (var->bits_per_pixel <= 32)
var->bits_per_pixel = 32;
else
return -EINVAL;
if (var->xres_virtual < var->xoffset + var->xres)
var->xres_virtual = var->xoffset + var->xres;
if (var->yres_virtual < var->yoffset + var->yres)
var->yres_virtual = var->yoffset + var->yres;
/*
* Memory limit
*/
line_length =
get_line_length(var->xres_virtual, var->bits_per_pixel);
if (line_length * var->yres_virtual > videomemorysize)
return -ENOMEM;
/*
* Now that we checked it we alter var. The reason being is that the video
* mode passed in might not work but slight changes to it might make it
* work. This way we let the user know what is acceptable.
*/
switch (var->bits_per_pixel) {
case 1:
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16: /* RGBA 5551 */
if (var->transp.length) {
var->red.offset = 0;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 10;
var->blue.length = 5;
var->transp.offset = 15;
var->transp.length = 1;
} else { /* RGB 565 */
var->red.offset = 0;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 11;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
}
break;
case 24: /* RGB 888 */
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 32: /* RGBA 8888 */
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
return 0;
}
/* This routine actually sets the video mode. It's in here where we
* the hardware state info->par and fix which can be affected by the
* change in par. For this driver it doesn't do much.
*/
static int vfb_set_par(struct fb_info *info)
{
switch (info->var.bits_per_pixel) {
case 1:
info->fix.visual = FB_VISUAL_MONO01;
break;
case 8:
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
case 24:
case 32:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
}
info->fix.line_length = get_line_length(info->var.xres_virtual,
info->var.bits_per_pixel);
return 0;
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int vfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
if (regno >= 256) /* no. of hw registers */
return 1;
/*
* Program hardware... do anything you want with transp
*/
/* grayscale works only partially under directcolor */
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue =
(red * 77 + green * 151 + blue * 28) >> 8;
}
/* Directcolor:
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* {hardwarespecific} contains width of RAMDAC
* cmap[X] is programmed to (X << red.offset) | (X << green.offset) | (X << blue.offset)
* RAMDAC[X] is programmed to (red, green, blue)
*
* Pseudocolor:
* var->{color}.offset is 0 unless the palette index takes less than
* bits_per_pixel bits and is stored in the upper
* bits of the pixel value
* var->{color}.length is set so that 1 << length is the number of available
* palette entries
* cmap is not used
* RAMDAC[X] is programmed to (red, green, blue)
*
* Truecolor:
* does not use DAC. Usually 3 are present.
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* cmap is programmed to (red << red.offset) | (green << green.offset) |
* (blue << blue.offset) | (transp << transp.offset)
* RAMDAC does not exist
*/
#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
case FB_VISUAL_PSEUDOCOLOR:
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
transp = CNVT_TOHW(transp, info->var.transp.length);
break;
case FB_VISUAL_DIRECTCOLOR:
red = CNVT_TOHW(red, 8); /* expect 8 bit DAC */
green = CNVT_TOHW(green, 8);
blue = CNVT_TOHW(blue, 8);
/* hey, there is bug in transp handling... */
transp = CNVT_TOHW(transp, 8);
break;
}
#undef CNVT_TOHW
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 v;
if (regno >= 16)
return 1;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
switch (info->var.bits_per_pixel) {
case 8:
break;
case 16:
((u32 *) (info->pseudo_palette))[regno] = v;
break;
case 24:
case 32:
((u32 *) (info->pseudo_palette))[regno] = v;
break;
}
return 0;
}
return 0;
}
/*
* Pan or Wrap the Display
*
* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
*/
static int vfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if (var->vmode & FB_VMODE_YWRAP) {
if (var->yoffset >= info->var.yres_virtual ||
var->xoffset)
return -EINVAL;
} else {
if (var->xoffset + info->var.xres > info->var.xres_virtual ||
var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
}
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP)
info->var.vmode |= FB_VMODE_YWRAP;
else
info->var.vmode &= ~FB_VMODE_YWRAP;
return 0;
}
/*
* Most drivers don't need their own mmap function
*/
static int vfb_mmap(struct fb_info *info,
struct vm_area_struct *vma)
{
return remap_vmalloc_range(vma, (void *)info->fix.smem_start, vma->vm_pgoff);
}
#ifndef MODULE
/*
* The virtual framebuffer driver is only enabled if explicitly
* requested by passing 'video=vfb:' (or any actual options).
*/
static int __init vfb_setup(char *options)
{
char *this_opt;
vfb_enable = 0;
if (!options)
return 1;
vfb_enable = 1;
if (!*options)
return 1;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
/* Test disable for backwards compatibility */
if (!strcmp(this_opt, "disable"))
vfb_enable = 0;
else
mode_option = this_opt;
}
return 1;
}
#endif /* MODULE */
/*
* Initialisation
*/
static int vfb_probe(struct platform_device *dev)
{
struct fb_info *info;
unsigned int size = PAGE_ALIGN(videomemorysize);
int retval = -ENOMEM;
/*
* For real video cards we use ioremap.
*/
if (!(videomemory = vmalloc_32_user(size)))
return retval;
info = framebuffer_alloc(sizeof(u32) * 256, &dev->dev);
if (!info)
goto err;
info->screen_buffer = videomemory;
info->fbops = &vfb_ops;
if (!fb_find_mode(&info->var, info, mode_option,
NULL, 0, &vfb_default, 8)){
fb_err(info, "Unable to find usable video mode.\n");
retval = -EINVAL;
goto err1;
}
vfb_fix.smem_start = (unsigned long) videomemory;
vfb_fix.smem_len = videomemorysize;
info->fix = vfb_fix;
info->pseudo_palette = info->par;
info->par = NULL;
retval = fb_alloc_cmap(&info->cmap, 256, 0);
if (retval < 0)
goto err1;
retval = register_framebuffer(info);
if (retval < 0)
goto err2;
platform_set_drvdata(dev, info);
vfb_set_par(info);
fb_info(info, "Virtual frame buffer device, using %ldK of video memory\n",
videomemorysize >> 10);
return 0;
err2:
fb_dealloc_cmap(&info->cmap);
err1:
framebuffer_release(info);
err:
vfree(videomemory);
return retval;
}
static void vfb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
if (info) {
unregister_framebuffer(info);
vfree(videomemory);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
}
static struct platform_driver vfb_driver = {
.probe = vfb_probe,
.remove_new = vfb_remove,
.driver = {
.name = "vfb",
},
};
static struct platform_device *vfb_device;
static int __init vfb_init(void)
{
int ret = 0;
#ifndef MODULE
char *option = NULL;
if (fb_get_options("vfb", &option))
return -ENODEV;
vfb_setup(option);
#endif
if (!vfb_enable)
return -ENXIO;
ret = platform_driver_register(&vfb_driver);
if (!ret) {
vfb_device = platform_device_alloc("vfb", 0);
if (vfb_device)
ret = platform_device_add(vfb_device);
else
ret = -ENOMEM;
if (ret) {
platform_device_put(vfb_device);
platform_driver_unregister(&vfb_driver);
}
}
return ret;
}
module_init(vfb_init);
#ifdef MODULE
static void __exit vfb_exit(void)
{
platform_device_unregister(vfb_device);
platform_driver_unregister(&vfb_driver);
}
module_exit(vfb_exit);
MODULE_LICENSE("GPL");
#endif /* MODULE */
| linux-master | drivers/video/fbdev/vfb.c |
/*
* linux/drivers/video/offb.c -- Open Firmware based frame buffer device
*
* Copyright (C) 1997 Geert Uytterhoeven
*
* This driver is partly based on the PowerMac console driver:
*
* Copyright (C) 1996 Paul Mackerras
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#ifdef CONFIG_PPC32
#include <asm/bootx.h>
#endif
#include "macmodes.h"
/* Supported palette hacks */
enum {
cmap_unknown,
cmap_simple, /* ATI Mach64 */
cmap_r128, /* ATI Rage128 */
cmap_M3A, /* ATI Rage Mobility M3 Head A */
cmap_M3B, /* ATI Rage Mobility M3 Head B */
cmap_radeon, /* ATI Radeon */
cmap_gxt2000, /* IBM GXT2000 */
cmap_avivo, /* ATI R5xx */
cmap_qemu, /* qemu vga */
};
struct offb_par {
volatile void __iomem *cmap_adr;
volatile void __iomem *cmap_data;
int cmap_type;
int blanked;
u32 pseudo_palette[16];
resource_size_t base;
resource_size_t size;
};
#ifdef CONFIG_PPC32
extern boot_infos_t *boot_infos;
#endif
/* Definitions used by the Avivo palette hack */
#define AVIVO_DC_LUT_RW_SELECT 0x6480
#define AVIVO_DC_LUT_RW_MODE 0x6484
#define AVIVO_DC_LUT_RW_INDEX 0x6488
#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
#define AVIVO_DC_LUT_PWL_DATA 0x6490
#define AVIVO_DC_LUT_30_COLOR 0x6494
#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
#define AVIVO_DC_LUT_AUTOFILL 0x64a0
#define AVIVO_DC_LUTA_CONTROL 0x64c0
#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
#define AVIVO_DC_LUTB_CONTROL 0x6cc0
#define AVIVO_DC_LUTB_BLACK_OFFSET_BLUE 0x6cc4
#define AVIVO_DC_LUTB_BLACK_OFFSET_GREEN 0x6cc8
#define AVIVO_DC_LUTB_BLACK_OFFSET_RED 0x6ccc
#define AVIVO_DC_LUTB_WHITE_OFFSET_BLUE 0x6cd0
#define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4
#define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int offb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct offb_par *par = (struct offb_par *) info->par;
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *pal = info->pseudo_palette;
u32 cr = red >> (16 - info->var.red.length);
u32 cg = green >> (16 - info->var.green.length);
u32 cb = blue >> (16 - info->var.blue.length);
u32 value;
if (regno >= 16)
return -EINVAL;
value = (cr << info->var.red.offset) |
(cg << info->var.green.offset) |
(cb << info->var.blue.offset);
if (info->var.transp.length > 0) {
u32 mask = (1 << info->var.transp.length) - 1;
mask <<= info->var.transp.offset;
value |= mask;
}
pal[regno] = value;
return 0;
}
if (regno > 255)
return -EINVAL;
red >>= 8;
green >>= 8;
blue >>= 8;
if (!par->cmap_adr)
return 0;
switch (par->cmap_type) {
case cmap_simple:
writeb(regno, par->cmap_adr);
writeb(red, par->cmap_data);
writeb(green, par->cmap_data);
writeb(blue, par->cmap_data);
break;
case cmap_M3A:
/* Clear PALETTE_ACCESS_CNTL in DAC_CNTL */
out_le32(par->cmap_adr + 0x58,
in_le32(par->cmap_adr + 0x58) & ~0x20);
fallthrough;
case cmap_r128:
/* Set palette index & data */
out_8(par->cmap_adr + 0xb0, regno);
out_le32(par->cmap_adr + 0xb4,
(red << 16 | green << 8 | blue));
break;
case cmap_M3B:
/* Set PALETTE_ACCESS_CNTL in DAC_CNTL */
out_le32(par->cmap_adr + 0x58,
in_le32(par->cmap_adr + 0x58) | 0x20);
/* Set palette index & data */
out_8(par->cmap_adr + 0xb0, regno);
out_le32(par->cmap_adr + 0xb4, (red << 16 | green << 8 | blue));
break;
case cmap_radeon:
/* Set palette index & data (could be smarter) */
out_8(par->cmap_adr + 0xb0, regno);
out_le32(par->cmap_adr + 0xb4, (red << 16 | green << 8 | blue));
break;
case cmap_gxt2000:
out_le32(((unsigned __iomem *) par->cmap_adr) + regno,
(red << 16 | green << 8 | blue));
break;
case cmap_avivo:
/* Write to both LUTs for now */
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writeb(regno, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
writel(((red) << 22) | ((green) << 12) | ((blue) << 2),
par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writeb(regno, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
writel(((red) << 22) | ((green) << 12) | ((blue) << 2),
par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
break;
}
return 0;
}
/*
* Blank the display.
*/
static int offb_blank(int blank, struct fb_info *info)
{
struct offb_par *par = (struct offb_par *) info->par;
int i, j;
if (!par->cmap_adr)
return 0;
if (!par->blanked)
if (!blank)
return 0;
par->blanked = blank;
if (blank)
for (i = 0; i < 256; i++) {
switch (par->cmap_type) {
case cmap_simple:
writeb(i, par->cmap_adr);
for (j = 0; j < 3; j++)
writeb(0, par->cmap_data);
break;
case cmap_M3A:
/* Clear PALETTE_ACCESS_CNTL in DAC_CNTL */
out_le32(par->cmap_adr + 0x58,
in_le32(par->cmap_adr + 0x58) & ~0x20);
fallthrough;
case cmap_r128:
/* Set palette index & data */
out_8(par->cmap_adr + 0xb0, i);
out_le32(par->cmap_adr + 0xb4, 0);
break;
case cmap_M3B:
/* Set PALETTE_ACCESS_CNTL in DAC_CNTL */
out_le32(par->cmap_adr + 0x58,
in_le32(par->cmap_adr + 0x58) | 0x20);
/* Set palette index & data */
out_8(par->cmap_adr + 0xb0, i);
out_le32(par->cmap_adr + 0xb4, 0);
break;
case cmap_radeon:
out_8(par->cmap_adr + 0xb0, i);
out_le32(par->cmap_adr + 0xb4, 0);
break;
case cmap_gxt2000:
out_le32(((unsigned __iomem *) par->cmap_adr) + i,
0);
break;
case cmap_avivo:
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writeb(i, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writeb(i, par->cmap_adr + AVIVO_DC_LUT_RW_INDEX);
writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR);
break;
}
} else
fb_set_cmap(&info->cmap, info);
return 0;
}
static int offb_set_par(struct fb_info *info)
{
struct offb_par *par = (struct offb_par *) info->par;
/* On avivo, initialize palette control */
if (par->cmap_type == cmap_avivo) {
writel(0, par->cmap_adr + AVIVO_DC_LUTA_CONTROL);
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_BLUE);
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_GREEN);
writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_RED);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_BLUE);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_GREEN);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_RED);
writel(0, par->cmap_adr + AVIVO_DC_LUTB_CONTROL);
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_BLUE);
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_GREEN);
writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_RED);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_BLUE);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_GREEN);
writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_RED);
writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE);
writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT);
writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE);
writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK);
}
return 0;
}
static void offb_destroy(struct fb_info *info)
{
struct offb_par *par = info->par;
if (info->screen_base)
iounmap(info->screen_base);
release_mem_region(par->base, par->size);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
static const struct fb_ops offb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_destroy = offb_destroy,
.fb_setcolreg = offb_setcolreg,
.fb_set_par = offb_set_par,
.fb_blank = offb_blank,
};
static void __iomem *offb_map_reg(struct device_node *np, int index,
unsigned long offset, unsigned long size)
{
const __be32 *addrp;
u64 asize, taddr;
unsigned int flags;
addrp = of_get_pci_address(np, index, &asize, &flags);
if (addrp == NULL)
addrp = of_get_address(np, index, &asize, &flags);
if (addrp == NULL)
return NULL;
if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
return NULL;
if ((offset + size) > asize)
return NULL;
taddr = of_translate_address(np, addrp);
if (taddr == OF_BAD_ADDR)
return NULL;
return ioremap(taddr + offset, size);
}
static void offb_init_palette_hacks(struct fb_info *info, struct device_node *dp,
unsigned long address)
{
struct offb_par *par = (struct offb_par *) info->par;
if (of_node_name_prefix(dp, "ATY,Rage128")) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_r128;
} else if (of_node_name_prefix(dp, "ATY,RageM3pA") ||
of_node_name_prefix(dp, "ATY,RageM3p12A")) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_M3A;
} else if (of_node_name_prefix(dp, "ATY,RageM3pB")) {
par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_M3B;
} else if (of_node_name_prefix(dp, "ATY,Rage6")) {
par->cmap_adr = offb_map_reg(dp, 1, 0, 0x1fff);
if (par->cmap_adr)
par->cmap_type = cmap_radeon;
} else if (of_node_name_prefix(dp, "ATY,")) {
unsigned long base = address & 0xff000000UL;
par->cmap_adr =
ioremap(base + 0x7ff000, 0x1000) + 0xcc0;
par->cmap_data = par->cmap_adr + 1;
par->cmap_type = cmap_simple;
} else if (dp && (of_device_is_compatible(dp, "pci1014,b7") ||
of_device_is_compatible(dp, "pci1014,21c"))) {
par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000);
if (par->cmap_adr)
par->cmap_type = cmap_gxt2000;
} else if (of_node_name_prefix(dp, "vga,Display-")) {
/* Look for AVIVO initialized by SLOF */
struct device_node *pciparent = of_get_parent(dp);
const u32 *vid, *did;
vid = of_get_property(pciparent, "vendor-id", NULL);
did = of_get_property(pciparent, "device-id", NULL);
/* This will match most R5xx */
if (vid && did && *vid == 0x1002 &&
((*did >= 0x7100 && *did < 0x7800) ||
(*did >= 0x9400))) {
par->cmap_adr = offb_map_reg(pciparent, 2, 0, 0x10000);
if (par->cmap_adr)
par->cmap_type = cmap_avivo;
}
of_node_put(pciparent);
} else if (dp && of_device_is_compatible(dp, "qemu,std-vga")) {
#ifdef __BIG_ENDIAN
const __be32 io_of_addr[3] = { 0x01000000, 0x0, 0x0 };
#else
const __be32 io_of_addr[3] = { 0x00000001, 0x0, 0x0 };
#endif
u64 io_addr = of_translate_address(dp, io_of_addr);
if (io_addr != OF_BAD_ADDR) {
par->cmap_adr = ioremap(io_addr + 0x3c8, 2);
if (par->cmap_adr) {
par->cmap_type = cmap_simple;
par->cmap_data = par->cmap_adr + 1;
}
}
}
info->fix.visual = (par->cmap_type != cmap_unknown) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_STATIC_PSEUDOCOLOR;
}
static void offb_init_fb(struct platform_device *parent, const char *name,
int width, int height, int depth,
int pitch, unsigned long address,
int foreign_endian, struct device_node *dp)
{
unsigned long res_size = pitch * height;
unsigned long res_start = address;
struct fb_fix_screeninfo *fix;
struct fb_var_screeninfo *var;
struct fb_info *info;
struct offb_par *par;
if (!request_mem_region(res_start, res_size, "offb"))
return;
printk(KERN_INFO
"Using unsupported %dx%d %s at %lx, depth=%d, pitch=%d\n",
width, height, name, address, depth, pitch);
if (depth != 8 && depth != 15 && depth != 16 && depth != 32) {
printk(KERN_ERR "%pOF: can't use depth = %d\n", dp, depth);
release_mem_region(res_start, res_size);
return;
}
info = framebuffer_alloc(sizeof(*par), &parent->dev);
if (!info) {
release_mem_region(res_start, res_size);
return;
}
platform_set_drvdata(parent, info);
par = info->par;
fix = &info->fix;
var = &info->var;
if (name) {
strcpy(fix->id, "OFfb ");
strncat(fix->id, name, sizeof(fix->id) - sizeof("OFfb "));
fix->id[sizeof(fix->id) - 1] = '\0';
} else
snprintf(fix->id, sizeof(fix->id), "OFfb %pOFn", dp);
var->xres = var->xres_virtual = width;
var->yres = var->yres_virtual = height;
fix->line_length = pitch;
fix->smem_start = address;
fix->smem_len = pitch * height;
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
par->cmap_type = cmap_unknown;
if (depth == 8)
offb_init_palette_hacks(info, dp, address);
else
fix->visual = FB_VISUAL_TRUECOLOR;
var->xoffset = var->yoffset = 0;
switch (depth) {
case 8:
var->bits_per_pixel = 8;
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 15: /* RGB 555 */
var->bits_per_pixel = 16;
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16: /* RGB 565 */
var->bits_per_pixel = 16;
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 32: /* RGB 888 */
var->bits_per_pixel = 32;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
}
var->red.msb_right = var->green.msb_right = var->blue.msb_right =
var->transp.msb_right = 0;
var->grayscale = 0;
var->nonstd = 0;
var->activate = 0;
var->height = var->width = -1;
var->pixclock = 10000;
var->left_margin = var->right_margin = 16;
var->upper_margin = var->lower_margin = 16;
var->hsync_len = var->vsync_len = 8;
var->sync = 0;
var->vmode = FB_VMODE_NONINTERLACED;
par->base = address;
par->size = fix->smem_len;
info->fbops = &offb_ops;
info->screen_base = ioremap(address, fix->smem_len);
info->pseudo_palette = par->pseudo_palette;
info->flags = foreign_endian;
fb_alloc_cmap(&info->cmap, 256, 0);
if (devm_aperture_acquire_for_platform_device(parent, par->base, par->size) < 0)
goto out_err;
if (register_framebuffer(info) < 0)
goto out_err;
fb_info(info, "Open Firmware frame buffer device on %pOF\n", dp);
return;
out_err:
fb_dealloc_cmap(&info->cmap);
iounmap(info->screen_base);
iounmap(par->cmap_adr);
par->cmap_adr = NULL;
framebuffer_release(info);
release_mem_region(res_start, res_size);
}
static void offb_init_nodriver(struct platform_device *parent, struct device_node *dp,
int no_real_node)
{
unsigned int len;
int i, width = 640, height = 480, depth = 8, pitch = 640;
unsigned int flags, rsize, addr_prop = 0;
unsigned long max_size = 0;
u64 rstart, address = OF_BAD_ADDR;
const __be32 *pp, *addrp, *up;
u64 asize;
int foreign_endian = 0;
#ifdef __BIG_ENDIAN
if (of_property_read_bool(dp, "little-endian"))
foreign_endian = FBINFO_FOREIGN_ENDIAN;
#else
if (of_property_read_bool(dp, "big-endian"))
foreign_endian = FBINFO_FOREIGN_ENDIAN;
#endif
pp = of_get_property(dp, "linux,bootx-depth", &len);
if (pp == NULL)
pp = of_get_property(dp, "depth", &len);
if (pp && len == sizeof(u32))
depth = be32_to_cpup(pp);
pp = of_get_property(dp, "linux,bootx-width", &len);
if (pp == NULL)
pp = of_get_property(dp, "width", &len);
if (pp && len == sizeof(u32))
width = be32_to_cpup(pp);
pp = of_get_property(dp, "linux,bootx-height", &len);
if (pp == NULL)
pp = of_get_property(dp, "height", &len);
if (pp && len == sizeof(u32))
height = be32_to_cpup(pp);
pp = of_get_property(dp, "linux,bootx-linebytes", &len);
if (pp == NULL)
pp = of_get_property(dp, "linebytes", &len);
if (pp && len == sizeof(u32) && (*pp != 0xffffffffu))
pitch = be32_to_cpup(pp);
else
pitch = width * ((depth + 7) / 8);
rsize = (unsigned long)pitch * (unsigned long)height;
/* Ok, now we try to figure out the address of the framebuffer.
*
* Unfortunately, Open Firmware doesn't provide a standard way to do
* so. All we can do is a dodgy heuristic that happens to work in
* practice. On most machines, the "address" property contains what
* we need, though not on Matrox cards found in IBM machines. What I've
* found that appears to give good results is to go through the PCI
* ranges and pick one that is both big enough and if possible encloses
* the "address" property. If none match, we pick the biggest
*/
up = of_get_property(dp, "linux,bootx-addr", &len);
if (up == NULL)
up = of_get_property(dp, "address", &len);
if (up && len == sizeof(u32))
addr_prop = *up;
/* Hack for when BootX is passing us */
if (no_real_node)
goto skip_addr;
for (i = 0; (addrp = of_get_address(dp, i, &asize, &flags))
!= NULL; i++) {
int match_addrp = 0;
if (!(flags & IORESOURCE_MEM))
continue;
if (asize < rsize)
continue;
rstart = of_translate_address(dp, addrp);
if (rstart == OF_BAD_ADDR)
continue;
if (addr_prop && (rstart <= addr_prop) &&
((rstart + asize) >= (addr_prop + rsize)))
match_addrp = 1;
if (match_addrp) {
address = addr_prop;
break;
}
if (rsize > max_size) {
max_size = rsize;
address = OF_BAD_ADDR;
}
if (address == OF_BAD_ADDR)
address = rstart;
}
skip_addr:
if (address == OF_BAD_ADDR && addr_prop)
address = (u64)addr_prop;
if (address != OF_BAD_ADDR) {
#ifdef CONFIG_PCI
const __be32 *vidp, *didp;
u32 vid, did;
struct pci_dev *pdev;
vidp = of_get_property(dp, "vendor-id", NULL);
didp = of_get_property(dp, "device-id", NULL);
if (vidp && didp) {
vid = be32_to_cpup(vidp);
did = be32_to_cpup(didp);
pdev = pci_get_device(vid, did, NULL);
if (!pdev || pci_enable_device(pdev))
return;
}
#endif
/* kludge for valkyrie */
if (of_node_name_eq(dp, "valkyrie"))
address += 0x1000;
offb_init_fb(parent, no_real_node ? "bootx" : NULL,
width, height, depth, pitch, address,
foreign_endian, no_real_node ? NULL : dp);
}
}
static void offb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
if (info)
unregister_framebuffer(info);
}
static int offb_probe_bootx_noscreen(struct platform_device *pdev)
{
offb_init_nodriver(pdev, of_chosen, 1);
return 0;
}
static struct platform_driver offb_driver_bootx_noscreen = {
.driver = {
.name = "bootx-noscreen",
},
.probe = offb_probe_bootx_noscreen,
.remove_new = offb_remove,
};
static int offb_probe_display(struct platform_device *pdev)
{
offb_init_nodriver(pdev, pdev->dev.of_node, 0);
return 0;
}
static const struct of_device_id offb_of_match_display[] = {
{ .compatible = "display", },
{ },
};
MODULE_DEVICE_TABLE(of, offb_of_match_display);
static struct platform_driver offb_driver_display = {
.driver = {
.name = "of-display",
.of_match_table = offb_of_match_display,
},
.probe = offb_probe_display,
.remove_new = offb_remove,
};
static int __init offb_init(void)
{
if (fb_get_options("offb", NULL))
return -ENODEV;
platform_driver_register(&offb_driver_bootx_noscreen);
platform_driver_register(&offb_driver_display);
return 0;
}
module_init(offb_init);
static void __exit offb_exit(void)
{
platform_driver_unregister(&offb_driver_display);
platform_driver_unregister(&offb_driver_bootx_noscreen);
}
module_exit(offb_exit);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/offb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for the Solomon SSD1307 OLED controller
*
* Copyright 2012 Free Electrons
*/
#include <linux/backlight.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/pwm.h>
#include <linux/uaccess.h>
#include <linux/regulator/consumer.h>
#define SSD1307FB_DATA 0x40
#define SSD1307FB_COMMAND 0x80
#define SSD1307FB_SET_ADDRESS_MODE 0x20
#define SSD1307FB_SET_ADDRESS_MODE_HORIZONTAL (0x00)
#define SSD1307FB_SET_ADDRESS_MODE_VERTICAL (0x01)
#define SSD1307FB_SET_ADDRESS_MODE_PAGE (0x02)
#define SSD1307FB_SET_COL_RANGE 0x21
#define SSD1307FB_SET_PAGE_RANGE 0x22
#define SSD1307FB_CONTRAST 0x81
#define SSD1307FB_SET_LOOKUP_TABLE 0x91
#define SSD1307FB_CHARGE_PUMP 0x8d
#define SSD1307FB_SEG_REMAP_ON 0xa1
#define SSD1307FB_DISPLAY_OFF 0xae
#define SSD1307FB_SET_MULTIPLEX_RATIO 0xa8
#define SSD1307FB_DISPLAY_ON 0xaf
#define SSD1307FB_START_PAGE_ADDRESS 0xb0
#define SSD1307FB_SET_DISPLAY_OFFSET 0xd3
#define SSD1307FB_SET_CLOCK_FREQ 0xd5
#define SSD1307FB_SET_AREA_COLOR_MODE 0xd8
#define SSD1307FB_SET_PRECHARGE_PERIOD 0xd9
#define SSD1307FB_SET_COM_PINS_CONFIG 0xda
#define SSD1307FB_SET_VCOMH 0xdb
#define MAX_CONTRAST 255
#define REFRESHRATE 1
static u_int refreshrate = REFRESHRATE;
module_param(refreshrate, uint, 0);
struct ssd1307fb_deviceinfo {
u32 default_vcomh;
u32 default_dclk_div;
u32 default_dclk_frq;
bool need_pwm;
bool need_chargepump;
};
struct ssd1307fb_par {
unsigned area_color_enable : 1;
unsigned com_invdir : 1;
unsigned com_lrremap : 1;
unsigned com_seq : 1;
unsigned lookup_table_set : 1;
unsigned low_power : 1;
unsigned seg_remap : 1;
u32 com_offset;
u32 contrast;
u32 dclk_div;
u32 dclk_frq;
const struct ssd1307fb_deviceinfo *device_info;
struct i2c_client *client;
u32 height;
struct fb_info *info;
u8 lookup_table[4];
u32 page_offset;
u32 col_offset;
u32 prechargep1;
u32 prechargep2;
struct pwm_device *pwm;
struct gpio_desc *reset;
struct regulator *vbat_reg;
u32 vcomh;
u32 width;
/* Cached address ranges */
u8 col_start;
u8 col_end;
u8 page_start;
u8 page_end;
};
struct ssd1307fb_array {
u8 type;
u8 data[];
};
static const struct fb_fix_screeninfo ssd1307fb_fix = {
.id = "Solomon SSD1307",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_MONO10,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static const struct fb_var_screeninfo ssd1307fb_var = {
.bits_per_pixel = 1,
.red = { .length = 1 },
.green = { .length = 1 },
.blue = { .length = 1 },
};
static struct ssd1307fb_array *ssd1307fb_alloc_array(u32 len, u8 type)
{
struct ssd1307fb_array *array;
array = kzalloc(sizeof(struct ssd1307fb_array) + len, GFP_KERNEL);
if (!array)
return NULL;
array->type = type;
return array;
}
static int ssd1307fb_write_array(struct i2c_client *client,
struct ssd1307fb_array *array, u32 len)
{
int ret;
len += sizeof(struct ssd1307fb_array);
ret = i2c_master_send(client, (u8 *)array, len);
if (ret != len) {
dev_err(&client->dev, "Couldn't send I2C command.\n");
return ret;
}
return 0;
}
static inline int ssd1307fb_write_cmd(struct i2c_client *client, u8 cmd)
{
struct ssd1307fb_array *array;
int ret;
array = ssd1307fb_alloc_array(1, SSD1307FB_COMMAND);
if (!array)
return -ENOMEM;
array->data[0] = cmd;
ret = ssd1307fb_write_array(client, array, 1);
kfree(array);
return ret;
}
static int ssd1307fb_set_col_range(struct ssd1307fb_par *par, u8 col_start,
u8 cols)
{
u8 col_end = col_start + cols - 1;
int ret;
if (col_start == par->col_start && col_end == par->col_end)
return 0;
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_COL_RANGE);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, col_start);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, col_end);
if (ret < 0)
return ret;
par->col_start = col_start;
par->col_end = col_end;
return 0;
}
static int ssd1307fb_set_page_range(struct ssd1307fb_par *par, u8 page_start,
u8 pages)
{
u8 page_end = page_start + pages - 1;
int ret;
if (page_start == par->page_start && page_end == par->page_end)
return 0;
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_PAGE_RANGE);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, page_start);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, page_end);
if (ret < 0)
return ret;
par->page_start = page_start;
par->page_end = page_end;
return 0;
}
static int ssd1307fb_update_rect(struct ssd1307fb_par *par, unsigned int x,
unsigned int y, unsigned int width,
unsigned int height)
{
struct ssd1307fb_array *array;
u8 *vmem = par->info->screen_buffer;
unsigned int line_length = par->info->fix.line_length;
unsigned int pages = DIV_ROUND_UP(y % 8 + height, 8);
u32 array_idx = 0;
int ret, i, j, k;
array = ssd1307fb_alloc_array(width * pages, SSD1307FB_DATA);
if (!array)
return -ENOMEM;
/*
* The screen is divided in pages, each having a height of 8
* pixels, and the width of the screen. When sending a byte of
* data to the controller, it gives the 8 bits for the current
* column. I.e, the first byte are the 8 bits of the first
* column, then the 8 bits for the second column, etc.
*
*
* Representation of the screen, assuming it is 5 bits
* wide. Each letter-number combination is a bit that controls
* one pixel.
*
* A0 A1 A2 A3 A4
* B0 B1 B2 B3 B4
* C0 C1 C2 C3 C4
* D0 D1 D2 D3 D4
* E0 E1 E2 E3 E4
* F0 F1 F2 F3 F4
* G0 G1 G2 G3 G4
* H0 H1 H2 H3 H4
*
* If you want to update this screen, you need to send 5 bytes:
* (1) A0 B0 C0 D0 E0 F0 G0 H0
* (2) A1 B1 C1 D1 E1 F1 G1 H1
* (3) A2 B2 C2 D2 E2 F2 G2 H2
* (4) A3 B3 C3 D3 E3 F3 G3 H3
* (5) A4 B4 C4 D4 E4 F4 G4 H4
*/
ret = ssd1307fb_set_col_range(par, par->col_offset + x, width);
if (ret < 0)
goto out_free;
ret = ssd1307fb_set_page_range(par, par->page_offset + y / 8, pages);
if (ret < 0)
goto out_free;
for (i = y / 8; i < y / 8 + pages; i++) {
int m = 8;
/* Last page may be partial */
if (8 * (i + 1) > par->height)
m = par->height % 8;
for (j = x; j < x + width; j++) {
u8 data = 0;
for (k = 0; k < m; k++) {
u8 byte = vmem[(8 * i + k) * line_length +
j / 8];
u8 bit = (byte >> (j % 8)) & 1;
data |= bit << k;
}
array->data[array_idx++] = data;
}
}
ret = ssd1307fb_write_array(par->client, array, width * pages);
out_free:
kfree(array);
return ret;
}
static int ssd1307fb_update_display(struct ssd1307fb_par *par)
{
return ssd1307fb_update_rect(par, 0, 0, par->width, par->height);
}
static int ssd1307fb_blank(int blank_mode, struct fb_info *info)
{
struct ssd1307fb_par *par = info->par;
if (blank_mode != FB_BLANK_UNBLANK)
return ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_OFF);
else
return ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_ON);
}
static void ssd1307fb_defio_damage_range(struct fb_info *info, off_t off, size_t len)
{
struct ssd1307fb_par *par = info->par;
ssd1307fb_update_display(par);
}
static void ssd1307fb_defio_damage_area(struct fb_info *info, u32 x, u32 y,
u32 width, u32 height)
{
struct ssd1307fb_par *par = info->par;
ssd1307fb_update_rect(par, x, y, width, height);
}
FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(ssd1307fb,
ssd1307fb_defio_damage_range,
ssd1307fb_defio_damage_area)
static const struct fb_ops ssd1307fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_DEFERRED_OPS(ssd1307fb),
.fb_blank = ssd1307fb_blank,
};
static void ssd1307fb_deferred_io(struct fb_info *info, struct list_head *pagereflist)
{
ssd1307fb_update_display(info->par);
}
static int ssd1307fb_init(struct ssd1307fb_par *par)
{
struct pwm_state pwmstate;
int ret;
u32 precharge, dclk, com_invdir, compins;
if (par->device_info->need_pwm) {
par->pwm = pwm_get(&par->client->dev, NULL);
if (IS_ERR(par->pwm)) {
dev_err(&par->client->dev, "Could not get PWM from device tree!\n");
return PTR_ERR(par->pwm);
}
pwm_init_state(par->pwm, &pwmstate);
pwm_set_relative_duty_cycle(&pwmstate, 50, 100);
pwm_apply_state(par->pwm, &pwmstate);
/* Enable the PWM */
pwm_enable(par->pwm);
dev_dbg(&par->client->dev, "Using PWM %s with a %lluns period.\n",
par->pwm->label, pwm_get_period(par->pwm));
}
/* Set initial contrast */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CONTRAST);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, par->contrast);
if (ret < 0)
return ret;
/* Set segment re-map */
if (par->seg_remap) {
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SEG_REMAP_ON);
if (ret < 0)
return ret;
}
/* Set COM direction */
com_invdir = 0xc0 | par->com_invdir << 3;
ret = ssd1307fb_write_cmd(par->client, com_invdir);
if (ret < 0)
return ret;
/* Set multiplex ratio value */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_MULTIPLEX_RATIO);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, par->height - 1);
if (ret < 0)
return ret;
/* set display offset value */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_DISPLAY_OFFSET);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, par->com_offset);
if (ret < 0)
return ret;
/* Set clock frequency */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_CLOCK_FREQ);
if (ret < 0)
return ret;
dclk = ((par->dclk_div - 1) & 0xf) | (par->dclk_frq & 0xf) << 4;
ret = ssd1307fb_write_cmd(par->client, dclk);
if (ret < 0)
return ret;
/* Set Area Color Mode ON/OFF & Low Power Display Mode */
if (par->area_color_enable || par->low_power) {
u32 mode;
ret = ssd1307fb_write_cmd(par->client,
SSD1307FB_SET_AREA_COLOR_MODE);
if (ret < 0)
return ret;
mode = (par->area_color_enable ? 0x30 : 0) |
(par->low_power ? 5 : 0);
ret = ssd1307fb_write_cmd(par->client, mode);
if (ret < 0)
return ret;
}
/* Set precharge period in number of ticks from the internal clock */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_PRECHARGE_PERIOD);
if (ret < 0)
return ret;
precharge = (par->prechargep1 & 0xf) | (par->prechargep2 & 0xf) << 4;
ret = ssd1307fb_write_cmd(par->client, precharge);
if (ret < 0)
return ret;
/* Set COM pins configuration */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_COM_PINS_CONFIG);
if (ret < 0)
return ret;
compins = 0x02 | !par->com_seq << 4 | par->com_lrremap << 5;
ret = ssd1307fb_write_cmd(par->client, compins);
if (ret < 0)
return ret;
/* Set VCOMH */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_VCOMH);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, par->vcomh);
if (ret < 0)
return ret;
/* Turn on the DC-DC Charge Pump */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CHARGE_PUMP);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client,
BIT(4) | (par->device_info->need_chargepump ? BIT(2) : 0));
if (ret < 0)
return ret;
/* Set lookup table */
if (par->lookup_table_set) {
int i;
ret = ssd1307fb_write_cmd(par->client,
SSD1307FB_SET_LOOKUP_TABLE);
if (ret < 0)
return ret;
for (i = 0; i < ARRAY_SIZE(par->lookup_table); ++i) {
u8 val = par->lookup_table[i];
if (val < 31 || val > 63)
dev_warn(&par->client->dev,
"lookup table index %d value out of range 31 <= %d <= 63\n",
i, val);
ret = ssd1307fb_write_cmd(par->client, val);
if (ret < 0)
return ret;
}
}
/* Switch to horizontal addressing mode */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_SET_ADDRESS_MODE);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client,
SSD1307FB_SET_ADDRESS_MODE_HORIZONTAL);
if (ret < 0)
return ret;
/* Clear the screen */
ret = ssd1307fb_update_display(par);
if (ret < 0)
return ret;
/* Turn on the display */
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_ON);
if (ret < 0)
return ret;
return 0;
}
static int ssd1307fb_update_bl(struct backlight_device *bdev)
{
struct ssd1307fb_par *par = bl_get_data(bdev);
int ret;
int brightness = bdev->props.brightness;
par->contrast = brightness;
ret = ssd1307fb_write_cmd(par->client, SSD1307FB_CONTRAST);
if (ret < 0)
return ret;
ret = ssd1307fb_write_cmd(par->client, par->contrast);
if (ret < 0)
return ret;
return 0;
}
static int ssd1307fb_get_brightness(struct backlight_device *bdev)
{
struct ssd1307fb_par *par = bl_get_data(bdev);
return par->contrast;
}
static int ssd1307fb_check_fb(struct backlight_device *bdev,
struct fb_info *info)
{
return (info->bl_dev == bdev);
}
static const struct backlight_ops ssd1307fb_bl_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = ssd1307fb_update_bl,
.get_brightness = ssd1307fb_get_brightness,
.check_fb = ssd1307fb_check_fb,
};
static struct ssd1307fb_deviceinfo ssd1307fb_ssd1305_deviceinfo = {
.default_vcomh = 0x34,
.default_dclk_div = 1,
.default_dclk_frq = 7,
};
static struct ssd1307fb_deviceinfo ssd1307fb_ssd1306_deviceinfo = {
.default_vcomh = 0x20,
.default_dclk_div = 1,
.default_dclk_frq = 8,
.need_chargepump = 1,
};
static struct ssd1307fb_deviceinfo ssd1307fb_ssd1307_deviceinfo = {
.default_vcomh = 0x20,
.default_dclk_div = 2,
.default_dclk_frq = 12,
.need_pwm = 1,
};
static struct ssd1307fb_deviceinfo ssd1307fb_ssd1309_deviceinfo = {
.default_vcomh = 0x34,
.default_dclk_div = 1,
.default_dclk_frq = 10,
};
static const struct of_device_id ssd1307fb_of_match[] = {
{
.compatible = "solomon,ssd1305fb-i2c",
.data = (void *)&ssd1307fb_ssd1305_deviceinfo,
},
{
.compatible = "solomon,ssd1306fb-i2c",
.data = (void *)&ssd1307fb_ssd1306_deviceinfo,
},
{
.compatible = "solomon,ssd1307fb-i2c",
.data = (void *)&ssd1307fb_ssd1307_deviceinfo,
},
{
.compatible = "solomon,ssd1309fb-i2c",
.data = (void *)&ssd1307fb_ssd1309_deviceinfo,
},
{},
};
MODULE_DEVICE_TABLE(of, ssd1307fb_of_match);
static int ssd1307fb_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct backlight_device *bl;
char bl_name[12];
struct fb_info *info;
struct fb_deferred_io *ssd1307fb_defio;
u32 vmem_size;
struct ssd1307fb_par *par;
void *vmem;
int ret;
info = framebuffer_alloc(sizeof(struct ssd1307fb_par), dev);
if (!info)
return -ENOMEM;
par = info->par;
par->info = info;
par->client = client;
par->device_info = device_get_match_data(dev);
par->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
if (IS_ERR(par->reset)) {
ret = dev_err_probe(dev, PTR_ERR(par->reset),
"failed to get reset gpio\n");
goto fb_alloc_error;
}
par->vbat_reg = devm_regulator_get_optional(dev, "vbat");
if (IS_ERR(par->vbat_reg)) {
ret = PTR_ERR(par->vbat_reg);
if (ret == -ENODEV) {
par->vbat_reg = NULL;
} else {
dev_err_probe(dev, ret, "failed to get VBAT regulator\n");
goto fb_alloc_error;
}
}
if (device_property_read_u32(dev, "solomon,width", &par->width))
par->width = 96;
if (device_property_read_u32(dev, "solomon,height", &par->height))
par->height = 16;
if (device_property_read_u32(dev, "solomon,page-offset", &par->page_offset))
par->page_offset = 1;
if (device_property_read_u32(dev, "solomon,col-offset", &par->col_offset))
par->col_offset = 0;
if (device_property_read_u32(dev, "solomon,com-offset", &par->com_offset))
par->com_offset = 0;
if (device_property_read_u32(dev, "solomon,prechargep1", &par->prechargep1))
par->prechargep1 = 2;
if (device_property_read_u32(dev, "solomon,prechargep2", &par->prechargep2))
par->prechargep2 = 2;
if (!device_property_read_u8_array(dev, "solomon,lookup-table",
par->lookup_table,
ARRAY_SIZE(par->lookup_table)))
par->lookup_table_set = 1;
par->seg_remap = !device_property_read_bool(dev, "solomon,segment-no-remap");
par->com_seq = device_property_read_bool(dev, "solomon,com-seq");
par->com_lrremap = device_property_read_bool(dev, "solomon,com-lrremap");
par->com_invdir = device_property_read_bool(dev, "solomon,com-invdir");
par->area_color_enable =
device_property_read_bool(dev, "solomon,area-color-enable");
par->low_power = device_property_read_bool(dev, "solomon,low-power");
par->contrast = 127;
par->vcomh = par->device_info->default_vcomh;
/* Setup display timing */
if (device_property_read_u32(dev, "solomon,dclk-div", &par->dclk_div))
par->dclk_div = par->device_info->default_dclk_div;
if (device_property_read_u32(dev, "solomon,dclk-frq", &par->dclk_frq))
par->dclk_frq = par->device_info->default_dclk_frq;
vmem_size = DIV_ROUND_UP(par->width, 8) * par->height;
vmem = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
get_order(vmem_size));
if (!vmem) {
dev_err(dev, "Couldn't allocate graphical memory.\n");
ret = -ENOMEM;
goto fb_alloc_error;
}
ssd1307fb_defio = devm_kzalloc(dev, sizeof(*ssd1307fb_defio),
GFP_KERNEL);
if (!ssd1307fb_defio) {
dev_err(dev, "Couldn't allocate deferred io.\n");
ret = -ENOMEM;
goto fb_alloc_error;
}
ssd1307fb_defio->delay = HZ / refreshrate;
ssd1307fb_defio->deferred_io = ssd1307fb_deferred_io;
info->fbops = &ssd1307fb_ops;
info->fix = ssd1307fb_fix;
info->fix.line_length = DIV_ROUND_UP(par->width, 8);
info->fbdefio = ssd1307fb_defio;
info->var = ssd1307fb_var;
info->var.xres = par->width;
info->var.xres_virtual = par->width;
info->var.yres = par->height;
info->var.yres_virtual = par->height;
info->screen_buffer = vmem;
info->fix.smem_start = __pa(vmem);
info->fix.smem_len = vmem_size;
fb_deferred_io_init(info);
i2c_set_clientdata(client, info);
if (par->reset) {
/* Reset the screen */
gpiod_set_value_cansleep(par->reset, 1);
udelay(4);
gpiod_set_value_cansleep(par->reset, 0);
udelay(4);
}
if (par->vbat_reg) {
ret = regulator_enable(par->vbat_reg);
if (ret) {
dev_err(dev, "failed to enable VBAT: %d\n", ret);
goto reset_oled_error;
}
}
ret = ssd1307fb_init(par);
if (ret)
goto regulator_enable_error;
ret = register_framebuffer(info);
if (ret) {
dev_err(dev, "Couldn't register the framebuffer\n");
goto panel_init_error;
}
snprintf(bl_name, sizeof(bl_name), "ssd1307fb%d", info->node);
bl = backlight_device_register(bl_name, dev, par, &ssd1307fb_bl_ops,
NULL);
if (IS_ERR(bl)) {
ret = PTR_ERR(bl);
dev_err(dev, "unable to register backlight device: %d\n", ret);
goto bl_init_error;
}
bl->props.brightness = par->contrast;
bl->props.max_brightness = MAX_CONTRAST;
info->bl_dev = bl;
dev_info(dev, "fb%d: %s framebuffer device registered, using %d bytes of video memory\n", info->node, info->fix.id, vmem_size);
return 0;
bl_init_error:
unregister_framebuffer(info);
panel_init_error:
pwm_disable(par->pwm);
pwm_put(par->pwm);
regulator_enable_error:
if (par->vbat_reg)
regulator_disable(par->vbat_reg);
reset_oled_error:
fb_deferred_io_cleanup(info);
fb_alloc_error:
framebuffer_release(info);
return ret;
}
static void ssd1307fb_remove(struct i2c_client *client)
{
struct fb_info *info = i2c_get_clientdata(client);
struct ssd1307fb_par *par = info->par;
ssd1307fb_write_cmd(par->client, SSD1307FB_DISPLAY_OFF);
backlight_device_unregister(info->bl_dev);
unregister_framebuffer(info);
pwm_disable(par->pwm);
pwm_put(par->pwm);
if (par->vbat_reg)
regulator_disable(par->vbat_reg);
fb_deferred_io_cleanup(info);
__free_pages(__va(info->fix.smem_start), get_order(info->fix.smem_len));
framebuffer_release(info);
}
static const struct i2c_device_id ssd1307fb_i2c_id[] = {
{ "ssd1305fb", 0 },
{ "ssd1306fb", 0 },
{ "ssd1307fb", 0 },
{ "ssd1309fb", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ssd1307fb_i2c_id);
static struct i2c_driver ssd1307fb_driver = {
.probe = ssd1307fb_probe,
.remove = ssd1307fb_remove,
.id_table = ssd1307fb_i2c_id,
.driver = {
.name = "ssd1307fb",
.of_match_table = ssd1307fb_of_match,
},
};
module_i2c_driver(ssd1307fb_driver);
MODULE_DESCRIPTION("FB driver for the Solomon SSD1307 OLED controller");
MODULE_AUTHOR("Maxime Ripard <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/ssd1307fb.c |
/*
* linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
*
* Modified to new api Jan 2001 by James Simmons ([email protected])
*
* Created 28 Dec 1997 by Geert Uytterhoeven
*
*
* I have started rewriting this driver as a example of the upcoming new API
* The primary goal is to remove the console code from fbdev and place it
* into fbcon.c. This reduces the code and makes writing a new fbdev driver
* easy since the author doesn't need to worry about console internals. It
* also allows the ability to run fbdev without a console/tty system on top
* of it.
*
* First the roles of struct fb_info and struct display have changed. Struct
* display will go away. The way the new framebuffer console code will
* work is that it will act to translate data about the tty/console in
* struct vc_data to data in a device independent way in struct fb_info. Then
* various functions in struct fb_ops will be called to store the device
* dependent state in the par field in struct fb_info and to change the
* hardware to that state. This allows a very clean separation of the fbdev
* layer from the console layer. It also allows one to use fbdev on its own
* which is a bounus for embedded devices. The reason this approach works is
* for each framebuffer device when used as a tty/console device is allocated
* a set of virtual terminals to it. Only one virtual terminal can be active
* per framebuffer device. We already have all the data we need in struct
* vc_data so why store a bunch of colormaps and other fbdev specific data
* per virtual terminal.
*
* As you can see doing this makes the con parameter pretty much useless
* for struct fb_ops functions, as it should be. Also having struct
* fb_var_screeninfo and other data in fb_info pretty much eliminates the
* need for get_fix and get_var. Once all drivers use the fix, var, and cmap
* fbcon can be written around these fields. This will also eliminate the
* need to regenerate struct fb_var_screeninfo, struct fb_fix_screeninfo
* struct fb_cmap every time get_var, get_fix, get_cmap functions are called
* as many drivers do now.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
/*
* This is just simple sample code.
*
* No warranty that it actually compiles.
* Even less warranty that it actually works :-)
*/
/*
* Driver data
*/
static char *mode_option;
/*
* If your driver supports multiple boards, you should make the
* below data types arrays, or allocate them dynamically (using kmalloc()).
*/
/*
* This structure defines the hardware state of the graphics card. Normally
* you place this in a header file in linux/include/video. This file usually
* also includes register information. That allows other driver subsystems
* and userland applications the ability to use the same header file to
* avoid duplicate work and easy porting of software.
*/
struct xxx_par;
/*
* Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
* if we don't use modedb. If we do use modedb see xxxfb_init how to use it
* to get a fb_var_screeninfo. Otherwise define a default var as well.
*/
static const struct fb_fix_screeninfo xxxfb_fix = {
.id = "FB's name",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 1,
.ypanstep = 1,
.ywrapstep = 1,
.accel = FB_ACCEL_NONE,
};
/*
* Modern graphical hardware not only supports pipelines but some
* also support multiple monitors where each display can have
* its own unique data. In this case each display could be
* represented by a separate framebuffer device thus a separate
* struct fb_info. Now the struct xxx_par represents the graphics
* hardware state thus only one exist per card. In this case the
* struct xxx_par for each graphics card would be shared between
* every struct fb_info that represents a framebuffer on that card.
* This allows when one display changes it video resolution (info->var)
* the other displays know instantly. Each display can always be
* aware of the entire hardware state that affects it because they share
* the same xxx_par struct. The other side of the coin is multiple
* graphics cards that pass data around until it is finally displayed
* on one monitor. Such examples are the voodoo 1 cards and high end
* NUMA graphics servers. For this case we have a bunch of pars, each
* one that represents a graphics state, that belong to one struct
* fb_info. Their you would want to have *par point to a array of device
* states and have each struct fb_ops function deal with all those
* states. I hope this covers every possible hardware design. If not
* feel free to send your ideas at [email protected]
*/
/*
* If your driver supports multiple boards or it supports multiple
* framebuffers, you should make these arrays, or allocate them
* dynamically using framebuffer_alloc() and free them with
* framebuffer_release().
*/
static struct fb_info info;
/*
* Each one represents the state of the hardware. Most hardware have
* just one hardware state. These here represent the default state(s).
*/
static struct xxx_par __initdata current_par;
/**
* xxxfb_open - Optional function. Called when the framebuffer is
* first accessed.
* @info: frame buffer structure that represents a single frame buffer
* @user: tell us if the userland (value=1) or the console is accessing
* the framebuffer.
*
* This function is the first function called in the framebuffer api.
* Usually you don't need to provide this function. The case where it
* is used is to change from a text mode hardware state to a graphics
* mode state.
*
* Returns negative errno on error, or zero on success.
*/
static int xxxfb_open(struct fb_info *info, int user)
{
return 0;
}
/**
* xxxfb_release - Optional function. Called when the framebuffer
* device is closed.
* @info: frame buffer structure that represents a single frame buffer
* @user: tell us if the userland (value=1) or the console is accessing
* the framebuffer.
*
* Thus function is called when we close /dev/fb or the framebuffer
* console system is released. Usually you don't need this function.
* The case where it is usually used is to go from a graphics state
* to a text mode state.
*
* Returns negative errno on error, or zero on success.
*/
static int xxxfb_release(struct fb_info *info, int user)
{
return 0;
}
/**
* xxxfb_check_var - Optional function. Validates a var passed in.
* @var: frame buffer variable screen structure
* @info: frame buffer structure that represents a single frame buffer
*
* Checks to see if the hardware supports the state requested by
* var passed in. This function does not alter the hardware state!!!
* This means the data stored in struct fb_info and struct xxx_par do
* not change. This includes the var inside of struct fb_info.
* Do NOT change these. This function can be called on its own if we
* intent to only test a mode and not actually set it. The stuff in
* modedb.c is a example of this. If the var passed in is slightly
* off by what the hardware can support then we alter the var PASSED in
* to what we can do.
*
* For values that are off, this function must round them _up_ to the
* next value that is supported by the hardware. If the value is
* greater than the highest value supported by the hardware, then this
* function must return -EINVAL.
*
* Exception to the above rule: Some drivers have a fixed mode, ie,
* the hardware is already set at boot up, and cannot be changed. In
* this case, it is more acceptable that this function just return
* a copy of the currently working var (info->var). Better is to not
* implement this function, as the upper layer will do the copying
* of the current var for you.
*
* Note: This is the only function where the contents of var can be
* freely adjusted after the driver has been registered. If you find
* that you have code outside of this function that alters the content
* of var, then you are doing something wrong. Note also that the
* contents of info->var must be left untouched at all times after
* driver registration.
*
* Returns negative errno on error, or zero on success.
*/
static int xxxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
/* ... */
return 0;
}
/**
* xxxfb_set_par - Optional function. Alters the hardware state.
* @info: frame buffer structure that represents a single frame buffer
*
* Using the fb_var_screeninfo in fb_info we set the resolution of the
* this particular framebuffer. This function alters the par AND the
* fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
* fb_info since we are using that data. This means we depend on the
* data in var inside fb_info to be supported by the hardware.
*
* This function is also used to recover/restore the hardware to a
* known working state.
*
* xxxfb_check_var is always called before xxxfb_set_par to ensure that
* the contents of var is always valid.
*
* Again if you can't change the resolution you don't need this function.
*
* However, even if your hardware does not support mode changing,
* a set_par might be needed to at least initialize the hardware to
* a known working state, especially if it came back from another
* process that also modifies the same hardware, such as X.
*
* If this is the case, a combination such as the following should work:
*
* static int xxxfb_check_var(struct fb_var_screeninfo *var,
* struct fb_info *info)
* {
* *var = info->var;
* return 0;
* }
*
* static int xxxfb_set_par(struct fb_info *info)
* {
* init your hardware here
* }
*
* Returns negative errno on error, or zero on success.
*/
static int xxxfb_set_par(struct fb_info *info)
{
struct xxx_par *par = info->par;
/* ... */
return 0;
}
/**
* xxxfb_setcolreg - Optional function. Sets a color register.
* @regno: Which register in the CLUT we are programming
* @red: The red value which can be up to 16 bits wide
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported, the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*
* Set a single color register. The values supplied have a 16 bit
* magnitude which needs to be scaled in this function for the hardware.
* Things to take into consideration are how many color registers, if
* any, are supported with the current color visual. With truecolor mode
* no color palettes are supported. Here a pseudo palette is created
* which we store the value in pseudo_palette in struct fb_info. For
* pseudocolor mode we have a limited color palette. To deal with this
* we can program what color is displayed for a particular pixel value.
* DirectColor is similar in that we can program each color field. If
* we have a static colormap we don't need to implement this function.
*
* Returns negative errno on error, or zero on success.
*/
static int xxxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
if (regno >= 256) /* no. of hw registers */
return -EINVAL;
/*
* Program hardware... do anything you want with transp
*/
/* grayscale works only partially under directcolor */
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
/* Directcolor:
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* {hardwarespecific} contains width of DAC
* pseudo_palette[X] is programmed to (X << red.offset) |
* (X << green.offset) |
* (X << blue.offset)
* RAMDAC[X] is programmed to (red, green, blue)
* color depth = SUM(var->{color}.length)
*
* Pseudocolor:
* var->{color}.offset is 0 unless the palette index takes less than
* bits_per_pixel bits and is stored in the upper
* bits of the pixel value
* var->{color}.length is set so that 1 << length is the number of
* available palette entries
* pseudo_palette is not used
* RAMDAC[X] is programmed to (red, green, blue)
* color depth = var->{color}.length
*
* Static pseudocolor:
* same as Pseudocolor, but the RAMDAC is not programmed (read-only)
*
* Mono01/Mono10:
* Has only 2 values, black on white or white on black (fg on bg),
* var->{color}.offset is 0
* white = (1 << var->{color}.length) - 1, black = 0
* pseudo_palette is not used
* RAMDAC does not exist
* color depth is always 2
*
* Truecolor:
* does not use RAMDAC (usually has 3 of them).
* var->{color}.offset contains start of bitfield
* var->{color}.length contains length of bitfield
* pseudo_palette is programmed to (red << red.offset) |
* (green << green.offset) |
* (blue << blue.offset) |
* (transp << transp.offset)
* RAMDAC does not exist
* color depth = SUM(var->{color}.length})
*
* The color depth is used by fbcon for choosing the logo and also
* for color palette transformation if color depth < 4
*
* As can be seen from the above, the field bits_per_pixel is _NOT_
* a criteria for describing the color visual.
*
* A common mistake is assuming that bits_per_pixel <= 8 is pseudocolor,
* and higher than that, true/directcolor. This is incorrect, one needs
* to look at the fix->visual.
*
* Another common mistake is using bits_per_pixel to calculate the color
* depth. The bits_per_pixel field does not directly translate to color
* depth. You have to compute for the color depth (using the color
* bitfields) and fix->visual as seen above.
*/
/*
* This is the point where the color is converted to something that
* is acceptable by the hardware.
*/
#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
transp = CNVT_TOHW(transp, info->var.transp.length);
#undef CNVT_TOHW
/*
* This is the point where the function feeds the color to the hardware
* palette after converting the colors to something acceptable by
* the hardware. Note, only FB_VISUAL_DIRECTCOLOR and
* FB_VISUAL_PSEUDOCOLOR visuals need to write to the hardware palette.
* If you have code that writes to the hardware CLUT, and it's not
* any of the above visuals, then you are doing something wrong.
*/
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR ||
info->fix.visual == FB_VISUAL_TRUECOLOR)
write_{red|green|blue|transp}_to_clut();
/* This is the point were you need to fill up the contents of
* info->pseudo_palette. This structure is used _only_ by fbcon, thus
* it only contains 16 entries to match the number of colors supported
* by the console. The pseudo_palette is used only if the visual is
* in directcolor or truecolor mode. With other visuals, the
* pseudo_palette is not used. (This might change in the future.)
*
* The contents of the pseudo_palette is in raw pixel format. Ie, each
* entry can be written directly to the framebuffer without any conversion.
* The pseudo_palette is (void *). However, if using the generic
* drawing functions (cfb_imageblit, cfb_fillrect), the pseudo_palette
* must be casted to (u32 *) _regardless_ of the bits per pixel. If the
* driver is using its own drawing functions, then it can use whatever
* size it wants.
*/
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
u32 v;
if (regno >= 16)
return -EINVAL;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
((u32*)(info->pseudo_palette))[regno] = v;
}
/* ... */
return 0;
}
/**
* xxxfb_pan_display - NOT a required function. Pans the display.
* @var: frame buffer variable screen structure
* @info: frame buffer structure that represents a single frame buffer
*
* Pan (or wrap, depending on the `vmode' field) the display using the
* `xoffset' and `yoffset' fields of the `var' structure.
* If the values don't fit, return -EINVAL.
*
* Returns negative errno on error, or zero on success.
*/
static int xxxfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
/*
* If your hardware does not support panning, _do_ _not_ implement this
* function. Creating a dummy function will just confuse user apps.
*/
/*
* Note that even if this function is fully functional, a setting of
* 0 in both xpanstep and ypanstep means that this function will never
* get called.
*/
/* ... */
return 0;
}
/**
* xxxfb_blank - NOT a required function. Blanks the display.
* @blank_mode: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*
* Blank the screen if blank_mode != FB_BLANK_UNBLANK, else unblank.
* Return 0 if blanking succeeded, != 0 if un-/blanking failed due to
* e.g. a video mode which doesn't support it.
*
* Implements VESA suspend and powerdown modes on hardware that supports
* disabling hsync/vsync:
*
* FB_BLANK_NORMAL = display is blanked, syncs are on.
* FB_BLANK_HSYNC_SUSPEND = hsync off
* FB_BLANK_VSYNC_SUSPEND = vsync off
* FB_BLANK_POWERDOWN = hsync and vsync off
*
* If implementing this function, at least support FB_BLANK_UNBLANK.
* Return !0 for any modes that are unimplemented.
*
*/
static int xxxfb_blank(int blank_mode, struct fb_info *info)
{
/* ... */
return 0;
}
/* ------------ Accelerated Functions --------------------- */
/*
* We provide our own functions if we have hardware acceleration
* or non packed pixel format layouts. If we have no hardware
* acceleration, we can use a generic unaccelerated function. If using
* a pack pixel format just use the functions in cfb_*.c. Each file
* has one of the three different accel functions we support.
*/
/**
* xxxfb_fillrect - REQUIRED function. Can use generic routines if
* non acclerated hardware and packed pixel based.
* Draws a rectangle on the screen.
*
* @info: frame buffer structure that represents a single frame buffer
* @region: The structure representing the rectangular region we
* wish to draw to.
*
* This drawing operation places/removes a retangle on the screen
* depending on the rastering operation with the value of color which
* is in the current color depth format.
*/
void xxxfb_fillrect(struct fb_info *p, const struct fb_fillrect *region)
{
/* Meaning of struct fb_fillrect
*
* @dx: The x and y corrdinates of the upper left hand corner of the
* @dy: area we want to draw to.
* @width: How wide the rectangle is we want to draw.
* @height: How tall the rectangle is we want to draw.
* @color: The color to fill in the rectangle with.
* @rop: The raster operation. We can draw the rectangle with a COPY
* of XOR which provides erasing effect.
*/
}
/**
* xxxfb_copyarea - REQUIRED function. Can use generic routines if
* non acclerated hardware and packed pixel based.
* Copies one area of the screen to another area.
*
* @info: frame buffer structure that represents a single frame buffer
* @area: Structure providing the data to copy the framebuffer contents
* from one region to another.
*
* This drawing operation copies a rectangular area from one area of the
* screen to another area.
*/
void xxxfb_copyarea(struct fb_info *p, const struct fb_copyarea *area)
{
/*
* @dx: The x and y coordinates of the upper left hand corner of the
* @dy: destination area on the screen.
* @width: How wide the rectangle is we want to copy.
* @height: How tall the rectangle is we want to copy.
* @sx: The x and y coordinates of the upper left hand corner of the
* @sy: source area on the screen.
*/
}
/**
* xxxfb_imageblit - REQUIRED function. Can use generic routines if
* non acclerated hardware and packed pixel based.
* Copies a image from system memory to the screen.
*
* @info: frame buffer structure that represents a single frame buffer
* @image: structure defining the image.
*
* This drawing operation draws a image on the screen. It can be a
* mono image (needed for font handling) or a color image (needed for
* tux).
*/
void xxxfb_imageblit(struct fb_info *p, const struct fb_image *image)
{
/*
* @dx: The x and y coordinates of the upper left hand corner of the
* @dy: destination area to place the image on the screen.
* @width: How wide the image is we want to copy.
* @height: How tall the image is we want to copy.
* @fg_color: For mono bitmap images this is color data for
* @bg_color: the foreground and background of the image to
* write directly to the frmaebuffer.
* @depth: How many bits represent a single pixel for this image.
* @data: The actual data used to construct the image on the display.
* @cmap: The colormap used for color images.
*/
/*
* The generic function, cfb_imageblit, expects that the bitmap scanlines are
* padded to the next byte. Most hardware accelerators may require padding to
* the next u16 or the next u32. If that is the case, the driver can specify
* this by setting info->pixmap.scan_align = 2 or 4. See a more
* comprehensive description of the pixmap below.
*/
}
/**
* xxxfb_cursor - OPTIONAL. If your hardware lacks support
* for a cursor, leave this field NULL.
*
* @info: frame buffer structure that represents a single frame buffer
* @cursor: structure defining the cursor to draw.
*
* This operation is used to set or alter the properities of the
* cursor.
*
* Returns negative errno on error, or zero on success.
*/
int xxxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
/*
* @set: Which fields we are altering in struct fb_cursor
* @enable: Disable or enable the cursor
* @rop: The bit operation we want to do.
* @mask: This is the cursor mask bitmap.
* @dest: A image of the area we are going to display the cursor.
* Used internally by the driver.
* @hot: The hot spot.
* @image: The actual data for the cursor image.
*
* NOTES ON FLAGS (cursor->set):
*
* FB_CUR_SETIMAGE - the cursor image has changed (cursor->image.data)
* FB_CUR_SETPOS - the cursor position has changed (cursor->image.dx|dy)
* FB_CUR_SETHOT - the cursor hot spot has changed (cursor->hot.dx|dy)
* FB_CUR_SETCMAP - the cursor colors has changed (cursor->fg_color|bg_color)
* FB_CUR_SETSHAPE - the cursor bitmask has changed (cursor->mask)
* FB_CUR_SETSIZE - the cursor size has changed (cursor->width|height)
* FB_CUR_SETALL - everything has changed
*
* NOTES ON ROPs (cursor->rop, Raster Operation)
*
* ROP_XOR - cursor->image.data XOR cursor->mask
* ROP_COPY - curosr->image.data AND cursor->mask
*
* OTHER NOTES:
*
* - fbcon only supports a 2-color cursor (cursor->image.depth = 1)
* - The fb_cursor structure, @cursor, _will_ always contain valid
* fields, whether any particular bitfields in cursor->set is set
* or not.
*/
}
/**
* xxxfb_sync - NOT a required function. Normally the accel engine
* for a graphics card take a specific amount of time.
* Often we have to wait for the accelerator to finish
* its operation before we can write to the framebuffer
* so we can have consistent display output.
*
* @info: frame buffer structure that represents a single frame buffer
*
* If the driver has implemented its own hardware-based drawing function,
* implementing this function is highly recommended.
*/
int xxxfb_sync(struct fb_info *info)
{
return 0;
}
/*
* Frame buffer operations
*/
static const struct fb_ops xxxfb_ops = {
.owner = THIS_MODULE,
.fb_open = xxxfb_open,
.fb_read = xxxfb_read,
.fb_write = xxxfb_write,
.fb_release = xxxfb_release,
.fb_check_var = xxxfb_check_var,
.fb_set_par = xxxfb_set_par,
.fb_setcolreg = xxxfb_setcolreg,
.fb_blank = xxxfb_blank,
.fb_pan_display = xxxfb_pan_display,
.fb_fillrect = xxxfb_fillrect, /* Needed !!! */
.fb_copyarea = xxxfb_copyarea, /* Needed !!! */
.fb_imageblit = xxxfb_imageblit, /* Needed !!! */
.fb_cursor = xxxfb_cursor, /* Optional !!! */
.fb_sync = xxxfb_sync,
.fb_ioctl = xxxfb_ioctl,
.fb_mmap = xxxfb_mmap,
};
/* ------------------------------------------------------------------------- */
/*
* Initialization
*/
/* static int __init xxfb_probe (struct platform_device *pdev) -- for platform devs */
static int xxxfb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
{
struct fb_info *info;
struct xxx_par *par;
struct device *device = &dev->dev; /* or &pdev->dev */
int cmap_len, retval;
/*
* Remove firmware-based drivers that create resource conflicts.
*/
retval = aperture_remove_conflicting_pci_devices(pdev, "xxxfb");
if (retval)
return retval;
/*
* Dynamically allocate info and par
*/
info = framebuffer_alloc(sizeof(struct xxx_par), device);
if (!info) {
/* goto error path */
}
par = info->par;
/*
* Here we set the screen_base to the virtual memory address
* for the framebuffer. Usually we obtain the resource address
* from the bus layer and then translate it to virtual memory
* space via ioremap. Consult ioport.h.
*/
info->screen_base = framebuffer_virtual_memory;
info->fbops = &xxxfb_ops;
info->fix = xxxfb_fix;
info->pseudo_palette = pseudo_palette; /* The pseudopalette is an
* 16-member array
*/
/*
* Set up flags to indicate what sort of acceleration your
* driver can provide (pan/wrap/copyarea/etc.) and whether it
* is a module -- see FBINFO_* in include/linux/fb.h
*
* If your hardware can support any of the hardware accelerated functions
* fbcon performance will improve if info->flags is set properly.
*
* FBINFO_HWACCEL_COPYAREA - hardware moves
* FBINFO_HWACCEL_FILLRECT - hardware fills
* FBINFO_HWACCEL_IMAGEBLIT - hardware mono->color expansion
* FBINFO_HWACCEL_YPAN - hardware can pan display in y-axis
* FBINFO_HWACCEL_YWRAP - hardware can wrap display in y-axis
* FBINFO_HWACCEL_DISABLED - supports hardware accels, but disabled
* FBINFO_READS_FAST - if set, prefer moves over mono->color expansion
* FBINFO_MISC_TILEBLITTING - hardware can do tile blits
*
* NOTE: These are for fbcon use only.
*/
info->flags = 0;
/********************* This stage is optional ******************************/
/*
* The struct pixmap is a scratch pad for the drawing functions. This
* is where the monochrome bitmap is constructed by the higher layers
* and then passed to the accelerator. For drivers that uses
* cfb_imageblit, you can skip this part. For those that have a more
* rigorous requirement, this stage is needed
*/
/* PIXMAP_SIZE should be small enough to optimize drawing, but not
* large enough that memory is wasted. A safe size is
* (max_xres * max_font_height/8). max_xres is driver dependent,
* max_font_height is 32.
*/
info->pixmap.addr = kmalloc(PIXMAP_SIZE, GFP_KERNEL);
if (!info->pixmap.addr) {
/* goto error */
}
info->pixmap.size = PIXMAP_SIZE;
/*
* FB_PIXMAP_SYSTEM - memory is in system ram
* FB_PIXMAP_IO - memory is iomapped
* FB_PIXMAP_SYNC - if set, will call fb_sync() per access to pixmap,
* usually if FB_PIXMAP_IO is set.
*
* Currently, FB_PIXMAP_IO is unimplemented.
*/
info->pixmap.flags = FB_PIXMAP_SYSTEM;
/*
* scan_align is the number of padding for each scanline. It is in bytes.
* Thus for accelerators that need padding to the next u32, put 4 here.
*/
info->pixmap.scan_align = 4;
/*
* buf_align is the amount to be padded for the buffer. For example,
* the i810fb needs a scan_align of 2 but expects it to be fed with
* dwords, so a buf_align = 4 is required.
*/
info->pixmap.buf_align = 4;
/* access_align is how many bits can be accessed from the framebuffer
* ie. some epson cards allow 16-bit access only. Most drivers will
* be safe with u32 here.
*
* NOTE: This field is currently unused.
*/
info->pixmap.access_align = 32;
/***************************** End optional stage ***************************/
/*
* This should give a reasonable default video mode. The following is
* done when we can set a video mode.
*/
if (!mode_option)
mode_option = "640x480@60";
retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
if (!retval || retval == 4)
return -EINVAL;
/* This has to be done! */
if (fb_alloc_cmap(&info->cmap, cmap_len, 0))
return -ENOMEM;
/*
* The following is done in the case of having hardware with a static
* mode. If we are setting the mode ourselves we don't call this.
*/
info->var = xxxfb_var;
/*
* For drivers that can...
*/
xxxfb_check_var(&info->var, info);
/*
* Does a call to fb_set_par() before register_framebuffer needed? This
* will depend on you and the hardware. If you are sure that your driver
* is the only device in the system, a call to fb_set_par() is safe.
*
* Hardware in x86 systems has a VGA core. Calling set_par() at this
* point will corrupt the VGA console, so it might be safer to skip a
* call to set_par here and just allow fbcon to do it for you.
*/
/* xxxfb_set_par(info); */
if (register_framebuffer(info) < 0) {
fb_dealloc_cmap(&info->cmap);
return -EINVAL;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
pci_set_drvdata(dev, info); /* or platform_set_drvdata(pdev, info) */
return 0;
}
/*
* Cleanup
*/
/* static void xxxfb_remove(struct platform_device *pdev) */
static void xxxfb_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
/* or platform_get_drvdata(pdev); */
if (info) {
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
/* ... */
framebuffer_release(info);
}
}
#ifdef CONFIG_PCI
#ifdef CONFIG_PM
/**
* xxxfb_suspend - Optional but recommended function. Suspend the device.
* @dev: PCI device
* @msg: the suspend event code.
*
* See Documentation/driver-api/pm/devices.rst for more information
*/
static int xxxfb_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct xxxfb_par *par = info->par;
/* suspend here */
return 0;
}
/**
* xxxfb_resume - Optional but recommended function. Resume the device.
* @dev: PCI device
*
* See Documentation/driver-api/pm/devices.rst for more information
*/
static int xxxfb_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct xxxfb_par *par = info->par;
/* resume here */
return 0;
}
#else
#define xxxfb_suspend NULL
#define xxxfb_resume NULL
#endif /* CONFIG_PM */
static const struct pci_device_id xxxfb_id_table[] = {
{ PCI_VENDOR_ID_XXX, PCI_DEVICE_ID_XXX,
PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
PCI_CLASS_MASK, 0 },
{ 0, }
};
static SIMPLE_DEV_PM_OPS(xxxfb_pm_ops, xxxfb_suspend, xxxfb_resume);
/* For PCI drivers */
static struct pci_driver xxxfb_driver = {
.name = "xxxfb",
.id_table = xxxfb_id_table,
.probe = xxxfb_probe,
.remove = xxxfb_remove,
.driver.pm = xxxfb_pm_ops, /* optional but recommended */
};
MODULE_DEVICE_TABLE(pci, xxxfb_id_table);
static int __init xxxfb_init(void)
{
/*
* For kernel boot options (in 'video=xxxfb:<options>' format)
*/
#ifndef MODULE
char *option = NULL;
if (fb_get_options("xxxfb", &option))
return -ENODEV;
xxxfb_setup(option);
#endif
return pci_register_driver(&xxxfb_driver);
}
static void __exit xxxfb_exit(void)
{
pci_unregister_driver(&xxxfb_driver);
}
#else /* non PCI, platform drivers */
#include <linux/platform_device.h>
/* for platform devices */
#ifdef CONFIG_PM
/**
* xxxfb_suspend - Optional but recommended function. Suspend the device.
* @dev: platform device
* @msg: the suspend event code.
*
* See Documentation/driver-api/pm/devices.rst for more information
*/
static int xxxfb_suspend(struct platform_device *dev, pm_message_t msg)
{
struct fb_info *info = platform_get_drvdata(dev);
struct xxxfb_par *par = info->par;
/* suspend here */
return 0;
}
/**
* xxxfb_resume - Optional but recommended function. Resume the device.
* @dev: platform device
*
* See Documentation/driver-api/pm/devices.rst for more information
*/
static int xxxfb_resume(struct platform_dev *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
struct xxxfb_par *par = info->par;
/* resume here */
return 0;
}
#else
#define xxxfb_suspend NULL
#define xxxfb_resume NULL
#endif /* CONFIG_PM */
static struct platform_device_driver xxxfb_driver = {
.probe = xxxfb_probe,
.remove = xxxfb_remove,
.suspend = xxxfb_suspend, /* optional but recommended */
.resume = xxxfb_resume, /* optional but recommended */
.driver = {
.name = "xxxfb",
},
};
static struct platform_device *xxxfb_device;
#ifndef MODULE
/*
* Setup
*/
/*
* Only necessary if your driver takes special options,
* otherwise we fall back on the generic fb_setup().
*/
static int __init xxxfb_setup(char *options)
{
/* Parse user specified options (`video=xxxfb:') */
}
#endif /* MODULE */
static int __init xxxfb_init(void)
{
int ret;
/*
* For kernel boot options (in 'video=xxxfb:<options>' format)
*/
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("xxxfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("xxxfb", &option))
return -ENODEV;
xxxfb_setup(option);
#endif
ret = platform_driver_register(&xxxfb_driver);
if (!ret) {
xxxfb_device = platform_device_register_simple("xxxfb", 0,
NULL, 0);
if (IS_ERR(xxxfb_device)) {
platform_driver_unregister(&xxxfb_driver);
ret = PTR_ERR(xxxfb_device);
}
}
return ret;
}
static void __exit xxxfb_exit(void)
{
platform_device_unregister(xxxfb_device);
platform_driver_unregister(&xxxfb_driver);
}
#endif /* CONFIG_PCI */
/* ------------------------------------------------------------------------- */
/*
* Modularization
*/
module_init(xxxfb_init);
module_exit(xxxfb_exit);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/skeletonfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/* cg6.c: CGSIX (GX, GXplus, TGX) frame buffer driver
*
* Copyright (C) 2003, 2006 David S. Miller ([email protected])
* Copyright (C) 1996,1998 Jakub Jelinek ([email protected])
* Copyright (C) 1996 Miguel de Icaza ([email protected])
* Copyright (C) 1996 Eddie C. Dost ([email protected])
*
* Driver layout based loosely on tgafb.c, see that file for credits.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/fbio.h>
#include "sbuslib.h"
/*
* Local functions.
*/
static int cg6_setcolreg(unsigned, unsigned, unsigned, unsigned,
unsigned, struct fb_info *);
static int cg6_blank(int, struct fb_info *);
static void cg6_imageblit(struct fb_info *, const struct fb_image *);
static void cg6_fillrect(struct fb_info *, const struct fb_fillrect *);
static void cg6_copyarea(struct fb_info *info, const struct fb_copyarea *area);
static int cg6_sync(struct fb_info *);
static int cg6_mmap(struct fb_info *, struct vm_area_struct *);
static int cg6_ioctl(struct fb_info *, unsigned int, unsigned long);
static int cg6_pan_display(struct fb_var_screeninfo *, struct fb_info *);
/*
* Frame buffer operations
*/
static const struct fb_ops cg6_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = cg6_setcolreg,
.fb_blank = cg6_blank,
.fb_pan_display = cg6_pan_display,
.fb_fillrect = cg6_fillrect,
.fb_copyarea = cg6_copyarea,
.fb_imageblit = cg6_imageblit,
.fb_sync = cg6_sync,
.fb_mmap = cg6_mmap,
.fb_ioctl = cg6_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = sbusfb_compat_ioctl,
#endif
};
/* Offset of interesting structures in the OBIO space */
/*
* Brooktree is the video dac and is funny to program on the cg6.
* (it's even funnier on the cg3)
* The FBC could be the frame buffer control
* The FHC could is the frame buffer hardware control.
*/
#define CG6_ROM_OFFSET 0x0UL
#define CG6_BROOKTREE_OFFSET 0x200000UL
#define CG6_DHC_OFFSET 0x240000UL
#define CG6_ALT_OFFSET 0x280000UL
#define CG6_FHC_OFFSET 0x300000UL
#define CG6_THC_OFFSET 0x301000UL
#define CG6_FBC_OFFSET 0x700000UL
#define CG6_TEC_OFFSET 0x701000UL
#define CG6_RAM_OFFSET 0x800000UL
/* FHC definitions */
#define CG6_FHC_FBID_SHIFT 24
#define CG6_FHC_FBID_MASK 255
#define CG6_FHC_REV_SHIFT 20
#define CG6_FHC_REV_MASK 15
#define CG6_FHC_FROP_DISABLE (1 << 19)
#define CG6_FHC_ROW_DISABLE (1 << 18)
#define CG6_FHC_SRC_DISABLE (1 << 17)
#define CG6_FHC_DST_DISABLE (1 << 16)
#define CG6_FHC_RESET (1 << 15)
#define CG6_FHC_LITTLE_ENDIAN (1 << 13)
#define CG6_FHC_RES_MASK (3 << 11)
#define CG6_FHC_1024 (0 << 11)
#define CG6_FHC_1152 (1 << 11)
#define CG6_FHC_1280 (2 << 11)
#define CG6_FHC_1600 (3 << 11)
#define CG6_FHC_CPU_MASK (3 << 9)
#define CG6_FHC_CPU_SPARC (0 << 9)
#define CG6_FHC_CPU_68020 (1 << 9)
#define CG6_FHC_CPU_386 (2 << 9)
#define CG6_FHC_TEST (1 << 8)
#define CG6_FHC_TEST_X_SHIFT 4
#define CG6_FHC_TEST_X_MASK 15
#define CG6_FHC_TEST_Y_SHIFT 0
#define CG6_FHC_TEST_Y_MASK 15
/* FBC mode definitions */
#define CG6_FBC_BLIT_IGNORE 0x00000000
#define CG6_FBC_BLIT_NOSRC 0x00100000
#define CG6_FBC_BLIT_SRC 0x00200000
#define CG6_FBC_BLIT_ILLEGAL 0x00300000
#define CG6_FBC_BLIT_MASK 0x00300000
#define CG6_FBC_VBLANK 0x00080000
#define CG6_FBC_MODE_IGNORE 0x00000000
#define CG6_FBC_MODE_COLOR8 0x00020000
#define CG6_FBC_MODE_COLOR1 0x00040000
#define CG6_FBC_MODE_HRMONO 0x00060000
#define CG6_FBC_MODE_MASK 0x00060000
#define CG6_FBC_DRAW_IGNORE 0x00000000
#define CG6_FBC_DRAW_RENDER 0x00008000
#define CG6_FBC_DRAW_PICK 0x00010000
#define CG6_FBC_DRAW_ILLEGAL 0x00018000
#define CG6_FBC_DRAW_MASK 0x00018000
#define CG6_FBC_BWRITE0_IGNORE 0x00000000
#define CG6_FBC_BWRITE0_ENABLE 0x00002000
#define CG6_FBC_BWRITE0_DISABLE 0x00004000
#define CG6_FBC_BWRITE0_ILLEGAL 0x00006000
#define CG6_FBC_BWRITE0_MASK 0x00006000
#define CG6_FBC_BWRITE1_IGNORE 0x00000000
#define CG6_FBC_BWRITE1_ENABLE 0x00000800
#define CG6_FBC_BWRITE1_DISABLE 0x00001000
#define CG6_FBC_BWRITE1_ILLEGAL 0x00001800
#define CG6_FBC_BWRITE1_MASK 0x00001800
#define CG6_FBC_BREAD_IGNORE 0x00000000
#define CG6_FBC_BREAD_0 0x00000200
#define CG6_FBC_BREAD_1 0x00000400
#define CG6_FBC_BREAD_ILLEGAL 0x00000600
#define CG6_FBC_BREAD_MASK 0x00000600
#define CG6_FBC_BDISP_IGNORE 0x00000000
#define CG6_FBC_BDISP_0 0x00000080
#define CG6_FBC_BDISP_1 0x00000100
#define CG6_FBC_BDISP_ILLEGAL 0x00000180
#define CG6_FBC_BDISP_MASK 0x00000180
#define CG6_FBC_INDEX_MOD 0x00000040
#define CG6_FBC_INDEX_MASK 0x00000030
/* THC definitions */
#define CG6_THC_MISC_REV_SHIFT 16
#define CG6_THC_MISC_REV_MASK 15
#define CG6_THC_MISC_RESET (1 << 12)
#define CG6_THC_MISC_VIDEO (1 << 10)
#define CG6_THC_MISC_SYNC (1 << 9)
#define CG6_THC_MISC_VSYNC (1 << 8)
#define CG6_THC_MISC_SYNC_ENAB (1 << 7)
#define CG6_THC_MISC_CURS_RES (1 << 6)
#define CG6_THC_MISC_INT_ENAB (1 << 5)
#define CG6_THC_MISC_INT (1 << 4)
#define CG6_THC_MISC_INIT 0x9f
#define CG6_THC_CURSOFF ((65536-32) | ((65536-32) << 16))
/* The contents are unknown */
struct cg6_tec {
int tec_matrix;
int tec_clip;
int tec_vdc;
};
struct cg6_thc {
u32 thc_pad0[512];
u32 thc_hs; /* hsync timing */
u32 thc_hsdvs;
u32 thc_hd;
u32 thc_vs; /* vsync timing */
u32 thc_vd;
u32 thc_refresh;
u32 thc_misc;
u32 thc_pad1[56];
u32 thc_cursxy; /* cursor x,y position (16 bits each) */
u32 thc_cursmask[32]; /* cursor mask bits */
u32 thc_cursbits[32]; /* what to show where mask enabled */
};
struct cg6_fbc {
u32 xxx0[1];
u32 mode;
u32 clip;
u32 xxx1[1];
u32 s;
u32 draw;
u32 blit;
u32 font;
u32 xxx2[24];
u32 x0, y0, z0, color0;
u32 x1, y1, z1, color1;
u32 x2, y2, z2, color2;
u32 x3, y3, z3, color3;
u32 offx, offy;
u32 xxx3[2];
u32 incx, incy;
u32 xxx4[2];
u32 clipminx, clipminy;
u32 xxx5[2];
u32 clipmaxx, clipmaxy;
u32 xxx6[2];
u32 fg;
u32 bg;
u32 alu;
u32 pm;
u32 pixelm;
u32 xxx7[2];
u32 patalign;
u32 pattern[8];
u32 xxx8[432];
u32 apointx, apointy, apointz;
u32 xxx9[1];
u32 rpointx, rpointy, rpointz;
u32 xxx10[5];
u32 pointr, pointg, pointb, pointa;
u32 alinex, aliney, alinez;
u32 xxx11[1];
u32 rlinex, rliney, rlinez;
u32 xxx12[5];
u32 liner, lineg, lineb, linea;
u32 atrix, atriy, atriz;
u32 xxx13[1];
u32 rtrix, rtriy, rtriz;
u32 xxx14[5];
u32 trir, trig, trib, tria;
u32 aquadx, aquady, aquadz;
u32 xxx15[1];
u32 rquadx, rquady, rquadz;
u32 xxx16[5];
u32 quadr, quadg, quadb, quada;
u32 arectx, arecty, arectz;
u32 xxx17[1];
u32 rrectx, rrecty, rrectz;
u32 xxx18[5];
u32 rectr, rectg, rectb, recta;
};
struct bt_regs {
u32 addr;
u32 color_map;
u32 control;
u32 cursor;
};
struct cg6_par {
spinlock_t lock;
struct bt_regs __iomem *bt;
struct cg6_fbc __iomem *fbc;
struct cg6_thc __iomem *thc;
struct cg6_tec __iomem *tec;
u32 __iomem *fhc;
u32 flags;
#define CG6_FLAG_BLANKED 0x00000001
unsigned long which_io;
};
static int cg6_sync(struct fb_info *info)
{
struct cg6_par *par = (struct cg6_par *)info->par;
struct cg6_fbc __iomem *fbc = par->fbc;
int limit = 10000;
do {
if (!(sbus_readl(&fbc->s) & 0x10000000))
break;
udelay(10);
} while (--limit > 0);
return 0;
}
static void cg6_switch_from_graph(struct cg6_par *par)
{
struct cg6_thc __iomem *thc = par->thc;
unsigned long flags;
spin_lock_irqsave(&par->lock, flags);
/* Hide the cursor. */
sbus_writel(CG6_THC_CURSOFF, &thc->thc_cursxy);
spin_unlock_irqrestore(&par->lock, flags);
}
static int cg6_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct cg6_par *par = (struct cg6_par *)info->par;
/* We just use this to catch switches out of
* graphics mode.
*/
cg6_switch_from_graph(par);
if (var->xoffset || var->yoffset || var->vmode)
return -EINVAL;
return 0;
}
/**
* cg6_fillrect - Draws a rectangle on the screen.
*
* @info: frame buffer structure that represents a single frame buffer
* @rect: structure defining the rectagle and operation.
*/
static void cg6_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct cg6_par *par = (struct cg6_par *)info->par;
struct cg6_fbc __iomem *fbc = par->fbc;
unsigned long flags;
s32 val;
/* CG6 doesn't handle ROP_XOR */
spin_lock_irqsave(&par->lock, flags);
cg6_sync(info);
sbus_writel(rect->color, &fbc->fg);
sbus_writel(~(u32)0, &fbc->pixelm);
sbus_writel(0xea80ff00, &fbc->alu);
sbus_writel(0, &fbc->s);
sbus_writel(0, &fbc->clip);
sbus_writel(~(u32)0, &fbc->pm);
sbus_writel(rect->dy, &fbc->arecty);
sbus_writel(rect->dx, &fbc->arectx);
sbus_writel(rect->dy + rect->height, &fbc->arecty);
sbus_writel(rect->dx + rect->width, &fbc->arectx);
do {
val = sbus_readl(&fbc->draw);
} while (val < 0 && (val & 0x20000000));
spin_unlock_irqrestore(&par->lock, flags);
}
/**
* cg6_copyarea - Copies one area of the screen to another area.
*
* @info: frame buffer structure that represents a single frame buffer
* @area: Structure providing the data to copy the framebuffer contents
* from one region to another.
*
* This drawing operation copies a rectangular area from one area of the
* screen to another area.
*/
static void cg6_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct cg6_par *par = (struct cg6_par *)info->par;
struct cg6_fbc __iomem *fbc = par->fbc;
unsigned long flags;
int i;
spin_lock_irqsave(&par->lock, flags);
cg6_sync(info);
sbus_writel(0xff, &fbc->fg);
sbus_writel(0x00, &fbc->bg);
sbus_writel(~0, &fbc->pixelm);
sbus_writel(0xe880cccc, &fbc->alu);
sbus_writel(0, &fbc->s);
sbus_writel(0, &fbc->clip);
sbus_writel(area->sy, &fbc->y0);
sbus_writel(area->sx, &fbc->x0);
sbus_writel(area->sy + area->height - 1, &fbc->y1);
sbus_writel(area->sx + area->width - 1, &fbc->x1);
sbus_writel(area->dy, &fbc->y2);
sbus_writel(area->dx, &fbc->x2);
sbus_writel(area->dy + area->height - 1, &fbc->y3);
sbus_writel(area->dx + area->width - 1, &fbc->x3);
do {
i = sbus_readl(&fbc->blit);
} while (i < 0 && (i & 0x20000000));
spin_unlock_irqrestore(&par->lock, flags);
}
/**
* cg6_imageblit - Copies a image from system memory to the screen.
*
* @info: frame buffer structure that represents a single frame buffer
* @image: structure defining the image.
*/
static void cg6_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct cg6_par *par = (struct cg6_par *)info->par;
struct cg6_fbc __iomem *fbc = par->fbc;
const u8 *data = image->data;
unsigned long flags;
u32 x, y;
int i, width;
if (image->depth > 1) {
cfb_imageblit(info, image);
return;
}
spin_lock_irqsave(&par->lock, flags);
cg6_sync(info);
sbus_writel(image->fg_color, &fbc->fg);
sbus_writel(image->bg_color, &fbc->bg);
sbus_writel(0x140000, &fbc->mode);
sbus_writel(0xe880fc30, &fbc->alu);
sbus_writel(~(u32)0, &fbc->pixelm);
sbus_writel(0, &fbc->s);
sbus_writel(0, &fbc->clip);
sbus_writel(0xff, &fbc->pm);
sbus_writel(32, &fbc->incx);
sbus_writel(0, &fbc->incy);
x = image->dx;
y = image->dy;
for (i = 0; i < image->height; i++) {
width = image->width;
while (width >= 32) {
u32 val;
sbus_writel(y, &fbc->y0);
sbus_writel(x, &fbc->x0);
sbus_writel(x + 32 - 1, &fbc->x1);
val = ((u32)data[0] << 24) |
((u32)data[1] << 16) |
((u32)data[2] << 8) |
((u32)data[3] << 0);
sbus_writel(val, &fbc->font);
data += 4;
x += 32;
width -= 32;
}
if (width) {
u32 val;
sbus_writel(y, &fbc->y0);
sbus_writel(x, &fbc->x0);
sbus_writel(x + width - 1, &fbc->x1);
if (width <= 8) {
val = (u32) data[0] << 24;
data += 1;
} else if (width <= 16) {
val = ((u32) data[0] << 24) |
((u32) data[1] << 16);
data += 2;
} else {
val = ((u32) data[0] << 24) |
((u32) data[1] << 16) |
((u32) data[2] << 8);
data += 3;
}
sbus_writel(val, &fbc->font);
}
y += 1;
x = image->dx;
}
spin_unlock_irqrestore(&par->lock, flags);
}
/**
* cg6_setcolreg - Sets a color register.
*
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*/
static int cg6_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct cg6_par *par = (struct cg6_par *)info->par;
struct bt_regs __iomem *bt = par->bt;
unsigned long flags;
if (regno >= 256)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
spin_lock_irqsave(&par->lock, flags);
sbus_writel((u32)regno << 24, &bt->addr);
sbus_writel((u32)red << 24, &bt->color_map);
sbus_writel((u32)green << 24, &bt->color_map);
sbus_writel((u32)blue << 24, &bt->color_map);
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
/**
* cg6_blank - Blanks the display.
*
* @blank: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int cg6_blank(int blank, struct fb_info *info)
{
struct cg6_par *par = (struct cg6_par *)info->par;
struct cg6_thc __iomem *thc = par->thc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&par->lock, flags);
val = sbus_readl(&thc->thc_misc);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
val |= CG6_THC_MISC_VIDEO;
par->flags &= ~CG6_FLAG_BLANKED;
break;
case FB_BLANK_NORMAL: /* Normal blanking */
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
case FB_BLANK_POWERDOWN: /* Poweroff */
val &= ~CG6_THC_MISC_VIDEO;
par->flags |= CG6_FLAG_BLANKED;
break;
}
sbus_writel(val, &thc->thc_misc);
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
static struct sbus_mmap_map cg6_mmap_map[] = {
{
.voff = CG6_FBC,
.poff = CG6_FBC_OFFSET,
.size = PAGE_SIZE
},
{
.voff = CG6_TEC,
.poff = CG6_TEC_OFFSET,
.size = PAGE_SIZE
},
{
.voff = CG6_BTREGS,
.poff = CG6_BROOKTREE_OFFSET,
.size = PAGE_SIZE
},
{
.voff = CG6_FHC,
.poff = CG6_FHC_OFFSET,
.size = PAGE_SIZE
},
{
.voff = CG6_THC,
.poff = CG6_THC_OFFSET,
.size = PAGE_SIZE
},
{
.voff = CG6_ROM,
.poff = CG6_ROM_OFFSET,
.size = 0x10000
},
{
.voff = CG6_RAM,
.poff = CG6_RAM_OFFSET,
.size = SBUS_MMAP_FBSIZE(1)
},
{
.voff = CG6_DHC,
.poff = CG6_DHC_OFFSET,
.size = 0x40000
},
{ .size = 0 }
};
static int cg6_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct cg6_par *par = (struct cg6_par *)info->par;
return sbusfb_mmap_helper(cg6_mmap_map,
info->fix.smem_start, info->fix.smem_len,
par->which_io, vma);
}
static int cg6_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
return sbusfb_ioctl_helper(cmd, arg, info,
FBTYPE_SUNFAST_COLOR, 8, info->fix.smem_len);
}
/*
* Initialisation
*/
static void cg6_init_fix(struct fb_info *info, int linebytes)
{
struct cg6_par *par = (struct cg6_par *)info->par;
const char *cg6_cpu_name, *cg6_card_name;
u32 conf;
conf = sbus_readl(par->fhc);
switch (conf & CG6_FHC_CPU_MASK) {
case CG6_FHC_CPU_SPARC:
cg6_cpu_name = "sparc";
break;
case CG6_FHC_CPU_68020:
cg6_cpu_name = "68020";
break;
default:
cg6_cpu_name = "i386";
break;
}
if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) {
if (info->fix.smem_len <= 0x100000)
cg6_card_name = "TGX";
else
cg6_card_name = "TGX+";
} else {
if (info->fix.smem_len <= 0x100000)
cg6_card_name = "GX";
else
cg6_card_name = "GX+";
}
sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name);
info->fix.id[sizeof(info->fix.id) - 1] = 0;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = linebytes;
info->fix.accel = FB_ACCEL_SUN_CGSIX;
}
/* Initialize Brooktree DAC */
static void cg6_bt_init(struct cg6_par *par)
{
struct bt_regs __iomem *bt = par->bt;
sbus_writel(0x04 << 24, &bt->addr); /* color planes */
sbus_writel(0xff << 24, &bt->control);
sbus_writel(0x05 << 24, &bt->addr);
sbus_writel(0x00 << 24, &bt->control);
sbus_writel(0x06 << 24, &bt->addr); /* overlay plane */
sbus_writel(0x73 << 24, &bt->control);
sbus_writel(0x07 << 24, &bt->addr);
sbus_writel(0x00 << 24, &bt->control);
}
static void cg6_chip_init(struct fb_info *info)
{
struct cg6_par *par = (struct cg6_par *)info->par;
struct cg6_tec __iomem *tec = par->tec;
struct cg6_fbc __iomem *fbc = par->fbc;
struct cg6_thc __iomem *thc = par->thc;
u32 rev, conf, mode;
int i;
/* Hide the cursor. */
sbus_writel(CG6_THC_CURSOFF, &thc->thc_cursxy);
/* Turn off stuff in the Transform Engine. */
sbus_writel(0, &tec->tec_matrix);
sbus_writel(0, &tec->tec_clip);
sbus_writel(0, &tec->tec_vdc);
/* Take care of bugs in old revisions. */
rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK;
if (rev < 5) {
conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) |
CG6_FHC_CPU_68020 | CG6_FHC_TEST |
(11 << CG6_FHC_TEST_X_SHIFT) |
(11 << CG6_FHC_TEST_Y_SHIFT);
if (rev < 2)
conf |= CG6_FHC_DST_DISABLE;
sbus_writel(conf, par->fhc);
}
/* Set things in the FBC. Bad things appear to happen if we do
* back to back store/loads on the mode register, so copy it
* out instead. */
mode = sbus_readl(&fbc->mode);
do {
i = sbus_readl(&fbc->s);
} while (i & 0x10000000);
mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK |
CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK |
CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK |
CG6_FBC_BDISP_MASK);
mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 |
CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE |
CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 |
CG6_FBC_BDISP_0);
sbus_writel(mode, &fbc->mode);
sbus_writel(0, &fbc->clip);
sbus_writel(0, &fbc->offx);
sbus_writel(0, &fbc->offy);
sbus_writel(0, &fbc->clipminx);
sbus_writel(0, &fbc->clipminy);
sbus_writel(info->var.xres - 1, &fbc->clipmaxx);
sbus_writel(info->var.yres - 1, &fbc->clipmaxy);
}
static void cg6_unmap_regs(struct platform_device *op, struct fb_info *info,
struct cg6_par *par)
{
if (par->fbc)
of_iounmap(&op->resource[0], par->fbc, 4096);
if (par->tec)
of_iounmap(&op->resource[0], par->tec, sizeof(struct cg6_tec));
if (par->thc)
of_iounmap(&op->resource[0], par->thc, sizeof(struct cg6_thc));
if (par->bt)
of_iounmap(&op->resource[0], par->bt, sizeof(struct bt_regs));
if (par->fhc)
of_iounmap(&op->resource[0], par->fhc, sizeof(u32));
if (info->screen_base)
of_iounmap(&op->resource[0], info->screen_base,
info->fix.smem_len);
}
static int cg6_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct fb_info *info;
struct cg6_par *par;
int linebytes, err;
int dblbuf;
info = framebuffer_alloc(sizeof(struct cg6_par), &op->dev);
err = -ENOMEM;
if (!info)
goto out_err;
par = info->par;
spin_lock_init(&par->lock);
info->fix.smem_start = op->resource[0].start;
par->which_io = op->resource[0].flags & IORESOURCE_BITS;
sbusfb_fill_var(&info->var, dp, 8);
info->var.red.length = 8;
info->var.green.length = 8;
info->var.blue.length = 8;
linebytes = of_getintprop_default(dp, "linebytes",
info->var.xres);
info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
dblbuf = of_getintprop_default(dp, "dblbuf", 0);
if (dblbuf)
info->fix.smem_len *= 4;
par->fbc = of_ioremap(&op->resource[0], CG6_FBC_OFFSET,
4096, "cgsix fbc");
par->tec = of_ioremap(&op->resource[0], CG6_TEC_OFFSET,
sizeof(struct cg6_tec), "cgsix tec");
par->thc = of_ioremap(&op->resource[0], CG6_THC_OFFSET,
sizeof(struct cg6_thc), "cgsix thc");
par->bt = of_ioremap(&op->resource[0], CG6_BROOKTREE_OFFSET,
sizeof(struct bt_regs), "cgsix dac");
par->fhc = of_ioremap(&op->resource[0], CG6_FHC_OFFSET,
sizeof(u32), "cgsix fhc");
info->flags = FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
FBINFO_READS_FAST;
info->fbops = &cg6_ops;
info->screen_base = of_ioremap(&op->resource[0], CG6_RAM_OFFSET,
info->fix.smem_len, "cgsix ram");
if (!par->fbc || !par->tec || !par->thc ||
!par->bt || !par->fhc || !info->screen_base)
goto out_unmap_regs;
info->var.accel_flags = FB_ACCELF_TEXT;
cg6_bt_init(par);
cg6_chip_init(info);
cg6_blank(FB_BLANK_UNBLANK, info);
if (fb_alloc_cmap(&info->cmap, 256, 0))
goto out_unmap_regs;
fb_set_cmap(&info->cmap, info);
cg6_init_fix(info, linebytes);
err = register_framebuffer(info);
if (err < 0)
goto out_dealloc_cmap;
dev_set_drvdata(&op->dev, info);
printk(KERN_INFO "%pOF: CGsix [%s] at %lx:%lx\n",
dp, info->fix.id,
par->which_io, info->fix.smem_start);
return 0;
out_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
out_unmap_regs:
cg6_unmap_regs(op, info, par);
framebuffer_release(info);
out_err:
return err;
}
static void cg6_remove(struct platform_device *op)
{
struct fb_info *info = dev_get_drvdata(&op->dev);
struct cg6_par *par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
cg6_unmap_regs(op, info, par);
framebuffer_release(info);
}
static const struct of_device_id cg6_match[] = {
{
.name = "cgsix",
},
{
.name = "cgthree+",
},
{},
};
MODULE_DEVICE_TABLE(of, cg6_match);
static struct platform_driver cg6_driver = {
.driver = {
.name = "cg6",
.of_match_table = cg6_match,
},
.probe = cg6_probe,
.remove_new = cg6_remove,
};
static int __init cg6_init(void)
{
if (fb_get_options("cg6fb", NULL))
return -ENODEV;
return platform_driver_register(&cg6_driver);
}
static void __exit cg6_exit(void)
{
platform_driver_unregister(&cg6_driver);
}
module_init(cg6_init);
module_exit(cg6_exit);
MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/cg6.c |
/* sunxvr1000.c: Sun XVR-1000 fb driver for sparc64 systems
*
* License: GPL
*
* Copyright (C) 2010 David S. Miller ([email protected])
*/
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
struct gfb_info {
struct fb_info *info;
char __iomem *fb_base;
unsigned long fb_base_phys;
struct device_node *of_node;
unsigned int width;
unsigned int height;
unsigned int depth;
unsigned int fb_size;
u32 pseudo_palette[16];
};
static int gfb_get_props(struct gfb_info *gp)
{
gp->width = of_getintprop_default(gp->of_node, "width", 0);
gp->height = of_getintprop_default(gp->of_node, "height", 0);
gp->depth = of_getintprop_default(gp->of_node, "depth", 32);
if (!gp->width || !gp->height) {
printk(KERN_ERR "gfb: Critical properties missing for %pOF\n",
gp->of_node);
return -EINVAL;
}
return 0;
}
static int gfb_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
u32 value;
if (regno < 16) {
red >>= 8;
green >>= 8;
blue >>= 8;
value = (blue << 16) | (green << 8) | red;
((u32 *)info->pseudo_palette)[regno] = value;
}
return 0;
}
static const struct fb_ops gfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = gfb_setcolreg,
};
static int gfb_set_fbinfo(struct gfb_info *gp)
{
struct fb_info *info = gp->info;
struct fb_var_screeninfo *var = &info->var;
info->fbops = &gfb_ops;
info->screen_base = gp->fb_base;
info->screen_size = gp->fb_size;
info->pseudo_palette = gp->pseudo_palette;
/* Fill fix common fields */
strscpy(info->fix.id, "gfb", sizeof(info->fix.id));
info->fix.smem_start = gp->fb_base_phys;
info->fix.smem_len = gp->fb_size;
info->fix.type = FB_TYPE_PACKED_PIXELS;
if (gp->depth == 32 || gp->depth == 24)
info->fix.visual = FB_VISUAL_TRUECOLOR;
else
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
var->xres = gp->width;
var->yres = gp->height;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->bits_per_pixel = gp->depth;
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
if (fb_alloc_cmap(&info->cmap, 256, 0)) {
printk(KERN_ERR "gfb: Cannot allocate color map.\n");
return -ENOMEM;
}
return 0;
}
static int gfb_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct fb_info *info;
struct gfb_info *gp;
int err;
info = framebuffer_alloc(sizeof(struct gfb_info), &op->dev);
if (!info) {
err = -ENOMEM;
goto err_out;
}
gp = info->par;
gp->info = info;
gp->of_node = dp;
gp->fb_base_phys = op->resource[6].start;
err = gfb_get_props(gp);
if (err)
goto err_release_fb;
/* Framebuffer length is the same regardless of resolution. */
info->fix.line_length = 16384;
gp->fb_size = info->fix.line_length * gp->height;
gp->fb_base = of_ioremap(&op->resource[6], 0,
gp->fb_size, "gfb fb");
if (!gp->fb_base) {
err = -ENOMEM;
goto err_release_fb;
}
err = gfb_set_fbinfo(gp);
if (err)
goto err_unmap_fb;
printk("gfb: Found device at %pOF\n", dp);
err = register_framebuffer(info);
if (err < 0) {
printk(KERN_ERR "gfb: Could not register framebuffer %pOF\n",
dp);
goto err_unmap_fb;
}
dev_set_drvdata(&op->dev, info);
return 0;
err_unmap_fb:
of_iounmap(&op->resource[6], gp->fb_base, gp->fb_size);
err_release_fb:
framebuffer_release(info);
err_out:
return err;
}
static const struct of_device_id gfb_match[] = {
{
.name = "SUNW,gfb",
},
{},
};
static struct platform_driver gfb_driver = {
.probe = gfb_probe,
.driver = {
.name = "gfb",
.of_match_table = gfb_match,
.suppress_bind_attrs = true,
},
};
static int __init gfb_init(void)
{
if (fb_get_options("gfb", NULL))
return -ENODEV;
return platform_driver_register(&gfb_driver);
}
device_initcall(gfb_init);
| linux-master | drivers/video/fbdev/sunxvr1000.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2008-2009 MontaVista Software Inc.
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* Based on the LCD driver for TI Avalanche processors written by
* Ajay Singh and Shalom Hai.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/console.h>
#include <linux/regulator/consumer.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/lcm.h>
#include <video/da8xx-fb.h>
#include <asm/div64.h>
#define DRIVER_NAME "da8xx_lcdc"
#define LCD_VERSION_1 1
#define LCD_VERSION_2 2
/* LCD Status Register */
#define LCD_END_OF_FRAME1 BIT(9)
#define LCD_END_OF_FRAME0 BIT(8)
#define LCD_PL_LOAD_DONE BIT(6)
#define LCD_FIFO_UNDERFLOW BIT(5)
#define LCD_SYNC_LOST BIT(2)
#define LCD_FRAME_DONE BIT(0)
/* LCD DMA Control Register */
#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
#define LCD_DMA_BURST_1 0x0
#define LCD_DMA_BURST_2 0x1
#define LCD_DMA_BURST_4 0x2
#define LCD_DMA_BURST_8 0x3
#define LCD_DMA_BURST_16 0x4
#define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
#define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
#define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
/* LCD Control Register */
#define LCD_CLK_DIVISOR(x) ((x) << 8)
#define LCD_RASTER_MODE 0x01
/* LCD Raster Control Register */
#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
#define PALETTE_AND_DATA 0x00
#define PALETTE_ONLY 0x01
#define DATA_ONLY 0x02
#define LCD_MONO_8BIT_MODE BIT(9)
#define LCD_RASTER_ORDER BIT(8)
#define LCD_TFT_MODE BIT(7)
#define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
#define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
#define LCD_V1_PL_INT_ENA BIT(4)
#define LCD_V2_PL_INT_ENA BIT(6)
#define LCD_MONOCHROME_MODE BIT(1)
#define LCD_RASTER_ENABLE BIT(0)
#define LCD_TFT_ALT_ENABLE BIT(23)
#define LCD_STN_565_ENABLE BIT(24)
#define LCD_V2_DMA_CLK_EN BIT(2)
#define LCD_V2_LIDD_CLK_EN BIT(1)
#define LCD_V2_CORE_CLK_EN BIT(0)
#define LCD_V2_LPP_B10 26
#define LCD_V2_TFT_24BPP_MODE BIT(25)
#define LCD_V2_TFT_24BPP_UNPACK BIT(26)
/* LCD Raster Timing 2 Register */
#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
#define LCD_SYNC_CTRL BIT(25)
#define LCD_SYNC_EDGE BIT(24)
#define LCD_INVERT_PIXEL_CLOCK BIT(22)
#define LCD_INVERT_LINE_CLOCK BIT(21)
#define LCD_INVERT_FRAME_CLOCK BIT(20)
/* LCD Block */
#define LCD_PID_REG 0x0
#define LCD_CTRL_REG 0x4
#define LCD_STAT_REG 0x8
#define LCD_RASTER_CTRL_REG 0x28
#define LCD_RASTER_TIMING_0_REG 0x2C
#define LCD_RASTER_TIMING_1_REG 0x30
#define LCD_RASTER_TIMING_2_REG 0x34
#define LCD_DMA_CTRL_REG 0x40
#define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
#define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
#define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
#define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
/* Interrupt Registers available only in Version 2 */
#define LCD_RAW_STAT_REG 0x58
#define LCD_MASKED_STAT_REG 0x5c
#define LCD_INT_ENABLE_SET_REG 0x60
#define LCD_INT_ENABLE_CLR_REG 0x64
#define LCD_END_OF_INT_IND_REG 0x68
/* Clock registers available only on Version 2 */
#define LCD_CLK_ENABLE_REG 0x6c
#define LCD_CLK_RESET_REG 0x70
#define LCD_CLK_MAIN_RESET BIT(3)
#define LCD_NUM_BUFFERS 2
#define PALETTE_SIZE 256
#define CLK_MIN_DIV 2
#define CLK_MAX_DIV 255
static void __iomem *da8xx_fb_reg_base;
static unsigned int lcd_revision;
static irq_handler_t lcdc_irq_handler;
static wait_queue_head_t frame_done_wq;
static int frame_done_flag;
static unsigned int lcdc_read(unsigned int addr)
{
return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
}
static void lcdc_write(unsigned int val, unsigned int addr)
{
__raw_writel(val, da8xx_fb_reg_base + (addr));
}
struct da8xx_fb_par {
struct device *dev;
dma_addr_t p_palette_base;
unsigned char *v_palette_base;
dma_addr_t vram_phys;
unsigned long vram_size;
void *vram_virt;
unsigned int dma_start;
unsigned int dma_end;
struct clk *lcdc_clk;
int irq;
unsigned int palette_sz;
int blank;
wait_queue_head_t vsync_wait;
int vsync_flag;
int vsync_timeout;
spinlock_t lock_for_chan_update;
/*
* LCDC has 2 ping pong DMA channels, channel 0
* and channel 1.
*/
unsigned int which_dma_channel_done;
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
#endif
unsigned int lcdc_clk_rate;
struct regulator *lcd_supply;
u32 pseudo_palette[16];
struct fb_videomode mode;
struct lcd_ctrl_config cfg;
};
static struct fb_var_screeninfo da8xx_fb_var;
static struct fb_fix_screeninfo da8xx_fb_fix = {
.id = "DA8xx FB Drv",
.type = FB_TYPE_PACKED_PIXELS,
.type_aux = 0,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE
};
static struct fb_videomode known_lcd_panels[] = {
/* Sharp LCD035Q3DG01 */
[0] = {
.name = "Sharp_LCD035Q3DG01",
.xres = 320,
.yres = 240,
.pixclock = KHZ2PICOS(4607),
.left_margin = 6,
.right_margin = 8,
.upper_margin = 2,
.lower_margin = 2,
.hsync_len = 0,
.vsync_len = 0,
.sync = FB_SYNC_CLK_INVERT,
},
/* Sharp LK043T1DG01 */
[1] = {
.name = "Sharp_LK043T1DG01",
.xres = 480,
.yres = 272,
.pixclock = KHZ2PICOS(7833),
.left_margin = 2,
.right_margin = 2,
.upper_margin = 2,
.lower_margin = 2,
.hsync_len = 41,
.vsync_len = 10,
.sync = 0,
.flag = 0,
},
[2] = {
/* Hitachi SP10Q010 */
.name = "SP10Q010",
.xres = 320,
.yres = 240,
.pixclock = KHZ2PICOS(7833),
.left_margin = 10,
.right_margin = 10,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 10,
.vsync_len = 10,
.sync = 0,
.flag = 0,
},
[3] = {
/* Densitron 84-0023-001T */
.name = "Densitron_84-0023-001T",
.xres = 320,
.yres = 240,
.pixclock = KHZ2PICOS(6400),
.left_margin = 0,
.right_margin = 0,
.upper_margin = 0,
.lower_margin = 0,
.hsync_len = 30,
.vsync_len = 3,
.sync = 0,
},
};
static bool da8xx_fb_is_raster_enabled(void)
{
return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE);
}
/* Enable the Raster Engine of the LCD Controller */
static void lcd_enable_raster(void)
{
u32 reg;
/* Put LCDC in reset for several cycles */
if (lcd_revision == LCD_VERSION_2)
/* Write 1 to reset LCDC */
lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
mdelay(1);
/* Bring LCDC out of reset */
if (lcd_revision == LCD_VERSION_2)
lcdc_write(0, LCD_CLK_RESET_REG);
mdelay(1);
/* Above reset sequence doesnot reset register context */
reg = lcdc_read(LCD_RASTER_CTRL_REG);
if (!(reg & LCD_RASTER_ENABLE))
lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
}
/* Disable the Raster Engine of the LCD Controller */
static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done)
{
u32 reg;
int ret;
reg = lcdc_read(LCD_RASTER_CTRL_REG);
if (reg & LCD_RASTER_ENABLE)
lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
else
/* return if already disabled */
return;
if ((wait_for_frame_done == DA8XX_FRAME_WAIT) &&
(lcd_revision == LCD_VERSION_2)) {
frame_done_flag = 0;
ret = wait_event_interruptible_timeout(frame_done_wq,
frame_done_flag != 0,
msecs_to_jiffies(50));
if (ret == 0)
pr_err("LCD Controller timed out\n");
}
}
static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
{
u32 start;
u32 end;
u32 reg_ras;
u32 reg_dma;
u32 reg_int;
/* init reg to clear PLM (loading mode) fields */
reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
reg_ras &= ~(3 << 20);
reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
if (load_mode == LOAD_DATA) {
start = par->dma_start;
end = par->dma_end;
reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
if (lcd_revision == LCD_VERSION_1) {
reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
} else {
reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
LCD_V2_END_OF_FRAME0_INT_ENA |
LCD_V2_END_OF_FRAME1_INT_ENA |
LCD_FRAME_DONE | LCD_SYNC_LOST;
lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
}
reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
} else if (load_mode == LOAD_PALETTE) {
start = par->p_palette_base;
end = start + par->palette_sz - 1;
reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
if (lcd_revision == LCD_VERSION_1) {
reg_ras |= LCD_V1_PL_INT_ENA;
} else {
reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
LCD_V2_PL_INT_ENA;
lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
}
lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
}
lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
/*
* The Raster enable bit must be set after all other control fields are
* set.
*/
lcd_enable_raster();
}
/* Configure the Burst Size and fifo threhold of DMA */
static int lcd_cfg_dma(int burst_size, int fifo_th)
{
u32 reg;
reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
switch (burst_size) {
case 1:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
break;
case 2:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
break;
case 4:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
break;
case 8:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
break;
case 16:
default:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
break;
}
reg |= (fifo_th << 8);
lcdc_write(reg, LCD_DMA_CTRL_REG);
return 0;
}
static void lcd_cfg_ac_bias(int period, int transitions_per_int)
{
u32 reg;
/* Set the AC Bias Period and Number of Transisitons per Interrupt */
reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
reg |= LCD_AC_BIAS_FREQUENCY(period) |
LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
}
static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
int front_porch)
{
u32 reg;
reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff;
reg |= (((back_porch-1) & 0xff) << 24)
| (((front_porch-1) & 0xff) << 16)
| (((pulse_width-1) & 0x3f) << 10);
lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
/*
* LCDC Version 2 adds some extra bits that increase the allowable
* size of the horizontal timing registers.
* remember that the registers use 0 to represent 1 so all values
* that get set into register need to be decremented by 1
*/
if (lcd_revision == LCD_VERSION_2) {
/* Mask off the bits we want to change */
reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff;
reg |= ((front_porch-1) & 0x300) >> 8;
reg |= ((back_porch-1) & 0x300) >> 4;
reg |= ((pulse_width-1) & 0x3c0) << 21;
lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
}
}
static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
int front_porch)
{
u32 reg;
reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
reg |= ((back_porch & 0xff) << 24)
| ((front_porch & 0xff) << 16)
| (((pulse_width-1) & 0x3f) << 10);
lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
}
static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
struct fb_videomode *panel)
{
u32 reg;
u32 reg_int;
reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
LCD_MONO_8BIT_MODE |
LCD_MONOCHROME_MODE);
switch (cfg->panel_shade) {
case MONOCHROME:
reg |= LCD_MONOCHROME_MODE;
if (cfg->mono_8bit_mode)
reg |= LCD_MONO_8BIT_MODE;
break;
case COLOR_ACTIVE:
reg |= LCD_TFT_MODE;
if (cfg->tft_alt_mode)
reg |= LCD_TFT_ALT_ENABLE;
break;
case COLOR_PASSIVE:
/* AC bias applicable only for Pasive panels */
lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
if (cfg->bpp == 12 && cfg->stn_565_mode)
reg |= LCD_STN_565_ENABLE;
break;
default:
return -EINVAL;
}
/* enable additional interrupts here */
if (lcd_revision == LCD_VERSION_1) {
reg |= LCD_V1_UNDERFLOW_INT_ENA;
} else {
reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
LCD_V2_UNDERFLOW_INT_ENA;
lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
}
lcdc_write(reg, LCD_RASTER_CTRL_REG);
reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
reg |= LCD_SYNC_CTRL;
if (cfg->sync_edge)
reg |= LCD_SYNC_EDGE;
else
reg &= ~LCD_SYNC_EDGE;
if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
reg |= LCD_INVERT_LINE_CLOCK;
else
reg &= ~LCD_INVERT_LINE_CLOCK;
if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
reg |= LCD_INVERT_FRAME_CLOCK;
else
reg &= ~LCD_INVERT_FRAME_CLOCK;
lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
return 0;
}
static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
u32 bpp, u32 raster_order)
{
u32 reg;
if (bpp > 16 && lcd_revision == LCD_VERSION_1)
return -EINVAL;
/* Set the Panel Width */
/* Pixels per line = (PPL + 1)*16 */
if (lcd_revision == LCD_VERSION_1) {
/*
* 0x3F in bits 4..9 gives max horizontal resolution = 1024
* pixels.
*/
width &= 0x3f0;
} else {
/*
* 0x7F in bits 4..10 gives max horizontal resolution = 2048
* pixels.
*/
width &= 0x7f0;
}
reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
reg &= 0xfffffc00;
if (lcd_revision == LCD_VERSION_1) {
reg |= ((width >> 4) - 1) << 4;
} else {
width = (width >> 4) - 1;
reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
}
lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
/* Set the Panel Height */
/* Set bits 9:0 of Lines Per Pixel */
reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
/* Set bit 10 of Lines Per Pixel */
if (lcd_revision == LCD_VERSION_2) {
reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
reg |= ((height - 1) & 0x400) << 16;
lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
}
/* Set the Raster Order of the Frame Buffer */
reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
if (raster_order)
reg |= LCD_RASTER_ORDER;
par->palette_sz = 16 * 2;
switch (bpp) {
case 1:
case 2:
case 4:
case 16:
break;
case 24:
reg |= LCD_V2_TFT_24BPP_MODE;
break;
case 32:
reg |= LCD_V2_TFT_24BPP_MODE;
reg |= LCD_V2_TFT_24BPP_UNPACK;
break;
case 8:
par->palette_sz = 256 * 2;
break;
default:
return -EINVAL;
}
lcdc_write(reg, LCD_RASTER_CTRL_REG);
return 0;
}
#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct da8xx_fb_par *par = info->par;
unsigned short *palette = (unsigned short *) par->v_palette_base;
u_short pal;
int update_hw = 0;
if (regno > 255)
return 1;
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
return 1;
if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
return -EINVAL;
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
break;
case FB_VISUAL_PSEUDOCOLOR:
switch (info->var.bits_per_pixel) {
case 4:
if (regno > 15)
return -EINVAL;
if (info->var.grayscale) {
pal = regno;
} else {
red >>= 4;
green >>= 8;
blue >>= 12;
pal = red & 0x0f00;
pal |= green & 0x00f0;
pal |= blue & 0x000f;
}
if (regno == 0)
pal |= 0x2000;
palette[regno] = pal;
break;
case 8:
red >>= 4;
green >>= 8;
blue >>= 12;
pal = (red & 0x0f00);
pal |= (green & 0x00f0);
pal |= (blue & 0x000f);
if (palette[regno] != pal) {
update_hw = 1;
palette[regno] = pal;
}
break;
}
break;
}
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 v;
if (regno > 15)
return -EINVAL;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
((u32 *) (info->pseudo_palette))[regno] = v;
if (palette[0] != 0x4000) {
update_hw = 1;
palette[0] = 0x4000;
}
}
/* Update the palette in the h/w as needed. */
if (update_hw)
lcd_blit(LOAD_PALETTE, par);
return 0;
}
#undef CNVT_TOHW
static void da8xx_fb_lcd_reset(void)
{
/* DMA has to be disabled */
lcdc_write(0, LCD_DMA_CTRL_REG);
lcdc_write(0, LCD_RASTER_CTRL_REG);
if (lcd_revision == LCD_VERSION_2) {
lcdc_write(0, LCD_INT_ENABLE_SET_REG);
/* Write 1 to reset */
lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
lcdc_write(0, LCD_CLK_RESET_REG);
}
}
static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par,
unsigned lcdc_clk_div,
unsigned lcdc_clk_rate)
{
int ret;
if (par->lcdc_clk_rate != lcdc_clk_rate) {
ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate);
if (ret) {
dev_err(par->dev,
"unable to set clock rate at %u\n",
lcdc_clk_rate);
return ret;
}
par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
}
/* Configure the LCD clock divisor. */
lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) |
(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
if (lcd_revision == LCD_VERSION_2)
lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
return 0;
}
static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
unsigned pixclock,
unsigned *lcdc_clk_rate)
{
unsigned lcdc_clk_div;
pixclock = PICOS2KHZ(pixclock) * 1000;
*lcdc_clk_rate = par->lcdc_clk_rate;
if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) {
*lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
pixclock * CLK_MAX_DIV);
lcdc_clk_div = CLK_MAX_DIV;
} else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) {
*lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
pixclock * CLK_MIN_DIV);
lcdc_clk_div = CLK_MIN_DIV;
} else {
lcdc_clk_div = *lcdc_clk_rate / pixclock;
}
return lcdc_clk_div;
}
static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
struct fb_videomode *mode)
{
unsigned lcdc_clk_rate;
unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock,
&lcdc_clk_rate);
return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate);
}
static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
unsigned pixclock)
{
unsigned lcdc_clk_div, lcdc_clk_rate;
lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate);
return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div));
}
static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
struct fb_videomode *panel)
{
u32 bpp;
int ret = 0;
ret = da8xx_fb_calc_config_clk_divider(par, panel);
if (ret) {
dev_err(par->dev, "unable to configure clock\n");
return ret;
}
if (panel->sync & FB_SYNC_CLK_INVERT)
lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
else
lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
/* Configure the DMA burst size and fifo threshold. */
ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
if (ret < 0)
return ret;
/* Configure the vertical and horizontal sync properties. */
lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len,
panel->lower_margin);
lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len,
panel->right_margin);
/* Configure for disply */
ret = lcd_cfg_display(cfg, panel);
if (ret < 0)
return ret;
bpp = cfg->bpp;
if (bpp == 12)
bpp = 16;
ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
(unsigned int)panel->yres, bpp,
cfg->raster_order);
if (ret < 0)
return ret;
/* Configure FDD */
lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
(cfg->fdd << 12), LCD_RASTER_CTRL_REG);
return 0;
}
/* IRQ handler for version 2 of LCDC */
static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
{
struct da8xx_fb_par *par = arg;
u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
lcd_disable_raster(DA8XX_FRAME_NOWAIT);
lcdc_write(stat, LCD_MASKED_STAT_REG);
lcd_enable_raster();
} else if (stat & LCD_PL_LOAD_DONE) {
/*
* Must disable raster before changing state of any control bit.
* And also must be disabled before clearing the PL loading
* interrupt via the following write to the status register. If
* this is done after then one gets multiple PL done interrupts.
*/
lcd_disable_raster(DA8XX_FRAME_NOWAIT);
lcdc_write(stat, LCD_MASKED_STAT_REG);
/* Disable PL completion interrupt */
lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
/* Setup and start data loading mode */
lcd_blit(LOAD_DATA, par);
} else {
lcdc_write(stat, LCD_MASKED_STAT_REG);
if (stat & LCD_END_OF_FRAME0) {
par->which_dma_channel_done = 0;
lcdc_write(par->dma_start,
LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
lcdc_write(par->dma_end,
LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
par->vsync_flag = 1;
wake_up_interruptible(&par->vsync_wait);
}
if (stat & LCD_END_OF_FRAME1) {
par->which_dma_channel_done = 1;
lcdc_write(par->dma_start,
LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
lcdc_write(par->dma_end,
LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
par->vsync_flag = 1;
wake_up_interruptible(&par->vsync_wait);
}
/* Set only when controller is disabled and at the end of
* active frame
*/
if (stat & BIT(0)) {
frame_done_flag = 1;
wake_up_interruptible(&frame_done_wq);
}
}
lcdc_write(0, LCD_END_OF_INT_IND_REG);
return IRQ_HANDLED;
}
/* IRQ handler for version 1 LCDC */
static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
{
struct da8xx_fb_par *par = arg;
u32 stat = lcdc_read(LCD_STAT_REG);
u32 reg_ras;
if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
lcd_disable_raster(DA8XX_FRAME_NOWAIT);
lcdc_write(stat, LCD_STAT_REG);
lcd_enable_raster();
} else if (stat & LCD_PL_LOAD_DONE) {
/*
* Must disable raster before changing state of any control bit.
* And also must be disabled before clearing the PL loading
* interrupt via the following write to the status register. If
* this is done after then one gets multiple PL done interrupts.
*/
lcd_disable_raster(DA8XX_FRAME_NOWAIT);
lcdc_write(stat, LCD_STAT_REG);
/* Disable PL completion inerrupt */
reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
reg_ras &= ~LCD_V1_PL_INT_ENA;
lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
/* Setup and start data loading mode */
lcd_blit(LOAD_DATA, par);
} else {
lcdc_write(stat, LCD_STAT_REG);
if (stat & LCD_END_OF_FRAME0) {
par->which_dma_channel_done = 0;
lcdc_write(par->dma_start,
LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
lcdc_write(par->dma_end,
LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
par->vsync_flag = 1;
wake_up_interruptible(&par->vsync_wait);
}
if (stat & LCD_END_OF_FRAME1) {
par->which_dma_channel_done = 1;
lcdc_write(par->dma_start,
LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
lcdc_write(par->dma_end,
LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
par->vsync_flag = 1;
wake_up_interruptible(&par->vsync_wait);
}
}
return IRQ_HANDLED;
}
static int fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int err = 0;
struct da8xx_fb_par *par = info->par;
int bpp = var->bits_per_pixel >> 3;
unsigned long line_size = var->xres_virtual * bpp;
if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
return -EINVAL;
switch (var->bits_per_pixel) {
case 1:
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
var->nonstd = 0;
break;
case 4:
var->red.offset = 0;
var->red.length = 4;
var->green.offset = 0;
var->green.length = 4;
var->blue.offset = 0;
var->blue.length = 4;
var->transp.offset = 0;
var->transp.length = 0;
var->nonstd = FB_NONSTD_REV_PIX_IN_B;
break;
case 16: /* RGB 565 */
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
var->nonstd = 0;
break;
case 24:
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->nonstd = 0;
break;
case 32:
var->transp.offset = 24;
var->transp.length = 8;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->nonstd = 0;
break;
default:
err = -EINVAL;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
if (line_size * var->yres_virtual > par->vram_size)
var->yres_virtual = par->vram_size / line_size;
if (var->yres > var->yres_virtual)
var->yres = var->yres_virtual;
if (var->xres > var->xres_virtual)
var->xres = var->xres_virtual;
if (var->xres + var->xoffset > var->xres_virtual)
var->xoffset = var->xres_virtual - var->xres;
if (var->yres + var->yoffset > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
return err;
}
#ifdef CONFIG_CPU_FREQ
static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
unsigned long val, void *data)
{
struct da8xx_fb_par *par;
par = container_of(nb, struct da8xx_fb_par, freq_transition);
if (val == CPUFREQ_POSTCHANGE) {
if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) {
par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
lcd_disable_raster(DA8XX_FRAME_WAIT);
da8xx_fb_calc_config_clk_divider(par, &par->mode);
if (par->blank == FB_BLANK_UNBLANK)
lcd_enable_raster();
}
}
return 0;
}
static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
{
par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
return cpufreq_register_notifier(&par->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
}
static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
{
cpufreq_unregister_notifier(&par->freq_transition,
CPUFREQ_TRANSITION_NOTIFIER);
}
#endif
static void fb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
struct da8xx_fb_par *par = info->par;
int ret;
#ifdef CONFIG_CPU_FREQ
lcd_da8xx_cpufreq_deregister(par);
#endif
if (par->lcd_supply) {
ret = regulator_disable(par->lcd_supply);
if (ret)
dev_warn(&dev->dev, "Failed to disable regulator (%pe)\n",
ERR_PTR(ret));
}
lcd_disable_raster(DA8XX_FRAME_WAIT);
lcdc_write(0, LCD_RASTER_CTRL_REG);
/* disable DMA */
lcdc_write(0, LCD_DMA_CTRL_REG);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
pm_runtime_put_sync(&dev->dev);
pm_runtime_disable(&dev->dev);
framebuffer_release(info);
}
/*
* Function to wait for vertical sync which for this LCD peripheral
* translates into waiting for the current raster frame to complete.
*/
static int fb_wait_for_vsync(struct fb_info *info)
{
struct da8xx_fb_par *par = info->par;
int ret;
/*
* Set flag to 0 and wait for isr to set to 1. It would seem there is a
* race condition here where the ISR could have occurred just before or
* just after this set. But since we are just coarsely waiting for
* a frame to complete then that's OK. i.e. if the frame completed
* just before this code executed then we have to wait another full
* frame time but there is no way to avoid such a situation. On the
* other hand if the frame completed just after then we don't need
* to wait long at all. Either way we are guaranteed to return to the
* user immediately after a frame completion which is all that is
* required.
*/
par->vsync_flag = 0;
ret = wait_event_interruptible_timeout(par->vsync_wait,
par->vsync_flag != 0,
par->vsync_timeout);
if (ret < 0)
return ret;
if (ret == 0)
return -ETIMEDOUT;
return 0;
}
static int fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct lcd_sync_arg sync_arg;
switch (cmd) {
case FBIOGET_CONTRAST:
case FBIOPUT_CONTRAST:
case FBIGET_BRIGHTNESS:
case FBIPUT_BRIGHTNESS:
case FBIGET_COLOR:
case FBIPUT_COLOR:
return -ENOTTY;
case FBIPUT_HSYNC:
if (copy_from_user(&sync_arg, (char *)arg,
sizeof(struct lcd_sync_arg)))
return -EFAULT;
lcd_cfg_horizontal_sync(sync_arg.back_porch,
sync_arg.pulse_width,
sync_arg.front_porch);
break;
case FBIPUT_VSYNC:
if (copy_from_user(&sync_arg, (char *)arg,
sizeof(struct lcd_sync_arg)))
return -EFAULT;
lcd_cfg_vertical_sync(sync_arg.back_porch,
sync_arg.pulse_width,
sync_arg.front_porch);
break;
case FBIO_WAITFORVSYNC:
return fb_wait_for_vsync(info);
default:
return -EINVAL;
}
return 0;
}
static int cfb_blank(int blank, struct fb_info *info)
{
struct da8xx_fb_par *par = info->par;
int ret = 0;
if (par->blank == blank)
return 0;
par->blank = blank;
switch (blank) {
case FB_BLANK_UNBLANK:
lcd_enable_raster();
if (par->lcd_supply) {
ret = regulator_enable(par->lcd_supply);
if (ret)
return ret;
}
break;
case FB_BLANK_NORMAL:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
if (par->lcd_supply) {
ret = regulator_disable(par->lcd_supply);
if (ret)
return ret;
}
lcd_disable_raster(DA8XX_FRAME_WAIT);
break;
default:
ret = -EINVAL;
}
return ret;
}
/*
* Set new x,y offsets in the virtual display for the visible area and switch
* to the new mode.
*/
static int da8xx_pan_display(struct fb_var_screeninfo *var,
struct fb_info *fbi)
{
int ret = 0;
struct fb_var_screeninfo new_var;
struct da8xx_fb_par *par = fbi->par;
struct fb_fix_screeninfo *fix = &fbi->fix;
unsigned int end;
unsigned int start;
unsigned long irq_flags;
if (var->xoffset != fbi->var.xoffset ||
var->yoffset != fbi->var.yoffset) {
memcpy(&new_var, &fbi->var, sizeof(new_var));
new_var.xoffset = var->xoffset;
new_var.yoffset = var->yoffset;
if (fb_check_var(&new_var, fbi))
ret = -EINVAL;
else {
memcpy(&fbi->var, &new_var, sizeof(new_var));
start = fix->smem_start +
new_var.yoffset * fix->line_length +
new_var.xoffset * fbi->var.bits_per_pixel / 8;
end = start + fbi->var.yres * fix->line_length - 1;
par->dma_start = start;
par->dma_end = end;
spin_lock_irqsave(&par->lock_for_chan_update,
irq_flags);
if (par->which_dma_channel_done == 0) {
lcdc_write(par->dma_start,
LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
lcdc_write(par->dma_end,
LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
} else if (par->which_dma_channel_done == 1) {
lcdc_write(par->dma_start,
LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
lcdc_write(par->dma_end,
LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
}
spin_unlock_irqrestore(&par->lock_for_chan_update,
irq_flags);
}
}
return ret;
}
static int da8xxfb_set_par(struct fb_info *info)
{
struct da8xx_fb_par *par = info->par;
int ret;
bool raster = da8xx_fb_is_raster_enabled();
if (raster)
lcd_disable_raster(DA8XX_FRAME_WAIT);
fb_var_to_videomode(&par->mode, &info->var);
par->cfg.bpp = info->var.bits_per_pixel;
info->fix.visual = (par->cfg.bpp <= 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
ret = lcd_init(par, &par->cfg, &par->mode);
if (ret < 0) {
dev_err(par->dev, "lcd init failed\n");
return ret;
}
par->dma_start = info->fix.smem_start +
info->var.yoffset * info->fix.line_length +
info->var.xoffset * info->var.bits_per_pixel / 8;
par->dma_end = par->dma_start +
info->var.yres * info->fix.line_length - 1;
lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
if (raster)
lcd_enable_raster();
return 0;
}
static const struct fb_ops da8xx_fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = fb_check_var,
.fb_set_par = da8xxfb_set_par,
.fb_setcolreg = fb_setcolreg,
.fb_pan_display = da8xx_pan_display,
.fb_ioctl = fb_ioctl,
.fb_blank = cfb_blank,
};
static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
{
struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev);
struct fb_videomode *lcdc_info;
int i;
for (i = 0, lcdc_info = known_lcd_panels;
i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
break;
}
if (i == ARRAY_SIZE(known_lcd_panels)) {
dev_err(&dev->dev, "no panel found\n");
return NULL;
}
dev_info(&dev->dev, "found %s panel\n", lcdc_info->name);
return lcdc_info;
}
static int fb_probe(struct platform_device *device)
{
struct da8xx_lcdc_platform_data *fb_pdata =
dev_get_platdata(&device->dev);
struct lcd_ctrl_config *lcd_cfg;
struct fb_videomode *lcdc_info;
struct fb_info *da8xx_fb_info;
struct da8xx_fb_par *par;
struct clk *tmp_lcdc_clk;
int ret;
unsigned long ulcm;
if (fb_pdata == NULL) {
dev_err(&device->dev, "Can not get platform data\n");
return -ENOENT;
}
lcdc_info = da8xx_fb_get_videomode(device);
if (lcdc_info == NULL)
return -ENODEV;
da8xx_fb_reg_base = devm_platform_ioremap_resource(device, 0);
if (IS_ERR(da8xx_fb_reg_base))
return PTR_ERR(da8xx_fb_reg_base);
tmp_lcdc_clk = devm_clk_get(&device->dev, "fck");
if (IS_ERR(tmp_lcdc_clk))
return dev_err_probe(&device->dev, PTR_ERR(tmp_lcdc_clk),
"Can not get device clock\n");
pm_runtime_enable(&device->dev);
pm_runtime_get_sync(&device->dev);
/* Determine LCD IP Version */
switch (lcdc_read(LCD_PID_REG)) {
case 0x4C100102:
lcd_revision = LCD_VERSION_1;
break;
case 0x4F200800:
case 0x4F201000:
lcd_revision = LCD_VERSION_2;
break;
default:
dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
"defaulting to LCD revision 1\n",
lcdc_read(LCD_PID_REG));
lcd_revision = LCD_VERSION_1;
break;
}
lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
if (!lcd_cfg) {
ret = -EINVAL;
goto err_pm_runtime_disable;
}
da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
&device->dev);
if (!da8xx_fb_info) {
ret = -ENOMEM;
goto err_pm_runtime_disable;
}
par = da8xx_fb_info->par;
par->dev = &device->dev;
par->lcdc_clk = tmp_lcdc_clk;
par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
par->lcd_supply = devm_regulator_get_optional(&device->dev, "lcd");
if (IS_ERR(par->lcd_supply)) {
if (PTR_ERR(par->lcd_supply) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto err_release_fb;
}
par->lcd_supply = NULL;
} else {
ret = regulator_enable(par->lcd_supply);
if (ret)
goto err_release_fb;
}
fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
par->cfg = *lcd_cfg;
da8xx_fb_lcd_reset();
/* allocate frame buffer */
par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE);
par->vram_size = roundup(par->vram_size/8, ulcm);
par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
par->vram_virt = dmam_alloc_coherent(par->dev,
par->vram_size,
&par->vram_phys,
GFP_KERNEL | GFP_DMA);
if (!par->vram_virt) {
dev_err(&device->dev,
"GLCD: kmalloc for frame buffer failed\n");
ret = -EINVAL;
goto err_disable_reg;
}
da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
da8xx_fb_fix.smem_start = par->vram_phys;
da8xx_fb_fix.smem_len = par->vram_size;
da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8;
par->dma_start = par->vram_phys;
par->dma_end = par->dma_start + lcdc_info->yres *
da8xx_fb_fix.line_length - 1;
/* allocate palette buffer */
par->v_palette_base = dmam_alloc_coherent(par->dev, PALETTE_SIZE,
&par->p_palette_base,
GFP_KERNEL | GFP_DMA);
if (!par->v_palette_base) {
dev_err(&device->dev,
"GLCD: kmalloc for palette buffer failed\n");
ret = -EINVAL;
goto err_release_fb;
}
par->irq = platform_get_irq(device, 0);
if (par->irq < 0) {
ret = -ENOENT;
goto err_release_fb;
}
da8xx_fb_var.grayscale =
lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
/* Initialize fbinfo */
da8xx_fb_info->fix = da8xx_fb_fix;
da8xx_fb_info->var = da8xx_fb_var;
da8xx_fb_info->fbops = &da8xx_fb_ops;
da8xx_fb_info->pseudo_palette = par->pseudo_palette;
da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
if (ret)
goto err_disable_reg;
da8xx_fb_info->cmap.len = par->palette_sz;
/* initialize var_screeninfo */
da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
fb_set_var(da8xx_fb_info, &da8xx_fb_var);
platform_set_drvdata(device, da8xx_fb_info);
/* initialize the vsync wait queue */
init_waitqueue_head(&par->vsync_wait);
par->vsync_timeout = HZ / 5;
par->which_dma_channel_done = -1;
spin_lock_init(&par->lock_for_chan_update);
/* Register the Frame Buffer */
if (register_framebuffer(da8xx_fb_info) < 0) {
dev_err(&device->dev,
"GLCD: Frame Buffer Registration Failed!\n");
ret = -EINVAL;
goto err_dealloc_cmap;
}
#ifdef CONFIG_CPU_FREQ
ret = lcd_da8xx_cpufreq_register(par);
if (ret) {
dev_err(&device->dev, "failed to register cpufreq\n");
goto err_cpu_freq;
}
#endif
if (lcd_revision == LCD_VERSION_1)
lcdc_irq_handler = lcdc_irq_handler_rev01;
else {
init_waitqueue_head(&frame_done_wq);
lcdc_irq_handler = lcdc_irq_handler_rev02;
}
ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0,
DRIVER_NAME, par);
if (ret)
goto irq_freq;
return 0;
irq_freq:
#ifdef CONFIG_CPU_FREQ
lcd_da8xx_cpufreq_deregister(par);
err_cpu_freq:
#endif
unregister_framebuffer(da8xx_fb_info);
err_dealloc_cmap:
fb_dealloc_cmap(&da8xx_fb_info->cmap);
err_disable_reg:
if (par->lcd_supply)
regulator_disable(par->lcd_supply);
err_release_fb:
framebuffer_release(da8xx_fb_info);
err_pm_runtime_disable:
pm_runtime_put_sync(&device->dev);
pm_runtime_disable(&device->dev);
return ret;
}
#ifdef CONFIG_PM_SLEEP
static struct lcdc_context {
u32 clk_enable;
u32 ctrl;
u32 dma_ctrl;
u32 raster_timing_0;
u32 raster_timing_1;
u32 raster_timing_2;
u32 int_enable_set;
u32 dma_frm_buf_base_addr_0;
u32 dma_frm_buf_ceiling_addr_0;
u32 dma_frm_buf_base_addr_1;
u32 dma_frm_buf_ceiling_addr_1;
u32 raster_ctrl;
} reg_context;
static void lcd_context_save(void)
{
if (lcd_revision == LCD_VERSION_2) {
reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
}
reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
reg_context.dma_frm_buf_base_addr_0 =
lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
reg_context.dma_frm_buf_ceiling_addr_0 =
lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
reg_context.dma_frm_buf_base_addr_1 =
lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
reg_context.dma_frm_buf_ceiling_addr_1 =
lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
return;
}
static void lcd_context_restore(void)
{
if (lcd_revision == LCD_VERSION_2) {
lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
}
lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
lcdc_write(reg_context.dma_frm_buf_base_addr_0,
LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
lcdc_write(reg_context.dma_frm_buf_base_addr_1,
LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
return;
}
static int fb_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct da8xx_fb_par *par = info->par;
int ret;
console_lock();
if (par->lcd_supply) {
ret = regulator_disable(par->lcd_supply);
if (ret)
return ret;
}
fb_set_suspend(info, 1);
lcd_disable_raster(DA8XX_FRAME_WAIT);
lcd_context_save();
pm_runtime_put_sync(dev);
console_unlock();
return 0;
}
static int fb_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct da8xx_fb_par *par = info->par;
int ret;
console_lock();
pm_runtime_get_sync(dev);
lcd_context_restore();
if (par->blank == FB_BLANK_UNBLANK) {
lcd_enable_raster();
if (par->lcd_supply) {
ret = regulator_enable(par->lcd_supply);
if (ret)
return ret;
}
}
fb_set_suspend(info, 0);
console_unlock();
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(fb_pm_ops, fb_suspend, fb_resume);
static struct platform_driver da8xx_fb_driver = {
.probe = fb_probe,
.remove_new = fb_remove,
.driver = {
.name = DRIVER_NAME,
.pm = &fb_pm_ops,
},
};
module_platform_driver(da8xx_fb_driver);
MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
MODULE_AUTHOR("Texas Instruments");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/da8xx-fb.c |
/*
* linux/drivers/video/fm2fb.c -- BSC FrameMaster II/Rainbow II frame buffer
* device
*
* Copyright (C) 1998 Steffen A. Mork ([email protected])
* Copyright (C) 1999 Geert Uytterhoeven
*
* Written for 2.0.x by Steffen A. Mork
* Ported to 2.1.x by Geert Uytterhoeven
* Ported to new api by James Simmons
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/zorro.h>
#include <asm/io.h>
/*
* Some technical notes:
*
* The BSC FrameMaster II (or Rainbow II) is a simple very dumb
* frame buffer which allows to display 24 bit true color images.
* Each pixel is 32 bit width so it's very easy to maintain the
* frame buffer. One long word has the following layout:
* AARRGGBB which means: AA the alpha channel byte, RR the red
* channel, GG the green channel and BB the blue channel.
*
* The FrameMaster II supports the following video modes.
* - PAL/NTSC
* - interlaced/non interlaced
* - composite sync/sync/sync over green
*
* The resolution is to the following both ones:
* - 768x576 (PAL)
* - 768x480 (NTSC)
*
* This means that pixel access per line is fixed due to the
* fixed line width. In case of maximal resolution the frame
* buffer needs an amount of memory of 1.769.472 bytes which
* is near to 2 MByte (the allocated address space of Zorro2).
* The memory is channel interleaved. That means every channel
* owns four VRAMs. Unfortunately most FrameMasters II are
* not assembled with memory for the alpha channel. In this
* case it could be possible to add the frame buffer into the
* normal memory pool.
*
* At relative address 0x1ffff8 of the frame buffers base address
* there exists a control register with the number of
* four control bits. They have the following meaning:
* bit value meaning
*
* 0 1 0=interlaced/1=non interlaced
* 1 2 0=video out disabled/1=video out enabled
* 2 4 0=normal mode as jumpered via JP8/1=complement mode
* 3 8 0=read onboard ROM/1 normal operation (required)
*
* As mentioned above there are several jumper. I think there
* is not very much information about the FrameMaster II in
* the world so I add these information for completeness.
*
* JP1 interlace selection (1-2 non interlaced/2-3 interlaced)
* JP2 wait state creation (leave as is!)
* JP3 wait state creation (leave as is!)
* JP4 modulate composite sync on green output (1-2 composite
* sync on green channel/2-3 normal composite sync)
* JP5 create test signal, shorting this jumper will create
* a white screen
* JP6 sync creation (1-2 composite sync/2-3 H-sync output)
* JP8 video mode (1-2 PAL/2-3 NTSC)
*
* With the following jumpering table you can connect the
* FrameMaster II to a normal TV via SCART connector:
* JP1: 2-3
* JP4: 2-3
* JP6: 2-3
* JP8: 1-2 (means PAL for Europe)
*
* NOTE:
* There is no other possibility to change the video timings
* except the interlaced/non interlaced, sync control and the
* video mode PAL (50 Hz)/NTSC (60 Hz). Inside this
* FrameMaster II driver are assumed values to avoid anomalies
* to a future X server. Except the pixel clock is really
* constant at 30 MHz.
*
* 9 pin female video connector:
*
* 1 analog red 0.7 Vss
* 2 analog green 0.7 Vss
* 3 analog blue 0.7 Vss
* 4 H-sync TTL
* 5 V-sync TTL
* 6 ground
* 7 ground
* 8 ground
* 9 ground
*
* Some performance notes:
* The FrameMaster II was not designed to display a console
* this driver would do! It was designed to display still true
* color images. Imagine: When scroll up a text line there
* must copied ca. 1.7 MBytes to another place inside this
* frame buffer. This means 1.7 MByte read and 1.7 MByte write
* over the slow 16 bit wide Zorro2 bus! A scroll of one
* line needs 1 second so do not expect to much from this
* driver - he is at the limit!
*
*/
/*
* definitions
*/
#define FRAMEMASTER_SIZE 0x200000
#define FRAMEMASTER_REG 0x1ffff8
#define FRAMEMASTER_NOLACE 1
#define FRAMEMASTER_ENABLE 2
#define FRAMEMASTER_COMPL 4
#define FRAMEMASTER_ROM 8
static volatile unsigned char *fm2fb_reg;
static struct fb_fix_screeninfo fb_fix = {
.smem_len = FRAMEMASTER_REG,
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.line_length = (768 << 2),
.mmio_len = (8),
.accel = FB_ACCEL_NONE,
};
static int fm2fb_mode = -1;
#define FM2FB_MODE_PAL 0
#define FM2FB_MODE_NTSC 1
static struct fb_var_screeninfo fb_var_modes[] = {
{
/* 768 x 576, 32 bpp (PAL) */
768, 576, 768, 576, 0, 0, 32, 0,
{ 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 24, 8, 0 },
0, FB_ACTIVATE_NOW, -1, -1, FB_ACCEL_NONE,
33333, 10, 102, 10, 5, 80, 34, FB_SYNC_COMP_HIGH_ACT, 0
}, {
/* 768 x 480, 32 bpp (NTSC - not supported yet */
768, 480, 768, 480, 0, 0, 32, 0,
{ 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 24, 8, 0 },
0, FB_ACTIVATE_NOW, -1, -1, FB_ACCEL_NONE,
33333, 10, 102, 10, 5, 80, 34, FB_SYNC_COMP_HIGH_ACT, 0
}
};
/*
* Interface used by the world
*/
static int fm2fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int fm2fb_blank(int blank, struct fb_info *info);
static const struct fb_ops fm2fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = fm2fb_setcolreg,
.fb_blank = fm2fb_blank,
};
/*
* Blank the display.
*/
static int fm2fb_blank(int blank, struct fb_info *info)
{
unsigned char t = FRAMEMASTER_ROM;
if (!blank)
t |= FRAMEMASTER_ENABLE | FRAMEMASTER_NOLACE;
fm2fb_reg[0] = t;
return 0;
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int fm2fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
if (regno < 16) {
red >>= 8;
green >>= 8;
blue >>= 8;
((u32*)(info->pseudo_palette))[regno] = (red << 16) |
(green << 8) | blue;
}
return 0;
}
/*
* Initialisation
*/
static int fm2fb_probe(struct zorro_dev *z, const struct zorro_device_id *id);
static const struct zorro_device_id fm2fb_devices[] = {
{ ZORRO_PROD_BSC_FRAMEMASTER_II },
{ ZORRO_PROD_HELFRICH_RAINBOW_II },
{ 0 }
};
MODULE_DEVICE_TABLE(zorro, fm2fb_devices);
static struct zorro_driver fm2fb_driver = {
.name = "fm2fb",
.id_table = fm2fb_devices,
.probe = fm2fb_probe,
};
static int fm2fb_probe(struct zorro_dev *z, const struct zorro_device_id *id)
{
struct fb_info *info;
unsigned long *ptr;
int is_fm;
int x, y;
is_fm = z->id == ZORRO_PROD_BSC_FRAMEMASTER_II;
if (!zorro_request_device(z,"fm2fb"))
return -ENXIO;
info = framebuffer_alloc(16 * sizeof(u32), &z->dev);
if (!info) {
zorro_release_device(z);
return -ENOMEM;
}
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
framebuffer_release(info);
zorro_release_device(z);
return -ENOMEM;
}
/* assigning memory to kernel space */
fb_fix.smem_start = zorro_resource_start(z);
info->screen_base = ioremap(fb_fix.smem_start, FRAMEMASTER_SIZE);
fb_fix.mmio_start = fb_fix.smem_start + FRAMEMASTER_REG;
fm2fb_reg = (unsigned char *)(info->screen_base+FRAMEMASTER_REG);
strcpy(fb_fix.id, is_fm ? "FrameMaster II" : "Rainbow II");
/* make EBU color bars on display */
ptr = (unsigned long *)fb_fix.smem_start;
for (y = 0; y < 576; y++) {
for (x = 0; x < 96; x++) *ptr++ = 0xffffff;/* white */
for (x = 0; x < 96; x++) *ptr++ = 0xffff00;/* yellow */
for (x = 0; x < 96; x++) *ptr++ = 0x00ffff;/* cyan */
for (x = 0; x < 96; x++) *ptr++ = 0x00ff00;/* green */
for (x = 0; x < 96; x++) *ptr++ = 0xff00ff;/* magenta */
for (x = 0; x < 96; x++) *ptr++ = 0xff0000;/* red */
for (x = 0; x < 96; x++) *ptr++ = 0x0000ff;/* blue */
for (x = 0; x < 96; x++) *ptr++ = 0x000000;/* black */
}
fm2fb_blank(0, info);
if (fm2fb_mode == -1)
fm2fb_mode = FM2FB_MODE_PAL;
info->fbops = &fm2fb_ops;
info->var = fb_var_modes[fm2fb_mode];
info->pseudo_palette = info->par;
info->par = NULL;
info->fix = fb_fix;
if (register_framebuffer(info) < 0) {
fb_dealloc_cmap(&info->cmap);
iounmap(info->screen_base);
framebuffer_release(info);
zorro_release_device(z);
return -EINVAL;
}
fb_info(info, "%s frame buffer device\n", fb_fix.id);
return 0;
}
static int __init fm2fb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "pal", 3))
fm2fb_mode = FM2FB_MODE_PAL;
else if (!strncmp(this_opt, "ntsc", 4))
fm2fb_mode = FM2FB_MODE_NTSC;
}
return 0;
}
static int __init fm2fb_init(void)
{
char *option = NULL;
if (fb_get_options("fm2fb", &option))
return -ENODEV;
fm2fb_setup(option);
return zorro_register_driver(&fm2fb_driver);
}
module_init(fm2fb_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/fm2fb.c |
/*
* linux/drivers/video/stifb.c -
* Low level Frame buffer driver for HP workstations with
* STI (standard text interface) video firmware.
*
* Copyright (C) 2001-2006 Helge Deller <[email protected]>
* Portions Copyright (C) 2001 Thomas Bogendoerfer <[email protected]>
*
* Based on:
* - linux/drivers/video/artistfb.c -- Artist frame buffer driver
* Copyright (C) 2000 Philipp Rumpf <[email protected]>
* - based on skeletonfb, which was
* Created 28 Dec 1997 by Geert Uytterhoeven
* - HP Xhp cfb-based X11 window driver for XFree86
* (c)Copyright 1992 Hewlett-Packard Co.
*
*
* The following graphics display devices (NGLE family) are supported by this driver:
*
* HPA4070A known as "HCRX", a 1280x1024 color device with 8 planes
* HPA4071A known as "HCRX24", a 1280x1024 color device with 24 planes,
* optionally available with a hardware accelerator as HPA4071A_Z
* HPA1659A known as "CRX", a 1280x1024 color device with 8 planes
* HPA1439A known as "CRX24", a 1280x1024 color device with 24 planes,
* optionally available with a hardware accelerator.
* HPA1924A known as "GRX", a 1280x1024 grayscale device with 8 planes
* HPA2269A known as "Dual CRX", a 1280x1024 color device with 8 planes,
* implements support for two displays on a single graphics card.
* HP710C internal graphics support optionally available on the HP9000s710 SPU,
* supports 1280x1024 color displays with 8 planes.
* HP710G same as HP710C, 1280x1024 grayscale only
* HP710L same as HP710C, 1024x768 color only
* HP712 internal graphics support on HP9000s712 SPU, supports 640x480,
* 1024x768 or 1280x1024 color displays on 8 planes (Artist)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
/* TODO:
* - 1bpp mode is completely untested
* - add support for h/w acceleration
* - add hardware cursor
* - automatically disable double buffering (e.g. on RDI precisionbook laptop)
*/
/* on supported graphic devices you may:
* #define FALLBACK_TO_1BPP to fall back to 1 bpp, or
* #undef FALLBACK_TO_1BPP to reject support for unsupported cards */
#undef FALLBACK_TO_1BPP
#undef DEBUG_STIFB_REGS /* debug sti register accesses */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <asm/grfioctl.h> /* for HP-UX compatibility */
#include <linux/uaccess.h>
#include <video/sticore.h>
/* REGION_BASE(fb_info, index) returns the physical address for region <index> */
#define REGION_BASE(fb_info, index) \
F_EXTEND(fb_info->sti->regions_phys[index])
#define NGLEDEVDEPROM_CRT_REGION 1
#define NR_PALETTE 256
typedef struct {
__s32 video_config_reg;
__s32 misc_video_start;
__s32 horiz_timing_fmt;
__s32 serr_timing_fmt;
__s32 vert_timing_fmt;
__s32 horiz_state;
__s32 vert_state;
__s32 vtg_state_elements;
__s32 pipeline_delay;
__s32 misc_video_end;
} video_setup_t;
typedef struct {
__s16 sizeof_ngle_data;
__s16 x_size_visible; /* visible screen dim in pixels */
__s16 y_size_visible;
__s16 pad2[15];
__s16 cursor_pipeline_delay;
__s16 video_interleaves;
__s32 pad3[11];
} ngle_rom_t;
struct stifb_info {
struct fb_info info;
unsigned int id;
ngle_rom_t ngle_rom;
struct sti_struct *sti;
int deviceSpecificConfig;
u32 pseudo_palette[16];
};
static int __initdata stifb_bpp_pref[MAX_STI_ROMS];
/* ------------------- chipset specific functions -------------------------- */
/* offsets to graphic-chip internal registers */
#define REG_1 0x000118
#define REG_2 0x000480
#define REG_3 0x0004a0
#define REG_4 0x000600
#define REG_6 0x000800
#define REG_7 0x000804
#define REG_8 0x000820
#define REG_9 0x000a04
#define REG_10 0x018000
#define REG_11 0x018004
#define REG_12 0x01800c
#define REG_13 0x018018
#define REG_14 0x01801c
#define REG_15 0x200000
#define REG_15b0 0x200000
#define REG_16b1 0x200005
#define REG_16b3 0x200007
#define REG_21 0x200218
#define REG_22 0x0005a0
#define REG_23 0x0005c0
#define REG_24 0x000808
#define REG_25 0x000b00
#define REG_26 0x200118
#define REG_27 0x200308
#define REG_32 0x21003c
#define REG_33 0x210040
#define REG_34 0x200008
#define REG_35 0x018010
#define REG_38 0x210020
#define REG_39 0x210120
#define REG_40 0x210130
#define REG_42 0x210028
#define REG_43 0x21002c
#define REG_44 0x210030
#define REG_45 0x210034
#define READ_BYTE(fb,reg) gsc_readb((fb)->info.fix.mmio_start + (reg))
#define READ_WORD(fb,reg) gsc_readl((fb)->info.fix.mmio_start + (reg))
#ifndef DEBUG_STIFB_REGS
# define DEBUG_OFF()
# define DEBUG_ON()
# define WRITE_BYTE(value,fb,reg) gsc_writeb((value),(fb)->info.fix.mmio_start + (reg))
# define WRITE_WORD(value,fb,reg) gsc_writel((value),(fb)->info.fix.mmio_start + (reg))
#else
static int debug_on = 1;
# define DEBUG_OFF() debug_on=0
# define DEBUG_ON() debug_on=1
# define WRITE_BYTE(value,fb,reg) do { if (debug_on) \
printk(KERN_DEBUG "%30s: WRITE_BYTE(0x%06x) = 0x%02x (old=0x%02x)\n", \
__func__, reg, value, READ_BYTE(fb,reg)); \
gsc_writeb((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
# define WRITE_WORD(value,fb,reg) do { if (debug_on) \
printk(KERN_DEBUG "%30s: WRITE_WORD(0x%06x) = 0x%08x (old=0x%08x)\n", \
__func__, reg, value, READ_WORD(fb,reg)); \
gsc_writel((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
#endif /* DEBUG_STIFB_REGS */
#define ENABLE 1 /* for enabling/disabling screen */
#define DISABLE 0
#define NGLE_LOCK(fb_info) do { } while (0)
#define NGLE_UNLOCK(fb_info) do { } while (0)
static void
SETUP_HW(struct stifb_info *fb)
{
char stat;
do {
stat = READ_BYTE(fb, REG_15b0);
if (!stat)
stat = READ_BYTE(fb, REG_15b0);
} while (stat);
}
static void
SETUP_FB(struct stifb_info *fb)
{
unsigned int reg10_value = 0;
SETUP_HW(fb);
switch (fb->id)
{
case CRT_ID_VISUALIZE_EG:
case S9000_ID_ARTIST:
case S9000_ID_A1659A:
reg10_value = 0x13601000;
break;
case S9000_ID_A1439A:
if (fb->info.var.bits_per_pixel == 32)
reg10_value = 0xBBA0A000;
else
reg10_value = 0x13601000;
break;
case S9000_ID_HCRX:
if (fb->info.var.bits_per_pixel == 32)
reg10_value = 0xBBA0A000;
else
reg10_value = 0x13602000;
break;
case S9000_ID_TIMBER:
case CRX24_OVERLAY_PLANES:
reg10_value = 0x13602000;
break;
}
if (reg10_value)
WRITE_WORD(reg10_value, fb, REG_10);
WRITE_WORD(0x83000300, fb, REG_14);
SETUP_HW(fb);
WRITE_BYTE(1, fb, REG_16b1);
}
static void
START_IMAGE_COLORMAP_ACCESS(struct stifb_info *fb)
{
SETUP_HW(fb);
WRITE_WORD(0xBBE0F000, fb, REG_10);
WRITE_WORD(0x03000300, fb, REG_14);
WRITE_WORD(~0, fb, REG_13);
}
static void
WRITE_IMAGE_COLOR(struct stifb_info *fb, int index, int color)
{
SETUP_HW(fb);
WRITE_WORD(((0x100+index)<<2), fb, REG_3);
WRITE_WORD(color, fb, REG_4);
}
static void
FINISH_IMAGE_COLORMAP_ACCESS(struct stifb_info *fb)
{
WRITE_WORD(0x400, fb, REG_2);
if (fb->info.var.bits_per_pixel == 32) {
WRITE_WORD(0x83000100, fb, REG_1);
} else {
if (fb->id == S9000_ID_ARTIST || fb->id == CRT_ID_VISUALIZE_EG)
WRITE_WORD(0x80000100, fb, REG_26);
else
WRITE_WORD(0x80000100, fb, REG_1);
}
SETUP_FB(fb);
}
static void
SETUP_RAMDAC(struct stifb_info *fb)
{
SETUP_HW(fb);
WRITE_WORD(0x04000000, fb, 0x1020);
WRITE_WORD(0xff000000, fb, 0x1028);
}
static void
CRX24_SETUP_RAMDAC(struct stifb_info *fb)
{
SETUP_HW(fb);
WRITE_WORD(0x04000000, fb, 0x1000);
WRITE_WORD(0x02000000, fb, 0x1004);
WRITE_WORD(0xff000000, fb, 0x1008);
WRITE_WORD(0x05000000, fb, 0x1000);
WRITE_WORD(0x02000000, fb, 0x1004);
WRITE_WORD(0x03000000, fb, 0x1008);
}
#if 0
static void
HCRX_SETUP_RAMDAC(struct stifb_info *fb)
{
WRITE_WORD(0xffffffff, fb, REG_32);
}
#endif
static void
CRX24_SET_OVLY_MASK(struct stifb_info *fb)
{
SETUP_HW(fb);
WRITE_WORD(0x13a02000, fb, REG_11);
WRITE_WORD(0x03000300, fb, REG_14);
WRITE_WORD(0x000017f0, fb, REG_3);
WRITE_WORD(0xffffffff, fb, REG_13);
WRITE_WORD(0xffffffff, fb, REG_22);
WRITE_WORD(0x00000000, fb, REG_23);
}
static void
ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
{
unsigned int value = enable ? 0x43000000 : 0x03000000;
SETUP_HW(fb);
WRITE_WORD(0x06000000, fb, 0x1030);
WRITE_WORD(value, fb, 0x1038);
}
static void
CRX24_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
{
unsigned int value = enable ? 0x10000000 : 0x30000000;
SETUP_HW(fb);
WRITE_WORD(0x01000000, fb, 0x1000);
WRITE_WORD(0x02000000, fb, 0x1004);
WRITE_WORD(value, fb, 0x1008);
}
static void
ARTIST_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
{
u32 DregsMiscVideo = REG_21;
u32 DregsMiscCtl = REG_27;
SETUP_HW(fb);
if (enable) {
WRITE_WORD(READ_WORD(fb, DregsMiscVideo) | 0x0A000000, fb, DregsMiscVideo);
WRITE_WORD(READ_WORD(fb, DregsMiscCtl) | 0x00800000, fb, DregsMiscCtl);
} else {
WRITE_WORD(READ_WORD(fb, DregsMiscVideo) & ~0x0A000000, fb, DregsMiscVideo);
WRITE_WORD(READ_WORD(fb, DregsMiscCtl) & ~0x00800000, fb, DregsMiscCtl);
}
}
#define GET_ROMTABLE_INDEX(fb) \
(READ_BYTE(fb, REG_16b3) - 1)
#define HYPER_CONFIG_PLANES_24 0x00000100
#define IS_24_DEVICE(fb) \
(fb->deviceSpecificConfig & HYPER_CONFIG_PLANES_24)
#define IS_888_DEVICE(fb) \
(!(IS_24_DEVICE(fb)))
#define GET_FIFO_SLOTS(fb, cnt, numslots) \
{ while (cnt < numslots) \
cnt = READ_WORD(fb, REG_34); \
cnt -= numslots; \
}
#define IndexedDcd 0 /* Pixel data is indexed (pseudo) color */
#define Otc04 2 /* Pixels in each longword transfer (4) */
#define Otc32 5 /* Pixels in each longword transfer (32) */
#define Ots08 3 /* Each pixel is size (8)d transfer (1) */
#define OtsIndirect 6 /* Each bit goes through FG/BG color(8) */
#define AddrLong 5 /* FB address is Long aligned (pixel) */
#define BINovly 0x2 /* 8 bit overlay */
#define BINapp0I 0x0 /* Application Buffer 0, Indexed */
#define BINapp1I 0x1 /* Application Buffer 1, Indexed */
#define BINapp0F8 0xa /* Application Buffer 0, Fractional 8-8-8 */
#define BINattr 0xd /* Attribute Bitmap */
#define RopSrc 0x3
#define BitmapExtent08 3 /* Each write hits ( 8) bits in depth */
#define BitmapExtent32 5 /* Each write hits (32) bits in depth */
#define DataDynamic 0 /* Data register reloaded by direct access */
#define MaskDynamic 1 /* Mask register reloaded by direct access */
#define MaskOtc 0 /* Mask contains Object Count valid bits */
#define MaskAddrOffset(offset) (offset)
#define StaticReg(en) (en)
#define BGx(en) (en)
#define FGx(en) (en)
#define BAJustPoint(offset) (offset)
#define BAIndexBase(base) (base)
#define BA(F,C,S,A,J,B,I) \
(((F)<<31)|((C)<<27)|((S)<<24)|((A)<<21)|((J)<<16)|((B)<<12)|(I))
#define IBOvals(R,M,X,S,D,L,B,F) \
(((R)<<8)|((M)<<16)|((X)<<24)|((S)<<29)|((D)<<28)|((L)<<31)|((B)<<1)|(F))
#define NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb, val) \
WRITE_WORD(val, fb, REG_14)
#define NGLE_QUICK_SET_DST_BM_ACCESS(fb, val) \
WRITE_WORD(val, fb, REG_11)
#define NGLE_QUICK_SET_CTL_PLN_REG(fb, val) \
WRITE_WORD(val, fb, REG_12)
#define NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, plnmsk32) \
WRITE_WORD(plnmsk32, fb, REG_13)
#define NGLE_REALLY_SET_IMAGE_FG_COLOR(fb, fg32) \
WRITE_WORD(fg32, fb, REG_35)
#define NGLE_SET_TRANSFERDATA(fb, val) \
WRITE_WORD(val, fb, REG_8)
#define NGLE_SET_DSTXY(fb, val) \
WRITE_WORD(val, fb, REG_6)
#define NGLE_LONG_FB_ADDRESS(fbaddrbase, x, y) ( \
(u32) (fbaddrbase) + \
( (unsigned int) ( (y) << 13 ) | \
(unsigned int) ( (x) << 2 ) ) \
)
#define NGLE_BINC_SET_DSTADDR(fb, addr) \
WRITE_WORD(addr, fb, REG_3)
#define NGLE_BINC_SET_SRCADDR(fb, addr) \
WRITE_WORD(addr, fb, REG_2)
#define NGLE_BINC_SET_DSTMASK(fb, mask) \
WRITE_WORD(mask, fb, REG_22)
#define NGLE_BINC_WRITE32(fb, data32) \
WRITE_WORD(data32, fb, REG_23)
#define START_COLORMAPLOAD(fb, cmapBltCtlData32) \
WRITE_WORD((cmapBltCtlData32), fb, REG_38)
#define SET_LENXY_START_RECFILL(fb, lenxy) \
WRITE_WORD(lenxy, fb, REG_9)
#define SETUP_COPYAREA(fb) \
WRITE_BYTE(0, fb, REG_16b1)
static void
HYPER_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
{
u32 DregsHypMiscVideo = REG_33;
unsigned int value;
SETUP_HW(fb);
value = READ_WORD(fb, DregsHypMiscVideo);
if (enable)
value |= 0x0A000000;
else
value &= ~0x0A000000;
WRITE_WORD(value, fb, DregsHypMiscVideo);
}
/* BufferNumbers used by SETUP_ATTR_ACCESS() */
#define BUFF0_CMAP0 0x00001e02
#define BUFF1_CMAP0 0x02001e02
#define BUFF1_CMAP3 0x0c001e02
#define ARTIST_CMAP0 0x00000102
#define HYPER_CMAP8 0x00000100
#define HYPER_CMAP24 0x00000800
static void
SETUP_ATTR_ACCESS(struct stifb_info *fb, unsigned BufferNumber)
{
SETUP_HW(fb);
WRITE_WORD(0x2EA0D000, fb, REG_11);
WRITE_WORD(0x23000302, fb, REG_14);
WRITE_WORD(BufferNumber, fb, REG_12);
WRITE_WORD(0xffffffff, fb, REG_8);
}
static void
SET_ATTR_SIZE(struct stifb_info *fb, int width, int height)
{
/* REG_6 seems to have special values when run on a
RDI precisionbook parisc laptop (INTERNAL_EG_DX1024 or
INTERNAL_EG_X1024). The values are:
0x2f0: internal (LCD) & external display enabled
0x2a0: external display only
0x000: zero on standard artist graphic cards
*/
WRITE_WORD(0x00000000, fb, REG_6);
WRITE_WORD((width<<16) | height, fb, REG_9);
WRITE_WORD(0x05000000, fb, REG_6);
WRITE_WORD(0x00040001, fb, REG_9);
}
static void
FINISH_ATTR_ACCESS(struct stifb_info *fb)
{
SETUP_HW(fb);
WRITE_WORD(0x00000000, fb, REG_12);
}
static void
elkSetupPlanes(struct stifb_info *fb)
{
SETUP_RAMDAC(fb);
SETUP_FB(fb);
}
static void
ngleSetupAttrPlanes(struct stifb_info *fb, int BufferNumber)
{
SETUP_ATTR_ACCESS(fb, BufferNumber);
SET_ATTR_SIZE(fb, fb->info.var.xres, fb->info.var.yres);
FINISH_ATTR_ACCESS(fb);
SETUP_FB(fb);
}
static void
rattlerSetupPlanes(struct stifb_info *fb)
{
int saved_id, y;
/* Write RAMDAC pixel read mask register so all overlay
* planes are display-enabled. (CRX24 uses Bt462 pixel
* read mask register for overlay planes, not image planes).
*/
CRX24_SETUP_RAMDAC(fb);
/* change fb->id temporarily to fool SETUP_FB() */
saved_id = fb->id;
fb->id = CRX24_OVERLAY_PLANES;
SETUP_FB(fb);
fb->id = saved_id;
for (y = 0; y < fb->info.var.yres; ++y)
fb_memset_io(fb->info.screen_base + y * fb->info.fix.line_length,
0xff, fb->info.var.xres * fb->info.var.bits_per_pixel/8);
CRX24_SET_OVLY_MASK(fb);
SETUP_FB(fb);
}
#define HYPER_CMAP_TYPE 0
#define NGLE_CMAP_INDEXED0_TYPE 0
#define NGLE_CMAP_OVERLAY_TYPE 3
/* typedef of LUT (Colormap) BLT Control Register */
typedef union /* Note assumption that fields are packed left-to-right */
{ u32 all;
struct
{
unsigned enable : 1;
unsigned waitBlank : 1;
unsigned reserved1 : 4;
unsigned lutOffset : 10; /* Within destination LUT */
unsigned lutType : 2; /* Cursor, image, overlay */
unsigned reserved2 : 4;
unsigned length : 10;
} fields;
} NgleLutBltCtl;
#if 0
static NgleLutBltCtl
setNgleLutBltCtl(struct stifb_info *fb, int offsetWithinLut, int length)
{
NgleLutBltCtl lutBltCtl;
/* set enable, zero reserved fields */
lutBltCtl.all = 0x80000000;
lutBltCtl.fields.length = length;
switch (fb->id)
{
case S9000_ID_A1439A: /* CRX24 */
if (fb->var.bits_per_pixel == 8) {
lutBltCtl.fields.lutType = NGLE_CMAP_OVERLAY_TYPE;
lutBltCtl.fields.lutOffset = 0;
} else {
lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
lutBltCtl.fields.lutOffset = 0 * 256;
}
break;
case S9000_ID_ARTIST:
lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
lutBltCtl.fields.lutOffset = 0 * 256;
break;
default:
lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
lutBltCtl.fields.lutOffset = 0;
break;
}
/* Offset points to start of LUT. Adjust for within LUT */
lutBltCtl.fields.lutOffset += offsetWithinLut;
return lutBltCtl;
}
#endif
static NgleLutBltCtl
setHyperLutBltCtl(struct stifb_info *fb, int offsetWithinLut, int length)
{
NgleLutBltCtl lutBltCtl;
/* set enable, zero reserved fields */
lutBltCtl.all = 0x80000000;
lutBltCtl.fields.length = length;
lutBltCtl.fields.lutType = HYPER_CMAP_TYPE;
/* Expect lutIndex to be 0 or 1 for image cmaps, 2 or 3 for overlay cmaps */
if (fb->info.var.bits_per_pixel == 8)
lutBltCtl.fields.lutOffset = 2 * 256;
else
lutBltCtl.fields.lutOffset = 0 * 256;
/* Offset points to start of LUT. Adjust for within LUT */
lutBltCtl.fields.lutOffset += offsetWithinLut;
return lutBltCtl;
}
static void hyperUndoITE(struct stifb_info *fb)
{
int nFreeFifoSlots = 0;
u32 fbAddr;
NGLE_LOCK(fb);
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 1);
WRITE_WORD(0xffffffff, fb, REG_32);
/* Write overlay transparency mask so only entry 255 is transparent */
/* Hardware setup for full-depth write to "magic" location */
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 7);
NGLE_QUICK_SET_DST_BM_ACCESS(fb,
BA(IndexedDcd, Otc04, Ots08, AddrLong,
BAJustPoint(0), BINovly, BAIndexBase(0)));
NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
IBOvals(RopSrc, MaskAddrOffset(0),
BitmapExtent08, StaticReg(0),
DataDynamic, MaskOtc, BGx(0), FGx(0)));
/* Now prepare to write to the "magic" location */
fbAddr = NGLE_LONG_FB_ADDRESS(0, 1532, 0);
NGLE_BINC_SET_DSTADDR(fb, fbAddr);
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffff);
NGLE_BINC_SET_DSTMASK(fb, 0xffffffff);
/* Finally, write a zero to clear the mask */
NGLE_BINC_WRITE32(fb, 0);
NGLE_UNLOCK(fb);
}
static void
ngleDepth8_ClearImagePlanes(struct stifb_info *fb)
{
/* FIXME! */
}
static void
ngleDepth24_ClearImagePlanes(struct stifb_info *fb)
{
/* FIXME! */
}
static void
ngleResetAttrPlanes(struct stifb_info *fb, unsigned int ctlPlaneReg)
{
int nFreeFifoSlots = 0;
u32 packed_dst;
u32 packed_len;
NGLE_LOCK(fb);
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 4);
NGLE_QUICK_SET_DST_BM_ACCESS(fb,
BA(IndexedDcd, Otc32, OtsIndirect,
AddrLong, BAJustPoint(0),
BINattr, BAIndexBase(0)));
NGLE_QUICK_SET_CTL_PLN_REG(fb, ctlPlaneReg);
NGLE_SET_TRANSFERDATA(fb, 0xffffffff);
NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
IBOvals(RopSrc, MaskAddrOffset(0),
BitmapExtent08, StaticReg(1),
DataDynamic, MaskOtc,
BGx(0), FGx(0)));
packed_dst = 0;
packed_len = (fb->info.var.xres << 16) | fb->info.var.yres;
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 2);
NGLE_SET_DSTXY(fb, packed_dst);
SET_LENXY_START_RECFILL(fb, packed_len);
/*
* In order to work around an ELK hardware problem (Buffy doesn't
* always flush it's buffers when writing to the attribute
* planes), at least 4 pixels must be written to the attribute
* planes starting at (X == 1280) and (Y != to the last Y written
* by BIF):
*/
if (fb->id == S9000_ID_A1659A) { /* ELK_DEVICE_ID */
/* It's safe to use scanline zero: */
packed_dst = (1280 << 16);
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 2);
NGLE_SET_DSTXY(fb, packed_dst);
packed_len = (4 << 16) | 1;
SET_LENXY_START_RECFILL(fb, packed_len);
} /* ELK Hardware Kludge */
/**** Finally, set the Control Plane Register back to zero: ****/
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 1);
NGLE_QUICK_SET_CTL_PLN_REG(fb, 0);
NGLE_UNLOCK(fb);
}
static void
ngleClearOverlayPlanes(struct stifb_info *fb, int mask, int data)
{
int nFreeFifoSlots = 0;
u32 packed_dst;
u32 packed_len;
NGLE_LOCK(fb);
/* Hardware setup */
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 8);
NGLE_QUICK_SET_DST_BM_ACCESS(fb,
BA(IndexedDcd, Otc04, Ots08, AddrLong,
BAJustPoint(0), BINovly, BAIndexBase(0)));
NGLE_SET_TRANSFERDATA(fb, 0xffffffff); /* Write foreground color */
NGLE_REALLY_SET_IMAGE_FG_COLOR(fb, data);
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, mask);
packed_dst = 0;
packed_len = (fb->info.var.xres << 16) | fb->info.var.yres;
NGLE_SET_DSTXY(fb, packed_dst);
/* Write zeroes to overlay planes */
NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
IBOvals(RopSrc, MaskAddrOffset(0),
BitmapExtent08, StaticReg(0),
DataDynamic, MaskOtc, BGx(0), FGx(0)));
SET_LENXY_START_RECFILL(fb, packed_len);
NGLE_UNLOCK(fb);
}
static void
hyperResetPlanes(struct stifb_info *fb, int enable)
{
unsigned int controlPlaneReg;
NGLE_LOCK(fb);
if (IS_24_DEVICE(fb))
if (fb->info.var.bits_per_pixel == 32)
controlPlaneReg = 0x04000F00;
else
controlPlaneReg = 0x00000F00; /* 0x00000800 should be enough, but lets clear all 4 bits */
else
controlPlaneReg = 0x00000F00; /* 0x00000100 should be enough, but lets clear all 4 bits */
switch (enable) {
case ENABLE:
/* clear screen */
if (IS_24_DEVICE(fb))
ngleDepth24_ClearImagePlanes(fb);
else
ngleDepth8_ClearImagePlanes(fb);
/* Paint attribute planes for default case.
* On Hyperdrive, this means all windows using overlay cmap 0. */
ngleResetAttrPlanes(fb, controlPlaneReg);
/* clear overlay planes */
ngleClearOverlayPlanes(fb, 0xff, 255);
/**************************************************
** Also need to counteract ITE settings
**************************************************/
hyperUndoITE(fb);
break;
case DISABLE:
/* clear screen */
if (IS_24_DEVICE(fb))
ngleDepth24_ClearImagePlanes(fb);
else
ngleDepth8_ClearImagePlanes(fb);
ngleResetAttrPlanes(fb, controlPlaneReg);
ngleClearOverlayPlanes(fb, 0xff, 0);
break;
case -1: /* RESET */
hyperUndoITE(fb);
ngleResetAttrPlanes(fb, controlPlaneReg);
break;
}
NGLE_UNLOCK(fb);
}
/* Return pointer to in-memory structure holding ELK device-dependent ROM values. */
static void
ngleGetDeviceRomData(struct stifb_info *fb)
{
#if 0
XXX: FIXME: !!!
int *pBytePerLongDevDepData;/* data byte == LSB */
int *pRomTable;
NgleDevRomData *pPackedDevRomData;
int sizePackedDevRomData = sizeof(*pPackedDevRomData);
char *pCard8;
int i;
char *mapOrigin = NULL;
int romTableIdx;
pPackedDevRomData = fb->ngle_rom;
SETUP_HW(fb);
if (fb->id == S9000_ID_ARTIST) {
pPackedDevRomData->cursor_pipeline_delay = 4;
pPackedDevRomData->video_interleaves = 4;
} else {
/* Get pointer to unpacked byte/long data in ROM */
pBytePerLongDevDepData = fb->sti->regions[NGLEDEVDEPROM_CRT_REGION];
/* Tomcat supports several resolutions: 1280x1024, 1024x768, 640x480 */
if (fb->id == S9000_ID_TOMCAT)
{
/* jump to the correct ROM table */
GET_ROMTABLE_INDEX(romTableIdx);
while (romTableIdx > 0)
{
pCard8 = (Card8 *) pPackedDevRomData;
pRomTable = pBytePerLongDevDepData;
/* Pack every fourth byte from ROM into structure */
for (i = 0; i < sizePackedDevRomData; i++)
{
*pCard8++ = (Card8) (*pRomTable++);
}
pBytePerLongDevDepData = (Card32 *)
((Card8 *) pBytePerLongDevDepData +
pPackedDevRomData->sizeof_ngle_data);
romTableIdx--;
}
}
pCard8 = (Card8 *) pPackedDevRomData;
/* Pack every fourth byte from ROM into structure */
for (i = 0; i < sizePackedDevRomData; i++)
{
*pCard8++ = (Card8) (*pBytePerLongDevDepData++);
}
}
SETUP_FB(fb);
#endif
}
#define HYPERBOWL_MODE_FOR_8_OVER_88_LUT0_NO_TRANSPARENCIES 4
#define HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE 8
#define HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE 10
#define HYPERBOWL_MODE2_8_24 15
/* HCRX specific boot-time initialization */
static void __init
SETUP_HCRX(struct stifb_info *fb)
{
int hyperbowl;
int nFreeFifoSlots = 0;
if (fb->id != S9000_ID_HCRX)
return;
/* Initialize Hyperbowl registers */
GET_FIFO_SLOTS(fb, nFreeFifoSlots, 7);
if (IS_24_DEVICE(fb)) {
hyperbowl = (fb->info.var.bits_per_pixel == 32) ?
HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE :
HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE;
/* First write to Hyperbowl must happen twice (bug) */
WRITE_WORD(hyperbowl, fb, REG_40);
WRITE_WORD(hyperbowl, fb, REG_40);
WRITE_WORD(HYPERBOWL_MODE2_8_24, fb, REG_39);
WRITE_WORD(0x014c0148, fb, REG_42); /* Set lut 0 to be the direct color */
WRITE_WORD(0x404c4048, fb, REG_43);
WRITE_WORD(0x034c0348, fb, REG_44);
WRITE_WORD(0x444c4448, fb, REG_45);
} else {
hyperbowl = HYPERBOWL_MODE_FOR_8_OVER_88_LUT0_NO_TRANSPARENCIES;
/* First write to Hyperbowl must happen twice (bug) */
WRITE_WORD(hyperbowl, fb, REG_40);
WRITE_WORD(hyperbowl, fb, REG_40);
WRITE_WORD(0x00000000, fb, REG_42);
WRITE_WORD(0x00000000, fb, REG_43);
WRITE_WORD(0x00000000, fb, REG_44);
WRITE_WORD(0x444c4048, fb, REG_45);
}
}
/* ------------------- driver specific functions --------------------------- */
static int
stifb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct stifb_info *fb = container_of(info, struct stifb_info, info);
if (var->xres != fb->info.var.xres ||
var->yres != fb->info.var.yres ||
var->bits_per_pixel != fb->info.var.bits_per_pixel)
return -EINVAL;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->xoffset = 0;
var->yoffset = 0;
var->grayscale = fb->info.var.grayscale;
var->red.length = fb->info.var.red.length;
var->green.length = fb->info.var.green.length;
var->blue.length = fb->info.var.blue.length;
return 0;
}
static int
stifb_setcolreg(u_int regno, u_int red, u_int green,
u_int blue, u_int transp, struct fb_info *info)
{
struct stifb_info *fb = container_of(info, struct stifb_info, info);
u32 color;
if (regno >= NR_PALETTE)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
DEBUG_OFF();
START_IMAGE_COLORMAP_ACCESS(fb);
if (unlikely(fb->info.var.grayscale)) {
/* gray = 0.30*R + 0.59*G + 0.11*B */
color = ((red * 77) +
(green * 151) +
(blue * 28)) >> 8;
} else {
color = ((red << 16) |
(green << 8) |
(blue));
}
if (fb->info.fix.visual == FB_VISUAL_DIRECTCOLOR) {
struct fb_var_screeninfo *var = &fb->info.var;
if (regno < 16)
((u32 *)fb->info.pseudo_palette)[regno] =
regno << var->red.offset |
regno << var->green.offset |
regno << var->blue.offset;
}
WRITE_IMAGE_COLOR(fb, regno, color);
if (fb->id == S9000_ID_HCRX) {
NgleLutBltCtl lutBltCtl;
lutBltCtl = setHyperLutBltCtl(fb,
0, /* Offset w/i LUT */
256); /* Load entire LUT */
NGLE_BINC_SET_SRCADDR(fb,
NGLE_LONG_FB_ADDRESS(0, 0x100, 0));
/* 0x100 is same as used in WRITE_IMAGE_COLOR() */
START_COLORMAPLOAD(fb, lutBltCtl.all);
SETUP_FB(fb);
} else {
/* cleanup colormap hardware */
FINISH_IMAGE_COLORMAP_ACCESS(fb);
}
DEBUG_ON();
return 0;
}
static int
stifb_blank(int blank_mode, struct fb_info *info)
{
struct stifb_info *fb = container_of(info, struct stifb_info, info);
int enable = (blank_mode == 0) ? ENABLE : DISABLE;
switch (fb->id) {
case S9000_ID_A1439A:
CRX24_ENABLE_DISABLE_DISPLAY(fb, enable);
break;
case CRT_ID_VISUALIZE_EG:
case S9000_ID_ARTIST:
ARTIST_ENABLE_DISABLE_DISPLAY(fb, enable);
break;
case S9000_ID_HCRX:
HYPER_ENABLE_DISABLE_DISPLAY(fb, enable);
break;
case S9000_ID_A1659A:
case S9000_ID_TIMBER:
case CRX24_OVERLAY_PLANES:
default:
ENABLE_DISABLE_DISPLAY(fb, enable);
break;
}
SETUP_FB(fb);
return 0;
}
static void
stifb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct stifb_info *fb = container_of(info, struct stifb_info, info);
SETUP_COPYAREA(fb);
SETUP_HW(fb);
if (fb->info.var.bits_per_pixel == 32) {
WRITE_WORD(0xBBA0A000, fb, REG_10);
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffffff);
} else {
WRITE_WORD(fb->id == S9000_ID_HCRX ? 0x13a02000 : 0x13a01000, fb, REG_10);
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xff);
}
NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
IBOvals(RopSrc, MaskAddrOffset(0),
BitmapExtent08, StaticReg(1),
DataDynamic, MaskOtc, BGx(0), FGx(0)));
WRITE_WORD(((area->sx << 16) | area->sy), fb, REG_24);
WRITE_WORD(((area->width << 16) | area->height), fb, REG_7);
WRITE_WORD(((area->dx << 16) | area->dy), fb, REG_25);
SETUP_FB(fb);
}
#define ARTIST_VRAM_SIZE 0x000804
#define ARTIST_VRAM_SRC 0x000808
#define ARTIST_VRAM_SIZE_TRIGGER_WINFILL 0x000a04
#define ARTIST_VRAM_DEST_TRIGGER_BLOCKMOVE 0x000b00
#define ARTIST_SRC_BM_ACCESS 0x018008
#define ARTIST_FGCOLOR 0x018010
#define ARTIST_BGCOLOR 0x018014
#define ARTIST_BITMAP_OP 0x01801c
static void
stifb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct stifb_info *fb = container_of(info, struct stifb_info, info);
if (rect->rop != ROP_COPY ||
(fb->id == S9000_ID_HCRX && fb->info.var.bits_per_pixel == 32))
return cfb_fillrect(info, rect);
SETUP_HW(fb);
if (fb->info.var.bits_per_pixel == 32) {
WRITE_WORD(0xBBA0A000, fb, REG_10);
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffffff);
} else {
WRITE_WORD(fb->id == S9000_ID_HCRX ? 0x13a02000 : 0x13a01000, fb, REG_10);
NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xff);
}
WRITE_WORD(0x03000300, fb, ARTIST_BITMAP_OP);
WRITE_WORD(0x2ea01000, fb, ARTIST_SRC_BM_ACCESS);
NGLE_QUICK_SET_DST_BM_ACCESS(fb, 0x2ea01000);
NGLE_REALLY_SET_IMAGE_FG_COLOR(fb, rect->color);
WRITE_WORD(0, fb, ARTIST_BGCOLOR);
NGLE_SET_DSTXY(fb, (rect->dx << 16) | (rect->dy));
SET_LENXY_START_RECFILL(fb, (rect->width << 16) | (rect->height));
SETUP_FB(fb);
}
static void __init
stifb_init_display(struct stifb_info *fb)
{
int id = fb->id;
SETUP_FB(fb);
/* HCRX specific initialization */
SETUP_HCRX(fb);
/*
if (id == S9000_ID_HCRX)
hyperInitSprite(fb);
else
ngleInitSprite(fb);
*/
/* Initialize the image planes. */
switch (id) {
case S9000_ID_HCRX:
hyperResetPlanes(fb, ENABLE);
break;
case S9000_ID_A1439A:
rattlerSetupPlanes(fb);
break;
case S9000_ID_A1659A:
case S9000_ID_ARTIST:
case CRT_ID_VISUALIZE_EG:
elkSetupPlanes(fb);
break;
}
/* Clear attribute planes on non HCRX devices. */
switch (id) {
case S9000_ID_A1659A:
case S9000_ID_A1439A:
if (fb->info.var.bits_per_pixel == 32)
ngleSetupAttrPlanes(fb, BUFF1_CMAP3);
else {
ngleSetupAttrPlanes(fb, BUFF1_CMAP0);
}
if (id == S9000_ID_A1439A)
ngleClearOverlayPlanes(fb, 0xff, 0);
break;
case S9000_ID_ARTIST:
case CRT_ID_VISUALIZE_EG:
if (fb->info.var.bits_per_pixel == 32)
ngleSetupAttrPlanes(fb, BUFF1_CMAP3);
else {
ngleSetupAttrPlanes(fb, ARTIST_CMAP0);
}
break;
}
stifb_blank(0, (struct fb_info *)fb); /* 0=enable screen */
SETUP_FB(fb);
}
/* ------------ Interfaces to hardware functions ------------ */
static const struct fb_ops stifb_ops = {
.owner = THIS_MODULE,
.fb_check_var = stifb_check_var,
.fb_setcolreg = stifb_setcolreg,
.fb_blank = stifb_blank,
.fb_fillrect = stifb_fillrect,
.fb_copyarea = stifb_copyarea,
.fb_imageblit = cfb_imageblit,
};
/*
* Initialization
*/
static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref)
{
struct fb_fix_screeninfo *fix;
struct fb_var_screeninfo *var;
struct stifb_info *fb;
struct fb_info *info;
unsigned long sti_rom_address;
char modestr[32];
char *dev_name;
int bpp, xres, yres;
fb = kzalloc(sizeof(*fb), GFP_ATOMIC);
if (!fb)
return -ENOMEM;
info = &fb->info;
/* set struct to a known state */
fix = &info->fix;
var = &info->var;
fb->sti = sti;
dev_name = sti->sti_data->inq_outptr.dev_name;
/* store upper 32bits of the graphics id */
fb->id = fb->sti->graphics_id[0];
/* only supported cards are allowed */
switch (fb->id) {
case CRT_ID_VISUALIZE_EG:
/* Visualize cards can run either in "double buffer" or
"standard" mode. Depending on the mode, the card reports
a different device name, e.g. "INTERNAL_EG_DX1024" in double
buffer mode and "INTERNAL_EG_X1024" in standard mode.
Since this driver only supports standard mode, we check
if the device name contains the string "DX" and tell the
user how to reconfigure the card. */
if (strstr(dev_name, "DX")) {
printk(KERN_WARNING
"WARNING: stifb framebuffer driver does not support '%s' in double-buffer mode.\n"
"WARNING: Please disable the double-buffer mode in IPL menu (the PARISC-BIOS).\n",
dev_name);
goto out_err0;
}
fallthrough;
case S9000_ID_ARTIST:
case S9000_ID_HCRX:
case S9000_ID_TIMBER:
case S9000_ID_A1659A:
case S9000_ID_A1439A:
break;
default:
printk(KERN_WARNING "stifb: '%s' (id: 0x%08x) not supported.\n",
dev_name, fb->id);
goto out_err0;
}
/* default to 8 bpp on most graphic chips */
bpp = 8;
xres = sti_onscreen_x(fb->sti);
yres = sti_onscreen_y(fb->sti);
ngleGetDeviceRomData(fb);
/* get (virtual) io region base addr */
fix->mmio_start = REGION_BASE(fb,2);
fix->mmio_len = 0x400000;
/* Reject any device not in the NGLE family */
switch (fb->id) {
case S9000_ID_A1659A: /* CRX/A1659A */
break;
case S9000_ID_ELM: /* GRX, grayscale but else same as A1659A */
var->grayscale = 1;
fb->id = S9000_ID_A1659A;
break;
case S9000_ID_TIMBER: /* HP9000/710 Any (may be a grayscale device) */
if (strstr(dev_name, "GRAYSCALE") ||
strstr(dev_name, "Grayscale") ||
strstr(dev_name, "grayscale"))
var->grayscale = 1;
break;
case S9000_ID_TOMCAT: /* Dual CRX, behaves else like a CRX */
/* FIXME: TomCat supports two heads:
* fb.iobase = REGION_BASE(fb_info,3);
* fb.screen_base = ioremap(REGION_BASE(fb_info,2),xxx);
* for now we only support the left one ! */
xres = fb->ngle_rom.x_size_visible;
yres = fb->ngle_rom.y_size_visible;
fb->id = S9000_ID_A1659A;
break;
case S9000_ID_A1439A: /* CRX24/A1439A */
bpp = 32;
break;
case S9000_ID_HCRX: /* Hyperdrive/HCRX */
memset(&fb->ngle_rom, 0, sizeof(fb->ngle_rom));
if ((fb->sti->regions_phys[0] & 0xfc000000) ==
(fb->sti->regions_phys[2] & 0xfc000000))
sti_rom_address = F_EXTEND(fb->sti->regions_phys[0]);
else
sti_rom_address = F_EXTEND(fb->sti->regions_phys[1]);
fb->deviceSpecificConfig = gsc_readl(sti_rom_address);
if (IS_24_DEVICE(fb)) {
if (bpp_pref == 8 || bpp_pref == 32)
bpp = bpp_pref;
else
bpp = 32;
} else
bpp = 8;
READ_WORD(fb, REG_15);
SETUP_HW(fb);
break;
case CRT_ID_VISUALIZE_EG:
case S9000_ID_ARTIST: /* Artist */
break;
default:
#ifdef FALLBACK_TO_1BPP
printk(KERN_WARNING
"stifb: Unsupported graphics card (id=0x%08x) "
"- now trying 1bpp mode instead\n",
fb->id);
bpp = 1; /* default to 1 bpp */
break;
#else
printk(KERN_WARNING
"stifb: Unsupported graphics card (id=0x%08x) "
"- skipping.\n",
fb->id);
goto out_err0;
#endif
}
/* get framebuffer physical and virtual base addr & len (64bit ready) */
fix->smem_start = F_EXTEND(fb->sti->regions_phys[1]);
fix->smem_len = fb->sti->regions[1].region_desc.length * 4096;
fix->line_length = (fb->sti->glob_cfg->total_x * bpp) / 8;
if (!fix->line_length)
fix->line_length = 2048; /* default */
/* limit fbsize to max visible screen size */
if (fix->smem_len > yres*fix->line_length)
fix->smem_len = ALIGN(yres*fix->line_length, 4*1024*1024);
fix->accel = FB_ACCEL_NONE;
switch (bpp) {
case 1:
fix->type = FB_TYPE_PLANES; /* well, sort of */
fix->visual = FB_VISUAL_MONO10;
var->red.length = var->green.length = var->blue.length = 1;
break;
case 8:
fix->type = FB_TYPE_PACKED_PIXELS;
fix->visual = FB_VISUAL_PSEUDOCOLOR;
var->red.length = var->green.length = var->blue.length = 8;
break;
case 32:
fix->type = FB_TYPE_PACKED_PIXELS;
fix->visual = FB_VISUAL_DIRECTCOLOR;
var->red.length = var->green.length = var->blue.length = var->transp.length = 8;
var->blue.offset = 0;
var->green.offset = 8;
var->red.offset = 16;
var->transp.offset = 24;
break;
default:
break;
}
var->xres = var->xres_virtual = xres;
var->yres = var->yres_virtual = yres;
var->bits_per_pixel = bpp;
strcpy(fix->id, "stifb");
info->fbops = &stifb_ops;
info->screen_base = ioremap(REGION_BASE(fb,1), fix->smem_len);
if (!info->screen_base) {
printk(KERN_ERR "stifb: failed to map memory\n");
goto out_err0;
}
info->screen_size = fix->smem_len;
info->flags = FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
info->pseudo_palette = &fb->pseudo_palette;
scnprintf(modestr, sizeof(modestr), "%dx%d-%d", xres, yres, bpp);
fb_find_mode(&info->var, info, modestr, NULL, 0, NULL, bpp);
/* This has to be done !!! */
if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0))
goto out_err1;
stifb_init_display(fb);
if (!request_mem_region(fix->smem_start, fix->smem_len, "stifb fb")) {
printk(KERN_ERR "stifb: cannot reserve fb region 0x%04lx-0x%04lx\n",
fix->smem_start, fix->smem_start+fix->smem_len);
goto out_err2;
}
if (!request_mem_region(fix->mmio_start, fix->mmio_len, "stifb mmio")) {
printk(KERN_ERR "stifb: cannot reserve sti mmio region 0x%04lx-0x%04lx\n",
fix->mmio_start, fix->mmio_start+fix->mmio_len);
goto out_err3;
}
/* save for primary gfx device detection & unregister_framebuffer() */
sti->info = info;
if (register_framebuffer(&fb->info) < 0)
goto out_err4;
fb_info(&fb->info, "%s %dx%d-%d frame buffer device, %s, id: %04x, mmio: 0x%04lx\n",
fix->id,
var->xres,
var->yres,
var->bits_per_pixel,
dev_name,
fb->id,
fix->mmio_start);
return 0;
out_err4:
release_mem_region(fix->mmio_start, fix->mmio_len);
out_err3:
release_mem_region(fix->smem_start, fix->smem_len);
out_err2:
fb_dealloc_cmap(&info->cmap);
out_err1:
iounmap(info->screen_base);
out_err0:
kfree(fb);
sti->info = NULL;
return -ENXIO;
}
static int stifb_disabled __initdata;
int __init
stifb_setup(char *options);
static int __init stifb_init(void)
{
struct sti_struct *sti;
struct sti_struct *def_sti;
int i;
#ifndef MODULE
char *option = NULL;
if (fb_get_options("stifb", &option))
return -ENODEV;
stifb_setup(option);
#endif
if (stifb_disabled) {
printk(KERN_INFO "stifb: disabled by \"stifb=off\" kernel parameter\n");
return -ENXIO;
}
def_sti = sti_get_rom(0);
if (def_sti) {
for (i = 1; i <= MAX_STI_ROMS; i++) {
sti = sti_get_rom(i);
if (!sti)
break;
if (sti == def_sti) {
stifb_init_fb(sti, stifb_bpp_pref[i - 1]);
break;
}
}
}
for (i = 1; i <= MAX_STI_ROMS; i++) {
sti = sti_get_rom(i);
if (!sti)
break;
if (sti == def_sti)
continue;
stifb_init_fb(sti, stifb_bpp_pref[i - 1]);
}
return 0;
}
/*
* Cleanup
*/
static void __exit
stifb_cleanup(void)
{
struct sti_struct *sti;
int i;
for (i = 1; i <= MAX_STI_ROMS; i++) {
sti = sti_get_rom(i);
if (!sti)
break;
if (sti->info) {
struct fb_info *info = sti->info;
unregister_framebuffer(sti->info);
release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
release_mem_region(info->fix.smem_start, info->fix.smem_len);
if (info->screen_base)
iounmap(info->screen_base);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
sti->info = NULL;
}
}
int __init
stifb_setup(char *options)
{
int i;
if (!options || !*options)
return 1;
if (strncmp(options, "off", 3) == 0) {
stifb_disabled = 1;
options += 3;
}
if (strncmp(options, "bpp", 3) == 0) {
options += 3;
for (i = 0; i < MAX_STI_ROMS; i++) {
if (*options++ != ':')
break;
stifb_bpp_pref[i] = simple_strtoul(options, &options, 10);
}
}
return 1;
}
__setup("stifb=", stifb_setup);
module_init(stifb_init);
module_exit(stifb_cleanup);
MODULE_AUTHOR("Helge Deller <[email protected]>, Thomas Bogendoerfer <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for HP's NGLE series graphics cards in HP PARISC machines");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/stifb.c |
// SPDX-License-Identifier: GPL-2.0
/* sbuslib.c: Helper library for SBUS framebuffer drivers.
*
* Copyright (C) 2003 David S. Miller ([email protected])
*/
#include <linux/compat.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/uaccess.h>
#include <linux/of.h>
#include <asm/fbio.h>
#include "sbuslib.h"
void sbusfb_fill_var(struct fb_var_screeninfo *var, struct device_node *dp,
int bpp)
{
memset(var, 0, sizeof(*var));
var->xres = of_getintprop_default(dp, "width", 1152);
var->yres = of_getintprop_default(dp, "height", 900);
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->bits_per_pixel = bpp;
}
EXPORT_SYMBOL(sbusfb_fill_var);
static unsigned long sbusfb_mmapsize(long size, unsigned long fbsize)
{
if (size == SBUS_MMAP_EMPTY) return 0;
if (size >= 0) return size;
return fbsize * (-size);
}
int sbusfb_mmap_helper(struct sbus_mmap_map *map,
unsigned long physbase,
unsigned long fbsize,
unsigned long iospace,
struct vm_area_struct *vma)
{
unsigned int size, page, r, map_size;
unsigned long map_offset = 0;
unsigned long off;
int i;
if (!(vma->vm_flags & (VM_SHARED | VM_MAYSHARE)))
return -EINVAL;
size = vma->vm_end - vma->vm_start;
if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
return -EINVAL;
off = vma->vm_pgoff << PAGE_SHIFT;
/* VM_IO | VM_DONTEXPAND | VM_DONTDUMP are set by remap_pfn_range() */
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
/* Each page, see which map applies */
for (page = 0; page < size; ){
map_size = 0;
for (i = 0; map[i].size; i++)
if (map[i].voff == off+page) {
map_size = sbusfb_mmapsize(map[i].size, fbsize);
#ifdef __sparc_v9__
#define POFF_MASK (PAGE_MASK|0x1UL)
#else
#define POFF_MASK (PAGE_MASK)
#endif
map_offset = (physbase + map[i].poff) & POFF_MASK;
break;
}
if (!map_size) {
page += PAGE_SIZE;
continue;
}
if (page + map_size > size)
map_size = size - page;
r = io_remap_pfn_range(vma,
vma->vm_start + page,
MK_IOSPACE_PFN(iospace,
map_offset >> PAGE_SHIFT),
map_size,
vma->vm_page_prot);
if (r)
return -EAGAIN;
page += map_size;
}
return 0;
}
EXPORT_SYMBOL(sbusfb_mmap_helper);
int sbusfb_ioctl_helper(unsigned long cmd, unsigned long arg,
struct fb_info *info,
int type, int fb_depth, unsigned long fb_size)
{
switch(cmd) {
case FBIOGTYPE: {
struct fbtype __user *f = (struct fbtype __user *) arg;
if (put_user(type, &f->fb_type) ||
put_user(info->var.yres, &f->fb_height) ||
put_user(info->var.xres, &f->fb_width) ||
put_user(fb_depth, &f->fb_depth) ||
put_user(0, &f->fb_cmsize) ||
put_user(fb_size, &f->fb_cmsize))
return -EFAULT;
return 0;
}
case FBIOPUTCMAP_SPARC: {
struct fbcmap __user *c = (struct fbcmap __user *) arg;
struct fb_cmap cmap;
u16 red, green, blue;
u8 red8, green8, blue8;
unsigned char __user *ured;
unsigned char __user *ugreen;
unsigned char __user *ublue;
unsigned int index, count, i;
if (get_user(index, &c->index) ||
get_user(count, &c->count) ||
get_user(ured, &c->red) ||
get_user(ugreen, &c->green) ||
get_user(ublue, &c->blue))
return -EFAULT;
cmap.len = 1;
cmap.red = &red;
cmap.green = &green;
cmap.blue = &blue;
cmap.transp = NULL;
for (i = 0; i < count; i++) {
int err;
if (get_user(red8, &ured[i]) ||
get_user(green8, &ugreen[i]) ||
get_user(blue8, &ublue[i]))
return -EFAULT;
red = red8 << 8;
green = green8 << 8;
blue = blue8 << 8;
cmap.start = index + i;
err = fb_set_cmap(&cmap, info);
if (err)
return err;
}
return 0;
}
case FBIOGETCMAP_SPARC: {
struct fbcmap __user *c = (struct fbcmap __user *) arg;
unsigned char __user *ured;
unsigned char __user *ugreen;
unsigned char __user *ublue;
struct fb_cmap *cmap = &info->cmap;
unsigned int index, count, i;
u8 red, green, blue;
if (get_user(index, &c->index) ||
get_user(count, &c->count) ||
get_user(ured, &c->red) ||
get_user(ugreen, &c->green) ||
get_user(ublue, &c->blue))
return -EFAULT;
if (index > cmap->len || count > cmap->len - index)
return -EINVAL;
for (i = 0; i < count; i++) {
red = cmap->red[index + i] >> 8;
green = cmap->green[index + i] >> 8;
blue = cmap->blue[index + i] >> 8;
if (put_user(red, &ured[i]) ||
put_user(green, &ugreen[i]) ||
put_user(blue, &ublue[i]))
return -EFAULT;
}
return 0;
}
default:
return -EINVAL;
}
}
EXPORT_SYMBOL(sbusfb_ioctl_helper);
#ifdef CONFIG_COMPAT
int sbusfb_compat_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
switch (cmd) {
case FBIOGTYPE:
case FBIOSATTR:
case FBIOGATTR:
case FBIOSVIDEO:
case FBIOGVIDEO:
case FBIOSCURSOR32:
case FBIOGCURSOR32: /* This is not implemented yet.
Later it should be converted... */
case FBIOSCURPOS:
case FBIOGCURPOS:
case FBIOGCURMAX:
return info->fbops->fb_ioctl(info, cmd, arg);
case FBIOPUTCMAP32:
case FBIOPUTCMAP_SPARC: {
struct fbcmap32 c;
struct fb_cmap cmap;
u16 red, green, blue;
u8 red8, green8, blue8;
unsigned char __user *ured;
unsigned char __user *ugreen;
unsigned char __user *ublue;
unsigned int i;
if (copy_from_user(&c, compat_ptr(arg), sizeof(c)))
return -EFAULT;
ured = compat_ptr(c.red);
ugreen = compat_ptr(c.green);
ublue = compat_ptr(c.blue);
cmap.len = 1;
cmap.red = &red;
cmap.green = &green;
cmap.blue = &blue;
cmap.transp = NULL;
for (i = 0; i < c.count; i++) {
int err;
if (get_user(red8, &ured[i]) ||
get_user(green8, &ugreen[i]) ||
get_user(blue8, &ublue[i]))
return -EFAULT;
red = red8 << 8;
green = green8 << 8;
blue = blue8 << 8;
cmap.start = c.index + i;
err = fb_set_cmap(&cmap, info);
if (err)
return err;
}
return 0;
}
case FBIOGETCMAP32: {
struct fbcmap32 c;
unsigned char __user *ured;
unsigned char __user *ugreen;
unsigned char __user *ublue;
struct fb_cmap *cmap = &info->cmap;
unsigned int index, i;
u8 red, green, blue;
if (copy_from_user(&c, compat_ptr(arg), sizeof(c)))
return -EFAULT;
index = c.index;
ured = compat_ptr(c.red);
ugreen = compat_ptr(c.green);
ublue = compat_ptr(c.blue);
if (index > cmap->len || c.count > cmap->len - index)
return -EINVAL;
for (i = 0; i < c.count; i++) {
red = cmap->red[index + i] >> 8;
green = cmap->green[index + i] >> 8;
blue = cmap->blue[index + i] >> 8;
if (put_user(red, &ured[i]) ||
put_user(green, &ugreen[i]) ||
put_user(blue, &ublue[i]))
return -EFAULT;
}
return 0;
}
default:
return -ENOIOCTLCMD;
}
}
EXPORT_SYMBOL(sbusfb_compat_ioctl);
#endif
| linux-master | drivers/video/fbdev/sbuslib.c |
// SPDX-License-Identifier: GPL-2.0-only
/* linux/drivers/video/sm501fb.c
*
* Copyright (c) 2006 Simtec Electronics
* Vincent Sanders <[email protected]>
* Ben Dooks <[email protected]>
*
* Framebuffer driver for the Silicon Motion SM501
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/vmalloc.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/workqueue.h>
#include <linux/wait.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <asm/div64.h>
#ifdef CONFIG_PM
#include <linux/pm.h>
#endif
#include <linux/sm501.h>
#include <linux/sm501-regs.h>
#include "edid.h"
static char *fb_mode = "640x480-16@60";
static unsigned long default_bpp = 16;
static const struct fb_videomode sm501_default_mode = {
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 20833,
.left_margin = 142,
.right_margin = 13,
.upper_margin = 21,
.lower_margin = 1,
.hsync_len = 69,
.vsync_len = 3,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
#define NR_PALETTE 256
enum sm501_controller {
HEAD_CRT = 0,
HEAD_PANEL = 1,
};
/* SM501 memory address.
*
* This structure is used to track memory usage within the SM501 framebuffer
* allocation. The sm_addr field is stored as an offset as it is often used
* against both the physical and mapped addresses.
*/
struct sm501_mem {
unsigned long size;
unsigned long sm_addr; /* offset from base of sm501 fb. */
void __iomem *k_addr;
};
/* private data that is shared between all frambuffers* */
struct sm501fb_info {
struct device *dev;
struct fb_info *fb[2]; /* fb info for both heads */
struct resource *fbmem_res; /* framebuffer resource */
struct resource *regs_res; /* registers resource */
struct resource *regs2d_res; /* 2d registers resource */
struct sm501_platdata_fb *pdata; /* our platform data */
unsigned long pm_crt_ctrl; /* pm: crt ctrl save */
int irq;
int swap_endian; /* set to swap rgb=>bgr */
void __iomem *regs; /* remapped registers */
void __iomem *regs2d; /* 2d remapped registers */
void __iomem *fbmem; /* remapped framebuffer */
size_t fbmem_len; /* length of remapped region */
u8 *edid_data;
};
/* per-framebuffer private data */
struct sm501fb_par {
u32 pseudo_palette[16];
enum sm501_controller head;
struct sm501_mem cursor;
struct sm501_mem screen;
struct fb_ops ops;
void *store_fb;
void *store_cursor;
void __iomem *cursor_regs;
struct sm501fb_info *info;
};
/* Helper functions */
static inline int h_total(struct fb_var_screeninfo *var)
{
return var->xres + var->left_margin +
var->right_margin + var->hsync_len;
}
static inline int v_total(struct fb_var_screeninfo *var)
{
return var->yres + var->upper_margin +
var->lower_margin + var->vsync_len;
}
/* sm501fb_sync_regs()
*
* This call is mainly for PCI bus systems where we need to
* ensure that any writes to the bus are completed before the
* next phase, or after completing a function.
*/
static inline void sm501fb_sync_regs(struct sm501fb_info *info)
{
smc501_readl(info->regs);
}
/* sm501_alloc_mem
*
* This is an attempt to lay out memory for the two framebuffers and
* everything else
*
* |fbmem_res->start fbmem_res->end|
* | |
* |fb[0].fix.smem_start | |fb[1].fix.smem_start | 2K |
* |-> fb[0].fix.smem_len <-| spare |-> fb[1].fix.smem_len <-|-> cursors <-|
*
* The "spare" space is for the 2d engine data
* the fixed is space for the cursors (2x1Kbyte)
*
* we need to allocate memory for the 2D acceleration engine
* command list and the data for the engine to deal with.
*
* - all allocations must be 128bit aligned
* - cursors are 64x64x2 bits (1Kbyte)
*
*/
#define SM501_MEMF_CURSOR (1)
#define SM501_MEMF_PANEL (2)
#define SM501_MEMF_CRT (4)
#define SM501_MEMF_ACCEL (8)
static int sm501_alloc_mem(struct sm501fb_info *inf, struct sm501_mem *mem,
unsigned int why, size_t size, u32 smem_len)
{
struct sm501fb_par *par;
struct fb_info *fbi;
unsigned int ptr;
unsigned int end;
switch (why) {
case SM501_MEMF_CURSOR:
ptr = inf->fbmem_len - size;
inf->fbmem_len = ptr; /* adjust available memory. */
break;
case SM501_MEMF_PANEL:
if (size > inf->fbmem_len)
return -ENOMEM;
ptr = inf->fbmem_len - size;
fbi = inf->fb[HEAD_CRT];
/* round down, some programs such as directfb do not draw
* 0,0 correctly unless the start is aligned to a page start.
*/
if (ptr > 0)
ptr &= ~(PAGE_SIZE - 1);
if (fbi && ptr < smem_len)
return -ENOMEM;
break;
case SM501_MEMF_CRT:
ptr = 0;
/* check to see if we have panel memory allocated
* which would put an limit on available memory. */
fbi = inf->fb[HEAD_PANEL];
if (fbi) {
par = fbi->par;
end = par->screen.k_addr ? par->screen.sm_addr : inf->fbmem_len;
} else
end = inf->fbmem_len;
if ((ptr + size) > end)
return -ENOMEM;
break;
case SM501_MEMF_ACCEL:
fbi = inf->fb[HEAD_CRT];
ptr = fbi ? smem_len : 0;
fbi = inf->fb[HEAD_PANEL];
if (fbi) {
par = fbi->par;
end = par->screen.sm_addr;
} else
end = inf->fbmem_len;
if ((ptr + size) > end)
return -ENOMEM;
break;
default:
return -EINVAL;
}
mem->size = size;
mem->sm_addr = ptr;
mem->k_addr = inf->fbmem + ptr;
dev_dbg(inf->dev, "%s: result %08lx, %p - %u, %zd\n",
__func__, mem->sm_addr, mem->k_addr, why, size);
return 0;
}
/* sm501fb_ps_to_hz
*
* Converts a period in picoseconds to Hz.
*
* Note, we try to keep this in Hz to minimise rounding with
* the limited PLL settings on the SM501.
*/
static unsigned long sm501fb_ps_to_hz(unsigned long psvalue)
{
unsigned long long numerator=1000000000000ULL;
/* 10^12 / picosecond period gives frequency in Hz */
do_div(numerator, psvalue);
return (unsigned long)numerator;
}
/* sm501fb_hz_to_ps is identical to the opposite transform */
#define sm501fb_hz_to_ps(x) sm501fb_ps_to_hz(x)
/* sm501fb_setup_gamma
*
* Programs a linear 1.0 gamma ramp in case the gamma
* correction is enabled without programming anything else.
*/
static void sm501fb_setup_gamma(struct sm501fb_info *fbi,
unsigned long palette)
{
unsigned long value = 0;
int offset;
/* set gamma values */
for (offset = 0; offset < 256 * 4; offset += 4) {
smc501_writel(value, fbi->regs + palette + offset);
value += 0x010101; /* Advance RGB by 1,1,1.*/
}
}
/* sm501fb_check_var
*
* check common variables for both panel and crt
*/
static int sm501fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *sm = par->info;
unsigned long tmp;
/* check we can fit these values into the registers */
if (var->hsync_len > 255 || var->vsync_len > 63)
return -EINVAL;
/* hdisplay end and hsync start */
if ((var->xres + var->right_margin) > 4096)
return -EINVAL;
/* vdisplay end and vsync start */
if ((var->yres + var->lower_margin) > 2048)
return -EINVAL;
/* hard limits of device */
if (h_total(var) > 4096 || v_total(var) > 2048)
return -EINVAL;
/* check our line length is going to be 128 bit aligned */
tmp = (var->xres * var->bits_per_pixel) / 8;
if ((tmp & 15) != 0)
return -EINVAL;
/* check the virtual size */
if (var->xres_virtual > 4096 || var->yres_virtual > 2048)
return -EINVAL;
/* can cope with 8,16 or 32bpp */
if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel == 24)
var->bits_per_pixel = 32;
/* set r/g/b positions and validate bpp */
switch(var->bits_per_pixel) {
case 8:
var->red.length = var->bits_per_pixel;
var->red.offset = 0;
var->green.length = var->bits_per_pixel;
var->green.offset = 0;
var->blue.length = var->bits_per_pixel;
var->blue.offset = 0;
var->transp.length = 0;
var->transp.offset = 0;
break;
case 16:
if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
var->blue.offset = 11;
var->green.offset = 5;
var->red.offset = 0;
} else {
var->red.offset = 11;
var->green.offset = 5;
var->blue.offset = 0;
}
var->transp.offset = 0;
var->red.length = 5;
var->green.length = 6;
var->blue.length = 5;
var->transp.length = 0;
break;
case 32:
if (sm->pdata->flags & SM501_FBPD_SWAP_FB_ENDIAN) {
var->transp.offset = 0;
var->red.offset = 8;
var->green.offset = 16;
var->blue.offset = 24;
} else {
var->transp.offset = 24;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
}
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.length = 0;
break;
default:
return -EINVAL;
}
return 0;
}
/*
* sm501fb_check_var_crt():
*
* check the parameters for the CRT head, and either bring them
* back into range, or return -EINVAL.
*/
static int sm501fb_check_var_crt(struct fb_var_screeninfo *var,
struct fb_info *info)
{
return sm501fb_check_var(var, info);
}
/* sm501fb_check_var_pnl():
*
* check the parameters for the CRT head, and either bring them
* back into range, or return -EINVAL.
*/
static int sm501fb_check_var_pnl(struct fb_var_screeninfo *var,
struct fb_info *info)
{
return sm501fb_check_var(var, info);
}
/* sm501fb_set_par_common
*
* set common registers for framebuffers
*/
static int sm501fb_set_par_common(struct fb_info *info,
struct fb_var_screeninfo *var)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
unsigned long pixclock; /* pixelclock in Hz */
unsigned long sm501pixclock; /* pixelclock the 501 can achieve in Hz */
unsigned int mem_type;
unsigned int clock_type;
unsigned int head_addr;
unsigned int smem_len;
dev_dbg(fbi->dev, "%s: %dx%d, bpp = %d, virtual %dx%d\n",
__func__, var->xres, var->yres, var->bits_per_pixel,
var->xres_virtual, var->yres_virtual);
switch (par->head) {
case HEAD_CRT:
mem_type = SM501_MEMF_CRT;
clock_type = SM501_CLOCK_V2XCLK;
head_addr = SM501_DC_CRT_FB_ADDR;
break;
case HEAD_PANEL:
mem_type = SM501_MEMF_PANEL;
clock_type = SM501_CLOCK_P2XCLK;
head_addr = SM501_DC_PANEL_FB_ADDR;
break;
default:
mem_type = 0; /* stop compiler warnings */
head_addr = 0;
clock_type = 0;
}
switch (var->bits_per_pixel) {
case 8:
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 32:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
}
/* allocate fb memory within 501 */
info->fix.line_length = (var->xres_virtual * var->bits_per_pixel)/8;
smem_len = info->fix.line_length * var->yres_virtual;
dev_dbg(fbi->dev, "%s: line length = %u\n", __func__,
info->fix.line_length);
if (sm501_alloc_mem(fbi, &par->screen, mem_type, smem_len, smem_len)) {
dev_err(fbi->dev, "no memory available\n");
return -ENOMEM;
}
mutex_lock(&info->mm_lock);
info->fix.smem_start = fbi->fbmem_res->start + par->screen.sm_addr;
info->fix.smem_len = smem_len;
mutex_unlock(&info->mm_lock);
info->screen_base = fbi->fbmem + par->screen.sm_addr;
info->screen_size = info->fix.smem_len;
/* set start of framebuffer to the screen */
smc501_writel(par->screen.sm_addr | SM501_ADDR_FLIP,
fbi->regs + head_addr);
/* program CRT clock */
pixclock = sm501fb_ps_to_hz(var->pixclock);
sm501pixclock = sm501_set_clock(fbi->dev->parent, clock_type,
pixclock);
/* update fb layer with actual clock used */
var->pixclock = sm501fb_hz_to_ps(sm501pixclock);
dev_dbg(fbi->dev, "%s: pixclock(ps) = %u, pixclock(Hz) = %lu, "
"sm501pixclock = %lu, error = %ld%%\n",
__func__, var->pixclock, pixclock, sm501pixclock,
((pixclock - sm501pixclock)*100)/pixclock);
return 0;
}
/* sm501fb_set_par_geometry
*
* set the geometry registers for specified framebuffer.
*/
static void sm501fb_set_par_geometry(struct fb_info *info,
struct fb_var_screeninfo *var)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
void __iomem *base = fbi->regs;
unsigned long reg;
if (par->head == HEAD_CRT)
base += SM501_DC_CRT_H_TOT;
else
base += SM501_DC_PANEL_H_TOT;
/* set framebuffer width and display width */
reg = info->fix.line_length;
reg |= ((var->xres * var->bits_per_pixel)/8) << 16;
smc501_writel(reg, fbi->regs + (par->head == HEAD_CRT ?
SM501_DC_CRT_FB_OFFSET : SM501_DC_PANEL_FB_OFFSET));
/* program horizontal total */
reg = (h_total(var) - 1) << 16;
reg |= (var->xres - 1);
smc501_writel(reg, base + SM501_OFF_DC_H_TOT);
/* program horizontal sync */
reg = var->hsync_len << 16;
reg |= var->xres + var->right_margin - 1;
smc501_writel(reg, base + SM501_OFF_DC_H_SYNC);
/* program vertical total */
reg = (v_total(var) - 1) << 16;
reg |= (var->yres - 1);
smc501_writel(reg, base + SM501_OFF_DC_V_TOT);
/* program vertical sync */
reg = var->vsync_len << 16;
reg |= var->yres + var->lower_margin - 1;
smc501_writel(reg, base + SM501_OFF_DC_V_SYNC);
}
/* sm501fb_pan_crt
*
* pan the CRT display output within an virtual framebuffer
*/
static int sm501fb_pan_crt(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
unsigned int bytes_pixel = info->var.bits_per_pixel / 8;
unsigned long reg;
unsigned long xoffs;
xoffs = var->xoffset * bytes_pixel;
reg = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
reg &= ~SM501_DC_CRT_CONTROL_PIXEL_MASK;
reg |= ((xoffs & 15) / bytes_pixel) << 4;
smc501_writel(reg, fbi->regs + SM501_DC_CRT_CONTROL);
reg = (par->screen.sm_addr + xoffs +
var->yoffset * info->fix.line_length);
smc501_writel(reg | SM501_ADDR_FLIP, fbi->regs + SM501_DC_CRT_FB_ADDR);
sm501fb_sync_regs(fbi);
return 0;
}
/* sm501fb_pan_pnl
*
* pan the panel display output within an virtual framebuffer
*/
static int sm501fb_pan_pnl(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
unsigned long reg;
reg = var->xoffset | (info->var.xres_virtual << 16);
smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_WIDTH);
reg = var->yoffset | (info->var.yres_virtual << 16);
smc501_writel(reg, fbi->regs + SM501_DC_PANEL_FB_HEIGHT);
sm501fb_sync_regs(fbi);
return 0;
}
/* sm501fb_set_par_crt
*
* Set the CRT video mode from the fb_info structure
*/
static int sm501fb_set_par_crt(struct fb_info *info)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
struct fb_var_screeninfo *var = &info->var;
unsigned long control; /* control register */
int ret;
/* activate new configuration */
dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
/* enable CRT DAC - note 0 is on!*/
sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
control = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
control &= (SM501_DC_CRT_CONTROL_PIXEL_MASK |
SM501_DC_CRT_CONTROL_GAMMA |
SM501_DC_CRT_CONTROL_BLANK |
SM501_DC_CRT_CONTROL_SEL |
SM501_DC_CRT_CONTROL_CP |
SM501_DC_CRT_CONTROL_TVP);
/* set the sync polarities before we check data source */
if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
control |= SM501_DC_CRT_CONTROL_HSP;
if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
control |= SM501_DC_CRT_CONTROL_VSP;
if ((control & SM501_DC_CRT_CONTROL_SEL) == 0) {
/* the head is displaying panel data... */
sm501_alloc_mem(fbi, &par->screen, SM501_MEMF_CRT, 0,
info->fix.smem_len);
goto out_update;
}
ret = sm501fb_set_par_common(info, var);
if (ret) {
dev_err(fbi->dev, "failed to set common parameters\n");
return ret;
}
sm501fb_pan_crt(var, info);
sm501fb_set_par_geometry(info, var);
control |= SM501_FIFO_3; /* fill if >3 free slots */
switch(var->bits_per_pixel) {
case 8:
control |= SM501_DC_CRT_CONTROL_8BPP;
break;
case 16:
control |= SM501_DC_CRT_CONTROL_16BPP;
sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
break;
case 32:
control |= SM501_DC_CRT_CONTROL_32BPP;
sm501fb_setup_gamma(fbi, SM501_DC_CRT_PALETTE);
break;
default:
BUG();
}
control |= SM501_DC_CRT_CONTROL_SEL; /* CRT displays CRT data */
control |= SM501_DC_CRT_CONTROL_TE; /* enable CRT timing */
control |= SM501_DC_CRT_CONTROL_ENABLE; /* enable CRT plane */
out_update:
dev_dbg(fbi->dev, "new control is %08lx\n", control);
smc501_writel(control, fbi->regs + SM501_DC_CRT_CONTROL);
sm501fb_sync_regs(fbi);
return 0;
}
static void sm501fb_panel_power(struct sm501fb_info *fbi, int to)
{
unsigned long control;
void __iomem *ctrl_reg = fbi->regs + SM501_DC_PANEL_CONTROL;
struct sm501_platdata_fbsub *pd = fbi->pdata->fb_pnl;
control = smc501_readl(ctrl_reg);
if (to && (control & SM501_DC_PANEL_CONTROL_VDD) == 0) {
/* enable panel power */
control |= SM501_DC_PANEL_CONTROL_VDD; /* FPVDDEN */
smc501_writel(control, ctrl_reg);
sm501fb_sync_regs(fbi);
mdelay(10);
control |= SM501_DC_PANEL_CONTROL_DATA; /* DATA */
smc501_writel(control, ctrl_reg);
sm501fb_sync_regs(fbi);
mdelay(10);
/* VBIASEN */
if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
if (pd->flags & SM501FB_FLAG_PANEL_INV_VBIASEN)
control &= ~SM501_DC_PANEL_CONTROL_BIAS;
else
control |= SM501_DC_PANEL_CONTROL_BIAS;
smc501_writel(control, ctrl_reg);
sm501fb_sync_regs(fbi);
mdelay(10);
}
if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
if (pd->flags & SM501FB_FLAG_PANEL_INV_FPEN)
control &= ~SM501_DC_PANEL_CONTROL_FPEN;
else
control |= SM501_DC_PANEL_CONTROL_FPEN;
smc501_writel(control, ctrl_reg);
sm501fb_sync_regs(fbi);
mdelay(10);
}
} else if (!to && (control & SM501_DC_PANEL_CONTROL_VDD) != 0) {
/* disable panel power */
if (!(pd->flags & SM501FB_FLAG_PANEL_NO_FPEN)) {
if (pd->flags & SM501FB_FLAG_PANEL_INV_FPEN)
control |= SM501_DC_PANEL_CONTROL_FPEN;
else
control &= ~SM501_DC_PANEL_CONTROL_FPEN;
smc501_writel(control, ctrl_reg);
sm501fb_sync_regs(fbi);
mdelay(10);
}
if (!(pd->flags & SM501FB_FLAG_PANEL_NO_VBIASEN)) {
if (pd->flags & SM501FB_FLAG_PANEL_INV_VBIASEN)
control |= SM501_DC_PANEL_CONTROL_BIAS;
else
control &= ~SM501_DC_PANEL_CONTROL_BIAS;
smc501_writel(control, ctrl_reg);
sm501fb_sync_regs(fbi);
mdelay(10);
}
control &= ~SM501_DC_PANEL_CONTROL_DATA;
smc501_writel(control, ctrl_reg);
sm501fb_sync_regs(fbi);
mdelay(10);
control &= ~SM501_DC_PANEL_CONTROL_VDD;
smc501_writel(control, ctrl_reg);
sm501fb_sync_regs(fbi);
mdelay(10);
}
sm501fb_sync_regs(fbi);
}
/* sm501fb_set_par_pnl
*
* Set the panel video mode from the fb_info structure
*/
static int sm501fb_set_par_pnl(struct fb_info *info)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
struct fb_var_screeninfo *var = &info->var;
unsigned long control;
unsigned long reg;
int ret;
dev_dbg(fbi->dev, "%s(%p)\n", __func__, info);
/* activate this new configuration */
ret = sm501fb_set_par_common(info, var);
if (ret)
return ret;
sm501fb_pan_pnl(var, info);
sm501fb_set_par_geometry(info, var);
/* update control register */
control = smc501_readl(fbi->regs + SM501_DC_PANEL_CONTROL);
control &= (SM501_DC_PANEL_CONTROL_GAMMA |
SM501_DC_PANEL_CONTROL_VDD |
SM501_DC_PANEL_CONTROL_DATA |
SM501_DC_PANEL_CONTROL_BIAS |
SM501_DC_PANEL_CONTROL_FPEN |
SM501_DC_PANEL_CONTROL_CP |
SM501_DC_PANEL_CONTROL_CK |
SM501_DC_PANEL_CONTROL_HP |
SM501_DC_PANEL_CONTROL_VP |
SM501_DC_PANEL_CONTROL_HPD |
SM501_DC_PANEL_CONTROL_VPD);
control |= SM501_FIFO_3; /* fill if >3 free slots */
switch(var->bits_per_pixel) {
case 8:
control |= SM501_DC_PANEL_CONTROL_8BPP;
break;
case 16:
control |= SM501_DC_PANEL_CONTROL_16BPP;
sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
break;
case 32:
control |= SM501_DC_PANEL_CONTROL_32BPP;
sm501fb_setup_gamma(fbi, SM501_DC_PANEL_PALETTE);
break;
default:
BUG();
}
smc501_writel(0x0, fbi->regs + SM501_DC_PANEL_PANNING_CONTROL);
/* panel plane top left and bottom right location */
smc501_writel(0x00, fbi->regs + SM501_DC_PANEL_TL_LOC);
reg = var->xres - 1;
reg |= (var->yres - 1) << 16;
smc501_writel(reg, fbi->regs + SM501_DC_PANEL_BR_LOC);
/* program panel control register */
control |= SM501_DC_PANEL_CONTROL_TE; /* enable PANEL timing */
control |= SM501_DC_PANEL_CONTROL_EN; /* enable PANEL gfx plane */
if ((var->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
control |= SM501_DC_PANEL_CONTROL_HSP;
if ((var->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
control |= SM501_DC_PANEL_CONTROL_VSP;
smc501_writel(control, fbi->regs + SM501_DC_PANEL_CONTROL);
sm501fb_sync_regs(fbi);
/* ensure the panel interface is not tristated at this point */
sm501_modify_reg(fbi->dev->parent, SM501_SYSTEM_CONTROL,
0, SM501_SYSCTRL_PANEL_TRISTATE);
/* power the panel up */
sm501fb_panel_power(fbi, 1);
return 0;
}
/* chan_to_field
*
* convert a colour value into a field position
*
* from pxafb.c
*/
static inline unsigned int chan_to_field(unsigned int chan,
struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
/* sm501fb_setcolreg
*
* set the colour mapping for modes that support palettised data
*/
static int sm501fb_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
void __iomem *base = fbi->regs;
unsigned int val;
if (par->head == HEAD_CRT)
base += SM501_DC_CRT_PALETTE;
else
base += SM501_DC_PANEL_PALETTE;
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
/* true-colour, use pseuo-palette */
if (regno < 16) {
u32 *pal = par->pseudo_palette;
val = chan_to_field(red, &info->var.red);
val |= chan_to_field(green, &info->var.green);
val |= chan_to_field(blue, &info->var.blue);
pal[regno] = val;
}
break;
case FB_VISUAL_PSEUDOCOLOR:
if (regno < 256) {
val = (red >> 8) << 16;
val |= (green >> 8) << 8;
val |= blue >> 8;
smc501_writel(val, base + (regno * 4));
}
break;
default:
return 1; /* unknown type */
}
return 0;
}
/* sm501fb_blank_pnl
*
* Blank or un-blank the panel interface
*/
static int sm501fb_blank_pnl(int blank_mode, struct fb_info *info)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
switch (blank_mode) {
case FB_BLANK_POWERDOWN:
sm501fb_panel_power(fbi, 0);
break;
case FB_BLANK_UNBLANK:
sm501fb_panel_power(fbi, 1);
break;
case FB_BLANK_NORMAL:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
default:
return 1;
}
return 0;
}
/* sm501fb_blank_crt
*
* Blank or un-blank the crt interface
*/
static int sm501fb_blank_crt(int blank_mode, struct fb_info *info)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
unsigned long ctrl;
dev_dbg(fbi->dev, "%s(mode=%d, %p)\n", __func__, blank_mode, info);
ctrl = smc501_readl(fbi->regs + SM501_DC_CRT_CONTROL);
switch (blank_mode) {
case FB_BLANK_POWERDOWN:
ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
sm501_misc_control(fbi->dev->parent, SM501_MISC_DAC_POWER, 0);
fallthrough;
case FB_BLANK_NORMAL:
ctrl |= SM501_DC_CRT_CONTROL_BLANK;
break;
case FB_BLANK_UNBLANK:
ctrl &= ~SM501_DC_CRT_CONTROL_BLANK;
ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
sm501_misc_control(fbi->dev->parent, 0, SM501_MISC_DAC_POWER);
break;
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
default:
return 1;
}
smc501_writel(ctrl, fbi->regs + SM501_DC_CRT_CONTROL);
sm501fb_sync_regs(fbi);
return 0;
}
/* sm501fb_cursor
*
* set or change the hardware cursor parameters
*/
static int sm501fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
void __iomem *base = fbi->regs;
unsigned long hwc_addr;
unsigned long fg, bg;
dev_dbg(fbi->dev, "%s(%p,%p)\n", __func__, info, cursor);
if (par->head == HEAD_CRT)
base += SM501_DC_CRT_HWC_BASE;
else
base += SM501_DC_PANEL_HWC_BASE;
/* check not being asked to exceed capabilities */
if (cursor->image.width > 64)
return -EINVAL;
if (cursor->image.height > 64)
return -EINVAL;
if (cursor->image.depth > 1)
return -EINVAL;
hwc_addr = smc501_readl(base + SM501_OFF_HWC_ADDR);
if (cursor->enable)
smc501_writel(hwc_addr | SM501_HWC_EN,
base + SM501_OFF_HWC_ADDR);
else
smc501_writel(hwc_addr & ~SM501_HWC_EN,
base + SM501_OFF_HWC_ADDR);
/* set data */
if (cursor->set & FB_CUR_SETPOS) {
unsigned int x = cursor->image.dx;
unsigned int y = cursor->image.dy;
if (x >= 2048 || y >= 2048 )
return -EINVAL;
dev_dbg(fbi->dev, "set position %d,%d\n", x, y);
//y += cursor->image.height;
smc501_writel(x | (y << 16), base + SM501_OFF_HWC_LOC);
}
if (cursor->set & FB_CUR_SETCMAP) {
unsigned int bg_col = cursor->image.bg_color;
unsigned int fg_col = cursor->image.fg_color;
dev_dbg(fbi->dev, "%s: update cmap (%08x,%08x)\n",
__func__, bg_col, fg_col);
bg = ((info->cmap.red[bg_col] & 0xF8) << 8) |
((info->cmap.green[bg_col] & 0xFC) << 3) |
((info->cmap.blue[bg_col] & 0xF8) >> 3);
fg = ((info->cmap.red[fg_col] & 0xF8) << 8) |
((info->cmap.green[fg_col] & 0xFC) << 3) |
((info->cmap.blue[fg_col] & 0xF8) >> 3);
dev_dbg(fbi->dev, "fgcol %08lx, bgcol %08lx\n", fg, bg);
smc501_writel(bg, base + SM501_OFF_HWC_COLOR_1_2);
smc501_writel(fg, base + SM501_OFF_HWC_COLOR_3);
}
if (cursor->set & FB_CUR_SETSIZE ||
cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
/* SM501 cursor is a two bpp 64x64 bitmap this routine
* clears it to transparent then combines the cursor
* shape plane with the colour plane to set the
* cursor */
int x, y;
const unsigned char *pcol = cursor->image.data;
const unsigned char *pmsk = cursor->mask;
void __iomem *dst = par->cursor.k_addr;
unsigned char dcol = 0;
unsigned char dmsk = 0;
unsigned int op;
dev_dbg(fbi->dev, "%s: setting shape (%d,%d)\n",
__func__, cursor->image.width, cursor->image.height);
for (op = 0; op < (64*64*2)/8; op+=4)
smc501_writel(0x0, dst + op);
for (y = 0; y < cursor->image.height; y++) {
for (x = 0; x < cursor->image.width; x++) {
if ((x % 8) == 0) {
dcol = *pcol++;
dmsk = *pmsk++;
} else {
dcol >>= 1;
dmsk >>= 1;
}
if (dmsk & 1) {
op = (dcol & 1) ? 1 : 3;
op <<= ((x % 4) * 2);
op |= readb(dst + (x / 4));
writeb(op, dst + (x / 4));
}
}
dst += (64*2)/8;
}
}
sm501fb_sync_regs(fbi); /* ensure cursor data flushed */
return 0;
}
/* sm501fb_crtsrc_show
*
* device attribute code to show where the crt output is sourced from
*/
static ssize_t sm501fb_crtsrc_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct sm501fb_info *info = dev_get_drvdata(dev);
unsigned long ctrl;
ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
ctrl &= SM501_DC_CRT_CONTROL_SEL;
return sysfs_emit(buf, "%s\n", ctrl ? "crt" : "panel");
}
/* sm501fb_crtsrc_show
*
* device attribute code to set where the crt output is sourced from
*/
static ssize_t sm501fb_crtsrc_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct sm501fb_info *info = dev_get_drvdata(dev);
enum sm501_controller head;
unsigned long ctrl;
if (len < 1)
return -EINVAL;
if (strncasecmp(buf, "crt", 3) == 0)
head = HEAD_CRT;
else if (strncasecmp(buf, "panel", 5) == 0)
head = HEAD_PANEL;
else
return -EINVAL;
dev_info(dev, "setting crt source to head %d\n", head);
ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
if (head == HEAD_CRT) {
ctrl |= SM501_DC_CRT_CONTROL_SEL;
ctrl |= SM501_DC_CRT_CONTROL_ENABLE;
ctrl |= SM501_DC_CRT_CONTROL_TE;
} else {
ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
ctrl &= ~SM501_DC_CRT_CONTROL_ENABLE;
ctrl &= ~SM501_DC_CRT_CONTROL_TE;
}
smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
sm501fb_sync_regs(info);
return len;
}
/* Prepare the device_attr for registration with sysfs later */
static DEVICE_ATTR(crt_src, 0664, sm501fb_crtsrc_show, sm501fb_crtsrc_store);
/* sm501fb_show_regs
*
* show the primary sm501 registers
*/
static int sm501fb_show_regs(struct sm501fb_info *info, char *ptr,
unsigned int start, unsigned int len)
{
void __iomem *mem = info->regs;
char *buf = ptr;
unsigned int reg;
for (reg = start; reg < (len + start); reg += 4)
ptr += sprintf(ptr, "%08x = %08x\n", reg,
smc501_readl(mem + reg));
return ptr - buf;
}
/* sm501fb_debug_show_crt
*
* show the crt control and cursor registers
*/
static ssize_t sm501fb_debug_show_crt(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct sm501fb_info *info = dev_get_drvdata(dev);
char *ptr = buf;
ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_CONTROL, 0x40);
ptr += sm501fb_show_regs(info, ptr, SM501_DC_CRT_HWC_BASE, 0x10);
return ptr - buf;
}
static DEVICE_ATTR(fbregs_crt, 0444, sm501fb_debug_show_crt, NULL);
/* sm501fb_debug_show_pnl
*
* show the panel control and cursor registers
*/
static ssize_t sm501fb_debug_show_pnl(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct sm501fb_info *info = dev_get_drvdata(dev);
char *ptr = buf;
ptr += sm501fb_show_regs(info, ptr, 0x0, 0x40);
ptr += sm501fb_show_regs(info, ptr, SM501_DC_PANEL_HWC_BASE, 0x10);
return ptr - buf;
}
static DEVICE_ATTR(fbregs_pnl, 0444, sm501fb_debug_show_pnl, NULL);
static struct attribute *sm501fb_attrs[] = {
&dev_attr_crt_src.attr,
&dev_attr_fbregs_pnl.attr,
&dev_attr_fbregs_crt.attr,
NULL,
};
ATTRIBUTE_GROUPS(sm501fb);
/* acceleration operations */
static int sm501fb_sync(struct fb_info *info)
{
int count = 1000000;
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
/* wait for the 2d engine to be ready */
while ((count > 0) &&
(smc501_readl(fbi->regs + SM501_SYSTEM_CONTROL) &
SM501_SYSCTRL_2D_ENGINE_STATUS) != 0)
count--;
if (count <= 0) {
fb_err(info, "Timeout waiting for 2d engine sync\n");
return 1;
}
return 0;
}
static void sm501fb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
int width = area->width;
int height = area->height;
int sx = area->sx;
int sy = area->sy;
int dx = area->dx;
int dy = area->dy;
unsigned long rtl = 0;
/* source clip */
if ((sx >= info->var.xres_virtual) ||
(sy >= info->var.yres_virtual))
/* source Area not within virtual screen, skipping */
return;
if ((sx + width) >= info->var.xres_virtual)
width = info->var.xres_virtual - sx - 1;
if ((sy + height) >= info->var.yres_virtual)
height = info->var.yres_virtual - sy - 1;
/* dest clip */
if ((dx >= info->var.xres_virtual) ||
(dy >= info->var.yres_virtual))
/* Destination Area not within virtual screen, skipping */
return;
if ((dx + width) >= info->var.xres_virtual)
width = info->var.xres_virtual - dx - 1;
if ((dy + height) >= info->var.yres_virtual)
height = info->var.yres_virtual - dy - 1;
if ((sx < dx) || (sy < dy)) {
rtl = 1 << 27;
sx += width - 1;
dx += width - 1;
sy += height - 1;
dy += height - 1;
}
if (sm501fb_sync(info))
return;
/* set the base addresses */
smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
smc501_writel(par->screen.sm_addr,
fbi->regs2d + SM501_2D_DESTINATION_BASE);
/* set the window width */
smc501_writel((info->var.xres << 16) | info->var.xres,
fbi->regs2d + SM501_2D_WINDOW_WIDTH);
/* set window stride */
smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
fbi->regs2d + SM501_2D_PITCH);
/* set data format */
switch (info->var.bits_per_pixel) {
case 8:
smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH);
break;
case 16:
smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
break;
case 32:
smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
break;
}
/* 2d compare mask */
smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
/* 2d mask */
smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
/* source and destination x y */
smc501_writel((sx << 16) | sy, fbi->regs2d + SM501_2D_SOURCE);
smc501_writel((dx << 16) | dy, fbi->regs2d + SM501_2D_DESTINATION);
/* w/h */
smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
/* do area move */
smc501_writel(0x800000cc | rtl, fbi->regs2d + SM501_2D_CONTROL);
}
static void sm501fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct sm501fb_par *par = info->par;
struct sm501fb_info *fbi = par->info;
int width = rect->width, height = rect->height;
if ((rect->dx >= info->var.xres_virtual) ||
(rect->dy >= info->var.yres_virtual))
/* Rectangle not within virtual screen, skipping */
return;
if ((rect->dx + width) >= info->var.xres_virtual)
width = info->var.xres_virtual - rect->dx - 1;
if ((rect->dy + height) >= info->var.yres_virtual)
height = info->var.yres_virtual - rect->dy - 1;
if (sm501fb_sync(info))
return;
/* set the base addresses */
smc501_writel(par->screen.sm_addr, fbi->regs2d + SM501_2D_SOURCE_BASE);
smc501_writel(par->screen.sm_addr,
fbi->regs2d + SM501_2D_DESTINATION_BASE);
/* set the window width */
smc501_writel((info->var.xres << 16) | info->var.xres,
fbi->regs2d + SM501_2D_WINDOW_WIDTH);
/* set window stride */
smc501_writel((info->var.xres_virtual << 16) | info->var.xres_virtual,
fbi->regs2d + SM501_2D_PITCH);
/* set data format */
switch (info->var.bits_per_pixel) {
case 8:
smc501_writel(0, fbi->regs2d + SM501_2D_STRETCH);
break;
case 16:
smc501_writel(0x00100000, fbi->regs2d + SM501_2D_STRETCH);
break;
case 32:
smc501_writel(0x00200000, fbi->regs2d + SM501_2D_STRETCH);
break;
}
/* 2d compare mask */
smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_COLOR_COMPARE_MASK);
/* 2d mask */
smc501_writel(0xffffffff, fbi->regs2d + SM501_2D_MASK);
/* colour */
smc501_writel(rect->color, fbi->regs2d + SM501_2D_FOREGROUND);
/* x y */
smc501_writel((rect->dx << 16) | rect->dy,
fbi->regs2d + SM501_2D_DESTINATION);
/* w/h */
smc501_writel((width << 16) | height, fbi->regs2d + SM501_2D_DIMENSION);
/* do rectangle fill */
smc501_writel(0x800100cc, fbi->regs2d + SM501_2D_CONTROL);
}
static struct fb_ops sm501fb_ops_crt = {
.owner = THIS_MODULE,
.fb_check_var = sm501fb_check_var_crt,
.fb_set_par = sm501fb_set_par_crt,
.fb_blank = sm501fb_blank_crt,
.fb_setcolreg = sm501fb_setcolreg,
.fb_pan_display = sm501fb_pan_crt,
.fb_cursor = sm501fb_cursor,
.fb_fillrect = sm501fb_fillrect,
.fb_copyarea = sm501fb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_sync = sm501fb_sync,
};
static struct fb_ops sm501fb_ops_pnl = {
.owner = THIS_MODULE,
.fb_check_var = sm501fb_check_var_pnl,
.fb_set_par = sm501fb_set_par_pnl,
.fb_pan_display = sm501fb_pan_pnl,
.fb_blank = sm501fb_blank_pnl,
.fb_setcolreg = sm501fb_setcolreg,
.fb_cursor = sm501fb_cursor,
.fb_fillrect = sm501fb_fillrect,
.fb_copyarea = sm501fb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_sync = sm501fb_sync,
};
/* sm501_init_cursor
*
* initialise hw cursor parameters
*/
static int sm501_init_cursor(struct fb_info *fbi, unsigned int reg_base)
{
struct sm501fb_par *par;
struct sm501fb_info *info;
int ret;
if (fbi == NULL)
return 0;
par = fbi->par;
info = par->info;
par->cursor_regs = info->regs + reg_base;
ret = sm501_alloc_mem(info, &par->cursor, SM501_MEMF_CURSOR, 1024,
fbi->fix.smem_len);
if (ret < 0)
return ret;
/* initialise the colour registers */
smc501_writel(par->cursor.sm_addr,
par->cursor_regs + SM501_OFF_HWC_ADDR);
smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_LOC);
smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_1_2);
smc501_writel(0x00, par->cursor_regs + SM501_OFF_HWC_COLOR_3);
sm501fb_sync_regs(info);
return 0;
}
/* sm501fb_info_start
*
* fills the par structure claiming resources and remapping etc.
*/
static int sm501fb_start(struct sm501fb_info *info,
struct platform_device *pdev)
{
struct resource *res;
struct device *dev = &pdev->dev;
int k;
int ret;
info->irq = ret = platform_get_irq(pdev, 0);
if (ret < 0) {
/* we currently do not use the IRQ */
dev_warn(dev, "no irq for device\n");
}
/* allocate, reserve and remap resources for display
* controller registers */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(dev, "no resource definition for registers\n");
ret = -ENOENT;
goto err_release;
}
info->regs_res = request_mem_region(res->start,
resource_size(res),
pdev->name);
if (info->regs_res == NULL) {
dev_err(dev, "cannot claim registers\n");
ret = -ENXIO;
goto err_release;
}
info->regs = ioremap(res->start, resource_size(res));
if (info->regs == NULL) {
dev_err(dev, "cannot remap registers\n");
ret = -ENXIO;
goto err_regs_res;
}
/* allocate, reserve and remap resources for 2d
* controller registers */
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (res == NULL) {
dev_err(dev, "no resource definition for 2d registers\n");
ret = -ENOENT;
goto err_regs_map;
}
info->regs2d_res = request_mem_region(res->start,
resource_size(res),
pdev->name);
if (info->regs2d_res == NULL) {
dev_err(dev, "cannot claim registers\n");
ret = -ENXIO;
goto err_regs_map;
}
info->regs2d = ioremap(res->start, resource_size(res));
if (info->regs2d == NULL) {
dev_err(dev, "cannot remap registers\n");
ret = -ENXIO;
goto err_regs2d_res;
}
/* allocate, reserve resources for framebuffer */
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
if (res == NULL) {
dev_err(dev, "no memory resource defined\n");
ret = -ENXIO;
goto err_regs2d_map;
}
info->fbmem_res = request_mem_region(res->start,
resource_size(res),
pdev->name);
if (info->fbmem_res == NULL) {
dev_err(dev, "cannot claim framebuffer\n");
ret = -ENXIO;
goto err_regs2d_map;
}
info->fbmem = ioremap(res->start, resource_size(res));
if (info->fbmem == NULL) {
dev_err(dev, "cannot remap framebuffer\n");
ret = -ENXIO;
goto err_mem_res;
}
info->fbmem_len = resource_size(res);
/* clear framebuffer memory - avoids garbage data on unused fb */
memset_io(info->fbmem, 0, info->fbmem_len);
/* clear palette ram - undefined at power on */
for (k = 0; k < (256 * 3); k++)
smc501_writel(0, info->regs + SM501_DC_PANEL_PALETTE + (k * 4));
/* enable display controller */
sm501_unit_power(dev->parent, SM501_GATE_DISPLAY, 1);
/* enable 2d controller */
sm501_unit_power(dev->parent, SM501_GATE_2D_ENGINE, 1);
/* setup cursors */
sm501_init_cursor(info->fb[HEAD_CRT], SM501_DC_CRT_HWC_ADDR);
sm501_init_cursor(info->fb[HEAD_PANEL], SM501_DC_PANEL_HWC_ADDR);
return 0; /* everything is setup */
err_mem_res:
release_mem_region(info->fbmem_res->start,
resource_size(info->fbmem_res));
err_regs2d_map:
iounmap(info->regs2d);
err_regs2d_res:
release_mem_region(info->regs2d_res->start,
resource_size(info->regs2d_res));
err_regs_map:
iounmap(info->regs);
err_regs_res:
release_mem_region(info->regs_res->start,
resource_size(info->regs_res));
err_release:
return ret;
}
static void sm501fb_stop(struct sm501fb_info *info)
{
/* disable display controller */
sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
iounmap(info->fbmem);
release_mem_region(info->fbmem_res->start,
resource_size(info->fbmem_res));
iounmap(info->regs2d);
release_mem_region(info->regs2d_res->start,
resource_size(info->regs2d_res));
iounmap(info->regs);
release_mem_region(info->regs_res->start,
resource_size(info->regs_res));
}
static int sm501fb_init_fb(struct fb_info *fb, enum sm501_controller head,
const char *fbname)
{
struct sm501_platdata_fbsub *pd;
struct sm501fb_par *par = fb->par;
struct sm501fb_info *info = par->info;
unsigned long ctrl;
unsigned int enable;
int ret;
switch (head) {
case HEAD_CRT:
pd = info->pdata->fb_crt;
ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
enable = (ctrl & SM501_DC_CRT_CONTROL_ENABLE) ? 1 : 0;
/* ensure we set the correct source register */
if (info->pdata->fb_route != SM501_FB_CRT_PANEL) {
ctrl |= SM501_DC_CRT_CONTROL_SEL;
smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
}
break;
case HEAD_PANEL:
pd = info->pdata->fb_pnl;
ctrl = smc501_readl(info->regs + SM501_DC_PANEL_CONTROL);
enable = (ctrl & SM501_DC_PANEL_CONTROL_EN) ? 1 : 0;
break;
default:
pd = NULL; /* stop compiler warnings */
ctrl = 0;
enable = 0;
BUG();
}
dev_info(info->dev, "fb %s %sabled at start\n",
fbname, enable ? "en" : "dis");
/* check to see if our routing allows this */
if (head == HEAD_CRT && info->pdata->fb_route == SM501_FB_CRT_PANEL) {
ctrl &= ~SM501_DC_CRT_CONTROL_SEL;
smc501_writel(ctrl, info->regs + SM501_DC_CRT_CONTROL);
enable = 0;
}
strscpy(fb->fix.id, fbname, sizeof(fb->fix.id));
memcpy(&par->ops,
(head == HEAD_CRT) ? &sm501fb_ops_crt : &sm501fb_ops_pnl,
sizeof(struct fb_ops));
/* update ops dependent on what we've been passed */
if ((pd->flags & SM501FB_FLAG_USE_HWCURSOR) == 0)
par->ops.fb_cursor = NULL;
fb->fbops = &par->ops;
fb->flags = FBINFO_READS_FAST |
FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
#if defined(CONFIG_OF)
#ifdef __BIG_ENDIAN
if (of_property_read_bool(info->dev->parent->of_node, "little-endian"))
fb->flags |= FBINFO_FOREIGN_ENDIAN;
#else
if (of_property_read_bool(info->dev->parent->of_node, "big-endian"))
fb->flags |= FBINFO_FOREIGN_ENDIAN;
#endif
#endif
/* fixed data */
fb->fix.type = FB_TYPE_PACKED_PIXELS;
fb->fix.type_aux = 0;
fb->fix.xpanstep = 1;
fb->fix.ypanstep = 1;
fb->fix.ywrapstep = 0;
fb->fix.accel = FB_ACCEL_NONE;
/* screenmode */
fb->var.nonstd = 0;
fb->var.activate = FB_ACTIVATE_NOW;
fb->var.accel_flags = 0;
fb->var.vmode = FB_VMODE_NONINTERLACED;
fb->var.bits_per_pixel = 16;
if (info->edid_data) {
/* Now build modedb from EDID */
fb_edid_to_monspecs(info->edid_data, &fb->monspecs);
fb_videomode_to_modelist(fb->monspecs.modedb,
fb->monspecs.modedb_len,
&fb->modelist);
}
if (enable && (pd->flags & SM501FB_FLAG_USE_INIT_MODE) && 0) {
/* TODO read the mode from the current display */
} else {
if (pd->def_mode) {
dev_info(info->dev, "using supplied mode\n");
fb_videomode_to_var(&fb->var, pd->def_mode);
fb->var.bits_per_pixel = pd->def_bpp ? pd->def_bpp : 8;
fb->var.xres_virtual = fb->var.xres;
fb->var.yres_virtual = fb->var.yres;
} else {
if (info->edid_data) {
ret = fb_find_mode(&fb->var, fb, fb_mode,
fb->monspecs.modedb,
fb->monspecs.modedb_len,
&sm501_default_mode, default_bpp);
/* edid_data is no longer needed, free it */
kfree(info->edid_data);
} else {
ret = fb_find_mode(&fb->var, fb,
NULL, NULL, 0, NULL, 8);
}
switch (ret) {
case 1:
dev_info(info->dev, "using mode specified in "
"@mode\n");
break;
case 2:
dev_info(info->dev, "using mode specified in "
"@mode with ignored refresh rate\n");
break;
case 3:
dev_info(info->dev, "using mode default "
"mode\n");
break;
case 4:
dev_info(info->dev, "using mode from list\n");
break;
default:
dev_info(info->dev, "ret = %d\n", ret);
dev_info(info->dev, "failed to find mode\n");
return -EINVAL;
}
}
}
/* initialise and set the palette */
if (fb_alloc_cmap(&fb->cmap, NR_PALETTE, 0)) {
dev_err(info->dev, "failed to allocate cmap memory\n");
return -ENOMEM;
}
fb_set_cmap(&fb->cmap, fb);
ret = (fb->fbops->fb_check_var)(&fb->var, fb);
if (ret)
dev_err(info->dev, "check_var() failed on initial setup?\n");
return 0;
}
/* default platform data if none is supplied (ie, PCI device) */
static struct sm501_platdata_fbsub sm501fb_pdata_crt = {
.flags = (SM501FB_FLAG_USE_INIT_MODE |
SM501FB_FLAG_USE_HWCURSOR |
SM501FB_FLAG_USE_HWACCEL |
SM501FB_FLAG_DISABLE_AT_EXIT),
};
static struct sm501_platdata_fbsub sm501fb_pdata_pnl = {
.flags = (SM501FB_FLAG_USE_INIT_MODE |
SM501FB_FLAG_USE_HWCURSOR |
SM501FB_FLAG_USE_HWACCEL |
SM501FB_FLAG_DISABLE_AT_EXIT),
};
static struct sm501_platdata_fb sm501fb_def_pdata = {
.fb_route = SM501_FB_OWN,
.fb_crt = &sm501fb_pdata_crt,
.fb_pnl = &sm501fb_pdata_pnl,
};
static char driver_name_crt[] = "sm501fb-crt";
static char driver_name_pnl[] = "sm501fb-panel";
static int sm501fb_probe_one(struct sm501fb_info *info,
enum sm501_controller head)
{
unsigned char *name = (head == HEAD_CRT) ? "crt" : "panel";
struct sm501_platdata_fbsub *pd;
struct sm501fb_par *par;
struct fb_info *fbi;
pd = (head == HEAD_CRT) ? info->pdata->fb_crt : info->pdata->fb_pnl;
/* Do not initialise if we've not been given any platform data */
if (pd == NULL) {
dev_info(info->dev, "no data for fb %s (disabled)\n", name);
return 0;
}
fbi = framebuffer_alloc(sizeof(struct sm501fb_par), info->dev);
if (!fbi)
return -ENOMEM;
par = fbi->par;
par->info = info;
par->head = head;
fbi->pseudo_palette = &par->pseudo_palette;
info->fb[head] = fbi;
return 0;
}
/* Free up anything allocated by sm501fb_init_fb */
static void sm501_free_init_fb(struct sm501fb_info *info,
enum sm501_controller head)
{
struct fb_info *fbi = info->fb[head];
if (!fbi)
return;
fb_dealloc_cmap(&fbi->cmap);
}
static int sm501fb_start_one(struct sm501fb_info *info,
enum sm501_controller head, const char *drvname)
{
struct fb_info *fbi = info->fb[head];
int ret;
if (!fbi)
return 0;
mutex_init(&info->fb[head]->mm_lock);
ret = sm501fb_init_fb(info->fb[head], head, drvname);
if (ret) {
dev_err(info->dev, "cannot initialise fb %s\n", drvname);
return ret;
}
ret = register_framebuffer(info->fb[head]);
if (ret) {
dev_err(info->dev, "failed to register fb %s\n", drvname);
sm501_free_init_fb(info, head);
return ret;
}
dev_info(info->dev, "fb%d: %s frame buffer\n", fbi->node, fbi->fix.id);
return 0;
}
static int sm501fb_probe(struct platform_device *pdev)
{
struct sm501fb_info *info;
struct device *dev = &pdev->dev;
int ret;
/* allocate our framebuffers */
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (!info) {
dev_err(dev, "failed to allocate state\n");
return -ENOMEM;
}
info->dev = dev = &pdev->dev;
platform_set_drvdata(pdev, info);
if (dev->parent->platform_data) {
struct sm501_platdata *pd = dev->parent->platform_data;
info->pdata = pd->fb;
}
if (info->pdata == NULL) {
int found = 0;
#if defined(CONFIG_OF)
struct device_node *np = pdev->dev.parent->of_node;
const u8 *prop;
const char *cp;
int len;
info->pdata = &sm501fb_def_pdata;
if (np) {
/* Get EDID */
cp = of_get_property(np, "mode", &len);
if (cp)
strcpy(fb_mode, cp);
prop = of_get_property(np, "edid", &len);
if (prop && len == EDID_LENGTH) {
info->edid_data = kmemdup(prop, EDID_LENGTH,
GFP_KERNEL);
if (info->edid_data)
found = 1;
}
}
#endif
if (!found) {
dev_info(dev, "using default configuration data\n");
info->pdata = &sm501fb_def_pdata;
}
}
/* probe for the presence of each panel */
ret = sm501fb_probe_one(info, HEAD_CRT);
if (ret < 0) {
dev_err(dev, "failed to probe CRT\n");
goto err_alloc;
}
ret = sm501fb_probe_one(info, HEAD_PANEL);
if (ret < 0) {
dev_err(dev, "failed to probe PANEL\n");
goto err_probed_crt;
}
if (info->fb[HEAD_PANEL] == NULL &&
info->fb[HEAD_CRT] == NULL) {
dev_err(dev, "no framebuffers found\n");
ret = -ENODEV;
goto err_alloc;
}
/* get the resources for both of the framebuffers */
ret = sm501fb_start(info, pdev);
if (ret) {
dev_err(dev, "cannot initialise SM501\n");
goto err_probed_panel;
}
ret = sm501fb_start_one(info, HEAD_CRT, driver_name_crt);
if (ret) {
dev_err(dev, "failed to start CRT\n");
goto err_started;
}
ret = sm501fb_start_one(info, HEAD_PANEL, driver_name_pnl);
if (ret) {
dev_err(dev, "failed to start Panel\n");
goto err_started_crt;
}
/* we registered, return ok */
return 0;
err_started_crt:
unregister_framebuffer(info->fb[HEAD_CRT]);
sm501_free_init_fb(info, HEAD_CRT);
err_started:
sm501fb_stop(info);
err_probed_panel:
framebuffer_release(info->fb[HEAD_PANEL]);
err_probed_crt:
framebuffer_release(info->fb[HEAD_CRT]);
err_alloc:
kfree(info);
return ret;
}
/*
* Cleanup
*/
static void sm501fb_remove(struct platform_device *pdev)
{
struct sm501fb_info *info = platform_get_drvdata(pdev);
struct fb_info *fbinfo_crt = info->fb[0];
struct fb_info *fbinfo_pnl = info->fb[1];
sm501_free_init_fb(info, HEAD_CRT);
sm501_free_init_fb(info, HEAD_PANEL);
if (fbinfo_crt)
unregister_framebuffer(fbinfo_crt);
if (fbinfo_pnl)
unregister_framebuffer(fbinfo_pnl);
sm501fb_stop(info);
kfree(info);
framebuffer_release(fbinfo_pnl);
framebuffer_release(fbinfo_crt);
}
#ifdef CONFIG_PM
static int sm501fb_suspend_fb(struct sm501fb_info *info,
enum sm501_controller head)
{
struct fb_info *fbi = info->fb[head];
struct sm501fb_par *par;
if (!fbi)
return 0;
par = fbi->par;
if (par->screen.size == 0)
return 0;
/* blank the relevant interface to ensure unit power minimised */
(par->ops.fb_blank)(FB_BLANK_POWERDOWN, fbi);
/* tell console/fb driver we are suspending */
console_lock();
fb_set_suspend(fbi, 1);
console_unlock();
/* backup copies in case chip is powered down over suspend */
par->store_fb = vmalloc(par->screen.size);
if (par->store_fb == NULL) {
dev_err(info->dev, "no memory to store screen\n");
return -ENOMEM;
}
par->store_cursor = vmalloc(par->cursor.size);
if (par->store_cursor == NULL) {
dev_err(info->dev, "no memory to store cursor\n");
goto err_nocursor;
}
dev_dbg(info->dev, "suspending screen to %p\n", par->store_fb);
dev_dbg(info->dev, "suspending cursor to %p\n", par->store_cursor);
memcpy_fromio(par->store_fb, par->screen.k_addr, par->screen.size);
memcpy_fromio(par->store_cursor, par->cursor.k_addr, par->cursor.size);
return 0;
err_nocursor:
vfree(par->store_fb);
par->store_fb = NULL;
return -ENOMEM;
}
static void sm501fb_resume_fb(struct sm501fb_info *info,
enum sm501_controller head)
{
struct fb_info *fbi = info->fb[head];
struct sm501fb_par *par;
if (!fbi)
return;
par = fbi->par;
if (par->screen.size == 0)
return;
/* re-activate the configuration */
(par->ops.fb_set_par)(fbi);
/* restore the data */
dev_dbg(info->dev, "restoring screen from %p\n", par->store_fb);
dev_dbg(info->dev, "restoring cursor from %p\n", par->store_cursor);
if (par->store_fb)
memcpy_toio(par->screen.k_addr, par->store_fb,
par->screen.size);
if (par->store_cursor)
memcpy_toio(par->cursor.k_addr, par->store_cursor,
par->cursor.size);
console_lock();
fb_set_suspend(fbi, 0);
console_unlock();
vfree(par->store_fb);
vfree(par->store_cursor);
}
/* suspend and resume support */
static int sm501fb_suspend(struct platform_device *pdev, pm_message_t state)
{
struct sm501fb_info *info = platform_get_drvdata(pdev);
/* store crt control to resume with */
info->pm_crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
sm501fb_suspend_fb(info, HEAD_CRT);
sm501fb_suspend_fb(info, HEAD_PANEL);
/* turn off the clocks, in case the device is not powered down */
sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
return 0;
}
#define SM501_CRT_CTRL_SAVE (SM501_DC_CRT_CONTROL_TVP | \
SM501_DC_CRT_CONTROL_SEL)
static int sm501fb_resume(struct platform_device *pdev)
{
struct sm501fb_info *info = platform_get_drvdata(pdev);
unsigned long crt_ctrl;
sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 1);
/* restore the items we want to be saved for crt control */
crt_ctrl = smc501_readl(info->regs + SM501_DC_CRT_CONTROL);
crt_ctrl &= ~SM501_CRT_CTRL_SAVE;
crt_ctrl |= info->pm_crt_ctrl & SM501_CRT_CTRL_SAVE;
smc501_writel(crt_ctrl, info->regs + SM501_DC_CRT_CONTROL);
sm501fb_resume_fb(info, HEAD_CRT);
sm501fb_resume_fb(info, HEAD_PANEL);
return 0;
}
#else
#define sm501fb_suspend NULL
#define sm501fb_resume NULL
#endif
static struct platform_driver sm501fb_driver = {
.probe = sm501fb_probe,
.remove_new = sm501fb_remove,
.suspend = sm501fb_suspend,
.resume = sm501fb_resume,
.driver = {
.name = "sm501-fb",
.dev_groups = sm501fb_groups,
},
};
module_platform_driver(sm501fb_driver);
module_param_named(mode, fb_mode, charp, 0);
MODULE_PARM_DESC(mode,
"Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
module_param_named(bpp, default_bpp, ulong, 0);
MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified mode");
MODULE_AUTHOR("Ben Dooks, Vincent Sanders");
MODULE_DESCRIPTION("SM501 Framebuffer driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/sm501fb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* smscufx.c -- Framebuffer driver for SMSC UFX USB controller
*
* Copyright (C) 2011 Steve Glendinning <[email protected]>
* Copyright (C) 2009 Roberto De Ioris <[email protected]>
* Copyright (C) 2009 Jaya Kumar <[email protected]>
* Copyright (C) 2009 Bernie Thompson <[email protected]>
*
* Based on udlfb, with work from Florian Echtler, Henrik Bjerregaard Pedersen,
* and others.
*
* Works well with Bernie Thompson's X DAMAGE patch to xf86-video-fbdev
* available from http://git.plugable.com
*
* Layout is based on skeletonfb by James Simmons and Geert Uytterhoeven,
* usb-skeleton by GregKH.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/usb.h>
#include <linux/uaccess.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/vmalloc.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "edid.h"
#define check_warn(status, fmt, args...) \
({ if (status < 0) pr_warn(fmt, ##args); })
#define check_warn_return(status, fmt, args...) \
({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
#define check_warn_goto_error(status, fmt, args...) \
({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
#define all_bits_set(x, bits) (((x) & (bits)) == (bits))
#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
/*
* TODO: Propose standard fb.h ioctl for reporting damage,
* using _IOWR() and one of the existing area structs from fb.h
* Consider these ioctls deprecated, but they're still used by the
* DisplayLink X server as yet - need both to be modified in tandem
* when new ioctl(s) are ready.
*/
#define UFX_IOCTL_RETURN_EDID (0xAD)
#define UFX_IOCTL_REPORT_DAMAGE (0xAA)
/* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
#define BULK_SIZE (512)
#define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE)
#define WRITES_IN_FLIGHT (4)
#define GET_URB_TIMEOUT (HZ)
#define FREE_URB_TIMEOUT (HZ*2)
#define BPP 2
#define UFX_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */
#define UFX_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */
struct dloarea {
int x, y;
int w, h;
};
struct urb_node {
struct list_head entry;
struct ufx_data *dev;
struct delayed_work release_urb_work;
struct urb *urb;
};
struct urb_list {
struct list_head list;
spinlock_t lock;
struct semaphore limit_sem;
int available;
int count;
size_t size;
};
struct ufx_data {
struct usb_device *udev;
struct device *gdev; /* &udev->dev */
struct fb_info *info;
struct urb_list urbs;
struct kref kref;
int fb_count;
bool virtualized; /* true when physical usb device not present */
atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */
u8 *edid; /* null until we read edid from hw or get from sysfs */
size_t edid_size;
u32 pseudo_palette[256];
};
static struct fb_fix_screeninfo ufx_fix = {
.id = "smscufx",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static const u32 smscufx_info_flags = FBINFO_READS_FAST |
FBINFO_VIRTFB | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_COPYAREA | FBINFO_MISC_ALWAYS_SETPAR;
static const struct usb_device_id id_table[] = {
{USB_DEVICE(0x0424, 0x9d00),},
{USB_DEVICE(0x0424, 0x9d01),},
{},
};
MODULE_DEVICE_TABLE(usb, id_table);
/* module options */
static bool console; /* Optionally allow fbcon to consume first framebuffer */
static bool fb_defio = true; /* Optionally enable fb_defio mmap support */
/* ufx keeps a list of urbs for efficient bulk transfers */
static void ufx_urb_completion(struct urb *urb);
static struct urb *ufx_get_urb(struct ufx_data *dev);
static int ufx_submit_urb(struct ufx_data *dev, struct urb * urb, size_t len);
static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size);
static void ufx_free_urb_list(struct ufx_data *dev);
static DEFINE_MUTEX(disconnect_mutex);
/* reads a control register */
static int ufx_reg_read(struct ufx_data *dev, u32 index, u32 *data)
{
u32 *buf = kmalloc(4, GFP_KERNEL);
int ret;
BUG_ON(!dev);
if (!buf)
return -ENOMEM;
ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
USB_VENDOR_REQUEST_READ_REGISTER,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
le32_to_cpus(buf);
*data = *buf;
kfree(buf);
if (unlikely(ret < 0))
pr_warn("Failed to read register index 0x%08x\n", index);
return ret;
}
/* writes a control register */
static int ufx_reg_write(struct ufx_data *dev, u32 index, u32 data)
{
u32 *buf = kmalloc(4, GFP_KERNEL);
int ret;
BUG_ON(!dev);
if (!buf)
return -ENOMEM;
*buf = data;
cpu_to_le32s(buf);
ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
USB_VENDOR_REQUEST_WRITE_REGISTER,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
kfree(buf);
if (unlikely(ret < 0))
pr_warn("Failed to write register index 0x%08x with value "
"0x%08x\n", index, data);
return ret;
}
static int ufx_reg_clear_and_set_bits(struct ufx_data *dev, u32 index,
u32 bits_to_clear, u32 bits_to_set)
{
u32 data;
int status = ufx_reg_read(dev, index, &data);
check_warn_return(status, "ufx_reg_clear_and_set_bits error reading "
"0x%x", index);
data &= (~bits_to_clear);
data |= bits_to_set;
status = ufx_reg_write(dev, index, data);
check_warn_return(status, "ufx_reg_clear_and_set_bits error writing "
"0x%x", index);
return 0;
}
static int ufx_reg_set_bits(struct ufx_data *dev, u32 index, u32 bits)
{
return ufx_reg_clear_and_set_bits(dev, index, 0, bits);
}
static int ufx_reg_clear_bits(struct ufx_data *dev, u32 index, u32 bits)
{
return ufx_reg_clear_and_set_bits(dev, index, bits, 0);
}
static int ufx_lite_reset(struct ufx_data *dev)
{
int status;
u32 value;
status = ufx_reg_write(dev, 0x3008, 0x00000001);
check_warn_return(status, "ufx_lite_reset error writing 0x3008");
status = ufx_reg_read(dev, 0x3008, &value);
check_warn_return(status, "ufx_lite_reset error reading 0x3008");
return (value == 0) ? 0 : -EIO;
}
/* If display is unblanked, then blank it */
static int ufx_blank(struct ufx_data *dev, bool wait)
{
u32 dc_ctrl, dc_sts;
int i;
int status = ufx_reg_read(dev, 0x2004, &dc_sts);
check_warn_return(status, "ufx_blank error reading 0x2004");
status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
check_warn_return(status, "ufx_blank error reading 0x2000");
/* return success if display is already blanked */
if ((dc_sts & 0x00000100) || (dc_ctrl & 0x00000100))
return 0;
/* request the DC to blank the display */
dc_ctrl |= 0x00000100;
status = ufx_reg_write(dev, 0x2000, dc_ctrl);
check_warn_return(status, "ufx_blank error writing 0x2000");
/* return success immediately if we don't have to wait */
if (!wait)
return 0;
for (i = 0; i < 250; i++) {
status = ufx_reg_read(dev, 0x2004, &dc_sts);
check_warn_return(status, "ufx_blank error reading 0x2004");
if (dc_sts & 0x00000100)
return 0;
}
/* timed out waiting for display to blank */
return -EIO;
}
/* If display is blanked, then unblank it */
static int ufx_unblank(struct ufx_data *dev, bool wait)
{
u32 dc_ctrl, dc_sts;
int i;
int status = ufx_reg_read(dev, 0x2004, &dc_sts);
check_warn_return(status, "ufx_unblank error reading 0x2004");
status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
check_warn_return(status, "ufx_unblank error reading 0x2000");
/* return success if display is already unblanked */
if (((dc_sts & 0x00000100) == 0) || ((dc_ctrl & 0x00000100) == 0))
return 0;
/* request the DC to unblank the display */
dc_ctrl &= ~0x00000100;
status = ufx_reg_write(dev, 0x2000, dc_ctrl);
check_warn_return(status, "ufx_unblank error writing 0x2000");
/* return success immediately if we don't have to wait */
if (!wait)
return 0;
for (i = 0; i < 250; i++) {
status = ufx_reg_read(dev, 0x2004, &dc_sts);
check_warn_return(status, "ufx_unblank error reading 0x2004");
if ((dc_sts & 0x00000100) == 0)
return 0;
}
/* timed out waiting for display to unblank */
return -EIO;
}
/* If display is enabled, then disable it */
static int ufx_disable(struct ufx_data *dev, bool wait)
{
u32 dc_ctrl, dc_sts;
int i;
int status = ufx_reg_read(dev, 0x2004, &dc_sts);
check_warn_return(status, "ufx_disable error reading 0x2004");
status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
check_warn_return(status, "ufx_disable error reading 0x2000");
/* return success if display is already disabled */
if (((dc_sts & 0x00000001) == 0) || ((dc_ctrl & 0x00000001) == 0))
return 0;
/* request the DC to disable the display */
dc_ctrl &= ~(0x00000001);
status = ufx_reg_write(dev, 0x2000, dc_ctrl);
check_warn_return(status, "ufx_disable error writing 0x2000");
/* return success immediately if we don't have to wait */
if (!wait)
return 0;
for (i = 0; i < 250; i++) {
status = ufx_reg_read(dev, 0x2004, &dc_sts);
check_warn_return(status, "ufx_disable error reading 0x2004");
if ((dc_sts & 0x00000001) == 0)
return 0;
}
/* timed out waiting for display to disable */
return -EIO;
}
/* If display is disabled, then enable it */
static int ufx_enable(struct ufx_data *dev, bool wait)
{
u32 dc_ctrl, dc_sts;
int i;
int status = ufx_reg_read(dev, 0x2004, &dc_sts);
check_warn_return(status, "ufx_enable error reading 0x2004");
status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
check_warn_return(status, "ufx_enable error reading 0x2000");
/* return success if display is already enabled */
if ((dc_sts & 0x00000001) || (dc_ctrl & 0x00000001))
return 0;
/* request the DC to enable the display */
dc_ctrl |= 0x00000001;
status = ufx_reg_write(dev, 0x2000, dc_ctrl);
check_warn_return(status, "ufx_enable error writing 0x2000");
/* return success immediately if we don't have to wait */
if (!wait)
return 0;
for (i = 0; i < 250; i++) {
status = ufx_reg_read(dev, 0x2004, &dc_sts);
check_warn_return(status, "ufx_enable error reading 0x2004");
if (dc_sts & 0x00000001)
return 0;
}
/* timed out waiting for display to enable */
return -EIO;
}
static int ufx_config_sys_clk(struct ufx_data *dev)
{
int status = ufx_reg_write(dev, 0x700C, 0x8000000F);
check_warn_return(status, "error writing 0x700C");
status = ufx_reg_write(dev, 0x7014, 0x0010024F);
check_warn_return(status, "error writing 0x7014");
status = ufx_reg_write(dev, 0x7010, 0x00000000);
check_warn_return(status, "error writing 0x7010");
status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A);
check_warn_return(status, "error clearing PLL1 bypass in 0x700C");
msleep(1);
status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000);
check_warn_return(status, "error clearing output gate in 0x700C");
return 0;
}
static int ufx_config_ddr2(struct ufx_data *dev)
{
int status, i = 0;
u32 tmp;
status = ufx_reg_write(dev, 0x0004, 0x001F0F77);
check_warn_return(status, "error writing 0x0004");
status = ufx_reg_write(dev, 0x0008, 0xFFF00000);
check_warn_return(status, "error writing 0x0008");
status = ufx_reg_write(dev, 0x000C, 0x0FFF2222);
check_warn_return(status, "error writing 0x000C");
status = ufx_reg_write(dev, 0x0010, 0x00030814);
check_warn_return(status, "error writing 0x0010");
status = ufx_reg_write(dev, 0x0014, 0x00500019);
check_warn_return(status, "error writing 0x0014");
status = ufx_reg_write(dev, 0x0018, 0x020D0F15);
check_warn_return(status, "error writing 0x0018");
status = ufx_reg_write(dev, 0x001C, 0x02532305);
check_warn_return(status, "error writing 0x001C");
status = ufx_reg_write(dev, 0x0020, 0x0B030905);
check_warn_return(status, "error writing 0x0020");
status = ufx_reg_write(dev, 0x0024, 0x00000827);
check_warn_return(status, "error writing 0x0024");
status = ufx_reg_write(dev, 0x0028, 0x00000000);
check_warn_return(status, "error writing 0x0028");
status = ufx_reg_write(dev, 0x002C, 0x00000042);
check_warn_return(status, "error writing 0x002C");
status = ufx_reg_write(dev, 0x0030, 0x09520000);
check_warn_return(status, "error writing 0x0030");
status = ufx_reg_write(dev, 0x0034, 0x02223314);
check_warn_return(status, "error writing 0x0034");
status = ufx_reg_write(dev, 0x0038, 0x00430043);
check_warn_return(status, "error writing 0x0038");
status = ufx_reg_write(dev, 0x003C, 0xF00F000F);
check_warn_return(status, "error writing 0x003C");
status = ufx_reg_write(dev, 0x0040, 0xF380F00F);
check_warn_return(status, "error writing 0x0040");
status = ufx_reg_write(dev, 0x0044, 0xF00F0496);
check_warn_return(status, "error writing 0x0044");
status = ufx_reg_write(dev, 0x0048, 0x03080406);
check_warn_return(status, "error writing 0x0048");
status = ufx_reg_write(dev, 0x004C, 0x00001000);
check_warn_return(status, "error writing 0x004C");
status = ufx_reg_write(dev, 0x005C, 0x00000007);
check_warn_return(status, "error writing 0x005C");
status = ufx_reg_write(dev, 0x0100, 0x54F00012);
check_warn_return(status, "error writing 0x0100");
status = ufx_reg_write(dev, 0x0104, 0x00004012);
check_warn_return(status, "error writing 0x0104");
status = ufx_reg_write(dev, 0x0118, 0x40404040);
check_warn_return(status, "error writing 0x0118");
status = ufx_reg_write(dev, 0x0000, 0x00000001);
check_warn_return(status, "error writing 0x0000");
while (i++ < 500) {
status = ufx_reg_read(dev, 0x0000, &tmp);
check_warn_return(status, "error reading 0x0000");
if (all_bits_set(tmp, 0xC0000000))
return 0;
}
pr_err("DDR2 initialisation timed out, reg 0x0000=0x%08x", tmp);
return -ETIMEDOUT;
}
struct pll_values {
u32 div_r0;
u32 div_f0;
u32 div_q0;
u32 range0;
u32 div_r1;
u32 div_f1;
u32 div_q1;
u32 range1;
};
static u32 ufx_calc_range(u32 ref_freq)
{
if (ref_freq >= 88000000)
return 7;
if (ref_freq >= 54000000)
return 6;
if (ref_freq >= 34000000)
return 5;
if (ref_freq >= 21000000)
return 4;
if (ref_freq >= 13000000)
return 3;
if (ref_freq >= 8000000)
return 2;
return 1;
}
/* calculates PLL divider settings for a desired target frequency */
static void ufx_calc_pll_values(const u32 clk_pixel_pll, struct pll_values *asic_pll)
{
const u32 ref_clk = 25000000;
u32 div_r0, div_f0, div_q0, div_r1, div_f1, div_q1;
u32 min_error = clk_pixel_pll;
for (div_r0 = 1; div_r0 <= 32; div_r0++) {
u32 ref_freq0 = ref_clk / div_r0;
if (ref_freq0 < 5000000)
break;
if (ref_freq0 > 200000000)
continue;
for (div_f0 = 1; div_f0 <= 256; div_f0++) {
u32 vco_freq0 = ref_freq0 * div_f0;
if (vco_freq0 < 350000000)
continue;
if (vco_freq0 > 700000000)
break;
for (div_q0 = 0; div_q0 < 7; div_q0++) {
u32 pllout_freq0 = vco_freq0 / (1 << div_q0);
if (pllout_freq0 < 5000000)
break;
if (pllout_freq0 > 200000000)
continue;
for (div_r1 = 1; div_r1 <= 32; div_r1++) {
u32 ref_freq1 = pllout_freq0 / div_r1;
if (ref_freq1 < 5000000)
break;
for (div_f1 = 1; div_f1 <= 256; div_f1++) {
u32 vco_freq1 = ref_freq1 * div_f1;
if (vco_freq1 < 350000000)
continue;
if (vco_freq1 > 700000000)
break;
for (div_q1 = 0; div_q1 < 7; div_q1++) {
u32 pllout_freq1 = vco_freq1 / (1 << div_q1);
int error = abs(pllout_freq1 - clk_pixel_pll);
if (pllout_freq1 < 5000000)
break;
if (pllout_freq1 > 700000000)
continue;
if (error < min_error) {
min_error = error;
/* final returned value is equal to calculated value - 1
* because a value of 0 = divide by 1 */
asic_pll->div_r0 = div_r0 - 1;
asic_pll->div_f0 = div_f0 - 1;
asic_pll->div_q0 = div_q0;
asic_pll->div_r1 = div_r1 - 1;
asic_pll->div_f1 = div_f1 - 1;
asic_pll->div_q1 = div_q1;
asic_pll->range0 = ufx_calc_range(ref_freq0);
asic_pll->range1 = ufx_calc_range(ref_freq1);
if (min_error == 0)
return;
}
}
}
}
}
}
}
}
/* sets analog bit PLL configuration values */
static int ufx_config_pix_clk(struct ufx_data *dev, u32 pixclock)
{
struct pll_values asic_pll = {0};
u32 value, clk_pixel, clk_pixel_pll;
int status;
/* convert pixclock (in ps) to frequency (in Hz) */
clk_pixel = PICOS2KHZ(pixclock) * 1000;
pr_debug("pixclock %d ps = clk_pixel %d Hz", pixclock, clk_pixel);
/* clk_pixel = 1/2 clk_pixel_pll */
clk_pixel_pll = clk_pixel * 2;
ufx_calc_pll_values(clk_pixel_pll, &asic_pll);
/* Keep BYPASS and RESET signals asserted until configured */
status = ufx_reg_write(dev, 0x7000, 0x8000000F);
check_warn_return(status, "error writing 0x7000");
value = (asic_pll.div_f1 | (asic_pll.div_r1 << 8) |
(asic_pll.div_q1 << 16) | (asic_pll.range1 << 20));
status = ufx_reg_write(dev, 0x7008, value);
check_warn_return(status, "error writing 0x7008");
value = (asic_pll.div_f0 | (asic_pll.div_r0 << 8) |
(asic_pll.div_q0 << 16) | (asic_pll.range0 << 20));
status = ufx_reg_write(dev, 0x7004, value);
check_warn_return(status, "error writing 0x7004");
status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005);
check_warn_return(status,
"error clearing PLL0 bypass bits in 0x7000");
msleep(1);
status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A);
check_warn_return(status,
"error clearing PLL1 bypass bits in 0x7000");
msleep(1);
status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000);
check_warn_return(status, "error clearing gate bits in 0x7000");
return 0;
}
static int ufx_set_vid_mode(struct ufx_data *dev, struct fb_var_screeninfo *var)
{
u32 temp;
u16 h_total, h_active, h_blank_start, h_blank_end, h_sync_start, h_sync_end;
u16 v_total, v_active, v_blank_start, v_blank_end, v_sync_start, v_sync_end;
int status = ufx_reg_write(dev, 0x8028, 0);
check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad");
status = ufx_reg_write(dev, 0x8024, 0);
check_warn_return(status, "ufx_set_vid_mode error disabling VDAC");
/* shut everything down before changing timing */
status = ufx_blank(dev, true);
check_warn_return(status, "ufx_set_vid_mode error blanking display");
status = ufx_disable(dev, true);
check_warn_return(status, "ufx_set_vid_mode error disabling display");
status = ufx_config_pix_clk(dev, var->pixclock);
check_warn_return(status, "ufx_set_vid_mode error configuring pixclock");
status = ufx_reg_write(dev, 0x2000, 0x00000104);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2000");
/* set horizontal timings */
h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
h_active = var->xres;
h_blank_start = var->xres + var->right_margin;
h_blank_end = var->xres + var->right_margin + var->hsync_len;
h_sync_start = var->xres + var->right_margin;
h_sync_end = var->xres + var->right_margin + var->hsync_len;
temp = ((h_total - 1) << 16) | (h_active - 1);
status = ufx_reg_write(dev, 0x2008, temp);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2008");
temp = ((h_blank_start - 1) << 16) | (h_blank_end - 1);
status = ufx_reg_write(dev, 0x200C, temp);
check_warn_return(status, "ufx_set_vid_mode error writing 0x200C");
temp = ((h_sync_start - 1) << 16) | (h_sync_end - 1);
status = ufx_reg_write(dev, 0x2010, temp);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2010");
/* set vertical timings */
v_total = var->upper_margin + var->yres + var->lower_margin + var->vsync_len;
v_active = var->yres;
v_blank_start = var->yres + var->lower_margin;
v_blank_end = var->yres + var->lower_margin + var->vsync_len;
v_sync_start = var->yres + var->lower_margin;
v_sync_end = var->yres + var->lower_margin + var->vsync_len;
temp = ((v_total - 1) << 16) | (v_active - 1);
status = ufx_reg_write(dev, 0x2014, temp);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2014");
temp = ((v_blank_start - 1) << 16) | (v_blank_end - 1);
status = ufx_reg_write(dev, 0x2018, temp);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2018");
temp = ((v_sync_start - 1) << 16) | (v_sync_end - 1);
status = ufx_reg_write(dev, 0x201C, temp);
check_warn_return(status, "ufx_set_vid_mode error writing 0x201C");
status = ufx_reg_write(dev, 0x2020, 0x00000000);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2020");
status = ufx_reg_write(dev, 0x2024, 0x00000000);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2024");
/* Set the frame length register (#pix * 2 bytes/pixel) */
temp = var->xres * var->yres * 2;
temp = (temp + 7) & (~0x7);
status = ufx_reg_write(dev, 0x2028, temp);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2028");
/* enable desired output interface & disable others */
status = ufx_reg_write(dev, 0x2040, 0);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
status = ufx_reg_write(dev, 0x2044, 0);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2044");
status = ufx_reg_write(dev, 0x2048, 0);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2048");
/* set the sync polarities & enable bit */
temp = 0x00000001;
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
temp |= 0x00000010;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
temp |= 0x00000008;
status = ufx_reg_write(dev, 0x2040, temp);
check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
/* start everything back up */
status = ufx_enable(dev, true);
check_warn_return(status, "ufx_set_vid_mode error enabling display");
/* Unblank the display */
status = ufx_unblank(dev, true);
check_warn_return(status, "ufx_set_vid_mode error unblanking display");
/* enable RGB pad */
status = ufx_reg_write(dev, 0x8028, 0x00000003);
check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad");
/* enable VDAC */
status = ufx_reg_write(dev, 0x8024, 0x00000007);
check_warn_return(status, "ufx_set_vid_mode error enabling VDAC");
return 0;
}
static int ufx_ops_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
unsigned long start = vma->vm_start;
unsigned long size = vma->vm_end - vma->vm_start;
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
unsigned long page, pos;
if (info->fbdefio)
return fb_deferred_io_mmap(info, vma);
if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
return -EINVAL;
if (size > info->fix.smem_len)
return -EINVAL;
if (offset > info->fix.smem_len - size)
return -EINVAL;
pos = (unsigned long)info->fix.smem_start + offset;
pr_debug("mmap() framebuffer addr:%lu size:%lu\n",
pos, size);
while (size > 0) {
page = vmalloc_to_pfn((void *)pos);
if (remap_pfn_range(vma, start, page, PAGE_SIZE, PAGE_SHARED))
return -EAGAIN;
start += PAGE_SIZE;
pos += PAGE_SIZE;
if (size > PAGE_SIZE)
size -= PAGE_SIZE;
else
size = 0;
}
return 0;
}
static void ufx_raw_rect(struct ufx_data *dev, u16 *cmd, int x, int y,
int width, int height)
{
size_t packed_line_len = ALIGN((width * 2), 4);
size_t packed_rect_len = packed_line_len * height;
int line;
BUG_ON(!dev);
BUG_ON(!dev->info);
/* command word */
*((u32 *)&cmd[0]) = cpu_to_le32(0x01);
/* length word */
*((u32 *)&cmd[2]) = cpu_to_le32(packed_rect_len + 16);
cmd[4] = cpu_to_le16(x);
cmd[5] = cpu_to_le16(y);
cmd[6] = cpu_to_le16(width);
cmd[7] = cpu_to_le16(height);
/* frame base address */
*((u32 *)&cmd[8]) = cpu_to_le32(0);
/* color mode and horizontal resolution */
cmd[10] = cpu_to_le16(0x4000 | dev->info->var.xres);
/* vertical resolution */
cmd[11] = cpu_to_le16(dev->info->var.yres);
/* packed data */
for (line = 0; line < height; line++) {
const int line_offset = dev->info->fix.line_length * (y + line);
const int byte_offset = line_offset + (x * BPP);
memcpy(&cmd[(24 + (packed_line_len * line)) / 2],
(char *)dev->info->fix.smem_start + byte_offset, width * BPP);
}
}
static int ufx_handle_damage(struct ufx_data *dev, int x, int y,
int width, int height)
{
size_t packed_line_len = ALIGN((width * 2), 4);
int len, status, urb_lines, start_line = 0;
if ((width <= 0) || (height <= 0) ||
(x + width > dev->info->var.xres) ||
(y + height > dev->info->var.yres))
return -EINVAL;
if (!atomic_read(&dev->usb_active))
return 0;
while (start_line < height) {
struct urb *urb = ufx_get_urb(dev);
if (!urb) {
pr_warn("ufx_handle_damage unable to get urb");
return 0;
}
/* assume we have enough space to transfer at least one line */
BUG_ON(urb->transfer_buffer_length < (24 + (width * 2)));
/* calculate the maximum number of lines we could fit in */
urb_lines = (urb->transfer_buffer_length - 24) / packed_line_len;
/* but we might not need this many */
urb_lines = min(urb_lines, (height - start_line));
memset(urb->transfer_buffer, 0, urb->transfer_buffer_length);
ufx_raw_rect(dev, urb->transfer_buffer, x, (y + start_line), width, urb_lines);
len = 24 + (packed_line_len * urb_lines);
status = ufx_submit_urb(dev, urb, len);
check_warn_return(status, "Error submitting URB");
start_line += urb_lines;
}
return 0;
}
/* Path triggered by usermode clients who write to filesystem
* e.g. cat filename > /dev/fb1
* Not used by X Windows or text-mode console. But useful for testing.
* Slow because of extra copy and we must assume all pixels dirty. */
static ssize_t ufx_ops_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos)
{
ssize_t result;
struct ufx_data *dev = info->par;
u32 offset = (u32) *ppos;
result = fb_sys_write(info, buf, count, ppos);
if (result > 0) {
int start = max((int)(offset / info->fix.line_length), 0);
int lines = min((u32)((result / info->fix.line_length) + 1),
(u32)info->var.yres);
ufx_handle_damage(dev, 0, start, info->var.xres, lines);
}
return result;
}
static void ufx_ops_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct ufx_data *dev = info->par;
sys_copyarea(info, area);
ufx_handle_damage(dev, area->dx, area->dy,
area->width, area->height);
}
static void ufx_ops_imageblit(struct fb_info *info,
const struct fb_image *image)
{
struct ufx_data *dev = info->par;
sys_imageblit(info, image);
ufx_handle_damage(dev, image->dx, image->dy,
image->width, image->height);
}
static void ufx_ops_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
struct ufx_data *dev = info->par;
sys_fillrect(info, rect);
ufx_handle_damage(dev, rect->dx, rect->dy, rect->width,
rect->height);
}
/* NOTE: fb_defio.c is holding info->fbdefio.mutex
* Touching ANY framebuffer memory that triggers a page fault
* in fb_defio will cause a deadlock, when it also tries to
* grab the same mutex. */
static void ufx_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist)
{
struct ufx_data *dev = info->par;
struct fb_deferred_io_pageref *pageref;
if (!fb_defio)
return;
if (!atomic_read(&dev->usb_active))
return;
/* walk the written page list and render each to device */
list_for_each_entry(pageref, pagereflist, list) {
/* create a rectangle of full screen width that encloses the
* entire dirty framebuffer page */
const int x = 0;
const int width = dev->info->var.xres;
const int y = pageref->offset / (width * 2);
int height = (PAGE_SIZE / (width * 2)) + 1;
height = min(height, (int)(dev->info->var.yres - y));
BUG_ON(y >= dev->info->var.yres);
BUG_ON((y + height) > dev->info->var.yres);
ufx_handle_damage(dev, x, y, width, height);
}
}
static int ufx_ops_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct ufx_data *dev = info->par;
struct dloarea *area = NULL;
if (!atomic_read(&dev->usb_active))
return 0;
/* TODO: Update X server to get this from sysfs instead */
if (cmd == UFX_IOCTL_RETURN_EDID) {
u8 __user *edid = (u8 __user *)arg;
if (copy_to_user(edid, dev->edid, dev->edid_size))
return -EFAULT;
return 0;
}
/* TODO: Help propose a standard fb.h ioctl to report mmap damage */
if (cmd == UFX_IOCTL_REPORT_DAMAGE) {
/* If we have a damage-aware client, turn fb_defio "off"
* To avoid perf imact of unnecessary page fault handling.
* Done by resetting the delay for this fb_info to a very
* long period. Pages will become writable and stay that way.
* Reset to normal value when all clients have closed this fb.
*/
if (info->fbdefio)
info->fbdefio->delay = UFX_DEFIO_WRITE_DISABLE;
area = (struct dloarea *)arg;
if (area->x < 0)
area->x = 0;
if (area->x > info->var.xres)
area->x = info->var.xres;
if (area->y < 0)
area->y = 0;
if (area->y > info->var.yres)
area->y = info->var.yres;
ufx_handle_damage(dev, area->x, area->y, area->w, area->h);
}
return 0;
}
/* taken from vesafb */
static int
ufx_ops_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
int err = 0;
if (regno >= info->cmap.len)
return 1;
if (regno < 16) {
if (info->var.red.offset == 10) {
/* 1:5:5:5 */
((u32 *) (info->pseudo_palette))[regno] =
((red & 0xf800) >> 1) |
((green & 0xf800) >> 6) | ((blue & 0xf800) >> 11);
} else {
/* 0:5:6:5 */
((u32 *) (info->pseudo_palette))[regno] =
((red & 0xf800)) |
((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
}
}
return err;
}
/* It's common for several clients to have framebuffer open simultaneously.
* e.g. both fbcon and X. Makes things interesting.
* Assumes caller is holding info->lock (for open and release at least) */
static int ufx_ops_open(struct fb_info *info, int user)
{
struct ufx_data *dev = info->par;
/* fbcon aggressively connects to first framebuffer it finds,
* preventing other clients (X) from working properly. Usually
* not what the user wants. Fail by default with option to enable. */
if (user == 0 && !console)
return -EBUSY;
mutex_lock(&disconnect_mutex);
/* If the USB device is gone, we don't accept new opens */
if (dev->virtualized) {
mutex_unlock(&disconnect_mutex);
return -ENODEV;
}
dev->fb_count++;
kref_get(&dev->kref);
if (fb_defio && (info->fbdefio == NULL)) {
/* enable defio at last moment if not disabled by client */
struct fb_deferred_io *fbdefio;
fbdefio = kzalloc(sizeof(*fbdefio), GFP_KERNEL);
if (fbdefio) {
fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
fbdefio->deferred_io = ufx_dpy_deferred_io;
}
info->fbdefio = fbdefio;
fb_deferred_io_init(info);
}
pr_debug("open /dev/fb%d user=%d fb_info=%p count=%d",
info->node, user, info, dev->fb_count);
mutex_unlock(&disconnect_mutex);
return 0;
}
/*
* Called when all client interfaces to start transactions have been disabled,
* and all references to our device instance (ufx_data) are released.
* Every transaction must have a reference, so we know are fully spun down
*/
static void ufx_free(struct kref *kref)
{
struct ufx_data *dev = container_of(kref, struct ufx_data, kref);
kfree(dev);
}
static void ufx_ops_destory(struct fb_info *info)
{
struct ufx_data *dev = info->par;
int node = info->node;
/* Assume info structure is freed after this point */
framebuffer_release(info);
pr_debug("fb_info for /dev/fb%d has been freed", node);
/* release reference taken by kref_init in probe() */
kref_put(&dev->kref, ufx_free);
}
static void ufx_release_urb_work(struct work_struct *work)
{
struct urb_node *unode = container_of(work, struct urb_node,
release_urb_work.work);
up(&unode->dev->urbs.limit_sem);
}
static void ufx_free_framebuffer(struct ufx_data *dev)
{
struct fb_info *info = dev->info;
if (info->cmap.len != 0)
fb_dealloc_cmap(&info->cmap);
if (info->monspecs.modedb)
fb_destroy_modedb(info->monspecs.modedb);
vfree(info->screen_buffer);
fb_destroy_modelist(&info->modelist);
dev->info = NULL;
/* ref taken in probe() as part of registering framebfufer */
kref_put(&dev->kref, ufx_free);
}
/*
* Assumes caller is holding info->lock mutex (for open and release at least)
*/
static int ufx_ops_release(struct fb_info *info, int user)
{
struct ufx_data *dev = info->par;
mutex_lock(&disconnect_mutex);
dev->fb_count--;
/* We can't free fb_info here - fbmem will touch it when we return */
if (dev->virtualized && (dev->fb_count == 0))
ufx_free_framebuffer(dev);
if ((dev->fb_count == 0) && (info->fbdefio)) {
fb_deferred_io_cleanup(info);
kfree(info->fbdefio);
info->fbdefio = NULL;
}
pr_debug("released /dev/fb%d user=%d count=%d",
info->node, user, dev->fb_count);
kref_put(&dev->kref, ufx_free);
mutex_unlock(&disconnect_mutex);
return 0;
}
/* Check whether a video mode is supported by the chip
* We start from monitor's modes, so don't need to filter that here */
static int ufx_is_valid_mode(struct fb_videomode *mode,
struct fb_info *info)
{
if ((mode->xres * mode->yres) > (2048 * 1152)) {
pr_debug("%dx%d too many pixels",
mode->xres, mode->yres);
return 0;
}
if (mode->pixclock < 5000) {
pr_debug("%dx%d %dps pixel clock too fast",
mode->xres, mode->yres, mode->pixclock);
return 0;
}
pr_debug("%dx%d (pixclk %dps %dMHz) valid mode", mode->xres, mode->yres,
mode->pixclock, (1000000 / mode->pixclock));
return 1;
}
static void ufx_var_color_format(struct fb_var_screeninfo *var)
{
const struct fb_bitfield red = { 11, 5, 0 };
const struct fb_bitfield green = { 5, 6, 0 };
const struct fb_bitfield blue = { 0, 5, 0 };
var->bits_per_pixel = 16;
var->red = red;
var->green = green;
var->blue = blue;
}
static int ufx_ops_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct fb_videomode mode;
/* TODO: support dynamically changing framebuffer size */
if ((var->xres * var->yres * 2) > info->fix.smem_len)
return -EINVAL;
/* set device-specific elements of var unrelated to mode */
ufx_var_color_format(var);
fb_var_to_videomode(&mode, var);
if (!ufx_is_valid_mode(&mode, info))
return -EINVAL;
return 0;
}
static int ufx_ops_set_par(struct fb_info *info)
{
struct ufx_data *dev = info->par;
int result;
u16 *pix_framebuffer;
int i;
pr_debug("set_par mode %dx%d", info->var.xres, info->var.yres);
result = ufx_set_vid_mode(dev, &info->var);
if ((result == 0) && (dev->fb_count == 0)) {
/* paint greenscreen */
pix_framebuffer = (u16 *)info->screen_buffer;
for (i = 0; i < info->fix.smem_len / 2; i++)
pix_framebuffer[i] = 0x37e6;
ufx_handle_damage(dev, 0, 0, info->var.xres, info->var.yres);
}
/* re-enable defio if previously disabled by damage tracking */
if (info->fbdefio)
info->fbdefio->delay = UFX_DEFIO_WRITE_DELAY;
return result;
}
/* In order to come back from full DPMS off, we need to set the mode again */
static int ufx_ops_blank(int blank_mode, struct fb_info *info)
{
struct ufx_data *dev = info->par;
ufx_set_vid_mode(dev, &info->var);
return 0;
}
static const struct fb_ops ufx_ops = {
.owner = THIS_MODULE,
.fb_read = fb_sys_read,
.fb_write = ufx_ops_write,
.fb_setcolreg = ufx_ops_setcolreg,
.fb_fillrect = ufx_ops_fillrect,
.fb_copyarea = ufx_ops_copyarea,
.fb_imageblit = ufx_ops_imageblit,
.fb_mmap = ufx_ops_mmap,
.fb_ioctl = ufx_ops_ioctl,
.fb_open = ufx_ops_open,
.fb_release = ufx_ops_release,
.fb_blank = ufx_ops_blank,
.fb_check_var = ufx_ops_check_var,
.fb_set_par = ufx_ops_set_par,
.fb_destroy = ufx_ops_destory,
};
/* Assumes &info->lock held by caller
* Assumes no active clients have framebuffer open */
static int ufx_realloc_framebuffer(struct ufx_data *dev, struct fb_info *info)
{
int old_len = info->fix.smem_len;
int new_len;
unsigned char *old_fb = info->screen_buffer;
unsigned char *new_fb;
pr_debug("Reallocating framebuffer. Addresses will change!");
new_len = info->fix.line_length * info->var.yres;
if (PAGE_ALIGN(new_len) > old_len) {
/*
* Alloc system memory for virtual framebuffer
*/
new_fb = vmalloc(new_len);
if (!new_fb)
return -ENOMEM;
if (info->screen_buffer) {
memcpy(new_fb, old_fb, old_len);
vfree(info->screen_buffer);
}
info->screen_buffer = new_fb;
info->fix.smem_len = PAGE_ALIGN(new_len);
info->fix.smem_start = (unsigned long) new_fb;
info->flags = smscufx_info_flags;
}
return 0;
}
/* sets up I2C Controller for 100 Kbps, std. speed, 7-bit addr, master,
* restart enabled, but no start byte, enable controller */
static int ufx_i2c_init(struct ufx_data *dev)
{
u32 tmp;
/* disable the controller before it can be reprogrammed */
int status = ufx_reg_write(dev, 0x106C, 0x00);
check_warn_return(status, "failed to disable I2C");
/* Setup the clock count registers
* (12+1) = 13 clks @ 2.5 MHz = 5.2 uS */
status = ufx_reg_write(dev, 0x1018, 12);
check_warn_return(status, "error writing 0x1018");
/* (6+8) = 14 clks @ 2.5 MHz = 5.6 uS */
status = ufx_reg_write(dev, 0x1014, 6);
check_warn_return(status, "error writing 0x1014");
status = ufx_reg_read(dev, 0x1000, &tmp);
check_warn_return(status, "error reading 0x1000");
/* set speed to std mode */
tmp &= ~(0x06);
tmp |= 0x02;
/* 7-bit (not 10-bit) addressing */
tmp &= ~(0x10);
/* enable restart conditions and master mode */
tmp |= 0x21;
status = ufx_reg_write(dev, 0x1000, tmp);
check_warn_return(status, "error writing 0x1000");
/* Set normal tx using target address 0 */
status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000);
check_warn_return(status, "error setting TX mode bits in 0x1004");
/* Enable the controller */
status = ufx_reg_write(dev, 0x106C, 0x01);
check_warn_return(status, "failed to enable I2C");
return 0;
}
/* sets the I2C port mux and target address */
static int ufx_i2c_configure(struct ufx_data *dev)
{
int status = ufx_reg_write(dev, 0x106C, 0x00);
check_warn_return(status, "failed to disable I2C");
status = ufx_reg_write(dev, 0x3010, 0x00000000);
check_warn_return(status, "failed to write 0x3010");
/* A0h is std for any EDID, right shifted by one */
status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1));
check_warn_return(status, "failed to set TAR bits in 0x1004");
status = ufx_reg_write(dev, 0x106C, 0x01);
check_warn_return(status, "failed to enable I2C");
return 0;
}
/* wait for BUSY to clear, with a timeout of 50ms with 10ms sleeps. if no
* monitor is connected, there is no error except for timeout */
static int ufx_i2c_wait_busy(struct ufx_data *dev)
{
u32 tmp;
int i, status;
for (i = 0; i < 15; i++) {
status = ufx_reg_read(dev, 0x1100, &tmp);
check_warn_return(status, "0x1100 read failed");
/* if BUSY is clear, check for error */
if ((tmp & 0x80000000) == 0) {
if (tmp & 0x20000000) {
pr_warn("I2C read failed, 0x1100=0x%08x", tmp);
return -EIO;
}
return 0;
}
/* perform the first 10 retries without delay */
if (i >= 10)
msleep(10);
}
pr_warn("I2C access timed out, resetting I2C hardware");
status = ufx_reg_write(dev, 0x1100, 0x40000000);
check_warn_return(status, "0x1100 write failed");
return -ETIMEDOUT;
}
/* reads a 128-byte EDID block from the currently selected port and TAR */
static int ufx_read_edid(struct ufx_data *dev, u8 *edid, int edid_len)
{
int i, j, status;
u32 *edid_u32 = (u32 *)edid;
BUG_ON(edid_len != EDID_LENGTH);
status = ufx_i2c_configure(dev);
if (status < 0) {
pr_err("ufx_i2c_configure failed");
return status;
}
memset(edid, 0xff, EDID_LENGTH);
/* Read the 128-byte EDID as 2 bursts of 64 bytes */
for (i = 0; i < 2; i++) {
u32 temp = 0x28070000 | (63 << 20) | (((u32)(i * 64)) << 8);
status = ufx_reg_write(dev, 0x1100, temp);
check_warn_return(status, "Failed to write 0x1100");
temp |= 0x80000000;
status = ufx_reg_write(dev, 0x1100, temp);
check_warn_return(status, "Failed to write 0x1100");
status = ufx_i2c_wait_busy(dev);
check_warn_return(status, "Timeout waiting for I2C BUSY to clear");
for (j = 0; j < 16; j++) {
u32 data_reg_addr = 0x1110 + (j * 4);
status = ufx_reg_read(dev, data_reg_addr, edid_u32++);
check_warn_return(status, "Error reading i2c data");
}
}
/* all FF's in the first 16 bytes indicates nothing is connected */
for (i = 0; i < 16; i++) {
if (edid[i] != 0xFF) {
pr_debug("edid data read successfully");
return EDID_LENGTH;
}
}
pr_warn("edid data contains all 0xff");
return -ETIMEDOUT;
}
/* 1) use sw default
* 2) Parse into various fb_info structs
* 3) Allocate virtual framebuffer memory to back highest res mode
*
* Parses EDID into three places used by various parts of fbdev:
* fb_var_screeninfo contains the timing of the monitor's preferred mode
* fb_info.monspecs is full parsed EDID info, including monspecs.modedb
* fb_info.modelist is a linked list of all monitor & VESA modes which work
*
* If EDID is not readable/valid, then modelist is all VESA modes,
* monspecs is NULL, and fb_var_screeninfo is set to safe VESA mode
* Returns 0 if successful */
static int ufx_setup_modes(struct ufx_data *dev, struct fb_info *info,
char *default_edid, size_t default_edid_size)
{
const struct fb_videomode *default_vmode = NULL;
u8 *edid;
int i, result = 0, tries = 3;
if (refcount_read(&info->count)) /* only use mutex if info has been registered */
mutex_lock(&info->lock);
edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
if (!edid) {
result = -ENOMEM;
goto error;
}
fb_destroy_modelist(&info->modelist);
memset(&info->monspecs, 0, sizeof(info->monspecs));
/* Try to (re)read EDID from hardware first
* EDID data may return, but not parse as valid
* Try again a few times, in case of e.g. analog cable noise */
while (tries--) {
i = ufx_read_edid(dev, edid, EDID_LENGTH);
if (i >= EDID_LENGTH)
fb_edid_to_monspecs(edid, &info->monspecs);
if (info->monspecs.modedb_len > 0) {
dev->edid = edid;
dev->edid_size = i;
break;
}
}
/* If that fails, use a previously returned EDID if available */
if (info->monspecs.modedb_len == 0) {
pr_err("Unable to get valid EDID from device/display\n");
if (dev->edid) {
fb_edid_to_monspecs(dev->edid, &info->monspecs);
if (info->monspecs.modedb_len > 0)
pr_err("Using previously queried EDID\n");
}
}
/* If that fails, use the default EDID we were handed */
if (info->monspecs.modedb_len == 0) {
if (default_edid_size >= EDID_LENGTH) {
fb_edid_to_monspecs(default_edid, &info->monspecs);
if (info->monspecs.modedb_len > 0) {
memcpy(edid, default_edid, default_edid_size);
dev->edid = edid;
dev->edid_size = default_edid_size;
pr_err("Using default/backup EDID\n");
}
}
}
/* If we've got modes, let's pick a best default mode */
if (info->monspecs.modedb_len > 0) {
for (i = 0; i < info->monspecs.modedb_len; i++) {
if (ufx_is_valid_mode(&info->monspecs.modedb[i], info))
fb_add_videomode(&info->monspecs.modedb[i],
&info->modelist);
else /* if we've removed top/best mode */
info->monspecs.misc &= ~FB_MISC_1ST_DETAIL;
}
default_vmode = fb_find_best_display(&info->monspecs,
&info->modelist);
}
/* If everything else has failed, fall back to safe default mode */
if (default_vmode == NULL) {
struct fb_videomode fb_vmode = {0};
/* Add the standard VESA modes to our modelist
* Since we don't have EDID, there may be modes that
* overspec monitor and/or are incorrect aspect ratio, etc.
* But at least the user has a chance to choose
*/
for (i = 0; i < VESA_MODEDB_SIZE; i++) {
if (ufx_is_valid_mode((struct fb_videomode *)
&vesa_modes[i], info))
fb_add_videomode(&vesa_modes[i],
&info->modelist);
}
/* default to resolution safe for projectors
* (since they are most common case without EDID)
*/
fb_vmode.xres = 800;
fb_vmode.yres = 600;
fb_vmode.refresh = 60;
default_vmode = fb_find_nearest_mode(&fb_vmode,
&info->modelist);
}
/* If we have good mode and no active clients */
if ((default_vmode != NULL) && (dev->fb_count == 0)) {
fb_videomode_to_var(&info->var, default_vmode);
ufx_var_color_format(&info->var);
/* with mode size info, we can now alloc our framebuffer */
memcpy(&info->fix, &ufx_fix, sizeof(ufx_fix));
info->fix.line_length = info->var.xres *
(info->var.bits_per_pixel / 8);
result = ufx_realloc_framebuffer(dev, info);
} else
result = -EINVAL;
error:
if (edid && (dev->edid != edid))
kfree(edid);
if (refcount_read(&info->count))
mutex_unlock(&info->lock);
return result;
}
static int ufx_usb_probe(struct usb_interface *interface,
const struct usb_device_id *id)
{
struct usb_device *usbdev;
struct ufx_data *dev;
struct fb_info *info;
int retval = -ENOMEM;
u32 id_rev, fpga_rev;
/* usb initialization */
usbdev = interface_to_usbdev(interface);
BUG_ON(!usbdev);
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
if (dev == NULL) {
dev_err(&usbdev->dev, "ufx_usb_probe: failed alloc of dev struct\n");
return -ENOMEM;
}
/* we need to wait for both usb and fbdev to spin down on disconnect */
kref_init(&dev->kref); /* matching kref_put in usb .disconnect fn */
kref_get(&dev->kref); /* matching kref_put in free_framebuffer_work */
dev->udev = usbdev;
dev->gdev = &usbdev->dev; /* our generic struct device * */
usb_set_intfdata(interface, dev);
dev_dbg(dev->gdev, "%s %s - serial #%s\n",
usbdev->manufacturer, usbdev->product, usbdev->serial);
dev_dbg(dev->gdev, "vid_%04x&pid_%04x&rev_%04x driver's ufx_data struct at %p\n",
le16_to_cpu(usbdev->descriptor.idVendor),
le16_to_cpu(usbdev->descriptor.idProduct),
le16_to_cpu(usbdev->descriptor.bcdDevice), dev);
dev_dbg(dev->gdev, "console enable=%d\n", console);
dev_dbg(dev->gdev, "fb_defio enable=%d\n", fb_defio);
if (!ufx_alloc_urb_list(dev, WRITES_IN_FLIGHT, MAX_TRANSFER)) {
dev_err(dev->gdev, "ufx_alloc_urb_list failed\n");
goto put_ref;
}
/* We don't register a new USB class. Our client interface is fbdev */
/* allocates framebuffer driver structure, not framebuffer memory */
info = framebuffer_alloc(0, &usbdev->dev);
if (!info) {
dev_err(dev->gdev, "framebuffer_alloc failed\n");
goto free_urb_list;
}
dev->info = info;
info->par = dev;
info->pseudo_palette = dev->pseudo_palette;
info->fbops = &ufx_ops;
INIT_LIST_HEAD(&info->modelist);
retval = fb_alloc_cmap(&info->cmap, 256, 0);
if (retval < 0) {
dev_err(dev->gdev, "fb_alloc_cmap failed %x\n", retval);
goto destroy_modedb;
}
retval = ufx_reg_read(dev, 0x3000, &id_rev);
check_warn_goto_error(retval, "error %d reading 0x3000 register from device", retval);
dev_dbg(dev->gdev, "ID_REV register value 0x%08x", id_rev);
retval = ufx_reg_read(dev, 0x3004, &fpga_rev);
check_warn_goto_error(retval, "error %d reading 0x3004 register from device", retval);
dev_dbg(dev->gdev, "FPGA_REV register value 0x%08x", fpga_rev);
dev_dbg(dev->gdev, "resetting device");
retval = ufx_lite_reset(dev);
check_warn_goto_error(retval, "error %d resetting device", retval);
dev_dbg(dev->gdev, "configuring system clock");
retval = ufx_config_sys_clk(dev);
check_warn_goto_error(retval, "error %d configuring system clock", retval);
dev_dbg(dev->gdev, "configuring DDR2 controller");
retval = ufx_config_ddr2(dev);
check_warn_goto_error(retval, "error %d initialising DDR2 controller", retval);
dev_dbg(dev->gdev, "configuring I2C controller");
retval = ufx_i2c_init(dev);
check_warn_goto_error(retval, "error %d initialising I2C controller", retval);
dev_dbg(dev->gdev, "selecting display mode");
retval = ufx_setup_modes(dev, info, NULL, 0);
check_warn_goto_error(retval, "unable to find common mode for display and adapter");
retval = ufx_reg_set_bits(dev, 0x4000, 0x00000001);
if (retval < 0) {
dev_err(dev->gdev, "error %d enabling graphics engine", retval);
goto setup_modes;
}
/* ready to begin using device */
atomic_set(&dev->usb_active, 1);
dev_dbg(dev->gdev, "checking var");
retval = ufx_ops_check_var(&info->var, info);
if (retval < 0) {
dev_err(dev->gdev, "error %d ufx_ops_check_var", retval);
goto reset_active;
}
dev_dbg(dev->gdev, "setting par");
retval = ufx_ops_set_par(info);
if (retval < 0) {
dev_err(dev->gdev, "error %d ufx_ops_set_par", retval);
goto reset_active;
}
dev_dbg(dev->gdev, "registering framebuffer");
retval = register_framebuffer(info);
if (retval < 0) {
dev_err(dev->gdev, "error %d register_framebuffer", retval);
goto reset_active;
}
dev_info(dev->gdev, "SMSC UDX USB device /dev/fb%d attached. %dx%d resolution."
" Using %dK framebuffer memory\n", info->node,
info->var.xres, info->var.yres, info->fix.smem_len >> 10);
return 0;
reset_active:
atomic_set(&dev->usb_active, 0);
setup_modes:
fb_destroy_modedb(info->monspecs.modedb);
vfree(info->screen_buffer);
fb_destroy_modelist(&info->modelist);
error:
fb_dealloc_cmap(&info->cmap);
destroy_modedb:
framebuffer_release(info);
free_urb_list:
if (dev->urbs.count > 0)
ufx_free_urb_list(dev);
put_ref:
kref_put(&dev->kref, ufx_free); /* ref for framebuffer */
kref_put(&dev->kref, ufx_free); /* last ref from kref_init */
return retval;
}
static void ufx_usb_disconnect(struct usb_interface *interface)
{
struct ufx_data *dev;
struct fb_info *info;
mutex_lock(&disconnect_mutex);
dev = usb_get_intfdata(interface);
info = dev->info;
pr_debug("USB disconnect starting\n");
/* we virtualize until all fb clients release. Then we free */
dev->virtualized = true;
/* When non-active we'll update virtual framebuffer, but no new urbs */
atomic_set(&dev->usb_active, 0);
usb_set_intfdata(interface, NULL);
/* if clients still have us open, will be freed on last close */
if (dev->fb_count == 0)
ufx_free_framebuffer(dev);
/* this function will wait for all in-flight urbs to complete */
if (dev->urbs.count > 0)
ufx_free_urb_list(dev);
pr_debug("freeing ufx_data %p", dev);
unregister_framebuffer(info);
mutex_unlock(&disconnect_mutex);
}
static struct usb_driver ufx_driver = {
.name = "smscufx",
.probe = ufx_usb_probe,
.disconnect = ufx_usb_disconnect,
.id_table = id_table,
};
module_usb_driver(ufx_driver);
static void ufx_urb_completion(struct urb *urb)
{
struct urb_node *unode = urb->context;
struct ufx_data *dev = unode->dev;
unsigned long flags;
/* sync/async unlink faults aren't errors */
if (urb->status) {
if (!(urb->status == -ENOENT ||
urb->status == -ECONNRESET ||
urb->status == -ESHUTDOWN)) {
pr_err("%s - nonzero write bulk status received: %d\n",
__func__, urb->status);
atomic_set(&dev->lost_pixels, 1);
}
}
urb->transfer_buffer_length = dev->urbs.size; /* reset to actual */
spin_lock_irqsave(&dev->urbs.lock, flags);
list_add_tail(&unode->entry, &dev->urbs.list);
dev->urbs.available++;
spin_unlock_irqrestore(&dev->urbs.lock, flags);
/* When using fb_defio, we deadlock if up() is called
* while another is waiting. So queue to another process */
if (fb_defio)
schedule_delayed_work(&unode->release_urb_work, 0);
else
up(&dev->urbs.limit_sem);
}
static void ufx_free_urb_list(struct ufx_data *dev)
{
int count = dev->urbs.count;
struct list_head *node;
struct urb_node *unode;
struct urb *urb;
int ret;
unsigned long flags;
pr_debug("Waiting for completes and freeing all render urbs\n");
/* keep waiting and freeing, until we've got 'em all */
while (count--) {
/* Getting interrupted means a leak, but ok at shutdown*/
ret = down_interruptible(&dev->urbs.limit_sem);
if (ret)
break;
spin_lock_irqsave(&dev->urbs.lock, flags);
node = dev->urbs.list.next; /* have reserved one with sem */
list_del_init(node);
spin_unlock_irqrestore(&dev->urbs.lock, flags);
unode = list_entry(node, struct urb_node, entry);
urb = unode->urb;
/* Free each separately allocated piece */
usb_free_coherent(urb->dev, dev->urbs.size,
urb->transfer_buffer, urb->transfer_dma);
usb_free_urb(urb);
kfree(node);
}
}
static int ufx_alloc_urb_list(struct ufx_data *dev, int count, size_t size)
{
int i = 0;
struct urb *urb;
struct urb_node *unode;
char *buf;
spin_lock_init(&dev->urbs.lock);
dev->urbs.size = size;
INIT_LIST_HEAD(&dev->urbs.list);
while (i < count) {
unode = kzalloc(sizeof(*unode), GFP_KERNEL);
if (!unode)
break;
unode->dev = dev;
INIT_DELAYED_WORK(&unode->release_urb_work,
ufx_release_urb_work);
urb = usb_alloc_urb(0, GFP_KERNEL);
if (!urb) {
kfree(unode);
break;
}
unode->urb = urb;
buf = usb_alloc_coherent(dev->udev, size, GFP_KERNEL,
&urb->transfer_dma);
if (!buf) {
kfree(unode);
usb_free_urb(urb);
break;
}
/* urb->transfer_buffer_length set to actual before submit */
usb_fill_bulk_urb(urb, dev->udev, usb_sndbulkpipe(dev->udev, 1),
buf, size, ufx_urb_completion, unode);
urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
list_add_tail(&unode->entry, &dev->urbs.list);
i++;
}
sema_init(&dev->urbs.limit_sem, i);
dev->urbs.count = i;
dev->urbs.available = i;
pr_debug("allocated %d %d byte urbs\n", i, (int) size);
return i;
}
static struct urb *ufx_get_urb(struct ufx_data *dev)
{
int ret = 0;
struct list_head *entry;
struct urb_node *unode;
struct urb *urb = NULL;
unsigned long flags;
/* Wait for an in-flight buffer to complete and get re-queued */
ret = down_timeout(&dev->urbs.limit_sem, GET_URB_TIMEOUT);
if (ret) {
atomic_set(&dev->lost_pixels, 1);
pr_warn("wait for urb interrupted: %x available: %d\n",
ret, dev->urbs.available);
goto error;
}
spin_lock_irqsave(&dev->urbs.lock, flags);
BUG_ON(list_empty(&dev->urbs.list)); /* reserved one with limit_sem */
entry = dev->urbs.list.next;
list_del_init(entry);
dev->urbs.available--;
spin_unlock_irqrestore(&dev->urbs.lock, flags);
unode = list_entry(entry, struct urb_node, entry);
urb = unode->urb;
error:
return urb;
}
static int ufx_submit_urb(struct ufx_data *dev, struct urb *urb, size_t len)
{
int ret;
BUG_ON(len > dev->urbs.size);
urb->transfer_buffer_length = len; /* set to actual payload len */
ret = usb_submit_urb(urb, GFP_KERNEL);
if (ret) {
ufx_urb_completion(urb); /* because no one else will */
atomic_set(&dev->lost_pixels, 1);
pr_err("usb_submit_urb error %x\n", ret);
}
return ret;
}
module_param(console, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
MODULE_PARM_DESC(console, "Allow fbcon to be used on this display");
module_param(fb_defio, bool, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
MODULE_PARM_DESC(fb_defio, "Enable fb_defio mmap support");
MODULE_AUTHOR("Steve Glendinning <[email protected]>");
MODULE_DESCRIPTION("SMSC UFX kernel framebuffer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/smscufx.c |
/*
* linux/drivers/video/maxinefb.c
*
* DECstation 5000/xx onboard framebuffer support ... derived from:
* "HP300 Topcat framebuffer support (derived from macfb of all things)
* Phil Blundell <[email protected]> 1998", the original code can be
* found in the file hpfb.c in the same directory.
*
* DECstation related code Copyright (C) 1999,2000,2001 by
* Michael Engel <[email protected]> and
* Karsten Merker <[email protected]>.
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
*/
/*
* Changes:
* 2001/01/27 removed debugging and testing code, fixed fb_ops
* initialization which had caused a crash before,
* general cleanup, first official release (KM)
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <video/maxinefb.h>
/* bootinfo.h defines the machine type values, needed when checking */
/* whether are really running on a maxine, KM */
#include <asm/bootinfo.h>
static struct fb_info fb_info;
static const struct fb_var_screeninfo maxinefb_defined = {
.xres = 1024,
.yres = 768,
.xres_virtual = 1024,
.yres_virtual = 768,
.bits_per_pixel =8,
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_fix_screeninfo maxinefb_fix __initdata = {
.id = "Maxine",
.smem_len = (1024*768),
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.line_length = 1024,
};
/* Handle the funny Inmos RamDAC/video controller ... */
void maxinefb_ims332_write_register(int regno, register unsigned int val)
{
register unsigned char *regs = (char *) MAXINEFB_IMS332_ADDRESS;
unsigned char *wptr;
wptr = regs + 0xa0000 + (regno << 4);
*((volatile unsigned int *) (regs)) = (val >> 8) & 0xff00;
*((volatile unsigned short *) (wptr)) = val;
}
unsigned int maxinefb_ims332_read_register(int regno)
{
register unsigned char *regs = (char *) MAXINEFB_IMS332_ADDRESS;
unsigned char *rptr;
register unsigned int j, k;
rptr = regs + 0x80000 + (regno << 4);
j = *((volatile unsigned short *) rptr);
k = *((volatile unsigned short *) regs);
return (j & 0xffff) | ((k & 0xff00) << 8);
}
/* Set the palette */
static int maxinefb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
/* value to be written into the palette reg. */
unsigned long hw_colorvalue = 0;
if (regno > 255)
return 1;
red >>= 8; /* The cmap fields are 16 bits */
green >>= 8; /* wide, but the harware colormap */
blue >>= 8; /* registers are only 8 bits wide */
hw_colorvalue = (blue << 16) + (green << 8) + (red);
maxinefb_ims332_write_register(IMS332_REG_COLOR_PALETTE + regno,
hw_colorvalue);
return 0;
}
static const struct fb_ops maxinefb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = maxinefb_setcolreg,
};
int __init maxinefb_init(void)
{
unsigned long fboff;
unsigned long fb_start;
int i;
if (fb_get_options("maxinefb", NULL))
return -ENODEV;
/* Validate we're on the proper machine type */
if (mips_machtype != MACH_DS5000_XX) {
return -EINVAL;
}
printk(KERN_INFO "Maxinefb: Personal DECstation detected\n");
printk(KERN_INFO "Maxinefb: initializing onboard framebuffer\n");
/* Framebuffer display memory base address */
fb_start = DS5000_xx_ONBOARD_FBMEM_START;
/* Clear screen */
for (fboff = fb_start; fboff < fb_start + 0x1ffff; fboff++)
*(volatile unsigned char *)fboff = 0x0;
maxinefb_fix.smem_start = fb_start;
/* erase hardware cursor */
for (i = 0; i < 512; i++) {
maxinefb_ims332_write_register(IMS332_REG_CURSOR_RAM + i,
0);
/*
if (i&0x8 == 0)
maxinefb_ims332_write_register (IMS332_REG_CURSOR_RAM + i, 0x0f);
else
maxinefb_ims332_write_register (IMS332_REG_CURSOR_RAM + i, 0xf0);
*/
}
fb_info.fbops = &maxinefb_ops;
fb_info.screen_base = (char *)maxinefb_fix.smem_start;
fb_info.var = maxinefb_defined;
fb_info.fix = maxinefb_fix;
fb_alloc_cmap(&fb_info.cmap, 256, 0);
if (register_framebuffer(&fb_info) < 0)
return 1;
return 0;
}
static void __exit maxinefb_exit(void)
{
unregister_framebuffer(&fb_info);
}
#ifdef MODULE
MODULE_LICENSE("GPL");
#endif
module_init(maxinefb_init);
module_exit(maxinefb_exit);
| linux-master | drivers/video/fbdev/maxinefb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Frame buffer driver for the Carmine GPU.
*
* The driver configures the GPU as follows
* - FB0 is display 0 with unique memory area
* - FB1 is display 1 with unique memory area
* - both display use 32 bit colors
*/
#include <linux/aperture.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/module.h>
#include "carminefb.h"
#include "carminefb_regs.h"
#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
#error "The endianness of the target host has not been defined."
#endif
/*
* The initial video mode can be supplied via two different ways:
* - as a string that is passed to fb_find_mode() (module option fb_mode_str)
* - as an integer that picks the video mode from carmine_modedb[] (module
* option fb_mode)
*
* If nothing is used than the initial video mode will be the
* CARMINEFB_DEFAULT_VIDEO_MODE member of the carmine_modedb[].
*/
#define CARMINEFB_DEFAULT_VIDEO_MODE 1
static unsigned int fb_mode = CARMINEFB_DEFAULT_VIDEO_MODE;
module_param(fb_mode, uint, 0444);
MODULE_PARM_DESC(fb_mode, "Initial video mode as integer.");
static char *fb_mode_str;
module_param(fb_mode_str, charp, 0444);
MODULE_PARM_DESC(fb_mode_str, "Initial video mode in characters.");
/*
* Carminefb displays:
* 0b000 None
* 0b001 Display 0
* 0b010 Display 1
*/
static int fb_displays = CARMINE_USE_DISPLAY0 | CARMINE_USE_DISPLAY1;
module_param(fb_displays, int, 0444);
MODULE_PARM_DESC(fb_displays, "Bit mode, which displays are used");
struct carmine_hw {
void __iomem *v_regs;
void __iomem *screen_mem;
struct fb_info *fb[MAX_DISPLAY];
};
struct carmine_resolution {
u32 htp;
u32 hsp;
u32 hsw;
u32 hdp;
u32 vtr;
u32 vsp;
u32 vsw;
u32 vdp;
u32 disp_mode;
};
struct carmine_fb {
void __iomem *display_reg;
void __iomem *screen_base;
u32 smem_offset;
u32 cur_mode;
u32 new_mode;
struct carmine_resolution *res;
u32 pseudo_palette[16];
};
static struct fb_fix_screeninfo carminefb_fix = {
.id = "Carmine",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.accel = FB_ACCEL_NONE,
};
static const struct fb_videomode carmine_modedb[] = {
{
.name = "640x480",
.xres = 640,
.yres = 480,
}, {
.name = "800x600",
.xres = 800,
.yres = 600,
},
};
static struct carmine_resolution car_modes[] = {
{
/* 640x480 */
.htp = 800,
.hsp = 672,
.hsw = 96,
.hdp = 640,
.vtr = 525,
.vsp = 490,
.vsw = 2,
.vdp = 480,
.disp_mode = 0x1400,
},
{
/* 800x600 */
.htp = 1060,
.hsp = 864,
.hsw = 72,
.hdp = 800,
.vtr = 628,
.vsp = 601,
.vsw = 2,
.vdp = 600,
.disp_mode = 0x0d00,
}
};
static int carmine_find_mode(const struct fb_var_screeninfo *var)
{
int i;
for (i = 0; i < ARRAY_SIZE(car_modes); i++)
if (car_modes[i].hdp == var->xres &&
car_modes[i].vdp == var->yres)
return i;
return -EINVAL;
}
static void c_set_disp_reg(const struct carmine_fb *par,
u32 offset, u32 val)
{
writel(val, par->display_reg + offset);
}
static u32 c_get_disp_reg(const struct carmine_fb *par,
u32 offset)
{
return readl(par->display_reg + offset);
}
static void c_set_hw_reg(const struct carmine_hw *hw,
u32 offset, u32 val)
{
writel(val, hw->v_regs + offset);
}
static u32 c_get_hw_reg(const struct carmine_hw *hw,
u32 offset)
{
return readl(hw->v_regs + offset);
}
static int carmine_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
if (regno >= 16)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
transp >>= 8;
((__be32 *)info->pseudo_palette)[regno] = cpu_to_be32(transp << 24 |
red << 0 | green << 8 | blue << 16);
return 0;
}
static int carmine_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int ret;
ret = carmine_find_mode(var);
if (ret < 0)
return ret;
if (var->grayscale || var->rotate || var->nonstd)
return -EINVAL;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->bits_per_pixel = 32;
#ifdef __BIG_ENDIAN
var->transp.offset = 24;
var->red.offset = 0;
var->green.offset = 8;
var->blue.offset = 16;
#else
var->transp.offset = 24;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
#endif
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.length = 8;
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
return 0;
}
static void carmine_init_display_param(struct carmine_fb *par)
{
u32 width;
u32 height;
u32 param;
u32 window_size;
u32 soffset = par->smem_offset;
c_set_disp_reg(par, CARMINE_DISP_REG_C_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_MLMR_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_CURSOR_MODE,
CARMINE_CURSOR0_PRIORITY_MASK |
CARMINE_CURSOR1_PRIORITY_MASK |
CARMINE_CURSOR_CUTZ_MASK);
/* Set default cursor position */
c_set_disp_reg(par, CARMINE_DISP_REG_CUR1_POS, 0 << 16 | 0);
c_set_disp_reg(par, CARMINE_DISP_REG_CUR2_POS, 0 << 16 | 0);
/* Set default display mode */
c_set_disp_reg(par, CARMINE_DISP_REG_L0_EXT_MODE, CARMINE_WINDOW_MODE |
CARMINE_EXT_CMODE_DIRECT24_RGBA);
c_set_disp_reg(par, CARMINE_DISP_REG_L1_EXT_MODE,
CARMINE_EXT_CMODE_DIRECT24_RGBA);
c_set_disp_reg(par, CARMINE_DISP_REG_L2_EXT_MODE, CARMINE_EXTEND_MODE |
CARMINE_EXT_CMODE_DIRECT24_RGBA);
c_set_disp_reg(par, CARMINE_DISP_REG_L3_EXT_MODE, CARMINE_EXTEND_MODE |
CARMINE_EXT_CMODE_DIRECT24_RGBA);
c_set_disp_reg(par, CARMINE_DISP_REG_L4_EXT_MODE, CARMINE_EXTEND_MODE |
CARMINE_EXT_CMODE_DIRECT24_RGBA);
c_set_disp_reg(par, CARMINE_DISP_REG_L5_EXT_MODE, CARMINE_EXTEND_MODE |
CARMINE_EXT_CMODE_DIRECT24_RGBA);
c_set_disp_reg(par, CARMINE_DISP_REG_L6_EXT_MODE, CARMINE_EXTEND_MODE |
CARMINE_EXT_CMODE_DIRECT24_RGBA);
c_set_disp_reg(par, CARMINE_DISP_REG_L7_EXT_MODE, CARMINE_EXTEND_MODE |
CARMINE_EXT_CMODE_DIRECT24_RGBA);
/* Set default frame size to layer mode register */
width = par->res->hdp * 4 / CARMINE_DISP_WIDTH_UNIT;
width = width << CARMINE_DISP_WIDTH_SHIFT;
height = par->res->vdp - 1;
param = width | height;
c_set_disp_reg(par, CARMINE_DISP_REG_L0_MODE_W_H, param);
c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIDTH, width);
c_set_disp_reg(par, CARMINE_DISP_REG_L2_MODE_W_H, param);
c_set_disp_reg(par, CARMINE_DISP_REG_L3_MODE_W_H, param);
c_set_disp_reg(par, CARMINE_DISP_REG_L4_MODE_W_H, param);
c_set_disp_reg(par, CARMINE_DISP_REG_L5_MODE_W_H, param);
c_set_disp_reg(par, CARMINE_DISP_REG_L6_MODE_W_H, param);
c_set_disp_reg(par, CARMINE_DISP_REG_L7_MODE_W_H, param);
/* Set default pos and size */
window_size = (par->res->vdp - 1) << CARMINE_DISP_WIN_H_SHIFT;
window_size |= par->res->hdp;
c_set_disp_reg(par, CARMINE_DISP_REG_L0_WIN_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L0_WIN_SIZE, window_size);
c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIN_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L1_WIN_SIZE, window_size);
c_set_disp_reg(par, CARMINE_DISP_REG_L2_WIN_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L2_WIN_SIZE, window_size);
c_set_disp_reg(par, CARMINE_DISP_REG_L3_WIN_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L3_WIN_SIZE, window_size);
c_set_disp_reg(par, CARMINE_DISP_REG_L4_WIN_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L4_WIN_SIZE, window_size);
c_set_disp_reg(par, CARMINE_DISP_REG_L5_WIN_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L5_WIN_SIZE, window_size);
c_set_disp_reg(par, CARMINE_DISP_REG_L6_WIN_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L6_WIN_SIZE, window_size);
c_set_disp_reg(par, CARMINE_DISP_REG_L7_WIN_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L7_WIN_SIZE, window_size);
/* Set default origin address */
c_set_disp_reg(par, CARMINE_DISP_REG_L0_ORG_ADR, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L1_ORG_ADR, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L2_ORG_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L3_ORG_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L4_ORG_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L5_ORG_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L6_ORG_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L7_ORG_ADR1, soffset);
/* Set default display address */
c_set_disp_reg(par, CARMINE_DISP_REG_L0_DISP_ADR, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L2_DISP_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L3_DISP_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L4_DISP_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L5_DISP_ADR1, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L6_DISP_ADR0, soffset);
c_set_disp_reg(par, CARMINE_DISP_REG_L7_DISP_ADR0, soffset);
/* Set default display position */
c_set_disp_reg(par, CARMINE_DISP_REG_L0_DISP_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L2_DISP_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L3_DISP_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L4_DISP_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L5_DISP_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L6_DISP_POS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L7_DISP_POS, 0);
/* Set default blend mode */
c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L0, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L1, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L2, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L3, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L4, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L5, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L6, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_BLEND_MODE_L7, 0);
/* default transparency mode */
c_set_disp_reg(par, CARMINE_DISP_REG_L0_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L1_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L2_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L3_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L4_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L5_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L6_TRANS, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L7_TRANS, 0);
/* Set default read skip parameter */
c_set_disp_reg(par, CARMINE_DISP_REG_L0RM, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L2RM, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L3RM, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L4RM, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L5RM, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L6RM, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L7RM, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L0PX, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L2PX, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L3PX, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L4PX, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L5PX, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L6PX, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L7PX, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L0PY, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L2PY, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L3PY, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L4PY, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L5PY, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L6PY, 0);
c_set_disp_reg(par, CARMINE_DISP_REG_L7PY, 0);
}
static void set_display_parameters(struct carmine_fb *par)
{
u32 mode;
u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw;
/*
* display timing. Parameters are decreased by one because hardware
* spec is 0 to (n - 1)
* */
hdp = par->res->hdp - 1;
vdp = par->res->vdp - 1;
htp = par->res->htp - 1;
hsp = par->res->hsp - 1;
hsw = par->res->hsw - 1;
vtr = par->res->vtr - 1;
vsp = par->res->vsp - 1;
vsw = par->res->vsw - 1;
c_set_disp_reg(par, CARMINE_DISP_REG_H_TOTAL,
htp << CARMINE_DISP_HTP_SHIFT);
c_set_disp_reg(par, CARMINE_DISP_REG_H_PERIOD,
(hdp << CARMINE_DISP_HDB_SHIFT) | hdp);
c_set_disp_reg(par, CARMINE_DISP_REG_V_H_W_H_POS,
(vsw << CARMINE_DISP_VSW_SHIFT) |
(hsw << CARMINE_DISP_HSW_SHIFT) |
(hsp));
c_set_disp_reg(par, CARMINE_DISP_REG_V_TOTAL,
vtr << CARMINE_DISP_VTR_SHIFT);
c_set_disp_reg(par, CARMINE_DISP_REG_V_PERIOD_POS,
(vdp << CARMINE_DISP_VDP_SHIFT) | vsp);
/* clock */
mode = c_get_disp_reg(par, CARMINE_DISP_REG_DCM1);
mode = (mode & ~CARMINE_DISP_DCM_MASK) |
(par->res->disp_mode & CARMINE_DISP_DCM_MASK);
/* enable video output and layer 0 */
mode |= CARMINE_DEN | CARMINE_L0E;
c_set_disp_reg(par, CARMINE_DISP_REG_DCM1, mode);
}
static int carmine_set_par(struct fb_info *info)
{
struct carmine_fb *par = info->par;
int ret;
ret = carmine_find_mode(&info->var);
if (ret < 0)
return ret;
par->new_mode = ret;
if (par->cur_mode != par->new_mode) {
par->cur_mode = par->new_mode;
par->res = &car_modes[par->new_mode];
carmine_init_display_param(par);
set_display_parameters(par);
}
info->fix.line_length = info->var.xres * info->var.bits_per_pixel / 8;
return 0;
}
static int init_hardware(struct carmine_hw *hw)
{
u32 flags;
u32 loops;
u32 ret;
/* Initialize Carmine */
/* Sets internal clock */
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE,
CARMINE_DFLT_IP_CLOCK_ENABLE);
/* Video signal output is turned off */
c_set_hw_reg(hw, CARMINE_DISP0_REG + CARMINE_DISP_REG_DCM1, 0);
c_set_hw_reg(hw, CARMINE_DISP1_REG + CARMINE_DISP_REG_DCM1, 0);
/* Software reset */
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_SOFTWARE_RESET, 1);
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_SOFTWARE_RESET, 0);
/* I/O mode settings */
flags = CARMINE_DFLT_IP_DCTL_IO_CONT1 << 16 |
CARMINE_DFLT_IP_DCTL_IO_CONT0;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_IOCONT1_IOCONT0,
flags);
/* DRAM initial sequence */
flags = CARMINE_DFLT_IP_DCTL_MODE << 16 | CARMINE_DFLT_IP_DCTL_ADD;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_MODE_ADD,
flags);
flags = CARMINE_DFLT_IP_DCTL_SET_TIME1 << 16 |
CARMINE_DFLT_IP_DCTL_EMODE;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_SETTIME1_EMODE,
flags);
flags = CARMINE_DFLT_IP_DCTL_REFRESH << 16 |
CARMINE_DFLT_IP_DCTL_SET_TIME2;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_REFRESH_SETTIME2,
flags);
flags = CARMINE_DFLT_IP_DCTL_RESERVE2 << 16 |
CARMINE_DFLT_IP_DCTL_FIFO_DEPTH;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV2_RSV1, flags);
flags = CARMINE_DFLT_IP_DCTL_DDRIF2 << 16 | CARMINE_DFLT_IP_DCTL_DDRIF1;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_DDRIF2_DDRIF1,
flags);
flags = CARMINE_DFLT_IP_DCTL_RESERVE0 << 16 |
CARMINE_DFLT_IP_DCTL_STATES;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV0_STATES,
flags);
/* Executes DLL reset */
if (CARMINE_DCTL_DLL_RESET) {
for (loops = 0; loops < CARMINE_DCTL_INIT_WAIT_LIMIT; loops++) {
ret = c_get_hw_reg(hw, CARMINE_DCTL_REG +
CARMINE_DCTL_REG_RSV0_STATES);
ret &= CARMINE_DCTL_REG_STATES_MASK;
if (!ret)
break;
mdelay(CARMINE_DCTL_INIT_WAIT_INTERVAL);
}
if (loops >= CARMINE_DCTL_INIT_WAIT_LIMIT) {
printk(KERN_ERR "DRAM init failed\n");
return -EIO;
}
}
flags = CARMINE_DFLT_IP_DCTL_MODE_AFT_RST << 16 |
CARMINE_DFLT_IP_DCTL_ADD;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_MODE_ADD, flags);
flags = CARMINE_DFLT_IP_DCTL_RESERVE0 << 16 |
CARMINE_DFLT_IP_DCTL_STATES_AFT_RST;
c_set_hw_reg(hw, CARMINE_DCTL_REG + CARMINE_DCTL_REG_RSV0_STATES,
flags);
/* Initialize the write back register */
c_set_hw_reg(hw, CARMINE_WB_REG + CARMINE_WB_REG_WBM,
CARMINE_WB_REG_WBM_DEFAULT);
/* Initialize the Kottos registers */
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_VRINTM, 0);
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_VRERRM, 0);
/* Set DC offsets */
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_PX, 0);
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_PY, 0);
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_LX, 0);
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_LY, 0);
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_TX, 0);
c_set_hw_reg(hw, CARMINE_GRAPH_REG + CARMINE_GRAPH_REG_DC_OFFSET_TY, 0);
return 0;
}
static const struct fb_ops carminefb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = carmine_check_var,
.fb_set_par = carmine_set_par,
.fb_setcolreg = carmine_setcolreg,
};
static int alloc_carmine_fb(void __iomem *regs, void __iomem *smem_base,
int smem_offset, struct device *device,
struct fb_info **rinfo)
{
int ret;
struct fb_info *info;
struct carmine_fb *par;
info = framebuffer_alloc(sizeof *par, device);
if (!info)
return -ENOMEM;
par = info->par;
par->display_reg = regs;
par->smem_offset = smem_offset;
info->screen_base = smem_base + smem_offset;
info->screen_size = CARMINE_DISPLAY_MEM;
info->fbops = &carminefb_ops;
info->fix = carminefb_fix;
info->pseudo_palette = par->pseudo_palette;
ret = fb_alloc_cmap(&info->cmap, 256, 1);
if (ret < 0)
goto err_free_fb;
if (fb_mode >= ARRAY_SIZE(carmine_modedb))
fb_mode = CARMINEFB_DEFAULT_VIDEO_MODE;
par->cur_mode = par->new_mode = ~0;
ret = fb_find_mode(&info->var, info, fb_mode_str, carmine_modedb,
ARRAY_SIZE(carmine_modedb),
&carmine_modedb[fb_mode], 32);
if (!ret || ret == 4) {
ret = -EINVAL;
goto err_dealloc_cmap;
}
fb_videomode_to_modelist(carmine_modedb, ARRAY_SIZE(carmine_modedb),
&info->modelist);
ret = register_framebuffer(info);
if (ret < 0)
goto err_dealloc_cmap;
fb_info(info, "%s frame buffer device\n", info->fix.id);
*rinfo = info;
return 0;
err_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
err_free_fb:
framebuffer_release(info);
return ret;
}
static void cleanup_fb_device(struct fb_info *info)
{
if (info) {
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
}
static int carminefb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
{
struct carmine_hw *hw;
struct device *device = &dev->dev;
struct fb_info *info;
int ret;
ret = aperture_remove_conflicting_pci_devices(dev, "carminefb");
if (ret)
return ret;
ret = pci_enable_device(dev);
if (ret)
return ret;
ret = -ENOMEM;
hw = kzalloc(sizeof *hw, GFP_KERNEL);
if (!hw)
goto err_enable_pci;
carminefb_fix.mmio_start = pci_resource_start(dev, CARMINE_CONFIG_BAR);
carminefb_fix.mmio_len = pci_resource_len(dev, CARMINE_CONFIG_BAR);
if (!request_mem_region(carminefb_fix.mmio_start,
carminefb_fix.mmio_len,
"carminefb regbase")) {
printk(KERN_ERR "carminefb: Can't reserve regbase.\n");
ret = -EBUSY;
goto err_free_hw;
}
hw->v_regs = ioremap(carminefb_fix.mmio_start,
carminefb_fix.mmio_len);
if (!hw->v_regs) {
printk(KERN_ERR "carminefb: Can't remap %s register.\n",
carminefb_fix.id);
goto err_free_reg_mmio;
}
carminefb_fix.smem_start = pci_resource_start(dev, CARMINE_MEMORY_BAR);
carminefb_fix.smem_len = pci_resource_len(dev, CARMINE_MEMORY_BAR);
/* The memory area tends to be very large (256 MiB). Remap only what
* is required for that largest resolution to avoid remaps at run
* time
*/
if (carminefb_fix.smem_len > CARMINE_TOTAL_DIPLAY_MEM)
carminefb_fix.smem_len = CARMINE_TOTAL_DIPLAY_MEM;
else if (carminefb_fix.smem_len < CARMINE_TOTAL_DIPLAY_MEM) {
printk(KERN_ERR "carminefb: Memory bar is only %d bytes, %d "
"are required.", carminefb_fix.smem_len,
CARMINE_TOTAL_DIPLAY_MEM);
goto err_unmap_vregs;
}
if (!request_mem_region(carminefb_fix.smem_start,
carminefb_fix.smem_len, "carminefb smem")) {
printk(KERN_ERR "carminefb: Can't reserve smem.\n");
goto err_unmap_vregs;
}
hw->screen_mem = ioremap(carminefb_fix.smem_start,
carminefb_fix.smem_len);
if (!hw->screen_mem) {
printk(KERN_ERR "carmine: Can't ioremap smem area.\n");
goto err_reg_smem;
}
ret = init_hardware(hw);
if (ret)
goto err_unmap_screen;
info = NULL;
if (fb_displays & CARMINE_USE_DISPLAY0) {
ret = alloc_carmine_fb(hw->v_regs + CARMINE_DISP0_REG,
hw->screen_mem, CARMINE_DISPLAY_MEM * 0,
device, &info);
if (ret)
goto err_deinit_hw;
}
hw->fb[0] = info;
info = NULL;
if (fb_displays & CARMINE_USE_DISPLAY1) {
ret = alloc_carmine_fb(hw->v_regs + CARMINE_DISP1_REG,
hw->screen_mem, CARMINE_DISPLAY_MEM * 1,
device, &info);
if (ret)
goto err_cleanup_fb0;
}
hw->fb[1] = info;
info = NULL;
pci_set_drvdata(dev, hw);
return 0;
err_cleanup_fb0:
cleanup_fb_device(hw->fb[0]);
err_deinit_hw:
/* disable clock, etc */
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE, 0);
err_unmap_screen:
iounmap(hw->screen_mem);
err_reg_smem:
release_mem_region(carminefb_fix.smem_start, carminefb_fix.smem_len);
err_unmap_vregs:
iounmap(hw->v_regs);
err_free_reg_mmio:
release_mem_region(carminefb_fix.mmio_start, carminefb_fix.mmio_len);
err_free_hw:
kfree(hw);
err_enable_pci:
pci_disable_device(dev);
return ret;
}
static void carminefb_remove(struct pci_dev *dev)
{
struct carmine_hw *hw = pci_get_drvdata(dev);
struct fb_fix_screeninfo fix;
int i;
/* in case we use only fb1 and not fb1 */
if (hw->fb[0])
fix = hw->fb[0]->fix;
else
fix = hw->fb[1]->fix;
/* deactivate display(s) and switch clocks */
c_set_hw_reg(hw, CARMINE_DISP0_REG + CARMINE_DISP_REG_DCM1, 0);
c_set_hw_reg(hw, CARMINE_DISP1_REG + CARMINE_DISP_REG_DCM1, 0);
c_set_hw_reg(hw, CARMINE_CTL_REG + CARMINE_CTL_REG_CLOCK_ENABLE, 0);
for (i = 0; i < MAX_DISPLAY; i++)
cleanup_fb_device(hw->fb[i]);
iounmap(hw->screen_mem);
release_mem_region(fix.smem_start, fix.smem_len);
iounmap(hw->v_regs);
release_mem_region(fix.mmio_start, fix.mmio_len);
pci_disable_device(dev);
kfree(hw);
}
#define PCI_VENDOR_ID_FUJITU_LIMITED 0x10cf
static struct pci_device_id carmine_devices[] = {
{
PCI_DEVICE(PCI_VENDOR_ID_FUJITU_LIMITED, 0x202b)},
{0, 0, 0, 0, 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, carmine_devices);
static struct pci_driver carmine_pci_driver = {
.name = "carminefb",
.id_table = carmine_devices,
.probe = carminefb_probe,
.remove = carminefb_remove,
};
static int __init carminefb_init(void)
{
if (fb_modesetting_disabled("carminefb"))
return -ENODEV;
if (!(fb_displays &
(CARMINE_USE_DISPLAY0 | CARMINE_USE_DISPLAY1))) {
printk(KERN_ERR "If you disable both displays than you don't "
"need the driver at all\n");
return -EINVAL;
}
return pci_register_driver(&carmine_pci_driver);
}
module_init(carminefb_init);
static void __exit carminefb_cleanup(void)
{
pci_unregister_driver(&carmine_pci_driver);
}
module_exit(carminefb_cleanup);
MODULE_AUTHOR("Sebastian Siewior <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for Fujitsu Carmine based devices");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/carminefb.c |
/*
* linux/drivers/video/pmag-ba-fb.c
*
* PMAG-BA TURBOchannel Color Frame Buffer (CFB) card support,
* derived from:
* "HP300 Topcat framebuffer support (derived from macfb of all things)
* Phil Blundell <[email protected]> 1998", the original code can be
* found in the file hpfb.c in the same directory.
*
* Based on digital document:
* "PMAG-BA TURBOchannel Color Frame Buffer
* Functional Specification", Revision 1.2, August 27, 1990
*
* DECstation related code Copyright (C) 1999, 2000, 2001 by
* Michael Engel <[email protected]>,
* Karsten Merker <[email protected]> and
* Harald Koerfgen.
* Copyright (c) 2005, 2006 Maciej W. Rozycki
* Copyright (c) 2005 James Simmons
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*/
#include <linux/compiler.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/tc.h>
#include <linux/types.h>
#include <asm/io.h>
#include <video/pmag-ba-fb.h>
struct pmagbafb_par {
volatile void __iomem *mmio;
volatile u32 __iomem *dac;
};
static const struct fb_var_screeninfo pmagbafb_defined = {
.xres = 1024,
.yres = 864,
.xres_virtual = 1024,
.yres_virtual = 864,
.bits_per_pixel = 8,
.red.length = 8,
.green.length = 8,
.blue.length = 8,
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.accel_flags = FB_ACCEL_NONE,
.pixclock = 14452,
.left_margin = 116,
.right_margin = 12,
.upper_margin = 34,
.lower_margin = 0,
.hsync_len = 128,
.vsync_len = 3,
.sync = FB_SYNC_ON_GREEN,
.vmode = FB_VMODE_NONINTERLACED,
};
static const struct fb_fix_screeninfo pmagbafb_fix = {
.id = "PMAG-BA",
.smem_len = (1024 * 1024),
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.line_length = 1024,
.mmio_len = PMAG_BA_SIZE - PMAG_BA_BT459,
};
static inline void dac_write(struct pmagbafb_par *par, unsigned int reg, u8 v)
{
writeb(v, par->dac + reg / 4);
}
static inline u8 dac_read(struct pmagbafb_par *par, unsigned int reg)
{
return readb(par->dac + reg / 4);
}
/*
* Set the palette.
*/
static int pmagbafb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
struct pmagbafb_par *par = info->par;
if (regno >= info->cmap.len)
return 1;
red >>= 8; /* The cmap fields are 16 bits */
green >>= 8; /* wide, but the hardware colormap */
blue >>= 8; /* registers are only 8 bits wide */
mb();
dac_write(par, BT459_ADDR_LO, regno);
dac_write(par, BT459_ADDR_HI, 0x00);
wmb();
dac_write(par, BT459_CMAP, red);
wmb();
dac_write(par, BT459_CMAP, green);
wmb();
dac_write(par, BT459_CMAP, blue);
return 0;
}
static const struct fb_ops pmagbafb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = pmagbafb_setcolreg,
};
/*
* Turn the hardware cursor off.
*/
static void pmagbafb_erase_cursor(struct fb_info *info)
{
struct pmagbafb_par *par = info->par;
mb();
dac_write(par, BT459_ADDR_LO, 0x00);
dac_write(par, BT459_ADDR_HI, 0x03);
wmb();
dac_write(par, BT459_DATA, 0x00);
}
static int pmagbafb_probe(struct device *dev)
{
struct tc_dev *tdev = to_tc_dev(dev);
resource_size_t start, len;
struct fb_info *info;
struct pmagbafb_par *par;
int err;
info = framebuffer_alloc(sizeof(struct pmagbafb_par), dev);
if (!info)
return -ENOMEM;
par = info->par;
dev_set_drvdata(dev, info);
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
printk(KERN_ERR "%s: Cannot allocate color map\n",
dev_name(dev));
err = -ENOMEM;
goto err_alloc;
}
info->fbops = &pmagbafb_ops;
info->fix = pmagbafb_fix;
info->var = pmagbafb_defined;
/* Request the I/O MEM resource. */
start = tdev->resource.start;
len = tdev->resource.end - start + 1;
if (!request_mem_region(start, len, dev_name(dev))) {
printk(KERN_ERR "%s: Cannot reserve FB region\n",
dev_name(dev));
err = -EBUSY;
goto err_cmap;
}
/* MMIO mapping setup. */
info->fix.mmio_start = start;
par->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
if (!par->mmio) {
printk(KERN_ERR "%s: Cannot map MMIO\n", dev_name(dev));
err = -ENOMEM;
goto err_resource;
}
par->dac = par->mmio + PMAG_BA_BT459;
/* Frame buffer mapping setup. */
info->fix.smem_start = start + PMAG_BA_FBMEM;
info->screen_base = ioremap(info->fix.smem_start,
info->fix.smem_len);
if (!info->screen_base) {
printk(KERN_ERR "%s: Cannot map FB\n", dev_name(dev));
err = -ENOMEM;
goto err_mmio_map;
}
info->screen_size = info->fix.smem_len;
pmagbafb_erase_cursor(info);
err = register_framebuffer(info);
if (err < 0) {
printk(KERN_ERR "%s: Cannot register framebuffer\n",
dev_name(dev));
goto err_smem_map;
}
get_device(dev);
fb_info(info, "%s frame buffer device at %s\n",
info->fix.id, dev_name(dev));
return 0;
err_smem_map:
iounmap(info->screen_base);
err_mmio_map:
iounmap(par->mmio);
err_resource:
release_mem_region(start, len);
err_cmap:
fb_dealloc_cmap(&info->cmap);
err_alloc:
framebuffer_release(info);
return err;
}
static int pmagbafb_remove(struct device *dev)
{
struct tc_dev *tdev = to_tc_dev(dev);
struct fb_info *info = dev_get_drvdata(dev);
struct pmagbafb_par *par = info->par;
resource_size_t start, len;
put_device(dev);
unregister_framebuffer(info);
iounmap(info->screen_base);
iounmap(par->mmio);
start = tdev->resource.start;
len = tdev->resource.end - start + 1;
release_mem_region(start, len);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
return 0;
}
/*
* Initialize the framebuffer.
*/
static const struct tc_device_id pmagbafb_tc_table[] = {
{ "DEC ", "PMAG-BA " },
{ }
};
MODULE_DEVICE_TABLE(tc, pmagbafb_tc_table);
static struct tc_driver pmagbafb_driver = {
.id_table = pmagbafb_tc_table,
.driver = {
.name = "pmagbafb",
.bus = &tc_bus_type,
.probe = pmagbafb_probe,
.remove = pmagbafb_remove,
},
};
static int __init pmagbafb_init(void)
{
#ifndef MODULE
if (fb_get_options("pmagbafb", NULL))
return -ENXIO;
#endif
return tc_register_driver(&pmagbafb_driver);
}
static void __exit pmagbafb_exit(void)
{
tc_unregister_driver(&pmagbafb_driver);
}
module_init(pmagbafb_init);
module_exit(pmagbafb_exit);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/pmag-ba-fb.c |
/*
* BRIEF MODULE DESCRIPTION
* Au1100 LCD Driver.
*
* Rewritten for 2.6 by Embedded Alley Solutions
* <[email protected]>, based on submissions by
* Karl Lessard <[email protected]>
* <[email protected]>
*
* PM support added by Rodolfo Giometti <[email protected]>
* Cursor enable/disable by Rodolfo Giometti <[email protected]>
*
* Copyright 2002 MontaVista Software
* Author: MontaVista Software, Inc.
* [email protected] or [email protected]
*
* Copyright 2002 Alchemy Semiconductor
* Author: Alchemy Semiconductor
*
* Based on:
* linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
* Created 28 Dec 1997 by Geert Uytterhoeven
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ctype.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <asm/mach-au1x00/au1000.h>
#define DEBUG 0
#include "au1100fb.h"
#define DRIVER_NAME "au1100fb"
#define DRIVER_DESC "LCD controller driver for AU1100 processors"
#define to_au1100fb_device(_info) \
(_info ? container_of(_info, struct au1100fb_device, info) : NULL);
/* Bitfields format supported by the controller. Note that the order of formats
* SHOULD be the same as in the LCD_CONTROL_SBPPF field, so we can retrieve the
* right pixel format by doing rgb_bitfields[LCD_CONTROL_SBPPF_XXX >> LCD_CONTROL_SBPPF]
*/
struct fb_bitfield rgb_bitfields[][4] =
{
/* Red, Green, Blue, Transp */
{ { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
{ { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
{ { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
{ { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
{ { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
/* The last is used to describe 12bpp format */
{ { 8, 4, 0 }, { 4, 4, 0 }, { 0, 4, 0 }, { 0, 0, 0 } },
};
static struct fb_fix_screeninfo au1100fb_fix = {
.id = "AU1100 FB",
.xpanstep = 1,
.ypanstep = 1,
.type = FB_TYPE_PACKED_PIXELS,
.accel = FB_ACCEL_NONE,
};
static struct fb_var_screeninfo au1100fb_var = {
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
};
/* fb_blank
* Blank the screen. Depending on the mode, the screen will be
* activated with the backlight color, or desactivated
*/
static int au1100fb_fb_blank(int blank_mode, struct fb_info *fbi)
{
struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
print_dbg("fb_blank %d %p", blank_mode, fbi);
switch (blank_mode) {
case VESA_NO_BLANKING:
/* Turn on panel */
fbdev->regs->lcd_control |= LCD_CONTROL_GO;
wmb(); /* drain writebuffer */
break;
case VESA_VSYNC_SUSPEND:
case VESA_HSYNC_SUSPEND:
case VESA_POWERDOWN:
/* Turn off panel */
fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
wmb(); /* drain writebuffer */
break;
default:
break;
}
return 0;
}
/*
* Set hardware with var settings. This will enable the controller with a specific
* mode, normally validated with the fb_check_var method
*/
int au1100fb_setmode(struct au1100fb_device *fbdev)
{
struct fb_info *info = &fbdev->info;
u32 words;
int index;
if (!fbdev)
return -EINVAL;
/* Update var-dependent FB info */
if (panel_is_active(fbdev->panel) || panel_is_color(fbdev->panel)) {
if (info->var.bits_per_pixel <= 8) {
/* palettized */
info->var.red.offset = 0;
info->var.red.length = info->var.bits_per_pixel;
info->var.red.msb_right = 0;
info->var.green.offset = 0;
info->var.green.length = info->var.bits_per_pixel;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = info->var.bits_per_pixel;
info->var.blue.msb_right = 0;
info->var.transp.offset = 0;
info->var.transp.length = 0;
info->var.transp.msb_right = 0;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = info->var.xres_virtual /
(8/info->var.bits_per_pixel);
} else {
/* non-palettized */
index = (fbdev->panel->control_base & LCD_CONTROL_SBPPF_MASK) >> LCD_CONTROL_SBPPF_BIT;
info->var.red = rgb_bitfields[index][0];
info->var.green = rgb_bitfields[index][1];
info->var.blue = rgb_bitfields[index][2];
info->var.transp = rgb_bitfields[index][3];
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = info->var.xres_virtual << 1; /* depth=16 */
}
} else {
/* mono */
info->fix.visual = FB_VISUAL_MONO10;
info->fix.line_length = info->var.xres_virtual / 8;
}
info->screen_size = info->fix.line_length * info->var.yres_virtual;
info->var.rotate = ((fbdev->panel->control_base&LCD_CONTROL_SM_MASK) \
>> LCD_CONTROL_SM_BIT) * 90;
/* Determine BPP mode and format */
fbdev->regs->lcd_control = fbdev->panel->control_base;
fbdev->regs->lcd_horztiming = fbdev->panel->horztiming;
fbdev->regs->lcd_verttiming = fbdev->panel->verttiming;
fbdev->regs->lcd_clkcontrol = fbdev->panel->clkcontrol_base;
fbdev->regs->lcd_intenable = 0;
fbdev->regs->lcd_intstatus = 0;
fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(fbdev->fb_phys);
if (panel_is_dual(fbdev->panel)) {
/* Second panel display seconf half of screen if possible,
* otherwise display the same as the first panel */
if (info->var.yres_virtual >= (info->var.yres << 1)) {
fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys +
(info->fix.line_length *
(info->var.yres_virtual >> 1)));
} else {
fbdev->regs->lcd_dmaaddr1 = LCD_DMA_SA_N(fbdev->fb_phys);
}
}
words = info->fix.line_length / sizeof(u32);
if (!info->var.rotate || (info->var.rotate == 180)) {
words *= info->var.yres_virtual;
if (info->var.rotate /* 180 */) {
words -= (words % 8); /* should be divisable by 8 */
}
}
fbdev->regs->lcd_words = LCD_WRD_WRDS_N(words);
fbdev->regs->lcd_pwmdiv = 0;
fbdev->regs->lcd_pwmhi = 0;
/* Resume controller */
fbdev->regs->lcd_control |= LCD_CONTROL_GO;
mdelay(10);
au1100fb_fb_blank(VESA_NO_BLANKING, info);
return 0;
}
/* fb_setcolreg
* Set color in LCD palette.
*/
int au1100fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *fbi)
{
struct au1100fb_device *fbdev;
u32 *palette;
u32 value;
fbdev = to_au1100fb_device(fbi);
palette = fbdev->regs->lcd_palettebase;
if (regno > (AU1100_LCD_NBR_PALETTE_ENTRIES - 1))
return -EINVAL;
if (fbi->var.grayscale) {
/* Convert color to grayscale */
red = green = blue =
(19595 * red + 38470 * green + 7471 * blue) >> 16;
}
if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
/* Place color in the pseudopalette */
if (regno > 16)
return -EINVAL;
palette = (u32*)fbi->pseudo_palette;
red >>= (16 - fbi->var.red.length);
green >>= (16 - fbi->var.green.length);
blue >>= (16 - fbi->var.blue.length);
value = (red << fbi->var.red.offset) |
(green << fbi->var.green.offset)|
(blue << fbi->var.blue.offset);
value &= 0xFFFF;
} else if (panel_is_active(fbdev->panel)) {
/* COLOR TFT PALLETTIZED (use RGB 565) */
value = (red & 0xF800)|((green >> 5) & 0x07E0)|((blue >> 11) & 0x001F);
value &= 0xFFFF;
} else if (panel_is_color(fbdev->panel)) {
/* COLOR STN MODE */
value = (((panel_swap_rgb(fbdev->panel) ? blue : red) >> 12) & 0x000F) |
((green >> 8) & 0x00F0) |
(((panel_swap_rgb(fbdev->panel) ? red : blue) >> 4) & 0x0F00);
value &= 0xFFF;
} else {
/* MONOCHROME MODE */
value = (green >> 12) & 0x000F;
value &= 0xF;
}
palette[regno] = value;
return 0;
}
/* fb_pan_display
* Pan display in x and/or y as specified
*/
int au1100fb_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fbi)
{
struct au1100fb_device *fbdev;
int dy;
fbdev = to_au1100fb_device(fbi);
print_dbg("fb_pan_display %p %p", var, fbi);
if (!var || !fbdev) {
return -EINVAL;
}
if (var->xoffset - fbi->var.xoffset) {
/* No support for X panning for now! */
return -EINVAL;
}
print_dbg("fb_pan_display 2 %p %p", var, fbi);
dy = var->yoffset - fbi->var.yoffset;
if (dy) {
u32 dmaaddr;
print_dbg("Panning screen of %d lines", dy);
dmaaddr = fbdev->regs->lcd_dmaaddr0;
dmaaddr += (fbi->fix.line_length * dy);
/* TODO: Wait for current frame to finished */
fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
if (panel_is_dual(fbdev->panel)) {
dmaaddr = fbdev->regs->lcd_dmaaddr1;
dmaaddr += (fbi->fix.line_length * dy);
fbdev->regs->lcd_dmaaddr0 = LCD_DMA_SA_N(dmaaddr);
}
}
print_dbg("fb_pan_display 3 %p %p", var, fbi);
return 0;
}
/* fb_mmap
* Map video memory in user space. We don't use the generic fb_mmap method mainly
* to allow the use of the TLB streaming flag (CCA=6)
*/
int au1100fb_fb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
{
struct au1100fb_device *fbdev = to_au1100fb_device(fbi);
pgprot_val(vma->vm_page_prot) |= (6 << 9); //CCA=6
return dma_mmap_coherent(fbdev->dev, vma, fbdev->fb_mem, fbdev->fb_phys,
fbdev->fb_len);
}
static const struct fb_ops au1100fb_ops =
{
.owner = THIS_MODULE,
.fb_setcolreg = au1100fb_fb_setcolreg,
.fb_blank = au1100fb_fb_blank,
.fb_pan_display = au1100fb_fb_pan_display,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = au1100fb_fb_mmap,
};
/*-------------------------------------------------------------------------*/
static int au1100fb_setup(struct au1100fb_device *fbdev)
{
char *this_opt, *options;
int num_panels = ARRAY_SIZE(known_lcd_panels);
if (num_panels <= 0) {
print_err("No LCD panels supported by driver!");
return -ENODEV;
}
if (fb_get_options(DRIVER_NAME, &options))
return -ENODEV;
if (!options)
return -ENODEV;
while ((this_opt = strsep(&options, ",")) != NULL) {
/* Panel option */
if (!strncmp(this_opt, "panel:", 6)) {
int i;
this_opt += 6;
for (i = 0; i < num_panels; i++) {
if (!strncmp(this_opt, known_lcd_panels[i].name,
strlen(this_opt))) {
fbdev->panel = &known_lcd_panels[i];
fbdev->panel_idx = i;
break;
}
}
if (i >= num_panels) {
print_warn("Panel '%s' not supported!", this_opt);
return -ENODEV;
}
}
/* Unsupported option */
else
print_warn("Unsupported option \"%s\"", this_opt);
}
print_info("Panel=%s", fbdev->panel->name);
return 0;
}
static int au1100fb_drv_probe(struct platform_device *dev)
{
struct au1100fb_device *fbdev;
struct resource *regs_res;
struct clk *c;
/* Allocate new device private */
fbdev = devm_kzalloc(&dev->dev, sizeof(*fbdev), GFP_KERNEL);
if (!fbdev)
return -ENOMEM;
if (au1100fb_setup(fbdev))
goto failed;
platform_set_drvdata(dev, (void *)fbdev);
fbdev->dev = &dev->dev;
/* Allocate region for our registers and map them */
regs_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!regs_res) {
print_err("fail to retrieve registers resource");
return -EFAULT;
}
au1100fb_fix.mmio_start = regs_res->start;
au1100fb_fix.mmio_len = resource_size(regs_res);
if (!devm_request_mem_region(&dev->dev,
au1100fb_fix.mmio_start,
au1100fb_fix.mmio_len,
DRIVER_NAME)) {
print_err("fail to lock memory region at 0x%08lx",
au1100fb_fix.mmio_start);
return -EBUSY;
}
fbdev->regs = (struct au1100fb_regs*)KSEG1ADDR(au1100fb_fix.mmio_start);
print_dbg("Register memory map at %p", fbdev->regs);
print_dbg("phys=0x%08x, size=%d", fbdev->regs_phys, fbdev->regs_len);
c = clk_get(NULL, "lcd_intclk");
if (!IS_ERR(c)) {
fbdev->lcdclk = c;
clk_set_rate(c, 48000000);
clk_prepare_enable(c);
}
/* Allocate the framebuffer to the maximum screen size * nbr of video buffers */
fbdev->fb_len = fbdev->panel->xres * fbdev->panel->yres *
(fbdev->panel->bpp >> 3) * AU1100FB_NBR_VIDEO_BUFFERS;
fbdev->fb_mem = dmam_alloc_coherent(&dev->dev,
PAGE_ALIGN(fbdev->fb_len),
&fbdev->fb_phys, GFP_KERNEL);
if (!fbdev->fb_mem) {
print_err("fail to allocate framebuffer (size: %dK))",
fbdev->fb_len / 1024);
return -ENOMEM;
}
au1100fb_fix.smem_start = fbdev->fb_phys;
au1100fb_fix.smem_len = fbdev->fb_len;
print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
/* load the panel info into the var struct */
au1100fb_var.bits_per_pixel = fbdev->panel->bpp;
au1100fb_var.xres = fbdev->panel->xres;
au1100fb_var.xres_virtual = au1100fb_var.xres;
au1100fb_var.yres = fbdev->panel->yres;
au1100fb_var.yres_virtual = au1100fb_var.yres;
fbdev->info.screen_base = fbdev->fb_mem;
fbdev->info.fbops = &au1100fb_ops;
fbdev->info.fix = au1100fb_fix;
fbdev->info.pseudo_palette =
devm_kcalloc(&dev->dev, 16, sizeof(u32), GFP_KERNEL);
if (!fbdev->info.pseudo_palette)
return -ENOMEM;
if (fb_alloc_cmap(&fbdev->info.cmap, AU1100_LCD_NBR_PALETTE_ENTRIES, 0) < 0) {
print_err("Fail to allocate colormap (%d entries)",
AU1100_LCD_NBR_PALETTE_ENTRIES);
return -EFAULT;
}
fbdev->info.var = au1100fb_var;
/* Set h/w registers */
au1100fb_setmode(fbdev);
/* Register new framebuffer */
if (register_framebuffer(&fbdev->info) < 0) {
print_err("cannot register new framebuffer");
goto failed;
}
return 0;
failed:
if (fbdev->lcdclk) {
clk_disable_unprepare(fbdev->lcdclk);
clk_put(fbdev->lcdclk);
}
if (fbdev->info.cmap.len != 0) {
fb_dealloc_cmap(&fbdev->info.cmap);
}
return -ENODEV;
}
void au1100fb_drv_remove(struct platform_device *dev)
{
struct au1100fb_device *fbdev = NULL;
fbdev = platform_get_drvdata(dev);
#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
#endif
fbdev->regs->lcd_control &= ~LCD_CONTROL_GO;
/* Clean up all probe data */
unregister_framebuffer(&fbdev->info);
fb_dealloc_cmap(&fbdev->info.cmap);
if (fbdev->lcdclk) {
clk_disable_unprepare(fbdev->lcdclk);
clk_put(fbdev->lcdclk);
}
}
#ifdef CONFIG_PM
static struct au1100fb_regs fbregs;
int au1100fb_drv_suspend(struct platform_device *dev, pm_message_t state)
{
struct au1100fb_device *fbdev = platform_get_drvdata(dev);
if (!fbdev)
return 0;
/* Blank the LCD */
au1100fb_fb_blank(VESA_POWERDOWN, &fbdev->info);
clk_disable(fbdev->lcdclk);
memcpy(&fbregs, fbdev->regs, sizeof(struct au1100fb_regs));
return 0;
}
int au1100fb_drv_resume(struct platform_device *dev)
{
struct au1100fb_device *fbdev = platform_get_drvdata(dev);
if (!fbdev)
return 0;
memcpy(fbdev->regs, &fbregs, sizeof(struct au1100fb_regs));
clk_enable(fbdev->lcdclk);
/* Unblank the LCD */
au1100fb_fb_blank(VESA_NO_BLANKING, &fbdev->info);
return 0;
}
#else
#define au1100fb_drv_suspend NULL
#define au1100fb_drv_resume NULL
#endif
static struct platform_driver au1100fb_driver = {
.driver = {
.name = "au1100-lcd",
},
.probe = au1100fb_drv_probe,
.remove_new = au1100fb_drv_remove,
.suspend = au1100fb_drv_suspend,
.resume = au1100fb_drv_resume,
};
module_platform_driver(au1100fb_driver);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/au1100fb.c |
/*
* linux/drivers/video/vga16.c -- VGA 16-color framebuffer driver
*
* Copyright 1999 Ben Pfaff <[email protected]> and Petr Vandrovec <[email protected]>
* Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
* Based on VESA framebuffer (c) 1998 Gerd Knorr <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/screen_info.h>
#include <asm/io.h>
#include <video/vga.h>
#define MODE_SKIP4 1
#define MODE_8BPP 2
#define MODE_CFB 4
#define MODE_TEXT 8
/* --------------------------------------------------------------------- */
/*
* card parameters
*/
struct vga16fb_par {
/* structure holding original VGA register settings when the
screen is blanked */
struct {
unsigned char SeqCtrlIndex; /* Sequencer Index reg. */
unsigned char CrtCtrlIndex; /* CRT-Contr. Index reg. */
unsigned char CrtMiscIO; /* Miscellaneous register */
unsigned char HorizontalTotal; /* CRT-Controller:00h */
unsigned char HorizDisplayEnd; /* CRT-Controller:01h */
unsigned char StartHorizRetrace;/* CRT-Controller:04h */
unsigned char EndHorizRetrace; /* CRT-Controller:05h */
unsigned char Overflow; /* CRT-Controller:07h */
unsigned char StartVertRetrace; /* CRT-Controller:10h */
unsigned char EndVertRetrace; /* CRT-Controller:11h */
unsigned char ModeControl; /* CRT-Controller:17h */
unsigned char ClockingMode; /* Seq-Controller:01h */
} vga_state;
struct vgastate state;
unsigned int ref_count;
int palette_blanked, vesa_blanked, mode, isVGA;
u8 misc, pel_msk, vss, clkdiv;
u8 crtc[VGA_CRT_C];
};
/* --------------------------------------------------------------------- */
static struct fb_var_screeninfo vga16fb_defined = {
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel = 4,
.activate = FB_ACTIVATE_TEST,
.height = -1,
.width = -1,
.pixclock = 39721,
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED,
};
/* name should not depend on EGA/VGA */
static const struct fb_fix_screeninfo vga16fb_fix = {
.id = "VGA16 VGA",
.smem_start = VGA_FB_PHYS_BASE,
.smem_len = VGA_FB_PHYS_SIZE,
.type = FB_TYPE_VGA_PLANES,
.type_aux = FB_AUX_VGA_PLANES_VGA4,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 8,
.ypanstep = 1,
.line_length = 640 / 8,
.accel = FB_ACCEL_NONE
};
/* The VGA's weird architecture often requires that we read a byte and
write a byte to the same location. It doesn't matter *what* byte
we write, however. This is because all the action goes on behind
the scenes in the VGA's 32-bit latch register, and reading and writing
video memory just invokes latch behavior.
To avoid race conditions (is this necessary?), reading and writing
the memory byte should be done with a single instruction. One
suitable instruction is the x86 bitwise OR. The following
read-modify-write routine should optimize to one such bitwise
OR. */
static inline void rmw(volatile char __iomem *p)
{
readb(p);
writeb(1, p);
}
/* Set the Graphics Mode Register, and return its previous value.
Bits 0-1 are write mode, bit 3 is read mode. */
static inline int setmode(int mode)
{
int oldmode;
oldmode = vga_io_rgfx(VGA_GFX_MODE);
vga_io_w(VGA_GFX_D, mode);
return oldmode;
}
/* Select the Bit Mask Register and return its value. */
static inline int selectmask(void)
{
return vga_io_rgfx(VGA_GFX_BIT_MASK);
}
/* Set the value of the Bit Mask Register. It must already have been
selected with selectmask(). */
static inline void setmask(int mask)
{
vga_io_w(VGA_GFX_D, mask);
}
/* Set the Data Rotate Register and return its old value.
Bits 0-2 are rotate count, bits 3-4 are logical operation
(0=NOP, 1=AND, 2=OR, 3=XOR). */
static inline int setop(int op)
{
int oldop;
oldop = vga_io_rgfx(VGA_GFX_DATA_ROTATE);
vga_io_w(VGA_GFX_D, op);
return oldop;
}
/* Set the Enable Set/Reset Register and return its old value.
The code here always uses value 0xf for this register. */
static inline int setsr(int sr)
{
int oldsr;
oldsr = vga_io_rgfx(VGA_GFX_SR_ENABLE);
vga_io_w(VGA_GFX_D, sr);
return oldsr;
}
/* Set the Set/Reset Register and return its old value. */
static inline int setcolor(int color)
{
int oldcolor;
oldcolor = vga_io_rgfx(VGA_GFX_SR_VALUE);
vga_io_w(VGA_GFX_D, color);
return oldcolor;
}
/* Return the value in the Graphics Address Register. */
static inline int getindex(void)
{
return vga_io_r(VGA_GFX_I);
}
/* Set the value in the Graphics Address Register. */
static inline void setindex(int index)
{
vga_io_w(VGA_GFX_I, index);
}
/* Check if the video mode is supported by the driver */
static inline int check_mode_supported(const struct screen_info *si)
{
/* non-x86 architectures treat orig_video_isVGA as a boolean flag */
#if defined(CONFIG_X86)
/* only EGA and VGA in 16 color graphic mode are supported */
if (si->orig_video_isVGA != VIDEO_TYPE_EGAC &&
si->orig_video_isVGA != VIDEO_TYPE_VGAC)
return -ENODEV;
if (si->orig_video_mode != 0x0D && /* 320x200/4 (EGA) */
si->orig_video_mode != 0x0E && /* 640x200/4 (EGA) */
si->orig_video_mode != 0x10 && /* 640x350/4 (EGA) */
si->orig_video_mode != 0x12) /* 640x480/4 (VGA) */
return -ENODEV;
#endif
return 0;
}
static void vga16fb_pan_var(struct fb_info *info,
struct fb_var_screeninfo *var)
{
struct vga16fb_par *par = info->par;
u32 xoffset, pos;
xoffset = var->xoffset;
if (info->var.bits_per_pixel == 8) {
pos = (info->var.xres_virtual * var->yoffset + xoffset) >> 2;
} else if (par->mode & MODE_TEXT) {
int fh = 16; // FIXME !!! font height. Fugde for now.
pos = (info->var.xres_virtual * (var->yoffset / fh) + xoffset) >> 3;
} else {
if (info->var.nonstd)
xoffset--;
pos = (info->var.xres_virtual * var->yoffset + xoffset) >> 3;
}
vga_io_wcrt(VGA_CRTC_START_HI, pos >> 8);
vga_io_wcrt(VGA_CRTC_START_LO, pos & 0xFF);
/* if we support CFB4, then we must! support xoffset with pixel
* granularity if someone supports xoffset in bit resolution */
vga_io_r(VGA_IS1_RC); /* reset flip-flop */
vga_io_w(VGA_ATT_IW, VGA_ATC_PEL);
if (info->var.bits_per_pixel == 8)
vga_io_w(VGA_ATT_IW, (xoffset & 3) << 1);
else
vga_io_w(VGA_ATT_IW, xoffset & 7);
vga_io_r(VGA_IS1_RC);
vga_io_w(VGA_ATT_IW, 0x20);
}
static void vga16fb_update_fix(struct fb_info *info)
{
if (info->var.bits_per_pixel == 4) {
if (info->var.nonstd) {
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.line_length = info->var.xres_virtual / 2;
} else {
info->fix.type = FB_TYPE_VGA_PLANES;
info->fix.type_aux = FB_AUX_VGA_PLANES_VGA4;
info->fix.line_length = info->var.xres_virtual / 8;
}
} else if (info->var.bits_per_pixel == 0) {
info->fix.type = FB_TYPE_TEXT;
info->fix.type_aux = FB_AUX_TEXT_CGA;
info->fix.line_length = info->var.xres_virtual / 4;
} else { /* 8bpp */
if (info->var.nonstd) {
info->fix.type = FB_TYPE_VGA_PLANES;
info->fix.type_aux = FB_AUX_VGA_PLANES_CFB8;
info->fix.line_length = info->var.xres_virtual / 4;
} else {
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.line_length = info->var.xres_virtual;
}
}
}
static void vga16fb_clock_chip(struct vga16fb_par *par,
unsigned int *pixclock,
const struct fb_info *info,
int mul, int div)
{
static const struct {
u32 pixclock;
u8 misc;
u8 seq_clock_mode;
} *ptr, *best, vgaclocks[] = {
{ 79442 /* 12.587 */, 0x00, 0x08},
{ 70616 /* 14.161 */, 0x04, 0x08},
{ 39721 /* 25.175 */, 0x00, 0x00},
{ 35308 /* 28.322 */, 0x04, 0x00},
{ 0 /* bad */, 0x00, 0x00}};
int err;
*pixclock = (*pixclock * mul) / div;
best = vgaclocks;
err = *pixclock - best->pixclock;
if (err < 0) err = -err;
for (ptr = vgaclocks + 1; ptr->pixclock; ptr++) {
int tmp;
tmp = *pixclock - ptr->pixclock;
if (tmp < 0) tmp = -tmp;
if (tmp < err) {
err = tmp;
best = ptr;
}
}
par->misc |= best->misc;
par->clkdiv = best->seq_clock_mode;
*pixclock = (best->pixclock * div) / mul;
}
#define FAIL(X) return -EINVAL
static int vga16fb_open(struct fb_info *info, int user)
{
struct vga16fb_par *par = info->par;
if (!par->ref_count) {
memset(&par->state, 0, sizeof(struct vgastate));
par->state.flags = VGA_SAVE_FONTS | VGA_SAVE_MODE |
VGA_SAVE_CMAP;
save_vga(&par->state);
}
par->ref_count++;
return 0;
}
static int vga16fb_release(struct fb_info *info, int user)
{
struct vga16fb_par *par = info->par;
if (!par->ref_count)
return -EINVAL;
if (par->ref_count == 1)
restore_vga(&par->state);
par->ref_count--;
return 0;
}
static int vga16fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct vga16fb_par *par = info->par;
u32 xres, right, hslen, left, xtotal;
u32 yres, lower, vslen, upper, ytotal;
u32 vxres, xoffset, vyres, yoffset;
u32 pos;
u8 r7, rMode;
int shift;
int mode;
u32 maxmem;
par->pel_msk = 0xFF;
if (var->bits_per_pixel == 4) {
if (var->nonstd) {
if (!par->isVGA)
return -EINVAL;
shift = 3;
mode = MODE_SKIP4 | MODE_CFB;
maxmem = 16384;
par->pel_msk = 0x0F;
} else {
shift = 3;
mode = 0;
maxmem = 65536;
}
} else if (var->bits_per_pixel == 8) {
if (!par->isVGA)
return -EINVAL; /* no support on EGA */
shift = 2;
if (var->nonstd) {
mode = MODE_8BPP | MODE_CFB;
maxmem = 65536;
} else {
mode = MODE_SKIP4 | MODE_8BPP | MODE_CFB;
maxmem = 16384;
}
} else
return -EINVAL;
xres = (var->xres + 7) & ~7;
vxres = (var->xres_virtual + 0xF) & ~0xF;
xoffset = (var->xoffset + 7) & ~7;
left = (var->left_margin + 7) & ~7;
right = (var->right_margin + 7) & ~7;
hslen = (var->hsync_len + 7) & ~7;
if (vxres < xres)
vxres = xres;
if (xres + xoffset > vxres)
xoffset = vxres - xres;
var->xres = xres;
var->right_margin = right;
var->hsync_len = hslen;
var->left_margin = left;
var->xres_virtual = vxres;
var->xoffset = xoffset;
xres >>= shift;
right >>= shift;
hslen >>= shift;
left >>= shift;
vxres >>= shift;
xtotal = xres + right + hslen + left;
if (xtotal >= 256)
FAIL("xtotal too big");
if (hslen > 32)
FAIL("hslen too big");
if (right + hslen + left > 64)
FAIL("hblank too big");
par->crtc[VGA_CRTC_H_TOTAL] = xtotal - 5;
par->crtc[VGA_CRTC_H_BLANK_START] = xres - 1;
par->crtc[VGA_CRTC_H_DISP] = xres - 1;
pos = xres + right;
par->crtc[VGA_CRTC_H_SYNC_START] = pos;
pos += hslen;
par->crtc[VGA_CRTC_H_SYNC_END] = pos & 0x1F;
pos += left - 2; /* blank_end + 2 <= total + 5 */
par->crtc[VGA_CRTC_H_BLANK_END] = (pos & 0x1F) | 0x80;
if (pos & 0x20)
par->crtc[VGA_CRTC_H_SYNC_END] |= 0x80;
yres = var->yres;
lower = var->lower_margin;
vslen = var->vsync_len;
upper = var->upper_margin;
vyres = var->yres_virtual;
yoffset = var->yoffset;
if (yres > vyres)
vyres = yres;
if (vxres * vyres > maxmem) {
vyres = maxmem / vxres;
if (vyres < yres)
return -ENOMEM;
}
if (yoffset + yres > vyres)
yoffset = vyres - yres;
var->yres = yres;
var->lower_margin = lower;
var->vsync_len = vslen;
var->upper_margin = upper;
var->yres_virtual = vyres;
var->yoffset = yoffset;
if (var->vmode & FB_VMODE_DOUBLE) {
yres <<= 1;
lower <<= 1;
vslen <<= 1;
upper <<= 1;
}
ytotal = yres + lower + vslen + upper;
if (ytotal > 1024) {
ytotal >>= 1;
yres >>= 1;
lower >>= 1;
vslen >>= 1;
upper >>= 1;
rMode = 0x04;
} else
rMode = 0x00;
if (ytotal > 1024)
FAIL("ytotal too big");
if (vslen > 16)
FAIL("vslen too big");
par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
r7 = 0x10; /* disable linecompare */
if (ytotal & 0x100) r7 |= 0x01;
if (ytotal & 0x200) r7 |= 0x20;
par->crtc[VGA_CRTC_PRESET_ROW] = 0;
par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */
if (var->vmode & FB_VMODE_DOUBLE)
par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
par->crtc[VGA_CRTC_CURSOR_START] = 0x20;
par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
if ((mode & (MODE_CFB | MODE_8BPP)) == MODE_CFB)
xoffset--;
pos = yoffset * vxres + (xoffset >> shift);
par->crtc[VGA_CRTC_START_HI] = pos >> 8;
par->crtc[VGA_CRTC_START_LO] = pos & 0xFF;
par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
pos = yres - 1;
par->crtc[VGA_CRTC_V_DISP_END] = pos & 0xFF;
par->crtc[VGA_CRTC_V_BLANK_START] = pos & 0xFF;
if (pos & 0x100)
r7 |= 0x0A; /* 0x02 -> DISP_END, 0x08 -> BLANK_START */
if (pos & 0x200) {
r7 |= 0x40; /* 0x40 -> DISP_END */
par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20; /* BLANK_START */
}
pos += lower;
par->crtc[VGA_CRTC_V_SYNC_START] = pos & 0xFF;
if (pos & 0x100)
r7 |= 0x04;
if (pos & 0x200)
r7 |= 0x80;
pos += vslen;
par->crtc[VGA_CRTC_V_SYNC_END] = (pos & 0x0F) & ~0x10; /* disabled IRQ */
pos += upper - 1; /* blank_end + 1 <= ytotal + 2 */
par->crtc[VGA_CRTC_V_BLANK_END] = pos & 0xFF; /* 0x7F for original VGA,
but some SVGA chips requires all 8 bits to set */
if (vxres >= 512)
FAIL("vxres too long");
par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
if (mode & MODE_SKIP4)
par->crtc[VGA_CRTC_UNDERLINE] = 0x5F; /* 256, cfb8 */
else
par->crtc[VGA_CRTC_UNDERLINE] = 0x1F; /* 16, vgap */
par->crtc[VGA_CRTC_MODE] = rMode | ((mode & MODE_TEXT) ? 0xA3 : 0xE3);
par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
par->crtc[VGA_CRTC_OVERFLOW] = r7;
par->vss = 0x00; /* 3DA */
par->misc = 0xE3; /* enable CPU, ports 0x3Dx, positive sync */
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
par->misc &= ~0x40;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
par->misc &= ~0x80;
par->mode = mode;
if (mode & MODE_8BPP)
/* pixel clock == vga clock / 2 */
vga16fb_clock_chip(par, &var->pixclock, info, 1, 2);
else
/* pixel clock == vga clock */
vga16fb_clock_chip(par, &var->pixclock, info, 1, 1);
var->red.offset = var->green.offset = var->blue.offset =
var->transp.offset = 0;
var->red.length = var->green.length = var->blue.length =
(par->isVGA) ? 6 : 2;
var->transp.length = 0;
var->activate = FB_ACTIVATE_NOW;
var->height = -1;
var->width = -1;
var->accel_flags = 0;
return 0;
}
#undef FAIL
static int vga16fb_set_par(struct fb_info *info)
{
struct vga16fb_par *par = info->par;
u8 gdc[VGA_GFX_C];
u8 seq[VGA_SEQ_C];
u8 atc[VGA_ATT_C];
int fh, i;
seq[VGA_SEQ_CLOCK_MODE] = 0x01 | par->clkdiv;
if (par->mode & MODE_TEXT)
seq[VGA_SEQ_PLANE_WRITE] = 0x03;
else
seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
if (par->mode & MODE_TEXT)
seq[VGA_SEQ_MEMORY_MODE] = 0x03;
else if (par->mode & MODE_SKIP4)
seq[VGA_SEQ_MEMORY_MODE] = 0x0E;
else
seq[VGA_SEQ_MEMORY_MODE] = 0x06;
gdc[VGA_GFX_SR_VALUE] = 0x00;
gdc[VGA_GFX_SR_ENABLE] = 0x00;
gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
gdc[VGA_GFX_DATA_ROTATE] = 0x00;
gdc[VGA_GFX_PLANE_READ] = 0;
if (par->mode & MODE_TEXT) {
gdc[VGA_GFX_MODE] = 0x10;
gdc[VGA_GFX_MISC] = 0x06;
} else {
if (par->mode & MODE_CFB)
gdc[VGA_GFX_MODE] = 0x40;
else
gdc[VGA_GFX_MODE] = 0x00;
gdc[VGA_GFX_MISC] = 0x05;
}
gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
gdc[VGA_GFX_BIT_MASK] = 0xFF;
for (i = 0x00; i < 0x10; i++)
atc[i] = i;
if (par->mode & MODE_TEXT)
atc[VGA_ATC_MODE] = 0x04;
else if (par->mode & MODE_8BPP)
atc[VGA_ATC_MODE] = 0x41;
else
atc[VGA_ATC_MODE] = 0x81;
atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */
atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
if (par->mode & MODE_8BPP)
atc[VGA_ATC_PEL] = (info->var.xoffset & 3) << 1;
else
atc[VGA_ATC_PEL] = info->var.xoffset & 7;
atc[VGA_ATC_COLOR_PAGE] = 0x00;
if (par->mode & MODE_TEXT) {
fh = 16; // FIXME !!! Fudge font height.
par->crtc[VGA_CRTC_MAX_SCAN] = (par->crtc[VGA_CRTC_MAX_SCAN]
& ~0x1F) | (fh - 1);
}
vga_io_w(VGA_MIS_W, vga_io_r(VGA_MIS_R) | 0x01);
/* Enable graphics register modification */
if (!par->isVGA) {
vga_io_w(EGA_GFX_E0, 0x00);
vga_io_w(EGA_GFX_E1, 0x01);
}
/* update misc output register */
vga_io_w(VGA_MIS_W, par->misc);
/* synchronous reset on */
vga_io_wseq(0x00, 0x01);
if (par->isVGA)
vga_io_w(VGA_PEL_MSK, par->pel_msk);
/* write sequencer registers */
vga_io_wseq(VGA_SEQ_CLOCK_MODE, seq[VGA_SEQ_CLOCK_MODE] | 0x20);
for (i = 2; i < VGA_SEQ_C; i++) {
vga_io_wseq(i, seq[i]);
}
/* synchronous reset off */
vga_io_wseq(0x00, 0x03);
/* deprotect CRT registers 0-7 */
vga_io_wcrt(VGA_CRTC_V_SYNC_END, par->crtc[VGA_CRTC_V_SYNC_END]);
/* write CRT registers */
for (i = 0; i < VGA_CRTC_REGS; i++) {
vga_io_wcrt(i, par->crtc[i]);
}
/* write graphics controller registers */
for (i = 0; i < VGA_GFX_C; i++) {
vga_io_wgfx(i, gdc[i]);
}
/* write attribute controller registers */
for (i = 0; i < VGA_ATT_C; i++) {
vga_io_r(VGA_IS1_RC); /* reset flip-flop */
vga_io_wattr(i, atc[i]);
}
/* Wait for screen to stabilize. */
mdelay(50);
vga_io_wseq(VGA_SEQ_CLOCK_MODE, seq[VGA_SEQ_CLOCK_MODE]);
vga_io_r(VGA_IS1_RC);
vga_io_w(VGA_ATT_IW, 0x20);
vga16fb_update_fix(info);
return 0;
}
static void ega16_setpalette(int regno, unsigned red, unsigned green, unsigned blue)
{
static const unsigned char map[] = { 000, 001, 010, 011 };
int val;
if (regno >= 16)
return;
val = map[red>>14] | ((map[green>>14]) << 1) | ((map[blue>>14]) << 2);
vga_io_r(VGA_IS1_RC); /* ! 0x3BA */
vga_io_wattr(regno, val);
vga_io_r(VGA_IS1_RC); /* some clones need it */
vga_io_w(VGA_ATT_IW, 0x20); /* unblank screen */
}
static void vga16_setpalette(int regno, unsigned red, unsigned green, unsigned blue)
{
outb(regno, VGA_PEL_IW);
outb(red >> 10, VGA_PEL_D);
outb(green >> 10, VGA_PEL_D);
outb(blue >> 10, VGA_PEL_D);
}
static int vga16fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct vga16fb_par *par = info->par;
int gray;
/*
* Set a single color register. The values supplied are
* already rounded down to the hardware's capabilities
* (according to the entries in the `var' structure). Return
* != 0 for invalid regno.
*/
if (regno >= 256)
return 1;
gray = info->var.grayscale;
if (gray) {
/* gray = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
if (par->isVGA)
vga16_setpalette(regno,red,green,blue);
else
ega16_setpalette(regno,red,green,blue);
return 0;
}
static int vga16fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
vga16fb_pan_var(info, var);
return 0;
}
/* The following VESA blanking code is taken from vgacon.c. The VGA
blanking code was originally by Huang shi chao, and modified by
Christoph Rimek ([email protected]) and todd j. derr
([email protected]) for Linux. */
static void vga_vesa_blank(struct vga16fb_par *par, int mode)
{
unsigned char SeqCtrlIndex = vga_io_r(VGA_SEQ_I);
unsigned char CrtCtrlIndex = vga_io_r(VGA_CRT_IC);
/* save original values of VGA controller registers */
if(!par->vesa_blanked) {
par->vga_state.CrtMiscIO = vga_io_r(VGA_MIS_R);
//sti();
par->vga_state.HorizontalTotal = vga_io_rcrt(0x00); /* HorizontalTotal */
par->vga_state.HorizDisplayEnd = vga_io_rcrt(0x01); /* HorizDisplayEnd */
par->vga_state.StartHorizRetrace = vga_io_rcrt(0x04); /* StartHorizRetrace */
par->vga_state.EndHorizRetrace = vga_io_rcrt(0x05); /* EndHorizRetrace */
par->vga_state.Overflow = vga_io_rcrt(0x07); /* Overflow */
par->vga_state.StartVertRetrace = vga_io_rcrt(0x10); /* StartVertRetrace */
par->vga_state.EndVertRetrace = vga_io_rcrt(0x11); /* EndVertRetrace */
par->vga_state.ModeControl = vga_io_rcrt(0x17); /* ModeControl */
par->vga_state.ClockingMode = vga_io_rseq(0x01); /* ClockingMode */
}
/* assure that video is enabled */
/* "0x20" is VIDEO_ENABLE_bit in register 01 of sequencer */
vga_io_wseq(0x01, par->vga_state.ClockingMode | 0x20);
/* test for vertical retrace in process.... */
if ((par->vga_state.CrtMiscIO & 0x80) == 0x80)
vga_io_w(VGA_MIS_W, par->vga_state.CrtMiscIO & 0xef);
/*
* Set <End of vertical retrace> to minimum (0) and
* <Start of vertical Retrace> to maximum (incl. overflow)
* Result: turn off vertical sync (VSync) pulse.
*/
if (mode & FB_BLANK_VSYNC_SUSPEND) {
vga_io_wcrt(VGA_CRTC_V_SYNC_START, 0xff);
vga_io_wcrt(VGA_CRTC_V_SYNC_END, 0x40);
/* bits 9,10 of vert. retrace */
vga_io_wcrt(VGA_CRTC_OVERFLOW, par->vga_state.Overflow | 0x84);
}
if (mode & FB_BLANK_HSYNC_SUSPEND) {
/*
* Set <End of horizontal retrace> to minimum (0) and
* <Start of horizontal Retrace> to maximum
* Result: turn off horizontal sync (HSync) pulse.
*/
vga_io_wcrt(VGA_CRTC_H_SYNC_START, 0xff);
vga_io_wcrt(VGA_CRTC_H_SYNC_END, 0x00);
}
/* restore both index registers */
outb_p(SeqCtrlIndex, VGA_SEQ_I);
outb_p(CrtCtrlIndex, VGA_CRT_IC);
}
static void vga_vesa_unblank(struct vga16fb_par *par)
{
unsigned char SeqCtrlIndex = vga_io_r(VGA_SEQ_I);
unsigned char CrtCtrlIndex = vga_io_r(VGA_CRT_IC);
/* restore original values of VGA controller registers */
vga_io_w(VGA_MIS_W, par->vga_state.CrtMiscIO);
/* HorizontalTotal */
vga_io_wcrt(0x00, par->vga_state.HorizontalTotal);
/* HorizDisplayEnd */
vga_io_wcrt(0x01, par->vga_state.HorizDisplayEnd);
/* StartHorizRetrace */
vga_io_wcrt(0x04, par->vga_state.StartHorizRetrace);
/* EndHorizRetrace */
vga_io_wcrt(0x05, par->vga_state.EndHorizRetrace);
/* Overflow */
vga_io_wcrt(0x07, par->vga_state.Overflow);
/* StartVertRetrace */
vga_io_wcrt(0x10, par->vga_state.StartVertRetrace);
/* EndVertRetrace */
vga_io_wcrt(0x11, par->vga_state.EndVertRetrace);
/* ModeControl */
vga_io_wcrt(0x17, par->vga_state.ModeControl);
/* ClockingMode */
vga_io_wseq(0x01, par->vga_state.ClockingMode);
/* restore index/control registers */
vga_io_w(VGA_SEQ_I, SeqCtrlIndex);
vga_io_w(VGA_CRT_IC, CrtCtrlIndex);
}
static void vga_pal_blank(void)
{
int i;
for (i=0; i<16; i++) {
outb_p(i, VGA_PEL_IW);
outb_p(0, VGA_PEL_D);
outb_p(0, VGA_PEL_D);
outb_p(0, VGA_PEL_D);
}
}
/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
static int vga16fb_blank(int blank, struct fb_info *info)
{
struct vga16fb_par *par = info->par;
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblank */
if (par->vesa_blanked) {
vga_vesa_unblank(par);
par->vesa_blanked = 0;
}
if (par->palette_blanked) {
par->palette_blanked = 0;
}
break;
case FB_BLANK_NORMAL: /* blank */
vga_pal_blank();
par->palette_blanked = 1;
break;
default: /* VESA blanking */
vga_vesa_blank(par, blank);
par->vesa_blanked = 1;
break;
}
return 0;
}
static void vga_8planes_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
u32 dx = rect->dx, width = rect->width;
char oldindex = getindex();
char oldmode = setmode(0x40);
char oldmask = selectmask();
int line_ofs, height;
char oldop, oldsr;
char __iomem *where;
dx /= 4;
where = info->screen_base + dx + rect->dy * info->fix.line_length;
if (rect->rop == ROP_COPY) {
oldop = setop(0);
oldsr = setsr(0);
width /= 4;
line_ofs = info->fix.line_length - width;
setmask(0xff);
height = rect->height;
while (height--) {
int x;
/* we can do memset... */
for (x = width; x > 0; --x) {
writeb(rect->color, where);
where++;
}
where += line_ofs;
}
} else {
char oldcolor = setcolor(0xf);
int y;
oldop = setop(0x18);
oldsr = setsr(0xf);
setmask(0x0F);
for (y = 0; y < rect->height; y++) {
rmw(where);
rmw(where+1);
where += info->fix.line_length;
}
setcolor(oldcolor);
}
setmask(oldmask);
setsr(oldsr);
setop(oldop);
setmode(oldmode);
setindex(oldindex);
}
static void vga16fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
int x, x2, y2, vxres, vyres, width, height, line_ofs;
char __iomem *dst;
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
if (!rect->width || !rect->height || rect->dx > vxres || rect->dy > vyres)
return;
/* We could use hardware clipping but on many cards you get around
* hardware clipping by writing to framebuffer directly. */
x2 = rect->dx + rect->width;
y2 = rect->dy + rect->height;
x2 = x2 < vxres ? x2 : vxres;
y2 = y2 < vyres ? y2 : vyres;
width = x2 - rect->dx;
switch (info->fix.type) {
case FB_TYPE_VGA_PLANES:
if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
height = y2 - rect->dy;
width = rect->width/8;
line_ofs = info->fix.line_length - width;
dst = info->screen_base + (rect->dx/8) + rect->dy * info->fix.line_length;
switch (rect->rop) {
case ROP_COPY:
setmode(0);
setop(0);
setsr(0xf);
setcolor(rect->color);
selectmask();
setmask(0xff);
while (height--) {
for (x = 0; x < width; x++) {
writeb(0, dst);
dst++;
}
dst += line_ofs;
}
break;
case ROP_XOR:
setmode(0);
setop(0x18);
setsr(0xf);
setcolor(0xf);
selectmask();
setmask(0xff);
while (height--) {
for (x = 0; x < width; x++) {
rmw(dst);
dst++;
}
dst += line_ofs;
}
break;
}
} else
vga_8planes_fillrect(info, rect);
break;
case FB_TYPE_PACKED_PIXELS:
default:
cfb_fillrect(info, rect);
break;
}
}
static void vga_8planes_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
char oldindex = getindex();
char oldmode = setmode(0x41);
char oldop = setop(0);
char oldsr = setsr(0xf);
int height, line_ofs, x;
u32 sx, dx, width;
char __iomem *dest;
char __iomem *src;
height = area->height;
sx = area->sx / 4;
dx = area->dx / 4;
width = area->width / 4;
if (area->dy < area->sy || (area->dy == area->sy && dx < sx)) {
line_ofs = info->fix.line_length - width;
dest = info->screen_base + dx + area->dy * info->fix.line_length;
src = info->screen_base + sx + area->sy * info->fix.line_length;
while (height--) {
for (x = 0; x < width; x++) {
readb(src);
writeb(0, dest);
src++;
dest++;
}
src += line_ofs;
dest += line_ofs;
}
} else {
line_ofs = info->fix.line_length - width;
dest = info->screen_base + dx + width +
(area->dy + height - 1) * info->fix.line_length;
src = info->screen_base + sx + width +
(area->sy + height - 1) * info->fix.line_length;
while (height--) {
for (x = 0; x < width; x++) {
--src;
--dest;
readb(src);
writeb(0, dest);
}
src -= line_ofs;
dest -= line_ofs;
}
}
setsr(oldsr);
setop(oldop);
setmode(oldmode);
setindex(oldindex);
}
static void vga16fb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
int x, x2, y2, old_dx, old_dy, vxres, vyres;
int height, width, line_ofs;
char __iomem *dst = NULL;
char __iomem *src = NULL;
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
if (area->dx > vxres || area->sx > vxres || area->dy > vyres ||
area->sy > vyres)
return;
/* clip the destination */
old_dx = area->dx;
old_dy = area->dy;
/*
* We could use hardware clipping but on many cards you get around
* hardware clipping by writing to framebuffer directly.
*/
x2 = area->dx + area->width;
y2 = area->dy + area->height;
dx = area->dx > 0 ? area->dx : 0;
dy = area->dy > 0 ? area->dy : 0;
x2 = x2 < vxres ? x2 : vxres;
y2 = y2 < vyres ? y2 : vyres;
width = x2 - dx;
height = y2 - dy;
if (sx + dx < old_dx || sy + dy < old_dy)
return;
/* update sx1,sy1 */
sx += (dx - old_dx);
sy += (dy - old_dy);
/* the source must be completely inside the virtual screen */
if (sx + width > vxres || sy + height > vyres)
return;
switch (info->fix.type) {
case FB_TYPE_VGA_PLANES:
if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
width = width/8;
line_ofs = info->fix.line_length - width;
setmode(1);
setop(0);
setsr(0xf);
if (dy < sy || (dy == sy && dx < sx)) {
dst = info->screen_base + (dx/8) + dy * info->fix.line_length;
src = info->screen_base + (sx/8) + sy * info->fix.line_length;
while (height--) {
for (x = 0; x < width; x++) {
readb(src);
writeb(0, dst);
dst++;
src++;
}
src += line_ofs;
dst += line_ofs;
}
} else {
dst = info->screen_base + (dx/8) + width +
(dy + height - 1) * info->fix.line_length;
src = info->screen_base + (sx/8) + width +
(sy + height - 1) * info->fix.line_length;
while (height--) {
for (x = 0; x < width; x++) {
dst--;
src--;
readb(src);
writeb(0, dst);
}
src -= line_ofs;
dst -= line_ofs;
}
}
} else
vga_8planes_copyarea(info, area);
break;
case FB_TYPE_PACKED_PIXELS:
default:
cfb_copyarea(info, area);
break;
}
}
#define TRANS_MASK_LOW {0x0,0x8,0x4,0xC,0x2,0xA,0x6,0xE,0x1,0x9,0x5,0xD,0x3,0xB,0x7,0xF}
#define TRANS_MASK_HIGH {0x000, 0x800, 0x400, 0xC00, 0x200, 0xA00, 0x600, 0xE00, \
0x100, 0x900, 0x500, 0xD00, 0x300, 0xB00, 0x700, 0xF00}
#if defined(__LITTLE_ENDIAN)
static const u16 transl_l[] = TRANS_MASK_LOW;
static const u16 transl_h[] = TRANS_MASK_HIGH;
#elif defined(__BIG_ENDIAN)
static const u16 transl_l[] = TRANS_MASK_HIGH;
static const u16 transl_h[] = TRANS_MASK_LOW;
#else
#error "Only __BIG_ENDIAN and __LITTLE_ENDIAN are supported in vga-planes"
#endif
static void vga_8planes_imageblit(struct fb_info *info, const struct fb_image *image)
{
char oldindex = getindex();
char oldmode = setmode(0x40);
char oldop = setop(0);
char oldsr = setsr(0);
char oldmask = selectmask();
const unsigned char *cdat = image->data;
u32 dx = image->dx;
char __iomem *where;
int y;
dx /= 4;
where = info->screen_base + dx + image->dy * info->fix.line_length;
setmask(0xff);
writeb(image->bg_color, where);
readb(where);
selectmask();
setmask(image->fg_color ^ image->bg_color);
setmode(0x42);
setop(0x18);
for (y = 0; y < image->height; y++, where += info->fix.line_length)
writew(transl_h[cdat[y]&0xF] | transl_l[cdat[y] >> 4], where);
setmask(oldmask);
setsr(oldsr);
setop(oldop);
setmode(oldmode);
setindex(oldindex);
}
static void vga_imageblit_expand(struct fb_info *info, const struct fb_image *image)
{
char __iomem *where = info->screen_base + (image->dx/8) +
image->dy * info->fix.line_length;
struct vga16fb_par *par = info->par;
char *cdat = (char *) image->data;
char __iomem *dst;
int x, y;
switch (info->fix.type) {
case FB_TYPE_VGA_PLANES:
if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
if (par->isVGA) {
setmode(2);
setop(0);
setsr(0xf);
setcolor(image->fg_color);
selectmask();
setmask(0xff);
writeb(image->bg_color, where);
rmb();
readb(where); /* fill latches */
setmode(3);
wmb();
for (y = 0; y < image->height; y++) {
dst = where;
for (x = image->width/8; x--;)
writeb(*cdat++, dst++);
where += info->fix.line_length;
}
wmb();
} else {
setmode(0);
setop(0);
setsr(0xf);
setcolor(image->bg_color);
selectmask();
setmask(0xff);
for (y = 0; y < image->height; y++) {
dst = where;
for (x=image->width/8; x--;){
rmw(dst);
setcolor(image->fg_color);
selectmask();
if (*cdat) {
setmask(*cdat++);
rmw(dst++);
}
}
where += info->fix.line_length;
}
}
} else
vga_8planes_imageblit(info, image);
break;
case FB_TYPE_PACKED_PIXELS:
default:
cfb_imageblit(info, image);
break;
}
}
static void vga_imageblit_color(struct fb_info *info, const struct fb_image *image)
{
/*
* Draw logo
*/
struct vga16fb_par *par = info->par;
char __iomem *where =
info->screen_base + image->dy * info->fix.line_length +
image->dx/8;
const char *cdat = image->data;
char __iomem *dst;
int x, y;
switch (info->fix.type) {
case FB_TYPE_VGA_PLANES:
if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4 &&
par->isVGA) {
setsr(0xf);
setop(0);
setmode(0);
for (y = 0; y < image->height; y++) {
for (x = 0; x < image->width; x++) {
dst = where + x/8;
setcolor(*cdat);
selectmask();
setmask(1 << (7 - (x % 8)));
fb_readb(dst);
fb_writeb(0, dst);
cdat++;
}
where += info->fix.line_length;
}
}
break;
case FB_TYPE_PACKED_PIXELS:
cfb_imageblit(info, image);
break;
default:
break;
}
}
static void vga16fb_imageblit(struct fb_info *info, const struct fb_image *image)
{
if (image->depth == 1)
vga_imageblit_expand(info, image);
else
vga_imageblit_color(info, image);
}
static void vga16fb_destroy(struct fb_info *info)
{
iounmap(info->screen_base);
fb_dealloc_cmap(&info->cmap);
/* XXX unshare VGA regions */
framebuffer_release(info);
}
static const struct fb_ops vga16fb_ops = {
.owner = THIS_MODULE,
.fb_open = vga16fb_open,
.fb_release = vga16fb_release,
.fb_destroy = vga16fb_destroy,
.fb_check_var = vga16fb_check_var,
.fb_set_par = vga16fb_set_par,
.fb_setcolreg = vga16fb_setcolreg,
.fb_pan_display = vga16fb_pan_display,
.fb_blank = vga16fb_blank,
.fb_fillrect = vga16fb_fillrect,
.fb_copyarea = vga16fb_copyarea,
.fb_imageblit = vga16fb_imageblit,
};
static int vga16fb_probe(struct platform_device *dev)
{
struct screen_info *si;
struct fb_info *info;
struct vga16fb_par *par;
int i;
int ret = 0;
si = dev_get_platdata(&dev->dev);
if (!si)
return -ENODEV;
ret = check_mode_supported(si);
if (ret)
return ret;
printk(KERN_DEBUG "vga16fb: initializing\n");
info = framebuffer_alloc(sizeof(struct vga16fb_par), &dev->dev);
if (!info) {
ret = -ENOMEM;
goto err_fb_alloc;
}
/* XXX share VGA_FB_PHYS_BASE and I/O region with vgacon and others */
info->screen_base = (void __iomem *)VGA_MAP_MEM(VGA_FB_PHYS_BASE, 0);
if (!info->screen_base) {
printk(KERN_ERR "vga16fb: unable to map device\n");
ret = -ENOMEM;
goto err_ioremap;
}
printk(KERN_INFO "vga16fb: mapped to 0x%p\n", info->screen_base);
par = info->par;
#if defined(CONFIG_X86)
par->isVGA = si->orig_video_isVGA == VIDEO_TYPE_VGAC;
#else
/* non-x86 architectures treat orig_video_isVGA as a boolean flag */
par->isVGA = si->orig_video_isVGA;
#endif
par->palette_blanked = 0;
par->vesa_blanked = 0;
i = par->isVGA? 6 : 2;
vga16fb_defined.red.length = i;
vga16fb_defined.green.length = i;
vga16fb_defined.blue.length = i;
/* name should not depend on EGA/VGA */
info->fbops = &vga16fb_ops;
info->var = vga16fb_defined;
info->fix = vga16fb_fix;
/* supports rectangles with widths of multiples of 8 */
info->pixmap.blit_x = 1 << 7 | 1 << 15 | 1 << 23 | 1 << 31;
info->flags = FBINFO_HWACCEL_YPAN;
i = (info->var.bits_per_pixel == 8) ? 256 : 16;
ret = fb_alloc_cmap(&info->cmap, i, 0);
if (ret) {
printk(KERN_ERR "vga16fb: unable to allocate colormap\n");
ret = -ENOMEM;
goto err_alloc_cmap;
}
if (vga16fb_check_var(&info->var, info)) {
printk(KERN_ERR "vga16fb: unable to validate variable\n");
ret = -EINVAL;
goto err_check_var;
}
vga16fb_update_fix(info);
ret = devm_aperture_acquire_for_platform_device(dev, VGA_FB_PHYS_BASE, VGA_FB_PHYS_SIZE);
if (ret)
goto err_check_var;
if (register_framebuffer(info) < 0) {
printk(KERN_ERR "vga16fb: unable to register framebuffer\n");
ret = -EINVAL;
goto err_check_var;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
platform_set_drvdata(dev, info);
return 0;
err_check_var:
fb_dealloc_cmap(&info->cmap);
err_alloc_cmap:
iounmap(info->screen_base);
err_ioremap:
framebuffer_release(info);
err_fb_alloc:
return ret;
}
static void vga16fb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
if (info)
unregister_framebuffer(info);
}
static const struct platform_device_id vga16fb_driver_id_table[] = {
{"ega-framebuffer", 0},
{"vga-framebuffer", 0},
{ }
};
MODULE_DEVICE_TABLE(platform, vga16fb_driver_id_table);
static struct platform_driver vga16fb_driver = {
.probe = vga16fb_probe,
.remove_new = vga16fb_remove,
.driver = {
.name = "vga16fb",
},
.id_table = vga16fb_driver_id_table,
};
module_platform_driver(vga16fb_driver);
MODULE_DESCRIPTION("Legacy VGA framebuffer device driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/vga16fb.c |
/*
* platinumfb.c -- frame buffer device for the PowerMac 'platinum' display
*
* Copyright (C) 1998 Franz Sirl
*
* Frame buffer structure from:
* drivers/video/controlfb.c -- frame buffer device for
* Apple 'control' display chip.
* Copyright (C) 1998 Dan Jacobowitz
*
* Hardware information from:
* platinum.c: Console support for PowerMac "platinum" display adaptor.
* Copyright (C) 1996 Paul Mackerras and Mark Abene
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#undef DEBUG
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/nvram.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include "macmodes.h"
#include "platinumfb.h"
static int default_vmode = VMODE_NVRAM;
static int default_cmode = CMODE_NVRAM;
struct fb_info_platinum {
struct fb_info *info;
int vmode, cmode;
int xres, yres;
int vxres, vyres;
int xoffset, yoffset;
struct {
__u8 red, green, blue;
} palette[256];
u32 pseudo_palette[16];
volatile struct cmap_regs __iomem *cmap_regs;
unsigned long cmap_regs_phys;
volatile struct platinum_regs __iomem *platinum_regs;
unsigned long platinum_regs_phys;
__u8 __iomem *frame_buffer;
volatile __u8 __iomem *base_frame_buffer;
unsigned long frame_buffer_phys;
unsigned long total_vram;
int clktype;
int dactype;
struct resource rsrc_fb, rsrc_reg;
};
/*
* Frame buffer device API
*/
static int platinumfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int platinumfb_blank(int blank_mode, struct fb_info *info);
static int platinumfb_set_par (struct fb_info *info);
static int platinumfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info);
/*
* internal functions
*/
static inline int platinum_vram_reqd(int video_mode, int color_mode);
static int read_platinum_sense(struct fb_info_platinum *pinfo);
static void set_platinum_clock(struct fb_info_platinum *pinfo);
static void platinum_set_hardware(struct fb_info_platinum *pinfo);
static int platinum_var_to_par(struct fb_var_screeninfo *var,
struct fb_info_platinum *pinfo,
int check_only);
/*
* Interface used by the world
*/
static const struct fb_ops platinumfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = platinumfb_check_var,
.fb_set_par = platinumfb_set_par,
.fb_setcolreg = platinumfb_setcolreg,
.fb_blank = platinumfb_blank,
};
/*
* Checks a var structure
*/
static int platinumfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
{
return platinum_var_to_par(var, info->par, 1);
}
/*
* Applies current var to display
*/
static int platinumfb_set_par (struct fb_info *info)
{
struct fb_info_platinum *pinfo = info->par;
struct platinum_regvals *init;
int err, offset = 0x20;
if((err = platinum_var_to_par(&info->var, pinfo, 0))) {
printk (KERN_ERR "platinumfb_set_par: error calling"
" platinum_var_to_par: %d.\n", err);
return err;
}
platinum_set_hardware(pinfo);
init = platinum_reg_init[pinfo->vmode-1];
if ((pinfo->vmode == VMODE_832_624_75) && (pinfo->cmode > CMODE_8))
offset = 0x10;
info->screen_base = pinfo->frame_buffer + init->fb_offset + offset;
mutex_lock(&info->mm_lock);
info->fix.smem_start = (pinfo->frame_buffer_phys) + init->fb_offset + offset;
mutex_unlock(&info->mm_lock);
info->fix.visual = (pinfo->cmode == CMODE_8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
info->fix.line_length = vmode_attrs[pinfo->vmode-1].hres * (1<<pinfo->cmode)
+ offset;
printk("line_length: %x\n", info->fix.line_length);
return 0;
}
static int platinumfb_blank(int blank, struct fb_info *fb)
{
/*
* Blank the screen if blank_mode != 0, else unblank. If blank == NULL
* then the caller blanks by setting the CLUT (Color Look Up Table) to all
* black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
* to e.g. a video mode which doesn't support it. Implements VESA suspend
* and powerdown modes on hardware that supports disabling hsync/vsync:
* blank_mode == 2: suspend vsync
* blank_mode == 3: suspend hsync
* blank_mode == 4: powerdown
*/
/* [danj] I think there's something fishy about those constants... */
/*
struct fb_info_platinum *info = (struct fb_info_platinum *) fb;
int ctrl;
ctrl = le32_to_cpup(&info->platinum_regs->ctrl.r) | 0x33;
if (blank)
--blank_mode;
if (blank & VESA_VSYNC_SUSPEND)
ctrl &= ~3;
if (blank & VESA_HSYNC_SUSPEND)
ctrl &= ~0x30;
out_le32(&info->platinum_regs->ctrl.r, ctrl);
*/
/* TODO: Figure out how the heck to powerdown this thing! */
return 0;
}
static int platinumfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct fb_info_platinum *pinfo = info->par;
volatile struct cmap_regs __iomem *cmap_regs = pinfo->cmap_regs;
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
pinfo->palette[regno].red = red;
pinfo->palette[regno].green = green;
pinfo->palette[regno].blue = blue;
out_8(&cmap_regs->addr, regno); /* tell clut what addr to fill */
out_8(&cmap_regs->lut, red); /* send one color channel at */
out_8(&cmap_regs->lut, green); /* a time... */
out_8(&cmap_regs->lut, blue);
if (regno < 16) {
int i;
u32 *pal = info->pseudo_palette;
switch (pinfo->cmode) {
case CMODE_16:
pal[regno] = (regno << 10) | (regno << 5) | regno;
break;
case CMODE_32:
i = (regno << 8) | regno;
pal[regno] = (i << 16) | i;
break;
}
}
return 0;
}
static inline int platinum_vram_reqd(int video_mode, int color_mode)
{
int baseval = vmode_attrs[video_mode-1].hres * (1<<color_mode);
if ((video_mode == VMODE_832_624_75) && (color_mode > CMODE_8))
baseval += 0x10;
else
baseval += 0x20;
return vmode_attrs[video_mode-1].vres * baseval + 0x1000;
}
#define STORE_D2(a, d) { \
out_8(&cmap_regs->addr, (a+32)); \
out_8(&cmap_regs->d2, (d)); \
}
static void set_platinum_clock(struct fb_info_platinum *pinfo)
{
volatile struct cmap_regs __iomem *cmap_regs = pinfo->cmap_regs;
struct platinum_regvals *init;
init = platinum_reg_init[pinfo->vmode-1];
STORE_D2(6, 0xc6);
out_8(&cmap_regs->addr,3+32);
if (in_8(&cmap_regs->d2) == 2) {
STORE_D2(7, init->clock_params[pinfo->clktype][0]);
STORE_D2(8, init->clock_params[pinfo->clktype][1]);
STORE_D2(3, 3);
} else {
STORE_D2(4, init->clock_params[pinfo->clktype][0]);
STORE_D2(5, init->clock_params[pinfo->clktype][1]);
STORE_D2(3, 2);
}
__delay(5000);
STORE_D2(9, 0xa6);
}
/* Now how about actually saying, Make it so! */
/* Some things in here probably don't need to be done each time. */
static void platinum_set_hardware(struct fb_info_platinum *pinfo)
{
volatile struct platinum_regs __iomem *platinum_regs = pinfo->platinum_regs;
volatile struct cmap_regs __iomem *cmap_regs = pinfo->cmap_regs;
struct platinum_regvals *init;
int i;
int vmode, cmode;
vmode = pinfo->vmode;
cmode = pinfo->cmode;
init = platinum_reg_init[vmode - 1];
/* Initialize display timing registers */
out_be32(&platinum_regs->reg[24].r, 7); /* turn display off */
for (i = 0; i < 26; ++i)
out_be32(&platinum_regs->reg[i+32].r, init->regs[i]);
out_be32(&platinum_regs->reg[26+32].r, (pinfo->total_vram == 0x100000 ?
init->offset[cmode] + 4 - cmode :
init->offset[cmode]));
out_be32(&platinum_regs->reg[16].r, (unsigned) pinfo->frame_buffer_phys+init->fb_offset+0x10);
out_be32(&platinum_regs->reg[18].r, init->pitch[cmode]);
out_be32(&platinum_regs->reg[19].r, (pinfo->total_vram == 0x100000 ?
init->mode[cmode+1] :
init->mode[cmode]));
out_be32(&platinum_regs->reg[20].r, (pinfo->total_vram == 0x100000 ? 0x11 : 0x1011));
out_be32(&platinum_regs->reg[21].r, 0x100);
out_be32(&platinum_regs->reg[22].r, 1);
out_be32(&platinum_regs->reg[23].r, 1);
out_be32(&platinum_regs->reg[26].r, 0xc00);
out_be32(&platinum_regs->reg[27].r, 0x235);
/* out_be32(&platinum_regs->reg[27].r, 0x2aa); */
STORE_D2(0, (pinfo->total_vram == 0x100000 ?
init->dacula_ctrl[cmode] & 0xf :
init->dacula_ctrl[cmode]));
STORE_D2(1, 4);
STORE_D2(2, 0);
set_platinum_clock(pinfo);
out_be32(&platinum_regs->reg[24].r, 0); /* turn display on */
}
/*
* Set misc info vars for this driver
*/
static void platinum_init_info(struct fb_info *info,
struct fb_info_platinum *pinfo)
{
/* Fill fb_info */
info->fbops = &platinumfb_ops;
info->pseudo_palette = pinfo->pseudo_palette;
info->screen_base = pinfo->frame_buffer + 0x20;
fb_alloc_cmap(&info->cmap, 256, 0);
/* Fill fix common fields */
strcpy(info->fix.id, "platinum");
info->fix.mmio_start = pinfo->platinum_regs_phys;
info->fix.mmio_len = 0x1000;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.smem_start = pinfo->frame_buffer_phys + 0x20; /* will be updated later */
info->fix.smem_len = pinfo->total_vram - 0x20;
info->fix.ywrapstep = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.type_aux = 0;
info->fix.accel = FB_ACCEL_NONE;
}
static int platinum_init_fb(struct fb_info *info)
{
struct fb_info_platinum *pinfo = info->par;
struct fb_var_screeninfo var;
int sense, rc;
sense = read_platinum_sense(pinfo);
printk(KERN_INFO "platinumfb: Monitor sense value = 0x%x, ", sense);
if (IS_REACHABLE(CONFIG_NVRAM) && default_vmode == VMODE_NVRAM)
default_vmode = nvram_read_byte(NV_VMODE);
if (default_vmode <= 0 || default_vmode > VMODE_MAX ||
!platinum_reg_init[default_vmode - 1]) {
default_vmode = mac_map_monitor_sense(sense);
if (!platinum_reg_init[default_vmode - 1])
default_vmode = VMODE_640_480_60;
}
if (IS_REACHABLE(CONFIG_NVRAM) && default_cmode == CMODE_NVRAM)
default_cmode = nvram_read_byte(NV_CMODE);
if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
default_cmode = CMODE_8;
/*
* Reduce the pixel size if we don't have enough VRAM.
*/
while(default_cmode > CMODE_8 &&
platinum_vram_reqd(default_vmode, default_cmode) > pinfo->total_vram)
default_cmode--;
printk("platinumfb: Using video mode %d and color mode %d.\n", default_vmode, default_cmode);
/* Setup default var */
if (mac_vmode_to_var(default_vmode, default_cmode, &var) < 0) {
/* This shouldn't happen! */
printk("mac_vmode_to_var(%d, %d,) failed\n", default_vmode, default_cmode);
try_again:
default_vmode = VMODE_640_480_60;
default_cmode = CMODE_8;
if (mac_vmode_to_var(default_vmode, default_cmode, &var) < 0) {
printk(KERN_ERR "platinumfb: mac_vmode_to_var() failed\n");
return -ENXIO;
}
}
/* Initialize info structure */
platinum_init_info(info, pinfo);
/* Apply default var */
info->var = var;
var.activate = FB_ACTIVATE_NOW;
rc = fb_set_var(info, &var);
if (rc && (default_vmode != VMODE_640_480_60 || default_cmode != CMODE_8))
goto try_again;
/* Register with fbdev layer */
rc = register_framebuffer(info);
if (rc < 0)
return rc;
fb_info(info, "Apple Platinum frame buffer device\n");
return 0;
}
/*
* Get the monitor sense value.
* Note that this can be called before calibrate_delay,
* so we can't use udelay.
*/
static int read_platinum_sense(struct fb_info_platinum *info)
{
volatile struct platinum_regs __iomem *platinum_regs = info->platinum_regs;
int sense;
out_be32(&platinum_regs->reg[23].r, 7); /* turn off drivers */
__delay(2000);
sense = (~in_be32(&platinum_regs->reg[23].r) & 7) << 8;
/* drive each sense line low in turn and collect the other 2 */
out_be32(&platinum_regs->reg[23].r, 3); /* drive A low */
__delay(2000);
sense |= (~in_be32(&platinum_regs->reg[23].r) & 3) << 4;
out_be32(&platinum_regs->reg[23].r, 5); /* drive B low */
__delay(2000);
sense |= (~in_be32(&platinum_regs->reg[23].r) & 4) << 1;
sense |= (~in_be32(&platinum_regs->reg[23].r) & 1) << 2;
out_be32(&platinum_regs->reg[23].r, 6); /* drive C low */
__delay(2000);
sense |= (~in_be32(&platinum_regs->reg[23].r) & 6) >> 1;
out_be32(&platinum_regs->reg[23].r, 7); /* turn off drivers */
return sense;
}
/*
* This routine takes a user-supplied var, and picks the best vmode/cmode from it.
* It also updates the var structure to the actual mode data obtained
*/
static int platinum_var_to_par(struct fb_var_screeninfo *var,
struct fb_info_platinum *pinfo,
int check_only)
{
int vmode, cmode;
if (mac_var_to_vmode(var, &vmode, &cmode) != 0) {
printk(KERN_ERR "platinum_var_to_par: mac_var_to_vmode unsuccessful.\n");
printk(KERN_ERR "platinum_var_to_par: var->xres = %d\n", var->xres);
printk(KERN_ERR "platinum_var_to_par: var->yres = %d\n", var->yres);
printk(KERN_ERR "platinum_var_to_par: var->xres_virtual = %d\n", var->xres_virtual);
printk(KERN_ERR "platinum_var_to_par: var->yres_virtual = %d\n", var->yres_virtual);
printk(KERN_ERR "platinum_var_to_par: var->bits_per_pixel = %d\n", var->bits_per_pixel);
printk(KERN_ERR "platinum_var_to_par: var->pixclock = %d\n", var->pixclock);
printk(KERN_ERR "platinum_var_to_par: var->vmode = %d\n", var->vmode);
return -EINVAL;
}
if (!platinum_reg_init[vmode-1]) {
printk(KERN_ERR "platinum_var_to_par, vmode %d not valid.\n", vmode);
return -EINVAL;
}
if (platinum_vram_reqd(vmode, cmode) > pinfo->total_vram) {
printk(KERN_ERR "platinum_var_to_par, not enough ram for vmode %d, cmode %d.\n", vmode, cmode);
return -EINVAL;
}
if (mac_vmode_to_var(vmode, cmode, var))
return -EINVAL;
if (check_only)
return 0;
pinfo->vmode = vmode;
pinfo->cmode = cmode;
pinfo->xres = vmode_attrs[vmode-1].hres;
pinfo->yres = vmode_attrs[vmode-1].vres;
pinfo->xoffset = 0;
pinfo->yoffset = 0;
pinfo->vxres = pinfo->xres;
pinfo->vyres = pinfo->yres;
return 0;
}
/*
* Parse user specified options (`video=platinumfb:')
*/
static int __init platinumfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "vmode:", 6)) {
int vmode = simple_strtoul(this_opt+6, NULL, 0);
if (vmode > 0 && vmode <= VMODE_MAX)
default_vmode = vmode;
} else if (!strncmp(this_opt, "cmode:", 6)) {
int depth = simple_strtoul(this_opt+6, NULL, 0);
switch (depth) {
case 0:
case 8:
default_cmode = CMODE_8;
break;
case 15:
case 16:
default_cmode = CMODE_16;
break;
case 24:
case 32:
default_cmode = CMODE_32;
break;
}
}
}
return 0;
}
#ifdef __powerpc__
#define invalidate_cache(addr) \
asm volatile("eieio; dcbf 0,%1" \
: "=m" (*(addr)) : "r" (addr) : "memory");
#else
#define invalidate_cache(addr)
#endif
static int platinumfb_probe(struct platform_device* odev)
{
struct device_node *dp = odev->dev.of_node;
struct fb_info *info;
struct fb_info_platinum *pinfo;
volatile __u8 *fbuffer;
int bank0, bank1, bank2, bank3, rc;
dev_info(&odev->dev, "Found Apple Platinum video hardware\n");
info = framebuffer_alloc(sizeof(*pinfo), &odev->dev);
if (!info)
return -ENOMEM;
pinfo = info->par;
if (of_address_to_resource(dp, 0, &pinfo->rsrc_reg) ||
of_address_to_resource(dp, 1, &pinfo->rsrc_fb)) {
dev_err(&odev->dev, "Can't get resources\n");
framebuffer_release(info);
return -ENXIO;
}
dev_dbg(&odev->dev, " registers : 0x%llx...0x%llx\n",
(unsigned long long)pinfo->rsrc_reg.start,
(unsigned long long)pinfo->rsrc_reg.end);
dev_dbg(&odev->dev, " framebuffer: 0x%llx...0x%llx\n",
(unsigned long long)pinfo->rsrc_fb.start,
(unsigned long long)pinfo->rsrc_fb.end);
/* Do not try to request register space, they overlap with the
* northbridge and that can fail. Only request framebuffer
*/
if (!request_mem_region(pinfo->rsrc_fb.start,
resource_size(&pinfo->rsrc_fb),
"platinumfb framebuffer")) {
printk(KERN_ERR "platinumfb: Can't request framebuffer !\n");
framebuffer_release(info);
return -ENXIO;
}
/* frame buffer - map only 4MB */
pinfo->frame_buffer_phys = pinfo->rsrc_fb.start;
pinfo->frame_buffer = ioremap_wt(pinfo->rsrc_fb.start, 0x400000);
pinfo->base_frame_buffer = pinfo->frame_buffer;
/* registers */
pinfo->platinum_regs_phys = pinfo->rsrc_reg.start;
pinfo->platinum_regs = ioremap(pinfo->rsrc_reg.start, 0x1000);
pinfo->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
request_mem_region(pinfo->cmap_regs_phys, 0x1000, "platinumfb cmap");
pinfo->cmap_regs = ioremap(pinfo->cmap_regs_phys, 0x1000);
/* Grok total video ram */
out_be32(&pinfo->platinum_regs->reg[16].r, (unsigned)pinfo->frame_buffer_phys);
out_be32(&pinfo->platinum_regs->reg[20].r, 0x1011); /* select max vram */
out_be32(&pinfo->platinum_regs->reg[24].r, 0); /* switch in vram */
fbuffer = pinfo->base_frame_buffer;
fbuffer[0x100000] = 0x34;
fbuffer[0x100008] = 0x0;
invalidate_cache(&fbuffer[0x100000]);
fbuffer[0x200000] = 0x56;
fbuffer[0x200008] = 0x0;
invalidate_cache(&fbuffer[0x200000]);
fbuffer[0x300000] = 0x78;
fbuffer[0x300008] = 0x0;
invalidate_cache(&fbuffer[0x300000]);
bank0 = 1; /* builtin 1MB vram, always there */
bank1 = fbuffer[0x100000] == 0x34;
bank2 = fbuffer[0x200000] == 0x56;
bank3 = fbuffer[0x300000] == 0x78;
pinfo->total_vram = (bank0 + bank1 + bank2 + bank3) * 0x100000;
printk(KERN_INFO "platinumfb: Total VRAM = %dMB (%d%d%d%d)\n",
(unsigned int) (pinfo->total_vram / 1024 / 1024),
bank3, bank2, bank1, bank0);
/*
* Try to determine whether we have an old or a new DACula.
*/
out_8(&pinfo->cmap_regs->addr, 0x40);
pinfo->dactype = in_8(&pinfo->cmap_regs->d2);
switch (pinfo->dactype) {
case 0x3c:
pinfo->clktype = 1;
printk(KERN_INFO "platinumfb: DACula type 0x3c\n");
break;
case 0x84:
pinfo->clktype = 0;
printk(KERN_INFO "platinumfb: DACula type 0x84\n");
break;
default:
pinfo->clktype = 0;
printk(KERN_INFO "platinumfb: Unknown DACula type: %x\n", pinfo->dactype);
break;
}
dev_set_drvdata(&odev->dev, info);
rc = platinum_init_fb(info);
if (rc != 0) {
iounmap(pinfo->frame_buffer);
iounmap(pinfo->platinum_regs);
iounmap(pinfo->cmap_regs);
framebuffer_release(info);
}
return rc;
}
static void platinumfb_remove(struct platform_device* odev)
{
struct fb_info *info = dev_get_drvdata(&odev->dev);
struct fb_info_platinum *pinfo = info->par;
unregister_framebuffer (info);
/* Unmap frame buffer and registers */
iounmap(pinfo->frame_buffer);
iounmap(pinfo->platinum_regs);
iounmap(pinfo->cmap_regs);
release_mem_region(pinfo->rsrc_fb.start,
resource_size(&pinfo->rsrc_fb));
release_mem_region(pinfo->cmap_regs_phys, 0x1000);
framebuffer_release(info);
}
static struct of_device_id platinumfb_match[] =
{
{
.name = "platinum",
},
{},
};
static struct platform_driver platinum_driver =
{
.driver = {
.name = "platinumfb",
.of_match_table = platinumfb_match,
},
.probe = platinumfb_probe,
.remove_new = platinumfb_remove,
};
static int __init platinumfb_init(void)
{
#ifndef MODULE
char *option = NULL;
if (fb_get_options("platinumfb", &option))
return -ENODEV;
platinumfb_setup(option);
#endif
platform_driver_register(&platinum_driver);
return 0;
}
static void __exit platinumfb_exit(void)
{
platform_driver_unregister(&platinum_driver);
}
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("framebuffer driver for Apple Platinum video");
module_init(platinumfb_init);
#ifdef MODULE
module_exit(platinumfb_exit);
#endif
| linux-master | drivers/video/fbdev/platinumfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/* ffb.c: Creator/Elite3D frame buffer driver
*
* Copyright (C) 2003, 2006 David S. Miller ([email protected])
* Copyright (C) 1997,1998,1999 Jakub Jelinek ([email protected])
*
* Driver layout based loosely on tgafb.c, see that file for credits.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/timer.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/io.h>
#include <asm/upa.h>
#include <asm/fbio.h>
#include "sbuslib.h"
/*
* Local functions.
*/
static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
unsigned, struct fb_info *);
static int ffb_blank(int, struct fb_info *);
static void ffb_imageblit(struct fb_info *, const struct fb_image *);
static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *);
static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *);
static int ffb_sync(struct fb_info *);
static int ffb_mmap(struct fb_info *, struct vm_area_struct *);
static int ffb_ioctl(struct fb_info *, unsigned int, unsigned long);
static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *);
/*
* Frame buffer operations
*/
static const struct fb_ops ffb_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = ffb_setcolreg,
.fb_blank = ffb_blank,
.fb_pan_display = ffb_pan_display,
.fb_fillrect = ffb_fillrect,
.fb_copyarea = ffb_copyarea,
.fb_imageblit = ffb_imageblit,
.fb_sync = ffb_sync,
.fb_mmap = ffb_mmap,
.fb_ioctl = ffb_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = sbusfb_compat_ioctl,
#endif
};
/* Register layout and definitions */
#define FFB_SFB8R_VOFF 0x00000000
#define FFB_SFB8G_VOFF 0x00400000
#define FFB_SFB8B_VOFF 0x00800000
#define FFB_SFB8X_VOFF 0x00c00000
#define FFB_SFB32_VOFF 0x01000000
#define FFB_SFB64_VOFF 0x02000000
#define FFB_FBC_REGS_VOFF 0x04000000
#define FFB_BM_FBC_REGS_VOFF 0x04002000
#define FFB_DFB8R_VOFF 0x04004000
#define FFB_DFB8G_VOFF 0x04404000
#define FFB_DFB8B_VOFF 0x04804000
#define FFB_DFB8X_VOFF 0x04c04000
#define FFB_DFB24_VOFF 0x05004000
#define FFB_DFB32_VOFF 0x06004000
#define FFB_DFB422A_VOFF 0x07004000 /* DFB 422 mode write to A */
#define FFB_DFB422AD_VOFF 0x07804000 /* DFB 422 mode with line doubling */
#define FFB_DFB24B_VOFF 0x08004000 /* DFB 24bit mode write to B */
#define FFB_DFB422B_VOFF 0x09004000 /* DFB 422 mode write to B */
#define FFB_DFB422BD_VOFF 0x09804000 /* DFB 422 mode with line doubling */
#define FFB_SFB16Z_VOFF 0x0a004000 /* 16bit mode Z planes */
#define FFB_SFB8Z_VOFF 0x0a404000 /* 8bit mode Z planes */
#define FFB_SFB422_VOFF 0x0ac04000 /* SFB 422 mode write to A/B */
#define FFB_SFB422D_VOFF 0x0b404000 /* SFB 422 mode with line doubling */
#define FFB_FBC_KREGS_VOFF 0x0bc04000
#define FFB_DAC_VOFF 0x0bc06000
#define FFB_PROM_VOFF 0x0bc08000
#define FFB_EXP_VOFF 0x0bc18000
#define FFB_SFB8R_POFF 0x04000000UL
#define FFB_SFB8G_POFF 0x04400000UL
#define FFB_SFB8B_POFF 0x04800000UL
#define FFB_SFB8X_POFF 0x04c00000UL
#define FFB_SFB32_POFF 0x05000000UL
#define FFB_SFB64_POFF 0x06000000UL
#define FFB_FBC_REGS_POFF 0x00600000UL
#define FFB_BM_FBC_REGS_POFF 0x00600000UL
#define FFB_DFB8R_POFF 0x01000000UL
#define FFB_DFB8G_POFF 0x01400000UL
#define FFB_DFB8B_POFF 0x01800000UL
#define FFB_DFB8X_POFF 0x01c00000UL
#define FFB_DFB24_POFF 0x02000000UL
#define FFB_DFB32_POFF 0x03000000UL
#define FFB_FBC_KREGS_POFF 0x00610000UL
#define FFB_DAC_POFF 0x00400000UL
#define FFB_PROM_POFF 0x00000000UL
#define FFB_EXP_POFF 0x00200000UL
#define FFB_DFB422A_POFF 0x09000000UL
#define FFB_DFB422AD_POFF 0x09800000UL
#define FFB_DFB24B_POFF 0x0a000000UL
#define FFB_DFB422B_POFF 0x0b000000UL
#define FFB_DFB422BD_POFF 0x0b800000UL
#define FFB_SFB16Z_POFF 0x0c800000UL
#define FFB_SFB8Z_POFF 0x0c000000UL
#define FFB_SFB422_POFF 0x0d000000UL
#define FFB_SFB422D_POFF 0x0d800000UL
/* Draw operations */
#define FFB_DRAWOP_DOT 0x00
#define FFB_DRAWOP_AADOT 0x01
#define FFB_DRAWOP_BRLINECAP 0x02
#define FFB_DRAWOP_BRLINEOPEN 0x03
#define FFB_DRAWOP_DDLINE 0x04
#define FFB_DRAWOP_AALINE 0x05
#define FFB_DRAWOP_TRIANGLE 0x06
#define FFB_DRAWOP_POLYGON 0x07
#define FFB_DRAWOP_RECTANGLE 0x08
#define FFB_DRAWOP_FASTFILL 0x09
#define FFB_DRAWOP_BCOPY 0x0a
#define FFB_DRAWOP_VSCROLL 0x0b
/* Pixel processor control */
/* Force WID */
#define FFB_PPC_FW_DISABLE 0x800000
#define FFB_PPC_FW_ENABLE 0xc00000
/* Auxiliary clip */
#define FFB_PPC_ACE_DISABLE 0x040000
#define FFB_PPC_ACE_AUX_SUB 0x080000
#define FFB_PPC_ACE_AUX_ADD 0x0c0000
/* Depth cue */
#define FFB_PPC_DCE_DISABLE 0x020000
#define FFB_PPC_DCE_ENABLE 0x030000
/* Alpha blend */
#define FFB_PPC_ABE_DISABLE 0x008000
#define FFB_PPC_ABE_ENABLE 0x00c000
/* View clip */
#define FFB_PPC_VCE_DISABLE 0x001000
#define FFB_PPC_VCE_2D 0x002000
#define FFB_PPC_VCE_3D 0x003000
/* Area pattern */
#define FFB_PPC_APE_DISABLE 0x000800
#define FFB_PPC_APE_ENABLE 0x000c00
/* Transparent background */
#define FFB_PPC_TBE_OPAQUE 0x000200
#define FFB_PPC_TBE_TRANSPARENT 0x000300
/* Z source */
#define FFB_PPC_ZS_VAR 0x000080
#define FFB_PPC_ZS_CONST 0x0000c0
/* Y source */
#define FFB_PPC_YS_VAR 0x000020
#define FFB_PPC_YS_CONST 0x000030
/* X source */
#define FFB_PPC_XS_WID 0x000004
#define FFB_PPC_XS_VAR 0x000008
#define FFB_PPC_XS_CONST 0x00000c
/* Color (BGR) source */
#define FFB_PPC_CS_VAR 0x000002
#define FFB_PPC_CS_CONST 0x000003
#define FFB_ROP_NEW 0x83
#define FFB_ROP_OLD 0x85
#define FFB_ROP_NEW_XOR_OLD 0x86
#define FFB_UCSR_FIFO_MASK 0x00000fff
#define FFB_UCSR_FB_BUSY 0x01000000
#define FFB_UCSR_RP_BUSY 0x02000000
#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
#define FFB_UCSR_READ_ERR 0x40000000
#define FFB_UCSR_FIFO_OVFL 0x80000000
#define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
struct ffb_fbc {
/* Next vertex registers */
u32 xxx1[3];
u32 alpha;
u32 red;
u32 green;
u32 blue;
u32 depth;
u32 y;
u32 x;
u32 xxx2[2];
u32 ryf;
u32 rxf;
u32 xxx3[2];
u32 dmyf;
u32 dmxf;
u32 xxx4[2];
u32 ebyi;
u32 ebxi;
u32 xxx5[2];
u32 by;
u32 bx;
u32 dy;
u32 dx;
u32 bh;
u32 bw;
u32 xxx6[2];
u32 xxx7[32];
/* Setup unit vertex state register */
u32 suvtx;
u32 xxx8[63];
/* Control registers */
u32 ppc;
u32 wid;
u32 fg;
u32 bg;
u32 consty;
u32 constz;
u32 xclip;
u32 dcss;
u32 vclipmin;
u32 vclipmax;
u32 vclipzmin;
u32 vclipzmax;
u32 dcsf;
u32 dcsb;
u32 dczf;
u32 dczb;
u32 xxx9;
u32 blendc;
u32 blendc1;
u32 blendc2;
u32 fbramitc;
u32 fbc;
u32 rop;
u32 cmp;
u32 matchab;
u32 matchc;
u32 magnab;
u32 magnc;
u32 fbcfg0;
u32 fbcfg1;
u32 fbcfg2;
u32 fbcfg3;
u32 ppcfg;
u32 pick;
u32 fillmode;
u32 fbramwac;
u32 pmask;
u32 xpmask;
u32 ypmask;
u32 zpmask;
u32 clip0min;
u32 clip0max;
u32 clip1min;
u32 clip1max;
u32 clip2min;
u32 clip2max;
u32 clip3min;
u32 clip3max;
/* New 3dRAM III support regs */
u32 rawblend2;
u32 rawpreblend;
u32 rawstencil;
u32 rawstencilctl;
u32 threedram1;
u32 threedram2;
u32 passin;
u32 rawclrdepth;
u32 rawpmask;
u32 rawcsrc;
u32 rawmatch;
u32 rawmagn;
u32 rawropblend;
u32 rawcmp;
u32 rawwac;
u32 fbramid;
u32 drawop;
u32 xxx10[2];
u32 fontlpat;
u32 xxx11;
u32 fontxy;
u32 fontw;
u32 fontinc;
u32 font;
u32 xxx12[3];
u32 blend2;
u32 preblend;
u32 stencil;
u32 stencilctl;
u32 xxx13[4];
u32 dcss1;
u32 dcss2;
u32 dcss3;
u32 widpmask;
u32 dcs2;
u32 dcs3;
u32 dcs4;
u32 xxx14;
u32 dcd2;
u32 dcd3;
u32 dcd4;
u32 xxx15;
u32 pattern[32];
u32 xxx16[256];
u32 devid;
u32 xxx17[63];
u32 ucsr;
u32 xxx18[31];
u32 mer;
};
struct ffb_dac {
u32 type;
u32 value;
u32 type2;
u32 value2;
};
#define FFB_DAC_UCTRL 0x1001 /* User Control */
#define FFB_DAC_UCTRL_MANREV 0x00000f00 /* 4-bit Manufacturing Revision */
#define FFB_DAC_UCTRL_MANREV_SHIFT 8
#define FFB_DAC_TGEN 0x6000 /* Timing Generator */
#define FFB_DAC_TGEN_VIDE 0x00000001 /* Video Enable */
#define FFB_DAC_DID 0x8000 /* Device Identification */
#define FFB_DAC_DID_PNUM 0x0ffff000 /* Device Part Number */
#define FFB_DAC_DID_PNUM_SHIFT 12
#define FFB_DAC_DID_REV 0xf0000000 /* Device Revision */
#define FFB_DAC_DID_REV_SHIFT 28
#define FFB_DAC_CUR_CTRL 0x100
#define FFB_DAC_CUR_CTRL_P0 0x00000001
#define FFB_DAC_CUR_CTRL_P1 0x00000002
struct ffb_par {
spinlock_t lock;
struct ffb_fbc __iomem *fbc;
struct ffb_dac __iomem *dac;
u32 flags;
#define FFB_FLAG_AFB 0x00000001 /* AFB m3 or m6 */
#define FFB_FLAG_BLANKED 0x00000002 /* screen is blanked */
#define FFB_FLAG_INVCURSOR 0x00000004 /* DAC has inverted cursor logic */
u32 fg_cache __attribute__((aligned (8)));
u32 bg_cache;
u32 rop_cache;
int fifo_cache;
unsigned long physbase;
unsigned long fbsize;
int board_type;
u32 pseudo_palette[16];
};
static void FFBFifo(struct ffb_par *par, int n)
{
struct ffb_fbc __iomem *fbc;
int cache = par->fifo_cache;
if (cache - n < 0) {
fbc = par->fbc;
do {
cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK);
cache -= 8;
} while (cache - n < 0);
}
par->fifo_cache = cache - n;
}
static void FFBWait(struct ffb_par *par)
{
struct ffb_fbc __iomem *fbc;
int limit = 10000;
fbc = par->fbc;
do {
if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0)
break;
if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) {
upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
}
udelay(10);
} while (--limit > 0);
}
static int ffb_sync(struct fb_info *p)
{
struct ffb_par *par = (struct ffb_par *)p->par;
FFBWait(par);
return 0;
}
static __inline__ void ffb_rop(struct ffb_par *par, u32 rop)
{
if (par->rop_cache != rop) {
FFBFifo(par, 1);
upa_writel(rop, &par->fbc->rop);
par->rop_cache = rop;
}
}
static void ffb_switch_from_graph(struct ffb_par *par)
{
struct ffb_fbc __iomem *fbc = par->fbc;
struct ffb_dac __iomem *dac = par->dac;
unsigned long flags;
spin_lock_irqsave(&par->lock, flags);
FFBWait(par);
par->fifo_cache = 0;
FFBFifo(par, 7);
upa_writel(FFB_PPC_VCE_DISABLE | FFB_PPC_TBE_OPAQUE |
FFB_PPC_APE_DISABLE | FFB_PPC_CS_CONST,
&fbc->ppc);
upa_writel(0x2000707f, &fbc->fbc);
upa_writel(par->rop_cache, &fbc->rop);
upa_writel(0xffffffff, &fbc->pmask);
upa_writel((1 << 16) | (0 << 0), &fbc->fontinc);
upa_writel(par->fg_cache, &fbc->fg);
upa_writel(par->bg_cache, &fbc->bg);
FFBWait(par);
/* Disable cursor. */
upa_writel(FFB_DAC_CUR_CTRL, &dac->type2);
if (par->flags & FFB_FLAG_INVCURSOR)
upa_writel(0, &dac->value2);
else
upa_writel((FFB_DAC_CUR_CTRL_P0 |
FFB_DAC_CUR_CTRL_P1), &dac->value2);
spin_unlock_irqrestore(&par->lock, flags);
}
static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct ffb_par *par = (struct ffb_par *)info->par;
/* We just use this to catch switches out of
* graphics mode.
*/
ffb_switch_from_graph(par);
if (var->xoffset || var->yoffset || var->vmode)
return -EINVAL;
return 0;
}
/**
* ffb_fillrect - Draws a rectangle on the screen.
*
* @info: frame buffer structure that represents a single frame buffer
* @rect: structure defining the rectagle and operation.
*/
static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct ffb_par *par = (struct ffb_par *)info->par;
struct ffb_fbc __iomem *fbc = par->fbc;
unsigned long flags;
u32 fg;
BUG_ON(rect->rop != ROP_COPY && rect->rop != ROP_XOR);
fg = ((u32 *)info->pseudo_palette)[rect->color];
spin_lock_irqsave(&par->lock, flags);
if (fg != par->fg_cache) {
FFBFifo(par, 1);
upa_writel(fg, &fbc->fg);
par->fg_cache = fg;
}
ffb_rop(par, rect->rop == ROP_COPY ?
FFB_ROP_NEW :
FFB_ROP_NEW_XOR_OLD);
FFBFifo(par, 5);
upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop);
upa_writel(rect->dy, &fbc->by);
upa_writel(rect->dx, &fbc->bx);
upa_writel(rect->height, &fbc->bh);
upa_writel(rect->width, &fbc->bw);
spin_unlock_irqrestore(&par->lock, flags);
}
/**
* ffb_copyarea - Copies on area of the screen to another area.
*
* @info: frame buffer structure that represents a single frame buffer
* @area: structure defining the source and destination.
*/
static void ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct ffb_par *par = (struct ffb_par *)info->par;
struct ffb_fbc __iomem *fbc = par->fbc;
unsigned long flags;
if (area->dx != area->sx ||
area->dy == area->sy) {
cfb_copyarea(info, area);
return;
}
spin_lock_irqsave(&par->lock, flags);
ffb_rop(par, FFB_ROP_OLD);
FFBFifo(par, 7);
upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop);
upa_writel(area->sy, &fbc->by);
upa_writel(area->sx, &fbc->bx);
upa_writel(area->dy, &fbc->dy);
upa_writel(area->dx, &fbc->dx);
upa_writel(area->height, &fbc->bh);
upa_writel(area->width, &fbc->bw);
spin_unlock_irqrestore(&par->lock, flags);
}
/**
* ffb_imageblit - Copies a image from system memory to the screen.
*
* @info: frame buffer structure that represents a single frame buffer
* @image: structure defining the image.
*/
static void ffb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct ffb_par *par = (struct ffb_par *)info->par;
struct ffb_fbc __iomem *fbc = par->fbc;
const u8 *data = image->data;
unsigned long flags;
u32 fg, bg, xy;
u64 fgbg;
int i, width, stride;
if (image->depth > 1) {
cfb_imageblit(info, image);
return;
}
fg = ((u32 *)info->pseudo_palette)[image->fg_color];
bg = ((u32 *)info->pseudo_palette)[image->bg_color];
fgbg = ((u64) fg << 32) | (u64) bg;
xy = (image->dy << 16) | image->dx;
width = image->width;
stride = ((width + 7) >> 3);
spin_lock_irqsave(&par->lock, flags);
if (fgbg != *(u64 *)&par->fg_cache) {
FFBFifo(par, 2);
upa_writeq(fgbg, &fbc->fg);
*(u64 *)&par->fg_cache = fgbg;
}
if (width >= 32) {
FFBFifo(par, 1);
upa_writel(32, &fbc->fontw);
}
while (width >= 32) {
const u8 *next_data = data + 4;
FFBFifo(par, 1);
upa_writel(xy, &fbc->fontxy);
xy += (32 << 0);
for (i = 0; i < image->height; i++) {
u32 val = (((u32)data[0] << 24) |
((u32)data[1] << 16) |
((u32)data[2] << 8) |
((u32)data[3] << 0));
FFBFifo(par, 1);
upa_writel(val, &fbc->font);
data += stride;
}
data = next_data;
width -= 32;
}
if (width) {
FFBFifo(par, 2);
upa_writel(width, &fbc->fontw);
upa_writel(xy, &fbc->fontxy);
for (i = 0; i < image->height; i++) {
u32 val = (((u32)data[0] << 24) |
((u32)data[1] << 16) |
((u32)data[2] << 8) |
((u32)data[3] << 0));
FFBFifo(par, 1);
upa_writel(val, &fbc->font);
data += stride;
}
}
spin_unlock_irqrestore(&par->lock, flags);
}
static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var)
{
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
}
/**
* ffb_setcolreg - Sets a color register.
*
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*/
static int ffb_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
u32 value;
if (regno >= 16)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
value = (blue << 16) | (green << 8) | red;
((u32 *)info->pseudo_palette)[regno] = value;
return 0;
}
/**
* ffb_blank - Optional function. Blanks the display.
* @blank: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int ffb_blank(int blank, struct fb_info *info)
{
struct ffb_par *par = (struct ffb_par *)info->par;
struct ffb_dac __iomem *dac = par->dac;
unsigned long flags;
u32 val;
int i;
spin_lock_irqsave(&par->lock, flags);
FFBWait(par);
upa_writel(FFB_DAC_TGEN, &dac->type);
val = upa_readl(&dac->value);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
val |= FFB_DAC_TGEN_VIDE;
par->flags &= ~FFB_FLAG_BLANKED;
break;
case FB_BLANK_NORMAL: /* Normal blanking */
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
case FB_BLANK_POWERDOWN: /* Poweroff */
val &= ~FFB_DAC_TGEN_VIDE;
par->flags |= FFB_FLAG_BLANKED;
break;
}
upa_writel(FFB_DAC_TGEN, &dac->type);
upa_writel(val, &dac->value);
for (i = 0; i < 10; i++) {
upa_writel(FFB_DAC_TGEN, &dac->type);
upa_readl(&dac->value);
}
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
static struct sbus_mmap_map ffb_mmap_map[] = {
{
.voff = FFB_SFB8R_VOFF,
.poff = FFB_SFB8R_POFF,
.size = 0x0400000
},
{
.voff = FFB_SFB8G_VOFF,
.poff = FFB_SFB8G_POFF,
.size = 0x0400000
},
{
.voff = FFB_SFB8B_VOFF,
.poff = FFB_SFB8B_POFF,
.size = 0x0400000
},
{
.voff = FFB_SFB8X_VOFF,
.poff = FFB_SFB8X_POFF,
.size = 0x0400000
},
{
.voff = FFB_SFB32_VOFF,
.poff = FFB_SFB32_POFF,
.size = 0x1000000
},
{
.voff = FFB_SFB64_VOFF,
.poff = FFB_SFB64_POFF,
.size = 0x2000000
},
{
.voff = FFB_FBC_REGS_VOFF,
.poff = FFB_FBC_REGS_POFF,
.size = 0x0002000
},
{
.voff = FFB_BM_FBC_REGS_VOFF,
.poff = FFB_BM_FBC_REGS_POFF,
.size = 0x0002000
},
{
.voff = FFB_DFB8R_VOFF,
.poff = FFB_DFB8R_POFF,
.size = 0x0400000
},
{
.voff = FFB_DFB8G_VOFF,
.poff = FFB_DFB8G_POFF,
.size = 0x0400000
},
{
.voff = FFB_DFB8B_VOFF,
.poff = FFB_DFB8B_POFF,
.size = 0x0400000
},
{
.voff = FFB_DFB8X_VOFF,
.poff = FFB_DFB8X_POFF,
.size = 0x0400000
},
{
.voff = FFB_DFB24_VOFF,
.poff = FFB_DFB24_POFF,
.size = 0x1000000
},
{
.voff = FFB_DFB32_VOFF,
.poff = FFB_DFB32_POFF,
.size = 0x1000000
},
{
.voff = FFB_FBC_KREGS_VOFF,
.poff = FFB_FBC_KREGS_POFF,
.size = 0x0002000
},
{
.voff = FFB_DAC_VOFF,
.poff = FFB_DAC_POFF,
.size = 0x0002000
},
{
.voff = FFB_PROM_VOFF,
.poff = FFB_PROM_POFF,
.size = 0x0010000
},
{
.voff = FFB_EXP_VOFF,
.poff = FFB_EXP_POFF,
.size = 0x0002000
},
{
.voff = FFB_DFB422A_VOFF,
.poff = FFB_DFB422A_POFF,
.size = 0x0800000
},
{
.voff = FFB_DFB422AD_VOFF,
.poff = FFB_DFB422AD_POFF,
.size = 0x0800000
},
{
.voff = FFB_DFB24B_VOFF,
.poff = FFB_DFB24B_POFF,
.size = 0x1000000
},
{
.voff = FFB_DFB422B_VOFF,
.poff = FFB_DFB422B_POFF,
.size = 0x0800000
},
{
.voff = FFB_DFB422BD_VOFF,
.poff = FFB_DFB422BD_POFF,
.size = 0x0800000
},
{
.voff = FFB_SFB16Z_VOFF,
.poff = FFB_SFB16Z_POFF,
.size = 0x0800000
},
{
.voff = FFB_SFB8Z_VOFF,
.poff = FFB_SFB8Z_POFF,
.size = 0x0800000
},
{
.voff = FFB_SFB422_VOFF,
.poff = FFB_SFB422_POFF,
.size = 0x0800000
},
{
.voff = FFB_SFB422D_VOFF,
.poff = FFB_SFB422D_POFF,
.size = 0x0800000
},
{ .size = 0 }
};
static int ffb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct ffb_par *par = (struct ffb_par *)info->par;
return sbusfb_mmap_helper(ffb_mmap_map,
par->physbase, par->fbsize,
0, vma);
}
static int ffb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
struct ffb_par *par = (struct ffb_par *)info->par;
return sbusfb_ioctl_helper(cmd, arg, info,
FBTYPE_CREATOR, 24, par->fbsize);
}
/*
* Initialisation
*/
static void ffb_init_fix(struct fb_info *info)
{
struct ffb_par *par = (struct ffb_par *)info->par;
const char *ffb_type_name;
if (!(par->flags & FFB_FLAG_AFB)) {
if ((par->board_type & 0x7) == 0x3)
ffb_type_name = "Creator 3D";
else
ffb_type_name = "Creator";
} else
ffb_type_name = "Elite 3D";
strscpy(info->fix.id, ffb_type_name, sizeof(info->fix.id));
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_TRUECOLOR;
/* Framebuffer length is the same regardless of resolution. */
info->fix.line_length = 8192;
info->fix.accel = FB_ACCEL_SUN_CREATOR;
}
static int ffb_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct ffb_fbc __iomem *fbc;
struct ffb_dac __iomem *dac;
struct fb_info *info;
struct ffb_par *par;
u32 dac_pnum, dac_rev, dac_mrev;
int err;
info = framebuffer_alloc(sizeof(struct ffb_par), &op->dev);
err = -ENOMEM;
if (!info)
goto out_err;
par = info->par;
spin_lock_init(&par->lock);
par->fbc = of_ioremap(&op->resource[2], 0,
sizeof(struct ffb_fbc), "ffb fbc");
if (!par->fbc)
goto out_release_fb;
par->dac = of_ioremap(&op->resource[1], 0,
sizeof(struct ffb_dac), "ffb dac");
if (!par->dac)
goto out_unmap_fbc;
par->rop_cache = FFB_ROP_NEW;
par->physbase = op->resource[0].start;
/* Don't mention copyarea, so SCROLL_REDRAW is always
* used. It is the fastest on this chip.
*/
info->flags = (/* FBINFO_HWACCEL_COPYAREA | */
FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_IMAGEBLIT);
info->fbops = &ffb_ops;
info->screen_base = (char *) par->physbase + FFB_DFB24_POFF;
info->pseudo_palette = par->pseudo_palette;
sbusfb_fill_var(&info->var, dp, 32);
par->fbsize = PAGE_ALIGN(info->var.xres * info->var.yres * 4);
ffb_fixup_var_rgb(&info->var);
info->var.accel_flags = FB_ACCELF_TEXT;
if (of_node_name_eq(dp, "SUNW,afb"))
par->flags |= FFB_FLAG_AFB;
par->board_type = of_getintprop_default(dp, "board_type", 0);
fbc = par->fbc;
if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
dac = par->dac;
upa_writel(FFB_DAC_DID, &dac->type);
dac_pnum = upa_readl(&dac->value);
dac_rev = (dac_pnum & FFB_DAC_DID_REV) >> FFB_DAC_DID_REV_SHIFT;
dac_pnum = (dac_pnum & FFB_DAC_DID_PNUM) >> FFB_DAC_DID_PNUM_SHIFT;
upa_writel(FFB_DAC_UCTRL, &dac->type);
dac_mrev = upa_readl(&dac->value);
dac_mrev = (dac_mrev & FFB_DAC_UCTRL_MANREV) >>
FFB_DAC_UCTRL_MANREV_SHIFT;
/* Elite3D has different DAC revision numbering, and no DAC revisions
* have the reversed meaning of cursor enable. Otherwise, Pacifica 1
* ramdacs with manufacturing revision less than 3 have inverted
* cursor logic. We identify Pacifica 1 as not Pacifica 2, the
* latter having a part number value of 0x236e.
*/
if ((par->flags & FFB_FLAG_AFB) || dac_pnum == 0x236e) {
par->flags &= ~FFB_FLAG_INVCURSOR;
} else {
if (dac_mrev < 3)
par->flags |= FFB_FLAG_INVCURSOR;
}
ffb_switch_from_graph(par);
/* Unblank it just to be sure. When there are multiple
* FFB/AFB cards in the system, or it is not the OBP
* chosen console, it will have video outputs off in
* the DAC.
*/
ffb_blank(FB_BLANK_UNBLANK, info);
if (fb_alloc_cmap(&info->cmap, 256, 0))
goto out_unmap_dac;
ffb_init_fix(info);
err = register_framebuffer(info);
if (err < 0)
goto out_dealloc_cmap;
dev_set_drvdata(&op->dev, info);
printk(KERN_INFO "%pOF: %s at %016lx, type %d, "
"DAC pnum[%x] rev[%d] manuf_rev[%d]\n",
dp,
((par->flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
par->physbase, par->board_type,
dac_pnum, dac_rev, dac_mrev);
return 0;
out_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
out_unmap_dac:
of_iounmap(&op->resource[1], par->dac, sizeof(struct ffb_dac));
out_unmap_fbc:
of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
out_release_fb:
framebuffer_release(info);
out_err:
return err;
}
static void ffb_remove(struct platform_device *op)
{
struct fb_info *info = dev_get_drvdata(&op->dev);
struct ffb_par *par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
of_iounmap(&op->resource[2], par->fbc, sizeof(struct ffb_fbc));
of_iounmap(&op->resource[1], par->dac, sizeof(struct ffb_dac));
framebuffer_release(info);
}
static const struct of_device_id ffb_match[] = {
{
.name = "SUNW,ffb",
},
{
.name = "SUNW,afb",
},
{},
};
MODULE_DEVICE_TABLE(of, ffb_match);
static struct platform_driver ffb_driver = {
.driver = {
.name = "ffb",
.of_match_table = ffb_match,
},
.probe = ffb_probe,
.remove_new = ffb_remove,
};
static int __init ffb_init(void)
{
if (fb_get_options("ffb", NULL))
return -ENODEV;
return platform_driver_register(&ffb_driver);
}
static void __exit ffb_exit(void)
{
platform_driver_unregister(&ffb_driver);
}
module_init(ffb_init);
module_exit(ffb_exit);
MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/ffb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Cobalt/SEAD3 LCD frame buffer driver.
*
* Copyright (C) 2008 Yoichi Yuasa <[email protected]>
* Copyright (C) 2012 MIPS Technologies, Inc.
*/
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/uaccess.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/sched/signal.h>
/*
* Cursor position address
* \X 0 1 2 ... 14 15
* Y+----+----+----+---+----+----+
* 0|0x00|0x01|0x02|...|0x0e|0x0f|
* +----+----+----+---+----+----+
* 1|0x40|0x41|0x42|...|0x4e|0x4f|
* +----+----+----+---+----+----+
*/
#define LCD_DATA_REG_OFFSET 0x10
#define LCD_XRES_MAX 16
#define LCD_YRES_MAX 2
#define LCD_CHARS_MAX 32
#define LCD_CLEAR 0x01
#define LCD_CURSOR_MOVE_HOME 0x02
#define LCD_RESET 0x06
#define LCD_OFF 0x08
#define LCD_CURSOR_OFF 0x0c
#define LCD_CURSOR_BLINK_OFF 0x0e
#define LCD_CURSOR_ON 0x0f
#define LCD_ON LCD_CURSOR_ON
#define LCD_CURSOR_MOVE_LEFT 0x10
#define LCD_CURSOR_MOVE_RIGHT 0x14
#define LCD_DISPLAY_LEFT 0x18
#define LCD_DISPLAY_RIGHT 0x1c
#define LCD_PRERESET 0x3f /* execute 4 times continuously */
#define LCD_BUSY 0x80
#define LCD_GRAPHIC_MODE 0x40
#define LCD_TEXT_MODE 0x80
#define LCD_CUR_POS_MASK 0x7f
#define LCD_CUR_POS(x) ((x) & LCD_CUR_POS_MASK)
#define LCD_TEXT_POS(x) ((x) | LCD_TEXT_MODE)
static inline void lcd_write_control(struct fb_info *info, u8 control)
{
writel((u32)control << 24, info->screen_base);
}
static inline u8 lcd_read_control(struct fb_info *info)
{
return readl(info->screen_base) >> 24;
}
static inline void lcd_write_data(struct fb_info *info, u8 data)
{
writel((u32)data << 24, info->screen_base + LCD_DATA_REG_OFFSET);
}
static inline u8 lcd_read_data(struct fb_info *info)
{
return readl(info->screen_base + LCD_DATA_REG_OFFSET) >> 24;
}
static int lcd_busy_wait(struct fb_info *info)
{
u8 val = 0;
int timeout = 10, retval = 0;
do {
val = lcd_read_control(info);
val &= LCD_BUSY;
if (val != LCD_BUSY)
break;
if (msleep_interruptible(1))
return -EINTR;
timeout--;
} while (timeout);
if (val == LCD_BUSY)
retval = -EBUSY;
return retval;
}
static void lcd_clear(struct fb_info *info)
{
int i;
for (i = 0; i < 4; i++) {
udelay(150);
lcd_write_control(info, LCD_PRERESET);
}
udelay(150);
lcd_write_control(info, LCD_CLEAR);
udelay(150);
lcd_write_control(info, LCD_RESET);
}
static const struct fb_fix_screeninfo cobalt_lcdfb_fix = {
.id = "cobalt-lcd",
.type = FB_TYPE_TEXT,
.type_aux = FB_AUX_TEXT_MDA,
.visual = FB_VISUAL_MONO01,
.line_length = LCD_XRES_MAX,
.accel = FB_ACCEL_NONE,
};
static ssize_t cobalt_lcdfb_read(struct fb_info *info, char __user *buf,
size_t count, loff_t *ppos)
{
char src[LCD_CHARS_MAX];
unsigned long pos;
int len, retval = 0;
if (!info->screen_base)
return -ENODEV;
pos = *ppos;
if (pos >= LCD_CHARS_MAX || count == 0)
return 0;
if (count > LCD_CHARS_MAX)
count = LCD_CHARS_MAX;
if (pos + count > LCD_CHARS_MAX)
count = LCD_CHARS_MAX - pos;
for (len = 0; len < count; len++) {
retval = lcd_busy_wait(info);
if (retval < 0)
break;
lcd_write_control(info, LCD_TEXT_POS(pos));
retval = lcd_busy_wait(info);
if (retval < 0)
break;
src[len] = lcd_read_data(info);
if (pos == 0x0f)
pos = 0x40;
else
pos++;
}
if (retval < 0 && signal_pending(current))
return -ERESTARTSYS;
if (copy_to_user(buf, src, len))
return -EFAULT;
*ppos += len;
return len;
}
static ssize_t cobalt_lcdfb_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos)
{
char dst[LCD_CHARS_MAX];
unsigned long pos;
int len, retval = 0;
if (!info->screen_base)
return -ENODEV;
pos = *ppos;
if (pos >= LCD_CHARS_MAX || count == 0)
return 0;
if (count > LCD_CHARS_MAX)
count = LCD_CHARS_MAX;
if (pos + count > LCD_CHARS_MAX)
count = LCD_CHARS_MAX - pos;
if (copy_from_user(dst, buf, count))
return -EFAULT;
for (len = 0; len < count; len++) {
retval = lcd_busy_wait(info);
if (retval < 0)
break;
lcd_write_control(info, LCD_TEXT_POS(pos));
retval = lcd_busy_wait(info);
if (retval < 0)
break;
lcd_write_data(info, dst[len]);
if (pos == 0x0f)
pos = 0x40;
else
pos++;
}
if (retval < 0 && signal_pending(current))
return -ERESTARTSYS;
*ppos += len;
return len;
}
static int cobalt_lcdfb_blank(int blank_mode, struct fb_info *info)
{
int retval;
retval = lcd_busy_wait(info);
if (retval < 0)
return retval;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
lcd_write_control(info, LCD_ON);
break;
default:
lcd_write_control(info, LCD_OFF);
break;
}
return 0;
}
static int cobalt_lcdfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
u32 x, y;
int retval;
switch (cursor->set) {
case FB_CUR_SETPOS:
x = cursor->image.dx;
y = cursor->image.dy;
if (x >= LCD_XRES_MAX || y >= LCD_YRES_MAX)
return -EINVAL;
retval = lcd_busy_wait(info);
if (retval < 0)
return retval;
lcd_write_control(info,
LCD_TEXT_POS(info->fix.line_length * y + x));
break;
default:
return -EINVAL;
}
retval = lcd_busy_wait(info);
if (retval < 0)
return retval;
if (cursor->enable)
lcd_write_control(info, LCD_CURSOR_ON);
else
lcd_write_control(info, LCD_CURSOR_OFF);
return 0;
}
static const struct fb_ops cobalt_lcd_fbops = {
.owner = THIS_MODULE,
.fb_read = cobalt_lcdfb_read,
.fb_write = cobalt_lcdfb_write,
.fb_blank = cobalt_lcdfb_blank,
.fb_cursor = cobalt_lcdfb_cursor,
};
static int cobalt_lcdfb_probe(struct platform_device *dev)
{
struct fb_info *info;
struct resource *res;
int retval;
info = framebuffer_alloc(0, &dev->dev);
if (!info)
return -ENOMEM;
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
if (!res) {
framebuffer_release(info);
return -EBUSY;
}
info->screen_size = resource_size(res);
info->screen_base = devm_ioremap(&dev->dev, res->start,
info->screen_size);
if (!info->screen_base) {
framebuffer_release(info);
return -ENOMEM;
}
info->fbops = &cobalt_lcd_fbops;
info->fix = cobalt_lcdfb_fix;
info->fix.smem_start = res->start;
info->fix.smem_len = info->screen_size;
info->pseudo_palette = NULL;
info->par = NULL;
retval = register_framebuffer(info);
if (retval < 0) {
framebuffer_release(info);
return retval;
}
platform_set_drvdata(dev, info);
lcd_clear(info);
fb_info(info, "Cobalt server LCD frame buffer device\n");
return 0;
}
static void cobalt_lcdfb_remove(struct platform_device *dev)
{
struct fb_info *info;
info = platform_get_drvdata(dev);
if (info) {
unregister_framebuffer(info);
framebuffer_release(info);
}
}
static struct platform_driver cobalt_lcdfb_driver = {
.probe = cobalt_lcdfb_probe,
.remove_new = cobalt_lcdfb_remove,
.driver = {
.name = "cobalt-lcd",
},
};
module_platform_driver(cobalt_lcdfb_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Yoichi Yuasa");
MODULE_DESCRIPTION("Cobalt server LCD frame buffer driver");
| linux-master | drivers/video/fbdev/cobalt_lcdfb.c |
/*
* Silicon Motion SM7XX frame buffer device
*
* Copyright (C) 2006 Silicon Motion Technology Corp.
* Authors: Ge Wang, [email protected]
* Boyod [email protected]
*
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin, [email protected]
*
* Copyright (C) 2011 Igalia, S.L.
* Author: Javier M. Mellid <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Framebuffer driver for Silicon Motion SM710, SM712, SM721 and SM722 chips
*/
#include <linux/aperture.h>
#include <linux/io.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/module.h>
#include <linux/console.h>
#include <linux/pm.h>
#include "sm712.h"
struct smtcfb_screen_info {
u16 lfb_width;
u16 lfb_height;
u16 lfb_depth;
};
/*
* Private structure
*/
struct smtcfb_info {
struct pci_dev *pdev;
struct fb_info *fb;
u16 chip_id;
u8 chip_rev_id;
void __iomem *lfb; /* linear frame buffer */
void __iomem *dp_regs; /* drawing processor control regs */
void __iomem *vp_regs; /* video processor control regs */
void __iomem *cp_regs; /* capture processor control regs */
void __iomem *mmio; /* memory map IO port */
u_int width;
u_int height;
u_int hz;
u32 colreg[17];
};
void __iomem *smtc_regbaseaddress; /* Memory Map IO starting address */
static const struct fb_var_screeninfo smtcfb_var = {
.xres = 1024,
.yres = 600,
.xres_virtual = 1024,
.yres_virtual = 600,
.bits_per_pixel = 16,
.red = {16, 8, 0},
.green = {8, 8, 0},
.blue = {0, 8, 0},
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
.nonstd = 0,
.accel_flags = FB_ACCELF_TEXT,
};
static struct fb_fix_screeninfo smtcfb_fix = {
.id = "smXXXfb",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.line_length = 800 * 3,
.accel = FB_ACCEL_SMI_LYNX,
.type_aux = 0,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
};
struct vesa_mode {
char index[6];
u16 lfb_width;
u16 lfb_height;
u16 lfb_depth;
};
static const struct vesa_mode vesa_mode_table[] = {
{"0x301", 640, 480, 8},
{"0x303", 800, 600, 8},
{"0x305", 1024, 768, 8},
{"0x307", 1280, 1024, 8},
{"0x311", 640, 480, 16},
{"0x314", 800, 600, 16},
{"0x317", 1024, 768, 16},
{"0x31A", 1280, 1024, 16},
{"0x312", 640, 480, 24},
{"0x315", 800, 600, 24},
{"0x318", 1024, 768, 24},
{"0x31B", 1280, 1024, 24},
};
/**********************************************************************
SM712 Mode table.
**********************************************************************/
static const struct modeinit vgamode[] = {
{
/* mode#0: 640 x 480 16Bpp 60Hz */
640, 480, 16, 60,
/* Init_MISC */
0xE3,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x00, 0x0E,
},
{ /* Init_SR10_SR24 */
0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
},
{ /* Init_CR90_CRA7 */
0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
},
},
{
/* mode#1: 640 x 480 24Bpp 60Hz */
640, 480, 24, 60,
/* Init_MISC */
0xE3,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x00, 0x0E,
},
{ /* Init_SR10_SR24 */
0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
},
{ /* Init_CR90_CRA7 */
0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
},
},
{
/* mode#0: 640 x 480 32Bpp 60Hz */
640, 480, 32, 60,
/* Init_MISC */
0xE3,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x00, 0x0E,
},
{ /* Init_SR10_SR24 */
0xFF, 0xBE, 0xEF, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x32, 0x03, 0xA0, 0x09, 0xC0, 0x32, 0x32, 0x32,
0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x32, 0x32, 0x32,
0x04, 0x24, 0x63, 0x4F, 0x52, 0x0B, 0xDF, 0xEA,
0x04, 0x50, 0x19, 0x32, 0x32, 0x00, 0x00, 0x32,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x07, 0x82, 0x07, 0x04,
0x00, 0x45, 0x30, 0x30, 0x40, 0x30,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x32,
0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x32, 0x32,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xFF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0x5F, 0x4F, 0x4F, 0x00, 0x53, 0x1F, 0x0B, 0x3E,
0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xEA, 0x0C, 0xDF, 0x50, 0x40, 0xDF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x03, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xFF, 0xFD,
0x5F, 0x4F, 0x00, 0x54, 0x00, 0x0B, 0xDF, 0x00,
0xEA, 0x0C, 0x2E, 0x00, 0x4F, 0xDF,
},
{ /* Init_CR90_CRA7 */
0x56, 0xDD, 0x5E, 0xEA, 0x87, 0x44, 0x8F, 0x55,
0x0A, 0x8F, 0x55, 0x0A, 0x00, 0x00, 0x18, 0x00,
0x11, 0x10, 0x0B, 0x0A, 0x0A, 0x0A, 0x0A, 0x00,
},
},
{ /* mode#2: 800 x 600 16Bpp 60Hz */
800, 600, 16, 60,
/* Init_MISC */
0x2B,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x03, 0x0E,
},
{ /* Init_SR10_SR24 */
0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x34, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24,
0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24,
0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24,
0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
0x02, 0x45, 0x30, 0x35, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
},
{ /* Init_CR90_CRA7 */
0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
},
},
{ /* mode#3: 800 x 600 24Bpp 60Hz */
800, 600, 24, 60,
0x2B,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x03, 0x0E,
},
{ /* Init_SR10_SR24 */
0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x36, 0x03, 0x20, 0x09, 0xC0, 0x36, 0x36, 0x36,
0x36, 0x36, 0x36, 0x36, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x36, 0x36, 0x36,
0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
0x04, 0x55, 0x59, 0x36, 0x36, 0x00, 0x00, 0x36,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
0x02, 0x45, 0x30, 0x30, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x36,
0xF7, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0x36, 0x36,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
},
{ /* Init_CR90_CRA7 */
0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
},
},
{ /* mode#7: 800 x 600 32Bpp 60Hz */
800, 600, 32, 60,
/* Init_MISC */
0x2B,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x03, 0x0E,
},
{ /* Init_SR10_SR24 */
0xFF, 0xBE, 0xEE, 0xFF, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x34, 0x03, 0x20, 0x09, 0xC0, 0x24, 0x24, 0x24,
0x24, 0x24, 0x24, 0x24, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x38, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x24, 0x24, 0x24,
0x04, 0x48, 0x83, 0x63, 0x68, 0x72, 0x57, 0x58,
0x04, 0x55, 0x59, 0x24, 0x24, 0x00, 0x00, 0x24,
0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x1C, 0x85, 0x35, 0x13,
0x02, 0x45, 0x30, 0x35, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0x00, 0x00, 0x00, 0x6F, 0x7F, 0x7F, 0xFF, 0x24,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x24, 0x24,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFF, 0xBF, 0xFF, 0xFF, 0xED, 0xED, 0xED,
0x7B, 0xFF, 0xFF, 0xFF, 0xBF, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0x7F, 0x63, 0x63, 0x00, 0x68, 0x18, 0x72, 0xF0,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x58, 0x0C, 0x57, 0x64, 0x40, 0x57, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x03, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xE7, 0xBF, 0xFD,
0x7F, 0x63, 0x00, 0x69, 0x18, 0x72, 0x57, 0x00,
0x58, 0x0C, 0xE0, 0x20, 0x63, 0x57,
},
{ /* Init_CR90_CRA7 */
0x56, 0x4B, 0x5E, 0x55, 0x86, 0x9D, 0x8E, 0xAA,
0xDB, 0x2A, 0xDF, 0x33, 0x00, 0x00, 0x18, 0x00,
0x20, 0x1F, 0x1A, 0x19, 0x0F, 0x0F, 0x0F, 0x00,
},
},
/* We use 1024x768 table to light 1024x600 panel for lemote */
{ /* mode#4: 1024 x 600 16Bpp 60Hz */
1024, 600, 16, 60,
/* Init_MISC */
0xEB,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x00, 0x0E,
},
{ /* Init_SR10_SR24 */
0xC8, 0x40, 0x14, 0x60, 0x00, 0x0A, 0x17, 0x20,
0x51, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x00, 0x01,
},
{ /* Init_SR30_SR75 */
0x22, 0x03, 0x24, 0x09, 0xC0, 0x22, 0x22, 0x22,
0x22, 0x22, 0x22, 0x22, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x22, 0x22, 0x22,
0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
0x00, 0x60, 0x59, 0x22, 0x22, 0x00, 0x00, 0x22,
0x01, 0x80, 0x7A, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x16, 0x02, 0x0D, 0x82, 0x09, 0x02,
0x04, 0x45, 0x3F, 0x30, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
0xA3, 0x7F, 0x00, 0x82, 0x0b, 0x6f, 0x57, 0x00,
0x5c, 0x0f, 0xE0, 0xe0, 0x7F, 0x57,
},
{ /* Init_CR90_CRA7 */
0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
},
},
{ /* 1024 x 768 16Bpp 60Hz */
1024, 768, 16, 60,
/* Init_MISC */
0xEB,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x03, 0x0E,
},
{ /* Init_SR10_SR24 */
0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
0x0F, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02,
0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00,
0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF,
},
{ /* Init_CR90_CRA7 */
0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
},
},
{ /* mode#5: 1024 x 768 24Bpp 60Hz */
1024, 768, 24, 60,
/* Init_MISC */
0xEB,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x03, 0x0E,
},
{ /* Init_SR10_SR24 */
0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x30, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02,
0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00,
0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF,
},
{ /* Init_CR90_CRA7 */
0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
},
},
{ /* mode#4: 1024 x 768 32Bpp 60Hz */
1024, 768, 32, 60,
/* Init_MISC */
0xEB,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x03, 0x0E,
},
{ /* Init_SR10_SR24 */
0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x32, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x3B, 0x0D, 0x09, 0x02,
0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
0x00, 0x00, 0x00, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
0xA3, 0x7F, 0x00, 0x86, 0x15, 0x24, 0xFF, 0x00,
0x01, 0x07, 0xE5, 0x20, 0x7F, 0xFF,
},
{ /* Init_CR90_CRA7 */
0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
},
},
{ /* mode#6: 320 x 240 16Bpp 60Hz */
320, 240, 16, 60,
/* Init_MISC */
0xEB,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x03, 0x0E,
},
{ /* Init_SR10_SR24 */
0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x32, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x08, 0x43, 0x08, 0x43,
0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
0x00, 0x00, 0x30, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
0x2E, 0x27, 0x00, 0x2b, 0x0c, 0x0F, 0xEF, 0x00,
0xFe, 0x0f, 0x01, 0xC0, 0x27, 0xEF,
},
{ /* Init_CR90_CRA7 */
0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
},
},
{ /* mode#8: 320 x 240 32Bpp 60Hz */
320, 240, 32, 60,
/* Init_MISC */
0xEB,
{ /* Init_SR0_SR4 */
0x03, 0x01, 0x0F, 0x03, 0x0E,
},
{ /* Init_SR10_SR24 */
0xF3, 0xB6, 0xC0, 0xDD, 0x00, 0x0E, 0x17, 0x2C,
0x99, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0xC4, 0x32, 0x02, 0x01, 0x01,
},
{ /* Init_SR30_SR75 */
0x38, 0x03, 0x20, 0x09, 0xC0, 0x3A, 0x3A, 0x3A,
0x3A, 0x3A, 0x3A, 0x3A, 0x00, 0x00, 0x03, 0xFF,
0x00, 0xFC, 0x00, 0x00, 0x20, 0x18, 0x00, 0xFC,
0x20, 0x0C, 0x44, 0x20, 0x00, 0x00, 0x00, 0x3A,
0x06, 0x68, 0xA7, 0x7F, 0x83, 0x24, 0xFF, 0x03,
0x00, 0x60, 0x59, 0x3A, 0x3A, 0x00, 0x00, 0x3A,
0x01, 0x80, 0x7E, 0x1A, 0x1A, 0x00, 0x00, 0x00,
0x50, 0x03, 0x74, 0x14, 0x08, 0x43, 0x08, 0x43,
0x04, 0x45, 0x30, 0x30, 0x40, 0x20,
},
{ /* Init_SR80_SR93 */
0xFF, 0x07, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A,
0xF7, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3A, 0x3A,
0x00, 0x00, 0x00, 0x00,
},
{ /* Init_SRA0_SRAF */
0x00, 0xFB, 0x9F, 0x01, 0x00, 0xED, 0xED, 0xED,
0x7B, 0xFB, 0xFF, 0xFF, 0x97, 0xEF, 0xBF, 0xDF,
},
{ /* Init_GR00_GR08 */
0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
0xFF,
},
{ /* Init_AR00_AR14 */
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x41, 0x00, 0x0F, 0x00, 0x00,
},
{ /* Init_CR00_CR18 */
0xA3, 0x7F, 0x7F, 0x00, 0x85, 0x16, 0x24, 0xF5,
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x03, 0x09, 0xFF, 0x80, 0x40, 0xFF, 0x00, 0xE3,
0xFF,
},
{ /* Init_CR30_CR4D */
0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x20,
0x00, 0x00, 0x30, 0x40, 0x00, 0xFF, 0xBF, 0xFF,
0x2E, 0x27, 0x00, 0x2b, 0x0c, 0x0F, 0xEF, 0x00,
0xFe, 0x0f, 0x01, 0xC0, 0x27, 0xEF,
},
{ /* Init_CR90_CRA7 */
0x55, 0xD9, 0x5D, 0xE1, 0x86, 0x1B, 0x8E, 0x26,
0xDA, 0x8D, 0xDE, 0x94, 0x00, 0x00, 0x18, 0x00,
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x15, 0x03,
},
},
};
static struct smtcfb_screen_info smtc_scr_info;
static char *mode_option;
/* process command line options, get vga parameter */
static void __init sm7xx_vga_setup(char *options)
{
int i;
if (!options || !*options)
return;
smtc_scr_info.lfb_width = 0;
smtc_scr_info.lfb_height = 0;
smtc_scr_info.lfb_depth = 0;
pr_debug("%s = %s\n", __func__, options);
for (i = 0; i < ARRAY_SIZE(vesa_mode_table); i++) {
if (strstr(options, vesa_mode_table[i].index)) {
smtc_scr_info.lfb_width = vesa_mode_table[i].lfb_width;
smtc_scr_info.lfb_height =
vesa_mode_table[i].lfb_height;
smtc_scr_info.lfb_depth = vesa_mode_table[i].lfb_depth;
return;
}
}
}
static void sm712_setpalette(int regno, unsigned int red, unsigned int green,
unsigned int blue, struct fb_info *info)
{
/* set bit 5:4 = 01 (write LCD RAM only) */
smtc_seqw(0x66, (smtc_seqr(0x66) & 0xC3) | 0x10);
smtc_mmiowb(regno, dac_reg);
smtc_mmiowb(red >> 10, dac_val);
smtc_mmiowb(green >> 10, dac_val);
smtc_mmiowb(blue >> 10, dac_val);
}
/* chan_to_field
*
* convert a colour value into a field position
*
* from pxafb.c
*/
static inline unsigned int chan_to_field(unsigned int chan,
struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int smtc_blank(int blank_mode, struct fb_info *info)
{
struct smtcfb_info *sfb = info->par;
/* clear DPMS setting */
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* Screen On: HSync: On, VSync : On */
switch (sfb->chip_id) {
case 0x710:
case 0x712:
smtc_seqw(0x6a, 0x16);
smtc_seqw(0x6b, 0x02);
break;
case 0x720:
smtc_seqw(0x6a, 0x0d);
smtc_seqw(0x6b, 0x02);
break;
}
smtc_seqw(0x23, (smtc_seqr(0x23) & (~0xc0)));
smtc_seqw(0x01, (smtc_seqr(0x01) & (~0x20)));
smtc_seqw(0x21, (smtc_seqr(0x21) & 0x77));
smtc_seqw(0x22, (smtc_seqr(0x22) & (~0x30)));
smtc_seqw(0x31, (smtc_seqr(0x31) | 0x03));
smtc_seqw(0x24, (smtc_seqr(0x24) | 0x01));
break;
case FB_BLANK_NORMAL:
/* Screen Off: HSync: On, VSync : On Soft blank */
smtc_seqw(0x24, (smtc_seqr(0x24) | 0x01));
smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
smtc_seqw(0x23, (smtc_seqr(0x23) & (~0xc0)));
smtc_seqw(0x01, (smtc_seqr(0x01) & (~0x20)));
smtc_seqw(0x22, (smtc_seqr(0x22) & (~0x30)));
smtc_seqw(0x6a, 0x16);
smtc_seqw(0x6b, 0x02);
break;
case FB_BLANK_VSYNC_SUSPEND:
/* Screen On: HSync: On, VSync : Off */
smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0x20));
smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x20));
smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
smtc_seqw(0x6a, 0x0c);
smtc_seqw(0x6b, 0x02);
break;
case FB_BLANK_HSYNC_SUSPEND:
/* Screen On: HSync: Off, VSync : On */
smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0xD8));
smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x10));
smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
smtc_seqw(0x6a, 0x0c);
smtc_seqw(0x6b, 0x02);
break;
case FB_BLANK_POWERDOWN:
/* Screen On: HSync: Off, VSync : Off */
smtc_seqw(0x24, (smtc_seqr(0x24) & (~0x01)));
smtc_seqw(0x31, ((smtc_seqr(0x31) & (~0x07)) | 0x00));
smtc_seqw(0x23, ((smtc_seqr(0x23) & (~0xc0)) | 0xD8));
smtc_seqw(0x01, (smtc_seqr(0x01) | 0x20));
smtc_seqw(0x21, (smtc_seqr(0x21) | 0x88));
smtc_seqw(0x20, (smtc_seqr(0x20) & (~0xB0)));
smtc_seqw(0x22, ((smtc_seqr(0x22) & (~0x30)) | 0x30));
smtc_seqw(0x34, (smtc_seqr(0x34) | 0x80));
smtc_seqw(0x6a, 0x0c);
smtc_seqw(0x6b, 0x02);
break;
default:
return -EINVAL;
}
return 0;
}
static int smtc_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int trans, struct fb_info *info)
{
struct smtcfb_info *sfb;
u32 val;
sfb = info->par;
if (regno > 255)
return 1;
switch (sfb->fb->fix.visual) {
case FB_VISUAL_DIRECTCOLOR:
case FB_VISUAL_TRUECOLOR:
/*
* 16/32 bit true-colour, use pseudo-palette for 16 base color
*/
if (regno >= 16)
break;
if (sfb->fb->var.bits_per_pixel == 16) {
u32 *pal = sfb->fb->pseudo_palette;
val = chan_to_field(red, &sfb->fb->var.red);
val |= chan_to_field(green, &sfb->fb->var.green);
val |= chan_to_field(blue, &sfb->fb->var.blue);
pal[regno] = pal_rgb(red, green, blue, val);
} else {
u32 *pal = sfb->fb->pseudo_palette;
val = chan_to_field(red, &sfb->fb->var.red);
val |= chan_to_field(green, &sfb->fb->var.green);
val |= chan_to_field(blue, &sfb->fb->var.blue);
pal[regno] = big_swap(val);
}
break;
case FB_VISUAL_PSEUDOCOLOR:
/* color depth 8 bit */
sm712_setpalette(regno, red, green, blue, info);
break;
default:
return 1; /* unknown type */
}
return 0;
}
static ssize_t smtcfb_read(struct fb_info *info, char __user *buf,
size_t count, loff_t *ppos)
{
unsigned long p = *ppos;
u32 *buffer, *dst;
u32 __iomem *src;
int c, i, cnt = 0, err = 0;
unsigned long total_size;
if (!info->screen_base)
return -ENODEV;
total_size = info->screen_size;
if (total_size == 0)
total_size = info->fix.smem_len;
if (p >= total_size)
return 0;
if (count >= total_size)
count = total_size;
if (count + p > total_size)
count = total_size - p;
buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
if (!buffer)
return -ENOMEM;
src = (u32 __iomem *)(info->screen_base + p);
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
while (count) {
c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
dst = buffer;
for (i = (c + 3) >> 2; i--;) {
u32 val;
val = fb_readl(src);
*dst = big_swap(val);
src++;
dst++;
}
if (copy_to_user(buf, buffer, c)) {
err = -EFAULT;
break;
}
*ppos += c;
buf += c;
cnt += c;
count -= c;
}
kfree(buffer);
return (err) ? err : cnt;
}
static ssize_t smtcfb_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos)
{
unsigned long p = *ppos;
u32 *buffer, *src;
u32 __iomem *dst;
int c, i, cnt = 0, err = 0;
unsigned long total_size;
if (!info->screen_base)
return -ENODEV;
total_size = info->screen_size;
if (total_size == 0)
total_size = info->fix.smem_len;
if (p > total_size)
return -EFBIG;
if (count > total_size) {
err = -EFBIG;
count = total_size;
}
if (count + p > total_size) {
if (!err)
err = -ENOSPC;
count = total_size - p;
}
buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
if (!buffer)
return -ENOMEM;
dst = (u32 __iomem *)(info->screen_base + p);
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
while (count) {
c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
src = buffer;
if (copy_from_user(src, buf, c)) {
err = -EFAULT;
break;
}
for (i = (c + 3) >> 2; i--;) {
fb_writel(big_swap(*src), dst);
dst++;
src++;
}
*ppos += c;
buf += c;
cnt += c;
count -= c;
}
kfree(buffer);
return (cnt) ? cnt : err;
}
static void sm7xx_set_timing(struct smtcfb_info *sfb)
{
int i = 0, j = 0;
u32 m_nscreenstride;
dev_dbg(&sfb->pdev->dev,
"sfb->width=%d sfb->height=%d sfb->fb->var.bits_per_pixel=%d sfb->hz=%d\n",
sfb->width, sfb->height, sfb->fb->var.bits_per_pixel, sfb->hz);
for (j = 0; j < ARRAY_SIZE(vgamode); j++) {
if (vgamode[j].mmsizex != sfb->width ||
vgamode[j].mmsizey != sfb->height ||
vgamode[j].bpp != sfb->fb->var.bits_per_pixel ||
vgamode[j].hz != sfb->hz)
continue;
dev_dbg(&sfb->pdev->dev,
"vgamode[j].mmsizex=%d vgamode[j].mmSizeY=%d vgamode[j].bpp=%d vgamode[j].hz=%d\n",
vgamode[j].mmsizex, vgamode[j].mmsizey,
vgamode[j].bpp, vgamode[j].hz);
dev_dbg(&sfb->pdev->dev, "vgamode index=%d\n", j);
smtc_mmiowb(0x0, 0x3c6);
smtc_seqw(0, 0x1);
smtc_mmiowb(vgamode[j].init_misc, 0x3c2);
/* init SEQ register SR00 - SR04 */
for (i = 0; i < SIZE_SR00_SR04; i++)
smtc_seqw(i, vgamode[j].init_sr00_sr04[i]);
/* init SEQ register SR10 - SR24 */
for (i = 0; i < SIZE_SR10_SR24; i++)
smtc_seqw(i + 0x10, vgamode[j].init_sr10_sr24[i]);
/* init SEQ register SR30 - SR75 */
for (i = 0; i < SIZE_SR30_SR75; i++)
if ((i + 0x30) != 0x30 && (i + 0x30) != 0x62 &&
(i + 0x30) != 0x6a && (i + 0x30) != 0x6b &&
(i + 0x30) != 0x70 && (i + 0x30) != 0x71 &&
(i + 0x30) != 0x74 && (i + 0x30) != 0x75)
smtc_seqw(i + 0x30,
vgamode[j].init_sr30_sr75[i]);
/* init SEQ register SR80 - SR93 */
for (i = 0; i < SIZE_SR80_SR93; i++)
smtc_seqw(i + 0x80, vgamode[j].init_sr80_sr93[i]);
/* init SEQ register SRA0 - SRAF */
for (i = 0; i < SIZE_SRA0_SRAF; i++)
smtc_seqw(i + 0xa0, vgamode[j].init_sra0_sraf[i]);
/* init Graphic register GR00 - GR08 */
for (i = 0; i < SIZE_GR00_GR08; i++)
smtc_grphw(i, vgamode[j].init_gr00_gr08[i]);
/* init Attribute register AR00 - AR14 */
for (i = 0; i < SIZE_AR00_AR14; i++)
smtc_attrw(i, vgamode[j].init_ar00_ar14[i]);
/* init CRTC register CR00 - CR18 */
for (i = 0; i < SIZE_CR00_CR18; i++)
smtc_crtcw(i, vgamode[j].init_cr00_cr18[i]);
/* init CRTC register CR30 - CR4D */
for (i = 0; i < SIZE_CR30_CR4D; i++) {
if ((i + 0x30) >= 0x3B && (i + 0x30) <= 0x3F)
/* side-effect, don't write to CR3B-CR3F */
continue;
smtc_crtcw(i + 0x30, vgamode[j].init_cr30_cr4d[i]);
}
/* init CRTC register CR90 - CRA7 */
for (i = 0; i < SIZE_CR90_CRA7; i++)
smtc_crtcw(i + 0x90, vgamode[j].init_cr90_cra7[i]);
}
smtc_mmiowb(0x67, 0x3c2);
/* set VPR registers */
writel(0x0, sfb->vp_regs + 0x0C);
writel(0x0, sfb->vp_regs + 0x40);
/* set data width */
m_nscreenstride = (sfb->width * sfb->fb->var.bits_per_pixel) / 64;
switch (sfb->fb->var.bits_per_pixel) {
case 8:
writel(0x0, sfb->vp_regs + 0x0);
break;
case 16:
writel(0x00020000, sfb->vp_regs + 0x0);
break;
case 24:
writel(0x00040000, sfb->vp_regs + 0x0);
break;
case 32:
writel(0x00030000, sfb->vp_regs + 0x0);
break;
}
writel((u32)(((m_nscreenstride + 2) << 16) | m_nscreenstride),
sfb->vp_regs + 0x10);
}
static void smtc_set_timing(struct smtcfb_info *sfb)
{
switch (sfb->chip_id) {
case 0x710:
case 0x712:
case 0x720:
sm7xx_set_timing(sfb);
break;
}
}
static void smtcfb_setmode(struct smtcfb_info *sfb)
{
switch (sfb->fb->var.bits_per_pixel) {
case 32:
sfb->fb->fix.visual = FB_VISUAL_TRUECOLOR;
sfb->fb->fix.line_length = sfb->fb->var.xres * 4;
sfb->fb->var.red.length = 8;
sfb->fb->var.green.length = 8;
sfb->fb->var.blue.length = 8;
sfb->fb->var.red.offset = 16;
sfb->fb->var.green.offset = 8;
sfb->fb->var.blue.offset = 0;
break;
case 24:
sfb->fb->fix.visual = FB_VISUAL_TRUECOLOR;
sfb->fb->fix.line_length = sfb->fb->var.xres * 3;
sfb->fb->var.red.length = 8;
sfb->fb->var.green.length = 8;
sfb->fb->var.blue.length = 8;
sfb->fb->var.red.offset = 16;
sfb->fb->var.green.offset = 8;
sfb->fb->var.blue.offset = 0;
break;
case 8:
sfb->fb->fix.visual = FB_VISUAL_PSEUDOCOLOR;
sfb->fb->fix.line_length = sfb->fb->var.xres;
sfb->fb->var.red.length = 3;
sfb->fb->var.green.length = 3;
sfb->fb->var.blue.length = 2;
sfb->fb->var.red.offset = 5;
sfb->fb->var.green.offset = 2;
sfb->fb->var.blue.offset = 0;
break;
case 16:
default:
sfb->fb->fix.visual = FB_VISUAL_TRUECOLOR;
sfb->fb->fix.line_length = sfb->fb->var.xres * 2;
sfb->fb->var.red.length = 5;
sfb->fb->var.green.length = 6;
sfb->fb->var.blue.length = 5;
sfb->fb->var.red.offset = 11;
sfb->fb->var.green.offset = 5;
sfb->fb->var.blue.offset = 0;
break;
}
sfb->width = sfb->fb->var.xres;
sfb->height = sfb->fb->var.yres;
sfb->hz = 60;
smtc_set_timing(sfb);
}
static int smtc_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
/* sanity checks */
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
/* set valid default bpp */
if ((var->bits_per_pixel != 8) && (var->bits_per_pixel != 16) &&
(var->bits_per_pixel != 24) && (var->bits_per_pixel != 32))
var->bits_per_pixel = 16;
return 0;
}
static int smtc_set_par(struct fb_info *info)
{
smtcfb_setmode(info->par);
return 0;
}
static const struct fb_ops smtcfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = smtc_check_var,
.fb_set_par = smtc_set_par,
.fb_setcolreg = smtc_setcolreg,
.fb_blank = smtc_blank,
.fb_fillrect = cfb_fillrect,
.fb_imageblit = cfb_imageblit,
.fb_copyarea = cfb_copyarea,
.fb_read = smtcfb_read,
.fb_write = smtcfb_write,
};
/*
* Unmap in the memory mapped IO registers
*/
static void smtc_unmap_mmio(struct smtcfb_info *sfb)
{
if (sfb && smtc_regbaseaddress)
smtc_regbaseaddress = NULL;
}
/*
* Map in the screen memory
*/
static int smtc_map_smem(struct smtcfb_info *sfb,
struct pci_dev *pdev, u_long smem_len)
{
sfb->fb->fix.smem_start = pci_resource_start(pdev, 0);
if (sfb->chip_id == 0x720)
/* on SM720, the framebuffer starts at the 1 MB offset */
sfb->fb->fix.smem_start += 0x00200000;
/* XXX: is it safe for SM720 on Big-Endian? */
if (sfb->fb->var.bits_per_pixel == 32)
sfb->fb->fix.smem_start += big_addr;
sfb->fb->fix.smem_len = smem_len;
sfb->fb->screen_base = sfb->lfb;
if (!sfb->fb->screen_base) {
dev_err(&pdev->dev,
"%s: unable to map screen memory\n", sfb->fb->fix.id);
return -ENOMEM;
}
return 0;
}
/*
* Unmap in the screen memory
*
*/
static void smtc_unmap_smem(struct smtcfb_info *sfb)
{
if (sfb && sfb->fb->screen_base) {
if (sfb->chip_id == 0x720)
sfb->fb->screen_base -= 0x00200000;
iounmap(sfb->fb->screen_base);
sfb->fb->screen_base = NULL;
}
}
/*
* We need to wake up the device and make sure its in linear memory mode.
*/
static inline void sm7xx_init_hw(void)
{
outb_p(0x18, 0x3c4);
outb_p(0x11, 0x3c5);
}
static u_long sm7xx_vram_probe(struct smtcfb_info *sfb)
{
u8 vram;
switch (sfb->chip_id) {
case 0x710:
case 0x712:
/*
* Assume SM712 graphics chip has 4MB VRAM.
*
* FIXME: SM712 can have 2MB VRAM, which is used on earlier
* laptops, such as IBM Thinkpad 240X. This driver would
* probably crash on those machines. If anyone gets one of
* those and is willing to help, run "git blame" and send me
* an E-mail.
*/
return 0x00400000;
case 0x720:
outb_p(0x76, 0x3c4);
vram = inb_p(0x3c5) >> 6;
if (vram == 0x00)
return 0x00800000; /* 8 MB */
else if (vram == 0x01)
return 0x01000000; /* 16 MB */
else if (vram == 0x02)
return 0x00400000; /* illegal, fallback to 4 MB */
else if (vram == 0x03)
return 0x00400000; /* 4 MB */
}
return 0; /* unknown hardware */
}
static void sm7xx_resolution_probe(struct smtcfb_info *sfb)
{
/* get mode parameter from smtc_scr_info */
if (smtc_scr_info.lfb_width != 0) {
sfb->fb->var.xres = smtc_scr_info.lfb_width;
sfb->fb->var.yres = smtc_scr_info.lfb_height;
sfb->fb->var.bits_per_pixel = smtc_scr_info.lfb_depth;
goto final;
}
/*
* No parameter, default resolution is 1024x768-16.
*
* FIXME: earlier laptops, such as IBM Thinkpad 240X, has a 800x600
* panel, also see the comments about Thinkpad 240X above.
*/
sfb->fb->var.xres = SCREEN_X_RES;
sfb->fb->var.yres = SCREEN_Y_RES_PC;
sfb->fb->var.bits_per_pixel = SCREEN_BPP;
#ifdef CONFIG_MIPS
/*
* Loongson MIPS netbooks use 1024x600 LCD panels, which is the original
* target platform of this driver, but nearly all old x86 laptops have
* 1024x768. Lighting 768 panels using 600's timings would partially
* garble the display, so we don't want that. But it's not possible to
* distinguish them reliably.
*
* So we change the default to 768, but keep 600 as-is on MIPS.
*/
sfb->fb->var.yres = SCREEN_Y_RES_NETBOOK;
#endif
final:
big_pixel_depth(sfb->fb->var.bits_per_pixel, smtc_scr_info.lfb_depth);
}
static int smtcfb_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct smtcfb_info *sfb;
struct fb_info *info;
u_long smem_size;
int err;
unsigned long mmio_base;
dev_info(&pdev->dev, "Silicon Motion display driver.\n");
err = aperture_remove_conflicting_pci_devices(pdev, "smtcfb");
if (err)
return err;
err = pci_enable_device(pdev); /* enable SMTC chip */
if (err)
return err;
err = pci_request_region(pdev, 0, "sm7xxfb");
if (err < 0) {
dev_err(&pdev->dev, "cannot reserve framebuffer region\n");
goto failed_regions;
}
sprintf(smtcfb_fix.id, "sm%Xfb", ent->device);
info = framebuffer_alloc(sizeof(*sfb), &pdev->dev);
if (!info) {
err = -ENOMEM;
goto failed_free;
}
sfb = info->par;
sfb->fb = info;
sfb->chip_id = ent->device;
sfb->pdev = pdev;
info->fbops = &smtcfb_ops;
info->fix = smtcfb_fix;
info->var = smtcfb_var;
info->pseudo_palette = sfb->colreg;
info->par = sfb;
pci_set_drvdata(pdev, sfb);
sm7xx_init_hw();
/* Map address and memory detection */
mmio_base = pci_resource_start(pdev, 0);
pci_read_config_byte(pdev, PCI_REVISION_ID, &sfb->chip_rev_id);
smem_size = sm7xx_vram_probe(sfb);
dev_info(&pdev->dev, "%lu MiB of VRAM detected.\n",
smem_size / 1048576);
switch (sfb->chip_id) {
case 0x710:
case 0x712:
sfb->fb->fix.mmio_start = mmio_base + 0x00400000;
sfb->fb->fix.mmio_len = 0x00400000;
sfb->lfb = ioremap(mmio_base, mmio_addr);
if (!sfb->lfb) {
dev_err(&pdev->dev,
"%s: unable to map memory mapped IO!\n",
sfb->fb->fix.id);
err = -ENOMEM;
goto failed_fb;
}
sfb->mmio = (smtc_regbaseaddress =
sfb->lfb + 0x00700000);
sfb->dp_regs = sfb->lfb + 0x00408000;
sfb->vp_regs = sfb->lfb + 0x0040c000;
if (sfb->fb->var.bits_per_pixel == 32) {
sfb->lfb += big_addr;
dev_info(&pdev->dev, "sfb->lfb=%p\n", sfb->lfb);
}
/* set MCLK = 14.31818 * (0x16 / 0x2) */
smtc_seqw(0x6a, 0x16);
smtc_seqw(0x6b, 0x02);
smtc_seqw(0x62, 0x3e);
/* enable PCI burst */
smtc_seqw(0x17, 0x20);
/* enable word swap */
if (sfb->fb->var.bits_per_pixel == 32)
seqw17();
break;
case 0x720:
sfb->fb->fix.mmio_start = mmio_base;
sfb->fb->fix.mmio_len = 0x00200000;
sfb->dp_regs = ioremap(mmio_base, 0x00200000 + smem_size);
if (!sfb->dp_regs) {
dev_err(&pdev->dev,
"%s: unable to map memory mapped IO!\n",
sfb->fb->fix.id);
err = -ENOMEM;
goto failed_fb;
}
sfb->lfb = sfb->dp_regs + 0x00200000;
sfb->mmio = (smtc_regbaseaddress =
sfb->dp_regs + 0x000c0000);
sfb->vp_regs = sfb->dp_regs + 0x800;
smtc_seqw(0x62, 0xff);
smtc_seqw(0x6a, 0x0d);
smtc_seqw(0x6b, 0x02);
break;
default:
dev_err(&pdev->dev,
"No valid Silicon Motion display chip was detected!\n");
err = -ENODEV;
goto failed_fb;
}
/* probe and decide resolution */
sm7xx_resolution_probe(sfb);
/* can support 32 bpp */
if (sfb->fb->var.bits_per_pixel == 15)
sfb->fb->var.bits_per_pixel = 16;
sfb->fb->var.xres_virtual = sfb->fb->var.xres;
sfb->fb->var.yres_virtual = sfb->fb->var.yres;
err = smtc_map_smem(sfb, pdev, smem_size);
if (err)
goto failed;
/*
* The screen would be temporarily garbled when sm712fb takes over
* vesafb or VGA text mode. Zero the framebuffer.
*/
memset_io(sfb->lfb, 0, sfb->fb->fix.smem_len);
err = register_framebuffer(info);
if (err < 0)
goto failed;
dev_info(&pdev->dev,
"Silicon Motion SM%X Rev%X primary display mode %dx%d-%d Init Complete.\n",
sfb->chip_id, sfb->chip_rev_id, sfb->fb->var.xres,
sfb->fb->var.yres, sfb->fb->var.bits_per_pixel);
return 0;
failed:
dev_err(&pdev->dev, "Silicon Motion, Inc. primary display init fail.\n");
smtc_unmap_smem(sfb);
smtc_unmap_mmio(sfb);
failed_fb:
framebuffer_release(info);
failed_free:
pci_release_region(pdev, 0);
failed_regions:
pci_disable_device(pdev);
return err;
}
/*
* 0x710 (LynxEM)
* 0x712 (LynxEM+)
* 0x720 (Lynx3DM, Lynx3DM+)
*/
static const struct pci_device_id smtcfb_pci_table[] = {
{ PCI_DEVICE(0x126f, 0x710), },
{ PCI_DEVICE(0x126f, 0x712), },
{ PCI_DEVICE(0x126f, 0x720), },
{0,}
};
MODULE_DEVICE_TABLE(pci, smtcfb_pci_table);
static void smtcfb_pci_remove(struct pci_dev *pdev)
{
struct smtcfb_info *sfb;
sfb = pci_get_drvdata(pdev);
smtc_unmap_smem(sfb);
smtc_unmap_mmio(sfb);
unregister_framebuffer(sfb->fb);
framebuffer_release(sfb->fb);
pci_release_region(pdev, 0);
pci_disable_device(pdev);
}
static int __maybe_unused smtcfb_pci_suspend(struct device *device)
{
struct smtcfb_info *sfb = dev_get_drvdata(device);
/* set the hw in sleep mode use external clock and self memory refresh
* so that we can turn off internal PLLs later on
*/
smtc_seqw(0x20, (smtc_seqr(0x20) | 0xc0));
smtc_seqw(0x69, (smtc_seqr(0x69) & 0xf7));
console_lock();
fb_set_suspend(sfb->fb, 1);
console_unlock();
/* additionally turn off all function blocks including internal PLLs */
smtc_seqw(0x21, 0xff);
return 0;
}
static int __maybe_unused smtcfb_pci_resume(struct device *device)
{
struct smtcfb_info *sfb = dev_get_drvdata(device);
/* reinit hardware */
sm7xx_init_hw();
switch (sfb->chip_id) {
case 0x710:
case 0x712:
/* set MCLK = 14.31818 * (0x16 / 0x2) */
smtc_seqw(0x6a, 0x16);
smtc_seqw(0x6b, 0x02);
smtc_seqw(0x62, 0x3e);
/* enable PCI burst */
smtc_seqw(0x17, 0x20);
if (sfb->fb->var.bits_per_pixel == 32)
seqw17();
break;
case 0x720:
smtc_seqw(0x62, 0xff);
smtc_seqw(0x6a, 0x0d);
smtc_seqw(0x6b, 0x02);
break;
}
smtc_seqw(0x34, (smtc_seqr(0x34) | 0xc0));
smtc_seqw(0x33, ((smtc_seqr(0x33) | 0x08) & 0xfb));
smtcfb_setmode(sfb);
console_lock();
fb_set_suspend(sfb->fb, 0);
console_unlock();
return 0;
}
static SIMPLE_DEV_PM_OPS(sm7xx_pm_ops, smtcfb_pci_suspend, smtcfb_pci_resume);
static struct pci_driver smtcfb_driver = {
.name = "smtcfb",
.id_table = smtcfb_pci_table,
.probe = smtcfb_pci_probe,
.remove = smtcfb_pci_remove,
.driver.pm = &sm7xx_pm_ops,
};
static int __init sm712fb_init(void)
{
char *option = NULL;
if (fb_modesetting_disabled("sm712fb"))
return -ENODEV;
if (fb_get_options("sm712fb", &option))
return -ENODEV;
if (option && *option)
mode_option = option;
sm7xx_vga_setup(mode_option);
return pci_register_driver(&smtcfb_driver);
}
module_init(sm712fb_init);
static void __exit sm712fb_exit(void)
{
pci_unregister_driver(&smtcfb_driver);
}
module_exit(sm712fb_exit);
MODULE_AUTHOR("Siliconmotion ");
MODULE_DESCRIPTION("Framebuffer driver for SMI Graphic Cards");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/sm712fb.c |
/*
* linux/drivers/video/metronomefb.c -- FB driver for Metronome controller
*
* Copyright (C) 2008, Jaya Kumar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
*
* This work was made possible by help and equipment support from E-Ink
* Corporation. https://www.eink.com/
*
* This driver is written to be used with the Metronome display controller.
* It is intended to be architecture independent. A board specific driver
* must be used to perform all the physical IO interactions. An example
* is provided as am200epd.c
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/firmware.h>
#include <linux/dma-mapping.h>
#include <linux/uaccess.h>
#include <linux/irq.h>
#include <video/metronomefb.h>
#include <asm/unaligned.h>
/* Display specific information */
#define DPY_W 832
#define DPY_H 622
static int user_wfm_size;
/* frame differs from image. frame includes non-visible pixels */
struct epd_frame {
int fw; /* frame width */
int fh; /* frame height */
u16 config[4];
int wfm_size;
};
static struct epd_frame epd_frame_table[] = {
{
.fw = 832,
.fh = 622,
.config = {
15 /* sdlew */
| 2 << 8 /* sdosz */
| 0 << 11 /* sdor */
| 0 << 12 /* sdces */
| 0 << 15, /* sdcer */
42 /* gdspl */
| 1 << 8 /* gdr1 */
| 1 << 9 /* sdshr */
| 0 << 15, /* gdspp */
18 /* gdspw */
| 0 << 15, /* dispc */
599 /* vdlc */
| 0 << 11 /* dsi */
| 0 << 12, /* dsic */
},
.wfm_size = 47001,
},
{
.fw = 1088,
.fh = 791,
.config = {
0x0104,
0x031f,
0x0088,
0x02ff,
},
.wfm_size = 46770,
},
{
.fw = 1200,
.fh = 842,
.config = {
0x0101,
0x030e,
0x0012,
0x0280,
},
.wfm_size = 46770,
},
};
static struct fb_fix_screeninfo metronomefb_fix = {
.id = "metronomefb",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_STATIC_PSEUDOCOLOR,
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
.line_length = DPY_W,
.accel = FB_ACCEL_NONE,
};
static struct fb_var_screeninfo metronomefb_var = {
.xres = DPY_W,
.yres = DPY_H,
.xres_virtual = DPY_W,
.yres_virtual = DPY_H,
.bits_per_pixel = 8,
.grayscale = 1,
.nonstd = 1,
.red = { 4, 3, 0 },
.green = { 0, 0, 0 },
.blue = { 0, 0, 0 },
.transp = { 0, 0, 0 },
};
/* the waveform structure that is coming from userspace firmware */
struct waveform_hdr {
u8 stuff[32];
u8 wmta[3];
u8 fvsn;
u8 luts;
u8 mc;
u8 trc;
u8 stuff3;
u8 endb;
u8 swtb;
u8 stuff2a[2];
u8 stuff2b[3];
u8 wfm_cs;
} __attribute__ ((packed));
/* main metronomefb functions */
static u8 calc_cksum(int start, int end, u8 *mem)
{
u8 tmp = 0;
int i;
for (i = start; i < end; i++)
tmp += mem[i];
return tmp;
}
static u16 calc_img_cksum(u16 *start, int length)
{
u16 tmp = 0;
while (length--)
tmp += *start++;
return tmp;
}
/* here we decode the incoming waveform file and populate metromem */
static int load_waveform(u8 *mem, size_t size, int m, int t,
struct metronomefb_par *par)
{
int tta;
int wmta;
int trn = 0;
int i;
unsigned char v;
u8 cksum;
int cksum_idx;
int wfm_idx, owfm_idx;
int mem_idx = 0;
struct waveform_hdr *wfm_hdr;
u8 *metromem = par->metromem_wfm;
struct device *dev = par->info->device;
if (user_wfm_size)
epd_frame_table[par->dt].wfm_size = user_wfm_size;
if (size != epd_frame_table[par->dt].wfm_size) {
dev_err(dev, "Error: unexpected size %zd != %d\n", size,
epd_frame_table[par->dt].wfm_size);
return -EINVAL;
}
wfm_hdr = (struct waveform_hdr *) mem;
if (wfm_hdr->fvsn != 1) {
dev_err(dev, "Error: bad fvsn %x\n", wfm_hdr->fvsn);
return -EINVAL;
}
if (wfm_hdr->luts != 0) {
dev_err(dev, "Error: bad luts %x\n", wfm_hdr->luts);
return -EINVAL;
}
cksum = calc_cksum(32, 47, mem);
if (cksum != wfm_hdr->wfm_cs) {
dev_err(dev, "Error: bad cksum %x != %x\n", cksum,
wfm_hdr->wfm_cs);
return -EINVAL;
}
wfm_hdr->mc += 1;
wfm_hdr->trc += 1;
for (i = 0; i < 5; i++) {
if (*(wfm_hdr->stuff2a + i) != 0) {
dev_err(dev, "Error: unexpected value in padding\n");
return -EINVAL;
}
}
/* calculating trn. trn is something used to index into
the waveform. presumably selecting the right one for the
desired temperature. it works out the offset of the first
v that exceeds the specified temperature */
if ((sizeof(*wfm_hdr) + wfm_hdr->trc) > size)
return -EINVAL;
for (i = sizeof(*wfm_hdr); i <= sizeof(*wfm_hdr) + wfm_hdr->trc; i++) {
if (mem[i] > t) {
trn = i - sizeof(*wfm_hdr) - 1;
break;
}
}
/* check temperature range table checksum */
cksum_idx = sizeof(*wfm_hdr) + wfm_hdr->trc + 1;
if (cksum_idx >= size)
return -EINVAL;
cksum = calc_cksum(sizeof(*wfm_hdr), cksum_idx, mem);
if (cksum != mem[cksum_idx]) {
dev_err(dev, "Error: bad temperature range table cksum"
" %x != %x\n", cksum, mem[cksum_idx]);
return -EINVAL;
}
/* check waveform mode table address checksum */
wmta = get_unaligned_le32(wfm_hdr->wmta) & 0x00FFFFFF;
cksum_idx = wmta + m*4 + 3;
if (cksum_idx >= size)
return -EINVAL;
cksum = calc_cksum(cksum_idx - 3, cksum_idx, mem);
if (cksum != mem[cksum_idx]) {
dev_err(dev, "Error: bad mode table address cksum"
" %x != %x\n", cksum, mem[cksum_idx]);
return -EINVAL;
}
/* check waveform temperature table address checksum */
tta = get_unaligned_le32(mem + wmta + m * 4) & 0x00FFFFFF;
cksum_idx = tta + trn*4 + 3;
if (cksum_idx >= size)
return -EINVAL;
cksum = calc_cksum(cksum_idx - 3, cksum_idx, mem);
if (cksum != mem[cksum_idx]) {
dev_err(dev, "Error: bad temperature table address cksum"
" %x != %x\n", cksum, mem[cksum_idx]);
return -EINVAL;
}
/* here we do the real work of putting the waveform into the
metromem buffer. this does runlength decoding of the waveform */
wfm_idx = get_unaligned_le32(mem + tta + trn * 4) & 0x00FFFFFF;
owfm_idx = wfm_idx;
if (wfm_idx >= size)
return -EINVAL;
while (wfm_idx < size) {
unsigned char rl;
v = mem[wfm_idx++];
if (v == wfm_hdr->swtb) {
while (((v = mem[wfm_idx++]) != wfm_hdr->swtb) &&
wfm_idx < size)
metromem[mem_idx++] = v;
continue;
}
if (v == wfm_hdr->endb)
break;
rl = mem[wfm_idx++];
for (i = 0; i <= rl; i++)
metromem[mem_idx++] = v;
}
cksum_idx = wfm_idx;
if (cksum_idx >= size)
return -EINVAL;
cksum = calc_cksum(owfm_idx, cksum_idx, mem);
if (cksum != mem[cksum_idx]) {
dev_err(dev, "Error: bad waveform data cksum"
" %x != %x\n", cksum, mem[cksum_idx]);
return -EINVAL;
}
par->frame_count = (mem_idx/64);
return 0;
}
static int metronome_display_cmd(struct metronomefb_par *par)
{
int i;
u16 cs;
u16 opcode;
static u8 borderval;
/* setup display command
we can't immediately set the opcode since the controller
will try parse the command before we've set it all up
so we just set cs here and set the opcode at the end */
if (par->metromem_cmd->opcode == 0xCC40)
opcode = cs = 0xCC41;
else
opcode = cs = 0xCC40;
/* set the args ( 2 bytes ) for display */
i = 0;
par->metromem_cmd->args[i] = 1 << 3 /* border update */
| ((borderval++ % 4) & 0x0F) << 4
| (par->frame_count - 1) << 8;
cs += par->metromem_cmd->args[i++];
/* the rest are 0 */
memset((u8 *) (par->metromem_cmd->args + i), 0, (32-i)*2);
par->metromem_cmd->csum = cs;
par->metromem_cmd->opcode = opcode; /* display cmd */
return par->board->met_wait_event_intr(par);
}
static int metronome_powerup_cmd(struct metronomefb_par *par)
{
int i;
u16 cs;
/* setup power up command */
par->metromem_cmd->opcode = 0x1234; /* pwr up pseudo cmd */
cs = par->metromem_cmd->opcode;
/* set pwr1,2,3 to 1024 */
for (i = 0; i < 3; i++) {
par->metromem_cmd->args[i] = 1024;
cs += par->metromem_cmd->args[i];
}
/* the rest are 0 */
memset(&par->metromem_cmd->args[i], 0,
(ARRAY_SIZE(par->metromem_cmd->args) - i) * 2);
par->metromem_cmd->csum = cs;
msleep(1);
par->board->set_rst(par, 1);
msleep(1);
par->board->set_stdby(par, 1);
return par->board->met_wait_event(par);
}
static int metronome_config_cmd(struct metronomefb_par *par)
{
/* setup config command
we can't immediately set the opcode since the controller
will try parse the command before we've set it all up */
memcpy(par->metromem_cmd->args, epd_frame_table[par->dt].config,
sizeof(epd_frame_table[par->dt].config));
/* the rest are 0 */
memset(&par->metromem_cmd->args[4], 0,
(ARRAY_SIZE(par->metromem_cmd->args) - 4) * 2);
par->metromem_cmd->csum = 0xCC10;
par->metromem_cmd->csum += calc_img_cksum(par->metromem_cmd->args, 4);
par->metromem_cmd->opcode = 0xCC10; /* config cmd */
return par->board->met_wait_event(par);
}
static int metronome_init_cmd(struct metronomefb_par *par)
{
int i;
u16 cs;
/* setup init command
we can't immediately set the opcode since the controller
will try parse the command before we've set it all up
so we just set cs here and set the opcode at the end */
cs = 0xCC20;
/* set the args ( 2 bytes ) for init */
i = 0;
par->metromem_cmd->args[i] = 0;
cs += par->metromem_cmd->args[i++];
/* the rest are 0 */
memset((u8 *) (par->metromem_cmd->args + i), 0, (32-i)*2);
par->metromem_cmd->csum = cs;
par->metromem_cmd->opcode = 0xCC20; /* init cmd */
return par->board->met_wait_event(par);
}
static int metronome_init_regs(struct metronomefb_par *par)
{
int res;
res = par->board->setup_io(par);
if (res)
return res;
res = metronome_powerup_cmd(par);
if (res)
return res;
res = metronome_config_cmd(par);
if (res)
return res;
res = metronome_init_cmd(par);
return res;
}
static void metronomefb_dpy_update(struct metronomefb_par *par)
{
int fbsize;
u16 cksum;
unsigned char *buf = par->info->screen_buffer;
fbsize = par->info->fix.smem_len;
/* copy from vm to metromem */
memcpy(par->metromem_img, buf, fbsize);
cksum = calc_img_cksum((u16 *) par->metromem_img, fbsize/2);
*((u16 *)(par->metromem_img) + fbsize/2) = cksum;
metronome_display_cmd(par);
}
static u16 metronomefb_dpy_update_page(struct metronomefb_par *par, int index)
{
int i;
u16 csum = 0;
u16 *buf = (u16 *)(par->info->screen_buffer + index);
u16 *img = (u16 *)(par->metromem_img + index);
/* swizzle from vm to metromem and recalc cksum at the same time*/
for (i = 0; i < PAGE_SIZE/2; i++) {
*(img + i) = (buf[i] << 5) & 0xE0E0;
csum += *(img + i);
}
return csum;
}
/* this is called back from the deferred io workqueue */
static void metronomefb_dpy_deferred_io(struct fb_info *info, struct list_head *pagereflist)
{
u16 cksum;
struct fb_deferred_io_pageref *pageref;
struct metronomefb_par *par = info->par;
/* walk the written page list and swizzle the data */
list_for_each_entry(pageref, pagereflist, list) {
unsigned long pgoffset = pageref->offset >> PAGE_SHIFT;
cksum = metronomefb_dpy_update_page(par, pageref->offset);
par->metromem_img_csum -= par->csum_table[pgoffset];
par->csum_table[pgoffset] = cksum;
par->metromem_img_csum += cksum;
}
metronome_display_cmd(par);
}
static void metronomefb_defio_damage_range(struct fb_info *info, off_t off, size_t len)
{
struct metronomefb_par *par = info->par;
metronomefb_dpy_update(par);
}
static void metronomefb_defio_damage_area(struct fb_info *info, u32 x, u32 y,
u32 width, u32 height)
{
struct metronomefb_par *par = info->par;
metronomefb_dpy_update(par);
}
FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(metronomefb,
metronomefb_defio_damage_range,
metronomefb_defio_damage_area)
static const struct fb_ops metronomefb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_DEFERRED_OPS(metronomefb),
};
static struct fb_deferred_io metronomefb_defio = {
.delay = HZ,
.sort_pagereflist = true,
.deferred_io = metronomefb_dpy_deferred_io,
};
static int metronomefb_probe(struct platform_device *dev)
{
struct fb_info *info;
struct metronome_board *board;
int retval = -ENOMEM;
int videomemorysize;
unsigned char *videomemory;
struct metronomefb_par *par;
const struct firmware *fw_entry;
int i;
int panel_type;
int fw, fh;
int epd_dt_index;
/* pick up board specific routines */
board = dev->dev.platform_data;
if (!board)
return -EINVAL;
/* try to count device specific driver, if can't, platform recalls */
if (!try_module_get(board->owner))
return -ENODEV;
info = framebuffer_alloc(sizeof(struct metronomefb_par), &dev->dev);
if (!info)
goto err;
/* we have two blocks of memory.
info->screen_buffer which is vm, and is the fb used by apps.
par->metromem which is physically contiguous memory and
contains the display controller commands, waveform,
processed image data and padding. this is the data pulled
by the device's LCD controller and pushed to Metronome.
the metromem memory is allocated by the board driver and
is provided to us */
panel_type = board->get_panel_type();
switch (panel_type) {
case 6:
epd_dt_index = 0;
break;
case 8:
epd_dt_index = 1;
break;
case 97:
epd_dt_index = 2;
break;
default:
dev_err(&dev->dev, "Unexpected panel type. Defaulting to 6\n");
epd_dt_index = 0;
break;
}
fw = epd_frame_table[epd_dt_index].fw;
fh = epd_frame_table[epd_dt_index].fh;
/* we need to add a spare page because our csum caching scheme walks
* to the end of the page */
videomemorysize = PAGE_SIZE + (fw * fh);
videomemory = vzalloc(videomemorysize);
if (!videomemory)
goto err_fb_rel;
info->screen_buffer = videomemory;
info->fbops = &metronomefb_ops;
metronomefb_fix.line_length = fw;
metronomefb_var.xres = fw;
metronomefb_var.yres = fh;
metronomefb_var.xres_virtual = fw;
metronomefb_var.yres_virtual = fh;
info->var = metronomefb_var;
info->fix = metronomefb_fix;
info->fix.smem_len = videomemorysize;
par = info->par;
par->info = info;
par->board = board;
par->dt = epd_dt_index;
init_waitqueue_head(&par->waitq);
/* this table caches per page csum values. */
par->csum_table = vmalloc(videomemorysize/PAGE_SIZE);
if (!par->csum_table)
goto err_vfree;
/* the physical framebuffer that we use is setup by
* the platform device driver. It will provide us
* with cmd, wfm and image memory in a contiguous area. */
retval = board->setup_fb(par);
if (retval) {
dev_err(&dev->dev, "Failed to setup fb\n");
goto err_csum_table;
}
/* after this point we should have a framebuffer */
if ((!par->metromem_wfm) || (!par->metromem_img) ||
(!par->metromem_dma)) {
dev_err(&dev->dev, "fb access failure\n");
retval = -EINVAL;
goto err_csum_table;
}
info->fix.smem_start = par->metromem_dma;
/* load the waveform in. assume mode 3, temp 31 for now
a) request the waveform file from userspace
b) process waveform and decode into metromem */
retval = request_firmware(&fw_entry, "metronome.wbf", &dev->dev);
if (retval < 0) {
dev_err(&dev->dev, "Failed to get waveform\n");
goto err_csum_table;
}
retval = load_waveform((u8 *) fw_entry->data, fw_entry->size, 3, 31,
par);
release_firmware(fw_entry);
if (retval < 0) {
dev_err(&dev->dev, "Failed processing waveform\n");
goto err_csum_table;
}
retval = board->setup_irq(info);
if (retval)
goto err_csum_table;
retval = metronome_init_regs(par);
if (retval < 0)
goto err_free_irq;
info->flags = FBINFO_VIRTFB;
info->fbdefio = &metronomefb_defio;
fb_deferred_io_init(info);
retval = fb_alloc_cmap(&info->cmap, 8, 0);
if (retval < 0) {
dev_err(&dev->dev, "Failed to allocate colormap\n");
goto err_free_irq;
}
/* set cmap */
for (i = 0; i < 8; i++)
info->cmap.red[i] = (((2*i)+1)*(0xFFFF))/16;
memcpy(info->cmap.green, info->cmap.red, sizeof(u16)*8);
memcpy(info->cmap.blue, info->cmap.red, sizeof(u16)*8);
retval = register_framebuffer(info);
if (retval < 0)
goto err_cmap;
platform_set_drvdata(dev, info);
dev_dbg(&dev->dev,
"fb%d: Metronome frame buffer device, using %dK of video"
" memory\n", info->node, videomemorysize >> 10);
return 0;
err_cmap:
fb_dealloc_cmap(&info->cmap);
err_free_irq:
board->cleanup(par);
err_csum_table:
vfree(par->csum_table);
err_vfree:
vfree(videomemory);
err_fb_rel:
framebuffer_release(info);
err:
module_put(board->owner);
return retval;
}
static void metronomefb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
if (info) {
struct metronomefb_par *par = info->par;
unregister_framebuffer(info);
fb_deferred_io_cleanup(info);
fb_dealloc_cmap(&info->cmap);
par->board->cleanup(par);
vfree(par->csum_table);
vfree(info->screen_buffer);
module_put(par->board->owner);
dev_dbg(&dev->dev, "calling release\n");
framebuffer_release(info);
}
}
static struct platform_driver metronomefb_driver = {
.probe = metronomefb_probe,
.remove_new = metronomefb_remove,
.driver = {
.name = "metronomefb",
},
};
module_platform_driver(metronomefb_driver);
module_param(user_wfm_size, uint, 0);
MODULE_PARM_DESC(user_wfm_size, "Set custom waveform size");
MODULE_DESCRIPTION("fbdev driver for Metronome controller");
MODULE_AUTHOR("Jaya Kumar");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE("metronome.wbf");
| linux-master | drivers/video/fbdev/metronomefb.c |
/*
* linux/drivers/video/macmodes.c -- Standard MacOS video modes
*
* Copyright (C) 1998 Geert Uytterhoeven
*
* 2000 - Removal of OpenFirmware dependencies by:
* - Ani Joshi
* - Brad Douglas <[email protected]>
*
* 2001 - Documented with DocBook
* - Brad Douglas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/string.h>
#include <linux/module.h>
#include "macmodes.h"
/*
* MacOS video mode definitions
*
* Order IS important! If you change these, don't forget to update
* mac_modes[] below!
*/
#define DEFAULT_MODEDB_INDEX 0
static const struct fb_videomode mac_modedb[] = {
{
/* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
"mac2", 60, 512, 384, 63828, 80, 16, 19, 1, 32, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
"mac5", 60, 640, 480, 39722, 32, 32, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
"mac6", 67, 640, 480, 33334, 80, 80, 39, 3, 64, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
"mac7", 75, 640, 870, 17457, 80, 32, 42, 3, 80, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
"mac9", 56, 800, 600, 27778, 112, 40, 22, 1, 72, 2,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
"mac10", 60, 800, 600, 25000, 72, 56, 23, 1, 128, 4,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
"mac11", 72, 800, 600, 20000, 48, 72, 23, 37, 120, 6,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
"mac12", 75, 800, 600, 20203, 144, 32, 21, 1, 80, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
"mac13", 75, 832, 624, 17362, 208, 48, 39, 1, 64, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768, 60 Hz, Non-Interlaced (65.00 MHz dotclock) */
"mac14", 60, 1024, 768, 15385, 144, 40, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768, 72 Hz, Non-Interlaced (75.00 MHz dotclock) */
"mac15", 72, 1024, 768, 13334, 128, 40, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
"mac16", 75, 1024, 768, 12699, 176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
"mac17", 75, 1024, 768, 12699, 160, 32, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1152x870, 75 Hz, Non-Interlaced (100.0 MHz dotclock) */
"mac18", 75, 1152, 870, 10000, 128, 48, 39, 3, 128, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1280x960, 75 Hz, Non-Interlaced (126.00 MHz dotclock) */
"mac19", 75, 1280, 960, 7937, 224, 32, 36, 1, 144, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024, 75 Hz, Non-Interlaced (135.00 MHz dotclock) */
"mac20", 75, 1280, 1024, 7408, 232, 64, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1152x768, 60 Hz, Titanium PowerBook */
"mac21", 60, 1152, 768, 15386, 158, 26, 29, 3, 136, 6,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1024, 60 Hz, Non-Interlaced (112.27 MHz dotclock) */
"mac22", 60, 1600, 1024, 8908, 88, 104, 1, 10, 16, 1,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}
#if 0
/* Anyone who has timings for these? */
{
/* VMODE_512_384_60I: 512x384, 60Hz, Interlaced (NTSC) */
"mac1", 60, 512, 384, pixclock, left, right, upper, lower, hslen, vslen,
sync, FB_VMODE_INTERLACED
}, {
/* VMODE_640_480_50I: 640x480, 50Hz, Interlaced (PAL) */
"mac3", 50, 640, 480, pixclock, left, right, upper, lower, hslen, vslen,
sync, FB_VMODE_INTERLACED
}, {
/* VMODE_640_480_60I: 640x480, 60Hz, Interlaced (NTSC) */
"mac4", 60, 640, 480, pixclock, left, right, upper, lower, hslen, vslen,
sync, FB_VMODE_INTERLACED
}, {
/* VMODE_768_576_50I: 768x576, 50Hz (PAL full frame), Interlaced */
"mac8", 50, 768, 576, pixclock, left, right, upper, lower, hslen, vslen,
sync, FB_VMODE_INTERLACED
},
#endif
};
/*
* Mapping between MacOS video mode numbers and video mode definitions
*
* These MUST be ordered in
* - increasing resolution
* - decreasing pixel clock period
*/
static const struct mode_map {
int vmode;
const struct fb_videomode *mode;
} mac_modes[] = {
/* 512x384 */
{ VMODE_512_384_60, &mac_modedb[0] },
/* 640x480 */
{ VMODE_640_480_60, &mac_modedb[1] },
{ VMODE_640_480_67, &mac_modedb[2] },
/* 640x870 */
{ VMODE_640_870_75P, &mac_modedb[3] },
/* 800x600 */
{ VMODE_800_600_56, &mac_modedb[4] },
{ VMODE_800_600_60, &mac_modedb[5] },
{ VMODE_800_600_75, &mac_modedb[7] },
{ VMODE_800_600_72, &mac_modedb[6] },
/* 832x624 */
{ VMODE_832_624_75, &mac_modedb[8] },
/* 1024x768 */
{ VMODE_1024_768_60, &mac_modedb[9] },
{ VMODE_1024_768_70, &mac_modedb[10] },
{ VMODE_1024_768_75V, &mac_modedb[11] },
{ VMODE_1024_768_75, &mac_modedb[12] },
/* 1152x768 */
{ VMODE_1152_768_60, &mac_modedb[16] },
/* 1152x870 */
{ VMODE_1152_870_75, &mac_modedb[13] },
/* 1280x960 */
{ VMODE_1280_960_75, &mac_modedb[14] },
/* 1280x1024 */
{ VMODE_1280_1024_75, &mac_modedb[15] },
/* 1600x1024 */
{ VMODE_1600_1024_60, &mac_modedb[17] },
{ -1, NULL }
};
/*
* Mapping between monitor sense values and MacOS video mode numbers
*/
static const struct monitor_map {
int sense;
int vmode;
} mac_monitors[] = {
{ 0x000, VMODE_1280_1024_75 }, /* 21" RGB */
{ 0x114, VMODE_640_870_75P }, /* Portrait Monochrome */
{ 0x221, VMODE_512_384_60 }, /* 12" RGB*/
{ 0x331, VMODE_1280_1024_75 }, /* 21" RGB (Radius) */
{ 0x334, VMODE_1280_1024_75 }, /* 21" mono (Radius) */
{ 0x335, VMODE_1280_1024_75 }, /* 21" mono */
{ 0x40A, VMODE_640_480_60I }, /* NTSC */
{ 0x51E, VMODE_640_870_75P }, /* Portrait RGB */
{ 0x603, VMODE_832_624_75 }, /* 12"-16" multiscan */
{ 0x60b, VMODE_1024_768_70 }, /* 13"-19" multiscan */
{ 0x623, VMODE_1152_870_75 }, /* 13"-21" multiscan */
{ 0x62b, VMODE_640_480_67 }, /* 13"/14" RGB */
{ 0x700, VMODE_640_480_50I }, /* PAL */
{ 0x714, VMODE_640_480_60I }, /* NTSC */
{ 0x717, VMODE_800_600_75 }, /* VGA */
{ 0x72d, VMODE_832_624_75 }, /* 16" RGB (Goldfish) */
{ 0x730, VMODE_768_576_50I }, /* PAL (Alternate) */
{ 0x73a, VMODE_1152_870_75 }, /* 3rd party 19" */
{ 0x73f, VMODE_640_480_67 }, /* no sense lines connected at all */
{ 0xBEEF, VMODE_1600_1024_60 }, /* 22" Apple Cinema Display */
{ -1, VMODE_640_480_60 }, /* catch-all, must be last */
};
/**
* mac_vmode_to_var - converts vmode/cmode pair to var structure
* @vmode: MacOS video mode
* @cmode: MacOS color mode
* @var: frame buffer video mode structure
*
* Converts a MacOS vmode/cmode pair to a frame buffer video
* mode structure.
*
* Returns negative errno on error, or zero for success.
*
*/
int mac_vmode_to_var(int vmode, int cmode, struct fb_var_screeninfo *var)
{
const struct fb_videomode *mode = NULL;
const struct mode_map *map;
for (map = mac_modes; map->vmode != -1; map++)
if (map->vmode == vmode) {
mode = map->mode;
break;
}
if (!mode)
return -EINVAL;
memset(var, 0, sizeof(struct fb_var_screeninfo));
switch (cmode) {
case CMODE_8:
var->bits_per_pixel = 8;
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
case CMODE_16:
var->bits_per_pixel = 16;
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 0;
var->blue.length = 5;
break;
case CMODE_32:
var->bits_per_pixel = 32;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
default:
return -EINVAL;
}
var->xres = mode->xres;
var->yres = mode->yres;
var->xres_virtual = mode->xres;
var->yres_virtual = mode->yres;
var->height = -1;
var->width = -1;
var->pixclock = mode->pixclock;
var->left_margin = mode->left_margin;
var->right_margin = mode->right_margin;
var->upper_margin = mode->upper_margin;
var->lower_margin = mode->lower_margin;
var->hsync_len = mode->hsync_len;
var->vsync_len = mode->vsync_len;
var->sync = mode->sync;
var->vmode = mode->vmode;
return 0;
}
EXPORT_SYMBOL(mac_vmode_to_var);
/**
* mac_var_to_vmode - convert var structure to MacOS vmode/cmode pair
* @var: frame buffer video mode structure
* @vmode: MacOS video mode
* @cmode: MacOS color mode
*
* Converts a frame buffer video mode structure to a MacOS
* vmode/cmode pair.
*
* Returns negative errno on error, or zero for success.
*
*/
int mac_var_to_vmode(const struct fb_var_screeninfo *var, int *vmode,
int *cmode)
{
const struct mode_map *map;
if (var->bits_per_pixel <= 8)
*cmode = CMODE_8;
else if (var->bits_per_pixel <= 16)
*cmode = CMODE_16;
else if (var->bits_per_pixel <= 32)
*cmode = CMODE_32;
else
return -EINVAL;
/*
* Find the mac_mode with a matching resolution or failing that, the
* closest larger resolution. Skip modes with a shorter pixel clock period.
*/
for (map = mac_modes; map->vmode != -1; map++) {
const struct fb_videomode *mode = map->mode;
if (var->xres > mode->xres || var->yres > mode->yres)
continue;
if (var->xres_virtual > mode->xres || var->yres_virtual > mode->yres)
continue;
if (var->pixclock > mode->pixclock)
continue;
if ((var->vmode & FB_VMODE_MASK) != mode->vmode)
continue;
*vmode = map->vmode;
/*
* Having found a good resolution, find the matching pixel clock
* or failing that, the closest longer pixel clock period.
*/
map++;
while (map->vmode != -1) {
const struct fb_videomode *clk_mode = map->mode;
if (mode->xres != clk_mode->xres || mode->yres != clk_mode->yres)
break;
if (var->pixclock > mode->pixclock)
break;
if (mode->vmode != clk_mode->vmode)
continue;
*vmode = map->vmode;
map++;
}
return 0;
}
return -EINVAL;
}
/**
* mac_map_monitor_sense - Convert monitor sense to vmode
* @sense: Macintosh monitor sense number
*
* Converts a Macintosh monitor sense number to a MacOS
* vmode number.
*
* Returns MacOS vmode video mode number.
*
*/
int mac_map_monitor_sense(int sense)
{
const struct monitor_map *map;
for (map = mac_monitors; map->sense != -1; map++)
if (map->sense == sense)
break;
return map->vmode;
}
EXPORT_SYMBOL(mac_map_monitor_sense);
/**
* mac_find_mode - find a video mode
* @var: frame buffer user defined part of display
* @info: frame buffer info structure
* @mode_option: video mode name (see mac_modedb[])
* @default_bpp: default color depth in bits per pixel
*
* Finds a suitable video mode. Tries to set mode specified
* by @mode_option. If the name of the wanted mode begins with
* 'mac', the Mac video mode database will be used, otherwise it
* will fall back to the standard video mode database.
*
* Note: Function marked as __init and can only be used during
* system boot.
*
* Returns error code from fb_find_mode (see fb_find_mode
* function).
*
*/
int mac_find_mode(struct fb_var_screeninfo *var, struct fb_info *info,
const char *mode_option, unsigned int default_bpp)
{
const struct fb_videomode *db = NULL;
unsigned int dbsize = 0;
if (mode_option && !strncmp(mode_option, "mac", 3)) {
mode_option += 3;
db = mac_modedb;
dbsize = ARRAY_SIZE(mac_modedb);
}
return fb_find_mode(var, info, mode_option, db, dbsize,
&mac_modedb[DEFAULT_MODEDB_INDEX], default_bpp);
}
EXPORT_SYMBOL(mac_find_mode);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/macmodes.c |
/*
* linux/drivers/video/q40fb.c -- Q40 frame buffer device
*
* Copyright (C) 2001
*
* Richard Zidlicky <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <asm/setup.h>
#include <asm/q40_master.h>
#include <linux/fb.h>
#include <linux/module.h>
#define Q40_PHYS_SCREEN_ADDR 0xFE800000
static struct fb_fix_screeninfo q40fb_fix = {
.id = "Q40",
.smem_len = 1024*1024,
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.line_length = 1024*2,
.accel = FB_ACCEL_NONE,
};
static const struct fb_var_screeninfo q40fb_var = {
.xres = 1024,
.yres = 512,
.xres_virtual = 1024,
.yres_virtual = 512,
.bits_per_pixel = 16,
.red = {6, 5, 0},
.green = {11, 5, 0},
.blue = {0, 6, 0},
.activate = FB_ACTIVATE_NOW,
.height = 230,
.width = 300,
.vmode = FB_VMODE_NONINTERLACED,
};
static int q40fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
/*
* Set a single color register. The values supplied have a 16 bit
* magnitude.
* Return != 0 for invalid regno.
*/
if (regno > 255)
return 1;
red>>=11;
green>>=11;
blue>>=10;
if (regno < 16) {
((u32 *)info->pseudo_palette)[regno] = ((red & 31) <<6) |
((green & 31) << 11) |
(blue & 63);
}
return 0;
}
static const struct fb_ops q40fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = q40fb_setcolreg,
};
static int q40fb_probe(struct platform_device *dev)
{
struct fb_info *info;
if (!MACH_IS_Q40)
return -ENXIO;
/* mapped in q40/config.c */
q40fb_fix.smem_start = Q40_PHYS_SCREEN_ADDR;
info = framebuffer_alloc(sizeof(u32) * 16, &dev->dev);
if (!info)
return -ENOMEM;
info->var = q40fb_var;
info->fix = q40fb_fix;
info->fbops = &q40fb_ops;
info->pseudo_palette = info->par;
info->par = NULL;
info->screen_base = (char *) q40fb_fix.smem_start;
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
framebuffer_release(info);
return -ENOMEM;
}
master_outb(3, DISPLAY_CONTROL_REG);
if (register_framebuffer(info) < 0) {
printk(KERN_ERR "Unable to register Q40 frame buffer\n");
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
return -EINVAL;
}
fb_info(info, "Q40 frame buffer alive and kicking !\n");
return 0;
}
static struct platform_driver q40fb_driver = {
.probe = q40fb_probe,
.driver = {
.name = "q40fb",
},
};
static struct platform_device q40fb_device = {
.name = "q40fb",
};
static int __init q40fb_init(void)
{
int ret = 0;
if (fb_get_options("q40fb", NULL))
return -ENODEV;
ret = platform_driver_register(&q40fb_driver);
if (!ret) {
ret = platform_device_register(&q40fb_device);
if (ret)
platform_driver_unregister(&q40fb_driver);
}
return ret;
}
module_init(q40fb_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/q40fb.c |
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