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/*
* OpenCores VGA/LCD 2.0 core frame buffer driver
*
* Copyright (C) 2013 Stefan Kristiansson, [email protected]
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/string.h>
#include <linux/slab.h>
/* OCFB register defines */
#define OCFB_CTRL 0x000
#define OCFB_STAT 0x004
#define OCFB_HTIM 0x008
#define OCFB_VTIM 0x00c
#define OCFB_HVLEN 0x010
#define OCFB_VBARA 0x014
#define OCFB_PALETTE 0x800
#define OCFB_CTRL_VEN 0x00000001 /* Video Enable */
#define OCFB_CTRL_HIE 0x00000002 /* HSync Interrupt Enable */
#define OCFB_CTRL_PC 0x00000800 /* 8-bit Pseudo Color Enable*/
#define OCFB_CTRL_CD8 0x00000000 /* Color Depth 8 */
#define OCFB_CTRL_CD16 0x00000200 /* Color Depth 16 */
#define OCFB_CTRL_CD24 0x00000400 /* Color Depth 24 */
#define OCFB_CTRL_CD32 0x00000600 /* Color Depth 32 */
#define OCFB_CTRL_VBL1 0x00000000 /* Burst Length 1 */
#define OCFB_CTRL_VBL2 0x00000080 /* Burst Length 2 */
#define OCFB_CTRL_VBL4 0x00000100 /* Burst Length 4 */
#define OCFB_CTRL_VBL8 0x00000180 /* Burst Length 8 */
#define PALETTE_SIZE 256
#define OCFB_NAME "OC VGA/LCD"
static char *mode_option;
static const struct fb_videomode default_mode = {
/* 640x480 @ 60 Hz, 31.5 kHz hsync */
NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
0, FB_VMODE_NONINTERLACED
};
struct ocfb_dev {
struct fb_info info;
void __iomem *regs;
/* flag indicating whether the regs are little endian accessed */
int little_endian;
/* Physical and virtual addresses of framebuffer */
dma_addr_t fb_phys;
void __iomem *fb_virt;
u32 pseudo_palette[PALETTE_SIZE];
};
#ifndef MODULE
static int __init ocfb_setup(char *options)
{
char *curr_opt;
if (!options || !*options)
return 0;
while ((curr_opt = strsep(&options, ",")) != NULL) {
if (!*curr_opt)
continue;
mode_option = curr_opt;
}
return 0;
}
#endif
static inline u32 ocfb_readreg(struct ocfb_dev *fbdev, loff_t offset)
{
if (fbdev->little_endian)
return ioread32(fbdev->regs + offset);
else
return ioread32be(fbdev->regs + offset);
}
static void ocfb_writereg(struct ocfb_dev *fbdev, loff_t offset, u32 data)
{
if (fbdev->little_endian)
iowrite32(data, fbdev->regs + offset);
else
iowrite32be(data, fbdev->regs + offset);
}
static int ocfb_setupfb(struct ocfb_dev *fbdev)
{
unsigned long bpp_config;
struct fb_var_screeninfo *var = &fbdev->info.var;
struct device *dev = fbdev->info.device;
u32 hlen;
u32 vlen;
/* Disable display */
ocfb_writereg(fbdev, OCFB_CTRL, 0);
/* Register framebuffer address */
fbdev->little_endian = 0;
ocfb_writereg(fbdev, OCFB_VBARA, fbdev->fb_phys);
/* Detect endianess */
if (ocfb_readreg(fbdev, OCFB_VBARA) != fbdev->fb_phys) {
fbdev->little_endian = 1;
ocfb_writereg(fbdev, OCFB_VBARA, fbdev->fb_phys);
}
/* Horizontal timings */
ocfb_writereg(fbdev, OCFB_HTIM, (var->hsync_len - 1) << 24 |
(var->left_margin - 1) << 16 | (var->xres - 1));
/* Vertical timings */
ocfb_writereg(fbdev, OCFB_VTIM, (var->vsync_len - 1) << 24 |
(var->upper_margin - 1) << 16 | (var->yres - 1));
/* Total length of frame */
hlen = var->left_margin + var->right_margin + var->hsync_len +
var->xres;
vlen = var->upper_margin + var->lower_margin + var->vsync_len +
var->yres;
ocfb_writereg(fbdev, OCFB_HVLEN, (hlen - 1) << 16 | (vlen - 1));
bpp_config = OCFB_CTRL_CD8;
switch (var->bits_per_pixel) {
case 8:
if (!var->grayscale)
bpp_config |= OCFB_CTRL_PC; /* enable palette */
break;
case 16:
bpp_config |= OCFB_CTRL_CD16;
break;
case 24:
bpp_config |= OCFB_CTRL_CD24;
break;
case 32:
bpp_config |= OCFB_CTRL_CD32;
break;
default:
dev_err(dev, "no bpp specified\n");
break;
}
/* maximum (8) VBL (video memory burst length) */
bpp_config |= OCFB_CTRL_VBL8;
/* Enable output */
ocfb_writereg(fbdev, OCFB_CTRL, (OCFB_CTRL_VEN | bpp_config));
return 0;
}
static int ocfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct ocfb_dev *fbdev = (struct ocfb_dev *)info->par;
u32 color;
if (regno >= info->cmap.len) {
dev_err(info->device, "regno >= cmap.len\n");
return 1;
}
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
red >>= (16 - info->var.red.length);
green >>= (16 - info->var.green.length);
blue >>= (16 - info->var.blue.length);
transp >>= (16 - info->var.transp.length);
if (info->var.bits_per_pixel == 8 && !info->var.grayscale) {
regno <<= 2;
color = (red << 16) | (green << 8) | blue;
ocfb_writereg(fbdev, OCFB_PALETTE + regno, color);
} else {
((u32 *)(info->pseudo_palette))[regno] =
(red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
}
return 0;
}
static int ocfb_init_fix(struct ocfb_dev *fbdev)
{
struct fb_var_screeninfo *var = &fbdev->info.var;
struct fb_fix_screeninfo *fix = &fbdev->info.fix;
strcpy(fix->id, OCFB_NAME);
fix->line_length = var->xres * var->bits_per_pixel/8;
fix->smem_len = fix->line_length * var->yres;
fix->type = FB_TYPE_PACKED_PIXELS;
if (var->bits_per_pixel == 8 && !var->grayscale)
fix->visual = FB_VISUAL_PSEUDOCOLOR;
else
fix->visual = FB_VISUAL_TRUECOLOR;
return 0;
}
static int ocfb_init_var(struct ocfb_dev *fbdev)
{
struct fb_var_screeninfo *var = &fbdev->info.var;
var->accel_flags = FB_ACCEL_NONE;
var->activate = FB_ACTIVATE_NOW;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
switch (var->bits_per_pixel) {
case 8:
var->transp.offset = 0;
var->transp.length = 0;
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
case 16:
var->transp.offset = 0;
var->transp.length = 0;
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
break;
case 24:
var->transp.offset = 0;
var->transp.length = 0;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
case 32:
var->transp.offset = 24;
var->transp.length = 8;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
}
return 0;
}
static const struct fb_ops ocfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = ocfb_setcolreg,
};
static int ocfb_probe(struct platform_device *pdev)
{
int ret = 0;
struct ocfb_dev *fbdev;
int fbsize;
fbdev = devm_kzalloc(&pdev->dev, sizeof(*fbdev), GFP_KERNEL);
if (!fbdev)
return -ENOMEM;
platform_set_drvdata(pdev, fbdev);
fbdev->info.fbops = &ocfb_ops;
fbdev->info.device = &pdev->dev;
fbdev->info.par = fbdev;
/* Video mode setup */
if (!fb_find_mode(&fbdev->info.var, &fbdev->info, mode_option,
NULL, 0, &default_mode, 16)) {
dev_err(&pdev->dev, "No valid video modes found\n");
return -EINVAL;
}
ocfb_init_var(fbdev);
ocfb_init_fix(fbdev);
fbdev->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(fbdev->regs))
return PTR_ERR(fbdev->regs);
/* Allocate framebuffer memory */
fbsize = fbdev->info.fix.smem_len;
fbdev->fb_virt = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(fbsize),
&fbdev->fb_phys, GFP_KERNEL);
if (!fbdev->fb_virt) {
dev_err(&pdev->dev,
"Frame buffer memory allocation failed\n");
return -ENOMEM;
}
fbdev->info.fix.smem_start = fbdev->fb_phys;
fbdev->info.screen_base = fbdev->fb_virt;
fbdev->info.pseudo_palette = fbdev->pseudo_palette;
/* Clear framebuffer */
memset_io(fbdev->fb_virt, 0, fbsize);
/* Setup and enable the framebuffer */
ocfb_setupfb(fbdev);
if (fbdev->little_endian)
fbdev->info.flags |= FBINFO_FOREIGN_ENDIAN;
/* Allocate color map */
ret = fb_alloc_cmap(&fbdev->info.cmap, PALETTE_SIZE, 0);
if (ret) {
dev_err(&pdev->dev, "Color map allocation failed\n");
goto err_dma_free;
}
/* Register framebuffer */
ret = register_framebuffer(&fbdev->info);
if (ret) {
dev_err(&pdev->dev, "Framebuffer registration failed\n");
goto err_dealloc_cmap;
}
return 0;
err_dealloc_cmap:
fb_dealloc_cmap(&fbdev->info.cmap);
err_dma_free:
dma_free_coherent(&pdev->dev, PAGE_ALIGN(fbsize), fbdev->fb_virt,
fbdev->fb_phys);
return ret;
}
static void ocfb_remove(struct platform_device *pdev)
{
struct ocfb_dev *fbdev = platform_get_drvdata(pdev);
unregister_framebuffer(&fbdev->info);
fb_dealloc_cmap(&fbdev->info.cmap);
dma_free_coherent(&pdev->dev, PAGE_ALIGN(fbdev->info.fix.smem_len),
fbdev->fb_virt, fbdev->fb_phys);
/* Disable display */
ocfb_writereg(fbdev, OCFB_CTRL, 0);
platform_set_drvdata(pdev, NULL);
}
static const struct of_device_id ocfb_match[] = {
{ .compatible = "opencores,ocfb", },
{},
};
MODULE_DEVICE_TABLE(of, ocfb_match);
static struct platform_driver ocfb_driver = {
.probe = ocfb_probe,
.remove_new = ocfb_remove,
.driver = {
.name = "ocfb_fb",
.of_match_table = ocfb_match,
}
};
/*
* Init and exit routines
*/
static int __init ocfb_init(void)
{
#ifndef MODULE
char *option = NULL;
if (fb_get_options("ocfb", &option))
return -ENODEV;
ocfb_setup(option);
#endif
return platform_driver_register(&ocfb_driver);
}
static void __exit ocfb_exit(void)
{
platform_driver_unregister(&ocfb_driver);
}
module_init(ocfb_init);
module_exit(ocfb_exit);
MODULE_AUTHOR("Stefan Kristiansson <[email protected]>");
MODULE_DESCRIPTION("OpenCores VGA/LCD 2.0 frame buffer driver");
MODULE_LICENSE("GPL v2");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Video mode ('<xres>x<yres>[-<bpp>][@refresh]')");
| linux-master | drivers/video/fbdev/ocfb.c |
/*
* Fast C2P (Chunky-to-Planar) Conversion
*
* Copyright (C) 2003-2008 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/string.h>
#include <asm/unaligned.h>
#include "c2p.h"
#include "c2p_core.h"
/*
* Perform a full C2P step on 32 8-bit pixels, stored in 8 32-bit words
* containing
* - 32 8-bit chunky pixels on input
* - permutated planar data (1 plane per 32-bit word) on output
*/
static void c2p_32x8(u32 d[8])
{
transp8(d, 16, 4);
transp8(d, 8, 2);
transp8(d, 4, 1);
transp8(d, 2, 4);
transp8(d, 1, 2);
}
/*
* Array containing the permutation indices of the planar data after c2p
*/
static const int perm_c2p_32x8[8] = { 7, 5, 3, 1, 6, 4, 2, 0 };
/*
* Store a full block of planar data after c2p conversion
*/
static inline void store_planar(void *dst, u32 dst_inc, u32 bpp, u32 d[8])
{
int i;
for (i = 0; i < bpp; i++, dst += dst_inc)
put_unaligned_be32(d[perm_c2p_32x8[i]], dst);
}
/*
* Store a partial block of planar data after c2p conversion
*/
static inline void store_planar_masked(void *dst, u32 dst_inc, u32 bpp,
u32 d[8], u32 mask)
{
int i;
for (i = 0; i < bpp; i++, dst += dst_inc)
put_unaligned_be32(comp(d[perm_c2p_32x8[i]],
get_unaligned_be32(dst), mask),
dst);
}
/*
* c2p_planar - Copy 8-bit chunky image data to a planar frame buffer
* @dst: Starting address of the planar frame buffer
* @dx: Horizontal destination offset (in pixels)
* @dy: Vertical destination offset (in pixels)
* @width: Image width (in pixels)
* @height: Image height (in pixels)
* @dst_nextline: Frame buffer offset to the next line (in bytes)
* @dst_nextplane: Frame buffer offset to the next plane (in bytes)
* @src_nextline: Image offset to the next line (in bytes)
* @bpp: Bits per pixel of the planar frame buffer (1-8)
*/
void c2p_planar(void *dst, const void *src, u32 dx, u32 dy, u32 width,
u32 height, u32 dst_nextline, u32 dst_nextplane,
u32 src_nextline, u32 bpp)
{
union {
u8 pixels[32];
u32 words[8];
} d;
u32 dst_idx, first, last, w;
const u8 *c;
void *p;
dst += dy*dst_nextline+(dx & ~31);
dst_idx = dx % 32;
first = 0xffffffffU >> dst_idx;
last = ~(0xffffffffU >> ((dst_idx+width) % 32));
while (height--) {
c = src;
p = dst;
w = width;
if (dst_idx+width <= 32) {
/* Single destination word */
first &= last;
memset(d.pixels, 0, sizeof(d));
memcpy(d.pixels+dst_idx, c, width);
c += width;
c2p_32x8(d.words);
store_planar_masked(p, dst_nextplane, bpp, d.words,
first);
p += 4;
} else {
/* Multiple destination words */
w = width;
/* Leading bits */
if (dst_idx) {
w = 32 - dst_idx;
memset(d.pixels, 0, dst_idx);
memcpy(d.pixels+dst_idx, c, w);
c += w;
c2p_32x8(d.words);
store_planar_masked(p, dst_nextplane, bpp,
d.words, first);
p += 4;
w = width-w;
}
/* Main chunk */
while (w >= 32) {
memcpy(d.pixels, c, 32);
c += 32;
c2p_32x8(d.words);
store_planar(p, dst_nextplane, bpp, d.words);
p += 4;
w -= 32;
}
/* Trailing bits */
w %= 32;
if (w > 0) {
memcpy(d.pixels, c, w);
memset(d.pixels+w, 0, 32-w);
c2p_32x8(d.words);
store_planar_masked(p, dst_nextplane, bpp,
d.words, last);
}
}
src += src_nextline;
dst += dst_nextline;
}
}
EXPORT_SYMBOL_GPL(c2p_planar);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/c2p_planar.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Simplest possible simple frame-buffer driver, as a platform device
*
* Copyright (c) 2013, Stephen Warren
*
* Based on q40fb.c, which was:
* Copyright (C) 2001 Richard Zidlicky <[email protected]>
*
* Also based on offb.c, which was:
* Copyright (C) 1997 Geert Uytterhoeven
* Copyright (C) 1996 Paul Mackerras
*/
#include <linux/aperture.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_data/simplefb.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_clk.h>
#include <linux/of_platform.h>
#include <linux/parser.h>
#include <linux/regulator/consumer.h>
static const struct fb_fix_screeninfo simplefb_fix = {
.id = "simple",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.accel = FB_ACCEL_NONE,
};
static const struct fb_var_screeninfo simplefb_var = {
.height = -1,
.width = -1,
.activate = FB_ACTIVATE_NOW,
.vmode = FB_VMODE_NONINTERLACED,
};
#define PSEUDO_PALETTE_SIZE 16
static int simplefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
u32 *pal = info->pseudo_palette;
u32 cr = red >> (16 - info->var.red.length);
u32 cg = green >> (16 - info->var.green.length);
u32 cb = blue >> (16 - info->var.blue.length);
u32 value;
if (regno >= PSEUDO_PALETTE_SIZE)
return -EINVAL;
value = (cr << info->var.red.offset) |
(cg << info->var.green.offset) |
(cb << info->var.blue.offset);
if (info->var.transp.length > 0) {
u32 mask = (1 << info->var.transp.length) - 1;
mask <<= info->var.transp.offset;
value |= mask;
}
pal[regno] = value;
return 0;
}
struct simplefb_par {
u32 palette[PSEUDO_PALETTE_SIZE];
resource_size_t base;
resource_size_t size;
struct resource *mem;
#if defined CONFIG_OF && defined CONFIG_COMMON_CLK
bool clks_enabled;
unsigned int clk_count;
struct clk **clks;
#endif
#if defined CONFIG_OF && defined CONFIG_REGULATOR
bool regulators_enabled;
u32 regulator_count;
struct regulator **regulators;
#endif
};
static void simplefb_clocks_destroy(struct simplefb_par *par);
static void simplefb_regulators_destroy(struct simplefb_par *par);
/*
* fb_ops.fb_destroy is called by the last put_fb_info() call at the end
* of unregister_framebuffer() or fb_release(). Do any cleanup here.
*/
static void simplefb_destroy(struct fb_info *info)
{
struct simplefb_par *par = info->par;
struct resource *mem = par->mem;
simplefb_regulators_destroy(info->par);
simplefb_clocks_destroy(info->par);
if (info->screen_base)
iounmap(info->screen_base);
framebuffer_release(info);
if (mem)
release_mem_region(mem->start, resource_size(mem));
}
static const struct fb_ops simplefb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_destroy = simplefb_destroy,
.fb_setcolreg = simplefb_setcolreg,
};
static struct simplefb_format simplefb_formats[] = SIMPLEFB_FORMATS;
struct simplefb_params {
u32 width;
u32 height;
u32 stride;
struct simplefb_format *format;
};
static int simplefb_parse_dt(struct platform_device *pdev,
struct simplefb_params *params)
{
struct device_node *np = pdev->dev.of_node;
int ret;
const char *format;
int i;
ret = of_property_read_u32(np, "width", ¶ms->width);
if (ret) {
dev_err(&pdev->dev, "Can't parse width property\n");
return ret;
}
ret = of_property_read_u32(np, "height", ¶ms->height);
if (ret) {
dev_err(&pdev->dev, "Can't parse height property\n");
return ret;
}
ret = of_property_read_u32(np, "stride", ¶ms->stride);
if (ret) {
dev_err(&pdev->dev, "Can't parse stride property\n");
return ret;
}
ret = of_property_read_string(np, "format", &format);
if (ret) {
dev_err(&pdev->dev, "Can't parse format property\n");
return ret;
}
params->format = NULL;
for (i = 0; i < ARRAY_SIZE(simplefb_formats); i++) {
if (strcmp(format, simplefb_formats[i].name))
continue;
params->format = &simplefb_formats[i];
break;
}
if (!params->format) {
dev_err(&pdev->dev, "Invalid format value\n");
return -EINVAL;
}
return 0;
}
static int simplefb_parse_pd(struct platform_device *pdev,
struct simplefb_params *params)
{
struct simplefb_platform_data *pd = dev_get_platdata(&pdev->dev);
int i;
params->width = pd->width;
params->height = pd->height;
params->stride = pd->stride;
params->format = NULL;
for (i = 0; i < ARRAY_SIZE(simplefb_formats); i++) {
if (strcmp(pd->format, simplefb_formats[i].name))
continue;
params->format = &simplefb_formats[i];
break;
}
if (!params->format) {
dev_err(&pdev->dev, "Invalid format value\n");
return -EINVAL;
}
return 0;
}
#if defined CONFIG_OF && defined CONFIG_COMMON_CLK
/*
* Clock handling code.
*
* Here we handle the clocks property of our "simple-framebuffer" dt node.
* This is necessary so that we can make sure that any clocks needed by
* the display engine that the bootloader set up for us (and for which it
* provided a simplefb dt node), stay up, for the life of the simplefb
* driver.
*
* When the driver unloads, we cleanly disable, and then release the clocks.
*
* We only complain about errors here, no action is taken as the most likely
* error can only happen due to a mismatch between the bootloader which set
* up simplefb, and the clock definitions in the device tree. Chances are
* that there are no adverse effects, and if there are, a clean teardown of
* the fb probe will not help us much either. So just complain and carry on,
* and hope that the user actually gets a working fb at the end of things.
*/
static int simplefb_clocks_get(struct simplefb_par *par,
struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct clk *clock;
int i;
if (dev_get_platdata(&pdev->dev) || !np)
return 0;
par->clk_count = of_clk_get_parent_count(np);
if (!par->clk_count)
return 0;
par->clks = kcalloc(par->clk_count, sizeof(struct clk *), GFP_KERNEL);
if (!par->clks)
return -ENOMEM;
for (i = 0; i < par->clk_count; i++) {
clock = of_clk_get(np, i);
if (IS_ERR(clock)) {
if (PTR_ERR(clock) == -EPROBE_DEFER) {
while (--i >= 0) {
clk_put(par->clks[i]);
}
kfree(par->clks);
return -EPROBE_DEFER;
}
dev_err(&pdev->dev, "%s: clock %d not found: %ld\n",
__func__, i, PTR_ERR(clock));
continue;
}
par->clks[i] = clock;
}
return 0;
}
static void simplefb_clocks_enable(struct simplefb_par *par,
struct platform_device *pdev)
{
int i, ret;
for (i = 0; i < par->clk_count; i++) {
if (par->clks[i]) {
ret = clk_prepare_enable(par->clks[i]);
if (ret) {
dev_err(&pdev->dev,
"%s: failed to enable clock %d: %d\n",
__func__, i, ret);
clk_put(par->clks[i]);
par->clks[i] = NULL;
}
}
}
par->clks_enabled = true;
}
static void simplefb_clocks_destroy(struct simplefb_par *par)
{
int i;
if (!par->clks)
return;
for (i = 0; i < par->clk_count; i++) {
if (par->clks[i]) {
if (par->clks_enabled)
clk_disable_unprepare(par->clks[i]);
clk_put(par->clks[i]);
}
}
kfree(par->clks);
}
#else
static int simplefb_clocks_get(struct simplefb_par *par,
struct platform_device *pdev) { return 0; }
static void simplefb_clocks_enable(struct simplefb_par *par,
struct platform_device *pdev) { }
static void simplefb_clocks_destroy(struct simplefb_par *par) { }
#endif
#if defined CONFIG_OF && defined CONFIG_REGULATOR
#define SUPPLY_SUFFIX "-supply"
/*
* Regulator handling code.
*
* Here we handle the num-supplies and vin*-supply properties of our
* "simple-framebuffer" dt node. This is necessary so that we can make sure
* that any regulators needed by the display hardware that the bootloader
* set up for us (and for which it provided a simplefb dt node), stay up,
* for the life of the simplefb driver.
*
* When the driver unloads, we cleanly disable, and then release the
* regulators.
*
* We only complain about errors here, no action is taken as the most likely
* error can only happen due to a mismatch between the bootloader which set
* up simplefb, and the regulator definitions in the device tree. Chances are
* that there are no adverse effects, and if there are, a clean teardown of
* the fb probe will not help us much either. So just complain and carry on,
* and hope that the user actually gets a working fb at the end of things.
*/
static int simplefb_regulators_get(struct simplefb_par *par,
struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct property *prop;
struct regulator *regulator;
const char *p;
int count = 0, i = 0;
if (dev_get_platdata(&pdev->dev) || !np)
return 0;
/* Count the number of regulator supplies */
for_each_property_of_node(np, prop) {
p = strstr(prop->name, SUPPLY_SUFFIX);
if (p && p != prop->name)
count++;
}
if (!count)
return 0;
par->regulators = devm_kcalloc(&pdev->dev, count,
sizeof(struct regulator *), GFP_KERNEL);
if (!par->regulators)
return -ENOMEM;
/* Get all the regulators */
for_each_property_of_node(np, prop) {
char name[32]; /* 32 is max size of property name */
p = strstr(prop->name, SUPPLY_SUFFIX);
if (!p || p == prop->name)
continue;
strscpy(name, prop->name,
strlen(prop->name) - strlen(SUPPLY_SUFFIX) + 1);
regulator = devm_regulator_get_optional(&pdev->dev, name);
if (IS_ERR(regulator)) {
if (PTR_ERR(regulator) == -EPROBE_DEFER)
return -EPROBE_DEFER;
dev_err(&pdev->dev, "regulator %s not found: %ld\n",
name, PTR_ERR(regulator));
continue;
}
par->regulators[i++] = regulator;
}
par->regulator_count = i;
return 0;
}
static void simplefb_regulators_enable(struct simplefb_par *par,
struct platform_device *pdev)
{
int i, ret;
/* Enable all the regulators */
for (i = 0; i < par->regulator_count; i++) {
ret = regulator_enable(par->regulators[i]);
if (ret) {
dev_err(&pdev->dev,
"failed to enable regulator %d: %d\n",
i, ret);
devm_regulator_put(par->regulators[i]);
par->regulators[i] = NULL;
}
}
par->regulators_enabled = true;
}
static void simplefb_regulators_destroy(struct simplefb_par *par)
{
int i;
if (!par->regulators || !par->regulators_enabled)
return;
for (i = 0; i < par->regulator_count; i++)
if (par->regulators[i])
regulator_disable(par->regulators[i]);
}
#else
static int simplefb_regulators_get(struct simplefb_par *par,
struct platform_device *pdev) { return 0; }
static void simplefb_regulators_enable(struct simplefb_par *par,
struct platform_device *pdev) { }
static void simplefb_regulators_destroy(struct simplefb_par *par) { }
#endif
static int simplefb_probe(struct platform_device *pdev)
{
int ret;
struct simplefb_params params;
struct fb_info *info;
struct simplefb_par *par;
struct resource *res, *mem;
if (fb_get_options("simplefb", NULL))
return -ENODEV;
ret = -ENODEV;
if (dev_get_platdata(&pdev->dev))
ret = simplefb_parse_pd(pdev, ¶ms);
else if (pdev->dev.of_node)
ret = simplefb_parse_dt(pdev, ¶ms);
if (ret)
return ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "No memory resource\n");
return -EINVAL;
}
mem = request_mem_region(res->start, resource_size(res), "simplefb");
if (!mem) {
/*
* We cannot make this fatal. Sometimes this comes from magic
* spaces our resource handlers simply don't know about. Use
* the I/O-memory resource as-is and try to map that instead.
*/
dev_warn(&pdev->dev, "simplefb: cannot reserve video memory at %pR\n", res);
mem = res;
}
info = framebuffer_alloc(sizeof(struct simplefb_par), &pdev->dev);
if (!info) {
ret = -ENOMEM;
goto error_release_mem_region;
}
platform_set_drvdata(pdev, info);
par = info->par;
info->fix = simplefb_fix;
info->fix.smem_start = mem->start;
info->fix.smem_len = resource_size(mem);
info->fix.line_length = params.stride;
info->var = simplefb_var;
info->var.xres = params.width;
info->var.yres = params.height;
info->var.xres_virtual = params.width;
info->var.yres_virtual = params.height;
info->var.bits_per_pixel = params.format->bits_per_pixel;
info->var.red = params.format->red;
info->var.green = params.format->green;
info->var.blue = params.format->blue;
info->var.transp = params.format->transp;
par->base = info->fix.smem_start;
par->size = info->fix.smem_len;
info->fbops = &simplefb_ops;
info->screen_base = ioremap_wc(info->fix.smem_start,
info->fix.smem_len);
if (!info->screen_base) {
ret = -ENOMEM;
goto error_fb_release;
}
info->pseudo_palette = par->palette;
ret = simplefb_clocks_get(par, pdev);
if (ret < 0)
goto error_unmap;
ret = simplefb_regulators_get(par, pdev);
if (ret < 0)
goto error_clocks;
simplefb_clocks_enable(par, pdev);
simplefb_regulators_enable(par, pdev);
dev_info(&pdev->dev, "framebuffer at 0x%lx, 0x%x bytes\n",
info->fix.smem_start, info->fix.smem_len);
dev_info(&pdev->dev, "format=%s, mode=%dx%dx%d, linelength=%d\n",
params.format->name,
info->var.xres, info->var.yres,
info->var.bits_per_pixel, info->fix.line_length);
if (mem != res)
par->mem = mem; /* release in clean-up handler */
ret = devm_aperture_acquire_for_platform_device(pdev, par->base, par->size);
if (ret) {
dev_err(&pdev->dev, "Unable to acquire aperture: %d\n", ret);
goto error_regulators;
}
ret = register_framebuffer(info);
if (ret < 0) {
dev_err(&pdev->dev, "Unable to register simplefb: %d\n", ret);
goto error_regulators;
}
dev_info(&pdev->dev, "fb%d: simplefb registered!\n", info->node);
return 0;
error_regulators:
simplefb_regulators_destroy(par);
error_clocks:
simplefb_clocks_destroy(par);
error_unmap:
iounmap(info->screen_base);
error_fb_release:
framebuffer_release(info);
error_release_mem_region:
if (mem != res)
release_mem_region(mem->start, resource_size(mem));
return ret;
}
static void simplefb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
/* simplefb_destroy takes care of info cleanup */
unregister_framebuffer(info);
}
static const struct of_device_id simplefb_of_match[] = {
{ .compatible = "simple-framebuffer", },
{ },
};
MODULE_DEVICE_TABLE(of, simplefb_of_match);
static struct platform_driver simplefb_driver = {
.driver = {
.name = "simple-framebuffer",
.of_match_table = simplefb_of_match,
},
.probe = simplefb_probe,
.remove_new = simplefb_remove,
};
module_platform_driver(simplefb_driver);
MODULE_AUTHOR("Stephen Warren <[email protected]>");
MODULE_DESCRIPTION("Simple framebuffer driver");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/simplefb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Driver for Aeroflex Gaisler SVGACTRL framebuffer device.
*
* 2011 (c) Aeroflex Gaisler AB
*
* Full documentation of the core can be found here:
* https://www.gaisler.com/products/grlib/grip.pdf
*
* Contributors: Kristoffer Glembo <[email protected]>
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/io.h>
struct grvga_regs {
u32 status; /* 0x00 */
u32 video_length; /* 0x04 */
u32 front_porch; /* 0x08 */
u32 sync_length; /* 0x0C */
u32 line_length; /* 0x10 */
u32 fb_pos; /* 0x14 */
u32 clk_vector[4]; /* 0x18 */
u32 clut; /* 0x20 */
};
struct grvga_par {
struct grvga_regs *regs;
u32 color_palette[16]; /* 16 entry pseudo palette used by fbcon in true color mode */
int clk_sel;
int fb_alloced; /* = 1 if framebuffer is allocated in main memory */
};
static const struct fb_videomode grvga_modedb[] = {
{
/* 640x480 @ 60 Hz */
NULL, 60, 640, 480, 40000, 48, 16, 39, 11, 96, 2,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 60 Hz */
NULL, 60, 800, 600, 25000, 88, 40, 23, 1, 128, 4,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 72 Hz */
NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 60 Hz */
NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED
}
};
static const struct fb_fix_screeninfo grvga_fix = {
.id = "AG SVGACTRL",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
static int grvga_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct grvga_par *par = info->par;
int i;
if (!var->xres)
var->xres = 1;
if (!var->yres)
var->yres = 1;
if (var->bits_per_pixel <= 8)
var->bits_per_pixel = 8;
else if (var->bits_per_pixel <= 16)
var->bits_per_pixel = 16;
else if (var->bits_per_pixel <= 24)
var->bits_per_pixel = 24;
else if (var->bits_per_pixel <= 32)
var->bits_per_pixel = 32;
else
return -EINVAL;
var->xres_virtual = var->xres;
var->yres_virtual = 2*var->yres;
if (info->fix.smem_len) {
if ((var->yres_virtual*var->xres_virtual*var->bits_per_pixel/8) > info->fix.smem_len)
return -ENOMEM;
}
/* Which clocks that are available can be read out in these registers */
for (i = 0; i <= 3 ; i++) {
if (var->pixclock == par->regs->clk_vector[i])
break;
}
if (i <= 3)
par->clk_sel = i;
else
return -EINVAL;
switch (info->var.bits_per_pixel) {
case 8:
var->red = (struct fb_bitfield) {0, 8, 0}; /* offset, length, msb-right */
var->green = (struct fb_bitfield) {0, 8, 0};
var->blue = (struct fb_bitfield) {0, 8, 0};
var->transp = (struct fb_bitfield) {0, 0, 0};
break;
case 16:
var->red = (struct fb_bitfield) {11, 5, 0};
var->green = (struct fb_bitfield) {5, 6, 0};
var->blue = (struct fb_bitfield) {0, 5, 0};
var->transp = (struct fb_bitfield) {0, 0, 0};
break;
case 24:
case 32:
var->red = (struct fb_bitfield) {16, 8, 0};
var->green = (struct fb_bitfield) {8, 8, 0};
var->blue = (struct fb_bitfield) {0, 8, 0};
var->transp = (struct fb_bitfield) {24, 8, 0};
break;
default:
return -EINVAL;
}
return 0;
}
static int grvga_set_par(struct fb_info *info)
{
u32 func = 0;
struct grvga_par *par = info->par;
__raw_writel(((info->var.yres - 1) << 16) | (info->var.xres - 1),
&par->regs->video_length);
__raw_writel((info->var.lower_margin << 16) | (info->var.right_margin),
&par->regs->front_porch);
__raw_writel((info->var.vsync_len << 16) | (info->var.hsync_len),
&par->regs->sync_length);
__raw_writel(((info->var.yres + info->var.lower_margin + info->var.upper_margin + info->var.vsync_len - 1) << 16) |
(info->var.xres + info->var.right_margin + info->var.left_margin + info->var.hsync_len - 1),
&par->regs->line_length);
switch (info->var.bits_per_pixel) {
case 8:
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
func = 1;
break;
case 16:
info->fix.visual = FB_VISUAL_TRUECOLOR;
func = 2;
break;
case 24:
case 32:
info->fix.visual = FB_VISUAL_TRUECOLOR;
func = 3;
break;
default:
return -EINVAL;
}
__raw_writel((par->clk_sel << 6) | (func << 4) | 1,
&par->regs->status);
info->fix.line_length = (info->var.xres_virtual*info->var.bits_per_pixel)/8;
return 0;
}
static int grvga_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info)
{
struct grvga_par *par;
par = info->par;
if (regno >= 256) /* Size of CLUT */
return -EINVAL;
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
transp = CNVT_TOHW(transp, info->var.transp.length);
#undef CNVT_TOHW
/* In PSEUDOCOLOR we use the hardware CLUT */
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
__raw_writel((regno << 24) | (red << 16) | (green << 8) | blue,
&par->regs->clut);
/* Truecolor uses the pseudo palette */
else if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 v;
if (regno >= 16)
return -EINVAL;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
((u32 *) (info->pseudo_palette))[regno] = v;
}
return 0;
}
static int grvga_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct grvga_par *par = info->par;
struct fb_fix_screeninfo *fix = &info->fix;
u32 base_addr;
if (var->xoffset != 0)
return -EINVAL;
base_addr = fix->smem_start + (var->yoffset * fix->line_length);
base_addr &= ~3UL;
/* Set framebuffer base address */
__raw_writel(base_addr,
&par->regs->fb_pos);
return 0;
}
static const struct fb_ops grvga_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = grvga_check_var,
.fb_set_par = grvga_set_par,
.fb_setcolreg = grvga_setcolreg,
.fb_pan_display = grvga_pan_display,
};
static int grvga_parse_custom(char *options,
struct fb_var_screeninfo *screendata)
{
char *this_opt;
int count = 0;
if (!options || !*options)
return -1;
while ((this_opt = strsep(&options, " ")) != NULL) {
if (!*this_opt)
continue;
switch (count) {
case 0:
screendata->pixclock = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 1:
screendata->xres = screendata->xres_virtual = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 2:
screendata->right_margin = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 3:
screendata->hsync_len = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 4:
screendata->left_margin = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 5:
screendata->yres = screendata->yres_virtual = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 6:
screendata->lower_margin = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 7:
screendata->vsync_len = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 8:
screendata->upper_margin = simple_strtoul(this_opt, NULL, 0);
count++;
break;
case 9:
screendata->bits_per_pixel = simple_strtoul(this_opt, NULL, 0);
count++;
break;
default:
return -1;
}
}
screendata->activate = FB_ACTIVATE_NOW;
screendata->vmode = FB_VMODE_NONINTERLACED;
return 0;
}
static int grvga_probe(struct platform_device *dev)
{
struct fb_info *info;
int retval = -ENOMEM;
unsigned long virtual_start;
unsigned long grvga_fix_addr = 0;
unsigned long physical_start = 0;
unsigned long grvga_mem_size = 0;
struct grvga_par *par = NULL;
char *options = NULL, *mode_opt = NULL;
info = framebuffer_alloc(sizeof(struct grvga_par), &dev->dev);
if (!info)
return -ENOMEM;
/* Expecting: "grvga: modestring, [addr:<framebuffer physical address>], [size:<framebuffer size>]
*
* If modestring is custom:<custom mode string> we parse the string which then contains all videoparameters
* If address is left out, we allocate memory,
* if size is left out we only allocate enough to support the given mode.
*/
if (fb_get_options("grvga", &options)) {
retval = -ENODEV;
goto free_fb;
}
if (!options || !*options)
options = "640x480-8@60";
while (1) {
char *this_opt = strsep(&options, ",");
if (!this_opt)
break;
if (!strncmp(this_opt, "custom", 6)) {
if (grvga_parse_custom(this_opt, &info->var) < 0) {
dev_err(&dev->dev, "Failed to parse custom mode (%s).\n", this_opt);
retval = -EINVAL;
goto free_fb;
}
} else if (!strncmp(this_opt, "addr", 4))
grvga_fix_addr = simple_strtoul(this_opt + 5, NULL, 16);
else if (!strncmp(this_opt, "size", 4))
grvga_mem_size = simple_strtoul(this_opt + 5, NULL, 0);
else
mode_opt = this_opt;
}
par = info->par;
info->fbops = &grvga_ops;
info->fix = grvga_fix;
info->pseudo_palette = par->color_palette;
info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
info->fix.smem_len = grvga_mem_size;
if (!devm_request_mem_region(&dev->dev, dev->resource[0].start,
resource_size(&dev->resource[0]), "grlib-svgactrl regs")) {
dev_err(&dev->dev, "registers already mapped\n");
retval = -EBUSY;
goto free_fb;
}
par->regs = of_ioremap(&dev->resource[0], 0,
resource_size(&dev->resource[0]),
"grlib-svgactrl regs");
if (!par->regs) {
dev_err(&dev->dev, "failed to map registers\n");
retval = -ENOMEM;
goto free_fb;
}
retval = fb_alloc_cmap(&info->cmap, 256, 0);
if (retval < 0) {
dev_err(&dev->dev, "failed to allocate mem with fb_alloc_cmap\n");
retval = -ENOMEM;
goto unmap_regs;
}
if (mode_opt) {
retval = fb_find_mode(&info->var, info, mode_opt,
grvga_modedb, sizeof(grvga_modedb), &grvga_modedb[0], 8);
if (!retval || retval == 4) {
retval = -EINVAL;
goto dealloc_cmap;
}
}
if (!grvga_mem_size)
grvga_mem_size = info->var.xres_virtual * info->var.yres_virtual * info->var.bits_per_pixel/8;
if (grvga_fix_addr) {
/* Got framebuffer base address from argument list */
physical_start = grvga_fix_addr;
if (!devm_request_mem_region(&dev->dev, physical_start,
grvga_mem_size, dev->name)) {
dev_err(&dev->dev, "failed to request memory region\n");
retval = -ENOMEM;
goto dealloc_cmap;
}
virtual_start = (unsigned long) ioremap(physical_start, grvga_mem_size);
if (!virtual_start) {
dev_err(&dev->dev, "error mapping framebuffer memory\n");
retval = -ENOMEM;
goto dealloc_cmap;
}
} else { /* Allocate frambuffer memory */
unsigned long page;
virtual_start = (unsigned long) __get_free_pages(GFP_DMA,
get_order(grvga_mem_size));
if (!virtual_start) {
dev_err(&dev->dev,
"unable to allocate framebuffer memory (%lu bytes)\n",
grvga_mem_size);
retval = -ENOMEM;
goto dealloc_cmap;
}
physical_start = dma_map_single(&dev->dev, (void *)virtual_start, grvga_mem_size, DMA_TO_DEVICE);
/* Set page reserved so that mmap will work. This is necessary
* since we'll be remapping normal memory.
*/
for (page = virtual_start;
page < PAGE_ALIGN(virtual_start + grvga_mem_size);
page += PAGE_SIZE) {
SetPageReserved(virt_to_page(page));
}
par->fb_alloced = 1;
}
memset((unsigned long *) virtual_start, 0, grvga_mem_size);
info->screen_base = (char __iomem *) virtual_start;
info->fix.smem_start = physical_start;
info->fix.smem_len = grvga_mem_size;
dev_set_drvdata(&dev->dev, info);
dev_info(&dev->dev,
"Aeroflex Gaisler framebuffer device (fb%d), %dx%d-%d, using %luK of video memory @ %p\n",
info->node, info->var.xres, info->var.yres, info->var.bits_per_pixel,
grvga_mem_size >> 10, info->screen_base);
retval = register_framebuffer(info);
if (retval < 0) {
dev_err(&dev->dev, "failed to register framebuffer\n");
goto free_mem;
}
__raw_writel(physical_start, &par->regs->fb_pos);
__raw_writel(__raw_readl(&par->regs->status) | 1, /* Enable framebuffer */
&par->regs->status);
return 0;
free_mem:
if (grvga_fix_addr)
iounmap((void *)virtual_start);
else
kfree((void *)virtual_start);
dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
unmap_regs:
of_iounmap(&dev->resource[0], par->regs,
resource_size(&dev->resource[0]));
free_fb:
framebuffer_release(info);
return retval;
}
static void grvga_remove(struct platform_device *device)
{
struct fb_info *info = dev_get_drvdata(&device->dev);
struct grvga_par *par;
if (info) {
par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
of_iounmap(&device->resource[0], par->regs,
resource_size(&device->resource[0]));
if (!par->fb_alloced)
iounmap(info->screen_base);
else
kfree((void *)info->screen_base);
framebuffer_release(info);
}
}
static struct of_device_id svgactrl_of_match[] = {
{
.name = "GAISLER_SVGACTRL",
},
{
.name = "01_063",
},
{},
};
MODULE_DEVICE_TABLE(of, svgactrl_of_match);
static struct platform_driver grvga_driver = {
.driver = {
.name = "grlib-svgactrl",
.of_match_table = svgactrl_of_match,
},
.probe = grvga_probe,
.remove_new = grvga_remove,
};
module_platform_driver(grvga_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Aeroflex Gaisler");
MODULE_DESCRIPTION("Aeroflex Gaisler framebuffer device driver");
| linux-master | drivers/video/fbdev/grvga.c |
// SPDX-License-Identifier: GPL-2.0-only
/* linux/drivers/video/s3c-fb.c
*
* Copyright 2008 Openmoko Inc.
* Copyright 2008-2010 Simtec Electronics
* Ben Dooks <[email protected]>
* http://armlinux.simtec.co.uk/
*
* Samsung SoC Framebuffer driver
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/video_s3c.h>
#include <video/samsung_fimd.h>
/* This driver will export a number of framebuffer interfaces depending
* on the configuration passed in via the platform data. Each fb instance
* maps to a hardware window. Currently there is no support for runtime
* setting of the alpha-blending functions that each window has, so only
* window 0 is actually useful.
*
* Window 0 is treated specially, it is used for the basis of the LCD
* output timings and as the control for the output power-down state.
*/
/* note, the previous use of <mach/regs-fb.h> to get platform specific data
* has been replaced by using the platform device name to pick the correct
* configuration data for the system.
*/
#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
#undef writel
#define writel(v, r) do { \
pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \
__raw_writel(v, r); \
} while (0)
#endif /* FB_S3C_DEBUG_REGWRITE */
/* irq_flags bits */
#define S3C_FB_VSYNC_IRQ_EN 0
#define VSYNC_TIMEOUT_MSEC 50
struct s3c_fb;
#define VALID_BPP(x) (1 << ((x) - 1))
#define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
#define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
#define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
#define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
#define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
/**
* struct s3c_fb_variant - fb variant information
* @is_2443: Set if S3C2443/S3C2416 style hardware.
* @nr_windows: The number of windows.
* @vidtcon: The base for the VIDTCONx registers
* @wincon: The base for the WINxCON registers.
* @winmap: The base for the WINxMAP registers.
* @keycon: The abse for the WxKEYCON registers.
* @buf_start: Offset of buffer start registers.
* @buf_size: Offset of buffer size registers.
* @buf_end: Offset of buffer end registers.
* @osd: The base for the OSD registers.
* @osd_stride: stride of osd
* @palette: Address of palette memory, or 0 if none.
* @has_prtcon: Set if has PRTCON register.
* @has_shadowcon: Set if has SHADOWCON register.
* @has_blendcon: Set if has BLENDCON register.
* @has_clksel: Set if VIDCON0 register has CLKSEL bit.
* @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits.
*/
struct s3c_fb_variant {
unsigned int is_2443:1;
unsigned short nr_windows;
unsigned int vidtcon;
unsigned short wincon;
unsigned short winmap;
unsigned short keycon;
unsigned short buf_start;
unsigned short buf_end;
unsigned short buf_size;
unsigned short osd;
unsigned short osd_stride;
unsigned short palette[S3C_FB_MAX_WIN];
unsigned int has_prtcon:1;
unsigned int has_shadowcon:1;
unsigned int has_blendcon:1;
unsigned int has_clksel:1;
unsigned int has_fixvclk:1;
};
/**
* struct s3c_fb_win_variant
* @has_osd_c: Set if has OSD C register.
* @has_osd_d: Set if has OSD D register.
* @has_osd_alpha: Set if can change alpha transparency for a window.
* @palette_sz: Size of palette in entries.
* @palette_16bpp: Set if palette is 16bits wide.
* @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
* register is located at the given offset from OSD_BASE.
* @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
*
* valid_bpp bit x is set if (x+1)BPP is supported.
*/
struct s3c_fb_win_variant {
unsigned int has_osd_c:1;
unsigned int has_osd_d:1;
unsigned int has_osd_alpha:1;
unsigned int palette_16bpp:1;
unsigned short osd_size_off;
unsigned short palette_sz;
u32 valid_bpp;
};
/**
* struct s3c_fb_driverdata - per-device type driver data for init time.
* @variant: The variant information for this driver.
* @win: The window information for each window.
*/
struct s3c_fb_driverdata {
struct s3c_fb_variant variant;
struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
};
/**
* struct s3c_fb_palette - palette information
* @r: Red bitfield.
* @g: Green bitfield.
* @b: Blue bitfield.
* @a: Alpha bitfield.
*/
struct s3c_fb_palette {
struct fb_bitfield r;
struct fb_bitfield g;
struct fb_bitfield b;
struct fb_bitfield a;
};
/**
* struct s3c_fb_win - per window private data for each framebuffer.
* @windata: The platform data supplied for the window configuration.
* @parent: The hardware that this window is part of.
* @fbinfo: Pointer pack to the framebuffer info for this window.
* @variant: The variant information for this window.
* @palette_buffer: Buffer/cache to hold palette entries.
* @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
* @index: The window number of this window.
* @palette: The bitfields for changing r/g/b into a hardware palette entry.
*/
struct s3c_fb_win {
struct s3c_fb_pd_win *windata;
struct s3c_fb *parent;
struct fb_info *fbinfo;
struct s3c_fb_palette palette;
struct s3c_fb_win_variant variant;
u32 *palette_buffer;
u32 pseudo_palette[16];
unsigned int index;
};
/**
* struct s3c_fb_vsync - vsync information
* @wait: a queue for processes waiting for vsync
* @count: vsync interrupt count
*/
struct s3c_fb_vsync {
wait_queue_head_t wait;
unsigned int count;
};
/**
* struct s3c_fb - overall hardware state of the hardware
* @slock: The spinlock protection for this data structure.
* @dev: The device that we bound to, for printing, etc.
* @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
* @lcd_clk: The clk (sclk) feeding pixclk.
* @regs: The mapped hardware registers.
* @variant: Variant information for this hardware.
* @enabled: A bitmask of enabled hardware windows.
* @output_on: Flag if the physical output is enabled.
* @pdata: The platform configuration data passed with the device.
* @windows: The hardware windows that have been claimed.
* @irq_no: IRQ line number
* @irq_flags: irq flags
* @vsync_info: VSYNC-related information (count, queues...)
*/
struct s3c_fb {
spinlock_t slock;
struct device *dev;
struct clk *bus_clk;
struct clk *lcd_clk;
void __iomem *regs;
struct s3c_fb_variant variant;
unsigned char enabled;
bool output_on;
struct s3c_fb_platdata *pdata;
struct s3c_fb_win *windows[S3C_FB_MAX_WIN];
int irq_no;
unsigned long irq_flags;
struct s3c_fb_vsync vsync_info;
};
/**
* s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
* @win: The device window.
* @bpp: The bit depth.
*/
static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
{
return win->variant.valid_bpp & VALID_BPP(bpp);
}
/**
* s3c_fb_check_var() - framebuffer layer request to verify a given mode.
* @var: The screen information to verify.
* @info: The framebuffer device.
*
* Framebuffer layer call to verify the given information and allow us to
* update various information depending on the hardware capabilities.
*/
static int s3c_fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct s3c_fb_win *win = info->par;
struct s3c_fb *sfb = win->parent;
dev_dbg(sfb->dev, "checking parameters\n");
var->xres_virtual = max(var->xres_virtual, var->xres);
var->yres_virtual = max(var->yres_virtual, var->yres);
if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
win->index, var->bits_per_pixel);
return -EINVAL;
}
/* always ensure these are zero, for drop through cases below */
var->transp.offset = 0;
var->transp.length = 0;
switch (var->bits_per_pixel) {
case 1:
case 2:
case 4:
case 8:
if (sfb->variant.palette[win->index] != 0) {
/* non palletised, A:1,R:2,G:3,B:2 mode */
var->red.offset = 5;
var->green.offset = 2;
var->blue.offset = 0;
var->red.length = 2;
var->green.length = 3;
var->blue.length = 2;
var->transp.offset = 7;
var->transp.length = 1;
} else {
var->red.offset = 0;
var->red.length = var->bits_per_pixel;
var->green = var->red;
var->blue = var->red;
}
break;
case 19:
/* 666 with one bit alpha/transparency */
var->transp.offset = 18;
var->transp.length = 1;
fallthrough;
case 18:
var->bits_per_pixel = 32;
/* 666 format */
var->red.offset = 12;
var->green.offset = 6;
var->blue.offset = 0;
var->red.length = 6;
var->green.length = 6;
var->blue.length = 6;
break;
case 16:
/* 16 bpp, 565 format */
var->red.offset = 11;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = 5;
var->green.length = 6;
var->blue.length = 5;
break;
case 32:
case 28:
case 25:
var->transp.length = var->bits_per_pixel - 24;
var->transp.offset = 24;
fallthrough;
case 24:
/* our 24bpp is unpacked, so 32bpp */
var->bits_per_pixel = 32;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
break;
default:
dev_err(sfb->dev, "invalid bpp\n");
return -EINVAL;
}
dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
return 0;
}
/**
* s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
* @sfb: The hardware state.
* @pixclk: The pixel clock wanted, in picoseconds.
*
* Given the specified pixel clock, work out the necessary divider to get
* close to the output frequency.
*/
static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
{
unsigned long clk;
unsigned long long tmp;
unsigned int result;
if (sfb->variant.has_clksel)
clk = clk_get_rate(sfb->bus_clk);
else
clk = clk_get_rate(sfb->lcd_clk);
tmp = (unsigned long long)clk;
tmp *= pixclk;
do_div(tmp, 1000000000UL);
result = (unsigned int)tmp / 1000;
dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
pixclk, clk, result, result ? clk / result : clk);
return result;
}
/**
* s3c_fb_align_word() - align pixel count to word boundary
* @bpp: The number of bits per pixel
* @pix: The value to be aligned.
*
* Align the given pixel count so that it will start on an 32bit word
* boundary.
*/
static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
{
int pix_per_word;
if (bpp > 16)
return pix;
pix_per_word = (8 * 32) / bpp;
return ALIGN(pix, pix_per_word);
}
/**
* vidosd_set_size() - set OSD size for a window
*
* @win: the window to set OSD size for
* @size: OSD size register value
*/
static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
{
struct s3c_fb *sfb = win->parent;
/* OSD can be set up if osd_size_off != 0 for this window */
if (win->variant.osd_size_off)
writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
+ win->variant.osd_size_off);
}
/**
* vidosd_set_alpha() - set alpha transparency for a window
*
* @win: the window to set OSD size for
* @alpha: alpha register value
*/
static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
{
struct s3c_fb *sfb = win->parent;
if (win->variant.has_osd_alpha)
writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
}
/**
* shadow_protect_win() - disable updating values from shadow registers at vsync
*
* @win: window to protect registers for
* @protect: 1 to protect (disable updates)
*/
static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
{
struct s3c_fb *sfb = win->parent;
u32 reg;
if (protect) {
if (sfb->variant.has_prtcon) {
writel(PRTCON_PROTECT, sfb->regs + PRTCON);
} else if (sfb->variant.has_shadowcon) {
reg = readl(sfb->regs + SHADOWCON);
writel(reg | SHADOWCON_WINx_PROTECT(win->index),
sfb->regs + SHADOWCON);
}
} else {
if (sfb->variant.has_prtcon) {
writel(0, sfb->regs + PRTCON);
} else if (sfb->variant.has_shadowcon) {
reg = readl(sfb->regs + SHADOWCON);
writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
sfb->regs + SHADOWCON);
}
}
}
/**
* s3c_fb_enable() - Set the state of the main LCD output
* @sfb: The main framebuffer state.
* @enable: The state to set.
*/
static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
{
u32 vidcon0 = readl(sfb->regs + VIDCON0);
if (enable && !sfb->output_on)
pm_runtime_get_sync(sfb->dev);
if (enable) {
vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
} else {
/* see the note in the framebuffer datasheet about
* why you cannot take both of these bits down at the
* same time. */
if (vidcon0 & VIDCON0_ENVID) {
vidcon0 |= VIDCON0_ENVID;
vidcon0 &= ~VIDCON0_ENVID_F;
}
}
writel(vidcon0, sfb->regs + VIDCON0);
if (!enable && sfb->output_on)
pm_runtime_put_sync(sfb->dev);
sfb->output_on = enable;
}
/**
* s3c_fb_set_par() - framebuffer request to set new framebuffer state.
* @info: The framebuffer to change.
*
* Framebuffer layer request to set a new mode for the specified framebuffer
*/
static int s3c_fb_set_par(struct fb_info *info)
{
struct fb_var_screeninfo *var = &info->var;
struct s3c_fb_win *win = info->par;
struct s3c_fb *sfb = win->parent;
void __iomem *regs = sfb->regs;
void __iomem *buf;
int win_no = win->index;
u32 alpha = 0;
u32 data;
u32 pagewidth;
dev_dbg(sfb->dev, "setting framebuffer parameters\n");
pm_runtime_get_sync(sfb->dev);
shadow_protect_win(win, 1);
switch (var->bits_per_pixel) {
case 32:
case 24:
case 16:
case 12:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 8:
if (win->variant.palette_sz >= 256)
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
else
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 1:
info->fix.visual = FB_VISUAL_MONO01;
break;
default:
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
}
info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
/* disable the window whilst we update it */
writel(0, regs + WINCON(win_no));
if (!sfb->output_on)
s3c_fb_enable(sfb, 1);
/* write the buffer address */
/* start and end registers stride is 8 */
buf = regs + win_no * 8;
writel(info->fix.smem_start, buf + sfb->variant.buf_start);
data = info->fix.smem_start + info->fix.line_length * var->yres;
writel(data, buf + sfb->variant.buf_end);
pagewidth = (var->xres * var->bits_per_pixel) >> 3;
data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) |
VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) |
VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth);
writel(data, regs + sfb->variant.buf_size + (win_no * 4));
/* write 'OSD' registers to control position of framebuffer */
data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) |
VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0);
writel(data, regs + VIDOSD_A(win_no, sfb->variant));
data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
var->xres - 1)) |
VIDOSDxB_BOTRIGHT_Y(var->yres - 1) |
VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel,
var->xres - 1)) |
VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1);
writel(data, regs + VIDOSD_B(win_no, sfb->variant));
data = var->xres * var->yres;
alpha = VIDISD14C_ALPHA1_R(0xf) |
VIDISD14C_ALPHA1_G(0xf) |
VIDISD14C_ALPHA1_B(0xf);
vidosd_set_alpha(win, alpha);
vidosd_set_size(win, data);
/* Enable DMA channel for this window */
if (sfb->variant.has_shadowcon) {
data = readl(sfb->regs + SHADOWCON);
data |= SHADOWCON_CHx_ENABLE(win_no);
writel(data, sfb->regs + SHADOWCON);
}
data = WINCONx_ENWIN;
sfb->enabled |= (1 << win->index);
/* note, since we have to round up the bits-per-pixel, we end up
* relying on the bitfield information for r/g/b/a to work out
* exactly which mode of operation is intended. */
switch (var->bits_per_pixel) {
case 1:
data |= WINCON0_BPPMODE_1BPP;
data |= WINCONx_BITSWP;
data |= WINCONx_BURSTLEN_4WORD;
break;
case 2:
data |= WINCON0_BPPMODE_2BPP;
data |= WINCONx_BITSWP;
data |= WINCONx_BURSTLEN_8WORD;
break;
case 4:
data |= WINCON0_BPPMODE_4BPP;
data |= WINCONx_BITSWP;
data |= WINCONx_BURSTLEN_8WORD;
break;
case 8:
if (var->transp.length != 0)
data |= WINCON1_BPPMODE_8BPP_1232;
else
data |= WINCON0_BPPMODE_8BPP_PALETTE;
data |= WINCONx_BURSTLEN_8WORD;
data |= WINCONx_BYTSWP;
break;
case 16:
if (var->transp.length != 0)
data |= WINCON1_BPPMODE_16BPP_A1555;
else
data |= WINCON0_BPPMODE_16BPP_565;
data |= WINCONx_HAWSWP;
data |= WINCONx_BURSTLEN_16WORD;
break;
case 24:
case 32:
if (var->red.length == 6) {
if (var->transp.length != 0)
data |= WINCON1_BPPMODE_19BPP_A1666;
else
data |= WINCON1_BPPMODE_18BPP_666;
} else if (var->transp.length == 1)
data |= WINCON1_BPPMODE_25BPP_A1888
| WINCON1_BLD_PIX;
else if ((var->transp.length == 4) ||
(var->transp.length == 8))
data |= WINCON1_BPPMODE_28BPP_A4888
| WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
else
data |= WINCON0_BPPMODE_24BPP_888;
data |= WINCONx_WSWP;
data |= WINCONx_BURSTLEN_16WORD;
break;
}
/* Enable the colour keying for the window below this one */
if (win_no > 0) {
u32 keycon0_data = 0, keycon1_data = 0;
void __iomem *keycon = regs + sfb->variant.keycon;
keycon0_data = ~(WxKEYCON0_KEYBL_EN |
WxKEYCON0_KEYEN_F |
WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
keycon1_data = WxKEYCON1_COLVAL(0xffffff);
keycon += (win_no - 1) * 8;
writel(keycon0_data, keycon + WKEYCON0);
writel(keycon1_data, keycon + WKEYCON1);
}
writel(data, regs + sfb->variant.wincon + (win_no * 4));
writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
/* Set alpha value width */
if (sfb->variant.has_blendcon) {
data = readl(sfb->regs + BLENDCON);
data &= ~BLENDCON_NEW_MASK;
if (var->transp.length > 4)
data |= BLENDCON_NEW_8BIT_ALPHA_VALUE;
else
data |= BLENDCON_NEW_4BIT_ALPHA_VALUE;
writel(data, sfb->regs + BLENDCON);
}
shadow_protect_win(win, 0);
pm_runtime_put_sync(sfb->dev);
return 0;
}
/**
* s3c_fb_update_palette() - set or schedule a palette update.
* @sfb: The hardware information.
* @win: The window being updated.
* @reg: The palette index being changed.
* @value: The computed palette value.
*
* Change the value of a palette register, either by directly writing to
* the palette (this requires the palette RAM to be disconnected from the
* hardware whilst this is in progress) or schedule the update for later.
*
* At the moment, since we have no VSYNC interrupt support, we simply set
* the palette entry directly.
*/
static void s3c_fb_update_palette(struct s3c_fb *sfb,
struct s3c_fb_win *win,
unsigned int reg,
u32 value)
{
void __iomem *palreg;
u32 palcon;
palreg = sfb->regs + sfb->variant.palette[win->index];
dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
__func__, win->index, reg, palreg, value);
win->palette_buffer[reg] = value;
palcon = readl(sfb->regs + WPALCON);
writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
if (win->variant.palette_16bpp)
writew(value, palreg + (reg * 2));
else
writel(value, palreg + (reg * 4));
writel(palcon, sfb->regs + WPALCON);
}
static inline unsigned int chan_to_field(unsigned int chan,
struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
/**
* s3c_fb_setcolreg() - framebuffer layer request to change palette.
* @regno: The palette index to change.
* @red: The red field for the palette data.
* @green: The green field for the palette data.
* @blue: The blue field for the palette data.
* @transp: The transparency (alpha) field for the palette data.
* @info: The framebuffer being changed.
*/
static int s3c_fb_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct s3c_fb_win *win = info->par;
struct s3c_fb *sfb = win->parent;
unsigned int val;
dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
__func__, win->index, regno, red, green, blue);
pm_runtime_get_sync(sfb->dev);
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
/* true-colour, use pseudo-palette */
if (regno < 16) {
u32 *pal = info->pseudo_palette;
val = chan_to_field(red, &info->var.red);
val |= chan_to_field(green, &info->var.green);
val |= chan_to_field(blue, &info->var.blue);
pal[regno] = val;
}
break;
case FB_VISUAL_PSEUDOCOLOR:
if (regno < win->variant.palette_sz) {
val = chan_to_field(red, &win->palette.r);
val |= chan_to_field(green, &win->palette.g);
val |= chan_to_field(blue, &win->palette.b);
s3c_fb_update_palette(sfb, win, regno, val);
}
break;
default:
pm_runtime_put_sync(sfb->dev);
return 1; /* unknown type */
}
pm_runtime_put_sync(sfb->dev);
return 0;
}
/**
* s3c_fb_blank() - blank or unblank the given window
* @blank_mode: The blank state from FB_BLANK_*
* @info: The framebuffer to blank.
*
* Framebuffer layer request to change the power state.
*/
static int s3c_fb_blank(int blank_mode, struct fb_info *info)
{
struct s3c_fb_win *win = info->par;
struct s3c_fb *sfb = win->parent;
unsigned int index = win->index;
u32 wincon;
u32 output_on = sfb->output_on;
dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
pm_runtime_get_sync(sfb->dev);
wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
switch (blank_mode) {
case FB_BLANK_POWERDOWN:
wincon &= ~WINCONx_ENWIN;
sfb->enabled &= ~(1 << index);
fallthrough; /* to FB_BLANK_NORMAL */
case FB_BLANK_NORMAL:
/* disable the DMA and display 0x0 (black) */
shadow_protect_win(win, 1);
writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
sfb->regs + sfb->variant.winmap + (index * 4));
shadow_protect_win(win, 0);
break;
case FB_BLANK_UNBLANK:
shadow_protect_win(win, 1);
writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
shadow_protect_win(win, 0);
wincon |= WINCONx_ENWIN;
sfb->enabled |= (1 << index);
break;
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
default:
pm_runtime_put_sync(sfb->dev);
return 1;
}
shadow_protect_win(win, 1);
writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
/* Check the enabled state to see if we need to be running the
* main LCD interface, as if there are no active windows then
* it is highly likely that we also do not need to output
* anything.
*/
s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
shadow_protect_win(win, 0);
pm_runtime_put_sync(sfb->dev);
return output_on == sfb->output_on;
}
/**
* s3c_fb_pan_display() - Pan the display.
*
* Note that the offsets can be written to the device at any time, as their
* values are latched at each vsync automatically. This also means that only
* the last call to this function will have any effect on next vsync, but
* there is no need to sleep waiting for it to prevent tearing.
*
* @var: The screen information to verify.
* @info: The framebuffer device.
*/
static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct s3c_fb_win *win = info->par;
struct s3c_fb *sfb = win->parent;
void __iomem *buf = sfb->regs + win->index * 8;
unsigned int start_boff, end_boff;
pm_runtime_get_sync(sfb->dev);
/* Offset in bytes to the start of the displayed area */
start_boff = var->yoffset * info->fix.line_length;
/* X offset depends on the current bpp */
if (info->var.bits_per_pixel >= 8) {
start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
} else {
switch (info->var.bits_per_pixel) {
case 4:
start_boff += var->xoffset >> 1;
break;
case 2:
start_boff += var->xoffset >> 2;
break;
case 1:
start_boff += var->xoffset >> 3;
break;
default:
dev_err(sfb->dev, "invalid bpp\n");
pm_runtime_put_sync(sfb->dev);
return -EINVAL;
}
}
/* Offset in bytes to the end of the displayed area */
end_boff = start_boff + info->var.yres * info->fix.line_length;
/* Temporarily turn off per-vsync update from shadow registers until
* both start and end addresses are updated to prevent corruption */
shadow_protect_win(win, 1);
writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
shadow_protect_win(win, 0);
pm_runtime_put_sync(sfb->dev);
return 0;
}
/**
* s3c_fb_enable_irq() - enable framebuffer interrupts
* @sfb: main hardware state
*/
static void s3c_fb_enable_irq(struct s3c_fb *sfb)
{
void __iomem *regs = sfb->regs;
u32 irq_ctrl_reg;
if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
/* IRQ disabled, enable it */
irq_ctrl_reg = readl(regs + VIDINTCON0);
irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
writel(irq_ctrl_reg, regs + VIDINTCON0);
}
}
/**
* s3c_fb_disable_irq() - disable framebuffer interrupts
* @sfb: main hardware state
*/
static void s3c_fb_disable_irq(struct s3c_fb *sfb)
{
void __iomem *regs = sfb->regs;
u32 irq_ctrl_reg;
if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
/* IRQ enabled, disable it */
irq_ctrl_reg = readl(regs + VIDINTCON0);
irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
writel(irq_ctrl_reg, regs + VIDINTCON0);
}
}
static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
{
struct s3c_fb *sfb = dev_id;
void __iomem *regs = sfb->regs;
u32 irq_sts_reg;
spin_lock(&sfb->slock);
irq_sts_reg = readl(regs + VIDINTCON1);
if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
/* VSYNC interrupt, accept it */
writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
sfb->vsync_info.count++;
wake_up_interruptible(&sfb->vsync_info.wait);
}
/* We only support waiting for VSYNC for now, so it's safe
* to always disable irqs here.
*/
s3c_fb_disable_irq(sfb);
spin_unlock(&sfb->slock);
return IRQ_HANDLED;
}
/**
* s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
* @sfb: main hardware state
* @crtc: head index.
*/
static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
{
unsigned long count;
int ret;
if (crtc != 0)
return -ENODEV;
pm_runtime_get_sync(sfb->dev);
count = sfb->vsync_info.count;
s3c_fb_enable_irq(sfb);
ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
count != sfb->vsync_info.count,
msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
pm_runtime_put_sync(sfb->dev);
if (ret == 0)
return -ETIMEDOUT;
return 0;
}
static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct s3c_fb_win *win = info->par;
struct s3c_fb *sfb = win->parent;
int ret;
u32 crtc;
switch (cmd) {
case FBIO_WAITFORVSYNC:
if (get_user(crtc, (u32 __user *)arg)) {
ret = -EFAULT;
break;
}
ret = s3c_fb_wait_for_vsync(sfb, crtc);
break;
default:
ret = -ENOTTY;
}
return ret;
}
static const struct fb_ops s3c_fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = s3c_fb_check_var,
.fb_set_par = s3c_fb_set_par,
.fb_blank = s3c_fb_blank,
.fb_setcolreg = s3c_fb_setcolreg,
.fb_pan_display = s3c_fb_pan_display,
.fb_ioctl = s3c_fb_ioctl,
};
/**
* s3c_fb_missing_pixclock() - calculates pixel clock
* @mode: The video mode to change.
*
* Calculate the pixel clock when none has been given through platform data.
*/
static void s3c_fb_missing_pixclock(struct fb_videomode *mode)
{
u64 pixclk = 1000000000000ULL;
u32 div;
div = mode->left_margin + mode->hsync_len + mode->right_margin +
mode->xres;
div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
mode->yres;
div *= mode->refresh ? : 60;
do_div(pixclk, div);
mode->pixclock = pixclk;
}
/**
* s3c_fb_alloc_memory() - allocate display memory for framebuffer window
* @sfb: The base resources for the hardware.
* @win: The window to initialise memory for.
*
* Allocate memory for the given framebuffer.
*/
static int s3c_fb_alloc_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
{
struct s3c_fb_pd_win *windata = win->windata;
unsigned int real_size, virt_size, size;
struct fb_info *fbi = win->fbinfo;
dma_addr_t map_dma;
dev_dbg(sfb->dev, "allocating memory for display\n");
real_size = windata->xres * windata->yres;
virt_size = windata->virtual_x * windata->virtual_y;
dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
real_size, windata->xres, windata->yres,
virt_size, windata->virtual_x, windata->virtual_y);
size = (real_size > virt_size) ? real_size : virt_size;
size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
size /= 8;
fbi->fix.smem_len = size;
size = PAGE_ALIGN(size);
dev_dbg(sfb->dev, "want %u bytes for window\n", size);
fbi->screen_buffer = dma_alloc_wc(sfb->dev, size, &map_dma, GFP_KERNEL);
if (!fbi->screen_buffer)
return -ENOMEM;
dev_dbg(sfb->dev, "mapped %x to %p\n",
(unsigned int)map_dma, fbi->screen_buffer);
memset(fbi->screen_buffer, 0x0, size);
fbi->fix.smem_start = map_dma;
return 0;
}
/**
* s3c_fb_free_memory() - free the display memory for the given window
* @sfb: The base resources for the hardware.
* @win: The window to free the display memory for.
*
* Free the display memory allocated by s3c_fb_alloc_memory().
*/
static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
{
struct fb_info *fbi = win->fbinfo;
if (fbi->screen_buffer)
dma_free_wc(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
fbi->screen_buffer, fbi->fix.smem_start);
}
/**
* s3c_fb_release_win() - release resources for a framebuffer window.
* @sfb: The base resources for the hardware.
* @win: The window to cleanup the resources for.
*
* Release the resources that where claimed for the hardware window,
* such as the framebuffer instance and any memory claimed for it.
*/
static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
{
u32 data;
if (win->fbinfo) {
if (sfb->variant.has_shadowcon) {
data = readl(sfb->regs + SHADOWCON);
data &= ~SHADOWCON_CHx_ENABLE(win->index);
data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
writel(data, sfb->regs + SHADOWCON);
}
unregister_framebuffer(win->fbinfo);
if (win->fbinfo->cmap.len)
fb_dealloc_cmap(&win->fbinfo->cmap);
s3c_fb_free_memory(sfb, win);
framebuffer_release(win->fbinfo);
}
}
/**
* s3c_fb_probe_win() - register an hardware window
* @sfb: The base resources for the hardware
* @win_no: The window number
* @variant: The variant information for this window.
* @res: Pointer to where to place the resultant window.
*
* Allocate and do the basic initialisation for one of the hardware's graphics
* windows.
*/
static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
struct s3c_fb_win_variant *variant,
struct s3c_fb_win **res)
{
struct fb_videomode initmode;
struct s3c_fb_pd_win *windata;
struct s3c_fb_win *win;
struct fb_info *fbinfo;
int palette_size;
int ret;
dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
init_waitqueue_head(&sfb->vsync_info.wait);
palette_size = variant->palette_sz * 4;
fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
palette_size * sizeof(u32), sfb->dev);
if (!fbinfo)
return -ENOMEM;
windata = sfb->pdata->win[win_no];
initmode = *sfb->pdata->vtiming;
WARN_ON(windata->max_bpp == 0);
WARN_ON(windata->xres == 0);
WARN_ON(windata->yres == 0);
win = fbinfo->par;
*res = win;
win->variant = *variant;
win->fbinfo = fbinfo;
win->parent = sfb;
win->windata = windata;
win->index = win_no;
win->palette_buffer = (u32 *)(win + 1);
ret = s3c_fb_alloc_memory(sfb, win);
if (ret) {
dev_err(sfb->dev, "failed to allocate display memory\n");
return ret;
}
/* setup the r/b/g positions for the window's palette */
if (win->variant.palette_16bpp) {
/* Set RGB 5:6:5 as default */
win->palette.r.offset = 11;
win->palette.r.length = 5;
win->palette.g.offset = 5;
win->palette.g.length = 6;
win->palette.b.offset = 0;
win->palette.b.length = 5;
} else {
/* Set 8bpp or 8bpp and 1bit alpha */
win->palette.r.offset = 16;
win->palette.r.length = 8;
win->palette.g.offset = 8;
win->palette.g.length = 8;
win->palette.b.offset = 0;
win->palette.b.length = 8;
}
/* setup the initial video mode from the window */
initmode.xres = windata->xres;
initmode.yres = windata->yres;
fb_videomode_to_var(&fbinfo->var, &initmode);
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
fbinfo->fix.accel = FB_ACCEL_NONE;
fbinfo->var.activate = FB_ACTIVATE_NOW;
fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
fbinfo->var.bits_per_pixel = windata->default_bpp;
fbinfo->fbops = &s3c_fb_ops;
fbinfo->pseudo_palette = &win->pseudo_palette;
/* prepare to actually start the framebuffer */
ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
if (ret < 0) {
dev_err(sfb->dev, "check_var failed on initial video params\n");
return ret;
}
/* create initial colour map */
ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
if (ret == 0)
fb_set_cmap(&fbinfo->cmap, fbinfo);
else
dev_err(sfb->dev, "failed to allocate fb cmap\n");
s3c_fb_set_par(fbinfo);
dev_dbg(sfb->dev, "about to register framebuffer\n");
/* run the check_var and set_par on our configuration. */
ret = register_framebuffer(fbinfo);
if (ret < 0) {
dev_err(sfb->dev, "failed to register framebuffer\n");
return ret;
}
dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
return 0;
}
/**
* s3c_fb_set_rgb_timing() - set video timing for rgb interface.
* @sfb: The base resources for the hardware.
*
* Set horizontal and vertical lcd rgb interface timing.
*/
static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
{
struct fb_videomode *vmode = sfb->pdata->vtiming;
void __iomem *regs = sfb->regs;
int clkdiv;
u32 data;
if (!vmode->pixclock)
s3c_fb_missing_pixclock(vmode);
clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
data = sfb->pdata->vidcon0;
data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
if (clkdiv > 1)
data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
else
data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
if (sfb->variant.is_2443)
data |= (1 << 5);
writel(data, regs + VIDCON0);
data = VIDTCON0_VBPD(vmode->upper_margin - 1) |
VIDTCON0_VFPD(vmode->lower_margin - 1) |
VIDTCON0_VSPW(vmode->vsync_len - 1);
writel(data, regs + sfb->variant.vidtcon);
data = VIDTCON1_HBPD(vmode->left_margin - 1) |
VIDTCON1_HFPD(vmode->right_margin - 1) |
VIDTCON1_HSPW(vmode->hsync_len - 1);
writel(data, regs + sfb->variant.vidtcon + 4);
data = VIDTCON2_LINEVAL(vmode->yres - 1) |
VIDTCON2_HOZVAL(vmode->xres - 1) |
VIDTCON2_LINEVAL_E(vmode->yres - 1) |
VIDTCON2_HOZVAL_E(vmode->xres - 1);
writel(data, regs + sfb->variant.vidtcon + 8);
}
/**
* s3c_fb_clear_win() - clear hardware window registers.
* @sfb: The base resources for the hardware.
* @win: The window to process.
*
* Reset the specific window registers to a known state.
*/
static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
{
void __iomem *regs = sfb->regs;
u32 reg;
writel(0, regs + sfb->variant.wincon + (win * 4));
writel(0, regs + VIDOSD_A(win, sfb->variant));
writel(0, regs + VIDOSD_B(win, sfb->variant));
writel(0, regs + VIDOSD_C(win, sfb->variant));
if (sfb->variant.has_shadowcon) {
reg = readl(sfb->regs + SHADOWCON);
reg &= ~(SHADOWCON_WINx_PROTECT(win) |
SHADOWCON_CHx_ENABLE(win) |
SHADOWCON_CHx_LOCAL_ENABLE(win));
writel(reg, sfb->regs + SHADOWCON);
}
}
static int s3c_fb_probe(struct platform_device *pdev)
{
const struct platform_device_id *platid;
struct s3c_fb_driverdata *fbdrv;
struct device *dev = &pdev->dev;
struct s3c_fb_platdata *pd;
struct s3c_fb *sfb;
int win;
int ret = 0;
u32 reg;
platid = platform_get_device_id(pdev);
fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
dev_err(dev, "too many windows, cannot attach\n");
return -EINVAL;
}
pd = dev_get_platdata(&pdev->dev);
if (!pd) {
dev_err(dev, "no platform data specified\n");
return -EINVAL;
}
sfb = devm_kzalloc(dev, sizeof(*sfb), GFP_KERNEL);
if (!sfb)
return -ENOMEM;
dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
sfb->dev = dev;
sfb->pdata = pd;
sfb->variant = fbdrv->variant;
spin_lock_init(&sfb->slock);
sfb->bus_clk = devm_clk_get(dev, "lcd");
if (IS_ERR(sfb->bus_clk))
return dev_err_probe(dev, PTR_ERR(sfb->bus_clk),
"failed to get bus clock\n");
clk_prepare_enable(sfb->bus_clk);
if (!sfb->variant.has_clksel) {
sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");
if (IS_ERR(sfb->lcd_clk)) {
ret = dev_err_probe(dev, PTR_ERR(sfb->lcd_clk),
"failed to get lcd clock\n");
goto err_bus_clk;
}
clk_prepare_enable(sfb->lcd_clk);
}
pm_runtime_enable(sfb->dev);
sfb->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sfb->regs)) {
ret = PTR_ERR(sfb->regs);
goto err_lcd_clk;
}
sfb->irq_no = platform_get_irq(pdev, 0);
if (sfb->irq_no < 0) {
ret = -ENOENT;
goto err_lcd_clk;
}
ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,
0, "s3c_fb", sfb);
if (ret) {
dev_err(dev, "irq request failed\n");
goto err_lcd_clk;
}
dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
platform_set_drvdata(pdev, sfb);
pm_runtime_get_sync(sfb->dev);
/* setup gpio and output polarity controls */
pd->setup_gpio();
writel(pd->vidcon1, sfb->regs + VIDCON1);
/* set video clock running at under-run */
if (sfb->variant.has_fixvclk) {
reg = readl(sfb->regs + VIDCON1);
reg &= ~VIDCON1_VCLK_MASK;
reg |= VIDCON1_VCLK_RUN;
writel(reg, sfb->regs + VIDCON1);
}
/* zero all windows before we do anything */
for (win = 0; win < fbdrv->variant.nr_windows; win++)
s3c_fb_clear_win(sfb, win);
/* initialise colour key controls */
for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
void __iomem *regs = sfb->regs + sfb->variant.keycon;
regs += (win * 8);
writel(0xffffff, regs + WKEYCON0);
writel(0xffffff, regs + WKEYCON1);
}
s3c_fb_set_rgb_timing(sfb);
/* we have the register setup, start allocating framebuffers */
for (win = 0; win < fbdrv->variant.nr_windows; win++) {
if (!pd->win[win])
continue;
ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
&sfb->windows[win]);
if (ret < 0) {
dev_err(dev, "failed to create window %d\n", win);
for (; win >= 0; win--)
s3c_fb_release_win(sfb, sfb->windows[win]);
goto err_pm_runtime;
}
}
platform_set_drvdata(pdev, sfb);
pm_runtime_put_sync(sfb->dev);
return 0;
err_pm_runtime:
pm_runtime_put_sync(sfb->dev);
err_lcd_clk:
pm_runtime_disable(sfb->dev);
if (!sfb->variant.has_clksel)
clk_disable_unprepare(sfb->lcd_clk);
err_bus_clk:
clk_disable_unprepare(sfb->bus_clk);
return ret;
}
/**
* s3c_fb_remove() - Cleanup on module finalisation
* @pdev: The platform device we are bound to.
*
* Shutdown and then release all the resources that the driver allocated
* on initialisation.
*/
static void s3c_fb_remove(struct platform_device *pdev)
{
struct s3c_fb *sfb = platform_get_drvdata(pdev);
int win;
pm_runtime_get_sync(sfb->dev);
for (win = 0; win < S3C_FB_MAX_WIN; win++)
if (sfb->windows[win])
s3c_fb_release_win(sfb, sfb->windows[win]);
if (!sfb->variant.has_clksel)
clk_disable_unprepare(sfb->lcd_clk);
clk_disable_unprepare(sfb->bus_clk);
pm_runtime_put_sync(sfb->dev);
pm_runtime_disable(sfb->dev);
}
#ifdef CONFIG_PM_SLEEP
static int s3c_fb_suspend(struct device *dev)
{
struct s3c_fb *sfb = dev_get_drvdata(dev);
struct s3c_fb_win *win;
int win_no;
pm_runtime_get_sync(sfb->dev);
for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
win = sfb->windows[win_no];
if (!win)
continue;
/* use the blank function to push into power-down */
s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
}
if (!sfb->variant.has_clksel)
clk_disable_unprepare(sfb->lcd_clk);
clk_disable_unprepare(sfb->bus_clk);
pm_runtime_put_sync(sfb->dev);
return 0;
}
static int s3c_fb_resume(struct device *dev)
{
struct s3c_fb *sfb = dev_get_drvdata(dev);
struct s3c_fb_platdata *pd = sfb->pdata;
struct s3c_fb_win *win;
int win_no;
u32 reg;
pm_runtime_get_sync(sfb->dev);
clk_prepare_enable(sfb->bus_clk);
if (!sfb->variant.has_clksel)
clk_prepare_enable(sfb->lcd_clk);
/* setup gpio and output polarity controls */
pd->setup_gpio();
writel(pd->vidcon1, sfb->regs + VIDCON1);
/* set video clock running at under-run */
if (sfb->variant.has_fixvclk) {
reg = readl(sfb->regs + VIDCON1);
reg &= ~VIDCON1_VCLK_MASK;
reg |= VIDCON1_VCLK_RUN;
writel(reg, sfb->regs + VIDCON1);
}
/* zero all windows before we do anything */
for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
s3c_fb_clear_win(sfb, win_no);
for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
void __iomem *regs = sfb->regs + sfb->variant.keycon;
win = sfb->windows[win_no];
if (!win)
continue;
shadow_protect_win(win, 1);
regs += (win_no * 8);
writel(0xffffff, regs + WKEYCON0);
writel(0xffffff, regs + WKEYCON1);
shadow_protect_win(win, 0);
}
s3c_fb_set_rgb_timing(sfb);
/* restore framebuffers */
for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
win = sfb->windows[win_no];
if (!win)
continue;
dev_dbg(dev, "resuming window %d\n", win_no);
s3c_fb_set_par(win->fbinfo);
}
pm_runtime_put_sync(sfb->dev);
return 0;
}
#endif
#ifdef CONFIG_PM
static int s3c_fb_runtime_suspend(struct device *dev)
{
struct s3c_fb *sfb = dev_get_drvdata(dev);
if (!sfb->variant.has_clksel)
clk_disable_unprepare(sfb->lcd_clk);
clk_disable_unprepare(sfb->bus_clk);
return 0;
}
static int s3c_fb_runtime_resume(struct device *dev)
{
struct s3c_fb *sfb = dev_get_drvdata(dev);
struct s3c_fb_platdata *pd = sfb->pdata;
clk_prepare_enable(sfb->bus_clk);
if (!sfb->variant.has_clksel)
clk_prepare_enable(sfb->lcd_clk);
/* setup gpio and output polarity controls */
pd->setup_gpio();
writel(pd->vidcon1, sfb->regs + VIDCON1);
return 0;
}
#endif
#define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
#define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
[0] = {
.has_osd_c = 1,
.osd_size_off = 0x8,
.palette_sz = 256,
.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
VALID_BPP(18) | VALID_BPP(24)),
},
[1] = {
.has_osd_c = 1,
.has_osd_d = 1,
.osd_size_off = 0xc,
.has_osd_alpha = 1,
.palette_sz = 256,
.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
VALID_BPP(18) | VALID_BPP(19) |
VALID_BPP(24) | VALID_BPP(25) |
VALID_BPP(28)),
},
[2] = {
.has_osd_c = 1,
.has_osd_d = 1,
.osd_size_off = 0xc,
.has_osd_alpha = 1,
.palette_sz = 16,
.palette_16bpp = 1,
.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
VALID_BPP(18) | VALID_BPP(19) |
VALID_BPP(24) | VALID_BPP(25) |
VALID_BPP(28)),
},
[3] = {
.has_osd_c = 1,
.has_osd_alpha = 1,
.palette_sz = 16,
.palette_16bpp = 1,
.valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
VALID_BPP(18) | VALID_BPP(19) |
VALID_BPP(24) | VALID_BPP(25) |
VALID_BPP(28)),
},
[4] = {
.has_osd_c = 1,
.has_osd_alpha = 1,
.palette_sz = 4,
.palette_16bpp = 1,
.valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
VALID_BPP(16) | VALID_BPP(18) |
VALID_BPP(19) | VALID_BPP(24) |
VALID_BPP(25) | VALID_BPP(28)),
},
};
static struct s3c_fb_driverdata s3c_fb_data_64xx = {
.variant = {
.nr_windows = 5,
.vidtcon = VIDTCON0,
.wincon = WINCON(0),
.winmap = WINxMAP(0),
.keycon = WKEYCON,
.osd = VIDOSD_BASE,
.osd_stride = 16,
.buf_start = VIDW_BUF_START(0),
.buf_size = VIDW_BUF_SIZE(0),
.buf_end = VIDW_BUF_END(0),
.palette = {
[0] = 0x400,
[1] = 0x800,
[2] = 0x300,
[3] = 0x320,
[4] = 0x340,
},
.has_prtcon = 1,
.has_clksel = 1,
},
.win[0] = &s3c_fb_data_64xx_wins[0],
.win[1] = &s3c_fb_data_64xx_wins[1],
.win[2] = &s3c_fb_data_64xx_wins[2],
.win[3] = &s3c_fb_data_64xx_wins[3],
.win[4] = &s3c_fb_data_64xx_wins[4],
};
/* S3C2443/S3C2416 style hardware */
static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
.variant = {
.nr_windows = 2,
.is_2443 = 1,
.vidtcon = 0x08,
.wincon = 0x14,
.winmap = 0xd0,
.keycon = 0xb0,
.osd = 0x28,
.osd_stride = 12,
.buf_start = 0x64,
.buf_size = 0x94,
.buf_end = 0x7c,
.palette = {
[0] = 0x400,
[1] = 0x800,
},
.has_clksel = 1,
},
.win[0] = &(struct s3c_fb_win_variant) {
.palette_sz = 256,
.valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
},
.win[1] = &(struct s3c_fb_win_variant) {
.has_osd_c = 1,
.has_osd_alpha = 1,
.palette_sz = 256,
.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
VALID_BPP(18) | VALID_BPP(19) |
VALID_BPP(24) | VALID_BPP(25) |
VALID_BPP(28)),
},
};
static const struct platform_device_id s3c_fb_driver_ids[] = {
{
.name = "s3c-fb",
.driver_data = (unsigned long)&s3c_fb_data_64xx,
}, {
.name = "s3c2443-fb",
.driver_data = (unsigned long)&s3c_fb_data_s3c2443,
},
{},
};
MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
static const struct dev_pm_ops s3cfb_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
NULL)
};
static struct platform_driver s3c_fb_driver = {
.probe = s3c_fb_probe,
.remove_new = s3c_fb_remove,
.id_table = s3c_fb_driver_ids,
.driver = {
.name = "s3c-fb",
.pm = &s3cfb_pm_ops,
},
};
module_platform_driver(s3c_fb_driver);
MODULE_AUTHOR("Ben Dooks <[email protected]>");
MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/s3c-fb.c |
/*
* linux/drivers/video/hitfb.c -- Hitachi LCD frame buffer device
*
* (C) 1999 Mihai Spatar
* (C) 2000 YAEGASHI Takeshi
* (C) 2003, 2004 Paul Mundt
* (C) 2003, 2004, 2006 Andriy Skulysh
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <asm/machvec.h>
#include <linux/uaccess.h>
#include <asm/io.h>
#include <asm/hd64461.h>
#include <cpu/dac.h>
#define WIDTH 640
static struct fb_var_screeninfo hitfb_var = {
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_fix_screeninfo hitfb_fix = {
.id = "Hitachi HD64461",
.type = FB_TYPE_PACKED_PIXELS,
.accel = FB_ACCEL_NONE,
};
static volatile void __iomem *hitfb_offset_to_addr(unsigned int offset)
{
return (__force volatile void __iomem *)(uintptr_t)offset;
}
static u16 hitfb_readw(unsigned int offset)
{
return fb_readw(hitfb_offset_to_addr(offset));
}
static void hitfb_writew(u16 value, unsigned int offset)
{
fb_writew(value, hitfb_offset_to_addr(offset));
}
static inline void hitfb_accel_wait(void)
{
while (hitfb_readw(HD64461_GRCFGR) & HD64461_GRCFGR_ACCSTATUS)
;
}
static inline void hitfb_accel_start(int truecolor)
{
if (truecolor) {
hitfb_writew(6, HD64461_GRCFGR);
} else {
hitfb_writew(7, HD64461_GRCFGR);
}
}
static inline void hitfb_accel_set_dest(int truecolor, u16 dx, u16 dy,
u16 width, u16 height)
{
u32 saddr = WIDTH * dy + dx;
if (truecolor)
saddr <<= 1;
hitfb_writew(width-1, HD64461_BBTDWR);
hitfb_writew(height-1, HD64461_BBTDHR);
hitfb_writew(saddr & 0xffff, HD64461_BBTDSARL);
hitfb_writew(saddr >> 16, HD64461_BBTDSARH);
}
static inline void hitfb_accel_bitblt(int truecolor, u16 sx, u16 sy, u16 dx,
u16 dy, u16 width, u16 height, u16 rop,
u32 mask_addr)
{
u32 saddr, daddr;
u32 maddr = 0;
height--;
width--;
hitfb_writew(rop, HD64461_BBTROPR);
if ((sy < dy) || ((sy == dy) && (sx <= dx))) {
saddr = WIDTH * (sy + height) + sx + width;
daddr = WIDTH * (dy + height) + dx + width;
if (mask_addr) {
if (truecolor)
maddr = ((width >> 3) + 1) * (height + 1) - 1;
else
maddr =
(((width >> 4) + 1) * (height + 1) - 1) * 2;
hitfb_writew((1 << 5) | 1, HD64461_BBTMDR);
} else
hitfb_writew(1, HD64461_BBTMDR);
} else {
saddr = WIDTH * sy + sx;
daddr = WIDTH * dy + dx;
if (mask_addr) {
hitfb_writew((1 << 5), HD64461_BBTMDR);
} else {
hitfb_writew(0, HD64461_BBTMDR);
}
}
if (truecolor) {
saddr <<= 1;
daddr <<= 1;
}
hitfb_writew(width, HD64461_BBTDWR);
hitfb_writew(height, HD64461_BBTDHR);
hitfb_writew(saddr & 0xffff, HD64461_BBTSSARL);
hitfb_writew(saddr >> 16, HD64461_BBTSSARH);
hitfb_writew(daddr & 0xffff, HD64461_BBTDSARL);
hitfb_writew(daddr >> 16, HD64461_BBTDSARH);
if (mask_addr) {
maddr += mask_addr;
hitfb_writew(maddr & 0xffff, HD64461_BBTMARL);
hitfb_writew(maddr >> 16, HD64461_BBTMARH);
}
hitfb_accel_start(truecolor);
}
static void hitfb_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
{
if (rect->rop != ROP_COPY)
cfb_fillrect(p, rect);
else {
hitfb_accel_wait();
hitfb_writew(0x00f0, HD64461_BBTROPR);
hitfb_writew(16, HD64461_BBTMDR);
if (p->var.bits_per_pixel == 16) {
hitfb_writew(((u32 *) (p->pseudo_palette))[rect->color],
HD64461_GRSCR);
hitfb_accel_set_dest(1, rect->dx, rect->dy, rect->width,
rect->height);
hitfb_accel_start(1);
} else {
hitfb_writew(rect->color, HD64461_GRSCR);
hitfb_accel_set_dest(0, rect->dx, rect->dy, rect->width,
rect->height);
hitfb_accel_start(0);
}
}
}
static void hitfb_copyarea(struct fb_info *p, const struct fb_copyarea *area)
{
hitfb_accel_wait();
hitfb_accel_bitblt(p->var.bits_per_pixel == 16, area->sx, area->sy,
area->dx, area->dy, area->width, area->height,
0x00cc, 0);
}
static int hitfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int xoffset = var->xoffset;
int yoffset = var->yoffset;
if (xoffset != 0)
return -EINVAL;
hitfb_writew((yoffset*info->fix.line_length)>>10, HD64461_LCDCBAR);
return 0;
}
static int hitfb_blank(int blank_mode, struct fb_info *info)
{
unsigned short v;
if (blank_mode) {
v = hitfb_readw(HD64461_LDR1);
v &= ~HD64461_LDR1_DON;
hitfb_writew(v, HD64461_LDR1);
v = hitfb_readw(HD64461_LCDCCR);
v |= HD64461_LCDCCR_MOFF;
hitfb_writew(v, HD64461_LCDCCR);
v = hitfb_readw(HD64461_STBCR);
v |= HD64461_STBCR_SLCDST;
hitfb_writew(v, HD64461_STBCR);
} else {
v = hitfb_readw(HD64461_STBCR);
v &= ~HD64461_STBCR_SLCDST;
hitfb_writew(v, HD64461_STBCR);
v = hitfb_readw(HD64461_LCDCCR);
v &= ~(HD64461_LCDCCR_MOFF | HD64461_LCDCCR_STREQ);
hitfb_writew(v, HD64461_LCDCCR);
do {
v = hitfb_readw(HD64461_LCDCCR);
} while(v&HD64461_LCDCCR_STBACK);
v = hitfb_readw(HD64461_LDR1);
v |= HD64461_LDR1_DON;
hitfb_writew(v, HD64461_LDR1);
}
return 0;
}
static int hitfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *info)
{
if (regno >= 256)
return 1;
switch (info->var.bits_per_pixel) {
case 8:
hitfb_writew(regno << 8, HD64461_CPTWAR);
hitfb_writew(red >> 10, HD64461_CPTWDR);
hitfb_writew(green >> 10, HD64461_CPTWDR);
hitfb_writew(blue >> 10, HD64461_CPTWDR);
break;
case 16:
if (regno >= 16)
return 1;
((u32 *) (info->pseudo_palette))[regno] =
((red & 0xf800)) |
((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
break;
}
return 0;
}
static int hitfb_sync(struct fb_info *info)
{
hitfb_accel_wait();
return 0;
}
static int hitfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
int maxy;
var->xres = info->var.xres;
var->xres_virtual = info->var.xres;
var->yres = info->var.yres;
if ((var->bits_per_pixel != 8) && (var->bits_per_pixel != 16))
var->bits_per_pixel = info->var.bits_per_pixel;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
maxy = info->fix.smem_len / var->xres;
if (var->bits_per_pixel == 16)
maxy /= 2;
if (var->yres_virtual > maxy)
var->yres_virtual = maxy;
var->xoffset = 0;
var->yoffset = 0;
switch (var->bits_per_pixel) {
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16: /* RGB 565 */
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
}
return 0;
}
static int hitfb_set_par(struct fb_info *info)
{
unsigned short ldr3;
switch (info->var.bits_per_pixel) {
case 8:
info->fix.line_length = info->var.xres;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.ypanstep = 16;
break;
case 16:
info->fix.line_length = info->var.xres*2;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.ypanstep = 8;
break;
}
hitfb_writew(info->fix.line_length, HD64461_LCDCLOR);
ldr3 = hitfb_readw(HD64461_LDR3);
ldr3 &= ~15;
ldr3 |= (info->var.bits_per_pixel == 8) ? 4 : 8;
hitfb_writew(ldr3, HD64461_LDR3);
return 0;
}
static const struct fb_ops hitfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = hitfb_check_var,
.fb_set_par = hitfb_set_par,
.fb_setcolreg = hitfb_setcolreg,
.fb_blank = hitfb_blank,
.fb_sync = hitfb_sync,
.fb_pan_display = hitfb_pan_display,
.fb_fillrect = hitfb_fillrect,
.fb_copyarea = hitfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static int hitfb_probe(struct platform_device *dev)
{
unsigned short lcdclor, ldr3, ldvndr;
struct fb_info *info;
int ret;
if (fb_get_options("hitfb", NULL))
return -ENODEV;
hitfb_fix.mmio_start = HD64461_IO_OFFSET(0x1000);
hitfb_fix.mmio_len = 0x1000;
hitfb_fix.smem_start = HD64461_IO_OFFSET(0x02000000);
hitfb_fix.smem_len = 512 * 1024;
lcdclor = hitfb_readw(HD64461_LCDCLOR);
ldvndr = hitfb_readw(HD64461_LDVNDR);
ldr3 = hitfb_readw(HD64461_LDR3);
switch (ldr3 & 15) {
default:
case 4:
hitfb_var.bits_per_pixel = 8;
hitfb_var.xres = lcdclor;
break;
case 8:
hitfb_var.bits_per_pixel = 16;
hitfb_var.xres = lcdclor / 2;
break;
}
hitfb_fix.line_length = lcdclor;
hitfb_fix.visual = (hitfb_var.bits_per_pixel == 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
hitfb_var.yres = ldvndr + 1;
hitfb_var.xres_virtual = hitfb_var.xres;
hitfb_var.yres_virtual = hitfb_fix.smem_len / lcdclor;
switch (hitfb_var.bits_per_pixel) {
case 8:
hitfb_var.red.offset = 0;
hitfb_var.red.length = 8;
hitfb_var.green.offset = 0;
hitfb_var.green.length = 8;
hitfb_var.blue.offset = 0;
hitfb_var.blue.length = 8;
hitfb_var.transp.offset = 0;
hitfb_var.transp.length = 0;
break;
case 16: /* RGB 565 */
hitfb_var.red.offset = 11;
hitfb_var.red.length = 5;
hitfb_var.green.offset = 5;
hitfb_var.green.length = 6;
hitfb_var.blue.offset = 0;
hitfb_var.blue.length = 5;
hitfb_var.transp.offset = 0;
hitfb_var.transp.length = 0;
break;
}
info = framebuffer_alloc(sizeof(u32) * 16, &dev->dev);
if (unlikely(!info))
return -ENOMEM;
info->fbops = &hitfb_ops;
info->var = hitfb_var;
info->fix = hitfb_fix;
info->pseudo_palette = info->par;
info->flags = FBINFO_HWACCEL_YPAN |
FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
info->screen_base = (char __iomem *)(uintptr_t)hitfb_fix.smem_start;
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (unlikely(ret < 0))
goto err_fb;
ret = register_framebuffer(info);
if (unlikely(ret < 0))
goto err;
platform_set_drvdata(dev, info);
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
err:
fb_dealloc_cmap(&info->cmap);
err_fb:
framebuffer_release(info);
return ret;
}
static void hitfb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
static int hitfb_suspend(struct device *dev)
{
u16 v;
hitfb_blank(1, NULL);
v = hitfb_readw(HD64461_STBCR);
v |= HD64461_STBCR_SLCKE_IST;
hitfb_writew(v, HD64461_STBCR);
return 0;
}
static int hitfb_resume(struct device *dev)
{
u16 v;
v = hitfb_readw(HD64461_STBCR);
v &= ~HD64461_STBCR_SLCKE_OST;
msleep(100);
v = hitfb_readw(HD64461_STBCR);
v &= ~HD64461_STBCR_SLCKE_IST;
hitfb_writew(v, HD64461_STBCR);
hitfb_blank(0, NULL);
return 0;
}
static const struct dev_pm_ops hitfb_dev_pm_ops = {
.suspend = hitfb_suspend,
.resume = hitfb_resume,
};
static struct platform_driver hitfb_driver = {
.probe = hitfb_probe,
.remove_new = hitfb_remove,
.driver = {
.name = "hitfb",
.pm = &hitfb_dev_pm_ops,
},
};
static struct platform_device hitfb_device = {
.name = "hitfb",
.id = -1,
};
static int __init hitfb_init(void)
{
int ret;
ret = platform_driver_register(&hitfb_driver);
if (!ret) {
ret = platform_device_register(&hitfb_device);
if (ret)
platform_driver_unregister(&hitfb_driver);
}
return ret;
}
static void __exit hitfb_exit(void)
{
platform_device_unregister(&hitfb_device);
platform_driver_unregister(&hitfb_driver);
}
module_init(hitfb_init);
module_exit(hitfb_exit);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/hitfb.c |
// SPDX-License-Identifier: GPL-2.0-only
/* leo.c: LEO frame buffer driver
*
* Copyright (C) 2003, 2006 David S. Miller ([email protected])
* Copyright (C) 1996-1999 Jakub Jelinek ([email protected])
* Copyright (C) 1997 Michal Rehacek ([email protected])
*
* Driver layout based loosely on tgafb.c, see that file for credits.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <asm/fbio.h>
#include "sbuslib.h"
/*
* Local functions.
*/
static int leo_setcolreg(unsigned, unsigned, unsigned, unsigned,
unsigned, struct fb_info *);
static int leo_blank(int, struct fb_info *);
static int leo_mmap(struct fb_info *, struct vm_area_struct *);
static int leo_ioctl(struct fb_info *, unsigned int, unsigned long);
static int leo_pan_display(struct fb_var_screeninfo *, struct fb_info *);
/*
* Frame buffer operations
*/
static const struct fb_ops leo_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = leo_setcolreg,
.fb_blank = leo_blank,
.fb_pan_display = leo_pan_display,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = leo_mmap,
.fb_ioctl = leo_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = sbusfb_compat_ioctl,
#endif
};
#define LEO_OFF_LC_SS0_KRN 0x00200000UL
#define LEO_OFF_LC_SS0_USR 0x00201000UL
#define LEO_OFF_LC_SS1_KRN 0x01200000UL
#define LEO_OFF_LC_SS1_USR 0x01201000UL
#define LEO_OFF_LD_SS0 0x00400000UL
#define LEO_OFF_LD_SS1 0x01400000UL
#define LEO_OFF_LD_GBL 0x00401000UL
#define LEO_OFF_LX_KRN 0x00600000UL
#define LEO_OFF_LX_CURSOR 0x00601000UL
#define LEO_OFF_SS0 0x00800000UL
#define LEO_OFF_SS1 0x01800000UL
#define LEO_OFF_UNK 0x00602000UL
#define LEO_OFF_UNK2 0x00000000UL
#define LEO_CUR_ENABLE 0x00000080
#define LEO_CUR_UPDATE 0x00000030
#define LEO_CUR_PROGRESS 0x00000006
#define LEO_CUR_UPDATECMAP 0x00000003
#define LEO_CUR_TYPE_MASK 0x00000000
#define LEO_CUR_TYPE_IMAGE 0x00000020
#define LEO_CUR_TYPE_CMAP 0x00000050
struct leo_cursor {
u8 xxx0[16];
u32 cur_type;
u32 cur_misc;
u32 cur_cursxy;
u32 cur_data;
};
#define LEO_KRN_TYPE_CLUT0 0x00001000
#define LEO_KRN_TYPE_CLUT1 0x00001001
#define LEO_KRN_TYPE_CLUT2 0x00001002
#define LEO_KRN_TYPE_WID 0x00001003
#define LEO_KRN_TYPE_UNK 0x00001006
#define LEO_KRN_TYPE_VIDEO 0x00002003
#define LEO_KRN_TYPE_CLUTDATA 0x00004000
#define LEO_KRN_CSR_ENABLE 0x00000008
#define LEO_KRN_CSR_PROGRESS 0x00000004
#define LEO_KRN_CSR_UNK 0x00000002
#define LEO_KRN_CSR_UNK2 0x00000001
struct leo_lx_krn {
u32 krn_type;
u32 krn_csr;
u32 krn_value;
};
struct leo_lc_ss0_krn {
u32 misc;
u8 xxx0[0x800-4];
u32 rev;
};
struct leo_lc_ss0_usr {
u32 csr;
u32 addrspace;
u32 fontmsk;
u32 fontt;
u32 extent;
u32 src;
u32 dst;
u32 copy;
u32 fill;
};
struct leo_lc_ss1_krn {
u8 unknown;
};
struct leo_lc_ss1_usr {
u8 unknown;
};
struct leo_ld_ss0 {
u8 xxx0[0xe00];
u32 csr;
u32 wid;
u32 wmask;
u32 widclip;
u32 vclipmin;
u32 vclipmax;
u32 pickmin; /* SS1 only */
u32 pickmax; /* SS1 only */
u32 fg;
u32 bg;
u32 src; /* Copy/Scroll (SS0 only) */
u32 dst; /* Copy/Scroll/Fill (SS0 only) */
u32 extent; /* Copy/Scroll/Fill size (SS0 only) */
u32 xxx1[3];
u32 setsem; /* SS1 only */
u32 clrsem; /* SS1 only */
u32 clrpick; /* SS1 only */
u32 clrdat; /* SS1 only */
u32 alpha; /* SS1 only */
u8 xxx2[0x2c];
u32 winbg;
u32 planemask;
u32 rop;
u32 z;
u32 dczf; /* SS1 only */
u32 dczb; /* SS1 only */
u32 dcs; /* SS1 only */
u32 dczs; /* SS1 only */
u32 pickfb; /* SS1 only */
u32 pickbb; /* SS1 only */
u32 dcfc; /* SS1 only */
u32 forcecol; /* SS1 only */
u32 door[8]; /* SS1 only */
u32 pick[5]; /* SS1 only */
};
#define LEO_SS1_MISC_ENABLE 0x00000001
#define LEO_SS1_MISC_STEREO 0x00000002
struct leo_ld_ss1 {
u8 xxx0[0xef4];
u32 ss1_misc;
};
struct leo_ld_gbl {
u8 unknown;
};
struct leo_par {
spinlock_t lock;
struct leo_lx_krn __iomem *lx_krn;
struct leo_lc_ss0_usr __iomem *lc_ss0_usr;
struct leo_ld_ss0 __iomem *ld_ss0;
struct leo_ld_ss1 __iomem *ld_ss1;
struct leo_cursor __iomem *cursor;
u32 extent;
u32 clut_data[256];
u32 flags;
#define LEO_FLAG_BLANKED 0x00000001
unsigned long which_io;
};
static void leo_wait(struct leo_lx_krn __iomem *lx_krn)
{
int i;
for (i = 0;
(sbus_readl(&lx_krn->krn_csr) & LEO_KRN_CSR_PROGRESS) &&
i < 300000;
i++)
udelay(1); /* Busy wait at most 0.3 sec */
return;
}
static void leo_switch_from_graph(struct fb_info *info)
{
struct leo_par *par = (struct leo_par *) info->par;
struct leo_ld_ss0 __iomem *ss = par->ld_ss0;
struct leo_cursor __iomem *cursor = par->cursor;
unsigned long flags;
u32 val;
spin_lock_irqsave(&par->lock, flags);
par->extent = ((info->var.xres - 1) |
((info->var.yres - 1) << 16));
sbus_writel(0xffffffff, &ss->wid);
sbus_writel(0xffff, &ss->wmask);
sbus_writel(0, &ss->vclipmin);
sbus_writel(par->extent, &ss->vclipmax);
sbus_writel(0, &ss->fg);
sbus_writel(0xff000000, &ss->planemask);
sbus_writel(0x310850, &ss->rop);
sbus_writel(0, &ss->widclip);
sbus_writel((info->var.xres-1) | ((info->var.yres-1) << 11),
&par->lc_ss0_usr->extent);
sbus_writel(4, &par->lc_ss0_usr->addrspace);
sbus_writel(0x80000000, &par->lc_ss0_usr->fill);
sbus_writel(0, &par->lc_ss0_usr->fontt);
do {
val = sbus_readl(&par->lc_ss0_usr->csr);
} while (val & 0x20000000);
/* setup screen buffer for cfb_* functions */
sbus_writel(1, &ss->wid);
sbus_writel(0x00ffffff, &ss->planemask);
sbus_writel(0x310b90, &ss->rop);
sbus_writel(0, &par->lc_ss0_usr->addrspace);
/* hide cursor */
sbus_writel(sbus_readl(&cursor->cur_misc) & ~LEO_CUR_ENABLE, &cursor->cur_misc);
spin_unlock_irqrestore(&par->lock, flags);
}
static int leo_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
/* We just use this to catch switches out of
* graphics mode.
*/
leo_switch_from_graph(info);
if (var->xoffset || var->yoffset || var->vmode)
return -EINVAL;
return 0;
}
/**
* leo_setcolreg - Optional function. Sets a color register.
* @regno: boolean, 0 copy local, 1 get_user() function
* @red: frame buffer colormap structure
* @green: The green value which can be up to 16 bits wide
* @blue: The blue value which can be up to 16 bits wide.
* @transp: If supported the alpha value which can be up to 16 bits wide.
* @info: frame buffer info structure
*/
static int leo_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct leo_par *par = (struct leo_par *) info->par;
struct leo_lx_krn __iomem *lx_krn = par->lx_krn;
unsigned long flags;
u32 val;
int i;
if (regno >= 256)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
par->clut_data[regno] = red | (green << 8) | (blue << 16);
spin_lock_irqsave(&par->lock, flags);
leo_wait(lx_krn);
sbus_writel(LEO_KRN_TYPE_CLUTDATA, &lx_krn->krn_type);
for (i = 0; i < 256; i++)
sbus_writel(par->clut_data[i], &lx_krn->krn_value);
sbus_writel(LEO_KRN_TYPE_CLUT0, &lx_krn->krn_type);
val = sbus_readl(&lx_krn->krn_csr);
val |= (LEO_KRN_CSR_UNK | LEO_KRN_CSR_UNK2);
sbus_writel(val, &lx_krn->krn_csr);
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
/**
* leo_blank - Optional function. Blanks the display.
* @blank: the blank mode we want.
* @info: frame buffer structure that represents a single frame buffer
*/
static int leo_blank(int blank, struct fb_info *info)
{
struct leo_par *par = (struct leo_par *) info->par;
struct leo_lx_krn __iomem *lx_krn = par->lx_krn;
unsigned long flags;
u32 val;
spin_lock_irqsave(&par->lock, flags);
switch (blank) {
case FB_BLANK_UNBLANK: /* Unblanking */
val = sbus_readl(&lx_krn->krn_csr);
val |= LEO_KRN_CSR_ENABLE;
sbus_writel(val, &lx_krn->krn_csr);
par->flags &= ~LEO_FLAG_BLANKED;
break;
case FB_BLANK_NORMAL: /* Normal blanking */
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
case FB_BLANK_POWERDOWN: /* Poweroff */
val = sbus_readl(&lx_krn->krn_csr);
val &= ~LEO_KRN_CSR_ENABLE;
sbus_writel(val, &lx_krn->krn_csr);
par->flags |= LEO_FLAG_BLANKED;
break;
}
spin_unlock_irqrestore(&par->lock, flags);
return 0;
}
static struct sbus_mmap_map leo_mmap_map[] = {
{
.voff = LEO_SS0_MAP,
.poff = LEO_OFF_SS0,
.size = 0x800000
},
{
.voff = LEO_LC_SS0_USR_MAP,
.poff = LEO_OFF_LC_SS0_USR,
.size = 0x1000
},
{
.voff = LEO_LD_SS0_MAP,
.poff = LEO_OFF_LD_SS0,
.size = 0x1000
},
{
.voff = LEO_LX_CURSOR_MAP,
.poff = LEO_OFF_LX_CURSOR,
.size = 0x1000
},
{
.voff = LEO_SS1_MAP,
.poff = LEO_OFF_SS1,
.size = 0x800000
},
{
.voff = LEO_LC_SS1_USR_MAP,
.poff = LEO_OFF_LC_SS1_USR,
.size = 0x1000
},
{
.voff = LEO_LD_SS1_MAP,
.poff = LEO_OFF_LD_SS1,
.size = 0x1000
},
{
.voff = LEO_UNK_MAP,
.poff = LEO_OFF_UNK,
.size = 0x1000
},
{
.voff = LEO_LX_KRN_MAP,
.poff = LEO_OFF_LX_KRN,
.size = 0x1000
},
{
.voff = LEO_LC_SS0_KRN_MAP,
.poff = LEO_OFF_LC_SS0_KRN,
.size = 0x1000
},
{
.voff = LEO_LC_SS1_KRN_MAP,
.poff = LEO_OFF_LC_SS1_KRN,
.size = 0x1000
},
{
.voff = LEO_LD_GBL_MAP,
.poff = LEO_OFF_LD_GBL,
.size = 0x1000
},
{
.voff = LEO_UNK2_MAP,
.poff = LEO_OFF_UNK2,
.size = 0x100000
},
{ .size = 0 }
};
static int leo_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct leo_par *par = (struct leo_par *)info->par;
return sbusfb_mmap_helper(leo_mmap_map,
info->fix.smem_start, info->fix.smem_len,
par->which_io, vma);
}
static int leo_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
return sbusfb_ioctl_helper(cmd, arg, info,
FBTYPE_SUNLEO, 32, info->fix.smem_len);
}
/*
* Initialisation
*/
static void
leo_init_fix(struct fb_info *info, struct device_node *dp)
{
snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = 8192;
info->fix.accel = FB_ACCEL_SUN_LEO;
}
static void leo_wid_put(struct fb_info *info, struct fb_wid_list *wl)
{
struct leo_par *par = (struct leo_par *) info->par;
struct leo_lx_krn __iomem *lx_krn = par->lx_krn;
struct fb_wid_item *wi;
unsigned long flags;
u32 val;
int i, j;
spin_lock_irqsave(&par->lock, flags);
leo_wait(lx_krn);
for (i = 0, wi = wl->wl_list; i < wl->wl_count; i++, wi++) {
switch (wi->wi_type) {
case FB_WID_DBL_8:
j = (wi->wi_index & 0xf) + 0x40;
break;
case FB_WID_DBL_24:
j = wi->wi_index & 0x3f;
break;
default:
continue;
}
sbus_writel(0x5800 + j, &lx_krn->krn_type);
sbus_writel(wi->wi_values[0], &lx_krn->krn_value);
}
sbus_writel(LEO_KRN_TYPE_WID, &lx_krn->krn_type);
val = sbus_readl(&lx_krn->krn_csr);
val |= (LEO_KRN_CSR_UNK | LEO_KRN_CSR_UNK2);
sbus_writel(val, &lx_krn->krn_csr);
spin_unlock_irqrestore(&par->lock, flags);
}
static void leo_init_wids(struct fb_info *info)
{
struct fb_wid_item wi;
struct fb_wid_list wl;
wl.wl_count = 1;
wl.wl_list = &wi;
wi.wi_type = FB_WID_DBL_8;
wi.wi_index = 0;
wi.wi_values [0] = 0x2c0;
leo_wid_put(info, &wl);
wi.wi_index = 1;
wi.wi_values [0] = 0x30;
leo_wid_put(info, &wl);
wi.wi_index = 2;
wi.wi_values [0] = 0x20;
leo_wid_put(info, &wl);
wi.wi_type = FB_WID_DBL_24;
wi.wi_index = 1;
wi.wi_values [0] = 0x30;
leo_wid_put(info, &wl);
}
static void leo_init_hw(struct fb_info *info)
{
struct leo_par *par = (struct leo_par *) info->par;
u32 val;
val = sbus_readl(&par->ld_ss1->ss1_misc);
val |= LEO_SS1_MISC_ENABLE;
sbus_writel(val, &par->ld_ss1->ss1_misc);
leo_switch_from_graph(info);
}
static void leo_fixup_var_rgb(struct fb_var_screeninfo *var)
{
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 16;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
}
static void leo_unmap_regs(struct platform_device *op, struct fb_info *info,
struct leo_par *par)
{
if (par->lc_ss0_usr)
of_iounmap(&op->resource[0], par->lc_ss0_usr, 0x1000);
if (par->ld_ss0)
of_iounmap(&op->resource[0], par->ld_ss0, 0x1000);
if (par->ld_ss1)
of_iounmap(&op->resource[0], par->ld_ss1, 0x1000);
if (par->lx_krn)
of_iounmap(&op->resource[0], par->lx_krn, 0x1000);
if (par->cursor)
of_iounmap(&op->resource[0],
par->cursor, sizeof(struct leo_cursor));
if (info->screen_base)
of_iounmap(&op->resource[0], info->screen_base, 0x800000);
}
static int leo_probe(struct platform_device *op)
{
struct device_node *dp = op->dev.of_node;
struct fb_info *info;
struct leo_par *par;
int linebytes, err;
info = framebuffer_alloc(sizeof(struct leo_par), &op->dev);
err = -ENOMEM;
if (!info)
goto out_err;
par = info->par;
spin_lock_init(&par->lock);
info->fix.smem_start = op->resource[0].start;
par->which_io = op->resource[0].flags & IORESOURCE_BITS;
sbusfb_fill_var(&info->var, dp, 32);
leo_fixup_var_rgb(&info->var);
linebytes = of_getintprop_default(dp, "linebytes",
info->var.xres);
info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
par->lc_ss0_usr =
of_ioremap(&op->resource[0], LEO_OFF_LC_SS0_USR,
0x1000, "leolc ss0usr");
par->ld_ss0 =
of_ioremap(&op->resource[0], LEO_OFF_LD_SS0,
0x1000, "leold ss0");
par->ld_ss1 =
of_ioremap(&op->resource[0], LEO_OFF_LD_SS1,
0x1000, "leold ss1");
par->lx_krn =
of_ioremap(&op->resource[0], LEO_OFF_LX_KRN,
0x1000, "leolx krn");
par->cursor =
of_ioremap(&op->resource[0], LEO_OFF_LX_CURSOR,
sizeof(struct leo_cursor), "leolx cursor");
info->screen_base =
of_ioremap(&op->resource[0], LEO_OFF_SS0,
0x800000, "leo ram");
if (!par->lc_ss0_usr ||
!par->ld_ss0 ||
!par->ld_ss1 ||
!par->lx_krn ||
!par->cursor ||
!info->screen_base)
goto out_unmap_regs;
info->fbops = &leo_ops;
info->pseudo_palette = par->clut_data;
leo_init_wids(info);
leo_init_hw(info);
leo_blank(FB_BLANK_UNBLANK, info);
if (fb_alloc_cmap(&info->cmap, 256, 0))
goto out_unmap_regs;
leo_init_fix(info, dp);
err = register_framebuffer(info);
if (err < 0)
goto out_dealloc_cmap;
dev_set_drvdata(&op->dev, info);
printk(KERN_INFO "%pOF: leo at %lx:%lx\n",
dp,
par->which_io, info->fix.smem_start);
return 0;
out_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
out_unmap_regs:
leo_unmap_regs(op, info, par);
framebuffer_release(info);
out_err:
return err;
}
static void leo_remove(struct platform_device *op)
{
struct fb_info *info = dev_get_drvdata(&op->dev);
struct leo_par *par = info->par;
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
leo_unmap_regs(op, info, par);
framebuffer_release(info);
}
static const struct of_device_id leo_match[] = {
{
.name = "SUNW,leo",
},
{},
};
MODULE_DEVICE_TABLE(of, leo_match);
static struct platform_driver leo_driver = {
.driver = {
.name = "leo",
.of_match_table = leo_match,
},
.probe = leo_probe,
.remove_new = leo_remove,
};
static int __init leo_init(void)
{
if (fb_get_options("leofb", NULL))
return -ENODEV;
return platform_driver_register(&leo_driver);
}
static void __exit leo_exit(void)
{
platform_driver_unregister(&leo_driver);
}
module_init(leo_init);
module_exit(leo_exit);
MODULE_DESCRIPTION("framebuffer driver for LEO chipsets");
MODULE_AUTHOR("David S. Miller <[email protected]>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/leo.c |
/* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D fb driver for sparc64 systems
*
* License: GPL
*
* Copyright (C) 2007 David S. Miller ([email protected])
*/
#include <linux/aperture.h>
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/of.h>
#include <asm/io.h>
/* XXX This device has a 'dev-comm' property which apparently is
* XXX a pointer into the openfirmware's address space which is
* XXX a shared area the kernel driver can use to keep OBP
* XXX informed about the current resolution setting. The idea
* XXX is that the kernel can change resolutions, and as long
* XXX as the values in the 'dev-comm' area are accurate then
* XXX OBP can still render text properly to the console.
* XXX
* XXX I'm still working out the layout of this and whether there
* XXX are any signatures we need to look for etc.
*/
struct e3d_info {
struct fb_info *info;
struct pci_dev *pdev;
spinlock_t lock;
char __iomem *fb_base;
unsigned long fb_base_phys;
unsigned long fb8_buf_diff;
unsigned long regs_base_phys;
void __iomem *ramdac;
struct device_node *of_node;
unsigned int width;
unsigned int height;
unsigned int depth;
unsigned int fb_size;
u32 fb_base_reg;
u32 fb8_0_off;
u32 fb8_1_off;
u32 pseudo_palette[16];
};
static int e3d_get_props(struct e3d_info *ep)
{
ep->width = of_getintprop_default(ep->of_node, "width", 0);
ep->height = of_getintprop_default(ep->of_node, "height", 0);
ep->depth = of_getintprop_default(ep->of_node, "depth", 8);
if (!ep->width || !ep->height) {
printk(KERN_ERR "e3d: Critical properties missing for %s\n",
pci_name(ep->pdev));
return -EINVAL;
}
return 0;
}
/* My XVR-500 comes up, at 1280x768 and a FB base register value of
* 0x04000000, the following video layout register values:
*
* RAMDAC_VID_WH 0x03ff04ff
* RAMDAC_VID_CFG 0x1a0b0088
* RAMDAC_VID_32FB_0 0x04000000
* RAMDAC_VID_32FB_1 0x04800000
* RAMDAC_VID_8FB_0 0x05000000
* RAMDAC_VID_8FB_1 0x05200000
* RAMDAC_VID_XXXFB 0x05400000
* RAMDAC_VID_YYYFB 0x05c00000
* RAMDAC_VID_ZZZFB 0x05e00000
*/
/* Video layout registers */
#define RAMDAC_VID_WH 0x00000070UL /* (height-1)<<16 | (width-1) */
#define RAMDAC_VID_CFG 0x00000074UL /* 0x1a000088|(linesz_log2<<16) */
#define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */
#define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */
#define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */
#define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */
#define RAMDAC_VID_XXXFB 0x00000088UL /* PCI base of XXX FB */
#define RAMDAC_VID_YYYFB 0x0000008cUL /* PCI base of YYY FB */
#define RAMDAC_VID_ZZZFB 0x00000090UL /* PCI base of ZZZ FB */
/* CLUT registers */
#define RAMDAC_INDEX 0x000000bcUL
#define RAMDAC_DATA 0x000000c0UL
static void e3d_clut_write(struct e3d_info *ep, int index, u32 val)
{
void __iomem *ramdac = ep->ramdac;
unsigned long flags;
spin_lock_irqsave(&ep->lock, flags);
writel(index, ramdac + RAMDAC_INDEX);
writel(val, ramdac + RAMDAC_DATA);
spin_unlock_irqrestore(&ep->lock, flags);
}
static int e3d_setcolreg(unsigned regno,
unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct e3d_info *ep = info->par;
u32 red_8, green_8, blue_8;
u32 red_10, green_10, blue_10;
u32 value;
if (regno >= 256)
return 1;
red_8 = red >> 8;
green_8 = green >> 8;
blue_8 = blue >> 8;
value = (blue_8 << 24) | (green_8 << 16) | (red_8 << 8);
if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16)
((u32 *)info->pseudo_palette)[regno] = value;
red_10 = red >> 6;
green_10 = green >> 6;
blue_10 = blue >> 6;
value = (blue_10 << 20) | (green_10 << 10) | (red_10 << 0);
e3d_clut_write(ep, regno, value);
return 0;
}
/* XXX This is a bit of a hack. I can't figure out exactly how the
* XXX two 8bpp areas of the framebuffer work. I imagine there is
* XXX a WID attribute somewhere else in the framebuffer which tells
* XXX the ramdac which of the two 8bpp framebuffer regions to take
* XXX the pixel from. So, for now, render into both regions to make
* XXX sure the pixel shows up.
*/
static void e3d_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct e3d_info *ep = info->par;
unsigned long flags;
spin_lock_irqsave(&ep->lock, flags);
cfb_imageblit(info, image);
info->screen_base += ep->fb8_buf_diff;
cfb_imageblit(info, image);
info->screen_base -= ep->fb8_buf_diff;
spin_unlock_irqrestore(&ep->lock, flags);
}
static void e3d_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct e3d_info *ep = info->par;
unsigned long flags;
spin_lock_irqsave(&ep->lock, flags);
cfb_fillrect(info, rect);
info->screen_base += ep->fb8_buf_diff;
cfb_fillrect(info, rect);
info->screen_base -= ep->fb8_buf_diff;
spin_unlock_irqrestore(&ep->lock, flags);
}
static void e3d_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct e3d_info *ep = info->par;
unsigned long flags;
spin_lock_irqsave(&ep->lock, flags);
cfb_copyarea(info, area);
info->screen_base += ep->fb8_buf_diff;
cfb_copyarea(info, area);
info->screen_base -= ep->fb8_buf_diff;
spin_unlock_irqrestore(&ep->lock, flags);
}
static const struct fb_ops e3d_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = e3d_setcolreg,
.fb_fillrect = e3d_fillrect,
.fb_copyarea = e3d_copyarea,
.fb_imageblit = e3d_imageblit,
};
static int e3d_set_fbinfo(struct e3d_info *ep)
{
struct fb_info *info = ep->info;
struct fb_var_screeninfo *var = &info->var;
info->fbops = &e3d_ops;
info->screen_base = ep->fb_base;
info->screen_size = ep->fb_size;
info->pseudo_palette = ep->pseudo_palette;
/* Fill fix common fields */
strscpy(info->fix.id, "e3d", sizeof(info->fix.id));
info->fix.smem_start = ep->fb_base_phys;
info->fix.smem_len = ep->fb_size;
info->fix.type = FB_TYPE_PACKED_PIXELS;
if (ep->depth == 32 || ep->depth == 24)
info->fix.visual = FB_VISUAL_TRUECOLOR;
else
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
var->xres = ep->width;
var->yres = ep->height;
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->bits_per_pixel = ep->depth;
var->red.offset = 8;
var->red.length = 8;
var->green.offset = 16;
var->green.length = 8;
var->blue.offset = 24;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
if (fb_alloc_cmap(&info->cmap, 256, 0)) {
printk(KERN_ERR "e3d: Cannot allocate color map.\n");
return -ENOMEM;
}
return 0;
}
static int e3d_pci_register(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct device_node *of_node;
const char *device_type;
struct fb_info *info;
struct e3d_info *ep;
unsigned int line_length;
int err;
err = aperture_remove_conflicting_pci_devices(pdev, "e3dfb");
if (err)
return err;
of_node = pci_device_to_OF_node(pdev);
if (!of_node) {
printk(KERN_ERR "e3d: Cannot find OF node of %s\n",
pci_name(pdev));
return -ENODEV;
}
device_type = of_get_property(of_node, "device_type", NULL);
if (!device_type) {
printk(KERN_INFO "e3d: Ignoring secondary output device "
"at %s\n", pci_name(pdev));
return -ENODEV;
}
err = pci_enable_device(pdev);
if (err < 0) {
printk(KERN_ERR "e3d: Cannot enable PCI device %s\n",
pci_name(pdev));
goto err_out;
}
info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev);
if (!info) {
err = -ENOMEM;
goto err_disable;
}
ep = info->par;
ep->info = info;
ep->pdev = pdev;
spin_lock_init(&ep->lock);
ep->of_node = of_node;
/* Read the PCI base register of the frame buffer, which we
* need in order to interpret the RAMDAC_VID_*FB* values in
* the ramdac correctly.
*/
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
&ep->fb_base_reg);
ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK;
ep->regs_base_phys = pci_resource_start (pdev, 1);
err = pci_request_region(pdev, 1, "e3d regs");
if (err < 0) {
printk("e3d: Cannot request region 1 for %s\n",
pci_name(pdev));
goto err_release_fb;
}
ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000);
if (!ep->ramdac) {
err = -ENOMEM;
goto err_release_pci1;
}
ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0);
ep->fb8_0_off -= ep->fb_base_reg;
ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1);
ep->fb8_1_off -= ep->fb_base_reg;
ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off;
ep->fb_base_phys = pci_resource_start (pdev, 0);
ep->fb_base_phys += ep->fb8_0_off;
err = pci_request_region(pdev, 0, "e3d framebuffer");
if (err < 0) {
printk("e3d: Cannot request region 0 for %s\n",
pci_name(pdev));
goto err_unmap_ramdac;
}
err = e3d_get_props(ep);
if (err)
goto err_release_pci0;
line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff;
line_length = 1 << line_length;
switch (ep->depth) {
case 8:
info->fix.line_length = line_length;
break;
case 16:
info->fix.line_length = line_length * 2;
break;
case 24:
info->fix.line_length = line_length * 3;
break;
case 32:
info->fix.line_length = line_length * 4;
break;
}
ep->fb_size = info->fix.line_length * ep->height;
ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size);
if (!ep->fb_base) {
err = -ENOMEM;
goto err_release_pci0;
}
err = e3d_set_fbinfo(ep);
if (err)
goto err_unmap_fb;
pci_set_drvdata(pdev, info);
printk("e3d: Found device at %s\n", pci_name(pdev));
err = register_framebuffer(info);
if (err < 0) {
printk(KERN_ERR "e3d: Could not register framebuffer %s\n",
pci_name(pdev));
goto err_free_cmap;
}
return 0;
err_free_cmap:
fb_dealloc_cmap(&info->cmap);
err_unmap_fb:
iounmap(ep->fb_base);
err_release_pci0:
pci_release_region(pdev, 0);
err_unmap_ramdac:
iounmap(ep->ramdac);
err_release_pci1:
pci_release_region(pdev, 1);
err_release_fb:
framebuffer_release(info);
err_disable:
pci_disable_device(pdev);
err_out:
return err;
}
static const struct pci_device_id e3d_pci_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a0), },
{ PCI_DEVICE(0x1091, 0x7a0), },
{ PCI_DEVICE(PCI_VENDOR_ID_3DLABS, 0x7a2), },
{ .vendor = PCI_VENDOR_ID_3DLABS,
.device = PCI_ANY_ID,
.subvendor = PCI_VENDOR_ID_3DLABS,
.subdevice = 0x0108,
},
{ .vendor = PCI_VENDOR_ID_3DLABS,
.device = PCI_ANY_ID,
.subvendor = PCI_VENDOR_ID_3DLABS,
.subdevice = 0x0140,
},
{ .vendor = PCI_VENDOR_ID_3DLABS,
.device = PCI_ANY_ID,
.subvendor = PCI_VENDOR_ID_3DLABS,
.subdevice = 0x1024,
},
{ 0, }
};
static struct pci_driver e3d_driver = {
.driver = {
.suppress_bind_attrs = true,
},
.name = "e3d",
.id_table = e3d_pci_table,
.probe = e3d_pci_register,
};
static int __init e3d_init(void)
{
if (fb_modesetting_disabled("e3d"))
return -ENODEV;
if (fb_get_options("e3d", NULL))
return -ENODEV;
return pci_register_driver(&e3d_driver);
}
device_initcall(e3d_init);
| linux-master | drivers/video/fbdev/sunxvr500.c |
/*
* linux/drivers/video/atafb.c -- Atari builtin chipset frame buffer device
*
* Copyright (C) 1994 Martin Schaller & Roman Hodek
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* History:
* - 03 Jan 95: Original version by Martin Schaller: The TT driver and
* all the device independent stuff
* - 09 Jan 95: Roman: I've added the hardware abstraction (hw_switch)
* and wrote the Falcon, ST(E), and External drivers
* based on the original TT driver.
* - 07 May 95: Martin: Added colormap operations for the external driver
* - 21 May 95: Martin: Added support for overscan
* Andreas: some bug fixes for this
* - Jul 95: Guenther Kelleter <[email protected]>:
* Programmable Falcon video modes
* (thanks to Christian Cartus for documentation
* of VIDEL registers).
* - 27 Dec 95: Guenther: Implemented user definable video modes "user[0-7]"
* on minor 24...31. "user0" may be set on commandline by
* "R<x>;<y>;<depth>". (Makes sense only on Falcon)
* Video mode switch on Falcon now done at next VBL interrupt
* to avoid the annoying right shift of the screen.
* - 23 Sep 97: Juergen: added xres_virtual for cards like ProMST
* The external-part is legacy, therefore hardware-specific
* functions like panning/hardwarescrolling/blanking isn't
* supported.
* - 29 Sep 97: Juergen: added Romans suggestion for pan_display
* (var->xoffset was changed even if no set_screen_base avail.)
* - 05 Oct 97: Juergen: extfb (PACKED_PIXEL) is FB_PSEUDOCOLOR 'cause
* we know how to set the colors
* ext_*palette: read from ext_colors (former MV300_colors)
* write to ext_colors and RAMDAC
*
* To do:
* - For the Falcon it is not possible to set random video modes on
* SM124 and SC/TV, only the bootup resolution is supported.
*
*/
#define ATAFB_TT
#define ATAFB_STE
#define ATAFB_EXT
#define ATAFB_FALCON
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <asm/setup.h>
#include <linux/uaccess.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/atarihw.h>
#include <asm/atariints.h>
#include <asm/atari_stram.h>
#include <linux/fb.h>
#include <asm/atarikb.h>
#include "c2p.h"
#include "atafb.h"
#define SWITCH_ACIA 0x01 /* modes for switch on OverScan */
#define SWITCH_SND6 0x40
#define SWITCH_SND7 0x80
#define SWITCH_NONE 0x00
static int default_par; /* default resolution (0=none) */
static unsigned long default_mem_req;
static int hwscroll = -1;
static int use_hwscroll = 1;
static int sttt_xres = 640, st_yres = 400, tt_yres = 480;
static int sttt_xres_virtual = 640, sttt_yres_virtual = 400;
static int ovsc_offset, ovsc_addlen;
/*
* Hardware parameters for current mode
*/
static struct atafb_par {
void *screen_base;
int yres_virtual;
u_long next_line;
#if defined ATAFB_TT || defined ATAFB_STE
union {
struct {
int mode;
int sync;
} tt, st;
#endif
#ifdef ATAFB_FALCON
struct falcon_hw {
/* Here are fields for storing a video mode, as direct
* parameters for the hardware.
*/
short sync;
short line_width;
short line_offset;
short st_shift;
short f_shift;
short vid_control;
short vid_mode;
short xoffset;
short hht, hbb, hbe, hdb, hde, hss;
short vft, vbb, vbe, vdb, vde, vss;
/* auxiliary information */
short mono;
short ste_mode;
short bpp;
u32 pseudo_palette[16];
} falcon;
#endif
/* Nothing needed for external mode */
} hw;
} current_par;
/* Don't calculate an own resolution, and thus don't change the one found when
* booting (currently used for the Falcon to keep settings for internal video
* hardware extensions (e.g. ScreenBlaster) */
static int DontCalcRes = 0;
#ifdef ATAFB_FALCON
#define HHT hw.falcon.hht
#define HBB hw.falcon.hbb
#define HBE hw.falcon.hbe
#define HDB hw.falcon.hdb
#define HDE hw.falcon.hde
#define HSS hw.falcon.hss
#define VFT hw.falcon.vft
#define VBB hw.falcon.vbb
#define VBE hw.falcon.vbe
#define VDB hw.falcon.vdb
#define VDE hw.falcon.vde
#define VSS hw.falcon.vss
#define VCO_CLOCK25 0x04
#define VCO_CSYPOS 0x10
#define VCO_VSYPOS 0x20
#define VCO_HSYPOS 0x40
#define VCO_SHORTOFFS 0x100
#define VMO_DOUBLE 0x01
#define VMO_INTER 0x02
#define VMO_PREMASK 0x0c
#endif
static struct fb_info fb_info = {
.fix = {
.id = "Atari ",
.visual = FB_VISUAL_PSEUDOCOLOR,
.accel = FB_ACCEL_NONE,
}
};
static void *screen_base; /* base address of screen */
static unsigned long phys_screen_base; /* (only for Overscan) */
static int screen_len;
static int current_par_valid;
static int mono_moni;
#ifdef ATAFB_EXT
/* external video handling */
static unsigned int external_xres;
static unsigned int external_xres_virtual;
static unsigned int external_yres;
/*
* not needed - atafb will never support panning/hardwarescroll with external
* static unsigned int external_yres_virtual;
*/
static unsigned int external_depth;
static int external_pmode;
static void *external_screen_base;
static unsigned long external_addr;
static unsigned long external_len;
static unsigned long external_vgaiobase;
static unsigned int external_bitspercol = 6;
/*
* JOE <[email protected]>:
* added card type for external driver, is only needed for
* colormap handling.
*/
enum cardtype { IS_VGA, IS_MV300 };
static enum cardtype external_card_type = IS_VGA;
/*
* The MV300 mixes the color registers. So we need an array of munged
* indices in order to access the correct reg.
*/
static int MV300_reg_1bit[2] = {
0, 1
};
static int MV300_reg_4bit[16] = {
0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15
};
static int MV300_reg_8bit[256] = {
0, 128, 64, 192, 32, 160, 96, 224, 16, 144, 80, 208, 48, 176, 112, 240,
8, 136, 72, 200, 40, 168, 104, 232, 24, 152, 88, 216, 56, 184, 120, 248,
4, 132, 68, 196, 36, 164, 100, 228, 20, 148, 84, 212, 52, 180, 116, 244,
12, 140, 76, 204, 44, 172, 108, 236, 28, 156, 92, 220, 60, 188, 124, 252,
2, 130, 66, 194, 34, 162, 98, 226, 18, 146, 82, 210, 50, 178, 114, 242,
10, 138, 74, 202, 42, 170, 106, 234, 26, 154, 90, 218, 58, 186, 122, 250,
6, 134, 70, 198, 38, 166, 102, 230, 22, 150, 86, 214, 54, 182, 118, 246,
14, 142, 78, 206, 46, 174, 110, 238, 30, 158, 94, 222, 62, 190, 126, 254,
1, 129, 65, 193, 33, 161, 97, 225, 17, 145, 81, 209, 49, 177, 113, 241,
9, 137, 73, 201, 41, 169, 105, 233, 25, 153, 89, 217, 57, 185, 121, 249,
5, 133, 69, 197, 37, 165, 101, 229, 21, 149, 85, 213, 53, 181, 117, 245,
13, 141, 77, 205, 45, 173, 109, 237, 29, 157, 93, 221, 61, 189, 125, 253,
3, 131, 67, 195, 35, 163, 99, 227, 19, 147, 83, 211, 51, 179, 115, 243,
11, 139, 75, 203, 43, 171, 107, 235, 27, 155, 91, 219, 59, 187, 123, 251,
7, 135, 71, 199, 39, 167, 103, 231, 23, 151, 87, 215, 55, 183, 119, 247,
15, 143, 79, 207, 47, 175, 111, 239, 31, 159, 95, 223, 63, 191, 127, 255
};
static int *MV300_reg = MV300_reg_8bit;
#endif /* ATAFB_EXT */
/*
* struct fb_ops {
* * open/release and usage marking
* struct module *owner;
* int (*fb_open)(struct fb_info *info, int user);
* int (*fb_release)(struct fb_info *info, int user);
*
* * For framebuffers with strange non linear layouts or that do not
* * work with normal memory mapped access
* ssize_t (*fb_read)(struct file *file, char __user *buf, size_t count, loff_t *ppos);
* ssize_t (*fb_write)(struct file *file, const char __user *buf, size_t count, loff_t *ppos);
*
* * checks var and eventually tweaks it to something supported,
* * DOES NOT MODIFY PAR *
* int (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info);
*
* * set the video mode according to info->var *
* int (*fb_set_par)(struct fb_info *info);
*
* * set color register *
* int (*fb_setcolreg)(unsigned int regno, unsigned int red, unsigned int green,
* unsigned int blue, unsigned int transp, struct fb_info *info);
*
* * set color registers in batch *
* int (*fb_setcmap)(struct fb_cmap *cmap, struct fb_info *info);
*
* * blank display *
* int (*fb_blank)(int blank, struct fb_info *info);
*
* * pan display *
* int (*fb_pan_display)(struct fb_var_screeninfo *var, struct fb_info *info);
*
* *** The meat of the drawing engine ***
* * Draws a rectangle *
* void (*fb_fillrect) (struct fb_info *info, const struct fb_fillrect *rect);
* * Copy data from area to another *
* void (*fb_copyarea) (struct fb_info *info, const struct fb_copyarea *region);
* * Draws a image to the display *
* void (*fb_imageblit) (struct fb_info *info, const struct fb_image *image);
*
* * Draws cursor *
* int (*fb_cursor) (struct fb_info *info, struct fb_cursor *cursor);
*
* * wait for blit idle, optional *
* int (*fb_sync)(struct fb_info *info);
*
* * perform fb specific ioctl (optional) *
* int (*fb_ioctl)(struct fb_info *info, unsigned int cmd,
* unsigned long arg);
*
* * Handle 32bit compat ioctl (optional) *
* int (*fb_compat_ioctl)(struct fb_info *info, unsigned int cmd,
* unsigned long arg);
*
* * perform fb specific mmap *
* int (*fb_mmap)(struct fb_info *info, struct vm_area_struct *vma);
* } ;
*/
/* ++roman: This structure abstracts from the underlying hardware (ST(e),
* TT, or Falcon.
*
* int (*detect)(void)
* This function should detect the current video mode settings and
* store them in atafb_predefined[0] for later reference by the
* user. Return the index+1 of an equivalent predefined mode or 0
* if there is no such.
*
* int (*encode_fix)(struct fb_fix_screeninfo *fix,
* struct atafb_par *par)
* This function should fill in the 'fix' structure based on the
* values in the 'par' structure.
* !!! Obsolete, perhaps !!!
*
* int (*decode_var)(struct fb_var_screeninfo *var,
* struct atafb_par *par)
* Get the video params out of 'var'. If a value doesn't fit, round
* it up, if it's too big, return EINVAL.
* Round up in the following order: bits_per_pixel, xres, yres,
* xres_virtual, yres_virtual, xoffset, yoffset, grayscale, bitfields,
* horizontal timing, vertical timing.
*
* int (*encode_var)(struct fb_var_screeninfo *var,
* struct atafb_par *par);
* Fill the 'var' structure based on the values in 'par' and maybe
* other values read out of the hardware.
*
* void (*get_par)(struct atafb_par *par)
* Fill the hardware's 'par' structure.
* !!! Used only by detect() !!!
*
* void (*set_par)(struct atafb_par *par)
* Set the hardware according to 'par'.
*
* void (*set_screen_base)(void *s_base)
* Set the base address of the displayed frame buffer. Only called
* if yres_virtual > yres or xres_virtual > xres.
*
* int (*blank)(int blank_mode)
* Blank the screen if blank_mode != 0, else unblank. If blank == NULL then
* the caller blanks by setting the CLUT to all black. Return 0 if blanking
* succeeded, !=0 if un-/blanking failed due to e.g. a video mode which
* doesn't support it. Implements VESA suspend and powerdown modes on
* hardware that supports disabling hsync/vsync:
* blank_mode == 2: suspend vsync, 3:suspend hsync, 4: powerdown.
*/
static struct fb_hwswitch {
int (*detect)(void);
int (*encode_fix)(struct fb_fix_screeninfo *fix,
struct atafb_par *par);
int (*decode_var)(struct fb_var_screeninfo *var,
struct atafb_par *par);
int (*encode_var)(struct fb_var_screeninfo *var,
struct atafb_par *par);
void (*get_par)(struct atafb_par *par);
void (*set_par)(struct atafb_par *par);
void (*set_screen_base)(void *s_base);
int (*blank)(int blank_mode);
int (*pan_display)(struct fb_var_screeninfo *var,
struct fb_info *info);
} *fbhw;
static char *autodetect_names[] = { "autodetect", NULL };
static char *stlow_names[] = { "stlow", NULL };
static char *stmid_names[] = { "stmid", "default5", NULL };
static char *sthigh_names[] = { "sthigh", "default4", NULL };
static char *ttlow_names[] = { "ttlow", NULL };
static char *ttmid_names[] = { "ttmid", "default1", NULL };
static char *tthigh_names[] = { "tthigh", "default2", NULL };
static char *vga2_names[] = { "vga2", NULL };
static char *vga4_names[] = { "vga4", NULL };
static char *vga16_names[] = { "vga16", "default3", NULL };
static char *vga256_names[] = { "vga256", NULL };
static char *falh2_names[] = { "falh2", NULL };
static char *falh16_names[] = { "falh16", NULL };
static char **fb_var_names[] = {
autodetect_names,
stlow_names,
stmid_names,
sthigh_names,
ttlow_names,
ttmid_names,
tthigh_names,
vga2_names,
vga4_names,
vga16_names,
vga256_names,
falh2_names,
falh16_names,
NULL
};
static struct fb_var_screeninfo atafb_predefined[] = {
/*
* yres_virtual == 0 means use hw-scrolling if possible, else yres
*/
{ /* autodetect */
0, 0, 0, 0, 0, 0, 0, 0, /* xres-grayscale */
{0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, /* red green blue tran*/
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* st low */
320, 200, 320, 0, 0, 0, 4, 0,
{0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* st mid */
640, 200, 640, 0, 0, 0, 2, 0,
{0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* st high */
640, 400, 640, 0, 0, 0, 1, 0,
{0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* tt low */
320, 480, 320, 0, 0, 0, 8, 0,
{0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* tt mid */
640, 480, 640, 0, 0, 0, 4, 0,
{0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* tt high */
1280, 960, 1280, 0, 0, 0, 1, 0,
{0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* vga2 */
640, 480, 640, 0, 0, 0, 1, 0,
{0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* vga4 */
640, 480, 640, 0, 0, 0, 2, 0,
{0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* vga16 */
640, 480, 640, 0, 0, 0, 4, 0,
{0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* vga256 */
640, 480, 640, 0, 0, 0, 8, 0,
{0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* falh2 */
896, 608, 896, 0, 0, 0, 1, 0,
{0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ /* falh16 */
896, 608, 896, 0, 0, 0, 4, 0,
{0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0 },
};
static int num_atafb_predefined = ARRAY_SIZE(atafb_predefined);
static struct fb_videomode atafb_modedb[] __initdata = {
/*
* Atari Video Modes
*
* If you change these, make sure to update DEFMODE_* as well!
*/
/*
* ST/TT Video Modes
*/
{
/* 320x200, 15 kHz, 60 Hz (ST low) */
"st-low", 60, 320, 200, 32000, 32, 16, 31, 14, 96, 4,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x200, 15 kHz, 60 Hz (ST medium) */
"st-mid", 60, 640, 200, 32000, 32, 16, 31, 14, 96, 4,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x400, 30.25 kHz, 63.5 Hz (ST high) */
"st-high", 63, 640, 400, 32000, 128, 0, 40, 14, 128, 4,
0, FB_VMODE_NONINTERLACED
}, {
/* 320x480, 15 kHz, 60 Hz (TT low) */
"tt-low", 60, 320, 480, 31041, 120, 100, 8, 16, 140, 30,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480, 29 kHz, 57 Hz (TT medium) */
"tt-mid", 60, 640, 480, 31041, 120, 100, 8, 16, 140, 30,
0, FB_VMODE_NONINTERLACED
}, {
/* 1280x960, 72 kHz, 72 Hz (TT high) */
"tt-high", 72, 1280, 960, 7760, 260, 60, 36, 4, 192, 4,
0, FB_VMODE_NONINTERLACED
},
/*
* VGA Video Modes
*/
{
/* 640x480, 31 kHz, 60 Hz (VGA) */
"vga", 60, 640, 480, 39721, 42, 18, 31, 11, 100, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x400, 31 kHz, 70 Hz (VGA) */
"vga70", 70, 640, 400, 39721, 42, 18, 31, 11, 100, 3,
FB_SYNC_VERT_HIGH_ACT | FB_SYNC_COMP_HIGH_ACT, FB_VMODE_NONINTERLACED
},
/*
* Falcon HiRes Video Modes
*/
{
/* 896x608, 31 kHz, 60 Hz (Falcon High) */
"falh", 60, 896, 608, 32000, 18, 42, 31, 1, 96,3,
0, FB_VMODE_NONINTERLACED
},
};
#define NUM_TOTAL_MODES ARRAY_SIZE(atafb_modedb)
static char *mode_option __initdata = NULL;
/* default modes */
#define DEFMODE_TT 5 /* "tt-high" for TT */
#define DEFMODE_F30 7 /* "vga70" for Falcon */
#define DEFMODE_STE 2 /* "st-high" for ST/E */
#define DEFMODE_EXT 6 /* "vga" for external */
static int get_video_mode(char *vname)
{
char ***name_list;
char **name;
int i;
name_list = fb_var_names;
for (i = 0; i < num_atafb_predefined; i++) {
name = *name_list++;
if (!name || !*name)
break;
while (*name) {
if (!strcmp(vname, *name))
return i + 1;
name++;
}
}
return 0;
}
/* ------------------- TT specific functions ---------------------- */
#ifdef ATAFB_TT
static int tt_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par)
{
int mode;
strcpy(fix->id, "Atari Builtin");
fix->smem_start = phys_screen_base;
fix->smem_len = screen_len;
fix->type = FB_TYPE_INTERLEAVED_PLANES;
fix->type_aux = 2;
fix->visual = FB_VISUAL_PSEUDOCOLOR;
mode = par->hw.tt.mode & TT_SHIFTER_MODEMASK;
if (mode == TT_SHIFTER_TTHIGH || mode == TT_SHIFTER_STHIGH) {
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
if (mode == TT_SHIFTER_TTHIGH)
fix->visual = FB_VISUAL_MONO01;
}
fix->xpanstep = 0;
fix->ypanstep = 1;
fix->ywrapstep = 0;
fix->line_length = par->next_line;
fix->accel = FB_ACCEL_ATARIBLITT;
return 0;
}
static int tt_decode_var(struct fb_var_screeninfo *var, struct atafb_par *par)
{
int xres = var->xres;
int yres = var->yres;
int bpp = var->bits_per_pixel;
int linelen;
int yres_virtual = var->yres_virtual;
if (mono_moni) {
if (bpp > 1 || xres > sttt_xres * 2 || yres > tt_yres * 2)
return -EINVAL;
par->hw.tt.mode = TT_SHIFTER_TTHIGH;
xres = sttt_xres * 2;
yres = tt_yres * 2;
bpp = 1;
} else {
if (bpp > 8 || xres > sttt_xres || yres > tt_yres)
return -EINVAL;
if (bpp > 4) {
if (xres > sttt_xres / 2 || yres > tt_yres)
return -EINVAL;
par->hw.tt.mode = TT_SHIFTER_TTLOW;
xres = sttt_xres / 2;
yres = tt_yres;
bpp = 8;
} else if (bpp > 2) {
if (xres > sttt_xres || yres > tt_yres)
return -EINVAL;
if (xres > sttt_xres / 2 || yres > st_yres / 2) {
par->hw.tt.mode = TT_SHIFTER_TTMID;
xres = sttt_xres;
yres = tt_yres;
bpp = 4;
} else {
par->hw.tt.mode = TT_SHIFTER_STLOW;
xres = sttt_xres / 2;
yres = st_yres / 2;
bpp = 4;
}
} else if (bpp > 1) {
if (xres > sttt_xres || yres > st_yres / 2)
return -EINVAL;
par->hw.tt.mode = TT_SHIFTER_STMID;
xres = sttt_xres;
yres = st_yres / 2;
bpp = 2;
} else if (var->xres > sttt_xres || var->yres > st_yres) {
return -EINVAL;
} else {
par->hw.tt.mode = TT_SHIFTER_STHIGH;
xres = sttt_xres;
yres = st_yres;
bpp = 1;
}
}
if (yres_virtual <= 0)
yres_virtual = 0;
else if (yres_virtual < yres)
yres_virtual = yres;
if (var->sync & FB_SYNC_EXT)
par->hw.tt.sync = 0;
else
par->hw.tt.sync = 1;
linelen = xres * bpp / 8;
if (yres_virtual * linelen > screen_len && screen_len)
return -EINVAL;
if (yres * linelen > screen_len && screen_len)
return -EINVAL;
if (var->yoffset + yres > yres_virtual && yres_virtual)
return -EINVAL;
par->yres_virtual = yres_virtual;
par->screen_base = screen_base + var->yoffset * linelen;
par->next_line = linelen;
return 0;
}
static int tt_encode_var(struct fb_var_screeninfo *var, struct atafb_par *par)
{
int linelen;
memset(var, 0, sizeof(struct fb_var_screeninfo));
var->red.offset = 0;
var->red.length = 4;
var->red.msb_right = 0;
var->grayscale = 0;
var->pixclock = 31041;
var->left_margin = 120; /* these may be incorrect */
var->right_margin = 100;
var->upper_margin = 8;
var->lower_margin = 16;
var->hsync_len = 140;
var->vsync_len = 30;
var->height = -1;
var->width = -1;
if (par->hw.tt.sync & 1)
var->sync = 0;
else
var->sync = FB_SYNC_EXT;
switch (par->hw.tt.mode & TT_SHIFTER_MODEMASK) {
case TT_SHIFTER_STLOW:
var->xres = sttt_xres / 2;
var->xres_virtual = sttt_xres_virtual / 2;
var->yres = st_yres / 2;
var->bits_per_pixel = 4;
break;
case TT_SHIFTER_STMID:
var->xres = sttt_xres;
var->xres_virtual = sttt_xres_virtual;
var->yres = st_yres / 2;
var->bits_per_pixel = 2;
break;
case TT_SHIFTER_STHIGH:
var->xres = sttt_xres;
var->xres_virtual = sttt_xres_virtual;
var->yres = st_yres;
var->bits_per_pixel = 1;
break;
case TT_SHIFTER_TTLOW:
var->xres = sttt_xres / 2;
var->xres_virtual = sttt_xres_virtual / 2;
var->yres = tt_yres;
var->bits_per_pixel = 8;
break;
case TT_SHIFTER_TTMID:
var->xres = sttt_xres;
var->xres_virtual = sttt_xres_virtual;
var->yres = tt_yres;
var->bits_per_pixel = 4;
break;
case TT_SHIFTER_TTHIGH:
var->red.length = 0;
var->xres = sttt_xres * 2;
var->xres_virtual = sttt_xres_virtual * 2;
var->yres = tt_yres * 2;
var->bits_per_pixel = 1;
break;
}
var->blue = var->green = var->red;
var->transp.offset = 0;
var->transp.length = 0;
var->transp.msb_right = 0;
linelen = var->xres_virtual * var->bits_per_pixel / 8;
if (!use_hwscroll)
var->yres_virtual = var->yres;
else if (screen_len) {
if (par->yres_virtual)
var->yres_virtual = par->yres_virtual;
else
/* yres_virtual == 0 means use maximum */
var->yres_virtual = screen_len / linelen;
} else {
if (hwscroll < 0)
var->yres_virtual = 2 * var->yres;
else
var->yres_virtual = var->yres + hwscroll * 16;
}
var->xoffset = 0;
if (screen_base)
var->yoffset = (par->screen_base - screen_base) / linelen;
else
var->yoffset = 0;
var->nonstd = 0;
var->activate = 0;
var->vmode = FB_VMODE_NONINTERLACED;
return 0;
}
static void tt_get_par(struct atafb_par *par)
{
unsigned long addr;
par->hw.tt.mode = shifter_tt.tt_shiftmode;
par->hw.tt.sync = shifter_st.syncmode;
addr = ((shifter_st.bas_hi & 0xff) << 16) |
((shifter_st.bas_md & 0xff) << 8) |
((shifter_st.bas_lo & 0xff));
par->screen_base = atari_stram_to_virt(addr);
}
static void tt_set_par(struct atafb_par *par)
{
shifter_tt.tt_shiftmode = par->hw.tt.mode;
shifter_st.syncmode = par->hw.tt.sync;
/* only set screen_base if really necessary */
if (current_par.screen_base != par->screen_base)
fbhw->set_screen_base(par->screen_base);
}
static int tt_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
if ((shifter_tt.tt_shiftmode & TT_SHIFTER_MODEMASK) == TT_SHIFTER_STHIGH)
regno += 254;
if (regno > 255)
return 1;
tt_palette[regno] = (((red >> 12) << 8) | ((green >> 12) << 4) |
(blue >> 12));
if ((shifter_tt.tt_shiftmode & TT_SHIFTER_MODEMASK) ==
TT_SHIFTER_STHIGH && regno == 254)
tt_palette[0] = 0;
return 0;
}
static int tt_detect(void)
{
struct atafb_par par;
/* Determine the connected monitor: The DMA sound must be
* disabled before reading the MFP GPIP, because the Sound
* Done Signal and the Monochrome Detect are XORed together!
*
* Even on a TT, we should look if there is a DMA sound. It was
* announced that the Eagle is TT compatible, but only the PCM is
* missing...
*/
if (ATARIHW_PRESENT(PCM_8BIT)) {
tt_dmasnd.ctrl = DMASND_CTRL_OFF;
udelay(20); /* wait a while for things to settle down */
}
mono_moni = (st_mfp.par_dt_reg & 0x80) == 0;
tt_get_par(&par);
tt_encode_var(&atafb_predefined[0], &par);
return 1;
}
#endif /* ATAFB_TT */
/* ------------------- Falcon specific functions ---------------------- */
#ifdef ATAFB_FALCON
static int mon_type; /* Falcon connected monitor */
static int f030_bus_width; /* Falcon ram bus width (for vid_control) */
#define F_MON_SM 0
#define F_MON_SC 1
#define F_MON_VGA 2
#define F_MON_TV 3
static struct pixel_clock {
unsigned long f; /* f/[Hz] */
unsigned long t; /* t/[ps] (=1/f) */
int right, hsync, left; /* standard timing in clock cycles, not pixel */
/* hsync initialized in falcon_detect() */
int sync_mask; /* or-mask for hw.falcon.sync to set this clock */
int control_mask; /* ditto, for hw.falcon.vid_control */
} f25 = {
25175000, 39721, 18, 0, 42, 0x0, VCO_CLOCK25
}, f32 = {
32000000, 31250, 18, 0, 42, 0x0, 0
}, fext = {
0, 0, 18, 0, 42, 0x1, 0
};
/* VIDEL-prescale values [mon_type][pixel_length from VCO] */
static int vdl_prescale[4][3] = {
{ 4,2,1 }, { 4,2,1 }, { 4,2,2 }, { 4,2,1 }
};
/* Default hsync timing [mon_type] in picoseconds */
static long h_syncs[4] = { 3000000, 4875000, 4000000, 4875000 };
static inline int hxx_prescale(struct falcon_hw *hw)
{
return hw->ste_mode ? 16
: vdl_prescale[mon_type][hw->vid_mode >> 2 & 0x3];
}
static int falcon_encode_fix(struct fb_fix_screeninfo *fix,
struct atafb_par *par)
{
strcpy(fix->id, "Atari Builtin");
fix->smem_start = phys_screen_base;
fix->smem_len = screen_len;
fix->type = FB_TYPE_INTERLEAVED_PLANES;
fix->type_aux = 2;
fix->visual = FB_VISUAL_PSEUDOCOLOR;
fix->xpanstep = 1;
fix->ypanstep = 1;
fix->ywrapstep = 0;
if (par->hw.falcon.mono) {
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
/* no smooth scrolling with longword aligned video mem */
fix->xpanstep = 32;
} else if (par->hw.falcon.f_shift & 0x100) {
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
/* Is this ok or should it be DIRECTCOLOR? */
fix->visual = FB_VISUAL_TRUECOLOR;
fix->xpanstep = 2;
}
fix->line_length = par->next_line;
fix->accel = FB_ACCEL_ATARIBLITT;
return 0;
}
static int falcon_decode_var(struct fb_var_screeninfo *var,
struct atafb_par *par)
{
int bpp = var->bits_per_pixel;
int xres = var->xres;
int yres = var->yres;
int xres_virtual = var->xres_virtual;
int yres_virtual = var->yres_virtual;
int left_margin, right_margin, hsync_len;
int upper_margin, lower_margin, vsync_len;
int linelen;
int interlace = 0, doubleline = 0;
struct pixel_clock *pclock;
int plen; /* width of pixel in clock cycles */
int xstretch;
int prescale;
int longoffset = 0;
int hfreq, vfreq;
int hdb_off, hde_off, base_off;
int gstart, gend1, gend2, align;
/*
Get the video params out of 'var'. If a value doesn't fit, round
it up, if it's too big, return EINVAL.
Round up in the following order: bits_per_pixel, xres, yres,
xres_virtual, yres_virtual, xoffset, yoffset, grayscale, bitfields,
horizontal timing, vertical timing.
There is a maximum of screen resolution determined by pixelclock
and minimum frame rate -- (X+hmarg.)*(Y+vmarg.)*vfmin <= pixelclock.
In interlace mode this is " * " *vfmin <= pixelclock.
Additional constraints: hfreq.
Frequency range for multisync monitors is given via command line.
For TV and SM124 both frequencies are fixed.
X % 16 == 0 to fit 8x?? font (except 1 bitplane modes must use X%32 == 0)
Y % 16 == 0 to fit 8x16 font
Y % 8 == 0 if Y<400
Currently interlace and doubleline mode in var are ignored.
On SM124 and TV only the standard resolutions can be used.
*/
/* Reject uninitialized mode */
if (!xres || !yres || !bpp)
return -EINVAL;
if (mon_type == F_MON_SM && bpp != 1)
return -EINVAL;
if (bpp <= 1) {
bpp = 1;
par->hw.falcon.f_shift = 0x400;
par->hw.falcon.st_shift = 0x200;
} else if (bpp <= 2) {
bpp = 2;
par->hw.falcon.f_shift = 0x000;
par->hw.falcon.st_shift = 0x100;
} else if (bpp <= 4) {
bpp = 4;
par->hw.falcon.f_shift = 0x000;
par->hw.falcon.st_shift = 0x000;
} else if (bpp <= 8) {
bpp = 8;
par->hw.falcon.f_shift = 0x010;
} else if (bpp <= 16) {
bpp = 16; /* packed pixel mode */
par->hw.falcon.f_shift = 0x100; /* hicolor, no overlay */
} else
return -EINVAL;
par->hw.falcon.bpp = bpp;
if (mon_type == F_MON_SM || DontCalcRes) {
/* Skip all calculations. VGA/TV/SC1224 only supported. */
struct fb_var_screeninfo *myvar = &atafb_predefined[0];
if (bpp > myvar->bits_per_pixel ||
var->xres > myvar->xres ||
var->yres > myvar->yres)
return -EINVAL;
fbhw->get_par(par); /* Current par will be new par */
goto set_screen_base; /* Don't forget this */
}
/* Only some fixed resolutions < 640x400 */
if (xres <= 320)
xres = 320;
else if (xres <= 640 && bpp != 16)
xres = 640;
if (yres <= 200)
yres = 200;
else if (yres <= 240)
yres = 240;
else if (yres <= 400)
yres = 400;
/* 2 planes must use STE compatibility mode */
par->hw.falcon.ste_mode = bpp == 2;
par->hw.falcon.mono = bpp == 1;
/* Total and visible scanline length must be a multiple of one longword,
* this and the console fontwidth yields the alignment for xres and
* xres_virtual.
* TODO: this way "odd" fontheights are not supported
*
* Special case in STE mode: blank and graphic positions don't align,
* avoid trash at right margin
*/
if (par->hw.falcon.ste_mode)
xres = (xres + 63) & ~63;
else if (bpp == 1)
xres = (xres + 31) & ~31;
else
xres = (xres + 15) & ~15;
if (yres >= 400)
yres = (yres + 15) & ~15;
else
yres = (yres + 7) & ~7;
if (xres_virtual < xres)
xres_virtual = xres;
else if (bpp == 1)
xres_virtual = (xres_virtual + 31) & ~31;
else
xres_virtual = (xres_virtual + 15) & ~15;
if (yres_virtual <= 0)
yres_virtual = 0;
else if (yres_virtual < yres)
yres_virtual = yres;
par->hw.falcon.line_width = bpp * xres / 16;
par->hw.falcon.line_offset = bpp * (xres_virtual - xres) / 16;
/* single or double pixel width */
xstretch = (xres < 640) ? 2 : 1;
#if 0 /* SM124 supports only 640x400, this is rejected above */
if (mon_type == F_MON_SM) {
if (xres != 640 && yres != 400)
return -EINVAL;
plen = 1;
pclock = &f32;
/* SM124-mode is special */
par->hw.falcon.ste_mode = 1;
par->hw.falcon.f_shift = 0x000;
par->hw.falcon.st_shift = 0x200;
left_margin = hsync_len = 128 / plen;
right_margin = 0;
/* TODO set all margins */
} else
#endif
if (mon_type == F_MON_SC || mon_type == F_MON_TV) {
plen = 2 * xstretch;
if (var->pixclock > f32.t * plen)
return -EINVAL;
pclock = &f32;
if (yres > 240)
interlace = 1;
if (var->pixclock == 0) {
/* set some minimal margins which center the screen */
left_margin = 32;
right_margin = 18;
hsync_len = pclock->hsync / plen;
upper_margin = 31;
lower_margin = 14;
vsync_len = interlace ? 3 : 4;
} else {
left_margin = var->left_margin;
right_margin = var->right_margin;
hsync_len = var->hsync_len;
upper_margin = var->upper_margin;
lower_margin = var->lower_margin;
vsync_len = var->vsync_len;
if (var->vmode & FB_VMODE_INTERLACED) {
upper_margin = (upper_margin + 1) / 2;
lower_margin = (lower_margin + 1) / 2;
vsync_len = (vsync_len + 1) / 2;
} else if (var->vmode & FB_VMODE_DOUBLE) {
upper_margin *= 2;
lower_margin *= 2;
vsync_len *= 2;
}
}
} else { /* F_MON_VGA */
if (bpp == 16)
xstretch = 2; /* Double pixel width only for hicolor */
/* Default values are used for vert./hor. timing if no pixelclock given. */
if (var->pixclock == 0) {
/* Choose master pixelclock depending on hor. timing */
plen = 1 * xstretch;
if ((plen * xres + f25.right + f25.hsync + f25.left) *
fb_info.monspecs.hfmin < f25.f)
pclock = &f25;
else if ((plen * xres + f32.right + f32.hsync +
f32.left) * fb_info.monspecs.hfmin < f32.f)
pclock = &f32;
else if ((plen * xres + fext.right + fext.hsync +
fext.left) * fb_info.monspecs.hfmin < fext.f &&
fext.f)
pclock = &fext;
else
return -EINVAL;
left_margin = pclock->left / plen;
right_margin = pclock->right / plen;
hsync_len = pclock->hsync / plen;
upper_margin = 31;
lower_margin = 11;
vsync_len = 3;
} else {
/* Choose largest pixelclock <= wanted clock */
int i;
unsigned long pcl = ULONG_MAX;
pclock = 0;
for (i = 1; i <= 4; i *= 2) {
if (f25.t * i >= var->pixclock &&
f25.t * i < pcl) {
pcl = f25.t * i;
pclock = &f25;
}
if (f32.t * i >= var->pixclock &&
f32.t * i < pcl) {
pcl = f32.t * i;
pclock = &f32;
}
if (fext.t && fext.t * i >= var->pixclock &&
fext.t * i < pcl) {
pcl = fext.t * i;
pclock = &fext;
}
}
if (!pclock)
return -EINVAL;
plen = pcl / pclock->t;
left_margin = var->left_margin;
right_margin = var->right_margin;
hsync_len = var->hsync_len;
upper_margin = var->upper_margin;
lower_margin = var->lower_margin;
vsync_len = var->vsync_len;
/* Internal unit is [single lines per (half-)frame] */
if (var->vmode & FB_VMODE_INTERLACED) {
/* # lines in half frame */
/* External unit is [lines per full frame] */
upper_margin = (upper_margin + 1) / 2;
lower_margin = (lower_margin + 1) / 2;
vsync_len = (vsync_len + 1) / 2;
} else if (var->vmode & FB_VMODE_DOUBLE) {
/* External unit is [double lines per frame] */
upper_margin *= 2;
lower_margin *= 2;
vsync_len *= 2;
}
}
if (pclock == &fext)
longoffset = 1; /* VIDEL doesn't synchronize on short offset */
}
/* Is video bus bandwidth (32MB/s) too low for this resolution? */
/* this is definitely wrong if bus clock != 32MHz */
if (pclock->f / plen / 8 * bpp > 32000000L)
return -EINVAL;
if (vsync_len < 1)
vsync_len = 1;
/* include sync lengths in right/lower margin for all calculations */
right_margin += hsync_len;
lower_margin += vsync_len;
/* ! In all calculations of margins we use # of lines in half frame
* (which is a full frame in non-interlace mode), so we can switch
* between interlace and non-interlace without messing around
* with these.
*/
again:
/* Set base_offset 128 and video bus width */
par->hw.falcon.vid_control = mon_type | f030_bus_width;
if (!longoffset)
par->hw.falcon.vid_control |= VCO_SHORTOFFS; /* base_offset 64 */
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
par->hw.falcon.vid_control |= VCO_HSYPOS;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
par->hw.falcon.vid_control |= VCO_VSYPOS;
/* Pixelclock */
par->hw.falcon.vid_control |= pclock->control_mask;
/* External or internal clock */
par->hw.falcon.sync = pclock->sync_mask | 0x2;
/* Pixellength and prescale */
par->hw.falcon.vid_mode = (2 / plen) << 2;
if (doubleline)
par->hw.falcon.vid_mode |= VMO_DOUBLE;
if (interlace)
par->hw.falcon.vid_mode |= VMO_INTER;
/*********************
* Horizontal timing: unit = [master clock cycles]
* unit of hxx-registers: [master clock cycles * prescale]
* Hxx-registers are 9 bit wide
*
* 1 line = ((hht + 2) * 2 * prescale) clock cycles
*
* graphic output = hdb & 0x200 ?
* ((hht + 2) * 2 - hdb + hde) * prescale - hdboff + hdeoff:
* (hht + 2 - hdb + hde) * prescale - hdboff + hdeoff
* (this must be a multiple of plen*128/bpp, on VGA pixels
* to the right may be cut off with a bigger right margin)
*
* start of graphics relative to start of 1st halfline = hdb & 0x200 ?
* (hdb - hht - 2) * prescale + hdboff :
* hdb * prescale + hdboff
*
* end of graphics relative to start of 1st halfline =
* (hde + hht + 2) * prescale + hdeoff
*********************/
/* Calculate VIDEL registers */
{
prescale = hxx_prescale(&par->hw.falcon);
base_off = par->hw.falcon.vid_control & VCO_SHORTOFFS ? 64 : 128;
/* Offsets depend on video mode */
/* Offsets are in clock cycles, divide by prescale to
* calculate hd[be]-registers
*/
if (par->hw.falcon.f_shift & 0x100) {
align = 1;
hde_off = 0;
hdb_off = (base_off + 16 * plen) + prescale;
} else {
align = 128 / bpp;
hde_off = ((128 / bpp + 2) * plen);
if (par->hw.falcon.ste_mode)
hdb_off = (64 + base_off + (128 / bpp + 2) * plen) + prescale;
else
hdb_off = (base_off + (128 / bpp + 18) * plen) + prescale;
}
gstart = (prescale / 2 + plen * left_margin) / prescale;
/* gend1 is for hde (gend-gstart multiple of align), shifter's xres */
gend1 = gstart + roundup(xres, align) * plen / prescale;
/* gend2 is for hbb, visible xres (rest to gend1 is cut off by hblank) */
gend2 = gstart + xres * plen / prescale;
par->HHT = plen * (left_margin + xres + right_margin) /
(2 * prescale) - 2;
/* par->HHT = (gend2 + plen * right_margin / prescale) / 2 - 2;*/
par->HDB = gstart - hdb_off / prescale;
par->HBE = gstart;
if (par->HDB < 0)
par->HDB += par->HHT + 2 + 0x200;
par->HDE = gend1 - par->HHT - 2 - hde_off / prescale;
par->HBB = gend2 - par->HHT - 2;
#if 0
/* One more Videl constraint: data fetch of two lines must not overlap */
if ((par->HDB & 0x200) && (par->HDB & ~0x200) - par->HDE <= 5) {
/* if this happens increase margins, decrease hfreq. */
}
#endif
if (hde_off % prescale)
par->HBB++; /* compensate for non matching hde and hbb */
par->HSS = par->HHT + 2 - plen * hsync_len / prescale;
if (par->HSS < par->HBB)
par->HSS = par->HBB;
}
/* check hor. frequency */
hfreq = pclock->f / ((par->HHT + 2) * prescale * 2);
if (hfreq > fb_info.monspecs.hfmax && mon_type != F_MON_VGA) {
/* ++guenther: ^^^^^^^^^^^^^^^^^^^ can't remember why I did this */
/* Too high -> enlarge margin */
left_margin += 1;
right_margin += 1;
goto again;
}
if (hfreq > fb_info.monspecs.hfmax || hfreq < fb_info.monspecs.hfmin)
return -EINVAL;
/* Vxx-registers */
/* All Vxx must be odd in non-interlace, since frame starts in the middle
* of the first displayed line!
* One frame consists of VFT+1 half lines. VFT+1 must be even in
* non-interlace, odd in interlace mode for synchronisation.
* Vxx-registers are 11 bit wide
*/
par->VBE = (upper_margin * 2 + 1); /* must begin on odd halfline */
par->VDB = par->VBE;
par->VDE = yres;
if (!interlace)
par->VDE <<= 1;
if (doubleline)
par->VDE <<= 1; /* VDE now half lines per (half-)frame */
par->VDE += par->VDB;
par->VBB = par->VDE;
par->VFT = par->VBB + (lower_margin * 2 - 1) - 1;
par->VSS = par->VFT + 1 - (vsync_len * 2 - 1);
/* vbb,vss,vft must be even in interlace mode */
if (interlace) {
par->VBB++;
par->VSS++;
par->VFT++;
}
/* V-frequency check, hope I didn't create any loop here. */
/* Interlace and doubleline are mutually exclusive. */
vfreq = (hfreq * 2) / (par->VFT + 1);
if (vfreq > fb_info.monspecs.vfmax && !doubleline && !interlace) {
/* Too high -> try again with doubleline */
doubleline = 1;
goto again;
} else if (vfreq < fb_info.monspecs.vfmin && !interlace && !doubleline) {
/* Too low -> try again with interlace */
interlace = 1;
goto again;
} else if (vfreq < fb_info.monspecs.vfmin && doubleline) {
/* Doubleline too low -> clear doubleline and enlarge margins */
int lines;
doubleline = 0;
for (lines = 0;
(hfreq * 2) / (par->VFT + 1 + 4 * lines - 2 * yres) >
fb_info.monspecs.vfmax;
lines++)
;
upper_margin += lines;
lower_margin += lines;
goto again;
} else if (vfreq > fb_info.monspecs.vfmax && doubleline) {
/* Doubleline too high -> enlarge margins */
int lines;
for (lines = 0;
(hfreq * 2) / (par->VFT + 1 + 4 * lines) >
fb_info.monspecs.vfmax;
lines += 2)
;
upper_margin += lines;
lower_margin += lines;
goto again;
} else if (vfreq > fb_info.monspecs.vfmax && interlace) {
/* Interlace, too high -> enlarge margins */
int lines;
for (lines = 0;
(hfreq * 2) / (par->VFT + 1 + 4 * lines) >
fb_info.monspecs.vfmax;
lines++)
;
upper_margin += lines;
lower_margin += lines;
goto again;
} else if (vfreq < fb_info.monspecs.vfmin ||
vfreq > fb_info.monspecs.vfmax)
return -EINVAL;
set_screen_base:
linelen = xres_virtual * bpp / 8;
if (yres_virtual * linelen > screen_len && screen_len)
return -EINVAL;
if (yres * linelen > screen_len && screen_len)
return -EINVAL;
if (var->yoffset + yres > yres_virtual && yres_virtual)
return -EINVAL;
par->yres_virtual = yres_virtual;
par->screen_base = screen_base + var->yoffset * linelen;
par->hw.falcon.xoffset = 0;
par->next_line = linelen;
return 0;
}
static int falcon_encode_var(struct fb_var_screeninfo *var,
struct atafb_par *par)
{
/* !!! only for VGA !!! */
int linelen;
int prescale, plen;
int hdb_off, hde_off, base_off;
struct falcon_hw *hw = &par->hw.falcon;
memset(var, 0, sizeof(struct fb_var_screeninfo));
/* possible frequencies: 25.175 or 32MHz */
var->pixclock = hw->sync & 0x1 ? fext.t :
hw->vid_control & VCO_CLOCK25 ? f25.t : f32.t;
var->height = -1;
var->width = -1;
var->sync = 0;
if (hw->vid_control & VCO_HSYPOS)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (hw->vid_control & VCO_VSYPOS)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
var->vmode = FB_VMODE_NONINTERLACED;
if (hw->vid_mode & VMO_INTER)
var->vmode |= FB_VMODE_INTERLACED;
if (hw->vid_mode & VMO_DOUBLE)
var->vmode |= FB_VMODE_DOUBLE;
/* visible y resolution:
* Graphics display starts at line VDB and ends at line
* VDE. If interlace mode off unit of VC-registers is
* half lines, else lines.
*/
var->yres = hw->vde - hw->vdb;
if (!(var->vmode & FB_VMODE_INTERLACED))
var->yres >>= 1;
if (var->vmode & FB_VMODE_DOUBLE)
var->yres >>= 1;
/*
* to get bpp, we must examine f_shift and st_shift.
* f_shift is valid if any of bits no. 10, 8 or 4
* is set. Priority in f_shift is: 10 ">" 8 ">" 4, i.e.
* if bit 10 set then bit 8 and bit 4 don't care...
* If all these bits are 0 get display depth from st_shift
* (as for ST and STE)
*/
if (hw->f_shift & 0x400) /* 2 colors */
var->bits_per_pixel = 1;
else if (hw->f_shift & 0x100) /* hicolor */
var->bits_per_pixel = 16;
else if (hw->f_shift & 0x010) /* 8 bitplanes */
var->bits_per_pixel = 8;
else if (hw->st_shift == 0)
var->bits_per_pixel = 4;
else if (hw->st_shift == 0x100)
var->bits_per_pixel = 2;
else /* if (hw->st_shift == 0x200) */
var->bits_per_pixel = 1;
var->xres = hw->line_width * 16 / var->bits_per_pixel;
var->xres_virtual = var->xres + hw->line_offset * 16 / var->bits_per_pixel;
if (hw->xoffset)
var->xres_virtual += 16;
if (var->bits_per_pixel == 16) {
var->red.offset = 11;
var->red.length = 5;
var->red.msb_right = 0;
var->green.offset = 5;
var->green.length = 6;
var->green.msb_right = 0;
var->blue.offset = 0;
var->blue.length = 5;
var->blue.msb_right = 0;
} else {
var->red.offset = 0;
var->red.length = hw->ste_mode ? 4 : 6;
if (var->red.length > var->bits_per_pixel)
var->red.length = var->bits_per_pixel;
var->red.msb_right = 0;
var->grayscale = 0;
var->blue = var->green = var->red;
}
var->transp.offset = 0;
var->transp.length = 0;
var->transp.msb_right = 0;
linelen = var->xres_virtual * var->bits_per_pixel / 8;
if (screen_len) {
if (par->yres_virtual)
var->yres_virtual = par->yres_virtual;
else
/* yres_virtual == 0 means use maximum */
var->yres_virtual = screen_len / linelen;
} else {
if (hwscroll < 0)
var->yres_virtual = 2 * var->yres;
else
var->yres_virtual = var->yres + hwscroll * 16;
}
var->xoffset = 0; /* TODO change this */
/* hdX-offsets */
prescale = hxx_prescale(hw);
plen = 4 >> (hw->vid_mode >> 2 & 0x3);
base_off = hw->vid_control & VCO_SHORTOFFS ? 64 : 128;
if (hw->f_shift & 0x100) {
hde_off = 0;
hdb_off = (base_off + 16 * plen) + prescale;
} else {
hde_off = ((128 / var->bits_per_pixel + 2) * plen);
if (hw->ste_mode)
hdb_off = (64 + base_off + (128 / var->bits_per_pixel + 2) * plen)
+ prescale;
else
hdb_off = (base_off + (128 / var->bits_per_pixel + 18) * plen)
+ prescale;
}
/* Right margin includes hsync */
var->left_margin = hdb_off + prescale * ((hw->hdb & 0x1ff) -
(hw->hdb & 0x200 ? 2 + hw->hht : 0));
if (hw->ste_mode || mon_type != F_MON_VGA)
var->right_margin = prescale * (hw->hht + 2 - hw->hde) - hde_off;
else
/* can't use this in ste_mode, because hbb is +1 off */
var->right_margin = prescale * (hw->hht + 2 - hw->hbb);
var->hsync_len = prescale * (hw->hht + 2 - hw->hss);
/* Lower margin includes vsync */
var->upper_margin = hw->vdb / 2; /* round down to full lines */
var->lower_margin = (hw->vft + 1 - hw->vde + 1) / 2; /* round up */
var->vsync_len = (hw->vft + 1 - hw->vss + 1) / 2; /* round up */
if (var->vmode & FB_VMODE_INTERLACED) {
var->upper_margin *= 2;
var->lower_margin *= 2;
var->vsync_len *= 2;
} else if (var->vmode & FB_VMODE_DOUBLE) {
var->upper_margin = (var->upper_margin + 1) / 2;
var->lower_margin = (var->lower_margin + 1) / 2;
var->vsync_len = (var->vsync_len + 1) / 2;
}
var->pixclock *= plen;
var->left_margin /= plen;
var->right_margin /= plen;
var->hsync_len /= plen;
var->right_margin -= var->hsync_len;
var->lower_margin -= var->vsync_len;
if (screen_base)
var->yoffset = (par->screen_base - screen_base) / linelen;
else
var->yoffset = 0;
var->nonstd = 0; /* what is this for? */
var->activate = 0;
return 0;
}
static int f_change_mode;
static struct falcon_hw f_new_mode;
static int f_pan_display;
static void falcon_get_par(struct atafb_par *par)
{
unsigned long addr;
struct falcon_hw *hw = &par->hw.falcon;
hw->line_width = shifter_f030.scn_width;
hw->line_offset = shifter_f030.off_next;
hw->st_shift = videl.st_shift & 0x300;
hw->f_shift = videl.f_shift;
hw->vid_control = videl.control;
hw->vid_mode = videl.mode;
hw->sync = shifter_st.syncmode & 0x1;
hw->xoffset = videl.xoffset & 0xf;
hw->hht = videl.hht;
hw->hbb = videl.hbb;
hw->hbe = videl.hbe;
hw->hdb = videl.hdb;
hw->hde = videl.hde;
hw->hss = videl.hss;
hw->vft = videl.vft;
hw->vbb = videl.vbb;
hw->vbe = videl.vbe;
hw->vdb = videl.vdb;
hw->vde = videl.vde;
hw->vss = videl.vss;
addr = (shifter_st.bas_hi & 0xff) << 16 |
(shifter_st.bas_md & 0xff) << 8 |
(shifter_st.bas_lo & 0xff);
par->screen_base = atari_stram_to_virt(addr);
/* derived parameters */
hw->ste_mode = (hw->f_shift & 0x510) == 0 && hw->st_shift == 0x100;
hw->mono = (hw->f_shift & 0x400) ||
((hw->f_shift & 0x510) == 0 && hw->st_shift == 0x200);
}
static void falcon_set_par(struct atafb_par *par)
{
f_change_mode = 0;
/* only set screen_base if really necessary */
if (current_par.screen_base != par->screen_base)
fbhw->set_screen_base(par->screen_base);
/* Don't touch any other registers if we keep the default resolution */
if (DontCalcRes)
return;
/* Tell vbl-handler to change video mode.
* We change modes only on next VBL, to avoid desynchronisation
* (a shift to the right and wrap around by a random number of pixels
* in all monochrome modes).
* This seems to work on my Falcon.
*/
f_new_mode = par->hw.falcon;
f_change_mode = 1;
}
static irqreturn_t falcon_vbl_switcher(int irq, void *dummy)
{
struct falcon_hw *hw = &f_new_mode;
if (f_change_mode) {
f_change_mode = 0;
if (hw->sync & 0x1) {
/* Enable external pixelclock. This code only for ScreenWonder */
*(volatile unsigned short *)0xffff9202 = 0xffbf;
} else {
/* Turn off external clocks. Read sets all output bits to 1. */
*(volatile unsigned short *)0xffff9202;
}
shifter_st.syncmode = hw->sync;
videl.hht = hw->hht;
videl.hbb = hw->hbb;
videl.hbe = hw->hbe;
videl.hdb = hw->hdb;
videl.hde = hw->hde;
videl.hss = hw->hss;
videl.vft = hw->vft;
videl.vbb = hw->vbb;
videl.vbe = hw->vbe;
videl.vdb = hw->vdb;
videl.vde = hw->vde;
videl.vss = hw->vss;
videl.f_shift = 0; /* write enables Falcon palette, 0: 4 planes */
if (hw->ste_mode) {
videl.st_shift = hw->st_shift; /* write enables STE palette */
} else {
/* IMPORTANT:
* set st_shift 0, so we can tell the screen-depth if f_shift == 0.
* Writing 0 to f_shift enables 4 plane Falcon mode but
* doesn't set st_shift. st_shift != 0 (!= 4planes) is impossible
* with Falcon palette.
*/
videl.st_shift = 0;
/* now back to Falcon palette mode */
videl.f_shift = hw->f_shift;
}
/* writing to st_shift changed scn_width and vid_mode */
videl.xoffset = hw->xoffset;
shifter_f030.scn_width = hw->line_width;
shifter_f030.off_next = hw->line_offset;
videl.control = hw->vid_control;
videl.mode = hw->vid_mode;
}
if (f_pan_display) {
f_pan_display = 0;
videl.xoffset = current_par.hw.falcon.xoffset;
shifter_f030.off_next = current_par.hw.falcon.line_offset;
}
return IRQ_HANDLED;
}
static int falcon_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct atafb_par *par = info->par;
int xoffset;
int bpp = info->var.bits_per_pixel;
if (bpp == 1)
var->xoffset = round_up(var->xoffset, 32);
if (bpp != 16)
par->hw.falcon.xoffset = var->xoffset & 15;
else {
par->hw.falcon.xoffset = 0;
var->xoffset = round_up(var->xoffset, 2);
}
par->hw.falcon.line_offset = bpp *
(info->var.xres_virtual - info->var.xres) / 16;
if (par->hw.falcon.xoffset)
par->hw.falcon.line_offset -= bpp;
xoffset = var->xoffset - par->hw.falcon.xoffset;
par->screen_base = screen_base +
(var->yoffset * info->var.xres_virtual + xoffset) * bpp / 8;
if (fbhw->set_screen_base)
fbhw->set_screen_base(par->screen_base);
else
return -EINVAL; /* shouldn't happen */
f_pan_display = 1;
return 0;
}
static int falcon_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
if (regno > 255)
return 1;
f030_col[regno] = (((red & 0xfc00) << 16) |
((green & 0xfc00) << 8) |
((blue & 0xfc00) >> 8));
if (regno < 16) {
shifter_tt.color_reg[regno] =
((((red & 0xe000) >> 13) | ((red & 0x1000) >> 12)) << 8) |
((((green & 0xe000) >> 13) | ((green & 0x1000) >> 12)) << 4) |
((blue & 0xe000) >> 13) | ((blue & 0x1000) >> 12);
((u32 *)info->pseudo_palette)[regno] = ((red & 0xf800) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11));
}
return 0;
}
static int falcon_blank(int blank_mode)
{
/* ++guenther: we can switch off graphics by changing VDB and VDE,
* so VIDEL doesn't hog the bus while saving.
* (this may affect usleep()).
*/
int vdb, vss, hbe, hss;
if (mon_type == F_MON_SM) /* this doesn't work on SM124 */
return 1;
vdb = current_par.VDB;
vss = current_par.VSS;
hbe = current_par.HBE;
hss = current_par.HSS;
if (blank_mode >= 1) {
/* disable graphics output (this speeds up the CPU) ... */
vdb = current_par.VFT + 1;
/* ... and blank all lines */
hbe = current_par.HHT + 2;
}
/* use VESA suspend modes on VGA monitors */
if (mon_type == F_MON_VGA) {
if (blank_mode == 2 || blank_mode == 4)
vss = current_par.VFT + 1;
if (blank_mode == 3 || blank_mode == 4)
hss = current_par.HHT + 2;
}
videl.vdb = vdb;
videl.vss = vss;
videl.hbe = hbe;
videl.hss = hss;
return 0;
}
static int falcon_detect(void)
{
struct atafb_par par;
unsigned char fhw;
/* Determine connected monitor and set monitor parameters */
fhw = *(unsigned char *)0xffff8006;
mon_type = fhw >> 6 & 0x3;
/* bit 1 of fhw: 1=32 bit ram bus, 0=16 bit */
f030_bus_width = fhw << 6 & 0x80;
switch (mon_type) {
case F_MON_SM:
fb_info.monspecs.vfmin = 70;
fb_info.monspecs.vfmax = 72;
fb_info.monspecs.hfmin = 35713;
fb_info.monspecs.hfmax = 35715;
break;
case F_MON_SC:
case F_MON_TV:
/* PAL...NTSC */
fb_info.monspecs.vfmin = 49; /* not 50, since TOS defaults to 49.9x Hz */
fb_info.monspecs.vfmax = 60;
fb_info.monspecs.hfmin = 15620;
fb_info.monspecs.hfmax = 15755;
break;
}
/* initialize hsync-len */
f25.hsync = h_syncs[mon_type] / f25.t;
f32.hsync = h_syncs[mon_type] / f32.t;
if (fext.t)
fext.hsync = h_syncs[mon_type] / fext.t;
falcon_get_par(&par);
falcon_encode_var(&atafb_predefined[0], &par);
/* Detected mode is always the "autodetect" slot */
return 1;
}
#endif /* ATAFB_FALCON */
/* ------------------- ST(E) specific functions ---------------------- */
#ifdef ATAFB_STE
static int stste_encode_fix(struct fb_fix_screeninfo *fix,
struct atafb_par *par)
{
int mode;
strcpy(fix->id, "Atari Builtin");
fix->smem_start = phys_screen_base;
fix->smem_len = screen_len;
fix->type = FB_TYPE_INTERLEAVED_PLANES;
fix->type_aux = 2;
fix->visual = FB_VISUAL_PSEUDOCOLOR;
mode = par->hw.st.mode & 3;
if (mode == ST_HIGH) {
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
fix->visual = FB_VISUAL_MONO10;
}
if (ATARIHW_PRESENT(EXTD_SHIFTER)) {
fix->xpanstep = 16;
fix->ypanstep = 1;
} else {
fix->xpanstep = 0;
fix->ypanstep = 0;
}
fix->ywrapstep = 0;
fix->line_length = par->next_line;
fix->accel = FB_ACCEL_ATARIBLITT;
return 0;
}
static int stste_decode_var(struct fb_var_screeninfo *var,
struct atafb_par *par)
{
int xres = var->xres;
int yres = var->yres;
int bpp = var->bits_per_pixel;
int linelen;
int yres_virtual = var->yres_virtual;
if (mono_moni) {
if (bpp > 1 || xres > sttt_xres || yres > st_yres)
return -EINVAL;
par->hw.st.mode = ST_HIGH;
xres = sttt_xres;
yres = st_yres;
bpp = 1;
} else {
if (bpp > 4 || xres > sttt_xres || yres > st_yres)
return -EINVAL;
if (bpp > 2) {
if (xres > sttt_xres / 2 || yres > st_yres / 2)
return -EINVAL;
par->hw.st.mode = ST_LOW;
xres = sttt_xres / 2;
yres = st_yres / 2;
bpp = 4;
} else if (bpp > 1) {
if (xres > sttt_xres || yres > st_yres / 2)
return -EINVAL;
par->hw.st.mode = ST_MID;
xres = sttt_xres;
yres = st_yres / 2;
bpp = 2;
} else
return -EINVAL;
}
if (yres_virtual <= 0)
yres_virtual = 0;
else if (yres_virtual < yres)
yres_virtual = yres;
if (var->sync & FB_SYNC_EXT)
par->hw.st.sync = (par->hw.st.sync & ~1) | 1;
else
par->hw.st.sync = (par->hw.st.sync & ~1);
linelen = xres * bpp / 8;
if (yres_virtual * linelen > screen_len && screen_len)
return -EINVAL;
if (yres * linelen > screen_len && screen_len)
return -EINVAL;
if (var->yoffset + yres > yres_virtual && yres_virtual)
return -EINVAL;
par->yres_virtual = yres_virtual;
par->screen_base = screen_base + var->yoffset * linelen;
par->next_line = linelen;
return 0;
}
static int stste_encode_var(struct fb_var_screeninfo *var,
struct atafb_par *par)
{
int linelen;
memset(var, 0, sizeof(struct fb_var_screeninfo));
var->red.offset = 0;
var->red.length = ATARIHW_PRESENT(EXTD_SHIFTER) ? 4 : 3;
var->red.msb_right = 0;
var->grayscale = 0;
var->pixclock = 31041;
var->left_margin = 120; /* these are incorrect */
var->right_margin = 100;
var->upper_margin = 8;
var->lower_margin = 16;
var->hsync_len = 140;
var->vsync_len = 30;
var->height = -1;
var->width = -1;
if (!(par->hw.st.sync & 1))
var->sync = 0;
else
var->sync = FB_SYNC_EXT;
switch (par->hw.st.mode & 3) {
case ST_LOW:
var->xres = sttt_xres / 2;
var->yres = st_yres / 2;
var->bits_per_pixel = 4;
break;
case ST_MID:
var->xres = sttt_xres;
var->yres = st_yres / 2;
var->bits_per_pixel = 2;
break;
case ST_HIGH:
var->xres = sttt_xres;
var->yres = st_yres;
var->bits_per_pixel = 1;
break;
}
var->blue = var->green = var->red;
var->transp.offset = 0;
var->transp.length = 0;
var->transp.msb_right = 0;
var->xres_virtual = sttt_xres_virtual;
linelen = var->xres_virtual * var->bits_per_pixel / 8;
ovsc_addlen = linelen * (sttt_yres_virtual - st_yres);
if (!use_hwscroll)
var->yres_virtual = var->yres;
else if (screen_len) {
if (par->yres_virtual)
var->yres_virtual = par->yres_virtual;
else
/* yres_virtual == 0 means use maximum */
var->yres_virtual = screen_len / linelen;
} else {
if (hwscroll < 0)
var->yres_virtual = 2 * var->yres;
else
var->yres_virtual = var->yres + hwscroll * 16;
}
var->xoffset = 0;
if (screen_base)
var->yoffset = (par->screen_base - screen_base) / linelen;
else
var->yoffset = 0;
var->nonstd = 0;
var->activate = 0;
var->vmode = FB_VMODE_NONINTERLACED;
return 0;
}
static void stste_get_par(struct atafb_par *par)
{
unsigned long addr;
par->hw.st.mode = shifter_tt.st_shiftmode;
par->hw.st.sync = shifter_st.syncmode;
addr = ((shifter_st.bas_hi & 0xff) << 16) |
((shifter_st.bas_md & 0xff) << 8);
if (ATARIHW_PRESENT(EXTD_SHIFTER))
addr |= (shifter_st.bas_lo & 0xff);
par->screen_base = atari_stram_to_virt(addr);
}
static void stste_set_par(struct atafb_par *par)
{
shifter_tt.st_shiftmode = par->hw.st.mode;
shifter_st.syncmode = par->hw.st.sync;
/* only set screen_base if really necessary */
if (current_par.screen_base != par->screen_base)
fbhw->set_screen_base(par->screen_base);
}
static int stste_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
if (regno > 15)
return 1;
red >>= 12;
blue >>= 12;
green >>= 12;
if (ATARIHW_PRESENT(EXTD_SHIFTER))
shifter_tt.color_reg[regno] =
((((red & 0xe) >> 1) | ((red & 1) << 3)) << 8) |
((((green & 0xe) >> 1) | ((green & 1) << 3)) << 4) |
((blue & 0xe) >> 1) | ((blue & 1) << 3);
else
shifter_tt.color_reg[regno] =
((red & 0xe) << 7) |
((green & 0xe) << 3) |
((blue & 0xe) >> 1);
return 0;
}
static int stste_detect(void)
{
struct atafb_par par;
/* Determine the connected monitor: The DMA sound must be
* disabled before reading the MFP GPIP, because the Sound
* Done Signal and the Monochrome Detect are XORed together!
*/
if (ATARIHW_PRESENT(PCM_8BIT)) {
tt_dmasnd.ctrl = DMASND_CTRL_OFF;
udelay(20); /* wait a while for things to settle down */
}
mono_moni = (st_mfp.par_dt_reg & 0x80) == 0;
stste_get_par(&par);
stste_encode_var(&atafb_predefined[0], &par);
if (!ATARIHW_PRESENT(EXTD_SHIFTER))
use_hwscroll = 0;
return 1;
}
static void stste_set_screen_base(void *s_base)
{
unsigned long addr;
addr = atari_stram_to_phys(s_base);
/* Setup Screen Memory */
shifter_st.bas_hi = (unsigned char)((addr & 0xff0000) >> 16);
shifter_st.bas_md = (unsigned char)((addr & 0x00ff00) >> 8);
if (ATARIHW_PRESENT(EXTD_SHIFTER))
shifter_st.bas_lo = (unsigned char)(addr & 0x0000ff);
}
#endif /* ATAFB_STE */
/* Switching the screen size should be done during vsync, otherwise
* the margins may get messed up. This is a well known problem of
* the ST's video system.
*
* Unfortunately there is hardly any way to find the vsync, as the
* vertical blank interrupt is no longer in time on machines with
* overscan type modifications.
*
* We can, however, use Timer B to safely detect the black shoulder,
* but then we've got to guess an appropriate delay to find the vsync.
* This might not work on every machine.
*
* martin_rogge @ ki.maus.de, 8th Aug 1995
*/
#define LINE_DELAY (mono_moni ? 30 : 70)
#define SYNC_DELAY (mono_moni ? 1500 : 2000)
/* SWITCH_ACIA may be used for Falcon (ScreenBlaster III internal!) */
static void st_ovsc_switch(void)
{
unsigned long flags;
register unsigned char old, new;
if (!(atari_switches & ATARI_SWITCH_OVSC_MASK))
return;
local_irq_save(flags);
st_mfp.tim_ct_b = 0x10;
st_mfp.active_edge |= 8;
st_mfp.tim_ct_b = 0;
st_mfp.tim_dt_b = 0xf0;
st_mfp.tim_ct_b = 8;
while (st_mfp.tim_dt_b > 1) /* TOS does it this way, don't ask why */
;
new = st_mfp.tim_dt_b;
do {
udelay(LINE_DELAY);
old = new;
new = st_mfp.tim_dt_b;
} while (old != new);
st_mfp.tim_ct_b = 0x10;
udelay(SYNC_DELAY);
if (atari_switches & ATARI_SWITCH_OVSC_IKBD)
acia.key_ctrl = ACIA_DIV64 | ACIA_D8N1S | ACIA_RHTID | ACIA_RIE;
if (atari_switches & ATARI_SWITCH_OVSC_MIDI)
acia.mid_ctrl = ACIA_DIV16 | ACIA_D8N1S | ACIA_RHTID;
if (atari_switches & (ATARI_SWITCH_OVSC_SND6|ATARI_SWITCH_OVSC_SND7)) {
sound_ym.rd_data_reg_sel = 14;
sound_ym.wd_data = sound_ym.rd_data_reg_sel |
((atari_switches & ATARI_SWITCH_OVSC_SND6) ? 0x40:0) |
((atari_switches & ATARI_SWITCH_OVSC_SND7) ? 0x80:0);
}
local_irq_restore(flags);
}
/* ------------------- External Video ---------------------- */
#ifdef ATAFB_EXT
static int ext_encode_fix(struct fb_fix_screeninfo *fix, struct atafb_par *par)
{
strcpy(fix->id, "Unknown Extern");
fix->smem_start = external_addr;
fix->smem_len = PAGE_ALIGN(external_len);
if (external_depth == 1) {
fix->type = FB_TYPE_PACKED_PIXELS;
/* The letters 'n' and 'i' in the "atavideo=external:" stand
* for "normal" and "inverted", rsp., in the monochrome case */
fix->visual =
(external_pmode == FB_TYPE_INTERLEAVED_PLANES ||
external_pmode == FB_TYPE_PACKED_PIXELS) ?
FB_VISUAL_MONO10 : FB_VISUAL_MONO01;
} else {
/* Use STATIC if we don't know how to access color registers */
int visual = external_vgaiobase ?
FB_VISUAL_PSEUDOCOLOR :
FB_VISUAL_STATIC_PSEUDOCOLOR;
switch (external_pmode) {
case -1: /* truecolor */
fix->type = FB_TYPE_PACKED_PIXELS;
fix->visual = FB_VISUAL_TRUECOLOR;
break;
case FB_TYPE_PACKED_PIXELS:
fix->type = FB_TYPE_PACKED_PIXELS;
fix->visual = visual;
break;
case FB_TYPE_PLANES:
fix->type = FB_TYPE_PLANES;
fix->visual = visual;
break;
case FB_TYPE_INTERLEAVED_PLANES:
fix->type = FB_TYPE_INTERLEAVED_PLANES;
fix->type_aux = 2;
fix->visual = visual;
break;
}
}
fix->xpanstep = 0;
fix->ypanstep = 0;
fix->ywrapstep = 0;
fix->line_length = par->next_line;
return 0;
}
static int ext_decode_var(struct fb_var_screeninfo *var, struct atafb_par *par)
{
struct fb_var_screeninfo *myvar = &atafb_predefined[0];
if (var->bits_per_pixel > myvar->bits_per_pixel ||
var->xres > myvar->xres ||
var->xres_virtual > myvar->xres_virtual ||
var->yres > myvar->yres ||
var->xoffset > 0 ||
var->yoffset > 0)
return -EINVAL;
par->next_line = external_xres_virtual * external_depth / 8;
return 0;
}
static int ext_encode_var(struct fb_var_screeninfo *var, struct atafb_par *par)
{
memset(var, 0, sizeof(struct fb_var_screeninfo));
var->red.offset = 0;
var->red.length = (external_pmode == -1) ? external_depth / 3 :
(external_vgaiobase ? external_bitspercol : 0);
var->red.msb_right = 0;
var->grayscale = 0;
var->pixclock = 31041;
var->left_margin = 120; /* these are surely incorrect */
var->right_margin = 100;
var->upper_margin = 8;
var->lower_margin = 16;
var->hsync_len = 140;
var->vsync_len = 30;
var->height = -1;
var->width = -1;
var->sync = 0;
var->xres = external_xres;
var->yres = external_yres;
var->xres_virtual = external_xres_virtual;
var->bits_per_pixel = external_depth;
var->blue = var->green = var->red;
var->transp.offset = 0;
var->transp.length = 0;
var->transp.msb_right = 0;
var->yres_virtual = var->yres;
var->xoffset = 0;
var->yoffset = 0;
var->nonstd = 0;
var->activate = 0;
var->vmode = FB_VMODE_NONINTERLACED;
return 0;
}
static void ext_get_par(struct atafb_par *par)
{
par->screen_base = external_screen_base;
}
static void ext_set_par(struct atafb_par *par)
{
}
#define OUTB(port,val) \
*((unsigned volatile char *) ((port)+external_vgaiobase)) = (val)
#define INB(port) \
(*((unsigned volatile char *) ((port)+external_vgaiobase)))
#define DACDelay \
do { \
unsigned char tmp = INB(0x3da); \
tmp = INB(0x3da); \
} while (0)
static int ext_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
unsigned char colmask = (1 << external_bitspercol) - 1;
if (!external_vgaiobase)
return 1;
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
switch (external_card_type) {
case IS_VGA:
OUTB(0x3c8, regno);
DACDelay;
OUTB(0x3c9, red & colmask);
DACDelay;
OUTB(0x3c9, green & colmask);
DACDelay;
OUTB(0x3c9, blue & colmask);
DACDelay;
return 0;
case IS_MV300:
OUTB((MV300_reg[regno] << 2) + 1, red);
OUTB((MV300_reg[regno] << 2) + 1, green);
OUTB((MV300_reg[regno] << 2) + 1, blue);
return 0;
default:
return 1;
}
}
static int ext_detect(void)
{
struct fb_var_screeninfo *myvar = &atafb_predefined[0];
struct atafb_par dummy_par;
myvar->xres = external_xres;
myvar->xres_virtual = external_xres_virtual;
myvar->yres = external_yres;
myvar->bits_per_pixel = external_depth;
ext_encode_var(myvar, &dummy_par);
return 1;
}
#endif /* ATAFB_EXT */
/* ------ This is the same for most hardware types -------- */
static void set_screen_base(void *s_base)
{
unsigned long addr;
addr = atari_stram_to_phys(s_base);
/* Setup Screen Memory */
shifter_st.bas_hi = (unsigned char)((addr & 0xff0000) >> 16);
shifter_st.bas_md = (unsigned char)((addr & 0x00ff00) >> 8);
shifter_st.bas_lo = (unsigned char)(addr & 0x0000ff);
}
static int pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct atafb_par *par = info->par;
if (!fbhw->set_screen_base ||
(!ATARIHW_PRESENT(EXTD_SHIFTER) && var->xoffset))
return -EINVAL;
var->xoffset = round_up(var->xoffset, 16);
par->screen_base = screen_base +
(var->yoffset * info->var.xres_virtual + var->xoffset)
* info->var.bits_per_pixel / 8;
fbhw->set_screen_base(par->screen_base);
return 0;
}
/* ------------ Interfaces to hardware functions ------------ */
#ifdef ATAFB_TT
static struct fb_hwswitch tt_switch = {
.detect = tt_detect,
.encode_fix = tt_encode_fix,
.decode_var = tt_decode_var,
.encode_var = tt_encode_var,
.get_par = tt_get_par,
.set_par = tt_set_par,
.set_screen_base = set_screen_base,
.pan_display = pan_display,
};
#endif
#ifdef ATAFB_FALCON
static struct fb_hwswitch falcon_switch = {
.detect = falcon_detect,
.encode_fix = falcon_encode_fix,
.decode_var = falcon_decode_var,
.encode_var = falcon_encode_var,
.get_par = falcon_get_par,
.set_par = falcon_set_par,
.set_screen_base = set_screen_base,
.blank = falcon_blank,
.pan_display = falcon_pan_display,
};
#endif
#ifdef ATAFB_STE
static struct fb_hwswitch st_switch = {
.detect = stste_detect,
.encode_fix = stste_encode_fix,
.decode_var = stste_decode_var,
.encode_var = stste_encode_var,
.get_par = stste_get_par,
.set_par = stste_set_par,
.set_screen_base = stste_set_screen_base,
.pan_display = pan_display
};
#endif
#ifdef ATAFB_EXT
static struct fb_hwswitch ext_switch = {
.detect = ext_detect,
.encode_fix = ext_encode_fix,
.decode_var = ext_decode_var,
.encode_var = ext_encode_var,
.get_par = ext_get_par,
.set_par = ext_set_par,
};
#endif
static void ata_get_par(struct atafb_par *par)
{
if (current_par_valid)
*par = current_par;
else
fbhw->get_par(par);
}
static void ata_set_par(struct atafb_par *par)
{
fbhw->set_par(par);
current_par = *par;
current_par_valid = 1;
}
/* =========================================================== */
/* ============== Hardware Independent Functions ============= */
/* =========================================================== */
/* used for hardware scrolling */
static int do_fb_set_var(struct fb_var_screeninfo *var, int isactive)
{
int err, activate;
struct atafb_par par;
err = fbhw->decode_var(var, &par);
if (err)
return err;
activate = var->activate;
if (((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) && isactive)
ata_set_par(&par);
fbhw->encode_var(var, &par);
var->activate = activate;
return 0;
}
/* fbhw->encode_fix() must be called with fb_info->mm_lock held
* if it is called after the register_framebuffer() - not a case here
*/
static int atafb_get_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
{
struct atafb_par par;
int err;
// Get fix directly (case con == -1 before)??
err = fbhw->decode_var(&info->var, &par);
if (err)
return err;
memset(fix, 0, sizeof(struct fb_fix_screeninfo));
err = fbhw->encode_fix(fix, &par);
return err;
}
static int atafb_get_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct atafb_par par;
ata_get_par(&par);
fbhw->encode_var(var, &par);
return 0;
}
// No longer called by fbcon!
// Still called by set_var internally
static void atafb_set_disp(struct fb_info *info)
{
atafb_get_var(&info->var, info);
atafb_get_fix(&info->fix, info);
/* Note: smem_start derives from phys_screen_base, not screen_base! */
info->screen_base = (external_addr ? external_screen_base :
atari_stram_to_virt(info->fix.smem_start));
}
static int
atafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (!fbhw->pan_display)
return -EINVAL;
return fbhw->pan_display(var, info);
}
/*
* generic drawing routines; imageblit needs updating for image depth > 1
*/
static void atafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct atafb_par *par = info->par;
int x2, y2;
u32 width, height;
if (!rect->width || !rect->height)
return;
#ifdef ATAFB_FALCON
if (info->var.bits_per_pixel == 16) {
cfb_fillrect(info, rect);
return;
}
#endif
/*
* We could use hardware clipping but on many cards you get around
* hardware clipping by writing to framebuffer directly.
* */
x2 = rect->dx + rect->width;
y2 = rect->dy + rect->height;
x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
width = x2 - rect->dx;
height = y2 - rect->dy;
if (info->var.bits_per_pixel == 1)
atafb_mfb_fillrect(info, par->next_line, rect->color,
rect->dy, rect->dx, height, width);
else if (info->var.bits_per_pixel == 2)
atafb_iplan2p2_fillrect(info, par->next_line, rect->color,
rect->dy, rect->dx, height, width);
else if (info->var.bits_per_pixel == 4)
atafb_iplan2p4_fillrect(info, par->next_line, rect->color,
rect->dy, rect->dx, height, width);
else
atafb_iplan2p8_fillrect(info, par->next_line, rect->color,
rect->dy, rect->dx, height, width);
return;
}
static void atafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct atafb_par *par = info->par;
int x2, y2;
u32 dx, dy, sx, sy, width, height;
int rev_copy = 0;
#ifdef ATAFB_FALCON
if (info->var.bits_per_pixel == 16) {
cfb_copyarea(info, area);
return;
}
#endif
/* clip the destination */
x2 = area->dx + area->width;
y2 = area->dy + area->height;
dx = area->dx > 0 ? area->dx : 0;
dy = area->dy > 0 ? area->dy : 0;
x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
width = x2 - dx;
height = y2 - dy;
if (area->sx + dx < area->dx || area->sy + dy < area->dy)
return;
/* update sx,sy */
sx = area->sx + (dx - area->dx);
sy = area->sy + (dy - area->dy);
/* the source must be completely inside the virtual screen */
if (sx + width > info->var.xres_virtual ||
sy + height > info->var.yres_virtual)
return;
if (dy > sy || (dy == sy && dx > sx)) {
dy += height;
sy += height;
rev_copy = 1;
}
if (info->var.bits_per_pixel == 1)
atafb_mfb_copyarea(info, par->next_line, sy, sx, dy, dx, height, width);
else if (info->var.bits_per_pixel == 2)
atafb_iplan2p2_copyarea(info, par->next_line, sy, sx, dy, dx, height, width);
else if (info->var.bits_per_pixel == 4)
atafb_iplan2p4_copyarea(info, par->next_line, sy, sx, dy, dx, height, width);
else
atafb_iplan2p8_copyarea(info, par->next_line, sy, sx, dy, dx, height, width);
return;
}
static void atafb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct atafb_par *par = info->par;
int x2, y2;
const char *src;
u32 dx, dy, width, height, pitch;
#ifdef ATAFB_FALCON
if (info->var.bits_per_pixel == 16) {
cfb_imageblit(info, image);
return;
}
#endif
/*
* We could use hardware clipping but on many cards you get around
* hardware clipping by writing to framebuffer directly like we are
* doing here.
*/
x2 = image->dx + image->width;
y2 = image->dy + image->height;
dx = image->dx;
dy = image->dy;
x2 = x2 < info->var.xres_virtual ? x2 : info->var.xres_virtual;
y2 = y2 < info->var.yres_virtual ? y2 : info->var.yres_virtual;
width = x2 - dx;
height = y2 - dy;
if (image->depth == 1) {
// used for font data
src = image->data;
pitch = (image->width + 7) / 8;
while (height--) {
if (info->var.bits_per_pixel == 1)
atafb_mfb_linefill(info, par->next_line,
dy, dx, width, src,
image->bg_color, image->fg_color);
else if (info->var.bits_per_pixel == 2)
atafb_iplan2p2_linefill(info, par->next_line,
dy, dx, width, src,
image->bg_color, image->fg_color);
else if (info->var.bits_per_pixel == 4)
atafb_iplan2p4_linefill(info, par->next_line,
dy, dx, width, src,
image->bg_color, image->fg_color);
else
atafb_iplan2p8_linefill(info, par->next_line,
dy, dx, width, src,
image->bg_color, image->fg_color);
dy++;
src += pitch;
}
} else {
c2p_iplan2(info->screen_base, image->data, dx, dy, width,
height, par->next_line, image->width,
info->var.bits_per_pixel);
}
}
static int
atafb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
switch (cmd) {
#ifdef FBCMD_GET_CURRENTPAR
case FBCMD_GET_CURRENTPAR:
if (copy_to_user((void *)arg, ¤t_par,
sizeof(struct atafb_par)))
return -EFAULT;
return 0;
#endif
#ifdef FBCMD_SET_CURRENTPAR
case FBCMD_SET_CURRENTPAR:
if (copy_from_user(¤t_par, (void *)arg,
sizeof(struct atafb_par)))
return -EFAULT;
ata_set_par(¤t_par);
return 0;
#endif
}
return -EINVAL;
}
/* (un)blank/poweroff
* 0 = unblank
* 1 = blank
* 2 = suspend vsync
* 3 = suspend hsync
* 4 = off
*/
static int atafb_blank(int blank, struct fb_info *info)
{
unsigned short black[16];
struct fb_cmap cmap;
if (fbhw->blank && !fbhw->blank(blank))
return 1;
if (blank) {
memset(black, 0, 16 * sizeof(unsigned short));
cmap.red = black;
cmap.green = black;
cmap.blue = black;
cmap.transp = NULL;
cmap.start = 0;
cmap.len = 16;
fb_set_cmap(&cmap, info);
}
#if 0
else
do_install_cmap(info);
#endif
return 0;
}
/*
* New fbcon interface ...
*/
/* check var by decoding var into hw par, rounding if necessary,
* then encoding hw par back into new, validated var */
static int atafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
int err;
struct atafb_par par;
/* Validate wanted screen parameters */
// if ((err = ata_decode_var(var, &par)))
err = fbhw->decode_var(var, &par);
if (err)
return err;
/* Encode (possibly rounded) screen parameters */
fbhw->encode_var(var, &par);
return 0;
}
/* actually set hw par by decoding var, then setting hardware from
* hw par just decoded */
static int atafb_set_par(struct fb_info *info)
{
struct atafb_par *par = info->par;
/* Decode wanted screen parameters */
fbhw->decode_var(&info->var, par);
mutex_lock(&info->mm_lock);
fbhw->encode_fix(&info->fix, par);
mutex_unlock(&info->mm_lock);
/* Set new videomode */
ata_set_par(par);
return 0;
}
static struct fb_ops atafb_ops = {
.owner = THIS_MODULE,
.fb_check_var = atafb_check_var,
.fb_set_par = atafb_set_par,
.fb_blank = atafb_blank,
.fb_pan_display = atafb_pan_display,
.fb_fillrect = atafb_fillrect,
.fb_copyarea = atafb_copyarea,
.fb_imageblit = atafb_imageblit,
.fb_ioctl = atafb_ioctl,
};
static void check_default_par(int detected_mode)
{
char default_name[10];
int i;
struct fb_var_screeninfo var;
unsigned long min_mem;
/* First try the user supplied mode */
if (default_par) {
var = atafb_predefined[default_par - 1];
var.activate = FB_ACTIVATE_TEST;
if (do_fb_set_var(&var, 1))
default_par = 0; /* failed */
}
/* Next is the autodetected one */
if (!default_par) {
var = atafb_predefined[detected_mode - 1]; /* autodetect */
var.activate = FB_ACTIVATE_TEST;
if (!do_fb_set_var(&var, 1))
default_par = detected_mode;
}
/* If that also failed, try some default modes... */
if (!default_par) {
/* try default1, default2... */
for (i = 1; i < 10; i++) {
sprintf(default_name,"default%d", i);
default_par = get_video_mode(default_name);
if (!default_par)
panic("can't set default video mode");
var = atafb_predefined[default_par - 1];
var.activate = FB_ACTIVATE_TEST;
if (!do_fb_set_var(&var,1))
break; /* ok */
}
}
min_mem = var.xres_virtual * var.yres_virtual * var.bits_per_pixel / 8;
if (default_mem_req < min_mem)
default_mem_req = min_mem;
}
#ifdef ATAFB_EXT
static void __init atafb_setup_ext(char *spec)
{
int xres, xres_virtual, yres, depth, planes;
unsigned long addr, len;
char *p;
/* Format is: <xres>;<yres>;<depth>;<plane organ.>;
* <screen mem addr>
* [;<screen mem length>[;<vgaiobase>[;<bits-per-col>[;<colorreg-type>
* [;<xres-virtual>]]]]]
*
* 09/23/97 Juergen
* <xres_virtual>: hardware's x-resolution (f.e. ProMST)
*
* Even xres_virtual is available, we neither support panning nor hw-scrolling!
*/
p = strsep(&spec, ";");
if (!p || !*p)
return;
xres_virtual = xres = simple_strtoul(p, NULL, 10);
if (xres <= 0)
return;
p = strsep(&spec, ";");
if (!p || !*p)
return;
yres = simple_strtoul(p, NULL, 10);
if (yres <= 0)
return;
p = strsep(&spec, ";");
if (!p || !*p)
return;
depth = simple_strtoul(p, NULL, 10);
if (depth != 1 && depth != 2 && depth != 4 && depth != 8 &&
depth != 16 && depth != 24)
return;
p = strsep(&spec, ";");
if (!p || !*p)
return;
if (*p == 'i')
planes = FB_TYPE_INTERLEAVED_PLANES;
else if (*p == 'p')
planes = FB_TYPE_PACKED_PIXELS;
else if (*p == 'n')
planes = FB_TYPE_PLANES;
else if (*p == 't')
planes = -1; /* true color */
else
return;
p = strsep(&spec, ";");
if (!p || !*p)
return;
addr = simple_strtoul(p, NULL, 0);
p = strsep(&spec, ";");
if (!p || !*p)
len = xres * yres * depth / 8;
else
len = simple_strtoul(p, NULL, 0);
p = strsep(&spec, ";");
if (p && *p)
external_vgaiobase = simple_strtoul(p, NULL, 0);
p = strsep(&spec, ";");
if (p && *p) {
external_bitspercol = simple_strtoul(p, NULL, 0);
if (external_bitspercol > 8)
external_bitspercol = 8;
else if (external_bitspercol < 1)
external_bitspercol = 1;
}
p = strsep(&spec, ";");
if (p && *p) {
if (!strcmp(p, "vga"))
external_card_type = IS_VGA;
if (!strcmp(p, "mv300"))
external_card_type = IS_MV300;
}
p = strsep(&spec, ";");
if (p && *p) {
xres_virtual = simple_strtoul(p, NULL, 10);
if (xres_virtual < xres)
xres_virtual = xres;
if (xres_virtual * yres * depth / 8 > len)
len = xres_virtual * yres * depth / 8;
}
external_xres = xres;
external_xres_virtual = xres_virtual;
external_yres = yres;
external_depth = depth;
external_pmode = planes;
external_addr = addr;
external_len = len;
if (external_card_type == IS_MV300) {
switch (external_depth) {
case 1:
MV300_reg = MV300_reg_1bit;
break;
case 4:
MV300_reg = MV300_reg_4bit;
break;
case 8:
MV300_reg = MV300_reg_8bit;
break;
}
}
}
#endif /* ATAFB_EXT */
static void __init atafb_setup_int(char *spec)
{
/* Format to config extended internal video hardware like OverScan:
* "internal:<xres>;<yres>;<xres_max>;<yres_max>;<offset>"
* Explanation:
* <xres>: x-resolution
* <yres>: y-resolution
* The following are only needed if you have an overscan which
* needs a black border:
* <xres_max>: max. length of a line in pixels your OverScan hardware would allow
* <yres_max>: max. number of lines your OverScan hardware would allow
* <offset>: Offset from physical beginning to visible beginning
* of screen in bytes
*/
int xres;
char *p;
if (!(p = strsep(&spec, ";")) || !*p)
return;
xres = simple_strtoul(p, NULL, 10);
if (!(p = strsep(&spec, ";")) || !*p)
return;
sttt_xres = xres;
tt_yres = st_yres = simple_strtoul(p, NULL, 10);
if ((p = strsep(&spec, ";")) && *p)
sttt_xres_virtual = simple_strtoul(p, NULL, 10);
if ((p = strsep(&spec, ";")) && *p)
sttt_yres_virtual = simple_strtoul(p, NULL, 0);
if ((p = strsep(&spec, ";")) && *p)
ovsc_offset = simple_strtoul(p, NULL, 0);
if (ovsc_offset || (sttt_yres_virtual != st_yres))
use_hwscroll = 0;
}
#ifdef ATAFB_FALCON
static void __init atafb_setup_mcap(char *spec)
{
char *p;
int vmin, vmax, hmin, hmax;
/* Format for monitor capabilities is: <Vmin>;<Vmax>;<Hmin>;<Hmax>
* <V*> vertical freq. in Hz
* <H*> horizontal freq. in kHz
*/
if (!(p = strsep(&spec, ";")) || !*p)
return;
vmin = simple_strtoul(p, NULL, 10);
if (vmin <= 0)
return;
if (!(p = strsep(&spec, ";")) || !*p)
return;
vmax = simple_strtoul(p, NULL, 10);
if (vmax <= 0 || vmax <= vmin)
return;
if (!(p = strsep(&spec, ";")) || !*p)
return;
hmin = 1000 * simple_strtoul(p, NULL, 10);
if (hmin <= 0)
return;
if (!(p = strsep(&spec, "")) || !*p)
return;
hmax = 1000 * simple_strtoul(p, NULL, 10);
if (hmax <= 0 || hmax <= hmin)
return;
fb_info.monspecs.vfmin = vmin;
fb_info.monspecs.vfmax = vmax;
fb_info.monspecs.hfmin = hmin;
fb_info.monspecs.hfmax = hmax;
}
#endif /* ATAFB_FALCON */
static void __init atafb_setup_user(char *spec)
{
/* Format of user defined video mode is: <xres>;<yres>;<depth>
*/
char *p;
int xres, yres, depth, temp;
p = strsep(&spec, ";");
if (!p || !*p)
return;
xres = simple_strtoul(p, NULL, 10);
p = strsep(&spec, ";");
if (!p || !*p)
return;
yres = simple_strtoul(p, NULL, 10);
p = strsep(&spec, "");
if (!p || !*p)
return;
depth = simple_strtoul(p, NULL, 10);
temp = get_video_mode("user0");
if (temp) {
default_par = temp;
atafb_predefined[default_par - 1].xres = xres;
atafb_predefined[default_par - 1].yres = yres;
atafb_predefined[default_par - 1].bits_per_pixel = depth;
}
}
static int __init atafb_setup(char *options)
{
char *this_opt;
int temp;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if ((temp = get_video_mode(this_opt))) {
default_par = temp;
mode_option = this_opt;
} else if (!strcmp(this_opt, "inverse"))
fb_invert_cmaps();
else if (!strncmp(this_opt, "hwscroll_", 9)) {
hwscroll = simple_strtoul(this_opt + 9, NULL, 10);
if (hwscroll < 0)
hwscroll = 0;
if (hwscroll > 200)
hwscroll = 200;
}
#ifdef ATAFB_EXT
else if (!strcmp(this_opt, "mv300")) {
external_bitspercol = 8;
external_card_type = IS_MV300;
} else if (!strncmp(this_opt, "external:", 9))
atafb_setup_ext(this_opt + 9);
#endif
else if (!strncmp(this_opt, "internal:", 9))
atafb_setup_int(this_opt + 9);
#ifdef ATAFB_FALCON
else if (!strncmp(this_opt, "eclock:", 7)) {
fext.f = simple_strtoul(this_opt + 7, NULL, 10);
/* external pixelclock in kHz --> ps */
fext.t = 1000000000 / fext.f;
fext.f *= 1000;
} else if (!strncmp(this_opt, "monitorcap:", 11))
atafb_setup_mcap(this_opt + 11);
#endif
else if (!strcmp(this_opt, "keep"))
DontCalcRes = 1;
else if (!strncmp(this_opt, "R", 1))
atafb_setup_user(this_opt + 1);
}
return 0;
}
static int __init atafb_probe(struct platform_device *pdev)
{
int pad, detected_mode, error;
unsigned int defmode = 0;
unsigned long mem_req;
char *option = NULL;
if (fb_get_options("atafb", &option))
return -ENODEV;
atafb_setup(option);
dev_dbg(&pdev->dev, "%s: start\n", __func__);
do {
#ifdef ATAFB_EXT
if (external_addr) {
dev_dbg(&pdev->dev, "initializing external hw\n");
fbhw = &ext_switch;
atafb_ops.fb_setcolreg = &ext_setcolreg;
defmode = DEFMODE_EXT;
break;
}
#endif
#ifdef ATAFB_TT
if (ATARIHW_PRESENT(TT_SHIFTER)) {
dev_dbg(&pdev->dev, "initializing TT hw\n");
fbhw = &tt_switch;
atafb_ops.fb_setcolreg = &tt_setcolreg;
defmode = DEFMODE_TT;
break;
}
#endif
#ifdef ATAFB_FALCON
if (ATARIHW_PRESENT(VIDEL_SHIFTER)) {
dev_dbg(&pdev->dev, "initializing Falcon hw\n");
fbhw = &falcon_switch;
atafb_ops.fb_setcolreg = &falcon_setcolreg;
error = request_irq(IRQ_AUTO_4, falcon_vbl_switcher, 0,
"framebuffer:modeswitch",
falcon_vbl_switcher);
if (error)
return error;
defmode = DEFMODE_F30;
break;
}
#endif
#ifdef ATAFB_STE
if (ATARIHW_PRESENT(STND_SHIFTER) ||
ATARIHW_PRESENT(EXTD_SHIFTER)) {
dev_dbg(&pdev->dev, "initializing ST/E hw\n");
fbhw = &st_switch;
atafb_ops.fb_setcolreg = &stste_setcolreg;
defmode = DEFMODE_STE;
break;
}
fbhw = &st_switch;
atafb_ops.fb_setcolreg = &stste_setcolreg;
dev_warn(&pdev->dev,
"Cannot determine video hardware; defaulting to ST(e)\n");
#else /* ATAFB_STE */
/* no default driver included */
/* Nobody will ever see this message :-) */
panic("Cannot initialize video hardware");
#endif
} while (0);
/* Multisync monitor capabilities */
/* Atari-TOS defaults if no boot option present */
if (fb_info.monspecs.hfmin == 0) {
fb_info.monspecs.hfmin = 31000;
fb_info.monspecs.hfmax = 32000;
fb_info.monspecs.vfmin = 58;
fb_info.monspecs.vfmax = 62;
}
detected_mode = fbhw->detect();
check_default_par(detected_mode);
#ifdef ATAFB_EXT
if (!external_addr) {
#endif /* ATAFB_EXT */
mem_req = default_mem_req + ovsc_offset + ovsc_addlen;
mem_req = PAGE_ALIGN(mem_req) + PAGE_SIZE;
screen_base = atari_stram_alloc(mem_req, "atafb");
if (!screen_base)
panic("Cannot allocate screen memory");
memset(screen_base, 0, mem_req);
pad = -(unsigned long)screen_base & (PAGE_SIZE - 1);
screen_base += pad;
phys_screen_base = atari_stram_to_phys(screen_base + ovsc_offset);
screen_len = (mem_req - pad - ovsc_offset) & PAGE_MASK;
st_ovsc_switch();
if (CPU_IS_040_OR_060) {
/* On a '040+, the cache mode of video RAM must be set to
* write-through also for internal video hardware! */
cache_push(atari_stram_to_phys(screen_base), screen_len);
kernel_set_cachemode(screen_base, screen_len,
IOMAP_WRITETHROUGH);
}
dev_info(&pdev->dev, "phys_screen_base %lx screen_len %d\n",
phys_screen_base, screen_len);
#ifdef ATAFB_EXT
} else {
/* Map the video memory (physical address given) to somewhere
* in the kernel address space.
*/
external_screen_base = ioremap_wt(external_addr, external_len);
if (external_vgaiobase)
external_vgaiobase =
(unsigned long)ioremap(external_vgaiobase, 0x10000);
screen_base = external_screen_base;
phys_screen_base = external_addr;
screen_len = external_len & PAGE_MASK;
memset (screen_base, 0, external_len);
}
#endif /* ATAFB_EXT */
// strcpy(fb_info.mode->name, "Atari Builtin ");
fb_info.fbops = &atafb_ops;
// try to set default (detected; requested) var
do_fb_set_var(&atafb_predefined[default_par - 1], 1);
// reads hw state into current par, which may not be sane yet
ata_get_par(¤t_par);
fb_info.par = ¤t_par;
// tries to read from HW which may not be initialized yet
// so set sane var first, then call atafb_set_par
atafb_get_var(&fb_info.var, &fb_info);
#ifdef ATAFB_FALCON
fb_info.pseudo_palette = current_par.hw.falcon.pseudo_palette;
#endif
if (!fb_find_mode(&fb_info.var, &fb_info, mode_option, atafb_modedb,
NUM_TOTAL_MODES, &atafb_modedb[defmode],
fb_info.var.bits_per_pixel)) {
return -EINVAL;
}
fb_videomode_to_modelist(atafb_modedb, NUM_TOTAL_MODES,
&fb_info.modelist);
atafb_set_disp(&fb_info);
fb_alloc_cmap(&(fb_info.cmap), 1 << fb_info.var.bits_per_pixel, 0);
dev_info(&pdev->dev, "Determined %dx%d, depth %d\n", fb_info.var.xres,
fb_info.var.yres, fb_info.var.bits_per_pixel);
if ((fb_info.var.xres != fb_info.var.xres_virtual) ||
(fb_info.var.yres != fb_info.var.yres_virtual))
dev_info(&pdev->dev, " virtual %dx%d\n",
fb_info.var.xres_virtual, fb_info.var.yres_virtual);
if (register_framebuffer(&fb_info) < 0) {
#ifdef ATAFB_EXT
if (external_addr) {
iounmap(external_screen_base);
external_addr = 0;
}
if (external_vgaiobase) {
iounmap((void*)external_vgaiobase);
external_vgaiobase = 0;
}
#endif
return -EINVAL;
}
fb_info(&fb_info, "frame buffer device, using %dK of video memory\n",
screen_len >> 10);
/* TODO: This driver cannot be unloaded yet */
return 0;
}
static void atafb_shutdown(struct platform_device *pdev)
{
/* Unblank before kexec */
if (fbhw->blank)
fbhw->blank(0);
}
static struct platform_driver atafb_driver = {
.shutdown = atafb_shutdown,
.driver = {
.name = "atafb",
},
};
static int __init atafb_init(void)
{
struct platform_device *pdev;
if (!MACH_IS_ATARI)
return -ENODEV;
pdev = platform_device_register_simple("atafb", -1, NULL, 0);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
return platform_driver_probe(&atafb_driver, atafb_probe);
}
device_initcall(atafb_init);
| linux-master | drivers/video/fbdev/atafb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Frame buffer driver for Trident TGUI, Blade and Image series
*
* Copyright 2001, 2002 - Jani Monoses <[email protected]>
* Copyright 2009 Krzysztof Helt <[email protected]>
*
* CREDITS:(in order of appearance)
* skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
* Special thanks ;) to Mattia Crivellini <[email protected]>
* much inspired by the XFree86 4.x Trident driver sources
* by Alan Hourihane the FreeVGA project
* Francesco Salvestrini <[email protected]> XP support,
* code, suggestions
* TODO:
* timing value tweaking so it looks good on every monitor in every mode
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <video/vga.h>
#include <video/trident.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
struct tridentfb_par {
void __iomem *io_virt; /* iospace virtual memory address */
u32 pseudo_pal[16];
int chip_id;
int flatpanel;
void (*init_accel) (struct tridentfb_par *, int, int);
void (*wait_engine) (struct tridentfb_par *);
void (*fill_rect)
(struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
void (*copy_rect)
(struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
void (*image_blit)
(struct tridentfb_par *par, const char*,
u32, u32, u32, u32, u32, u32);
unsigned char eng_oper; /* engine operation... */
bool ddc_registered;
struct i2c_adapter ddc_adapter;
struct i2c_algo_bit_data ddc_algo;
};
static struct fb_fix_screeninfo tridentfb_fix = {
.id = "Trident",
.type = FB_TYPE_PACKED_PIXELS,
.ypanstep = 1,
.visual = FB_VISUAL_PSEUDOCOLOR,
.accel = FB_ACCEL_NONE,
};
/* defaults which are normally overriden by user values */
/* video mode */
static char *mode_option;
static int bpp = 8;
static int noaccel;
static int center;
static int stretch;
static int fp;
static int crt;
static int memsize;
static int memdiff;
static int nativex;
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
module_param_named(mode, mode_option, charp, 0);
MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
module_param(bpp, int, 0);
module_param(center, int, 0);
module_param(stretch, int, 0);
module_param(noaccel, int, 0);
module_param(memsize, int, 0);
module_param(memdiff, int, 0);
module_param(nativex, int, 0);
module_param(fp, int, 0);
MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
module_param(crt, int, 0);
MODULE_PARM_DESC(crt, "Define if CRT is connected");
static inline int is_oldclock(int id)
{
return (id == TGUI9440) ||
(id == TGUI9660) ||
(id == CYBER9320);
}
static inline int is_oldprotect(int id)
{
return is_oldclock(id) ||
(id == PROVIDIA9685) ||
(id == CYBER9382) ||
(id == CYBER9385);
}
static inline int is_blade(int id)
{
return (id == BLADE3D) ||
(id == CYBERBLADEE4) ||
(id == CYBERBLADEi7) ||
(id == CYBERBLADEi7D) ||
(id == CYBERBLADEi1) ||
(id == CYBERBLADEi1D) ||
(id == CYBERBLADEAi1) ||
(id == CYBERBLADEAi1D);
}
static inline int is_xp(int id)
{
return (id == CYBERBLADEXPAi1) ||
(id == CYBERBLADEXPm8) ||
(id == CYBERBLADEXPm16);
}
static inline int is3Dchip(int id)
{
return is_blade(id) || is_xp(id) ||
(id == CYBER9397) || (id == CYBER9397DVD) ||
(id == CYBER9520) || (id == CYBER9525DVD) ||
(id == IMAGE975) || (id == IMAGE985);
}
static inline int iscyber(int id)
{
switch (id) {
case CYBER9388:
case CYBER9382:
case CYBER9385:
case CYBER9397:
case CYBER9397DVD:
case CYBER9520:
case CYBER9525DVD:
case CYBERBLADEE4:
case CYBERBLADEi7D:
case CYBERBLADEi1:
case CYBERBLADEi1D:
case CYBERBLADEAi1:
case CYBERBLADEAi1D:
case CYBERBLADEXPAi1:
return 1;
case CYBER9320:
case CYBERBLADEi7: /* VIA MPV4 integrated version */
default:
/* case CYBERBLDAEXPm8: Strange */
/* case CYBERBLDAEXPm16: Strange */
return 0;
}
}
static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
{
fb_writeb(val, p->io_virt + reg);
}
static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
{
return fb_readb(p->io_virt + reg);
}
static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
{
fb_writel(v, par->io_virt + r);
}
static inline u32 readmmr(struct tridentfb_par *par, u16 r)
{
return fb_readl(par->io_virt + r);
}
#define DDC_SDA_TGUI BIT(0)
#define DDC_SCL_TGUI BIT(1)
#define DDC_SCL_DRIVE_TGUI BIT(2)
#define DDC_SDA_DRIVE_TGUI BIT(3)
#define DDC_MASK_TGUI (DDC_SCL_DRIVE_TGUI | DDC_SDA_DRIVE_TGUI)
static void tridentfb_ddc_setscl_tgui(void *data, int val)
{
struct tridentfb_par *par = data;
u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
if (val)
reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */
else
reg |= DDC_SCL_DRIVE_TGUI; /* drive low */
vga_mm_wcrt(par->io_virt, I2C, reg);
}
static void tridentfb_ddc_setsda_tgui(void *data, int val)
{
struct tridentfb_par *par = data;
u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
if (val)
reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */
else
reg |= DDC_SDA_DRIVE_TGUI; /* drive low */
vga_mm_wcrt(par->io_virt, I2C, reg);
}
static int tridentfb_ddc_getsda_tgui(void *data)
{
struct tridentfb_par *par = data;
return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
}
#define DDC_SDA_IN BIT(0)
#define DDC_SCL_OUT BIT(1)
#define DDC_SDA_OUT BIT(3)
#define DDC_SCL_IN BIT(6)
#define DDC_MASK (DDC_SCL_OUT | DDC_SDA_OUT)
static void tridentfb_ddc_setscl(void *data, int val)
{
struct tridentfb_par *par = data;
unsigned char reg;
reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
if (val)
reg |= DDC_SCL_OUT;
else
reg &= ~DDC_SCL_OUT;
vga_mm_wcrt(par->io_virt, I2C, reg);
}
static void tridentfb_ddc_setsda(void *data, int val)
{
struct tridentfb_par *par = data;
unsigned char reg;
reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
if (!val)
reg |= DDC_SDA_OUT;
else
reg &= ~DDC_SDA_OUT;
vga_mm_wcrt(par->io_virt, I2C, reg);
}
static int tridentfb_ddc_getscl(void *data)
{
struct tridentfb_par *par = data;
return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
}
static int tridentfb_ddc_getsda(void *data)
{
struct tridentfb_par *par = data;
return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
}
static int tridentfb_setup_ddc_bus(struct fb_info *info)
{
struct tridentfb_par *par = info->par;
strscpy(par->ddc_adapter.name, info->fix.id,
sizeof(par->ddc_adapter.name));
par->ddc_adapter.owner = THIS_MODULE;
par->ddc_adapter.class = I2C_CLASS_DDC;
par->ddc_adapter.algo_data = &par->ddc_algo;
par->ddc_adapter.dev.parent = info->device;
if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
par->ddc_algo.setsda = tridentfb_ddc_setsda_tgui;
par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui;
par->ddc_algo.getsda = tridentfb_ddc_getsda_tgui;
/* no getscl */
} else {
par->ddc_algo.setsda = tridentfb_ddc_setsda;
par->ddc_algo.setscl = tridentfb_ddc_setscl;
par->ddc_algo.getsda = tridentfb_ddc_getsda;
par->ddc_algo.getscl = tridentfb_ddc_getscl;
}
par->ddc_algo.udelay = 10;
par->ddc_algo.timeout = 20;
par->ddc_algo.data = par;
i2c_set_adapdata(&par->ddc_adapter, par);
return i2c_bit_add_bus(&par->ddc_adapter);
}
/*
* Blade specific acceleration.
*/
#define point(x, y) ((y) << 16 | (x))
static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
{
int v1 = (pitch >> 3) << 20;
int tmp = bpp == 24 ? 2 : (bpp >> 4);
int v2 = v1 | (tmp << 29);
writemmr(par, 0x21C0, v2);
writemmr(par, 0x21C4, v2);
writemmr(par, 0x21B8, v2);
writemmr(par, 0x21BC, v2);
writemmr(par, 0x21D0, v1);
writemmr(par, 0x21D4, v1);
writemmr(par, 0x21C8, v1);
writemmr(par, 0x21CC, v1);
writemmr(par, 0x216C, 0);
}
static void blade_wait_engine(struct tridentfb_par *par)
{
while (readmmr(par, STATUS) & 0xFA800000)
cpu_relax();
}
static void blade_fill_rect(struct tridentfb_par *par,
u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
{
writemmr(par, COLOR, c);
writemmr(par, ROP, rop ? ROP_X : ROP_S);
writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
writemmr(par, DST1, point(x, y));
writemmr(par, DST2, point(x + w - 1, y + h - 1));
}
static void blade_image_blit(struct tridentfb_par *par, const char *data,
u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
{
unsigned size = ((w + 31) >> 5) * h;
writemmr(par, COLOR, c);
writemmr(par, BGCOLOR, b);
writemmr(par, CMD, 0xa0000000 | 3 << 19);
writemmr(par, DST1, point(x, y));
writemmr(par, DST2, point(x + w - 1, y + h - 1));
iowrite32_rep(par->io_virt + 0x10000, data, size);
}
static void blade_copy_rect(struct tridentfb_par *par,
u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
{
int direction = 2;
u32 s1 = point(x1, y1);
u32 s2 = point(x1 + w - 1, y1 + h - 1);
u32 d1 = point(x2, y2);
u32 d2 = point(x2 + w - 1, y2 + h - 1);
if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
direction = 0;
writemmr(par, ROP, ROP_S);
writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
writemmr(par, SRC1, direction ? s2 : s1);
writemmr(par, SRC2, direction ? s1 : s2);
writemmr(par, DST1, direction ? d2 : d1);
writemmr(par, DST2, direction ? d1 : d2);
}
/*
* BladeXP specific acceleration functions
*/
static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
{
unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
switch (pitch << (bpp >> 3)) {
case 8192:
case 512:
x |= 0x00;
break;
case 1024:
x |= 0x04;
break;
case 2048:
x |= 0x08;
break;
case 4096:
x |= 0x0C;
break;
}
t_outb(par, x, 0x2125);
par->eng_oper = x | 0x40;
writemmr(par, 0x2154, v1);
writemmr(par, 0x2150, v1);
t_outb(par, 3, 0x2126);
}
static void xp_wait_engine(struct tridentfb_par *par)
{
int count = 0;
int timeout = 0;
while (t_inb(par, STATUS) & 0x80) {
count++;
if (count == 10000000) {
/* Timeout */
count = 9990000;
timeout++;
if (timeout == 8) {
/* Reset engine */
t_outb(par, 0x00, STATUS);
return;
}
}
cpu_relax();
}
}
static void xp_fill_rect(struct tridentfb_par *par,
u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
{
writemmr(par, 0x2127, ROP_P);
writemmr(par, 0x2158, c);
writemmr(par, DRAWFL, 0x4000);
writemmr(par, OLDDIM, point(h, w));
writemmr(par, OLDDST, point(y, x));
t_outb(par, 0x01, OLDCMD);
t_outb(par, par->eng_oper, 0x2125);
}
static void xp_copy_rect(struct tridentfb_par *par,
u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
{
u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
int direction = 0x0004;
if ((x1 < x2) && (y1 == y2)) {
direction |= 0x0200;
x1_tmp = x1 + w - 1;
x2_tmp = x2 + w - 1;
} else {
x1_tmp = x1;
x2_tmp = x2;
}
if (y1 < y2) {
direction |= 0x0100;
y1_tmp = y1 + h - 1;
y2_tmp = y2 + h - 1;
} else {
y1_tmp = y1;
y2_tmp = y2;
}
writemmr(par, DRAWFL, direction);
t_outb(par, ROP_S, 0x2127);
writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
writemmr(par, OLDDIM, point(h, w));
t_outb(par, 0x01, OLDCMD);
}
/*
* Image specific acceleration functions
*/
static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
{
int tmp = bpp == 24 ? 2: (bpp >> 4);
writemmr(par, 0x2120, 0xF0000000);
writemmr(par, 0x2120, 0x40000000 | tmp);
writemmr(par, 0x2120, 0x80000000);
writemmr(par, 0x2144, 0x00000000);
writemmr(par, 0x2148, 0x00000000);
writemmr(par, 0x2150, 0x00000000);
writemmr(par, 0x2154, 0x00000000);
writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
writemmr(par, 0x216C, 0x00000000);
writemmr(par, 0x2170, 0x00000000);
writemmr(par, 0x217C, 0x00000000);
writemmr(par, 0x2120, 0x10000000);
writemmr(par, 0x2130, (2047 << 16) | 2047);
}
static void image_wait_engine(struct tridentfb_par *par)
{
while (readmmr(par, 0x2164) & 0xF0000000)
cpu_relax();
}
static void image_fill_rect(struct tridentfb_par *par,
u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
{
writemmr(par, 0x2120, 0x80000000);
writemmr(par, 0x2120, 0x90000000 | ROP_S);
writemmr(par, 0x2144, c);
writemmr(par, DST1, point(x, y));
writemmr(par, DST2, point(x + w - 1, y + h - 1));
writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
}
static void image_copy_rect(struct tridentfb_par *par,
u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
{
int direction = 0x4;
u32 s1 = point(x1, y1);
u32 s2 = point(x1 + w - 1, y1 + h - 1);
u32 d1 = point(x2, y2);
u32 d2 = point(x2 + w - 1, y2 + h - 1);
if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
direction = 0;
writemmr(par, 0x2120, 0x80000000);
writemmr(par, 0x2120, 0x90000000 | ROP_S);
writemmr(par, SRC1, direction ? s2 : s1);
writemmr(par, SRC2, direction ? s1 : s2);
writemmr(par, DST1, direction ? d2 : d1);
writemmr(par, DST2, direction ? d1 : d2);
writemmr(par, 0x2124,
0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
}
/*
* TGUI 9440/96XX acceleration
*/
static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
{
unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
/* disable clipping */
writemmr(par, 0x2148, 0);
writemmr(par, 0x214C, point(4095, 2047));
switch ((pitch * bpp) / 8) {
case 8192:
case 512:
x |= 0x00;
break;
case 1024:
x |= 0x04;
break;
case 2048:
x |= 0x08;
break;
case 4096:
x |= 0x0C;
break;
}
fb_writew(x, par->io_virt + 0x2122);
}
static void tgui_fill_rect(struct tridentfb_par *par,
u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
{
t_outb(par, ROP_P, 0x2127);
writemmr(par, OLDCLR, c);
writemmr(par, DRAWFL, 0x4020);
writemmr(par, OLDDIM, point(w - 1, h - 1));
writemmr(par, OLDDST, point(x, y));
t_outb(par, 1, OLDCMD);
}
static void tgui_copy_rect(struct tridentfb_par *par,
u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
{
int flags = 0;
u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
if ((x1 < x2) && (y1 == y2)) {
flags |= 0x0200;
x1_tmp = x1 + w - 1;
x2_tmp = x2 + w - 1;
} else {
x1_tmp = x1;
x2_tmp = x2;
}
if (y1 < y2) {
flags |= 0x0100;
y1_tmp = y1 + h - 1;
y2_tmp = y2 + h - 1;
} else {
y1_tmp = y1;
y2_tmp = y2;
}
writemmr(par, DRAWFL, 0x4 | flags);
t_outb(par, ROP_S, 0x2127);
writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
writemmr(par, OLDDIM, point(w - 1, h - 1));
t_outb(par, 1, OLDCMD);
}
/*
* Accel functions called by the upper layers
*/
static void tridentfb_fillrect(struct fb_info *info,
const struct fb_fillrect *fr)
{
struct tridentfb_par *par = info->par;
int col;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_fillrect(info, fr);
return;
}
if (info->var.bits_per_pixel == 8) {
col = fr->color;
col |= col << 8;
col |= col << 16;
} else
col = ((u32 *)(info->pseudo_palette))[fr->color];
par->wait_engine(par);
par->fill_rect(par, fr->dx, fr->dy, fr->width,
fr->height, col, fr->rop);
}
static void tridentfb_imageblit(struct fb_info *info,
const struct fb_image *img)
{
struct tridentfb_par *par = info->par;
int col, bgcol;
if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
cfb_imageblit(info, img);
return;
}
if (info->var.bits_per_pixel == 8) {
col = img->fg_color;
col |= col << 8;
col |= col << 16;
bgcol = img->bg_color;
bgcol |= bgcol << 8;
bgcol |= bgcol << 16;
} else {
col = ((u32 *)(info->pseudo_palette))[img->fg_color];
bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
}
par->wait_engine(par);
if (par->image_blit)
par->image_blit(par, img->data, img->dx, img->dy,
img->width, img->height, col, bgcol);
else
cfb_imageblit(info, img);
}
static void tridentfb_copyarea(struct fb_info *info,
const struct fb_copyarea *ca)
{
struct tridentfb_par *par = info->par;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_copyarea(info, ca);
return;
}
par->wait_engine(par);
par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
ca->width, ca->height);
}
static int tridentfb_sync(struct fb_info *info)
{
struct tridentfb_par *par = info->par;
if (!(info->flags & FBINFO_HWACCEL_DISABLED))
par->wait_engine(par);
return 0;
}
/*
* Hardware access functions
*/
static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
{
return vga_mm_rcrt(par->io_virt, reg);
}
static inline void write3X4(struct tridentfb_par *par, int reg,
unsigned char val)
{
vga_mm_wcrt(par->io_virt, reg, val);
}
static inline unsigned char read3CE(struct tridentfb_par *par,
unsigned char reg)
{
return vga_mm_rgfx(par->io_virt, reg);
}
static inline void writeAttr(struct tridentfb_par *par, int reg,
unsigned char val)
{
fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
vga_mm_wattr(par->io_virt, reg, val);
}
static inline void write3CE(struct tridentfb_par *par, int reg,
unsigned char val)
{
vga_mm_wgfx(par->io_virt, reg, val);
}
static void enable_mmio(struct tridentfb_par *par)
{
/* Goto New Mode */
vga_io_rseq(0x0B);
/* Unprotect registers */
vga_io_wseq(NewMode1, 0x80);
if (!is_oldprotect(par->chip_id))
vga_io_wseq(Protection, 0x92);
/* Enable MMIO */
outb(PCIReg, 0x3D4);
outb(inb(0x3D5) | 0x01, 0x3D5);
}
static void disable_mmio(struct tridentfb_par *par)
{
/* Goto New Mode */
vga_mm_rseq(par->io_virt, 0x0B);
/* Unprotect registers */
vga_mm_wseq(par->io_virt, NewMode1, 0x80);
if (!is_oldprotect(par->chip_id))
vga_mm_wseq(par->io_virt, Protection, 0x92);
/* Disable MMIO */
t_outb(par, PCIReg, 0x3D4);
t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
}
static inline void crtc_unlock(struct tridentfb_par *par)
{
write3X4(par, VGA_CRTC_V_SYNC_END,
read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
}
/* Return flat panel's maximum x resolution */
static int get_nativex(struct tridentfb_par *par)
{
int x, y, tmp;
if (nativex)
return nativex;
tmp = (read3CE(par, VertStretch) >> 4) & 3;
switch (tmp) {
case 0:
x = 1280; y = 1024;
break;
case 2:
x = 1024; y = 768;
break;
case 3:
x = 800; y = 600;
break;
case 1:
default:
x = 640; y = 480;
break;
}
output("%dx%d flat panel found\n", x, y);
return x;
}
/* Set pitch */
static inline void set_lwidth(struct tridentfb_par *par, int width)
{
write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
/* chips older than TGUI9660 have only 1 width bit in AddColReg */
/* touching the other one breaks I2C/DDC */
if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
write3X4(par, AddColReg,
(read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
else
write3X4(par, AddColReg,
(read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
}
/* For resolutions smaller than FP resolution stretch */
static void screen_stretch(struct tridentfb_par *par)
{
if (par->chip_id != CYBERBLADEXPAi1)
write3CE(par, BiosReg, 0);
else
write3CE(par, BiosReg, 8);
write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
}
/* For resolutions smaller than FP resolution center */
static inline void screen_center(struct tridentfb_par *par)
{
write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
}
/* Address of first shown pixel in display memory */
static void set_screen_start(struct tridentfb_par *par, int base)
{
u8 tmp;
write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
tmp = read3X4(par, CRTCModuleTest) & 0xDF;
write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
tmp = read3X4(par, CRTHiOrd) & 0xF8;
write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
}
/* Set dotclock frequency */
static void set_vclk(struct tridentfb_par *par, unsigned long freq)
{
int m, n, k;
unsigned long fi, d, di;
unsigned char best_m = 0, best_n = 0, best_k = 0;
unsigned char hi, lo;
unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
d = 20000;
for (k = shift; k >= 0; k--)
for (m = 1; m < 32; m++) {
n = ((m + 2) << shift) - 8;
for (n = (n < 0 ? 0 : n); n < 122; n++) {
fi = ((14318l * (n + 8)) / (m + 2)) >> k;
di = abs(fi - freq);
if (di < d || (di == d && k == best_k)) {
d = di;
best_n = n;
best_m = m;
best_k = k;
}
if (fi > freq)
break;
}
}
if (is_oldclock(par->chip_id)) {
lo = best_n | (best_m << 7);
hi = (best_m >> 1) | (best_k << 4);
} else {
lo = best_n;
hi = best_m | (best_k << 6);
}
if (is3Dchip(par->chip_id)) {
vga_mm_wseq(par->io_virt, ClockHigh, hi);
vga_mm_wseq(par->io_virt, ClockLow, lo);
} else {
t_outb(par, lo, 0x43C8);
t_outb(par, hi, 0x43C9);
}
debug("VCLK = %X %X\n", hi, lo);
}
/* Set number of lines for flat panels*/
static void set_number_of_lines(struct tridentfb_par *par, int lines)
{
int tmp = read3CE(par, CyberEnhance) & 0x8F;
if (lines > 1024)
tmp |= 0x50;
else if (lines > 768)
tmp |= 0x30;
else if (lines > 600)
tmp |= 0x20;
else if (lines > 480)
tmp |= 0x10;
write3CE(par, CyberEnhance, tmp);
}
/*
* If we see that FP is active we assume we have one.
* Otherwise we have a CRT display. User can override.
*/
static int is_flatpanel(struct tridentfb_par *par)
{
if (fp)
return 1;
if (crt || !iscyber(par->chip_id))
return 0;
return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
}
/* Try detecting the video memory size */
static unsigned int get_memsize(struct tridentfb_par *par)
{
unsigned char tmp, tmp2;
unsigned int k;
/* If memory size provided by user */
if (memsize)
k = memsize * Kb;
else
switch (par->chip_id) {
case CYBER9525DVD:
k = 2560 * Kb;
break;
default:
tmp = read3X4(par, SPR) & 0x0F;
switch (tmp) {
case 0x01:
k = 512 * Kb;
break;
case 0x02:
k = 6 * Mb; /* XP */
break;
case 0x03:
k = 1 * Mb;
break;
case 0x04:
k = 8 * Mb;
break;
case 0x06:
k = 10 * Mb; /* XP */
break;
case 0x07:
k = 2 * Mb;
break;
case 0x08:
k = 12 * Mb; /* XP */
break;
case 0x0A:
k = 14 * Mb; /* XP */
break;
case 0x0C:
k = 16 * Mb; /* XP */
break;
case 0x0E: /* XP */
tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
switch (tmp2) {
case 0x00:
k = 20 * Mb;
break;
case 0x01:
k = 24 * Mb;
break;
case 0x10:
k = 28 * Mb;
break;
case 0x11:
k = 32 * Mb;
break;
default:
k = 1 * Mb;
break;
}
break;
case 0x0F:
k = 4 * Mb;
break;
default:
k = 1 * Mb;
break;
}
}
k -= memdiff * Kb;
output("framebuffer size = %d Kb\n", k / Kb);
return k;
}
/* See if we can handle the video mode described in var */
static int tridentfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct tridentfb_par *par = info->par;
int bpp = var->bits_per_pixel;
int line_length;
int ramdac = 230000; /* 230MHz for most 3D chips */
debug("enter\n");
if (!var->pixclock)
return -EINVAL;
/* check color depth */
if (bpp == 24)
bpp = var->bits_per_pixel = 32;
if (bpp != 8 && bpp != 16 && bpp != 32)
return -EINVAL;
if (par->chip_id == TGUI9440 && bpp == 32)
return -EINVAL;
/* check whether resolution fits on panel and in memory */
if (par->flatpanel && nativex && var->xres > nativex)
return -EINVAL;
/* various resolution checks */
var->xres = (var->xres + 7) & ~0x7;
if (var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if (var->yres > var->yres_virtual)
var->yres_virtual = var->yres;
if (var->xres_virtual > 4095 || var->yres > 2048)
return -EINVAL;
/* prevent from position overflow for acceleration */
if (var->yres_virtual > 0xffff)
return -EINVAL;
line_length = var->xres_virtual * bpp / 8;
if (!is3Dchip(par->chip_id) &&
!(info->flags & FBINFO_HWACCEL_DISABLED)) {
/* acceleration requires line length to be power of 2 */
if (line_length <= 512)
var->xres_virtual = 512 * 8 / bpp;
else if (line_length <= 1024)
var->xres_virtual = 1024 * 8 / bpp;
else if (line_length <= 2048)
var->xres_virtual = 2048 * 8 / bpp;
else if (line_length <= 4096)
var->xres_virtual = 4096 * 8 / bpp;
else if (line_length <= 8192)
var->xres_virtual = 8192 * 8 / bpp;
else
return -EINVAL;
line_length = var->xres_virtual * bpp / 8;
}
/* datasheet specifies how to set panning only up to 4 MB */
if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
var->yres_virtual = ((4 << 20) / line_length) + var->yres;
if (line_length * var->yres_virtual > info->fix.smem_len)
return -EINVAL;
switch (bpp) {
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green = var->red;
var->blue = var->red;
break;
case 16:
var->red.offset = 11;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = 5;
var->green.length = 6;
var->blue.length = 5;
break;
case 32:
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
default:
return -EINVAL;
}
if (is_xp(par->chip_id))
ramdac = 350000;
switch (par->chip_id) {
case TGUI9440:
ramdac = (bpp >= 16) ? 45000 : 90000;
break;
case CYBER9320:
case TGUI9660:
ramdac = 135000;
break;
case PROVIDIA9685:
case CYBER9388:
case CYBER9382:
case CYBER9385:
ramdac = 170000;
break;
}
/* The clock is doubled for 32 bpp */
if (bpp == 32)
ramdac /= 2;
if (PICOS2KHZ(var->pixclock) > ramdac)
return -EINVAL;
debug("exit\n");
return 0;
}
/* Pan the display */
static int tridentfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct tridentfb_par *par = info->par;
unsigned int offset;
debug("enter\n");
offset = (var->xoffset + (var->yoffset * info->var.xres_virtual))
* info->var.bits_per_pixel / 32;
set_screen_start(par, offset);
debug("exit\n");
return 0;
}
static inline void shadowmode_on(struct tridentfb_par *par)
{
write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
}
/* Set the hardware to the requested video mode */
static int tridentfb_set_par(struct fb_info *info)
{
struct tridentfb_par *par = info->par;
u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
struct fb_var_screeninfo *var = &info->var;
int bpp = var->bits_per_pixel;
unsigned char tmp;
unsigned long vclk;
debug("enter\n");
hdispend = var->xres / 8 - 1;
hsyncstart = (var->xres + var->right_margin) / 8;
hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
htotal = (var->xres + var->left_margin + var->right_margin +
var->hsync_len) / 8 - 5;
hblankstart = hdispend + 1;
hblankend = htotal + 3;
vdispend = var->yres - 1;
vsyncstart = var->yres + var->lower_margin;
vsyncend = vsyncstart + var->vsync_len;
vtotal = var->upper_margin + vsyncend - 2;
vblankstart = vdispend + 1;
vblankend = vtotal;
if (info->var.vmode & FB_VMODE_INTERLACED) {
vtotal /= 2;
vdispend /= 2;
vsyncstart /= 2;
vsyncend /= 2;
vblankstart /= 2;
vblankend /= 2;
}
enable_mmio(par);
crtc_unlock(par);
write3CE(par, CyberControl, 8);
tmp = 0xEB;
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
tmp &= ~0x40;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
tmp &= ~0x80;
if (par->flatpanel && var->xres < nativex) {
/*
* on flat panels with native size larger
* than requested resolution decide whether
* we stretch or center
*/
t_outb(par, tmp | 0xC0, VGA_MIS_W);
shadowmode_on(par);
if (center)
screen_center(par);
else if (stretch)
screen_stretch(par);
} else {
t_outb(par, tmp, VGA_MIS_W);
write3CE(par, CyberControl, 8);
}
/* vertical timing values */
write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
/* horizontal timing values */
write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
write3X4(par, VGA_CRTC_H_SYNC_END,
(hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
/* higher bits of vertical timing values */
tmp = 0x10;
if (vtotal & 0x100) tmp |= 0x01;
if (vdispend & 0x100) tmp |= 0x02;
if (vsyncstart & 0x100) tmp |= 0x04;
if (vblankstart & 0x100) tmp |= 0x08;
if (vtotal & 0x200) tmp |= 0x20;
if (vdispend & 0x200) tmp |= 0x40;
if (vsyncstart & 0x200) tmp |= 0x80;
write3X4(par, VGA_CRTC_OVERFLOW, tmp);
tmp = read3X4(par, CRTHiOrd) & 0x07;
tmp |= 0x08; /* line compare bit 10 */
if (vtotal & 0x400) tmp |= 0x80;
if (vblankstart & 0x400) tmp |= 0x40;
if (vsyncstart & 0x400) tmp |= 0x20;
if (vdispend & 0x400) tmp |= 0x10;
write3X4(par, CRTHiOrd, tmp);
tmp = (htotal >> 8) & 0x01;
tmp |= (hdispend >> 7) & 0x02;
tmp |= (hsyncstart >> 5) & 0x08;
tmp |= (hblankstart >> 4) & 0x10;
write3X4(par, HorizOverflow, tmp);
tmp = 0x40;
if (vblankstart & 0x200) tmp |= 0x20;
//FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
write3X4(par, VGA_CRTC_PRESET_ROW, 0);
write3X4(par, VGA_CRTC_MODE, 0xC3);
write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
/* enable access extended memory */
write3X4(par, CRTCModuleTest, tmp);
tmp = read3CE(par, MiscIntContReg) & ~0x4;
if (info->var.vmode & FB_VMODE_INTERLACED)
tmp |= 0x4;
write3CE(par, MiscIntContReg, tmp);
/* enable GE for text acceleration */
write3X4(par, GraphEngReg, 0x80);
switch (bpp) {
case 8:
tmp = 0x00;
break;
case 16:
tmp = 0x05;
break;
case 24:
tmp = 0x29;
break;
case 32:
tmp = 0x09;
break;
}
write3X4(par, PixelBusReg, tmp);
tmp = read3X4(par, DRAMControl);
if (!is_oldprotect(par->chip_id))
tmp |= 0x10;
if (iscyber(par->chip_id))
tmp |= 0x20;
write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
if (!is_xp(par->chip_id))
write3X4(par, Performance, read3X4(par, Performance) | 0x10);
/* MMIO & PCI read and write burst enable */
if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
vga_mm_wseq(par->io_virt, 0, 3);
vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
/* enable 4 maps because needed in chain4 mode */
vga_mm_wseq(par->io_virt, 2, 0x0F);
vga_mm_wseq(par->io_virt, 3, 0);
vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
/* convert from picoseconds to kHz */
vclk = PICOS2KHZ(info->var.pixclock);
/* divide clock by 2 if 32bpp chain4 mode display and CPU path */
tmp = read3CE(par, MiscExtFunc) & 0xF0;
if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
tmp |= 8;
vclk *= 2;
}
set_vclk(par, vclk);
write3CE(par, MiscExtFunc, tmp | 0x12);
write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
write3CE(par, 0x6, 0x05); /* graphics mode */
write3CE(par, 0x7, 0x0F); /* planes? */
/* graphics mode and support 256 color modes */
writeAttr(par, 0x10, 0x41);
writeAttr(par, 0x12, 0x0F); /* planes */
writeAttr(par, 0x13, 0); /* horizontal pel panning */
/* colors */
for (tmp = 0; tmp < 0x10; tmp++)
writeAttr(par, tmp, tmp);
fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
switch (bpp) {
case 8:
tmp = 0;
break;
case 16:
tmp = 0x30;
break;
case 24:
case 32:
tmp = 0xD0;
break;
}
t_inb(par, VGA_PEL_IW);
t_inb(par, VGA_PEL_MSK);
t_inb(par, VGA_PEL_MSK);
t_inb(par, VGA_PEL_MSK);
t_inb(par, VGA_PEL_MSK);
t_outb(par, tmp, VGA_PEL_MSK);
t_inb(par, VGA_PEL_IW);
if (par->flatpanel)
set_number_of_lines(par, info->var.yres);
info->fix.line_length = info->var.xres_virtual * bpp / 8;
set_lwidth(par, info->fix.line_length / 8);
if (!(info->flags & FBINFO_HWACCEL_DISABLED))
par->init_accel(par, info->var.xres_virtual, bpp);
info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
info->cmap.len = (bpp == 8) ? 256 : 16;
debug("exit\n");
return 0;
}
/* Set one color register */
static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
int bpp = info->var.bits_per_pixel;
struct tridentfb_par *par = info->par;
if (regno >= info->cmap.len)
return 1;
if (bpp == 8) {
t_outb(par, 0xFF, VGA_PEL_MSK);
t_outb(par, regno, VGA_PEL_IW);
t_outb(par, red >> 10, VGA_PEL_D);
t_outb(par, green >> 10, VGA_PEL_D);
t_outb(par, blue >> 10, VGA_PEL_D);
} else if (regno < 16) {
if (bpp == 16) { /* RGB 565 */
u32 col;
col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
((blue & 0xF800) >> 11);
col |= col << 16;
((u32 *)(info->pseudo_palette))[regno] = col;
} else if (bpp == 32) /* ARGB 8888 */
((u32 *)info->pseudo_palette)[regno] =
((transp & 0xFF00) << 16) |
((red & 0xFF00) << 8) |
((green & 0xFF00)) |
((blue & 0xFF00) >> 8);
}
return 0;
}
/* Try blanking the screen. For flat panels it does nothing */
static int tridentfb_blank(int blank_mode, struct fb_info *info)
{
unsigned char PMCont, DPMSCont;
struct tridentfb_par *par = info->par;
debug("enter\n");
if (par->flatpanel)
return 0;
t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
PMCont = t_inb(par, 0x83C6) & 0xFC;
DPMSCont = read3CE(par, PowerStatus) & 0xFC;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
/* Screen: On, HSync: On, VSync: On */
case FB_BLANK_NORMAL:
/* Screen: Off, HSync: On, VSync: On */
PMCont |= 0x03;
DPMSCont |= 0x00;
break;
case FB_BLANK_HSYNC_SUSPEND:
/* Screen: Off, HSync: Off, VSync: On */
PMCont |= 0x02;
DPMSCont |= 0x01;
break;
case FB_BLANK_VSYNC_SUSPEND:
/* Screen: Off, HSync: On, VSync: Off */
PMCont |= 0x02;
DPMSCont |= 0x02;
break;
case FB_BLANK_POWERDOWN:
/* Screen: Off, HSync: Off, VSync: Off */
PMCont |= 0x00;
DPMSCont |= 0x03;
break;
}
write3CE(par, PowerStatus, DPMSCont);
t_outb(par, 4, 0x83C8);
t_outb(par, PMCont, 0x83C6);
debug("exit\n");
/* let fbcon do a softblank for us */
return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
}
static const struct fb_ops tridentfb_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = tridentfb_setcolreg,
.fb_pan_display = tridentfb_pan_display,
.fb_blank = tridentfb_blank,
.fb_check_var = tridentfb_check_var,
.fb_set_par = tridentfb_set_par,
.fb_fillrect = tridentfb_fillrect,
.fb_copyarea = tridentfb_copyarea,
.fb_imageblit = tridentfb_imageblit,
.fb_sync = tridentfb_sync,
};
static int trident_pci_probe(struct pci_dev *dev,
const struct pci_device_id *id)
{
int err;
unsigned char revision;
struct fb_info *info;
struct tridentfb_par *default_par;
int chip3D;
int chip_id;
bool found = false;
err = aperture_remove_conflicting_pci_devices(dev, "tridentfb");
if (err)
return err;
err = pcim_enable_device(dev);
if (err)
return err;
info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
if (!info)
return -ENOMEM;
default_par = info->par;
chip_id = id->device;
/* If PCI id is 0x9660 then further detect chip type */
if (chip_id == TGUI9660) {
revision = vga_io_rseq(RevisionID);
switch (revision) {
case 0x21:
chip_id = PROVIDIA9685;
break;
case 0x22:
case 0x23:
chip_id = CYBER9397;
break;
case 0x2A:
chip_id = CYBER9397DVD;
break;
case 0x30:
case 0x33:
case 0x34:
case 0x35:
case 0x38:
case 0x3A:
case 0xB3:
chip_id = CYBER9385;
break;
case 0x40 ... 0x43:
chip_id = CYBER9382;
break;
case 0x4A:
chip_id = CYBER9388;
break;
default:
break;
}
}
chip3D = is3Dchip(chip_id);
if (is_xp(chip_id)) {
default_par->init_accel = xp_init_accel;
default_par->wait_engine = xp_wait_engine;
default_par->fill_rect = xp_fill_rect;
default_par->copy_rect = xp_copy_rect;
tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
} else if (is_blade(chip_id)) {
default_par->init_accel = blade_init_accel;
default_par->wait_engine = blade_wait_engine;
default_par->fill_rect = blade_fill_rect;
default_par->copy_rect = blade_copy_rect;
default_par->image_blit = blade_image_blit;
tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
} else if (chip3D) { /* 3DImage family left */
default_par->init_accel = image_init_accel;
default_par->wait_engine = image_wait_engine;
default_par->fill_rect = image_fill_rect;
default_par->copy_rect = image_copy_rect;
tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
} else { /* TGUI 9440/96XX family */
default_par->init_accel = tgui_init_accel;
default_par->wait_engine = xp_wait_engine;
default_par->fill_rect = tgui_fill_rect;
default_par->copy_rect = tgui_copy_rect;
tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
}
default_par->chip_id = chip_id;
/* setup MMIO region */
tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
if (!request_mem_region(tridentfb_fix.mmio_start,
tridentfb_fix.mmio_len, "tridentfb")) {
debug("request_region failed!\n");
framebuffer_release(info);
return -1;
}
default_par->io_virt = ioremap(tridentfb_fix.mmio_start,
tridentfb_fix.mmio_len);
if (!default_par->io_virt) {
debug("ioremap failed\n");
err = -1;
goto out_unmap1;
}
enable_mmio(default_par);
/* setup framebuffer memory */
tridentfb_fix.smem_start = pci_resource_start(dev, 0);
tridentfb_fix.smem_len = get_memsize(default_par);
if (!request_mem_region(tridentfb_fix.smem_start,
tridentfb_fix.smem_len, "tridentfb")) {
debug("request_mem_region failed!\n");
disable_mmio(info->par);
err = -1;
goto out_unmap1;
}
info->screen_base = ioremap(tridentfb_fix.smem_start,
tridentfb_fix.smem_len);
if (!info->screen_base) {
debug("ioremap failed\n");
err = -1;
goto out_unmap2;
}
default_par->flatpanel = is_flatpanel(default_par);
if (default_par->flatpanel)
nativex = get_nativex(default_par);
info->fix = tridentfb_fix;
info->fbops = &tridentfb_ops;
info->pseudo_palette = default_par->pseudo_pal;
info->flags = FBINFO_HWACCEL_YPAN;
if (!noaccel && default_par->init_accel) {
info->flags &= ~FBINFO_HWACCEL_DISABLED;
info->flags |= FBINFO_HWACCEL_COPYAREA;
info->flags |= FBINFO_HWACCEL_FILLRECT;
} else
info->flags |= FBINFO_HWACCEL_DISABLED;
if (is_blade(chip_id) && chip_id != BLADE3D)
info->flags |= FBINFO_READS_FAST;
info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
if (!info->pixmap.addr) {
err = -ENOMEM;
goto out_unmap2;
}
info->pixmap.size = 4096;
info->pixmap.buf_align = 4;
info->pixmap.scan_align = 1;
info->pixmap.access_align = 32;
info->pixmap.flags = FB_PIXMAP_SYSTEM;
info->var.bits_per_pixel = 8;
if (default_par->image_blit) {
info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
info->pixmap.scan_align = 4;
}
if (noaccel) {
printk(KERN_DEBUG "disabling acceleration\n");
info->flags |= FBINFO_HWACCEL_DISABLED;
info->pixmap.scan_align = 1;
}
if (tridentfb_setup_ddc_bus(info) == 0) {
u8 *edid = fb_ddc_read(&default_par->ddc_adapter);
default_par->ddc_registered = true;
if (edid) {
fb_edid_to_monspecs(edid, &info->monspecs);
kfree(edid);
if (!info->monspecs.modedb)
dev_err(info->device, "error getting mode database\n");
else {
const struct fb_videomode *m;
fb_videomode_to_modelist(info->monspecs.modedb,
info->monspecs.modedb_len,
&info->modelist);
m = fb_find_best_display(&info->monspecs,
&info->modelist);
if (m) {
fb_videomode_to_var(&info->var, m);
/* fill all other info->var's fields */
if (tridentfb_check_var(&info->var,
info) == 0)
found = true;
}
}
}
}
if (!mode_option && !found)
mode_option = "640x480-8@60";
/* Prepare startup mode */
if (mode_option) {
err = fb_find_mode(&info->var, info, mode_option,
info->monspecs.modedb,
info->monspecs.modedb_len,
NULL, info->var.bits_per_pixel);
if (!err || err == 4) {
err = -EINVAL;
dev_err(info->device, "mode %s not found\n",
mode_option);
fb_destroy_modedb(info->monspecs.modedb);
info->monspecs.modedb = NULL;
goto out_unmap2;
}
}
fb_destroy_modedb(info->monspecs.modedb);
info->monspecs.modedb = NULL;
err = fb_alloc_cmap(&info->cmap, 256, 0);
if (err < 0)
goto out_unmap2;
info->var.activate |= FB_ACTIVATE_NOW;
info->device = &dev->dev;
if (register_framebuffer(info) < 0) {
printk(KERN_ERR "tridentfb: could not register framebuffer\n");
fb_dealloc_cmap(&info->cmap);
err = -EINVAL;
goto out_unmap2;
}
output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
info->node, info->fix.id, info->var.xres,
info->var.yres, info->var.bits_per_pixel);
pci_set_drvdata(dev, info);
return 0;
out_unmap2:
if (default_par->ddc_registered)
i2c_del_adapter(&default_par->ddc_adapter);
kfree(info->pixmap.addr);
if (info->screen_base)
iounmap(info->screen_base);
disable_mmio(info->par);
out_unmap1:
if (default_par->io_virt)
iounmap(default_par->io_virt);
framebuffer_release(info);
return err;
}
static void trident_pci_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
struct tridentfb_par *par = info->par;
unregister_framebuffer(info);
if (par->ddc_registered)
i2c_del_adapter(&par->ddc_adapter);
iounmap(par->io_virt);
iounmap(info->screen_base);
kfree(info->pixmap.addr);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
/* List of boards that we are trying to support */
static const struct pci_device_id trident_devices[] = {
{PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0,}
};
MODULE_DEVICE_TABLE(pci, trident_devices);
static struct pci_driver tridentfb_pci_driver = {
.name = "tridentfb",
.id_table = trident_devices,
.probe = trident_pci_probe,
.remove = trident_pci_remove,
};
/*
* Parse user specified options (`video=trident:')
* example:
* video=trident:800x600,bpp=16,noaccel
*/
#ifndef MODULE
static int __init tridentfb_setup(char *options)
{
char *opt;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
if (!strncmp(opt, "noaccel", 7))
noaccel = 1;
else if (!strncmp(opt, "fp", 2))
fp = 1;
else if (!strncmp(opt, "crt", 3))
fp = 0;
else if (!strncmp(opt, "bpp=", 4))
bpp = simple_strtoul(opt + 4, NULL, 0);
else if (!strncmp(opt, "center", 6))
center = 1;
else if (!strncmp(opt, "stretch", 7))
stretch = 1;
else if (!strncmp(opt, "memsize=", 8))
memsize = simple_strtoul(opt + 8, NULL, 0);
else if (!strncmp(opt, "memdiff=", 8))
memdiff = simple_strtoul(opt + 8, NULL, 0);
else if (!strncmp(opt, "nativex=", 8))
nativex = simple_strtoul(opt + 8, NULL, 0);
else
mode_option = opt;
}
return 0;
}
#endif
static int __init tridentfb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("tridentfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("tridentfb", &option))
return -ENODEV;
tridentfb_setup(option);
#endif
return pci_register_driver(&tridentfb_pci_driver);
}
static void __exit tridentfb_exit(void)
{
pci_unregister_driver(&tridentfb_pci_driver);
}
module_init(tridentfb_init);
module_exit(tridentfb_exit);
MODULE_AUTHOR("Jani Monoses <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
MODULE_LICENSE("GPL");
MODULE_ALIAS("cyblafb");
| linux-master | drivers/video/fbdev/tridentfb.c |
/*
* linux/drivers/video/sa1100fb.c
*
* Copyright (C) 1999 Eric A. Thomas
* Based on acornfb.c Copyright (C) Russell King.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* StrongARM 1100 LCD Controller Frame Buffer Driver
*
* Please direct your questions and comments on this driver to the following
* email address:
*
* [email protected]
*
* Clean patches should be sent to the ARM Linux Patch System. Please see the
* following web page for more information:
*
* https://www.arm.linux.org.uk/developer/patches/info.shtml
*
* Thank you.
*
* Known problems:
* - With the Neponset plugged into an Assabet, LCD powerdown
* doesn't work (LCD stays powered up). Therefore we shouldn't
* blank the screen.
* - We don't limit the CPU clock rate nor the mode selection
* according to the available SDRAM bandwidth.
*
* Other notes:
* - Linear grayscale palettes and the kernel.
* Such code does not belong in the kernel. The kernel frame buffer
* drivers do not expect a linear colourmap, but a colourmap based on
* the VT100 standard mapping.
*
* If your _userspace_ requires a linear colourmap, then the setup of
* such a colourmap belongs _in userspace_, not in the kernel. Code
* to set the colourmap correctly from user space has been sent to
* David Neuer. It's around 8 lines of C code, plus another 4 to
* detect if we are using grayscale.
*
* - The following must never be specified in a panel definition:
* LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
*
* - The following should be specified:
* either LCCR0_Color or LCCR0_Mono
* either LCCR0_Sngl or LCCR0_Dual
* either LCCR0_Act or LCCR0_Pas
* either LCCR3_OutEnH or LCCD3_OutEnL
* either LCCR3_PixRsEdg or LCCR3_PixFlEdg
* either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
*
* Code Status:
* 1999/04/01:
* - Driver appears to be working for Brutus 320x200x8bpp mode. Other
* resolutions are working, but only the 8bpp mode is supported.
* Changes need to be made to the palette encode and decode routines
* to support 4 and 16 bpp modes.
* Driver is not designed to be a module. The FrameBuffer is statically
* allocated since dynamic allocation of a 300k buffer cannot be
* guaranteed.
*
* 1999/06/17:
* - FrameBuffer memory is now allocated at run-time when the
* driver is initialized.
*
* 2000/04/10: Nicolas Pitre <[email protected]>
* - Big cleanup for dynamic selection of machine type at run time.
*
* 2000/07/19: Jamey Hicks <[email protected]>
* - Support for Bitsy aka Compaq iPAQ H3600 added.
*
* 2000/08/07: Tak-Shing Chan <[email protected]>
* Jeff Sutherland <[email protected]>
* - Resolved an issue caused by a change made to the Assabet's PLD
* earlier this year which broke the framebuffer driver for newer
* Phase 4 Assabets. Some other parameters were changed to optimize
* for the Sharp display.
*
* 2000/08/09: Kunihiko IMAI <[email protected]>
* - XP860 support added
*
* 2000/08/19: Mark Huang <[email protected]>
* - Allows standard options to be passed on the kernel command line
* for most common passive displays.
*
* 2000/08/29:
* - s/save_flags_cli/local_irq_save/
* - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
*
* 2000/10/10: Erik Mouw <[email protected]>
* - Updated LART stuff. Fixed some minor bugs.
*
* 2000/10/30: Murphy Chen <[email protected]>
* - Pangolin support added
*
* 2000/10/31: Roman Jordan <[email protected]>
* - Huw Webpanel support added
*
* 2000/11/23: Eric Peng <[email protected]>
* - Freebird add
*
* 2001/02/07: Jamey Hicks <[email protected]>
* Cliff Brake <[email protected]>
* - Added PM callback
*
* 2001/05/26: <[email protected]>
* - Fix 16bpp so that (a) we use the right colours rather than some
* totally random colour depending on what was in page 0, and (b)
* we don't de-reference a NULL pointer.
* - remove duplicated implementation of consistent_alloc()
* - convert dma address types to dma_addr_t
* - remove unused 'montype' stuff
* - remove redundant zero inits of init_var after the initial
* memset.
* - remove allow_modeset (acornfb idea does not belong here)
*
* 2001/05/28: <[email protected]>
* - massive cleanup - move machine dependent data into structures
* - I've left various #warnings in - if you see one, and know
* the hardware concerned, please get in contact with me.
*
* 2001/05/31: <[email protected]>
* - Fix LCCR1 HSW value, fix all machine type specifications to
* keep values in line. (Please check your machine type specs)
*
* 2001/06/10: <[email protected]>
* - Fiddle with the LCD controller from task context only; mainly
* so that we can run with interrupts on, and sleep.
* - Convert #warnings into #errors. No pain, no gain. ;)
*
* 2001/06/14: <[email protected]>
* - Make the palette BPS value for 12bpp come out correctly.
* - Take notice of "greyscale" on any colour depth.
* - Make truecolor visuals use the RGB channel encoding information.
*
* 2001/07/02: <[email protected]>
* - Fix colourmap problems.
*
* 2001/07/13: <[email protected]>
* - Added support for the ICP LCD-Kit01 on LART. This LCD is
* manufactured by Prime View, model no V16C6448AB
*
* 2001/07/23: <[email protected]>
* - Hand merge version from handhelds.org CVS tree. See patch
* notes for 595/1 for more information.
* - Drop 12bpp (it's 16bpp with different colour register mappings).
* - This hardware can not do direct colour. Therefore we don't
* support it.
*
* 2001/07/27: <[email protected]>
* - Halve YRES on dual scan LCDs.
*
* 2001/08/22: <[email protected]>
* - Add b/w iPAQ pixclock value.
*
* 2001/10/12: <[email protected]>
* - Add patch 681/1 and clean up stork definitions.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <video/sa1100fb.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
/*
* Complain if VAR is out of range.
*/
#define DEBUG_VAR 1
#include "sa1100fb.h"
static const struct sa1100fb_rgb rgb_4 = {
.red = { .offset = 0, .length = 4, },
.green = { .offset = 0, .length = 4, },
.blue = { .offset = 0, .length = 4, },
.transp = { .offset = 0, .length = 0, },
};
static const struct sa1100fb_rgb rgb_8 = {
.red = { .offset = 0, .length = 8, },
.green = { .offset = 0, .length = 8, },
.blue = { .offset = 0, .length = 8, },
.transp = { .offset = 0, .length = 0, },
};
static const struct sa1100fb_rgb def_rgb_16 = {
.red = { .offset = 11, .length = 5, },
.green = { .offset = 5, .length = 6, },
.blue = { .offset = 0, .length = 5, },
.transp = { .offset = 0, .length = 0, },
};
static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
{
unsigned long flags;
local_irq_save(flags);
/*
* We need to handle two requests being made at the same time.
* There are two important cases:
* 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
* We must perform the unblanking, which will do our REENABLE for us.
* 2. When we are blanking, but immediately unblank before we have
* blanked. We do the "REENABLE" thing here as well, just to be sure.
*/
if (fbi->task_state == C_ENABLE && state == C_REENABLE)
state = (u_int) -1;
if (fbi->task_state == C_DISABLE && state == C_ENABLE)
state = C_REENABLE;
if (state != (u_int)-1) {
fbi->task_state = state;
schedule_work(&fbi->task);
}
local_irq_restore(flags);
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
/*
* Convert bits-per-pixel to a hardware palette PBS value.
*/
static inline u_int palette_pbs(struct fb_var_screeninfo *var)
{
int ret = 0;
switch (var->bits_per_pixel) {
case 4: ret = 0 << 12; break;
case 8: ret = 1 << 12; break;
case 16: ret = 2 << 12; break;
}
return ret;
}
static int
sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct sa1100fb_info *fbi =
container_of(info, struct sa1100fb_info, fb);
u_int val, ret = 1;
if (regno < fbi->palette_size) {
val = ((red >> 4) & 0xf00);
val |= ((green >> 8) & 0x0f0);
val |= ((blue >> 12) & 0x00f);
if (regno == 0)
val |= palette_pbs(&fbi->fb.var);
fbi->palette_cpu[regno] = val;
ret = 0;
}
return ret;
}
static int
sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct sa1100fb_info *fbi =
container_of(info, struct sa1100fb_info, fb);
unsigned int val;
int ret = 1;
/*
* If inverse mode was selected, invert all the colours
* rather than the register number. The register number
* is what you poke into the framebuffer to produce the
* colour you requested.
*/
if (fbi->inf->cmap_inverse) {
red = 0xffff - red;
green = 0xffff - green;
blue = 0xffff - blue;
}
/*
* If greyscale is true, then we convert the RGB value
* to greyscale no mater what visual we are using.
*/
if (fbi->fb.var.grayscale)
red = green = blue = (19595 * red + 38470 * green +
7471 * blue) >> 16;
switch (fbi->fb.fix.visual) {
case FB_VISUAL_TRUECOLOR:
/*
* 12 or 16-bit True Colour. We encode the RGB value
* according to the RGB bitfield information.
*/
if (regno < 16) {
val = chan_to_field(red, &fbi->fb.var.red);
val |= chan_to_field(green, &fbi->fb.var.green);
val |= chan_to_field(blue, &fbi->fb.var.blue);
fbi->pseudo_palette[regno] = val;
ret = 0;
}
break;
case FB_VISUAL_STATIC_PSEUDOCOLOR:
case FB_VISUAL_PSEUDOCOLOR:
ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
break;
}
return ret;
}
#ifdef CONFIG_CPU_FREQ
/*
* sa1100fb_display_dma_period()
* Calculate the minimum period (in picoseconds) between two DMA
* requests for the LCD controller. If we hit this, it means we're
* doing nothing but LCD DMA.
*/
static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
{
/*
* Period = pixclock * bits_per_byte * bytes_per_transfer
* / memory_bits_per_pixel;
*/
return var->pixclock * 8 * 16 / var->bits_per_pixel;
}
#endif
/*
* sa1100fb_check_var():
* Round up in the following order: bits_per_pixel, xres,
* yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
* bitfields, horizontal timing, vertical timing.
*/
static int
sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct sa1100fb_info *fbi =
container_of(info, struct sa1100fb_info, fb);
int rgbidx;
if (var->xres < MIN_XRES)
var->xres = MIN_XRES;
if (var->yres < MIN_YRES)
var->yres = MIN_YRES;
if (var->xres > fbi->inf->xres)
var->xres = fbi->inf->xres;
if (var->yres > fbi->inf->yres)
var->yres = fbi->inf->yres;
var->xres_virtual = max(var->xres_virtual, var->xres);
var->yres_virtual = max(var->yres_virtual, var->yres);
dev_dbg(fbi->dev, "var->bits_per_pixel=%d\n", var->bits_per_pixel);
switch (var->bits_per_pixel) {
case 4:
rgbidx = RGB_4;
break;
case 8:
rgbidx = RGB_8;
break;
case 16:
rgbidx = RGB_16;
break;
default:
return -EINVAL;
}
/*
* Copy the RGB parameters for this display
* from the machine specific parameters.
*/
var->red = fbi->rgb[rgbidx]->red;
var->green = fbi->rgb[rgbidx]->green;
var->blue = fbi->rgb[rgbidx]->blue;
var->transp = fbi->rgb[rgbidx]->transp;
dev_dbg(fbi->dev, "RGBT length = %d:%d:%d:%d\n",
var->red.length, var->green.length, var->blue.length,
var->transp.length);
dev_dbg(fbi->dev, "RGBT offset = %d:%d:%d:%d\n",
var->red.offset, var->green.offset, var->blue.offset,
var->transp.offset);
#ifdef CONFIG_CPU_FREQ
dev_dbg(fbi->dev, "dma period = %d ps, clock = %ld kHz\n",
sa1100fb_display_dma_period(var),
clk_get_rate(fbi->clk) / 1000);
#endif
return 0;
}
static void sa1100fb_set_visual(struct sa1100fb_info *fbi, u32 visual)
{
if (fbi->inf->set_visual)
fbi->inf->set_visual(visual);
}
/*
* sa1100fb_set_par():
* Set the user defined part of the display for the specified console
*/
static int sa1100fb_set_par(struct fb_info *info)
{
struct sa1100fb_info *fbi =
container_of(info, struct sa1100fb_info, fb);
struct fb_var_screeninfo *var = &info->var;
unsigned long palette_mem_size;
dev_dbg(fbi->dev, "set_par\n");
if (var->bits_per_pixel == 16)
fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
else if (!fbi->inf->cmap_static)
fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
else {
/*
* Some people have weird ideas about wanting static
* pseudocolor maps. I suspect their user space
* applications are broken.
*/
fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
}
fbi->fb.fix.line_length = var->xres_virtual *
var->bits_per_pixel / 8;
fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
palette_mem_size = fbi->palette_size * sizeof(u16);
dev_dbg(fbi->dev, "palette_mem_size = 0x%08lx\n", palette_mem_size);
fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
/*
* Set (any) board control register to handle new color depth
*/
sa1100fb_set_visual(fbi, fbi->fb.fix.visual);
sa1100fb_activate_var(var, fbi);
return 0;
}
#if 0
static int
sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
struct fb_info *info)
{
struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
/*
* Make sure the user isn't doing something stupid.
*/
if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->inf->cmap_static))
return -EINVAL;
return gen_set_cmap(cmap, kspc, con, info);
}
#endif
/*
* Formal definition of the VESA spec:
* On
* This refers to the state of the display when it is in full operation
* Stand-By
* This defines an optional operating state of minimal power reduction with
* the shortest recovery time
* Suspend
* This refers to a level of power management in which substantial power
* reduction is achieved by the display. The display can have a longer
* recovery time from this state than from the Stand-by state
* Off
* This indicates that the display is consuming the lowest level of power
* and is non-operational. Recovery from this state may optionally require
* the user to manually power on the monitor
*
* Now, the fbdev driver adds an additional state, (blank), where they
* turn off the video (maybe by colormap tricks), but don't mess with the
* video itself: think of it semantically between on and Stand-By.
*
* So here's what we should do in our fbdev blank routine:
*
* VESA_NO_BLANKING (mode 0) Video on, front/back light on
* VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
* VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
* VESA_POWERDOWN (mode 3) Video off, front/back light off
*
* This will match the matrox implementation.
*/
/*
* sa1100fb_blank():
* Blank the display by setting all palette values to zero. Note, the
* 12 and 16 bpp modes don't really use the palette, so this will not
* blank the display in all modes.
*/
static int sa1100fb_blank(int blank, struct fb_info *info)
{
struct sa1100fb_info *fbi =
container_of(info, struct sa1100fb_info, fb);
int i;
dev_dbg(fbi->dev, "sa1100fb_blank: blank=%d\n", blank);
switch (blank) {
case FB_BLANK_POWERDOWN:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_NORMAL:
if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
for (i = 0; i < fbi->palette_size; i++)
sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
sa1100fb_schedule_work(fbi, C_DISABLE);
break;
case FB_BLANK_UNBLANK:
if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
fb_set_cmap(&fbi->fb.cmap, info);
sa1100fb_schedule_work(fbi, C_ENABLE);
}
return 0;
}
static int sa1100fb_mmap(struct fb_info *info,
struct vm_area_struct *vma)
{
struct sa1100fb_info *fbi =
container_of(info, struct sa1100fb_info, fb);
unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
if (off < info->fix.smem_len) {
vma->vm_pgoff += 1; /* skip over the palette */
return dma_mmap_wc(fbi->dev, vma, fbi->map_cpu, fbi->map_dma,
fbi->map_size);
}
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
return vm_iomap_memory(vma, info->fix.mmio_start, info->fix.mmio_len);
}
static const struct fb_ops sa1100fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = sa1100fb_check_var,
.fb_set_par = sa1100fb_set_par,
// .fb_set_cmap = sa1100fb_set_cmap,
.fb_setcolreg = sa1100fb_setcolreg,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_blank = sa1100fb_blank,
.fb_mmap = sa1100fb_mmap,
};
/*
* Calculate the PCD value from the clock rate (in picoseconds).
* We take account of the PPCR clock setting.
*/
static inline unsigned int get_pcd(struct sa1100fb_info *fbi,
unsigned int pixclock)
{
unsigned int pcd = clk_get_rate(fbi->clk) / 100 / 1000;
pcd *= pixclock;
pcd /= 10000000;
return pcd + 1; /* make up for integer math truncations */
}
/*
* sa1100fb_activate_var():
* Configures LCD Controller based on entries in var parameter. Settings are
* only written to the controller if changes were made.
*/
static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
{
struct sa1100fb_lcd_reg new_regs;
u_int half_screen_size, yres, pcd;
u_long flags;
dev_dbg(fbi->dev, "Configuring SA1100 LCD\n");
dev_dbg(fbi->dev, "var: xres=%d hslen=%d lm=%d rm=%d\n",
var->xres, var->hsync_len,
var->left_margin, var->right_margin);
dev_dbg(fbi->dev, "var: yres=%d vslen=%d um=%d bm=%d\n",
var->yres, var->vsync_len,
var->upper_margin, var->lower_margin);
#if DEBUG_VAR
if (var->xres < 16 || var->xres > 1024)
dev_err(fbi->dev, "%s: invalid xres %d\n",
fbi->fb.fix.id, var->xres);
if (var->hsync_len < 1 || var->hsync_len > 64)
dev_err(fbi->dev, "%s: invalid hsync_len %d\n",
fbi->fb.fix.id, var->hsync_len);
if (var->left_margin < 1 || var->left_margin > 255)
dev_err(fbi->dev, "%s: invalid left_margin %d\n",
fbi->fb.fix.id, var->left_margin);
if (var->right_margin < 1 || var->right_margin > 255)
dev_err(fbi->dev, "%s: invalid right_margin %d\n",
fbi->fb.fix.id, var->right_margin);
if (var->yres < 1 || var->yres > 1024)
dev_err(fbi->dev, "%s: invalid yres %d\n",
fbi->fb.fix.id, var->yres);
if (var->vsync_len < 1 || var->vsync_len > 64)
dev_err(fbi->dev, "%s: invalid vsync_len %d\n",
fbi->fb.fix.id, var->vsync_len);
if (var->upper_margin < 0 || var->upper_margin > 255)
dev_err(fbi->dev, "%s: invalid upper_margin %d\n",
fbi->fb.fix.id, var->upper_margin);
if (var->lower_margin < 0 || var->lower_margin > 255)
dev_err(fbi->dev, "%s: invalid lower_margin %d\n",
fbi->fb.fix.id, var->lower_margin);
#endif
new_regs.lccr0 = fbi->inf->lccr0 |
LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
new_regs.lccr1 =
LCCR1_DisWdth(var->xres) +
LCCR1_HorSnchWdth(var->hsync_len) +
LCCR1_BegLnDel(var->left_margin) +
LCCR1_EndLnDel(var->right_margin);
/*
* If we have a dual scan LCD, then we need to halve
* the YRES parameter.
*/
yres = var->yres;
if (fbi->inf->lccr0 & LCCR0_Dual)
yres /= 2;
new_regs.lccr2 =
LCCR2_DisHght(yres) +
LCCR2_VrtSnchWdth(var->vsync_len) +
LCCR2_BegFrmDel(var->upper_margin) +
LCCR2_EndFrmDel(var->lower_margin);
pcd = get_pcd(fbi, var->pixclock);
new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->inf->lccr3 |
(var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
(var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
dev_dbg(fbi->dev, "nlccr0 = 0x%08lx\n", new_regs.lccr0);
dev_dbg(fbi->dev, "nlccr1 = 0x%08lx\n", new_regs.lccr1);
dev_dbg(fbi->dev, "nlccr2 = 0x%08lx\n", new_regs.lccr2);
dev_dbg(fbi->dev, "nlccr3 = 0x%08lx\n", new_regs.lccr3);
half_screen_size = var->bits_per_pixel;
half_screen_size = half_screen_size * var->xres * var->yres / 16;
/* Update shadow copy atomically */
local_irq_save(flags);
fbi->dbar1 = fbi->palette_dma;
fbi->dbar2 = fbi->screen_dma + half_screen_size;
fbi->reg_lccr0 = new_regs.lccr0;
fbi->reg_lccr1 = new_regs.lccr1;
fbi->reg_lccr2 = new_regs.lccr2;
fbi->reg_lccr3 = new_regs.lccr3;
local_irq_restore(flags);
/*
* Only update the registers if the controller is enabled
* and something has changed.
*/
if (readl_relaxed(fbi->base + LCCR0) != fbi->reg_lccr0 ||
readl_relaxed(fbi->base + LCCR1) != fbi->reg_lccr1 ||
readl_relaxed(fbi->base + LCCR2) != fbi->reg_lccr2 ||
readl_relaxed(fbi->base + LCCR3) != fbi->reg_lccr3 ||
readl_relaxed(fbi->base + DBAR1) != fbi->dbar1 ||
readl_relaxed(fbi->base + DBAR2) != fbi->dbar2)
sa1100fb_schedule_work(fbi, C_REENABLE);
return 0;
}
/*
* NOTE! The following functions are purely helpers for set_ctrlr_state.
* Do not call them directly; set_ctrlr_state does the correct serialisation
* to ensure that things happen in the right way 100% of time time.
* -- rmk
*/
static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
{
dev_dbg(fbi->dev, "backlight o%s\n", on ? "n" : "ff");
if (fbi->inf->backlight_power)
fbi->inf->backlight_power(on);
}
static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
{
dev_dbg(fbi->dev, "LCD power o%s\n", on ? "n" : "ff");
if (fbi->inf->lcd_power)
fbi->inf->lcd_power(on);
}
static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
{
u_int mask = 0;
/*
* Enable GPIO<9:2> for LCD use if:
* 1. Active display, or
* 2. Color Dual Passive display
*
* see table 11.8 on page 11-27 in the SA1100 manual
* -- Erik.
*
* SA1110 spec update nr. 25 says we can and should
* clear LDD15 to 12 for 4 or 8bpp modes with active
* panels.
*/
if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
(fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
if (fbi->fb.var.bits_per_pixel > 8 ||
(fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
}
if (mask) {
unsigned long flags;
/*
* SA-1100 requires the GPIO direction register set
* appropriately for the alternate function. Hence
* we set it here via bitmask rather than excessive
* fiddling via the GPIO subsystem - and even then
* we'll still have to deal with GAFR.
*/
local_irq_save(flags);
GPDR |= mask;
GAFR |= mask;
local_irq_restore(flags);
}
}
static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
{
dev_dbg(fbi->dev, "Enabling LCD controller\n");
/*
* Make sure the mode bits are present in the first palette entry
*/
fbi->palette_cpu[0] &= 0xcfff;
fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
/* enable LCD controller clock */
clk_prepare_enable(fbi->clk);
/* Sequence from 11.7.10 */
writel_relaxed(fbi->reg_lccr3, fbi->base + LCCR3);
writel_relaxed(fbi->reg_lccr2, fbi->base + LCCR2);
writel_relaxed(fbi->reg_lccr1, fbi->base + LCCR1);
writel_relaxed(fbi->reg_lccr0 & ~LCCR0_LEN, fbi->base + LCCR0);
writel_relaxed(fbi->dbar1, fbi->base + DBAR1);
writel_relaxed(fbi->dbar2, fbi->base + DBAR2);
writel_relaxed(fbi->reg_lccr0 | LCCR0_LEN, fbi->base + LCCR0);
if (fbi->shannon_lcden)
gpiod_set_value(fbi->shannon_lcden, 1);
dev_dbg(fbi->dev, "DBAR1: 0x%08x\n", readl_relaxed(fbi->base + DBAR1));
dev_dbg(fbi->dev, "DBAR2: 0x%08x\n", readl_relaxed(fbi->base + DBAR2));
dev_dbg(fbi->dev, "LCCR0: 0x%08x\n", readl_relaxed(fbi->base + LCCR0));
dev_dbg(fbi->dev, "LCCR1: 0x%08x\n", readl_relaxed(fbi->base + LCCR1));
dev_dbg(fbi->dev, "LCCR2: 0x%08x\n", readl_relaxed(fbi->base + LCCR2));
dev_dbg(fbi->dev, "LCCR3: 0x%08x\n", readl_relaxed(fbi->base + LCCR3));
}
static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
{
DECLARE_WAITQUEUE(wait, current);
u32 lccr0;
dev_dbg(fbi->dev, "Disabling LCD controller\n");
if (fbi->shannon_lcden)
gpiod_set_value(fbi->shannon_lcden, 0);
set_current_state(TASK_UNINTERRUPTIBLE);
add_wait_queue(&fbi->ctrlr_wait, &wait);
/* Clear LCD Status Register */
writel_relaxed(~0, fbi->base + LCSR);
lccr0 = readl_relaxed(fbi->base + LCCR0);
lccr0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
writel_relaxed(lccr0, fbi->base + LCCR0);
lccr0 &= ~LCCR0_LEN; /* Disable LCD Controller */
writel_relaxed(lccr0, fbi->base + LCCR0);
schedule_timeout(20 * HZ / 1000);
remove_wait_queue(&fbi->ctrlr_wait, &wait);
/* disable LCD controller clock */
clk_disable_unprepare(fbi->clk);
}
/*
* sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
*/
static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id)
{
struct sa1100fb_info *fbi = dev_id;
unsigned int lcsr = readl_relaxed(fbi->base + LCSR);
if (lcsr & LCSR_LDD) {
u32 lccr0 = readl_relaxed(fbi->base + LCCR0) | LCCR0_LDM;
writel_relaxed(lccr0, fbi->base + LCCR0);
wake_up(&fbi->ctrlr_wait);
}
writel_relaxed(lcsr, fbi->base + LCSR);
return IRQ_HANDLED;
}
/*
* This function must be called from task context only, since it will
* sleep when disabling the LCD controller, or if we get two contending
* processes trying to alter state.
*/
static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
{
u_int old_state;
mutex_lock(&fbi->ctrlr_lock);
old_state = fbi->state;
/*
* Hack around fbcon initialisation.
*/
if (old_state == C_STARTUP && state == C_REENABLE)
state = C_ENABLE;
switch (state) {
case C_DISABLE_CLKCHANGE:
/*
* Disable controller for clock change. If the
* controller is already disabled, then do nothing.
*/
if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
fbi->state = state;
sa1100fb_disable_controller(fbi);
}
break;
case C_DISABLE_PM:
case C_DISABLE:
/*
* Disable controller
*/
if (old_state != C_DISABLE) {
fbi->state = state;
__sa1100fb_backlight_power(fbi, 0);
if (old_state != C_DISABLE_CLKCHANGE)
sa1100fb_disable_controller(fbi);
__sa1100fb_lcd_power(fbi, 0);
}
break;
case C_ENABLE_CLKCHANGE:
/*
* Enable the controller after clock change. Only
* do this if we were disabled for the clock change.
*/
if (old_state == C_DISABLE_CLKCHANGE) {
fbi->state = C_ENABLE;
sa1100fb_enable_controller(fbi);
}
break;
case C_REENABLE:
/*
* Re-enable the controller only if it was already
* enabled. This is so we reprogram the control
* registers.
*/
if (old_state == C_ENABLE) {
sa1100fb_disable_controller(fbi);
sa1100fb_setup_gpio(fbi);
sa1100fb_enable_controller(fbi);
}
break;
case C_ENABLE_PM:
/*
* Re-enable the controller after PM. This is not
* perfect - think about the case where we were doing
* a clock change, and we suspended half-way through.
*/
if (old_state != C_DISABLE_PM)
break;
fallthrough;
case C_ENABLE:
/*
* Power up the LCD screen, enable controller, and
* turn on the backlight.
*/
if (old_state != C_ENABLE) {
fbi->state = C_ENABLE;
sa1100fb_setup_gpio(fbi);
__sa1100fb_lcd_power(fbi, 1);
sa1100fb_enable_controller(fbi);
__sa1100fb_backlight_power(fbi, 1);
}
break;
}
mutex_unlock(&fbi->ctrlr_lock);
}
/*
* Our LCD controller task (which is called when we blank or unblank)
* via keventd.
*/
static void sa1100fb_task(struct work_struct *w)
{
struct sa1100fb_info *fbi = container_of(w, struct sa1100fb_info, task);
u_int state = xchg(&fbi->task_state, -1);
set_ctrlr_state(fbi, state);
}
#ifdef CONFIG_CPU_FREQ
/*
* CPU clock speed change handler. We need to adjust the LCD timing
* parameters when the CPU clock is adjusted by the power management
* subsystem.
*/
static int
sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
void *data)
{
struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
u_int pcd;
switch (val) {
case CPUFREQ_PRECHANGE:
set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
break;
case CPUFREQ_POSTCHANGE:
pcd = get_pcd(fbi, fbi->fb.var.pixclock);
fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
break;
}
return 0;
}
#endif
#ifdef CONFIG_PM
/*
* Power management hooks. Note that we won't be called from IRQ context,
* unlike the blank functions above, so we may sleep.
*/
static int sa1100fb_suspend(struct platform_device *dev, pm_message_t state)
{
struct sa1100fb_info *fbi = platform_get_drvdata(dev);
set_ctrlr_state(fbi, C_DISABLE_PM);
return 0;
}
static int sa1100fb_resume(struct platform_device *dev)
{
struct sa1100fb_info *fbi = platform_get_drvdata(dev);
set_ctrlr_state(fbi, C_ENABLE_PM);
return 0;
}
#else
#define sa1100fb_suspend NULL
#define sa1100fb_resume NULL
#endif
/*
* sa1100fb_map_video_memory():
* Allocates the DRAM memory for the frame buffer. This buffer is
* remapped into a non-cached, non-buffered, memory region to
* allow palette and pixel writes to occur without flushing the
* cache. Once this area is remapped, all virtual memory
* access to the video memory should occur at the new region.
*/
static int sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
{
/*
* We reserve one page for the palette, plus the size
* of the framebuffer.
*/
fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
fbi->map_cpu = dma_alloc_wc(fbi->dev, fbi->map_size, &fbi->map_dma,
GFP_KERNEL);
if (fbi->map_cpu) {
fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
/*
* FIXME: this is actually the wrong thing to place in
* smem_start. But fbdev suffers from the problem that
* it needs an API which doesn't exist (in this case,
* dma_writecombine_mmap)
*/
fbi->fb.fix.smem_start = fbi->screen_dma;
}
return fbi->map_cpu ? 0 : -ENOMEM;
}
/* Fake monspecs to fill in fbinfo structure */
static const struct fb_monspecs monspecs = {
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 50,
.vfmax = 65,
};
static struct sa1100fb_info *sa1100fb_init_fbinfo(struct device *dev)
{
struct sa1100fb_mach_info *inf = dev_get_platdata(dev);
struct sa1100fb_info *fbi;
unsigned i;
fbi = devm_kzalloc(dev, sizeof(struct sa1100fb_info), GFP_KERNEL);
if (!fbi)
return NULL;
fbi->dev = dev;
strcpy(fbi->fb.fix.id, SA1100_NAME);
fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fb.fix.type_aux = 0;
fbi->fb.fix.xpanstep = 0;
fbi->fb.fix.ypanstep = 0;
fbi->fb.fix.ywrapstep = 0;
fbi->fb.fix.accel = FB_ACCEL_NONE;
fbi->fb.var.nonstd = 0;
fbi->fb.var.activate = FB_ACTIVATE_NOW;
fbi->fb.var.height = -1;
fbi->fb.var.width = -1;
fbi->fb.var.accel_flags = 0;
fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
fbi->fb.fbops = &sa1100fb_ops;
fbi->fb.monspecs = monspecs;
fbi->fb.pseudo_palette = fbi->pseudo_palette;
fbi->rgb[RGB_4] = &rgb_4;
fbi->rgb[RGB_8] = &rgb_8;
fbi->rgb[RGB_16] = &def_rgb_16;
/*
* People just don't seem to get this. We don't support
* anything but correct entries now, so panic if someone
* does something stupid.
*/
if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
inf->pixclock == 0)
panic("sa1100fb error: invalid LCCR3 fields set or zero "
"pixclock.");
fbi->fb.var.xres = inf->xres;
fbi->fb.var.xres_virtual = inf->xres;
fbi->fb.var.yres = inf->yres;
fbi->fb.var.yres_virtual = inf->yres;
fbi->fb.var.bits_per_pixel = inf->bpp;
fbi->fb.var.pixclock = inf->pixclock;
fbi->fb.var.hsync_len = inf->hsync_len;
fbi->fb.var.left_margin = inf->left_margin;
fbi->fb.var.right_margin = inf->right_margin;
fbi->fb.var.vsync_len = inf->vsync_len;
fbi->fb.var.upper_margin = inf->upper_margin;
fbi->fb.var.lower_margin = inf->lower_margin;
fbi->fb.var.sync = inf->sync;
fbi->fb.var.grayscale = inf->cmap_greyscale;
fbi->state = C_STARTUP;
fbi->task_state = (u_char)-1;
fbi->fb.fix.smem_len = inf->xres * inf->yres *
inf->bpp / 8;
fbi->inf = inf;
/* Copy the RGB bitfield overrides */
for (i = 0; i < NR_RGB; i++)
if (inf->rgb[i])
fbi->rgb[i] = inf->rgb[i];
init_waitqueue_head(&fbi->ctrlr_wait);
INIT_WORK(&fbi->task, sa1100fb_task);
mutex_init(&fbi->ctrlr_lock);
return fbi;
}
static int sa1100fb_probe(struct platform_device *pdev)
{
struct sa1100fb_info *fbi;
int ret, irq;
if (!dev_get_platdata(&pdev->dev)) {
dev_err(&pdev->dev, "no platform LCD data\n");
return -EINVAL;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return -EINVAL;
fbi = sa1100fb_init_fbinfo(&pdev->dev);
if (!fbi)
return -ENOMEM;
fbi->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(fbi->base))
return PTR_ERR(fbi->base);
fbi->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(fbi->clk))
return PTR_ERR(fbi->clk);
ret = devm_request_irq(&pdev->dev, irq, sa1100fb_handle_irq, 0,
"LCD", fbi);
if (ret) {
dev_err(&pdev->dev, "request_irq failed: %d\n", ret);
return ret;
}
fbi->shannon_lcden = gpiod_get_optional(&pdev->dev, "shannon-lcden",
GPIOD_OUT_LOW);
if (IS_ERR(fbi->shannon_lcden))
return PTR_ERR(fbi->shannon_lcden);
/* Initialize video memory */
ret = sa1100fb_map_video_memory(fbi);
if (ret)
return ret;
/*
* This makes sure that our colour bitfield
* descriptors are correctly initialised.
*/
sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
platform_set_drvdata(pdev, fbi);
ret = register_framebuffer(&fbi->fb);
if (ret < 0) {
dma_free_wc(fbi->dev, fbi->map_size, fbi->map_cpu,
fbi->map_dma);
return ret;
}
#ifdef CONFIG_CPU_FREQ
fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
#endif
/* This driver cannot be unloaded at the moment */
return 0;
}
static struct platform_driver sa1100fb_driver = {
.probe = sa1100fb_probe,
.suspend = sa1100fb_suspend,
.resume = sa1100fb_resume,
.driver = {
.name = "sa11x0-fb",
},
};
int __init sa1100fb_init(void)
{
if (fb_get_options("sa1100fb", NULL))
return -ENODEV;
return platform_driver_register(&sa1100fb_driver);
}
module_init(sa1100fb_init);
MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/sa1100fb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (C) 2012 Intel, Inc.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/acpi.h>
enum {
FB_GET_WIDTH = 0x00,
FB_GET_HEIGHT = 0x04,
FB_INT_STATUS = 0x08,
FB_INT_ENABLE = 0x0c,
FB_SET_BASE = 0x10,
FB_SET_ROTATION = 0x14,
FB_SET_BLANK = 0x18,
FB_GET_PHYS_WIDTH = 0x1c,
FB_GET_PHYS_HEIGHT = 0x20,
FB_INT_VSYNC = 1U << 0,
FB_INT_BASE_UPDATE_DONE = 1U << 1
};
struct goldfish_fb {
void __iomem *reg_base;
int irq;
spinlock_t lock;
wait_queue_head_t wait;
int base_update_count;
int rotation;
struct fb_info fb;
u32 cmap[16];
};
static irqreturn_t goldfish_fb_interrupt(int irq, void *dev_id)
{
unsigned long irq_flags;
struct goldfish_fb *fb = dev_id;
u32 status;
spin_lock_irqsave(&fb->lock, irq_flags);
status = readl(fb->reg_base + FB_INT_STATUS);
if (status & FB_INT_BASE_UPDATE_DONE) {
fb->base_update_count++;
wake_up(&fb->wait);
}
spin_unlock_irqrestore(&fb->lock, irq_flags);
return status ? IRQ_HANDLED : IRQ_NONE;
}
static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
{
unsigned int mask = (1 << bf->length) - 1;
return (val >> (16 - bf->length) & mask) << bf->offset;
}
static int
goldfish_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
unsigned int blue, unsigned int transp, struct fb_info *info)
{
struct goldfish_fb *fb = container_of(info, struct goldfish_fb, fb);
if (regno < 16) {
fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
convert_bitfield(blue, &fb->fb.var.blue) |
convert_bitfield(green, &fb->fb.var.green) |
convert_bitfield(red, &fb->fb.var.red);
return 0;
} else {
return 1;
}
}
static int goldfish_fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if ((var->rotate & 1) != (info->var.rotate & 1)) {
if ((var->xres != info->var.yres) ||
(var->yres != info->var.xres) ||
(var->xres_virtual != info->var.yres) ||
(var->yres_virtual > info->var.xres * 2) ||
(var->yres_virtual < info->var.xres)) {
return -EINVAL;
}
} else {
if ((var->xres != info->var.xres) ||
(var->yres != info->var.yres) ||
(var->xres_virtual != info->var.xres) ||
(var->yres_virtual > info->var.yres * 2) ||
(var->yres_virtual < info->var.yres)) {
return -EINVAL;
}
}
if ((var->xoffset != info->var.xoffset) ||
(var->bits_per_pixel != info->var.bits_per_pixel) ||
(var->grayscale != info->var.grayscale)) {
return -EINVAL;
}
return 0;
}
static int goldfish_fb_set_par(struct fb_info *info)
{
struct goldfish_fb *fb = container_of(info, struct goldfish_fb, fb);
if (fb->rotation != fb->fb.var.rotate) {
info->fix.line_length = info->var.xres * 2;
fb->rotation = fb->fb.var.rotate;
writel(fb->rotation, fb->reg_base + FB_SET_ROTATION);
}
return 0;
}
static int goldfish_fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
unsigned long irq_flags;
int base_update_count;
struct goldfish_fb *fb = container_of(info, struct goldfish_fb, fb);
spin_lock_irqsave(&fb->lock, irq_flags);
base_update_count = fb->base_update_count;
writel(fb->fb.fix.smem_start + fb->fb.var.xres * 2 * var->yoffset,
fb->reg_base + FB_SET_BASE);
spin_unlock_irqrestore(&fb->lock, irq_flags);
wait_event_timeout(fb->wait,
fb->base_update_count != base_update_count, HZ / 15);
if (fb->base_update_count == base_update_count)
pr_err("%s: timeout waiting for base update\n", __func__);
return 0;
}
static int goldfish_fb_blank(int blank, struct fb_info *info)
{
struct goldfish_fb *fb = container_of(info, struct goldfish_fb, fb);
switch (blank) {
case FB_BLANK_NORMAL:
writel(1, fb->reg_base + FB_SET_BLANK);
break;
case FB_BLANK_UNBLANK:
writel(0, fb->reg_base + FB_SET_BLANK);
break;
}
return 0;
}
static const struct fb_ops goldfish_fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = goldfish_fb_check_var,
.fb_set_par = goldfish_fb_set_par,
.fb_setcolreg = goldfish_fb_setcolreg,
.fb_pan_display = goldfish_fb_pan_display,
.fb_blank = goldfish_fb_blank,
};
static int goldfish_fb_probe(struct platform_device *pdev)
{
int ret;
struct resource *r;
struct goldfish_fb *fb;
size_t framesize;
u32 width, height;
dma_addr_t fbpaddr;
fb = kzalloc(sizeof(*fb), GFP_KERNEL);
if (fb == NULL) {
ret = -ENOMEM;
goto err_fb_alloc_failed;
}
spin_lock_init(&fb->lock);
init_waitqueue_head(&fb->wait);
platform_set_drvdata(pdev, fb);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (r == NULL) {
ret = -ENODEV;
goto err_no_io_base;
}
fb->reg_base = ioremap(r->start, PAGE_SIZE);
if (fb->reg_base == NULL) {
ret = -ENOMEM;
goto err_no_io_base;
}
fb->irq = platform_get_irq(pdev, 0);
if (fb->irq < 0) {
ret = fb->irq;
goto err_no_irq;
}
width = readl(fb->reg_base + FB_GET_WIDTH);
height = readl(fb->reg_base + FB_GET_HEIGHT);
fb->fb.fbops = &goldfish_fb_ops;
fb->fb.pseudo_palette = fb->cmap;
fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
fb->fb.fix.line_length = width * 2;
fb->fb.fix.accel = FB_ACCEL_NONE;
fb->fb.fix.ypanstep = 1;
fb->fb.var.xres = width;
fb->fb.var.yres = height;
fb->fb.var.xres_virtual = width;
fb->fb.var.yres_virtual = height * 2;
fb->fb.var.bits_per_pixel = 16;
fb->fb.var.activate = FB_ACTIVATE_NOW;
fb->fb.var.height = readl(fb->reg_base + FB_GET_PHYS_HEIGHT);
fb->fb.var.width = readl(fb->reg_base + FB_GET_PHYS_WIDTH);
fb->fb.var.pixclock = 0;
fb->fb.var.red.offset = 11;
fb->fb.var.red.length = 5;
fb->fb.var.green.offset = 5;
fb->fb.var.green.length = 6;
fb->fb.var.blue.offset = 0;
fb->fb.var.blue.length = 5;
framesize = width * height * 2 * 2;
fb->fb.screen_base = (char __force __iomem *)dma_alloc_coherent(
&pdev->dev, framesize,
&fbpaddr, GFP_KERNEL);
pr_debug("allocating frame buffer %d * %d, got %p\n",
width, height, fb->fb.screen_base);
if (fb->fb.screen_base == NULL) {
ret = -ENOMEM;
goto err_alloc_screen_base_failed;
}
fb->fb.fix.smem_start = fbpaddr;
fb->fb.fix.smem_len = framesize;
ret = fb_set_var(&fb->fb, &fb->fb.var);
if (ret)
goto err_fb_set_var_failed;
ret = request_irq(fb->irq, goldfish_fb_interrupt, IRQF_SHARED,
pdev->name, fb);
if (ret)
goto err_request_irq_failed;
writel(FB_INT_BASE_UPDATE_DONE, fb->reg_base + FB_INT_ENABLE);
goldfish_fb_pan_display(&fb->fb.var, &fb->fb); /* updates base */
ret = register_framebuffer(&fb->fb);
if (ret)
goto err_register_framebuffer_failed;
return 0;
err_register_framebuffer_failed:
free_irq(fb->irq, fb);
err_request_irq_failed:
err_fb_set_var_failed:
dma_free_coherent(&pdev->dev, framesize,
(void *)fb->fb.screen_base,
fb->fb.fix.smem_start);
err_alloc_screen_base_failed:
err_no_irq:
iounmap(fb->reg_base);
err_no_io_base:
kfree(fb);
err_fb_alloc_failed:
return ret;
}
static void goldfish_fb_remove(struct platform_device *pdev)
{
size_t framesize;
struct goldfish_fb *fb = platform_get_drvdata(pdev);
framesize = fb->fb.var.xres_virtual * fb->fb.var.yres_virtual * 2;
unregister_framebuffer(&fb->fb);
free_irq(fb->irq, fb);
dma_free_coherent(&pdev->dev, framesize, (void *)fb->fb.screen_base,
fb->fb.fix.smem_start);
iounmap(fb->reg_base);
kfree(fb);
}
static const struct of_device_id goldfish_fb_of_match[] = {
{ .compatible = "google,goldfish-fb", },
{},
};
MODULE_DEVICE_TABLE(of, goldfish_fb_of_match);
#ifdef CONFIG_ACPI
static const struct acpi_device_id goldfish_fb_acpi_match[] = {
{ "GFSH0004", 0 },
{ },
};
MODULE_DEVICE_TABLE(acpi, goldfish_fb_acpi_match);
#endif
static struct platform_driver goldfish_fb_driver = {
.probe = goldfish_fb_probe,
.remove_new = goldfish_fb_remove,
.driver = {
.name = "goldfish_fb",
.of_match_table = goldfish_fb_of_match,
.acpi_match_table = ACPI_PTR(goldfish_fb_acpi_match),
}
};
module_platform_driver(goldfish_fb_driver);
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/goldfishfb.c |
/*
* linux/drivers/video/iplan2p2.c -- Low level frame buffer operations for
* interleaved bitplanes à la Atari (2
* planes, 2 bytes interleave)
*
* Created 5 Apr 1997 by Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/setup.h>
#include "atafb.h"
#define BPL 2
#include "atafb_utils.h"
void atafb_iplan2p2_copyarea(struct fb_info *info, u_long next_line,
int sy, int sx, int dy, int dx,
int height, int width)
{
/* bmove() has to distinguish two major cases: If both, source and
* destination, start at even addresses or both are at odd
* addresses, just the first odd and last even column (if present)
* require special treatment (memmove_col()). The rest between
* then can be copied by normal operations, because all adjacent
* bytes are affected and are to be stored in the same order.
* The pathological case is when the move should go from an odd
* address to an even or vice versa. Since the bytes in the plane
* words must be assembled in new order, it seems wisest to make
* all movements by memmove_col().
*/
u8 *src, *dst;
u32 *s, *d;
int w, l , i, j;
u_int colsize;
u_int upwards = (dy < sy) || (dy == sy && dx < sx);
colsize = height;
if (!((sx ^ dx) & 15)) {
/* odd->odd or even->even */
if (upwards) {
src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL);
if (sx & 15) {
memmove32_col(dst, src, 0xff00ff, height, next_line - BPL * 2);
src += BPL * 2;
dst += BPL * 2;
width -= 8;
}
w = width >> 4;
if (w) {
s = (u32 *)src;
d = (u32 *)dst;
w *= BPL / 2;
l = next_line - w * 4;
for (j = height; j > 0; j--) {
for (i = w; i > 0; i--)
*d++ = *s++;
s = (u32 *)((u8 *)s + l);
d = (u32 *)((u8 *)d + l);
}
}
if (width & 15)
memmove32_col(dst + width / (8 / BPL), src + width / (8 / BPL),
0xff00ff00, height, next_line - BPL * 2);
} else {
src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL);
if ((sx + width) & 15) {
src -= BPL * 2;
dst -= BPL * 2;
memmove32_col(dst, src, 0xff00ff00, colsize, -next_line - BPL * 2);
width -= 8;
}
w = width >> 4;
if (w) {
s = (u32 *)src;
d = (u32 *)dst;
w *= BPL / 2;
l = next_line - w * 4;
for (j = height; j > 0; j--) {
for (i = w; i > 0; i--)
*--d = *--s;
s = (u32 *)((u8 *)s - l);
d = (u32 *)((u8 *)d - l);
}
}
if (sx & 15)
memmove32_col(dst - (width - 16) / (8 / BPL),
src - (width - 16) / (8 / BPL),
0xff00ff, colsize, -next_line - BPL * 2);
}
} else {
/* odd->even or even->odd */
if (upwards) {
u32 *src32, *dst32;
u32 pval[4], v, v1, mask;
int i, j, w, f;
src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL);
mask = 0xff00ff00;
f = 0;
w = width;
if (sx & 15) {
f = 1;
w += 8;
}
if ((sx + width) & 15)
f |= 2;
w >>= 4;
for (i = height; i; i--) {
src32 = (u32 *)src;
dst32 = (u32 *)dst;
if (f & 1) {
pval[0] = (*src32++ << 8) & mask;
} else {
pval[0] = dst32[0] & mask;
}
for (j = w; j > 0; j--) {
v = *src32++;
v1 = v & mask;
*dst32++ = pval[0] | (v1 >> 8);
pval[0] = (v ^ v1) << 8;
}
if (f & 2) {
dst32[0] = (dst32[0] & mask) | pval[0];
}
src += next_line;
dst += next_line;
}
} else {
u32 *src32, *dst32;
u32 pval[4], v, v1, mask;
int i, j, w, f;
src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL);
mask = 0xff00ff;
f = 0;
w = width;
if ((dx + width) & 15)
f = 1;
if (sx & 15) {
f |= 2;
w += 8;
}
w >>= 4;
for (i = height; i; i--) {
src32 = (u32 *)src;
dst32 = (u32 *)dst;
if (f & 1) {
pval[0] = dst32[-1] & mask;
} else {
pval[0] = (*--src32 >> 8) & mask;
}
for (j = w; j > 0; j--) {
v = *--src32;
v1 = v & mask;
*--dst32 = pval[0] | (v1 << 8);
pval[0] = (v ^ v1) >> 8;
}
if (!(f & 2)) {
dst32[-1] = (dst32[-1] & mask) | pval[0];
}
src -= next_line;
dst -= next_line;
}
}
}
}
void atafb_iplan2p2_fillrect(struct fb_info *info, u_long next_line, u32 color,
int sy, int sx, int height, int width)
{
u32 *dest;
int rows, i;
u32 cval[4];
dest = (u32 *)(info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL));
if (sx & 15) {
u8 *dest8 = (u8 *)dest + 1;
expand8_col2mask(color, cval);
for (i = height; i; i--) {
fill8_col(dest8, cval);
dest8 += next_line;
}
dest += BPL / 2;
width -= 8;
}
expand16_col2mask(color, cval);
rows = width >> 4;
if (rows) {
u32 *d = dest;
u32 off = next_line - rows * BPL * 2;
for (i = height; i; i--) {
d = fill16_col(d, rows, cval);
d = (u32 *)((long)d + off);
}
dest += rows * BPL / 2;
width &= 15;
}
if (width) {
u8 *dest8 = (u8 *)dest;
expand8_col2mask(color, cval);
for (i = height; i; i--) {
fill8_col(dest8, cval);
dest8 += next_line;
}
}
}
void atafb_iplan2p2_linefill(struct fb_info *info, u_long next_line,
int dy, int dx, u32 width,
const u8 *data, u32 bgcolor, u32 fgcolor)
{
u32 *dest;
const u16 *data16;
int rows;
u32 fgm[4], bgm[4], m;
dest = (u32 *)(info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL));
if (dx & 15) {
fill8_2col((u8 *)dest + 1, fgcolor, bgcolor, *data++);
dest += BPL / 2;
width -= 8;
}
if (width >= 16) {
data16 = (const u16 *)data;
expand16_2col2mask(fgcolor, bgcolor, fgm, bgm);
for (rows = width / 16; rows; rows--) {
u16 d = *data16++;
m = d | ((u32)d << 16);
*dest++ = (m & fgm[0]) ^ bgm[0];
}
data = (const u8 *)data16;
width &= 15;
}
if (width)
fill8_2col((u8 *)dest, fgcolor, bgcolor, *data);
}
| linux-master | drivers/video/fbdev/atafb_iplan2p2.c |
// SPDX-License-Identifier: GPL-2.0
/*
* SH7760/SH7763 LCDC Framebuffer driver.
*
* (c) 2006-2008 MSC Vertriebsges.m.b.H.,
* Manuel Lauss <[email protected]>
* (c) 2008 Nobuhiro Iwamatsu <[email protected]>
*
* PLEASE HAVE A LOOK AT Documentation/fb/sh7760fb.rst!
*
* Thanks to Siegfried Schaefer <s.schaefer at schaefer-edv.de>
* for his original source and testing!
*
* sh7760_setcolreg get from drivers/video/sh_mobile_lcdcfb.c
*/
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/fb.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <asm/sh7760fb.h>
struct sh7760fb_par {
void __iomem *base;
int irq;
struct sh7760fb_platdata *pd; /* display information */
dma_addr_t fbdma; /* physical address */
int rot; /* rotation enabled? */
u32 pseudo_palette[16];
struct platform_device *dev;
struct resource *ioarea;
struct completion vsync; /* vsync irq event */
};
static irqreturn_t sh7760fb_irq(int irq, void *data)
{
struct completion *c = data;
complete(c);
return IRQ_HANDLED;
}
/* wait_for_lps - wait until power supply has reached a certain state. */
static int wait_for_lps(struct sh7760fb_par *par, int val)
{
int i = 100;
while (--i && ((ioread16(par->base + LDPMMR) & 3) != val))
msleep(1);
if (i <= 0)
return -ETIMEDOUT;
return 0;
}
/* en/disable the LCDC */
static int sh7760fb_blank(int blank, struct fb_info *info)
{
struct sh7760fb_par *par = info->par;
struct sh7760fb_platdata *pd = par->pd;
unsigned short cntr = ioread16(par->base + LDCNTR);
unsigned short intr = ioread16(par->base + LDINTR);
int lps;
if (blank == FB_BLANK_UNBLANK) {
intr |= VINT_START;
cntr = LDCNTR_DON2 | LDCNTR_DON;
lps = 3;
} else {
intr &= ~VINT_START;
cntr = LDCNTR_DON2;
lps = 0;
}
if (pd->blank)
pd->blank(blank);
iowrite16(intr, par->base + LDINTR);
iowrite16(cntr, par->base + LDCNTR);
return wait_for_lps(par, lps);
}
static int sh7760_setcolreg (u_int regno,
u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
u32 *palette = info->pseudo_palette;
if (regno >= 16)
return -EINVAL;
/* only FB_VISUAL_TRUECOLOR supported */
red >>= 16 - info->var.red.length;
green >>= 16 - info->var.green.length;
blue >>= 16 - info->var.blue.length;
transp >>= 16 - info->var.transp.length;
palette[regno] = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
return 0;
}
static int sh7760fb_get_color_info(struct fb_info *info,
u16 lddfr, int *bpp, int *gray)
{
int lbpp, lgray;
lgray = lbpp = 0;
switch (lddfr & LDDFR_COLOR_MASK) {
case LDDFR_1BPP_MONO:
lgray = 1;
lbpp = 1;
break;
case LDDFR_2BPP_MONO:
lgray = 1;
lbpp = 2;
break;
case LDDFR_4BPP_MONO:
lgray = 1;
fallthrough;
case LDDFR_4BPP:
lbpp = 4;
break;
case LDDFR_6BPP_MONO:
lgray = 1;
fallthrough;
case LDDFR_8BPP:
lbpp = 8;
break;
case LDDFR_16BPP_RGB555:
case LDDFR_16BPP_RGB565:
lbpp = 16;
lgray = 0;
break;
default:
fb_dbg(info, "unsupported LDDFR bit depth.\n");
return -EINVAL;
}
if (bpp)
*bpp = lbpp;
if (gray)
*gray = lgray;
return 0;
}
static int sh7760fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct fb_fix_screeninfo *fix = &info->fix;
struct sh7760fb_par *par = info->par;
int ret, bpp;
/* get color info from register value */
ret = sh7760fb_get_color_info(info, par->pd->lddfr, &bpp, NULL);
if (ret)
return ret;
var->bits_per_pixel = bpp;
if ((var->grayscale) && (var->bits_per_pixel == 1))
fix->visual = FB_VISUAL_MONO10;
else if (var->bits_per_pixel >= 15)
fix->visual = FB_VISUAL_TRUECOLOR;
else
fix->visual = FB_VISUAL_PSEUDOCOLOR;
/* TODO: add some more validation here */
return 0;
}
/*
* sh7760fb_set_par - set videomode.
*
* NOTE: The rotation, grayscale and DSTN codepaths are
* totally untested!
*/
static int sh7760fb_set_par(struct fb_info *info)
{
struct sh7760fb_par *par = info->par;
struct fb_videomode *vm = par->pd->def_mode;
unsigned long sbase, dstn_off, ldsarl, stride;
unsigned short hsynp, hsynw, htcn, hdcn;
unsigned short vsynp, vsynw, vtln, vdln;
unsigned short lddfr, ldmtr;
int ret, bpp, gray;
par->rot = par->pd->rotate;
/* rotate only works with xres <= 320 */
if (par->rot && (vm->xres > 320)) {
fb_dbg(info, "rotation disabled due to display size\n");
par->rot = 0;
}
/* calculate LCDC reg vals from display parameters */
hsynp = vm->right_margin + vm->xres;
hsynw = vm->hsync_len;
htcn = vm->left_margin + hsynp + hsynw;
hdcn = vm->xres;
vsynp = vm->lower_margin + vm->yres;
vsynw = vm->vsync_len;
vtln = vm->upper_margin + vsynp + vsynw;
vdln = vm->yres;
/* get color info from register value */
ret = sh7760fb_get_color_info(info, par->pd->lddfr, &bpp, &gray);
if (ret)
return ret;
fb_dbg(info, "%dx%d %dbpp %s (orientation %s)\n", hdcn,
vdln, bpp, gray ? "grayscale" : "color",
par->rot ? "rotated" : "normal");
#ifdef CONFIG_CPU_LITTLE_ENDIAN
lddfr = par->pd->lddfr | (1 << 8);
#else
lddfr = par->pd->lddfr & ~(1 << 8);
#endif
ldmtr = par->pd->ldmtr;
if (!(vm->sync & FB_SYNC_HOR_HIGH_ACT))
ldmtr |= LDMTR_CL1POL;
if (!(vm->sync & FB_SYNC_VERT_HIGH_ACT))
ldmtr |= LDMTR_FLMPOL;
/* shut down LCDC before changing display parameters */
sh7760fb_blank(FB_BLANK_POWERDOWN, info);
iowrite16(par->pd->ldickr, par->base + LDICKR); /* pixclock */
iowrite16(ldmtr, par->base + LDMTR); /* polarities */
iowrite16(lddfr, par->base + LDDFR); /* color/depth */
iowrite16((par->rot ? 1 << 13 : 0), par->base + LDSMR); /* rotate */
iowrite16(par->pd->ldpmmr, par->base + LDPMMR); /* Power Management */
iowrite16(par->pd->ldpspr, par->base + LDPSPR); /* Power Supply Ctrl */
/* display resolution */
iowrite16(((htcn >> 3) - 1) | (((hdcn >> 3) - 1) << 8),
par->base + LDHCNR);
iowrite16(vdln - 1, par->base + LDVDLNR);
iowrite16(vtln - 1, par->base + LDVTLNR);
/* h/v sync signals */
iowrite16((vsynp - 1) | ((vsynw - 1) << 12), par->base + LDVSYNR);
iowrite16(((hsynp >> 3) - 1) | (((hsynw >> 3) - 1) << 12),
par->base + LDHSYNR);
/* AC modulation sig */
iowrite16(par->pd->ldaclnr, par->base + LDACLNR);
stride = (par->rot) ? vtln : hdcn;
if (!gray)
stride *= (bpp + 7) >> 3;
else {
if (bpp == 1)
stride >>= 3;
else if (bpp == 2)
stride >>= 2;
else if (bpp == 4)
stride >>= 1;
/* 6 bpp == 8 bpp */
}
/* if rotated, stride must be power of 2 */
if (par->rot) {
unsigned long bit = 1 << 31;
while (bit) {
if (stride & bit)
break;
bit >>= 1;
}
if (stride & ~bit)
stride = bit << 1; /* not P-o-2, round up */
}
iowrite16(stride, par->base + LDLAOR);
/* set display mem start address */
sbase = (unsigned long)par->fbdma;
if (par->rot)
sbase += (hdcn - 1) * stride;
iowrite32(sbase, par->base + LDSARU);
/*
* for DSTN need to set address for lower half.
* I (mlau) don't know which address to set it to,
* so I guessed at (stride * yres/2).
*/
if (((ldmtr & 0x003f) >= LDMTR_DSTN_MONO_8) &&
((ldmtr & 0x003f) <= LDMTR_DSTN_COLOR_16)) {
fb_dbg(info, " ***** DSTN untested! *****\n");
dstn_off = stride;
if (par->rot)
dstn_off *= hdcn >> 1;
else
dstn_off *= vdln >> 1;
ldsarl = sbase + dstn_off;
} else
ldsarl = 0;
iowrite32(ldsarl, par->base + LDSARL); /* mem for lower half of DSTN */
info->fix.line_length = stride;
sh7760fb_check_var(&info->var, info);
sh7760fb_blank(FB_BLANK_UNBLANK, info); /* panel on! */
fb_dbg(info, "hdcn : %6d htcn : %6d\n", hdcn, htcn);
fb_dbg(info, "hsynw : %6d hsynp : %6d\n", hsynw, hsynp);
fb_dbg(info, "vdln : %6d vtln : %6d\n", vdln, vtln);
fb_dbg(info, "vsynw : %6d vsynp : %6d\n", vsynw, vsynp);
fb_dbg(info, "clksrc: %6d clkdiv: %6d\n",
(par->pd->ldickr >> 12) & 3, par->pd->ldickr & 0x1f);
fb_dbg(info, "ldpmmr: 0x%04x ldpspr: 0x%04x\n", par->pd->ldpmmr,
par->pd->ldpspr);
fb_dbg(info, "ldmtr : 0x%04x lddfr : 0x%04x\n", ldmtr, lddfr);
fb_dbg(info, "ldlaor: %ld\n", stride);
fb_dbg(info, "ldsaru: 0x%08lx ldsarl: 0x%08lx\n", sbase, ldsarl);
return 0;
}
static const struct fb_ops sh7760fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_blank = sh7760fb_blank,
.fb_check_var = sh7760fb_check_var,
.fb_setcolreg = sh7760_setcolreg,
.fb_set_par = sh7760fb_set_par,
};
static void sh7760fb_free_mem(struct fb_info *info)
{
struct sh7760fb_par *par = info->par;
if (!info->screen_base)
return;
dma_free_coherent(info->device, info->screen_size,
info->screen_base, par->fbdma);
par->fbdma = 0;
info->screen_base = NULL;
info->screen_size = 0;
}
/* allocate the framebuffer memory. This memory must be in Area3,
* (dictated by the DMA engine) and contiguous, at a 512 byte boundary.
*/
static int sh7760fb_alloc_mem(struct fb_info *info)
{
struct sh7760fb_par *par = info->par;
void *fbmem;
unsigned long vram;
int ret, bpp;
if (info->screen_base)
return 0;
/* get color info from register value */
ret = sh7760fb_get_color_info(info, par->pd->lddfr, &bpp, NULL);
if (ret) {
printk(KERN_ERR "colinfo\n");
return ret;
}
/* min VRAM: xres_min = 16, yres_min = 1, bpp = 1: 2byte -> 1 page
max VRAM: xres_max = 1024, yres_max = 1024, bpp = 16: 2MB */
vram = info->var.xres * info->var.yres;
if (info->var.grayscale) {
if (bpp == 1)
vram >>= 3;
else if (bpp == 2)
vram >>= 2;
else if (bpp == 4)
vram >>= 1;
} else if (bpp > 8)
vram *= 2;
if ((vram < 1) || (vram > 1024 * 2048)) {
fb_dbg(info, "too much VRAM required. Check settings\n");
return -ENODEV;
}
if (vram < PAGE_SIZE)
vram = PAGE_SIZE;
fbmem = dma_alloc_coherent(info->device, vram, &par->fbdma, GFP_KERNEL);
if (!fbmem)
return -ENOMEM;
if ((par->fbdma & SH7760FB_DMA_MASK) != SH7760FB_DMA_MASK) {
sh7760fb_free_mem(info);
dev_err(info->device, "kernel gave me memory at 0x%08lx, which is"
"unusable for the LCDC\n", (unsigned long)par->fbdma);
return -ENOMEM;
}
info->screen_base = fbmem;
info->screen_size = vram;
info->fix.smem_start = (unsigned long)info->screen_base;
info->fix.smem_len = info->screen_size;
return 0;
}
static int sh7760fb_probe(struct platform_device *pdev)
{
struct fb_info *info;
struct resource *res;
struct sh7760fb_par *par;
int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (unlikely(res == NULL)) {
dev_err(&pdev->dev, "invalid resource\n");
return -EINVAL;
}
info = framebuffer_alloc(sizeof(struct sh7760fb_par), &pdev->dev);
if (!info)
return -ENOMEM;
par = info->par;
par->dev = pdev;
par->pd = pdev->dev.platform_data;
if (!par->pd) {
dev_dbg(&pdev->dev, "no display setup data!\n");
ret = -ENODEV;
goto out_fb;
}
par->ioarea = request_mem_region(res->start,
resource_size(res), pdev->name);
if (!par->ioarea) {
dev_err(&pdev->dev, "mmio area busy\n");
ret = -EBUSY;
goto out_fb;
}
par->base = ioremap(res->start, resource_size(res));
if (!par->base) {
dev_err(&pdev->dev, "cannot remap\n");
ret = -ENODEV;
goto out_res;
}
iowrite16(0, par->base + LDINTR); /* disable vsync irq */
par->irq = platform_get_irq(pdev, 0);
if (par->irq >= 0) {
ret = request_irq(par->irq, sh7760fb_irq, 0,
"sh7760-lcdc", &par->vsync);
if (ret) {
dev_err(&pdev->dev, "cannot grab IRQ\n");
par->irq = -ENXIO;
} else
disable_irq_nosync(par->irq);
}
fb_videomode_to_var(&info->var, par->pd->def_mode);
ret = sh7760fb_alloc_mem(info);
if (ret) {
dev_dbg(info->device, "framebuffer memory allocation failed!\n");
goto out_unmap;
}
info->pseudo_palette = par->pseudo_palette;
/* fixup color register bitpositions. These are fixed by hardware */
info->var.red.offset = 11;
info->var.red.length = 5;
info->var.red.msb_right = 0;
info->var.green.offset = 5;
info->var.green.length = 6;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = 5;
info->var.blue.msb_right = 0;
info->var.transp.offset = 0;
info->var.transp.length = 0;
info->var.transp.msb_right = 0;
strcpy(info->fix.id, "sh7760-lcdc");
/* set the DON2 bit now, before cmap allocation, as it will randomize
* palette memory.
*/
iowrite16(LDCNTR_DON2, par->base + LDCNTR);
info->fbops = &sh7760fb_ops;
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (ret) {
dev_dbg(&pdev->dev, "Unable to allocate cmap memory\n");
goto out_mem;
}
ret = register_framebuffer(info);
if (ret < 0) {
dev_dbg(&pdev->dev, "cannot register fb!\n");
goto out_cmap;
}
platform_set_drvdata(pdev, info);
printk(KERN_INFO "%s: memory at phys 0x%08lx-0x%08lx, size %ld KiB\n",
pdev->name,
(unsigned long)par->fbdma,
(unsigned long)(par->fbdma + info->screen_size - 1),
info->screen_size >> 10);
return 0;
out_cmap:
sh7760fb_blank(FB_BLANK_POWERDOWN, info);
fb_dealloc_cmap(&info->cmap);
out_mem:
sh7760fb_free_mem(info);
out_unmap:
if (par->irq >= 0)
free_irq(par->irq, &par->vsync);
iounmap(par->base);
out_res:
release_mem_region(res->start, resource_size(res));
out_fb:
framebuffer_release(info);
return ret;
}
static void sh7760fb_remove(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
struct sh7760fb_par *par = info->par;
sh7760fb_blank(FB_BLANK_POWERDOWN, info);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
sh7760fb_free_mem(info);
if (par->irq >= 0)
free_irq(par->irq, &par->vsync);
iounmap(par->base);
release_mem_region(par->ioarea->start, resource_size(par->ioarea));
framebuffer_release(info);
}
static struct platform_driver sh7760_lcdc_driver = {
.driver = {
.name = "sh7760-lcdc",
},
.probe = sh7760fb_probe,
.remove_new = sh7760fb_remove,
};
module_platform_driver(sh7760_lcdc_driver);
MODULE_AUTHOR("Nobuhiro Iwamatsu, Manuel Lauss");
MODULE_DESCRIPTION("FBdev for SH7760/63 integrated LCD Controller");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/sh7760fb.c |
/*
* linux/drivers/video/iplan2p8.c -- Low level frame buffer operations for
* interleaved bitplanes à la Atari (8
* planes, 2 bytes interleave)
*
* Created 5 Apr 1997 by Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/setup.h>
#include "atafb.h"
#define BPL 8
#include "atafb_utils.h"
/* Copies a 8 plane column from 's', height 'h', to 'd'. */
/* This expands a 8 bit color into two longs for two movepl (8 plane)
* operations.
*/
void atafb_iplan2p8_copyarea(struct fb_info *info, u_long next_line,
int sy, int sx, int dy, int dx,
int height, int width)
{
/* bmove() has to distinguish two major cases: If both, source and
* destination, start at even addresses or both are at odd
* addresses, just the first odd and last even column (if present)
* require special treatment (memmove_col()). The rest between
* then can be copied by normal operations, because all adjacent
* bytes are affected and are to be stored in the same order.
* The pathological case is when the move should go from an odd
* address to an even or vice versa. Since the bytes in the plane
* words must be assembled in new order, it seems wisest to make
* all movements by memmove_col().
*/
u8 *src, *dst;
u32 *s, *d;
int w, l , i, j;
u_int colsize;
u_int upwards = (dy < sy) || (dy == sy && dx < sx);
colsize = height;
if (!((sx ^ dx) & 15)) {
/* odd->odd or even->even */
if (upwards) {
src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL);
if (sx & 15) {
memmove32_col(dst, src, 0xff00ff, height, next_line - BPL * 2);
src += BPL * 2;
dst += BPL * 2;
width -= 8;
}
w = width >> 4;
if (w) {
s = (u32 *)src;
d = (u32 *)dst;
w *= BPL / 2;
l = next_line - w * 4;
for (j = height; j > 0; j--) {
for (i = w; i > 0; i--)
*d++ = *s++;
s = (u32 *)((u8 *)s + l);
d = (u32 *)((u8 *)d + l);
}
}
if (width & 15)
memmove32_col(dst + width / (8 / BPL), src + width / (8 / BPL),
0xff00ff00, height, next_line - BPL * 2);
} else {
src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL);
if ((sx + width) & 15) {
src -= BPL * 2;
dst -= BPL * 2;
memmove32_col(dst, src, 0xff00ff00, colsize, -next_line - BPL * 2);
width -= 8;
}
w = width >> 4;
if (w) {
s = (u32 *)src;
d = (u32 *)dst;
w *= BPL / 2;
l = next_line - w * 4;
for (j = height; j > 0; j--) {
for (i = w; i > 0; i--)
*--d = *--s;
s = (u32 *)((u8 *)s - l);
d = (u32 *)((u8 *)d - l);
}
}
if (sx & 15)
memmove32_col(dst - (width - 16) / (8 / BPL),
src - (width - 16) / (8 / BPL),
0xff00ff, colsize, -next_line - BPL * 2);
}
} else {
/* odd->even or even->odd */
if (upwards) {
u32 *src32, *dst32;
u32 pval[4], v, v1, mask;
int i, j, w, f;
src = (u8 *)info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL);
mask = 0xff00ff00;
f = 0;
w = width;
if (sx & 15) {
f = 1;
w += 8;
}
if ((sx + width) & 15)
f |= 2;
w >>= 4;
for (i = height; i; i--) {
src32 = (u32 *)src;
dst32 = (u32 *)dst;
if (f & 1) {
pval[0] = (*src32++ << 8) & mask;
pval[1] = (*src32++ << 8) & mask;
pval[2] = (*src32++ << 8) & mask;
pval[3] = (*src32++ << 8) & mask;
} else {
pval[0] = dst32[0] & mask;
pval[1] = dst32[1] & mask;
pval[2] = dst32[2] & mask;
pval[3] = dst32[3] & mask;
}
for (j = w; j > 0; j--) {
v = *src32++;
v1 = v & mask;
*dst32++ = pval[0] | (v1 >> 8);
pval[0] = (v ^ v1) << 8;
v = *src32++;
v1 = v & mask;
*dst32++ = pval[1] | (v1 >> 8);
pval[1] = (v ^ v1) << 8;
v = *src32++;
v1 = v & mask;
*dst32++ = pval[2] | (v1 >> 8);
pval[2] = (v ^ v1) << 8;
v = *src32++;
v1 = v & mask;
*dst32++ = pval[3] | (v1 >> 8);
pval[3] = (v ^ v1) << 8;
}
if (f & 2) {
dst32[0] = (dst32[0] & mask) | pval[0];
dst32[1] = (dst32[1] & mask) | pval[1];
dst32[2] = (dst32[2] & mask) | pval[2];
dst32[3] = (dst32[3] & mask) | pval[3];
}
src += next_line;
dst += next_line;
}
} else {
u32 *src32, *dst32;
u32 pval[4], v, v1, mask;
int i, j, w, f;
src = (u8 *)info->screen_base + (sy - 1) * next_line + ((sx + width + 8) & ~15) / (8 / BPL);
dst = (u8 *)info->screen_base + (dy - 1) * next_line + ((dx + width + 8) & ~15) / (8 / BPL);
mask = 0xff00ff;
f = 0;
w = width;
if ((dx + width) & 15)
f = 1;
if (sx & 15) {
f |= 2;
w += 8;
}
w >>= 4;
for (i = height; i; i--) {
src32 = (u32 *)src;
dst32 = (u32 *)dst;
if (f & 1) {
pval[0] = dst32[-1] & mask;
pval[1] = dst32[-2] & mask;
pval[2] = dst32[-3] & mask;
pval[3] = dst32[-4] & mask;
} else {
pval[0] = (*--src32 >> 8) & mask;
pval[1] = (*--src32 >> 8) & mask;
pval[2] = (*--src32 >> 8) & mask;
pval[3] = (*--src32 >> 8) & mask;
}
for (j = w; j > 0; j--) {
v = *--src32;
v1 = v & mask;
*--dst32 = pval[0] | (v1 << 8);
pval[0] = (v ^ v1) >> 8;
v = *--src32;
v1 = v & mask;
*--dst32 = pval[1] | (v1 << 8);
pval[1] = (v ^ v1) >> 8;
v = *--src32;
v1 = v & mask;
*--dst32 = pval[2] | (v1 << 8);
pval[2] = (v ^ v1) >> 8;
v = *--src32;
v1 = v & mask;
*--dst32 = pval[3] | (v1 << 8);
pval[3] = (v ^ v1) >> 8;
}
if (!(f & 2)) {
dst32[-1] = (dst32[-1] & mask) | pval[0];
dst32[-2] = (dst32[-2] & mask) | pval[1];
dst32[-3] = (dst32[-3] & mask) | pval[2];
dst32[-4] = (dst32[-4] & mask) | pval[3];
}
src -= next_line;
dst -= next_line;
}
}
}
}
void atafb_iplan2p8_fillrect(struct fb_info *info, u_long next_line, u32 color,
int sy, int sx, int height, int width)
{
u32 *dest;
int rows, i;
u32 cval[4];
dest = (u32 *)(info->screen_base + sy * next_line + (sx & ~15) / (8 / BPL));
if (sx & 15) {
u8 *dest8 = (u8 *)dest + 1;
expand8_col2mask(color, cval);
for (i = height; i; i--) {
fill8_col(dest8, cval);
dest8 += next_line;
}
dest += BPL / 2;
width -= 8;
}
expand16_col2mask(color, cval);
rows = width >> 4;
if (rows) {
u32 *d = dest;
u32 off = next_line - rows * BPL * 2;
for (i = height; i; i--) {
d = fill16_col(d, rows, cval);
d = (u32 *)((long)d + off);
}
dest += rows * BPL / 2;
width &= 15;
}
if (width) {
u8 *dest8 = (u8 *)dest;
expand8_col2mask(color, cval);
for (i = height; i; i--) {
fill8_col(dest8, cval);
dest8 += next_line;
}
}
}
void atafb_iplan2p8_linefill(struct fb_info *info, u_long next_line,
int dy, int dx, u32 width,
const u8 *data, u32 bgcolor, u32 fgcolor)
{
u32 *dest;
const u16 *data16;
int rows;
u32 fgm[4], bgm[4], m;
dest = (u32 *)(info->screen_base + dy * next_line + (dx & ~15) / (8 / BPL));
if (dx & 15) {
fill8_2col((u8 *)dest + 1, fgcolor, bgcolor, *data++);
dest += BPL / 2;
width -= 8;
}
if (width >= 16) {
data16 = (const u16 *)data;
expand16_2col2mask(fgcolor, bgcolor, fgm, bgm);
for (rows = width / 16; rows; rows--) {
u16 d = *data16++;
m = d | ((u32)d << 16);
*dest++ = (m & fgm[0]) ^ bgm[0];
*dest++ = (m & fgm[1]) ^ bgm[1];
*dest++ = (m & fgm[2]) ^ bgm[2];
*dest++ = (m & fgm[3]) ^ bgm[3];
}
data = (const u8 *)data16;
width &= 15;
}
if (width)
fill8_2col((u8 *)dest, fgcolor, bgcolor, *data);
}
| linux-master | drivers/video/fbdev/atafb_iplan2p8.c |
/*
* BRIEF MODULE DESCRIPTION
* Au1200 LCD Driver.
*
* Copyright 2004-2005 AMD
* Author: AMD
*
* Based on:
* linux/drivers/video/skeletonfb.c -- Skeleton for a frame buffer device
* Created 28 Dec 1997 by Geert Uytterhoeven
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ctype.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <asm/mach-au1x00/au1000.h>
#include <asm/mach-au1x00/au1200fb.h> /* platform_data */
#include "au1200fb.h"
#define DRIVER_NAME "au1200fb"
#define DRIVER_DESC "LCD controller driver for AU1200 processors"
#define DEBUG 0
#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
#if DEBUG
#define print_dbg(f, arg...) printk(KERN_DEBUG __FILE__ ": " f "\n", ## arg)
#else
#define print_dbg(f, arg...) do {} while (0)
#endif
#define AU1200_LCD_FB_IOCTL 0x46FF
#define AU1200_LCD_SET_SCREEN 1
#define AU1200_LCD_GET_SCREEN 2
#define AU1200_LCD_SET_WINDOW 3
#define AU1200_LCD_GET_WINDOW 4
#define AU1200_LCD_SET_PANEL 5
#define AU1200_LCD_GET_PANEL 6
#define SCREEN_SIZE (1<< 1)
#define SCREEN_BACKCOLOR (1<< 2)
#define SCREEN_BRIGHTNESS (1<< 3)
#define SCREEN_COLORKEY (1<< 4)
#define SCREEN_MASK (1<< 5)
struct au1200_lcd_global_regs_t {
unsigned int flags;
unsigned int xsize;
unsigned int ysize;
unsigned int backcolor;
unsigned int brightness;
unsigned int colorkey;
unsigned int mask;
unsigned int panel_choice;
char panel_desc[80];
};
#define WIN_POSITION (1<< 0)
#define WIN_ALPHA_COLOR (1<< 1)
#define WIN_ALPHA_MODE (1<< 2)
#define WIN_PRIORITY (1<< 3)
#define WIN_CHANNEL (1<< 4)
#define WIN_BUFFER_FORMAT (1<< 5)
#define WIN_COLOR_ORDER (1<< 6)
#define WIN_PIXEL_ORDER (1<< 7)
#define WIN_SIZE (1<< 8)
#define WIN_COLORKEY_MODE (1<< 9)
#define WIN_DOUBLE_BUFFER_MODE (1<< 10)
#define WIN_RAM_ARRAY_MODE (1<< 11)
#define WIN_BUFFER_SCALE (1<< 12)
#define WIN_ENABLE (1<< 13)
struct au1200_lcd_window_regs_t {
unsigned int flags;
unsigned int xpos;
unsigned int ypos;
unsigned int alpha_color;
unsigned int alpha_mode;
unsigned int priority;
unsigned int channel;
unsigned int buffer_format;
unsigned int color_order;
unsigned int pixel_order;
unsigned int xsize;
unsigned int ysize;
unsigned int colorkey_mode;
unsigned int double_buffer_mode;
unsigned int ram_array_mode;
unsigned int xscale;
unsigned int yscale;
unsigned int enable;
};
struct au1200_lcd_iodata_t {
unsigned int subcmd;
struct au1200_lcd_global_regs_t global;
struct au1200_lcd_window_regs_t window;
};
#if defined(__BIG_ENDIAN)
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
#else
#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
#endif
#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
/* Private, per-framebuffer management information (independent of the panel itself) */
struct au1200fb_device {
struct fb_info *fb_info; /* FB driver info record */
struct au1200fb_platdata *pd;
struct device *dev;
int plane;
unsigned char* fb_mem; /* FrameBuffer memory map */
unsigned int fb_len;
dma_addr_t fb_phys;
};
/********************************************************************/
/* LCD controller restrictions */
#define AU1200_LCD_MAX_XRES 1280
#define AU1200_LCD_MAX_YRES 1024
#define AU1200_LCD_MAX_BPP 32
#define AU1200_LCD_MAX_CLK 96000000 /* fixme: this needs to go away ? */
#define AU1200_LCD_NBR_PALETTE_ENTRIES 256
/* Default number of visible screen buffer to allocate */
#define AU1200FB_NBR_VIDEO_BUFFERS 1
/* Default maximum number of fb devices to create */
#define MAX_DEVICE_COUNT 4
/* Default window configuration entry to use (see windows[]) */
#define DEFAULT_WINDOW_INDEX 2
/********************************************************************/
static struct fb_info *_au1200fb_infos[MAX_DEVICE_COUNT];
static struct au1200_lcd *lcd = (struct au1200_lcd *) AU1200_LCD_ADDR;
static int device_count = MAX_DEVICE_COUNT;
static int window_index = DEFAULT_WINDOW_INDEX; /* default is zero */
static int panel_index = 2; /* default is zero */
static struct window_settings *win;
static struct panel_settings *panel;
static int noblanking = 1;
static int nohwcursor = 0;
struct window_settings {
unsigned char name[64];
uint32 mode_backcolor;
uint32 mode_colorkey;
uint32 mode_colorkeymsk;
struct {
int xres;
int yres;
int xpos;
int ypos;
uint32 mode_winctrl1; /* winctrl1[FRM,CCO,PO,PIPE] */
uint32 mode_winenable;
} w[4];
};
#if defined(__BIG_ENDIAN)
#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_00
#else
#define LCD_WINCTRL1_PO_16BPP LCD_WINCTRL1_PO_01
#endif
/*
* Default window configurations
*/
static struct window_settings windows[] = {
{ /* Index 0 */
"0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
/* mode_backcolor */ 0x006600ff,
/* mode_colorkey,msk*/ 0, 0,
{
{
/* xres, yres, xpos, ypos */ 0, 0, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP,
/* mode_winenable*/ LCD_WINENABLE_WEN0,
},
{
/* xres, yres, xpos, ypos */ 100, 100, 100, 100,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP |
LCD_WINCTRL1_PIPE,
/* mode_winenable*/ LCD_WINENABLE_WEN1,
},
{
/* xres, yres, xpos, ypos */ 0, 0, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP,
/* mode_winenable*/ 0,
},
{
/* xres, yres, xpos, ypos */ 0, 0, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP |
LCD_WINCTRL1_PIPE,
/* mode_winenable*/ 0,
},
},
},
{ /* Index 1 */
"0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
/* mode_backcolor */ 0x006600ff,
/* mode_colorkey,msk*/ 0, 0,
{
{
/* xres, yres, xpos, ypos */ 320, 240, 5, 5,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_24BPP |
LCD_WINCTRL1_PO_00,
/* mode_winenable*/ LCD_WINENABLE_WEN0,
},
{
/* xres, yres, xpos, ypos */ 0, 0, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565
| LCD_WINCTRL1_PO_16BPP,
/* mode_winenable*/ 0,
},
{
/* xres, yres, xpos, ypos */ 100, 100, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP |
LCD_WINCTRL1_PIPE,
/* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/,
},
{
/* xres, yres, xpos, ypos */ 200, 25, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP |
LCD_WINCTRL1_PIPE,
/* mode_winenable*/ 0,
},
},
},
{ /* Index 2 */
"0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
/* mode_backcolor */ 0x006600ff,
/* mode_colorkey,msk*/ 0, 0,
{
{
/* xres, yres, xpos, ypos */ 0, 0, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP,
/* mode_winenable*/ LCD_WINENABLE_WEN0,
},
{
/* xres, yres, xpos, ypos */ 0, 0, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP,
/* mode_winenable*/ 0,
},
{
/* xres, yres, xpos, ypos */ 0, 0, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_32BPP |
LCD_WINCTRL1_PO_00|LCD_WINCTRL1_PIPE,
/* mode_winenable*/ 0/*LCD_WINENABLE_WEN2*/,
},
{
/* xres, yres, xpos, ypos */ 0, 0, 0, 0,
/* mode_winctrl1 */ LCD_WINCTRL1_FRM_16BPP565 |
LCD_WINCTRL1_PO_16BPP |
LCD_WINCTRL1_PIPE,
/* mode_winenable*/ 0,
},
},
},
/* Need VGA 640 @ 24bpp, @ 32bpp */
/* Need VGA 800 @ 24bpp, @ 32bpp */
/* Need VGA 1024 @ 24bpp, @ 32bpp */
};
/*
* Controller configurations for various panels.
*/
struct panel_settings
{
const char name[25]; /* Full name <vendor>_<model> */
struct fb_monspecs monspecs; /* FB monitor specs */
/* panel timings */
uint32 mode_screen;
uint32 mode_horztiming;
uint32 mode_verttiming;
uint32 mode_clkcontrol;
uint32 mode_pwmdiv;
uint32 mode_pwmhi;
uint32 mode_outmask;
uint32 mode_fifoctrl;
uint32 mode_backlight;
uint32 lcdclk;
#define Xres min_xres
#define Yres min_yres
u32 min_xres; /* Minimum horizontal resolution */
u32 max_xres; /* Maximum horizontal resolution */
u32 min_yres; /* Minimum vertical resolution */
u32 max_yres; /* Maximum vertical resolution */
};
/********************************************************************/
/* fixme: Maybe a modedb for the CRT ? otherwise panels should be as-is */
/* List of panels known to work with the AU1200 LCD controller.
* To add a new panel, enter the same specifications as the
* Generic_TFT one, and MAKE SURE that it doesn't conflicts
* with the controller restrictions. Restrictions are:
*
* STN color panels: max_bpp <= 12
* STN mono panels: max_bpp <= 4
* TFT panels: max_bpp <= 16
* max_xres <= 800
* max_yres <= 600
*/
static struct panel_settings known_lcd_panels[] =
{
[0] = { /* QVGA 320x240 H:33.3kHz V:110Hz */
.name = "QVGA_320x240",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = LCD_SCREEN_SX_N(320) |
LCD_SCREEN_SY_N(240),
.mode_horztiming = 0x00c4623b,
.mode_verttiming = 0x00502814,
.mode_clkcontrol = 0x00020002, /* /4=24Mhz */
.mode_pwmdiv = 0x00000000,
.mode_pwmhi = 0x00000000,
.mode_outmask = 0x00FFFFFF,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 96,
320, 320,
240, 240,
},
[1] = { /* VGA 640x480 H:30.3kHz V:58Hz */
.name = "VGA_640x480",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = 0x13f9df80,
.mode_horztiming = 0x003c5859,
.mode_verttiming = 0x00741201,
.mode_clkcontrol = 0x00020001, /* /4=24Mhz */
.mode_pwmdiv = 0x00000000,
.mode_pwmhi = 0x00000000,
.mode_outmask = 0x00FFFFFF,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 96,
640, 480,
640, 480,
},
[2] = { /* SVGA 800x600 H:46.1kHz V:69Hz */
.name = "SVGA_800x600",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = 0x18fa5780,
.mode_horztiming = 0x00dc7e77,
.mode_verttiming = 0x00584805,
.mode_clkcontrol = 0x00020000, /* /2=48Mhz */
.mode_pwmdiv = 0x00000000,
.mode_pwmhi = 0x00000000,
.mode_outmask = 0x00FFFFFF,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 96,
800, 800,
600, 600,
},
[3] = { /* XVGA 1024x768 H:56.2kHz V:70Hz */
.name = "XVGA_1024x768",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = 0x1ffaff80,
.mode_horztiming = 0x007d0e57,
.mode_verttiming = 0x00740a01,
.mode_clkcontrol = 0x000A0000, /* /1 */
.mode_pwmdiv = 0x00000000,
.mode_pwmhi = 0x00000000,
.mode_outmask = 0x00FFFFFF,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 72,
1024, 1024,
768, 768,
},
[4] = { /* XVGA XVGA 1280x1024 H:68.5kHz V:65Hz */
.name = "XVGA_1280x1024",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = 0x27fbff80,
.mode_horztiming = 0x00cdb2c7,
.mode_verttiming = 0x00600002,
.mode_clkcontrol = 0x000A0000, /* /1 */
.mode_pwmdiv = 0x00000000,
.mode_pwmhi = 0x00000000,
.mode_outmask = 0x00FFFFFF,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 120,
1280, 1280,
1024, 1024,
},
[5] = { /* Samsung 1024x768 TFT */
.name = "Samsung_1024x768_TFT",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = 0x1ffaff80,
.mode_horztiming = 0x018cc677,
.mode_verttiming = 0x00241217,
.mode_clkcontrol = 0x00000000, /* SCB 0x1 /4=24Mhz */
.mode_pwmdiv = 0x8000063f, /* SCB 0x0 */
.mode_pwmhi = 0x03400000, /* SCB 0x0 */
.mode_outmask = 0x00FFFFFF,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 96,
1024, 1024,
768, 768,
},
[6] = { /* Toshiba 640x480 TFT */
.name = "Toshiba_640x480_TFT",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = LCD_SCREEN_SX_N(640) |
LCD_SCREEN_SY_N(480),
.mode_horztiming = LCD_HORZTIMING_HPW_N(96) |
LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(51),
.mode_verttiming = LCD_VERTTIMING_VPW_N(2) |
LCD_VERTTIMING_VND1_N(11) | LCD_VERTTIMING_VND2_N(32),
.mode_clkcontrol = 0x00000000, /* /4=24Mhz */
.mode_pwmdiv = 0x8000063f,
.mode_pwmhi = 0x03400000,
.mode_outmask = 0x00fcfcfc,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 96,
640, 480,
640, 480,
},
[7] = { /* Sharp 320x240 TFT */
.name = "Sharp_320x240_TFT",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 12500,
.hfmax = 20000,
.vfmin = 38,
.vfmax = 81,
.dclkmin = 4500000,
.dclkmax = 6800000,
.input = FB_DISP_RGB,
},
.mode_screen = LCD_SCREEN_SX_N(320) |
LCD_SCREEN_SY_N(240),
.mode_horztiming = LCD_HORZTIMING_HPW_N(60) |
LCD_HORZTIMING_HND1_N(13) | LCD_HORZTIMING_HND2_N(2),
.mode_verttiming = LCD_VERTTIMING_VPW_N(2) |
LCD_VERTTIMING_VND1_N(2) | LCD_VERTTIMING_VND2_N(5),
.mode_clkcontrol = LCD_CLKCONTROL_PCD_N(7), /*16=6Mhz*/
.mode_pwmdiv = 0x8000063f,
.mode_pwmhi = 0x03400000,
.mode_outmask = 0x00fcfcfc,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 96, /* 96MHz AUXPLL */
320, 320,
240, 240,
},
[8] = { /* Toppoly TD070WGCB2 7" 856x480 TFT */
.name = "Toppoly_TD070WGCB2",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = LCD_SCREEN_SX_N(856) |
LCD_SCREEN_SY_N(480),
.mode_horztiming = LCD_HORZTIMING_HND2_N(43) |
LCD_HORZTIMING_HND1_N(43) | LCD_HORZTIMING_HPW_N(114),
.mode_verttiming = LCD_VERTTIMING_VND2_N(20) |
LCD_VERTTIMING_VND1_N(21) | LCD_VERTTIMING_VPW_N(4),
.mode_clkcontrol = 0x00020001, /* /4=24Mhz */
.mode_pwmdiv = 0x8000063f,
.mode_pwmhi = 0x03400000,
.mode_outmask = 0x00fcfcfc,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 96,
856, 856,
480, 480,
},
[9] = {
.name = "DB1300_800x480",
.monspecs = {
.modedb = NULL,
.modedb_len = 0,
.hfmin = 30000,
.hfmax = 70000,
.vfmin = 60,
.vfmax = 60,
.dclkmin = 6000000,
.dclkmax = 28000000,
.input = FB_DISP_RGB,
},
.mode_screen = LCD_SCREEN_SX_N(800) |
LCD_SCREEN_SY_N(480),
.mode_horztiming = LCD_HORZTIMING_HPW_N(5) |
LCD_HORZTIMING_HND1_N(16) |
LCD_HORZTIMING_HND2_N(8),
.mode_verttiming = LCD_VERTTIMING_VPW_N(4) |
LCD_VERTTIMING_VND1_N(8) |
LCD_VERTTIMING_VND2_N(5),
.mode_clkcontrol = LCD_CLKCONTROL_PCD_N(1) |
LCD_CLKCONTROL_IV |
LCD_CLKCONTROL_IH,
.mode_pwmdiv = 0x00000000,
.mode_pwmhi = 0x00000000,
.mode_outmask = 0x00FFFFFF,
.mode_fifoctrl = 0x2f2f2f2f,
.mode_backlight = 0x00000000,
.lcdclk = 96,
800, 800,
480, 480,
},
};
#define NUM_PANELS (ARRAY_SIZE(known_lcd_panels))
/********************************************************************/
static int winbpp (unsigned int winctrl1)
{
int bits = 0;
/* how many bits are needed for each pixel format */
switch (winctrl1 & LCD_WINCTRL1_FRM) {
case LCD_WINCTRL1_FRM_1BPP:
bits = 1;
break;
case LCD_WINCTRL1_FRM_2BPP:
bits = 2;
break;
case LCD_WINCTRL1_FRM_4BPP:
bits = 4;
break;
case LCD_WINCTRL1_FRM_8BPP:
bits = 8;
break;
case LCD_WINCTRL1_FRM_12BPP:
case LCD_WINCTRL1_FRM_16BPP655:
case LCD_WINCTRL1_FRM_16BPP565:
case LCD_WINCTRL1_FRM_16BPP556:
case LCD_WINCTRL1_FRM_16BPPI1555:
case LCD_WINCTRL1_FRM_16BPPI5551:
case LCD_WINCTRL1_FRM_16BPPA1555:
case LCD_WINCTRL1_FRM_16BPPA5551:
bits = 16;
break;
case LCD_WINCTRL1_FRM_24BPP:
case LCD_WINCTRL1_FRM_32BPP:
bits = 32;
break;
}
return bits;
}
static int fbinfo2index (struct fb_info *fb_info)
{
int i;
for (i = 0; i < device_count; ++i) {
if (fb_info == _au1200fb_infos[i])
return i;
}
printk("au1200fb: ERROR: fbinfo2index failed!\n");
return -1;
}
static int au1200_setlocation (struct au1200fb_device *fbdev, int plane,
int xpos, int ypos)
{
uint32 winctrl0, winctrl1, winenable, fb_offset = 0;
int xsz, ysz;
/* FIX!!! NOT CHECKING FOR COMPLETE OFFSCREEN YET */
winctrl0 = lcd->window[plane].winctrl0;
winctrl1 = lcd->window[plane].winctrl1;
winctrl0 &= (LCD_WINCTRL0_A | LCD_WINCTRL0_AEN);
winctrl1 &= ~(LCD_WINCTRL1_SZX | LCD_WINCTRL1_SZY);
/* Check for off-screen adjustments */
xsz = win->w[plane].xres;
ysz = win->w[plane].yres;
if ((xpos + win->w[plane].xres) > panel->Xres) {
/* Off-screen to the right */
xsz = panel->Xres - xpos; /* off by 1 ??? */
/*printk("off screen right\n");*/
}
if ((ypos + win->w[plane].yres) > panel->Yres) {
/* Off-screen to the bottom */
ysz = panel->Yres - ypos; /* off by 1 ??? */
/*printk("off screen bottom\n");*/
}
if (xpos < 0) {
/* Off-screen to the left */
xsz = win->w[plane].xres + xpos;
fb_offset += (((0 - xpos) * winbpp(lcd->window[plane].winctrl1))/8);
xpos = 0;
/*printk("off screen left\n");*/
}
if (ypos < 0) {
/* Off-screen to the top */
ysz = win->w[plane].yres + ypos;
/* fixme: fb_offset += ((0-ypos)*fb_pars[plane].line_length); */
ypos = 0;
/*printk("off screen top\n");*/
}
/* record settings */
win->w[plane].xpos = xpos;
win->w[plane].ypos = ypos;
xsz -= 1;
ysz -= 1;
winctrl0 |= (xpos << 21);
winctrl0 |= (ypos << 10);
winctrl1 |= (xsz << 11);
winctrl1 |= (ysz << 0);
/* Disable the window while making changes, then restore WINEN */
winenable = lcd->winenable & (1 << plane);
wmb(); /* drain writebuffer */
lcd->winenable &= ~(1 << plane);
lcd->window[plane].winctrl0 = winctrl0;
lcd->window[plane].winctrl1 = winctrl1;
lcd->window[plane].winbuf0 =
lcd->window[plane].winbuf1 = fbdev->fb_phys;
lcd->window[plane].winbufctrl = 0; /* select winbuf0 */
lcd->winenable |= winenable;
wmb(); /* drain writebuffer */
return 0;
}
static void au1200_setpanel(struct panel_settings *newpanel,
struct au1200fb_platdata *pd)
{
/*
* Perform global setup/init of LCD controller
*/
uint32 winenable;
/* Make sure all windows disabled */
winenable = lcd->winenable;
lcd->winenable = 0;
wmb(); /* drain writebuffer */
/*
* Ensure everything is disabled before reconfiguring
*/
if (lcd->screen & LCD_SCREEN_SEN) {
/* Wait for vertical sync period */
lcd->intstatus = LCD_INT_SS;
while ((lcd->intstatus & LCD_INT_SS) == 0)
;
lcd->screen &= ~LCD_SCREEN_SEN; /*disable the controller*/
do {
lcd->intstatus = lcd->intstatus; /*clear interrupts*/
wmb(); /* drain writebuffer */
/*wait for controller to shut down*/
} while ((lcd->intstatus & LCD_INT_SD) == 0);
/* Call shutdown of current panel (if up) */
/* this must occur last, because if an external clock is driving
the controller, the clock cannot be turned off before first
shutting down the controller.
*/
if (pd->panel_shutdown)
pd->panel_shutdown();
}
/* Newpanel == NULL indicates a shutdown operation only */
if (newpanel == NULL)
return;
panel = newpanel;
printk("Panel(%s), %dx%d\n", panel->name, panel->Xres, panel->Yres);
/*
* Setup clocking if internal LCD clock source (assumes sys_auxpll valid)
*/
if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT))
{
struct clk *c = clk_get(NULL, "lcd_intclk");
long r, pc = panel->lcdclk * 1000000;
if (!IS_ERR(c)) {
r = clk_round_rate(c, pc);
if ((pc - r) < (pc / 10)) { /* 10% slack */
clk_set_rate(c, r);
clk_prepare_enable(c);
}
clk_put(c);
}
}
/*
* Configure panel timings
*/
lcd->screen = panel->mode_screen;
lcd->horztiming = panel->mode_horztiming;
lcd->verttiming = panel->mode_verttiming;
lcd->clkcontrol = panel->mode_clkcontrol;
lcd->pwmdiv = panel->mode_pwmdiv;
lcd->pwmhi = panel->mode_pwmhi;
lcd->outmask = panel->mode_outmask;
lcd->fifoctrl = panel->mode_fifoctrl;
wmb(); /* drain writebuffer */
/* fixme: Check window settings to make sure still valid
* for new geometry */
#if 0
au1200_setlocation(fbdev, 0, win->w[0].xpos, win->w[0].ypos);
au1200_setlocation(fbdev, 1, win->w[1].xpos, win->w[1].ypos);
au1200_setlocation(fbdev, 2, win->w[2].xpos, win->w[2].ypos);
au1200_setlocation(fbdev, 3, win->w[3].xpos, win->w[3].ypos);
#endif
lcd->winenable = winenable;
/*
* Re-enable screen now that it is configured
*/
lcd->screen |= LCD_SCREEN_SEN;
wmb(); /* drain writebuffer */
/* Call init of panel */
if (pd->panel_init)
pd->panel_init();
/* FIX!!!! not appropriate on panel change!!! Global setup/init */
lcd->intenable = 0;
lcd->intstatus = ~0;
lcd->backcolor = win->mode_backcolor;
/* Setup Color Key - FIX!!! */
lcd->colorkey = win->mode_colorkey;
lcd->colorkeymsk = win->mode_colorkeymsk;
/* Setup HWCursor - FIX!!! Need to support this eventually */
lcd->hwc.cursorctrl = 0;
lcd->hwc.cursorpos = 0;
lcd->hwc.cursorcolor0 = 0;
lcd->hwc.cursorcolor1 = 0;
lcd->hwc.cursorcolor2 = 0;
lcd->hwc.cursorcolor3 = 0;
#if 0
#define D(X) printk("%25s: %08X\n", #X, X)
D(lcd->screen);
D(lcd->horztiming);
D(lcd->verttiming);
D(lcd->clkcontrol);
D(lcd->pwmdiv);
D(lcd->pwmhi);
D(lcd->outmask);
D(lcd->fifoctrl);
D(lcd->window[0].winctrl0);
D(lcd->window[0].winctrl1);
D(lcd->window[0].winctrl2);
D(lcd->window[0].winbuf0);
D(lcd->window[0].winbuf1);
D(lcd->window[0].winbufctrl);
D(lcd->window[1].winctrl0);
D(lcd->window[1].winctrl1);
D(lcd->window[1].winctrl2);
D(lcd->window[1].winbuf0);
D(lcd->window[1].winbuf1);
D(lcd->window[1].winbufctrl);
D(lcd->window[2].winctrl0);
D(lcd->window[2].winctrl1);
D(lcd->window[2].winctrl2);
D(lcd->window[2].winbuf0);
D(lcd->window[2].winbuf1);
D(lcd->window[2].winbufctrl);
D(lcd->window[3].winctrl0);
D(lcd->window[3].winctrl1);
D(lcd->window[3].winctrl2);
D(lcd->window[3].winbuf0);
D(lcd->window[3].winbuf1);
D(lcd->window[3].winbufctrl);
D(lcd->winenable);
D(lcd->intenable);
D(lcd->intstatus);
D(lcd->backcolor);
D(lcd->winenable);
D(lcd->colorkey);
D(lcd->colorkeymsk);
D(lcd->hwc.cursorctrl);
D(lcd->hwc.cursorpos);
D(lcd->hwc.cursorcolor0);
D(lcd->hwc.cursorcolor1);
D(lcd->hwc.cursorcolor2);
D(lcd->hwc.cursorcolor3);
#endif
}
static void au1200_setmode(struct au1200fb_device *fbdev)
{
int plane = fbdev->plane;
/* Window/plane setup */
lcd->window[plane].winctrl1 = ( 0
| LCD_WINCTRL1_PRI_N(plane)
| win->w[plane].mode_winctrl1 /* FRM,CCO,PO,PIPE */
) ;
au1200_setlocation(fbdev, plane, win->w[plane].xpos, win->w[plane].ypos);
lcd->window[plane].winctrl2 = ( 0
| LCD_WINCTRL2_CKMODE_00
| LCD_WINCTRL2_DBM
| LCD_WINCTRL2_BX_N(fbdev->fb_info->fix.line_length)
| LCD_WINCTRL2_SCX_1
| LCD_WINCTRL2_SCY_1
) ;
lcd->winenable |= win->w[plane].mode_winenable;
wmb(); /* drain writebuffer */
}
/* Inline helpers */
/*#define panel_is_dual(panel) ((panel->mode_screen & LCD_SCREEN_PT) == LCD_SCREEN_PT_010)*/
/*#define panel_is_active(panel)((panel->mode_screen & LCD_SCREEN_PT) == LCD_SCREEN_PT_010)*/
#define panel_is_color(panel) ((panel->mode_screen & LCD_SCREEN_PT) <= LCD_SCREEN_PT_CDSTN)
/* Bitfields format supported by the controller. */
static struct fb_bitfield rgb_bitfields[][4] = {
/* Red, Green, Blue, Transp */
[LCD_WINCTRL1_FRM_16BPP655 >> 25] =
{ { 10, 6, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
[LCD_WINCTRL1_FRM_16BPP565 >> 25] =
{ { 11, 5, 0 }, { 5, 6, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
[LCD_WINCTRL1_FRM_16BPP556 >> 25] =
{ { 11, 5, 0 }, { 6, 5, 0 }, { 0, 6, 0 }, { 0, 0, 0 } },
[LCD_WINCTRL1_FRM_16BPPI1555 >> 25] =
{ { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 0, 0, 0 } },
[LCD_WINCTRL1_FRM_16BPPI5551 >> 25] =
{ { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 0, 0 } },
[LCD_WINCTRL1_FRM_16BPPA1555 >> 25] =
{ { 10, 5, 0 }, { 5, 5, 0 }, { 0, 5, 0 }, { 15, 1, 0 } },
[LCD_WINCTRL1_FRM_16BPPA5551 >> 25] =
{ { 11, 5, 0 }, { 6, 5, 0 }, { 1, 5, 0 }, { 0, 1, 0 } },
[LCD_WINCTRL1_FRM_24BPP >> 25] =
{ { 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 0, 0, 0 } },
[LCD_WINCTRL1_FRM_32BPP >> 25] =
{ { 16, 8, 0 }, { 8, 8, 0 }, { 0, 8, 0 }, { 24, 0, 0 } },
};
/*-------------------------------------------------------------------------*/
/* Helpers */
static void au1200fb_update_fbinfo(struct fb_info *fbi)
{
/* FIX!!!! This also needs to take the window pixel format into account!!! */
/* Update var-dependent FB info */
if (panel_is_color(panel)) {
if (fbi->var.bits_per_pixel <= 8) {
/* palettized */
fbi->fix.visual = FB_VISUAL_PSEUDOCOLOR;
fbi->fix.line_length = fbi->var.xres_virtual /
(8/fbi->var.bits_per_pixel);
} else {
/* non-palettized */
fbi->fix.visual = FB_VISUAL_TRUECOLOR;
fbi->fix.line_length = fbi->var.xres_virtual * (fbi->var.bits_per_pixel / 8);
}
} else {
/* mono FIX!!! mono 8 and 4 bits */
fbi->fix.visual = FB_VISUAL_MONO10;
fbi->fix.line_length = fbi->var.xres_virtual / 8;
}
fbi->screen_size = fbi->fix.line_length * fbi->var.yres_virtual;
print_dbg("line length: %d\n", fbi->fix.line_length);
print_dbg("bits_per_pixel: %d\n", fbi->var.bits_per_pixel);
}
/*-------------------------------------------------------------------------*/
/* AU1200 framebuffer driver */
/* fb_check_var
* Validate var settings with hardware restrictions and modify it if necessary
*/
static int au1200fb_fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *fbi)
{
struct au1200fb_device *fbdev = fbi->par;
u32 pixclock;
int screen_size, plane;
if (!var->pixclock)
return -EINVAL;
plane = fbdev->plane;
/* Make sure that the mode respect all LCD controller and
* panel restrictions. */
var->xres = win->w[plane].xres;
var->yres = win->w[plane].yres;
/* No need for virtual resolution support */
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
var->bits_per_pixel = winbpp(win->w[plane].mode_winctrl1);
screen_size = var->xres_virtual * var->yres_virtual;
if (var->bits_per_pixel > 8) screen_size *= (var->bits_per_pixel / 8);
else screen_size /= (8/var->bits_per_pixel);
if (fbdev->fb_len < screen_size)
return -EINVAL; /* Virtual screen is to big, abort */
/* FIX!!!! what are the implicaitons of ignoring this for windows ??? */
/* The max LCD clock is fixed to 48MHz (value of AUX_CLK). The pixel
* clock can only be obtain by dividing this value by an even integer.
* Fallback to a slower pixel clock if necessary. */
pixclock = max((u32)(PICOS2KHZ(var->pixclock) * 1000), fbi->monspecs.dclkmin);
pixclock = min3(pixclock, fbi->monspecs.dclkmax, (u32)AU1200_LCD_MAX_CLK/2);
if (AU1200_LCD_MAX_CLK % pixclock) {
int diff = AU1200_LCD_MAX_CLK % pixclock;
pixclock -= diff;
}
var->pixclock = KHZ2PICOS(pixclock/1000);
#if 0
if (!panel_is_active(panel)) {
int pcd = AU1200_LCD_MAX_CLK / (pixclock * 2) - 1;
if (!panel_is_color(panel)
&& (panel->control_base & LCD_CONTROL_MPI) && (pcd < 3)) {
/* STN 8bit mono panel support is up to 6MHz pixclock */
var->pixclock = KHZ2PICOS(6000);
} else if (!pcd) {
/* Other STN panel support is up to 12MHz */
var->pixclock = KHZ2PICOS(12000);
}
}
#endif
/* Set bitfield accordingly */
switch (var->bits_per_pixel) {
case 16:
{
/* 16bpp True color.
* These must be set to MATCH WINCTRL[FORM] */
int idx;
idx = (win->w[0].mode_winctrl1 & LCD_WINCTRL1_FRM) >> 25;
var->red = rgb_bitfields[idx][0];
var->green = rgb_bitfields[idx][1];
var->blue = rgb_bitfields[idx][2];
var->transp = rgb_bitfields[idx][3];
break;
}
case 32:
{
/* 32bpp True color.
* These must be set to MATCH WINCTRL[FORM] */
int idx;
idx = (win->w[0].mode_winctrl1 & LCD_WINCTRL1_FRM) >> 25;
var->red = rgb_bitfields[idx][0];
var->green = rgb_bitfields[idx][1];
var->blue = rgb_bitfields[idx][2];
var->transp = rgb_bitfields[idx][3];
break;
}
default:
print_dbg("Unsupported depth %dbpp", var->bits_per_pixel);
return -EINVAL;
}
return 0;
}
/* fb_set_par
* Set hardware with var settings. This will enable the controller with a
* specific mode, normally validated with the fb_check_var method
*/
static int au1200fb_fb_set_par(struct fb_info *fbi)
{
struct au1200fb_device *fbdev = fbi->par;
au1200fb_update_fbinfo(fbi);
au1200_setmode(fbdev);
return 0;
}
/* fb_setcolreg
* Set color in LCD palette.
*/
static int au1200fb_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp, struct fb_info *fbi)
{
volatile u32 *palette = lcd->palette;
u32 value;
if (regno > (AU1200_LCD_NBR_PALETTE_ENTRIES - 1))
return -EINVAL;
if (fbi->var.grayscale) {
/* Convert color to grayscale */
red = green = blue =
(19595 * red + 38470 * green + 7471 * blue) >> 16;
}
if (fbi->fix.visual == FB_VISUAL_TRUECOLOR) {
/* Place color in the pseudopalette */
if (regno > 16)
return -EINVAL;
palette = (u32*) fbi->pseudo_palette;
red >>= (16 - fbi->var.red.length);
green >>= (16 - fbi->var.green.length);
blue >>= (16 - fbi->var.blue.length);
value = (red << fbi->var.red.offset) |
(green << fbi->var.green.offset)|
(blue << fbi->var.blue.offset);
value &= 0xFFFF;
} else if (1 /*FIX!!! panel_is_active(fbdev->panel)*/) {
/* COLOR TFT PALLETTIZED (use RGB 565) */
value = (red & 0xF800)|((green >> 5) &
0x07E0)|((blue >> 11) & 0x001F);
value &= 0xFFFF;
} else if (0 /*panel_is_color(fbdev->panel)*/) {
/* COLOR STN MODE */
value = 0x1234;
value &= 0xFFF;
} else {
/* MONOCHROME MODE */
value = (green >> 12) & 0x000F;
value &= 0xF;
}
palette[regno] = value;
return 0;
}
/* fb_blank
* Blank the screen. Depending on the mode, the screen will be
* activated with the backlight color, or desactivated
*/
static int au1200fb_fb_blank(int blank_mode, struct fb_info *fbi)
{
struct au1200fb_device *fbdev = fbi->par;
/* Short-circuit screen blanking */
if (noblanking)
return 0;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
/* printk("turn on panel\n"); */
au1200_setpanel(panel, fbdev->pd);
break;
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_POWERDOWN:
/* printk("turn off panel\n"); */
au1200_setpanel(NULL, fbdev->pd);
break;
default:
break;
}
/* FB_BLANK_NORMAL is a soft blank */
return (blank_mode == FB_BLANK_NORMAL) ? -EINVAL : 0;
}
/* fb_mmap
* Map video memory in user space. We don't use the generic fb_mmap
* method mainly to allow the use of the TLB streaming flag (CCA=6)
*/
static int au1200fb_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct au1200fb_device *fbdev = info->par;
return dma_mmap_coherent(fbdev->dev, vma,
fbdev->fb_mem, fbdev->fb_phys, fbdev->fb_len);
}
static void set_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
{
unsigned int hi1, divider;
/* SCREEN_SIZE: user cannot reset size, must switch panel choice */
if (pdata->flags & SCREEN_BACKCOLOR)
lcd->backcolor = pdata->backcolor;
if (pdata->flags & SCREEN_BRIGHTNESS) {
// limit brightness pwm duty to >= 30/1600
if (pdata->brightness < 30) {
pdata->brightness = 30;
}
divider = (lcd->pwmdiv & 0x3FFFF) + 1;
hi1 = (((pdata->brightness & 0xFF)+1) * divider >> 8);
lcd->pwmhi &= 0xFFFF;
lcd->pwmhi |= (hi1 << 16);
}
if (pdata->flags & SCREEN_COLORKEY)
lcd->colorkey = pdata->colorkey;
if (pdata->flags & SCREEN_MASK)
lcd->colorkeymsk = pdata->mask;
wmb(); /* drain writebuffer */
}
static void get_global(u_int cmd, struct au1200_lcd_global_regs_t *pdata)
{
unsigned int hi1, divider;
pdata->xsize = ((lcd->screen & LCD_SCREEN_SX) >> 19) + 1;
pdata->ysize = ((lcd->screen & LCD_SCREEN_SY) >> 8) + 1;
pdata->backcolor = lcd->backcolor;
pdata->colorkey = lcd->colorkey;
pdata->mask = lcd->colorkeymsk;
// brightness
hi1 = (lcd->pwmhi >> 16) + 1;
divider = (lcd->pwmdiv & 0x3FFFF) + 1;
pdata->brightness = ((hi1 << 8) / divider) - 1;
wmb(); /* drain writebuffer */
}
static void set_window(unsigned int plane,
struct au1200_lcd_window_regs_t *pdata)
{
unsigned int val, bpp;
/* Window control register 0 */
if (pdata->flags & WIN_POSITION) {
val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_OX |
LCD_WINCTRL0_OY);
val |= ((pdata->xpos << 21) & LCD_WINCTRL0_OX);
val |= ((pdata->ypos << 10) & LCD_WINCTRL0_OY);
lcd->window[plane].winctrl0 = val;
}
if (pdata->flags & WIN_ALPHA_COLOR) {
val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_A);
val |= ((pdata->alpha_color << 2) & LCD_WINCTRL0_A);
lcd->window[plane].winctrl0 = val;
}
if (pdata->flags & WIN_ALPHA_MODE) {
val = lcd->window[plane].winctrl0 & ~(LCD_WINCTRL0_AEN);
val |= ((pdata->alpha_mode << 1) & LCD_WINCTRL0_AEN);
lcd->window[plane].winctrl0 = val;
}
/* Window control register 1 */
if (pdata->flags & WIN_PRIORITY) {
val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PRI);
val |= ((pdata->priority << 30) & LCD_WINCTRL1_PRI);
lcd->window[plane].winctrl1 = val;
}
if (pdata->flags & WIN_CHANNEL) {
val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PIPE);
val |= ((pdata->channel << 29) & LCD_WINCTRL1_PIPE);
lcd->window[plane].winctrl1 = val;
}
if (pdata->flags & WIN_BUFFER_FORMAT) {
val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_FRM);
val |= ((pdata->buffer_format << 25) & LCD_WINCTRL1_FRM);
lcd->window[plane].winctrl1 = val;
}
if (pdata->flags & WIN_COLOR_ORDER) {
val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_CCO);
val |= ((pdata->color_order << 24) & LCD_WINCTRL1_CCO);
lcd->window[plane].winctrl1 = val;
}
if (pdata->flags & WIN_PIXEL_ORDER) {
val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_PO);
val |= ((pdata->pixel_order << 22) & LCD_WINCTRL1_PO);
lcd->window[plane].winctrl1 = val;
}
if (pdata->flags & WIN_SIZE) {
val = lcd->window[plane].winctrl1 & ~(LCD_WINCTRL1_SZX |
LCD_WINCTRL1_SZY);
val |= (((pdata->xsize << 11) - 1) & LCD_WINCTRL1_SZX);
val |= (((pdata->ysize) - 1) & LCD_WINCTRL1_SZY);
lcd->window[plane].winctrl1 = val;
/* program buffer line width */
bpp = winbpp(val) / 8;
val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_BX);
val |= (((pdata->xsize * bpp) << 8) & LCD_WINCTRL2_BX);
lcd->window[plane].winctrl2 = val;
}
/* Window control register 2 */
if (pdata->flags & WIN_COLORKEY_MODE) {
val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_CKMODE);
val |= ((pdata->colorkey_mode << 24) & LCD_WINCTRL2_CKMODE);
lcd->window[plane].winctrl2 = val;
}
if (pdata->flags & WIN_DOUBLE_BUFFER_MODE) {
val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_DBM);
val |= ((pdata->double_buffer_mode << 23) & LCD_WINCTRL2_DBM);
lcd->window[plane].winctrl2 = val;
}
if (pdata->flags & WIN_RAM_ARRAY_MODE) {
val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_RAM);
val |= ((pdata->ram_array_mode << 21) & LCD_WINCTRL2_RAM);
lcd->window[plane].winctrl2 = val;
}
/* Buffer line width programmed with WIN_SIZE */
if (pdata->flags & WIN_BUFFER_SCALE) {
val = lcd->window[plane].winctrl2 & ~(LCD_WINCTRL2_SCX |
LCD_WINCTRL2_SCY);
val |= ((pdata->xsize << 11) & LCD_WINCTRL2_SCX);
val |= ((pdata->ysize) & LCD_WINCTRL2_SCY);
lcd->window[plane].winctrl2 = val;
}
if (pdata->flags & WIN_ENABLE) {
val = lcd->winenable;
val &= ~(1<<plane);
val |= (pdata->enable & 1) << plane;
lcd->winenable = val;
}
wmb(); /* drain writebuffer */
}
static void get_window(unsigned int plane,
struct au1200_lcd_window_regs_t *pdata)
{
/* Window control register 0 */
pdata->xpos = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OX) >> 21;
pdata->ypos = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_OY) >> 10;
pdata->alpha_color = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_A) >> 2;
pdata->alpha_mode = (lcd->window[plane].winctrl0 & LCD_WINCTRL0_AEN) >> 1;
/* Window control register 1 */
pdata->priority = (lcd->window[plane].winctrl1& LCD_WINCTRL1_PRI) >> 30;
pdata->channel = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_PIPE) >> 29;
pdata->buffer_format = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_FRM) >> 25;
pdata->color_order = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_CCO) >> 24;
pdata->pixel_order = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_PO) >> 22;
pdata->xsize = ((lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZX) >> 11) + 1;
pdata->ysize = (lcd->window[plane].winctrl1 & LCD_WINCTRL1_SZY) + 1;
/* Window control register 2 */
pdata->colorkey_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_CKMODE) >> 24;
pdata->double_buffer_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_DBM) >> 23;
pdata->ram_array_mode = (lcd->window[plane].winctrl2 & LCD_WINCTRL2_RAM) >> 21;
pdata->enable = (lcd->winenable >> plane) & 1;
wmb(); /* drain writebuffer */
}
static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct au1200fb_device *fbdev = info->par;
int plane;
int val;
plane = fbinfo2index(info);
print_dbg("au1200fb: ioctl %d on plane %d\n", cmd, plane);
if (cmd == AU1200_LCD_FB_IOCTL) {
struct au1200_lcd_iodata_t iodata;
if (copy_from_user(&iodata, (void __user *) arg, sizeof(iodata)))
return -EFAULT;
print_dbg("FB IOCTL called\n");
switch (iodata.subcmd) {
case AU1200_LCD_SET_SCREEN:
print_dbg("AU1200_LCD_SET_SCREEN\n");
set_global(cmd, &iodata.global);
break;
case AU1200_LCD_GET_SCREEN:
print_dbg("AU1200_LCD_GET_SCREEN\n");
get_global(cmd, &iodata.global);
break;
case AU1200_LCD_SET_WINDOW:
print_dbg("AU1200_LCD_SET_WINDOW\n");
set_window(plane, &iodata.window);
break;
case AU1200_LCD_GET_WINDOW:
print_dbg("AU1200_LCD_GET_WINDOW\n");
get_window(plane, &iodata.window);
break;
case AU1200_LCD_SET_PANEL:
print_dbg("AU1200_LCD_SET_PANEL\n");
if ((iodata.global.panel_choice >= 0) &&
(iodata.global.panel_choice <
NUM_PANELS))
{
struct panel_settings *newpanel;
panel_index = iodata.global.panel_choice;
newpanel = &known_lcd_panels[panel_index];
au1200_setpanel(newpanel, fbdev->pd);
}
break;
case AU1200_LCD_GET_PANEL:
print_dbg("AU1200_LCD_GET_PANEL\n");
iodata.global.panel_choice = panel_index;
break;
default:
return -EINVAL;
}
val = copy_to_user((void __user *) arg, &iodata, sizeof(iodata));
if (val) {
print_dbg("error: could not copy %d bytes\n", val);
return -EFAULT;
}
}
return 0;
}
static const struct fb_ops au1200fb_fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = au1200fb_fb_check_var,
.fb_set_par = au1200fb_fb_set_par,
.fb_setcolreg = au1200fb_fb_setcolreg,
.fb_blank = au1200fb_fb_blank,
.fb_fillrect = sys_fillrect,
.fb_copyarea = sys_copyarea,
.fb_imageblit = sys_imageblit,
.fb_read = fb_sys_read,
.fb_write = fb_sys_write,
.fb_sync = NULL,
.fb_ioctl = au1200fb_ioctl,
.fb_mmap = au1200fb_fb_mmap,
};
/*-------------------------------------------------------------------------*/
static irqreturn_t au1200fb_handle_irq(int irq, void* dev_id)
{
/* Nothing to do for now, just clear any pending interrupt */
lcd->intstatus = lcd->intstatus;
wmb(); /* drain writebuffer */
return IRQ_HANDLED;
}
/*-------------------------------------------------------------------------*/
/* AU1200 LCD device probe helpers */
static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev)
{
struct fb_info *fbi = fbdev->fb_info;
int bpp, ret;
fbi->fbops = &au1200fb_fb_ops;
bpp = winbpp(win->w[fbdev->plane].mode_winctrl1);
/* Copy monitor specs from panel data */
/* fixme: we're setting up LCD controller windows, so these dont give a
damn as to what the monitor specs are (the panel itself does, but that
isn't done here...so maybe need a generic catchall monitor setting??? */
memcpy(&fbi->monspecs, &panel->monspecs, sizeof(struct fb_monspecs));
/* We first try the user mode passed in argument. If that failed,
* or if no one has been specified, we default to the first mode of the
* panel list. Note that after this call, var data will be set */
if (!fb_find_mode(&fbi->var,
fbi,
NULL, /* drv_info.opt_mode, */
fbi->monspecs.modedb,
fbi->monspecs.modedb_len,
fbi->monspecs.modedb,
bpp)) {
print_err("Cannot find valid mode for panel %s", panel->name);
return -EFAULT;
}
fbi->pseudo_palette = kcalloc(16, sizeof(u32), GFP_KERNEL);
if (!fbi->pseudo_palette)
return -ENOMEM;
ret = fb_alloc_cmap(&fbi->cmap, AU1200_LCD_NBR_PALETTE_ENTRIES, 0);
if (ret < 0) {
print_err("Fail to allocate colormap (%d entries)",
AU1200_LCD_NBR_PALETTE_ENTRIES);
return ret;
}
strncpy(fbi->fix.id, "AU1200", sizeof(fbi->fix.id));
fbi->fix.smem_start = fbdev->fb_phys;
fbi->fix.smem_len = fbdev->fb_len;
fbi->fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fix.xpanstep = 0;
fbi->fix.ypanstep = 0;
fbi->fix.mmio_start = 0;
fbi->fix.mmio_len = 0;
fbi->fix.accel = FB_ACCEL_NONE;
fbi->screen_buffer = fbdev->fb_mem;
au1200fb_update_fbinfo(fbi);
return 0;
}
/*-------------------------------------------------------------------------*/
static int au1200fb_setup(struct au1200fb_platdata *pd)
{
char *options = NULL;
char *this_opt, *endptr;
int num_panels = ARRAY_SIZE(known_lcd_panels);
int panel_idx = -1;
fb_get_options(DRIVER_NAME, &options);
if (!options)
goto out;
while ((this_opt = strsep(&options, ",")) != NULL) {
/* Panel option - can be panel name,
* "bs" for board-switch, or number/index */
if (!strncmp(this_opt, "panel:", 6)) {
int i;
long int li;
char *endptr;
this_opt += 6;
/* First check for index, which allows
* to short circuit this mess */
li = simple_strtol(this_opt, &endptr, 0);
if (*endptr == '\0')
panel_idx = (int)li;
else if (strcmp(this_opt, "bs") == 0)
panel_idx = pd->panel_index();
else {
for (i = 0; i < num_panels; i++) {
if (!strcmp(this_opt,
known_lcd_panels[i].name)) {
panel_idx = i;
break;
}
}
}
if ((panel_idx < 0) || (panel_idx >= num_panels))
print_warn("Panel %s not supported!", this_opt);
else
panel_index = panel_idx;
} else if (strncmp(this_opt, "nohwcursor", 10) == 0)
nohwcursor = 1;
else if (strncmp(this_opt, "devices:", 8) == 0) {
this_opt += 8;
device_count = simple_strtol(this_opt, &endptr, 0);
if ((device_count < 0) ||
(device_count > MAX_DEVICE_COUNT))
device_count = MAX_DEVICE_COUNT;
} else if (strncmp(this_opt, "wincfg:", 7) == 0) {
this_opt += 7;
window_index = simple_strtol(this_opt, &endptr, 0);
if ((window_index < 0) ||
(window_index >= ARRAY_SIZE(windows)))
window_index = DEFAULT_WINDOW_INDEX;
} else if (strncmp(this_opt, "off", 3) == 0)
return 1;
else
print_warn("Unsupported option \"%s\"", this_opt);
}
out:
return 0;
}
/* AU1200 LCD controller device driver */
static int au1200fb_drv_probe(struct platform_device *dev)
{
struct au1200fb_device *fbdev;
struct au1200fb_platdata *pd;
struct fb_info *fbi = NULL;
int bpp, plane, ret, irq;
print_info("" DRIVER_DESC "");
pd = dev->dev.platform_data;
if (!pd)
return -ENODEV;
/* Setup driver with options */
if (au1200fb_setup(pd))
return -ENODEV;
/* Point to the panel selected */
panel = &known_lcd_panels[panel_index];
win = &windows[window_index];
printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name);
printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name);
for (plane = 0; plane < device_count; ++plane) {
bpp = winbpp(win->w[plane].mode_winctrl1);
if (win->w[plane].xres == 0)
win->w[plane].xres = panel->Xres;
if (win->w[plane].yres == 0)
win->w[plane].yres = panel->Yres;
fbi = framebuffer_alloc(sizeof(struct au1200fb_device),
&dev->dev);
if (!fbi) {
ret = -ENOMEM;
goto failed;
}
_au1200fb_infos[plane] = fbi;
fbdev = fbi->par;
fbdev->fb_info = fbi;
fbdev->pd = pd;
fbdev->dev = &dev->dev;
fbdev->plane = plane;
/* Allocate the framebuffer to the maximum screen size */
fbdev->fb_len = (win->w[plane].xres * win->w[plane].yres * bpp) / 8;
fbdev->fb_mem = dmam_alloc_attrs(&dev->dev,
PAGE_ALIGN(fbdev->fb_len),
&fbdev->fb_phys, GFP_KERNEL, 0);
if (!fbdev->fb_mem) {
print_err("fail to allocate framebuffer (size: %dK))",
fbdev->fb_len / 1024);
ret = -ENOMEM;
goto failed;
}
print_dbg("Framebuffer memory map at %p", fbdev->fb_mem);
print_dbg("phys=0x%08x, size=%dK", fbdev->fb_phys, fbdev->fb_len / 1024);
/* Init FB data */
ret = au1200fb_init_fbinfo(fbdev);
if (ret < 0)
goto failed;
/* Register new framebuffer */
ret = register_framebuffer(fbi);
if (ret < 0) {
print_err("cannot register new framebuffer");
goto failed;
}
au1200fb_fb_set_par(fbi);
#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
if (plane == 0)
if (fb_prepare_logo(fbi, FB_ROTATE_UR)) {
/* Start display and show logo on boot */
fb_set_cmap(&fbi->cmap, fbi);
fb_show_logo(fbi, FB_ROTATE_UR);
}
#endif
}
/* Now hook interrupt too */
irq = platform_get_irq(dev, 0);
if (irq < 0)
return irq;
ret = request_irq(irq, au1200fb_handle_irq,
IRQF_SHARED, "lcd", (void *)dev);
if (ret) {
print_err("fail to request interrupt line %d (err: %d)",
irq, ret);
goto failed;
}
platform_set_drvdata(dev, pd);
/* Kickstart the panel */
au1200_setpanel(panel, pd);
return 0;
failed:
for (plane = 0; plane < device_count; ++plane) {
fbi = _au1200fb_infos[plane];
if (!fbi)
break;
/* Clean up all probe data */
unregister_framebuffer(fbi);
if (fbi->cmap.len != 0)
fb_dealloc_cmap(&fbi->cmap);
kfree(fbi->pseudo_palette);
framebuffer_release(fbi);
_au1200fb_infos[plane] = NULL;
}
return ret;
}
static void au1200fb_drv_remove(struct platform_device *dev)
{
struct au1200fb_platdata *pd = platform_get_drvdata(dev);
struct fb_info *fbi;
int plane;
/* Turn off the panel */
au1200_setpanel(NULL, pd);
for (plane = 0; plane < device_count; ++plane) {
fbi = _au1200fb_infos[plane];
/* Clean up all probe data */
unregister_framebuffer(fbi);
if (fbi->cmap.len != 0)
fb_dealloc_cmap(&fbi->cmap);
kfree(fbi->pseudo_palette);
framebuffer_release(fbi);
_au1200fb_infos[plane] = NULL;
}
free_irq(platform_get_irq(dev, 0), (void *)dev);
}
#ifdef CONFIG_PM
static int au1200fb_drv_suspend(struct device *dev)
{
struct au1200fb_platdata *pd = dev_get_drvdata(dev);
au1200_setpanel(NULL, pd);
lcd->outmask = 0;
wmb(); /* drain writebuffer */
return 0;
}
static int au1200fb_drv_resume(struct device *dev)
{
struct au1200fb_platdata *pd = dev_get_drvdata(dev);
struct fb_info *fbi;
int i;
/* Kickstart the panel */
au1200_setpanel(panel, pd);
for (i = 0; i < device_count; i++) {
fbi = _au1200fb_infos[i];
au1200fb_fb_set_par(fbi);
}
return 0;
}
static const struct dev_pm_ops au1200fb_pmops = {
.suspend = au1200fb_drv_suspend,
.resume = au1200fb_drv_resume,
.freeze = au1200fb_drv_suspend,
.thaw = au1200fb_drv_resume,
};
#define AU1200FB_PMOPS (&au1200fb_pmops)
#else
#define AU1200FB_PMOPS NULL
#endif /* CONFIG_PM */
static struct platform_driver au1200fb_driver = {
.driver = {
.name = "au1200-lcd",
.pm = AU1200FB_PMOPS,
},
.probe = au1200fb_drv_probe,
.remove_new = au1200fb_drv_remove,
};
module_platform_driver(au1200fb_driver);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/au1200fb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* HP300 Topcat framebuffer support (derived from macfb of all things)
* Phil Blundell <[email protected]> 1998
* DIO-II, colour map and Catseye support by
* Kars de Jong <[email protected]>, May 2004.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/dio.h>
#include <asm/io.h>
#include <linux/uaccess.h>
static struct fb_info fb_info = {
.fix = {
.id = "HP300 ",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.accel = FB_ACCEL_NONE,
}
};
static unsigned long fb_regs;
static unsigned char fb_bitmask;
#define TC_NBLANK 0x4080
#define TC_WEN 0x4088
#define TC_REN 0x408c
#define TC_FBEN 0x4090
#define TC_PRR 0x40ea
/* These defines match the X window system */
#define RR_CLEAR 0x0
#define RR_COPY 0x3
#define RR_NOOP 0x5
#define RR_XOR 0x6
#define RR_INVERT 0xa
#define RR_COPYINVERTED 0xc
#define RR_SET 0xf
/* blitter regs */
#define BUSY 0x4044
#define WMRR 0x40ef
#define SOURCE_X 0x40f2
#define SOURCE_Y 0x40f6
#define DEST_X 0x40fa
#define DEST_Y 0x40fe
#define WHEIGHT 0x4106
#define WWIDTH 0x4102
#define WMOVE 0x409c
static struct fb_var_screeninfo hpfb_defined = {
.red = {
.length = 8,
},
.green = {
.length = 8,
},
.blue = {
.length = 8,
},
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.vmode = FB_VMODE_NONINTERLACED,
};
static int hpfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
/* use MSBs */
unsigned char _red =red>>8;
unsigned char _green=green>>8;
unsigned char _blue =blue>>8;
unsigned char _regno=regno;
/*
* Set a single color register. The values supplied are
* already rounded down to the hardware's capabilities
* (according to the entries in the `var' structure). Return
* != 0 for invalid regno.
*/
if (regno >= info->cmap.len)
return 1;
while (in_be16(fb_regs + 0x6002) & 0x4) udelay(1);
out_be16(fb_regs + 0x60ba, 0xff);
out_be16(fb_regs + 0x60b2, _red);
out_be16(fb_regs + 0x60b4, _green);
out_be16(fb_regs + 0x60b6, _blue);
out_be16(fb_regs + 0x60b8, ~_regno);
out_be16(fb_regs + 0x60f0, 0xff);
udelay(100);
while (in_be16(fb_regs + 0x6002) & 0x4) udelay(1);
out_be16(fb_regs + 0x60b2, 0);
out_be16(fb_regs + 0x60b4, 0);
out_be16(fb_regs + 0x60b6, 0);
out_be16(fb_regs + 0x60b8, 0);
return 0;
}
/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
static int hpfb_blank(int blank, struct fb_info *info)
{
out_8(fb_regs + TC_NBLANK, (blank ? 0x00 : fb_bitmask));
return 0;
}
static void topcat_blit(int x0, int y0, int x1, int y1, int w, int h, int rr)
{
if (rr >= 0) {
while (in_8(fb_regs + BUSY) & fb_bitmask)
;
}
out_8(fb_regs + TC_FBEN, fb_bitmask);
if (rr >= 0) {
out_8(fb_regs + TC_WEN, fb_bitmask);
out_8(fb_regs + WMRR, rr);
}
out_be16(fb_regs + SOURCE_X, x0);
out_be16(fb_regs + SOURCE_Y, y0);
out_be16(fb_regs + DEST_X, x1);
out_be16(fb_regs + DEST_Y, y1);
out_be16(fb_regs + WWIDTH, w);
out_be16(fb_regs + WHEIGHT, h);
out_8(fb_regs + WMOVE, fb_bitmask);
}
static void hpfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
topcat_blit(area->sx, area->sy, area->dx, area->dy, area->width, area->height, RR_COPY);
}
static void hpfb_fillrect(struct fb_info *p, const struct fb_fillrect *region)
{
u8 clr;
clr = region->color & 0xff;
while (in_8(fb_regs + BUSY) & fb_bitmask)
;
/* Foreground */
out_8(fb_regs + TC_WEN, fb_bitmask & clr);
out_8(fb_regs + WMRR, (region->rop == ROP_COPY ? RR_SET : RR_INVERT));
/* Background */
out_8(fb_regs + TC_WEN, fb_bitmask & ~clr);
out_8(fb_regs + WMRR, (region->rop == ROP_COPY ? RR_CLEAR : RR_NOOP));
topcat_blit(region->dx, region->dy, region->dx, region->dy, region->width, region->height, -1);
}
static int hpfb_sync(struct fb_info *info)
{
/*
* Since we also access the framebuffer directly, we have to wait
* until the block mover is finished
*/
while (in_8(fb_regs + BUSY) & fb_bitmask)
;
out_8(fb_regs + TC_WEN, fb_bitmask);
out_8(fb_regs + TC_PRR, RR_COPY);
out_8(fb_regs + TC_FBEN, fb_bitmask);
return 0;
}
static const struct fb_ops hpfb_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = hpfb_setcolreg,
.fb_blank = hpfb_blank,
.fb_fillrect = hpfb_fillrect,
.fb_copyarea = hpfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_sync = hpfb_sync,
};
/* Common to all HP framebuffers */
#define HPFB_FBWMSB 0x05 /* Frame buffer width */
#define HPFB_FBWLSB 0x07
#define HPFB_FBHMSB 0x09 /* Frame buffer height */
#define HPFB_FBHLSB 0x0b
#define HPFB_DWMSB 0x0d /* Display width */
#define HPFB_DWLSB 0x0f
#define HPFB_DHMSB 0x11 /* Display height */
#define HPFB_DHLSB 0x13
#define HPFB_NUMPLANES 0x5b /* Number of colour planes */
#define HPFB_FBOMSB 0x5d /* Frame buffer offset */
#define HPFB_FBOLSB 0x5f
static int hpfb_init_one(unsigned long phys_base, unsigned long virt_base)
{
unsigned long fboff, fb_width, fb_height, fb_start;
int ret;
fb_regs = virt_base;
fboff = (in_8(fb_regs + HPFB_FBOMSB) << 8) | in_8(fb_regs + HPFB_FBOLSB);
fb_info.fix.smem_start = (in_8(fb_regs + fboff) << 16);
if (phys_base >= DIOII_BASE) {
fb_info.fix.smem_start += phys_base;
}
if (DIO_SECID(fb_regs) != DIO_ID2_TOPCAT) {
/* This is the magic incantation the HP X server uses to make Catseye boards work. */
while (in_be16(fb_regs+0x4800) & 1)
;
out_be16(fb_regs+0x4800, 0); /* Catseye status */
out_be16(fb_regs+0x4510, 0); /* VB */
out_be16(fb_regs+0x4512, 0); /* TCNTRL */
out_be16(fb_regs+0x4514, 0); /* ACNTRL */
out_be16(fb_regs+0x4516, 0); /* PNCNTRL */
out_be16(fb_regs+0x4206, 0x90); /* RUG Command/Status */
out_be16(fb_regs+0x60a2, 0); /* Overlay Mask */
out_be16(fb_regs+0x60bc, 0); /* Ram Select */
}
/*
* Fill in the available video resolution
*/
fb_width = (in_8(fb_regs + HPFB_FBWMSB) << 8) | in_8(fb_regs + HPFB_FBWLSB);
fb_info.fix.line_length = fb_width;
fb_height = (in_8(fb_regs + HPFB_FBHMSB) << 8) | in_8(fb_regs + HPFB_FBHLSB);
fb_info.fix.smem_len = fb_width * fb_height;
fb_start = (unsigned long)ioremap_wt(fb_info.fix.smem_start,
fb_info.fix.smem_len);
hpfb_defined.xres = (in_8(fb_regs + HPFB_DWMSB) << 8) | in_8(fb_regs + HPFB_DWLSB);
hpfb_defined.yres = (in_8(fb_regs + HPFB_DHMSB) << 8) | in_8(fb_regs + HPFB_DHLSB);
hpfb_defined.xres_virtual = hpfb_defined.xres;
hpfb_defined.yres_virtual = hpfb_defined.yres;
hpfb_defined.bits_per_pixel = in_8(fb_regs + HPFB_NUMPLANES);
printk(KERN_INFO "hpfb: framebuffer at 0x%lx, mapped to 0x%lx, size %dk\n",
fb_info.fix.smem_start, fb_start, fb_info.fix.smem_len/1024);
printk(KERN_INFO "hpfb: mode is %dx%dx%d, linelength=%d\n",
hpfb_defined.xres, hpfb_defined.yres, hpfb_defined.bits_per_pixel, fb_info.fix.line_length);
/*
* Give the hardware a bit of a prod and work out how many bits per
* pixel are supported.
*/
out_8(fb_regs + TC_WEN, 0xff);
out_8(fb_regs + TC_PRR, RR_COPY);
out_8(fb_regs + TC_FBEN, 0xff);
out_8(fb_start, 0xff);
fb_bitmask = in_8(fb_start);
out_8(fb_start, 0);
/*
* Enable reading/writing of all the planes.
*/
out_8(fb_regs + TC_WEN, fb_bitmask);
out_8(fb_regs + TC_PRR, RR_COPY);
out_8(fb_regs + TC_REN, fb_bitmask);
out_8(fb_regs + TC_FBEN, fb_bitmask);
/*
* Clear the screen.
*/
topcat_blit(0, 0, 0, 0, fb_width, fb_height, RR_CLEAR);
/*
* Let there be consoles..
*/
if (DIO_SECID(fb_regs) == DIO_ID2_TOPCAT)
strcat(fb_info.fix.id, "Topcat");
else
strcat(fb_info.fix.id, "Catseye");
fb_info.fbops = &hpfb_ops;
fb_info.var = hpfb_defined;
fb_info.screen_base = (char *)fb_start;
ret = fb_alloc_cmap(&fb_info.cmap, 1 << hpfb_defined.bits_per_pixel, 0);
if (ret < 0)
goto unmap_screen_base;
ret = register_framebuffer(&fb_info);
if (ret < 0)
goto dealloc_cmap;
fb_info(&fb_info, "%s frame buffer device\n", fb_info.fix.id);
return 0;
dealloc_cmap:
fb_dealloc_cmap(&fb_info.cmap);
unmap_screen_base:
if (fb_info.screen_base) {
iounmap(fb_info.screen_base);
fb_info.screen_base = NULL;
}
return ret;
}
/*
* Check that the secondary ID indicates that we have some hope of working with this
* framebuffer. The catseye boards are pretty much like topcats and we can muddle through.
*/
#define topcat_sid_ok(x) (((x) == DIO_ID2_LRCATSEYE) || ((x) == DIO_ID2_HRCCATSEYE) \
|| ((x) == DIO_ID2_HRMCATSEYE) || ((x) == DIO_ID2_TOPCAT))
/*
* Initialise the framebuffer
*/
static int hpfb_dio_probe(struct dio_dev *d, const struct dio_device_id *ent)
{
unsigned long paddr, vaddr;
paddr = d->resource.start;
if (!request_mem_region(d->resource.start, resource_size(&d->resource), d->name))
return -EBUSY;
if (d->scode >= DIOII_SCBASE) {
vaddr = (unsigned long)ioremap(paddr, resource_size(&d->resource));
} else {
vaddr = paddr + DIO_VIRADDRBASE;
}
printk(KERN_INFO "Topcat found at DIO select code %d "
"(secondary id %02x)\n", d->scode, (d->id >> 8) & 0xff);
if (hpfb_init_one(paddr, vaddr)) {
if (d->scode >= DIOII_SCBASE)
iounmap((void *)vaddr);
return -ENOMEM;
}
return 0;
}
static void hpfb_remove_one(struct dio_dev *d)
{
unregister_framebuffer(&fb_info);
if (d->scode >= DIOII_SCBASE)
iounmap((void *)fb_regs);
release_mem_region(d->resource.start, resource_size(&d->resource));
fb_dealloc_cmap(&fb_info.cmap);
if (fb_info.screen_base)
iounmap(fb_info.screen_base);
}
static struct dio_device_id hpfb_dio_tbl[] = {
{ DIO_ENCODE_ID(DIO_ID_FBUFFER, DIO_ID2_LRCATSEYE) },
{ DIO_ENCODE_ID(DIO_ID_FBUFFER, DIO_ID2_HRCCATSEYE) },
{ DIO_ENCODE_ID(DIO_ID_FBUFFER, DIO_ID2_HRMCATSEYE) },
{ DIO_ENCODE_ID(DIO_ID_FBUFFER, DIO_ID2_TOPCAT) },
{ 0 }
};
static struct dio_driver hpfb_driver = {
.name = "hpfb",
.id_table = hpfb_dio_tbl,
.probe = hpfb_dio_probe,
.remove = hpfb_remove_one,
};
static int __init hpfb_init(void)
{
unsigned int sid;
unsigned char i;
int err;
/* Topcats can be on the internal IO bus or real DIO devices.
* The internal variant sits at 0x560000; it has primary
* and secondary ID registers just like the DIO version.
* So we merge the two detection routines.
*
* Perhaps this #define should be in a global header file:
* I believe it's common to all internal fbs, not just topcat.
*/
#define INTFBVADDR 0xf0560000
#define INTFBPADDR 0x560000
if (!MACH_IS_HP300)
return -ENODEV;
if (fb_get_options("hpfb", NULL))
return -ENODEV;
err = dio_register_driver(&hpfb_driver);
if (err)
return err;
err = copy_from_kernel_nofault(&i, (unsigned char *)INTFBVADDR + DIO_IDOFF, 1);
if (!err && (i == DIO_ID_FBUFFER) && topcat_sid_ok(sid = DIO_SECID(INTFBVADDR))) {
if (!request_mem_region(INTFBPADDR, DIO_DEVSIZE, "Internal Topcat"))
return -EBUSY;
printk(KERN_INFO "Internal Topcat found (secondary id %02x)\n", sid);
if (hpfb_init_one(INTFBPADDR, INTFBVADDR)) {
return -ENOMEM;
}
}
return 0;
}
static void __exit hpfb_cleanup_module(void)
{
dio_unregister_driver(&hpfb_driver);
}
module_init(hpfb_init);
module_exit(hpfb_cleanup_module);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/hpfb.c |
/*
* linux/drivers/video/pmag-aa-fb.c
* Copyright 2002 Karsten Merker <[email protected]>
*
* PMAG-AA TurboChannel framebuffer card support ... derived from
* pmag-ba-fb.c, which is Copyright (C) 1999, 2000, 2001 by
* Michael Engel <[email protected]>, Karsten Merker <[email protected]>
* and Harald Koerfgen <[email protected]>, which itself is derived from
* "HP300 Topcat framebuffer support (derived from macfb of all things)
* Phil Blundell <[email protected]> 1998"
* Copyright (c) 2016 Maciej W. Rozycki
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* 2002-09-28 Karsten Merker <[email protected]>
* Version 0.01: First try to get a PMAG-AA running.
*
* 2003-02-24 Thiemo Seufer <[email protected]>
* Version 0.02: Major code cleanup.
*
* 2003-09-21 Thiemo Seufer <[email protected]>
* Hardware cursor support.
*
* 2016-02-21 Maciej W. Rozycki <[email protected]>
* Version 0.03: Rewritten for the new FB and TC APIs.
*/
#include <linux/compiler.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/tc.h>
#include <linux/timer.h>
#include "bt455.h"
#include "bt431.h"
/* Version information */
#define DRIVER_VERSION "0.03"
#define DRIVER_AUTHOR "Karsten Merker <[email protected]>"
#define DRIVER_DESCRIPTION "PMAG-AA Framebuffer Driver"
/*
* Bt455 RAM DAC register base offset (rel. to TC slot base address).
*/
#define PMAG_AA_BT455_OFFSET 0x100000
/*
* Bt431 cursor generator offset (rel. to TC slot base address).
*/
#define PMAG_AA_BT431_OFFSET 0x180000
/*
* Begin of PMAG-AA framebuffer memory relative to TC slot address,
* resolution is 1280x1024x1 (8 bits deep, but only LSB is used).
*/
#define PMAG_AA_ONBOARD_FBMEM_OFFSET 0x200000
struct aafb_par {
void __iomem *mmio;
struct bt455_regs __iomem *bt455;
struct bt431_regs __iomem *bt431;
};
static const struct fb_var_screeninfo aafb_defined = {
.xres = 1280,
.yres = 1024,
.xres_virtual = 2048,
.yres_virtual = 1024,
.bits_per_pixel = 8,
.grayscale = 1,
.red.length = 0,
.green.length = 1,
.blue.length = 0,
.activate = FB_ACTIVATE_NOW,
.accel_flags = FB_ACCEL_NONE,
.pixclock = 7645,
.left_margin = 224,
.right_margin = 32,
.upper_margin = 33,
.lower_margin = 3,
.hsync_len = 160,
.vsync_len = 3,
.sync = FB_SYNC_ON_GREEN,
.vmode = FB_VMODE_NONINTERLACED,
};
static const struct fb_fix_screeninfo aafb_fix = {
.id = "PMAG-AA",
.smem_len = (2048 * 1024),
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_MONO10,
.ypanstep = 1,
.ywrapstep = 1,
.line_length = 2048,
.mmio_len = PMAG_AA_ONBOARD_FBMEM_OFFSET - PMAG_AA_BT455_OFFSET,
};
static int aafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct aafb_par *par = info->par;
if (cursor->image.height > BT431_CURSOR_SIZE ||
cursor->image.width > BT431_CURSOR_SIZE) {
bt431_erase_cursor(par->bt431);
return -EINVAL;
}
if (!cursor->enable)
bt431_erase_cursor(par->bt431);
if (cursor->set & FB_CUR_SETPOS)
bt431_position_cursor(par->bt431,
cursor->image.dx, cursor->image.dy);
if (cursor->set & FB_CUR_SETCMAP) {
u8 fg = cursor->image.fg_color ? 0xf : 0x0;
u8 bg = cursor->image.bg_color ? 0xf : 0x0;
bt455_write_cmap_entry(par->bt455, 8, bg);
bt455_write_cmap_next(par->bt455, bg);
bt455_write_ovly_next(par->bt455, fg);
}
if (cursor->set & (FB_CUR_SETSIZE | FB_CUR_SETSHAPE | FB_CUR_SETIMAGE))
bt431_set_cursor(par->bt431,
cursor->image.data, cursor->mask, cursor->rop,
cursor->image.width, cursor->image.height);
if (cursor->enable)
bt431_enable_cursor(par->bt431);
return 0;
}
/* 0 unblanks, any other blanks. */
static int aafb_blank(int blank, struct fb_info *info)
{
struct aafb_par *par = info->par;
u8 val = blank ? 0x00 : 0x0f;
bt455_write_cmap_entry(par->bt455, 1, val);
return 0;
}
static const struct fb_ops aafb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_blank = aafb_blank,
.fb_cursor = aafb_cursor,
};
static int pmagaafb_probe(struct device *dev)
{
struct tc_dev *tdev = to_tc_dev(dev);
resource_size_t start, len;
struct fb_info *info;
struct aafb_par *par;
int err;
info = framebuffer_alloc(sizeof(struct aafb_par), dev);
if (!info)
return -ENOMEM;
par = info->par;
dev_set_drvdata(dev, info);
info->fbops = &aafb_ops;
info->fix = aafb_fix;
info->var = aafb_defined;
/* Request the I/O MEM resource. */
start = tdev->resource.start;
len = tdev->resource.end - start + 1;
if (!request_mem_region(start, len, dev_name(dev))) {
printk(KERN_ERR "%s: Cannot reserve FB region\n",
dev_name(dev));
err = -EBUSY;
goto err_alloc;
}
/* MMIO mapping setup. */
info->fix.mmio_start = start + PMAG_AA_BT455_OFFSET;
par->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
if (!par->mmio) {
printk(KERN_ERR "%s: Cannot map MMIO\n", dev_name(dev));
err = -ENOMEM;
goto err_resource;
}
par->bt455 = par->mmio - PMAG_AA_BT455_OFFSET + PMAG_AA_BT455_OFFSET;
par->bt431 = par->mmio - PMAG_AA_BT455_OFFSET + PMAG_AA_BT431_OFFSET;
/* Frame buffer mapping setup. */
info->fix.smem_start = start + PMAG_AA_ONBOARD_FBMEM_OFFSET;
info->screen_base = ioremap(info->fix.smem_start,
info->fix.smem_len);
if (!info->screen_base) {
printk(KERN_ERR "%s: Cannot map FB\n", dev_name(dev));
err = -ENOMEM;
goto err_mmio_map;
}
info->screen_size = info->fix.smem_len;
/* Init colormap. */
bt455_write_cmap_entry(par->bt455, 0, 0x0);
bt455_write_cmap_next(par->bt455, 0xf);
/* Init hardware cursor. */
bt431_erase_cursor(par->bt431);
bt431_init_cursor(par->bt431);
err = register_framebuffer(info);
if (err < 0) {
printk(KERN_ERR "%s: Cannot register framebuffer\n",
dev_name(dev));
goto err_smem_map;
}
get_device(dev);
pr_info("fb%d: %s frame buffer device at %s\n",
info->node, info->fix.id, dev_name(dev));
return 0;
err_smem_map:
iounmap(info->screen_base);
err_mmio_map:
iounmap(par->mmio);
err_resource:
release_mem_region(start, len);
err_alloc:
framebuffer_release(info);
return err;
}
static int pmagaafb_remove(struct device *dev)
{
struct tc_dev *tdev = to_tc_dev(dev);
struct fb_info *info = dev_get_drvdata(dev);
struct aafb_par *par = info->par;
resource_size_t start, len;
put_device(dev);
unregister_framebuffer(info);
iounmap(info->screen_base);
iounmap(par->mmio);
start = tdev->resource.start;
len = tdev->resource.end - start + 1;
release_mem_region(start, len);
framebuffer_release(info);
return 0;
}
/*
* Initialise the framebuffer.
*/
static const struct tc_device_id pmagaafb_tc_table[] = {
{ "DEC ", "PMAG-AA " },
{ }
};
MODULE_DEVICE_TABLE(tc, pmagaafb_tc_table);
static struct tc_driver pmagaafb_driver = {
.id_table = pmagaafb_tc_table,
.driver = {
.name = "pmagaafb",
.bus = &tc_bus_type,
.probe = pmagaafb_probe,
.remove = pmagaafb_remove,
},
};
static int __init pmagaafb_init(void)
{
#ifndef MODULE
if (fb_get_options("pmagaafb", NULL))
return -ENXIO;
#endif
return tc_register_driver(&pmagaafb_driver);
}
static void __exit pmagaafb_exit(void)
{
tc_unregister_driver(&pmagaafb_driver);
}
module_init(pmagaafb_init);
module_exit(pmagaafb_exit);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESCRIPTION);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/pmag-aa-fb.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/vt8500lcdfb.c
*
* Copyright (C) 2010 Alexey Charkov <[email protected]>
*
* Based on skeletonfb.c and pxafb.c
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/wait.h>
#include <video/of_display_timing.h>
#include "vt8500lcdfb.h"
#include "wmt_ge_rops.h"
#ifdef CONFIG_OF
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/memblock.h>
#endif
#define to_vt8500lcd_info(__info) container_of(__info, \
struct vt8500lcd_info, fb)
static int vt8500lcd_set_par(struct fb_info *info)
{
struct vt8500lcd_info *fbi = to_vt8500lcd_info(info);
int reg_bpp = 5; /* 16bpp */
int i;
unsigned long control0;
if (!fbi)
return -EINVAL;
if (info->var.bits_per_pixel <= 8) {
/* palettized */
info->var.red.offset = 0;
info->var.red.length = info->var.bits_per_pixel;
info->var.red.msb_right = 0;
info->var.green.offset = 0;
info->var.green.length = info->var.bits_per_pixel;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = info->var.bits_per_pixel;
info->var.blue.msb_right = 0;
info->var.transp.offset = 0;
info->var.transp.length = 0;
info->var.transp.msb_right = 0;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = info->var.xres_virtual /
(8/info->var.bits_per_pixel);
} else {
/* non-palettized */
info->var.transp.offset = 0;
info->var.transp.length = 0;
info->var.transp.msb_right = 0;
if (info->var.bits_per_pixel == 16) {
/* RGB565 */
info->var.red.offset = 11;
info->var.red.length = 5;
info->var.red.msb_right = 0;
info->var.green.offset = 5;
info->var.green.length = 6;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = 5;
info->var.blue.msb_right = 0;
} else {
/* Equal depths per channel */
info->var.red.offset = info->var.bits_per_pixel
* 2 / 3;
info->var.red.length = info->var.bits_per_pixel / 3;
info->var.red.msb_right = 0;
info->var.green.offset = info->var.bits_per_pixel / 3;
info->var.green.length = info->var.bits_per_pixel / 3;
info->var.green.msb_right = 0;
info->var.blue.offset = 0;
info->var.blue.length = info->var.bits_per_pixel / 3;
info->var.blue.msb_right = 0;
}
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.line_length = info->var.bits_per_pixel > 16 ?
info->var.xres_virtual << 2 :
info->var.xres_virtual << 1;
}
for (i = 0; i < 8; i++) {
if (bpp_values[i] == info->var.bits_per_pixel)
reg_bpp = i;
}
control0 = readl(fbi->regbase) & ~0xf;
writel(0, fbi->regbase);
while (readl(fbi->regbase + 0x38) & 0x10)
/* wait */;
writel((((info->var.hsync_len - 1) & 0x3f) << 26)
| ((info->var.left_margin & 0xff) << 18)
| (((info->var.xres - 1) & 0x3ff) << 8)
| (info->var.right_margin & 0xff), fbi->regbase + 0x4);
writel((((info->var.vsync_len - 1) & 0x3f) << 26)
| ((info->var.upper_margin & 0xff) << 18)
| (((info->var.yres - 1) & 0x3ff) << 8)
| (info->var.lower_margin & 0xff), fbi->regbase + 0x8);
writel((((info->var.yres - 1) & 0x400) << 2)
| ((info->var.xres - 1) & 0x400), fbi->regbase + 0x10);
writel(0x80000000, fbi->regbase + 0x20);
writel(control0 | (reg_bpp << 1) | 0x100, fbi->regbase);
return 0;
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int vt8500lcd_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info) {
struct vt8500lcd_info *fbi = to_vt8500lcd_info(info);
int ret = 1;
unsigned int val;
if (regno >= 256)
return -EINVAL;
if (info->var.grayscale)
red = green = blue =
(19595 * red + 38470 * green + 7471 * blue) >> 16;
switch (fbi->fb.fix.visual) {
case FB_VISUAL_TRUECOLOR:
if (regno < 16) {
u32 *pal = fbi->fb.pseudo_palette;
val = chan_to_field(red, &fbi->fb.var.red);
val |= chan_to_field(green, &fbi->fb.var.green);
val |= chan_to_field(blue, &fbi->fb.var.blue);
pal[regno] = val;
ret = 0;
}
break;
case FB_VISUAL_STATIC_PSEUDOCOLOR:
case FB_VISUAL_PSEUDOCOLOR:
writew((red & 0xf800)
| ((green >> 5) & 0x7e0)
| ((blue >> 11) & 0x1f),
fbi->palette_cpu + sizeof(u16) * regno);
break;
}
return ret;
}
static int vt8500lcd_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
int ret = 0;
struct vt8500lcd_info *fbi = to_vt8500lcd_info(info);
if (cmd == FBIO_WAITFORVSYNC) {
/* Unmask End of Frame interrupt */
writel(0xffffffff ^ (1 << 3), fbi->regbase + 0x3c);
ret = wait_event_interruptible_timeout(fbi->wait,
readl(fbi->regbase + 0x38) & (1 << 3), HZ / 10);
/* Mask back to reduce unwanted interrupt traffic */
writel(0xffffffff, fbi->regbase + 0x3c);
if (ret < 0)
return ret;
if (ret == 0)
return -ETIMEDOUT;
}
return ret;
}
static int vt8500lcd_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
unsigned pixlen = info->fix.line_length / info->var.xres_virtual;
unsigned off = pixlen * var->xoffset
+ info->fix.line_length * var->yoffset;
struct vt8500lcd_info *fbi = to_vt8500lcd_info(info);
writel((1 << 31)
| (((info->var.xres_virtual - info->var.xres) * pixlen / 4) << 20)
| (off >> 2), fbi->regbase + 0x20);
return 0;
}
/*
* vt8500lcd_blank():
* Blank the display by setting all palette values to zero. Note,
* True Color modes do not really use the palette, so this will not
* blank the display in all modes.
*/
static int vt8500lcd_blank(int blank, struct fb_info *info)
{
int i;
switch (blank) {
case FB_BLANK_POWERDOWN:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_NORMAL:
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR ||
info->fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
for (i = 0; i < 256; i++)
vt8500lcd_setcolreg(i, 0, 0, 0, 0, info);
fallthrough;
case FB_BLANK_UNBLANK:
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR ||
info->fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
fb_set_cmap(&info->cmap, info);
}
return 0;
}
static const struct fb_ops vt8500lcd_ops = {
.owner = THIS_MODULE,
.fb_set_par = vt8500lcd_set_par,
.fb_setcolreg = vt8500lcd_setcolreg,
.fb_fillrect = wmt_ge_fillrect,
.fb_copyarea = wmt_ge_copyarea,
.fb_imageblit = sys_imageblit,
.fb_sync = wmt_ge_sync,
.fb_ioctl = vt8500lcd_ioctl,
.fb_pan_display = vt8500lcd_pan_display,
.fb_blank = vt8500lcd_blank,
};
static irqreturn_t vt8500lcd_handle_irq(int irq, void *dev_id)
{
struct vt8500lcd_info *fbi = dev_id;
if (readl(fbi->regbase + 0x38) & (1 << 3))
wake_up_interruptible(&fbi->wait);
writel(0xffffffff, fbi->regbase + 0x38);
return IRQ_HANDLED;
}
static int vt8500lcd_probe(struct platform_device *pdev)
{
struct vt8500lcd_info *fbi;
struct resource *res;
struct display_timings *disp_timing;
void *addr;
int irq, ret;
struct fb_videomode of_mode;
u32 bpp;
dma_addr_t fb_mem_phys;
unsigned long fb_mem_len;
void *fb_mem_virt;
ret = -ENOMEM;
fbi = NULL;
fbi = devm_kzalloc(&pdev->dev, sizeof(struct vt8500lcd_info)
+ sizeof(u32) * 16, GFP_KERNEL);
if (!fbi)
return -ENOMEM;
strcpy(fbi->fb.fix.id, "VT8500 LCD");
fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fbi->fb.fix.xpanstep = 0;
fbi->fb.fix.ypanstep = 1;
fbi->fb.fix.ywrapstep = 0;
fbi->fb.fix.accel = FB_ACCEL_NONE;
fbi->fb.var.nonstd = 0;
fbi->fb.var.activate = FB_ACTIVATE_NOW;
fbi->fb.var.height = -1;
fbi->fb.var.width = -1;
fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
fbi->fb.fbops = &vt8500lcd_ops;
fbi->fb.flags = FBINFO_HWACCEL_COPYAREA
| FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_YPAN
| FBINFO_VIRTFB
| FBINFO_PARTIAL_PAN_OK;
fbi->fb.node = -1;
addr = fbi;
addr = addr + sizeof(struct vt8500lcd_info);
fbi->fb.pseudo_palette = addr;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "no I/O memory resource defined\n");
return -ENODEV;
}
res = request_mem_region(res->start, resource_size(res), "vt8500lcd");
if (res == NULL) {
dev_err(&pdev->dev, "failed to request I/O memory\n");
return -EBUSY;
}
fbi->regbase = ioremap(res->start, resource_size(res));
if (fbi->regbase == NULL) {
dev_err(&pdev->dev, "failed to map I/O memory\n");
ret = -EBUSY;
goto failed_free_res;
}
disp_timing = of_get_display_timings(pdev->dev.of_node);
if (!disp_timing) {
ret = -EINVAL;
goto failed_free_io;
}
ret = of_get_fb_videomode(pdev->dev.of_node, &of_mode,
OF_USE_NATIVE_MODE);
if (ret)
goto failed_free_io;
ret = of_property_read_u32(pdev->dev.of_node, "bits-per-pixel", &bpp);
if (ret)
goto failed_free_io;
/* try allocating the framebuffer */
fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
GFP_KERNEL);
if (!fb_mem_virt) {
pr_err("%s: Failed to allocate framebuffer\n", __func__);
ret = -ENOMEM;
goto failed_free_io;
}
fbi->fb.fix.smem_start = fb_mem_phys;
fbi->fb.fix.smem_len = fb_mem_len;
fbi->fb.screen_base = fb_mem_virt;
fbi->palette_size = PAGE_ALIGN(512);
fbi->palette_cpu = dma_alloc_coherent(&pdev->dev,
fbi->palette_size,
&fbi->palette_phys,
GFP_KERNEL);
if (fbi->palette_cpu == NULL) {
dev_err(&pdev->dev, "Failed to allocate palette buffer\n");
ret = -ENOMEM;
goto failed_free_io;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no IRQ defined\n");
ret = -ENODEV;
goto failed_free_palette;
}
ret = request_irq(irq, vt8500lcd_handle_irq, 0, "LCD", fbi);
if (ret) {
dev_err(&pdev->dev, "request_irq failed: %d\n", ret);
ret = -EBUSY;
goto failed_free_palette;
}
init_waitqueue_head(&fbi->wait);
if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
dev_err(&pdev->dev, "Failed to allocate color map\n");
ret = -ENOMEM;
goto failed_free_irq;
}
fb_videomode_to_var(&fbi->fb.var, &of_mode);
fbi->fb.var.xres_virtual = of_mode.xres;
fbi->fb.var.yres_virtual = of_mode.yres * 2;
fbi->fb.var.bits_per_pixel = bpp;
ret = vt8500lcd_set_par(&fbi->fb);
if (ret) {
dev_err(&pdev->dev, "Failed to set parameters\n");
goto failed_free_cmap;
}
writel(fbi->fb.fix.smem_start >> 22, fbi->regbase + 0x1c);
writel((fbi->palette_phys & 0xfffffe00) | 1, fbi->regbase + 0x18);
platform_set_drvdata(pdev, fbi);
ret = register_framebuffer(&fbi->fb);
if (ret < 0) {
dev_err(&pdev->dev,
"Failed to register framebuffer device: %d\n", ret);
goto failed_free_cmap;
}
/*
* Ok, now enable the LCD controller
*/
writel(readl(fbi->regbase) | 1, fbi->regbase);
return 0;
failed_free_cmap:
if (fbi->fb.cmap.len)
fb_dealloc_cmap(&fbi->fb.cmap);
failed_free_irq:
free_irq(irq, fbi);
failed_free_palette:
dma_free_coherent(&pdev->dev, fbi->palette_size,
fbi->palette_cpu, fbi->palette_phys);
failed_free_io:
iounmap(fbi->regbase);
failed_free_res:
release_mem_region(res->start, resource_size(res));
return ret;
}
static void vt8500lcd_remove(struct platform_device *pdev)
{
struct vt8500lcd_info *fbi = platform_get_drvdata(pdev);
struct resource *res;
int irq;
unregister_framebuffer(&fbi->fb);
writel(0, fbi->regbase);
if (fbi->fb.cmap.len)
fb_dealloc_cmap(&fbi->fb.cmap);
irq = platform_get_irq(pdev, 0);
free_irq(irq, fbi);
dma_free_coherent(&pdev->dev, fbi->palette_size,
fbi->palette_cpu, fbi->palette_phys);
iounmap(fbi->regbase);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(res->start, resource_size(res));
}
static const struct of_device_id via_dt_ids[] = {
{ .compatible = "via,vt8500-fb", },
{}
};
static struct platform_driver vt8500lcd_driver = {
.probe = vt8500lcd_probe,
.remove_new = vt8500lcd_remove,
.driver = {
.name = "vt8500-lcd",
.of_match_table = of_match_ptr(via_dt_ids),
},
};
module_platform_driver(vt8500lcd_driver);
MODULE_AUTHOR("Alexey Charkov <[email protected]>");
MODULE_DESCRIPTION("LCD controller driver for VIA VT8500");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, via_dt_ids);
| linux-master | drivers/video/fbdev/vt8500lcdfb.c |
/*
* SuperH Mobile LCDC Framebuffer
*
* Copyright (c) 2008 Magnus Damm
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/atomic.h>
#include <linux/backlight.h>
#include <linux/clk.h>
#include <linux/console.h>
#include <linux/ctype.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/fbcon.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ioctl.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/vmalloc.h>
#include <video/sh_mobile_lcdc.h>
#include "sh_mobile_lcdcfb.h"
/* ----------------------------------------------------------------------------
* Overlay register definitions
*/
#define LDBCR 0xb00
#define LDBCR_UPC(n) (1 << ((n) + 16))
#define LDBCR_UPF(n) (1 << ((n) + 8))
#define LDBCR_UPD(n) (1 << ((n) + 0))
#define LDBnBSIFR(n) (0xb20 + (n) * 0x20 + 0x00)
#define LDBBSIFR_EN (1 << 31)
#define LDBBSIFR_VS (1 << 29)
#define LDBBSIFR_BRSEL (1 << 28)
#define LDBBSIFR_MX (1 << 27)
#define LDBBSIFR_MY (1 << 26)
#define LDBBSIFR_CV3 (3 << 24)
#define LDBBSIFR_CV2 (2 << 24)
#define LDBBSIFR_CV1 (1 << 24)
#define LDBBSIFR_CV0 (0 << 24)
#define LDBBSIFR_CV_MASK (3 << 24)
#define LDBBSIFR_LAY_MASK (0xff << 16)
#define LDBBSIFR_LAY_SHIFT 16
#define LDBBSIFR_ROP3_MASK (0xff << 16)
#define LDBBSIFR_ROP3_SHIFT 16
#define LDBBSIFR_AL_PL8 (3 << 14)
#define LDBBSIFR_AL_PL1 (2 << 14)
#define LDBBSIFR_AL_PK (1 << 14)
#define LDBBSIFR_AL_1 (0 << 14)
#define LDBBSIFR_AL_MASK (3 << 14)
#define LDBBSIFR_SWPL (1 << 10)
#define LDBBSIFR_SWPW (1 << 9)
#define LDBBSIFR_SWPB (1 << 8)
#define LDBBSIFR_RY (1 << 7)
#define LDBBSIFR_CHRR_420 (2 << 0)
#define LDBBSIFR_CHRR_422 (1 << 0)
#define LDBBSIFR_CHRR_444 (0 << 0)
#define LDBBSIFR_RPKF_ARGB32 (0x00 << 0)
#define LDBBSIFR_RPKF_RGB16 (0x03 << 0)
#define LDBBSIFR_RPKF_RGB24 (0x0b << 0)
#define LDBBSIFR_RPKF_MASK (0x1f << 0)
#define LDBnBSSZR(n) (0xb20 + (n) * 0x20 + 0x04)
#define LDBBSSZR_BVSS_MASK (0xfff << 16)
#define LDBBSSZR_BVSS_SHIFT 16
#define LDBBSSZR_BHSS_MASK (0xfff << 0)
#define LDBBSSZR_BHSS_SHIFT 0
#define LDBnBLOCR(n) (0xb20 + (n) * 0x20 + 0x08)
#define LDBBLOCR_CVLC_MASK (0xfff << 16)
#define LDBBLOCR_CVLC_SHIFT 16
#define LDBBLOCR_CHLC_MASK (0xfff << 0)
#define LDBBLOCR_CHLC_SHIFT 0
#define LDBnBSMWR(n) (0xb20 + (n) * 0x20 + 0x0c)
#define LDBBSMWR_BSMWA_MASK (0xffff << 16)
#define LDBBSMWR_BSMWA_SHIFT 16
#define LDBBSMWR_BSMW_MASK (0xffff << 0)
#define LDBBSMWR_BSMW_SHIFT 0
#define LDBnBSAYR(n) (0xb20 + (n) * 0x20 + 0x10)
#define LDBBSAYR_FG1A_MASK (0xff << 24)
#define LDBBSAYR_FG1A_SHIFT 24
#define LDBBSAYR_FG1R_MASK (0xff << 16)
#define LDBBSAYR_FG1R_SHIFT 16
#define LDBBSAYR_FG1G_MASK (0xff << 8)
#define LDBBSAYR_FG1G_SHIFT 8
#define LDBBSAYR_FG1B_MASK (0xff << 0)
#define LDBBSAYR_FG1B_SHIFT 0
#define LDBnBSACR(n) (0xb20 + (n) * 0x20 + 0x14)
#define LDBBSACR_FG2A_MASK (0xff << 24)
#define LDBBSACR_FG2A_SHIFT 24
#define LDBBSACR_FG2R_MASK (0xff << 16)
#define LDBBSACR_FG2R_SHIFT 16
#define LDBBSACR_FG2G_MASK (0xff << 8)
#define LDBBSACR_FG2G_SHIFT 8
#define LDBBSACR_FG2B_MASK (0xff << 0)
#define LDBBSACR_FG2B_SHIFT 0
#define LDBnBSAAR(n) (0xb20 + (n) * 0x20 + 0x18)
#define LDBBSAAR_AP_MASK (0xff << 24)
#define LDBBSAAR_AP_SHIFT 24
#define LDBBSAAR_R_MASK (0xff << 16)
#define LDBBSAAR_R_SHIFT 16
#define LDBBSAAR_GY_MASK (0xff << 8)
#define LDBBSAAR_GY_SHIFT 8
#define LDBBSAAR_B_MASK (0xff << 0)
#define LDBBSAAR_B_SHIFT 0
#define LDBnBPPCR(n) (0xb20 + (n) * 0x20 + 0x1c)
#define LDBBPPCR_AP_MASK (0xff << 24)
#define LDBBPPCR_AP_SHIFT 24
#define LDBBPPCR_R_MASK (0xff << 16)
#define LDBBPPCR_R_SHIFT 16
#define LDBBPPCR_GY_MASK (0xff << 8)
#define LDBBPPCR_GY_SHIFT 8
#define LDBBPPCR_B_MASK (0xff << 0)
#define LDBBPPCR_B_SHIFT 0
#define LDBnBBGCL(n) (0xb10 + (n) * 0x04)
#define LDBBBGCL_BGA_MASK (0xff << 24)
#define LDBBBGCL_BGA_SHIFT 24
#define LDBBBGCL_BGR_MASK (0xff << 16)
#define LDBBBGCL_BGR_SHIFT 16
#define LDBBBGCL_BGG_MASK (0xff << 8)
#define LDBBBGCL_BGG_SHIFT 8
#define LDBBBGCL_BGB_MASK (0xff << 0)
#define LDBBBGCL_BGB_SHIFT 0
#define SIDE_B_OFFSET 0x1000
#define MIRROR_OFFSET 0x2000
#define MAX_XRES 1920
#define MAX_YRES 1080
enum sh_mobile_lcdc_overlay_mode {
LCDC_OVERLAY_BLEND,
LCDC_OVERLAY_ROP3,
};
/*
* struct sh_mobile_lcdc_overlay - LCDC display overlay
*
* @channel: LCDC channel this overlay belongs to
* @cfg: Overlay configuration
* @info: Frame buffer device
* @index: Overlay index (0-3)
* @base: Overlay registers base address
* @enabled: True if the overlay is enabled
* @mode: Overlay blending mode (alpha blend or ROP3)
* @alpha: Global alpha blending value (0-255, for alpha blending mode)
* @rop3: Raster operation (for ROP3 mode)
* @fb_mem: Frame buffer virtual memory address
* @fb_size: Frame buffer size in bytes
* @dma_handle: Frame buffer DMA address
* @base_addr_y: Overlay base address (RGB or luma component)
* @base_addr_c: Overlay base address (chroma component)
* @pan_y_offset: Panning linear offset in bytes (luma component)
* @format: Current pixelf format
* @xres: Horizontal visible resolution
* @xres_virtual: Horizontal total resolution
* @yres: Vertical visible resolution
* @yres_virtual: Vertical total resolution
* @pitch: Overlay line pitch
* @pos_x: Horizontal overlay position
* @pos_y: Vertical overlay position
*/
struct sh_mobile_lcdc_overlay {
struct sh_mobile_lcdc_chan *channel;
const struct sh_mobile_lcdc_overlay_cfg *cfg;
struct fb_info *info;
unsigned int index;
unsigned long base;
bool enabled;
enum sh_mobile_lcdc_overlay_mode mode;
unsigned int alpha;
unsigned int rop3;
void *fb_mem;
unsigned long fb_size;
dma_addr_t dma_handle;
unsigned long base_addr_y;
unsigned long base_addr_c;
unsigned long pan_y_offset;
const struct sh_mobile_lcdc_format_info *format;
unsigned int xres;
unsigned int xres_virtual;
unsigned int yres;
unsigned int yres_virtual;
unsigned int pitch;
int pos_x;
int pos_y;
};
struct sh_mobile_lcdc_priv {
void __iomem *base;
int irq;
atomic_t hw_usecnt;
struct device *dev;
struct clk *dot_clk;
unsigned long lddckr;
struct sh_mobile_lcdc_chan ch[2];
struct sh_mobile_lcdc_overlay overlays[4];
int started;
int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
};
/* -----------------------------------------------------------------------------
* Registers access
*/
static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
[LDDCKPAT1R] = 0x400,
[LDDCKPAT2R] = 0x404,
[LDMT1R] = 0x418,
[LDMT2R] = 0x41c,
[LDMT3R] = 0x420,
[LDDFR] = 0x424,
[LDSM1R] = 0x428,
[LDSM2R] = 0x42c,
[LDSA1R] = 0x430,
[LDSA2R] = 0x434,
[LDMLSR] = 0x438,
[LDHCNR] = 0x448,
[LDHSYNR] = 0x44c,
[LDVLNR] = 0x450,
[LDVSYNR] = 0x454,
[LDPMR] = 0x460,
[LDHAJR] = 0x4a0,
};
static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
[LDDCKPAT1R] = 0x408,
[LDDCKPAT2R] = 0x40c,
[LDMT1R] = 0x600,
[LDMT2R] = 0x604,
[LDMT3R] = 0x608,
[LDDFR] = 0x60c,
[LDSM1R] = 0x610,
[LDSM2R] = 0x614,
[LDSA1R] = 0x618,
[LDMLSR] = 0x620,
[LDHCNR] = 0x624,
[LDHSYNR] = 0x628,
[LDVLNR] = 0x62c,
[LDVSYNR] = 0x630,
[LDPMR] = 0x63c,
};
static bool banked(int reg_nr)
{
switch (reg_nr) {
case LDMT1R:
case LDMT2R:
case LDMT3R:
case LDDFR:
case LDSM1R:
case LDSA1R:
case LDSA2R:
case LDMLSR:
case LDHCNR:
case LDHSYNR:
case LDVLNR:
case LDVSYNR:
return true;
}
return false;
}
static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
{
return chan->cfg->chan == LCDC_CHAN_SUBLCD;
}
static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
int reg_nr, unsigned long data)
{
iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
if (banked(reg_nr))
iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
SIDE_B_OFFSET);
}
static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
int reg_nr, unsigned long data)
{
iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
MIRROR_OFFSET);
}
static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
int reg_nr)
{
return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
}
static void lcdc_write_overlay(struct sh_mobile_lcdc_overlay *ovl,
int reg, unsigned long data)
{
iowrite32(data, ovl->channel->lcdc->base + reg);
iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET);
}
static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
unsigned long reg_offs, unsigned long data)
{
iowrite32(data, priv->base + reg_offs);
}
static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
unsigned long reg_offs)
{
return ioread32(priv->base + reg_offs);
}
static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
unsigned long reg_offs,
unsigned long mask, unsigned long until)
{
while ((lcdc_read(priv, reg_offs) & mask) != until)
cpu_relax();
}
/* -----------------------------------------------------------------------------
* Clock management
*/
static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
{
if (atomic_inc_and_test(&priv->hw_usecnt)) {
clk_prepare_enable(priv->dot_clk);
pm_runtime_get_sync(priv->dev);
}
}
static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
{
if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
pm_runtime_put(priv->dev);
clk_disable_unprepare(priv->dot_clk);
}
}
static int sh_mobile_lcdc_setup_clocks(struct sh_mobile_lcdc_priv *priv,
int clock_source)
{
struct clk *clk;
char *str;
switch (clock_source) {
case LCDC_CLK_BUS:
str = "bus_clk";
priv->lddckr = LDDCKR_ICKSEL_BUS;
break;
case LCDC_CLK_PERIPHERAL:
str = "peripheral_clk";
priv->lddckr = LDDCKR_ICKSEL_MIPI;
break;
case LCDC_CLK_EXTERNAL:
str = NULL;
priv->lddckr = LDDCKR_ICKSEL_HDMI;
break;
default:
return -EINVAL;
}
if (str == NULL)
return 0;
clk = clk_get(priv->dev, str);
if (IS_ERR(clk)) {
dev_err(priv->dev, "cannot get dot clock %s\n", str);
return PTR_ERR(clk);
}
priv->dot_clk = clk;
return 0;
}
/* -----------------------------------------------------------------------------
* Display, panel and deferred I/O
*/
static void lcdc_sys_write_index(void *handle, unsigned long data)
{
struct sh_mobile_lcdc_chan *ch = handle;
lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
(lcdc_chan_is_sublcd(ch) ? 2 : 0));
lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
}
static void lcdc_sys_write_data(void *handle, unsigned long data)
{
struct sh_mobile_lcdc_chan *ch = handle;
lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
(lcdc_chan_is_sublcd(ch) ? 2 : 0));
lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
}
static unsigned long lcdc_sys_read_data(void *handle)
{
struct sh_mobile_lcdc_chan *ch = handle;
lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
(lcdc_chan_is_sublcd(ch) ? 2 : 0));
udelay(1);
lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
}
static struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
.write_index = lcdc_sys_write_index,
.write_data = lcdc_sys_write_data,
.read_data = lcdc_sys_read_data,
};
static int sh_mobile_lcdc_sginit(struct fb_info *info, struct list_head *pagereflist)
{
struct sh_mobile_lcdc_chan *ch = info->par;
unsigned int nr_pages_max = ch->fb_size >> PAGE_SHIFT;
struct fb_deferred_io_pageref *pageref;
int nr_pages = 0;
sg_init_table(ch->sglist, nr_pages_max);
list_for_each_entry(pageref, pagereflist, list) {
sg_set_page(&ch->sglist[nr_pages++], pageref->page, PAGE_SIZE, 0);
}
return nr_pages;
}
static void sh_mobile_lcdc_deferred_io(struct fb_info *info, struct list_head *pagereflist)
{
struct sh_mobile_lcdc_chan *ch = info->par;
const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
/* enable clocks before accessing hardware */
sh_mobile_lcdc_clk_on(ch->lcdc);
/*
* It's possible to get here without anything on the pagereflist via
* sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
* invocation. In the former case, the acceleration routines are
* stepped in to when using the framebuffer console causing the
* workqueue to be scheduled without any dirty pages on the list.
*
* Despite this, a panel update is still needed given that the
* acceleration routines have their own methods for writing in
* that still need to be updated.
*
* The fsync() and empty pagereflist case could be optimized for,
* but we don't bother, as any application exhibiting such
* behaviour is fundamentally broken anyways.
*/
if (!list_empty(pagereflist)) {
unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagereflist);
/* trigger panel update */
dma_map_sg(ch->lcdc->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
if (panel->start_transfer)
panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
dma_unmap_sg(ch->lcdc->dev, ch->sglist, nr_pages,
DMA_TO_DEVICE);
} else {
if (panel->start_transfer)
panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
}
}
static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
{
struct fb_deferred_io *fbdefio = info->fbdefio;
if (fbdefio)
schedule_delayed_work(&info->deferred_work, fbdefio->delay);
}
static void sh_mobile_lcdc_display_on(struct sh_mobile_lcdc_chan *ch)
{
const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
if (ch->tx_dev) {
int ret;
ret = ch->tx_dev->ops->display_on(ch->tx_dev);
if (ret < 0)
return;
if (ret == SH_MOBILE_LCDC_DISPLAY_DISCONNECTED)
ch->info->state = FBINFO_STATE_SUSPENDED;
}
/* HDMI must be enabled before LCDC configuration */
if (panel->display_on)
panel->display_on();
}
static void sh_mobile_lcdc_display_off(struct sh_mobile_lcdc_chan *ch)
{
const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
if (panel->display_off)
panel->display_off();
if (ch->tx_dev)
ch->tx_dev->ops->display_off(ch->tx_dev);
}
/* -----------------------------------------------------------------------------
* Format helpers
*/
struct sh_mobile_lcdc_format_info {
u32 fourcc;
unsigned int bpp;
bool yuv;
u32 lddfr;
};
static const struct sh_mobile_lcdc_format_info sh_mobile_format_infos[] = {
{
.fourcc = V4L2_PIX_FMT_RGB565,
.bpp = 16,
.yuv = false,
.lddfr = LDDFR_PKF_RGB16,
}, {
.fourcc = V4L2_PIX_FMT_BGR24,
.bpp = 24,
.yuv = false,
.lddfr = LDDFR_PKF_RGB24,
}, {
.fourcc = V4L2_PIX_FMT_BGR32,
.bpp = 32,
.yuv = false,
.lddfr = LDDFR_PKF_ARGB32,
}, {
.fourcc = V4L2_PIX_FMT_NV12,
.bpp = 12,
.yuv = true,
.lddfr = LDDFR_CC | LDDFR_YF_420,
}, {
.fourcc = V4L2_PIX_FMT_NV21,
.bpp = 12,
.yuv = true,
.lddfr = LDDFR_CC | LDDFR_YF_420,
}, {
.fourcc = V4L2_PIX_FMT_NV16,
.bpp = 16,
.yuv = true,
.lddfr = LDDFR_CC | LDDFR_YF_422,
}, {
.fourcc = V4L2_PIX_FMT_NV61,
.bpp = 16,
.yuv = true,
.lddfr = LDDFR_CC | LDDFR_YF_422,
}, {
.fourcc = V4L2_PIX_FMT_NV24,
.bpp = 24,
.yuv = true,
.lddfr = LDDFR_CC | LDDFR_YF_444,
}, {
.fourcc = V4L2_PIX_FMT_NV42,
.bpp = 24,
.yuv = true,
.lddfr = LDDFR_CC | LDDFR_YF_444,
},
};
static const struct sh_mobile_lcdc_format_info *
sh_mobile_format_info(u32 fourcc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(sh_mobile_format_infos); ++i) {
if (sh_mobile_format_infos[i].fourcc == fourcc)
return &sh_mobile_format_infos[i];
}
return NULL;
}
static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var)
{
if (var->grayscale > 1)
return var->grayscale;
switch (var->bits_per_pixel) {
case 16:
return V4L2_PIX_FMT_RGB565;
case 24:
return V4L2_PIX_FMT_BGR24;
case 32:
return V4L2_PIX_FMT_BGR32;
default:
return 0;
}
}
static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var)
{
return var->grayscale > 1;
}
/* -----------------------------------------------------------------------------
* Start, stop and IRQ
*/
static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
{
struct sh_mobile_lcdc_priv *priv = data;
struct sh_mobile_lcdc_chan *ch;
unsigned long ldintr;
int is_sub;
int k;
/* Acknowledge interrupts and disable further VSYNC End IRQs. */
ldintr = lcdc_read(priv, _LDINTR);
lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
/* figure out if this interrupt is for main or sub lcd */
is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
/* wake up channel and disable clocks */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
if (!ch->enabled)
continue;
/* Frame End */
if (ldintr & LDINTR_FS) {
if (is_sub == lcdc_chan_is_sublcd(ch)) {
ch->frame_end = 1;
wake_up(&ch->frame_end_wait);
sh_mobile_lcdc_clk_off(priv);
}
}
/* VSYNC End */
if (ldintr & LDINTR_VES)
complete(&ch->vsync_completion);
}
return IRQ_HANDLED;
}
static int sh_mobile_lcdc_wait_for_vsync(struct sh_mobile_lcdc_chan *ch)
{
unsigned long ldintr;
int ret;
/* Enable VSync End interrupt and be careful not to acknowledge any
* pending interrupt.
*/
ldintr = lcdc_read(ch->lcdc, _LDINTR);
ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
lcdc_write(ch->lcdc, _LDINTR, ldintr);
ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
msecs_to_jiffies(100));
if (!ret)
return -ETIMEDOUT;
return 0;
}
static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
int start)
{
unsigned long tmp = lcdc_read(priv, _LDCNT2R);
int k;
/* start or stop the lcdc */
if (start)
lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
else
lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
/* wait until power is applied/stopped on all channels */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
while (1) {
tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
& LDPMR_LPS;
if (start && tmp == LDPMR_LPS)
break;
if (!start && tmp == 0)
break;
cpu_relax();
}
if (!start)
lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
}
static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
{
const struct fb_var_screeninfo *var = &ch->info->var;
const struct fb_videomode *mode = &ch->display.mode;
unsigned long h_total, hsync_pos, display_h_total;
u32 tmp;
tmp = ch->ldmt1r_value;
tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
tmp |= (ch->cfg->flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
tmp |= (ch->cfg->flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
tmp |= (ch->cfg->flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
tmp |= (ch->cfg->flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
tmp |= (ch->cfg->flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
lcdc_write_chan(ch, LDMT1R, tmp);
/* setup SYS bus */
lcdc_write_chan(ch, LDMT2R, ch->cfg->sys_bus_cfg.ldmt2r);
lcdc_write_chan(ch, LDMT3R, ch->cfg->sys_bus_cfg.ldmt3r);
/* horizontal configuration */
h_total = mode->xres + mode->hsync_len + mode->left_margin
+ mode->right_margin;
tmp = h_total / 8; /* HTCN */
tmp |= (min(mode->xres, ch->xres) / 8) << 16; /* HDCN */
lcdc_write_chan(ch, LDHCNR, tmp);
hsync_pos = mode->xres + mode->right_margin;
tmp = hsync_pos / 8; /* HSYNP */
tmp |= (mode->hsync_len / 8) << 16; /* HSYNW */
lcdc_write_chan(ch, LDHSYNR, tmp);
/* vertical configuration */
tmp = mode->yres + mode->vsync_len + mode->upper_margin
+ mode->lower_margin; /* VTLN */
tmp |= min(mode->yres, ch->yres) << 16; /* VDLN */
lcdc_write_chan(ch, LDVLNR, tmp);
tmp = mode->yres + mode->lower_margin; /* VSYNP */
tmp |= mode->vsync_len << 16; /* VSYNW */
lcdc_write_chan(ch, LDVSYNR, tmp);
/* Adjust horizontal synchronisation for HDMI */
display_h_total = mode->xres + mode->hsync_len + mode->left_margin
+ mode->right_margin;
tmp = ((mode->xres & 7) << 24) | ((display_h_total & 7) << 16)
| ((mode->hsync_len & 7) << 8) | (hsync_pos & 7);
lcdc_write_chan(ch, LDHAJR, tmp);
lcdc_write_chan_mirror(ch, LDHAJR, tmp);
}
static void sh_mobile_lcdc_overlay_setup(struct sh_mobile_lcdc_overlay *ovl)
{
u32 format = 0;
if (!ovl->enabled) {
lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
lcdc_write_overlay(ovl, LDBnBSIFR(ovl->index), 0);
lcdc_write(ovl->channel->lcdc, LDBCR,
LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
return;
}
ovl->base_addr_y = ovl->dma_handle;
ovl->base_addr_c = ovl->dma_handle
+ ovl->xres_virtual * ovl->yres_virtual;
switch (ovl->mode) {
case LCDC_OVERLAY_BLEND:
format = LDBBSIFR_EN | (ovl->alpha << LDBBSIFR_LAY_SHIFT);
break;
case LCDC_OVERLAY_ROP3:
format = LDBBSIFR_EN | LDBBSIFR_BRSEL
| (ovl->rop3 << LDBBSIFR_ROP3_SHIFT);
break;
}
switch (ovl->format->fourcc) {
case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_NV21:
case V4L2_PIX_FMT_NV61:
case V4L2_PIX_FMT_NV42:
format |= LDBBSIFR_SWPL | LDBBSIFR_SWPW;
break;
case V4L2_PIX_FMT_BGR24:
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV24:
format |= LDBBSIFR_SWPL | LDBBSIFR_SWPW | LDBBSIFR_SWPB;
break;
case V4L2_PIX_FMT_BGR32:
default:
format |= LDBBSIFR_SWPL;
break;
}
switch (ovl->format->fourcc) {
case V4L2_PIX_FMT_RGB565:
format |= LDBBSIFR_AL_1 | LDBBSIFR_RY | LDBBSIFR_RPKF_RGB16;
break;
case V4L2_PIX_FMT_BGR24:
format |= LDBBSIFR_AL_1 | LDBBSIFR_RY | LDBBSIFR_RPKF_RGB24;
break;
case V4L2_PIX_FMT_BGR32:
format |= LDBBSIFR_AL_PK | LDBBSIFR_RY | LDBBSIFR_RPKF_ARGB32;
break;
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV21:
format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_420;
break;
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV61:
format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_422;
break;
case V4L2_PIX_FMT_NV24:
case V4L2_PIX_FMT_NV42:
format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_444;
break;
}
lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
lcdc_write_overlay(ovl, LDBnBSIFR(ovl->index), format);
lcdc_write_overlay(ovl, LDBnBSSZR(ovl->index),
(ovl->yres << LDBBSSZR_BVSS_SHIFT) |
(ovl->xres << LDBBSSZR_BHSS_SHIFT));
lcdc_write_overlay(ovl, LDBnBLOCR(ovl->index),
(ovl->pos_y << LDBBLOCR_CVLC_SHIFT) |
(ovl->pos_x << LDBBLOCR_CHLC_SHIFT));
lcdc_write_overlay(ovl, LDBnBSMWR(ovl->index),
ovl->pitch << LDBBSMWR_BSMW_SHIFT);
lcdc_write_overlay(ovl, LDBnBSAYR(ovl->index), ovl->base_addr_y);
lcdc_write_overlay(ovl, LDBnBSACR(ovl->index), ovl->base_addr_c);
lcdc_write(ovl->channel->lcdc, LDBCR,
LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
}
/*
* __sh_mobile_lcdc_start - Configure and start the LCDC
* @priv: LCDC device
*
* Configure all enabled channels and start the LCDC device. All external
* devices (clocks, MERAM, panels, ...) are not touched by this function.
*/
static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
{
struct sh_mobile_lcdc_chan *ch;
unsigned long tmp;
int k, m;
/* Enable LCDC channels. Read data from external memory, avoid using the
* BEU for now.
*/
lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
/* Stop the LCDC first and disable all interrupts. */
sh_mobile_lcdc_start_stop(priv, 0);
lcdc_write(priv, _LDINTR, 0);
/* Configure power supply, dot clocks and start them. */
tmp = priv->lddckr;
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
if (!ch->enabled)
continue;
/* Power supply */
lcdc_write_chan(ch, LDPMR, 0);
m = ch->cfg->clock_divider;
if (!m)
continue;
/* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
* denominator.
*/
lcdc_write_chan(ch, LDDCKPAT1R, 0);
lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
if (m == 1)
m = LDDCKR_MOSEL;
tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
}
lcdc_write(priv, _LDDCKR, tmp);
lcdc_write(priv, _LDDCKSTPR, 0);
lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
/* Setup geometry, format, frame buffer memory and operation mode. */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
if (!ch->enabled)
continue;
sh_mobile_lcdc_geometry(ch);
tmp = ch->format->lddfr;
if (ch->format->yuv) {
switch (ch->colorspace) {
case V4L2_COLORSPACE_REC709:
tmp |= LDDFR_CF1;
break;
case V4L2_COLORSPACE_JPEG:
tmp |= LDDFR_CF0;
break;
}
}
lcdc_write_chan(ch, LDDFR, tmp);
lcdc_write_chan(ch, LDMLSR, ch->line_size);
lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
if (ch->format->yuv)
lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
/* When using deferred I/O mode, configure the LCDC for one-shot
* operation and enable the frame end interrupt. Otherwise use
* continuous read mode.
*/
if (ch->ldmt1r_value & LDMT1R_IFM &&
ch->cfg->sys_bus_cfg.deferred_io_msec) {
lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
lcdc_write(priv, _LDINTR, LDINTR_FE);
} else {
lcdc_write_chan(ch, LDSM1R, 0);
}
}
/* Word and long word swap. */
switch (priv->ch[0].format->fourcc) {
case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_NV21:
case V4L2_PIX_FMT_NV61:
case V4L2_PIX_FMT_NV42:
tmp = LDDDSR_LS | LDDDSR_WS;
break;
case V4L2_PIX_FMT_BGR24:
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV24:
tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
break;
case V4L2_PIX_FMT_BGR32:
default:
tmp = LDDDSR_LS;
break;
}
lcdc_write(priv, _LDDDSR, tmp);
/* Enable the display output. */
lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
sh_mobile_lcdc_start_stop(priv, 1);
priv->started = 1;
}
static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
{
struct sh_mobile_lcdc_chan *ch;
unsigned long tmp;
int ret;
int k;
/* enable clocks before accessing the hardware */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
if (priv->ch[k].enabled)
sh_mobile_lcdc_clk_on(priv);
}
/* reset */
lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
const struct sh_mobile_lcdc_panel_cfg *panel;
ch = &priv->ch[k];
if (!ch->enabled)
continue;
panel = &ch->cfg->panel_cfg;
if (panel->setup_sys) {
ret = panel->setup_sys(ch, &sh_mobile_lcdc_sys_bus_ops);
if (ret)
return ret;
}
}
/* Compute frame buffer base address and pitch for each channel. */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
if (!ch->enabled)
continue;
ch->base_addr_y = ch->dma_handle;
ch->base_addr_c = ch->dma_handle
+ ch->xres_virtual * ch->yres_virtual;
ch->line_size = ch->pitch;
}
for (k = 0; k < ARRAY_SIZE(priv->overlays); ++k) {
struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[k];
sh_mobile_lcdc_overlay_setup(ovl);
}
/* Start the LCDC. */
__sh_mobile_lcdc_start(priv);
/* Setup deferred I/O, tell the board code to enable the panels, and
* turn backlight on.
*/
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
if (!ch->enabled)
continue;
tmp = ch->cfg->sys_bus_cfg.deferred_io_msec;
if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
ch->defio.delay = msecs_to_jiffies(tmp);
ch->info->fbdefio = &ch->defio;
fb_deferred_io_init(ch->info);
}
sh_mobile_lcdc_display_on(ch);
if (ch->bl) {
ch->bl->props.power = FB_BLANK_UNBLANK;
backlight_update_status(ch->bl);
}
}
return 0;
}
static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
{
struct sh_mobile_lcdc_chan *ch;
int k;
/* clean up deferred io and ask board code to disable panel */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
if (!ch->enabled)
continue;
/* deferred io mode:
* flush frame, and wait for frame end interrupt
* clean up deferred io and enable clock
*/
if (ch->info && ch->info->fbdefio) {
ch->frame_end = 0;
schedule_delayed_work(&ch->info->deferred_work, 0);
wait_event(ch->frame_end_wait, ch->frame_end);
fb_deferred_io_cleanup(ch->info);
ch->info->fbdefio = NULL;
sh_mobile_lcdc_clk_on(priv);
}
if (ch->bl) {
ch->bl->props.power = FB_BLANK_POWERDOWN;
backlight_update_status(ch->bl);
}
sh_mobile_lcdc_display_off(ch);
}
/* stop the lcdc */
if (priv->started) {
sh_mobile_lcdc_start_stop(priv, 0);
priv->started = 0;
}
/* stop clocks */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
if (priv->ch[k].enabled)
sh_mobile_lcdc_clk_off(priv);
}
static int __sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if (var->xres > MAX_XRES || var->yres > MAX_YRES)
return -EINVAL;
/* Make sure the virtual resolution is at least as big as the visible
* resolution.
*/
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
if (sh_mobile_format_is_fourcc(var)) {
const struct sh_mobile_lcdc_format_info *format;
format = sh_mobile_format_info(var->grayscale);
if (format == NULL)
return -EINVAL;
var->bits_per_pixel = format->bpp;
/* Default to RGB and JPEG color-spaces for RGB and YUV formats
* respectively.
*/
if (!format->yuv)
var->colorspace = V4L2_COLORSPACE_SRGB;
else if (var->colorspace != V4L2_COLORSPACE_REC709)
var->colorspace = V4L2_COLORSPACE_JPEG;
} else {
if (var->bits_per_pixel <= 16) { /* RGB 565 */
var->bits_per_pixel = 16;
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
} else if (var->bits_per_pixel <= 24) { /* RGB 888 */
var->bits_per_pixel = 24;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
} else if (var->bits_per_pixel <= 32) { /* RGBA 888 */
var->bits_per_pixel = 32;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
} else
return -EINVAL;
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
}
/* Make sure we don't exceed our allocated memory. */
if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
info->fix.smem_len)
return -EINVAL;
return 0;
}
/* -----------------------------------------------------------------------------
* Frame buffer operations - Overlays
*/
static ssize_t
overlay_alpha_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct sh_mobile_lcdc_overlay *ovl = info->par;
return sysfs_emit(buf, "%u\n", ovl->alpha);
}
static ssize_t
overlay_alpha_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(dev);
struct sh_mobile_lcdc_overlay *ovl = info->par;
unsigned int alpha;
char *endp;
alpha = simple_strtoul(buf, &endp, 10);
if (isspace(*endp))
endp++;
if (endp - buf != count)
return -EINVAL;
if (alpha > 255)
return -EINVAL;
if (ovl->alpha != alpha) {
ovl->alpha = alpha;
if (ovl->mode == LCDC_OVERLAY_BLEND && ovl->enabled)
sh_mobile_lcdc_overlay_setup(ovl);
}
return count;
}
static ssize_t
overlay_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct sh_mobile_lcdc_overlay *ovl = info->par;
return sysfs_emit(buf, "%u\n", ovl->mode);
}
static ssize_t
overlay_mode_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(dev);
struct sh_mobile_lcdc_overlay *ovl = info->par;
unsigned int mode;
char *endp;
mode = simple_strtoul(buf, &endp, 10);
if (isspace(*endp))
endp++;
if (endp - buf != count)
return -EINVAL;
if (mode != LCDC_OVERLAY_BLEND && mode != LCDC_OVERLAY_ROP3)
return -EINVAL;
if (ovl->mode != mode) {
ovl->mode = mode;
if (ovl->enabled)
sh_mobile_lcdc_overlay_setup(ovl);
}
return count;
}
static ssize_t
overlay_position_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct sh_mobile_lcdc_overlay *ovl = info->par;
return sysfs_emit(buf, "%d,%d\n", ovl->pos_x, ovl->pos_y);
}
static ssize_t
overlay_position_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(dev);
struct sh_mobile_lcdc_overlay *ovl = info->par;
char *endp;
int pos_x;
int pos_y;
pos_x = simple_strtol(buf, &endp, 10);
if (*endp != ',')
return -EINVAL;
pos_y = simple_strtol(endp + 1, &endp, 10);
if (isspace(*endp))
endp++;
if (endp - buf != count)
return -EINVAL;
if (ovl->pos_x != pos_x || ovl->pos_y != pos_y) {
ovl->pos_x = pos_x;
ovl->pos_y = pos_y;
if (ovl->enabled)
sh_mobile_lcdc_overlay_setup(ovl);
}
return count;
}
static ssize_t
overlay_rop3_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct sh_mobile_lcdc_overlay *ovl = info->par;
return sysfs_emit(buf, "%u\n", ovl->rop3);
}
static ssize_t
overlay_rop3_store(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(dev);
struct sh_mobile_lcdc_overlay *ovl = info->par;
unsigned int rop3;
char *endp;
rop3 = simple_strtoul(buf, &endp, 10);
if (isspace(*endp))
endp++;
if (endp - buf != count)
return -EINVAL;
if (rop3 > 255)
return -EINVAL;
if (ovl->rop3 != rop3) {
ovl->rop3 = rop3;
if (ovl->mode == LCDC_OVERLAY_ROP3 && ovl->enabled)
sh_mobile_lcdc_overlay_setup(ovl);
}
return count;
}
static const struct device_attribute overlay_sysfs_attrs[] = {
__ATTR(ovl_alpha, S_IRUGO|S_IWUSR,
overlay_alpha_show, overlay_alpha_store),
__ATTR(ovl_mode, S_IRUGO|S_IWUSR,
overlay_mode_show, overlay_mode_store),
__ATTR(ovl_position, S_IRUGO|S_IWUSR,
overlay_position_show, overlay_position_store),
__ATTR(ovl_rop3, S_IRUGO|S_IWUSR,
overlay_rop3_show, overlay_rop3_store),
};
static const struct fb_fix_screeninfo sh_mobile_lcdc_overlay_fix = {
.id = "SH Mobile LCDC",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.accel = FB_ACCEL_NONE,
.xpanstep = 1,
.ypanstep = 1,
.ywrapstep = 0,
.capabilities = FB_CAP_FOURCC,
};
static int sh_mobile_lcdc_overlay_pan(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sh_mobile_lcdc_overlay *ovl = info->par;
unsigned long base_addr_y;
unsigned long base_addr_c;
unsigned long y_offset;
unsigned long c_offset;
if (!ovl->format->yuv) {
y_offset = (var->yoffset * ovl->xres_virtual + var->xoffset)
* ovl->format->bpp / 8;
c_offset = 0;
} else {
unsigned int xsub = ovl->format->bpp < 24 ? 2 : 1;
unsigned int ysub = ovl->format->bpp < 16 ? 2 : 1;
y_offset = var->yoffset * ovl->xres_virtual + var->xoffset;
c_offset = var->yoffset / ysub * ovl->xres_virtual * 2 / xsub
+ var->xoffset * 2 / xsub;
}
/* If the Y offset hasn't changed, the C offset hasn't either. There's
* nothing to do in that case.
*/
if (y_offset == ovl->pan_y_offset)
return 0;
/* Set the source address for the next refresh */
base_addr_y = ovl->dma_handle + y_offset;
base_addr_c = ovl->dma_handle + ovl->xres_virtual * ovl->yres_virtual
+ c_offset;
ovl->base_addr_y = base_addr_y;
ovl->base_addr_c = base_addr_c;
ovl->pan_y_offset = y_offset;
lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
lcdc_write_overlay(ovl, LDBnBSAYR(ovl->index), ovl->base_addr_y);
lcdc_write_overlay(ovl, LDBnBSACR(ovl->index), ovl->base_addr_c);
lcdc_write(ovl->channel->lcdc, LDBCR,
LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
return 0;
}
static int sh_mobile_lcdc_overlay_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct sh_mobile_lcdc_overlay *ovl = info->par;
switch (cmd) {
case FBIO_WAITFORVSYNC:
return sh_mobile_lcdc_wait_for_vsync(ovl->channel);
default:
return -ENOIOCTLCMD;
}
}
static int sh_mobile_lcdc_overlay_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
return __sh_mobile_lcdc_check_var(var, info);
}
static int sh_mobile_lcdc_overlay_set_par(struct fb_info *info)
{
struct sh_mobile_lcdc_overlay *ovl = info->par;
ovl->format =
sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
ovl->xres = info->var.xres;
ovl->xres_virtual = info->var.xres_virtual;
ovl->yres = info->var.yres;
ovl->yres_virtual = info->var.yres_virtual;
if (ovl->format->yuv)
ovl->pitch = info->var.xres_virtual;
else
ovl->pitch = info->var.xres_virtual * ovl->format->bpp / 8;
sh_mobile_lcdc_overlay_setup(ovl);
info->fix.line_length = ovl->pitch;
if (sh_mobile_format_is_fourcc(&info->var)) {
info->fix.type = FB_TYPE_FOURCC;
info->fix.visual = FB_VISUAL_FOURCC;
} else {
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_TRUECOLOR;
}
return 0;
}
/* Overlay blanking. Disable the overlay when blanked. */
static int sh_mobile_lcdc_overlay_blank(int blank, struct fb_info *info)
{
struct sh_mobile_lcdc_overlay *ovl = info->par;
ovl->enabled = !blank;
sh_mobile_lcdc_overlay_setup(ovl);
/* Prevent the backlight from receiving a blanking event by returning
* a non-zero value.
*/
return 1;
}
static int
sh_mobile_lcdc_overlay_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct sh_mobile_lcdc_overlay *ovl = info->par;
if (info->fbdefio)
return fb_deferred_io_mmap(info, vma);
return dma_mmap_coherent(ovl->channel->lcdc->dev, vma, ovl->fb_mem,
ovl->dma_handle, ovl->fb_size);
}
static const struct fb_ops sh_mobile_lcdc_overlay_ops = {
.owner = THIS_MODULE,
.fb_read = fb_sys_read,
.fb_write = fb_sys_write,
.fb_fillrect = sys_fillrect,
.fb_copyarea = sys_copyarea,
.fb_imageblit = sys_imageblit,
.fb_blank = sh_mobile_lcdc_overlay_blank,
.fb_pan_display = sh_mobile_lcdc_overlay_pan,
.fb_ioctl = sh_mobile_lcdc_overlay_ioctl,
.fb_check_var = sh_mobile_lcdc_overlay_check_var,
.fb_set_par = sh_mobile_lcdc_overlay_set_par,
.fb_mmap = sh_mobile_lcdc_overlay_mmap,
};
static void
sh_mobile_lcdc_overlay_fb_unregister(struct sh_mobile_lcdc_overlay *ovl)
{
struct fb_info *info = ovl->info;
if (info == NULL || info->dev == NULL)
return;
unregister_framebuffer(ovl->info);
}
static int
sh_mobile_lcdc_overlay_fb_register(struct sh_mobile_lcdc_overlay *ovl)
{
struct sh_mobile_lcdc_priv *lcdc = ovl->channel->lcdc;
struct fb_info *info = ovl->info;
unsigned int i;
int ret;
if (info == NULL)
return 0;
ret = register_framebuffer(info);
if (ret < 0)
return ret;
dev_info(lcdc->dev, "registered %s/overlay %u as %dx%d %dbpp.\n",
dev_name(lcdc->dev), ovl->index, info->var.xres,
info->var.yres, info->var.bits_per_pixel);
for (i = 0; i < ARRAY_SIZE(overlay_sysfs_attrs); ++i) {
ret = device_create_file(info->dev, &overlay_sysfs_attrs[i]);
if (ret < 0)
return ret;
}
return 0;
}
static void
sh_mobile_lcdc_overlay_fb_cleanup(struct sh_mobile_lcdc_overlay *ovl)
{
struct fb_info *info = ovl->info;
if (info == NULL || info->device == NULL)
return;
framebuffer_release(info);
}
static int
sh_mobile_lcdc_overlay_fb_init(struct sh_mobile_lcdc_overlay *ovl)
{
struct sh_mobile_lcdc_priv *priv = ovl->channel->lcdc;
struct fb_var_screeninfo *var;
struct fb_info *info;
/* Allocate and initialize the frame buffer device. */
info = framebuffer_alloc(0, priv->dev);
if (!info)
return -ENOMEM;
ovl->info = info;
info->fbops = &sh_mobile_lcdc_overlay_ops;
info->device = priv->dev;
info->screen_buffer = ovl->fb_mem;
info->par = ovl;
/* Initialize fixed screen information. Restrict pan to 2 lines steps
* for NV12 and NV21.
*/
info->fix = sh_mobile_lcdc_overlay_fix;
snprintf(info->fix.id, sizeof(info->fix.id),
"SH Mobile LCDC Overlay %u", ovl->index);
info->fix.smem_start = ovl->dma_handle;
info->fix.smem_len = ovl->fb_size;
info->fix.line_length = ovl->pitch;
if (ovl->format->yuv)
info->fix.visual = FB_VISUAL_FOURCC;
else
info->fix.visual = FB_VISUAL_TRUECOLOR;
switch (ovl->format->fourcc) {
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV21:
info->fix.ypanstep = 2;
fallthrough;
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV61:
info->fix.xpanstep = 2;
}
/* Initialize variable screen information. */
var = &info->var;
memset(var, 0, sizeof(*var));
var->xres = ovl->xres;
var->yres = ovl->yres;
var->xres_virtual = ovl->xres_virtual;
var->yres_virtual = ovl->yres_virtual;
var->activate = FB_ACTIVATE_NOW;
/* Use the legacy API by default for RGB formats, and the FOURCC API
* for YUV formats.
*/
if (!ovl->format->yuv)
var->bits_per_pixel = ovl->format->bpp;
else
var->grayscale = ovl->format->fourcc;
return sh_mobile_lcdc_overlay_check_var(var, info);
}
/* -----------------------------------------------------------------------------
* Frame buffer operations - main frame buffer
*/
static int sh_mobile_lcdc_setcolreg(u_int regno,
u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
u32 *palette = info->pseudo_palette;
if (regno >= PALETTE_NR)
return -EINVAL;
/* only FB_VISUAL_TRUECOLOR supported */
red >>= 16 - info->var.red.length;
green >>= 16 - info->var.green.length;
blue >>= 16 - info->var.blue.length;
transp >>= 16 - info->var.transp.length;
palette[regno] = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
return 0;
}
static const struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
.id = "SH Mobile LCDC",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.accel = FB_ACCEL_NONE,
.xpanstep = 1,
.ypanstep = 1,
.ywrapstep = 0,
.capabilities = FB_CAP_FOURCC,
};
static void sh_mobile_lcdc_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
sys_fillrect(info, rect);
sh_mobile_lcdc_deferred_io_touch(info);
}
static void sh_mobile_lcdc_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
sys_copyarea(info, area);
sh_mobile_lcdc_deferred_io_touch(info);
}
static void sh_mobile_lcdc_imageblit(struct fb_info *info,
const struct fb_image *image)
{
sys_imageblit(info, image);
sh_mobile_lcdc_deferred_io_touch(info);
}
static int sh_mobile_lcdc_pan(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sh_mobile_lcdc_chan *ch = info->par;
struct sh_mobile_lcdc_priv *priv = ch->lcdc;
unsigned long ldrcntr;
unsigned long base_addr_y, base_addr_c;
unsigned long y_offset;
unsigned long c_offset;
if (!ch->format->yuv) {
y_offset = (var->yoffset * ch->xres_virtual + var->xoffset)
* ch->format->bpp / 8;
c_offset = 0;
} else {
unsigned int xsub = ch->format->bpp < 24 ? 2 : 1;
unsigned int ysub = ch->format->bpp < 16 ? 2 : 1;
y_offset = var->yoffset * ch->xres_virtual + var->xoffset;
c_offset = var->yoffset / ysub * ch->xres_virtual * 2 / xsub
+ var->xoffset * 2 / xsub;
}
/* If the Y offset hasn't changed, the C offset hasn't either. There's
* nothing to do in that case.
*/
if (y_offset == ch->pan_y_offset)
return 0;
/* Set the source address for the next refresh */
base_addr_y = ch->dma_handle + y_offset;
base_addr_c = ch->dma_handle + ch->xres_virtual * ch->yres_virtual
+ c_offset;
ch->base_addr_y = base_addr_y;
ch->base_addr_c = base_addr_c;
ch->pan_y_offset = y_offset;
lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
if (ch->format->yuv)
lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
ldrcntr = lcdc_read(priv, _LDRCNTR);
if (lcdc_chan_is_sublcd(ch))
lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
else
lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
sh_mobile_lcdc_deferred_io_touch(info);
return 0;
}
static int sh_mobile_lcdc_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct sh_mobile_lcdc_chan *ch = info->par;
int retval;
switch (cmd) {
case FBIO_WAITFORVSYNC:
retval = sh_mobile_lcdc_wait_for_vsync(ch);
break;
default:
retval = -ENOIOCTLCMD;
break;
}
return retval;
}
static void sh_mobile_fb_reconfig(struct fb_info *info)
{
struct sh_mobile_lcdc_chan *ch = info->par;
struct fb_var_screeninfo var;
struct fb_videomode mode;
if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
/* More framebuffer users are active */
return;
fb_var_to_videomode(&mode, &info->var);
if (fb_mode_is_equal(&ch->display.mode, &mode))
return;
/* Display has been re-plugged, framebuffer is free now, reconfigure */
var = info->var;
fb_videomode_to_var(&var, &ch->display.mode);
var.width = ch->display.width;
var.height = ch->display.height;
var.activate = FB_ACTIVATE_NOW;
if (fb_set_var(info, &var) < 0)
/* Couldn't reconfigure, hopefully, can continue as before */
return;
fbcon_update_vcs(info, true);
}
/*
* Locking: both .fb_release() and .fb_open() are called with info->lock held if
* user == 1, or with console sem held, if user == 0.
*/
static int sh_mobile_lcdc_release(struct fb_info *info, int user)
{
struct sh_mobile_lcdc_chan *ch = info->par;
mutex_lock(&ch->open_lock);
dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
ch->use_count--;
/* Nothing to reconfigure, when called from fbcon */
if (user) {
console_lock();
sh_mobile_fb_reconfig(info);
console_unlock();
}
mutex_unlock(&ch->open_lock);
return 0;
}
static int sh_mobile_lcdc_open(struct fb_info *info, int user)
{
struct sh_mobile_lcdc_chan *ch = info->par;
mutex_lock(&ch->open_lock);
ch->use_count++;
dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
mutex_unlock(&ch->open_lock);
return 0;
}
static int sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sh_mobile_lcdc_chan *ch = info->par;
struct sh_mobile_lcdc_priv *p = ch->lcdc;
unsigned int best_dist = (unsigned int)-1;
unsigned int best_xres = 0;
unsigned int best_yres = 0;
unsigned int i;
int ret;
/* If board code provides us with a list of available modes, make sure
* we use one of them. Find the mode closest to the requested one. The
* distance between two modes is defined as the size of the
* non-overlapping parts of the two rectangles.
*/
for (i = 0; i < ch->cfg->num_modes; ++i) {
const struct fb_videomode *mode = &ch->cfg->lcd_modes[i];
unsigned int dist;
/* We can only round up. */
if (var->xres > mode->xres || var->yres > mode->yres)
continue;
dist = var->xres * var->yres + mode->xres * mode->yres
- 2 * min(var->xres, mode->xres)
* min(var->yres, mode->yres);
if (dist < best_dist) {
best_xres = mode->xres;
best_yres = mode->yres;
best_dist = dist;
}
}
/* If no available mode can be used, return an error. */
if (ch->cfg->num_modes != 0) {
if (best_dist == (unsigned int)-1)
return -EINVAL;
var->xres = best_xres;
var->yres = best_yres;
}
ret = __sh_mobile_lcdc_check_var(var, info);
if (ret < 0)
return ret;
/* only accept the forced_fourcc for dual channel configurations */
if (p->forced_fourcc &&
p->forced_fourcc != sh_mobile_format_fourcc(var))
return -EINVAL;
return 0;
}
static int sh_mobile_lcdc_set_par(struct fb_info *info)
{
struct sh_mobile_lcdc_chan *ch = info->par;
int ret;
sh_mobile_lcdc_stop(ch->lcdc);
ch->format = sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
ch->colorspace = info->var.colorspace;
ch->xres = info->var.xres;
ch->xres_virtual = info->var.xres_virtual;
ch->yres = info->var.yres;
ch->yres_virtual = info->var.yres_virtual;
if (ch->format->yuv)
ch->pitch = info->var.xres_virtual;
else
ch->pitch = info->var.xres_virtual * ch->format->bpp / 8;
ret = sh_mobile_lcdc_start(ch->lcdc);
if (ret < 0)
dev_err(info->dev, "%s: unable to restart LCDC\n", __func__);
info->fix.line_length = ch->pitch;
if (sh_mobile_format_is_fourcc(&info->var)) {
info->fix.type = FB_TYPE_FOURCC;
info->fix.visual = FB_VISUAL_FOURCC;
} else {
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_TRUECOLOR;
}
return ret;
}
/*
* Screen blanking. Behavior is as follows:
* FB_BLANK_UNBLANK: screen unblanked, clocks enabled
* FB_BLANK_NORMAL: screen blanked, clocks enabled
* FB_BLANK_VSYNC,
* FB_BLANK_HSYNC,
* FB_BLANK_POWEROFF: screen blanked, clocks disabled
*/
static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
{
struct sh_mobile_lcdc_chan *ch = info->par;
struct sh_mobile_lcdc_priv *p = ch->lcdc;
/* blank the screen? */
if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
struct fb_fillrect rect = {
.width = ch->xres,
.height = ch->yres,
};
sh_mobile_lcdc_fillrect(info, &rect);
}
/* turn clocks on? */
if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
sh_mobile_lcdc_clk_on(p);
}
/* turn clocks off? */
if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
/* make sure the screen is updated with the black fill before
* switching the clocks off. one vsync is not enough since
* blanking may occur in the middle of a refresh. deferred io
* mode will reenable the clocks and update the screen in time,
* so it does not need this. */
if (!info->fbdefio) {
sh_mobile_lcdc_wait_for_vsync(ch);
sh_mobile_lcdc_wait_for_vsync(ch);
}
sh_mobile_lcdc_clk_off(p);
}
ch->blank_status = blank;
return 0;
}
static int
sh_mobile_lcdc_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct sh_mobile_lcdc_chan *ch = info->par;
if (info->fbdefio)
return fb_deferred_io_mmap(info, vma);
return dma_mmap_coherent(ch->lcdc->dev, vma, ch->fb_mem,
ch->dma_handle, ch->fb_size);
}
static const struct fb_ops sh_mobile_lcdc_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = sh_mobile_lcdc_setcolreg,
.fb_read = fb_sys_read,
.fb_write = fb_sys_write,
.fb_fillrect = sh_mobile_lcdc_fillrect,
.fb_copyarea = sh_mobile_lcdc_copyarea,
.fb_imageblit = sh_mobile_lcdc_imageblit,
.fb_blank = sh_mobile_lcdc_blank,
.fb_pan_display = sh_mobile_lcdc_pan,
.fb_ioctl = sh_mobile_lcdc_ioctl,
.fb_open = sh_mobile_lcdc_open,
.fb_release = sh_mobile_lcdc_release,
.fb_check_var = sh_mobile_lcdc_check_var,
.fb_set_par = sh_mobile_lcdc_set_par,
.fb_mmap = sh_mobile_lcdc_mmap,
};
static void
sh_mobile_lcdc_channel_fb_unregister(struct sh_mobile_lcdc_chan *ch)
{
if (ch->info && ch->info->dev)
unregister_framebuffer(ch->info);
}
static int
sh_mobile_lcdc_channel_fb_register(struct sh_mobile_lcdc_chan *ch)
{
struct fb_info *info = ch->info;
int ret;
if (info->fbdefio) {
ch->sglist = vmalloc(sizeof(struct scatterlist) *
ch->fb_size >> PAGE_SHIFT);
if (!ch->sglist)
return -ENOMEM;
}
info->bl_dev = ch->bl;
ret = register_framebuffer(info);
if (ret < 0)
return ret;
dev_info(ch->lcdc->dev, "registered %s/%s as %dx%d %dbpp.\n",
dev_name(ch->lcdc->dev), (ch->cfg->chan == LCDC_CHAN_MAINLCD) ?
"mainlcd" : "sublcd", info->var.xres, info->var.yres,
info->var.bits_per_pixel);
/* deferred io mode: disable clock to save power */
if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
sh_mobile_lcdc_clk_off(ch->lcdc);
return ret;
}
static void
sh_mobile_lcdc_channel_fb_cleanup(struct sh_mobile_lcdc_chan *ch)
{
struct fb_info *info = ch->info;
if (!info || !info->device)
return;
vfree(ch->sglist);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
static int
sh_mobile_lcdc_channel_fb_init(struct sh_mobile_lcdc_chan *ch,
const struct fb_videomode *modes,
unsigned int num_modes)
{
struct sh_mobile_lcdc_priv *priv = ch->lcdc;
struct fb_var_screeninfo *var;
struct fb_info *info;
int ret;
/* Allocate and initialize the frame buffer device. Create the modes
* list and allocate the color map.
*/
info = framebuffer_alloc(0, priv->dev);
if (!info)
return -ENOMEM;
ch->info = info;
info->fbops = &sh_mobile_lcdc_ops;
info->device = priv->dev;
info->screen_buffer = ch->fb_mem;
info->pseudo_palette = &ch->pseudo_palette;
info->par = ch;
fb_videomode_to_modelist(modes, num_modes, &info->modelist);
ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
if (ret < 0) {
dev_err(priv->dev, "unable to allocate cmap\n");
return ret;
}
/* Initialize fixed screen information. Restrict pan to 2 lines steps
* for NV12 and NV21.
*/
info->fix = sh_mobile_lcdc_fix;
info->fix.smem_start = ch->dma_handle;
info->fix.smem_len = ch->fb_size;
info->fix.line_length = ch->pitch;
if (ch->format->yuv)
info->fix.visual = FB_VISUAL_FOURCC;
else
info->fix.visual = FB_VISUAL_TRUECOLOR;
switch (ch->format->fourcc) {
case V4L2_PIX_FMT_NV12:
case V4L2_PIX_FMT_NV21:
info->fix.ypanstep = 2;
fallthrough;
case V4L2_PIX_FMT_NV16:
case V4L2_PIX_FMT_NV61:
info->fix.xpanstep = 2;
}
/* Initialize variable screen information using the first mode as
* default.
*/
var = &info->var;
fb_videomode_to_var(var, modes);
var->width = ch->display.width;
var->height = ch->display.height;
var->xres_virtual = ch->xres_virtual;
var->yres_virtual = ch->yres_virtual;
var->activate = FB_ACTIVATE_NOW;
/* Use the legacy API by default for RGB formats, and the FOURCC API
* for YUV formats.
*/
if (!ch->format->yuv)
var->bits_per_pixel = ch->format->bpp;
else
var->grayscale = ch->format->fourcc;
ret = sh_mobile_lcdc_check_var(var, info);
if (ret)
return ret;
return 0;
}
/* -----------------------------------------------------------------------------
* Backlight
*/
static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
{
struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
int brightness = bdev->props.brightness;
if (bdev->props.power != FB_BLANK_UNBLANK ||
bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
brightness = 0;
ch->bl_brightness = brightness;
return ch->cfg->bl_info.set_brightness(brightness);
}
static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
{
struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
return ch->bl_brightness;
}
static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
struct fb_info *info)
{
return (info->bl_dev == bdev);
}
static const struct backlight_ops sh_mobile_lcdc_bl_ops = {
.options = BL_CORE_SUSPENDRESUME,
.update_status = sh_mobile_lcdc_update_bl,
.get_brightness = sh_mobile_lcdc_get_brightness,
.check_fb = sh_mobile_lcdc_check_fb,
};
static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
struct sh_mobile_lcdc_chan *ch)
{
struct backlight_device *bl;
bl = backlight_device_register(ch->cfg->bl_info.name, parent, ch,
&sh_mobile_lcdc_bl_ops, NULL);
if (IS_ERR(bl)) {
dev_err(parent, "unable to register backlight device: %ld\n",
PTR_ERR(bl));
return NULL;
}
bl->props.max_brightness = ch->cfg->bl_info.max_brightness;
bl->props.brightness = bl->props.max_brightness;
backlight_update_status(bl);
return bl;
}
static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
{
backlight_device_unregister(bdev);
}
/* -----------------------------------------------------------------------------
* Power management
*/
static int sh_mobile_lcdc_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
return 0;
}
static int sh_mobile_lcdc_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
}
static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
{
struct sh_mobile_lcdc_priv *priv = dev_get_drvdata(dev);
/* turn off LCDC hardware */
lcdc_write(priv, _LDCNT1R, 0);
return 0;
}
static int sh_mobile_lcdc_runtime_resume(struct device *dev)
{
struct sh_mobile_lcdc_priv *priv = dev_get_drvdata(dev);
__sh_mobile_lcdc_start(priv);
return 0;
}
static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
.suspend = sh_mobile_lcdc_suspend,
.resume = sh_mobile_lcdc_resume,
.runtime_suspend = sh_mobile_lcdc_runtime_suspend,
.runtime_resume = sh_mobile_lcdc_runtime_resume,
};
/* -----------------------------------------------------------------------------
* Framebuffer notifier
*/
/* -----------------------------------------------------------------------------
* Probe/remove and driver init/exit
*/
static const struct fb_videomode default_720p = {
.name = "HDMI 720p",
.xres = 1280,
.yres = 720,
.left_margin = 220,
.right_margin = 110,
.hsync_len = 40,
.upper_margin = 20,
.lower_margin = 5,
.vsync_len = 5,
.pixclock = 13468,
.refresh = 60,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
};
static void sh_mobile_lcdc_remove(struct platform_device *pdev)
{
struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
unsigned int i;
for (i = 0; i < ARRAY_SIZE(priv->overlays); i++)
sh_mobile_lcdc_overlay_fb_unregister(&priv->overlays[i]);
for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
sh_mobile_lcdc_channel_fb_unregister(&priv->ch[i]);
sh_mobile_lcdc_stop(priv);
for (i = 0; i < ARRAY_SIZE(priv->overlays); i++) {
struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
sh_mobile_lcdc_overlay_fb_cleanup(ovl);
if (ovl->fb_mem)
dma_free_coherent(&pdev->dev, ovl->fb_size,
ovl->fb_mem, ovl->dma_handle);
}
for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
if (ch->tx_dev) {
ch->tx_dev->lcdc = NULL;
module_put(ch->cfg->tx_dev->dev.driver->owner);
}
sh_mobile_lcdc_channel_fb_cleanup(ch);
if (ch->fb_mem)
dma_free_coherent(&pdev->dev, ch->fb_size,
ch->fb_mem, ch->dma_handle);
}
for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
if (ch->bl)
sh_mobile_lcdc_bl_remove(ch->bl);
mutex_destroy(&ch->open_lock);
}
if (priv->dot_clk) {
pm_runtime_disable(&pdev->dev);
clk_put(priv->dot_clk);
}
if (priv->base)
iounmap(priv->base);
if (priv->irq)
free_irq(priv->irq, priv);
kfree(priv);
}
static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
{
int interface_type = ch->cfg->interface_type;
switch (interface_type) {
case RGB8:
case RGB9:
case RGB12A:
case RGB12B:
case RGB16:
case RGB18:
case RGB24:
case SYS8A:
case SYS8B:
case SYS8C:
case SYS8D:
case SYS9:
case SYS12:
case SYS16A:
case SYS16B:
case SYS16C:
case SYS18:
case SYS24:
break;
default:
return -EINVAL;
}
/* SUBLCD only supports SYS interface */
if (lcdc_chan_is_sublcd(ch)) {
if (!(interface_type & LDMT1R_IFM))
return -EINVAL;
interface_type &= ~LDMT1R_IFM;
}
ch->ldmt1r_value = interface_type;
return 0;
}
static int
sh_mobile_lcdc_overlay_init(struct sh_mobile_lcdc_overlay *ovl)
{
const struct sh_mobile_lcdc_format_info *format;
struct device *dev = ovl->channel->lcdc->dev;
int ret;
if (ovl->cfg->fourcc == 0)
return 0;
/* Validate the format. */
format = sh_mobile_format_info(ovl->cfg->fourcc);
if (format == NULL) {
dev_err(dev, "Invalid FOURCC %08x\n", ovl->cfg->fourcc);
return -EINVAL;
}
ovl->enabled = false;
ovl->mode = LCDC_OVERLAY_BLEND;
ovl->alpha = 255;
ovl->rop3 = 0;
ovl->pos_x = 0;
ovl->pos_y = 0;
/* The default Y virtual resolution is twice the panel size to allow for
* double-buffering.
*/
ovl->format = format;
ovl->xres = ovl->cfg->max_xres;
ovl->xres_virtual = ovl->xres;
ovl->yres = ovl->cfg->max_yres;
ovl->yres_virtual = ovl->yres * 2;
if (!format->yuv)
ovl->pitch = ovl->xres_virtual * format->bpp / 8;
else
ovl->pitch = ovl->xres_virtual;
/* Allocate frame buffer memory. */
ovl->fb_size = ovl->cfg->max_xres * ovl->cfg->max_yres
* format->bpp / 8 * 2;
ovl->fb_mem = dma_alloc_coherent(dev, ovl->fb_size, &ovl->dma_handle,
GFP_KERNEL);
if (!ovl->fb_mem) {
dev_err(dev, "unable to allocate buffer\n");
return -ENOMEM;
}
ret = sh_mobile_lcdc_overlay_fb_init(ovl);
if (ret < 0)
return ret;
return 0;
}
static int
sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_chan *ch)
{
const struct sh_mobile_lcdc_format_info *format;
const struct sh_mobile_lcdc_chan_cfg *cfg = ch->cfg;
struct device *dev = ch->lcdc->dev;
const struct fb_videomode *max_mode;
const struct fb_videomode *mode;
unsigned int num_modes;
unsigned int max_size;
unsigned int i;
/* Validate the format. */
format = sh_mobile_format_info(cfg->fourcc);
if (format == NULL) {
dev_err(dev, "Invalid FOURCC %08x.\n", cfg->fourcc);
return -EINVAL;
}
/* Iterate through the modes to validate them and find the highest
* resolution.
*/
max_mode = NULL;
max_size = 0;
for (i = 0, mode = cfg->lcd_modes; i < cfg->num_modes; i++, mode++) {
unsigned int size = mode->yres * mode->xres;
/* NV12/NV21 buffers must have even number of lines */
if ((cfg->fourcc == V4L2_PIX_FMT_NV12 ||
cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) {
dev_err(dev, "yres must be multiple of 2 for "
"YCbCr420 mode.\n");
return -EINVAL;
}
if (size > max_size) {
max_mode = mode;
max_size = size;
}
}
if (!max_size)
max_size = MAX_XRES * MAX_YRES;
else
dev_dbg(dev, "Found largest videomode %ux%u\n",
max_mode->xres, max_mode->yres);
if (cfg->lcd_modes == NULL) {
mode = &default_720p;
num_modes = 1;
} else {
mode = cfg->lcd_modes;
num_modes = cfg->num_modes;
}
/* Use the first mode as default. The default Y virtual resolution is
* twice the panel size to allow for double-buffering.
*/
ch->format = format;
ch->xres = mode->xres;
ch->xres_virtual = mode->xres;
ch->yres = mode->yres;
ch->yres_virtual = mode->yres * 2;
if (!format->yuv) {
ch->colorspace = V4L2_COLORSPACE_SRGB;
ch->pitch = ch->xres_virtual * format->bpp / 8;
} else {
ch->colorspace = V4L2_COLORSPACE_REC709;
ch->pitch = ch->xres_virtual;
}
ch->display.width = cfg->panel_cfg.width;
ch->display.height = cfg->panel_cfg.height;
ch->display.mode = *mode;
/* Allocate frame buffer memory. */
ch->fb_size = max_size * format->bpp / 8 * 2;
ch->fb_mem = dma_alloc_coherent(dev, ch->fb_size, &ch->dma_handle,
GFP_KERNEL);
if (ch->fb_mem == NULL) {
dev_err(dev, "unable to allocate buffer\n");
return -ENOMEM;
}
/* Initialize the transmitter device if present. */
if (cfg->tx_dev) {
if (!cfg->tx_dev->dev.driver ||
!try_module_get(cfg->tx_dev->dev.driver->owner)) {
dev_warn(dev, "unable to get transmitter device\n");
return -EINVAL;
}
ch->tx_dev = platform_get_drvdata(cfg->tx_dev);
ch->tx_dev->lcdc = ch;
ch->tx_dev->def_mode = *mode;
}
return sh_mobile_lcdc_channel_fb_init(ch, mode, num_modes);
}
static int sh_mobile_lcdc_probe(struct platform_device *pdev)
{
struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
struct sh_mobile_lcdc_priv *priv;
struct resource *res;
int num_channels;
int error;
int irq, i;
if (!pdata) {
dev_err(&pdev->dev, "no platform data defined\n");
return -EINVAL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq = platform_get_irq(pdev, 0);
if (!res || irq < 0) {
dev_err(&pdev->dev, "cannot get platform resources\n");
return -ENOENT;
}
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = &pdev->dev;
for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
mutex_init(&priv->ch[i].open_lock);
platform_set_drvdata(pdev, priv);
error = request_irq(irq, sh_mobile_lcdc_irq, 0,
dev_name(&pdev->dev), priv);
if (error) {
dev_err(&pdev->dev, "unable to request irq\n");
goto err1;
}
priv->irq = irq;
atomic_set(&priv->hw_usecnt, -1);
for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) {
struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels;
ch->lcdc = priv;
ch->cfg = &pdata->ch[i];
error = sh_mobile_lcdc_check_interface(ch);
if (error) {
dev_err(&pdev->dev, "unsupported interface type\n");
goto err1;
}
init_waitqueue_head(&ch->frame_end_wait);
init_completion(&ch->vsync_completion);
/* probe the backlight is there is one defined */
if (ch->cfg->bl_info.max_brightness)
ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
switch (pdata->ch[i].chan) {
case LCDC_CHAN_MAINLCD:
ch->enabled = LDCNT2R_ME;
ch->reg_offs = lcdc_offs_mainlcd;
num_channels++;
break;
case LCDC_CHAN_SUBLCD:
ch->enabled = LDCNT2R_SE;
ch->reg_offs = lcdc_offs_sublcd;
num_channels++;
break;
}
}
if (!num_channels) {
dev_err(&pdev->dev, "no channels defined\n");
error = -EINVAL;
goto err1;
}
/* for dual channel LCDC (MAIN + SUB) force shared format setting */
if (num_channels == 2)
priv->forced_fourcc = pdata->ch[0].fourcc;
priv->base = ioremap(res->start, resource_size(res));
if (!priv->base) {
error = -ENOMEM;
goto err1;
}
error = sh_mobile_lcdc_setup_clocks(priv, pdata->clock_source);
if (error) {
dev_err(&pdev->dev, "unable to setup clocks\n");
goto err1;
}
/* Enable runtime PM. */
pm_runtime_enable(&pdev->dev);
for (i = 0; i < num_channels; i++) {
struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
error = sh_mobile_lcdc_channel_init(ch);
if (error)
goto err1;
}
for (i = 0; i < ARRAY_SIZE(pdata->overlays); i++) {
struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
ovl->cfg = &pdata->overlays[i];
ovl->channel = &priv->ch[0];
error = sh_mobile_lcdc_overlay_init(ovl);
if (error)
goto err1;
}
error = sh_mobile_lcdc_start(priv);
if (error) {
dev_err(&pdev->dev, "unable to start hardware\n");
goto err1;
}
for (i = 0; i < num_channels; i++) {
struct sh_mobile_lcdc_chan *ch = priv->ch + i;
error = sh_mobile_lcdc_channel_fb_register(ch);
if (error)
goto err1;
}
for (i = 0; i < ARRAY_SIZE(pdata->overlays); i++) {
struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
error = sh_mobile_lcdc_overlay_fb_register(ovl);
if (error)
goto err1;
}
return 0;
err1:
sh_mobile_lcdc_remove(pdev);
return error;
}
static struct platform_driver sh_mobile_lcdc_driver = {
.driver = {
.name = "sh_mobile_lcdc_fb",
.pm = &sh_mobile_lcdc_dev_pm_ops,
},
.probe = sh_mobile_lcdc_probe,
.remove_new = sh_mobile_lcdc_remove,
};
module_platform_driver(sh_mobile_lcdc_driver);
MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
MODULE_AUTHOR("Magnus Damm <[email protected]>");
MODULE_LICENSE("GPL v2");
| linux-master | drivers/video/fbdev/sh_mobile_lcdcfb.c |
/*
* linux/drivers/video/n411.c -- Platform device for N411 EPD kit
*
* Copyright (C) 2008, Jaya Kumar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven.
*
* This driver is written to be used with the Hecuba display controller
* board, and tested with the EInk 800x600 display in 1 bit mode.
* The interface between Hecuba and the host is TTL based GPIO. The
* GPIO requirements are 8 writable data lines and 6 lines for control.
* Only 4 of the controls are actually used here but 6 for future use.
* The driver requires the IO addresses for data and control GPIO at
* load time. It is also possible to use this display with a standard
* PC parallel port.
*
* General notes:
* - User must set dio_addr=0xIOADDR cio_addr=0xIOADDR c2io_addr=0xIOADDR
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/list.h>
#include <linux/uaccess.h>
#include <linux/irq.h>
#include <video/hecubafb.h>
static unsigned long dio_addr;
static unsigned long cio_addr;
static unsigned long c2io_addr;
static unsigned long splashval;
static unsigned int nosplash;
static unsigned char ctl;
static void n411_set_ctl(struct hecubafb_par *par, unsigned char bit, unsigned
char state)
{
switch (bit) {
case HCB_CD_BIT:
if (state)
ctl &= ~(HCB_CD_BIT);
else
ctl |= HCB_CD_BIT;
break;
case HCB_DS_BIT:
if (state)
ctl &= ~(HCB_DS_BIT);
else
ctl |= HCB_DS_BIT;
break;
}
outb(ctl, cio_addr);
}
static unsigned char n411_get_ctl(struct hecubafb_par *par)
{
return inb(c2io_addr);
}
static void n411_set_data(struct hecubafb_par *par, unsigned char value)
{
outb(value, dio_addr);
}
static void n411_wait_for_ack(struct hecubafb_par *par, int clear)
{
int timeout;
unsigned char tmp;
timeout = 500;
do {
tmp = n411_get_ctl(par);
if ((tmp & HCB_ACK_BIT) && (!clear))
return;
else if (!(tmp & HCB_ACK_BIT) && (clear))
return;
udelay(1);
} while (timeout--);
printk(KERN_ERR "timed out waiting for ack\n");
}
static int n411_init_control(struct hecubafb_par *par)
{
unsigned char tmp;
/* for init, we want the following setup to be set:
WUP = lo
ACK = hi
DS = hi
RW = hi
CD = lo
*/
/* write WUP to lo, DS to hi, RW to hi, CD to lo */
ctl = HCB_WUP_BIT | HCB_RW_BIT | HCB_CD_BIT ;
n411_set_ctl(par, HCB_DS_BIT, 1);
/* check ACK is not lo */
tmp = n411_get_ctl(par);
if (tmp & HCB_ACK_BIT) {
printk(KERN_ERR "Fail because ACK is already low\n");
return -ENXIO;
}
return 0;
}
static int n411_init_board(struct hecubafb_par *par)
{
int retval;
retval = n411_init_control(par);
if (retval)
return retval;
par->send_command(par, APOLLO_INIT_DISPLAY);
par->send_data(par, 0x81);
/* have to wait while display resets */
udelay(1000);
/* if we were told to splash the screen, we just clear it */
if (!nosplash) {
par->send_command(par, APOLLO_ERASE_DISPLAY);
par->send_data(par, splashval);
}
return 0;
}
static struct hecuba_board n411_board = {
.owner = THIS_MODULE,
.init = n411_init_board,
.set_ctl = n411_set_ctl,
.set_data = n411_set_data,
.wait_for_ack = n411_wait_for_ack,
};
static struct platform_device *n411_device;
static int __init n411_init(void)
{
int ret;
if (!dio_addr || !cio_addr || !c2io_addr) {
printk(KERN_WARNING "no IO addresses supplied\n");
return -EINVAL;
}
/* request our platform independent driver */
request_module("hecubafb");
n411_device = platform_device_alloc("hecubafb", -1);
if (!n411_device)
return -ENOMEM;
ret = platform_device_add_data(n411_device, &n411_board,
sizeof(n411_board));
if (ret)
goto put_plat_device;
/* this _add binds hecubafb to n411. hecubafb refcounts n411 */
ret = platform_device_add(n411_device);
if (ret)
goto put_plat_device;
return 0;
put_plat_device:
platform_device_put(n411_device);
return ret;
}
static void __exit n411_exit(void)
{
platform_device_unregister(n411_device);
}
module_init(n411_init);
module_exit(n411_exit);
module_param(nosplash, uint, 0);
MODULE_PARM_DESC(nosplash, "Disable doing the splash screen");
module_param_hw(dio_addr, ulong, ioport, 0);
MODULE_PARM_DESC(dio_addr, "IO address for data, eg: 0x480");
module_param_hw(cio_addr, ulong, ioport, 0);
MODULE_PARM_DESC(cio_addr, "IO address for control, eg: 0x400");
module_param_hw(c2io_addr, ulong, ioport, 0);
MODULE_PARM_DESC(c2io_addr, "IO address for secondary control, eg: 0x408");
module_param(splashval, ulong, 0);
MODULE_PARM_DESC(splashval, "Splash pattern: 0x00 is black, 0x01 is white");
MODULE_DESCRIPTION("board driver for n411 hecuba/apollo epd kit");
MODULE_AUTHOR("Jaya Kumar");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/n411.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* framebuffer driver for VBE 2.0 compliant graphic boards
*
* switching to graphics mode happens at boot time (while
* running in real mode, see arch/i386/boot/video.S).
*
* (c) 1998 Gerd Knorr <[email protected]>
*
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/screen_info.h>
#include <linux/io.h>
#include <video/vga.h>
#define dac_reg (0x3c8)
#define dac_val (0x3c9)
/* --------------------------------------------------------------------- */
struct vesafb_par {
u32 pseudo_palette[256];
resource_size_t base;
resource_size_t size;
int wc_cookie;
struct resource *region;
};
static struct fb_var_screeninfo vesafb_defined = {
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.right_margin = 32,
.upper_margin = 16,
.lower_margin = 4,
.vsync_len = 4,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_fix_screeninfo vesafb_fix = {
.id = "VESA VGA",
.type = FB_TYPE_PACKED_PIXELS,
.accel = FB_ACCEL_NONE,
};
static int inverse __read_mostly;
static int mtrr __read_mostly; /* disable mtrr */
static int vram_remap; /* Set amount of memory to be used */
static int vram_total; /* Set total amount of memory */
static int pmi_setpal __read_mostly = 1; /* pmi for palette changes ??? */
static int ypan __read_mostly; /* 0..nothing, 1..ypan, 2..ywrap */
static void (*pmi_start)(void) __read_mostly;
static void (*pmi_pal) (void) __read_mostly;
static int depth __read_mostly;
static int vga_compat __read_mostly;
/* --------------------------------------------------------------------- */
static int vesafb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
#ifdef __i386__
int offset;
offset = (var->yoffset * info->fix.line_length + var->xoffset) / 4;
__asm__ __volatile__(
"call *(%%edi)"
: /* no return value */
: "a" (0x4f07), /* EAX */
"b" (0), /* EBX */
"c" (offset), /* ECX */
"d" (offset >> 16), /* EDX */
"D" (&pmi_start)); /* EDI */
#endif
return 0;
}
static int vesa_setpalette(int regno, unsigned red, unsigned green,
unsigned blue)
{
int shift = 16 - depth;
int err = -EINVAL;
/*
* Try VGA registers first...
*/
if (vga_compat) {
outb_p(regno, dac_reg);
outb_p(red >> shift, dac_val);
outb_p(green >> shift, dac_val);
outb_p(blue >> shift, dac_val);
err = 0;
}
#ifdef __i386__
/*
* Fallback to the PMI....
*/
if (err && pmi_setpal) {
struct { u_char blue, green, red, pad; } entry;
entry.red = red >> shift;
entry.green = green >> shift;
entry.blue = blue >> shift;
entry.pad = 0;
__asm__ __volatile__(
"call *(%%esi)"
: /* no return value */
: "a" (0x4f09), /* EAX */
"b" (0), /* EBX */
"c" (1), /* ECX */
"d" (regno), /* EDX */
"D" (&entry), /* EDI */
"S" (&pmi_pal)); /* ESI */
err = 0;
}
#endif
return err;
}
static int vesafb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
int err = 0;
/*
* Set a single color register. The values supplied are
* already rounded down to the hardware's capabilities
* (according to the entries in the `var' structure). Return
* != 0 for invalid regno.
*/
if (regno >= info->cmap.len)
return 1;
if (info->var.bits_per_pixel == 8)
err = vesa_setpalette(regno,red,green,blue);
else if (regno < 16) {
switch (info->var.bits_per_pixel) {
case 16:
if (info->var.red.offset == 10) {
/* 1:5:5:5 */
((u32*) (info->pseudo_palette))[regno] =
((red & 0xf800) >> 1) |
((green & 0xf800) >> 6) |
((blue & 0xf800) >> 11);
} else {
/* 0:5:6:5 */
((u32*) (info->pseudo_palette))[regno] =
((red & 0xf800) ) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
}
break;
case 24:
case 32:
red >>= 8;
green >>= 8;
blue >>= 8;
((u32 *)(info->pseudo_palette))[regno] =
(red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
break;
}
}
return err;
}
/*
* fb_ops.fb_destroy is called by the last put_fb_info() call at the end
* of unregister_framebuffer() or fb_release(). Do any cleanup here.
*/
static void vesafb_destroy(struct fb_info *info)
{
struct vesafb_par *par = info->par;
fb_dealloc_cmap(&info->cmap);
arch_phys_wc_del(par->wc_cookie);
if (info->screen_base)
iounmap(info->screen_base);
release_mem_region(par->base, par->size);
framebuffer_release(info);
}
static struct fb_ops vesafb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_destroy = vesafb_destroy,
.fb_setcolreg = vesafb_setcolreg,
.fb_pan_display = vesafb_pan_display,
};
static int vesafb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt) continue;
if (! strcmp(this_opt, "inverse"))
inverse=1;
else if (! strcmp(this_opt, "redraw"))
ypan=0;
else if (! strcmp(this_opt, "ypan"))
ypan=1;
else if (! strcmp(this_opt, "ywrap"))
ypan=2;
else if (! strcmp(this_opt, "vgapal"))
pmi_setpal=0;
else if (! strcmp(this_opt, "pmipal"))
pmi_setpal=1;
else if (! strncmp(this_opt, "mtrr:", 5))
mtrr = simple_strtoul(this_opt+5, NULL, 0);
else if (! strcmp(this_opt, "nomtrr"))
mtrr=0;
else if (! strncmp(this_opt, "vtotal:", 7))
vram_total = simple_strtoul(this_opt+7, NULL, 0);
else if (! strncmp(this_opt, "vremap:", 7))
vram_remap = simple_strtoul(this_opt+7, NULL, 0);
}
return 0;
}
static int vesafb_probe(struct platform_device *dev)
{
struct fb_info *info;
struct vesafb_par *par;
int i, err;
unsigned int size_vmode;
unsigned int size_remap;
unsigned int size_total;
char *option = NULL;
/* ignore error return of fb_get_options */
fb_get_options("vesafb", &option);
vesafb_setup(option);
if (screen_info.orig_video_isVGA != VIDEO_TYPE_VLFB)
return -ENODEV;
vga_compat = (screen_info.capabilities & 2) ? 0 : 1;
vesafb_fix.smem_start = screen_info.lfb_base;
vesafb_defined.bits_per_pixel = screen_info.lfb_depth;
if (15 == vesafb_defined.bits_per_pixel)
vesafb_defined.bits_per_pixel = 16;
vesafb_defined.xres = screen_info.lfb_width;
vesafb_defined.yres = screen_info.lfb_height;
vesafb_fix.line_length = screen_info.lfb_linelength;
vesafb_fix.visual = (vesafb_defined.bits_per_pixel == 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
/* size_vmode -- that is the amount of memory needed for the
* used video mode, i.e. the minimum amount of
* memory we need. */
size_vmode = vesafb_defined.yres * vesafb_fix.line_length;
/* size_total -- all video memory we have. Used for mtrr
* entries, resource allocation and bounds
* checking. */
size_total = screen_info.lfb_size * 65536;
if (vram_total)
size_total = vram_total * 1024 * 1024;
if (size_total < size_vmode)
size_total = size_vmode;
/* size_remap -- the amount of video memory we are going to
* use for vesafb. With modern cards it is no
* option to simply use size_total as that
* wastes plenty of kernel address space. */
size_remap = size_vmode * 2;
if (vram_remap)
size_remap = vram_remap * 1024 * 1024;
if (size_remap < size_vmode)
size_remap = size_vmode;
if (size_remap > size_total)
size_remap = size_total;
vesafb_fix.smem_len = size_remap;
#ifndef __i386__
screen_info.vesapm_seg = 0;
#endif
if (!request_mem_region(vesafb_fix.smem_start, size_total, "vesafb")) {
printk(KERN_WARNING
"vesafb: cannot reserve video memory at 0x%lx\n",
vesafb_fix.smem_start);
/* We cannot make this fatal. Sometimes this comes from magic
spaces our resource handlers simply don't know about */
}
info = framebuffer_alloc(sizeof(struct vesafb_par), &dev->dev);
if (!info) {
release_mem_region(vesafb_fix.smem_start, size_total);
return -ENOMEM;
}
platform_set_drvdata(dev, info);
par = info->par;
info->pseudo_palette = par->pseudo_palette;
par->base = screen_info.lfb_base;
par->size = size_total;
printk(KERN_INFO "vesafb: mode is %dx%dx%d, linelength=%d, pages=%d\n",
vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel, vesafb_fix.line_length, screen_info.pages);
if (screen_info.vesapm_seg) {
printk(KERN_INFO "vesafb: protected mode interface info at %04x:%04x\n",
screen_info.vesapm_seg,screen_info.vesapm_off);
}
if (screen_info.vesapm_seg < 0xc000)
ypan = pmi_setpal = 0; /* not available or some DOS TSR ... */
if (ypan || pmi_setpal) {
unsigned short *pmi_base;
pmi_base = (unsigned short*)phys_to_virt(((unsigned long)screen_info.vesapm_seg << 4) + screen_info.vesapm_off);
pmi_start = (void*)((char*)pmi_base + pmi_base[1]);
pmi_pal = (void*)((char*)pmi_base + pmi_base[2]);
printk(KERN_INFO "vesafb: pmi: set display start = %p, set palette = %p\n",pmi_start,pmi_pal);
if (pmi_base[3]) {
printk(KERN_INFO "vesafb: pmi: ports = ");
for (i = pmi_base[3]/2; pmi_base[i] != 0xffff; i++)
printk("%x ", pmi_base[i]);
printk("\n");
if (pmi_base[i] != 0xffff) {
/*
* memory areas not supported (yet?)
*
* Rules are: we have to set up a descriptor for the requested
* memory area and pass it in the ES register to the BIOS function.
*/
printk(KERN_INFO "vesafb: can't handle memory requests, pmi disabled\n");
ypan = pmi_setpal = 0;
}
}
}
if (vesafb_defined.bits_per_pixel == 8 && !pmi_setpal && !vga_compat) {
printk(KERN_WARNING "vesafb: hardware palette is unchangeable,\n"
" colors may be incorrect\n");
vesafb_fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
}
vesafb_defined.xres_virtual = vesafb_defined.xres;
vesafb_defined.yres_virtual = vesafb_fix.smem_len / vesafb_fix.line_length;
if (ypan && vesafb_defined.yres_virtual > vesafb_defined.yres) {
printk(KERN_INFO "vesafb: scrolling: %s using protected mode interface, yres_virtual=%d\n",
(ypan > 1) ? "ywrap" : "ypan",vesafb_defined.yres_virtual);
} else {
printk(KERN_INFO "vesafb: scrolling: redraw\n");
vesafb_defined.yres_virtual = vesafb_defined.yres;
ypan = 0;
}
/* some dummy values for timing to make fbset happy */
vesafb_defined.pixclock = 10000000 / vesafb_defined.xres * 1000 / vesafb_defined.yres;
vesafb_defined.left_margin = (vesafb_defined.xres / 8) & 0xf8;
vesafb_defined.hsync_len = (vesafb_defined.xres / 8) & 0xf8;
vesafb_defined.red.offset = screen_info.red_pos;
vesafb_defined.red.length = screen_info.red_size;
vesafb_defined.green.offset = screen_info.green_pos;
vesafb_defined.green.length = screen_info.green_size;
vesafb_defined.blue.offset = screen_info.blue_pos;
vesafb_defined.blue.length = screen_info.blue_size;
vesafb_defined.transp.offset = screen_info.rsvd_pos;
vesafb_defined.transp.length = screen_info.rsvd_size;
if (vesafb_defined.bits_per_pixel <= 8) {
depth = vesafb_defined.green.length;
vesafb_defined.red.length =
vesafb_defined.green.length =
vesafb_defined.blue.length =
vesafb_defined.bits_per_pixel;
}
printk(KERN_INFO "vesafb: %s: "
"size=%d:%d:%d:%d, shift=%d:%d:%d:%d\n",
(vesafb_defined.bits_per_pixel > 8) ?
"Truecolor" : (vga_compat || pmi_setpal) ?
"Pseudocolor" : "Static Pseudocolor",
screen_info.rsvd_size,
screen_info.red_size,
screen_info.green_size,
screen_info.blue_size,
screen_info.rsvd_pos,
screen_info.red_pos,
screen_info.green_pos,
screen_info.blue_pos);
vesafb_fix.ypanstep = ypan ? 1 : 0;
vesafb_fix.ywrapstep = (ypan>1) ? 1 : 0;
/* request failure does not faze us, as vgacon probably has this
* region already (FIXME) */
par->region = request_region(0x3c0, 32, "vesafb");
if (mtrr == 3) {
unsigned int temp_size = size_total;
/* Find the largest power-of-two */
temp_size = roundup_pow_of_two(temp_size);
/* Try and find a power of two to add */
do {
par->wc_cookie =
arch_phys_wc_add(vesafb_fix.smem_start,
temp_size);
temp_size >>= 1;
} while (temp_size >= PAGE_SIZE && par->wc_cookie < 0);
info->screen_base = ioremap_wc(vesafb_fix.smem_start, vesafb_fix.smem_len);
} else {
if (mtrr && mtrr != 3)
WARN_ONCE(1, "Only MTRR_TYPE_WRCOMB (3) make sense\n");
info->screen_base = ioremap(vesafb_fix.smem_start, vesafb_fix.smem_len);
}
if (!info->screen_base) {
printk(KERN_ERR
"vesafb: abort, cannot ioremap video memory 0x%x @ 0x%lx\n",
vesafb_fix.smem_len, vesafb_fix.smem_start);
err = -EIO;
goto err_release_region;
}
printk(KERN_INFO "vesafb: framebuffer at 0x%lx, mapped to 0x%p, "
"using %dk, total %dk\n",
vesafb_fix.smem_start, info->screen_base,
size_remap/1024, size_total/1024);
if (!ypan)
vesafb_ops.fb_pan_display = NULL;
info->fbops = &vesafb_ops;
info->var = vesafb_defined;
info->fix = vesafb_fix;
info->flags = (ypan ? FBINFO_HWACCEL_YPAN : 0);
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
err = -ENOMEM;
goto err_release_region;
}
err = devm_aperture_acquire_for_platform_device(dev, par->base, par->size);
if (err)
goto err_fb_dealloc_cmap;
if (register_framebuffer(info)<0) {
err = -EINVAL;
goto err_fb_dealloc_cmap;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
err_fb_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
err_release_region:
arch_phys_wc_del(par->wc_cookie);
if (info->screen_base)
iounmap(info->screen_base);
if (par->region)
release_region(0x3c0, 32);
framebuffer_release(info);
release_mem_region(vesafb_fix.smem_start, size_total);
return err;
}
static void vesafb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
if (((struct vesafb_par *)(info->par))->region)
release_region(0x3c0, 32);
/* vesafb_destroy takes care of info cleanup */
unregister_framebuffer(info);
}
static struct platform_driver vesafb_driver = {
.driver = {
.name = "vesa-framebuffer",
},
.probe = vesafb_probe,
.remove_new = vesafb_remove,
};
module_platform_driver(vesafb_driver);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/vesafb.c |
/*
* Xen para-virtual frame buffer device
*
* Copyright (C) 2005-2006 Anthony Liguori <[email protected]>
* Copyright (C) 2006-2008 Red Hat, Inc., Markus Armbruster <[email protected]>
*
* Based on linux/drivers/video/q40fb.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
/*
* TODO:
*
* Switch to grant tables when they become capable of dealing with the
* frame buffer.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/console.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <asm/xen/hypervisor.h>
#include <xen/xen.h>
#include <xen/events.h>
#include <xen/page.h>
#include <xen/interface/io/fbif.h>
#include <xen/interface/io/protocols.h>
#include <xen/xenbus.h>
#include <xen/platform_pci.h>
struct xenfb_info {
unsigned char *fb;
struct fb_info *fb_info;
int x1, y1, x2, y2; /* dirty rectangle,
protected by dirty_lock */
spinlock_t dirty_lock;
int nr_pages;
int irq;
struct xenfb_page *page;
unsigned long *gfns;
int update_wanted; /* XENFB_TYPE_UPDATE wanted */
int feature_resize; /* XENFB_TYPE_RESIZE ok */
struct xenfb_resize resize; /* protected by resize_lock */
int resize_dpy; /* ditto */
spinlock_t resize_lock;
struct xenbus_device *xbdev;
};
#define XENFB_DEFAULT_FB_LEN (XENFB_WIDTH * XENFB_HEIGHT * XENFB_DEPTH / 8)
enum { KPARAM_MEM, KPARAM_WIDTH, KPARAM_HEIGHT, KPARAM_CNT };
static int video[KPARAM_CNT] = { 2, XENFB_WIDTH, XENFB_HEIGHT };
module_param_array(video, int, NULL, 0);
MODULE_PARM_DESC(video,
"Video memory size in MB, width, height in pixels (default 2,800,600)");
static void xenfb_make_preferred_console(void);
static void xenfb_remove(struct xenbus_device *);
static void xenfb_init_shared_page(struct xenfb_info *, struct fb_info *);
static int xenfb_connect_backend(struct xenbus_device *, struct xenfb_info *);
static void xenfb_disconnect_backend(struct xenfb_info *);
static void xenfb_send_event(struct xenfb_info *info,
union xenfb_out_event *event)
{
u32 prod;
prod = info->page->out_prod;
/* caller ensures !xenfb_queue_full() */
mb(); /* ensure ring space available */
XENFB_OUT_RING_REF(info->page, prod) = *event;
wmb(); /* ensure ring contents visible */
info->page->out_prod = prod + 1;
notify_remote_via_irq(info->irq);
}
static void xenfb_do_update(struct xenfb_info *info,
int x, int y, int w, int h)
{
union xenfb_out_event event;
memset(&event, 0, sizeof(event));
event.type = XENFB_TYPE_UPDATE;
event.update.x = x;
event.update.y = y;
event.update.width = w;
event.update.height = h;
/* caller ensures !xenfb_queue_full() */
xenfb_send_event(info, &event);
}
static void xenfb_do_resize(struct xenfb_info *info)
{
union xenfb_out_event event;
memset(&event, 0, sizeof(event));
event.resize = info->resize;
/* caller ensures !xenfb_queue_full() */
xenfb_send_event(info, &event);
}
static int xenfb_queue_full(struct xenfb_info *info)
{
u32 cons, prod;
prod = info->page->out_prod;
cons = info->page->out_cons;
return prod - cons == XENFB_OUT_RING_LEN;
}
static void xenfb_handle_resize_dpy(struct xenfb_info *info)
{
unsigned long flags;
spin_lock_irqsave(&info->resize_lock, flags);
if (info->resize_dpy) {
if (!xenfb_queue_full(info)) {
info->resize_dpy = 0;
xenfb_do_resize(info);
}
}
spin_unlock_irqrestore(&info->resize_lock, flags);
}
static void xenfb_refresh(struct xenfb_info *info,
int x1, int y1, int w, int h)
{
unsigned long flags;
int x2 = x1 + w - 1;
int y2 = y1 + h - 1;
xenfb_handle_resize_dpy(info);
if (!info->update_wanted)
return;
spin_lock_irqsave(&info->dirty_lock, flags);
/* Combine with dirty rectangle: */
if (info->y1 < y1)
y1 = info->y1;
if (info->y2 > y2)
y2 = info->y2;
if (info->x1 < x1)
x1 = info->x1;
if (info->x2 > x2)
x2 = info->x2;
if (xenfb_queue_full(info)) {
/* Can't send right now, stash it in the dirty rectangle */
info->x1 = x1;
info->x2 = x2;
info->y1 = y1;
info->y2 = y2;
spin_unlock_irqrestore(&info->dirty_lock, flags);
return;
}
/* Clear dirty rectangle: */
info->x1 = info->y1 = INT_MAX;
info->x2 = info->y2 = 0;
spin_unlock_irqrestore(&info->dirty_lock, flags);
if (x1 <= x2 && y1 <= y2)
xenfb_do_update(info, x1, y1, x2 - x1 + 1, y2 - y1 + 1);
}
static void xenfb_deferred_io(struct fb_info *fb_info, struct list_head *pagereflist)
{
struct xenfb_info *info = fb_info->par;
struct fb_deferred_io_pageref *pageref;
unsigned long beg, end;
int y1, y2, miny, maxy;
miny = INT_MAX;
maxy = 0;
list_for_each_entry(pageref, pagereflist, list) {
beg = pageref->offset;
end = beg + PAGE_SIZE - 1;
y1 = beg / fb_info->fix.line_length;
y2 = end / fb_info->fix.line_length;
if (y2 >= fb_info->var.yres)
y2 = fb_info->var.yres - 1;
if (miny > y1)
miny = y1;
if (maxy < y2)
maxy = y2;
}
xenfb_refresh(info, 0, miny, fb_info->var.xres, maxy - miny + 1);
}
static struct fb_deferred_io xenfb_defio = {
.delay = HZ / 20,
.deferred_io = xenfb_deferred_io,
};
static int xenfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
u32 v;
if (regno > info->cmap.len)
return 1;
#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16)
red = CNVT_TOHW(red, info->var.red.length);
green = CNVT_TOHW(green, info->var.green.length);
blue = CNVT_TOHW(blue, info->var.blue.length);
#undef CNVT_TOHW
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
switch (info->var.bits_per_pixel) {
case 16:
case 24:
case 32:
((u32 *)info->pseudo_palette)[regno] = v;
break;
}
return 0;
}
static int
xenfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct xenfb_info *xenfb_info;
int required_mem_len;
xenfb_info = info->par;
if (!xenfb_info->feature_resize) {
if (var->xres == video[KPARAM_WIDTH] &&
var->yres == video[KPARAM_HEIGHT] &&
var->bits_per_pixel == xenfb_info->page->depth) {
return 0;
}
return -EINVAL;
}
/* Can't resize past initial width and height */
if (var->xres > video[KPARAM_WIDTH] || var->yres > video[KPARAM_HEIGHT])
return -EINVAL;
required_mem_len = var->xres * var->yres * xenfb_info->page->depth / 8;
if (var->bits_per_pixel == xenfb_info->page->depth &&
var->xres <= info->fix.line_length / (XENFB_DEPTH / 8) &&
required_mem_len <= info->fix.smem_len) {
var->xres_virtual = var->xres;
var->yres_virtual = var->yres;
return 0;
}
return -EINVAL;
}
static int xenfb_set_par(struct fb_info *info)
{
struct xenfb_info *xenfb_info;
unsigned long flags;
xenfb_info = info->par;
spin_lock_irqsave(&xenfb_info->resize_lock, flags);
xenfb_info->resize.type = XENFB_TYPE_RESIZE;
xenfb_info->resize.width = info->var.xres;
xenfb_info->resize.height = info->var.yres;
xenfb_info->resize.stride = info->fix.line_length;
xenfb_info->resize.depth = info->var.bits_per_pixel;
xenfb_info->resize.offset = 0;
xenfb_info->resize_dpy = 1;
spin_unlock_irqrestore(&xenfb_info->resize_lock, flags);
return 0;
}
static void xenfb_defio_damage_range(struct fb_info *info, off_t off, size_t len)
{
struct xenfb_info *xenfb_info = info->par;
xenfb_refresh(xenfb_info, 0, 0, xenfb_info->page->width, xenfb_info->page->height);
}
static void xenfb_defio_damage_area(struct fb_info *info, u32 x, u32 y,
u32 width, u32 height)
{
struct xenfb_info *xenfb_info = info->par;
xenfb_refresh(xenfb_info, x, y, width, height);
}
FB_GEN_DEFAULT_DEFERRED_SYSMEM_OPS(xenfb,
xenfb_defio_damage_range,
xenfb_defio_damage_area)
static const struct fb_ops xenfb_fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_DEFERRED_OPS(xenfb),
.fb_setcolreg = xenfb_setcolreg,
.fb_check_var = xenfb_check_var,
.fb_set_par = xenfb_set_par,
};
static irqreturn_t xenfb_event_handler(int rq, void *dev_id)
{
/*
* No in events recognized, simply ignore them all.
* If you need to recognize some, see xen-kbdfront's
* input_handler() for how to do that.
*/
struct xenfb_info *info = dev_id;
struct xenfb_page *page = info->page;
if (page->in_cons != page->in_prod) {
info->page->in_cons = info->page->in_prod;
notify_remote_via_irq(info->irq);
}
/* Flush dirty rectangle: */
xenfb_refresh(info, INT_MAX, INT_MAX, -INT_MAX, -INT_MAX);
return IRQ_HANDLED;
}
static int xenfb_probe(struct xenbus_device *dev,
const struct xenbus_device_id *id)
{
struct xenfb_info *info;
struct fb_info *fb_info;
int fb_size;
int val;
int ret = 0;
info = kzalloc(sizeof(*info), GFP_KERNEL);
if (info == NULL) {
xenbus_dev_fatal(dev, -ENOMEM, "allocating info structure");
return -ENOMEM;
}
/* Limit kernel param videoram amount to what is in xenstore */
if (xenbus_scanf(XBT_NIL, dev->otherend, "videoram", "%d", &val) == 1) {
if (val < video[KPARAM_MEM])
video[KPARAM_MEM] = val;
}
video[KPARAM_WIDTH] = xenbus_read_unsigned(dev->otherend, "width",
video[KPARAM_WIDTH]);
video[KPARAM_HEIGHT] = xenbus_read_unsigned(dev->otherend, "height",
video[KPARAM_HEIGHT]);
/* If requested res does not fit in available memory, use default */
fb_size = video[KPARAM_MEM] * 1024 * 1024;
if (video[KPARAM_WIDTH] * video[KPARAM_HEIGHT] * XENFB_DEPTH / 8
> fb_size) {
pr_warn("display parameters %d,%d,%d invalid, use defaults\n",
video[KPARAM_MEM], video[KPARAM_WIDTH],
video[KPARAM_HEIGHT]);
video[KPARAM_WIDTH] = XENFB_WIDTH;
video[KPARAM_HEIGHT] = XENFB_HEIGHT;
fb_size = XENFB_DEFAULT_FB_LEN;
}
dev_set_drvdata(&dev->dev, info);
info->xbdev = dev;
info->irq = -1;
info->x1 = info->y1 = INT_MAX;
spin_lock_init(&info->dirty_lock);
spin_lock_init(&info->resize_lock);
info->fb = vzalloc(fb_size);
if (info->fb == NULL)
goto error_nomem;
info->nr_pages = (fb_size + PAGE_SIZE - 1) >> PAGE_SHIFT;
info->gfns = vmalloc(array_size(sizeof(unsigned long), info->nr_pages));
if (!info->gfns)
goto error_nomem;
/* set up shared page */
info->page = (void *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
if (!info->page)
goto error_nomem;
/* abusing framebuffer_alloc() to allocate pseudo_palette */
fb_info = framebuffer_alloc(sizeof(u32) * 256, NULL);
if (fb_info == NULL)
goto error_nomem;
/* complete the abuse: */
fb_info->pseudo_palette = fb_info->par;
fb_info->par = info;
fb_info->screen_buffer = info->fb;
fb_info->fbops = &xenfb_fb_ops;
fb_info->var.xres_virtual = fb_info->var.xres = video[KPARAM_WIDTH];
fb_info->var.yres_virtual = fb_info->var.yres = video[KPARAM_HEIGHT];
fb_info->var.bits_per_pixel = XENFB_DEPTH;
fb_info->var.red = (struct fb_bitfield){16, 8, 0};
fb_info->var.green = (struct fb_bitfield){8, 8, 0};
fb_info->var.blue = (struct fb_bitfield){0, 8, 0};
fb_info->var.activate = FB_ACTIVATE_NOW;
fb_info->var.height = -1;
fb_info->var.width = -1;
fb_info->var.vmode = FB_VMODE_NONINTERLACED;
fb_info->fix.visual = FB_VISUAL_TRUECOLOR;
fb_info->fix.line_length = fb_info->var.xres * XENFB_DEPTH / 8;
fb_info->fix.smem_start = 0;
fb_info->fix.smem_len = fb_size;
strcpy(fb_info->fix.id, "xen");
fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
fb_info->fix.accel = FB_ACCEL_NONE;
fb_info->flags = FBINFO_VIRTFB;
ret = fb_alloc_cmap(&fb_info->cmap, 256, 0);
if (ret < 0) {
framebuffer_release(fb_info);
xenbus_dev_fatal(dev, ret, "fb_alloc_cmap");
goto error;
}
fb_info->fbdefio = &xenfb_defio;
fb_deferred_io_init(fb_info);
xenfb_init_shared_page(info, fb_info);
ret = xenfb_connect_backend(dev, info);
if (ret < 0) {
xenbus_dev_fatal(dev, ret, "xenfb_connect_backend");
goto error_fb;
}
ret = register_framebuffer(fb_info);
if (ret) {
xenbus_dev_fatal(dev, ret, "register_framebuffer");
goto error_fb;
}
info->fb_info = fb_info;
xenfb_make_preferred_console();
return 0;
error_fb:
fb_deferred_io_cleanup(fb_info);
fb_dealloc_cmap(&fb_info->cmap);
framebuffer_release(fb_info);
error_nomem:
if (!ret) {
ret = -ENOMEM;
xenbus_dev_fatal(dev, ret, "allocating device memory");
}
error:
xenfb_remove(dev);
return ret;
}
static void xenfb_make_preferred_console(void)
{
struct console *c;
if (console_set_on_cmdline)
return;
console_list_lock();
for_each_console(c) {
if (!strcmp(c->name, "tty") && c->index == 0)
break;
}
if (c)
console_force_preferred_locked(c);
console_list_unlock();
}
static int xenfb_resume(struct xenbus_device *dev)
{
struct xenfb_info *info = dev_get_drvdata(&dev->dev);
xenfb_disconnect_backend(info);
xenfb_init_shared_page(info, info->fb_info);
return xenfb_connect_backend(dev, info);
}
static void xenfb_remove(struct xenbus_device *dev)
{
struct xenfb_info *info = dev_get_drvdata(&dev->dev);
xenfb_disconnect_backend(info);
if (info->fb_info) {
fb_deferred_io_cleanup(info->fb_info);
unregister_framebuffer(info->fb_info);
fb_dealloc_cmap(&info->fb_info->cmap);
framebuffer_release(info->fb_info);
}
free_page((unsigned long)info->page);
vfree(info->gfns);
vfree(info->fb);
kfree(info);
}
static unsigned long vmalloc_to_gfn(void *address)
{
return xen_page_to_gfn(vmalloc_to_page(address));
}
static void xenfb_init_shared_page(struct xenfb_info *info,
struct fb_info *fb_info)
{
int i;
int epd = PAGE_SIZE / sizeof(info->gfns[0]);
for (i = 0; i < info->nr_pages; i++)
info->gfns[i] = vmalloc_to_gfn(info->fb + i * PAGE_SIZE);
for (i = 0; i * epd < info->nr_pages; i++)
info->page->pd[i] = vmalloc_to_gfn(&info->gfns[i * epd]);
info->page->width = fb_info->var.xres;
info->page->height = fb_info->var.yres;
info->page->depth = fb_info->var.bits_per_pixel;
info->page->line_length = fb_info->fix.line_length;
info->page->mem_length = fb_info->fix.smem_len;
info->page->in_cons = info->page->in_prod = 0;
info->page->out_cons = info->page->out_prod = 0;
}
static int xenfb_connect_backend(struct xenbus_device *dev,
struct xenfb_info *info)
{
int ret, evtchn, irq;
struct xenbus_transaction xbt;
ret = xenbus_alloc_evtchn(dev, &evtchn);
if (ret)
return ret;
irq = bind_evtchn_to_irqhandler(evtchn, xenfb_event_handler,
0, dev->devicetype, info);
if (irq < 0) {
xenbus_free_evtchn(dev, evtchn);
xenbus_dev_fatal(dev, ret, "bind_evtchn_to_irqhandler");
return irq;
}
again:
ret = xenbus_transaction_start(&xbt);
if (ret) {
xenbus_dev_fatal(dev, ret, "starting transaction");
goto unbind_irq;
}
ret = xenbus_printf(xbt, dev->nodename, "page-ref", "%lu",
virt_to_gfn(info->page));
if (ret)
goto error_xenbus;
ret = xenbus_printf(xbt, dev->nodename, "event-channel", "%u",
evtchn);
if (ret)
goto error_xenbus;
ret = xenbus_printf(xbt, dev->nodename, "protocol", "%s",
XEN_IO_PROTO_ABI_NATIVE);
if (ret)
goto error_xenbus;
ret = xenbus_printf(xbt, dev->nodename, "feature-update", "1");
if (ret)
goto error_xenbus;
ret = xenbus_transaction_end(xbt, 0);
if (ret) {
if (ret == -EAGAIN)
goto again;
xenbus_dev_fatal(dev, ret, "completing transaction");
goto unbind_irq;
}
xenbus_switch_state(dev, XenbusStateInitialised);
info->irq = irq;
return 0;
error_xenbus:
xenbus_transaction_end(xbt, 1);
xenbus_dev_fatal(dev, ret, "writing xenstore");
unbind_irq:
unbind_from_irqhandler(irq, info);
return ret;
}
static void xenfb_disconnect_backend(struct xenfb_info *info)
{
/* Prevent xenfb refresh */
info->update_wanted = 0;
if (info->irq >= 0)
unbind_from_irqhandler(info->irq, info);
info->irq = -1;
}
static void xenfb_backend_changed(struct xenbus_device *dev,
enum xenbus_state backend_state)
{
struct xenfb_info *info = dev_get_drvdata(&dev->dev);
switch (backend_state) {
case XenbusStateInitialising:
case XenbusStateInitialised:
case XenbusStateReconfiguring:
case XenbusStateReconfigured:
case XenbusStateUnknown:
break;
case XenbusStateInitWait:
xenbus_switch_state(dev, XenbusStateConnected);
break;
case XenbusStateConnected:
/*
* Work around xenbus race condition: If backend goes
* through InitWait to Connected fast enough, we can
* get Connected twice here.
*/
if (dev->state != XenbusStateConnected)
/* no InitWait seen yet, fudge it */
xenbus_switch_state(dev, XenbusStateConnected);
if (xenbus_read_unsigned(info->xbdev->otherend,
"request-update", 0))
info->update_wanted = 1;
info->feature_resize = xenbus_read_unsigned(dev->otherend,
"feature-resize", 0);
break;
case XenbusStateClosed:
if (dev->state == XenbusStateClosed)
break;
fallthrough; /* Missed the backend's CLOSING state */
case XenbusStateClosing:
xenbus_frontend_closed(dev);
break;
}
}
static const struct xenbus_device_id xenfb_ids[] = {
{ "vfb" },
{ "" }
};
static struct xenbus_driver xenfb_driver = {
.ids = xenfb_ids,
.probe = xenfb_probe,
.remove = xenfb_remove,
.resume = xenfb_resume,
.otherend_changed = xenfb_backend_changed,
.not_essential = true,
};
static int __init xenfb_init(void)
{
if (!xen_domain())
return -ENODEV;
/* Nothing to do if running in dom0. */
if (xen_initial_domain())
return -ENODEV;
if (!xen_has_pv_devices())
return -ENODEV;
return xenbus_register_frontend(&xenfb_driver);
}
static void __exit xenfb_cleanup(void)
{
xenbus_unregister_driver(&xenfb_driver);
}
module_init(xenfb_init);
module_exit(xenfb_cleanup);
MODULE_DESCRIPTION("Xen virtual framebuffer device frontend");
MODULE_LICENSE("GPL");
MODULE_ALIAS("xen:vfb");
| linux-master | drivers/video/fbdev/xen-fbfront.c |
/*
* linux/drivers/video/amba-clcd.c
*
* Copyright (C) 2001 ARM Limited, by David A Rusling
* Updated to 2.5, Deep Blue Solutions Ltd.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* ARM PrimeCell PL110 Color LCD Controller
*/
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/backlight.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/list.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_graph.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <video/display_timing.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
#define to_clcd(info) container_of(info, struct clcd_fb, fb)
/* This is limited to 16 characters when displayed by X startup */
static const char *clcd_name = "CLCD FB";
static inline void clcdfb_set_start(struct clcd_fb *fb)
{
unsigned long ustart = fb->fb.fix.smem_start;
unsigned long lstart;
ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
writel(ustart, fb->regs + CLCD_UBAS);
writel(lstart, fb->regs + CLCD_LBAS);
}
static void clcdfb_disable(struct clcd_fb *fb)
{
u32 val;
if (fb->board->disable)
fb->board->disable(fb);
if (fb->panel->backlight) {
fb->panel->backlight->props.power = FB_BLANK_POWERDOWN;
backlight_update_status(fb->panel->backlight);
}
val = readl(fb->regs + fb->off_cntl);
if (val & CNTL_LCDPWR) {
val &= ~CNTL_LCDPWR;
writel(val, fb->regs + fb->off_cntl);
msleep(20);
}
if (val & CNTL_LCDEN) {
val &= ~CNTL_LCDEN;
writel(val, fb->regs + fb->off_cntl);
}
/*
* Disable CLCD clock source.
*/
if (fb->clk_enabled) {
fb->clk_enabled = false;
clk_disable(fb->clk);
}
}
static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
{
/*
* Enable the CLCD clock source.
*/
if (!fb->clk_enabled) {
fb->clk_enabled = true;
clk_enable(fb->clk);
}
/*
* Bring up by first enabling..
*/
cntl |= CNTL_LCDEN;
writel(cntl, fb->regs + fb->off_cntl);
msleep(20);
/*
* and now apply power.
*/
cntl |= CNTL_LCDPWR;
writel(cntl, fb->regs + fb->off_cntl);
/*
* Turn on backlight
*/
if (fb->panel->backlight) {
fb->panel->backlight->props.power = FB_BLANK_UNBLANK;
backlight_update_status(fb->panel->backlight);
}
/*
* finally, enable the interface.
*/
if (fb->board->enable)
fb->board->enable(fb);
}
static int
clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
{
u32 caps;
int ret = 0;
if (fb->panel->caps && fb->board->caps)
caps = fb->panel->caps & fb->board->caps;
else {
/* Old way of specifying what can be used */
caps = fb->panel->cntl & CNTL_BGR ?
CLCD_CAP_BGR : CLCD_CAP_RGB;
/* But mask out 444 modes as they weren't supported */
caps &= ~CLCD_CAP_444;
}
/* Only TFT panels can do RGB888/BGR888 */
if (!(fb->panel->cntl & CNTL_LCDTFT))
caps &= ~CLCD_CAP_888;
memset(&var->transp, 0, sizeof(var->transp));
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
switch (var->bits_per_pixel) {
case 1:
case 2:
case 4:
case 8:
/* If we can't do 5551, reject */
caps &= CLCD_CAP_5551;
if (!caps) {
ret = -EINVAL;
break;
}
var->red.length = var->bits_per_pixel;
var->red.offset = 0;
var->green.length = var->bits_per_pixel;
var->green.offset = 0;
var->blue.length = var->bits_per_pixel;
var->blue.offset = 0;
break;
case 16:
/* If we can't do 444, 5551 or 565, reject */
if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) {
ret = -EINVAL;
break;
}
/*
* Green length can be 4, 5 or 6 depending whether
* we're operating in 444, 5551 or 565 mode.
*/
if (var->green.length == 4 && caps & CLCD_CAP_444)
caps &= CLCD_CAP_444;
if (var->green.length == 5 && caps & CLCD_CAP_5551)
caps &= CLCD_CAP_5551;
else if (var->green.length == 6 && caps & CLCD_CAP_565)
caps &= CLCD_CAP_565;
else {
/*
* PL110 officially only supports RGB555,
* but may be wired up to allow RGB565.
*/
if (caps & CLCD_CAP_565) {
var->green.length = 6;
caps &= CLCD_CAP_565;
} else if (caps & CLCD_CAP_5551) {
var->green.length = 5;
caps &= CLCD_CAP_5551;
} else {
var->green.length = 4;
caps &= CLCD_CAP_444;
}
}
if (var->green.length >= 5) {
var->red.length = 5;
var->blue.length = 5;
} else {
var->red.length = 4;
var->blue.length = 4;
}
break;
case 32:
/* If we can't do 888, reject */
caps &= CLCD_CAP_888;
if (!caps) {
ret = -EINVAL;
break;
}
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
default:
ret = -EINVAL;
break;
}
/*
* >= 16bpp displays have separate colour component bitfields
* encoded in the pixel data. Calculate their position from
* the bitfield length defined above.
*/
if (ret == 0 && var->bits_per_pixel >= 16) {
bool bgr, rgb;
bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0;
rgb = caps & CLCD_CAP_RGB && var->red.offset == 0;
if (!bgr && !rgb)
/*
* The requested format was not possible, try just
* our capabilities. One of BGR or RGB must be
* supported.
*/
bgr = caps & CLCD_CAP_BGR;
if (bgr) {
var->blue.offset = 0;
var->green.offset = var->blue.offset + var->blue.length;
var->red.offset = var->green.offset + var->green.length;
} else {
var->red.offset = 0;
var->green.offset = var->red.offset + var->red.length;
var->blue.offset = var->green.offset + var->green.length;
}
}
return ret;
}
static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct clcd_fb *fb = to_clcd(info);
int ret = -EINVAL;
if (fb->board->check)
ret = fb->board->check(fb, var);
if (ret == 0 &&
var->xres_virtual * var->bits_per_pixel / 8 *
var->yres_virtual > fb->fb.fix.smem_len)
ret = -EINVAL;
if (ret == 0)
ret = clcdfb_set_bitfields(fb, var);
return ret;
}
static int clcdfb_set_par(struct fb_info *info)
{
struct clcd_fb *fb = to_clcd(info);
struct clcd_regs regs;
fb->fb.fix.line_length = fb->fb.var.xres_virtual *
fb->fb.var.bits_per_pixel / 8;
if (fb->fb.var.bits_per_pixel <= 8)
fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
else
fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
fb->board->decode(fb, ®s);
clcdfb_disable(fb);
writel(regs.tim0, fb->regs + CLCD_TIM0);
writel(regs.tim1, fb->regs + CLCD_TIM1);
writel(regs.tim2, fb->regs + CLCD_TIM2);
writel(regs.tim3, fb->regs + CLCD_TIM3);
clcdfb_set_start(fb);
clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
fb->clcd_cntl = regs.cntl;
clcdfb_enable(fb, regs.cntl);
#ifdef DEBUG
printk(KERN_INFO
"CLCD: Registers set to\n"
" %08x %08x %08x %08x\n"
" %08x %08x %08x %08x\n",
readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl));
#endif
return 0;
}
static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
{
unsigned int mask = (1 << bf->length) - 1;
return (val >> (16 - bf->length) & mask) << bf->offset;
}
/*
* Set a single color register. The values supplied have a 16 bit
* magnitude. Return != 0 for invalid regno.
*/
static int
clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
unsigned int blue, unsigned int transp, struct fb_info *info)
{
struct clcd_fb *fb = to_clcd(info);
if (regno < 16)
fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
convert_bitfield(blue, &fb->fb.var.blue) |
convert_bitfield(green, &fb->fb.var.green) |
convert_bitfield(red, &fb->fb.var.red);
if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
u32 val, mask, newval;
newval = (red >> 11) & 0x001f;
newval |= (green >> 6) & 0x03e0;
newval |= (blue >> 1) & 0x7c00;
/*
* 3.2.11: if we're configured for big endian
* byte order, the palette entries are swapped.
*/
if (fb->clcd_cntl & CNTL_BEBO)
regno ^= 1;
if (regno & 1) {
newval <<= 16;
mask = 0x0000ffff;
} else {
mask = 0xffff0000;
}
val = readl(fb->regs + hw_reg) & mask;
writel(val | newval, fb->regs + hw_reg);
}
return regno > 255;
}
/*
* Blank the screen if blank_mode != 0, else unblank. If blank == NULL
* then the caller blanks by setting the CLUT (Color Look Up Table) to all
* black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
* to e.g. a video mode which doesn't support it. Implements VESA suspend
* and powerdown modes on hardware that supports disabling hsync/vsync:
* blank_mode == 2: suspend vsync
* blank_mode == 3: suspend hsync
* blank_mode == 4: powerdown
*/
static int clcdfb_blank(int blank_mode, struct fb_info *info)
{
struct clcd_fb *fb = to_clcd(info);
if (blank_mode != 0) {
clcdfb_disable(fb);
} else {
clcdfb_enable(fb, fb->clcd_cntl);
}
return 0;
}
static int clcdfb_mmap(struct fb_info *info,
struct vm_area_struct *vma)
{
struct clcd_fb *fb = to_clcd(info);
unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
int ret = -EINVAL;
len = info->fix.smem_len;
if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
fb->board->mmap)
ret = fb->board->mmap(fb, vma);
return ret;
}
static const struct fb_ops clcdfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = clcdfb_check_var,
.fb_set_par = clcdfb_set_par,
.fb_setcolreg = clcdfb_setcolreg,
.fb_blank = clcdfb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_mmap = clcdfb_mmap,
};
static int clcdfb_register(struct clcd_fb *fb)
{
int ret;
/*
* ARM PL111 always has IENB at 0x1c; it's only PL110
* which is reversed on some platforms.
*/
if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) {
fb->off_ienb = CLCD_PL111_IENB;
fb->off_cntl = CLCD_PL111_CNTL;
} else {
fb->off_ienb = CLCD_PL110_IENB;
fb->off_cntl = CLCD_PL110_CNTL;
}
fb->clk = clk_get(&fb->dev->dev, NULL);
if (IS_ERR(fb->clk)) {
ret = PTR_ERR(fb->clk);
goto out;
}
ret = clk_prepare(fb->clk);
if (ret)
goto free_clk;
fb->fb.device = &fb->dev->dev;
fb->fb.fix.mmio_start = fb->dev->res.start;
fb->fb.fix.mmio_len = resource_size(&fb->dev->res);
fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
if (!fb->regs) {
printk(KERN_ERR "CLCD: unable to remap registers\n");
ret = -ENOMEM;
goto clk_unprep;
}
fb->fb.fbops = &clcdfb_ops;
fb->fb.pseudo_palette = fb->cmap;
strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
fb->fb.fix.type_aux = 0;
fb->fb.fix.xpanstep = 0;
fb->fb.fix.ypanstep = 0;
fb->fb.fix.ywrapstep = 0;
fb->fb.fix.accel = FB_ACCEL_NONE;
fb->fb.var.xres = fb->panel->mode.xres;
fb->fb.var.yres = fb->panel->mode.yres;
fb->fb.var.xres_virtual = fb->panel->mode.xres;
fb->fb.var.yres_virtual = fb->panel->mode.yres;
fb->fb.var.bits_per_pixel = fb->panel->bpp;
fb->fb.var.grayscale = fb->panel->grayscale;
fb->fb.var.pixclock = fb->panel->mode.pixclock;
fb->fb.var.left_margin = fb->panel->mode.left_margin;
fb->fb.var.right_margin = fb->panel->mode.right_margin;
fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
fb->fb.var.sync = fb->panel->mode.sync;
fb->fb.var.vmode = fb->panel->mode.vmode;
fb->fb.var.activate = FB_ACTIVATE_NOW;
fb->fb.var.nonstd = 0;
fb->fb.var.height = fb->panel->height;
fb->fb.var.width = fb->panel->width;
fb->fb.var.accel_flags = 0;
fb->fb.monspecs.hfmin = 0;
fb->fb.monspecs.hfmax = 100000;
fb->fb.monspecs.vfmin = 0;
fb->fb.monspecs.vfmax = 400;
fb->fb.monspecs.dclkmin = 1000000;
fb->fb.monspecs.dclkmax = 100000000;
/*
* Make sure that the bitfields are set appropriately.
*/
clcdfb_set_bitfields(fb, &fb->fb.var);
/*
* Allocate colourmap.
*/
ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0);
if (ret)
goto unmap;
/*
* Ensure interrupts are disabled.
*/
writel(0, fb->regs + fb->off_ienb);
fb_set_var(&fb->fb, &fb->fb.var);
dev_info(&fb->dev->dev, "%s hardware, %s display\n",
fb->board->name, fb->panel->mode.name);
ret = register_framebuffer(&fb->fb);
if (ret == 0)
goto out;
printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
fb_dealloc_cmap(&fb->fb.cmap);
unmap:
iounmap(fb->regs);
clk_unprep:
clk_unprepare(fb->clk);
free_clk:
clk_put(fb->clk);
out:
return ret;
}
#ifdef CONFIG_OF
static int clcdfb_of_get_dpi_panel_mode(struct device_node *node,
struct clcd_panel *clcd_panel)
{
int err;
struct display_timing timing;
struct videomode video;
err = of_get_display_timing(node, "panel-timing", &timing);
if (err) {
pr_err("%pOF: problems parsing panel-timing (%d)\n", node, err);
return err;
}
videomode_from_timing(&timing, &video);
err = fb_videomode_from_videomode(&video, &clcd_panel->mode);
if (err)
return err;
/* Set up some inversion flags */
if (timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
clcd_panel->tim2 |= TIM2_IPC;
else if (!(timing.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE))
/*
* To preserve backwards compatibility, the IPC (inverted
* pixel clock) flag needs to be set on any display that
* doesn't explicitly specify that the pixel clock is
* active on the negative or positive edge.
*/
clcd_panel->tim2 |= TIM2_IPC;
if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW)
clcd_panel->tim2 |= TIM2_IHS;
if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW)
clcd_panel->tim2 |= TIM2_IVS;
if (timing.flags & DISPLAY_FLAGS_DE_LOW)
clcd_panel->tim2 |= TIM2_IOE;
return 0;
}
static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode)
{
return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres,
mode->refresh);
}
static int clcdfb_of_get_backlight(struct device *dev,
struct clcd_panel *clcd_panel)
{
struct backlight_device *backlight;
/* Look up the optional backlight device */
backlight = devm_of_find_backlight(dev);
if (IS_ERR(backlight))
return PTR_ERR(backlight);
clcd_panel->backlight = backlight;
return 0;
}
static int clcdfb_of_get_mode(struct device *dev, struct device_node *panel,
struct clcd_panel *clcd_panel)
{
int err;
struct fb_videomode *mode;
char *name;
int len;
/* Only directly connected DPI panels supported for now */
if (of_device_is_compatible(panel, "panel-dpi"))
err = clcdfb_of_get_dpi_panel_mode(panel, clcd_panel);
else
err = -ENOENT;
if (err)
return err;
mode = &clcd_panel->mode;
len = clcdfb_snprintf_mode(NULL, 0, mode);
name = devm_kzalloc(dev, len + 1, GFP_KERNEL);
if (!name)
return -ENOMEM;
clcdfb_snprintf_mode(name, len + 1, mode);
mode->name = name;
return 0;
}
static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0)
{
static struct {
unsigned int part;
u32 r0, g0, b0;
u32 caps;
} panels[] = {
{ 0x110, 1, 7, 13, CLCD_CAP_5551 },
{ 0x110, 0, 8, 16, CLCD_CAP_888 },
{ 0x110, 16, 8, 0, CLCD_CAP_888 },
{ 0x111, 4, 14, 20, CLCD_CAP_444 },
{ 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 },
{ 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 |
CLCD_CAP_565 },
{ 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 |
CLCD_CAP_565 | CLCD_CAP_888 },
};
int i;
/* Bypass pixel clock divider */
fb->panel->tim2 |= TIM2_BCD;
/* TFT display, vert. comp. interrupt at the start of the back porch */
fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1);
fb->panel->caps = 0;
/* Match the setup with known variants */
for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) {
if (amba_part(fb->dev) != panels[i].part)
continue;
if (g0 != panels[i].g0)
continue;
if (r0 == panels[i].r0 && b0 == panels[i].b0)
fb->panel->caps = panels[i].caps;
}
/*
* If we actually physically connected the R lines to B and
* vice versa
*/
if (r0 != 0 && b0 == 0)
fb->panel->bgr_connection = true;
return fb->panel->caps ? 0 : -EINVAL;
}
static int clcdfb_of_init_display(struct clcd_fb *fb)
{
struct device_node *endpoint, *panel;
int err;
unsigned int bpp;
u32 max_bandwidth;
u32 tft_r0b0g0[3];
fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL);
if (!fb->panel)
return -ENOMEM;
/*
* Fetch the panel endpoint.
*/
endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL);
if (!endpoint)
return -ENODEV;
panel = of_graph_get_remote_port_parent(endpoint);
if (!panel) {
err = -ENODEV;
goto out_endpoint_put;
}
err = clcdfb_of_get_backlight(&fb->dev->dev, fb->panel);
if (err)
goto out_panel_put;
err = clcdfb_of_get_mode(&fb->dev->dev, panel, fb->panel);
if (err)
goto out_panel_put;
err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth",
&max_bandwidth);
if (!err) {
/*
* max_bandwidth is in bytes per second and pixclock in
* pico-seconds, so the maximum allowed bits per pixel is
* 8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000)
* Rearrange this calculation to avoid overflow and then ensure
* result is a valid format.
*/
bpp = max_bandwidth / (1000 / 8)
/ PICOS2KHZ(fb->panel->mode.pixclock);
bpp = rounddown_pow_of_two(bpp);
if (bpp > 32)
bpp = 32;
} else
bpp = 32;
fb->panel->bpp = bpp;
#ifdef CONFIG_CPU_BIG_ENDIAN
fb->panel->cntl |= CNTL_BEBO;
#endif
fb->panel->width = -1;
fb->panel->height = -1;
if (of_property_read_u32_array(endpoint,
"arm,pl11x,tft-r0g0b0-pads",
tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) != 0) {
err = -ENOENT;
goto out_panel_put;
}
of_node_put(panel);
of_node_put(endpoint);
return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0],
tft_r0b0g0[1], tft_r0b0g0[2]);
out_panel_put:
of_node_put(panel);
out_endpoint_put:
of_node_put(endpoint);
return err;
}
static int clcdfb_of_vram_setup(struct clcd_fb *fb)
{
int err;
struct device_node *memory;
u64 size;
err = clcdfb_of_init_display(fb);
if (err)
return err;
memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0);
if (!memory)
return -ENODEV;
fb->fb.screen_base = of_iomap(memory, 0);
if (!fb->fb.screen_base) {
of_node_put(memory);
return -ENOMEM;
}
fb->fb.fix.smem_start = of_translate_address(memory,
of_get_address(memory, 0, &size, NULL));
fb->fb.fix.smem_len = size;
of_node_put(memory);
return 0;
}
static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
unsigned long off, user_size, kernel_size;
off = vma->vm_pgoff << PAGE_SHIFT;
user_size = vma->vm_end - vma->vm_start;
kernel_size = fb->fb.fix.smem_len;
if (off >= kernel_size || user_size > (kernel_size - off))
return -ENXIO;
return remap_pfn_range(vma, vma->vm_start,
__phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff,
user_size,
pgprot_writecombine(vma->vm_page_prot));
}
static void clcdfb_of_vram_remove(struct clcd_fb *fb)
{
iounmap(fb->fb.screen_base);
}
static int clcdfb_of_dma_setup(struct clcd_fb *fb)
{
unsigned long framesize;
dma_addr_t dma;
int err;
err = clcdfb_of_init_display(fb);
if (err)
return err;
framesize = PAGE_ALIGN(fb->panel->mode.xres * fb->panel->mode.yres *
fb->panel->bpp / 8);
fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize,
&dma, GFP_KERNEL);
if (!fb->fb.screen_base)
return -ENOMEM;
fb->fb.fix.smem_start = dma;
fb->fb.fix.smem_len = framesize;
return 0;
}
static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
fb->fb.fix.smem_start, fb->fb.fix.smem_len);
}
static void clcdfb_of_dma_remove(struct clcd_fb *fb)
{
dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len,
fb->fb.screen_base, fb->fb.fix.smem_start);
}
static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
{
struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board),
GFP_KERNEL);
struct device_node *node = dev->dev.of_node;
if (!board)
return NULL;
board->name = of_node_full_name(node);
board->caps = CLCD_CAP_ALL;
board->check = clcdfb_check;
board->decode = clcdfb_decode;
if (of_property_present(node, "memory-region")) {
board->setup = clcdfb_of_vram_setup;
board->mmap = clcdfb_of_vram_mmap;
board->remove = clcdfb_of_vram_remove;
} else {
board->setup = clcdfb_of_dma_setup;
board->mmap = clcdfb_of_dma_mmap;
board->remove = clcdfb_of_dma_remove;
}
return board;
}
#else
static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev)
{
return NULL;
}
#endif
static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
{
struct clcd_board *board = dev_get_platdata(&dev->dev);
struct clcd_fb *fb;
int ret;
if (!board)
board = clcdfb_of_get_board(dev);
if (!board)
return -EINVAL;
ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32));
if (ret)
goto out;
ret = amba_request_regions(dev, NULL);
if (ret) {
printk(KERN_ERR "CLCD: unable to reserve regs region\n");
goto out;
}
fb = kzalloc(sizeof(*fb), GFP_KERNEL);
if (!fb) {
ret = -ENOMEM;
goto free_region;
}
fb->dev = dev;
fb->board = board;
dev_info(&fb->dev->dev, "PL%03x designer %02x rev%u at 0x%08llx\n",
amba_part(dev), amba_manf(dev), amba_rev(dev),
(unsigned long long)dev->res.start);
ret = fb->board->setup(fb);
if (ret)
goto free_fb;
ret = clcdfb_register(fb);
if (ret == 0) {
amba_set_drvdata(dev, fb);
goto out;
}
fb->board->remove(fb);
free_fb:
kfree(fb);
free_region:
amba_release_regions(dev);
out:
return ret;
}
static void clcdfb_remove(struct amba_device *dev)
{
struct clcd_fb *fb = amba_get_drvdata(dev);
clcdfb_disable(fb);
unregister_framebuffer(&fb->fb);
if (fb->fb.cmap.len)
fb_dealloc_cmap(&fb->fb.cmap);
iounmap(fb->regs);
clk_unprepare(fb->clk);
clk_put(fb->clk);
fb->board->remove(fb);
kfree(fb);
amba_release_regions(dev);
}
static const struct amba_id clcdfb_id_table[] = {
{
.id = 0x00041110,
.mask = 0x000ffffe,
},
{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, clcdfb_id_table);
static struct amba_driver clcd_driver = {
.drv = {
.name = "clcd-pl11x",
},
.probe = clcdfb_probe,
.remove = clcdfb_remove,
.id_table = clcdfb_id_table,
};
static int __init amba_clcdfb_init(void)
{
if (fb_get_options("ambafb", NULL))
return -ENODEV;
return amba_driver_register(&clcd_driver);
}
module_init(amba_clcdfb_init);
static void __exit amba_clcdfb_exit(void)
{
amba_driver_unregister(&clcd_driver);
}
module_exit(amba_clcdfb_exit);
MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/amba-clcd.c |
/*
* drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
*
* Copyright 1999-2001 Jeff Garzik <[email protected]>
*
* Contributors (thanks, all!)
*
* David Eger:
* Overhaul for Linux 2.6
*
* Jeff Rugen:
* Major contributions; Motorola PowerStack (PPC and PCI) support,
* GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
*
* Geert Uytterhoeven:
* Excellent code review.
*
* Lars Hecking:
* Amiga updates and testing.
*
* Original cirrusfb author: Frank Neumann
*
* Based on retz3fb.c and cirrusfb.c:
* Copyright (C) 1997 Jes Sorensen
* Copyright (C) 1996 Frank Neumann
*
***************************************************************
*
* Format this code with GNU indent '-kr -i8 -pcs' options.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#ifdef CONFIG_ZORRO
#include <linux/zorro.h>
#endif
#ifdef CONFIG_PCI
#include <linux/pci.h>
#endif
#ifdef CONFIG_AMIGA
#include <asm/amigahw.h>
#endif
#include <video/vga.h>
#include <video/cirrus.h>
/*****************************************************************
*
* debugging and utility macros
*
*/
/* disable runtime assertions? */
/* #define CIRRUSFB_NDEBUG */
/* debugging assertions */
#ifndef CIRRUSFB_NDEBUG
#define assert(expr) \
if (!(expr)) { \
printk("Assertion failed! %s,%s,%s,line=%d\n", \
#expr, __FILE__, __func__, __LINE__); \
}
#else
#define assert(expr)
#endif
#define MB_ (1024 * 1024)
/*****************************************************************
*
* chipset information
*
*/
/* board types */
enum cirrus_board {
BT_NONE = 0,
BT_SD64, /* GD5434 */
BT_PICCOLO, /* GD5426 */
BT_PICASSO, /* GD5426 or GD5428 */
BT_SPECTRUM, /* GD5426 or GD5428 */
BT_PICASSO4, /* GD5446 */
BT_ALPINE, /* GD543x/4x */
BT_GD5480,
BT_LAGUNA, /* GD5462/64 */
BT_LAGUNAB, /* GD5465 */
};
/*
* per-board-type information, used for enumerating and abstracting
* chip-specific information
* NOTE: MUST be in the same order as enum cirrus_board in order to
* use direct indexing on this array
* NOTE: '__initdata' cannot be used as some of this info
* is required at runtime. Maybe separate into an init-only and
* a run-time table?
*/
static const struct cirrusfb_board_info_rec {
char *name; /* ASCII name of chipset */
long maxclock[5]; /* maximum video clock */
/* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
bool init_sr07 : 1; /* init SR07 during init_vgachip() */
bool init_sr1f : 1; /* write SR1F during init_vgachip() */
/* construct bit 19 of screen start address */
bool scrn_start_bit19 : 1;
/* initial SR07 value, then for each mode */
unsigned char sr07;
unsigned char sr07_1bpp;
unsigned char sr07_1bpp_mux;
unsigned char sr07_8bpp;
unsigned char sr07_8bpp_mux;
unsigned char sr1f; /* SR1F VGA initial register value */
} cirrusfb_board_info[] = {
[BT_SD64] = {
.name = "CL SD64",
.maxclock = {
/* guess */
/* the SD64/P4 have a higher max. videoclock */
135100, 135100, 85500, 85500, 0
},
.init_sr07 = true,
.init_sr1f = true,
.scrn_start_bit19 = true,
.sr07 = 0xF0,
.sr07_1bpp = 0xF0,
.sr07_1bpp_mux = 0xF6,
.sr07_8bpp = 0xF1,
.sr07_8bpp_mux = 0xF7,
.sr1f = 0x1E
},
[BT_PICCOLO] = {
.name = "CL Piccolo",
.maxclock = {
/* guess */
90000, 90000, 90000, 90000, 90000
},
.init_sr07 = true,
.init_sr1f = true,
.scrn_start_bit19 = false,
.sr07 = 0x80,
.sr07_1bpp = 0x80,
.sr07_8bpp = 0x81,
.sr1f = 0x22
},
[BT_PICASSO] = {
.name = "CL Picasso",
.maxclock = {
/* guess */
90000, 90000, 90000, 90000, 90000
},
.init_sr07 = true,
.init_sr1f = true,
.scrn_start_bit19 = false,
.sr07 = 0x20,
.sr07_1bpp = 0x20,
.sr07_8bpp = 0x21,
.sr1f = 0x22
},
[BT_SPECTRUM] = {
.name = "CL Spectrum",
.maxclock = {
/* guess */
90000, 90000, 90000, 90000, 90000
},
.init_sr07 = true,
.init_sr1f = true,
.scrn_start_bit19 = false,
.sr07 = 0x80,
.sr07_1bpp = 0x80,
.sr07_8bpp = 0x81,
.sr1f = 0x22
},
[BT_PICASSO4] = {
.name = "CL Picasso4",
.maxclock = {
135100, 135100, 85500, 85500, 0
},
.init_sr07 = true,
.init_sr1f = false,
.scrn_start_bit19 = true,
.sr07 = 0xA0,
.sr07_1bpp = 0xA0,
.sr07_1bpp_mux = 0xA6,
.sr07_8bpp = 0xA1,
.sr07_8bpp_mux = 0xA7,
.sr1f = 0
},
[BT_ALPINE] = {
.name = "CL Alpine",
.maxclock = {
/* for the GD5430. GD5446 can do more... */
85500, 85500, 50000, 28500, 0
},
.init_sr07 = true,
.init_sr1f = true,
.scrn_start_bit19 = true,
.sr07 = 0xA0,
.sr07_1bpp = 0xA0,
.sr07_1bpp_mux = 0xA6,
.sr07_8bpp = 0xA1,
.sr07_8bpp_mux = 0xA7,
.sr1f = 0x1C
},
[BT_GD5480] = {
.name = "CL GD5480",
.maxclock = {
135100, 200000, 200000, 135100, 135100
},
.init_sr07 = true,
.init_sr1f = true,
.scrn_start_bit19 = true,
.sr07 = 0x10,
.sr07_1bpp = 0x11,
.sr07_8bpp = 0x11,
.sr1f = 0x1C
},
[BT_LAGUNA] = {
.name = "CL Laguna",
.maxclock = {
/* taken from X11 code */
170000, 170000, 170000, 170000, 135100,
},
.init_sr07 = false,
.init_sr1f = false,
.scrn_start_bit19 = true,
},
[BT_LAGUNAB] = {
.name = "CL Laguna AGP",
.maxclock = {
/* taken from X11 code */
170000, 250000, 170000, 170000, 135100,
},
.init_sr07 = false,
.init_sr1f = false,
.scrn_start_bit19 = true,
}
};
#ifdef CONFIG_PCI
#define CHIP(id, btype) \
{ PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
static struct pci_device_id cirrusfb_pci_table[] = {
CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
{ 0, }
};
MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
#undef CHIP
#endif /* CONFIG_PCI */
#ifdef CONFIG_ZORRO
struct zorrocl {
enum cirrus_board type; /* Board type */
u32 regoffset; /* Offset of registers in first Zorro device */
u32 ramsize; /* Size of video RAM in first Zorro device */
/* If zero, use autoprobe on RAM device */
u32 ramoffset; /* Offset of video RAM in first Zorro device */
zorro_id ramid; /* Zorro ID of RAM device */
zorro_id ramid2; /* Zorro ID of optional second RAM device */
};
static const struct zorrocl zcl_sd64 = {
.type = BT_SD64,
.ramid = ZORRO_PROD_HELFRICH_SD64_RAM,
};
static const struct zorrocl zcl_piccolo = {
.type = BT_PICCOLO,
.ramid = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
};
static const struct zorrocl zcl_picasso = {
.type = BT_PICASSO,
.ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
};
static const struct zorrocl zcl_spectrum = {
.type = BT_SPECTRUM,
.ramid = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
};
static const struct zorrocl zcl_picasso4_z3 = {
.type = BT_PICASSO4,
.regoffset = 0x00600000,
.ramsize = 4 * MB_,
.ramoffset = 0x01000000, /* 0x02000000 for 64 MiB boards */
};
static const struct zorrocl zcl_picasso4_z2 = {
.type = BT_PICASSO4,
.regoffset = 0x10000,
.ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1,
.ramid2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2,
};
static const struct zorro_device_id cirrusfb_zorro_table[] = {
{
.id = ZORRO_PROD_HELFRICH_SD64_REG,
.driver_data = (unsigned long)&zcl_sd64,
}, {
.id = ZORRO_PROD_HELFRICH_PICCOLO_REG,
.driver_data = (unsigned long)&zcl_piccolo,
}, {
.id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
.driver_data = (unsigned long)&zcl_picasso,
}, {
.id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
.driver_data = (unsigned long)&zcl_spectrum,
}, {
.id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
.driver_data = (unsigned long)&zcl_picasso4_z3,
}, {
.id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG,
.driver_data = (unsigned long)&zcl_picasso4_z2,
},
{ 0 }
};
MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);
#endif /* CONFIG_ZORRO */
#ifdef CIRRUSFB_DEBUG
enum cirrusfb_dbg_reg_class {
CRT,
SEQ
};
#endif /* CIRRUSFB_DEBUG */
/* info about board */
struct cirrusfb_info {
u8 __iomem *regbase;
u8 __iomem *laguna_mmio;
enum cirrus_board btype;
unsigned char SFR; /* Shadow of special function register */
int multiplexing;
int doubleVCLK;
int blank_mode;
u32 pseudo_palette[16];
void (*unmap)(struct fb_info *info);
};
static bool noaccel;
static char *mode_option = "640x480@60";
/****************************************************************************/
/**** BEGIN PROTOTYPES ******************************************************/
/*--- Interface used by the world ------------------------------------------*/
static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info);
/*--- Internal routines ----------------------------------------------------*/
static void init_vgachip(struct fb_info *info);
static void switch_monitor(struct cirrusfb_info *cinfo, int on);
static void WGen(const struct cirrusfb_info *cinfo,
int regnum, unsigned char val);
static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
static void AttrOn(const struct cirrusfb_info *cinfo);
static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
unsigned char red, unsigned char green, unsigned char blue);
#if 0
static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
unsigned char *red, unsigned char *green,
unsigned char *blue);
#endif
static void cirrusfb_WaitBLT(u8 __iomem *regbase);
static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
u_short curx, u_short cury,
u_short destx, u_short desty,
u_short width, u_short height,
u_short line_length);
static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
u_short x, u_short y,
u_short width, u_short height,
u32 fg_color, u32 bg_color,
u_short line_length, u_char blitmode);
static void bestclock(long freq, int *nom, int *den, int *div);
#ifdef CIRRUSFB_DEBUG
static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
static void cirrusfb_dbg_print_regs(struct fb_info *info,
caddr_t regbase,
enum cirrusfb_dbg_reg_class reg_class, ...);
#endif /* CIRRUSFB_DEBUG */
/*** END PROTOTYPES ********************************************************/
/*****************************************************************************/
/*** BEGIN Interface Used by the World ***************************************/
static inline int is_laguna(const struct cirrusfb_info *cinfo)
{
return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
}
static int opencount;
/*--- Open /dev/fbx ---------------------------------------------------------*/
static int cirrusfb_open(struct fb_info *info, int user)
{
if (opencount++ == 0)
switch_monitor(info->par, 1);
return 0;
}
/*--- Close /dev/fbx --------------------------------------------------------*/
static int cirrusfb_release(struct fb_info *info, int user)
{
if (--opencount == 0)
switch_monitor(info->par, 0);
return 0;
}
/**** END Interface used by the World *************************************/
/****************************************************************************/
/**** BEGIN Hardware specific Routines **************************************/
/* Check if the MCLK is not a better clock source */
static int cirrusfb_check_mclk(struct fb_info *info, long freq)
{
struct cirrusfb_info *cinfo = info->par;
long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
/* Read MCLK value */
mclk = (14318 * mclk) >> 3;
dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
/* Determine if we should use MCLK instead of VCLK, and if so, what we
* should divide it by to get VCLK
*/
if (abs(freq - mclk) < 250) {
dev_dbg(info->device, "Using VCLK = MCLK\n");
return 1;
} else if (abs(freq - (mclk / 2)) < 250) {
dev_dbg(info->device, "Using VCLK = MCLK/2\n");
return 2;
}
return 0;
}
static int cirrusfb_check_pixclock(struct fb_var_screeninfo *var,
struct fb_info *info)
{
long freq;
long maxclock;
struct cirrusfb_info *cinfo = info->par;
unsigned maxclockidx = var->bits_per_pixel >> 3;
/* convert from ps to kHz */
freq = PICOS2KHZ(var->pixclock ? : 1);
maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
cinfo->multiplexing = 0;
/* If the frequency is greater than we can support, we might be able
* to use multiplexing for the video mode */
if (freq > maxclock) {
var->pixclock = KHZ2PICOS(maxclock);
while ((freq = PICOS2KHZ(var->pixclock)) > maxclock)
var->pixclock++;
}
dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
/*
* Additional constraint: 8bpp uses DAC clock doubling to allow maximum
* pixel clock
*/
if (var->bits_per_pixel == 8) {
switch (cinfo->btype) {
case BT_ALPINE:
case BT_SD64:
case BT_PICASSO4:
if (freq > 85500)
cinfo->multiplexing = 1;
break;
case BT_GD5480:
if (freq > 135100)
cinfo->multiplexing = 1;
break;
default:
break;
}
}
/* If we have a 1MB 5434, we need to put ourselves in a mode where
* the VCLK is double the pixel clock. */
cinfo->doubleVCLK = 0;
if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
var->bits_per_pixel == 16) {
cinfo->doubleVCLK = 1;
}
return 0;
}
static int cirrusfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int yres;
/* memory size in pixels */
unsigned int pixels;
struct cirrusfb_info *cinfo = info->par;
switch (var->bits_per_pixel) {
case 1:
var->red.offset = 0;
var->red.length = 1;
var->green = var->red;
var->blue = var->red;
break;
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green = var->red;
var->blue = var->red;
break;
case 16:
var->red.offset = 11;
var->green.offset = 5;
var->blue.offset = 0;
var->red.length = 5;
var->green.length = 6;
var->blue.length = 5;
break;
case 24:
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
break;
default:
dev_dbg(info->device,
"Unsupported bpp size: %d\n", var->bits_per_pixel);
return -EINVAL;
}
pixels = info->screen_size * 8 / var->bits_per_pixel;
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
/* use highest possible virtual resolution */
if (var->yres_virtual == -1) {
var->yres_virtual = pixels / var->xres_virtual;
dev_info(info->device,
"virtual resolution set to maximum of %dx%d\n",
var->xres_virtual, var->yres_virtual);
}
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
if (var->xres_virtual * var->yres_virtual > pixels) {
dev_err(info->device, "mode %dx%dx%d rejected... "
"virtual resolution too high to fit into video memory!\n",
var->xres_virtual, var->yres_virtual,
var->bits_per_pixel);
return -EINVAL;
}
/* truncate xoffset and yoffset to maximum if too high */
if (var->xoffset > var->xres_virtual - var->xres)
var->xoffset = var->xres_virtual - var->xres - 1;
if (var->yoffset > var->yres_virtual - var->yres)
var->yoffset = var->yres_virtual - var->yres - 1;
var->red.msb_right =
var->green.msb_right =
var->blue.msb_right =
var->transp.offset =
var->transp.length =
var->transp.msb_right = 0;
yres = var->yres;
if (var->vmode & FB_VMODE_DOUBLE)
yres *= 2;
else if (var->vmode & FB_VMODE_INTERLACED)
yres = (yres + 1) / 2;
if (yres >= 1280) {
dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
"special treatment required! (TODO)\n");
return -EINVAL;
}
if (cirrusfb_check_pixclock(var, info))
return -EINVAL;
if (!is_laguna(cinfo))
var->accel_flags = FB_ACCELF_TEXT;
return 0;
}
static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
{
struct cirrusfb_info *cinfo = info->par;
unsigned char old1f, old1e;
assert(cinfo != NULL);
old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
if (div) {
dev_dbg(info->device, "Set %s as pixclock source.\n",
(div == 2) ? "MCLK/2" : "MCLK");
old1f |= 0x40;
old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
if (div == 2)
old1e |= 1;
vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
}
vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
}
/*************************************************************************
cirrusfb_set_par_foo()
actually writes the values for a new video mode into the hardware,
**************************************************************************/
static int cirrusfb_set_par_foo(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
struct fb_var_screeninfo *var = &info->var;
u8 __iomem *regbase = cinfo->regbase;
unsigned char tmp;
int pitch;
const struct cirrusfb_board_info_rec *bi;
int hdispend, hsyncstart, hsyncend, htotal;
int yres, vdispend, vsyncstart, vsyncend, vtotal;
long freq;
int nom, den, div;
unsigned int control = 0, format = 0, threshold = 0;
dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
var->xres, var->yres, var->bits_per_pixel);
switch (var->bits_per_pixel) {
case 1:
info->fix.line_length = var->xres_virtual / 8;
info->fix.visual = FB_VISUAL_MONO10;
break;
case 8:
info->fix.line_length = var->xres_virtual;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
case 24:
info->fix.line_length = var->xres_virtual *
var->bits_per_pixel >> 3;
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
}
info->fix.type = FB_TYPE_PACKED_PIXELS;
init_vgachip(info);
bi = &cirrusfb_board_info[cinfo->btype];
hsyncstart = var->xres + var->right_margin;
hsyncend = hsyncstart + var->hsync_len;
htotal = (hsyncend + var->left_margin) / 8;
hdispend = var->xres / 8;
hsyncstart = hsyncstart / 8;
hsyncend = hsyncend / 8;
vdispend = var->yres;
vsyncstart = vdispend + var->lower_margin;
vsyncend = vsyncstart + var->vsync_len;
vtotal = vsyncend + var->upper_margin;
if (var->vmode & FB_VMODE_DOUBLE) {
vdispend *= 2;
vsyncstart *= 2;
vsyncend *= 2;
vtotal *= 2;
} else if (var->vmode & FB_VMODE_INTERLACED) {
vdispend = (vdispend + 1) / 2;
vsyncstart = (vsyncstart + 1) / 2;
vsyncend = (vsyncend + 1) / 2;
vtotal = (vtotal + 1) / 2;
}
yres = vdispend;
if (yres >= 1024) {
vtotal /= 2;
vsyncstart /= 2;
vsyncend /= 2;
vdispend /= 2;
}
vdispend -= 1;
vsyncstart -= 1;
vsyncend -= 1;
vtotal -= 2;
if (cinfo->multiplexing) {
htotal /= 2;
hsyncstart /= 2;
hsyncend /= 2;
hdispend /= 2;
}
htotal -= 5;
hdispend -= 1;
hsyncstart += 1;
hsyncend += 1;
/* unlock register VGA_CRTC_H_TOTAL..CRT7 */
vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
/* if debugging is enabled, all parameters get output before writing */
dev_dbg(info->device, "CRT0: %d\n", htotal);
vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
dev_dbg(info->device, "CRT1: %d\n", hdispend);
vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
/* + 128: Compatible read */
dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
128 + ((htotal + 5) % 32));
dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
tmp = hsyncend % 32;
if ((htotal + 5) & 32)
tmp += 128;
dev_dbg(info->device, "CRT5: %d\n", tmp);
vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
tmp = 16; /* LineCompare bit #9 */
if (vtotal & 256)
tmp |= 1;
if (vdispend & 256)
tmp |= 2;
if (vsyncstart & 256)
tmp |= 4;
if ((vdispend + 1) & 256)
tmp |= 8;
if (vtotal & 512)
tmp |= 32;
if (vdispend & 512)
tmp |= 64;
if (vsyncstart & 512)
tmp |= 128;
dev_dbg(info->device, "CRT7: %d\n", tmp);
vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
tmp = 0x40; /* LineCompare bit #8 */
if ((vdispend + 1) & 512)
tmp |= 0x20;
if (var->vmode & FB_VMODE_DOUBLE)
tmp |= 0x80;
dev_dbg(info->device, "CRT9: %d\n", tmp);
vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
dev_dbg(info->device, "CRT18: 0xff\n");
vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
tmp = 0;
if (var->vmode & FB_VMODE_INTERLACED)
tmp |= 1;
if ((htotal + 5) & 64)
tmp |= 16;
if ((htotal + 5) & 128)
tmp |= 32;
if (vtotal & 256)
tmp |= 64;
if (vtotal & 512)
tmp |= 128;
dev_dbg(info->device, "CRT1a: %d\n", tmp);
vga_wcrt(regbase, CL_CRT1A, tmp);
freq = PICOS2KHZ(var->pixclock);
if (var->bits_per_pixel == 24)
if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
freq *= 3;
if (cinfo->multiplexing)
freq /= 2;
if (cinfo->doubleVCLK)
freq *= 2;
bestclock(freq, &nom, &den, &div);
dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
freq, nom, den, div);
/* set VCLK0 */
/* hardware RefClock: 14.31818 MHz */
/* formula: VClk = (OSC * N) / (D * (1+P)) */
/* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
cinfo->btype == BT_SD64) {
/* if freq is close to mclk or mclk/2 select mclk
* as clock source
*/
int divMCLK = cirrusfb_check_mclk(info, freq);
if (divMCLK)
nom = 0;
cirrusfb_set_mclk_as_source(info, divMCLK);
}
if (is_laguna(cinfo)) {
long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
unsigned short tile_control;
if (cinfo->btype == BT_LAGUNAB) {
tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
tile_control &= ~0x80;
fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
}
fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
control = fb_readw(cinfo->laguna_mmio + 0x402);
threshold = fb_readw(cinfo->laguna_mmio + 0xea);
control &= ~0x6800;
format = 0;
threshold &= 0xffc0 & 0x3fbf;
}
if (nom) {
tmp = den << 1;
if (div != 0)
tmp |= 1;
/* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
if ((cinfo->btype == BT_SD64) ||
(cinfo->btype == BT_ALPINE) ||
(cinfo->btype == BT_GD5480))
tmp |= 0x80;
/* Laguna chipset has reversed clock registers */
if (is_laguna(cinfo)) {
vga_wseq(regbase, CL_SEQRE, tmp);
vga_wseq(regbase, CL_SEQR1E, nom);
} else {
vga_wseq(regbase, CL_SEQRE, nom);
vga_wseq(regbase, CL_SEQR1E, tmp);
}
}
if (yres >= 1024)
/* 1280x1024 */
vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
else
/* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
* address wrap, no compat. */
vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
/* don't know if it would hurt to also program this if no interlaced */
/* mode is used, but I feel better this way.. :-) */
if (var->vmode & FB_VMODE_INTERLACED)
vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
else
vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
/* adjust horizontal/vertical sync type (low/high), use VCLK3 */
/* enable display memory & CRTC I/O address for color mode */
tmp = 0x03 | 0xc;
if (var->sync & FB_SYNC_HOR_HIGH_ACT)
tmp |= 0x40;
if (var->sync & FB_SYNC_VERT_HIGH_ACT)
tmp |= 0x80;
WGen(cinfo, VGA_MIS_W, tmp);
/* text cursor on and start line */
vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
/* text cursor end line */
vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
/******************************************************
*
* 1 bpp
*
*/
/* programming for different color depths */
if (var->bits_per_pixel == 1) {
dev_dbg(info->device, "preparing for 1 bit deep display\n");
vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
/* SR07 */
switch (cinfo->btype) {
case BT_SD64:
case BT_PICCOLO:
case BT_PICASSO:
case BT_SPECTRUM:
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
vga_wseq(regbase, CL_SEQR7,
cinfo->multiplexing ?
bi->sr07_1bpp_mux : bi->sr07_1bpp);
break;
case BT_LAGUNA:
case BT_LAGUNAB:
vga_wseq(regbase, CL_SEQR7,
vga_rseq(regbase, CL_SEQR7) & ~0x01);
break;
default:
dev_warn(info->device, "unknown Board\n");
break;
}
/* Extended Sequencer Mode */
switch (cinfo->btype) {
case BT_PICCOLO:
case BT_SPECTRUM:
/* evtl d0 bei 1 bit? avoid FIFO underruns..? */
vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO:
/* ## vorher d0 avoid FIFO underruns..? */
vga_wseq(regbase, CL_SEQRF, 0xd0);
break;
case BT_SD64:
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
case BT_LAGUNA:
case BT_LAGUNAB:
/* do nothing */
break;
default:
dev_warn(info->device, "unknown Board\n");
break;
}
/* pixel mask: pass-through for first plane */
WGen(cinfo, VGA_PEL_MSK, 0x01);
if (cinfo->multiplexing)
/* hidden dac reg: 1280x1024 */
WHDR(cinfo, 0x4a);
else
/* hidden dac: nothing */
WHDR(cinfo, 0);
/* memory mode: odd/even, ext. memory */
vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
/* plane mask: only write to first plane */
vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
}
/******************************************************
*
* 8 bpp
*
*/
else if (var->bits_per_pixel == 8) {
dev_dbg(info->device, "preparing for 8 bit deep display\n");
switch (cinfo->btype) {
case BT_SD64:
case BT_PICCOLO:
case BT_PICASSO:
case BT_SPECTRUM:
case BT_PICASSO4:
case BT_ALPINE:
case BT_GD5480:
vga_wseq(regbase, CL_SEQR7,
cinfo->multiplexing ?
bi->sr07_8bpp_mux : bi->sr07_8bpp);
break;
case BT_LAGUNA:
case BT_LAGUNAB:
vga_wseq(regbase, CL_SEQR7,
vga_rseq(regbase, CL_SEQR7) | 0x01);
threshold |= 0x10;
break;
default:
dev_warn(info->device, "unknown Board\n");
break;
}
switch (cinfo->btype) {
case BT_PICCOLO:
case BT_PICASSO:
case BT_SPECTRUM:
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO4:
#ifdef CONFIG_ZORRO
/* ### INCOMPLETE!! */
vga_wseq(regbase, CL_SEQRF, 0xb8);
#endif
case BT_ALPINE:
case BT_SD64:
case BT_GD5480:
case BT_LAGUNA:
case BT_LAGUNAB:
/* do nothing */
break;
default:
dev_warn(info->device, "unknown board\n");
break;
}
/* mode register: 256 color mode */
vga_wgfx(regbase, VGA_GFX_MODE, 64);
if (cinfo->multiplexing)
/* hidden dac reg: 1280x1024 */
WHDR(cinfo, 0x4a);
else
/* hidden dac: nothing */
WHDR(cinfo, 0);
}
/******************************************************
*
* 16 bpp
*
*/
else if (var->bits_per_pixel == 16) {
dev_dbg(info->device, "preparing for 16 bit deep display\n");
switch (cinfo->btype) {
case BT_PICCOLO:
case BT_SPECTRUM:
vga_wseq(regbase, CL_SEQR7, 0x87);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO:
vga_wseq(regbase, CL_SEQR7, 0x27);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_SD64:
case BT_PICASSO4:
case BT_ALPINE:
/* Extended Sequencer Mode: 256c col. mode */
vga_wseq(regbase, CL_SEQR7,
cinfo->doubleVCLK ? 0xa3 : 0xa7);
break;
case BT_GD5480:
vga_wseq(regbase, CL_SEQR7, 0x17);
/* We already set SRF and SR1F */
break;
case BT_LAGUNA:
case BT_LAGUNAB:
vga_wseq(regbase, CL_SEQR7,
vga_rseq(regbase, CL_SEQR7) & ~0x01);
control |= 0x2000;
format |= 0x1400;
threshold |= 0x10;
break;
default:
dev_warn(info->device, "unknown Board\n");
break;
}
/* mode register: 256 color mode */
vga_wgfx(regbase, VGA_GFX_MODE, 64);
#ifdef CONFIG_PCI
WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
#elif defined(CONFIG_ZORRO)
/* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
#endif
}
/******************************************************
*
* 24 bpp
*
*/
else if (var->bits_per_pixel == 24) {
dev_dbg(info->device, "preparing for 24 bit deep display\n");
switch (cinfo->btype) {
case BT_PICCOLO:
case BT_SPECTRUM:
vga_wseq(regbase, CL_SEQR7, 0x85);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_PICASSO:
vga_wseq(regbase, CL_SEQR7, 0x25);
/* Fast Page-Mode writes */
vga_wseq(regbase, CL_SEQRF, 0xb0);
break;
case BT_SD64:
case BT_PICASSO4:
case BT_ALPINE:
/* Extended Sequencer Mode: 256c col. mode */
vga_wseq(regbase, CL_SEQR7, 0xa5);
break;
case BT_GD5480:
vga_wseq(regbase, CL_SEQR7, 0x15);
/* We already set SRF and SR1F */
break;
case BT_LAGUNA:
case BT_LAGUNAB:
vga_wseq(regbase, CL_SEQR7,
vga_rseq(regbase, CL_SEQR7) & ~0x01);
control |= 0x4000;
format |= 0x2400;
threshold |= 0x20;
break;
default:
dev_warn(info->device, "unknown Board\n");
break;
}
/* mode register: 256 color mode */
vga_wgfx(regbase, VGA_GFX_MODE, 64);
/* hidden dac reg: 8-8-8 mode (24 or 32) */
WHDR(cinfo, 0xc5);
}
/******************************************************
*
* unknown/unsupported bpp
*
*/
else
dev_err(info->device,
"What's this? requested color depth == %d.\n",
var->bits_per_pixel);
pitch = info->fix.line_length >> 3;
vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
tmp = 0x22;
if (pitch & 0x100)
tmp |= 0x10; /* offset overflow bit */
/* screen start addr #16-18, fastpagemode cycles */
vga_wcrt(regbase, CL_CRT1B, tmp);
/* screen start address bit 19 */
if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
if (is_laguna(cinfo)) {
tmp = 0;
if ((htotal + 5) & 256)
tmp |= 128;
if (hdispend & 256)
tmp |= 64;
if (hsyncstart & 256)
tmp |= 48;
if (vtotal & 1024)
tmp |= 8;
if (vdispend & 1024)
tmp |= 4;
if (vsyncstart & 1024)
tmp |= 3;
vga_wcrt(regbase, CL_CRT1E, tmp);
dev_dbg(info->device, "CRT1e: %d\n", tmp);
}
/* pixel panning */
vga_wattr(regbase, CL_AR33, 0);
/* [ EGS: SetOffset(); ] */
/* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
AttrOn(cinfo);
if (is_laguna(cinfo)) {
/* no tiles */
fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
fb_writew(format, cinfo->laguna_mmio + 0xc0);
fb_writew(threshold, cinfo->laguna_mmio + 0xea);
}
/* finally, turn on everything - turn off "FullBandwidth" bit */
/* also, set "DotClock%2" bit where requested */
tmp = 0x01;
/*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
if (var->vmode & FB_VMODE_CLOCK_HALVE)
tmp |= 0x08;
*/
vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
#ifdef CIRRUSFB_DEBUG
cirrusfb_dbg_reg_dump(info, NULL);
#endif
return 0;
}
/* for some reason incomprehensible to me, cirrusfb requires that you write
* the registers twice for the settings to take..grr. -dte */
static int cirrusfb_set_par(struct fb_info *info)
{
cirrusfb_set_par_foo(info);
return cirrusfb_set_par_foo(info);
}
static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
if (regno > 255)
return -EINVAL;
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 v;
red >>= (16 - info->var.red.length);
green >>= (16 - info->var.green.length);
blue >>= (16 - info->var.blue.length);
if (regno >= 16)
return 1;
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset);
cinfo->pseudo_palette[regno] = v;
return 0;
}
if (info->var.bits_per_pixel == 8)
WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
return 0;
}
/*************************************************************************
cirrusfb_pan_display()
performs display panning - provided hardware permits this
**************************************************************************/
static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int xoffset;
unsigned long base;
unsigned char tmp, xpix;
struct cirrusfb_info *cinfo = info->par;
/* no range checks for xoffset and yoffset, */
/* as fb_pan_display has already done this */
if (var->vmode & FB_VMODE_YWRAP)
return -EINVAL;
xoffset = var->xoffset * info->var.bits_per_pixel / 8;
base = var->yoffset * info->fix.line_length + xoffset;
if (info->var.bits_per_pixel == 1) {
/* base is already correct */
xpix = (unsigned char) (var->xoffset % 8);
} else {
base /= 4;
xpix = (unsigned char) ((xoffset % 4) * 2);
}
if (!is_laguna(cinfo))
cirrusfb_WaitBLT(cinfo->regbase);
/* lower 8 + 8 bits of screen start address */
vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
/* 0xf2 is %11110010, exclude tmp bits */
tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
/* construct bits 16, 17 and 18 of screen start address */
if (base & 0x10000)
tmp |= 0x01;
if (base & 0x20000)
tmp |= 0x04;
if (base & 0x40000)
tmp |= 0x08;
vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
/* construct bit 19 of screen start address */
if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
if (is_laguna(cinfo))
tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
else
tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
}
/* write pixel panning value to AR33; this does not quite work in 8bpp
*
* ### Piccolo..? Will this work?
*/
if (info->var.bits_per_pixel == 1)
vga_wattr(cinfo->regbase, CL_AR33, xpix);
return 0;
}
static int cirrusfb_blank(int blank_mode, struct fb_info *info)
{
/*
* Blank the screen if blank_mode != 0, else unblank. If blank == NULL
* then the caller blanks by setting the CLUT (Color Look Up Table)
* to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
* failed due to e.g. a video mode which doesn't support it.
* Implements VESA suspend and powerdown modes on hardware that
* supports disabling hsync/vsync:
* blank_mode == 2: suspend vsync
* blank_mode == 3: suspend hsync
* blank_mode == 4: powerdown
*/
unsigned char val;
struct cirrusfb_info *cinfo = info->par;
int current_mode = cinfo->blank_mode;
dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
if (info->state != FBINFO_STATE_RUNNING ||
current_mode == blank_mode) {
dev_dbg(info->device, "EXIT, returning 0\n");
return 0;
}
/* Undo current */
if (current_mode == FB_BLANK_NORMAL ||
current_mode == FB_BLANK_UNBLANK)
/* clear "FullBandwidth" bit */
val = 0;
else
/* set "FullBandwidth" bit */
val = 0x20;
val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
switch (blank_mode) {
case FB_BLANK_UNBLANK:
case FB_BLANK_NORMAL:
val = 0x00;
break;
case FB_BLANK_VSYNC_SUSPEND:
val = 0x04;
break;
case FB_BLANK_HSYNC_SUSPEND:
val = 0x02;
break;
case FB_BLANK_POWERDOWN:
val = 0x06;
break;
default:
dev_dbg(info->device, "EXIT, returning 1\n");
return 1;
}
vga_wgfx(cinfo->regbase, CL_GRE, val);
cinfo->blank_mode = blank_mode;
dev_dbg(info->device, "EXIT, returning 0\n");
/* Let fbcon do a soft blank for us */
return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
}
/**** END Hardware specific Routines **************************************/
/****************************************************************************/
/**** BEGIN Internal Routines ***********************************************/
static void init_vgachip(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
const struct cirrusfb_board_info_rec *bi;
assert(cinfo != NULL);
bi = &cirrusfb_board_info[cinfo->btype];
/* reset board globally */
switch (cinfo->btype) {
case BT_PICCOLO:
WSFR(cinfo, 0x01);
udelay(500);
WSFR(cinfo, 0x51);
udelay(500);
break;
case BT_PICASSO:
WSFR2(cinfo, 0xff);
udelay(500);
break;
case BT_SD64:
case BT_SPECTRUM:
WSFR(cinfo, 0x1f);
udelay(500);
WSFR(cinfo, 0x4f);
udelay(500);
break;
case BT_PICASSO4:
/* disable flickerfixer */
vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
mdelay(100);
/* mode */
vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
fallthrough;
case BT_GD5480:
/* from Klaus' NetBSD driver: */
vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
fallthrough;
case BT_ALPINE:
/* put blitter into 542x compat */
vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
break;
case BT_LAGUNA:
case BT_LAGUNAB:
/* Nothing to do to reset the board. */
break;
default:
dev_err(info->device, "Warning: Unknown board type\n");
break;
}
/* make sure RAM size set by this point */
assert(info->screen_size > 0);
/* the P4 is not fully initialized here; I rely on it having been */
/* inited under AmigaOS already, which seems to work just fine */
/* (Klaus advised to do it this way) */
if (cinfo->btype != BT_PICASSO4) {
WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
WGen(cinfo, CL_POS102, 0x01);
WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
if (cinfo->btype != BT_SD64)
WGen(cinfo, CL_VSSM2, 0x01);
/* reset sequencer logic */
vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
/* FullBandwidth (video off) and 8/9 dot clock */
vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
/* "magic cookie" - doesn't make any sense to me.. */
/* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
/* unlock all extension registers */
vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
switch (cinfo->btype) {
case BT_GD5480:
vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
break;
case BT_ALPINE:
case BT_LAGUNA:
case BT_LAGUNAB:
break;
case BT_SD64:
#ifdef CONFIG_ZORRO
vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
#endif
break;
default:
vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
break;
}
}
/* plane mask: nothing */
vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
/* character map select: doesn't even matter in gx mode */
vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
/* memory mode: chain4, ext. memory */
vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
/* controller-internal base address of video memory */
if (bi->init_sr07)
vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
/* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
/* EEPROM control: shouldn't be necessary to write to this at all.. */
/* graphics cursor X position (incomplete; position gives rem. 3 bits */
vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
/* graphics cursor Y position (..."... ) */
vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
/* graphics cursor attributes */
vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
/* graphics cursor pattern address */
vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
/* writing these on a P4 might give problems.. */
if (cinfo->btype != BT_PICASSO4) {
/* configuration readback and ext. color */
vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
/* signature generator */
vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
}
/* Screen A preset row scan: none */
vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
/* Text cursor start: disable text cursor */
vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
/* Text cursor end: - */
vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
/* text cursor location high: 0 */
vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
/* text cursor location low: 0 */
vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
/* Underline Row scanline: - */
vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
/* ### add 0x40 for text modes with > 30 MHz pixclock */
/* ext. display controls: ext.adr. wrap */
vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
/* Set/Reset registers: - */
vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
/* Set/Reset enable: - */
vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
/* Color Compare: - */
vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
/* Data Rotate: - */
vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
/* Read Map Select: - */
vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
/* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
/* Miscellaneous: memory map base address, graphics mode */
vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
/* Color Don't care: involve all planes */
vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
/* Bit Mask: no mask at all */
vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
is_laguna(cinfo))
/* (5434 can't have bit 3 set for bitblt) */
vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
else
/* Graphics controller mode extensions: finer granularity,
* 8byte data latches
*/
vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
/* Background color byte 1: - */
/* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
/* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
/* Attribute Controller palette registers: "identity mapping" */
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
/* Attribute Controller mode: graphics mode */
vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
/* Overscan color reg.: reg. 0 */
vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
/* Color Plane enable: Enable all 4 planes */
vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
/* Color Select: - */
vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
/* BLT Start/status: Blitter reset */
vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
/* - " - : "end-of-reset" */
vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
/* misc... */
WHDR(cinfo, 0); /* Hidden DAC register: - */
return;
}
static void switch_monitor(struct cirrusfb_info *cinfo, int on)
{
#ifdef CONFIG_ZORRO /* only works on Zorro boards */
static int IsOn = 0; /* XXX not ok for multiple boards */
if (cinfo->btype == BT_PICASSO4)
return; /* nothing to switch */
if (cinfo->btype == BT_ALPINE)
return; /* nothing to switch */
if (cinfo->btype == BT_GD5480)
return; /* nothing to switch */
if (cinfo->btype == BT_PICASSO) {
if ((on && !IsOn) || (!on && IsOn))
WSFR(cinfo, 0xff);
return;
}
if (on) {
switch (cinfo->btype) {
case BT_SD64:
WSFR(cinfo, cinfo->SFR | 0x21);
break;
case BT_PICCOLO:
WSFR(cinfo, cinfo->SFR | 0x28);
break;
case BT_SPECTRUM:
WSFR(cinfo, 0x6f);
break;
default: /* do nothing */ break;
}
} else {
switch (cinfo->btype) {
case BT_SD64:
WSFR(cinfo, cinfo->SFR & 0xde);
break;
case BT_PICCOLO:
WSFR(cinfo, cinfo->SFR & 0xd7);
break;
case BT_SPECTRUM:
WSFR(cinfo, 0x4f);
break;
default: /* do nothing */
break;
}
}
#endif /* CONFIG_ZORRO */
}
/******************************************/
/* Linux 2.6-style accelerated functions */
/******************************************/
static int cirrusfb_sync(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
if (!is_laguna(cinfo)) {
while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
cpu_relax();
}
return 0;
}
static void cirrusfb_fillrect(struct fb_info *info,
const struct fb_fillrect *region)
{
struct fb_fillrect modded;
int vxres, vyres;
struct cirrusfb_info *cinfo = info->par;
int m = info->var.bits_per_pixel;
u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
cinfo->pseudo_palette[region->color] : region->color;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_fillrect(info, region);
return;
}
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
memcpy(&modded, region, sizeof(struct fb_fillrect));
if (!modded.width || !modded.height ||
modded.dx >= vxres || modded.dy >= vyres)
return;
if (modded.dx + modded.width > vxres)
modded.width = vxres - modded.dx;
if (modded.dy + modded.height > vyres)
modded.height = vyres - modded.dy;
cirrusfb_RectFill(cinfo->regbase,
info->var.bits_per_pixel,
(region->dx * m) / 8, region->dy,
(region->width * m) / 8, region->height,
color, color,
info->fix.line_length, 0x40);
}
static void cirrusfb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
struct fb_copyarea modded;
u32 vxres, vyres;
struct cirrusfb_info *cinfo = info->par;
int m = info->var.bits_per_pixel;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_copyarea(info, area);
return;
}
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
memcpy(&modded, area, sizeof(struct fb_copyarea));
if (!modded.width || !modded.height ||
modded.sx >= vxres || modded.sy >= vyres ||
modded.dx >= vxres || modded.dy >= vyres)
return;
if (modded.sx + modded.width > vxres)
modded.width = vxres - modded.sx;
if (modded.dx + modded.width > vxres)
modded.width = vxres - modded.dx;
if (modded.sy + modded.height > vyres)
modded.height = vyres - modded.sy;
if (modded.dy + modded.height > vyres)
modded.height = vyres - modded.dy;
cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
(area->sx * m) / 8, area->sy,
(area->dx * m) / 8, area->dy,
(area->width * m) / 8, area->height,
info->fix.line_length);
}
static void cirrusfb_imageblit(struct fb_info *info,
const struct fb_image *image)
{
struct cirrusfb_info *cinfo = info->par;
unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
if (info->state != FBINFO_STATE_RUNNING)
return;
/* Alpine/SD64 does not work at 24bpp ??? */
if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
cfb_imageblit(info, image);
else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
op == 0xc)
cfb_imageblit(info, image);
else {
unsigned size = ((image->width + 7) >> 3) * image->height;
int m = info->var.bits_per_pixel;
u32 fg, bg;
if (info->var.bits_per_pixel == 8) {
fg = image->fg_color;
bg = image->bg_color;
} else {
fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
}
if (info->var.bits_per_pixel == 24) {
/* clear background first */
cirrusfb_RectFill(cinfo->regbase,
info->var.bits_per_pixel,
(image->dx * m) / 8, image->dy,
(image->width * m) / 8,
image->height,
bg, bg,
info->fix.line_length, 0x40);
}
cirrusfb_RectFill(cinfo->regbase,
info->var.bits_per_pixel,
(image->dx * m) / 8, image->dy,
(image->width * m) / 8, image->height,
fg, bg,
info->fix.line_length, op);
memcpy(info->screen_base, image->data, size);
}
}
#ifdef CONFIG_PCI
static int release_io_ports;
/* Pulled the logic from XFree86 Cirrus driver to get the memory size,
* based on the DRAM bandwidth bit and DRAM bank switching bit. This
* works with 1MB, 2MB and 4MB configurations (which the Motorola boards
* seem to have. */
static unsigned int cirrusfb_get_memsize(struct fb_info *info,
u8 __iomem *regbase)
{
unsigned long mem;
struct cirrusfb_info *cinfo = info->par;
if (is_laguna(cinfo)) {
unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
mem = ((SR14 & 7) + 1) << 20;
} else {
unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
switch ((SRF & 0x18)) {
case 0x08:
mem = 512 * 1024;
break;
case 0x10:
mem = 1024 * 1024;
break;
/* 64-bit DRAM data bus width; assume 2MB.
* Also indicates 2MB memory on the 5430.
*/
case 0x18:
mem = 2048 * 1024;
break;
default:
dev_warn(info->device, "Unknown memory size!\n");
mem = 1024 * 1024;
}
/* If DRAM bank switching is enabled, there must be
* twice as much memory installed. (4MB on the 5434)
*/
if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
mem *= 2;
}
/* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
return mem;
}
static void get_pci_addrs(const struct pci_dev *pdev,
unsigned long *display, unsigned long *registers)
{
assert(pdev != NULL);
assert(display != NULL);
assert(registers != NULL);
*display = 0;
*registers = 0;
/* This is a best-guess for now */
if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
*display = pci_resource_start(pdev, 1);
*registers = pci_resource_start(pdev, 0);
} else {
*display = pci_resource_start(pdev, 0);
*registers = pci_resource_start(pdev, 1);
}
assert(*display != 0);
}
static void cirrusfb_pci_unmap(struct fb_info *info)
{
struct pci_dev *pdev = to_pci_dev(info->device);
struct cirrusfb_info *cinfo = info->par;
if (cinfo->laguna_mmio == NULL)
iounmap(cinfo->laguna_mmio);
iounmap(info->screen_base);
#if 0 /* if system didn't claim this region, we would... */
release_mem_region(0xA0000, 65535);
#endif
if (release_io_ports)
release_region(0x3C0, 32);
pci_release_regions(pdev);
}
#endif /* CONFIG_PCI */
#ifdef CONFIG_ZORRO
static void cirrusfb_zorro_unmap(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
struct zorro_dev *zdev = to_zorro_dev(info->device);
if (info->fix.smem_start > 16 * MB_)
iounmap(info->screen_base);
if (info->fix.mmio_start > 16 * MB_)
iounmap(cinfo->regbase);
zorro_release_device(zdev);
}
#endif /* CONFIG_ZORRO */
/* function table of the above functions */
static const struct fb_ops cirrusfb_ops = {
.owner = THIS_MODULE,
.fb_open = cirrusfb_open,
.fb_release = cirrusfb_release,
.fb_setcolreg = cirrusfb_setcolreg,
.fb_check_var = cirrusfb_check_var,
.fb_set_par = cirrusfb_set_par,
.fb_pan_display = cirrusfb_pan_display,
.fb_blank = cirrusfb_blank,
.fb_fillrect = cirrusfb_fillrect,
.fb_copyarea = cirrusfb_copyarea,
.fb_sync = cirrusfb_sync,
.fb_imageblit = cirrusfb_imageblit,
};
static int cirrusfb_set_fbinfo(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
struct fb_var_screeninfo *var = &info->var;
info->pseudo_palette = cinfo->pseudo_palette;
info->flags = FBINFO_HWACCEL_XPAN
| FBINFO_HWACCEL_YPAN
| FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_IMAGEBLIT
| FBINFO_HWACCEL_COPYAREA;
if (noaccel || is_laguna(cinfo)) {
info->flags |= FBINFO_HWACCEL_DISABLED;
info->fix.accel = FB_ACCEL_NONE;
} else
info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
info->fbops = &cirrusfb_ops;
if (cinfo->btype == BT_GD5480) {
if (var->bits_per_pixel == 16)
info->screen_base += 1 * MB_;
if (var->bits_per_pixel == 32)
info->screen_base += 2 * MB_;
}
/* Fill fix common fields */
strscpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
sizeof(info->fix.id));
/* monochrome: only 1 memory plane */
/* 8 bit and above: Use whole memory area */
info->fix.smem_len = info->screen_size;
if (var->bits_per_pixel == 1)
info->fix.smem_len /= 4;
info->fix.type_aux = 0;
info->fix.xpanstep = 1;
info->fix.ypanstep = 1;
info->fix.ywrapstep = 0;
/* FIXME: map region at 0xB8000 if available, fill in here */
info->fix.mmio_len = 0;
fb_alloc_cmap(&info->cmap, 256, 0);
return 0;
}
static int cirrusfb_register(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
int err;
/* sanity checks */
assert(cinfo->btype != BT_NONE);
/* set all the vital stuff */
cirrusfb_set_fbinfo(info);
dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
if (!err) {
dev_dbg(info->device, "wrong initial video mode\n");
err = -EINVAL;
goto err_dealloc_cmap;
}
info->var.activate = FB_ACTIVATE_NOW;
err = cirrusfb_check_var(&info->var, info);
if (err < 0) {
/* should never happen */
dev_dbg(info->device,
"choking on default var... umm, no good.\n");
goto err_dealloc_cmap;
}
err = register_framebuffer(info);
if (err < 0) {
dev_err(info->device,
"could not register fb device; err = %d!\n", err);
goto err_dealloc_cmap;
}
return 0;
err_dealloc_cmap:
fb_dealloc_cmap(&info->cmap);
return err;
}
static void cirrusfb_cleanup(struct fb_info *info)
{
struct cirrusfb_info *cinfo = info->par;
switch_monitor(cinfo, 0);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
dev_dbg(info->device, "Framebuffer unregistered\n");
cinfo->unmap(info);
framebuffer_release(info);
}
#ifdef CONFIG_PCI
static int cirrusfb_pci_register(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct cirrusfb_info *cinfo;
struct fb_info *info;
unsigned long board_addr, board_size;
int ret;
ret = aperture_remove_conflicting_pci_devices(pdev, "cirrusfb");
if (ret)
return ret;
ret = pci_enable_device(pdev);
if (ret < 0) {
printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
goto err_out;
}
info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
if (!info) {
ret = -ENOMEM;
goto err_out;
}
cinfo = info->par;
cinfo->btype = (enum cirrus_board) ent->driver_data;
dev_dbg(info->device,
" Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
(unsigned long long)pdev->resource[0].start, cinfo->btype);
dev_dbg(info->device, " base address 1 is 0x%Lx\n",
(unsigned long long)pdev->resource[1].start);
dev_dbg(info->device,
"Attempt to get PCI info for Cirrus Graphics Card\n");
get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
/* FIXME: this forces VGA. alternatives? */
cinfo->regbase = NULL;
cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
board_addr, info->fix.mmio_start);
board_size = (cinfo->btype == BT_GD5480) ?
32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
ret = pci_request_regions(pdev, "cirrusfb");
if (ret < 0) {
dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
board_addr);
goto err_release_fb;
}
#if 0 /* if the system didn't claim this region, we would... */
if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
0xA0000L);
ret = -EBUSY;
goto err_release_regions;
}
#endif
if (request_region(0x3C0, 32, "cirrusfb"))
release_io_ports = 1;
info->screen_base = ioremap(board_addr, board_size);
if (!info->screen_base) {
ret = -EIO;
goto err_release_legacy;
}
info->fix.smem_start = board_addr;
info->screen_size = board_size;
cinfo->unmap = cirrusfb_pci_unmap;
dev_info(info->device,
"Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
info->screen_size >> 10, board_addr);
pci_set_drvdata(pdev, info);
ret = cirrusfb_register(info);
if (!ret)
return 0;
iounmap(info->screen_base);
err_release_legacy:
if (release_io_ports)
release_region(0x3C0, 32);
#if 0
release_mem_region(0xA0000, 65535);
err_release_regions:
#endif
pci_release_regions(pdev);
err_release_fb:
if (cinfo->laguna_mmio != NULL)
iounmap(cinfo->laguna_mmio);
framebuffer_release(info);
err_out:
return ret;
}
static void cirrusfb_pci_unregister(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
cirrusfb_cleanup(info);
}
static struct pci_driver cirrusfb_pci_driver = {
.name = "cirrusfb",
.id_table = cirrusfb_pci_table,
.probe = cirrusfb_pci_register,
.remove = cirrusfb_pci_unregister,
};
#endif /* CONFIG_PCI */
#ifdef CONFIG_ZORRO
static int cirrusfb_zorro_register(struct zorro_dev *z,
const struct zorro_device_id *ent)
{
struct fb_info *info;
int error;
const struct zorrocl *zcl;
enum cirrus_board btype;
unsigned long regbase, ramsize, rambase;
struct cirrusfb_info *cinfo;
info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
if (!info)
return -ENOMEM;
zcl = (const struct zorrocl *)ent->driver_data;
btype = zcl->type;
regbase = zorro_resource_start(z) + zcl->regoffset;
ramsize = zcl->ramsize;
if (ramsize) {
rambase = zorro_resource_start(z) + zcl->ramoffset;
if (zorro_resource_len(z) == 64 * MB_) {
/* Quirk for 64 MiB Picasso IV */
rambase += zcl->ramoffset;
}
} else {
struct zorro_dev *ram = zorro_find_device(zcl->ramid, NULL);
if (!ram || !zorro_resource_len(ram)) {
dev_err(info->device, "No video RAM found\n");
error = -ENODEV;
goto err_release_fb;
}
rambase = zorro_resource_start(ram);
ramsize = zorro_resource_len(ram);
if (zcl->ramid2 &&
(ram = zorro_find_device(zcl->ramid2, NULL))) {
if (zorro_resource_start(ram) != rambase + ramsize) {
dev_warn(info->device,
"Skipping non-contiguous RAM at %pR\n",
&ram->resource);
} else {
ramsize += zorro_resource_len(ram);
}
}
}
dev_info(info->device,
"%s board detected, REG at 0x%lx, %lu MiB RAM at 0x%lx\n",
cirrusfb_board_info[btype].name, regbase, ramsize / MB_,
rambase);
if (!zorro_request_device(z, "cirrusfb")) {
dev_err(info->device, "Cannot reserve %pR\n", &z->resource);
error = -EBUSY;
goto err_release_fb;
}
cinfo = info->par;
cinfo->btype = btype;
info->fix.mmio_start = regbase;
cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)
: ZTWO_VADDR(regbase);
if (!cinfo->regbase) {
dev_err(info->device, "Cannot map registers\n");
error = -EIO;
goto err_release_dev;
}
info->fix.smem_start = rambase;
info->screen_size = ramsize;
info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize)
: ZTWO_VADDR(rambase);
if (!info->screen_base) {
dev_err(info->device, "Cannot map video RAM\n");
error = -EIO;
goto err_unmap_reg;
}
cinfo->unmap = cirrusfb_zorro_unmap;
dev_info(info->device,
"Cirrus Logic chipset on Zorro bus, RAM (%lu MiB) at 0x%lx\n",
ramsize / MB_, rambase);
/* MCLK select etc. */
if (cirrusfb_board_info[btype].init_sr1f)
vga_wseq(cinfo->regbase, CL_SEQR1F,
cirrusfb_board_info[btype].sr1f);
error = cirrusfb_register(info);
if (error) {
dev_err(info->device, "Failed to register device, error %d\n",
error);
goto err_unmap_ram;
}
zorro_set_drvdata(z, info);
return 0;
err_unmap_ram:
if (rambase > 16 * MB_)
iounmap(info->screen_base);
err_unmap_reg:
if (regbase > 16 * MB_)
iounmap(cinfo->regbase);
err_release_dev:
zorro_release_device(z);
err_release_fb:
framebuffer_release(info);
return error;
}
static void cirrusfb_zorro_unregister(struct zorro_dev *z)
{
struct fb_info *info = zorro_get_drvdata(z);
cirrusfb_cleanup(info);
zorro_set_drvdata(z, NULL);
}
static struct zorro_driver cirrusfb_zorro_driver = {
.name = "cirrusfb",
.id_table = cirrusfb_zorro_table,
.probe = cirrusfb_zorro_register,
.remove = cirrusfb_zorro_unregister,
};
#endif /* CONFIG_ZORRO */
#ifndef MODULE
static int __init cirrusfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strcmp(this_opt, "noaccel"))
noaccel = 1;
else if (!strncmp(this_opt, "mode:", 5))
mode_option = this_opt + 5;
else
mode_option = this_opt;
}
return 0;
}
#endif
/*
* Modularization
*/
MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <[email protected]>");
MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
MODULE_LICENSE("GPL");
static int __init cirrusfb_init(void)
{
int error = 0;
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("cirrusfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("cirrusfb", &option))
return -ENODEV;
cirrusfb_setup(option);
#endif
#ifdef CONFIG_ZORRO
error |= zorro_register_driver(&cirrusfb_zorro_driver);
#endif
#ifdef CONFIG_PCI
error |= pci_register_driver(&cirrusfb_pci_driver);
#endif
return error;
}
static void __exit cirrusfb_exit(void)
{
#ifdef CONFIG_PCI
pci_unregister_driver(&cirrusfb_pci_driver);
#endif
#ifdef CONFIG_ZORRO
zorro_unregister_driver(&cirrusfb_zorro_driver);
#endif
}
module_init(cirrusfb_init);
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
module_param(noaccel, bool, 0);
MODULE_PARM_DESC(noaccel, "Disable acceleration");
#ifdef MODULE
module_exit(cirrusfb_exit);
#endif
/**********************************************************************/
/* about the following functions - I have used the same names for the */
/* functions as Markus Wild did in his Retina driver for NetBSD as */
/* they just made sense for this purpose. Apart from that, I wrote */
/* these functions myself. */
/**********************************************************************/
/*** WGen() - write into one of the external/general registers ***/
static void WGen(const struct cirrusfb_info *cinfo,
int regnum, unsigned char val)
{
unsigned long regofs = 0;
if (cinfo->btype == BT_PICASSO) {
/* Picasso II specific hack */
/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
regnum == CL_VSSM2) */
if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
regofs = 0xfff;
}
vga_w(cinfo->regbase, regofs + regnum, val);
}
/*** RGen() - read out one of the external/general registers ***/
static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
{
unsigned long regofs = 0;
if (cinfo->btype == BT_PICASSO) {
/* Picasso II specific hack */
/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
regnum == CL_VSSM2) */
if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
regofs = 0xfff;
}
return vga_r(cinfo->regbase, regofs + regnum);
}
/*** AttrOn() - turn on VideoEnable for Attribute controller ***/
static void AttrOn(const struct cirrusfb_info *cinfo)
{
assert(cinfo != NULL);
if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
/* if we're just in "write value" mode, write back the */
/* same value as before to not modify anything */
vga_w(cinfo->regbase, VGA_ATT_IW,
vga_r(cinfo->regbase, VGA_ATT_R));
}
/* turn on video bit */
/* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
/* dummy write on Reg0 to be on "write index" mode next time */
vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
}
/*** WHDR() - write into the Hidden DAC register ***/
/* as the HDR is the only extension register that requires special treatment
* (the other extension registers are accessible just like the "ordinary"
* registers of their functional group) here is a specialized routine for
* accessing the HDR
*/
static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
{
if (is_laguna(cinfo))
return;
if (cinfo->btype == BT_PICASSO) {
/* Klaus' hint for correct access to HDR on some boards */
/* first write 0 to pixel mask (3c6) */
WGen(cinfo, VGA_PEL_MSK, 0x00);
udelay(200);
/* next read dummy from pixel address (3c8) */
RGen(cinfo, VGA_PEL_IW);
udelay(200);
}
/* now do the usual stuff to access the HDR */
RGen(cinfo, VGA_PEL_MSK);
udelay(200);
RGen(cinfo, VGA_PEL_MSK);
udelay(200);
RGen(cinfo, VGA_PEL_MSK);
udelay(200);
RGen(cinfo, VGA_PEL_MSK);
udelay(200);
WGen(cinfo, VGA_PEL_MSK, val);
udelay(200);
if (cinfo->btype == BT_PICASSO) {
/* now first reset HDR access counter */
RGen(cinfo, VGA_PEL_IW);
udelay(200);
/* and at the end, restore the mask value */
/* ## is this mask always 0xff? */
WGen(cinfo, VGA_PEL_MSK, 0xff);
udelay(200);
}
}
/*** WSFR() - write to the "special function register" (SFR) ***/
static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
{
#ifdef CONFIG_ZORRO
assert(cinfo->regbase != NULL);
cinfo->SFR = val;
z_writeb(val, cinfo->regbase + 0x8000);
#endif
}
/* The Picasso has a second register for switching the monitor bit */
static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
{
#ifdef CONFIG_ZORRO
/* writing an arbitrary value to this one causes the monitor switcher */
/* to flip to Amiga display */
assert(cinfo->regbase != NULL);
cinfo->SFR = val;
z_writeb(val, cinfo->regbase + 0x9000);
#endif
}
/*** WClut - set CLUT entry (range: 0..63) ***/
static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
unsigned char green, unsigned char blue)
{
unsigned int data = VGA_PEL_D;
/* address write mode register is not translated.. */
vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
/* but DAC data register IS, at least for Picasso II */
if (cinfo->btype == BT_PICASSO)
data += 0xfff;
vga_w(cinfo->regbase, data, red);
vga_w(cinfo->regbase, data, green);
vga_w(cinfo->regbase, data, blue);
} else {
vga_w(cinfo->regbase, data, blue);
vga_w(cinfo->regbase, data, green);
vga_w(cinfo->regbase, data, red);
}
}
#if 0
/*** RClut - read CLUT entry (range 0..63) ***/
static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
unsigned char *green, unsigned char *blue)
{
unsigned int data = VGA_PEL_D;
vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
if (cinfo->btype == BT_PICASSO)
data += 0xfff;
*red = vga_r(cinfo->regbase, data);
*green = vga_r(cinfo->regbase, data);
*blue = vga_r(cinfo->regbase, data);
} else {
*blue = vga_r(cinfo->regbase, data);
*green = vga_r(cinfo->regbase, data);
*red = vga_r(cinfo->regbase, data);
}
}
#endif
/*******************************************************************
cirrusfb_WaitBLT()
Wait for the BitBLT engine to complete a possible earlier job
*********************************************************************/
/* FIXME: use interrupts instead */
static void cirrusfb_WaitBLT(u8 __iomem *regbase)
{
while (vga_rgfx(regbase, CL_GR31) & 0x08)
cpu_relax();
}
/*******************************************************************
cirrusfb_BitBLT()
perform accelerated "scrolling"
********************************************************************/
static void cirrusfb_set_blitter(u8 __iomem *regbase,
u_short nwidth, u_short nheight,
u_long nsrc, u_long ndest,
u_short bltmode, u_short line_length)
{
/* pitch: set to line_length */
/* dest pitch low */
vga_wgfx(regbase, CL_GR24, line_length & 0xff);
/* dest pitch hi */
vga_wgfx(regbase, CL_GR25, line_length >> 8);
/* source pitch low */
vga_wgfx(regbase, CL_GR26, line_length & 0xff);
/* source pitch hi */
vga_wgfx(regbase, CL_GR27, line_length >> 8);
/* BLT width: actual number of pixels - 1 */
/* BLT width low */
vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
/* BLT width hi */
vga_wgfx(regbase, CL_GR21, nwidth >> 8);
/* BLT height: actual number of lines -1 */
/* BLT height low */
vga_wgfx(regbase, CL_GR22, nheight & 0xff);
/* BLT width hi */
vga_wgfx(regbase, CL_GR23, nheight >> 8);
/* BLT destination */
/* BLT dest low */
vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
/* BLT dest mid */
vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
/* BLT dest hi */
vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
/* BLT source */
/* BLT src low */
vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
/* BLT src mid */
vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
/* BLT src hi */
vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
/* BLT mode */
vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
/* BLT ROP: SrcCopy */
vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
/* and finally: GO! */
vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
}
/*******************************************************************
cirrusfb_BitBLT()
perform accelerated "scrolling"
********************************************************************/
static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
u_short curx, u_short cury,
u_short destx, u_short desty,
u_short width, u_short height,
u_short line_length)
{
u_short nwidth = width - 1;
u_short nheight = height - 1;
u_long nsrc, ndest;
u_char bltmode;
bltmode = 0x00;
/* if source adr < dest addr, do the Blt backwards */
if (cury <= desty) {
if (cury == desty) {
/* if src and dest are on the same line, check x */
if (curx < destx)
bltmode |= 0x01;
} else
bltmode |= 0x01;
}
/* standard case: forward blitting */
nsrc = (cury * line_length) + curx;
ndest = (desty * line_length) + destx;
if (bltmode) {
/* this means start addresses are at the end,
* counting backwards
*/
nsrc += nheight * line_length + nwidth;
ndest += nheight * line_length + nwidth;
}
cirrusfb_WaitBLT(regbase);
cirrusfb_set_blitter(regbase, nwidth, nheight,
nsrc, ndest, bltmode, line_length);
}
/*******************************************************************
cirrusfb_RectFill()
perform accelerated rectangle fill
********************************************************************/
static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
u_short x, u_short y, u_short width, u_short height,
u32 fg_color, u32 bg_color, u_short line_length,
u_char blitmode)
{
u_long ndest = (y * line_length) + x;
u_char op;
cirrusfb_WaitBLT(regbase);
/* This is a ColorExpand Blt, using the */
/* same color for foreground and background */
vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
op = 0x80;
if (bits_per_pixel >= 16) {
vga_wgfx(regbase, CL_GR10, bg_color >> 8);
vga_wgfx(regbase, CL_GR11, fg_color >> 8);
op = 0x90;
}
if (bits_per_pixel >= 24) {
vga_wgfx(regbase, CL_GR12, bg_color >> 16);
vga_wgfx(regbase, CL_GR13, fg_color >> 16);
op = 0xa0;
}
if (bits_per_pixel == 32) {
vga_wgfx(regbase, CL_GR14, bg_color >> 24);
vga_wgfx(regbase, CL_GR15, fg_color >> 24);
op = 0xb0;
}
cirrusfb_set_blitter(regbase, width - 1, height - 1,
0, ndest, op | blitmode, line_length);
}
/**************************************************************************
* bestclock() - determine closest possible clock lower(?) than the
* desired pixel clock
**************************************************************************/
static void bestclock(long freq, int *nom, int *den, int *div)
{
int n, d;
long h, diff;
assert(nom != NULL);
assert(den != NULL);
assert(div != NULL);
*nom = 0;
*den = 0;
*div = 0;
if (freq < 8000)
freq = 8000;
diff = freq;
for (n = 32; n < 128; n++) {
int s = 0;
d = (14318 * n) / freq;
if ((d >= 7) && (d <= 63)) {
int temp = d;
if (temp > 31) {
s = 1;
temp >>= 1;
}
h = ((14318 * n) / temp) >> s;
h = h > freq ? h - freq : freq - h;
if (h < diff) {
diff = h;
*nom = n;
*den = temp;
*div = s;
}
}
d++;
if ((d >= 7) && (d <= 63)) {
if (d > 31) {
s = 1;
d >>= 1;
}
h = ((14318 * n) / d) >> s;
h = h > freq ? h - freq : freq - h;
if (h < diff) {
diff = h;
*nom = n;
*den = d;
*div = s;
}
}
}
}
/* -------------------------------------------------------------------------
*
* debugging functions
*
* -------------------------------------------------------------------------
*/
#ifdef CIRRUSFB_DEBUG
/*
* cirrusfb_dbg_print_regs
* @regbase: If using newmmio, the newmmio base address, otherwise %NULL
* @reg_class: type of registers to read: %CRT, or %SEQ
*
* DESCRIPTION:
* Dumps the given list of VGA CRTC registers. If @base is %NULL,
* old-style I/O ports are queried for information, otherwise MMIO is
* used at the given @base address to query the information.
*/
static void cirrusfb_dbg_print_regs(struct fb_info *info,
caddr_t regbase,
enum cirrusfb_dbg_reg_class reg_class, ...)
{
va_list list;
unsigned char val = 0;
unsigned reg;
char *name;
va_start(list, reg_class);
name = va_arg(list, char *);
while (name != NULL) {
reg = va_arg(list, int);
switch (reg_class) {
case CRT:
val = vga_rcrt(regbase, (unsigned char) reg);
break;
case SEQ:
val = vga_rseq(regbase, (unsigned char) reg);
break;
default:
/* should never occur */
assert(false);
break;
}
dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
name = va_arg(list, char *);
}
va_end(list);
}
/*
* cirrusfb_dbg_reg_dump
* @base: If using newmmio, the newmmio base address, otherwise %NULL
*
* DESCRIPTION:
* Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
* old-style I/O ports are queried for information, otherwise MMIO is
* used at the given @base address to query the information.
*/
static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
{
dev_dbg(info->device, "VGA CRTC register dump:\n");
cirrusfb_dbg_print_regs(info, regbase, CRT,
"CR00", 0x00,
"CR01", 0x01,
"CR02", 0x02,
"CR03", 0x03,
"CR04", 0x04,
"CR05", 0x05,
"CR06", 0x06,
"CR07", 0x07,
"CR08", 0x08,
"CR09", 0x09,
"CR0A", 0x0A,
"CR0B", 0x0B,
"CR0C", 0x0C,
"CR0D", 0x0D,
"CR0E", 0x0E,
"CR0F", 0x0F,
"CR10", 0x10,
"CR11", 0x11,
"CR12", 0x12,
"CR13", 0x13,
"CR14", 0x14,
"CR15", 0x15,
"CR16", 0x16,
"CR17", 0x17,
"CR18", 0x18,
"CR22", 0x22,
"CR24", 0x24,
"CR26", 0x26,
"CR2D", 0x2D,
"CR2E", 0x2E,
"CR2F", 0x2F,
"CR30", 0x30,
"CR31", 0x31,
"CR32", 0x32,
"CR33", 0x33,
"CR34", 0x34,
"CR35", 0x35,
"CR36", 0x36,
"CR37", 0x37,
"CR38", 0x38,
"CR39", 0x39,
"CR3A", 0x3A,
"CR3B", 0x3B,
"CR3C", 0x3C,
"CR3D", 0x3D,
"CR3E", 0x3E,
"CR3F", 0x3F,
NULL);
dev_dbg(info->device, "\n");
dev_dbg(info->device, "VGA SEQ register dump:\n");
cirrusfb_dbg_print_regs(info, regbase, SEQ,
"SR00", 0x00,
"SR01", 0x01,
"SR02", 0x02,
"SR03", 0x03,
"SR04", 0x04,
"SR08", 0x08,
"SR09", 0x09,
"SR0A", 0x0A,
"SR0B", 0x0B,
"SR0D", 0x0D,
"SR10", 0x10,
"SR11", 0x11,
"SR12", 0x12,
"SR13", 0x13,
"SR14", 0x14,
"SR15", 0x15,
"SR16", 0x16,
"SR17", 0x17,
"SR18", 0x18,
"SR19", 0x19,
"SR1A", 0x1A,
"SR1B", 0x1B,
"SR1C", 0x1C,
"SR1D", 0x1D,
"SR1E", 0x1E,
"SR1F", 0x1F,
NULL);
dev_dbg(info->device, "\n");
}
#endif /* CIRRUSFB_DEBUG */
| linux-master | drivers/video/fbdev/cirrusfb.c |
/*
* Freescale i.MX Frame Buffer device driver
*
* Copyright (C) 2004 Sascha Hauer, Pengutronix
* Based on acornfb.c Copyright (C) Russell King.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Please direct your questions and comments on this driver to the following
* email address:
*
* [email protected]
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/lcd.h>
#include <linux/math64.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regulator/consumer.h>
#include <video/of_display_timing.h>
#include <video/of_videomode.h>
#include <video/videomode.h>
#define PCR_TFT (1 << 31)
#define PCR_BPIX_8 (3 << 25)
#define PCR_BPIX_12 (4 << 25)
#define PCR_BPIX_16 (5 << 25)
#define PCR_BPIX_18 (6 << 25)
struct imx_fb_videomode {
struct fb_videomode mode;
u32 pcr;
bool aus_mode;
unsigned char bpp;
};
/*
* Complain if VAR is out of range.
*/
#define DEBUG_VAR 1
#define DRIVER_NAME "imx-fb"
#define LCDC_SSA 0x00
#define LCDC_SIZE 0x04
#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
#define YMAX_MASK_IMX1 0x1ff
#define YMAX_MASK_IMX21 0x3ff
#define LCDC_VPW 0x08
#define VPW_VPW(x) ((x) & 0x3ff)
#define LCDC_CPOS 0x0C
#define CPOS_CC1 (1<<31)
#define CPOS_CC0 (1<<30)
#define CPOS_OP (1<<28)
#define CPOS_CXP(x) (((x) & 3ff) << 16)
#define LCDC_LCWHB 0x10
#define LCWHB_BK_EN (1<<31)
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
#define LCWHB_CH(h) (((h) & 0x1f) << 16)
#define LCWHB_BD(x) ((x) & 0xff)
#define LCDC_LCHCC 0x14
#define LCDC_PCR 0x18
#define LCDC_HCR 0x1C
#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
#define HCR_H_WAIT_2(x) ((x) & 0xff)
#define LCDC_VCR 0x20
#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
#define VCR_V_WAIT_2(x) ((x) & 0xff)
#define LCDC_POS 0x24
#define POS_POS(x) ((x) & 1f)
#define LCDC_LSCR1 0x28
/* bit fields in imxfb.h */
#define LCDC_PWMR 0x2C
/* bit fields in imxfb.h */
#define LCDC_DMACR 0x30
/* bit fields in imxfb.h */
#define LCDC_RMCR 0x34
#define RMCR_LCDC_EN_MX1 (1<<1)
#define RMCR_SELF_REF (1<<0)
#define LCDC_LCDICR 0x38
#define LCDICR_INT_SYN (1<<2)
#define LCDICR_INT_CON (1)
#define LCDC_LCDISR 0x40
#define LCDISR_UDR_ERR (1<<3)
#define LCDISR_ERR_RES (1<<2)
#define LCDISR_EOF (1<<1)
#define LCDISR_BOF (1<<0)
#define IMXFB_LSCR1_DEFAULT 0x00120300
#define LCDC_LAUSCR 0x80
#define LAUSCR_AUS_MODE (1<<31)
/* Used fb-mode. Can be set on kernel command line, therefore file-static. */
static const char *fb_mode;
/*
* These are the bitfields for each
* display depth that we support.
*/
struct imxfb_rgb {
struct fb_bitfield red;
struct fb_bitfield green;
struct fb_bitfield blue;
struct fb_bitfield transp;
};
enum imxfb_type {
IMX1_FB,
IMX21_FB,
};
struct imxfb_info {
struct platform_device *pdev;
void __iomem *regs;
struct clk *clk_ipg;
struct clk *clk_ahb;
struct clk *clk_per;
enum imxfb_type devtype;
bool enabled;
/*
* These are the addresses we mapped
* the framebuffer memory region to.
*/
dma_addr_t map_dma;
u_int map_size;
u_int palette_size;
dma_addr_t dbar1;
dma_addr_t dbar2;
u_int pcr;
u_int lauscr;
u_int pwmr;
u_int lscr1;
u_int dmacr;
bool cmap_inverse;
bool cmap_static;
struct imx_fb_videomode *mode;
int num_modes;
struct regulator *lcd_pwr;
int lcd_pwr_enabled;
};
static const struct platform_device_id imxfb_devtype[] = {
{
.name = "imx1-fb",
.driver_data = IMX1_FB,
}, {
.name = "imx21-fb",
.driver_data = IMX21_FB,
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(platform, imxfb_devtype);
static const struct of_device_id imxfb_of_dev_id[] = {
{
.compatible = "fsl,imx1-fb",
.data = &imxfb_devtype[IMX1_FB],
}, {
.compatible = "fsl,imx21-fb",
.data = &imxfb_devtype[IMX21_FB],
}, {
/* sentinel */
}
};
MODULE_DEVICE_TABLE(of, imxfb_of_dev_id);
static inline int is_imx1_fb(struct imxfb_info *fbi)
{
return fbi->devtype == IMX1_FB;
}
#define IMX_NAME "IMX"
/*
* Minimum X and Y resolutions
*/
#define MIN_XRES 64
#define MIN_YRES 64
/* Actually this really is 18bit support, the lowest 2 bits of each colour
* are unused in hardware. We claim to have 24bit support to make software
* like X work, which does not support 18bit.
*/
static struct imxfb_rgb def_rgb_18 = {
.red = {.offset = 16, .length = 8,},
.green = {.offset = 8, .length = 8,},
.blue = {.offset = 0, .length = 8,},
.transp = {.offset = 0, .length = 0,},
};
static struct imxfb_rgb def_rgb_16_tft = {
.red = {.offset = 11, .length = 5,},
.green = {.offset = 5, .length = 6,},
.blue = {.offset = 0, .length = 5,},
.transp = {.offset = 0, .length = 0,},
};
static struct imxfb_rgb def_rgb_16_stn = {
.red = {.offset = 8, .length = 4,},
.green = {.offset = 4, .length = 4,},
.blue = {.offset = 0, .length = 4,},
.transp = {.offset = 0, .length = 0,},
};
static struct imxfb_rgb def_rgb_8 = {
.red = {.offset = 0, .length = 8,},
.green = {.offset = 0, .length = 8,},
.blue = {.offset = 0, .length = 8,},
.transp = {.offset = 0, .length = 0,},
};
static int imxfb_activate_var(struct fb_var_screeninfo *var,
struct fb_info *info);
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
u_int val, ret = 1;
#define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
if (regno < fbi->palette_size) {
val = (CNVT_TOHW(red, 4) << 8) |
(CNVT_TOHW(green,4) << 4) |
CNVT_TOHW(blue, 4);
writel(val, fbi->regs + 0x800 + (regno << 2));
ret = 0;
}
return ret;
}
static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
unsigned int val;
int ret = 1;
/*
* If inverse mode was selected, invert all the colours
* rather than the register number. The register number
* is what you poke into the framebuffer to produce the
* colour you requested.
*/
if (fbi->cmap_inverse) {
red = 0xffff - red;
green = 0xffff - green;
blue = 0xffff - blue;
}
/*
* If greyscale is true, then we convert the RGB value
* to greyscale no mater what visual we are using.
*/
if (info->var.grayscale)
red = green = blue = (19595 * red + 38470 * green +
7471 * blue) >> 16;
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
/*
* 12 or 16-bit True Colour. We encode the RGB value
* according to the RGB bitfield information.
*/
if (regno < 16) {
u32 *pal = info->pseudo_palette;
val = chan_to_field(red, &info->var.red);
val |= chan_to_field(green, &info->var.green);
val |= chan_to_field(blue, &info->var.blue);
pal[regno] = val;
ret = 0;
}
break;
case FB_VISUAL_STATIC_PSEUDOCOLOR:
case FB_VISUAL_PSEUDOCOLOR:
ret = imxfb_setpalettereg(regno, red, green, blue, trans, info);
break;
}
return ret;
}
static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi)
{
struct imx_fb_videomode *m;
int i;
if (!fb_mode)
return &fbi->mode[0];
for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) {
if (!strcmp(m->mode.name, fb_mode))
return m;
}
return NULL;
}
/*
* imxfb_check_var():
* Round up in the following order: bits_per_pixel, xres,
* yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
* bitfields, horizontal timing, vertical timing.
*/
static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
struct imxfb_rgb *rgb;
const struct imx_fb_videomode *imxfb_mode;
unsigned long lcd_clk;
unsigned long long tmp;
u32 pcr = 0;
if (var->xres < MIN_XRES)
var->xres = MIN_XRES;
if (var->yres < MIN_YRES)
var->yres = MIN_YRES;
imxfb_mode = imxfb_find_mode(fbi);
if (!imxfb_mode)
return -EINVAL;
var->xres = imxfb_mode->mode.xres;
var->yres = imxfb_mode->mode.yres;
var->bits_per_pixel = imxfb_mode->bpp;
var->pixclock = imxfb_mode->mode.pixclock;
var->hsync_len = imxfb_mode->mode.hsync_len;
var->left_margin = imxfb_mode->mode.left_margin;
var->right_margin = imxfb_mode->mode.right_margin;
var->vsync_len = imxfb_mode->mode.vsync_len;
var->upper_margin = imxfb_mode->mode.upper_margin;
var->lower_margin = imxfb_mode->mode.lower_margin;
var->sync = imxfb_mode->mode.sync;
var->xres_virtual = max(var->xres_virtual, var->xres);
var->yres_virtual = max(var->yres_virtual, var->yres);
pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
lcd_clk = clk_get_rate(fbi->clk_per);
tmp = var->pixclock * (unsigned long long)lcd_clk;
do_div(tmp, 1000000);
if (do_div(tmp, 1000000) > 500000)
tmp++;
pcr = (unsigned int)tmp;
if (--pcr > 0x3F) {
pcr = 0x3F;
printk(KERN_WARNING "Must limit pixel clock to %luHz\n",
lcd_clk / pcr);
}
switch (var->bits_per_pixel) {
case 32:
pcr |= PCR_BPIX_18;
rgb = &def_rgb_18;
break;
case 16:
default:
if (is_imx1_fb(fbi))
pcr |= PCR_BPIX_12;
else
pcr |= PCR_BPIX_16;
if (imxfb_mode->pcr & PCR_TFT)
rgb = &def_rgb_16_tft;
else
rgb = &def_rgb_16_stn;
break;
case 8:
pcr |= PCR_BPIX_8;
rgb = &def_rgb_8;
break;
}
/* add sync polarities */
pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25));
fbi->pcr = pcr;
/*
* The LCDC AUS Mode Control Register does not exist on imx1.
*/
if (!is_imx1_fb(fbi) && imxfb_mode->aus_mode)
fbi->lauscr = LAUSCR_AUS_MODE;
/*
* Copy the RGB parameters for this display
* from the machine specific parameters.
*/
var->red = rgb->red;
var->green = rgb->green;
var->blue = rgb->blue;
var->transp = rgb->transp;
pr_debug("RGBT length = %d:%d:%d:%d\n",
var->red.length, var->green.length, var->blue.length,
var->transp.length);
pr_debug("RGBT offset = %d:%d:%d:%d\n",
var->red.offset, var->green.offset, var->blue.offset,
var->transp.offset);
return 0;
}
/*
* imxfb_set_par():
* Set the user defined part of the display for the specified console
*/
static int imxfb_set_par(struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
struct fb_var_screeninfo *var = &info->var;
if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32)
info->fix.visual = FB_VISUAL_TRUECOLOR;
else if (!fbi->cmap_static)
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
else {
/*
* Some people have weird ideas about wanting static
* pseudocolor maps. I suspect their user space
* applications are broken.
*/
info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
}
info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
imxfb_activate_var(var, info);
return 0;
}
static int imxfb_enable_controller(struct imxfb_info *fbi)
{
int ret;
if (fbi->enabled)
return 0;
pr_debug("Enabling LCD controller\n");
writel(fbi->map_dma, fbi->regs + LCDC_SSA);
/* panning offset 0 (0 pixel offset) */
writel(0x00000000, fbi->regs + LCDC_POS);
/* disable hardware cursor */
writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
fbi->regs + LCDC_CPOS);
/*
* RMCR_LCDC_EN_MX1 is present on i.MX1 only, but doesn't hurt
* on other SoCs
*/
writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR);
ret = clk_prepare_enable(fbi->clk_ipg);
if (ret)
goto err_enable_ipg;
ret = clk_prepare_enable(fbi->clk_ahb);
if (ret)
goto err_enable_ahb;
ret = clk_prepare_enable(fbi->clk_per);
if (ret)
goto err_enable_per;
fbi->enabled = true;
return 0;
err_enable_per:
clk_disable_unprepare(fbi->clk_ahb);
err_enable_ahb:
clk_disable_unprepare(fbi->clk_ipg);
err_enable_ipg:
writel(0, fbi->regs + LCDC_RMCR);
return ret;
}
static void imxfb_disable_controller(struct imxfb_info *fbi)
{
if (!fbi->enabled)
return;
pr_debug("Disabling LCD controller\n");
clk_disable_unprepare(fbi->clk_per);
clk_disable_unprepare(fbi->clk_ahb);
clk_disable_unprepare(fbi->clk_ipg);
fbi->enabled = false;
writel(0, fbi->regs + LCDC_RMCR);
}
static int imxfb_blank(int blank, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
pr_debug("imxfb_blank: blank=%d\n", blank);
switch (blank) {
case FB_BLANK_POWERDOWN:
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
case FB_BLANK_NORMAL:
imxfb_disable_controller(fbi);
break;
case FB_BLANK_UNBLANK:
return imxfb_enable_controller(fbi);
}
return 0;
}
static const struct fb_ops imxfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = imxfb_check_var,
.fb_set_par = imxfb_set_par,
.fb_setcolreg = imxfb_setcolreg,
.fb_blank = imxfb_blank,
};
/*
* imxfb_activate_var():
* Configures LCD Controller based on entries in var parameter. Settings are
* only written to the controller if changes were made.
*/
static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct imxfb_info *fbi = info->par;
u32 ymax_mask = is_imx1_fb(fbi) ? YMAX_MASK_IMX1 : YMAX_MASK_IMX21;
pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
var->xres, var->hsync_len,
var->left_margin, var->right_margin);
pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
var->yres, var->vsync_len,
var->upper_margin, var->lower_margin);
#if DEBUG_VAR
if (var->xres < 16 || var->xres > 1024)
printk(KERN_ERR "%s: invalid xres %d\n",
info->fix.id, var->xres);
if (var->hsync_len < 1 || var->hsync_len > 64)
printk(KERN_ERR "%s: invalid hsync_len %d\n",
info->fix.id, var->hsync_len);
if (var->left_margin < 3 || var->left_margin > 255)
printk(KERN_ERR "%s: invalid left_margin %d\n",
info->fix.id, var->left_margin);
if (var->right_margin < 1 || var->right_margin > 255)
printk(KERN_ERR "%s: invalid right_margin %d\n",
info->fix.id, var->right_margin);
if (var->yres < 1 || var->yres > ymax_mask)
printk(KERN_ERR "%s: invalid yres %d\n",
info->fix.id, var->yres);
if (var->vsync_len > 100)
printk(KERN_ERR "%s: invalid vsync_len %d\n",
info->fix.id, var->vsync_len);
if (var->upper_margin > 63)
printk(KERN_ERR "%s: invalid upper_margin %d\n",
info->fix.id, var->upper_margin);
if (var->lower_margin > 255)
printk(KERN_ERR "%s: invalid lower_margin %d\n",
info->fix.id, var->lower_margin);
#endif
/* physical screen start address */
writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4),
fbi->regs + LCDC_VPW);
writel(HCR_H_WIDTH(var->hsync_len - 1) |
HCR_H_WAIT_1(var->right_margin - 1) |
HCR_H_WAIT_2(var->left_margin - 3),
fbi->regs + LCDC_HCR);
writel(VCR_V_WIDTH(var->vsync_len) |
VCR_V_WAIT_1(var->lower_margin) |
VCR_V_WAIT_2(var->upper_margin),
fbi->regs + LCDC_VCR);
writel(SIZE_XMAX(var->xres) | (var->yres & ymax_mask),
fbi->regs + LCDC_SIZE);
writel(fbi->pcr, fbi->regs + LCDC_PCR);
if (fbi->pwmr)
writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
/* dmacr = 0 is no valid value, as we need DMA control marks. */
if (fbi->dmacr)
writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
if (fbi->lauscr)
writel(fbi->lauscr, fbi->regs + LCDC_LAUSCR);
return 0;
}
static int imxfb_init_fbinfo(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct imxfb_info *fbi = info->par;
struct device_node *np;
pr_debug("%s\n",__func__);
info->pseudo_palette = devm_kmalloc_array(&pdev->dev, 16,
sizeof(u32), GFP_KERNEL);
if (!info->pseudo_palette)
return -ENOMEM;
memset(fbi, 0, sizeof(struct imxfb_info));
fbi->devtype = pdev->id_entry->driver_data;
strscpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &imxfb_ops;
info->flags = FBINFO_READS_FAST;
np = pdev->dev.of_node;
info->var.grayscale = of_property_read_bool(np,
"cmap-greyscale");
fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse");
fbi->cmap_static = of_property_read_bool(np, "cmap-static");
fbi->lscr1 = IMXFB_LSCR1_DEFAULT;
of_property_read_u32(np, "fsl,lpccr", &fbi->pwmr);
of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1);
of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr);
return 0;
}
static int imxfb_of_read_mode(struct device *dev, struct device_node *np,
struct imx_fb_videomode *imxfb_mode)
{
int ret;
struct fb_videomode *of_mode = &imxfb_mode->mode;
u32 bpp;
u32 pcr;
ret = of_property_read_string(np, "model", &of_mode->name);
if (ret)
of_mode->name = NULL;
ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE);
if (ret) {
dev_err(dev, "Failed to get videomode from DT\n");
return ret;
}
ret = of_property_read_u32(np, "bits-per-pixel", &bpp);
ret |= of_property_read_u32(np, "fsl,pcr", &pcr);
if (ret) {
dev_err(dev, "Failed to read bpp and pcr from DT\n");
return -EINVAL;
}
if (bpp < 1 || bpp > 255) {
dev_err(dev, "Bits per pixel have to be between 1 and 255\n");
return -EINVAL;
}
imxfb_mode->bpp = bpp;
imxfb_mode->pcr = pcr;
/*
* fsl,aus-mode is optional
*/
imxfb_mode->aus_mode = of_property_read_bool(np, "fsl,aus-mode");
return 0;
}
static int imxfb_lcd_check_fb(struct lcd_device *lcddev, struct fb_info *fi)
{
struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
if (!fi || fi->par == fbi)
return 1;
return 0;
}
static int imxfb_lcd_get_contrast(struct lcd_device *lcddev)
{
struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
return fbi->pwmr & 0xff;
}
static int imxfb_lcd_set_contrast(struct lcd_device *lcddev, int contrast)
{
struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
if (fbi->pwmr && fbi->enabled) {
if (contrast > 255)
contrast = 255;
else if (contrast < 0)
contrast = 0;
fbi->pwmr &= ~0xff;
fbi->pwmr |= contrast;
writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
}
return 0;
}
static int imxfb_lcd_get_power(struct lcd_device *lcddev)
{
struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
if (!IS_ERR(fbi->lcd_pwr) &&
!regulator_is_enabled(fbi->lcd_pwr))
return FB_BLANK_POWERDOWN;
return FB_BLANK_UNBLANK;
}
static int imxfb_regulator_set(struct imxfb_info *fbi, int enable)
{
int ret;
if (enable == fbi->lcd_pwr_enabled)
return 0;
if (enable)
ret = regulator_enable(fbi->lcd_pwr);
else
ret = regulator_disable(fbi->lcd_pwr);
if (ret == 0)
fbi->lcd_pwr_enabled = enable;
return ret;
}
static int imxfb_lcd_set_power(struct lcd_device *lcddev, int power)
{
struct imxfb_info *fbi = dev_get_drvdata(&lcddev->dev);
if (!IS_ERR(fbi->lcd_pwr))
return imxfb_regulator_set(fbi, power == FB_BLANK_UNBLANK);
return 0;
}
static struct lcd_ops imxfb_lcd_ops = {
.check_fb = imxfb_lcd_check_fb,
.get_contrast = imxfb_lcd_get_contrast,
.set_contrast = imxfb_lcd_set_contrast,
.get_power = imxfb_lcd_get_power,
.set_power = imxfb_lcd_set_power,
};
static int imxfb_setup(void)
{
char *opt, *options = NULL;
if (fb_get_options("imxfb", &options))
return -ENODEV;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
else
fb_mode = opt;
}
return 0;
}
static int imxfb_probe(struct platform_device *pdev)
{
struct imxfb_info *fbi;
struct lcd_device *lcd;
struct fb_info *info;
struct imx_fb_videomode *m;
const struct of_device_id *of_id;
struct device_node *display_np;
int ret, i;
int bytes_per_pixel;
dev_info(&pdev->dev, "i.MX Framebuffer driver\n");
ret = imxfb_setup();
if (ret < 0)
return ret;
of_id = of_match_device(imxfb_of_dev_id, &pdev->dev);
if (of_id)
pdev->id_entry = of_id->data;
info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
if (!info)
return -ENOMEM;
fbi = info->par;
platform_set_drvdata(pdev, info);
ret = imxfb_init_fbinfo(pdev);
if (ret < 0)
goto failed_init;
fb_mode = NULL;
display_np = of_parse_phandle(pdev->dev.of_node, "display", 0);
if (!display_np) {
dev_err(&pdev->dev, "No display defined in devicetree\n");
ret = -EINVAL;
goto failed_init;
}
/*
* imxfb does not support more modes, we choose only the native
* mode.
*/
fbi->num_modes = 1;
fbi->mode = devm_kzalloc(&pdev->dev,
sizeof(struct imx_fb_videomode), GFP_KERNEL);
if (!fbi->mode) {
ret = -ENOMEM;
of_node_put(display_np);
goto failed_init;
}
ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode);
of_node_put(display_np);
if (ret)
goto failed_init;
/* Calculate maximum bytes used per pixel. In most cases this should
* be the same as m->bpp/8 */
m = &fbi->mode[0];
bytes_per_pixel = (m->bpp + 7) / 8;
for (i = 0; i < fbi->num_modes; i++, m++)
info->fix.smem_len = max_t(size_t, info->fix.smem_len,
m->mode.xres * m->mode.yres * bytes_per_pixel);
fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
if (IS_ERR(fbi->clk_ipg)) {
ret = PTR_ERR(fbi->clk_ipg);
goto failed_init;
}
/*
* The LCDC controller does not have an enable bit. The
* controller starts directly when the clocks are enabled.
* If the clocks are enabled when the controller is not yet
* programmed with proper register values (enabled at the
* bootloader, for example) then it just goes into some undefined
* state.
* To avoid this issue, let's enable and disable LCDC IPG clock
* so that we force some kind of 'reset' to the LCDC block.
*/
ret = clk_prepare_enable(fbi->clk_ipg);
if (ret)
goto failed_init;
clk_disable_unprepare(fbi->clk_ipg);
fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
if (IS_ERR(fbi->clk_ahb)) {
ret = PTR_ERR(fbi->clk_ahb);
goto failed_init;
}
fbi->clk_per = devm_clk_get(&pdev->dev, "per");
if (IS_ERR(fbi->clk_per)) {
ret = PTR_ERR(fbi->clk_per);
goto failed_init;
}
fbi->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(fbi->regs)) {
ret = PTR_ERR(fbi->regs);
goto failed_init;
}
fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
info->screen_buffer = dma_alloc_wc(&pdev->dev, fbi->map_size,
&fbi->map_dma, GFP_KERNEL);
if (!info->screen_buffer) {
dev_err(&pdev->dev, "Failed to allocate video RAM\n");
ret = -ENOMEM;
goto failed_init;
}
info->fix.smem_start = fbi->map_dma;
INIT_LIST_HEAD(&info->modelist);
for (i = 0; i < fbi->num_modes; i++)
fb_add_videomode(&fbi->mode[i].mode, &info->modelist);
/*
* This makes sure that our colour bitfield
* descriptors are correctly initialised.
*/
imxfb_check_var(&info->var, info);
/*
* For modes > 8bpp, the color map is bypassed.
* Therefore, 256 entries are enough.
*/
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (ret < 0)
goto failed_cmap;
imxfb_set_par(info);
ret = register_framebuffer(info);
if (ret < 0) {
dev_err(&pdev->dev, "failed to register framebuffer\n");
goto failed_register;
}
fbi->lcd_pwr = devm_regulator_get(&pdev->dev, "lcd");
if (PTR_ERR(fbi->lcd_pwr) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
goto failed_lcd;
}
lcd = devm_lcd_device_register(&pdev->dev, "imxfb-lcd", &pdev->dev, fbi,
&imxfb_lcd_ops);
if (IS_ERR(lcd)) {
ret = PTR_ERR(lcd);
goto failed_lcd;
}
lcd->props.max_contrast = 0xff;
imxfb_enable_controller(fbi);
fbi->pdev = pdev;
return 0;
failed_lcd:
unregister_framebuffer(info);
failed_register:
fb_dealloc_cmap(&info->cmap);
failed_cmap:
dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer,
fbi->map_dma);
failed_init:
framebuffer_release(info);
return ret;
}
static void imxfb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct imxfb_info *fbi = info->par;
imxfb_disable_controller(fbi);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
dma_free_wc(&pdev->dev, fbi->map_size, info->screen_buffer,
fbi->map_dma);
framebuffer_release(info);
}
static int imxfb_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct imxfb_info *fbi = info->par;
imxfb_disable_controller(fbi);
return 0;
}
static int imxfb_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct imxfb_info *fbi = info->par;
imxfb_enable_controller(fbi);
return 0;
}
static DEFINE_SIMPLE_DEV_PM_OPS(imxfb_pm_ops, imxfb_suspend, imxfb_resume);
static struct platform_driver imxfb_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = imxfb_of_dev_id,
.pm = pm_sleep_ptr(&imxfb_pm_ops),
},
.probe = imxfb_probe,
.remove_new = imxfb_remove,
.id_table = imxfb_devtype,
};
module_platform_driver(imxfb_driver);
MODULE_DESCRIPTION("Freescale i.MX framebuffer driver");
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/imxfb.c |
/* $Id: g364fb.c,v 1.3 1998/08/28 22:43:00 tsbogend Exp $
*
* linux/drivers/video/g364fb.c -- Mips Magnum frame buffer device
*
* (C) 1998 Thomas Bogendoerfer
*
* This driver is based on tgafb.c
*
* Copyright (C) 1997 Geert Uytterhoeven
* Copyright (C) 1995 Jay Estabrook
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/console.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <asm/io.h>
#include <asm/jazz.h>
/*
* Various defines for the G364
*/
#define G364_MEM_BASE 0xe4400000
#define G364_PORT_BASE 0xe4000000
#define ID_REG 0xe4000000 /* Read only */
#define BOOT_REG 0xe4080000
#define TIMING_REG 0xe4080108 /* to 0x080170 - DON'T TOUCH! */
#define DISPLAY_REG 0xe4080118
#define VDISPLAY_REG 0xe4080150
#define MASK_REG 0xe4080200
#define CTLA_REG 0xe4080300
#define CURS_TOGGLE 0x800000
#define BIT_PER_PIX 0x700000 /* bits 22 to 20 of Control A */
#define DELAY_SAMPLE 0x080000
#define PORT_INTER 0x040000
#define PIX_PIPE_DEL 0x030000 /* bits 17 and 16 of Control A */
#define PIX_PIPE_DEL2 0x008000 /* same as above - don't ask me why */
#define TR_CYCLE_TOG 0x004000
#define VRAM_ADR_INC 0x003000 /* bits 13 and 12 of Control A */
#define BLANK_OFF 0x000800
#define FORCE_BLANK 0x000400
#define BLK_FUN_SWTCH 0x000200
#define BLANK_IO 0x000100
#define BLANK_LEVEL 0x000080
#define A_VID_FORM 0x000040
#define D_SYNC_FORM 0x000020
#define FRAME_FLY_PAT 0x000010
#define OP_MODE 0x000008
#define INTL_STAND 0x000004
#define SCRN_FORM 0x000002
#define ENABLE_VTG 0x000001
#define TOP_REG 0xe4080400
#define CURS_PAL_REG 0xe4080508 /* to 0x080518 */
#define CHKSUM_REG 0xe4080600 /* to 0x080610 - unused */
#define CURS_POS_REG 0xe4080638
#define CLR_PAL_REG 0xe4080800 /* to 0x080ff8 */
#define CURS_PAT_REG 0xe4081000 /* to 0x081ff8 */
#define MON_ID_REG 0xe4100000 /* unused */
#define RESET_REG 0xe4180000 /* Write only */
static struct fb_info fb_info;
static struct fb_fix_screeninfo fb_fix __initdata = {
.id = "G364 8plane",
.smem_start = 0x40000000, /* physical address */
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.ypanstep = 1,
.accel = FB_ACCEL_NONE,
};
static struct fb_var_screeninfo fb_var __initdata = {
.bits_per_pixel = 8,
.red = { 0, 8, 0 },
.green = { 0, 8, 0 },
.blue = { 0, 8, 0 },
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.pixclock = 39722,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED,
};
/*
* Interface used by the world
*/
int g364fb_init(void);
static int g364fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info);
static int g364fb_setcolreg(u_int regno, u_int red, u_int green,
u_int blue, u_int transp,
struct fb_info *info);
static int g364fb_blank(int blank, struct fb_info *info);
static const struct fb_ops g364fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_setcolreg = g364fb_setcolreg,
.fb_pan_display = g364fb_pan_display,
.fb_blank = g364fb_blank,
};
/*
* Pan or Wrap the Display
*
* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
*/
static int g364fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
if (var->xoffset ||
var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
*(unsigned int *) TOP_REG = var->yoffset * info->var.xres;
return 0;
}
/*
* Blank the display.
*/
static int g364fb_blank(int blank, struct fb_info *info)
{
if (blank)
*(unsigned int *) CTLA_REG |= FORCE_BLANK;
else
*(unsigned int *) CTLA_REG &= ~FORCE_BLANK;
return 0;
}
/*
* Set a single color register. Return != 0 for invalid regno.
*/
static int g364fb_setcolreg(u_int regno, u_int red, u_int green,
u_int blue, u_int transp, struct fb_info *info)
{
volatile unsigned int *ptr = (volatile unsigned int *) CLR_PAL_REG;
if (regno > 255)
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
ptr[regno << 1] = (red << 16) | (green << 8) | blue;
return 0;
}
/*
* Initialisation
*/
int __init g364fb_init(void)
{
volatile unsigned int *curs_pal_ptr =
(volatile unsigned int *) CURS_PAL_REG;
int mem, i;
if (fb_get_options("g364fb", NULL))
return -ENODEV;
/* TBD: G364 detection */
/* get the resolution set by ARC console */
*(volatile unsigned int *) CTLA_REG &= ~ENABLE_VTG;
fb_var.xres =
(*((volatile unsigned int *) DISPLAY_REG) & 0x00ffffff) * 4;
fb_var.yres =
(*((volatile unsigned int *) VDISPLAY_REG) & 0x00ffffff) / 2;
*(volatile unsigned int *) CTLA_REG |= ENABLE_VTG;
/* setup cursor */
curs_pal_ptr[0] |= 0x00ffffff;
curs_pal_ptr[2] |= 0x00ffffff;
curs_pal_ptr[4] |= 0x00ffffff;
/*
* first set the whole cursor to transparent
*/
for (i = 0; i < 512; i++)
*(unsigned short *) (CURS_PAT_REG + i * 8) = 0;
/*
* switch the last two lines to cursor palette 3
* we assume here, that FONTSIZE_X is 8
*/
*(unsigned short *) (CURS_PAT_REG + 14 * 64) = 0xffff;
*(unsigned short *) (CURS_PAT_REG + 15 * 64) = 0xffff;
fb_var.xres_virtual = fb_var.xres;
fb_fix.line_length = fb_var.xres_virtual * fb_var.bits_per_pixel / 8;
fb_fix.smem_start = 0x40000000; /* physical address */
/* get size of video memory; this is special for the JAZZ hardware */
mem = (r4030_read_reg32(JAZZ_R4030_CONFIG) >> 8) & 3;
fb_fix.smem_len = (1 << (mem * 2)) * 512 * 1024;
fb_var.yres_virtual = fb_fix.smem_len / fb_var.xres;
fb_info.fbops = &g364fb_ops;
fb_info.screen_base = (char *) G364_MEM_BASE; /* virtual kernel address */
fb_info.var = fb_var;
fb_info.fix = fb_fix;
fb_info.flags = FBINFO_HWACCEL_YPAN;
fb_alloc_cmap(&fb_info.cmap, 255, 0);
if (register_framebuffer(&fb_info) < 0)
return -EINVAL;
return 0;
}
module_init(g364fb_init);
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/g364fb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) Intel Corp. 2007.
* All Rights Reserved.
*
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
* develop this driver.
*
* This file is part of the Carillo Ranch video subsystem driver.
*
* Authors:
* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
* Alan Hourihane <alanh-at-tungstengraphics-dot-com>
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include "vermilion.h"
/* The PLL Clock register sits on Host bridge */
#define CRVML_DEVICE_MCH 0x5001
#define CRVML_REG_MCHBAR 0x44
#define CRVML_REG_MCHEN 0x54
#define CRVML_MCHEN_BIT (1 << 28)
#define CRVML_MCHMAP_SIZE 4096
#define CRVML_REG_CLOCK 0xc3c
#define CRVML_CLOCK_SHIFT 8
#define CRVML_CLOCK_MASK 0x00000f00
static struct pci_dev *mch_dev;
static u32 mch_bar;
static void __iomem *mch_regs_base;
static u32 saved_clock;
static const unsigned crvml_clocks[] = {
6750,
13500,
27000,
29700,
37125,
54000,
59400,
74250,
120000
/*
* There are more clocks, but they are disabled on the CR board.
*/
};
static const u32 crvml_clock_bits[] = {
0x0a,
0x09,
0x08,
0x07,
0x06,
0x05,
0x04,
0x03,
0x0b
};
static const unsigned crvml_num_clocks = ARRAY_SIZE(crvml_clocks);
static int crvml_sys_restore(struct vml_sys *sys)
{
void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
iowrite32(saved_clock, clock_reg);
ioread32(clock_reg);
return 0;
}
static int crvml_sys_save(struct vml_sys *sys)
{
void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
saved_clock = ioread32(clock_reg);
return 0;
}
static int crvml_nearest_index(const struct vml_sys *sys, int clock)
{
int i;
int cur_index = 0;
int cur_diff;
int diff;
cur_diff = clock - crvml_clocks[0];
cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff;
for (i = 1; i < crvml_num_clocks; ++i) {
diff = clock - crvml_clocks[i];
diff = (diff < 0) ? -diff : diff;
if (diff < cur_diff) {
cur_index = i;
cur_diff = diff;
}
}
return cur_index;
}
static int crvml_nearest_clock(const struct vml_sys *sys, int clock)
{
return crvml_clocks[crvml_nearest_index(sys, clock)];
}
static int crvml_set_clock(struct vml_sys *sys, int clock)
{
void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
int index;
u32 clock_val;
index = crvml_nearest_index(sys, clock);
if (crvml_clocks[index] != clock)
return -EINVAL;
clock_val = ioread32(clock_reg) & ~CRVML_CLOCK_MASK;
clock_val = crvml_clock_bits[index] << CRVML_CLOCK_SHIFT;
iowrite32(clock_val, clock_reg);
ioread32(clock_reg);
return 0;
}
static struct vml_sys cr_pll_ops = {
.name = "Carillo Ranch",
.save = crvml_sys_save,
.restore = crvml_sys_restore,
.set_clock = crvml_set_clock,
.nearest_clock = crvml_nearest_clock,
};
static int __init cr_pll_init(void)
{
int err;
u32 dev_en;
mch_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
CRVML_DEVICE_MCH, NULL);
if (!mch_dev) {
printk(KERN_ERR
"Could not find Carillo Ranch MCH device.\n");
return -ENODEV;
}
pci_read_config_dword(mch_dev, CRVML_REG_MCHEN, &dev_en);
if (!(dev_en & CRVML_MCHEN_BIT)) {
printk(KERN_ERR
"Carillo Ranch MCH device was not enabled.\n");
pci_dev_put(mch_dev);
return -ENODEV;
}
pci_read_config_dword(mch_dev, CRVML_REG_MCHBAR,
&mch_bar);
mch_regs_base =
ioremap(mch_bar, CRVML_MCHMAP_SIZE);
if (!mch_regs_base) {
printk(KERN_ERR
"Carillo Ranch MCH device was not enabled.\n");
pci_dev_put(mch_dev);
return -ENODEV;
}
err = vmlfb_register_subsys(&cr_pll_ops);
if (err) {
printk(KERN_ERR
"Carillo Ranch failed to initialize vml_sys.\n");
iounmap(mch_regs_base);
pci_dev_put(mch_dev);
return err;
}
return 0;
}
static void __exit cr_pll_exit(void)
{
vmlfb_unregister_subsys(&cr_pll_ops);
iounmap(mch_regs_base);
pci_dev_put(mch_dev);
}
module_init(cr_pll_init);
module_exit(cr_pll_exit);
MODULE_AUTHOR("Tungsten Graphics Inc.");
MODULE_DESCRIPTION("Carillo Ranch PLL Driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/vermilion/cr_pll.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) Intel Corp. 2007.
* All Rights Reserved.
*
* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
* develop this driver.
*
* This file is part of the Vermilion Range fb driver.
*
* Authors:
* Thomas Hellström <thomas-at-tungstengraphics-dot-com>
* Michel Dänzer <michel-at-tungstengraphics-dot-com>
* Alan Hourihane <alanh-at-tungstengraphics-dot-com>
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/pci.h>
#include <asm/set_memory.h>
#include <asm/tlbflush.h>
#include <linux/mmzone.h>
/* #define VERMILION_DEBUG */
#include "vermilion.h"
#define MODULE_NAME "vmlfb"
#define VML_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16)
static struct mutex vml_mutex;
static struct list_head global_no_mode;
static struct list_head global_has_mode;
static struct fb_ops vmlfb_ops;
static struct vml_sys *subsys = NULL;
static char *vml_default_mode = "1024x768@60";
static const struct fb_videomode defaultmode = {
NULL, 60, 1024, 768, 12896, 144, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED
};
static u32 vml_mem_requested = (10 * 1024 * 1024);
static u32 vml_mem_contig = (4 * 1024 * 1024);
static u32 vml_mem_min = (4 * 1024 * 1024);
static u32 vml_clocks[] = {
6750,
13500,
27000,
29700,
37125,
54000,
59400,
74250,
120000,
148500
};
static u32 vml_num_clocks = ARRAY_SIZE(vml_clocks);
/*
* Allocate a contiguous vram area and make its linear kernel map
* uncached.
*/
static int vmlfb_alloc_vram_area(struct vram_area *va, unsigned max_order,
unsigned min_order)
{
gfp_t flags;
unsigned long i;
max_order++;
do {
/*
* Really try hard to get the needed memory.
* We need memory below the first 32MB, so we
* add the __GFP_DMA flag that guarantees that we are
* below the first 16MB.
*/
flags = __GFP_DMA | __GFP_HIGH | __GFP_KSWAPD_RECLAIM;
va->logical =
__get_free_pages(flags, --max_order);
} while (va->logical == 0 && max_order > min_order);
if (!va->logical)
return -ENOMEM;
va->phys = virt_to_phys((void *)va->logical);
va->size = PAGE_SIZE << max_order;
va->order = max_order;
/*
* It seems like __get_free_pages only ups the usage count
* of the first page. This doesn't work with fault mapping, so
* up the usage count once more (XXX: should use split_page or
* compound page).
*/
memset((void *)va->logical, 0x00, va->size);
for (i = va->logical; i < va->logical + va->size; i += PAGE_SIZE) {
get_page(virt_to_page(i));
}
/*
* Change caching policy of the linear kernel map to avoid
* mapping type conflicts with user-space mappings.
*/
set_pages_uc(virt_to_page(va->logical), va->size >> PAGE_SHIFT);
printk(KERN_DEBUG MODULE_NAME
": Allocated %ld bytes vram area at 0x%08lx\n",
va->size, va->phys);
return 0;
}
/*
* Free a contiguous vram area and reset its linear kernel map
* mapping type.
*/
static void vmlfb_free_vram_area(struct vram_area *va)
{
unsigned long j;
if (va->logical) {
/*
* Reset the linear kernel map caching policy.
*/
set_pages_wb(virt_to_page(va->logical),
va->size >> PAGE_SHIFT);
/*
* Decrease the usage count on the pages we've used
* to compensate for upping when allocating.
*/
for (j = va->logical; j < va->logical + va->size;
j += PAGE_SIZE) {
(void)put_page_testzero(virt_to_page(j));
}
printk(KERN_DEBUG MODULE_NAME
": Freeing %ld bytes vram area at 0x%08lx\n",
va->size, va->phys);
free_pages(va->logical, va->order);
va->logical = 0;
}
}
/*
* Free allocated vram.
*/
static void vmlfb_free_vram(struct vml_info *vinfo)
{
int i;
for (i = 0; i < vinfo->num_areas; ++i) {
vmlfb_free_vram_area(&vinfo->vram[i]);
}
vinfo->num_areas = 0;
}
/*
* Allocate vram. Currently we try to allocate contiguous areas from the
* __GFP_DMA zone and puzzle them together. A better approach would be to
* allocate one contiguous area for scanout and use one-page allocations for
* offscreen areas. This requires user-space and GPU virtual mappings.
*/
static int vmlfb_alloc_vram(struct vml_info *vinfo,
size_t requested,
size_t min_total, size_t min_contig)
{
int i, j;
int order;
int contiguous;
int err;
struct vram_area *va;
struct vram_area *va2;
vinfo->num_areas = 0;
for (i = 0; i < VML_VRAM_AREAS; ++i) {
va = &vinfo->vram[i];
order = 0;
while (requested > (PAGE_SIZE << order) && order <= MAX_ORDER)
order++;
err = vmlfb_alloc_vram_area(va, order, 0);
if (err)
break;
if (i == 0) {
vinfo->vram_start = va->phys;
vinfo->vram_logical = (void __iomem *) va->logical;
vinfo->vram_contig_size = va->size;
vinfo->num_areas = 1;
} else {
contiguous = 0;
for (j = 0; j < i; ++j) {
va2 = &vinfo->vram[j];
if (va->phys + va->size == va2->phys ||
va2->phys + va2->size == va->phys) {
contiguous = 1;
break;
}
}
if (contiguous) {
vinfo->num_areas++;
if (va->phys < vinfo->vram_start) {
vinfo->vram_start = va->phys;
vinfo->vram_logical =
(void __iomem *)va->logical;
}
vinfo->vram_contig_size += va->size;
} else {
vmlfb_free_vram_area(va);
break;
}
}
if (requested < va->size)
break;
else
requested -= va->size;
}
if (vinfo->vram_contig_size > min_total &&
vinfo->vram_contig_size > min_contig) {
printk(KERN_DEBUG MODULE_NAME
": Contiguous vram: %ld bytes at physical 0x%08lx.\n",
(unsigned long)vinfo->vram_contig_size,
(unsigned long)vinfo->vram_start);
return 0;
}
printk(KERN_ERR MODULE_NAME
": Could not allocate requested minimal amount of vram.\n");
vmlfb_free_vram(vinfo);
return -ENOMEM;
}
/*
* Find the GPU to use with our display controller.
*/
static int vmlfb_get_gpu(struct vml_par *par)
{
mutex_lock(&vml_mutex);
par->gpu = pci_get_device(PCI_VENDOR_ID_INTEL, VML_DEVICE_GPU, NULL);
if (!par->gpu) {
mutex_unlock(&vml_mutex);
return -ENODEV;
}
mutex_unlock(&vml_mutex);
if (pci_enable_device(par->gpu) < 0) {
pci_dev_put(par->gpu);
return -ENODEV;
}
return 0;
}
/*
* Find a contiguous vram area that contains a given offset from vram start.
*/
static int vmlfb_vram_offset(struct vml_info *vinfo, unsigned long offset)
{
unsigned long aoffset;
unsigned i;
for (i = 0; i < vinfo->num_areas; ++i) {
aoffset = offset - (vinfo->vram[i].phys - vinfo->vram_start);
if (aoffset < vinfo->vram[i].size) {
return 0;
}
}
return -EINVAL;
}
/*
* Remap the MMIO register spaces of the VDC and the GPU.
*/
static int vmlfb_enable_mmio(struct vml_par *par)
{
int err;
par->vdc_mem_base = pci_resource_start(par->vdc, 0);
par->vdc_mem_size = pci_resource_len(par->vdc, 0);
if (!request_mem_region(par->vdc_mem_base, par->vdc_mem_size, "vmlfb")) {
printk(KERN_ERR MODULE_NAME
": Could not claim display controller MMIO.\n");
return -EBUSY;
}
par->vdc_mem = ioremap(par->vdc_mem_base, par->vdc_mem_size);
if (par->vdc_mem == NULL) {
printk(KERN_ERR MODULE_NAME
": Could not map display controller MMIO.\n");
err = -ENOMEM;
goto out_err_0;
}
par->gpu_mem_base = pci_resource_start(par->gpu, 0);
par->gpu_mem_size = pci_resource_len(par->gpu, 0);
if (!request_mem_region(par->gpu_mem_base, par->gpu_mem_size, "vmlfb")) {
printk(KERN_ERR MODULE_NAME ": Could not claim GPU MMIO.\n");
err = -EBUSY;
goto out_err_1;
}
par->gpu_mem = ioremap(par->gpu_mem_base, par->gpu_mem_size);
if (par->gpu_mem == NULL) {
printk(KERN_ERR MODULE_NAME ": Could not map GPU MMIO.\n");
err = -ENOMEM;
goto out_err_2;
}
return 0;
out_err_2:
release_mem_region(par->gpu_mem_base, par->gpu_mem_size);
out_err_1:
iounmap(par->vdc_mem);
out_err_0:
release_mem_region(par->vdc_mem_base, par->vdc_mem_size);
return err;
}
/*
* Unmap the VDC and GPU register spaces.
*/
static void vmlfb_disable_mmio(struct vml_par *par)
{
iounmap(par->gpu_mem);
release_mem_region(par->gpu_mem_base, par->gpu_mem_size);
iounmap(par->vdc_mem);
release_mem_region(par->vdc_mem_base, par->vdc_mem_size);
}
/*
* Release and uninit the VDC and GPU.
*/
static void vmlfb_release_devices(struct vml_par *par)
{
if (atomic_dec_and_test(&par->refcount)) {
pci_disable_device(par->gpu);
pci_disable_device(par->vdc);
}
}
/*
* Free up allocated resources for a device.
*/
static void vml_pci_remove(struct pci_dev *dev)
{
struct fb_info *info;
struct vml_info *vinfo;
struct vml_par *par;
info = pci_get_drvdata(dev);
if (info) {
vinfo = container_of(info, struct vml_info, info);
par = vinfo->par;
mutex_lock(&vml_mutex);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
vmlfb_free_vram(vinfo);
vmlfb_disable_mmio(par);
vmlfb_release_devices(par);
kfree(vinfo);
kfree(par);
mutex_unlock(&vml_mutex);
}
}
static void vmlfb_set_pref_pixel_format(struct fb_var_screeninfo *var)
{
switch (var->bits_per_pixel) {
case 16:
var->blue.offset = 0;
var->blue.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->red.offset = 10;
var->red.length = 5;
var->transp.offset = 15;
var->transp.length = 1;
break;
case 32:
var->blue.offset = 0;
var->blue.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->red.offset = 16;
var->red.length = 8;
var->transp.offset = 24;
var->transp.length = 0;
break;
default:
break;
}
var->blue.msb_right = var->green.msb_right =
var->red.msb_right = var->transp.msb_right = 0;
}
/*
* Device initialization.
* We initialize one vml_par struct per device and one vml_info
* struct per pipe. Currently we have only one pipe.
*/
static int vml_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct vml_info *vinfo;
struct fb_info *info;
struct vml_par *par;
int err;
err = aperture_remove_conflicting_pci_devices(dev, "vmlfb");
if (err)
return err;
par = kzalloc(sizeof(*par), GFP_KERNEL);
if (par == NULL)
return -ENOMEM;
vinfo = kzalloc(sizeof(*vinfo), GFP_KERNEL);
if (vinfo == NULL) {
err = -ENOMEM;
goto out_err_0;
}
vinfo->par = par;
par->vdc = dev;
atomic_set(&par->refcount, 1);
switch (id->device) {
case VML_DEVICE_VDC:
if ((err = vmlfb_get_gpu(par)))
goto out_err_1;
pci_set_drvdata(dev, &vinfo->info);
break;
default:
err = -ENODEV;
goto out_err_1;
}
info = &vinfo->info;
info->flags = FBINFO_PARTIAL_PAN_OK;
err = vmlfb_enable_mmio(par);
if (err)
goto out_err_2;
err = vmlfb_alloc_vram(vinfo, vml_mem_requested,
vml_mem_contig, vml_mem_min);
if (err)
goto out_err_3;
strcpy(info->fix.id, "Vermilion Range");
info->fix.mmio_start = 0;
info->fix.mmio_len = 0;
info->fix.smem_start = vinfo->vram_start;
info->fix.smem_len = vinfo->vram_contig_size;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.ypanstep = 1;
info->fix.xpanstep = 1;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->screen_base = vinfo->vram_logical;
info->pseudo_palette = vinfo->pseudo_palette;
info->par = par;
info->fbops = &vmlfb_ops;
info->device = &dev->dev;
INIT_LIST_HEAD(&vinfo->head);
vinfo->pipe_disabled = 1;
vinfo->cur_blank_mode = FB_BLANK_UNBLANK;
info->var.grayscale = 0;
info->var.bits_per_pixel = 16;
vmlfb_set_pref_pixel_format(&info->var);
if (!fb_find_mode
(&info->var, info, vml_default_mode, NULL, 0, &defaultmode, 16)) {
printk(KERN_ERR MODULE_NAME ": Could not find initial mode\n");
}
if (fb_alloc_cmap(&info->cmap, 256, 1) < 0) {
err = -ENOMEM;
goto out_err_4;
}
err = register_framebuffer(info);
if (err) {
printk(KERN_ERR MODULE_NAME ": Register framebuffer error.\n");
goto out_err_5;
}
printk("Initialized vmlfb\n");
return 0;
out_err_5:
fb_dealloc_cmap(&info->cmap);
out_err_4:
vmlfb_free_vram(vinfo);
out_err_3:
vmlfb_disable_mmio(par);
out_err_2:
vmlfb_release_devices(par);
out_err_1:
kfree(vinfo);
out_err_0:
kfree(par);
return err;
}
static int vmlfb_open(struct fb_info *info, int user)
{
/*
* Save registers here?
*/
return 0;
}
static int vmlfb_release(struct fb_info *info, int user)
{
/*
* Restore registers here.
*/
return 0;
}
static int vml_nearest_clock(int clock)
{
int i;
int cur_index;
int cur_diff;
int diff;
cur_index = 0;
cur_diff = clock - vml_clocks[0];
cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff;
for (i = 1; i < vml_num_clocks; ++i) {
diff = clock - vml_clocks[i];
diff = (diff < 0) ? -diff : diff;
if (diff < cur_diff) {
cur_index = i;
cur_diff = diff;
}
}
return vml_clocks[cur_index];
}
static int vmlfb_check_var_locked(struct fb_var_screeninfo *var,
struct vml_info *vinfo)
{
u32 pitch;
u64 mem;
int nearest_clock;
int clock;
int clock_diff;
struct fb_var_screeninfo v;
v = *var;
clock = PICOS2KHZ(var->pixclock);
if (subsys && subsys->nearest_clock) {
nearest_clock = subsys->nearest_clock(subsys, clock);
} else {
nearest_clock = vml_nearest_clock(clock);
}
/*
* Accept a 20% diff.
*/
clock_diff = nearest_clock - clock;
clock_diff = (clock_diff < 0) ? -clock_diff : clock_diff;
if (clock_diff > clock / 5) {
#if 0
printk(KERN_DEBUG MODULE_NAME ": Diff failure. %d %d\n",clock_diff,clock);
#endif
return -EINVAL;
}
v.pixclock = KHZ2PICOS(nearest_clock);
if (var->xres > VML_MAX_XRES || var->yres > VML_MAX_YRES) {
printk(KERN_DEBUG MODULE_NAME ": Resolution failure.\n");
return -EINVAL;
}
if (var->xres_virtual > VML_MAX_XRES_VIRTUAL) {
printk(KERN_DEBUG MODULE_NAME
": Virtual resolution failure.\n");
return -EINVAL;
}
switch (v.bits_per_pixel) {
case 0 ... 16:
v.bits_per_pixel = 16;
break;
case 17 ... 32:
v.bits_per_pixel = 32;
break;
default:
printk(KERN_DEBUG MODULE_NAME ": Invalid bpp: %d.\n",
var->bits_per_pixel);
return -EINVAL;
}
pitch = ALIGN((var->xres * var->bits_per_pixel) >> 3, 0x40);
mem = (u64)pitch * var->yres_virtual;
if (mem > vinfo->vram_contig_size) {
return -ENOMEM;
}
switch (v.bits_per_pixel) {
case 16:
if (var->blue.offset != 0 ||
var->blue.length != 5 ||
var->green.offset != 5 ||
var->green.length != 5 ||
var->red.offset != 10 ||
var->red.length != 5 ||
var->transp.offset != 15 || var->transp.length != 1) {
vmlfb_set_pref_pixel_format(&v);
}
break;
case 32:
if (var->blue.offset != 0 ||
var->blue.length != 8 ||
var->green.offset != 8 ||
var->green.length != 8 ||
var->red.offset != 16 ||
var->red.length != 8 ||
(var->transp.length != 0 && var->transp.length != 8) ||
(var->transp.length == 8 && var->transp.offset != 24)) {
vmlfb_set_pref_pixel_format(&v);
}
break;
default:
return -EINVAL;
}
*var = v;
return 0;
}
static int vmlfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct vml_info *vinfo = container_of(info, struct vml_info, info);
int ret;
mutex_lock(&vml_mutex);
ret = vmlfb_check_var_locked(var, vinfo);
mutex_unlock(&vml_mutex);
return ret;
}
static void vml_wait_vblank(struct vml_info *vinfo)
{
/* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
mdelay(20);
}
static void vmlfb_disable_pipe(struct vml_info *vinfo)
{
struct vml_par *par = vinfo->par;
/* Disable the MDVO pad */
VML_WRITE32(par, VML_RCOMPSTAT, 0);
while (!(VML_READ32(par, VML_RCOMPSTAT) & VML_MDVO_VDC_I_RCOMP)) ;
/* Disable display planes */
VML_WRITE32(par, VML_DSPCCNTR,
VML_READ32(par, VML_DSPCCNTR) & ~VML_GFX_ENABLE);
(void)VML_READ32(par, VML_DSPCCNTR);
/* Wait for vblank for the disable to take effect */
vml_wait_vblank(vinfo);
/* Next, disable display pipes */
VML_WRITE32(par, VML_PIPEACONF, 0);
(void)VML_READ32(par, VML_PIPEACONF);
vinfo->pipe_disabled = 1;
}
#ifdef VERMILION_DEBUG
static void vml_dump_regs(struct vml_info *vinfo)
{
struct vml_par *par = vinfo->par;
printk(KERN_DEBUG MODULE_NAME ": Modesetting register dump:\n");
printk(KERN_DEBUG MODULE_NAME ": \tHTOTAL_A : 0x%08x\n",
(unsigned)VML_READ32(par, VML_HTOTAL_A));
printk(KERN_DEBUG MODULE_NAME ": \tHBLANK_A : 0x%08x\n",
(unsigned)VML_READ32(par, VML_HBLANK_A));
printk(KERN_DEBUG MODULE_NAME ": \tHSYNC_A : 0x%08x\n",
(unsigned)VML_READ32(par, VML_HSYNC_A));
printk(KERN_DEBUG MODULE_NAME ": \tVTOTAL_A : 0x%08x\n",
(unsigned)VML_READ32(par, VML_VTOTAL_A));
printk(KERN_DEBUG MODULE_NAME ": \tVBLANK_A : 0x%08x\n",
(unsigned)VML_READ32(par, VML_VBLANK_A));
printk(KERN_DEBUG MODULE_NAME ": \tVSYNC_A : 0x%08x\n",
(unsigned)VML_READ32(par, VML_VSYNC_A));
printk(KERN_DEBUG MODULE_NAME ": \tDSPCSTRIDE : 0x%08x\n",
(unsigned)VML_READ32(par, VML_DSPCSTRIDE));
printk(KERN_DEBUG MODULE_NAME ": \tDSPCSIZE : 0x%08x\n",
(unsigned)VML_READ32(par, VML_DSPCSIZE));
printk(KERN_DEBUG MODULE_NAME ": \tDSPCPOS : 0x%08x\n",
(unsigned)VML_READ32(par, VML_DSPCPOS));
printk(KERN_DEBUG MODULE_NAME ": \tDSPARB : 0x%08x\n",
(unsigned)VML_READ32(par, VML_DSPARB));
printk(KERN_DEBUG MODULE_NAME ": \tDSPCADDR : 0x%08x\n",
(unsigned)VML_READ32(par, VML_DSPCADDR));
printk(KERN_DEBUG MODULE_NAME ": \tBCLRPAT_A : 0x%08x\n",
(unsigned)VML_READ32(par, VML_BCLRPAT_A));
printk(KERN_DEBUG MODULE_NAME ": \tCANVSCLR_A : 0x%08x\n",
(unsigned)VML_READ32(par, VML_CANVSCLR_A));
printk(KERN_DEBUG MODULE_NAME ": \tPIPEASRC : 0x%08x\n",
(unsigned)VML_READ32(par, VML_PIPEASRC));
printk(KERN_DEBUG MODULE_NAME ": \tPIPEACONF : 0x%08x\n",
(unsigned)VML_READ32(par, VML_PIPEACONF));
printk(KERN_DEBUG MODULE_NAME ": \tDSPCCNTR : 0x%08x\n",
(unsigned)VML_READ32(par, VML_DSPCCNTR));
printk(KERN_DEBUG MODULE_NAME ": \tRCOMPSTAT : 0x%08x\n",
(unsigned)VML_READ32(par, VML_RCOMPSTAT));
printk(KERN_DEBUG MODULE_NAME ": End of modesetting register dump.\n");
}
#endif
static int vmlfb_set_par_locked(struct vml_info *vinfo)
{
struct vml_par *par = vinfo->par;
struct fb_info *info = &vinfo->info;
struct fb_var_screeninfo *var = &info->var;
u32 htotal, hactive, hblank_start, hblank_end, hsync_start, hsync_end;
u32 vtotal, vactive, vblank_start, vblank_end, vsync_start, vsync_end;
u32 dspcntr;
int clock;
vinfo->bytes_per_pixel = var->bits_per_pixel >> 3;
vinfo->stride = ALIGN(var->xres_virtual * vinfo->bytes_per_pixel, 0x40);
info->fix.line_length = vinfo->stride;
if (!subsys)
return 0;
htotal =
var->xres + var->right_margin + var->hsync_len + var->left_margin;
hactive = var->xres;
hblank_start = var->xres;
hblank_end = htotal;
hsync_start = hactive + var->right_margin;
hsync_end = hsync_start + var->hsync_len;
vtotal =
var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
vactive = var->yres;
vblank_start = var->yres;
vblank_end = vtotal;
vsync_start = vactive + var->lower_margin;
vsync_end = vsync_start + var->vsync_len;
dspcntr = VML_GFX_ENABLE | VML_GFX_GAMMABYPASS;
clock = PICOS2KHZ(var->pixclock);
if (subsys->nearest_clock) {
clock = subsys->nearest_clock(subsys, clock);
} else {
clock = vml_nearest_clock(clock);
}
printk(KERN_DEBUG MODULE_NAME
": Set mode Hfreq : %d kHz, Vfreq : %d Hz.\n", clock / htotal,
((clock / htotal) * 1000) / vtotal);
switch (var->bits_per_pixel) {
case 16:
dspcntr |= VML_GFX_ARGB1555;
break;
case 32:
if (var->transp.length == 8)
dspcntr |= VML_GFX_ARGB8888 | VML_GFX_ALPHAMULT;
else
dspcntr |= VML_GFX_RGB0888;
break;
default:
return -EINVAL;
}
vmlfb_disable_pipe(vinfo);
mb();
if (subsys->set_clock)
subsys->set_clock(subsys, clock);
else
return -EINVAL;
VML_WRITE32(par, VML_HTOTAL_A, ((htotal - 1) << 16) | (hactive - 1));
VML_WRITE32(par, VML_HBLANK_A,
((hblank_end - 1) << 16) | (hblank_start - 1));
VML_WRITE32(par, VML_HSYNC_A,
((hsync_end - 1) << 16) | (hsync_start - 1));
VML_WRITE32(par, VML_VTOTAL_A, ((vtotal - 1) << 16) | (vactive - 1));
VML_WRITE32(par, VML_VBLANK_A,
((vblank_end - 1) << 16) | (vblank_start - 1));
VML_WRITE32(par, VML_VSYNC_A,
((vsync_end - 1) << 16) | (vsync_start - 1));
VML_WRITE32(par, VML_DSPCSTRIDE, vinfo->stride);
VML_WRITE32(par, VML_DSPCSIZE,
((var->yres - 1) << 16) | (var->xres - 1));
VML_WRITE32(par, VML_DSPCPOS, 0x00000000);
VML_WRITE32(par, VML_DSPARB, VML_FIFO_DEFAULT);
VML_WRITE32(par, VML_BCLRPAT_A, 0x00000000);
VML_WRITE32(par, VML_CANVSCLR_A, 0x00000000);
VML_WRITE32(par, VML_PIPEASRC,
((var->xres - 1) << 16) | (var->yres - 1));
wmb();
VML_WRITE32(par, VML_PIPEACONF, VML_PIPE_ENABLE);
wmb();
VML_WRITE32(par, VML_DSPCCNTR, dspcntr);
wmb();
VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
var->yoffset * vinfo->stride +
var->xoffset * vinfo->bytes_per_pixel);
VML_WRITE32(par, VML_RCOMPSTAT, VML_MDVO_PAD_ENABLE);
while (!(VML_READ32(par, VML_RCOMPSTAT) &
(VML_MDVO_VDC_I_RCOMP | VML_MDVO_PAD_ENABLE))) ;
vinfo->pipe_disabled = 0;
#ifdef VERMILION_DEBUG
vml_dump_regs(vinfo);
#endif
return 0;
}
static int vmlfb_set_par(struct fb_info *info)
{
struct vml_info *vinfo = container_of(info, struct vml_info, info);
int ret;
mutex_lock(&vml_mutex);
list_move(&vinfo->head, (subsys) ? &global_has_mode : &global_no_mode);
ret = vmlfb_set_par_locked(vinfo);
mutex_unlock(&vml_mutex);
return ret;
}
static int vmlfb_blank_locked(struct vml_info *vinfo)
{
struct vml_par *par = vinfo->par;
u32 cur = VML_READ32(par, VML_PIPEACONF);
switch (vinfo->cur_blank_mode) {
case FB_BLANK_UNBLANK:
if (vinfo->pipe_disabled) {
vmlfb_set_par_locked(vinfo);
}
VML_WRITE32(par, VML_PIPEACONF, cur & ~VML_PIPE_FORCE_BORDER);
(void)VML_READ32(par, VML_PIPEACONF);
break;
case FB_BLANK_NORMAL:
if (vinfo->pipe_disabled) {
vmlfb_set_par_locked(vinfo);
}
VML_WRITE32(par, VML_PIPEACONF, cur | VML_PIPE_FORCE_BORDER);
(void)VML_READ32(par, VML_PIPEACONF);
break;
case FB_BLANK_VSYNC_SUSPEND:
case FB_BLANK_HSYNC_SUSPEND:
if (!vinfo->pipe_disabled) {
vmlfb_disable_pipe(vinfo);
}
break;
case FB_BLANK_POWERDOWN:
if (!vinfo->pipe_disabled) {
vmlfb_disable_pipe(vinfo);
}
break;
default:
return -EINVAL;
}
return 0;
}
static int vmlfb_blank(int blank_mode, struct fb_info *info)
{
struct vml_info *vinfo = container_of(info, struct vml_info, info);
int ret;
mutex_lock(&vml_mutex);
vinfo->cur_blank_mode = blank_mode;
ret = vmlfb_blank_locked(vinfo);
mutex_unlock(&vml_mutex);
return ret;
}
static int vmlfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct vml_info *vinfo = container_of(info, struct vml_info, info);
struct vml_par *par = vinfo->par;
mutex_lock(&vml_mutex);
VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
var->yoffset * vinfo->stride +
var->xoffset * vinfo->bytes_per_pixel);
(void)VML_READ32(par, VML_DSPCADDR);
mutex_unlock(&vml_mutex);
return 0;
}
static int vmlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
u32 v;
if (regno >= 16)
return -EINVAL;
if (info->var.grayscale) {
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
if (info->fix.visual != FB_VISUAL_TRUECOLOR)
return -EINVAL;
red = VML_TOHW(red, info->var.red.length);
blue = VML_TOHW(blue, info->var.blue.length);
green = VML_TOHW(green, info->var.green.length);
transp = VML_TOHW(transp, info->var.transp.length);
v = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
switch (info->var.bits_per_pixel) {
case 16:
((u32 *) info->pseudo_palette)[regno] = v;
break;
case 24:
case 32:
((u32 *) info->pseudo_palette)[regno] = v;
break;
}
return 0;
}
static int vmlfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct vml_info *vinfo = container_of(info, struct vml_info, info);
unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
int ret;
unsigned long prot;
ret = vmlfb_vram_offset(vinfo, offset);
if (ret)
return -EINVAL;
prot = pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK;
pgprot_val(vma->vm_page_prot) =
prot | cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS);
return vm_iomap_memory(vma, vinfo->vram_start,
vinfo->vram_contig_size);
}
static int vmlfb_sync(struct fb_info *info)
{
return 0;
}
static int vmlfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
return -EINVAL; /* just to force soft_cursor() call */
}
static struct fb_ops vmlfb_ops = {
.owner = THIS_MODULE,
.fb_open = vmlfb_open,
.fb_release = vmlfb_release,
.fb_check_var = vmlfb_check_var,
.fb_set_par = vmlfb_set_par,
.fb_blank = vmlfb_blank,
.fb_pan_display = vmlfb_pan_display,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_cursor = vmlfb_cursor,
.fb_sync = vmlfb_sync,
.fb_mmap = vmlfb_mmap,
.fb_setcolreg = vmlfb_setcolreg
};
static const struct pci_device_id vml_ids[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, VML_DEVICE_VDC)},
{0}
};
static struct pci_driver vmlfb_pci_driver = {
.name = "vmlfb",
.id_table = vml_ids,
.probe = vml_pci_probe,
.remove = vml_pci_remove,
};
static void __exit vmlfb_cleanup(void)
{
pci_unregister_driver(&vmlfb_pci_driver);
}
static int __init vmlfb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("vmlfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options(MODULE_NAME, &option))
return -ENODEV;
#endif
printk(KERN_DEBUG MODULE_NAME ": initializing\n");
mutex_init(&vml_mutex);
INIT_LIST_HEAD(&global_no_mode);
INIT_LIST_HEAD(&global_has_mode);
return pci_register_driver(&vmlfb_pci_driver);
}
int vmlfb_register_subsys(struct vml_sys *sys)
{
struct vml_info *entry;
struct list_head *list;
u32 save_activate;
mutex_lock(&vml_mutex);
if (subsys != NULL) {
subsys->restore(subsys);
}
subsys = sys;
subsys->save(subsys);
/*
* We need to restart list traversal for each item, since we
* release the list mutex in the loop.
*/
list = global_no_mode.next;
while (list != &global_no_mode) {
list_del_init(list);
entry = list_entry(list, struct vml_info, head);
/*
* First, try the current mode which might not be
* completely validated with respect to the pixel clock.
*/
if (!vmlfb_check_var_locked(&entry->info.var, entry)) {
vmlfb_set_par_locked(entry);
list_add_tail(list, &global_has_mode);
} else {
/*
* Didn't work. Try to find another mode,
* that matches this subsys.
*/
mutex_unlock(&vml_mutex);
save_activate = entry->info.var.activate;
entry->info.var.bits_per_pixel = 16;
vmlfb_set_pref_pixel_format(&entry->info.var);
if (fb_find_mode(&entry->info.var,
&entry->info,
vml_default_mode, NULL, 0, NULL, 16)) {
entry->info.var.activate |=
FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
fb_set_var(&entry->info, &entry->info.var);
} else {
printk(KERN_ERR MODULE_NAME
": Sorry. no mode found for this subsys.\n");
}
entry->info.var.activate = save_activate;
mutex_lock(&vml_mutex);
}
vmlfb_blank_locked(entry);
list = global_no_mode.next;
}
mutex_unlock(&vml_mutex);
printk(KERN_DEBUG MODULE_NAME ": Registered %s subsystem.\n",
subsys->name ? subsys->name : "unknown");
return 0;
}
EXPORT_SYMBOL_GPL(vmlfb_register_subsys);
void vmlfb_unregister_subsys(struct vml_sys *sys)
{
struct vml_info *entry, *next;
mutex_lock(&vml_mutex);
if (subsys != sys) {
mutex_unlock(&vml_mutex);
return;
}
subsys->restore(subsys);
subsys = NULL;
list_for_each_entry_safe(entry, next, &global_has_mode, head) {
printk(KERN_DEBUG MODULE_NAME ": subsys disable pipe\n");
vmlfb_disable_pipe(entry);
list_move_tail(&entry->head, &global_no_mode);
}
mutex_unlock(&vml_mutex);
}
EXPORT_SYMBOL_GPL(vmlfb_unregister_subsys);
module_init(vmlfb_init);
module_exit(vmlfb_cleanup);
MODULE_AUTHOR("Tungsten Graphics");
MODULE_DESCRIPTION("Initialization of the Vermilion display devices");
MODULE_VERSION("1.0.0");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/vermilion/vermilion.c |
/*
* linux/drivers/video/kyro/STG4000OverlayDevice.c
*
* Copyright (C) 2000 Imagination Technologies Ltd
* Copyright (C) 2002 STMicroelectronics
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/types.h>
#include "STG4000Reg.h"
#include "STG4000Interface.h"
/* HW Defines */
#define STG4000_NO_SCALING 0x800
#define STG4000_NO_DECIMATION 0xFFFFFFFF
/* Primary surface */
#define STG4000_PRIM_NUM_PIX 5
#define STG4000_PRIM_ALIGN 4
#define STG4000_PRIM_ADDR_BITS 20
#define STG4000_PRIM_MIN_WIDTH 640
#define STG4000_PRIM_MAX_WIDTH 1600
#define STG4000_PRIM_MIN_HEIGHT 480
#define STG4000_PRIM_MAX_HEIGHT 1200
/* Overlay surface */
#define STG4000_OVRL_NUM_PIX 4
#define STG4000_OVRL_ALIGN 2
#define STG4000_OVRL_ADDR_BITS 20
#define STG4000_OVRL_NUM_MODES 5
#define STG4000_OVRL_MIN_WIDTH 0
#define STG4000_OVRL_MAX_WIDTH 720
#define STG4000_OVRL_MIN_HEIGHT 0
#define STG4000_OVRL_MAX_HEIGHT 576
/* Decimation and Scaling */
static u32 adwDecim8[33] = {
0xffffffff, 0xfffeffff, 0xffdffbff, 0xfefefeff, 0xfdf7efbf,
0xfbdf7bdf, 0xf7bbddef, 0xeeeeeeef, 0xeeddbb77, 0xedb76db7,
0xdb6db6db, 0xdb5b5b5b, 0xdab5ad6b, 0xd5ab55ab, 0xd555aaab,
0xaaaaaaab, 0xaaaa5555, 0xaa952a55, 0xa94a5295, 0xa5252525,
0xa4924925, 0x92491249, 0x91224489, 0x91111111, 0x90884211,
0x88410821, 0x88102041, 0x81010101, 0x80800801, 0x80010001,
0x80000001, 0x00000001, 0x00000000
};
typedef struct _OVRL_SRC_DEST {
/*clipped on-screen pixel position of overlay */
u32 ulDstX1;
u32 ulDstY1;
u32 ulDstX2;
u32 ulDstY2;
/*clipped pixel pos of source data within buffer thses need to be 128 bit word aligned */
u32 ulSrcX1;
u32 ulSrcY1;
u32 ulSrcX2;
u32 ulSrcY2;
/* on-screen pixel position of overlay */
s32 lDstX1;
s32 lDstY1;
s32 lDstX2;
s32 lDstY2;
} OVRL_SRC_DEST;
static u32 ovlWidth, ovlHeight, ovlStride;
static int ovlLinear;
void ResetOverlayRegisters(volatile STG4000REG __iomem *pSTGReg)
{
u32 tmp;
/* Set Overlay address to default */
tmp = STG_READ_REG(DACOverlayAddr);
CLEAR_BITS_FRM_TO(0, 20);
CLEAR_BIT(31);
STG_WRITE_REG(DACOverlayAddr, tmp);
/* Set Overlay U address */
tmp = STG_READ_REG(DACOverlayUAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACOverlayUAddr, tmp);
/* Set Overlay V address */
tmp = STG_READ_REG(DACOverlayVAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACOverlayVAddr, tmp);
/* Set Overlay Size */
tmp = STG_READ_REG(DACOverlaySize);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(12, 31);
STG_WRITE_REG(DACOverlaySize, tmp);
/* Set Overlay Vt Decimation */
tmp = STG4000_NO_DECIMATION;
STG_WRITE_REG(DACOverlayVtDec, tmp);
/* Set Overlay format to default value */
tmp = STG_READ_REG(DACPixelFormat);
CLEAR_BITS_FRM_TO(4, 7);
CLEAR_BITS_FRM_TO(16, 22);
STG_WRITE_REG(DACPixelFormat, tmp);
/* Set Vertical scaling to default */
tmp = STG_READ_REG(DACVerticalScal);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 22);
tmp |= STG4000_NO_SCALING; /* Set to no scaling */
STG_WRITE_REG(DACVerticalScal, tmp);
/* Set Horizontal Scaling to default */
tmp = STG_READ_REG(DACHorizontalScal);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 17);
tmp |= STG4000_NO_SCALING; /* Set to no scaling */
STG_WRITE_REG(DACHorizontalScal, tmp);
/* Set Blend mode to Alpha Blend */
/* ????? SG 08/11/2001 Surely this isn't the alpha blend mode,
hopefully its overwrite
*/
tmp = STG_READ_REG(DACBlendCtrl);
CLEAR_BITS_FRM_TO(0, 30);
tmp = (GRAPHICS_MODE << 28);
STG_WRITE_REG(DACBlendCtrl, tmp);
}
int CreateOverlaySurface(volatile STG4000REG __iomem *pSTGReg,
u32 inWidth,
u32 inHeight,
int bLinear,
u32 ulOverlayOffset,
u32 * retStride, u32 * retUVStride)
{
u32 tmp;
u32 ulStride;
if (inWidth > STG4000_OVRL_MAX_WIDTH ||
inHeight > STG4000_OVRL_MAX_HEIGHT) {
return -EINVAL;
}
/* Stride in 16 byte words - 16Bpp */
if (bLinear) {
/* Format is 16bits so num 16 byte words is width/8 */
if ((inWidth & 0x7) == 0) { /* inWidth % 8 */
ulStride = (inWidth / 8);
} else {
/* Round up to next 16byte boundary */
ulStride = ((inWidth + 8) / 8);
}
} else {
/* Y component is 8bits so num 16 byte words is width/16 */
if ((inWidth & 0xf) == 0) { /* inWidth % 16 */
ulStride = (inWidth / 16);
} else {
/* Round up to next 16byte boundary */
ulStride = ((inWidth + 16) / 16);
}
}
/* Set Overlay address and Format mode */
tmp = STG_READ_REG(DACOverlayAddr);
CLEAR_BITS_FRM_TO(0, 20);
if (bLinear) {
CLEAR_BIT(31); /* Overlay format to Linear */
} else {
tmp |= SET_BIT(31); /* Overlay format to Planer */
}
/* Only bits 24:4 of the Overlay address */
tmp |= (ulOverlayOffset >> 4);
STG_WRITE_REG(DACOverlayAddr, tmp);
if (!bLinear) {
u32 uvSize =
(inWidth & 0x1) ? (inWidth + 1 / 2) : (inWidth / 2);
u32 uvStride;
u32 ulOffset;
/* Y component is 8bits so num 32 byte words is width/32 */
if ((uvSize & 0xf) == 0) { /* inWidth % 16 */
uvStride = (uvSize / 16);
} else {
/* Round up to next 32byte boundary */
uvStride = ((uvSize + 16) / 16);
}
ulOffset = ulOverlayOffset + (inHeight * (ulStride * 16));
/* Align U,V data to 32byte boundary */
if ((ulOffset & 0x1f) != 0)
ulOffset = (ulOffset + 32L) & 0xffffffE0L;
tmp = STG_READ_REG(DACOverlayUAddr);
CLEAR_BITS_FRM_TO(0, 20);
tmp |= (ulOffset >> 4);
STG_WRITE_REG(DACOverlayUAddr, tmp);
ulOffset += (inHeight / 2) * (uvStride * 16);
/* Align U,V data to 32byte boundary */
if ((ulOffset & 0x1f) != 0)
ulOffset = (ulOffset + 32L) & 0xffffffE0L;
tmp = STG_READ_REG(DACOverlayVAddr);
CLEAR_BITS_FRM_TO(0, 20);
tmp |= (ulOffset >> 4);
STG_WRITE_REG(DACOverlayVAddr, tmp);
*retUVStride = uvStride * 16;
}
/* Set Overlay YUV pixel format
* Make sure that LUT not used - ??????
*/
tmp = STG_READ_REG(DACPixelFormat);
/* Only support Planer or UYVY linear formats */
CLEAR_BITS_FRM_TO(4, 9);
STG_WRITE_REG(DACPixelFormat, tmp);
ovlWidth = inWidth;
ovlHeight = inHeight;
ovlStride = ulStride;
ovlLinear = bLinear;
*retStride = ulStride << 4; /* In bytes */
return 0;
}
int SetOverlayBlendMode(volatile STG4000REG __iomem *pSTGReg,
OVRL_BLEND_MODE mode,
u32 ulAlpha, u32 ulColorKey)
{
u32 tmp;
tmp = STG_READ_REG(DACBlendCtrl);
CLEAR_BITS_FRM_TO(28, 30);
tmp |= (mode << 28);
switch (mode) {
case COLOR_KEY:
CLEAR_BITS_FRM_TO(0, 23);
tmp |= (ulColorKey & 0x00FFFFFF);
break;
case GLOBAL_ALPHA:
CLEAR_BITS_FRM_TO(24, 27);
tmp |= ((ulAlpha & 0xF) << 24);
break;
case CK_PIXEL_ALPHA:
CLEAR_BITS_FRM_TO(0, 23);
tmp |= (ulColorKey & 0x00FFFFFF);
break;
case CK_GLOBAL_ALPHA:
CLEAR_BITS_FRM_TO(0, 23);
tmp |= (ulColorKey & 0x00FFFFFF);
CLEAR_BITS_FRM_TO(24, 27);
tmp |= ((ulAlpha & 0xF) << 24);
break;
case GRAPHICS_MODE:
case PER_PIXEL_ALPHA:
break;
default:
return -EINVAL;
}
STG_WRITE_REG(DACBlendCtrl, tmp);
return 0;
}
void EnableOverlayPlane(volatile STG4000REG __iomem *pSTGReg)
{
u32 tmp;
/* Enable Overlay */
tmp = STG_READ_REG(DACPixelFormat);
tmp |= SET_BIT(7);
STG_WRITE_REG(DACPixelFormat, tmp);
/* Set video stream control */
tmp = STG_READ_REG(DACStreamCtrl);
tmp |= SET_BIT(1); /* video stream */
STG_WRITE_REG(DACStreamCtrl, tmp);
}
static u32 Overlap(u32 ulBits, u32 ulPattern)
{
u32 ulCount = 0;
while (ulBits) {
if (!(ulPattern & 1))
ulCount++;
ulBits--;
ulPattern = ulPattern >> 1;
}
return ulCount;
}
int SetOverlayViewPort(volatile STG4000REG __iomem *pSTGReg,
u32 left, u32 top,
u32 right, u32 bottom)
{
OVRL_SRC_DEST srcDest;
u32 ulSrcTop, ulSrcBottom;
u32 ulSrc, ulDest;
u32 ulFxScale, ulFxOffset;
u32 ulHeight, ulWidth;
u32 ulPattern;
u32 ulDecimate, ulDecimated;
u32 ulApplied;
u32 ulDacXScale, ulDacYScale;
u32 ulScale;
u32 ulLeft, ulRight;
u32 ulSrcLeft, ulSrcRight;
u32 ulScaleLeft;
u32 ulhDecim;
u32 ulsVal;
u32 ulVertDecFactor;
int bResult;
u32 ulClipOff = 0;
u32 ulBits = 0;
u32 ulsAdd = 0;
u32 tmp, ulStride;
u32 ulExcessPixels, ulClip, ulExtraLines;
srcDest.ulSrcX1 = 0;
srcDest.ulSrcY1 = 0;
srcDest.ulSrcX2 = ovlWidth - 1;
srcDest.ulSrcY2 = ovlHeight - 1;
srcDest.ulDstX1 = left;
srcDest.ulDstY1 = top;
srcDest.ulDstX2 = right;
srcDest.ulDstY2 = bottom;
srcDest.lDstX1 = srcDest.ulDstX1;
srcDest.lDstY1 = srcDest.ulDstY1;
srcDest.lDstX2 = srcDest.ulDstX2;
srcDest.lDstY2 = srcDest.ulDstY2;
/************* Vertical decimation/scaling ******************/
/* Get Src Top and Bottom */
ulSrcTop = srcDest.ulSrcY1;
ulSrcBottom = srcDest.ulSrcY2;
ulSrc = ulSrcBottom - ulSrcTop;
ulDest = srcDest.lDstY2 - srcDest.lDstY1; /* on-screen overlay */
if (ulSrc <= 1)
return -EINVAL;
/* First work out the position we are to display as offset from the
* source of the buffer
*/
ulFxScale = (ulDest << 11) / ulSrc; /* fixed point scale factor */
ulFxOffset = (srcDest.lDstY2 - srcDest.ulDstY2) << 11;
ulSrcBottom = ulSrcBottom - (ulFxOffset / ulFxScale);
ulSrc = ulSrcBottom - ulSrcTop;
ulHeight = ulSrc;
ulDest = srcDest.ulDstY2 - (srcDest.ulDstY1 - 1);
ulPattern = adwDecim8[ulBits];
/* At this point ulSrc represents the input decimator */
if (ulSrc > ulDest) {
ulDecimate = ulSrc - ulDest;
ulBits = 0;
ulApplied = ulSrc / 32;
while (((ulBits * ulApplied) +
Overlap((ulSrc % 32),
adwDecim8[ulBits])) < ulDecimate)
ulBits++;
ulPattern = adwDecim8[ulBits];
ulDecimated =
(ulBits * ulApplied) + Overlap((ulSrc % 32),
ulPattern);
ulSrc = ulSrc - ulDecimated; /* the number number of lines that will go into the scaler */
}
if (ulBits && (ulBits != 32)) {
ulVertDecFactor = (63 - ulBits) / (32 - ulBits); /* vertical decimation factor scaled up to nearest integer */
} else {
ulVertDecFactor = 1;
}
ulDacYScale = ((ulSrc - 1) * 2048) / (ulDest + 1);
tmp = STG_READ_REG(DACOverlayVtDec); /* Decimation */
CLEAR_BITS_FRM_TO(0, 31);
tmp = ulPattern;
STG_WRITE_REG(DACOverlayVtDec, tmp);
/***************** Horizontal decimation/scaling ***************************/
/*
* Now we handle the horizontal case, this is a simplified version of
* the vertical case in that we decimate by factors of 2. as we are
* working in words we should always be able to decimate by these
* factors. as we always have to have a buffer which is aligned to a
* whole number of 128 bit words, we must align the left side to the
* lowest to the next lowest 128 bit boundary, and the right hand edge
* to the next largets boundary, (in a similar way to how we didi it in
* PMX1) as the left and right hand edges are aligned to these
* boundaries normally this only becomes an issue when we are chopping
* of one of the sides We shall work out vertical stuff first
*/
ulSrc = srcDest.ulSrcX2 - srcDest.ulSrcX1;
ulDest = srcDest.lDstX2 - srcDest.lDstX1;
#ifdef _OLDCODE
ulLeft = srcDest.ulDstX1;
ulRight = srcDest.ulDstX2;
#else
if (srcDest.ulDstX1 > 2) {
ulLeft = srcDest.ulDstX1 + 2;
ulRight = srcDest.ulDstX2 + 1;
} else {
ulLeft = srcDest.ulDstX1;
ulRight = srcDest.ulDstX2 + 1;
}
#endif
/* first work out the position we are to display as offset from the source of the buffer */
bResult = 1;
do {
if (ulDest == 0)
return -EINVAL;
/* source pixels per dest pixel <<11 */
ulFxScale = ((ulSrc - 1) << 11) / (ulDest);
/* then number of destination pixels out we are */
ulFxOffset = ulFxScale * ((srcDest.ulDstX1 - srcDest.lDstX1) + ulClipOff);
ulFxOffset >>= 11;
/* this replaces the code which was making a decision as to use either ulFxOffset or ulSrcX1 */
ulSrcLeft = srcDest.ulSrcX1 + ulFxOffset;
/* then number of destination pixels out we are */
ulFxOffset = ulFxScale * (srcDest.lDstX2 - srcDest.ulDstX2);
ulFxOffset >>= 11;
ulSrcRight = srcDest.ulSrcX2 - ulFxOffset;
/*
* we must align these to our 128 bit boundaries. we shall
* round down the pixel pos to the nearest 8 pixels.
*/
ulScaleLeft = ulSrcLeft;
/* shift fxscale until it is in the range of the scaler */
ulhDecim = 0;
ulScale = (((ulSrcRight - ulSrcLeft) - 1) << (11 - ulhDecim)) / (ulRight - ulLeft + 2);
while (ulScale > 0x800) {
ulhDecim++;
ulScale = (((ulSrcRight - ulSrcLeft) - 1) << (11 - ulhDecim)) / (ulRight - ulLeft + 2);
}
/*
* to try and get the best values We first try and use
* src/dwdest for the scale factor, then we move onto src-1
*
* we want to check to see if we will need to clip data, if so
* then we should clip our source so that we don't need to
*/
if (!ovlLinear) {
ulSrcLeft &= ~0x1f;
/*
* we must align the right hand edge to the next 32
* pixel` boundary, must be on a 256 boundary so u, and
* v are 128 bit aligned
*/
ulSrcRight = (ulSrcRight + 0x1f) & ~0x1f;
} else {
ulSrcLeft &= ~0x7;
/*
* we must align the right hand edge to the next
* 8pixel` boundary
*/
ulSrcRight = (ulSrcRight + 0x7) & ~0x7;
}
/* this is the input size line store needs to cope with */
ulWidth = ulSrcRight - ulSrcLeft;
/*
* use unclipped value to work out scale factror this is the
* scale factor we want we shall now work out the horizonal
* decimation and scaling
*/
ulsVal = ((ulWidth / 8) >> ulhDecim);
if ((ulWidth != (ulsVal << ulhDecim) * 8))
ulsAdd = 1;
/* input pixels to scaler; */
ulSrc = ulWidth >> ulhDecim;
if (ulSrc <= 2)
return -EINVAL;
ulExcessPixels = ((((ulScaleLeft - ulSrcLeft)) << (11 - ulhDecim)) / ulScale);
ulClip = (ulSrc << 11) / ulScale;
ulClip -= (ulRight - ulLeft);
ulClip += ulExcessPixels;
if (ulClip)
ulClip--;
/* We may need to do more here if we really have a HW rev < 5 */
} while (!bResult);
ulExtraLines = (1 << ulhDecim) * ulVertDecFactor;
ulExtraLines += 64;
ulHeight += ulExtraLines;
ulDacXScale = ulScale;
tmp = STG_READ_REG(DACVerticalScal);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 22); /* Vertical Scaling */
/* Calculate new output line stride, this is always the number of 422
words in the line buffer, so it doesn't matter if the
mode is 420. Then set the vertical scale register.
*/
ulStride = (ulWidth >> (ulhDecim + 3)) + ulsAdd;
tmp |= ((ulStride << 16) | (ulDacYScale)); /* DAC_LS_CTRL = stride */
STG_WRITE_REG(DACVerticalScal, tmp);
/* Now set up the overlay size using the modified width and height
from decimate and scaling calculations
*/
tmp = STG_READ_REG(DACOverlaySize);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(12, 31);
if (ovlLinear) {
tmp |=
(ovlStride | ((ulHeight + 1) << 12) |
(((ulWidth / 8) - 1) << 23));
} else {
tmp |=
(ovlStride | ((ulHeight + 1) << 12) |
(((ulWidth / 32) - 1) << 23));
}
STG_WRITE_REG(DACOverlaySize, tmp);
/* Set Video Window Start */
tmp = ((ulLeft << 16)) | (srcDest.ulDstY1);
STG_WRITE_REG(DACVidWinStart, tmp);
/* Set Video Window End */
tmp = ((ulRight) << 16) | (srcDest.ulDstY2);
STG_WRITE_REG(DACVidWinEnd, tmp);
/* Finally set up the rest of the overlay regs in the order
done in the IMG driver
*/
tmp = STG_READ_REG(DACPixelFormat);
tmp = ((ulExcessPixels << 16) | tmp) & 0x7fffffff;
STG_WRITE_REG(DACPixelFormat, tmp);
tmp = STG_READ_REG(DACHorizontalScal);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 17);
tmp |= ((ulhDecim << 16) | (ulDacXScale));
STG_WRITE_REG(DACHorizontalScal, tmp);
return 0;
}
| linux-master | drivers/video/fbdev/kyro/STG4000OverlayDevice.c |
/*
* linux/drivers/video/kyro/fbdev.c
*
* Copyright (C) 2002 STMicroelectronics
* Copyright (C) 2003, 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/ioctl.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <video/kyro.h>
#include "STG4000Reg.h"
#include "STG4000Interface.h"
/*
* PCI Definitions
*/
#define PCI_VENDOR_ID_ST 0x104a
#define PCI_DEVICE_ID_STG4000 0x0010
#define KHZ2PICOS(a) (1000000000UL/(a))
/****************************************************************************/
static struct fb_fix_screeninfo kyro_fix = {
.id = "ST Kyro",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.accel = FB_ACCEL_NONE,
};
static const struct fb_var_screeninfo kyro_var = {
/* 640x480, 16bpp @ 60 Hz */
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel = 16,
.red = { 11, 5, 0 },
.green = { 5, 6, 0 },
.blue = { 0, 5, 0 },
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.pixclock = KHZ2PICOS(25175),
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED,
};
typedef struct {
STG4000REG __iomem *pSTGReg; /* Virtual address of PCI register region */
u32 ulNextFreeVidMem; /* Offset from start of vid mem to next free region */
u32 ulOverlayOffset; /* Offset from start of vid mem to overlay */
u32 ulOverlayStride; /* Interleaved YUV and 422 mode Y stride */
u32 ulOverlayUVStride; /* 422 mode U & V stride */
} device_info_t;
/* global graphics card info structure (one per card) */
static device_info_t deviceInfo;
static char *mode_option = NULL;
static int nopan = 0;
static int nowrap = 1;
static int nomtrr = 0;
/* PCI driver prototypes */
static int kyrofb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
static void kyrofb_remove(struct pci_dev *pdev);
static struct fb_videomode kyro_modedb[] = {
{
/* 640x350 @ 85Hz */
NULL, 85, 640, 350, KHZ2PICOS(31500),
96, 32, 60, 32, 64, 3,
FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 640x400 @ 85Hz */
NULL, 85, 640, 400, KHZ2PICOS(31500),
96, 32, 41, 1, 64, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 720x400 @ 85Hz */
NULL, 85, 720, 400, KHZ2PICOS(35500),
108, 36, 42, 1, 72, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 60Hz */
NULL, 60, 640, 480, KHZ2PICOS(25175),
48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 72Hz */
NULL, 72, 640, 480, KHZ2PICOS(31500),
128, 24, 28, 9, 40, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 75Hz */
NULL, 75, 640, 480, KHZ2PICOS(31500),
120, 16, 16, 1, 64, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 640x480 @ 85Hz */
NULL, 85, 640, 480, KHZ2PICOS(36000),
80, 56, 25, 1, 56, 3,
0, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 56Hz */
NULL, 56, 800, 600, KHZ2PICOS(36000),
128, 24, 22, 1, 72, 2,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 60Hz */
NULL, 60, 800, 600, KHZ2PICOS(40000),
88, 40, 23, 1, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 72Hz */
NULL, 72, 800, 600, KHZ2PICOS(50000),
64, 56, 23, 37, 120, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 75Hz */
NULL, 75, 800, 600, KHZ2PICOS(49500),
160, 16, 21, 1, 80, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 800x600 @ 85Hz */
NULL, 85, 800, 600, KHZ2PICOS(56250),
152, 32, 27, 1, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 60Hz */
NULL, 60, 1024, 768, KHZ2PICOS(65000),
160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 70Hz */
NULL, 70, 1024, 768, KHZ2PICOS(75000),
144, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 75Hz */
NULL, 75, 1024, 768, KHZ2PICOS(78750),
176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1024x768 @ 85Hz */
NULL, 85, 1024, 768, KHZ2PICOS(94500),
208, 48, 36, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1152x864 @ 75Hz */
NULL, 75, 1152, 864, KHZ2PICOS(108000),
256, 64, 32, 1, 128, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1280x960 @ 60Hz */
NULL, 60, 1280, 960, KHZ2PICOS(108000),
312, 96, 36, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1280x960 @ 85Hz */
NULL, 85, 1280, 960, KHZ2PICOS(148500),
224, 64, 47, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 60Hz */
NULL, 60, 1280, 1024, KHZ2PICOS(108000),
248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 75Hz */
NULL, 75, 1280, 1024, KHZ2PICOS(135000),
248, 16, 38, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1280x1024 @ 85Hz */
NULL, 85, 1280, 1024, KHZ2PICOS(157500),
224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 60Hz */
NULL, 60, 1600, 1200, KHZ2PICOS(162000),
304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 65Hz */
NULL, 65, 1600, 1200, KHZ2PICOS(175500),
304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 70Hz */
NULL, 70, 1600, 1200, KHZ2PICOS(189000),
304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 75Hz */
NULL, 75, 1600, 1200, KHZ2PICOS(202500),
304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 85Hz */
NULL, 85, 1600, 1200, KHZ2PICOS(229500),
304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1792x1344 @ 60Hz */
NULL, 60, 1792, 1344, KHZ2PICOS(204750),
328, 128, 46, 1, 200, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1792x1344 @ 75Hz */
NULL, 75, 1792, 1344, KHZ2PICOS(261000),
352, 96, 69, 1, 216, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1856x1392 @ 60Hz */
NULL, 60, 1856, 1392, KHZ2PICOS(218250),
352, 96, 43, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1856x1392 @ 75Hz */
NULL, 75, 1856, 1392, KHZ2PICOS(288000),
352, 128, 104, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1920x1440 @ 60Hz */
NULL, 60, 1920, 1440, KHZ2PICOS(234000),
344, 128, 56, 1, 208, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1920x1440 @ 75Hz */
NULL, 75, 1920, 1440, KHZ2PICOS(297000),
352, 144, 56, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
},
};
#define NUM_TOTAL_MODES ARRAY_SIZE(kyro_modedb)
/*
* This needs to be kept ordered corresponding to kyro_modedb.
*/
enum {
VMODE_640_350_85,
VMODE_640_400_85,
VMODE_720_400_85,
VMODE_640_480_60,
VMODE_640_480_72,
VMODE_640_480_75,
VMODE_640_480_85,
VMODE_800_600_56,
VMODE_800_600_60,
VMODE_800_600_72,
VMODE_800_600_75,
VMODE_800_600_85,
VMODE_1024_768_60,
VMODE_1024_768_70,
VMODE_1024_768_75,
VMODE_1024_768_85,
VMODE_1152_864_75,
VMODE_1280_960_60,
VMODE_1280_960_85,
VMODE_1280_1024_60,
VMODE_1280_1024_75,
VMODE_1280_1024_85,
VMODE_1600_1200_60,
VMODE_1600_1200_65,
VMODE_1600_1200_70,
VMODE_1600_1200_75,
VMODE_1600_1200_85,
VMODE_1792_1344_60,
VMODE_1792_1344_75,
VMODE_1856_1392_60,
VMODE_1856_1392_75,
VMODE_1920_1440_60,
VMODE_1920_1440_75,
};
/* Accessors */
static int kyro_dev_video_mode_set(struct fb_info *info)
{
struct kyrofb_info *par = info->par;
/* Turn off display */
StopVTG(deviceInfo.pSTGReg);
DisableRamdacOutput(deviceInfo.pSTGReg);
/* Bring us out of VGA and into Hi-Res mode, if not already. */
DisableVGA(deviceInfo.pSTGReg);
if (InitialiseRamdac(deviceInfo.pSTGReg,
info->var.bits_per_pixel,
info->var.xres, info->var.yres,
par->HSP, par->VSP, &par->PIXCLK) < 0)
return -EINVAL;
SetupVTG(deviceInfo.pSTGReg, par);
ResetOverlayRegisters(deviceInfo.pSTGReg);
/* Turn on display in new mode */
EnableRamdacOutput(deviceInfo.pSTGReg);
StartVTG(deviceInfo.pSTGReg);
deviceInfo.ulNextFreeVidMem = info->var.xres * info->var.yres *
info->var.bits_per_pixel;
deviceInfo.ulOverlayOffset = 0;
return 0;
}
static int kyro_dev_overlay_create(u32 ulWidth,
u32 ulHeight, int bLinear)
{
u32 offset;
u32 stride, uvStride;
if (deviceInfo.ulOverlayOffset != 0)
/*
* Can only create one overlay without resetting the card or
* changing display mode
*/
return -EINVAL;
ResetOverlayRegisters(deviceInfo.pSTGReg);
/* Overlays are addressed in multiples of 16bytes or 32bytes, so make
* sure the start offset is on an appropriate boundary.
*/
offset = deviceInfo.ulNextFreeVidMem;
if ((offset & 0x1f) != 0) {
offset = (offset + 32L) & 0xffffffE0L;
}
if (CreateOverlaySurface(deviceInfo.pSTGReg, ulWidth, ulHeight,
bLinear, offset, &stride, &uvStride) < 0)
return -EINVAL;
deviceInfo.ulOverlayOffset = offset;
deviceInfo.ulOverlayStride = stride;
deviceInfo.ulOverlayUVStride = uvStride;
deviceInfo.ulNextFreeVidMem = offset + (ulHeight * stride) + (ulHeight * 2 * uvStride);
SetOverlayBlendMode(deviceInfo.pSTGReg, GLOBAL_ALPHA, 0xf, 0x0);
return 0;
}
static int kyro_dev_overlay_viewport_set(u32 x, u32 y, u32 ulWidth, u32 ulHeight)
{
if (deviceInfo.ulOverlayOffset == 0)
/* probably haven't called CreateOverlay yet */
return -EINVAL;
if (ulWidth == 0 || ulWidth == 0xffffffff ||
ulHeight == 0 || ulHeight == 0xffffffff ||
(x < 2 && ulWidth + 2 == 0))
return -EINVAL;
/* Stop Ramdac Output */
DisableRamdacOutput(deviceInfo.pSTGReg);
SetOverlayViewPort(deviceInfo.pSTGReg,
x, y, x + ulWidth - 1, y + ulHeight - 1);
EnableOverlayPlane(deviceInfo.pSTGReg);
/* Start Ramdac Output */
EnableRamdacOutput(deviceInfo.pSTGReg);
return 0;
}
static inline unsigned long get_line_length(int x, int bpp)
{
return (unsigned long)((((x*bpp)+31)&~31) >> 3);
}
static int kyrofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct kyrofb_info *par = info->par;
if (!var->pixclock)
return -EINVAL;
if (var->bits_per_pixel != 16 && var->bits_per_pixel != 32) {
printk(KERN_WARNING "kyrofb: depth not supported: %u\n", var->bits_per_pixel);
return -EINVAL;
}
switch (var->bits_per_pixel) {
case 16:
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.length = 5;
break;
case 32:
var->transp.offset = 24;
var->red.offset = 16;
var->green.offset = 8;
var->blue.offset = 0;
var->red.length = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.length = 8;
break;
}
/* Height/Width of picture in mm */
var->height = var->width = -1;
/* Timing information. All values are in picoseconds */
/* par->PIXCLK is in 100Hz units. Convert to picoseconds -
* ensuring we do not exceed 32 bit precision
*/
/*
* XXX: Enabling this really screws over the pixclock value when we
* read it back with fbset. As such, leaving this commented out appears
* to do the right thing (at least for now) .. bearing in mind that we
* have infact already done the KHZ2PICOS conversion in both the modedb
* and kyro_var. -- PFM.
*/
// var->pixclock = 1000000000 / (par->PIXCLK / 10);
/* the header file claims we should use picoseconds
* - nobody else does though, the all use pixels and lines
* of h and v sizes. Both options here.
*/
/*
* If we're being called by __fb_try_mode(), then we don't want to
* override any of the var settings that we've already parsed
* from our modedb. -- PFM.
*/
if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_TEST)
return 0;
var->left_margin = par->HBP;
var->hsync_len = par->HST;
var->right_margin = par->HFP;
var->upper_margin = par->VBP;
var->vsync_len = par->VST;
var->lower_margin = par->VFP;
if (par->HSP == 1)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (par->VSP == 1)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
return 0;
}
static int kyrofb_set_par(struct fb_info *info)
{
struct kyrofb_info *par = info->par;
unsigned long lineclock;
unsigned long frameclock;
/* Actual resolution */
par->XRES = info->var.xres;
par->YRES = info->var.yres;
/* pixel depth */
par->PIXDEPTH = info->var.bits_per_pixel;
/* Refresh rate */
/* time for a line in ns */
lineclock = (info->var.pixclock * (info->var.xres +
info->var.right_margin +
info->var.hsync_len +
info->var.left_margin)) / 1000;
if (!lineclock)
return -EINVAL;
/* time for a frame in ns (precision in 32bpp) */
frameclock = lineclock * (info->var.yres +
info->var.lower_margin +
info->var.vsync_len +
info->var.upper_margin);
/* Calculate refresh rate and horrizontal clocks */
par->VFREQ = (1000000000 + (frameclock / 2)) / frameclock;
par->HCLK = (1000000000 + (lineclock / 2)) / lineclock;
par->PIXCLK = ((1000000000 + (info->var.pixclock / 2))
/ info->var.pixclock) * 10;
/* calculate horizontal timings */
par->HFP = info->var.right_margin;
par->HST = info->var.hsync_len;
par->HBP = info->var.left_margin;
par->HTot = par->XRES + par->HBP + par->HST + par->HFP;
/* calculate vertical timings */
par->VFP = info->var.lower_margin;
par->VST = info->var.vsync_len;
par->VBP = info->var.upper_margin;
par->VTot = par->YRES + par->VBP + par->VST + par->VFP;
par->HSP = (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 1 : 0;
par->VSP = (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 1 : 0;
kyro_dev_video_mode_set(info);
/* length of a line in bytes */
info->fix.line_length = get_line_length(par->XRES, par->PIXDEPTH);
info->fix.visual = FB_VISUAL_TRUECOLOR;
return 0;
}
static int kyrofb_setcolreg(u_int regno, u_int red, u_int green,
u_int blue, u_int transp, struct fb_info *info)
{
struct kyrofb_info *par = info->par;
if (regno > 255)
return 1; /* Invalid register */
if (regno < 16) {
switch (info->var.bits_per_pixel) {
case 16:
par->palette[regno] =
(red & 0xf800) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
break;
case 32:
red >>= 8; green >>= 8; blue >>= 8; transp >>= 8;
par->palette[regno] =
(transp << 24) | (red << 16) | (green << 8) | blue;
break;
}
}
return 0;
}
#ifndef MODULE
static int __init kyrofb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ","))) {
if (!*this_opt)
continue;
if (strcmp(this_opt, "nopan") == 0) {
nopan = 1;
} else if (strcmp(this_opt, "nowrap") == 0) {
nowrap = 1;
} else if (strcmp(this_opt, "nomtrr") == 0) {
nomtrr = 1;
} else {
mode_option = this_opt;
}
}
return 0;
}
#endif
static int kyrofb_ioctl(struct fb_info *info,
unsigned int cmd, unsigned long arg)
{
overlay_create ol_create;
overlay_viewport_set ol_viewport_set;
void __user *argp = (void __user *)arg;
switch (cmd) {
case KYRO_IOCTL_OVERLAY_CREATE:
if (copy_from_user(&ol_create, argp, sizeof(overlay_create)))
return -EFAULT;
if (kyro_dev_overlay_create(ol_create.ulWidth,
ol_create.ulHeight, 0) < 0) {
printk(KERN_ERR "Kyro FB: failed to create overlay surface.\n");
return -EINVAL;
}
break;
case KYRO_IOCTL_OVERLAY_VIEWPORT_SET:
if (copy_from_user(&ol_viewport_set, argp,
sizeof(overlay_viewport_set)))
return -EFAULT;
if (kyro_dev_overlay_viewport_set(ol_viewport_set.xOrgin,
ol_viewport_set.yOrgin,
ol_viewport_set.xSize,
ol_viewport_set.ySize) != 0)
{
printk(KERN_ERR "Kyro FB: failed to create overlay viewport.\n");
return -EINVAL;
}
break;
case KYRO_IOCTL_SET_VIDEO_MODE:
{
printk(KERN_ERR "Kyro FB: KYRO_IOCTL_SET_VIDEO_MODE is"
"obsolete, use the appropriate fb_ioctl()"
"command instead.\n");
return -EINVAL;
}
case KYRO_IOCTL_UVSTRIDE:
if (copy_to_user(argp, &deviceInfo.ulOverlayUVStride, sizeof(deviceInfo.ulOverlayUVStride)))
return -EFAULT;
break;
case KYRO_IOCTL_STRIDE:
if (copy_to_user(argp, &deviceInfo.ulOverlayStride, sizeof(deviceInfo.ulOverlayStride)))
return -EFAULT;
break;
case KYRO_IOCTL_OVERLAY_OFFSET:
if (copy_to_user(argp, &deviceInfo.ulOverlayOffset, sizeof(deviceInfo.ulOverlayOffset)))
return -EFAULT;
break;
}
return 0;
}
static const struct pci_device_id kyrofb_pci_tbl[] = {
{ PCI_VENDOR_ID_ST, PCI_DEVICE_ID_STG4000,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, kyrofb_pci_tbl);
static struct pci_driver kyrofb_pci_driver = {
.name = "kyrofb",
.id_table = kyrofb_pci_tbl,
.probe = kyrofb_probe,
.remove = kyrofb_remove,
};
static const struct fb_ops kyrofb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = kyrofb_check_var,
.fb_set_par = kyrofb_set_par,
.fb_setcolreg = kyrofb_setcolreg,
.fb_ioctl = kyrofb_ioctl,
};
static int kyrofb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct fb_info *info;
struct kyrofb_info *currentpar;
unsigned long size;
int err;
err = aperture_remove_conflicting_pci_devices(pdev, "kyrofb");
if (err)
return err;
if ((err = pci_enable_device(pdev))) {
printk(KERN_WARNING "kyrofb: Can't enable pdev: %d\n", err);
return err;
}
info = framebuffer_alloc(sizeof(struct kyrofb_info), &pdev->dev);
if (!info)
return -ENOMEM;
currentpar = info->par;
kyro_fix.smem_start = pci_resource_start(pdev, 0);
kyro_fix.smem_len = pci_resource_len(pdev, 0);
kyro_fix.mmio_start = pci_resource_start(pdev, 1);
kyro_fix.mmio_len = pci_resource_len(pdev, 1);
currentpar->regbase = deviceInfo.pSTGReg =
ioremap(kyro_fix.mmio_start, kyro_fix.mmio_len);
if (!currentpar->regbase)
goto out_free_fb;
info->screen_base = pci_ioremap_wc_bar(pdev, 0);
if (!info->screen_base)
goto out_unmap_regs;
if (!nomtrr)
currentpar->wc_cookie = arch_phys_wc_add(kyro_fix.smem_start,
kyro_fix.smem_len);
kyro_fix.ypanstep = nopan ? 0 : 1;
kyro_fix.ywrapstep = nowrap ? 0 : 1;
info->fbops = &kyrofb_ops;
info->fix = kyro_fix;
info->pseudo_palette = currentpar->palette;
SetCoreClockPLL(deviceInfo.pSTGReg, pdev);
deviceInfo.ulNextFreeVidMem = 0;
deviceInfo.ulOverlayOffset = 0;
/* This should give a reasonable default video mode */
if (!fb_find_mode(&info->var, info, mode_option, kyro_modedb,
NUM_TOTAL_MODES, &kyro_modedb[VMODE_1024_768_75], 32))
info->var = kyro_var;
fb_alloc_cmap(&info->cmap, 256, 0);
kyrofb_set_par(info);
kyrofb_check_var(&info->var, info);
size = get_line_length(info->var.xres_virtual,
info->var.bits_per_pixel);
size *= info->var.yres_virtual;
fb_memset_io(info->screen_base, 0, size);
if (register_framebuffer(info) < 0)
goto out_unmap;
fb_info(info, "%s frame buffer device, at %dx%d@%d using %ldk/%ldk of VRAM\n",
info->fix.id,
info->var.xres, info->var.yres, info->var.bits_per_pixel,
size >> 10, (unsigned long)info->fix.smem_len >> 10);
pci_set_drvdata(pdev, info);
return 0;
out_unmap:
iounmap(info->screen_base);
out_unmap_regs:
iounmap(currentpar->regbase);
out_free_fb:
framebuffer_release(info);
return -EINVAL;
}
static void kyrofb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct kyrofb_info *par = info->par;
/* Reset the board */
StopVTG(deviceInfo.pSTGReg);
DisableRamdacOutput(deviceInfo.pSTGReg);
/* Sync up the PLL */
SetCoreClockPLL(deviceInfo.pSTGReg, pdev);
deviceInfo.ulNextFreeVidMem = 0;
deviceInfo.ulOverlayOffset = 0;
iounmap(info->screen_base);
iounmap(par->regbase);
arch_phys_wc_del(par->wc_cookie);
unregister_framebuffer(info);
framebuffer_release(info);
}
static int __init kyrofb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("kyrofb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("kyrofb", &option))
return -ENODEV;
kyrofb_setup(option);
#endif
return pci_register_driver(&kyrofb_pci_driver);
}
static void __exit kyrofb_exit(void)
{
pci_unregister_driver(&kyrofb_pci_driver);
}
module_init(kyrofb_init);
#ifdef MODULE
module_exit(kyrofb_exit);
#endif
MODULE_AUTHOR("STMicroelectronics; Paul Mundt <[email protected]>");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/kyro/fbdev.c |
/*
* linux/drivers/video/kyro/STG4000VTG.c
*
* Copyright (C) 2002 STMicroelectronics
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/types.h>
#include <video/kyro.h>
#include "STG4000Reg.h"
#include "STG4000Interface.h"
void DisableVGA(volatile STG4000REG __iomem *pSTGReg)
{
u32 tmp;
volatile u32 count = 0, i;
/* Reset the VGA registers */
tmp = STG_READ_REG(SoftwareReset);
CLEAR_BIT(8);
STG_WRITE_REG(SoftwareReset, tmp);
/* Just for Delay */
for (i = 0; i < 1000; i++) {
count++;
}
/* Pull-out the VGA registers from reset */
tmp = STG_READ_REG(SoftwareReset);
tmp |= SET_BIT(8);
STG_WRITE_REG(SoftwareReset, tmp);
}
void StopVTG(volatile STG4000REG __iomem *pSTGReg)
{
u32 tmp = 0;
/* Stop Ver and Hor Sync Generator */
tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2);
CLEAR_BIT(31);
STG_WRITE_REG(DACSyncCtrl, tmp);
}
void StartVTG(volatile STG4000REG __iomem *pSTGReg)
{
u32 tmp = 0;
/* Start Ver and Hor Sync Generator */
tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31));
CLEAR_BIT(0);
CLEAR_BIT(2);
STG_WRITE_REG(DACSyncCtrl, tmp);
}
void SetupVTG(volatile STG4000REG __iomem *pSTGReg,
const struct kyrofb_info * pTiming)
{
u32 tmp = 0;
u32 margins = 0;
u32 ulBorder;
u32 xRes = pTiming->XRES;
u32 yRes = pTiming->YRES;
/* Horizontal */
u32 HAddrTime, HRightBorder, HLeftBorder;
u32 HBackPorcStrt, HFrontPorchStrt, HTotal,
HLeftBorderStrt, HRightBorderStrt, HDisplayStrt;
/* Vertical */
u32 VDisplayStrt, VBottomBorder, VTopBorder;
u32 VBackPorchStrt, VTotal, VTopBorderStrt,
VFrontPorchStrt, VBottomBorderStrt, VAddrTime;
/* Need to calculate the right border */
if ((xRes == 640) && (yRes == 480)) {
if ((pTiming->VFREQ == 60) || (pTiming->VFREQ == 72)) {
margins = 8;
}
}
/* Work out the Border */
ulBorder =
(pTiming->HTot -
(pTiming->HST + (pTiming->HBP - margins) + xRes +
(pTiming->HFP - margins))) >> 1;
/* Border the same for Vertical and Horizontal */
VBottomBorder = HLeftBorder = VTopBorder = HRightBorder = ulBorder;
/************ Get Timing values for Horizontal ******************/
HAddrTime = xRes;
HBackPorcStrt = pTiming->HST;
HTotal = pTiming->HTot;
HDisplayStrt =
pTiming->HST + (pTiming->HBP - margins) + HLeftBorder;
HLeftBorderStrt = HDisplayStrt - HLeftBorder;
HFrontPorchStrt =
pTiming->HST + (pTiming->HBP - margins) + HLeftBorder +
HAddrTime + HRightBorder;
HRightBorderStrt = HFrontPorchStrt - HRightBorder;
/************ Get Timing values for Vertical ******************/
VAddrTime = yRes;
VBackPorchStrt = pTiming->VST;
VTotal = pTiming->VTot;
VDisplayStrt =
pTiming->VST + (pTiming->VBP - margins) + VTopBorder;
VTopBorderStrt = VDisplayStrt - VTopBorder;
VFrontPorchStrt =
pTiming->VST + (pTiming->VBP - margins) + VTopBorder +
VAddrTime + VBottomBorder;
VBottomBorderStrt = VFrontPorchStrt - VBottomBorder;
/* Set Hor Timing 1, 2, 3 */
tmp = STG_READ_REG(DACHorTim1);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (HTotal) | (HBackPorcStrt << 16);
STG_WRITE_REG(DACHorTim1, tmp);
tmp = STG_READ_REG(DACHorTim2);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (HDisplayStrt << 16) | HLeftBorderStrt;
STG_WRITE_REG(DACHorTim2, tmp);
tmp = STG_READ_REG(DACHorTim3);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (HFrontPorchStrt << 16) | HRightBorderStrt;
STG_WRITE_REG(DACHorTim3, tmp);
/* Set Ver Timing 1, 2, 3 */
tmp = STG_READ_REG(DACVerTim1);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (VBackPorchStrt << 16) | (VTotal);
STG_WRITE_REG(DACVerTim1, tmp);
tmp = STG_READ_REG(DACVerTim2);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (VDisplayStrt << 16) | VTopBorderStrt;
STG_WRITE_REG(DACVerTim2, tmp);
tmp = STG_READ_REG(DACVerTim3);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (VFrontPorchStrt << 16) | VBottomBorderStrt;
STG_WRITE_REG(DACVerTim3, tmp);
/* Set Verical and Horizontal Polarity */
tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1);
if ((pTiming->HSP > 0) && (pTiming->VSP < 0)) { /* +hsync -vsync */
tmp &= ~0x8;
} else if ((pTiming->HSP < 0) && (pTiming->VSP > 0)) { /* -hsync +vsync */
tmp &= ~0x2;
} else if ((pTiming->HSP < 0) && (pTiming->VSP < 0)) { /* -hsync -vsync */
tmp &= ~0xA;
} else if ((pTiming->HSP > 0) && (pTiming->VSP > 0)) { /* +hsync -vsync */
tmp &= ~0x0;
}
STG_WRITE_REG(DACSyncCtrl, tmp);
}
| linux-master | drivers/video/fbdev/kyro/STG4000VTG.c |
/*
* linux/drivers/video/kyro/STG4000InitDevice.c
*
* Copyright (C) 2000 Imagination Technologies Ltd
* Copyright (C) 2002 STMicroelectronics
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/pci.h>
#include "STG4000Reg.h"
#include "STG4000Interface.h"
/* SDRAM fixed settings */
#define SDRAM_CFG_0 0x49A1
#define SDRAM_CFG_1 0xA732
#define SDRAM_CFG_2 0x31
#define SDRAM_ARB_CFG 0xA0
#define SDRAM_REFRESH 0x20
/* Reset values */
#define PMX2_SOFTRESET_DAC_RST 0x0001
#define PMX2_SOFTRESET_C1_RST 0x0004
#define PMX2_SOFTRESET_C2_RST 0x0008
#define PMX2_SOFTRESET_3D_RST 0x0010
#define PMX2_SOFTRESET_VIDIN_RST 0x0020
#define PMX2_SOFTRESET_TLB_RST 0x0040
#define PMX2_SOFTRESET_SD_RST 0x0080
#define PMX2_SOFTRESET_VGA_RST 0x0100
#define PMX2_SOFTRESET_ROM_RST 0x0200 /* reserved bit, do not reset */
#define PMX2_SOFTRESET_TA_RST 0x0400
#define PMX2_SOFTRESET_REG_RST 0x4000
#define PMX2_SOFTRESET_ALL 0x7fff
/* Core clock freq */
#define CORE_PLL_FREQ 1000000
/* Reference Clock freq */
#define REF_FREQ 14318
/* PCI Registers */
static u16 CorePllControl = 0x70;
#define PCI_CONFIG_SUBSYS_ID 0x2e
/* Misc */
#define CORE_PLL_MODE_REG_0_7 3
#define CORE_PLL_MODE_REG_8_15 2
#define CORE_PLL_MODE_CONFIG_REG 1
#define DAC_PLL_CONFIG_REG 0
#define STG_MAX_VCO 500000
#define STG_MIN_VCO 100000
/* PLL Clock */
#define STG4K3_PLL_SCALER 8 /* scale numbers by 2^8 for fixed point calc */
#define STG4K3_PLL_MIN_R 2 /* Minimum multiplier */
#define STG4K3_PLL_MAX_R 33 /* Max */
#define STG4K3_PLL_MIN_F 2 /* Minimum divisor */
#define STG4K3_PLL_MAX_F 513 /* Max */
#define STG4K3_PLL_MIN_OD 0 /* Min output divider (shift) */
#define STG4K3_PLL_MAX_OD 2 /* Max */
#define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
#define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
#define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
#define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
#define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
#define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
#define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
#define OS_DELAY(X) \
{ \
volatile u32 i,count=0; \
for(i=0;i<X;i++) count++; \
}
static u32 InitSDRAMRegisters(volatile STG4000REG __iomem *pSTGReg,
u32 dwSubSysID, u32 dwRevID)
{
static const u8 adwSDRAMArgCfg0[] = { 0xa0, 0x80, 0xa0, 0xa0, 0xa0 };
static const u16 adwSDRAMCfg1[] = { 0x8732, 0x8732, 0xa732, 0xa732, 0x8732 };
static const u16 adwSDRAMCfg2[] = { 0x87d2, 0x87d2, 0xa7d2, 0x87d2, 0xa7d2 };
static const u8 adwSDRAMRsh[] = { 36, 39, 40 };
static const u8 adwChipSpeed[] = { 110, 120, 125 };
u32 dwMemTypeIdx;
u32 dwChipSpeedIdx;
/* Get memory tpye and chip speed indexs from the SubSysDevID */
dwMemTypeIdx = (dwSubSysID & 0x70) >> 4;
dwChipSpeedIdx = (dwSubSysID & 0x180) >> 7;
if (dwMemTypeIdx > 4 || dwChipSpeedIdx > 2)
return 0;
/* Program SD-RAM interface */
STG_WRITE_REG(SDRAMArbiterConf, adwSDRAMArgCfg0[dwMemTypeIdx]);
if (dwRevID < 5) {
STG_WRITE_REG(SDRAMConf0, 0x49A1);
STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg1[dwMemTypeIdx]);
} else {
STG_WRITE_REG(SDRAMConf0, 0x4DF1);
STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg2[dwMemTypeIdx]);
}
STG_WRITE_REG(SDRAMConf2, 0x31);
STG_WRITE_REG(SDRAMRefresh, adwSDRAMRsh[dwChipSpeedIdx]);
return adwChipSpeed[dwChipSpeedIdx] * 10000;
}
u32 ProgramClock(u32 refClock,
u32 coreClock,
u32 * FOut, u32 * ROut, u32 * POut)
{
u32 R = 0, F = 0, OD = 0, ODIndex = 0;
u32 ulBestR = 0, ulBestF = 0, ulBestOD = 0;
u32 ulBestClk = 0, ulBestScore = 0;
u32 ulScore, ulPhaseScore, ulVcoScore;
u32 ulTmp = 0, ulVCO;
u32 ulScaleClockReq, ulMinClock, ulMaxClock;
static const unsigned char ODValues[] = { 1, 2, 0 };
/* Translate clock in Hz */
coreClock *= 100; /* in Hz */
refClock *= 1000; /* in Hz */
/* Work out acceptable clock
* The method calculates ~ +- 0.4% (1/256)
*/
ulMinClock = coreClock - (coreClock >> 8);
ulMaxClock = coreClock + (coreClock >> 8);
/* Scale clock required for use in calculations */
ulScaleClockReq = coreClock >> STG4K3_PLL_SCALER;
/* Iterate through post divider values */
for (ODIndex = 0; ODIndex < 3; ODIndex++) {
OD = ODValues[ODIndex];
R = STG4K3_PLL_MIN_R;
/* loop for pre-divider from min to max */
while (R <= STG4K3_PLL_MAX_R) {
/* estimate required feedback multiplier */
ulTmp = R * (ulScaleClockReq << OD);
/* F = ClkRequired * R * (2^OD) / Fref */
F = (u32)(ulTmp / (refClock >> STG4K3_PLL_SCALER));
/* compensate for accuracy */
if (F > STG4K3_PLL_MIN_F)
F--;
/*
* We should be close to our target frequency (if it's
* achievable with current OD & R) let's iterate
* through F for best fit
*/
while ((F >= STG4K3_PLL_MIN_F) &&
(F <= STG4K3_PLL_MAX_F)) {
/* Calc VCO at full accuracy */
ulVCO = refClock / R;
ulVCO = F * ulVCO;
/*
* Check it's within restricted VCO range
* unless of course the desired frequency is
* above the restricted range, then test
* against VCO limit
*/
if ((ulVCO >= STG4K3_PLL_MINR_VCO) &&
((ulVCO <= STG4K3_PLL_MAXR_VCO) ||
((coreClock > STG4K3_PLL_MAXR_VCO)
&& (ulVCO <= STG4K3_PLL_MAX_VCO)))) {
ulTmp = (ulVCO >> OD); /* Clock = VCO / (2^OD) */
/* Is this clock good enough? */
if ((ulTmp >= ulMinClock)
&& (ulTmp <= ulMaxClock)) {
ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K3_PLL_MAX_R)) >> 10);
ulVcoScore = ((ulVCO - STG4K3_PLL_MINR_VCO)) / ((STG4K3_PLL_MAXR_VCO - STG4K3_PLL_MINR_VCO) >> 10);
ulScore = ulPhaseScore + ulVcoScore;
if (!ulBestScore) {
ulBestOD = OD;
ulBestF = F;
ulBestR = R;
ulBestClk = ulTmp;
ulBestScore =
ulScore;
}
/* is this better, ( aim for highest Score) */
/*--------------------------------------------------------------------------
Here we want to use a scoring system which will take account of both the
value at the phase comparater and the VCO output
to do this we will use a cumulative score between the two
The way this ends up is that we choose the first value in the loop anyway
but we shall keep this code in case new restrictions come into play
--------------------------------------------------------------------------*/
if ((ulScore >= ulBestScore) && (OD > 0)) {
ulBestOD = OD;
ulBestF = F;
ulBestR = R;
ulBestClk = ulTmp;
ulBestScore =
ulScore;
}
}
}
F++;
}
R++;
}
}
/*
did we find anything?
Then return RFOD
*/
if (ulBestScore) {
*ROut = ulBestR;
*FOut = ulBestF;
if ((ulBestOD == 2) || (ulBestOD == 3)) {
*POut = 3;
} else
*POut = ulBestOD;
}
return (ulBestClk);
}
int SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev)
{
u32 F, R, P;
u16 core_pll = 0, sub;
u32 tmp;
u32 ulChipSpeed;
STG_WRITE_REG(IntMask, 0xFFFF);
/* Disable Primary Core Thread0 */
tmp = STG_READ_REG(Thread0Enable);
CLEAR_BIT(0);
STG_WRITE_REG(Thread0Enable, tmp);
/* Disable Primary Core Thread1 */
tmp = STG_READ_REG(Thread1Enable);
CLEAR_BIT(0);
STG_WRITE_REG(Thread1Enable, tmp);
STG_WRITE_REG(SoftwareReset,
PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST);
STG_WRITE_REG(SoftwareReset,
PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST |
PMX2_SOFTRESET_ROM_RST);
/* Need to play around to reset TA */
STG_WRITE_REG(TAConfiguration, 0);
STG_WRITE_REG(SoftwareReset,
PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST);
STG_WRITE_REG(SoftwareReset,
PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST |
PMX2_SOFTRESET_ROM_RST);
pci_read_config_word(pDev, PCI_CONFIG_SUBSYS_ID, &sub);
ulChipSpeed = InitSDRAMRegisters(pSTGReg, (u32)sub,
(u32)pDev->revision);
if (ulChipSpeed == 0)
return -EINVAL;
ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P);
core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
/* Set Core PLL Control to Core PLL Mode */
/* Send bits 0:7 of the Core PLL Mode register */
tmp = ((CORE_PLL_MODE_REG_0_7 << 8) | (core_pll & 0x00FF));
pci_write_config_word(pDev, CorePllControl, tmp);
/* Without some delay between the PCI config writes the clock does
not reliably set when the code is compiled -O3
*/
OS_DELAY(1000000);
tmp |= SET_BIT(14);
pci_write_config_word(pDev, CorePllControl, tmp);
OS_DELAY(1000000);
/* Send bits 8:15 of the Core PLL Mode register */
tmp =
((CORE_PLL_MODE_REG_8_15 << 8) | ((core_pll & 0xFF00) >> 8));
pci_write_config_word(pDev, CorePllControl, tmp);
OS_DELAY(1000000);
tmp |= SET_BIT(14);
pci_write_config_word(pDev, CorePllControl, tmp);
OS_DELAY(1000000);
STG_WRITE_REG(SoftwareReset, PMX2_SOFTRESET_ALL);
#if 0
/* Enable Primary Core Thread0 */
tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0));
STG_WRITE_REG(Thread0Enable, tmp);
/* Enable Primary Core Thread1 */
tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0));
STG_WRITE_REG(Thread1Enable, tmp);
#endif
return 0;
}
| linux-master | drivers/video/fbdev/kyro/STG4000InitDevice.c |
/*
* linux/drivers/video/kyro/STG4000Ramdac.c
*
* Copyright (C) 2002 STMicroelectronics
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <video/kyro.h>
#include "STG4000Reg.h"
#include "STG4000Interface.h"
static u32 STG_PIXEL_BUS_WIDTH = 128; /* 128 bit bus width */
static u32 REF_CLOCK = 14318;
int InitialiseRamdac(volatile STG4000REG __iomem * pSTGReg,
u32 displayDepth,
u32 displayWidth,
u32 displayHeight,
s32 HSyncPolarity,
s32 VSyncPolarity, u32 * pixelClock)
{
u32 tmp = 0;
u32 F = 0, R = 0, P = 0;
u32 stride = 0;
u32 ulPdiv = 0;
u32 physicalPixelDepth = 0;
/* Make sure DAC is in Reset */
tmp = STG_READ_REG(SoftwareReset);
if (tmp & 0x1) {
CLEAR_BIT(1);
STG_WRITE_REG(SoftwareReset, tmp);
}
/* Set Pixel Format */
tmp = STG_READ_REG(DACPixelFormat);
CLEAR_BITS_FRM_TO(0, 2);
/* Set LUT not used from 16bpp to 32 bpp ??? */
CLEAR_BITS_FRM_TO(8, 9);
switch (displayDepth) {
case 16:
{
physicalPixelDepth = 16;
tmp |= _16BPP;
break;
}
case 32:
{
/* Set for 32 bits per pixel */
physicalPixelDepth = 32;
tmp |= _32BPP;
break;
}
default:
return -EINVAL;
}
STG_WRITE_REG(DACPixelFormat, tmp);
/* Workout Bus transfer bandwidth according to pixel format */
ulPdiv = STG_PIXEL_BUS_WIDTH / physicalPixelDepth;
/* Get Screen Stride in pixels */
stride = displayWidth;
/* Set Primary size info */
tmp = STG_READ_REG(DACPrimSize);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(12, 31);
tmp |=
((((displayHeight - 1) << 12) | (((displayWidth / ulPdiv) -
1) << 23))
| (stride / ulPdiv));
STG_WRITE_REG(DACPrimSize, tmp);
/* Set Pixel Clock */
*pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P);
/* Set DAC PLL Mode */
tmp = STG_READ_REG(DACPLLMode);
CLEAR_BITS_FRM_TO(0, 15);
/* tmp |= ((P-1) | ((F-2) << 2) | ((R-2) << 11)); */
tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
STG_WRITE_REG(DACPLLMode, tmp);
/* Set Prim Address */
tmp = STG_READ_REG(DACPrimAddress);
CLEAR_BITS_FRM_TO(0, 20);
CLEAR_BITS_FRM_TO(20, 31);
STG_WRITE_REG(DACPrimAddress, tmp);
/* Set Cursor details with HW Cursor disabled */
tmp = STG_READ_REG(DACCursorCtrl);
tmp &= ~SET_BIT(31);
STG_WRITE_REG(DACCursorCtrl, tmp);
tmp = STG_READ_REG(DACCursorAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACCursorAddr, tmp);
/* Set Video Window */
tmp = STG_READ_REG(DACVidWinStart);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(16, 26);
STG_WRITE_REG(DACVidWinStart, tmp);
tmp = STG_READ_REG(DACVidWinEnd);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(16, 26);
STG_WRITE_REG(DACVidWinEnd, tmp);
/* Set DAC Border Color to default */
tmp = STG_READ_REG(DACBorderColor);
CLEAR_BITS_FRM_TO(0, 23);
STG_WRITE_REG(DACBorderColor, tmp);
/* Set Graphics and Overlay Burst Control */
STG_WRITE_REG(DACBurstCtrl, 0x0404);
/* Set CRC Trigger to default */
tmp = STG_READ_REG(DACCrcTrigger);
CLEAR_BIT(0);
STG_WRITE_REG(DACCrcTrigger, tmp);
/* Set Video Port Control to default */
tmp = STG_READ_REG(DigVidPortCtrl);
CLEAR_BIT(8);
CLEAR_BITS_FRM_TO(16, 27);
CLEAR_BITS_FRM_TO(1, 3);
CLEAR_BITS_FRM_TO(10, 11);
STG_WRITE_REG(DigVidPortCtrl, tmp);
return 0;
}
/* Ramdac control, turning output to the screen on and off */
void DisableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)
{
u32 tmp;
/* Disable DAC for Graphics Stream Control */
tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0);
STG_WRITE_REG(DACStreamCtrl, tmp);
}
void EnableRamdacOutput(volatile STG4000REG __iomem * pSTGReg)
{
u32 tmp;
/* Enable DAC for Graphics Stream Control */
tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0);
STG_WRITE_REG(DACStreamCtrl, tmp);
}
| linux-master | drivers/video/fbdev/kyro/STG4000Ramdac.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* linux/drivers/video/mmp/common.c
* This driver is a common framework for Marvell Display Controller
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Authors: Zhou Zhu <[email protected]>
*/
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/export.h>
#include <linux/module.h>
#include <video/mmp_disp.h>
static struct mmp_overlay *path_get_overlay(struct mmp_path *path,
int overlay_id)
{
if (path && overlay_id < path->overlay_num)
return &path->overlays[overlay_id];
return NULL;
}
static int path_check_status(struct mmp_path *path)
{
int i;
for (i = 0; i < path->overlay_num; i++)
if (path->overlays[i].status)
return 1;
return 0;
}
/*
* Get modelist write pointer of modelist.
* It also returns modelist number
* this function fetches modelist from phy/panel:
* for HDMI/parallel or dsi to hdmi cases, get from phy
* or get from panel
*/
static int path_get_modelist(struct mmp_path *path,
struct mmp_mode **modelist)
{
BUG_ON(!path || !modelist);
if (path->panel && path->panel->get_modelist)
return path->panel->get_modelist(path->panel, modelist);
return 0;
}
/*
* panel list is used to pair panel/path when path/panel registered
* path list is used for both buffer driver and platdriver
* plat driver do path register/unregister
* panel driver do panel register/unregister
* buffer driver get registered path
*/
static LIST_HEAD(panel_list);
static LIST_HEAD(path_list);
static DEFINE_MUTEX(disp_lock);
/*
* mmp_register_panel - register panel to panel_list and connect to path
* @p: panel to be registered
*
* this function provides interface for panel drivers to register panel
* to panel_list and connect to path which matchs panel->plat_path_name.
* no error returns when no matching path is found as path register after
* panel register is permitted.
*/
void mmp_register_panel(struct mmp_panel *panel)
{
struct mmp_path *path;
mutex_lock(&disp_lock);
/* add */
list_add_tail(&panel->node, &panel_list);
/* try to register to path */
list_for_each_entry(path, &path_list, node) {
if (!strcmp(panel->plat_path_name, path->name)) {
dev_info(panel->dev, "connect to path %s\n",
path->name);
path->panel = panel;
break;
}
}
mutex_unlock(&disp_lock);
}
EXPORT_SYMBOL_GPL(mmp_register_panel);
/*
* mmp_unregister_panel - unregister panel from panel_list and disconnect
* @p: panel to be unregistered
*
* this function provides interface for panel drivers to unregister panel
* from panel_list and disconnect from path.
*/
void mmp_unregister_panel(struct mmp_panel *panel)
{
struct mmp_path *path;
mutex_lock(&disp_lock);
list_del(&panel->node);
list_for_each_entry(path, &path_list, node) {
if (path->panel && path->panel == panel) {
dev_info(panel->dev, "disconnect from path %s\n",
path->name);
path->panel = NULL;
break;
}
}
mutex_unlock(&disp_lock);
}
EXPORT_SYMBOL_GPL(mmp_unregister_panel);
/*
* mmp_get_path - get path by name
* @p: path name
*
* this function checks path name in path_list and return matching path
* return NULL if no matching path
*/
struct mmp_path *mmp_get_path(const char *name)
{
struct mmp_path *path = NULL, *iter;
mutex_lock(&disp_lock);
list_for_each_entry(iter, &path_list, node) {
if (!strcmp(name, iter->name)) {
path = iter;
break;
}
}
mutex_unlock(&disp_lock);
return path;
}
EXPORT_SYMBOL_GPL(mmp_get_path);
/*
* mmp_register_path - init and register path by path_info
* @p: path info provided by display controller
*
* this function init by path info and register path to path_list
* this function also try to connect path with panel by name
*/
struct mmp_path *mmp_register_path(struct mmp_path_info *info)
{
int i;
struct mmp_path *path = NULL;
struct mmp_panel *panel;
path = kzalloc(struct_size(path, overlays, info->overlay_num),
GFP_KERNEL);
if (!path)
return NULL;
/* path set */
mutex_init(&path->access_ok);
path->dev = info->dev;
path->id = info->id;
path->name = info->name;
path->output_type = info->output_type;
path->overlay_num = info->overlay_num;
path->plat_data = info->plat_data;
path->ops.set_mode = info->set_mode;
mutex_lock(&disp_lock);
/* get panel */
list_for_each_entry(panel, &panel_list, node) {
if (!strcmp(info->name, panel->plat_path_name)) {
dev_info(path->dev, "get panel %s\n", panel->name);
path->panel = panel;
break;
}
}
dev_info(path->dev, "register %s, overlay_num %d\n",
path->name, path->overlay_num);
/* default op set: if already set by driver, never cover it */
if (!path->ops.check_status)
path->ops.check_status = path_check_status;
if (!path->ops.get_overlay)
path->ops.get_overlay = path_get_overlay;
if (!path->ops.get_modelist)
path->ops.get_modelist = path_get_modelist;
/* step3: init overlays */
for (i = 0; i < path->overlay_num; i++) {
path->overlays[i].path = path;
path->overlays[i].id = i;
mutex_init(&path->overlays[i].access_ok);
path->overlays[i].ops = info->overlay_ops;
}
/* add to pathlist */
list_add_tail(&path->node, &path_list);
mutex_unlock(&disp_lock);
return path;
}
EXPORT_SYMBOL_GPL(mmp_register_path);
/*
* mmp_unregister_path - unregister and destroy path
* @p: path to be destroyed.
*
* this function registers path and destroys it.
*/
void mmp_unregister_path(struct mmp_path *path)
{
int i;
if (!path)
return;
mutex_lock(&disp_lock);
/* del from pathlist */
list_del(&path->node);
/* deinit overlays */
for (i = 0; i < path->overlay_num; i++)
mutex_destroy(&path->overlays[i].access_ok);
mutex_destroy(&path->access_ok);
kfree(path);
mutex_unlock(&disp_lock);
}
EXPORT_SYMBOL_GPL(mmp_unregister_path);
MODULE_AUTHOR("Zhou Zhu <[email protected]>");
MODULE_DESCRIPTION("Marvell MMP display framework");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/mmp/core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* linux/drivers/video/mmp/panel/tpo_tj032md01bw.c
* active panel using spi interface to do init
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Authors: Guoqing Li <[email protected]>
* Lisa Du <[email protected]>
* Zhou Zhu <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/spi/spi.h>
#include <video/mmp_disp.h>
static u16 init[] = {
0x0801,
0x0800,
0x0200,
0x0304,
0x040e,
0x0903,
0x0b18,
0x0c53,
0x0d01,
0x0ee0,
0x0f01,
0x1058,
0x201e,
0x210a,
0x220a,
0x231e,
0x2400,
0x2532,
0x2600,
0x27ac,
0x2904,
0x2aa2,
0x2b45,
0x2c45,
0x2d15,
0x2e5a,
0x2fff,
0x306b,
0x310d,
0x3248,
0x3382,
0x34bd,
0x35e7,
0x3618,
0x3794,
0x3801,
0x395d,
0x3aae,
0x3bff,
0x07c9,
};
static u16 poweroff[] = {
0x07d9,
};
struct tpohvga_plat_data {
void (*plat_onoff)(int status);
struct spi_device *spi;
};
static void tpohvga_onoff(struct mmp_panel *panel, int status)
{
struct tpohvga_plat_data *plat = panel->plat_data;
int ret;
if (status) {
plat->plat_onoff(1);
ret = spi_write(plat->spi, init, sizeof(init));
if (ret < 0)
dev_warn(panel->dev, "init cmd failed(%d)\n", ret);
} else {
ret = spi_write(plat->spi, poweroff, sizeof(poweroff));
if (ret < 0)
dev_warn(panel->dev, "poweroff cmd failed(%d)\n", ret);
plat->plat_onoff(0);
}
}
static struct mmp_mode mmp_modes_tpohvga[] = {
[0] = {
.pixclock_freq = 10394400,
.refresh = 60,
.xres = 320,
.yres = 480,
.hsync_len = 10,
.left_margin = 15,
.right_margin = 10,
.vsync_len = 2,
.upper_margin = 4,
.lower_margin = 2,
.invert_pixclock = 1,
.pix_fmt_out = PIXFMT_RGB565,
},
};
static int tpohvga_get_modelist(struct mmp_panel *panel,
struct mmp_mode **modelist)
{
*modelist = mmp_modes_tpohvga;
return 1;
}
static struct mmp_panel panel_tpohvga = {
.name = "tpohvga",
.panel_type = PANELTYPE_ACTIVE,
.get_modelist = tpohvga_get_modelist,
.set_onoff = tpohvga_onoff,
};
static int tpohvga_probe(struct spi_device *spi)
{
struct mmp_mach_panel_info *mi;
int ret;
struct tpohvga_plat_data *plat_data;
/* get configs from platform data */
mi = spi->dev.platform_data;
if (mi == NULL) {
dev_err(&spi->dev, "%s: no platform data defined\n", __func__);
return -EINVAL;
}
/* setup spi related info */
spi->bits_per_word = 16;
ret = spi_setup(spi);
if (ret < 0) {
dev_err(&spi->dev, "spi setup failed %d", ret);
return ret;
}
plat_data = kzalloc(sizeof(*plat_data), GFP_KERNEL);
if (plat_data == NULL)
return -ENOMEM;
plat_data->spi = spi;
plat_data->plat_onoff = mi->plat_set_onoff;
panel_tpohvga.plat_data = plat_data;
panel_tpohvga.plat_path_name = mi->plat_path_name;
panel_tpohvga.dev = &spi->dev;
mmp_register_panel(&panel_tpohvga);
return 0;
}
static struct spi_driver panel_tpohvga_driver = {
.driver = {
.name = "tpo-hvga",
},
.probe = tpohvga_probe,
};
module_spi_driver(panel_tpohvga_driver);
MODULE_AUTHOR("Lisa Du<[email protected]>");
MODULE_DESCRIPTION("Panel driver for tpohvga");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/mmp/panel/tpo_tj032md01bw.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* linux/drivers/video/mmp/hw/mmp_ctrl.c
* Marvell MMP series Display Controller support
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Authors: Guoqing Li <[email protected]>
* Lisa Du <[email protected]>
* Zhou Zhu <[email protected]>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/vmalloc.h>
#include <linux/uaccess.h>
#include <linux/kthread.h>
#include <linux/io.h>
#include "mmp_ctrl.h"
static irqreturn_t ctrl_handle_irq(int irq, void *dev_id)
{
struct mmphw_ctrl *ctrl = (struct mmphw_ctrl *)dev_id;
u32 isr, imask, tmp;
isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
do {
/* clear clock only */
tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
if (tmp & isr)
writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);
} while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask);
return IRQ_HANDLED;
}
static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
{
u32 rbswap = 0, uvswap = 0, yuvswap = 0,
csc_en = 0, val = 0,
vid = overlay_is_vid(overlay);
switch (pix_fmt) {
case PIXFMT_RGB565:
case PIXFMT_RGB1555:
case PIXFMT_RGB888PACK:
case PIXFMT_RGB888UNPACK:
case PIXFMT_RGBA888:
rbswap = 1;
break;
case PIXFMT_VYUY:
case PIXFMT_YVU422P:
case PIXFMT_YVU420P:
uvswap = 1;
break;
case PIXFMT_YUYV:
yuvswap = 1;
break;
default:
break;
}
switch (pix_fmt) {
case PIXFMT_RGB565:
case PIXFMT_BGR565:
break;
case PIXFMT_RGB1555:
case PIXFMT_BGR1555:
val = 0x1;
break;
case PIXFMT_RGB888PACK:
case PIXFMT_BGR888PACK:
val = 0x2;
break;
case PIXFMT_RGB888UNPACK:
case PIXFMT_BGR888UNPACK:
val = 0x3;
break;
case PIXFMT_RGBA888:
case PIXFMT_BGRA888:
val = 0x4;
break;
case PIXFMT_UYVY:
case PIXFMT_VYUY:
case PIXFMT_YUYV:
val = 0x5;
csc_en = 1;
break;
case PIXFMT_YUV422P:
case PIXFMT_YVU422P:
val = 0x6;
csc_en = 1;
break;
case PIXFMT_YUV420P:
case PIXFMT_YVU420P:
val = 0x7;
csc_en = 1;
break;
default:
break;
}
return (dma_palette(0) | dma_fmt(vid, val) |
dma_swaprb(vid, rbswap) | dma_swapuv(vid, uvswap) |
dma_swapyuv(vid, yuvswap) | dma_csc(vid, csc_en));
}
static void dmafetch_set_fmt(struct mmp_overlay *overlay)
{
u32 tmp;
struct mmp_path *path = overlay->path;
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
tmp &= ~dma_mask(overlay_is_vid(overlay));
tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt);
writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
}
static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win)
{
struct lcd_regs *regs = path_regs(overlay->path);
/* assert win supported */
memcpy(&overlay->win, win, sizeof(struct mmp_win));
mutex_lock(&overlay->access_ok);
if (overlay_is_vid(overlay)) {
writel_relaxed(win->pitch[0],
(void __iomem *)®s->v_pitch_yc);
writel_relaxed(win->pitch[2] << 16 | win->pitch[1],
(void __iomem *)®s->v_pitch_uv);
writel_relaxed((win->ysrc << 16) | win->xsrc,
(void __iomem *)®s->v_size);
writel_relaxed((win->ydst << 16) | win->xdst,
(void __iomem *)®s->v_size_z);
writel_relaxed(win->ypos << 16 | win->xpos,
(void __iomem *)®s->v_start);
} else {
writel_relaxed(win->pitch[0], (void __iomem *)®s->g_pitch);
writel_relaxed((win->ysrc << 16) | win->xsrc,
(void __iomem *)®s->g_size);
writel_relaxed((win->ydst << 16) | win->xdst,
(void __iomem *)®s->g_size_z);
writel_relaxed(win->ypos << 16 | win->xpos,
(void __iomem *)®s->g_start);
}
dmafetch_set_fmt(overlay);
mutex_unlock(&overlay->access_ok);
}
static void dmafetch_onoff(struct mmp_overlay *overlay, int on)
{
u32 mask = overlay_is_vid(overlay) ? CFG_DMA_ENA_MASK :
CFG_GRA_ENA_MASK;
u32 enable = overlay_is_vid(overlay) ? CFG_DMA_ENA(1) : CFG_GRA_ENA(1);
u32 tmp;
struct mmp_path *path = overlay->path;
mutex_lock(&overlay->access_ok);
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
tmp &= ~mask;
tmp |= (on ? enable : 0);
writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
mutex_unlock(&overlay->access_ok);
}
static void path_enabledisable(struct mmp_path *path, int on)
{
u32 tmp;
mutex_lock(&path->access_ok);
tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
if (on)
tmp &= ~SCLK_DISABLE;
else
tmp |= SCLK_DISABLE;
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
mutex_unlock(&path->access_ok);
}
static void path_onoff(struct mmp_path *path, int on)
{
if (path->status == on) {
dev_info(path->dev, "path %s is already %s\n",
path->name, stat_name(path->status));
return;
}
if (on) {
path_enabledisable(path, 1);
if (path->panel && path->panel->set_onoff)
path->panel->set_onoff(path->panel, 1);
} else {
if (path->panel && path->panel->set_onoff)
path->panel->set_onoff(path->panel, 0);
path_enabledisable(path, 0);
}
path->status = on;
}
static void overlay_set_onoff(struct mmp_overlay *overlay, int on)
{
if (overlay->status == on) {
dev_info(overlay_to_ctrl(overlay)->dev, "overlay %s is already %s\n",
overlay->path->name, stat_name(overlay->status));
return;
}
overlay->status = on;
dmafetch_onoff(overlay, on);
if (overlay->path->ops.check_status(overlay->path)
!= overlay->path->status)
path_onoff(overlay->path, on);
}
static void overlay_set_fetch(struct mmp_overlay *overlay, int fetch_id)
{
overlay->dmafetch_id = fetch_id;
}
static int overlay_set_addr(struct mmp_overlay *overlay, struct mmp_addr *addr)
{
struct lcd_regs *regs = path_regs(overlay->path);
/* FIXME: assert addr supported */
memcpy(&overlay->addr, addr, sizeof(struct mmp_addr));
if (overlay_is_vid(overlay)) {
writel_relaxed(addr->phys[0], (void __iomem *)®s->v_y0);
writel_relaxed(addr->phys[1], (void __iomem *)®s->v_u0);
writel_relaxed(addr->phys[2], (void __iomem *)®s->v_v0);
} else
writel_relaxed(addr->phys[0], (void __iomem *)®s->g_0);
return overlay->addr.phys[0];
}
static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode)
{
struct lcd_regs *regs = path_regs(path);
u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,
link_config = path_to_path_plat(path)->link_config,
dsi_rbswap = path_to_path_plat(path)->link_config;
/* FIXME: assert videomode supported */
memcpy(&path->mode, mode, sizeof(struct mmp_mode));
mutex_lock(&path->access_ok);
/* polarity of timing signals */
tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;
tmp |= mode->vsync_invert ? 0 : 0x8;
tmp |= mode->hsync_invert ? 0 : 0x4;
tmp |= link_config & CFG_DUMBMODE_MASK;
tmp |= CFG_DUMB_ENA(1);
writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
/* interface rb_swap setting */
tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
(~(CFG_INTFRBSWAP_MASK));
tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK;
writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
writel_relaxed((mode->yres << 16) | mode->xres,
(void __iomem *)®s->screen_active);
writel_relaxed((mode->left_margin << 16) | mode->right_margin,
(void __iomem *)®s->screen_h_porch);
writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,
(void __iomem *)®s->screen_v_porch);
total_x = mode->xres + mode->left_margin + mode->right_margin +
mode->hsync_len;
total_y = mode->yres + mode->upper_margin + mode->lower_margin +
mode->vsync_len;
writel_relaxed((total_y << 16) | total_x,
(void __iomem *)®s->screen_size);
/* vsync ctrl */
if (path->output_type == PATH_OUT_DSI)
vsync_ctrl = 0x01330133;
else
vsync_ctrl = ((mode->xres + mode->right_margin) << 16)
| (mode->xres + mode->right_margin);
writel_relaxed(vsync_ctrl, (void __iomem *)®s->vsync_ctrl);
/* set pixclock div */
sclk_src = clk_get_rate(path_to_ctrl(path)->clk);
sclk_div = sclk_src / mode->pixclock_freq;
if (sclk_div * mode->pixclock_freq < sclk_src)
sclk_div++;
dev_info(path->dev, "%s sclk_src %d sclk_div 0x%x pclk %d\n",
__func__, sclk_src, sclk_div, mode->pixclock_freq);
tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
tmp &= ~CLK_INT_DIV_MASK;
tmp |= sclk_div;
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
mutex_unlock(&path->access_ok);
}
static struct mmp_overlay_ops mmphw_overlay_ops = {
.set_fetch = overlay_set_fetch,
.set_onoff = overlay_set_onoff,
.set_win = overlay_set_win,
.set_addr = overlay_set_addr,
};
static void ctrl_set_default(struct mmphw_ctrl *ctrl)
{
u32 tmp, irq_mask;
/*
* LCD Global control(LCD_TOP_CTRL) should be configed before
* any other LCD registers read/write, or there maybe issues.
*/
tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL);
tmp |= 0xfff0;
writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);
/* disable all interrupts */
irq_mask = path_imasks(0) | err_imask(0) |
path_imasks(1) | err_imask(1);
tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
tmp &= ~irq_mask;
tmp |= irq_mask;
writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);
}
static void path_set_default(struct mmp_path *path)
{
struct lcd_regs *regs = path_regs(path);
u32 dma_ctrl1, mask, tmp, path_config;
path_config = path_to_path_plat(path)->path_config;
/* Configure IOPAD: should be parallel only */
if (PATH_OUT_PARALLEL == path->output_type) {
mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK;
tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);
tmp &= ~mask;
tmp |= path_config;
writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);
}
/* Select path clock source */
tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
tmp &= ~SCLK_SRC_SEL_MASK;
tmp |= path_config;
writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
/*
* Configure default bits: vsync triggers DMA,
* power save enable, configure alpha registers to
* display 100% graphics, and set pixel command.
*/
dma_ctrl1 = 0x2032ff81;
dma_ctrl1 |= CFG_VSYNC_INV_MASK;
writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
/* Configure default register values */
writel_relaxed(0x00000000, (void __iomem *)®s->blank_color);
writel_relaxed(0x00000000, (void __iomem *)®s->g_1);
writel_relaxed(0x00000000, (void __iomem *)®s->g_start);
/*
* 1.enable multiple burst request in DMA AXI
* bus arbiter for faster read if not tv path;
* 2.enable horizontal smooth filter;
*/
mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1);
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
tmp |= mask;
if (PATH_TV == path->id)
tmp &= ~CFG_ARBFAST_ENA(1);
writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
}
static int path_init(struct mmphw_path_plat *path_plat,
struct mmp_mach_path_config *config)
{
struct mmphw_ctrl *ctrl = path_plat->ctrl;
struct mmp_path_info *path_info;
struct mmp_path *path = NULL;
dev_info(ctrl->dev, "%s: %s\n", __func__, config->name);
/* init driver data */
path_info = kzalloc(sizeof(*path_info), GFP_KERNEL);
if (!path_info)
return 0;
path_info->name = config->name;
path_info->id = path_plat->id;
path_info->dev = ctrl->dev;
path_info->overlay_num = config->overlay_num;
path_info->overlay_ops = &mmphw_overlay_ops;
path_info->set_mode = path_set_mode;
path_info->plat_data = path_plat;
/* create/register platform device */
path = mmp_register_path(path_info);
if (!path) {
kfree(path_info);
return 0;
}
path_plat->path = path;
path_plat->path_config = config->path_config;
path_plat->link_config = config->link_config;
path_plat->dsi_rbswap = config->dsi_rbswap;
path_set_default(path);
kfree(path_info);
return 1;
}
static void path_deinit(struct mmphw_path_plat *path_plat)
{
if (!path_plat)
return;
mmp_unregister_path(path_plat->path);
}
static int mmphw_probe(struct platform_device *pdev)
{
struct mmp_mach_plat_info *mi;
struct resource *res;
int ret, i, irq;
struct mmphw_path_plat *path_plat;
struct mmphw_ctrl *ctrl = NULL;
/* get resources from platform data */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL) {
dev_err(&pdev->dev, "%s: no IO memory defined\n", __func__);
ret = -ENOENT;
goto failed;
}
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = -ENOENT;
goto failed;
}
/* get configs from platform data */
mi = pdev->dev.platform_data;
if (mi == NULL || !mi->path_num || !mi->paths) {
dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
ret = -EINVAL;
goto failed;
}
/* allocate */
ctrl = devm_kzalloc(&pdev->dev,
struct_size(ctrl, path_plats, mi->path_num),
GFP_KERNEL);
if (!ctrl) {
ret = -ENOMEM;
goto failed;
}
ctrl->name = mi->name;
ctrl->path_num = mi->path_num;
ctrl->dev = &pdev->dev;
ctrl->irq = irq;
platform_set_drvdata(pdev, ctrl);
mutex_init(&ctrl->access_ok);
/* map registers.*/
if (!devm_request_mem_region(ctrl->dev, res->start,
resource_size(res), ctrl->name)) {
dev_err(ctrl->dev,
"can't request region for resource %pR\n", res);
ret = -EINVAL;
goto failed;
}
ctrl->reg_base = devm_ioremap(ctrl->dev,
res->start, resource_size(res));
if (ctrl->reg_base == NULL) {
dev_err(ctrl->dev, "%s: res %pR map failed\n", __func__, res);
ret = -ENOMEM;
goto failed;
}
/* request irq */
ret = devm_request_irq(ctrl->dev, ctrl->irq, ctrl_handle_irq,
IRQF_SHARED, "lcd_controller", ctrl);
if (ret < 0) {
dev_err(ctrl->dev, "%s unable to request IRQ %d\n",
__func__, ctrl->irq);
ret = -ENXIO;
goto failed;
}
/* get clock */
ctrl->clk = devm_clk_get(ctrl->dev, mi->clk_name);
if (IS_ERR(ctrl->clk)) {
ret = PTR_ERR(ctrl->clk);
dev_err_probe(ctrl->dev, ret,
"unable to get clk %s\n", mi->clk_name);
goto failed;
}
ret = clk_prepare_enable(ctrl->clk);
if (ret)
goto failed;
/* init global regs */
ctrl_set_default(ctrl);
/* init pathes from machine info and register them */
for (i = 0; i < ctrl->path_num; i++) {
/* get from config and machine info */
path_plat = &ctrl->path_plats[i];
path_plat->id = i;
path_plat->ctrl = ctrl;
/* path init */
if (!path_init(path_plat, &mi->paths[i])) {
ret = -EINVAL;
goto failed_path_init;
}
}
#ifdef CONFIG_MMP_DISP_SPI
ret = lcd_spi_register(ctrl);
if (ret < 0)
goto failed_path_init;
#endif
dev_info(ctrl->dev, "device init done\n");
return 0;
failed_path_init:
for (i = 0; i < ctrl->path_num; i++) {
path_plat = &ctrl->path_plats[i];
path_deinit(path_plat);
}
clk_disable_unprepare(ctrl->clk);
failed:
dev_err(&pdev->dev, "device init failed\n");
return ret;
}
static struct platform_driver mmphw_driver = {
.driver = {
.name = "mmp-disp",
},
.probe = mmphw_probe,
};
static int mmphw_init(void)
{
return platform_driver_register(&mmphw_driver);
}
module_init(mmphw_init);
MODULE_AUTHOR("Li Guoqing<[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for mmp");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/mmp/hw/mmp_ctrl.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* linux/drivers/video/mmp/hw/mmp_spi.c
* using the spi in LCD controler for commands send
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Authors: Guoqing Li <[email protected]>
* Lisa Du <[email protected]>
* Zhou Zhu <[email protected]>
*/
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spi/spi.h>
#include "mmp_ctrl.h"
/**
* spi_write - write command to the SPI port
* @spi: the SPI device.
* @data: can be 8/16/32-bit, MSB justified data to write.
*
* Wait bus transfer complete IRQ.
* The caller is expected to perform the necessary locking.
*
* Returns:
* %-ETIMEDOUT timeout occurred
* 0 success
*/
static inline int lcd_spi_write(struct spi_device *spi, u32 data)
{
int timeout = 100000, isr, ret = 0;
u32 tmp;
void __iomem *reg_base = (void __iomem *)
*(void **)spi_master_get_devdata(spi->master);
/* clear ISR */
writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR);
switch (spi->bits_per_word) {
case 8:
writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA);
break;
case 16:
writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA);
break;
case 32:
writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA);
break;
default:
dev_err(&spi->dev, "Wrong spi bit length\n");
}
/* SPI start to send command */
tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL);
tmp &= ~CFG_SPI_START_MASK;
tmp |= CFG_SPI_START(1);
writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
isr = readl_relaxed(reg_base + SPU_IRQ_ISR);
while (!(isr & SPI_IRQ_ENA_MASK)) {
udelay(100);
isr = readl_relaxed(reg_base + SPU_IRQ_ISR);
if (!--timeout) {
ret = -ETIMEDOUT;
dev_err(&spi->dev, "spi cmd send time out\n");
break;
}
}
tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL);
tmp &= ~CFG_SPI_START_MASK;
tmp |= CFG_SPI_START(0);
writel_relaxed(tmp, reg_base + LCD_SPU_SPI_CTRL);
writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR);
return ret;
}
static int lcd_spi_setup(struct spi_device *spi)
{
void __iomem *reg_base = (void __iomem *)
*(void **)spi_master_get_devdata(spi->master);
u32 tmp;
tmp = CFG_SCLKCNT(16) |
CFG_TXBITS(spi->bits_per_word) |
CFG_SPI_SEL(1) | CFG_SPI_ENA(1) |
CFG_SPI_3W4WB(1);
writel(tmp, reg_base + LCD_SPU_SPI_CTRL);
/*
* After set mode it need a time to pull up the spi singals,
* or it would cause the wrong waveform when send spi command,
* especially on pxa910h
*/
tmp = readl_relaxed(reg_base + SPU_IOPAD_CONTROL);
if ((tmp & CFG_IOPADMODE_MASK) != IOPAD_DUMB18SPI)
writel_relaxed(IOPAD_DUMB18SPI |
(tmp & ~CFG_IOPADMODE_MASK),
reg_base + SPU_IOPAD_CONTROL);
udelay(20);
return 0;
}
static int lcd_spi_one_transfer(struct spi_device *spi, struct spi_message *m)
{
struct spi_transfer *t;
int i;
list_for_each_entry(t, &m->transfers, transfer_list) {
switch (spi->bits_per_word) {
case 8:
for (i = 0; i < t->len; i++)
lcd_spi_write(spi, ((u8 *)t->tx_buf)[i]);
break;
case 16:
for (i = 0; i < t->len/2; i++)
lcd_spi_write(spi, ((u16 *)t->tx_buf)[i]);
break;
case 32:
for (i = 0; i < t->len/4; i++)
lcd_spi_write(spi, ((u32 *)t->tx_buf)[i]);
break;
default:
dev_err(&spi->dev, "Wrong spi bit length\n");
}
}
m->status = 0;
if (m->complete)
m->complete(m->context);
return 0;
}
int lcd_spi_register(struct mmphw_ctrl *ctrl)
{
struct spi_master *master;
void **p_regbase;
int err;
master = spi_alloc_master(ctrl->dev, sizeof(void *));
if (!master) {
dev_err(ctrl->dev, "unable to allocate SPI master\n");
return -ENOMEM;
}
p_regbase = spi_master_get_devdata(master);
*p_regbase = (void __force *)ctrl->reg_base;
/* set bus num to 5 to avoid conflict with other spi hosts */
master->bus_num = 5;
master->num_chipselect = 1;
master->setup = lcd_spi_setup;
master->transfer = lcd_spi_one_transfer;
err = spi_register_master(master);
if (err < 0) {
dev_err(ctrl->dev, "unable to register SPI master\n");
spi_master_put(master);
return err;
}
dev_info(&master->dev, "registered\n");
return 0;
}
| linux-master | drivers/video/fbdev/mmp/hw/mmp_spi.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* linux/drivers/video/mmp/fb/mmpfb.c
* Framebuffer driver for Marvell Display controller.
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Authors: Zhou Zhu <[email protected]>
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include "mmpfb.h"
static int var_to_pixfmt(struct fb_var_screeninfo *var)
{
/*
* Pseudocolor mode?
*/
if (var->bits_per_pixel == 8)
return PIXFMT_PSEUDOCOLOR;
/*
* Check for YUV422PLANAR.
*/
if (var->bits_per_pixel == 16 && var->red.length == 8 &&
var->green.length == 4 && var->blue.length == 4) {
if (var->green.offset >= var->blue.offset)
return PIXFMT_YUV422P;
else
return PIXFMT_YVU422P;
}
/*
* Check for YUV420PLANAR.
*/
if (var->bits_per_pixel == 12 && var->red.length == 8 &&
var->green.length == 2 && var->blue.length == 2) {
if (var->green.offset >= var->blue.offset)
return PIXFMT_YUV420P;
else
return PIXFMT_YVU420P;
}
/*
* Check for YUV422PACK.
*/
if (var->bits_per_pixel == 16 && var->red.length == 16 &&
var->green.length == 16 && var->blue.length == 16) {
if (var->red.offset == 0)
return PIXFMT_YUYV;
else if (var->green.offset >= var->blue.offset)
return PIXFMT_UYVY;
else
return PIXFMT_VYUY;
}
/*
* Check for 565/1555.
*/
if (var->bits_per_pixel == 16 && var->red.length <= 5 &&
var->green.length <= 6 && var->blue.length <= 5) {
if (var->transp.length == 0) {
if (var->red.offset >= var->blue.offset)
return PIXFMT_RGB565;
else
return PIXFMT_BGR565;
}
}
/*
* Check for 888/A888.
*/
if (var->bits_per_pixel <= 32 && var->red.length <= 8 &&
var->green.length <= 8 && var->blue.length <= 8) {
if (var->bits_per_pixel == 24 && var->transp.length == 0) {
if (var->red.offset >= var->blue.offset)
return PIXFMT_RGB888PACK;
else
return PIXFMT_BGR888PACK;
}
if (var->bits_per_pixel == 32 && var->transp.offset == 24) {
if (var->red.offset >= var->blue.offset)
return PIXFMT_RGBA888;
else
return PIXFMT_BGRA888;
} else {
if (var->red.offset >= var->blue.offset)
return PIXFMT_RGB888UNPACK;
else
return PIXFMT_BGR888UNPACK;
}
}
return -EINVAL;
}
static void pixfmt_to_var(struct fb_var_screeninfo *var, int pix_fmt)
{
switch (pix_fmt) {
case PIXFMT_RGB565:
var->bits_per_pixel = 16;
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_BGR565:
var->bits_per_pixel = 16;
var->red.offset = 0; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 11; var->blue.length = 5;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_RGB888UNPACK:
var->bits_per_pixel = 32;
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_BGR888UNPACK:
var->bits_per_pixel = 32;
var->red.offset = 0; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 16; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_RGBA888:
var->bits_per_pixel = 32;
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 24; var->transp.length = 8;
break;
case PIXFMT_BGRA888:
var->bits_per_pixel = 32;
var->red.offset = 0; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 16; var->blue.length = 8;
var->transp.offset = 24; var->transp.length = 8;
break;
case PIXFMT_RGB888PACK:
var->bits_per_pixel = 24;
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_BGR888PACK:
var->bits_per_pixel = 24;
var->red.offset = 0; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 16; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_YUV420P:
var->bits_per_pixel = 12;
var->red.offset = 4; var->red.length = 8;
var->green.offset = 2; var->green.length = 2;
var->blue.offset = 0; var->blue.length = 2;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_YVU420P:
var->bits_per_pixel = 12;
var->red.offset = 4; var->red.length = 8;
var->green.offset = 0; var->green.length = 2;
var->blue.offset = 2; var->blue.length = 2;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_YUV422P:
var->bits_per_pixel = 16;
var->red.offset = 8; var->red.length = 8;
var->green.offset = 4; var->green.length = 4;
var->blue.offset = 0; var->blue.length = 4;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_YVU422P:
var->bits_per_pixel = 16;
var->red.offset = 8; var->red.length = 8;
var->green.offset = 0; var->green.length = 4;
var->blue.offset = 4; var->blue.length = 4;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_UYVY:
var->bits_per_pixel = 16;
var->red.offset = 8; var->red.length = 16;
var->green.offset = 4; var->green.length = 16;
var->blue.offset = 0; var->blue.length = 16;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_VYUY:
var->bits_per_pixel = 16;
var->red.offset = 8; var->red.length = 16;
var->green.offset = 0; var->green.length = 16;
var->blue.offset = 4; var->blue.length = 16;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_YUYV:
var->bits_per_pixel = 16;
var->red.offset = 0; var->red.length = 16;
var->green.offset = 4; var->green.length = 16;
var->blue.offset = 8; var->blue.length = 16;
var->transp.offset = 0; var->transp.length = 0;
break;
case PIXFMT_PSEUDOCOLOR:
var->bits_per_pixel = 8;
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
break;
}
}
/*
* fb framework has its limitation:
* 1. input color/output color is not seprated
* 2. fb_videomode not include output color
* so for fb usage, we keep a output format which is not changed
* then it's added for mmpmode
*/
static void fbmode_to_mmpmode(struct mmp_mode *mode,
struct fb_videomode *videomode, int output_fmt)
{
u64 div_result = 1000000000000ll;
mode->name = videomode->name;
mode->refresh = videomode->refresh;
mode->xres = videomode->xres;
mode->yres = videomode->yres;
do_div(div_result, videomode->pixclock);
mode->pixclock_freq = (u32)div_result;
mode->left_margin = videomode->left_margin;
mode->right_margin = videomode->right_margin;
mode->upper_margin = videomode->upper_margin;
mode->lower_margin = videomode->lower_margin;
mode->hsync_len = videomode->hsync_len;
mode->vsync_len = videomode->vsync_len;
mode->hsync_invert = !!(videomode->sync & FB_SYNC_HOR_HIGH_ACT);
mode->vsync_invert = !!(videomode->sync & FB_SYNC_VERT_HIGH_ACT);
/* no defined flag in fb, use vmode>>3*/
mode->invert_pixclock = !!(videomode->vmode & 8);
mode->pix_fmt_out = output_fmt;
}
static void mmpmode_to_fbmode(struct fb_videomode *videomode,
struct mmp_mode *mode)
{
u64 div_result = 1000000000000ll;
videomode->name = mode->name;
videomode->refresh = mode->refresh;
videomode->xres = mode->xres;
videomode->yres = mode->yres;
do_div(div_result, mode->pixclock_freq);
videomode->pixclock = (u32)div_result;
videomode->left_margin = mode->left_margin;
videomode->right_margin = mode->right_margin;
videomode->upper_margin = mode->upper_margin;
videomode->lower_margin = mode->lower_margin;
videomode->hsync_len = mode->hsync_len;
videomode->vsync_len = mode->vsync_len;
videomode->sync = (mode->hsync_invert ? FB_SYNC_HOR_HIGH_ACT : 0)
| (mode->vsync_invert ? FB_SYNC_VERT_HIGH_ACT : 0);
videomode->vmode = mode->invert_pixclock ? 8 : 0;
}
static int mmpfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct mmpfb_info *fbi = info->par;
if (var->bits_per_pixel == 8)
return -EINVAL;
/*
* Basic geometry sanity checks.
*/
if (var->xoffset + var->xres > var->xres_virtual)
return -EINVAL;
if (var->yoffset + var->yres > var->yres_virtual)
return -EINVAL;
/*
* Check size of framebuffer.
*/
if (var->xres_virtual * var->yres_virtual *
(var->bits_per_pixel >> 3) > fbi->fb_size)
return -EINVAL;
return 0;
}
static unsigned int chan_to_field(unsigned int chan, struct fb_bitfield *bf)
{
return ((chan & 0xffff) >> (16 - bf->length)) << bf->offset;
}
static u32 to_rgb(u16 red, u16 green, u16 blue)
{
red >>= 8;
green >>= 8;
blue >>= 8;
return (red << 16) | (green << 8) | blue;
}
static int mmpfb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int trans, struct fb_info *info)
{
struct mmpfb_info *fbi = info->par;
u32 val;
if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) {
val = chan_to_field(red, &info->var.red);
val |= chan_to_field(green, &info->var.green);
val |= chan_to_field(blue , &info->var.blue);
fbi->pseudo_palette[regno] = val;
}
if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
val = to_rgb(red, green, blue);
/* TODO */
}
return 0;
}
static int mmpfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct mmpfb_info *fbi = info->par;
struct mmp_addr addr;
memset(&addr, 0, sizeof(addr));
addr.phys[0] = (var->yoffset * var->xres_virtual + var->xoffset)
* var->bits_per_pixel / 8 + fbi->fb_start_dma;
mmp_overlay_set_addr(fbi->overlay, &addr);
return 0;
}
static int var_update(struct fb_info *info)
{
struct mmpfb_info *fbi = info->par;
struct fb_var_screeninfo *var = &info->var;
struct fb_videomode *m;
int pix_fmt;
/* set pix_fmt */
pix_fmt = var_to_pixfmt(var);
if (pix_fmt < 0)
return -EINVAL;
pixfmt_to_var(var, pix_fmt);
fbi->pix_fmt = pix_fmt;
/* set var according to best video mode*/
m = (struct fb_videomode *)fb_match_mode(var, &info->modelist);
if (!m) {
dev_err(fbi->dev, "set par: no match mode, use best mode\n");
m = (struct fb_videomode *)fb_find_best_mode(var,
&info->modelist);
fb_videomode_to_var(var, m);
}
memcpy(&fbi->mode, m, sizeof(struct fb_videomode));
/* fix to 2* yres */
var->yres_virtual = var->yres * 2;
info->fix.visual = (pix_fmt == PIXFMT_PSEUDOCOLOR) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
info->fix.ypanstep = var->yres;
return 0;
}
static void mmpfb_set_win(struct fb_info *info)
{
struct mmpfb_info *fbi = info->par;
struct fb_var_screeninfo *var = &info->var;
struct mmp_win win;
u32 stride;
memset(&win, 0, sizeof(win));
win.xsrc = win.xdst = fbi->mode.xres;
win.ysrc = win.ydst = fbi->mode.yres;
win.pix_fmt = fbi->pix_fmt;
stride = pixfmt_to_stride(win.pix_fmt);
win.pitch[0] = var->xres_virtual * stride;
win.pitch[1] = win.pitch[2] =
(stride == 1) ? (var->xres_virtual >> 1) : 0;
mmp_overlay_set_win(fbi->overlay, &win);
}
static int mmpfb_set_par(struct fb_info *info)
{
struct mmpfb_info *fbi = info->par;
struct fb_var_screeninfo *var = &info->var;
struct mmp_addr addr;
struct mmp_mode mode;
int ret;
ret = var_update(info);
if (ret != 0)
return ret;
/* set window/path according to new videomode */
fbmode_to_mmpmode(&mode, &fbi->mode, fbi->output_fmt);
mmp_path_set_mode(fbi->path, &mode);
/* set window related info */
mmpfb_set_win(info);
/* set address always */
memset(&addr, 0, sizeof(addr));
addr.phys[0] = (var->yoffset * var->xres_virtual + var->xoffset)
* var->bits_per_pixel / 8 + fbi->fb_start_dma;
mmp_overlay_set_addr(fbi->overlay, &addr);
return 0;
}
static void mmpfb_power(struct mmpfb_info *fbi, int power)
{
struct mmp_addr addr;
struct fb_var_screeninfo *var = &fbi->fb_info->var;
/* for power on, always set address/window again */
if (power) {
/* set window related info */
mmpfb_set_win(fbi->fb_info);
/* set address always */
memset(&addr, 0, sizeof(addr));
addr.phys[0] = fbi->fb_start_dma +
(var->yoffset * var->xres_virtual + var->xoffset)
* var->bits_per_pixel / 8;
mmp_overlay_set_addr(fbi->overlay, &addr);
}
mmp_overlay_set_onoff(fbi->overlay, power);
}
static int mmpfb_blank(int blank, struct fb_info *info)
{
struct mmpfb_info *fbi = info->par;
mmpfb_power(fbi, (blank == FB_BLANK_UNBLANK));
return 0;
}
static const struct fb_ops mmpfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_blank = mmpfb_blank,
.fb_check_var = mmpfb_check_var,
.fb_set_par = mmpfb_set_par,
.fb_setcolreg = mmpfb_setcolreg,
.fb_pan_display = mmpfb_pan_display,
};
static int modes_setup(struct mmpfb_info *fbi)
{
struct fb_videomode *videomodes;
struct mmp_mode *mmp_modes;
struct fb_info *info = fbi->fb_info;
int videomode_num, i;
/* get videomodes from path */
videomode_num = mmp_path_get_modelist(fbi->path, &mmp_modes);
if (!videomode_num) {
dev_warn(fbi->dev, "can't get videomode num\n");
return 0;
}
/* put videomode list to info structure */
videomodes = kcalloc(videomode_num, sizeof(struct fb_videomode),
GFP_KERNEL);
if (!videomodes)
return -ENOMEM;
for (i = 0; i < videomode_num; i++)
mmpmode_to_fbmode(&videomodes[i], &mmp_modes[i]);
fb_videomode_to_modelist(videomodes, videomode_num, &info->modelist);
/* set videomode[0] as default mode */
memcpy(&fbi->mode, &videomodes[0], sizeof(struct fb_videomode));
fbi->output_fmt = mmp_modes[0].pix_fmt_out;
fb_videomode_to_var(&info->var, &fbi->mode);
mmp_path_set_mode(fbi->path, &mmp_modes[0]);
kfree(videomodes);
return videomode_num;
}
static int fb_info_setup(struct fb_info *info,
struct mmpfb_info *fbi)
{
int ret = 0;
/* Initialise static fb parameters.*/
info->flags = FBINFO_PARTIAL_PAN_OK |
FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN;
info->node = -1;
strcpy(info->fix.id, fbi->name);
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = info->var.yres;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->fix.smem_start = fbi->fb_start_dma;
info->fix.smem_len = fbi->fb_size;
info->fix.visual = (fbi->pix_fmt == PIXFMT_PSEUDOCOLOR) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
info->fix.line_length = info->var.xres_virtual *
info->var.bits_per_pixel / 8;
info->fbops = &mmpfb_ops;
info->pseudo_palette = fbi->pseudo_palette;
info->screen_buffer = fbi->fb_start;
info->screen_size = fbi->fb_size;
/* For FB framework: Allocate color map and Register framebuffer*/
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
ret = -ENOMEM;
return ret;
}
static void fb_info_clear(struct fb_info *info)
{
fb_dealloc_cmap(&info->cmap);
}
static int mmpfb_probe(struct platform_device *pdev)
{
struct mmp_buffer_driver_mach_info *mi;
struct fb_info *info;
struct mmpfb_info *fbi;
int ret, modes_num;
mi = pdev->dev.platform_data;
if (mi == NULL) {
dev_err(&pdev->dev, "no platform data defined\n");
return -EINVAL;
}
/* initialize fb */
info = framebuffer_alloc(sizeof(struct mmpfb_info), &pdev->dev);
if (info == NULL)
return -ENOMEM;
fbi = info->par;
/* init fb */
fbi->fb_info = info;
platform_set_drvdata(pdev, fbi);
fbi->dev = &pdev->dev;
fbi->name = mi->name;
fbi->pix_fmt = mi->default_pixfmt;
pixfmt_to_var(&info->var, fbi->pix_fmt);
mutex_init(&fbi->access_ok);
/* get display path by name */
fbi->path = mmp_get_path(mi->path_name);
if (!fbi->path) {
dev_err(&pdev->dev, "can't get the path %s\n", mi->path_name);
ret = -EINVAL;
goto failed_destroy_mutex;
}
dev_info(fbi->dev, "path %s get\n", fbi->path->name);
/* get overlay */
fbi->overlay = mmp_path_get_overlay(fbi->path, mi->overlay_id);
if (!fbi->overlay) {
ret = -EINVAL;
goto failed_destroy_mutex;
}
/* set fetch used */
mmp_overlay_set_fetch(fbi->overlay, mi->dmafetch_id);
modes_num = modes_setup(fbi);
if (modes_num < 0) {
ret = modes_num;
goto failed_destroy_mutex;
}
/*
* if get modes success, means not hotplug panels, use caculated buffer
* or use default size
*/
if (modes_num > 0) {
/* fix to 2* yres */
info->var.yres_virtual = info->var.yres * 2;
/* Allocate framebuffer memory: size = modes xy *4 */
fbi->fb_size = info->var.xres_virtual * info->var.yres_virtual
* info->var.bits_per_pixel / 8;
} else {
fbi->fb_size = MMPFB_DEFAULT_SIZE;
}
fbi->fb_start = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(fbi->fb_size),
&fbi->fb_start_dma, GFP_KERNEL);
if (fbi->fb_start == NULL) {
dev_err(&pdev->dev, "can't alloc framebuffer\n");
ret = -ENOMEM;
goto failed_destroy_mutex;
}
dev_info(fbi->dev, "fb %dk allocated\n", fbi->fb_size/1024);
/* fb power on */
if (modes_num > 0)
mmpfb_power(fbi, 1);
ret = fb_info_setup(info, fbi);
if (ret < 0)
goto failed_free_buff;
ret = register_framebuffer(info);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register fb: %d\n", ret);
ret = -ENXIO;
goto failed_clear_info;
}
dev_info(fbi->dev, "loaded to /dev/fb%d <%s>.\n",
info->node, info->fix.id);
#ifdef CONFIG_LOGO
if (fbi->fb_start) {
fb_prepare_logo(info, 0);
fb_show_logo(info, 0);
}
#endif
return 0;
failed_clear_info:
fb_info_clear(info);
failed_free_buff:
dma_free_coherent(&pdev->dev, PAGE_ALIGN(fbi->fb_size), fbi->fb_start,
fbi->fb_start_dma);
failed_destroy_mutex:
mutex_destroy(&fbi->access_ok);
dev_err(fbi->dev, "mmp-fb: frame buffer device init failed\n");
framebuffer_release(info);
return ret;
}
static struct platform_driver mmpfb_driver = {
.driver = {
.name = "mmp-fb",
},
.probe = mmpfb_probe,
};
static int mmpfb_init(void)
{
return platform_driver_register(&mmpfb_driver);
}
module_init(mmpfb_init);
MODULE_AUTHOR("Zhou Zhu <[email protected]>");
MODULE_DESCRIPTION("Framebuffer driver for Marvell displays");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/mmp/fb/mmpfb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Geode GX display controller.
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Portions from AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*/
#include <linux/spinlock.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/div64.h>
#include <asm/delay.h>
#include <linux/cs5535.h>
#include "gxfb.h"
unsigned int gx_frame_buffer_size(void)
{
unsigned int val;
if (!cs5535_has_vsa2()) {
uint32_t hi, lo;
/* The number of pages is (PMAX - PMIN)+1 */
rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
/* PMAX */
val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
/* PMIN */
val -= (lo & 0x000fffff);
val += 1;
/* The page size is 4k */
return (val << 12);
}
/* FB size can be obtained from the VSA II */
/* Virtual register class = 0x02 */
/* VG_MEM_SIZE(512Kb units) = 0x00 */
outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFFl;
return (val << 19);
}
int gx_line_delta(int xres, int bpp)
{
/* Must be a multiple of 8 bytes. */
return (xres * (bpp >> 3) + 7) & ~0x7;
}
void gx_set_mode(struct fb_info *info)
{
struct gxfb_par *par = info->par;
u32 gcfg, dcfg;
int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
/* Unlock the display controller registers. */
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
gcfg = read_dc(par, DC_GENERAL_CFG);
dcfg = read_dc(par, DC_DISPLAY_CFG);
/* Disable the timing generator. */
dcfg &= ~DC_DISPLAY_CFG_TGEN;
write_dc(par, DC_DISPLAY_CFG, dcfg);
/* Wait for pending memory requests before disabling the FIFO load. */
udelay(100);
/* Disable FIFO load and compression. */
gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
DC_GENERAL_CFG_DECE);
write_dc(par, DC_GENERAL_CFG, gcfg);
/* Setup DCLK and its divisor. */
gx_set_dclk_frequency(info);
/*
* Setup new mode.
*/
/* Clear all unused feature bits. */
gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
dcfg = 0;
/* Set FIFO priority (default 6/5) and enable. */
/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
(5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
/* Framebuffer start offset. */
write_dc(par, DC_FB_ST_OFFSET, 0);
/* Line delta and line buffer length. */
write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
write_dc(par, DC_LINE_SIZE,
((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
/* Enable graphics and video data and unmask address lines. */
dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
/* Set pixel format. */
switch (info->var.bits_per_pixel) {
case 8:
dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
break;
case 16:
dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
break;
case 32:
dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
dcfg |= DC_DISPLAY_CFG_PALB;
break;
}
/* Enable timing generator. */
dcfg |= DC_DISPLAY_CFG_TGEN;
/* Horizontal and vertical timings. */
hactive = info->var.xres;
hblankstart = hactive;
hsyncstart = hblankstart + info->var.right_margin;
hsyncend = hsyncstart + info->var.hsync_len;
hblankend = hsyncend + info->var.left_margin;
htotal = hblankend;
vactive = info->var.yres;
vblankstart = vactive;
vsyncstart = vblankstart + info->var.lower_margin;
vsyncend = vsyncstart + info->var.vsync_len;
vblankend = vsyncend + info->var.upper_margin;
vtotal = vblankend;
write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) |
((htotal - 1) << 16));
write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
((hblankend - 1) << 16));
write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1) |
((hsyncend - 1) << 16));
write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) |
((vtotal - 1) << 16));
write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
((vblankend - 1) << 16));
write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1) |
((vsyncend - 1) << 16));
/* Write final register values. */
write_dc(par, DC_DISPLAY_CFG, dcfg);
write_dc(par, DC_GENERAL_CFG, gcfg);
gx_configure_display(info);
/* Relock display controller registers */
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
}
void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
unsigned red, unsigned green, unsigned blue)
{
struct gxfb_par *par = info->par;
int val;
/* Hardware palette is in RGB 8-8-8 format. */
val = (red << 8) & 0xff0000;
val |= (green) & 0x00ff00;
val |= (blue >> 8) & 0x0000ff;
write_dc(par, DC_PAL_ADDRESS, regno);
write_dc(par, DC_PAL_DATA, val);
}
| linux-master | drivers/video/fbdev/geode/display_gx.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/video/geode/gx1fb_core.c
* -- Geode GX1 framebuffer driver
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include "geodefb.h"
#include "display_gx1.h"
#include "video_cs5530.h"
static char mode_option[32] = "640x480-16@60";
static int crt_option = 1;
static char panel_option[32] = "";
/* Modes relevant to the GX1 (taken from modedb.c) */
static const struct fb_videomode gx1_modedb[] = {
/* 640x480-60 VESA */
{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-75 VESA */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-85 VESA */
{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-60 VESA */
{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-75 VESA */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-85 VESA */
{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-60 VESA */
{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-75 VESA */
{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-85 VESA */
{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-60 VESA */
{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-85 VESA */
{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-60 VESA */
{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-75 VESA */
{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-85 VESA */
{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
};
static int gx1_line_delta(int xres, int bpp)
{
int line_delta = xres * (bpp >> 3);
if (line_delta > 2048)
line_delta = 4096;
else if (line_delta > 1024)
line_delta = 2048;
else
line_delta = 1024;
return line_delta;
}
static int gx1fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct geodefb_par *par = info->par;
/* Maximum resolution is 1280x1024. */
if (var->xres > 1280 || var->yres > 1024)
return -EINVAL;
if (par->panel_x && (var->xres > par->panel_x || var->yres > par->panel_y))
return -EINVAL;
/* Only 16 bpp and 8 bpp is supported by the hardware. */
if (var->bits_per_pixel == 16) {
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
var->transp.offset = 0; var->transp.length = 0;
} else if (var->bits_per_pixel == 8) {
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
var->transp.offset = 0; var->transp.length = 0;
} else
return -EINVAL;
/* Enough video memory? */
if (gx1_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
return -EINVAL;
/* FIXME: Check timing parameters here? */
return 0;
}
static int gx1fb_set_par(struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (info->var.bits_per_pixel == 16)
info->fix.visual = FB_VISUAL_TRUECOLOR;
else
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = gx1_line_delta(info->var.xres, info->var.bits_per_pixel);
par->dc_ops->set_mode(info);
return 0;
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int gx1fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *pal = info->pseudo_palette;
u32 v;
if (regno >= 16)
return -EINVAL;
v = chan_to_field(red, &info->var.red);
v |= chan_to_field(green, &info->var.green);
v |= chan_to_field(blue, &info->var.blue);
pal[regno] = v;
} else {
if (regno >= 256)
return -EINVAL;
par->dc_ops->set_palette_reg(info, regno, red, green, blue);
}
return 0;
}
static int gx1fb_blank(int blank_mode, struct fb_info *info)
{
struct geodefb_par *par = info->par;
return par->vid_ops->blank_display(info, blank_mode);
}
static int gx1fb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
{
struct geodefb_par *par = info->par;
unsigned gx_base;
int fb_len;
int ret;
gx_base = gx1_gx_base();
if (!gx_base)
return -ENODEV;
ret = pci_enable_device(dev);
if (ret < 0)
return ret;
ret = pci_request_region(dev, 0, "gx1fb (video)");
if (ret < 0)
return ret;
par->vid_regs = pci_ioremap_bar(dev, 0);
if (!par->vid_regs)
return -ENOMEM;
if (!request_mem_region(gx_base + 0x8300, 0x100, "gx1fb (display controller)"))
return -EBUSY;
par->dc_regs = ioremap(gx_base + 0x8300, 0x100);
if (!par->dc_regs)
return -ENOMEM;
if ((fb_len = gx1_frame_buffer_size()) < 0)
return -ENOMEM;
info->fix.smem_start = gx_base + 0x800000;
info->fix.smem_len = fb_len;
info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
if (!info->screen_base)
return -ENOMEM;
dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
info->fix.smem_len / 1024, info->fix.smem_start);
return 0;
}
static int parse_panel_option(struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (strcmp(panel_option, "") != 0) {
int x, y;
char *s;
x = simple_strtol(panel_option, &s, 10);
if (!x)
return -EINVAL;
y = simple_strtol(s + 1, NULL, 10);
if (!y)
return -EINVAL;
par->panel_x = x;
par->panel_y = y;
}
return 0;
}
static const struct fb_ops gx1fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = gx1fb_check_var,
.fb_set_par = gx1fb_set_par,
.fb_setcolreg = gx1fb_setcolreg,
.fb_blank = gx1fb_blank,
};
static struct fb_info *gx1fb_init_fbinfo(struct device *dev)
{
struct geodefb_par *par;
struct fb_info *info;
/* Alloc enough space for the pseudo palette. */
info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
if (!info)
return NULL;
par = info->par;
strcpy(info->fix.id, "GX1");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &gx1fb_ops;
info->node = -1;
info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);
info->var.grayscale = 0;
/* CRT and panel options */
par->enable_crt = crt_option;
if (parse_panel_option(info) < 0)
printk(KERN_WARNING "gx1fb: invalid 'panel' option -- disabling flat panel\n");
if (!par->panel_x)
par->enable_crt = 1; /* fall back to CRT if no panel is specified */
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
framebuffer_release(info);
return NULL;
}
return info;
}
static int gx1fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct geodefb_par *par;
struct fb_info *info;
int ret;
ret = aperture_remove_conflicting_pci_devices(pdev, "gx1fb");
if (ret)
return ret;
info = gx1fb_init_fbinfo(&pdev->dev);
if (!info)
return -ENOMEM;
par = info->par;
/* GX1 display controller and CS5530 video device */
par->dc_ops = &gx1_dc_ops;
par->vid_ops = &cs5530_vid_ops;
if ((ret = gx1fb_map_video_memory(info, pdev)) < 0) {
dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
goto err;
}
ret = fb_find_mode(&info->var, info, mode_option,
gx1_modedb, ARRAY_SIZE(gx1_modedb), NULL, 16);
if (ret == 0 || ret == 4) {
dev_err(&pdev->dev, "could not find valid video mode\n");
ret = -EINVAL;
goto err;
}
/* Clear the frame buffer of garbage. */
memset_io(info->screen_base, 0, info->fix.smem_len);
gx1fb_check_var(&info->var, info);
gx1fb_set_par(info);
if (register_framebuffer(info) < 0) {
ret = -EINVAL;
goto err;
}
pci_set_drvdata(pdev, info);
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
err:
if (info->screen_base) {
iounmap(info->screen_base);
pci_release_region(pdev, 0);
}
if (par->vid_regs) {
iounmap(par->vid_regs);
pci_release_region(pdev, 1);
}
if (par->dc_regs) {
iounmap(par->dc_regs);
release_mem_region(gx1_gx_base() + 0x8300, 0x100);
}
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
return ret;
}
static void gx1fb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct geodefb_par *par = info->par;
unregister_framebuffer(info);
iounmap((void __iomem *)info->screen_base);
pci_release_region(pdev, 0);
iounmap(par->vid_regs);
pci_release_region(pdev, 1);
iounmap(par->dc_regs);
release_mem_region(gx1_gx_base() + 0x8300, 0x100);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
#ifndef MODULE
static void __init gx1fb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return;
while ((this_opt = strsep(&options, ","))) {
if (!*this_opt)
continue;
if (!strncmp(this_opt, "mode:", 5))
strscpy(mode_option, this_opt + 5, sizeof(mode_option));
else if (!strncmp(this_opt, "crt:", 4))
crt_option = !!simple_strtoul(this_opt + 4, NULL, 0);
else if (!strncmp(this_opt, "panel:", 6))
strscpy(panel_option, this_opt + 6, sizeof(panel_option));
else
strscpy(mode_option, this_opt, sizeof(mode_option));
}
}
#endif
static struct pci_device_id gx1fb_id_table[] = {
{ PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_VIDEO,
PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
0xff0000, 0 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, gx1fb_id_table);
static struct pci_driver gx1fb_driver = {
.name = "gx1fb",
.id_table = gx1fb_id_table,
.probe = gx1fb_probe,
.remove = gx1fb_remove,
};
static int __init gx1fb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("gx1fb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("gx1fb", &option))
return -ENODEV;
gx1fb_setup(option);
#endif
return pci_register_driver(&gx1fb_driver);
}
static void gx1fb_cleanup(void)
{
pci_unregister_driver(&gx1fb_driver);
}
module_init(gx1fb_init);
module_exit(gx1fb_cleanup);
module_param_string(mode, mode_option, sizeof(mode_option), 0444);
MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");
module_param_named(crt, crt_option, int, 0444);
MODULE_PARM_DESC(crt, "enable CRT output. 0 = off, 1 = on (default)");
module_param_string(panel, panel_option, sizeof(panel_option), 0444);
MODULE_PARM_DESC(panel, "size of attached flat panel (<x>x<y>)");
MODULE_DESCRIPTION("framebuffer driver for the AMD Geode GX1");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/geode/gx1fb_core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/* Geode LX framebuffer driver
*
* Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <linux/uaccess.h>
#include <linux/delay.h>
#include <linux/cs5535.h>
#include "lxfb.h"
/* TODO
* Support panel scaling
* Add acceleration
* Add support for interlacing (TV out)
* Support compression
*/
/* This is the complete list of PLL frequencies that we can set -
* we will choose the closest match to the incoming clock.
* freq is the frequency of the dotclock * 1000 (for example,
* 24823 = 24.983 Mhz).
* pllval is the corresponding PLL value
*/
static const struct {
unsigned int pllval;
unsigned int freq;
} pll_table[] = {
{ 0x000131AC, 6231 },
{ 0x0001215D, 6294 },
{ 0x00011087, 6750 },
{ 0x0001216C, 7081 },
{ 0x0001218D, 7140 },
{ 0x000110C9, 7800 },
{ 0x00013147, 7875 },
{ 0x000110A7, 8258 },
{ 0x00012159, 8778 },
{ 0x00014249, 8875 },
{ 0x00010057, 9000 },
{ 0x0001219A, 9472 },
{ 0x00012158, 9792 },
{ 0x00010045, 10000 },
{ 0x00010089, 10791 },
{ 0x000110E7, 11225 },
{ 0x00012136, 11430 },
{ 0x00013207, 12375 },
{ 0x00012187, 12500 },
{ 0x00014286, 14063 },
{ 0x000110E5, 15016 },
{ 0x00014214, 16250 },
{ 0x00011105, 17045 },
{ 0x000131E4, 18563 },
{ 0x00013183, 18750 },
{ 0x00014284, 19688 },
{ 0x00011104, 20400 },
{ 0x00016363, 23625 },
{ 0x000031AC, 24923 },
{ 0x0000215D, 25175 },
{ 0x00001087, 27000 },
{ 0x0000216C, 28322 },
{ 0x0000218D, 28560 },
{ 0x000010C9, 31200 },
{ 0x00003147, 31500 },
{ 0x000010A7, 33032 },
{ 0x00002159, 35112 },
{ 0x00004249, 35500 },
{ 0x00000057, 36000 },
{ 0x0000219A, 37889 },
{ 0x00002158, 39168 },
{ 0x00000045, 40000 },
{ 0x00000089, 43163 },
{ 0x000010E7, 44900 },
{ 0x00002136, 45720 },
{ 0x00003207, 49500 },
{ 0x00002187, 50000 },
{ 0x00004286, 56250 },
{ 0x000010E5, 60065 },
{ 0x00004214, 65000 },
{ 0x00001105, 68179 },
{ 0x000031E4, 74250 },
{ 0x00003183, 75000 },
{ 0x00004284, 78750 },
{ 0x00001104, 81600 },
{ 0x00006363, 94500 },
{ 0x00005303, 97520 },
{ 0x00002183, 100187 },
{ 0x00002122, 101420 },
{ 0x00001081, 108000 },
{ 0x00006201, 113310 },
{ 0x00000041, 119650 },
{ 0x000041A1, 129600 },
{ 0x00002182, 133500 },
{ 0x000041B1, 135000 },
{ 0x00000051, 144000 },
{ 0x000041E1, 148500 },
{ 0x000062D1, 157500 },
{ 0x000031A1, 162000 },
{ 0x00000061, 169203 },
{ 0x00004231, 172800 },
{ 0x00002151, 175500 },
{ 0x000052E1, 189000 },
{ 0x00000071, 192000 },
{ 0x00003201, 198000 },
{ 0x00004291, 202500 },
{ 0x00001101, 204750 },
{ 0x00007481, 218250 },
{ 0x00004170, 229500 },
{ 0x00006210, 234000 },
{ 0x00003140, 251182 },
{ 0x00006250, 261000 },
{ 0x000041C0, 278400 },
{ 0x00005220, 280640 },
{ 0x00000050, 288000 },
{ 0x000041E0, 297000 },
{ 0x00002130, 320207 }
};
static void lx_set_dotpll(u32 pllval)
{
u32 dotpll_lo, dotpll_hi;
int i;
rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
return;
dotpll_hi = pllval;
dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX);
dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
/* Wait 100us for the PLL to lock */
udelay(100);
/* Now, loop for the lock bit */
for (i = 0; i < 1000; i++) {
rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
break;
}
/* Clear the reset bit */
dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
}
/* Set the clock based on the frequency specified by the current mode */
static void lx_set_clock(struct fb_info *info)
{
unsigned int diff, min, best = 0;
unsigned int freq, i;
freq = (unsigned int) (1000000000 / info->var.pixclock);
min = abs(pll_table[0].freq - freq);
for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
diff = abs(pll_table[i].freq - freq);
if (diff < min) {
min = diff;
best = i;
}
}
lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
}
static void lx_graphics_disable(struct fb_info *info)
{
struct lxfb_par *par = info->par;
unsigned int val, gcfg;
/* Note: This assumes that the video is in a quitet state */
write_vp(par, VP_A1T, 0);
write_vp(par, VP_A2T, 0);
write_vp(par, VP_A3T, 0);
/* Turn off the VGA and video enable */
val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE |
DC_GENERAL_CFG_VIDE);
write_dc(par, DC_GENERAL_CFG, val);
val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN;
write_vp(par, VP_VCFG, val);
write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK |
DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS);
val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN;
write_dc(par, DC_GENLK_CTL, val);
val = read_dc(par, DC_CLR_KEY);
write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN);
/* turn off the panel */
write_fp(par, FP_PM, read_fp(par, FP_PM) & ~FP_PM_P);
val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN;
write_vp(par, VP_MISC, val);
/* Turn off the display */
val = read_vp(par, VP_DCFG);
write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN));
gcfg = read_dc(par, DC_GENERAL_CFG);
gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE);
write_dc(par, DC_GENERAL_CFG, gcfg);
/* Turn off the TGEN */
val = read_dc(par, DC_DISPLAY_CFG);
val &= ~DC_DISPLAY_CFG_TGEN;
write_dc(par, DC_DISPLAY_CFG, val);
/* Wait 1000 usecs to ensure that the TGEN is clear */
udelay(1000);
/* Turn off the FIFO loader */
gcfg &= ~DC_GENERAL_CFG_DFLE;
write_dc(par, DC_GENERAL_CFG, gcfg);
/* Lastly, wait for the GP to go idle */
do {
val = read_gp(par, GP_BLT_STATUS);
} while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE));
}
static void lx_graphics_enable(struct fb_info *info)
{
struct lxfb_par *par = info->par;
u32 temp, config;
/* Set the video request register */
write_vp(par, VP_VRR, 0);
/* Set up the polarities */
config = read_vp(par, VP_DCFG);
config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY |
VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL);
config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT
| VP_DCFG_GV_GAM);
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
config |= VP_DCFG_CRT_HSYNC_POL;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
config |= VP_DCFG_CRT_VSYNC_POL;
if (par->output & OUTPUT_PANEL) {
u32 msrlo, msrhi;
write_fp(par, FP_PT1, 0);
temp = FP_PT2_SCRC;
if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
temp |= FP_PT2_HSP;
if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
temp |= FP_PT2_VSP;
write_fp(par, FP_PT2, temp);
write_fp(par, FP_DFC, FP_DFC_BC);
msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW;
msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH;
wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
}
if (par->output & OUTPUT_CRT) {
config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN |
VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN;
}
write_vp(par, VP_DCFG, config);
/* Turn the CRT dacs back on */
if (par->output & OUTPUT_CRT) {
temp = read_vp(par, VP_MISC);
temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN);
write_vp(par, VP_MISC, temp);
}
/* Turn the panel on (if it isn't already) */
if (par->output & OUTPUT_PANEL)
write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P);
}
unsigned int lx_framebuffer_size(void)
{
unsigned int val;
if (!cs5535_has_vsa2()) {
uint32_t hi, lo;
/* The number of pages is (PMAX - PMIN)+1 */
rdmsr(MSR_GLIU_P2D_RO0, lo, hi);
/* PMAX */
val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
/* PMIN */
val -= (lo & 0x000fffff);
val += 1;
/* The page size is 4k */
return (val << 12);
}
/* The frame buffer size is reported by a VSM in VSA II */
/* Virtual Register Class = 0x02 */
/* VG_MEM_SIZE (1MB units) = 0x00 */
outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX);
val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE;
return (val << 20);
}
void lx_set_mode(struct fb_info *info)
{
struct lxfb_par *par = info->par;
u64 msrval;
unsigned int max, dv, val, size;
unsigned int gcfg, dcfg;
int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
/* Unlock the DC registers */
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
lx_graphics_disable(info);
lx_set_clock(info);
/* Set output mode */
rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT;
if (par->output & OUTPUT_PANEL) {
msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP;
if (par->output & OUTPUT_CRT)
msrval |= MSR_LX_GLD_MSR_CONFIG_FPC;
else
msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC;
} else
msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT;
wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
/* Clear the various buffers */
/* FIXME: Adjust for panning here */
write_dc(par, DC_FB_ST_OFFSET, 0);
write_dc(par, DC_CB_ST_OFFSET, 0);
write_dc(par, DC_CURS_ST_OFFSET, 0);
/* FIXME: Add support for interlacing */
/* FIXME: Add support for scaling */
val = read_dc(par, DC_GENLK_CTL);
val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN |
DC_GENLK_CTL_FLICK_SEL_MASK);
/* Default scaling params */
write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
write_dc(par, DC_IRQ_FILT_CTL, 0);
write_dc(par, DC_GENLK_CTL, val);
/* FIXME: Support compression */
if (info->fix.line_length > 4096)
dv = DC_DV_CTL_DV_LINE_SIZE_8K;
else if (info->fix.line_length > 2048)
dv = DC_DV_CTL_DV_LINE_SIZE_4K;
else if (info->fix.line_length > 1024)
dv = DC_DV_CTL_DV_LINE_SIZE_2K;
else
dv = DC_DV_CTL_DV_LINE_SIZE_1K;
max = info->fix.line_length * info->var.yres;
max = (max + 0x3FF) & 0xFFFFFC00;
write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN);
val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE;
write_dc(par, DC_DV_CTL, val | dv);
size = info->var.xres * (info->var.bits_per_pixel >> 3);
write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
/* Set default watermark values */
rdmsrl(MSR_LX_SPARE_MSR, msrval);
msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO
| MSR_LX_SPARE_MSR_VFIFO_ARB_SEL
| MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M
| MSR_LX_SPARE_MSR_WM_LPEN_OVRD);
msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM |
MSR_LX_SPARE_MSR_DIS_INIT_V_PRI;
wrmsrl(MSR_LX_SPARE_MSR, msrval);
gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */
gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */
(0xb << DC_GENERAL_CFG_DFHPEL_SHIFT);
gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */
dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */
dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */
dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */
dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */
dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */
dcfg |= DC_DISPLAY_CFG_VISL;
dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */
/* Set the current BPP mode */
switch (info->var.bits_per_pixel) {
case 8:
dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
break;
case 16:
dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
break;
case 32:
case 24:
dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
break;
}
/* Now - set up the timings */
hactive = info->var.xres;
hblankstart = hactive;
hsyncstart = hblankstart + info->var.right_margin;
hsyncend = hsyncstart + info->var.hsync_len;
hblankend = hsyncend + info->var.left_margin;
htotal = hblankend;
vactive = info->var.yres;
vblankstart = vactive;
vsyncstart = vblankstart + info->var.lower_margin;
vsyncend = vsyncstart + info->var.vsync_len;
vblankend = vsyncend + info->var.upper_margin;
vtotal = vblankend;
write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
write_dc(par, DC_H_BLANK_TIMING,
(hblankstart - 1) | ((hblankend - 1) << 16));
write_dc(par, DC_H_SYNC_TIMING,
(hsyncstart - 1) | ((hsyncend - 1) << 16));
write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
write_dc(par, DC_V_BLANK_TIMING,
(vblankstart - 1) | ((vblankend - 1) << 16));
write_dc(par, DC_V_SYNC_TIMING,
(vsyncstart - 1) | ((vsyncend - 1) << 16));
write_dc(par, DC_FB_ACTIVE,
(info->var.xres - 1) << 16 | (info->var.yres - 1));
/* And re-enable the graphics output */
lx_graphics_enable(info);
/* Write the two main configuration registers */
write_dc(par, DC_DISPLAY_CFG, dcfg);
write_dc(par, DC_ARB_CFG, 0);
write_dc(par, DC_GENERAL_CFG, gcfg);
/* Lock the DC registers */
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
}
void lx_set_palette_reg(struct fb_info *info, unsigned regno,
unsigned red, unsigned green, unsigned blue)
{
struct lxfb_par *par = info->par;
int val;
/* Hardware palette is in RGB 8-8-8 format. */
val = (red << 8) & 0xff0000;
val |= (green) & 0x00ff00;
val |= (blue >> 8) & 0x0000ff;
write_dc(par, DC_PAL_ADDRESS, regno);
write_dc(par, DC_PAL_DATA, val);
}
int lx_blank_display(struct fb_info *info, int blank_mode)
{
struct lxfb_par *par = info->par;
u32 dcfg, misc, fp_pm;
int blank, hsync, vsync;
/* CRT power saving modes. */
switch (blank_mode) {
case FB_BLANK_UNBLANK:
blank = 0; hsync = 1; vsync = 1;
break;
case FB_BLANK_NORMAL:
blank = 1; hsync = 1; vsync = 1;
break;
case FB_BLANK_VSYNC_SUSPEND:
blank = 1; hsync = 1; vsync = 0;
break;
case FB_BLANK_HSYNC_SUSPEND:
blank = 1; hsync = 0; vsync = 1;
break;
case FB_BLANK_POWERDOWN:
blank = 1; hsync = 0; vsync = 0;
break;
default:
return -EINVAL;
}
dcfg = read_vp(par, VP_DCFG);
dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
VP_DCFG_CRT_EN);
if (!blank)
dcfg |= VP_DCFG_DAC_BL_EN | VP_DCFG_CRT_EN;
if (hsync)
dcfg |= VP_DCFG_HSYNC_EN;
if (vsync)
dcfg |= VP_DCFG_VSYNC_EN;
write_vp(par, VP_DCFG, dcfg);
misc = read_vp(par, VP_MISC);
if (vsync && hsync)
misc &= ~VP_MISC_DACPWRDN;
else
misc |= VP_MISC_DACPWRDN;
write_vp(par, VP_MISC, misc);
/* Power on/off flat panel */
if (par->output & OUTPUT_PANEL) {
fp_pm = read_fp(par, FP_PM);
if (blank_mode == FB_BLANK_POWERDOWN)
fp_pm &= ~FP_PM_P;
else
fp_pm |= FP_PM_P;
write_fp(par, FP_PM, fp_pm);
}
return 0;
}
static void lx_save_regs(struct lxfb_par *par)
{
uint32_t filt;
int i;
/* wait for the BLT engine to stop being busy */
do {
i = read_gp(par, GP_BLT_STATUS);
} while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE));
/* save MSRs */
rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
/* save registers */
memcpy(par->gp, par->gp_regs, sizeof(par->gp));
memcpy(par->dc, par->dc_regs, sizeof(par->dc));
memcpy(par->vp, par->vp_regs, sizeof(par->vp));
memcpy(par->fp, par->vp_regs + VP_FP_START, sizeof(par->fp));
/* save the display controller palette */
write_dc(par, DC_PAL_ADDRESS, 0);
for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++)
par->dc_pal[i] = read_dc(par, DC_PAL_DATA);
/* save the video processor palette */
write_vp(par, VP_PAR, 0);
for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++)
par->vp_pal[i] = read_vp(par, VP_PDR);
/* save the horizontal filter coefficients */
filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1);
par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2);
}
/* save the vertical filter coefficients */
filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1);
}
/* save video coeff ram */
memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff));
}
static void lx_restore_gfx_proc(struct lxfb_par *par)
{
int i;
/* a bunch of registers require GP_RASTER_MODE to be set first */
write_gp(par, GP_RASTER_MODE, par->gp[GP_RASTER_MODE]);
for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
switch (i) {
case GP_RASTER_MODE:
case GP_VECTOR_MODE:
case GP_BLT_MODE:
case GP_BLT_STATUS:
case GP_HST_SRC:
/* FIXME: restore LUT data */
case GP_LUT_INDEX:
case GP_LUT_DATA:
/* don't restore these registers */
break;
default:
write_gp(par, i, par->gp[i]);
}
}
}
static void lx_restore_display_ctlr(struct lxfb_par *par)
{
uint32_t filt;
int i;
wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare);
for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
switch (i) {
case DC_UNLOCK:
/* unlock the DC; runs first */
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
break;
case DC_GENERAL_CFG:
case DC_DISPLAY_CFG:
/* disable all while restoring */
write_dc(par, i, 0);
break;
case DC_DV_CTL:
/* set all ram to dirty */
write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM);
break;
case DC_RSVD_1:
case DC_RSVD_2:
case DC_RSVD_3:
case DC_LINE_CNT:
case DC_PAL_ADDRESS:
case DC_PAL_DATA:
case DC_DFIFO_DIAG:
case DC_CFIFO_DIAG:
case DC_FILT_COEFF1:
case DC_FILT_COEFF2:
case DC_RSVD_4:
case DC_RSVD_5:
/* don't restore these registers */
break;
default:
write_dc(par, i, par->dc[i]);
}
}
/* restore the palette */
write_dc(par, DC_PAL_ADDRESS, 0);
for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++)
write_dc(par, DC_PAL_DATA, par->dc_pal[i]);
/* restore the horizontal filter coefficients */
filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL;
for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) {
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]);
write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]);
}
/* restore the vertical filter coefficients */
filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL;
for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) {
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i);
write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]);
}
}
static void lx_restore_video_proc(struct lxfb_par *par)
{
int i;
wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg);
wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel);
for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
switch (i) {
case VP_VCFG:
case VP_DCFG:
case VP_PAR:
case VP_PDR:
case VP_CCS:
case VP_RSVD_0:
/* case VP_VDC: */ /* why should this not be restored? */
case VP_RSVD_1:
case VP_CRC32:
/* don't restore these registers */
break;
default:
write_vp(par, i, par->vp[i]);
}
}
/* restore video processor palette */
write_vp(par, VP_PAR, 0);
for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++)
write_vp(par, VP_PDR, par->vp_pal[i]);
/* restore video coeff ram */
memcpy(par->vp_regs + VP_VCR, par->vp_coeff, sizeof(par->vp_coeff));
}
static void lx_restore_regs(struct lxfb_par *par)
{
int i;
lx_set_dotpll((u32) (par->msr.dotpll >> 32));
lx_restore_gfx_proc(par);
lx_restore_display_ctlr(par);
lx_restore_video_proc(par);
/* Flat Panel */
for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
switch (i) {
case FP_PM:
case FP_RSVD_0:
case FP_RSVD_1:
case FP_RSVD_2:
case FP_RSVD_3:
case FP_RSVD_4:
/* don't restore these registers */
break;
default:
write_fp(par, i, par->fp[i]);
}
}
/* control the panel */
if (par->fp[FP_PM] & FP_PM_P) {
/* power on the panel if not already power{ed,ing} on */
if (!(read_fp(par, FP_PM) &
(FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
write_fp(par, FP_PM, par->fp[FP_PM]);
} else {
/* power down the panel if not already power{ed,ing} down */
if (!(read_fp(par, FP_PM) &
(FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
write_fp(par, FP_PM, par->fp[FP_PM]);
}
/* turn everything on */
write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
/* do this last; it will enable the FIFO load */
write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
/* lock the door behind us */
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
}
int lx_powerdown(struct fb_info *info)
{
struct lxfb_par *par = info->par;
if (par->powered_down)
return 0;
lx_save_regs(par);
lx_graphics_disable(info);
par->powered_down = 1;
return 0;
}
int lx_powerup(struct fb_info *info)
{
struct lxfb_par *par = info->par;
if (!par->powered_down)
return 0;
lx_restore_regs(par);
par->powered_down = 0;
return 0;
}
| linux-master | drivers/video/fbdev/geode/lxfb_ops.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Geode GX framebuffer driver.
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* This driver assumes that the BIOS has created a virtual PCI device header
* for the video device. The PCI header is assumed to contain the following
* BARs:
*
* BAR0 - framebuffer memory
* BAR1 - graphics processor registers
* BAR2 - display controller registers
* BAR3 - video processor and flat panel control registers.
*
* 16 MiB of framebuffer memory is assumed to be available.
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/console.h>
#include <linux/suspend.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/cs5535.h>
#include <asm/olpc.h>
#include "gxfb.h"
static char *mode_option;
static int vram;
static int vt_switch;
/* Modes relevant to the GX (taken from modedb.c) */
static struct fb_videomode gx_modedb[] = {
/* 640x480-60 VESA */
{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-75 VESA */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-85 VESA */
{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-60 VESA */
{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-75 VESA */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-85 VESA */
{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-60 VESA */
{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-75 VESA */
{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-85 VESA */
{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-60 VESA */
{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-85 VESA */
{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-60 VESA */
{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-75 VESA */
{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-85 VESA */
{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-60 VESA */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-75 VESA */
{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-85 VESA */
{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
};
static struct fb_videomode gx_dcon_modedb[] = {
/* The only mode the DCON has is 1200x900 */
{ NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 }
};
static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
{
if (olpc_has_dcon()) {
*modedb = (struct fb_videomode *) gx_dcon_modedb;
*size = ARRAY_SIZE(gx_dcon_modedb);
} else {
*modedb = (struct fb_videomode *) gx_modedb;
*size = ARRAY_SIZE(gx_modedb);
}
}
static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (var->xres > 1600 || var->yres > 1200)
return -EINVAL;
if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
return -EINVAL;
if (var->bits_per_pixel == 32) {
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else if (var->bits_per_pixel == 16) {
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
} else if (var->bits_per_pixel == 8) {
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else
return -EINVAL;
var->transp.offset = 0; var->transp.length = 0;
/* Enough video memory? */
if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
return -EINVAL;
/* FIXME: Check timing parameters here? */
return 0;
}
static int gxfb_set_par(struct fb_info *info)
{
if (info->var.bits_per_pixel > 8)
info->fix.visual = FB_VISUAL_TRUECOLOR;
else
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
gx_set_mode(info);
return 0;
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *pal = info->pseudo_palette;
u32 v;
if (regno >= 16)
return -EINVAL;
v = chan_to_field(red, &info->var.red);
v |= chan_to_field(green, &info->var.green);
v |= chan_to_field(blue, &info->var.blue);
pal[regno] = v;
} else {
if (regno >= 256)
return -EINVAL;
gx_set_hw_palette_reg(info, regno, red, green, blue);
}
return 0;
}
static int gxfb_blank(int blank_mode, struct fb_info *info)
{
return gx_blank_display(info, blank_mode);
}
static int gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
{
struct gxfb_par *par = info->par;
int ret;
ret = pci_enable_device(dev);
if (ret < 0)
return ret;
ret = pci_request_region(dev, 3, "gxfb (video processor)");
if (ret < 0)
return ret;
par->vid_regs = pci_ioremap_bar(dev, 3);
if (!par->vid_regs)
return -ENOMEM;
ret = pci_request_region(dev, 2, "gxfb (display controller)");
if (ret < 0)
return ret;
par->dc_regs = pci_ioremap_bar(dev, 2);
if (!par->dc_regs)
return -ENOMEM;
ret = pci_request_region(dev, 1, "gxfb (graphics processor)");
if (ret < 0)
return ret;
par->gp_regs = pci_ioremap_bar(dev, 1);
if (!par->gp_regs)
return -ENOMEM;
ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
if (ret < 0)
return ret;
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = vram ? vram : gx_frame_buffer_size();
info->screen_base = ioremap_wc(info->fix.smem_start,
info->fix.smem_len);
if (!info->screen_base)
return -ENOMEM;
/* Set the 16MiB aligned base address of the graphics memory region
* in the display controller */
write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n",
info->fix.smem_len / 1024, info->fix.smem_start);
return 0;
}
static const struct fb_ops gxfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = gxfb_check_var,
.fb_set_par = gxfb_set_par,
.fb_setcolreg = gxfb_setcolreg,
.fb_blank = gxfb_blank,
};
static struct fb_info *gxfb_init_fbinfo(struct device *dev)
{
struct gxfb_par *par;
struct fb_info *info;
/* Alloc enough space for the pseudo palette. */
info = framebuffer_alloc(sizeof(struct gxfb_par) + sizeof(u32) * 16,
dev);
if (!info)
return NULL;
par = info->par;
strcpy(info->fix.id, "Geode GX");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &gxfb_ops;
info->node = -1;
info->pseudo_palette = (void *)par + sizeof(struct gxfb_par);
info->var.grayscale = 0;
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
framebuffer_release(info);
return NULL;
}
return info;
}
static int __maybe_unused gxfb_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
console_lock();
gx_powerdown(info);
fb_set_suspend(info, 1);
console_unlock();
/* there's no point in setting PCI states; we emulate PCI, so
* we don't end up getting power savings anyways */
return 0;
}
static int __maybe_unused gxfb_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
int ret;
console_lock();
ret = gx_powerup(info);
if (ret) {
printk(KERN_ERR "gxfb: power up failed!\n");
return ret;
}
fb_set_suspend(info, 0);
console_unlock();
return 0;
}
static int gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct gxfb_par *par;
struct fb_info *info;
int ret;
unsigned long val;
struct fb_videomode *modedb_ptr;
unsigned int modedb_size;
ret = aperture_remove_conflicting_pci_devices(pdev, "gxfb");
if (ret)
return ret;
info = gxfb_init_fbinfo(&pdev->dev);
if (!info)
return -ENOMEM;
par = info->par;
if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
goto err;
}
/* Figure out if this is a TFT or CRT part */
rdmsrl(MSR_GX_GLD_MSR_CONFIG, val);
if ((val & MSR_GX_GLD_MSR_CONFIG_FP) == MSR_GX_GLD_MSR_CONFIG_FP)
par->enable_crt = 0;
else
par->enable_crt = 1;
get_modedb(&modedb_ptr, &modedb_size);
ret = fb_find_mode(&info->var, info, mode_option,
modedb_ptr, modedb_size, NULL, 16);
if (ret == 0 || ret == 4) {
dev_err(&pdev->dev, "could not find valid video mode\n");
ret = -EINVAL;
goto err;
}
/* Clear the frame buffer of garbage. */
memset_io(info->screen_base, 0, info->fix.smem_len);
gxfb_check_var(&info->var, info);
gxfb_set_par(info);
pm_set_vt_switch(vt_switch);
if (register_framebuffer(info) < 0) {
ret = -EINVAL;
goto err;
}
pci_set_drvdata(pdev, info);
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
err:
if (info->screen_base) {
iounmap(info->screen_base);
pci_release_region(pdev, 0);
}
if (par->vid_regs) {
iounmap(par->vid_regs);
pci_release_region(pdev, 3);
}
if (par->dc_regs) {
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
}
if (par->gp_regs) {
iounmap(par->gp_regs);
pci_release_region(pdev, 1);
}
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
return ret;
}
static void gxfb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct gxfb_par *par = info->par;
unregister_framebuffer(info);
iounmap((void __iomem *)info->screen_base);
pci_release_region(pdev, 0);
iounmap(par->vid_regs);
pci_release_region(pdev, 3);
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
iounmap(par->gp_regs);
pci_release_region(pdev, 1);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
static const struct pci_device_id gxfb_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, gxfb_id_table);
static const struct dev_pm_ops gxfb_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = gxfb_suspend,
.resume = gxfb_resume,
.freeze = NULL,
.thaw = gxfb_resume,
.poweroff = NULL,
.restore = gxfb_resume,
#endif
};
static struct pci_driver gxfb_driver = {
.name = "gxfb",
.id_table = gxfb_id_table,
.probe = gxfb_probe,
.remove = gxfb_remove,
.driver.pm = &gxfb_pm_ops,
};
#ifndef MODULE
static int __init gxfb_setup(char *options)
{
char *opt;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
mode_option = opt;
}
return 0;
}
#endif
static int __init gxfb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("gxfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("gxfb", &option))
return -ENODEV;
gxfb_setup(option);
#endif
return pci_register_driver(&gxfb_driver);
}
static void __exit gxfb_cleanup(void)
{
pci_unregister_driver(&gxfb_driver);
}
module_init(gxfb_init);
module_exit(gxfb_cleanup);
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
module_param(vram, int, 0);
MODULE_PARM_DESC(vram, "video memory size");
module_param(vt_switch, int, 0);
MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/geode/gxfb_core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Geode LX framebuffer driver.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Built from gxfb (which is Copyright (C) 2006 Arcom Control Systems Ltd.)
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/console.h>
#include <linux/mm.h>
#include <linux/suspend.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/uaccess.h>
#include <asm/olpc.h>
#include "lxfb.h"
static char *mode_option;
static int noclear, nopanel, nocrt;
static int vram;
static int vt_switch;
/* Most of these modes are sorted in ascending order, but
* since the first entry in this table is the "default" mode,
* we try to make it something sane - 640x480-60 is sane
*/
static struct fb_videomode geode_modedb[] = {
/* 640x480-60 */
{ NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x400-70 */
{ NULL, 70, 640, 400, 39770, 40, 8, 28, 5, 96, 2,
FB_SYNC_HOR_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x480-70 */
{ NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 640x480-72 */
{ NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x480-75 */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x480-85 */
{ NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 640x480-90 */
{ NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 640x480-100 */
{ NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 640x480-60 */
{ NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 800x600-56 */
{ NULL, 56, 800, 600, 27901, 128, 24, 22, 1, 72, 2,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-60 */
{ NULL, 60, 800, 600, 25131, 72, 32, 23, 1, 136, 4,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-70 */
{ NULL, 70, 800, 600, 21873, 120, 40, 21, 4, 80, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-72 */
{ NULL, 72, 800, 600, 20052, 64, 56, 23, 37, 120, 6,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-75 */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-85 */
{ NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-90 */
{ NULL, 90, 800, 600, 16648, 128, 40, 28, 1, 88, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-100 */
{ NULL, 100, 800, 600, 14667, 136, 48, 27, 1, 88, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 800x600-60 */
{ NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-60 */
{ NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-70 */
{ NULL, 70, 1024, 768, 13346, 144, 24, 29, 3, 136, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-72 */
{ NULL, 72, 1024, 768, 12702, 168, 56, 29, 4, 112, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-75 */
{ NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-85 */
{ NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-90 */
{ NULL, 90, 1024, 768, 9981, 176, 64, 37, 1, 112, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-100 */
{ NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1024x768-60 */
{ NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-60 */
{ NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-70 */
{ NULL, 70, 1152, 864, 10254, 192, 72, 32, 8, 120, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-72 */
{ NULL, 72, 1152, 864, 9866, 200, 72, 33, 7, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-75 */
{ NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-85 */
{ NULL, 85, 1152, 864, 8357, 200, 72, 37, 3, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-90 */
{ NULL, 90, 1152, 864, 7719, 208, 80, 42, 9, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-100 */
{ NULL, 100, 1152, 864, 6947, 208, 80, 48, 3, 128, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1152x864-60 */
{ NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-60 */
{ NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-70 */
{ NULL, 70, 1280, 1024, 7719, 224, 88, 38, 6, 136, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-72 */
{ NULL, 72, 1280, 1024, 7490, 224, 88, 39, 7, 136, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-75 */
{ NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-85 */
{ NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-90 */
{ NULL, 90, 1280, 1024, 5791, 240, 96, 51, 12, 144, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-100 */
{ NULL, 100, 1280, 1024, 5212, 240, 96, 57, 6, 144, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1280x1024-60 */
{ NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-60 */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-70 */
{ NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-72 */
{ NULL, 72, 1600, 1200, 5053, 288, 112, 47, 13, 176, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-75 */
{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-85 */
{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-90 */
{ NULL, 90, 1600, 1200, 3981, 304, 128, 60, 1, 176, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-100 */
{ NULL, 100, 1600, 1200, 3563, 304, 128, 67, 1, 176, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1600x1200-60 */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-60 */
{ NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-70 */
{ NULL, 70, 1920, 1440, 3593, 360, 152, 55, 8, 208, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-72 */
{ NULL, 72, 1920, 1440, 3472, 360, 152, 68, 4, 208, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-75 */
{ NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
0, FB_VMODE_NONINTERLACED, 0 },
/* 1920x1440-85 */
{ NULL, 85, 1920, 1440, 2929, 368, 152, 68, 1, 216, 3,
0, FB_VMODE_NONINTERLACED, 0 },
};
static struct fb_videomode olpc_dcon_modedb[] = {
/* The only mode the DCON has is 1200x900 */
{ NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, 0 }
};
static void get_modedb(struct fb_videomode **modedb, unsigned int *size)
{
if (olpc_has_dcon()) {
*modedb = (struct fb_videomode *) olpc_dcon_modedb;
*size = ARRAY_SIZE(olpc_dcon_modedb);
} else {
*modedb = (struct fb_videomode *) geode_modedb;
*size = ARRAY_SIZE(geode_modedb);
}
}
static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (!var->pixclock)
return -EINVAL;
if (var->xres > 1920 || var->yres > 1440)
return -EINVAL;
if (var->bits_per_pixel == 32) {
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else if (var->bits_per_pixel == 16) {
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
} else if (var->bits_per_pixel == 8) {
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else
return -EINVAL;
var->transp.offset = 0; var->transp.length = 0;
/* Enough video memory? */
if ((lx_get_pitch(var->xres, var->bits_per_pixel) * var->yres)
> info->fix.smem_len)
return -EINVAL;
return 0;
}
static int lxfb_set_par(struct fb_info *info)
{
if (info->var.bits_per_pixel > 8)
info->fix.visual = FB_VISUAL_TRUECOLOR;
else
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.line_length = lx_get_pitch(info->var.xres,
info->var.bits_per_pixel);
lx_set_mode(info);
return 0;
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int lxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *pal = info->pseudo_palette;
u32 v;
if (regno >= 16)
return -EINVAL;
v = chan_to_field(red, &info->var.red);
v |= chan_to_field(green, &info->var.green);
v |= chan_to_field(blue, &info->var.blue);
pal[regno] = v;
} else {
if (regno >= 256)
return -EINVAL;
lx_set_palette_reg(info, regno, red, green, blue);
}
return 0;
}
static int lxfb_blank(int blank_mode, struct fb_info *info)
{
return lx_blank_display(info, blank_mode);
}
static int lxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
{
struct lxfb_par *par = info->par;
int ret;
ret = pci_enable_device(dev);
if (ret)
return ret;
ret = pci_request_region(dev, 0, "lxfb-framebuffer");
if (ret)
return ret;
ret = pci_request_region(dev, 1, "lxfb-gp");
if (ret)
return ret;
ret = pci_request_region(dev, 2, "lxfb-vg");
if (ret)
return ret;
ret = pci_request_region(dev, 3, "lxfb-vp");
if (ret)
return ret;
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = vram ? vram : lx_framebuffer_size();
info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
ret = -ENOMEM;
if (info->screen_base == NULL)
return ret;
par->gp_regs = pci_ioremap_bar(dev, 1);
if (par->gp_regs == NULL)
return ret;
par->dc_regs = pci_ioremap_bar(dev, 2);
if (par->dc_regs == NULL)
return ret;
par->vp_regs = pci_ioremap_bar(dev, 3);
if (par->vp_regs == NULL)
return ret;
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_GLIU0_MEM_OFFSET, info->fix.smem_start & 0xFF000000);
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
dev_info(&dev->dev, "%d KB of video memory at 0x%lx\n",
info->fix.smem_len / 1024, info->fix.smem_start);
return 0;
}
static const struct fb_ops lxfb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = lxfb_check_var,
.fb_set_par = lxfb_set_par,
.fb_setcolreg = lxfb_setcolreg,
.fb_blank = lxfb_blank,
};
static struct fb_info *lxfb_init_fbinfo(struct device *dev)
{
struct lxfb_par *par;
struct fb_info *info;
/* Alloc enough space for the pseudo palette. */
info = framebuffer_alloc(sizeof(struct lxfb_par) + sizeof(u32) * 16,
dev);
if (!info)
return NULL;
par = info->par;
strcpy(info->fix.id, "Geode LX");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &lxfb_ops;
info->node = -1;
info->pseudo_palette = (void *)par + sizeof(struct lxfb_par);
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
framebuffer_release(info);
return NULL;
}
info->var.grayscale = 0;
return info;
}
static int __maybe_unused lxfb_suspend(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
console_lock();
lx_powerdown(info);
fb_set_suspend(info, 1);
console_unlock();
/* there's no point in setting PCI states; we emulate PCI, so
* we don't end up getting power savings anyways */
return 0;
}
static int __maybe_unused lxfb_resume(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
int ret;
console_lock();
ret = lx_powerup(info);
if (ret) {
printk(KERN_ERR "lxfb: power up failed!\n");
return ret;
}
fb_set_suspend(info, 0);
console_unlock();
return 0;
}
static int lxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct lxfb_par *par;
struct fb_info *info;
int ret;
struct fb_videomode *modedb_ptr;
unsigned int modedb_size;
ret = aperture_remove_conflicting_pci_devices(pdev, "lxfb");
if (ret)
return ret;
info = lxfb_init_fbinfo(&pdev->dev);
if (info == NULL)
return -ENOMEM;
par = info->par;
ret = lxfb_map_video_memory(info, pdev);
if (ret < 0) {
dev_err(&pdev->dev,
"failed to map frame buffer or controller registers\n");
goto err;
}
/* Set up the desired outputs */
par->output = 0;
par->output |= (nopanel) ? 0 : OUTPUT_PANEL;
par->output |= (nocrt) ? 0 : OUTPUT_CRT;
/* Set up the mode database */
get_modedb(&modedb_ptr, &modedb_size);
ret = fb_find_mode(&info->var, info, mode_option,
modedb_ptr, modedb_size, NULL, 16);
if (ret == 0 || ret == 4) {
dev_err(&pdev->dev, "could not find valid video mode\n");
ret = -EINVAL;
goto err;
}
/* Clear the screen of garbage, unless noclear was specified,
* in which case we assume the user knows what he is doing */
if (!noclear)
memset_io(info->screen_base, 0, info->fix.smem_len);
/* Set the mode */
lxfb_check_var(&info->var, info);
lxfb_set_par(info);
pm_set_vt_switch(vt_switch);
if (register_framebuffer(info) < 0) {
ret = -EINVAL;
goto err;
}
pci_set_drvdata(pdev, info);
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
err:
if (info->screen_base) {
iounmap(info->screen_base);
pci_release_region(pdev, 0);
}
if (par->gp_regs) {
iounmap(par->gp_regs);
pci_release_region(pdev, 1);
}
if (par->dc_regs) {
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
}
if (par->vp_regs) {
iounmap(par->vp_regs);
pci_release_region(pdev, 3);
}
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
return ret;
}
static void lxfb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct lxfb_par *par = info->par;
unregister_framebuffer(info);
iounmap(info->screen_base);
pci_release_region(pdev, 0);
iounmap(par->gp_regs);
pci_release_region(pdev, 1);
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
iounmap(par->vp_regs);
pci_release_region(pdev, 3);
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
static struct pci_device_id lxfb_id_table[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LX_VIDEO) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, lxfb_id_table);
static const struct dev_pm_ops lxfb_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = lxfb_suspend,
.resume = lxfb_resume,
.freeze = NULL,
.thaw = lxfb_resume,
.poweroff = NULL,
.restore = lxfb_resume,
#endif
};
static struct pci_driver lxfb_driver = {
.name = "lxfb",
.id_table = lxfb_id_table,
.probe = lxfb_probe,
.remove = lxfb_remove,
.driver.pm = &lxfb_pm_ops,
};
#ifndef MODULE
static int __init lxfb_setup(char *options)
{
char *opt;
if (!options || !*options)
return 0;
while ((opt = strsep(&options, ",")) != NULL) {
if (!*opt)
continue;
if (!strcmp(opt, "noclear"))
noclear = 1;
else if (!strcmp(opt, "nopanel"))
nopanel = 1;
else if (!strcmp(opt, "nocrt"))
nocrt = 1;
else
mode_option = opt;
}
return 0;
}
#endif
static int __init lxfb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("lxfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("lxfb", &option))
return -ENODEV;
lxfb_setup(option);
#endif
return pci_register_driver(&lxfb_driver);
}
static void __exit lxfb_cleanup(void)
{
pci_unregister_driver(&lxfb_driver);
}
module_init(lxfb_init);
module_exit(lxfb_cleanup);
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
module_param(vram, int, 0);
MODULE_PARM_DESC(vram, "video memory size");
module_param(vt_switch, int, 0);
MODULE_PARM_DESC(vt_switch, "enable VT switch during suspend/resume");
MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode LX");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/geode/lxfb_core.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/video/geode/video_cs5530.c
* -- CS5530 video device
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Based on AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/delay.h>
#include "geodefb.h"
#include "video_cs5530.h"
/*
* CS5530 PLL table. This maps pixclocks to the appropriate PLL register
* value.
*/
struct cs5530_pll_entry {
long pixclock; /* ps */
u32 pll_value;
};
static const struct cs5530_pll_entry cs5530_pll_table[] = {
{ 39721, 0x31C45801, }, /* 25.1750 MHz */
{ 35308, 0x20E36802, }, /* 28.3220 */
{ 31746, 0x33915801, }, /* 31.5000 */
{ 27777, 0x31EC4801, }, /* 36.0000 */
{ 26666, 0x21E22801, }, /* 37.5000 */
{ 25000, 0x33088801, }, /* 40.0000 */
{ 22271, 0x33E22801, }, /* 44.9000 */
{ 20202, 0x336C4801, }, /* 49.5000 */
{ 20000, 0x23088801, }, /* 50.0000 */
{ 19860, 0x23088801, }, /* 50.3500 */
{ 18518, 0x3708A801, }, /* 54.0000 */
{ 17777, 0x23E36802, }, /* 56.2500 */
{ 17733, 0x23E36802, }, /* 56.3916 */
{ 17653, 0x23E36802, }, /* 56.6444 */
{ 16949, 0x37C45801, }, /* 59.0000 */
{ 15873, 0x23EC4801, }, /* 63.0000 */
{ 15384, 0x37911801, }, /* 65.0000 */
{ 14814, 0x37963803, }, /* 67.5000 */
{ 14124, 0x37058803, }, /* 70.8000 */
{ 13888, 0x3710C805, }, /* 72.0000 */
{ 13333, 0x37E22801, }, /* 75.0000 */
{ 12698, 0x27915801, }, /* 78.7500 */
{ 12500, 0x37D8D802, }, /* 80.0000 */
{ 11135, 0x27588802, }, /* 89.8000 */
{ 10582, 0x27EC4802, }, /* 94.5000 */
{ 10101, 0x27AC6803, }, /* 99.0000 */
{ 10000, 0x27088801, }, /* 100.0000 */
{ 9259, 0x2710C805, }, /* 108.0000 */
{ 8888, 0x27E36802, }, /* 112.5000 */
{ 7692, 0x27C58803, }, /* 130.0000 */
{ 7407, 0x27316803, }, /* 135.0000 */
{ 6349, 0x2F915801, }, /* 157.5000 */
{ 6172, 0x2F08A801, }, /* 162.0000 */
{ 5714, 0x2FB11802, }, /* 175.0000 */
{ 5291, 0x2FEC4802, }, /* 189.0000 */
{ 4950, 0x2F963803, }, /* 202.0000 */
{ 4310, 0x2FB1B802, }, /* 232.0000 */
};
static void cs5530_set_dclk_frequency(struct fb_info *info)
{
struct geodefb_par *par = info->par;
int i;
u32 value;
long min, diff;
/* Search the table for the closest pixclock. */
value = cs5530_pll_table[0].pll_value;
min = cs5530_pll_table[0].pixclock - info->var.pixclock;
if (min < 0) min = -min;
for (i = 1; i < ARRAY_SIZE(cs5530_pll_table); i++) {
diff = cs5530_pll_table[i].pixclock - info->var.pixclock;
if (diff < 0L) diff = -diff;
if (diff < min) {
min = diff;
value = cs5530_pll_table[i].pll_value;
}
}
writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG);
writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */
udelay(500); /* wait for PLL to settle */
writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */
writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */
}
static void cs5530_configure_display(struct fb_info *info)
{
struct geodefb_par *par = info->par;
u32 dcfg;
dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
/* Clear bits from existing mode. */
dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK
| CS5530_DCFG_CRT_HSYNC_POL | CS5530_DCFG_CRT_VSYNC_POL
| CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN
| CS5530_DCFG_DAC_PWR_EN | CS5530_DCFG_VSYNC_EN
| CS5530_DCFG_HSYNC_EN);
/* Set default sync skew and power sequence delays. */
dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT
| CS5530_DCFG_GV_PAL_BYP);
/* Enable DACs, hsync and vsync for CRTs */
if (par->enable_crt) {
dcfg |= CS5530_DCFG_DAC_PWR_EN;
dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN;
}
/* Enable panel power and data if using a flat panel. */
if (par->panel_x > 0) {
dcfg |= CS5530_DCFG_FP_PWR_EN;
dcfg |= CS5530_DCFG_FP_DATA_EN;
}
/* Sync polarities. */
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
dcfg |= CS5530_DCFG_CRT_HSYNC_POL;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
dcfg |= CS5530_DCFG_CRT_VSYNC_POL;
writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
}
static int cs5530_blank_display(struct fb_info *info, int blank_mode)
{
struct geodefb_par *par = info->par;
u32 dcfg;
int blank, hsync, vsync;
switch (blank_mode) {
case FB_BLANK_UNBLANK:
blank = 0; hsync = 1; vsync = 1;
break;
case FB_BLANK_NORMAL:
blank = 1; hsync = 1; vsync = 1;
break;
case FB_BLANK_VSYNC_SUSPEND:
blank = 1; hsync = 1; vsync = 0;
break;
case FB_BLANK_HSYNC_SUSPEND:
blank = 1; hsync = 0; vsync = 1;
break;
case FB_BLANK_POWERDOWN:
blank = 1; hsync = 0; vsync = 0;
break;
default:
return -EINVAL;
}
dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
dcfg &= ~(CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN
| CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN
| CS5530_DCFG_FP_DATA_EN | CS5530_DCFG_FP_PWR_EN);
if (par->enable_crt) {
if (!blank)
dcfg |= CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN;
if (hsync)
dcfg |= CS5530_DCFG_HSYNC_EN;
if (vsync)
dcfg |= CS5530_DCFG_VSYNC_EN;
}
if (par->panel_x > 0) {
if (!blank)
dcfg |= CS5530_DCFG_FP_DATA_EN;
if (hsync && vsync)
dcfg |= CS5530_DCFG_FP_PWR_EN;
}
writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
return 0;
}
const struct geode_vid_ops cs5530_vid_ops = {
.set_dclk = cs5530_set_dclk_frequency,
.configure_display = cs5530_configure_display,
.blank_display = cs5530_blank_display,
};
| linux-master | drivers/video/fbdev/geode/video_cs5530.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/video/geode/display_gx1.c
* -- Geode GX1 display controller
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Based on AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*/
#include <linux/spinlock.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/div64.h>
#include <asm/delay.h>
#include "geodefb.h"
#include "display_gx1.h"
static DEFINE_SPINLOCK(gx1_conf_reg_lock);
static u8 gx1_read_conf_reg(u8 reg)
{
u8 val, ccr3;
unsigned long flags;
spin_lock_irqsave(&gx1_conf_reg_lock, flags);
outb(CONFIG_CCR3, 0x22);
ccr3 = inb(0x23);
outb(CONFIG_CCR3, 0x22);
outb(ccr3 | CONFIG_CCR3_MAPEN, 0x23);
outb(reg, 0x22);
val = inb(0x23);
outb(CONFIG_CCR3, 0x22);
outb(ccr3, 0x23);
spin_unlock_irqrestore(&gx1_conf_reg_lock, flags);
return val;
}
unsigned gx1_gx_base(void)
{
return (gx1_read_conf_reg(CONFIG_GCR) & 0x03) << 30;
}
int gx1_frame_buffer_size(void)
{
void __iomem *mc_regs;
u32 bank_cfg;
int d;
unsigned dram_size = 0, fb_base;
mc_regs = ioremap(gx1_gx_base() + 0x8400, 0x100);
if (!mc_regs)
return -ENOMEM;
/* Calculate the total size of both DIMM0 and DIMM1. */
bank_cfg = readl(mc_regs + MC_BANK_CFG);
for (d = 0; d < 2; d++) {
if ((bank_cfg & MC_BCFG_DIMM0_PG_SZ_MASK) != MC_BCFG_DIMM0_PG_SZ_NO_DIMM)
dram_size += 0x400000 << ((bank_cfg & MC_BCFG_DIMM0_SZ_MASK) >> 8);
bank_cfg >>= 16; /* look at DIMM1 next */
}
fb_base = (readl(mc_regs + MC_GBASE_ADD) & MC_GADD_GBADD_MASK) << 19;
iounmap(mc_regs);
return dram_size - fb_base;
}
static void gx1_set_mode(struct fb_info *info)
{
struct geodefb_par *par = info->par;
u32 gcfg, tcfg, ocfg, dclk_div, val;
int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
/* Unlock the display controller registers. */
readl(par->dc_regs + DC_UNLOCK);
writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
tcfg = readl(par->dc_regs + DC_TIMING_CFG);
/* Blank the display and disable the timing generator. */
tcfg &= ~(DC_TCFG_BLKE | DC_TCFG_TGEN);
writel(tcfg, par->dc_regs + DC_TIMING_CFG);
/* Wait for pending memory requests before disabling the FIFO load. */
udelay(100);
/* Disable FIFO load and compression. */
gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
/* Setup DCLK and its divisor. */
gcfg &= ~DC_GCFG_DCLK_MASK;
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
par->vid_ops->set_dclk(info);
dclk_div = DC_GCFG_DCLK_DIV_1; /* FIXME: may need to divide DCLK by 2 sometimes? */
gcfg |= dclk_div;
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
/* Wait for the clock generatation to settle. This is needed since
* some of the register writes that follow require that clock to be
* present. */
udelay(1000); /* FIXME: seems a little long */
/*
* Setup new mode.
*/
/* Clear all unused feature bits. */
gcfg = DC_GCFG_VRDY | dclk_div;
/* Set FIFO priority (default 6/5) and enable. */
/* FIXME: increase fifo priority for 1280x1024 modes? */
gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
/* FIXME: Set pixel and line double bits if necessary. */
/* Framebuffer start offset. */
writel(0, par->dc_regs + DC_FB_ST_OFFSET);
/* Line delta and line buffer length. */
writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA);
writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
par->dc_regs + DC_BUF_SIZE);
/* Output configuration. Enable panel data, set pixel format. */
ocfg = DC_OCFG_PCKE | DC_OCFG_PDEL | DC_OCFG_PDEH;
if (info->var.bits_per_pixel == 8) ocfg |= DC_OCFG_8BPP;
/* Enable timing generator, sync and FP data. */
tcfg = DC_TCFG_FPPE | DC_TCFG_HSYE | DC_TCFG_VSYE | DC_TCFG_BLKE
| DC_TCFG_TGEN;
/* Horizontal and vertical timings. */
hactive = info->var.xres;
hblankstart = hactive;
hsyncstart = hblankstart + info->var.right_margin;
hsyncend = hsyncstart + info->var.hsync_len;
hblankend = hsyncend + info->var.left_margin;
htotal = hblankend;
vactive = info->var.yres;
vblankstart = vactive;
vsyncstart = vblankstart + info->var.lower_margin;
vsyncend = vsyncstart + info->var.vsync_len;
vblankend = vsyncend + info->var.upper_margin;
vtotal = vblankend;
val = (hactive - 1) | ((htotal - 1) << 16);
writel(val, par->dc_regs + DC_H_TIMING_1);
val = (hblankstart - 1) | ((hblankend - 1) << 16);
writel(val, par->dc_regs + DC_H_TIMING_2);
val = (hsyncstart - 1) | ((hsyncend - 1) << 16);
writel(val, par->dc_regs + DC_H_TIMING_3);
writel(val, par->dc_regs + DC_FP_H_TIMING);
val = (vactive - 1) | ((vtotal - 1) << 16);
writel(val, par->dc_regs + DC_V_TIMING_1);
val = (vblankstart - 1) | ((vblankend - 1) << 16);
writel(val, par->dc_regs + DC_V_TIMING_2);
val = (vsyncstart - 1) | ((vsyncend - 1) << 16);
writel(val, par->dc_regs + DC_V_TIMING_3);
val = (vsyncstart - 2) | ((vsyncend - 2) << 16);
writel(val, par->dc_regs + DC_FP_V_TIMING);
/* Write final register values. */
writel(ocfg, par->dc_regs + DC_OUTPUT_CFG);
writel(tcfg, par->dc_regs + DC_TIMING_CFG);
udelay(1000); /* delay after TIMING_CFG. FIXME: perhaps a little long */
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
par->vid_ops->configure_display(info);
/* Relock display controller registers */
writel(0, par->dc_regs + DC_UNLOCK);
/* FIXME: write line_length and bpp to Graphics Pipeline GP_BLT_STATUS
* register. */
}
static void gx1_set_hw_palette_reg(struct fb_info *info, unsigned regno,
unsigned red, unsigned green, unsigned blue)
{
struct geodefb_par *par = info->par;
int val;
/* Hardware palette is in RGB 6-6-6 format. */
val = (red << 2) & 0x3f000;
val |= (green >> 4) & 0x00fc0;
val |= (blue >> 10) & 0x0003f;
writel(regno, par->dc_regs + DC_PAL_ADDRESS);
writel(val, par->dc_regs + DC_PAL_DATA);
}
const struct geode_dc_ops gx1_dc_ops = {
.set_mode = gx1_set_mode,
.set_palette_reg = gx1_set_hw_palette_reg,
};
| linux-master | drivers/video/fbdev/geode/display_gx1.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Geode GX video processor device.
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* Portions from AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/msr.h>
#include <linux/cs5535.h>
#include "gxfb.h"
/*
* Tables of register settings for various DOTCLKs.
*/
struct gx_pll_entry {
long pixclock; /* ps */
u32 sys_rstpll_bits;
u32 dotpll_value;
};
#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
static const struct gx_pll_entry gx_pll_table_48MHz[] = {
{ 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
{ 39721, 0, 0x00000037 }, /* 25.1750 */
{ 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
{ 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
{ 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
{ 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
{ 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
{ 22271, 0, 0x00000063 }, /* 44.9000 */
{ 20202, 0, 0x0000054B }, /* 49.5000 */
{ 20000, 0, 0x0000026E }, /* 50.0000 */
{ 19860, PREMULT2, 0x00000037 }, /* 50.3500 */
{ 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */
{ 17777, 0, 0x00000577 }, /* 56.2500 */
{ 17733, 0, 0x000007F7 }, /* 56.3916 */
{ 17653, 0, 0x0000057B }, /* 56.6444 */
{ 16949, PREMULT2, 0x00000707 }, /* 59.0000 */
{ 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */
{ 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */
{ 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */
{ 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */
{ 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
{ 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
{ 13333, 0, 0x00000052 }, /* 75.0000 */
{ 12698, 0, 0x00000056 }, /* 78.7500 */
{ 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
{ 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
{ 10582, 0, 0x000002D2 }, /* 94.5000 */
{ 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */
{ 10000, PREMULT2, 0x00000036 }, /* 100.0000 */
{ 9259, 0, 0x000007E2 }, /* 108.0000 */
{ 8888, 0, 0x000007F6 }, /* 112.5000 */
{ 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */
{ 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */
{ 6349, 0, 0x00000055 }, /* 157.5000 */
{ 6172, 0, 0x000009C1 }, /* 162.0000 */
{ 5787, PREMULT2, 0x0000002D }, /* 172.798 */
{ 5698, 0, 0x000002C1 }, /* 175.5000 */
{ 5291, 0, 0x000002D1 }, /* 189.0000 */
{ 4938, 0, 0x00000551 }, /* 202.5000 */
{ 4357, 0, 0x0000057D }, /* 229.5000 */
};
static const struct gx_pll_entry gx_pll_table_14MHz[] = {
{ 39721, 0, 0x00000037 }, /* 25.1750 */
{ 35308, 0, 0x00000B7B }, /* 28.3220 */
{ 31746, 0, 0x000004D3 }, /* 31.5000 */
{ 27777, 0, 0x00000BE3 }, /* 36.0000 */
{ 26666, 0, 0x0000074F }, /* 37.5000 */
{ 25000, 0, 0x0000050B }, /* 40.0000 */
{ 22271, 0, 0x00000063 }, /* 44.9000 */
{ 20202, 0, 0x0000054B }, /* 49.5000 */
{ 20000, 0, 0x0000026E }, /* 50.0000 */
{ 19860, 0, 0x000007C3 }, /* 50.3500 */
{ 18518, 0, 0x000007E3 }, /* 54.0000 */
{ 17777, 0, 0x00000577 }, /* 56.2500 */
{ 17733, 0, 0x000002FB }, /* 56.3916 */
{ 17653, 0, 0x0000057B }, /* 56.6444 */
{ 16949, 0, 0x0000058B }, /* 59.0000 */
{ 15873, 0, 0x0000095E }, /* 63.0000 */
{ 15384, 0, 0x0000096A }, /* 65.0000 */
{ 14814, 0, 0x00000BC2 }, /* 67.5000 */
{ 14124, 0, 0x0000098A }, /* 70.8000 */
{ 13888, 0, 0x00000BE2 }, /* 72.0000 */
{ 13333, 0, 0x00000052 }, /* 75.0000 */
{ 12698, 0, 0x00000056 }, /* 78.7500 */
{ 12500, 0, 0x0000050A }, /* 80.0000 */
{ 11135, 0, 0x0000078E }, /* 89.8000 */
{ 10582, 0, 0x000002D2 }, /* 94.5000 */
{ 10101, 0, 0x000011F6 }, /* 99.0000 */
{ 10000, 0, 0x0000054E }, /* 100.0000 */
{ 9259, 0, 0x000007E2 }, /* 108.0000 */
{ 8888, 0, 0x000002FA }, /* 112.5000 */
{ 7692, 0, 0x00000BB1 }, /* 130.0000 */
{ 7407, 0, 0x00000975 }, /* 135.0000 */
{ 6349, 0, 0x00000055 }, /* 157.5000 */
{ 6172, 0, 0x000009C1 }, /* 162.0000 */
{ 5698, 0, 0x000002C1 }, /* 175.5000 */
{ 5291, 0, 0x00000539 }, /* 189.0000 */
{ 4938, 0, 0x00000551 }, /* 202.5000 */
{ 4357, 0, 0x0000057D }, /* 229.5000 */
};
void gx_set_dclk_frequency(struct fb_info *info)
{
const struct gx_pll_entry *pll_table;
int pll_table_len;
int i, best_i;
long min, diff;
u64 dotpll, sys_rstpll;
int timeout = 1000;
/* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
if (cpu_data(0).x86_stepping == 1) {
pll_table = gx_pll_table_14MHz;
pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
} else {
pll_table = gx_pll_table_48MHz;
pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
}
/* Search the table for the closest pixclock. */
best_i = 0;
min = abs(pll_table[0].pixclock - info->var.pixclock);
for (i = 1; i < pll_table_len; i++) {
diff = abs(pll_table[i].pixclock - info->var.pixclock);
if (diff < min) {
min = diff;
best_i = i;
}
}
rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
rdmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Program new M, N and P. */
dotpll &= 0x00000000ffffffffull;
dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
wrmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Program dividers. */
sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
| MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
| MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
/* Clear reset bit to start PLL. */
dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
wrmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Wait for LOCK bit. */
do {
rdmsrl(MSR_GLCP_DOTPLL, dotpll);
} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
}
static void
gx_configure_tft(struct fb_info *info)
{
struct gxfb_par *par = info->par;
unsigned long val;
unsigned long fp;
/* Set up the DF pad select MSR */
rdmsrl(MSR_GX_MSR_PADSEL, val);
val &= ~MSR_GX_MSR_PADSEL_MASK;
val |= MSR_GX_MSR_PADSEL_TFT;
wrmsrl(MSR_GX_MSR_PADSEL, val);
/* Turn off the panel */
fp = read_fp(par, FP_PM);
fp &= ~FP_PM_P;
write_fp(par, FP_PM, fp);
/* Set timing 1 */
fp = read_fp(par, FP_PT1);
fp &= FP_PT1_VSIZE_MASK;
fp |= info->var.yres << FP_PT1_VSIZE_SHIFT;
write_fp(par, FP_PT1, fp);
/* Timing 2 */
/* Set bits that are always on for TFT */
fp = 0x0F100000;
/* Configure sync polarity */
if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
fp |= FP_PT2_VSP;
if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
fp |= FP_PT2_HSP;
write_fp(par, FP_PT2, fp);
/* Set the dither control */
write_fp(par, FP_DFC, FP_DFC_NFI);
/* Enable the FP data and power (in case the BIOS didn't) */
fp = read_vp(par, VP_DCFG);
fp |= VP_DCFG_FP_PWR_EN | VP_DCFG_FP_DATA_EN;
write_vp(par, VP_DCFG, fp);
/* Unblank the panel */
fp = read_fp(par, FP_PM);
fp |= FP_PM_P;
write_fp(par, FP_PM, fp);
}
void gx_configure_display(struct fb_info *info)
{
struct gxfb_par *par = info->par;
u32 dcfg, misc;
/* Write the display configuration */
dcfg = read_vp(par, VP_DCFG);
/* Disable hsync and vsync */
dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
write_vp(par, VP_DCFG, dcfg);
/* Clear bits from existing mode. */
dcfg &= ~(VP_DCFG_CRT_SYNC_SKW
| VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL
| VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN);
/* Set default sync skew. */
dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT;
/* Enable hsync and vsync. */
dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN;
misc = read_vp(par, VP_MISC);
/* Disable gamma correction */
misc |= VP_MISC_GAM_EN;
if (par->enable_crt) {
/* Power up the CRT DACs */
misc &= ~(VP_MISC_APWRDN | VP_MISC_DACPWRDN);
write_vp(par, VP_MISC, misc);
/* Only change the sync polarities if we are running
* in CRT mode. The FP polarities will be handled in
* gxfb_configure_tft */
if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
dcfg |= VP_DCFG_CRT_HSYNC_POL;
if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
dcfg |= VP_DCFG_CRT_VSYNC_POL;
} else {
/* Power down the CRT DACs if in FP mode */
misc |= (VP_MISC_APWRDN | VP_MISC_DACPWRDN);
write_vp(par, VP_MISC, misc);
}
/* Enable the display logic */
/* Set up the DACS to blank normally */
dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN;
/* Enable the external DAC VREF? */
write_vp(par, VP_DCFG, dcfg);
/* Set up the flat panel (if it is enabled) */
if (par->enable_crt == 0)
gx_configure_tft(info);
}
int gx_blank_display(struct fb_info *info, int blank_mode)
{
struct gxfb_par *par = info->par;
u32 dcfg, fp_pm;
int blank, hsync, vsync, crt;
/* CRT power saving modes. */
switch (blank_mode) {
case FB_BLANK_UNBLANK:
blank = 0; hsync = 1; vsync = 1; crt = 1;
break;
case FB_BLANK_NORMAL:
blank = 1; hsync = 1; vsync = 1; crt = 1;
break;
case FB_BLANK_VSYNC_SUSPEND:
blank = 1; hsync = 1; vsync = 0; crt = 1;
break;
case FB_BLANK_HSYNC_SUSPEND:
blank = 1; hsync = 0; vsync = 1; crt = 1;
break;
case FB_BLANK_POWERDOWN:
blank = 1; hsync = 0; vsync = 0; crt = 0;
break;
default:
return -EINVAL;
}
dcfg = read_vp(par, VP_DCFG);
dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN |
VP_DCFG_CRT_EN);
if (!blank)
dcfg |= VP_DCFG_DAC_BL_EN;
if (hsync)
dcfg |= VP_DCFG_HSYNC_EN;
if (vsync)
dcfg |= VP_DCFG_VSYNC_EN;
if (crt)
dcfg |= VP_DCFG_CRT_EN;
write_vp(par, VP_DCFG, dcfg);
/* Power on/off flat panel. */
if (par->enable_crt == 0) {
fp_pm = read_fp(par, FP_PM);
if (blank_mode == FB_BLANK_POWERDOWN)
fp_pm &= ~FP_PM_P;
else
fp_pm |= FP_PM_P;
write_fp(par, FP_PM, fp_pm);
}
return 0;
}
| linux-master | drivers/video/fbdev/geode/video_gx.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2008 Andres Salomon <[email protected]>
*/
#include <linux/fb.h>
#include <asm/io.h>
#include <asm/msr.h>
#include <linux/cs5535.h>
#include <asm/delay.h>
#include "gxfb.h"
static void gx_save_regs(struct gxfb_par *par)
{
int i;
/* wait for the BLT engine to stop being busy */
do {
i = read_gp(par, GP_BLT_STATUS);
} while (i & (GP_BLT_STATUS_BLT_PENDING | GP_BLT_STATUS_BLT_BUSY));
/* save MSRs */
rdmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel);
rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll);
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
/* save registers */
memcpy(par->gp, par->gp_regs, sizeof(par->gp));
memcpy(par->dc, par->dc_regs, sizeof(par->dc));
memcpy(par->vp, par->vid_regs, sizeof(par->vp));
memcpy(par->fp, par->vid_regs + VP_FP_START, sizeof(par->fp));
/* save the palette */
write_dc(par, DC_PAL_ADDRESS, 0);
for (i = 0; i < ARRAY_SIZE(par->pal); i++)
par->pal[i] = read_dc(par, DC_PAL_DATA);
}
static void gx_set_dotpll(uint32_t dotpll_hi)
{
uint32_t dotpll_lo;
int i;
rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo);
dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET;
dotpll_lo &= ~MSR_GLCP_DOTPLL_BYPASS;
wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
/* wait for the PLL to lock */
for (i = 0; i < 200; i++) {
rdmsrl(MSR_GLCP_DOTPLL, dotpll_lo);
if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK)
break;
udelay(1);
}
/* PLL set, unlock */
dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET;
wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
}
static void gx_restore_gfx_proc(struct gxfb_par *par)
{
int i;
for (i = 0; i < ARRAY_SIZE(par->gp); i++) {
switch (i) {
case GP_VECTOR_MODE:
case GP_BLT_MODE:
case GP_BLT_STATUS:
case GP_HST_SRC:
/* don't restore these registers */
break;
default:
write_gp(par, i, par->gp[i]);
}
}
}
static void gx_restore_display_ctlr(struct gxfb_par *par)
{
int i;
for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
switch (i) {
case DC_UNLOCK:
/* unlock the DC; runs first */
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
break;
case DC_GENERAL_CFG:
/* write without the enables */
write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE |
DC_GENERAL_CFG_ICNE |
DC_GENERAL_CFG_CURE |
DC_GENERAL_CFG_DFLE));
break;
case DC_DISPLAY_CFG:
/* write without the enables */
write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN |
DC_DISPLAY_CFG_GDEN |
DC_DISPLAY_CFG_TGEN));
break;
case DC_RSVD_0:
case DC_RSVD_1:
case DC_RSVD_2:
case DC_RSVD_3:
case DC_RSVD_4:
case DC_LINE_CNT:
case DC_PAL_ADDRESS:
case DC_PAL_DATA:
case DC_DFIFO_DIAG:
case DC_CFIFO_DIAG:
case DC_RSVD_5:
/* don't restore these registers */
break;
default:
write_dc(par, i, par->dc[i]);
}
}
/* restore the palette */
write_dc(par, DC_PAL_ADDRESS, 0);
for (i = 0; i < ARRAY_SIZE(par->pal); i++)
write_dc(par, DC_PAL_DATA, par->pal[i]);
}
static void gx_restore_video_proc(struct gxfb_par *par)
{
int i;
wrmsrl(MSR_GX_MSR_PADSEL, par->msr.padsel);
for (i = 0; i < ARRAY_SIZE(par->vp); i++) {
switch (i) {
case VP_VCFG:
/* don't enable video yet */
write_vp(par, i, par->vp[i] & ~VP_VCFG_VID_EN);
break;
case VP_DCFG:
/* don't enable CRT yet */
write_vp(par, i, par->vp[i] &
~(VP_DCFG_DAC_BL_EN | VP_DCFG_VSYNC_EN |
VP_DCFG_HSYNC_EN | VP_DCFG_CRT_EN));
break;
case VP_GAR:
case VP_GDR:
case VP_RSVD_0:
case VP_RSVD_1:
case VP_RSVD_2:
case VP_RSVD_3:
case VP_CRC32:
case VP_AWT:
case VP_VTM:
/* don't restore these registers */
break;
default:
write_vp(par, i, par->vp[i]);
}
}
}
static void gx_restore_regs(struct gxfb_par *par)
{
int i;
gx_set_dotpll((uint32_t) (par->msr.dotpll >> 32));
gx_restore_gfx_proc(par);
gx_restore_display_ctlr(par);
gx_restore_video_proc(par);
/* Flat Panel */
for (i = 0; i < ARRAY_SIZE(par->fp); i++) {
if (i != FP_PM && i != FP_RSVD_0)
write_fp(par, i, par->fp[i]);
}
}
static void gx_disable_graphics(struct gxfb_par *par)
{
/* shut down the engine */
write_vp(par, VP_VCFG, par->vp[VP_VCFG] & ~VP_VCFG_VID_EN);
write_vp(par, VP_DCFG, par->vp[VP_DCFG] & ~(VP_DCFG_DAC_BL_EN |
VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN | VP_DCFG_CRT_EN));
/* turn off the flat panel */
write_fp(par, FP_PM, par->fp[FP_PM] & ~FP_PM_P);
/* turn off display */
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] &
~(DC_GENERAL_CFG_VIDE | DC_GENERAL_CFG_ICNE |
DC_GENERAL_CFG_CURE | DC_GENERAL_CFG_DFLE));
write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] &
~(DC_DISPLAY_CFG_VDEN | DC_DISPLAY_CFG_GDEN |
DC_DISPLAY_CFG_TGEN));
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
}
static void gx_enable_graphics(struct gxfb_par *par)
{
uint32_t fp;
fp = read_fp(par, FP_PM);
if (par->fp[FP_PM] & FP_PM_P) {
/* power on the panel if not already power{ed,ing} on */
if (!(fp & (FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP)))
write_fp(par, FP_PM, par->fp[FP_PM]);
} else {
/* power down the panel if not already power{ed,ing} down */
if (!(fp & (FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN)))
write_fp(par, FP_PM, par->fp[FP_PM]);
}
/* turn everything on */
write_vp(par, VP_VCFG, par->vp[VP_VCFG]);
write_vp(par, VP_DCFG, par->vp[VP_DCFG]);
write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
/* do this last; it will enable the FIFO load */
write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]);
/* lock the door behind us */
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
}
int gx_powerdown(struct fb_info *info)
{
struct gxfb_par *par = info->par;
if (par->powered_down)
return 0;
gx_save_regs(par);
gx_disable_graphics(par);
par->powered_down = 1;
return 0;
}
int gx_powerup(struct fb_info *info)
{
struct gxfb_par *par = info->par;
if (!par->powered_down)
return 0;
gx_restore_regs(par);
gx_enable_graphics(par);
par->powered_down = 0;
return 0;
}
| linux-master | drivers/video/fbdev/geode/suspend_gx.c |
/*
* linux/drivers/video/console/fbcon_ud.c -- Software Rotation - 180 degrees
*
* Copyright (C) 2005 Antonino Daplas <adaplas @pol.net>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/vt_kern.h>
#include <linux/console.h>
#include <asm/types.h>
#include "fbcon.h"
#include "fbcon_rotate.h"
/*
* Rotation 180 degrees
*/
static void ud_update_attr(u8 *dst, u8 *src, int attribute,
struct vc_data *vc)
{
int i, offset = (vc->vc_font.height < 10) ? 1 : 2;
int width = (vc->vc_font.width + 7) >> 3;
unsigned int cellsize = vc->vc_font.height * width;
u8 c;
offset = offset * width;
for (i = 0; i < cellsize; i++) {
c = src[i];
if (attribute & FBCON_ATTRIBUTE_UNDERLINE && i < offset)
c = 0xff;
if (attribute & FBCON_ATTRIBUTE_BOLD)
c |= c << 1;
if (attribute & FBCON_ATTRIBUTE_REVERSE)
c = ~c;
dst[i] = c;
}
}
static void ud_bmove(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int dy, int dx, int height, int width)
{
struct fbcon_ops *ops = info->fbcon_par;
struct fb_copyarea area;
u32 vyres = GETVYRES(ops->p, info);
u32 vxres = GETVXRES(ops->p, info);
area.sy = vyres - ((sy + height) * vc->vc_font.height);
area.sx = vxres - ((sx + width) * vc->vc_font.width);
area.dy = vyres - ((dy + height) * vc->vc_font.height);
area.dx = vxres - ((dx + width) * vc->vc_font.width);
area.height = height * vc->vc_font.height;
area.width = width * vc->vc_font.width;
info->fbops->fb_copyarea(info, &area);
}
static void ud_clear(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int height, int width)
{
struct fbcon_ops *ops = info->fbcon_par;
struct fb_fillrect region;
int bgshift = (vc->vc_hi_font_mask) ? 13 : 12;
u32 vyres = GETVYRES(ops->p, info);
u32 vxres = GETVXRES(ops->p, info);
region.color = attr_bgcol_ec(bgshift,vc,info);
region.dy = vyres - ((sy + height) * vc->vc_font.height);
region.dx = vxres - ((sx + width) * vc->vc_font.width);
region.width = width * vc->vc_font.width;
region.height = height * vc->vc_font.height;
region.rop = ROP_COPY;
info->fbops->fb_fillrect(info, ®ion);
}
static inline void ud_putcs_aligned(struct vc_data *vc, struct fb_info *info,
const u16 *s, u32 attr, u32 cnt,
u32 d_pitch, u32 s_pitch, u32 cellsize,
struct fb_image *image, u8 *buf, u8 *dst)
{
struct fbcon_ops *ops = info->fbcon_par;
u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
u32 idx = vc->vc_font.width >> 3;
u8 *src;
while (cnt--) {
src = ops->fontbuffer + (scr_readw(s--) & charmask)*cellsize;
if (attr) {
ud_update_attr(buf, src, attr, vc);
src = buf;
}
if (likely(idx == 1))
__fb_pad_aligned_buffer(dst, d_pitch, src, idx,
image->height);
else
fb_pad_aligned_buffer(dst, d_pitch, src, idx,
image->height);
dst += s_pitch;
}
info->fbops->fb_imageblit(info, image);
}
static inline void ud_putcs_unaligned(struct vc_data *vc,
struct fb_info *info, const u16 *s,
u32 attr, u32 cnt, u32 d_pitch,
u32 s_pitch, u32 cellsize,
struct fb_image *image, u8 *buf,
u8 *dst)
{
struct fbcon_ops *ops = info->fbcon_par;
u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
u32 shift_low = 0, mod = vc->vc_font.width % 8;
u32 shift_high = 8;
u32 idx = vc->vc_font.width >> 3;
u8 *src;
while (cnt--) {
src = ops->fontbuffer + (scr_readw(s--) & charmask)*cellsize;
if (attr) {
ud_update_attr(buf, src, attr, vc);
src = buf;
}
fb_pad_unaligned_buffer(dst, d_pitch, src, idx,
image->height, shift_high,
shift_low, mod);
shift_low += mod;
dst += (shift_low >= 8) ? s_pitch : s_pitch - 1;
shift_low &= 7;
shift_high = 8 - shift_low;
}
info->fbops->fb_imageblit(info, image);
}
static void ud_putcs(struct vc_data *vc, struct fb_info *info,
const unsigned short *s, int count, int yy, int xx,
int fg, int bg)
{
struct fb_image image;
struct fbcon_ops *ops = info->fbcon_par;
u32 width = (vc->vc_font.width + 7)/8;
u32 cellsize = width * vc->vc_font.height;
u32 maxcnt = info->pixmap.size/cellsize;
u32 scan_align = info->pixmap.scan_align - 1;
u32 buf_align = info->pixmap.buf_align - 1;
u32 mod = vc->vc_font.width % 8, cnt, pitch, size;
u32 attribute = get_attribute(info, scr_readw(s));
u8 *dst, *buf = NULL;
u32 vyres = GETVYRES(ops->p, info);
u32 vxres = GETVXRES(ops->p, info);
if (!ops->fontbuffer)
return;
image.fg_color = fg;
image.bg_color = bg;
image.dy = vyres - ((yy * vc->vc_font.height) + vc->vc_font.height);
image.dx = vxres - ((xx + count) * vc->vc_font.width);
image.height = vc->vc_font.height;
image.depth = 1;
if (attribute) {
buf = kmalloc(cellsize, GFP_KERNEL);
if (!buf)
return;
}
s += count - 1;
while (count) {
if (count > maxcnt)
cnt = maxcnt;
else
cnt = count;
image.width = vc->vc_font.width * cnt;
pitch = ((image.width + 7) >> 3) + scan_align;
pitch &= ~scan_align;
size = pitch * image.height + buf_align;
size &= ~buf_align;
dst = fb_get_buffer_offset(info, &info->pixmap, size);
image.data = dst;
if (!mod)
ud_putcs_aligned(vc, info, s, attribute, cnt, pitch,
width, cellsize, &image, buf, dst);
else
ud_putcs_unaligned(vc, info, s, attribute, cnt, pitch,
width, cellsize, &image,
buf, dst);
image.dx += image.width;
count -= cnt;
s -= cnt;
xx += cnt;
}
/* buf is always NULL except when in monochrome mode, so in this case
it's a gain to check buf against NULL even though kfree() handles
NULL pointers just fine */
if (unlikely(buf))
kfree(buf);
}
static void ud_clear_margins(struct vc_data *vc, struct fb_info *info,
int color, int bottom_only)
{
unsigned int cw = vc->vc_font.width;
unsigned int ch = vc->vc_font.height;
unsigned int rw = info->var.xres - (vc->vc_cols*cw);
unsigned int bh = info->var.yres - (vc->vc_rows*ch);
struct fb_fillrect region;
region.color = color;
region.rop = ROP_COPY;
if ((int) rw > 0 && !bottom_only) {
region.dy = 0;
region.dx = info->var.xoffset;
region.width = rw;
region.height = info->var.yres_virtual;
info->fbops->fb_fillrect(info, ®ion);
}
if ((int) bh > 0) {
region.dy = info->var.yoffset;
region.dx = info->var.xoffset;
region.height = bh;
region.width = info->var.xres;
info->fbops->fb_fillrect(info, ®ion);
}
}
static void ud_cursor(struct vc_data *vc, struct fb_info *info, int mode,
int fg, int bg)
{
struct fb_cursor cursor;
struct fbcon_ops *ops = info->fbcon_par;
unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
int w = (vc->vc_font.width + 7) >> 3, c;
int y = real_y(ops->p, vc->state.y);
int attribute, use_sw = vc->vc_cursor_type & CUR_SW;
int err = 1, dx, dy;
char *src;
u32 vyres = GETVYRES(ops->p, info);
u32 vxres = GETVXRES(ops->p, info);
if (!ops->fontbuffer)
return;
cursor.set = 0;
c = scr_readw((u16 *) vc->vc_pos);
attribute = get_attribute(info, c);
src = ops->fontbuffer + ((c & charmask) * (w * vc->vc_font.height));
if (ops->cursor_state.image.data != src ||
ops->cursor_reset) {
ops->cursor_state.image.data = src;
cursor.set |= FB_CUR_SETIMAGE;
}
if (attribute) {
u8 *dst;
dst = kmalloc_array(w, vc->vc_font.height, GFP_ATOMIC);
if (!dst)
return;
kfree(ops->cursor_data);
ops->cursor_data = dst;
ud_update_attr(dst, src, attribute, vc);
src = dst;
}
if (ops->cursor_state.image.fg_color != fg ||
ops->cursor_state.image.bg_color != bg ||
ops->cursor_reset) {
ops->cursor_state.image.fg_color = fg;
ops->cursor_state.image.bg_color = bg;
cursor.set |= FB_CUR_SETCMAP;
}
if (ops->cursor_state.image.height != vc->vc_font.height ||
ops->cursor_state.image.width != vc->vc_font.width ||
ops->cursor_reset) {
ops->cursor_state.image.height = vc->vc_font.height;
ops->cursor_state.image.width = vc->vc_font.width;
cursor.set |= FB_CUR_SETSIZE;
}
dy = vyres - ((y * vc->vc_font.height) + vc->vc_font.height);
dx = vxres - ((vc->state.x * vc->vc_font.width) + vc->vc_font.width);
if (ops->cursor_state.image.dx != dx ||
ops->cursor_state.image.dy != dy ||
ops->cursor_reset) {
ops->cursor_state.image.dx = dx;
ops->cursor_state.image.dy = dy;
cursor.set |= FB_CUR_SETPOS;
}
if (ops->cursor_state.hot.x || ops->cursor_state.hot.y ||
ops->cursor_reset) {
ops->cursor_state.hot.x = cursor.hot.y = 0;
cursor.set |= FB_CUR_SETHOT;
}
if (cursor.set & FB_CUR_SETSIZE ||
vc->vc_cursor_type != ops->p->cursor_shape ||
ops->cursor_state.mask == NULL ||
ops->cursor_reset) {
char *mask = kmalloc_array(w, vc->vc_font.height, GFP_ATOMIC);
int cur_height, size, i = 0;
u8 msk = 0xff;
if (!mask)
return;
kfree(ops->cursor_state.mask);
ops->cursor_state.mask = mask;
ops->p->cursor_shape = vc->vc_cursor_type;
cursor.set |= FB_CUR_SETSHAPE;
switch (CUR_SIZE(ops->p->cursor_shape)) {
case CUR_NONE:
cur_height = 0;
break;
case CUR_UNDERLINE:
cur_height = (vc->vc_font.height < 10) ? 1 : 2;
break;
case CUR_LOWER_THIRD:
cur_height = vc->vc_font.height/3;
break;
case CUR_LOWER_HALF:
cur_height = vc->vc_font.height >> 1;
break;
case CUR_TWO_THIRDS:
cur_height = (vc->vc_font.height << 1)/3;
break;
case CUR_BLOCK:
default:
cur_height = vc->vc_font.height;
break;
}
size = cur_height * w;
while (size--)
mask[i++] = msk;
size = (vc->vc_font.height - cur_height) * w;
while (size--)
mask[i++] = ~msk;
}
switch (mode) {
case CM_ERASE:
ops->cursor_state.enable = 0;
break;
case CM_DRAW:
case CM_MOVE:
default:
ops->cursor_state.enable = (use_sw) ? 0 : 1;
break;
}
cursor.image.data = src;
cursor.image.fg_color = ops->cursor_state.image.fg_color;
cursor.image.bg_color = ops->cursor_state.image.bg_color;
cursor.image.dx = ops->cursor_state.image.dx;
cursor.image.dy = ops->cursor_state.image.dy;
cursor.image.height = ops->cursor_state.image.height;
cursor.image.width = ops->cursor_state.image.width;
cursor.hot.x = ops->cursor_state.hot.x;
cursor.hot.y = ops->cursor_state.hot.y;
cursor.mask = ops->cursor_state.mask;
cursor.enable = ops->cursor_state.enable;
cursor.image.depth = 1;
cursor.rop = ROP_XOR;
if (info->fbops->fb_cursor)
err = info->fbops->fb_cursor(info, &cursor);
if (err)
soft_cursor(info, &cursor);
ops->cursor_reset = 0;
}
static int ud_update_start(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
int xoffset, yoffset;
u32 vyres = GETVYRES(ops->p, info);
u32 vxres = GETVXRES(ops->p, info);
int err;
xoffset = vxres - info->var.xres - ops->var.xoffset;
yoffset = vyres - info->var.yres - ops->var.yoffset;
if (yoffset < 0)
yoffset += vyres;
ops->var.xoffset = xoffset;
ops->var.yoffset = yoffset;
err = fb_pan_display(info, &ops->var);
ops->var.xoffset = info->var.xoffset;
ops->var.yoffset = info->var.yoffset;
ops->var.vmode = info->var.vmode;
return err;
}
void fbcon_rotate_ud(struct fbcon_ops *ops)
{
ops->bmove = ud_bmove;
ops->clear = ud_clear;
ops->putcs = ud_putcs;
ops->clear_margins = ud_clear_margins;
ops->cursor = ud_cursor;
ops->update_start = ud_update_start;
}
| linux-master | drivers/video/fbdev/core/fbcon_ud.c |
/*
* linux/drivers/video/console/softcursor.c
*
* Generic software cursor for frame buffer devices
*
* Created 14 Nov 2002 by James Simmons
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/slab.h>
#include <asm/io.h>
#include "fbcon.h"
int soft_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct fbcon_ops *ops = info->fbcon_par;
unsigned int scan_align = info->pixmap.scan_align - 1;
unsigned int buf_align = info->pixmap.buf_align - 1;
unsigned int i, size, dsize, s_pitch, d_pitch;
struct fb_image *image;
u8 *src, *dst;
if (info->state != FBINFO_STATE_RUNNING)
return 0;
s_pitch = (cursor->image.width + 7) >> 3;
dsize = s_pitch * cursor->image.height;
if (dsize + sizeof(struct fb_image) != ops->cursor_size) {
kfree(ops->cursor_src);
ops->cursor_size = dsize + sizeof(struct fb_image);
ops->cursor_src = kmalloc(ops->cursor_size, GFP_ATOMIC);
if (!ops->cursor_src) {
ops->cursor_size = 0;
return -ENOMEM;
}
}
src = ops->cursor_src + sizeof(struct fb_image);
image = (struct fb_image *)ops->cursor_src;
*image = cursor->image;
d_pitch = (s_pitch + scan_align) & ~scan_align;
size = d_pitch * image->height + buf_align;
size &= ~buf_align;
dst = fb_get_buffer_offset(info, &info->pixmap, size);
if (cursor->enable) {
switch (cursor->rop) {
case ROP_XOR:
for (i = 0; i < dsize; i++)
src[i] = image->data[i] ^ cursor->mask[i];
break;
case ROP_COPY:
default:
for (i = 0; i < dsize; i++)
src[i] = image->data[i] & cursor->mask[i];
break;
}
} else
memcpy(src, image->data, dsize);
fb_pad_aligned_buffer(dst, d_pitch, src, s_pitch, image->height);
image->data = dst;
info->fbops->fb_imageblit(info, image);
return 0;
}
| linux-master | drivers/video/fbdev/core/softcursor.c |
/*
* linux/drivers/video/fb_cmdline.c
*
* Copyright (C) 2014 Intel Corp
* Copyright (C) 1994 Martin Schaller
*
* 2001 - Documented with DocBook
* - Brad Douglas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* Authors:
* Daniel Vetter <[email protected]>
*/
#include <linux/export.h>
#include <linux/fb.h>
#include <linux/string.h>
#include <video/cmdline.h>
/**
* fb_get_options - get kernel boot parameters
* @name: framebuffer name as it would appear in
* the boot parameter line
* (video=<name>:<options>)
* @option: the option will be stored here
*
* The caller owns the string returned in @option and is
* responsible for releasing the memory.
*
* NOTE: Needed to maintain backwards compatibility
*/
int fb_get_options(const char *name, char **option)
{
const char *options = NULL;
bool is_of = false;
bool enabled;
if (name)
is_of = strncmp(name, "offb", 4);
enabled = __video_get_options(name, &options, is_of);
if (options) {
if (!strncmp(options, "off", 3))
enabled = false;
}
if (option) {
if (options)
*option = kstrdup(options, GFP_KERNEL);
else
*option = NULL;
}
return enabled ? 0 : 1; // 0 on success, 1 otherwise
}
EXPORT_SYMBOL(fb_get_options);
| linux-master | drivers/video/fbdev/core/fb_cmdline.c |
/*
* linux/drivers/video/fb_notify.c
*
* Copyright (C) 2006 Antonino Daplas <[email protected]>
*
* 2001 - Documented with DocBook
* - Brad Douglas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/fb.h>
#include <linux/notifier.h>
#include <linux/export.h>
static BLOCKING_NOTIFIER_HEAD(fb_notifier_list);
/**
* fb_register_client - register a client notifier
* @nb: notifier block to callback on events
*
* Return: 0 on success, negative error code on failure.
*/
int fb_register_client(struct notifier_block *nb)
{
return blocking_notifier_chain_register(&fb_notifier_list, nb);
}
EXPORT_SYMBOL(fb_register_client);
/**
* fb_unregister_client - unregister a client notifier
* @nb: notifier block to callback on events
*
* Return: 0 on success, negative error code on failure.
*/
int fb_unregister_client(struct notifier_block *nb)
{
return blocking_notifier_chain_unregister(&fb_notifier_list, nb);
}
EXPORT_SYMBOL(fb_unregister_client);
/**
* fb_notifier_call_chain - notify clients of fb_events
* @val: value passed to callback
* @v: pointer passed to callback
*
* Return: The return value of the last notifier function
*/
int fb_notifier_call_chain(unsigned long val, void *v)
{
return blocking_notifier_call_chain(&fb_notifier_list, val, v);
}
EXPORT_SYMBOL_GPL(fb_notifier_call_chain);
| linux-master | drivers/video/fbdev/core/fb_notify.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* fbsysfs.c - framebuffer device class and attributes
*
* Copyright (c) 2004 James Simmons <[email protected]>
*/
#include <linux/console.h>
#include <linux/fb.h>
#include <linux/fbcon.h>
#include <linux/major.h>
#include "fb_internal.h"
#define FB_SYSFS_FLAG_ATTR 1
static int activate(struct fb_info *fb_info, struct fb_var_screeninfo *var)
{
int err;
var->activate |= FB_ACTIVATE_FORCE;
console_lock();
lock_fb_info(fb_info);
err = fb_set_var(fb_info, var);
if (!err)
fbcon_update_vcs(fb_info, var->activate & FB_ACTIVATE_ALL);
unlock_fb_info(fb_info);
console_unlock();
if (err)
return err;
return 0;
}
static int mode_string(char *buf, unsigned int offset,
const struct fb_videomode *mode)
{
char m = 'U';
char v = 'p';
if (mode->flag & FB_MODE_IS_DETAILED)
m = 'D';
if (mode->flag & FB_MODE_IS_VESA)
m = 'V';
if (mode->flag & FB_MODE_IS_STANDARD)
m = 'S';
if (mode->vmode & FB_VMODE_INTERLACED)
v = 'i';
if (mode->vmode & FB_VMODE_DOUBLE)
v = 'd';
return snprintf(&buf[offset], PAGE_SIZE - offset, "%c:%dx%d%c-%d\n",
m, mode->xres, mode->yres, v, mode->refresh);
}
static ssize_t store_mode(struct device *device, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
char mstr[100];
struct fb_var_screeninfo var;
struct fb_modelist *modelist;
struct fb_videomode *mode;
size_t i;
int err;
memset(&var, 0, sizeof(var));
list_for_each_entry(modelist, &fb_info->modelist, list) {
mode = &modelist->mode;
i = mode_string(mstr, 0, mode);
if (strncmp(mstr, buf, max(count, i)) == 0) {
var = fb_info->var;
fb_videomode_to_var(&var, mode);
if ((err = activate(fb_info, &var)))
return err;
fb_info->mode = mode;
return count;
}
}
return -EINVAL;
}
static ssize_t show_mode(struct device *device, struct device_attribute *attr,
char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
if (!fb_info->mode)
return 0;
return mode_string(buf, 0, fb_info->mode);
}
static ssize_t store_modes(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
LIST_HEAD(old_list);
int i = count / sizeof(struct fb_videomode);
if (i * sizeof(struct fb_videomode) != count)
return -EINVAL;
console_lock();
lock_fb_info(fb_info);
list_splice(&fb_info->modelist, &old_list);
fb_videomode_to_modelist((const struct fb_videomode *)buf, i,
&fb_info->modelist);
if (fb_new_modelist(fb_info)) {
fb_destroy_modelist(&fb_info->modelist);
list_splice(&old_list, &fb_info->modelist);
} else
fb_destroy_modelist(&old_list);
unlock_fb_info(fb_info);
console_unlock();
return 0;
}
static ssize_t show_modes(struct device *device, struct device_attribute *attr,
char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
unsigned int i;
struct fb_modelist *modelist;
const struct fb_videomode *mode;
i = 0;
list_for_each_entry(modelist, &fb_info->modelist, list) {
mode = &modelist->mode;
i += mode_string(buf, i, mode);
}
return i;
}
static ssize_t store_bpp(struct device *device, struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
struct fb_var_screeninfo var;
char ** last = NULL;
int err;
var = fb_info->var;
var.bits_per_pixel = simple_strtoul(buf, last, 0);
if ((err = activate(fb_info, &var)))
return err;
return count;
}
static ssize_t show_bpp(struct device *device, struct device_attribute *attr,
char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
return sysfs_emit(buf, "%d\n", fb_info->var.bits_per_pixel);
}
static ssize_t store_rotate(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
struct fb_var_screeninfo var;
char **last = NULL;
int err;
var = fb_info->var;
var.rotate = simple_strtoul(buf, last, 0);
if ((err = activate(fb_info, &var)))
return err;
return count;
}
static ssize_t show_rotate(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
return sysfs_emit(buf, "%d\n", fb_info->var.rotate);
}
static ssize_t store_virtual(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
struct fb_var_screeninfo var;
char *last = NULL;
int err;
var = fb_info->var;
var.xres_virtual = simple_strtoul(buf, &last, 0);
last++;
if (last - buf >= count)
return -EINVAL;
var.yres_virtual = simple_strtoul(last, &last, 0);
if ((err = activate(fb_info, &var)))
return err;
return count;
}
static ssize_t show_virtual(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
return sysfs_emit(buf, "%d,%d\n", fb_info->var.xres_virtual,
fb_info->var.yres_virtual);
}
static ssize_t show_stride(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
return sysfs_emit(buf, "%d\n", fb_info->fix.line_length);
}
static ssize_t store_blank(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
char *last = NULL;
int err, arg;
arg = simple_strtoul(buf, &last, 0);
console_lock();
err = fb_blank(fb_info, arg);
/* might again call into fb_blank */
fbcon_fb_blanked(fb_info, arg);
console_unlock();
if (err < 0)
return err;
return count;
}
static ssize_t show_blank(struct device *device,
struct device_attribute *attr, char *buf)
{
// struct fb_info *fb_info = dev_get_drvdata(device);
return 0;
}
static ssize_t store_console(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
// struct fb_info *fb_info = dev_get_drvdata(device);
return 0;
}
static ssize_t show_console(struct device *device,
struct device_attribute *attr, char *buf)
{
// struct fb_info *fb_info = dev_get_drvdata(device);
return 0;
}
static ssize_t store_cursor(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
// struct fb_info *fb_info = dev_get_drvdata(device);
return 0;
}
static ssize_t show_cursor(struct device *device,
struct device_attribute *attr, char *buf)
{
// struct fb_info *fb_info = dev_get_drvdata(device);
return 0;
}
static ssize_t store_pan(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
struct fb_var_screeninfo var;
char *last = NULL;
int err;
var = fb_info->var;
var.xoffset = simple_strtoul(buf, &last, 0);
last++;
if (last - buf >= count)
return -EINVAL;
var.yoffset = simple_strtoul(last, &last, 0);
console_lock();
err = fb_pan_display(fb_info, &var);
console_unlock();
if (err < 0)
return err;
return count;
}
static ssize_t show_pan(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
return sysfs_emit(buf, "%d,%d\n", fb_info->var.xoffset,
fb_info->var.yoffset);
}
static ssize_t show_name(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
return sysfs_emit(buf, "%s\n", fb_info->fix.id);
}
static ssize_t store_fbstate(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
u32 state;
char *last = NULL;
state = simple_strtoul(buf, &last, 0);
console_lock();
lock_fb_info(fb_info);
fb_set_suspend(fb_info, (int)state);
unlock_fb_info(fb_info);
console_unlock();
return count;
}
static ssize_t show_fbstate(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
return sysfs_emit(buf, "%d\n", fb_info->state);
}
#if IS_ENABLED(CONFIG_FB_BACKLIGHT)
static ssize_t store_bl_curve(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *fb_info = dev_get_drvdata(device);
u8 tmp_curve[FB_BACKLIGHT_LEVELS];
unsigned int i;
/* Some drivers don't use framebuffer_alloc(), but those also
* don't have backlights.
*/
if (!fb_info || !fb_info->bl_dev)
return -ENODEV;
if (count != (FB_BACKLIGHT_LEVELS / 8 * 24))
return -EINVAL;
for (i = 0; i < (FB_BACKLIGHT_LEVELS / 8); ++i)
if (sscanf(&buf[i * 24],
"%2hhx %2hhx %2hhx %2hhx %2hhx %2hhx %2hhx %2hhx\n",
&tmp_curve[i * 8 + 0],
&tmp_curve[i * 8 + 1],
&tmp_curve[i * 8 + 2],
&tmp_curve[i * 8 + 3],
&tmp_curve[i * 8 + 4],
&tmp_curve[i * 8 + 5],
&tmp_curve[i * 8 + 6],
&tmp_curve[i * 8 + 7]) != 8)
return -EINVAL;
/* If there has been an error in the input data, we won't
* reach this loop.
*/
mutex_lock(&fb_info->bl_curve_mutex);
for (i = 0; i < FB_BACKLIGHT_LEVELS; ++i)
fb_info->bl_curve[i] = tmp_curve[i];
mutex_unlock(&fb_info->bl_curve_mutex);
return count;
}
static ssize_t show_bl_curve(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fb_info *fb_info = dev_get_drvdata(device);
ssize_t len = 0;
unsigned int i;
/* Some drivers don't use framebuffer_alloc(), but those also
* don't have backlights.
*/
if (!fb_info || !fb_info->bl_dev)
return -ENODEV;
mutex_lock(&fb_info->bl_curve_mutex);
for (i = 0; i < FB_BACKLIGHT_LEVELS; i += 8)
len += scnprintf(&buf[len], PAGE_SIZE - len, "%8ph\n",
fb_info->bl_curve + i);
mutex_unlock(&fb_info->bl_curve_mutex);
return len;
}
#endif
/* When cmap is added back in it should be a binary attribute
* not a text one. Consideration should also be given to converting
* fbdev to use configfs instead of sysfs */
static struct device_attribute device_attrs[] = {
__ATTR(bits_per_pixel, S_IRUGO|S_IWUSR, show_bpp, store_bpp),
__ATTR(blank, S_IRUGO|S_IWUSR, show_blank, store_blank),
__ATTR(console, S_IRUGO|S_IWUSR, show_console, store_console),
__ATTR(cursor, S_IRUGO|S_IWUSR, show_cursor, store_cursor),
__ATTR(mode, S_IRUGO|S_IWUSR, show_mode, store_mode),
__ATTR(modes, S_IRUGO|S_IWUSR, show_modes, store_modes),
__ATTR(pan, S_IRUGO|S_IWUSR, show_pan, store_pan),
__ATTR(virtual_size, S_IRUGO|S_IWUSR, show_virtual, store_virtual),
__ATTR(name, S_IRUGO, show_name, NULL),
__ATTR(stride, S_IRUGO, show_stride, NULL),
__ATTR(rotate, S_IRUGO|S_IWUSR, show_rotate, store_rotate),
__ATTR(state, S_IRUGO|S_IWUSR, show_fbstate, store_fbstate),
#if IS_ENABLED(CONFIG_FB_BACKLIGHT)
__ATTR(bl_curve, S_IRUGO|S_IWUSR, show_bl_curve, store_bl_curve),
#endif
};
static int fb_init_device(struct fb_info *fb_info)
{
int i, error = 0;
dev_set_drvdata(fb_info->dev, fb_info);
fb_info->class_flag |= FB_SYSFS_FLAG_ATTR;
for (i = 0; i < ARRAY_SIZE(device_attrs); i++) {
error = device_create_file(fb_info->dev, &device_attrs[i]);
if (error)
break;
}
if (error) {
while (--i >= 0)
device_remove_file(fb_info->dev, &device_attrs[i]);
fb_info->class_flag &= ~FB_SYSFS_FLAG_ATTR;
}
return 0;
}
static void fb_cleanup_device(struct fb_info *fb_info)
{
unsigned int i;
if (fb_info->class_flag & FB_SYSFS_FLAG_ATTR) {
for (i = 0; i < ARRAY_SIZE(device_attrs); i++)
device_remove_file(fb_info->dev, &device_attrs[i]);
fb_info->class_flag &= ~FB_SYSFS_FLAG_ATTR;
}
}
int fb_device_create(struct fb_info *fb_info)
{
int node = fb_info->node;
dev_t devt = MKDEV(FB_MAJOR, node);
int ret;
fb_info->dev = device_create(fb_class, fb_info->device, devt, NULL, "fb%d", node);
if (IS_ERR(fb_info->dev)) {
/* Not fatal */
ret = PTR_ERR(fb_info->dev);
pr_warn("Unable to create device for framebuffer %d; error %d\n", node, ret);
fb_info->dev = NULL;
} else {
fb_init_device(fb_info);
}
return 0;
}
void fb_device_destroy(struct fb_info *fb_info)
{
dev_t devt = MKDEV(FB_MAJOR, fb_info->node);
if (!fb_info->dev)
return;
fb_cleanup_device(fb_info);
device_destroy(fb_class, devt);
fb_info->dev = NULL;
}
| linux-master | drivers/video/fbdev/core/fbsysfs.c |
/*
* drivers/video/fb_ddc.c - DDC/EDID read support.
*
* Copyright (C) 2006 Dennis Munsie <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/fb.h>
#include <linux/i2c-algo-bit.h>
#include <linux/slab.h>
#include "../edid.h"
#define DDC_ADDR 0x50
static unsigned char *fb_do_probe_ddc_edid(struct i2c_adapter *adapter)
{
unsigned char start = 0x0;
unsigned char *buf = kmalloc(EDID_LENGTH, GFP_KERNEL);
struct i2c_msg msgs[] = {
{
.addr = DDC_ADDR,
.flags = 0,
.len = 1,
.buf = &start,
}, {
.addr = DDC_ADDR,
.flags = I2C_M_RD,
.len = EDID_LENGTH,
.buf = buf,
}
};
if (!buf) {
dev_warn(&adapter->dev, "unable to allocate memory for EDID "
"block.\n");
return NULL;
}
if (i2c_transfer(adapter, msgs, 2) == 2)
return buf;
dev_warn(&adapter->dev, "unable to read EDID block.\n");
kfree(buf);
return NULL;
}
unsigned char *fb_ddc_read(struct i2c_adapter *adapter)
{
struct i2c_algo_bit_data *algo_data = adapter->algo_data;
unsigned char *edid = NULL;
int i, j;
algo_data->setscl(algo_data->data, 1);
for (i = 0; i < 3; i++) {
/* For some old monitors we need the
* following process to initialize/stop DDC
*/
algo_data->setsda(algo_data->data, 1);
msleep(13);
algo_data->setscl(algo_data->data, 1);
if (algo_data->getscl) {
for (j = 0; j < 5; j++) {
msleep(10);
if (algo_data->getscl(algo_data->data))
break;
}
if (j == 5)
continue;
} else {
udelay(algo_data->udelay);
}
algo_data->setsda(algo_data->data, 0);
msleep(15);
algo_data->setscl(algo_data->data, 0);
msleep(15);
algo_data->setsda(algo_data->data, 1);
msleep(15);
/* Do the real work */
edid = fb_do_probe_ddc_edid(adapter);
algo_data->setsda(algo_data->data, 0);
algo_data->setscl(algo_data->data, 0);
msleep(15);
algo_data->setscl(algo_data->data, 1);
if (algo_data->getscl) {
for (j = 0; j < 10; j++) {
msleep(10);
if (algo_data->getscl(algo_data->data))
break;
}
} else {
udelay(algo_data->udelay);
}
algo_data->setsda(algo_data->data, 1);
msleep(15);
algo_data->setscl(algo_data->data, 0);
algo_data->setsda(algo_data->data, 0);
if (edid)
break;
}
/* Release the DDC lines when done or the Apple Cinema HD display
* will switch off
*/
algo_data->setsda(algo_data->data, 1);
algo_data->setscl(algo_data->data, 1);
adapter->class |= I2C_CLASS_DDC;
return edid;
}
EXPORT_SYMBOL_GPL(fb_ddc_read);
MODULE_AUTHOR("Dennis Munsie <[email protected]>");
MODULE_DESCRIPTION("DDC/EDID reading support");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/fb_ddc.c |
/*
* linux/drivers/video/fb_sys_read.c - Generic file operations where
* framebuffer is in system RAM
*
* Copyright (C) 2007 Antonino Daplas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
*/
#include <linux/fb.h>
#include <linux/module.h>
#include <linux/uaccess.h>
ssize_t fb_sys_read(struct fb_info *info, char __user *buf, size_t count,
loff_t *ppos)
{
unsigned long p = *ppos;
void *src;
int err = 0;
unsigned long total_size, c;
ssize_t ret;
if (!info->screen_buffer)
return -ENODEV;
total_size = info->screen_size;
if (total_size == 0)
total_size = info->fix.smem_len;
if (p >= total_size)
return 0;
if (count >= total_size)
count = total_size;
if (count + p > total_size)
count = total_size - p;
src = info->screen_buffer + p;
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
c = copy_to_user(buf, src, count);
if (c)
err = -EFAULT;
ret = count - c;
*ppos += ret;
return ret ? ret : err;
}
EXPORT_SYMBOL_GPL(fb_sys_read);
ssize_t fb_sys_write(struct fb_info *info, const char __user *buf,
size_t count, loff_t *ppos)
{
unsigned long p = *ppos;
void *dst;
int err = 0;
unsigned long total_size, c;
size_t ret;
if (!info->screen_buffer)
return -ENODEV;
total_size = info->screen_size;
if (total_size == 0)
total_size = info->fix.smem_len;
if (p > total_size)
return -EFBIG;
if (count > total_size) {
err = -EFBIG;
count = total_size;
}
if (count + p > total_size) {
if (!err)
err = -ENOSPC;
count = total_size - p;
}
dst = info->screen_buffer + p;
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
c = copy_from_user(dst, buf, count);
if (c)
err = -EFAULT;
ret = count - c;
*ppos += ret;
return ret ? ret : err;
}
EXPORT_SYMBOL_GPL(fb_sys_write);
MODULE_AUTHOR("Antonino Daplas <[email protected]>");
MODULE_DESCRIPTION("Generic file read (fb in system RAM)");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/fb_sys_fops.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/proc_fs.h>
#include "fb_internal.h"
static struct proc_dir_entry *fb_proc_dir_entry;
static void *fb_seq_start(struct seq_file *m, loff_t *pos)
{
mutex_lock(®istration_lock);
return (*pos < FB_MAX) ? pos : NULL;
}
static void fb_seq_stop(struct seq_file *m, void *v)
{
mutex_unlock(®istration_lock);
}
static void *fb_seq_next(struct seq_file *m, void *v, loff_t *pos)
{
(*pos)++;
return (*pos < FB_MAX) ? pos : NULL;
}
static int fb_seq_show(struct seq_file *m, void *v)
{
int i = *(loff_t *)v;
struct fb_info *fi = registered_fb[i];
if (fi)
seq_printf(m, "%d %s\n", fi->node, fi->fix.id);
return 0;
}
static const struct seq_operations __maybe_unused fb_proc_seq_ops = {
.start = fb_seq_start,
.stop = fb_seq_stop,
.next = fb_seq_next,
.show = fb_seq_show,
};
int fb_init_procfs(void)
{
struct proc_dir_entry *proc;
proc = proc_create_seq("fb", 0, NULL, &fb_proc_seq_ops);
if (!proc)
return -ENOMEM;
fb_proc_dir_entry = proc;
return 0;
}
void fb_cleanup_procfs(void)
{
proc_remove(fb_proc_dir_entry);
}
| linux-master | drivers/video/fbdev/core/fb_procfs.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/compat.h>
#include <linux/console.h>
#include <linux/fb.h>
#include <linux/fbcon.h>
#include <linux/major.h>
#include "fb_internal.h"
/*
* We hold a reference to the fb_info in file->private_data,
* but if the current registered fb has changed, we don't
* actually want to use it.
*
* So look up the fb_info using the inode minor number,
* and just verify it against the reference we have.
*/
static struct fb_info *file_fb_info(struct file *file)
{
struct inode *inode = file_inode(file);
int fbidx = iminor(inode);
struct fb_info *info = registered_fb[fbidx];
if (info != file->private_data)
info = NULL;
return info;
}
static ssize_t fb_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
{
struct fb_info *info = file_fb_info(file);
if (!info)
return -ENODEV;
if (info->state != FBINFO_STATE_RUNNING)
return -EPERM;
if (info->fbops->fb_read)
return info->fbops->fb_read(info, buf, count, ppos);
return fb_io_read(info, buf, count, ppos);
}
static ssize_t fb_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
{
struct fb_info *info = file_fb_info(file);
if (!info)
return -ENODEV;
if (info->state != FBINFO_STATE_RUNNING)
return -EPERM;
if (info->fbops->fb_write)
return info->fbops->fb_write(info, buf, count, ppos);
return fb_io_write(info, buf, count, ppos);
}
static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
const struct fb_ops *fb;
struct fb_var_screeninfo var;
struct fb_fix_screeninfo fix;
struct fb_cmap cmap_from;
struct fb_cmap_user cmap;
void __user *argp = (void __user *)arg;
long ret = 0;
switch (cmd) {
case FBIOGET_VSCREENINFO:
lock_fb_info(info);
var = info->var;
unlock_fb_info(info);
ret = copy_to_user(argp, &var, sizeof(var)) ? -EFAULT : 0;
break;
case FBIOPUT_VSCREENINFO:
if (copy_from_user(&var, argp, sizeof(var)))
return -EFAULT;
/* only for kernel-internal use */
var.activate &= ~FB_ACTIVATE_KD_TEXT;
console_lock();
lock_fb_info(info);
ret = fbcon_modechange_possible(info, &var);
if (!ret)
ret = fb_set_var(info, &var);
if (!ret)
fbcon_update_vcs(info, var.activate & FB_ACTIVATE_ALL);
unlock_fb_info(info);
console_unlock();
if (!ret && copy_to_user(argp, &var, sizeof(var)))
ret = -EFAULT;
break;
case FBIOGET_FSCREENINFO:
lock_fb_info(info);
memcpy(&fix, &info->fix, sizeof(fix));
if (info->flags & FBINFO_HIDE_SMEM_START)
fix.smem_start = 0;
unlock_fb_info(info);
ret = copy_to_user(argp, &fix, sizeof(fix)) ? -EFAULT : 0;
break;
case FBIOPUTCMAP:
if (copy_from_user(&cmap, argp, sizeof(cmap)))
return -EFAULT;
ret = fb_set_user_cmap(&cmap, info);
break;
case FBIOGETCMAP:
if (copy_from_user(&cmap, argp, sizeof(cmap)))
return -EFAULT;
lock_fb_info(info);
cmap_from = info->cmap;
unlock_fb_info(info);
ret = fb_cmap_to_user(&cmap_from, &cmap);
break;
case FBIOPAN_DISPLAY:
if (copy_from_user(&var, argp, sizeof(var)))
return -EFAULT;
console_lock();
lock_fb_info(info);
ret = fb_pan_display(info, &var);
unlock_fb_info(info);
console_unlock();
if (ret == 0 && copy_to_user(argp, &var, sizeof(var)))
return -EFAULT;
break;
case FBIO_CURSOR:
ret = -EINVAL;
break;
case FBIOGET_CON2FBMAP:
ret = fbcon_get_con2fb_map_ioctl(argp);
break;
case FBIOPUT_CON2FBMAP:
ret = fbcon_set_con2fb_map_ioctl(argp);
break;
case FBIOBLANK:
if (arg > FB_BLANK_POWERDOWN)
return -EINVAL;
console_lock();
lock_fb_info(info);
ret = fb_blank(info, arg);
/* might again call into fb_blank */
fbcon_fb_blanked(info, arg);
unlock_fb_info(info);
console_unlock();
break;
default:
lock_fb_info(info);
fb = info->fbops;
if (fb->fb_ioctl)
ret = fb->fb_ioctl(info, cmd, arg);
else
ret = -ENOTTY;
unlock_fb_info(info);
}
return ret;
}
static long fb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
struct fb_info *info = file_fb_info(file);
if (!info)
return -ENODEV;
return do_fb_ioctl(info, cmd, arg);
}
#ifdef CONFIG_COMPAT
struct fb_fix_screeninfo32 {
char id[16];
compat_caddr_t smem_start;
u32 smem_len;
u32 type;
u32 type_aux;
u32 visual;
u16 xpanstep;
u16 ypanstep;
u16 ywrapstep;
u32 line_length;
compat_caddr_t mmio_start;
u32 mmio_len;
u32 accel;
u16 reserved[3];
};
struct fb_cmap32 {
u32 start;
u32 len;
compat_caddr_t red;
compat_caddr_t green;
compat_caddr_t blue;
compat_caddr_t transp;
};
static int fb_getput_cmap(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct fb_cmap32 cmap32;
struct fb_cmap cmap_from;
struct fb_cmap_user cmap;
if (copy_from_user(&cmap32, compat_ptr(arg), sizeof(cmap32)))
return -EFAULT;
cmap = (struct fb_cmap_user) {
.start = cmap32.start,
.len = cmap32.len,
.red = compat_ptr(cmap32.red),
.green = compat_ptr(cmap32.green),
.blue = compat_ptr(cmap32.blue),
.transp = compat_ptr(cmap32.transp),
};
if (cmd == FBIOPUTCMAP)
return fb_set_user_cmap(&cmap, info);
lock_fb_info(info);
cmap_from = info->cmap;
unlock_fb_info(info);
return fb_cmap_to_user(&cmap_from, &cmap);
}
static int do_fscreeninfo_to_user(struct fb_fix_screeninfo *fix,
struct fb_fix_screeninfo32 __user *fix32)
{
__u32 data;
int err;
err = copy_to_user(&fix32->id, &fix->id, sizeof(fix32->id));
data = (__u32) (unsigned long) fix->smem_start;
err |= put_user(data, &fix32->smem_start);
err |= put_user(fix->smem_len, &fix32->smem_len);
err |= put_user(fix->type, &fix32->type);
err |= put_user(fix->type_aux, &fix32->type_aux);
err |= put_user(fix->visual, &fix32->visual);
err |= put_user(fix->xpanstep, &fix32->xpanstep);
err |= put_user(fix->ypanstep, &fix32->ypanstep);
err |= put_user(fix->ywrapstep, &fix32->ywrapstep);
err |= put_user(fix->line_length, &fix32->line_length);
data = (__u32) (unsigned long) fix->mmio_start;
err |= put_user(data, &fix32->mmio_start);
err |= put_user(fix->mmio_len, &fix32->mmio_len);
err |= put_user(fix->accel, &fix32->accel);
err |= copy_to_user(fix32->reserved, fix->reserved,
sizeof(fix->reserved));
if (err)
return -EFAULT;
return 0;
}
static int fb_get_fscreeninfo(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct fb_fix_screeninfo fix;
lock_fb_info(info);
fix = info->fix;
if (info->flags & FBINFO_HIDE_SMEM_START)
fix.smem_start = 0;
unlock_fb_info(info);
return do_fscreeninfo_to_user(&fix, compat_ptr(arg));
}
static long fb_compat_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct fb_info *info = file_fb_info(file);
const struct fb_ops *fb;
long ret = -ENOIOCTLCMD;
if (!info)
return -ENODEV;
fb = info->fbops;
switch (cmd) {
case FBIOGET_VSCREENINFO:
case FBIOPUT_VSCREENINFO:
case FBIOPAN_DISPLAY:
case FBIOGET_CON2FBMAP:
case FBIOPUT_CON2FBMAP:
arg = (unsigned long) compat_ptr(arg);
fallthrough;
case FBIOBLANK:
ret = do_fb_ioctl(info, cmd, arg);
break;
case FBIOGET_FSCREENINFO:
ret = fb_get_fscreeninfo(info, cmd, arg);
break;
case FBIOGETCMAP:
case FBIOPUTCMAP:
ret = fb_getput_cmap(info, cmd, arg);
break;
default:
if (fb->fb_compat_ioctl)
ret = fb->fb_compat_ioctl(info, cmd, arg);
break;
}
return ret;
}
#endif
static int fb_mmap(struct file *file, struct vm_area_struct *vma)
{
struct fb_info *info = file_fb_info(file);
unsigned long mmio_pgoff;
unsigned long start;
u32 len;
if (!info)
return -ENODEV;
mutex_lock(&info->mm_lock);
if (info->fbops->fb_mmap) {
int res;
/*
* The framebuffer needs to be accessed decrypted, be sure
* SME protection is removed ahead of the call
*/
vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
res = info->fbops->fb_mmap(info, vma);
mutex_unlock(&info->mm_lock);
return res;
#if IS_ENABLED(CONFIG_FB_DEFERRED_IO)
} else if (info->fbdefio) {
/*
* FB deferred I/O wants you to handle mmap in your drivers. At a
* minimum, point struct fb_ops.fb_mmap to fb_deferred_io_mmap().
*/
dev_warn_once(info->dev, "fbdev mmap not set up for deferred I/O.\n");
mutex_unlock(&info->mm_lock);
return -ENODEV;
#endif
}
/*
* Ugh. This can be either the frame buffer mapping, or
* if pgoff points past it, the mmio mapping.
*/
start = info->fix.smem_start;
len = info->fix.smem_len;
mmio_pgoff = PAGE_ALIGN((start & ~PAGE_MASK) + len) >> PAGE_SHIFT;
if (vma->vm_pgoff >= mmio_pgoff) {
if (info->var.accel_flags) {
mutex_unlock(&info->mm_lock);
return -EINVAL;
}
vma->vm_pgoff -= mmio_pgoff;
start = info->fix.mmio_start;
len = info->fix.mmio_len;
}
mutex_unlock(&info->mm_lock);
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
fb_pgprotect(file, vma, start);
return vm_iomap_memory(vma, start, len);
}
static int fb_open(struct inode *inode, struct file *file)
__acquires(&info->lock)
__releases(&info->lock)
{
int fbidx = iminor(inode);
struct fb_info *info;
int res = 0;
info = get_fb_info(fbidx);
if (!info) {
request_module("fb%d", fbidx);
info = get_fb_info(fbidx);
if (!info)
return -ENODEV;
}
if (IS_ERR(info))
return PTR_ERR(info);
lock_fb_info(info);
if (!try_module_get(info->fbops->owner)) {
res = -ENODEV;
goto out;
}
file->private_data = info;
if (info->fbops->fb_open) {
res = info->fbops->fb_open(info, 1);
if (res)
module_put(info->fbops->owner);
}
#ifdef CONFIG_FB_DEFERRED_IO
if (info->fbdefio)
fb_deferred_io_open(info, inode, file);
#endif
out:
unlock_fb_info(info);
if (res)
put_fb_info(info);
return res;
}
static int fb_release(struct inode *inode, struct file *file)
__acquires(&info->lock)
__releases(&info->lock)
{
struct fb_info * const info = file->private_data;
lock_fb_info(info);
#if IS_ENABLED(CONFIG_FB_DEFERRED_IO)
if (info->fbdefio)
fb_deferred_io_release(info);
#endif
if (info->fbops->fb_release)
info->fbops->fb_release(info, 1);
module_put(info->fbops->owner);
unlock_fb_info(info);
put_fb_info(info);
return 0;
}
#if defined(CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA) && !defined(CONFIG_MMU)
static unsigned long get_fb_unmapped_area(struct file *filp,
unsigned long addr, unsigned long len,
unsigned long pgoff, unsigned long flags)
{
struct fb_info * const info = filp->private_data;
unsigned long fb_size = PAGE_ALIGN(info->fix.smem_len);
if (pgoff > fb_size || len > fb_size - pgoff)
return -EINVAL;
return (unsigned long)info->screen_base + pgoff;
}
#endif
static const struct file_operations fb_fops = {
.owner = THIS_MODULE,
.read = fb_read,
.write = fb_write,
.unlocked_ioctl = fb_ioctl,
#ifdef CONFIG_COMPAT
.compat_ioctl = fb_compat_ioctl,
#endif
.mmap = fb_mmap,
.open = fb_open,
.release = fb_release,
#if defined(HAVE_ARCH_FB_UNMAPPED_AREA) || \
(defined(CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA) && \
!defined(CONFIG_MMU))
.get_unmapped_area = get_fb_unmapped_area,
#endif
#ifdef CONFIG_FB_DEFERRED_IO
.fsync = fb_deferred_io_fsync,
#endif
.llseek = default_llseek,
};
int fb_register_chrdev(void)
{
int ret;
ret = register_chrdev(FB_MAJOR, "fb", &fb_fops);
if (ret) {
pr_err("Unable to get major %d for fb devs\n", FB_MAJOR);
return ret;
}
return ret;
}
void fb_unregister_chrdev(void)
{
unregister_chrdev(FB_MAJOR, "fb");
}
| linux-master | drivers/video/fbdev/core/fb_chrdev.c |
/*
* linux/drivers/video/fbcmap.c -- Colormap handling for frame buffer devices
*
* Created 15 Jun 1997 by Geert Uytterhoeven
*
* 2001 - Documented with DocBook
* - Brad Douglas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/string.h>
#include <linux/module.h>
#include <linux/fb.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
static u16 red2[] __read_mostly = {
0x0000, 0xaaaa
};
static u16 green2[] __read_mostly = {
0x0000, 0xaaaa
};
static u16 blue2[] __read_mostly = {
0x0000, 0xaaaa
};
static u16 red4[] __read_mostly = {
0x0000, 0xaaaa, 0x5555, 0xffff
};
static u16 green4[] __read_mostly = {
0x0000, 0xaaaa, 0x5555, 0xffff
};
static u16 blue4[] __read_mostly = {
0x0000, 0xaaaa, 0x5555, 0xffff
};
static u16 red8[] __read_mostly = {
0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa
};
static u16 green8[] __read_mostly = {
0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa
};
static u16 blue8[] __read_mostly = {
0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa
};
static u16 red16[] __read_mostly = {
0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff
};
static u16 green16[] __read_mostly = {
0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa,
0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff
};
static u16 blue16[] __read_mostly = {
0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa,
0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff
};
static const struct fb_cmap default_2_colors = {
.len=2, .red=red2, .green=green2, .blue=blue2
};
static const struct fb_cmap default_8_colors = {
.len=8, .red=red8, .green=green8, .blue=blue8
};
static const struct fb_cmap default_4_colors = {
.len=4, .red=red4, .green=green4, .blue=blue4
};
static const struct fb_cmap default_16_colors = {
.len=16, .red=red16, .green=green16, .blue=blue16
};
/**
* fb_alloc_cmap_gfp - allocate a colormap
* @cmap: frame buffer colormap structure
* @len: length of @cmap
* @transp: boolean, 1 if there is transparency, 0 otherwise
* @flags: flags for kmalloc memory allocation
*
* Allocates memory for a colormap @cmap. @len is the
* number of entries in the palette.
*
* Returns negative errno on error, or zero on success.
*
*/
int fb_alloc_cmap_gfp(struct fb_cmap *cmap, int len, int transp, gfp_t flags)
{
int size = len * sizeof(u16);
int ret = -ENOMEM;
flags |= __GFP_NOWARN;
if (cmap->len != len) {
fb_dealloc_cmap(cmap);
if (!len)
return 0;
cmap->red = kzalloc(size, flags);
if (!cmap->red)
goto fail;
cmap->green = kzalloc(size, flags);
if (!cmap->green)
goto fail;
cmap->blue = kzalloc(size, flags);
if (!cmap->blue)
goto fail;
if (transp) {
cmap->transp = kzalloc(size, flags);
if (!cmap->transp)
goto fail;
} else {
cmap->transp = NULL;
}
}
cmap->start = 0;
cmap->len = len;
ret = fb_copy_cmap(fb_default_cmap(len), cmap);
if (ret)
goto fail;
return 0;
fail:
fb_dealloc_cmap(cmap);
return ret;
}
int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp)
{
return fb_alloc_cmap_gfp(cmap, len, transp, GFP_ATOMIC);
}
/**
* fb_dealloc_cmap - deallocate a colormap
* @cmap: frame buffer colormap structure
*
* Deallocates a colormap that was previously allocated with
* fb_alloc_cmap().
*
*/
void fb_dealloc_cmap(struct fb_cmap *cmap)
{
kfree(cmap->red);
kfree(cmap->green);
kfree(cmap->blue);
kfree(cmap->transp);
cmap->red = cmap->green = cmap->blue = cmap->transp = NULL;
cmap->len = 0;
}
/**
* fb_copy_cmap - copy a colormap
* @from: frame buffer colormap structure
* @to: frame buffer colormap structure
*
* Copy contents of colormap from @from to @to.
*/
int fb_copy_cmap(const struct fb_cmap *from, struct fb_cmap *to)
{
unsigned int tooff = 0, fromoff = 0;
size_t size;
if (to->start > from->start)
fromoff = to->start - from->start;
else
tooff = from->start - to->start;
if (fromoff >= from->len || tooff >= to->len)
return -EINVAL;
size = min_t(size_t, to->len - tooff, from->len - fromoff);
if (size == 0)
return -EINVAL;
size *= sizeof(u16);
memcpy(to->red+tooff, from->red+fromoff, size);
memcpy(to->green+tooff, from->green+fromoff, size);
memcpy(to->blue+tooff, from->blue+fromoff, size);
if (from->transp && to->transp)
memcpy(to->transp+tooff, from->transp+fromoff, size);
return 0;
}
int fb_cmap_to_user(const struct fb_cmap *from, struct fb_cmap_user *to)
{
unsigned int tooff = 0, fromoff = 0;
size_t size;
if (to->start > from->start)
fromoff = to->start - from->start;
else
tooff = from->start - to->start;
if (fromoff >= from->len || tooff >= to->len)
return -EINVAL;
size = min_t(size_t, to->len - tooff, from->len - fromoff);
if (size == 0)
return -EINVAL;
size *= sizeof(u16);
if (copy_to_user(to->red+tooff, from->red+fromoff, size))
return -EFAULT;
if (copy_to_user(to->green+tooff, from->green+fromoff, size))
return -EFAULT;
if (copy_to_user(to->blue+tooff, from->blue+fromoff, size))
return -EFAULT;
if (from->transp && to->transp)
if (copy_to_user(to->transp+tooff, from->transp+fromoff, size))
return -EFAULT;
return 0;
}
/**
* fb_set_cmap - set the colormap
* @cmap: frame buffer colormap structure
* @info: frame buffer info structure
*
* Sets the colormap @cmap for a screen of device @info.
*
* Returns negative errno on error, or zero on success.
*
*/
int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *info)
{
int i, start, rc = 0;
u16 *red, *green, *blue, *transp;
u_int hred, hgreen, hblue, htransp = 0xffff;
red = cmap->red;
green = cmap->green;
blue = cmap->blue;
transp = cmap->transp;
start = cmap->start;
if (start < 0 || (!info->fbops->fb_setcolreg &&
!info->fbops->fb_setcmap))
return -EINVAL;
if (info->fbops->fb_setcmap) {
rc = info->fbops->fb_setcmap(cmap, info);
} else {
for (i = 0; i < cmap->len; i++) {
hred = *red++;
hgreen = *green++;
hblue = *blue++;
if (transp)
htransp = *transp++;
if (info->fbops->fb_setcolreg(start++,
hred, hgreen, hblue,
htransp, info))
break;
}
}
if (rc == 0)
fb_copy_cmap(cmap, &info->cmap);
return rc;
}
int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *info)
{
int rc, size = cmap->len * sizeof(u16);
struct fb_cmap umap;
if (size < 0 || size < cmap->len)
return -E2BIG;
memset(&umap, 0, sizeof(struct fb_cmap));
rc = fb_alloc_cmap_gfp(&umap, cmap->len, cmap->transp != NULL,
GFP_KERNEL);
if (rc)
return rc;
if (copy_from_user(umap.red, cmap->red, size) ||
copy_from_user(umap.green, cmap->green, size) ||
copy_from_user(umap.blue, cmap->blue, size) ||
(cmap->transp && copy_from_user(umap.transp, cmap->transp, size))) {
rc = -EFAULT;
goto out;
}
umap.start = cmap->start;
lock_fb_info(info);
rc = fb_set_cmap(&umap, info);
unlock_fb_info(info);
out:
fb_dealloc_cmap(&umap);
return rc;
}
/**
* fb_default_cmap - get default colormap
* @len: size of palette for a depth
*
* Gets the default colormap for a specific screen depth. @len
* is the size of the palette for a particular screen depth.
*
* Returns pointer to a frame buffer colormap structure.
*
*/
const struct fb_cmap *fb_default_cmap(int len)
{
if (len <= 2)
return &default_2_colors;
if (len <= 4)
return &default_4_colors;
if (len <= 8)
return &default_8_colors;
return &default_16_colors;
}
/**
* fb_invert_cmaps - invert all defaults colormaps
*
* Invert all default colormaps.
*
*/
void fb_invert_cmaps(void)
{
u_int i;
for (i = 0; i < ARRAY_SIZE(red2); i++) {
red2[i] = ~red2[i];
green2[i] = ~green2[i];
blue2[i] = ~blue2[i];
}
for (i = 0; i < ARRAY_SIZE(red4); i++) {
red4[i] = ~red4[i];
green4[i] = ~green4[i];
blue4[i] = ~blue4[i];
}
for (i = 0; i < ARRAY_SIZE(red8); i++) {
red8[i] = ~red8[i];
green8[i] = ~green8[i];
blue8[i] = ~blue8[i];
}
for (i = 0; i < ARRAY_SIZE(red16); i++) {
red16[i] = ~red16[i];
green16[i] = ~green16[i];
blue16[i] = ~blue16[i];
}
}
/*
* Visible symbols for modules
*/
EXPORT_SYMBOL(fb_alloc_cmap);
EXPORT_SYMBOL(fb_dealloc_cmap);
EXPORT_SYMBOL(fb_copy_cmap);
EXPORT_SYMBOL(fb_set_cmap);
EXPORT_SYMBOL(fb_default_cmap);
EXPORT_SYMBOL(fb_invert_cmaps);
| linux-master | drivers/video/fbdev/core/fbcmap.c |
/*
* linux/drivers/video/fbcon.c -- Low level frame buffer based console driver
*
* Copyright (C) 1995 Geert Uytterhoeven
*
*
* This file is based on the original Amiga console driver (amicon.c):
*
* Copyright (C) 1993 Hamish Macdonald
* Greg Harp
* Copyright (C) 1994 David Carter [[email protected]]
*
* with work by William Rucklidge ([email protected])
* Geert Uytterhoeven
* Jes Sorensen ([email protected])
* Martin Apel
*
* and on the original Atari console driver (atacon.c):
*
* Copyright (C) 1993 Bjoern Brauel
* Roman Hodek
*
* with work by Guenther Kelleter
* Martin Schaller
* Andreas Schwab
*
* Hardware cursor support added by Emmanuel Marty ([email protected])
* Smart redraw scrolling, arbitrary font width support, 512char font support
* and software scrollback added by
* Jakub Jelinek ([email protected])
*
* Random hacking by Martin Mares <[email protected]>
*
* 2001 - Documented with DocBook
* - Brad Douglas <[email protected]>
*
* The low level operations for the various display memory organizations are
* now in separate source files.
*
* Currently the following organizations are supported:
*
* o afb Amiga bitplanes
* o cfb{2,4,8,16,24,32} Packed pixels
* o ilbm Amiga interleaved bitplanes
* o iplan2p[248] Atari interleaved bitplanes
* o mfb Monochrome
* o vga VGA characters/attributes
*
* To do:
*
* - Implement 16 plane mode (iplan2p16)
*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/delay.h> /* MSch: for IRQ probe */
#include <linux/console.h>
#include <linux/string.h>
#include <linux/kd.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/fbcon.h>
#include <linux/vt_kern.h>
#include <linux/selection.h>
#include <linux/font.h>
#include <linux/smp.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/crc32.h> /* For counting font checksums */
#include <linux/uaccess.h>
#include <asm/irq.h>
#include "fbcon.h"
#include "fb_internal.h"
/*
* FIXME: Locking
*
* - fbcon state itself is protected by the console_lock, and the code does a
* pretty good job at making sure that lock is held everywhere it's needed.
*
* - fbcon doesn't bother with fb_lock/unlock at all. This is buggy, since it
* means concurrent access to the same fbdev from both fbcon and userspace
* will blow up. To fix this all fbcon calls from fbmem.c need to be moved out
* of fb_lock/unlock protected sections, since otherwise we'll recurse and
* deadlock eventually. Aside: Due to these deadlock issues the fbdev code in
* fbmem.c cannot use locking asserts, and there's lots of callers which get
* the rules wrong, e.g. fbsysfs.c entirely missed fb_lock/unlock calls too.
*/
enum {
FBCON_LOGO_CANSHOW = -1, /* the logo can be shown */
FBCON_LOGO_DRAW = -2, /* draw the logo to a console */
FBCON_LOGO_DONTSHOW = -3 /* do not show the logo */
};
static struct fbcon_display fb_display[MAX_NR_CONSOLES];
static struct fb_info *fbcon_registered_fb[FB_MAX];
static int fbcon_num_registered_fb;
#define fbcon_for_each_registered_fb(i) \
for (i = 0; WARN_CONSOLE_UNLOCKED(), i < FB_MAX; i++) \
if (!fbcon_registered_fb[i]) {} else
static signed char con2fb_map[MAX_NR_CONSOLES];
static signed char con2fb_map_boot[MAX_NR_CONSOLES];
static struct fb_info *fbcon_info_from_console(int console)
{
WARN_CONSOLE_UNLOCKED();
return fbcon_registered_fb[con2fb_map[console]];
}
static int logo_lines;
/* logo_shown is an index to vc_cons when >= 0; otherwise follows FBCON_LOGO
enums. */
static int logo_shown = FBCON_LOGO_CANSHOW;
/* console mappings */
static unsigned int first_fb_vc;
static unsigned int last_fb_vc = MAX_NR_CONSOLES - 1;
static int fbcon_is_default = 1;
static int primary_device = -1;
static int fbcon_has_console_bind;
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY
static int map_override;
static inline void fbcon_map_override(void)
{
map_override = 1;
}
#else
static inline void fbcon_map_override(void)
{
}
#endif /* CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY */
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER
static bool deferred_takeover = true;
#else
#define deferred_takeover false
#endif
/* font data */
static char fontname[40];
/* current fb_info */
static int info_idx = -1;
/* console rotation */
static int initial_rotation = -1;
static int fbcon_has_sysfs;
static int margin_color;
static const struct consw fb_con;
#define advance_row(p, delta) (unsigned short *)((unsigned long)(p) + (delta) * vc->vc_size_row)
static int fbcon_cursor_noblink;
#define divides(a, b) ((!(a) || (b)%(a)) ? 0 : 1)
/*
* Interface used by the world
*/
static void fbcon_clear_margins(struct vc_data *vc, int bottom_only);
static void fbcon_set_palette(struct vc_data *vc, const unsigned char *table);
/*
* Internal routines
*/
static void fbcon_set_disp(struct fb_info *info, struct fb_var_screeninfo *var,
int unit);
static void fbcon_redraw_move(struct vc_data *vc, struct fbcon_display *p,
int line, int count, int dy);
static void fbcon_modechanged(struct fb_info *info);
static void fbcon_set_all_vcs(struct fb_info *info);
static struct device *fbcon_device;
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_ROTATION
static inline void fbcon_set_rotation(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
if (!(info->flags & FBINFO_MISC_TILEBLITTING) &&
ops->p->con_rotate < 4)
ops->rotate = ops->p->con_rotate;
else
ops->rotate = 0;
}
static void fbcon_rotate(struct fb_info *info, u32 rotate)
{
struct fbcon_ops *ops= info->fbcon_par;
struct fb_info *fb_info;
if (!ops || ops->currcon == -1)
return;
fb_info = fbcon_info_from_console(ops->currcon);
if (info == fb_info) {
struct fbcon_display *p = &fb_display[ops->currcon];
if (rotate < 4)
p->con_rotate = rotate;
else
p->con_rotate = 0;
fbcon_modechanged(info);
}
}
static void fbcon_rotate_all(struct fb_info *info, u32 rotate)
{
struct fbcon_ops *ops = info->fbcon_par;
struct vc_data *vc;
struct fbcon_display *p;
int i;
if (!ops || ops->currcon < 0 || rotate > 3)
return;
for (i = first_fb_vc; i <= last_fb_vc; i++) {
vc = vc_cons[i].d;
if (!vc || vc->vc_mode != KD_TEXT ||
fbcon_info_from_console(i) != info)
continue;
p = &fb_display[vc->vc_num];
p->con_rotate = rotate;
}
fbcon_set_all_vcs(info);
}
#else
static inline void fbcon_set_rotation(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
ops->rotate = FB_ROTATE_UR;
}
static void fbcon_rotate(struct fb_info *info, u32 rotate)
{
return;
}
static void fbcon_rotate_all(struct fb_info *info, u32 rotate)
{
return;
}
#endif /* CONFIG_FRAMEBUFFER_CONSOLE_ROTATION */
static int fbcon_get_rotate(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
return (ops) ? ops->rotate : 0;
}
static inline int fbcon_is_inactive(struct vc_data *vc, struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
return (info->state != FBINFO_STATE_RUNNING ||
vc->vc_mode != KD_TEXT || ops->graphics);
}
static int get_color(struct vc_data *vc, struct fb_info *info,
u16 c, int is_fg)
{
int depth = fb_get_color_depth(&info->var, &info->fix);
int color = 0;
if (console_blanked) {
unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
c = vc->vc_video_erase_char & charmask;
}
if (depth != 1)
color = (is_fg) ? attr_fgcol((vc->vc_hi_font_mask) ? 9 : 8, c)
: attr_bgcol((vc->vc_hi_font_mask) ? 13 : 12, c);
switch (depth) {
case 1:
{
int col = mono_col(info);
/* 0 or 1 */
int fg = (info->fix.visual != FB_VISUAL_MONO01) ? col : 0;
int bg = (info->fix.visual != FB_VISUAL_MONO01) ? 0 : col;
if (console_blanked)
fg = bg;
color = (is_fg) ? fg : bg;
break;
}
case 2:
/*
* Scale down 16-colors to 4 colors. Default 4-color palette
* is grayscale. However, simply dividing the values by 4
* will not work, as colors 1, 2 and 3 will be scaled-down
* to zero rendering them invisible. So empirically convert
* colors to a sane 4-level grayscale.
*/
switch (color) {
case 0:
color = 0; /* black */
break;
case 1 ... 6:
color = 2; /* white */
break;
case 7 ... 8:
color = 1; /* gray */
break;
default:
color = 3; /* intense white */
break;
}
break;
case 3:
/*
* Last 8 entries of default 16-color palette is a more intense
* version of the first 8 (i.e., same chrominance, different
* luminance).
*/
color &= 7;
break;
}
return color;
}
static void fb_flashcursor(struct work_struct *work)
{
struct fbcon_ops *ops = container_of(work, struct fbcon_ops, cursor_work.work);
struct fb_info *info;
struct vc_data *vc = NULL;
int c;
int mode;
int ret;
/* FIXME: we should sort out the unbind locking instead */
/* instead we just fail to flash the cursor if we can't get
* the lock instead of blocking fbcon deinit */
ret = console_trylock();
if (ret == 0)
return;
/* protected by console_lock */
info = ops->info;
if (ops->currcon != -1)
vc = vc_cons[ops->currcon].d;
if (!vc || !con_is_visible(vc) ||
fbcon_info_from_console(vc->vc_num) != info ||
vc->vc_deccm != 1) {
console_unlock();
return;
}
c = scr_readw((u16 *) vc->vc_pos);
mode = (!ops->cursor_flash || ops->cursor_state.enable) ?
CM_ERASE : CM_DRAW;
ops->cursor(vc, info, mode, get_color(vc, info, c, 1),
get_color(vc, info, c, 0));
console_unlock();
queue_delayed_work(system_power_efficient_wq, &ops->cursor_work,
ops->cur_blink_jiffies);
}
static void fbcon_add_cursor_work(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
if (!fbcon_cursor_noblink)
queue_delayed_work(system_power_efficient_wq, &ops->cursor_work,
ops->cur_blink_jiffies);
}
static void fbcon_del_cursor_work(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
cancel_delayed_work_sync(&ops->cursor_work);
}
#ifndef MODULE
static int __init fb_console_setup(char *this_opt)
{
char *options;
int i, j;
if (!this_opt || !*this_opt)
return 1;
while ((options = strsep(&this_opt, ",")) != NULL) {
if (!strncmp(options, "font:", 5)) {
strscpy(fontname, options + 5, sizeof(fontname));
continue;
}
if (!strncmp(options, "scrollback:", 11)) {
pr_warn("Ignoring scrollback size option\n");
continue;
}
if (!strncmp(options, "map:", 4)) {
options += 4;
if (*options) {
for (i = 0, j = 0; i < MAX_NR_CONSOLES; i++) {
if (!options[j])
j = 0;
con2fb_map_boot[i] =
(options[j++]-'0') % FB_MAX;
}
fbcon_map_override();
}
continue;
}
if (!strncmp(options, "vc:", 3)) {
options += 3;
if (*options)
first_fb_vc = simple_strtoul(options, &options, 10) - 1;
if (first_fb_vc >= MAX_NR_CONSOLES)
first_fb_vc = 0;
if (*options++ == '-')
last_fb_vc = simple_strtoul(options, &options, 10) - 1;
if (last_fb_vc < first_fb_vc || last_fb_vc >= MAX_NR_CONSOLES)
last_fb_vc = MAX_NR_CONSOLES - 1;
fbcon_is_default = 0;
continue;
}
if (!strncmp(options, "rotate:", 7)) {
options += 7;
if (*options)
initial_rotation = simple_strtoul(options, &options, 0);
if (initial_rotation > 3)
initial_rotation = 0;
continue;
}
if (!strncmp(options, "margin:", 7)) {
options += 7;
if (*options)
margin_color = simple_strtoul(options, &options, 0);
continue;
}
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER
if (!strcmp(options, "nodefer")) {
deferred_takeover = false;
continue;
}
#endif
if (!strncmp(options, "logo-pos:", 9)) {
options += 9;
if (!strcmp(options, "center"))
fb_center_logo = true;
continue;
}
if (!strncmp(options, "logo-count:", 11)) {
options += 11;
if (*options)
fb_logo_count = simple_strtol(options, &options, 0);
continue;
}
}
return 1;
}
__setup("fbcon=", fb_console_setup);
#endif
static int search_fb_in_map(int idx)
{
int i, retval = 0;
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map[i] == idx)
retval = 1;
}
return retval;
}
static int search_for_mapped_con(void)
{
int i, retval = 0;
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map[i] != -1)
retval = 1;
}
return retval;
}
static int do_fbcon_takeover(int show_logo)
{
int err, i;
if (!fbcon_num_registered_fb)
return -ENODEV;
if (!show_logo)
logo_shown = FBCON_LOGO_DONTSHOW;
for (i = first_fb_vc; i <= last_fb_vc; i++)
con2fb_map[i] = info_idx;
err = do_take_over_console(&fb_con, first_fb_vc, last_fb_vc,
fbcon_is_default);
if (err) {
for (i = first_fb_vc; i <= last_fb_vc; i++)
con2fb_map[i] = -1;
info_idx = -1;
} else {
fbcon_has_console_bind = 1;
}
return err;
}
#ifdef MODULE
static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info,
int cols, int rows, int new_cols, int new_rows)
{
logo_shown = FBCON_LOGO_DONTSHOW;
}
#else
static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info,
int cols, int rows, int new_cols, int new_rows)
{
/* Need to make room for the logo */
struct fbcon_ops *ops = info->fbcon_par;
int cnt, erase = vc->vc_video_erase_char, step;
unsigned short *save = NULL, *r, *q;
int logo_height;
if (info->fbops->owner) {
logo_shown = FBCON_LOGO_DONTSHOW;
return;
}
/*
* remove underline attribute from erase character
* if black and white framebuffer.
*/
if (fb_get_color_depth(&info->var, &info->fix) == 1)
erase &= ~0x400;
logo_height = fb_prepare_logo(info, ops->rotate);
logo_lines = DIV_ROUND_UP(logo_height, vc->vc_font.height);
q = (unsigned short *) (vc->vc_origin +
vc->vc_size_row * rows);
step = logo_lines * cols;
for (r = q - logo_lines * cols; r < q; r++)
if (scr_readw(r) != vc->vc_video_erase_char)
break;
if (r != q && new_rows >= rows + logo_lines) {
save = kmalloc(array3_size(logo_lines, new_cols, 2),
GFP_KERNEL);
if (save) {
int i = min(cols, new_cols);
scr_memsetw(save, erase, array3_size(logo_lines, new_cols, 2));
r = q - step;
for (cnt = 0; cnt < logo_lines; cnt++, r += i)
scr_memcpyw(save + cnt * new_cols, r, 2 * i);
r = q;
}
}
if (r == q) {
/* We can scroll screen down */
r = q - step - cols;
for (cnt = rows - logo_lines; cnt > 0; cnt--) {
scr_memcpyw(r + step, r, vc->vc_size_row);
r -= cols;
}
if (!save) {
int lines;
if (vc->state.y + logo_lines >= rows)
lines = rows - vc->state.y - 1;
else
lines = logo_lines;
vc->state.y += lines;
vc->vc_pos += lines * vc->vc_size_row;
}
}
scr_memsetw((unsigned short *) vc->vc_origin,
erase,
vc->vc_size_row * logo_lines);
if (con_is_visible(vc) && vc->vc_mode == KD_TEXT) {
fbcon_clear_margins(vc, 0);
update_screen(vc);
}
if (save) {
q = (unsigned short *) (vc->vc_origin +
vc->vc_size_row *
rows);
scr_memcpyw(q, save, array3_size(logo_lines, new_cols, 2));
vc->state.y += logo_lines;
vc->vc_pos += logo_lines * vc->vc_size_row;
kfree(save);
}
if (logo_shown == FBCON_LOGO_DONTSHOW)
return;
if (logo_lines > vc->vc_bottom) {
logo_shown = FBCON_LOGO_CANSHOW;
printk(KERN_INFO
"fbcon_init: disable boot-logo (boot-logo bigger than screen).\n");
} else {
logo_shown = FBCON_LOGO_DRAW;
vc->vc_top = logo_lines;
}
}
#endif /* MODULE */
#ifdef CONFIG_FB_TILEBLITTING
static void set_blitting_type(struct vc_data *vc, struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
ops->p = &fb_display[vc->vc_num];
if ((info->flags & FBINFO_MISC_TILEBLITTING))
fbcon_set_tileops(vc, info);
else {
fbcon_set_rotation(info);
fbcon_set_bitops(ops);
}
}
static int fbcon_invalid_charcount(struct fb_info *info, unsigned charcount)
{
int err = 0;
if (info->flags & FBINFO_MISC_TILEBLITTING &&
info->tileops->fb_get_tilemax(info) < charcount)
err = 1;
return err;
}
#else
static void set_blitting_type(struct vc_data *vc, struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
info->flags &= ~FBINFO_MISC_TILEBLITTING;
ops->p = &fb_display[vc->vc_num];
fbcon_set_rotation(info);
fbcon_set_bitops(ops);
}
static int fbcon_invalid_charcount(struct fb_info *info, unsigned charcount)
{
return 0;
}
#endif /* CONFIG_MISC_TILEBLITTING */
static void fbcon_release(struct fb_info *info)
{
lock_fb_info(info);
if (info->fbops->fb_release)
info->fbops->fb_release(info, 0);
unlock_fb_info(info);
module_put(info->fbops->owner);
if (info->fbcon_par) {
struct fbcon_ops *ops = info->fbcon_par;
fbcon_del_cursor_work(info);
kfree(ops->cursor_state.mask);
kfree(ops->cursor_data);
kfree(ops->cursor_src);
kfree(ops->fontbuffer);
kfree(info->fbcon_par);
info->fbcon_par = NULL;
}
}
static int fbcon_open(struct fb_info *info)
{
struct fbcon_ops *ops;
if (!try_module_get(info->fbops->owner))
return -ENODEV;
lock_fb_info(info);
if (info->fbops->fb_open &&
info->fbops->fb_open(info, 0)) {
unlock_fb_info(info);
module_put(info->fbops->owner);
return -ENODEV;
}
unlock_fb_info(info);
ops = kzalloc(sizeof(struct fbcon_ops), GFP_KERNEL);
if (!ops) {
fbcon_release(info);
return -ENOMEM;
}
INIT_DELAYED_WORK(&ops->cursor_work, fb_flashcursor);
ops->info = info;
info->fbcon_par = ops;
ops->cur_blink_jiffies = HZ / 5;
return 0;
}
static int con2fb_acquire_newinfo(struct vc_data *vc, struct fb_info *info,
int unit)
{
int err;
err = fbcon_open(info);
if (err)
return err;
if (vc)
set_blitting_type(vc, info);
return err;
}
static void con2fb_release_oldinfo(struct vc_data *vc, struct fb_info *oldinfo,
struct fb_info *newinfo)
{
int ret;
fbcon_release(oldinfo);
/*
If oldinfo and newinfo are driving the same hardware,
the fb_release() method of oldinfo may attempt to
restore the hardware state. This will leave the
newinfo in an undefined state. Thus, a call to
fb_set_par() may be needed for the newinfo.
*/
if (newinfo && newinfo->fbops->fb_set_par) {
ret = newinfo->fbops->fb_set_par(newinfo);
if (ret)
printk(KERN_ERR "con2fb_release_oldinfo: "
"detected unhandled fb_set_par error, "
"error code %d\n", ret);
}
}
static void con2fb_init_display(struct vc_data *vc, struct fb_info *info,
int unit, int show_logo)
{
struct fbcon_ops *ops = info->fbcon_par;
int ret;
ops->currcon = fg_console;
if (info->fbops->fb_set_par && !ops->initialized) {
ret = info->fbops->fb_set_par(info);
if (ret)
printk(KERN_ERR "con2fb_init_display: detected "
"unhandled fb_set_par error, "
"error code %d\n", ret);
}
ops->initialized = true;
ops->graphics = 0;
fbcon_set_disp(info, &info->var, unit);
if (show_logo) {
struct vc_data *fg_vc = vc_cons[fg_console].d;
struct fb_info *fg_info =
fbcon_info_from_console(fg_console);
fbcon_prepare_logo(fg_vc, fg_info, fg_vc->vc_cols,
fg_vc->vc_rows, fg_vc->vc_cols,
fg_vc->vc_rows);
}
update_screen(vc_cons[fg_console].d);
}
/**
* set_con2fb_map - map console to frame buffer device
* @unit: virtual console number to map
* @newidx: frame buffer index to map virtual console to
* @user: user request
*
* Maps a virtual console @unit to a frame buffer device
* @newidx.
*
* This should be called with the console lock held.
*/
static int set_con2fb_map(int unit, int newidx, int user)
{
struct vc_data *vc = vc_cons[unit].d;
int oldidx = con2fb_map[unit];
struct fb_info *info = fbcon_registered_fb[newidx];
struct fb_info *oldinfo = NULL;
int err = 0, show_logo;
WARN_CONSOLE_UNLOCKED();
if (oldidx == newidx)
return 0;
if (!info)
return -EINVAL;
if (!search_for_mapped_con() || !con_is_bound(&fb_con)) {
info_idx = newidx;
return do_fbcon_takeover(0);
}
if (oldidx != -1)
oldinfo = fbcon_registered_fb[oldidx];
if (!search_fb_in_map(newidx)) {
err = con2fb_acquire_newinfo(vc, info, unit);
if (err)
return err;
fbcon_add_cursor_work(info);
}
con2fb_map[unit] = newidx;
/*
* If old fb is not mapped to any of the consoles,
* fbcon should release it.
*/
if (oldinfo && !search_fb_in_map(oldidx))
con2fb_release_oldinfo(vc, oldinfo, info);
show_logo = (fg_console == 0 && !user &&
logo_shown != FBCON_LOGO_DONTSHOW);
con2fb_map_boot[unit] = newidx;
con2fb_init_display(vc, info, unit, show_logo);
if (!search_fb_in_map(info_idx))
info_idx = newidx;
return err;
}
/*
* Low Level Operations
*/
/* NOTE: fbcon cannot be __init: it may be called from do_take_over_console later */
static int var_to_display(struct fbcon_display *disp,
struct fb_var_screeninfo *var,
struct fb_info *info)
{
disp->xres_virtual = var->xres_virtual;
disp->yres_virtual = var->yres_virtual;
disp->bits_per_pixel = var->bits_per_pixel;
disp->grayscale = var->grayscale;
disp->nonstd = var->nonstd;
disp->accel_flags = var->accel_flags;
disp->height = var->height;
disp->width = var->width;
disp->red = var->red;
disp->green = var->green;
disp->blue = var->blue;
disp->transp = var->transp;
disp->rotate = var->rotate;
disp->mode = fb_match_mode(var, &info->modelist);
if (disp->mode == NULL)
/* This should not happen */
return -EINVAL;
return 0;
}
static void display_to_var(struct fb_var_screeninfo *var,
struct fbcon_display *disp)
{
fb_videomode_to_var(var, disp->mode);
var->xres_virtual = disp->xres_virtual;
var->yres_virtual = disp->yres_virtual;
var->bits_per_pixel = disp->bits_per_pixel;
var->grayscale = disp->grayscale;
var->nonstd = disp->nonstd;
var->accel_flags = disp->accel_flags;
var->height = disp->height;
var->width = disp->width;
var->red = disp->red;
var->green = disp->green;
var->blue = disp->blue;
var->transp = disp->transp;
var->rotate = disp->rotate;
}
static const char *fbcon_startup(void)
{
const char *display_desc = "frame buffer device";
struct fbcon_display *p = &fb_display[fg_console];
struct vc_data *vc = vc_cons[fg_console].d;
const struct font_desc *font = NULL;
struct fb_info *info = NULL;
struct fbcon_ops *ops;
int rows, cols;
/*
* If num_registered_fb is zero, this is a call for the dummy part.
* The frame buffer devices weren't initialized yet.
*/
if (!fbcon_num_registered_fb || info_idx == -1)
return display_desc;
/*
* Instead of blindly using registered_fb[0], we use info_idx, set by
* fbcon_fb_registered();
*/
info = fbcon_registered_fb[info_idx];
if (!info)
return NULL;
if (fbcon_open(info))
return NULL;
ops = info->fbcon_par;
ops->currcon = -1;
ops->graphics = 1;
ops->cur_rotate = -1;
p->con_rotate = initial_rotation;
if (p->con_rotate == -1)
p->con_rotate = info->fbcon_rotate_hint;
if (p->con_rotate == -1)
p->con_rotate = FB_ROTATE_UR;
set_blitting_type(vc, info);
/* Setup default font */
if (!p->fontdata) {
if (!fontname[0] || !(font = find_font(fontname)))
font = get_default_font(info->var.xres,
info->var.yres,
info->pixmap.blit_x,
info->pixmap.blit_y);
vc->vc_font.width = font->width;
vc->vc_font.height = font->height;
vc->vc_font.data = (void *)(p->fontdata = font->data);
vc->vc_font.charcount = font->charcount;
}
cols = FBCON_SWAP(ops->rotate, info->var.xres, info->var.yres);
rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
cols /= vc->vc_font.width;
rows /= vc->vc_font.height;
vc_resize(vc, cols, rows);
pr_debug("mode: %s\n", info->fix.id);
pr_debug("visual: %d\n", info->fix.visual);
pr_debug("res: %dx%d-%d\n", info->var.xres,
info->var.yres,
info->var.bits_per_pixel);
fbcon_add_cursor_work(info);
return display_desc;
}
static void fbcon_init(struct vc_data *vc, int init)
{
struct fb_info *info;
struct fbcon_ops *ops;
struct vc_data **default_mode = vc->vc_display_fg;
struct vc_data *svc = *default_mode;
struct fbcon_display *t, *p = &fb_display[vc->vc_num];
int logo = 1, new_rows, new_cols, rows, cols;
int ret;
if (WARN_ON(info_idx == -1))
return;
if (con2fb_map[vc->vc_num] == -1)
con2fb_map[vc->vc_num] = info_idx;
info = fbcon_info_from_console(vc->vc_num);
if (logo_shown < 0 && console_loglevel <= CONSOLE_LOGLEVEL_QUIET)
logo_shown = FBCON_LOGO_DONTSHOW;
if (vc != svc || logo_shown == FBCON_LOGO_DONTSHOW ||
(info->fix.type == FB_TYPE_TEXT))
logo = 0;
if (var_to_display(p, &info->var, info))
return;
if (!info->fbcon_par)
con2fb_acquire_newinfo(vc, info, vc->vc_num);
/* If we are not the first console on this
fb, copy the font from that console */
t = &fb_display[fg_console];
if (!p->fontdata) {
if (t->fontdata) {
struct vc_data *fvc = vc_cons[fg_console].d;
vc->vc_font.data = (void *)(p->fontdata =
fvc->vc_font.data);
vc->vc_font.width = fvc->vc_font.width;
vc->vc_font.height = fvc->vc_font.height;
vc->vc_font.charcount = fvc->vc_font.charcount;
p->userfont = t->userfont;
if (p->userfont)
REFCOUNT(p->fontdata)++;
} else {
const struct font_desc *font = NULL;
if (!fontname[0] || !(font = find_font(fontname)))
font = get_default_font(info->var.xres,
info->var.yres,
info->pixmap.blit_x,
info->pixmap.blit_y);
vc->vc_font.width = font->width;
vc->vc_font.height = font->height;
vc->vc_font.data = (void *)(p->fontdata = font->data);
vc->vc_font.charcount = font->charcount;
}
}
vc->vc_can_do_color = (fb_get_color_depth(&info->var, &info->fix)!=1);
vc->vc_complement_mask = vc->vc_can_do_color ? 0x7700 : 0x0800;
if (vc->vc_font.charcount == 256) {
vc->vc_hi_font_mask = 0;
} else {
vc->vc_hi_font_mask = 0x100;
if (vc->vc_can_do_color)
vc->vc_complement_mask <<= 1;
}
if (!*svc->uni_pagedict_loc)
con_set_default_unimap(svc);
if (!*vc->uni_pagedict_loc)
con_copy_unimap(vc, svc);
ops = info->fbcon_par;
ops->cur_blink_jiffies = msecs_to_jiffies(vc->vc_cur_blink_ms);
p->con_rotate = initial_rotation;
if (p->con_rotate == -1)
p->con_rotate = info->fbcon_rotate_hint;
if (p->con_rotate == -1)
p->con_rotate = FB_ROTATE_UR;
set_blitting_type(vc, info);
cols = vc->vc_cols;
rows = vc->vc_rows;
new_cols = FBCON_SWAP(ops->rotate, info->var.xres, info->var.yres);
new_rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
new_cols /= vc->vc_font.width;
new_rows /= vc->vc_font.height;
/*
* We must always set the mode. The mode of the previous console
* driver could be in the same resolution but we are using different
* hardware so we have to initialize the hardware.
*
* We need to do it in fbcon_init() to prevent screen corruption.
*/
if (con_is_visible(vc) && vc->vc_mode == KD_TEXT) {
if (info->fbops->fb_set_par && !ops->initialized) {
ret = info->fbops->fb_set_par(info);
if (ret)
printk(KERN_ERR "fbcon_init: detected "
"unhandled fb_set_par error, "
"error code %d\n", ret);
}
ops->initialized = true;
}
ops->graphics = 0;
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION
if ((info->flags & FBINFO_HWACCEL_COPYAREA) &&
!(info->flags & FBINFO_HWACCEL_DISABLED))
p->scrollmode = SCROLL_MOVE;
else /* default to something safe */
p->scrollmode = SCROLL_REDRAW;
#endif
/*
* ++guenther: console.c:vc_allocate() relies on initializing
* vc_{cols,rows}, but we must not set those if we are only
* resizing the console.
*/
if (init) {
vc->vc_cols = new_cols;
vc->vc_rows = new_rows;
} else
vc_resize(vc, new_cols, new_rows);
if (logo)
fbcon_prepare_logo(vc, info, cols, rows, new_cols, new_rows);
if (ops->rotate_font && ops->rotate_font(info, vc)) {
ops->rotate = FB_ROTATE_UR;
set_blitting_type(vc, info);
}
ops->p = &fb_display[fg_console];
}
static void fbcon_free_font(struct fbcon_display *p)
{
if (p->userfont && p->fontdata && (--REFCOUNT(p->fontdata) == 0))
kfree(p->fontdata - FONT_EXTRA_WORDS * sizeof(int));
p->fontdata = NULL;
p->userfont = 0;
}
static void set_vc_hi_font(struct vc_data *vc, bool set);
static void fbcon_release_all(void)
{
struct fb_info *info;
int i, j, mapped;
fbcon_for_each_registered_fb(i) {
mapped = 0;
info = fbcon_registered_fb[i];
for (j = first_fb_vc; j <= last_fb_vc; j++) {
if (con2fb_map[j] == i) {
mapped = 1;
con2fb_map[j] = -1;
}
}
if (mapped)
fbcon_release(info);
}
}
static void fbcon_deinit(struct vc_data *vc)
{
struct fbcon_display *p = &fb_display[vc->vc_num];
struct fb_info *info;
struct fbcon_ops *ops;
int idx;
fbcon_free_font(p);
idx = con2fb_map[vc->vc_num];
if (idx == -1)
goto finished;
info = fbcon_registered_fb[idx];
if (!info)
goto finished;
ops = info->fbcon_par;
if (!ops)
goto finished;
if (con_is_visible(vc))
fbcon_del_cursor_work(info);
ops->initialized = false;
finished:
fbcon_free_font(p);
vc->vc_font.data = NULL;
if (vc->vc_hi_font_mask && vc->vc_screenbuf)
set_vc_hi_font(vc, false);
if (!con_is_bound(&fb_con))
fbcon_release_all();
if (vc->vc_num == logo_shown)
logo_shown = FBCON_LOGO_CANSHOW;
return;
}
/* ====================================================================== */
/* fbcon_XXX routines - interface used by the world
*
* This system is now divided into two levels because of complications
* caused by hardware scrolling. Top level functions:
*
* fbcon_bmove(), fbcon_clear(), fbcon_putc(), fbcon_clear_margins()
*
* handles y values in range [0, scr_height-1] that correspond to real
* screen positions. y_wrap shift means that first line of bitmap may be
* anywhere on this display. These functions convert lineoffsets to
* bitmap offsets and deal with the wrap-around case by splitting blits.
*
* fbcon_bmove_physical_8() -- These functions fast implementations
* fbcon_clear_physical_8() -- of original fbcon_XXX fns.
* fbcon_putc_physical_8() -- (font width != 8) may be added later
*
* WARNING:
*
* At the moment fbcon_putc() cannot blit across vertical wrap boundary
* Implies should only really hardware scroll in rows. Only reason for
* restriction is simplicity & efficiency at the moment.
*/
static void fbcon_clear(struct vc_data *vc, int sy, int sx, int height,
int width)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
struct fbcon_display *p = &fb_display[vc->vc_num];
u_int y_break;
if (fbcon_is_inactive(vc, info))
return;
if (!height || !width)
return;
if (sy < vc->vc_top && vc->vc_top == logo_lines) {
vc->vc_top = 0;
/*
* If the font dimensions are not an integral of the display
* dimensions then the ops->clear below won't end up clearing
* the margins. Call clear_margins here in case the logo
* bitmap stretched into the margin area.
*/
fbcon_clear_margins(vc, 0);
}
/* Split blits that cross physical y_wrap boundary */
y_break = p->vrows - p->yscroll;
if (sy < y_break && sy + height - 1 >= y_break) {
u_int b = y_break - sy;
ops->clear(vc, info, real_y(p, sy), sx, b, width);
ops->clear(vc, info, real_y(p, sy + b), sx, height - b,
width);
} else
ops->clear(vc, info, real_y(p, sy), sx, height, width);
}
static void fbcon_putcs(struct vc_data *vc, const unsigned short *s,
int count, int ypos, int xpos)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_display *p = &fb_display[vc->vc_num];
struct fbcon_ops *ops = info->fbcon_par;
if (!fbcon_is_inactive(vc, info))
ops->putcs(vc, info, s, count, real_y(p, ypos), xpos,
get_color(vc, info, scr_readw(s), 1),
get_color(vc, info, scr_readw(s), 0));
}
static void fbcon_putc(struct vc_data *vc, int c, int ypos, int xpos)
{
unsigned short chr;
scr_writew(c, &chr);
fbcon_putcs(vc, &chr, 1, ypos, xpos);
}
static void fbcon_clear_margins(struct vc_data *vc, int bottom_only)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
if (!fbcon_is_inactive(vc, info))
ops->clear_margins(vc, info, margin_color, bottom_only);
}
static void fbcon_cursor(struct vc_data *vc, int mode)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
int c = scr_readw((u16 *) vc->vc_pos);
ops->cur_blink_jiffies = msecs_to_jiffies(vc->vc_cur_blink_ms);
if (fbcon_is_inactive(vc, info) || vc->vc_deccm != 1)
return;
if (vc->vc_cursor_type & CUR_SW)
fbcon_del_cursor_work(info);
else
fbcon_add_cursor_work(info);
ops->cursor_flash = (mode == CM_ERASE) ? 0 : 1;
if (!ops->cursor)
return;
ops->cursor(vc, info, mode, get_color(vc, info, c, 1),
get_color(vc, info, c, 0));
}
static int scrollback_phys_max = 0;
static int scrollback_max = 0;
static int scrollback_current = 0;
static void fbcon_set_disp(struct fb_info *info, struct fb_var_screeninfo *var,
int unit)
{
struct fbcon_display *p, *t;
struct vc_data **default_mode, *vc;
struct vc_data *svc;
struct fbcon_ops *ops = info->fbcon_par;
int rows, cols;
p = &fb_display[unit];
if (var_to_display(p, var, info))
return;
vc = vc_cons[unit].d;
if (!vc)
return;
default_mode = vc->vc_display_fg;
svc = *default_mode;
t = &fb_display[svc->vc_num];
if (!vc->vc_font.data) {
vc->vc_font.data = (void *)(p->fontdata = t->fontdata);
vc->vc_font.width = (*default_mode)->vc_font.width;
vc->vc_font.height = (*default_mode)->vc_font.height;
vc->vc_font.charcount = (*default_mode)->vc_font.charcount;
p->userfont = t->userfont;
if (p->userfont)
REFCOUNT(p->fontdata)++;
}
var->activate = FB_ACTIVATE_NOW;
info->var.activate = var->activate;
var->yoffset = info->var.yoffset;
var->xoffset = info->var.xoffset;
fb_set_var(info, var);
ops->var = info->var;
vc->vc_can_do_color = (fb_get_color_depth(&info->var, &info->fix)!=1);
vc->vc_complement_mask = vc->vc_can_do_color ? 0x7700 : 0x0800;
if (vc->vc_font.charcount == 256) {
vc->vc_hi_font_mask = 0;
} else {
vc->vc_hi_font_mask = 0x100;
if (vc->vc_can_do_color)
vc->vc_complement_mask <<= 1;
}
if (!*svc->uni_pagedict_loc)
con_set_default_unimap(svc);
if (!*vc->uni_pagedict_loc)
con_copy_unimap(vc, svc);
cols = FBCON_SWAP(ops->rotate, info->var.xres, info->var.yres);
rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
cols /= vc->vc_font.width;
rows /= vc->vc_font.height;
vc_resize(vc, cols, rows);
if (con_is_visible(vc)) {
update_screen(vc);
}
}
static __inline__ void ywrap_up(struct vc_data *vc, int count)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
struct fbcon_display *p = &fb_display[vc->vc_num];
p->yscroll += count;
if (p->yscroll >= p->vrows) /* Deal with wrap */
p->yscroll -= p->vrows;
ops->var.xoffset = 0;
ops->var.yoffset = p->yscroll * vc->vc_font.height;
ops->var.vmode |= FB_VMODE_YWRAP;
ops->update_start(info);
scrollback_max += count;
if (scrollback_max > scrollback_phys_max)
scrollback_max = scrollback_phys_max;
scrollback_current = 0;
}
static __inline__ void ywrap_down(struct vc_data *vc, int count)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
struct fbcon_display *p = &fb_display[vc->vc_num];
p->yscroll -= count;
if (p->yscroll < 0) /* Deal with wrap */
p->yscroll += p->vrows;
ops->var.xoffset = 0;
ops->var.yoffset = p->yscroll * vc->vc_font.height;
ops->var.vmode |= FB_VMODE_YWRAP;
ops->update_start(info);
scrollback_max -= count;
if (scrollback_max < 0)
scrollback_max = 0;
scrollback_current = 0;
}
static __inline__ void ypan_up(struct vc_data *vc, int count)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_display *p = &fb_display[vc->vc_num];
struct fbcon_ops *ops = info->fbcon_par;
p->yscroll += count;
if (p->yscroll > p->vrows - vc->vc_rows) {
ops->bmove(vc, info, p->vrows - vc->vc_rows,
0, 0, 0, vc->vc_rows, vc->vc_cols);
p->yscroll -= p->vrows - vc->vc_rows;
}
ops->var.xoffset = 0;
ops->var.yoffset = p->yscroll * vc->vc_font.height;
ops->var.vmode &= ~FB_VMODE_YWRAP;
ops->update_start(info);
fbcon_clear_margins(vc, 1);
scrollback_max += count;
if (scrollback_max > scrollback_phys_max)
scrollback_max = scrollback_phys_max;
scrollback_current = 0;
}
static __inline__ void ypan_up_redraw(struct vc_data *vc, int t, int count)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
struct fbcon_display *p = &fb_display[vc->vc_num];
p->yscroll += count;
if (p->yscroll > p->vrows - vc->vc_rows) {
p->yscroll -= p->vrows - vc->vc_rows;
fbcon_redraw_move(vc, p, t + count, vc->vc_rows - count, t);
}
ops->var.xoffset = 0;
ops->var.yoffset = p->yscroll * vc->vc_font.height;
ops->var.vmode &= ~FB_VMODE_YWRAP;
ops->update_start(info);
fbcon_clear_margins(vc, 1);
scrollback_max += count;
if (scrollback_max > scrollback_phys_max)
scrollback_max = scrollback_phys_max;
scrollback_current = 0;
}
static __inline__ void ypan_down(struct vc_data *vc, int count)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_display *p = &fb_display[vc->vc_num];
struct fbcon_ops *ops = info->fbcon_par;
p->yscroll -= count;
if (p->yscroll < 0) {
ops->bmove(vc, info, 0, 0, p->vrows - vc->vc_rows,
0, vc->vc_rows, vc->vc_cols);
p->yscroll += p->vrows - vc->vc_rows;
}
ops->var.xoffset = 0;
ops->var.yoffset = p->yscroll * vc->vc_font.height;
ops->var.vmode &= ~FB_VMODE_YWRAP;
ops->update_start(info);
fbcon_clear_margins(vc, 1);
scrollback_max -= count;
if (scrollback_max < 0)
scrollback_max = 0;
scrollback_current = 0;
}
static __inline__ void ypan_down_redraw(struct vc_data *vc, int t, int count)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
struct fbcon_display *p = &fb_display[vc->vc_num];
p->yscroll -= count;
if (p->yscroll < 0) {
p->yscroll += p->vrows - vc->vc_rows;
fbcon_redraw_move(vc, p, t, vc->vc_rows - count, t + count);
}
ops->var.xoffset = 0;
ops->var.yoffset = p->yscroll * vc->vc_font.height;
ops->var.vmode &= ~FB_VMODE_YWRAP;
ops->update_start(info);
fbcon_clear_margins(vc, 1);
scrollback_max -= count;
if (scrollback_max < 0)
scrollback_max = 0;
scrollback_current = 0;
}
static void fbcon_redraw_move(struct vc_data *vc, struct fbcon_display *p,
int line, int count, int dy)
{
unsigned short *s = (unsigned short *)
(vc->vc_origin + vc->vc_size_row * line);
while (count--) {
unsigned short *start = s;
unsigned short *le = advance_row(s, 1);
unsigned short c;
int x = 0;
unsigned short attr = 1;
do {
c = scr_readw(s);
if (attr != (c & 0xff00)) {
attr = c & 0xff00;
if (s > start) {
fbcon_putcs(vc, start, s - start,
dy, x);
x += s - start;
start = s;
}
}
console_conditional_schedule();
s++;
} while (s < le);
if (s > start)
fbcon_putcs(vc, start, s - start, dy, x);
console_conditional_schedule();
dy++;
}
}
static void fbcon_redraw_blit(struct vc_data *vc, struct fb_info *info,
struct fbcon_display *p, int line, int count, int ycount)
{
int offset = ycount * vc->vc_cols;
unsigned short *d = (unsigned short *)
(vc->vc_origin + vc->vc_size_row * line);
unsigned short *s = d + offset;
struct fbcon_ops *ops = info->fbcon_par;
while (count--) {
unsigned short *start = s;
unsigned short *le = advance_row(s, 1);
unsigned short c;
int x = 0;
do {
c = scr_readw(s);
if (c == scr_readw(d)) {
if (s > start) {
ops->bmove(vc, info, line + ycount, x,
line, x, 1, s-start);
x += s - start + 1;
start = s + 1;
} else {
x++;
start++;
}
}
scr_writew(c, d);
console_conditional_schedule();
s++;
d++;
} while (s < le);
if (s > start)
ops->bmove(vc, info, line + ycount, x, line, x, 1,
s-start);
console_conditional_schedule();
if (ycount > 0)
line++;
else {
line--;
/* NOTE: We subtract two lines from these pointers */
s -= vc->vc_size_row;
d -= vc->vc_size_row;
}
}
}
static void fbcon_redraw(struct vc_data *vc, int line, int count, int offset)
{
unsigned short *d = (unsigned short *)
(vc->vc_origin + vc->vc_size_row * line);
unsigned short *s = d + offset;
while (count--) {
unsigned short *start = s;
unsigned short *le = advance_row(s, 1);
unsigned short c;
int x = 0;
unsigned short attr = 1;
do {
c = scr_readw(s);
if (attr != (c & 0xff00)) {
attr = c & 0xff00;
if (s > start) {
fbcon_putcs(vc, start, s - start,
line, x);
x += s - start;
start = s;
}
}
if (c == scr_readw(d)) {
if (s > start) {
fbcon_putcs(vc, start, s - start,
line, x);
x += s - start + 1;
start = s + 1;
} else {
x++;
start++;
}
}
scr_writew(c, d);
console_conditional_schedule();
s++;
d++;
} while (s < le);
if (s > start)
fbcon_putcs(vc, start, s - start, line, x);
console_conditional_schedule();
if (offset > 0)
line++;
else {
line--;
/* NOTE: We subtract two lines from these pointers */
s -= vc->vc_size_row;
d -= vc->vc_size_row;
}
}
}
static void fbcon_bmove_rec(struct vc_data *vc, struct fbcon_display *p, int sy, int sx,
int dy, int dx, int height, int width, u_int y_break)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
u_int b;
if (sy < y_break && sy + height > y_break) {
b = y_break - sy;
if (dy < sy) { /* Avoid trashing self */
fbcon_bmove_rec(vc, p, sy, sx, dy, dx, b, width,
y_break);
fbcon_bmove_rec(vc, p, sy + b, sx, dy + b, dx,
height - b, width, y_break);
} else {
fbcon_bmove_rec(vc, p, sy + b, sx, dy + b, dx,
height - b, width, y_break);
fbcon_bmove_rec(vc, p, sy, sx, dy, dx, b, width,
y_break);
}
return;
}
if (dy < y_break && dy + height > y_break) {
b = y_break - dy;
if (dy < sy) { /* Avoid trashing self */
fbcon_bmove_rec(vc, p, sy, sx, dy, dx, b, width,
y_break);
fbcon_bmove_rec(vc, p, sy + b, sx, dy + b, dx,
height - b, width, y_break);
} else {
fbcon_bmove_rec(vc, p, sy + b, sx, dy + b, dx,
height - b, width, y_break);
fbcon_bmove_rec(vc, p, sy, sx, dy, dx, b, width,
y_break);
}
return;
}
ops->bmove(vc, info, real_y(p, sy), sx, real_y(p, dy), dx,
height, width);
}
static void fbcon_bmove(struct vc_data *vc, int sy, int sx, int dy, int dx,
int height, int width)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_display *p = &fb_display[vc->vc_num];
if (fbcon_is_inactive(vc, info))
return;
if (!width || !height)
return;
/* Split blits that cross physical y_wrap case.
* Pathological case involves 4 blits, better to use recursive
* code rather than unrolled case
*
* Recursive invocations don't need to erase the cursor over and
* over again, so we use fbcon_bmove_rec()
*/
fbcon_bmove_rec(vc, p, sy, sx, dy, dx, height, width,
p->vrows - p->yscroll);
}
static bool fbcon_scroll(struct vc_data *vc, unsigned int t, unsigned int b,
enum con_scroll dir, unsigned int count)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_display *p = &fb_display[vc->vc_num];
int scroll_partial = info->flags & FBINFO_PARTIAL_PAN_OK;
if (fbcon_is_inactive(vc, info))
return true;
fbcon_cursor(vc, CM_ERASE);
/*
* ++Geert: Only use ywrap/ypan if the console is in text mode
* ++Andrew: Only use ypan on hardware text mode when scrolling the
* whole screen (prevents flicker).
*/
switch (dir) {
case SM_UP:
if (count > vc->vc_rows) /* Maximum realistic size */
count = vc->vc_rows;
switch (fb_scrollmode(p)) {
case SCROLL_MOVE:
fbcon_redraw_blit(vc, info, p, t, b - t - count,
count);
fbcon_clear(vc, b - count, 0, count, vc->vc_cols);
scr_memsetw((unsigned short *) (vc->vc_origin +
vc->vc_size_row *
(b - count)),
vc->vc_video_erase_char,
vc->vc_size_row * count);
return true;
case SCROLL_WRAP_MOVE:
if (b - t - count > 3 * vc->vc_rows >> 2) {
if (t > 0)
fbcon_bmove(vc, 0, 0, count, 0, t,
vc->vc_cols);
ywrap_up(vc, count);
if (vc->vc_rows - b > 0)
fbcon_bmove(vc, b - count, 0, b, 0,
vc->vc_rows - b,
vc->vc_cols);
} else if (info->flags & FBINFO_READS_FAST)
fbcon_bmove(vc, t + count, 0, t, 0,
b - t - count, vc->vc_cols);
else
goto redraw_up;
fbcon_clear(vc, b - count, 0, count, vc->vc_cols);
break;
case SCROLL_PAN_REDRAW:
if ((p->yscroll + count <=
2 * (p->vrows - vc->vc_rows))
&& ((!scroll_partial && (b - t == vc->vc_rows))
|| (scroll_partial
&& (b - t - count >
3 * vc->vc_rows >> 2)))) {
if (t > 0)
fbcon_redraw_move(vc, p, 0, t, count);
ypan_up_redraw(vc, t, count);
if (vc->vc_rows - b > 0)
fbcon_redraw_move(vc, p, b,
vc->vc_rows - b, b);
} else
fbcon_redraw_move(vc, p, t + count, b - t - count, t);
fbcon_clear(vc, b - count, 0, count, vc->vc_cols);
break;
case SCROLL_PAN_MOVE:
if ((p->yscroll + count <=
2 * (p->vrows - vc->vc_rows))
&& ((!scroll_partial && (b - t == vc->vc_rows))
|| (scroll_partial
&& (b - t - count >
3 * vc->vc_rows >> 2)))) {
if (t > 0)
fbcon_bmove(vc, 0, 0, count, 0, t,
vc->vc_cols);
ypan_up(vc, count);
if (vc->vc_rows - b > 0)
fbcon_bmove(vc, b - count, 0, b, 0,
vc->vc_rows - b,
vc->vc_cols);
} else if (info->flags & FBINFO_READS_FAST)
fbcon_bmove(vc, t + count, 0, t, 0,
b - t - count, vc->vc_cols);
else
goto redraw_up;
fbcon_clear(vc, b - count, 0, count, vc->vc_cols);
break;
case SCROLL_REDRAW:
redraw_up:
fbcon_redraw(vc, t, b - t - count,
count * vc->vc_cols);
fbcon_clear(vc, b - count, 0, count, vc->vc_cols);
scr_memsetw((unsigned short *) (vc->vc_origin +
vc->vc_size_row *
(b - count)),
vc->vc_video_erase_char,
vc->vc_size_row * count);
return true;
}
break;
case SM_DOWN:
if (count > vc->vc_rows) /* Maximum realistic size */
count = vc->vc_rows;
switch (fb_scrollmode(p)) {
case SCROLL_MOVE:
fbcon_redraw_blit(vc, info, p, b - 1, b - t - count,
-count);
fbcon_clear(vc, t, 0, count, vc->vc_cols);
scr_memsetw((unsigned short *) (vc->vc_origin +
vc->vc_size_row *
t),
vc->vc_video_erase_char,
vc->vc_size_row * count);
return true;
case SCROLL_WRAP_MOVE:
if (b - t - count > 3 * vc->vc_rows >> 2) {
if (vc->vc_rows - b > 0)
fbcon_bmove(vc, b, 0, b - count, 0,
vc->vc_rows - b,
vc->vc_cols);
ywrap_down(vc, count);
if (t > 0)
fbcon_bmove(vc, count, 0, 0, 0, t,
vc->vc_cols);
} else if (info->flags & FBINFO_READS_FAST)
fbcon_bmove(vc, t, 0, t + count, 0,
b - t - count, vc->vc_cols);
else
goto redraw_down;
fbcon_clear(vc, t, 0, count, vc->vc_cols);
break;
case SCROLL_PAN_MOVE:
if ((count - p->yscroll <= p->vrows - vc->vc_rows)
&& ((!scroll_partial && (b - t == vc->vc_rows))
|| (scroll_partial
&& (b - t - count >
3 * vc->vc_rows >> 2)))) {
if (vc->vc_rows - b > 0)
fbcon_bmove(vc, b, 0, b - count, 0,
vc->vc_rows - b,
vc->vc_cols);
ypan_down(vc, count);
if (t > 0)
fbcon_bmove(vc, count, 0, 0, 0, t,
vc->vc_cols);
} else if (info->flags & FBINFO_READS_FAST)
fbcon_bmove(vc, t, 0, t + count, 0,
b - t - count, vc->vc_cols);
else
goto redraw_down;
fbcon_clear(vc, t, 0, count, vc->vc_cols);
break;
case SCROLL_PAN_REDRAW:
if ((count - p->yscroll <= p->vrows - vc->vc_rows)
&& ((!scroll_partial && (b - t == vc->vc_rows))
|| (scroll_partial
&& (b - t - count >
3 * vc->vc_rows >> 2)))) {
if (vc->vc_rows - b > 0)
fbcon_redraw_move(vc, p, b, vc->vc_rows - b,
b - count);
ypan_down_redraw(vc, t, count);
if (t > 0)
fbcon_redraw_move(vc, p, count, t, 0);
} else
fbcon_redraw_move(vc, p, t, b - t - count, t + count);
fbcon_clear(vc, t, 0, count, vc->vc_cols);
break;
case SCROLL_REDRAW:
redraw_down:
fbcon_redraw(vc, b - 1, b - t - count,
-count * vc->vc_cols);
fbcon_clear(vc, t, 0, count, vc->vc_cols);
scr_memsetw((unsigned short *) (vc->vc_origin +
vc->vc_size_row *
t),
vc->vc_video_erase_char,
vc->vc_size_row * count);
return true;
}
}
return false;
}
static void updatescrollmode_accel(struct fbcon_display *p,
struct fb_info *info,
struct vc_data *vc)
{
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION
struct fbcon_ops *ops = info->fbcon_par;
int cap = info->flags;
u16 t = 0;
int ypan = FBCON_SWAP(ops->rotate, info->fix.ypanstep,
info->fix.xpanstep);
int ywrap = FBCON_SWAP(ops->rotate, info->fix.ywrapstep, t);
int yres = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
int vyres = FBCON_SWAP(ops->rotate, info->var.yres_virtual,
info->var.xres_virtual);
int good_pan = (cap & FBINFO_HWACCEL_YPAN) &&
divides(ypan, vc->vc_font.height) && vyres > yres;
int good_wrap = (cap & FBINFO_HWACCEL_YWRAP) &&
divides(ywrap, vc->vc_font.height) &&
divides(vc->vc_font.height, vyres) &&
divides(vc->vc_font.height, yres);
int reading_fast = cap & FBINFO_READS_FAST;
int fast_copyarea = (cap & FBINFO_HWACCEL_COPYAREA) &&
!(cap & FBINFO_HWACCEL_DISABLED);
int fast_imageblit = (cap & FBINFO_HWACCEL_IMAGEBLIT) &&
!(cap & FBINFO_HWACCEL_DISABLED);
if (good_wrap || good_pan) {
if (reading_fast || fast_copyarea)
p->scrollmode = good_wrap ?
SCROLL_WRAP_MOVE : SCROLL_PAN_MOVE;
else
p->scrollmode = good_wrap ? SCROLL_REDRAW :
SCROLL_PAN_REDRAW;
} else {
if (reading_fast || (fast_copyarea && !fast_imageblit))
p->scrollmode = SCROLL_MOVE;
else
p->scrollmode = SCROLL_REDRAW;
}
#endif
}
static void updatescrollmode(struct fbcon_display *p,
struct fb_info *info,
struct vc_data *vc)
{
struct fbcon_ops *ops = info->fbcon_par;
int fh = vc->vc_font.height;
int yres = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
int vyres = FBCON_SWAP(ops->rotate, info->var.yres_virtual,
info->var.xres_virtual);
p->vrows = vyres/fh;
if (yres > (fh * (vc->vc_rows + 1)))
p->vrows -= (yres - (fh * vc->vc_rows)) / fh;
if ((yres % fh) && (vyres % fh < yres % fh))
p->vrows--;
/* update scrollmode in case hardware acceleration is used */
updatescrollmode_accel(p, info, vc);
}
#define PITCH(w) (((w) + 7) >> 3)
#define CALC_FONTSZ(h, p, c) ((h) * (p) * (c)) /* size = height * pitch * charcount */
static int fbcon_resize(struct vc_data *vc, unsigned int width,
unsigned int height, unsigned int user)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
struct fbcon_display *p = &fb_display[vc->vc_num];
struct fb_var_screeninfo var = info->var;
int x_diff, y_diff, virt_w, virt_h, virt_fw, virt_fh;
if (p->userfont && FNTSIZE(vc->vc_font.data)) {
int size;
int pitch = PITCH(vc->vc_font.width);
/*
* If user font, ensure that a possible change to user font
* height or width will not allow a font data out-of-bounds access.
* NOTE: must use original charcount in calculation as font
* charcount can change and cannot be used to determine the
* font data allocated size.
*/
if (pitch <= 0)
return -EINVAL;
size = CALC_FONTSZ(vc->vc_font.height, pitch, vc->vc_font.charcount);
if (size > FNTSIZE(vc->vc_font.data))
return -EINVAL;
}
virt_w = FBCON_SWAP(ops->rotate, width, height);
virt_h = FBCON_SWAP(ops->rotate, height, width);
virt_fw = FBCON_SWAP(ops->rotate, vc->vc_font.width,
vc->vc_font.height);
virt_fh = FBCON_SWAP(ops->rotate, vc->vc_font.height,
vc->vc_font.width);
var.xres = virt_w * virt_fw;
var.yres = virt_h * virt_fh;
x_diff = info->var.xres - var.xres;
y_diff = info->var.yres - var.yres;
if (x_diff < 0 || x_diff > virt_fw ||
y_diff < 0 || y_diff > virt_fh) {
const struct fb_videomode *mode;
pr_debug("attempting resize %ix%i\n", var.xres, var.yres);
mode = fb_find_best_mode(&var, &info->modelist);
if (mode == NULL)
return -EINVAL;
display_to_var(&var, p);
fb_videomode_to_var(&var, mode);
if (virt_w > var.xres/virt_fw || virt_h > var.yres/virt_fh)
return -EINVAL;
pr_debug("resize now %ix%i\n", var.xres, var.yres);
if (con_is_visible(vc) && vc->vc_mode == KD_TEXT) {
var.activate = FB_ACTIVATE_NOW |
FB_ACTIVATE_FORCE;
fb_set_var(info, &var);
}
var_to_display(p, &info->var, info);
ops->var = info->var;
}
updatescrollmode(p, info, vc);
return 0;
}
static int fbcon_switch(struct vc_data *vc)
{
struct fb_info *info, *old_info = NULL;
struct fbcon_ops *ops;
struct fbcon_display *p = &fb_display[vc->vc_num];
struct fb_var_screeninfo var;
int i, ret, prev_console;
info = fbcon_info_from_console(vc->vc_num);
ops = info->fbcon_par;
if (logo_shown >= 0) {
struct vc_data *conp2 = vc_cons[logo_shown].d;
if (conp2->vc_top == logo_lines
&& conp2->vc_bottom == conp2->vc_rows)
conp2->vc_top = 0;
logo_shown = FBCON_LOGO_CANSHOW;
}
prev_console = ops->currcon;
if (prev_console != -1)
old_info = fbcon_info_from_console(prev_console);
/*
* FIXME: If we have multiple fbdev's loaded, we need to
* update all info->currcon. Perhaps, we can place this
* in a centralized structure, but this might break some
* drivers.
*
* info->currcon = vc->vc_num;
*/
fbcon_for_each_registered_fb(i) {
if (fbcon_registered_fb[i]->fbcon_par) {
struct fbcon_ops *o = fbcon_registered_fb[i]->fbcon_par;
o->currcon = vc->vc_num;
}
}
memset(&var, 0, sizeof(struct fb_var_screeninfo));
display_to_var(&var, p);
var.activate = FB_ACTIVATE_NOW;
/*
* make sure we don't unnecessarily trip the memcmp()
* in fb_set_var()
*/
info->var.activate = var.activate;
var.vmode |= info->var.vmode & ~FB_VMODE_MASK;
fb_set_var(info, &var);
ops->var = info->var;
if (old_info != NULL && (old_info != info ||
info->flags & FBINFO_MISC_ALWAYS_SETPAR)) {
if (info->fbops->fb_set_par) {
ret = info->fbops->fb_set_par(info);
if (ret)
printk(KERN_ERR "fbcon_switch: detected "
"unhandled fb_set_par error, "
"error code %d\n", ret);
}
if (old_info != info)
fbcon_del_cursor_work(old_info);
}
if (fbcon_is_inactive(vc, info) ||
ops->blank_state != FB_BLANK_UNBLANK)
fbcon_del_cursor_work(info);
else
fbcon_add_cursor_work(info);
set_blitting_type(vc, info);
ops->cursor_reset = 1;
if (ops->rotate_font && ops->rotate_font(info, vc)) {
ops->rotate = FB_ROTATE_UR;
set_blitting_type(vc, info);
}
vc->vc_can_do_color = (fb_get_color_depth(&info->var, &info->fix)!=1);
vc->vc_complement_mask = vc->vc_can_do_color ? 0x7700 : 0x0800;
if (vc->vc_font.charcount > 256)
vc->vc_complement_mask <<= 1;
updatescrollmode(p, info, vc);
switch (fb_scrollmode(p)) {
case SCROLL_WRAP_MOVE:
scrollback_phys_max = p->vrows - vc->vc_rows;
break;
case SCROLL_PAN_MOVE:
case SCROLL_PAN_REDRAW:
scrollback_phys_max = p->vrows - 2 * vc->vc_rows;
if (scrollback_phys_max < 0)
scrollback_phys_max = 0;
break;
default:
scrollback_phys_max = 0;
break;
}
scrollback_max = 0;
scrollback_current = 0;
if (!fbcon_is_inactive(vc, info)) {
ops->var.xoffset = ops->var.yoffset = p->yscroll = 0;
ops->update_start(info);
}
fbcon_set_palette(vc, color_table);
fbcon_clear_margins(vc, 0);
if (logo_shown == FBCON_LOGO_DRAW) {
logo_shown = fg_console;
fb_show_logo(info, ops->rotate);
update_region(vc,
vc->vc_origin + vc->vc_size_row * vc->vc_top,
vc->vc_size_row * (vc->vc_bottom -
vc->vc_top) / 2);
return 0;
}
return 1;
}
static void fbcon_generic_blank(struct vc_data *vc, struct fb_info *info,
int blank)
{
if (blank) {
unsigned short charmask = vc->vc_hi_font_mask ?
0x1ff : 0xff;
unsigned short oldc;
oldc = vc->vc_video_erase_char;
vc->vc_video_erase_char &= charmask;
fbcon_clear(vc, 0, 0, vc->vc_rows, vc->vc_cols);
vc->vc_video_erase_char = oldc;
}
}
static int fbcon_blank(struct vc_data *vc, int blank, int mode_switch)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
if (mode_switch) {
struct fb_var_screeninfo var = info->var;
ops->graphics = 1;
if (!blank) {
var.activate = FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE |
FB_ACTIVATE_KD_TEXT;
fb_set_var(info, &var);
ops->graphics = 0;
ops->var = info->var;
}
}
if (!fbcon_is_inactive(vc, info)) {
if (ops->blank_state != blank) {
ops->blank_state = blank;
fbcon_cursor(vc, blank ? CM_ERASE : CM_DRAW);
ops->cursor_flash = (!blank);
if (fb_blank(info, blank))
fbcon_generic_blank(vc, info, blank);
}
if (!blank)
update_screen(vc);
}
if (mode_switch || fbcon_is_inactive(vc, info) ||
ops->blank_state != FB_BLANK_UNBLANK)
fbcon_del_cursor_work(info);
else
fbcon_add_cursor_work(info);
return 0;
}
static int fbcon_debug_enter(struct vc_data *vc)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
ops->save_graphics = ops->graphics;
ops->graphics = 0;
if (info->fbops->fb_debug_enter)
info->fbops->fb_debug_enter(info);
fbcon_set_palette(vc, color_table);
return 0;
}
static int fbcon_debug_leave(struct vc_data *vc)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
ops->graphics = ops->save_graphics;
if (info->fbops->fb_debug_leave)
info->fbops->fb_debug_leave(info);
return 0;
}
static int fbcon_get_font(struct vc_data *vc, struct console_font *font, unsigned int vpitch)
{
u8 *fontdata = vc->vc_font.data;
u8 *data = font->data;
int i, j;
font->width = vc->vc_font.width;
font->height = vc->vc_font.height;
if (font->height > vpitch)
return -ENOSPC;
font->charcount = vc->vc_hi_font_mask ? 512 : 256;
if (!font->data)
return 0;
if (font->width <= 8) {
j = vc->vc_font.height;
if (font->charcount * j > FNTSIZE(fontdata))
return -EINVAL;
for (i = 0; i < font->charcount; i++) {
memcpy(data, fontdata, j);
memset(data + j, 0, vpitch - j);
data += vpitch;
fontdata += j;
}
} else if (font->width <= 16) {
j = vc->vc_font.height * 2;
if (font->charcount * j > FNTSIZE(fontdata))
return -EINVAL;
for (i = 0; i < font->charcount; i++) {
memcpy(data, fontdata, j);
memset(data + j, 0, 2*vpitch - j);
data += 2*vpitch;
fontdata += j;
}
} else if (font->width <= 24) {
if (font->charcount * (vc->vc_font.height * sizeof(u32)) > FNTSIZE(fontdata))
return -EINVAL;
for (i = 0; i < font->charcount; i++) {
for (j = 0; j < vc->vc_font.height; j++) {
*data++ = fontdata[0];
*data++ = fontdata[1];
*data++ = fontdata[2];
fontdata += sizeof(u32);
}
memset(data, 0, 3 * (vpitch - j));
data += 3 * (vpitch - j);
}
} else {
j = vc->vc_font.height * 4;
if (font->charcount * j > FNTSIZE(fontdata))
return -EINVAL;
for (i = 0; i < font->charcount; i++) {
memcpy(data, fontdata, j);
memset(data + j, 0, 4 * vpitch - j);
data += 4 * vpitch;
fontdata += j;
}
}
return 0;
}
/* set/clear vc_hi_font_mask and update vc attrs accordingly */
static void set_vc_hi_font(struct vc_data *vc, bool set)
{
if (!set) {
vc->vc_hi_font_mask = 0;
if (vc->vc_can_do_color) {
vc->vc_complement_mask >>= 1;
vc->vc_s_complement_mask >>= 1;
}
/* ++Edmund: reorder the attribute bits */
if (vc->vc_can_do_color) {
unsigned short *cp =
(unsigned short *) vc->vc_origin;
int count = vc->vc_screenbuf_size / 2;
unsigned short c;
for (; count > 0; count--, cp++) {
c = scr_readw(cp);
scr_writew(((c & 0xfe00) >> 1) |
(c & 0xff), cp);
}
c = vc->vc_video_erase_char;
vc->vc_video_erase_char =
((c & 0xfe00) >> 1) | (c & 0xff);
vc->vc_attr >>= 1;
}
} else {
vc->vc_hi_font_mask = 0x100;
if (vc->vc_can_do_color) {
vc->vc_complement_mask <<= 1;
vc->vc_s_complement_mask <<= 1;
}
/* ++Edmund: reorder the attribute bits */
{
unsigned short *cp =
(unsigned short *) vc->vc_origin;
int count = vc->vc_screenbuf_size / 2;
unsigned short c;
for (; count > 0; count--, cp++) {
unsigned short newc;
c = scr_readw(cp);
if (vc->vc_can_do_color)
newc =
((c & 0xff00) << 1) | (c &
0xff);
else
newc = c & ~0x100;
scr_writew(newc, cp);
}
c = vc->vc_video_erase_char;
if (vc->vc_can_do_color) {
vc->vc_video_erase_char =
((c & 0xff00) << 1) | (c & 0xff);
vc->vc_attr <<= 1;
} else
vc->vc_video_erase_char = c & ~0x100;
}
}
}
static int fbcon_do_set_font(struct vc_data *vc, int w, int h, int charcount,
const u8 * data, int userfont)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
struct fbcon_ops *ops = info->fbcon_par;
struct fbcon_display *p = &fb_display[vc->vc_num];
int resize, ret, old_userfont, old_width, old_height, old_charcount;
char *old_data = NULL;
resize = (w != vc->vc_font.width) || (h != vc->vc_font.height);
if (p->userfont)
old_data = vc->vc_font.data;
vc->vc_font.data = (void *)(p->fontdata = data);
old_userfont = p->userfont;
if ((p->userfont = userfont))
REFCOUNT(data)++;
old_width = vc->vc_font.width;
old_height = vc->vc_font.height;
old_charcount = vc->vc_font.charcount;
vc->vc_font.width = w;
vc->vc_font.height = h;
vc->vc_font.charcount = charcount;
if (vc->vc_hi_font_mask && charcount == 256)
set_vc_hi_font(vc, false);
else if (!vc->vc_hi_font_mask && charcount == 512)
set_vc_hi_font(vc, true);
if (resize) {
int cols, rows;
cols = FBCON_SWAP(ops->rotate, info->var.xres, info->var.yres);
rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
cols /= w;
rows /= h;
ret = vc_resize(vc, cols, rows);
if (ret)
goto err_out;
} else if (con_is_visible(vc)
&& vc->vc_mode == KD_TEXT) {
fbcon_clear_margins(vc, 0);
update_screen(vc);
}
if (old_data && (--REFCOUNT(old_data) == 0))
kfree(old_data - FONT_EXTRA_WORDS * sizeof(int));
return 0;
err_out:
p->fontdata = old_data;
vc->vc_font.data = (void *)old_data;
if (userfont) {
p->userfont = old_userfont;
if (--REFCOUNT(data) == 0)
kfree(data - FONT_EXTRA_WORDS * sizeof(int));
}
vc->vc_font.width = old_width;
vc->vc_font.height = old_height;
vc->vc_font.charcount = old_charcount;
return ret;
}
/*
* User asked to set font; we are guaranteed that charcount does not exceed 512
* but lets not assume that, since charcount of 512 is small for unicode support.
*/
static int fbcon_set_font(struct vc_data *vc, struct console_font *font,
unsigned int vpitch, unsigned int flags)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
unsigned charcount = font->charcount;
int w = font->width;
int h = font->height;
int size;
int i, csum;
u8 *new_data, *data = font->data;
int pitch = PITCH(font->width);
/* Is there a reason why fbconsole couldn't handle any charcount >256?
* If not this check should be changed to charcount < 256 */
if (charcount != 256 && charcount != 512)
return -EINVAL;
/* font bigger than screen resolution ? */
if (w > FBCON_SWAP(info->var.rotate, info->var.xres, info->var.yres) ||
h > FBCON_SWAP(info->var.rotate, info->var.yres, info->var.xres))
return -EINVAL;
if (font->width > 32 || font->height > 32)
return -EINVAL;
/* Make sure drawing engine can handle the font */
if (!(info->pixmap.blit_x & BIT(font->width - 1)) ||
!(info->pixmap.blit_y & BIT(font->height - 1)))
return -EINVAL;
/* Make sure driver can handle the font length */
if (fbcon_invalid_charcount(info, charcount))
return -EINVAL;
size = CALC_FONTSZ(h, pitch, charcount);
new_data = kmalloc(FONT_EXTRA_WORDS * sizeof(int) + size, GFP_USER);
if (!new_data)
return -ENOMEM;
memset(new_data, 0, FONT_EXTRA_WORDS * sizeof(int));
new_data += FONT_EXTRA_WORDS * sizeof(int);
FNTSIZE(new_data) = size;
REFCOUNT(new_data) = 0; /* usage counter */
for (i=0; i< charcount; i++) {
memcpy(new_data + i*h*pitch, data + i*vpitch*pitch, h*pitch);
}
/* Since linux has a nice crc32 function use it for counting font
* checksums. */
csum = crc32(0, new_data, size);
FNTSUM(new_data) = csum;
/* Check if the same font is on some other console already */
for (i = first_fb_vc; i <= last_fb_vc; i++) {
struct vc_data *tmp = vc_cons[i].d;
if (fb_display[i].userfont &&
fb_display[i].fontdata &&
FNTSUM(fb_display[i].fontdata) == csum &&
FNTSIZE(fb_display[i].fontdata) == size &&
tmp->vc_font.width == w &&
!memcmp(fb_display[i].fontdata, new_data, size)) {
kfree(new_data - FONT_EXTRA_WORDS * sizeof(int));
new_data = (u8 *)fb_display[i].fontdata;
break;
}
}
return fbcon_do_set_font(vc, font->width, font->height, charcount, new_data, 1);
}
static int fbcon_set_def_font(struct vc_data *vc, struct console_font *font, char *name)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
const struct font_desc *f;
if (!name)
f = get_default_font(info->var.xres, info->var.yres,
info->pixmap.blit_x, info->pixmap.blit_y);
else if (!(f = find_font(name)))
return -ENOENT;
font->width = f->width;
font->height = f->height;
return fbcon_do_set_font(vc, f->width, f->height, f->charcount, f->data, 0);
}
static u16 palette_red[16];
static u16 palette_green[16];
static u16 palette_blue[16];
static struct fb_cmap palette_cmap = {
0, 16, palette_red, palette_green, palette_blue, NULL
};
static void fbcon_set_palette(struct vc_data *vc, const unsigned char *table)
{
struct fb_info *info = fbcon_info_from_console(vc->vc_num);
int i, j, k, depth;
u8 val;
if (fbcon_is_inactive(vc, info))
return;
if (!con_is_visible(vc))
return;
depth = fb_get_color_depth(&info->var, &info->fix);
if (depth > 3) {
for (i = j = 0; i < 16; i++) {
k = table[i];
val = vc->vc_palette[j++];
palette_red[k] = (val << 8) | val;
val = vc->vc_palette[j++];
palette_green[k] = (val << 8) | val;
val = vc->vc_palette[j++];
palette_blue[k] = (val << 8) | val;
}
palette_cmap.len = 16;
palette_cmap.start = 0;
/*
* If framebuffer is capable of less than 16 colors,
* use default palette of fbcon.
*/
} else
fb_copy_cmap(fb_default_cmap(1 << depth), &palette_cmap);
fb_set_cmap(&palette_cmap, info);
}
static u16 *fbcon_screen_pos(const struct vc_data *vc, int offset)
{
return (u16 *) (vc->vc_origin + offset);
}
static unsigned long fbcon_getxy(struct vc_data *vc, unsigned long pos,
int *px, int *py)
{
unsigned long ret;
int x, y;
if (pos >= vc->vc_origin && pos < vc->vc_scr_end) {
unsigned long offset = (pos - vc->vc_origin) / 2;
x = offset % vc->vc_cols;
y = offset / vc->vc_cols;
ret = pos + (vc->vc_cols - x) * 2;
} else {
/* Should not happen */
x = y = 0;
ret = vc->vc_origin;
}
if (px)
*px = x;
if (py)
*py = y;
return ret;
}
/* As we might be inside of softback, we may work with non-contiguous buffer,
that's why we have to use a separate routine. */
static void fbcon_invert_region(struct vc_data *vc, u16 * p, int cnt)
{
while (cnt--) {
u16 a = scr_readw(p);
if (!vc->vc_can_do_color)
a ^= 0x0800;
else if (vc->vc_hi_font_mask == 0x100)
a = ((a) & 0x11ff) | (((a) & 0xe000) >> 4) |
(((a) & 0x0e00) << 4);
else
a = ((a) & 0x88ff) | (((a) & 0x7000) >> 4) |
(((a) & 0x0700) << 4);
scr_writew(a, p++);
}
}
void fbcon_suspended(struct fb_info *info)
{
struct vc_data *vc = NULL;
struct fbcon_ops *ops = info->fbcon_par;
if (!ops || ops->currcon < 0)
return;
vc = vc_cons[ops->currcon].d;
/* Clear cursor, restore saved data */
fbcon_cursor(vc, CM_ERASE);
}
void fbcon_resumed(struct fb_info *info)
{
struct vc_data *vc;
struct fbcon_ops *ops = info->fbcon_par;
if (!ops || ops->currcon < 0)
return;
vc = vc_cons[ops->currcon].d;
update_screen(vc);
}
static void fbcon_modechanged(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
struct vc_data *vc;
struct fbcon_display *p;
int rows, cols;
if (!ops || ops->currcon < 0)
return;
vc = vc_cons[ops->currcon].d;
if (vc->vc_mode != KD_TEXT ||
fbcon_info_from_console(ops->currcon) != info)
return;
p = &fb_display[vc->vc_num];
set_blitting_type(vc, info);
if (con_is_visible(vc)) {
var_to_display(p, &info->var, info);
cols = FBCON_SWAP(ops->rotate, info->var.xres, info->var.yres);
rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
cols /= vc->vc_font.width;
rows /= vc->vc_font.height;
vc_resize(vc, cols, rows);
updatescrollmode(p, info, vc);
scrollback_max = 0;
scrollback_current = 0;
if (!fbcon_is_inactive(vc, info)) {
ops->var.xoffset = ops->var.yoffset = p->yscroll = 0;
ops->update_start(info);
}
fbcon_set_palette(vc, color_table);
update_screen(vc);
}
}
static void fbcon_set_all_vcs(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
struct vc_data *vc;
struct fbcon_display *p;
int i, rows, cols, fg = -1;
if (!ops || ops->currcon < 0)
return;
for (i = first_fb_vc; i <= last_fb_vc; i++) {
vc = vc_cons[i].d;
if (!vc || vc->vc_mode != KD_TEXT ||
fbcon_info_from_console(i) != info)
continue;
if (con_is_visible(vc)) {
fg = i;
continue;
}
p = &fb_display[vc->vc_num];
set_blitting_type(vc, info);
var_to_display(p, &info->var, info);
cols = FBCON_SWAP(ops->rotate, info->var.xres, info->var.yres);
rows = FBCON_SWAP(ops->rotate, info->var.yres, info->var.xres);
cols /= vc->vc_font.width;
rows /= vc->vc_font.height;
vc_resize(vc, cols, rows);
}
if (fg != -1)
fbcon_modechanged(info);
}
void fbcon_update_vcs(struct fb_info *info, bool all)
{
if (all)
fbcon_set_all_vcs(info);
else
fbcon_modechanged(info);
}
EXPORT_SYMBOL(fbcon_update_vcs);
/* let fbcon check if it supports a new screen resolution */
int fbcon_modechange_possible(struct fb_info *info, struct fb_var_screeninfo *var)
{
struct fbcon_ops *ops = info->fbcon_par;
struct vc_data *vc;
unsigned int i;
WARN_CONSOLE_UNLOCKED();
if (!ops)
return 0;
/* prevent setting a screen size which is smaller than font size */
for (i = first_fb_vc; i <= last_fb_vc; i++) {
vc = vc_cons[i].d;
if (!vc || vc->vc_mode != KD_TEXT ||
fbcon_info_from_console(i) != info)
continue;
if (vc->vc_font.width > FBCON_SWAP(var->rotate, var->xres, var->yres) ||
vc->vc_font.height > FBCON_SWAP(var->rotate, var->yres, var->xres))
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(fbcon_modechange_possible);
int fbcon_mode_deleted(struct fb_info *info,
struct fb_videomode *mode)
{
struct fb_info *fb_info;
struct fbcon_display *p;
int i, j, found = 0;
/* before deletion, ensure that mode is not in use */
for (i = first_fb_vc; i <= last_fb_vc; i++) {
j = con2fb_map[i];
if (j == -1)
continue;
fb_info = fbcon_registered_fb[j];
if (fb_info != info)
continue;
p = &fb_display[i];
if (!p || !p->mode)
continue;
if (fb_mode_is_equal(p->mode, mode)) {
found = 1;
break;
}
}
return found;
}
#ifdef CONFIG_VT_HW_CONSOLE_BINDING
static void fbcon_unbind(void)
{
int ret;
ret = do_unbind_con_driver(&fb_con, first_fb_vc, last_fb_vc,
fbcon_is_default);
if (!ret)
fbcon_has_console_bind = 0;
}
#else
static inline void fbcon_unbind(void) {}
#endif /* CONFIG_VT_HW_CONSOLE_BINDING */
void fbcon_fb_unbind(struct fb_info *info)
{
int i, new_idx = -1;
int idx = info->node;
console_lock();
if (!fbcon_has_console_bind) {
console_unlock();
return;
}
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map[i] != idx &&
con2fb_map[i] != -1) {
new_idx = con2fb_map[i];
break;
}
}
if (new_idx != -1) {
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map[i] == idx)
set_con2fb_map(i, new_idx, 0);
}
} else {
struct fb_info *info = fbcon_registered_fb[idx];
/* This is sort of like set_con2fb_map, except it maps
* the consoles to no device and then releases the
* oldinfo to free memory and cancel the cursor blink
* timer. I can imagine this just becoming part of
* set_con2fb_map where new_idx is -1
*/
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map[i] == idx) {
con2fb_map[i] = -1;
if (!search_fb_in_map(idx)) {
con2fb_release_oldinfo(vc_cons[i].d,
info, NULL);
}
}
}
fbcon_unbind();
}
console_unlock();
}
void fbcon_fb_unregistered(struct fb_info *info)
{
int i, idx;
console_lock();
fbcon_registered_fb[info->node] = NULL;
fbcon_num_registered_fb--;
if (deferred_takeover) {
console_unlock();
return;
}
idx = info->node;
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map[i] == idx)
con2fb_map[i] = -1;
}
if (idx == info_idx) {
info_idx = -1;
fbcon_for_each_registered_fb(i) {
info_idx = i;
break;
}
}
if (info_idx != -1) {
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map[i] == -1)
con2fb_map[i] = info_idx;
}
}
if (primary_device == idx)
primary_device = -1;
if (!fbcon_num_registered_fb)
do_unregister_con_driver(&fb_con);
console_unlock();
}
void fbcon_remap_all(struct fb_info *info)
{
int i, idx = info->node;
console_lock();
if (deferred_takeover) {
for (i = first_fb_vc; i <= last_fb_vc; i++)
con2fb_map_boot[i] = idx;
fbcon_map_override();
console_unlock();
return;
}
for (i = first_fb_vc; i <= last_fb_vc; i++)
set_con2fb_map(i, idx, 0);
if (con_is_bound(&fb_con)) {
printk(KERN_INFO "fbcon: Remapping primary device, "
"fb%i, to tty %i-%i\n", idx,
first_fb_vc + 1, last_fb_vc + 1);
info_idx = idx;
}
console_unlock();
}
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY
static void fbcon_select_primary(struct fb_info *info)
{
if (!map_override && primary_device == -1 &&
fb_is_primary_device(info)) {
int i;
printk(KERN_INFO "fbcon: %s (fb%i) is primary device\n",
info->fix.id, info->node);
primary_device = info->node;
for (i = first_fb_vc; i <= last_fb_vc; i++)
con2fb_map_boot[i] = primary_device;
if (con_is_bound(&fb_con)) {
printk(KERN_INFO "fbcon: Remapping primary device, "
"fb%i, to tty %i-%i\n", info->node,
first_fb_vc + 1, last_fb_vc + 1);
info_idx = primary_device;
}
}
}
#else
static inline void fbcon_select_primary(struct fb_info *info)
{
return;
}
#endif /* CONFIG_FRAMEBUFFER_DETECT_PRIMARY */
static bool lockless_register_fb;
module_param_named_unsafe(lockless_register_fb, lockless_register_fb, bool, 0400);
MODULE_PARM_DESC(lockless_register_fb,
"Lockless framebuffer registration for debugging [default=off]");
/* called with console_lock held */
static int do_fb_registered(struct fb_info *info)
{
int ret = 0, i, idx;
WARN_CONSOLE_UNLOCKED();
fbcon_registered_fb[info->node] = info;
fbcon_num_registered_fb++;
idx = info->node;
fbcon_select_primary(info);
if (deferred_takeover) {
pr_info("fbcon: Deferring console take-over\n");
return 0;
}
if (info_idx == -1) {
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map_boot[i] == idx) {
info_idx = idx;
break;
}
}
if (info_idx != -1)
ret = do_fbcon_takeover(1);
} else {
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map_boot[i] == idx)
set_con2fb_map(i, idx, 0);
}
}
return ret;
}
int fbcon_fb_registered(struct fb_info *info)
{
int ret;
if (!lockless_register_fb)
console_lock();
else
atomic_inc(&ignore_console_lock_warning);
ret = do_fb_registered(info);
if (!lockless_register_fb)
console_unlock();
else
atomic_dec(&ignore_console_lock_warning);
return ret;
}
void fbcon_fb_blanked(struct fb_info *info, int blank)
{
struct fbcon_ops *ops = info->fbcon_par;
struct vc_data *vc;
if (!ops || ops->currcon < 0)
return;
vc = vc_cons[ops->currcon].d;
if (vc->vc_mode != KD_TEXT ||
fbcon_info_from_console(ops->currcon) != info)
return;
if (con_is_visible(vc)) {
if (blank)
do_blank_screen(0);
else
do_unblank_screen(0);
}
ops->blank_state = blank;
}
void fbcon_new_modelist(struct fb_info *info)
{
int i;
struct vc_data *vc;
struct fb_var_screeninfo var;
const struct fb_videomode *mode;
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (fbcon_info_from_console(i) != info)
continue;
if (!fb_display[i].mode)
continue;
vc = vc_cons[i].d;
display_to_var(&var, &fb_display[i]);
mode = fb_find_nearest_mode(fb_display[i].mode,
&info->modelist);
fb_videomode_to_var(&var, mode);
fbcon_set_disp(info, &var, vc->vc_num);
}
}
void fbcon_get_requirement(struct fb_info *info,
struct fb_blit_caps *caps)
{
struct vc_data *vc;
if (caps->flags) {
int i, charcnt;
for (i = first_fb_vc; i <= last_fb_vc; i++) {
vc = vc_cons[i].d;
if (vc && vc->vc_mode == KD_TEXT &&
info->node == con2fb_map[i]) {
caps->x |= 1 << (vc->vc_font.width - 1);
caps->y |= 1 << (vc->vc_font.height - 1);
charcnt = vc->vc_font.charcount;
if (caps->len < charcnt)
caps->len = charcnt;
}
}
} else {
vc = vc_cons[fg_console].d;
if (vc && vc->vc_mode == KD_TEXT &&
info->node == con2fb_map[fg_console]) {
caps->x = 1 << (vc->vc_font.width - 1);
caps->y = 1 << (vc->vc_font.height - 1);
caps->len = vc->vc_font.charcount;
}
}
}
int fbcon_set_con2fb_map_ioctl(void __user *argp)
{
struct fb_con2fbmap con2fb;
int ret;
if (copy_from_user(&con2fb, argp, sizeof(con2fb)))
return -EFAULT;
if (con2fb.console < 1 || con2fb.console > MAX_NR_CONSOLES)
return -EINVAL;
if (con2fb.framebuffer >= FB_MAX)
return -EINVAL;
if (!fbcon_registered_fb[con2fb.framebuffer])
request_module("fb%d", con2fb.framebuffer);
if (!fbcon_registered_fb[con2fb.framebuffer]) {
return -EINVAL;
}
console_lock();
ret = set_con2fb_map(con2fb.console - 1,
con2fb.framebuffer, 1);
console_unlock();
return ret;
}
int fbcon_get_con2fb_map_ioctl(void __user *argp)
{
struct fb_con2fbmap con2fb;
if (copy_from_user(&con2fb, argp, sizeof(con2fb)))
return -EFAULT;
if (con2fb.console < 1 || con2fb.console > MAX_NR_CONSOLES)
return -EINVAL;
console_lock();
con2fb.framebuffer = con2fb_map[con2fb.console - 1];
console_unlock();
return copy_to_user(argp, &con2fb, sizeof(con2fb)) ? -EFAULT : 0;
}
/*
* The console `switch' structure for the frame buffer based console
*/
static const struct consw fb_con = {
.owner = THIS_MODULE,
.con_startup = fbcon_startup,
.con_init = fbcon_init,
.con_deinit = fbcon_deinit,
.con_clear = fbcon_clear,
.con_putc = fbcon_putc,
.con_putcs = fbcon_putcs,
.con_cursor = fbcon_cursor,
.con_scroll = fbcon_scroll,
.con_switch = fbcon_switch,
.con_blank = fbcon_blank,
.con_font_set = fbcon_set_font,
.con_font_get = fbcon_get_font,
.con_font_default = fbcon_set_def_font,
.con_set_palette = fbcon_set_palette,
.con_invert_region = fbcon_invert_region,
.con_screen_pos = fbcon_screen_pos,
.con_getxy = fbcon_getxy,
.con_resize = fbcon_resize,
.con_debug_enter = fbcon_debug_enter,
.con_debug_leave = fbcon_debug_leave,
};
static ssize_t store_rotate(struct device *device,
struct device_attribute *attr, const char *buf,
size_t count)
{
struct fb_info *info;
int rotate, idx;
char **last = NULL;
console_lock();
idx = con2fb_map[fg_console];
if (idx == -1 || fbcon_registered_fb[idx] == NULL)
goto err;
info = fbcon_registered_fb[idx];
rotate = simple_strtoul(buf, last, 0);
fbcon_rotate(info, rotate);
err:
console_unlock();
return count;
}
static ssize_t store_rotate_all(struct device *device,
struct device_attribute *attr,const char *buf,
size_t count)
{
struct fb_info *info;
int rotate, idx;
char **last = NULL;
console_lock();
idx = con2fb_map[fg_console];
if (idx == -1 || fbcon_registered_fb[idx] == NULL)
goto err;
info = fbcon_registered_fb[idx];
rotate = simple_strtoul(buf, last, 0);
fbcon_rotate_all(info, rotate);
err:
console_unlock();
return count;
}
static ssize_t show_rotate(struct device *device,
struct device_attribute *attr,char *buf)
{
struct fb_info *info;
int rotate = 0, idx;
console_lock();
idx = con2fb_map[fg_console];
if (idx == -1 || fbcon_registered_fb[idx] == NULL)
goto err;
info = fbcon_registered_fb[idx];
rotate = fbcon_get_rotate(info);
err:
console_unlock();
return sysfs_emit(buf, "%d\n", rotate);
}
static ssize_t show_cursor_blink(struct device *device,
struct device_attribute *attr, char *buf)
{
struct fb_info *info;
struct fbcon_ops *ops;
int idx, blink = -1;
console_lock();
idx = con2fb_map[fg_console];
if (idx == -1 || fbcon_registered_fb[idx] == NULL)
goto err;
info = fbcon_registered_fb[idx];
ops = info->fbcon_par;
if (!ops)
goto err;
blink = delayed_work_pending(&ops->cursor_work);
err:
console_unlock();
return sysfs_emit(buf, "%d\n", blink);
}
static ssize_t store_cursor_blink(struct device *device,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct fb_info *info;
int blink, idx;
char **last = NULL;
console_lock();
idx = con2fb_map[fg_console];
if (idx == -1 || fbcon_registered_fb[idx] == NULL)
goto err;
info = fbcon_registered_fb[idx];
if (!info->fbcon_par)
goto err;
blink = simple_strtoul(buf, last, 0);
if (blink) {
fbcon_cursor_noblink = 0;
fbcon_add_cursor_work(info);
} else {
fbcon_cursor_noblink = 1;
fbcon_del_cursor_work(info);
}
err:
console_unlock();
return count;
}
static struct device_attribute device_attrs[] = {
__ATTR(rotate, S_IRUGO|S_IWUSR, show_rotate, store_rotate),
__ATTR(rotate_all, S_IWUSR, NULL, store_rotate_all),
__ATTR(cursor_blink, S_IRUGO|S_IWUSR, show_cursor_blink,
store_cursor_blink),
};
static int fbcon_init_device(void)
{
int i, error = 0;
fbcon_has_sysfs = 1;
for (i = 0; i < ARRAY_SIZE(device_attrs); i++) {
error = device_create_file(fbcon_device, &device_attrs[i]);
if (error)
break;
}
if (error) {
while (--i >= 0)
device_remove_file(fbcon_device, &device_attrs[i]);
fbcon_has_sysfs = 0;
}
return 0;
}
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER
static void fbcon_register_existing_fbs(struct work_struct *work)
{
int i;
console_lock();
deferred_takeover = false;
logo_shown = FBCON_LOGO_DONTSHOW;
fbcon_for_each_registered_fb(i)
do_fb_registered(fbcon_registered_fb[i]);
console_unlock();
}
static struct notifier_block fbcon_output_nb;
static DECLARE_WORK(fbcon_deferred_takeover_work, fbcon_register_existing_fbs);
static int fbcon_output_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
WARN_CONSOLE_UNLOCKED();
pr_info("fbcon: Taking over console\n");
dummycon_unregister_output_notifier(&fbcon_output_nb);
/* We may get called in atomic context */
schedule_work(&fbcon_deferred_takeover_work);
return NOTIFY_OK;
}
#endif
static void fbcon_start(void)
{
WARN_CONSOLE_UNLOCKED();
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER
if (conswitchp != &dummy_con)
deferred_takeover = false;
if (deferred_takeover) {
fbcon_output_nb.notifier_call = fbcon_output_notifier;
dummycon_register_output_notifier(&fbcon_output_nb);
return;
}
#endif
}
void __init fb_console_init(void)
{
int i;
console_lock();
fbcon_device = device_create(fb_class, NULL, MKDEV(0, 0), NULL,
"fbcon");
if (IS_ERR(fbcon_device)) {
printk(KERN_WARNING "Unable to create device "
"for fbcon; errno = %ld\n",
PTR_ERR(fbcon_device));
fbcon_device = NULL;
} else
fbcon_init_device();
for (i = 0; i < MAX_NR_CONSOLES; i++)
con2fb_map[i] = -1;
fbcon_start();
console_unlock();
}
#ifdef MODULE
static void __exit fbcon_deinit_device(void)
{
int i;
if (fbcon_has_sysfs) {
for (i = 0; i < ARRAY_SIZE(device_attrs); i++)
device_remove_file(fbcon_device, &device_attrs[i]);
fbcon_has_sysfs = 0;
}
}
void __exit fb_console_exit(void)
{
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER
console_lock();
if (deferred_takeover)
dummycon_unregister_output_notifier(&fbcon_output_nb);
console_unlock();
cancel_work_sync(&fbcon_deferred_takeover_work);
#endif
console_lock();
fbcon_deinit_device();
device_destroy(fb_class, MKDEV(0, 0));
do_unregister_con_driver(&fb_con);
console_unlock();
}
#endif
| linux-master | drivers/video/fbdev/core/fbcon.c |
/*
* Common utility functions for VGA-based graphics cards.
*
* Copyright (c) 2006-2007 Ondrej Zajicek <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/math.h>
#include <linux/svga.h>
#include <asm/types.h>
#include <asm/io.h>
/* Write a CRT register value spread across multiple registers */
void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
{
u8 regval, bitval, bitnum;
while (regset->regnum != VGA_REGSET_END_VAL) {
regval = vga_rcrt(regbase, regset->regnum);
bitnum = regset->lowbit;
while (bitnum <= regset->highbit) {
bitval = 1 << bitnum;
regval = regval & ~bitval;
if (value & 1) regval = regval | bitval;
bitnum ++;
value = value >> 1;
}
vga_wcrt(regbase, regset->regnum, regval);
regset ++;
}
}
/* Write a sequencer register value spread across multiple registers */
void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
{
u8 regval, bitval, bitnum;
while (regset->regnum != VGA_REGSET_END_VAL) {
regval = vga_rseq(regbase, regset->regnum);
bitnum = regset->lowbit;
while (bitnum <= regset->highbit) {
bitval = 1 << bitnum;
regval = regval & ~bitval;
if (value & 1) regval = regval | bitval;
bitnum ++;
value = value >> 1;
}
vga_wseq(regbase, regset->regnum, regval);
regset ++;
}
}
static unsigned int svga_regset_size(const struct vga_regset *regset)
{
u8 count = 0;
while (regset->regnum != VGA_REGSET_END_VAL) {
count += regset->highbit - regset->lowbit + 1;
regset ++;
}
return 1 << count;
}
/* ------------------------------------------------------------------------- */
/* Set graphics controller registers to sane values */
void svga_set_default_gfx_regs(void __iomem *regbase)
{
/* All standard GFX registers (GR00 - GR08) */
vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00);
vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00);
vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00);
vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0x00);
vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0x00);
vga_wgfx(regbase, VGA_GFX_MODE, 0x00);
/* vga_wgfx(regbase, VGA_GFX_MODE, 0x20); */
/* vga_wgfx(regbase, VGA_GFX_MODE, 0x40); */
vga_wgfx(regbase, VGA_GFX_MISC, 0x05);
/* vga_wgfx(regbase, VGA_GFX_MISC, 0x01); */
vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x0F);
vga_wgfx(regbase, VGA_GFX_BIT_MASK, 0xFF);
}
/* Set attribute controller registers to sane values */
void svga_set_default_atc_regs(void __iomem *regbase)
{
u8 count;
vga_r(regbase, 0x3DA);
vga_w(regbase, VGA_ATT_W, 0x00);
/* All standard ATC registers (AR00 - AR14) */
for (count = 0; count <= 0xF; count ++)
svga_wattr(regbase, count, count);
svga_wattr(regbase, VGA_ATC_MODE, 0x01);
/* svga_wattr(regbase, VGA_ATC_MODE, 0x41); */
svga_wattr(regbase, VGA_ATC_OVERSCAN, 0x00);
svga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 0x0F);
svga_wattr(regbase, VGA_ATC_PEL, 0x00);
svga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0x00);
vga_r(regbase, 0x3DA);
vga_w(regbase, VGA_ATT_W, 0x20);
}
/* Set sequencer registers to sane values */
void svga_set_default_seq_regs(void __iomem *regbase)
{
/* Standard sequencer registers (SR01 - SR04), SR00 is not set */
vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
/* vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
}
/* Set CRTC registers to sane values */
void svga_set_default_crt_regs(void __iomem *regbase)
{
/* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */
svga_wcrt_mask(regbase, 0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */
vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
svga_wcrt_mask(regbase, VGA_CRTC_MAX_SCAN, 0, 0x1F);
vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
vga_wcrt(regbase, VGA_CRTC_MODE, 0xE3);
}
void svga_set_textmode_vga_regs(void __iomem *regbase)
{
/* svga_wseq_mask(regbase, 0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */
vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x03);
vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */
vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0x1f);
svga_wcrt_mask(regbase, VGA_CRTC_MODE, 0x23, 0x7f);
vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0x0d);
vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 0x0e);
vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0x00);
vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0x00);
vga_wgfx(regbase, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */
vga_wgfx(regbase, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */
vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x00);
vga_r(regbase, 0x3DA);
vga_w(regbase, VGA_ATT_W, 0x00);
svga_wattr(regbase, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */
svga_wattr(regbase, 0x13, 0x08); /* Horizontal Pixel Panning Register */
vga_r(regbase, 0x3DA);
vga_w(regbase, VGA_ATT_W, 0x20);
}
#if 0
void svga_dump_var(struct fb_var_screeninfo *var, int node)
{
pr_debug("fb%d: var.vmode : 0x%X\n", node, var->vmode);
pr_debug("fb%d: var.xres : %d\n", node, var->xres);
pr_debug("fb%d: var.yres : %d\n", node, var->yres);
pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel);
pr_debug("fb%d: var.xres_virtual : %d\n", node, var->xres_virtual);
pr_debug("fb%d: var.yres_virtual : %d\n", node, var->yres_virtual);
pr_debug("fb%d: var.left_margin : %d\n", node, var->left_margin);
pr_debug("fb%d: var.right_margin : %d\n", node, var->right_margin);
pr_debug("fb%d: var.upper_margin : %d\n", node, var->upper_margin);
pr_debug("fb%d: var.lower_margin : %d\n", node, var->lower_margin);
pr_debug("fb%d: var.hsync_len : %d\n", node, var->hsync_len);
pr_debug("fb%d: var.vsync_len : %d\n", node, var->vsync_len);
pr_debug("fb%d: var.sync : 0x%X\n", node, var->sync);
pr_debug("fb%d: var.pixclock : %d\n\n", node, var->pixclock);
}
#endif /* 0 */
/* ------------------------------------------------------------------------- */
void svga_settile(struct fb_info *info, struct fb_tilemap *map)
{
const u8 *font = map->data;
u8 __iomem *fb = (u8 __iomem *)info->screen_base;
int i, c;
if ((map->width != 8) || (map->height != 16) ||
(map->depth != 1) || (map->length != 256)) {
fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
map->width, map->height, map->depth, map->length);
return;
}
fb += 2;
for (c = 0; c < map->length; c++) {
for (i = 0; i < map->height; i++) {
fb_writeb(font[i], fb + i * 4);
// fb[i * 4] = font[i];
}
fb += 128;
font += map->height;
}
}
/* Copy area in text (tileblit) mode */
void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area)
{
int dx, dy;
/* colstride is halved in this function because u16 are used */
int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
int rowstride = colstride * (info->var.xres_virtual / 8);
u16 __iomem *fb = (u16 __iomem *) info->screen_base;
u16 __iomem *src, *dst;
if ((area->sy > area->dy) ||
((area->sy == area->dy) && (area->sx > area->dx))) {
src = fb + area->sx * colstride + area->sy * rowstride;
dst = fb + area->dx * colstride + area->dy * rowstride;
} else {
src = fb + (area->sx + area->width - 1) * colstride
+ (area->sy + area->height - 1) * rowstride;
dst = fb + (area->dx + area->width - 1) * colstride
+ (area->dy + area->height - 1) * rowstride;
colstride = -colstride;
rowstride = -rowstride;
}
for (dy = 0; dy < area->height; dy++) {
u16 __iomem *src2 = src;
u16 __iomem *dst2 = dst;
for (dx = 0; dx < area->width; dx++) {
fb_writew(fb_readw(src2), dst2);
// *dst2 = *src2;
src2 += colstride;
dst2 += colstride;
}
src += rowstride;
dst += rowstride;
}
}
/* Fill area in text (tileblit) mode */
void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect)
{
int dx, dy;
int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
int rowstride = colstride * (info->var.xres_virtual / 8);
int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg);
u8 __iomem *fb = (u8 __iomem *)info->screen_base;
fb += rect->sx * colstride + rect->sy * rowstride;
for (dy = 0; dy < rect->height; dy++) {
u8 __iomem *fb2 = fb;
for (dx = 0; dx < rect->width; dx++) {
fb_writeb(rect->index, fb2);
fb_writeb(attr, fb2 + 1);
fb2 += colstride;
}
fb += rowstride;
}
}
/* Write text in text (tileblit) mode */
void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit)
{
int dx, dy, i;
int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
int rowstride = colstride * (info->var.xres_virtual / 8);
int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg);
u8 __iomem *fb = (u8 __iomem *)info->screen_base;
fb += blit->sx * colstride + blit->sy * rowstride;
i=0;
for (dy=0; dy < blit->height; dy ++) {
u8 __iomem *fb2 = fb;
for (dx = 0; dx < blit->width; dx ++) {
fb_writeb(blit->indices[i], fb2);
fb_writeb(attr, fb2 + 1);
fb2 += colstride;
i ++;
if (i == blit->length) return;
}
fb += rowstride;
}
}
/* Set cursor in text (tileblit) mode */
void svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor)
{
u8 cs = 0x0d;
u8 ce = 0x0e;
u16 pos = cursor->sx + (info->var.xoffset / 8)
+ (cursor->sy + (info->var.yoffset / 16))
* (info->var.xres_virtual / 8);
if (! cursor -> mode)
return;
svga_wcrt_mask(regbase, 0x0A, 0x20, 0x20); /* disable cursor */
if (cursor -> shape == FB_TILE_CURSOR_NONE)
return;
switch (cursor -> shape) {
case FB_TILE_CURSOR_UNDERLINE:
cs = 0x0d;
break;
case FB_TILE_CURSOR_LOWER_THIRD:
cs = 0x09;
break;
case FB_TILE_CURSOR_LOWER_HALF:
cs = 0x07;
break;
case FB_TILE_CURSOR_TWO_THIRDS:
cs = 0x05;
break;
case FB_TILE_CURSOR_BLOCK:
cs = 0x01;
break;
}
/* set cursor position */
vga_wcrt(regbase, 0x0E, pos >> 8);
vga_wcrt(regbase, 0x0F, pos & 0xFF);
vga_wcrt(regbase, 0x0B, ce); /* set cursor end */
vga_wcrt(regbase, 0x0A, cs); /* set cursor start and enable it */
}
int svga_get_tilemax(struct fb_info *info)
{
return 256;
}
/* Get capabilities of accelerator based on the mode */
void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps,
struct fb_var_screeninfo *var)
{
if (var->bits_per_pixel == 0) {
/* can only support 256 8x16 bitmap */
caps->x = 1 << (8 - 1);
caps->y = 1 << (16 - 1);
caps->len = 256;
} else {
caps->x = (var->bits_per_pixel == 4) ? 1 << (8 - 1) : ~(u32)0;
caps->y = ~(u32)0;
caps->len = ~(u32)0;
}
}
EXPORT_SYMBOL(svga_get_caps);
/* ------------------------------------------------------------------------- */
/*
* Compute PLL settings (M, N, R)
* F_VCO = (F_BASE * M) / N
* F_OUT = F_VCO / (2^R)
*/
int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node)
{
u16 am, an, ar;
u32 f_vco, f_current, delta_current, delta_best;
pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted);
ar = pll->r_max;
f_vco = f_wanted << ar;
/* overflow check */
if ((f_vco >> ar) != f_wanted)
return -EINVAL;
/* It is usually better to have greater VCO clock
because of better frequency stability.
So first try r_max, then r smaller. */
while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
ar--;
f_vco = f_vco >> 1;
}
/* VCO bounds check */
if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
return -EINVAL;
delta_best = 0xFFFFFFFF;
*m = 0;
*n = 0;
*r = ar;
am = pll->m_min;
an = pll->n_min;
while ((am <= pll->m_max) && (an <= pll->n_max)) {
f_current = (pll->f_base * am) / an;
delta_current = abs_diff (f_current, f_vco);
if (delta_current < delta_best) {
delta_best = delta_current;
*m = am;
*n = an;
}
if (f_current <= f_vco) {
am ++;
} else {
an ++;
}
}
f_current = (pll->f_base * *m) / *n;
pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current);
pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r);
return 0;
}
/* ------------------------------------------------------------------------- */
/* Check CRT timing values */
int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node)
{
u32 value;
var->xres = (var->xres+7)&~7;
var->left_margin = (var->left_margin+7)&~7;
var->right_margin = (var->right_margin+7)&~7;
var->hsync_len = (var->hsync_len+7)&~7;
/* Check horizontal total */
value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs))
return -EINVAL;
/* Check horizontal display and blank start */
value = var->xres;
if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs))
return -EINVAL;
if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs))
return -EINVAL;
/* Check horizontal sync start */
value = var->xres + var->right_margin;
if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs))
return -EINVAL;
/* Check horizontal blank end (or length) */
value = var->left_margin + var->right_margin + var->hsync_len;
if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs)))
return -EINVAL;
/* Check horizontal sync end (or length) */
value = var->hsync_len;
if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs)))
return -EINVAL;
/* Check vertical total */
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
if ((value - 1) >= svga_regset_size(tm->v_total_regs))
return -EINVAL;
/* Check vertical display and blank start */
value = var->yres;
if ((value - 1) >= svga_regset_size(tm->v_display_regs))
return -EINVAL;
if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs))
return -EINVAL;
/* Check vertical sync start */
value = var->yres + var->lower_margin;
if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs))
return -EINVAL;
/* Check vertical blank end (or length) */
value = var->upper_margin + var->lower_margin + var->vsync_len;
if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs)))
return -EINVAL;
/* Check vertical sync end (or length) */
value = var->vsync_len;
if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs)))
return -EINVAL;
return 0;
}
/* Set CRT timing registers */
void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm,
struct fb_var_screeninfo *var,
u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
{
u8 regval;
u32 value;
value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal total : %d\n", node, value);
svga_wcrt_multi(regbase, tm->h_total_regs, (value / 8) - 5);
value = var->xres;
value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal display : %d\n", node, value);
svga_wcrt_multi(regbase, tm->h_display_regs, (value / 8) - 1);
value = var->xres;
value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal blank start: %d\n", node, value);
svga_wcrt_multi(regbase, tm->h_blank_start_regs, (value / 8) - 1 + hborder);
value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal blank end : %d\n", node, value);
svga_wcrt_multi(regbase, tm->h_blank_end_regs, (value / 8) - 1 - hborder);
value = var->xres + var->right_margin;
value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal sync start : %d\n", node, value);
svga_wcrt_multi(regbase, tm->h_sync_start_regs, (value / 8));
value = var->xres + var->right_margin + var->hsync_len;
value = (value * hmul) / hdiv;
pr_debug("fb%d: horizontal sync end : %d\n", node, value);
svga_wcrt_multi(regbase, tm->h_sync_end_regs, (value / 8));
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical total : %d\n", node, value);
svga_wcrt_multi(regbase, tm->v_total_regs, value - 2);
value = var->yres;
value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical display : %d\n", node, value);
svga_wcrt_multi(regbase, tm->v_display_regs, value - 1);
value = var->yres;
value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical blank start : %d\n", node, value);
svga_wcrt_multi(regbase, tm->v_blank_start_regs, value);
value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical blank end : %d\n", node, value);
svga_wcrt_multi(regbase, tm->v_blank_end_regs, value - 2);
value = var->yres + var->lower_margin;
value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical sync start : %d\n", node, value);
svga_wcrt_multi(regbase, tm->v_sync_start_regs, value);
value = var->yres + var->lower_margin + var->vsync_len;
value = (value * vmul) / vdiv;
pr_debug("fb%d: vertical sync end : %d\n", node, value);
svga_wcrt_multi(regbase, tm->v_sync_end_regs, value);
/* Set horizontal and vertical sync pulse polarity in misc register */
regval = vga_r(regbase, VGA_MIS_R);
if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
pr_debug("fb%d: positive horizontal sync\n", node);
regval = regval & ~0x80;
} else {
pr_debug("fb%d: negative horizontal sync\n", node);
regval = regval | 0x80;
}
if (var->sync & FB_SYNC_VERT_HIGH_ACT) {
pr_debug("fb%d: positive vertical sync\n", node);
regval = regval & ~0x40;
} else {
pr_debug("fb%d: negative vertical sync\n\n", node);
regval = regval | 0x40;
}
vga_w(regbase, VGA_MIS_W, regval);
}
/* ------------------------------------------------------------------------- */
static inline int match_format(const struct svga_fb_format *frm,
struct fb_var_screeninfo *var)
{
int i = 0;
int stored = -EINVAL;
while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL)
{
if ((var->bits_per_pixel == frm->bits_per_pixel) &&
(var->red.length <= frm->red.length) &&
(var->green.length <= frm->green.length) &&
(var->blue.length <= frm->blue.length) &&
(var->transp.length <= frm->transp.length) &&
(var->nonstd == frm->nonstd))
return i;
if (var->bits_per_pixel == frm->bits_per_pixel)
stored = i;
i++;
frm++;
}
return stored;
}
int svga_match_format(const struct svga_fb_format *frm,
struct fb_var_screeninfo *var,
struct fb_fix_screeninfo *fix)
{
int i = match_format(frm, var);
if (i >= 0) {
var->bits_per_pixel = frm[i].bits_per_pixel;
var->red = frm[i].red;
var->green = frm[i].green;
var->blue = frm[i].blue;
var->transp = frm[i].transp;
var->nonstd = frm[i].nonstd;
if (fix != NULL) {
fix->type = frm[i].type;
fix->type_aux = frm[i].type_aux;
fix->visual = frm[i].visual;
fix->xpanstep = frm[i].xpanstep;
}
}
return i;
}
EXPORT_SYMBOL(svga_wcrt_multi);
EXPORT_SYMBOL(svga_wseq_multi);
EXPORT_SYMBOL(svga_set_default_gfx_regs);
EXPORT_SYMBOL(svga_set_default_atc_regs);
EXPORT_SYMBOL(svga_set_default_seq_regs);
EXPORT_SYMBOL(svga_set_default_crt_regs);
EXPORT_SYMBOL(svga_set_textmode_vga_regs);
EXPORT_SYMBOL(svga_settile);
EXPORT_SYMBOL(svga_tilecopy);
EXPORT_SYMBOL(svga_tilefill);
EXPORT_SYMBOL(svga_tileblit);
EXPORT_SYMBOL(svga_tilecursor);
EXPORT_SYMBOL(svga_get_tilemax);
EXPORT_SYMBOL(svga_compute_pll);
EXPORT_SYMBOL(svga_check_timings);
EXPORT_SYMBOL(svga_set_timings);
EXPORT_SYMBOL(svga_match_format);
MODULE_AUTHOR("Ondrej Zajicek <[email protected]>");
MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/svgalib.c |
/*
* linux/drivers/video/console/bitblit.c -- BitBlitting Operation
*
* Originally from the 'accel_*' routines in drivers/video/console/fbcon.c
*
* Copyright (C) 2004 Antonino Daplas <adaplas @pol.net>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/vt_kern.h>
#include <linux/console.h>
#include <asm/types.h>
#include "fbcon.h"
/*
* Accelerated handlers.
*/
static void update_attr(u8 *dst, u8 *src, int attribute,
struct vc_data *vc)
{
int i, offset = (vc->vc_font.height < 10) ? 1 : 2;
int width = DIV_ROUND_UP(vc->vc_font.width, 8);
unsigned int cellsize = vc->vc_font.height * width;
u8 c;
offset = cellsize - (offset * width);
for (i = 0; i < cellsize; i++) {
c = src[i];
if (attribute & FBCON_ATTRIBUTE_UNDERLINE && i >= offset)
c = 0xff;
if (attribute & FBCON_ATTRIBUTE_BOLD)
c |= c >> 1;
if (attribute & FBCON_ATTRIBUTE_REVERSE)
c = ~c;
dst[i] = c;
}
}
static void bit_bmove(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int dy, int dx, int height, int width)
{
struct fb_copyarea area;
area.sx = sx * vc->vc_font.width;
area.sy = sy * vc->vc_font.height;
area.dx = dx * vc->vc_font.width;
area.dy = dy * vc->vc_font.height;
area.height = height * vc->vc_font.height;
area.width = width * vc->vc_font.width;
info->fbops->fb_copyarea(info, &area);
}
static void bit_clear(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int height, int width)
{
int bgshift = (vc->vc_hi_font_mask) ? 13 : 12;
struct fb_fillrect region;
region.color = attr_bgcol_ec(bgshift, vc, info);
region.dx = sx * vc->vc_font.width;
region.dy = sy * vc->vc_font.height;
region.width = width * vc->vc_font.width;
region.height = height * vc->vc_font.height;
region.rop = ROP_COPY;
info->fbops->fb_fillrect(info, ®ion);
}
static inline void bit_putcs_aligned(struct vc_data *vc, struct fb_info *info,
const u16 *s, u32 attr, u32 cnt,
u32 d_pitch, u32 s_pitch, u32 cellsize,
struct fb_image *image, u8 *buf, u8 *dst)
{
u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
u32 idx = vc->vc_font.width >> 3;
u8 *src;
while (cnt--) {
src = vc->vc_font.data + (scr_readw(s++)&
charmask)*cellsize;
if (attr) {
update_attr(buf, src, attr, vc);
src = buf;
}
if (likely(idx == 1))
__fb_pad_aligned_buffer(dst, d_pitch, src, idx,
image->height);
else
fb_pad_aligned_buffer(dst, d_pitch, src, idx,
image->height);
dst += s_pitch;
}
info->fbops->fb_imageblit(info, image);
}
static inline void bit_putcs_unaligned(struct vc_data *vc,
struct fb_info *info, const u16 *s,
u32 attr, u32 cnt, u32 d_pitch,
u32 s_pitch, u32 cellsize,
struct fb_image *image, u8 *buf,
u8 *dst)
{
u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
u32 shift_low = 0, mod = vc->vc_font.width % 8;
u32 shift_high = 8;
u32 idx = vc->vc_font.width >> 3;
u8 *src;
while (cnt--) {
src = vc->vc_font.data + (scr_readw(s++)&
charmask)*cellsize;
if (attr) {
update_attr(buf, src, attr, vc);
src = buf;
}
fb_pad_unaligned_buffer(dst, d_pitch, src, idx,
image->height, shift_high,
shift_low, mod);
shift_low += mod;
dst += (shift_low >= 8) ? s_pitch : s_pitch - 1;
shift_low &= 7;
shift_high = 8 - shift_low;
}
info->fbops->fb_imageblit(info, image);
}
static void bit_putcs(struct vc_data *vc, struct fb_info *info,
const unsigned short *s, int count, int yy, int xx,
int fg, int bg)
{
struct fb_image image;
u32 width = DIV_ROUND_UP(vc->vc_font.width, 8);
u32 cellsize = width * vc->vc_font.height;
u32 maxcnt = info->pixmap.size/cellsize;
u32 scan_align = info->pixmap.scan_align - 1;
u32 buf_align = info->pixmap.buf_align - 1;
u32 mod = vc->vc_font.width % 8, cnt, pitch, size;
u32 attribute = get_attribute(info, scr_readw(s));
u8 *dst, *buf = NULL;
image.fg_color = fg;
image.bg_color = bg;
image.dx = xx * vc->vc_font.width;
image.dy = yy * vc->vc_font.height;
image.height = vc->vc_font.height;
image.depth = 1;
if (attribute) {
buf = kmalloc(cellsize, GFP_ATOMIC);
if (!buf)
return;
}
while (count) {
if (count > maxcnt)
cnt = maxcnt;
else
cnt = count;
image.width = vc->vc_font.width * cnt;
pitch = DIV_ROUND_UP(image.width, 8) + scan_align;
pitch &= ~scan_align;
size = pitch * image.height + buf_align;
size &= ~buf_align;
dst = fb_get_buffer_offset(info, &info->pixmap, size);
image.data = dst;
if (!mod)
bit_putcs_aligned(vc, info, s, attribute, cnt, pitch,
width, cellsize, &image, buf, dst);
else
bit_putcs_unaligned(vc, info, s, attribute, cnt,
pitch, width, cellsize, &image,
buf, dst);
image.dx += cnt * vc->vc_font.width;
count -= cnt;
s += cnt;
}
/* buf is always NULL except when in monochrome mode, so in this case
it's a gain to check buf against NULL even though kfree() handles
NULL pointers just fine */
if (unlikely(buf))
kfree(buf);
}
static void bit_clear_margins(struct vc_data *vc, struct fb_info *info,
int color, int bottom_only)
{
unsigned int cw = vc->vc_font.width;
unsigned int ch = vc->vc_font.height;
unsigned int rw = info->var.xres - (vc->vc_cols*cw);
unsigned int bh = info->var.yres - (vc->vc_rows*ch);
unsigned int rs = info->var.xres - rw;
unsigned int bs = info->var.yres - bh;
struct fb_fillrect region;
region.color = color;
region.rop = ROP_COPY;
if ((int) rw > 0 && !bottom_only) {
region.dx = info->var.xoffset + rs;
region.dy = 0;
region.width = rw;
region.height = info->var.yres_virtual;
info->fbops->fb_fillrect(info, ®ion);
}
if ((int) bh > 0) {
region.dx = info->var.xoffset;
region.dy = info->var.yoffset + bs;
region.width = rs;
region.height = bh;
info->fbops->fb_fillrect(info, ®ion);
}
}
static void bit_cursor(struct vc_data *vc, struct fb_info *info, int mode,
int fg, int bg)
{
struct fb_cursor cursor;
struct fbcon_ops *ops = info->fbcon_par;
unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
int w = DIV_ROUND_UP(vc->vc_font.width, 8), c;
int y = real_y(ops->p, vc->state.y);
int attribute, use_sw = vc->vc_cursor_type & CUR_SW;
int err = 1;
char *src;
cursor.set = 0;
if (!vc->vc_font.data)
return;
c = scr_readw((u16 *) vc->vc_pos);
attribute = get_attribute(info, c);
src = vc->vc_font.data + ((c & charmask) * (w * vc->vc_font.height));
if (ops->cursor_state.image.data != src ||
ops->cursor_reset) {
ops->cursor_state.image.data = src;
cursor.set |= FB_CUR_SETIMAGE;
}
if (attribute) {
u8 *dst;
dst = kmalloc_array(w, vc->vc_font.height, GFP_ATOMIC);
if (!dst)
return;
kfree(ops->cursor_data);
ops->cursor_data = dst;
update_attr(dst, src, attribute, vc);
src = dst;
}
if (ops->cursor_state.image.fg_color != fg ||
ops->cursor_state.image.bg_color != bg ||
ops->cursor_reset) {
ops->cursor_state.image.fg_color = fg;
ops->cursor_state.image.bg_color = bg;
cursor.set |= FB_CUR_SETCMAP;
}
if ((ops->cursor_state.image.dx != (vc->vc_font.width * vc->state.x)) ||
(ops->cursor_state.image.dy != (vc->vc_font.height * y)) ||
ops->cursor_reset) {
ops->cursor_state.image.dx = vc->vc_font.width * vc->state.x;
ops->cursor_state.image.dy = vc->vc_font.height * y;
cursor.set |= FB_CUR_SETPOS;
}
if (ops->cursor_state.image.height != vc->vc_font.height ||
ops->cursor_state.image.width != vc->vc_font.width ||
ops->cursor_reset) {
ops->cursor_state.image.height = vc->vc_font.height;
ops->cursor_state.image.width = vc->vc_font.width;
cursor.set |= FB_CUR_SETSIZE;
}
if (ops->cursor_state.hot.x || ops->cursor_state.hot.y ||
ops->cursor_reset) {
ops->cursor_state.hot.x = cursor.hot.y = 0;
cursor.set |= FB_CUR_SETHOT;
}
if (cursor.set & FB_CUR_SETSIZE ||
vc->vc_cursor_type != ops->p->cursor_shape ||
ops->cursor_state.mask == NULL ||
ops->cursor_reset) {
char *mask = kmalloc_array(w, vc->vc_font.height, GFP_ATOMIC);
int cur_height, size, i = 0;
u8 msk = 0xff;
if (!mask)
return;
kfree(ops->cursor_state.mask);
ops->cursor_state.mask = mask;
ops->p->cursor_shape = vc->vc_cursor_type;
cursor.set |= FB_CUR_SETSHAPE;
switch (CUR_SIZE(ops->p->cursor_shape)) {
case CUR_NONE:
cur_height = 0;
break;
case CUR_UNDERLINE:
cur_height = (vc->vc_font.height < 10) ? 1 : 2;
break;
case CUR_LOWER_THIRD:
cur_height = vc->vc_font.height/3;
break;
case CUR_LOWER_HALF:
cur_height = vc->vc_font.height >> 1;
break;
case CUR_TWO_THIRDS:
cur_height = (vc->vc_font.height << 1)/3;
break;
case CUR_BLOCK:
default:
cur_height = vc->vc_font.height;
break;
}
size = (vc->vc_font.height - cur_height) * w;
while (size--)
mask[i++] = ~msk;
size = cur_height * w;
while (size--)
mask[i++] = msk;
}
switch (mode) {
case CM_ERASE:
ops->cursor_state.enable = 0;
break;
case CM_DRAW:
case CM_MOVE:
default:
ops->cursor_state.enable = (use_sw) ? 0 : 1;
break;
}
cursor.image.data = src;
cursor.image.fg_color = ops->cursor_state.image.fg_color;
cursor.image.bg_color = ops->cursor_state.image.bg_color;
cursor.image.dx = ops->cursor_state.image.dx;
cursor.image.dy = ops->cursor_state.image.dy;
cursor.image.height = ops->cursor_state.image.height;
cursor.image.width = ops->cursor_state.image.width;
cursor.hot.x = ops->cursor_state.hot.x;
cursor.hot.y = ops->cursor_state.hot.y;
cursor.mask = ops->cursor_state.mask;
cursor.enable = ops->cursor_state.enable;
cursor.image.depth = 1;
cursor.rop = ROP_XOR;
if (info->fbops->fb_cursor)
err = info->fbops->fb_cursor(info, &cursor);
if (err)
soft_cursor(info, &cursor);
ops->cursor_reset = 0;
}
static int bit_update_start(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
int err;
err = fb_pan_display(info, &ops->var);
ops->var.xoffset = info->var.xoffset;
ops->var.yoffset = info->var.yoffset;
ops->var.vmode = info->var.vmode;
return err;
}
void fbcon_set_bitops(struct fbcon_ops *ops)
{
ops->bmove = bit_bmove;
ops->clear = bit_clear;
ops->putcs = bit_putcs;
ops->clear_margins = bit_clear_margins;
ops->cursor = bit_cursor;
ops->update_start = bit_update_start;
ops->rotate_font = NULL;
if (ops->rotate)
fbcon_set_rotate(ops);
}
| linux-master | drivers/video/fbdev/core/bitblit.c |
/*
* linux/drivers/video/console/fbcon_ccw.c -- Software Rotation - 270 degrees
*
* Copyright (C) 2005 Antonino Daplas <adaplas @pol.net>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/vt_kern.h>
#include <linux/console.h>
#include <asm/types.h>
#include "fbcon.h"
#include "fbcon_rotate.h"
/*
* Rotation 270 degrees
*/
static void ccw_update_attr(u8 *dst, u8 *src, int attribute,
struct vc_data *vc)
{
int i, j, offset = (vc->vc_font.height < 10) ? 1 : 2;
int width = (vc->vc_font.height + 7) >> 3;
int mod = vc->vc_font.height % 8;
u8 c, msk = ~(0xff << offset), msk1 = 0;
if (mod)
msk <<= (8 - mod);
if (offset > mod)
msk1 |= 0x01;
for (i = 0; i < vc->vc_font.width; i++) {
for (j = 0; j < width; j++) {
c = *src;
if (attribute & FBCON_ATTRIBUTE_UNDERLINE) {
if (j == width - 1)
c |= msk;
if (msk1 && j == width - 2)
c |= msk1;
}
if (attribute & FBCON_ATTRIBUTE_BOLD && i)
*(dst - width) |= c;
if (attribute & FBCON_ATTRIBUTE_REVERSE)
c = ~c;
src++;
*dst++ = c;
}
}
}
static void ccw_bmove(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int dy, int dx, int height, int width)
{
struct fbcon_ops *ops = info->fbcon_par;
struct fb_copyarea area;
u32 vyres = GETVYRES(ops->p, info);
area.sx = sy * vc->vc_font.height;
area.sy = vyres - ((sx + width) * vc->vc_font.width);
area.dx = dy * vc->vc_font.height;
area.dy = vyres - ((dx + width) * vc->vc_font.width);
area.width = height * vc->vc_font.height;
area.height = width * vc->vc_font.width;
info->fbops->fb_copyarea(info, &area);
}
static void ccw_clear(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int height, int width)
{
struct fbcon_ops *ops = info->fbcon_par;
struct fb_fillrect region;
int bgshift = (vc->vc_hi_font_mask) ? 13 : 12;
u32 vyres = GETVYRES(ops->p, info);
region.color = attr_bgcol_ec(bgshift,vc,info);
region.dx = sy * vc->vc_font.height;
region.dy = vyres - ((sx + width) * vc->vc_font.width);
region.height = width * vc->vc_font.width;
region.width = height * vc->vc_font.height;
region.rop = ROP_COPY;
info->fbops->fb_fillrect(info, ®ion);
}
static inline void ccw_putcs_aligned(struct vc_data *vc, struct fb_info *info,
const u16 *s, u32 attr, u32 cnt,
u32 d_pitch, u32 s_pitch, u32 cellsize,
struct fb_image *image, u8 *buf, u8 *dst)
{
struct fbcon_ops *ops = info->fbcon_par;
u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
u32 idx = (vc->vc_font.height + 7) >> 3;
u8 *src;
while (cnt--) {
src = ops->fontbuffer + (scr_readw(s--) & charmask)*cellsize;
if (attr) {
ccw_update_attr(buf, src, attr, vc);
src = buf;
}
if (likely(idx == 1))
__fb_pad_aligned_buffer(dst, d_pitch, src, idx,
vc->vc_font.width);
else
fb_pad_aligned_buffer(dst, d_pitch, src, idx,
vc->vc_font.width);
dst += d_pitch * vc->vc_font.width;
}
info->fbops->fb_imageblit(info, image);
}
static void ccw_putcs(struct vc_data *vc, struct fb_info *info,
const unsigned short *s, int count, int yy, int xx,
int fg, int bg)
{
struct fb_image image;
struct fbcon_ops *ops = info->fbcon_par;
u32 width = (vc->vc_font.height + 7)/8;
u32 cellsize = width * vc->vc_font.width;
u32 maxcnt = info->pixmap.size/cellsize;
u32 scan_align = info->pixmap.scan_align - 1;
u32 buf_align = info->pixmap.buf_align - 1;
u32 cnt, pitch, size;
u32 attribute = get_attribute(info, scr_readw(s));
u8 *dst, *buf = NULL;
u32 vyres = GETVYRES(ops->p, info);
if (!ops->fontbuffer)
return;
image.fg_color = fg;
image.bg_color = bg;
image.dx = yy * vc->vc_font.height;
image.dy = vyres - ((xx + count) * vc->vc_font.width);
image.width = vc->vc_font.height;
image.depth = 1;
if (attribute) {
buf = kmalloc(cellsize, GFP_KERNEL);
if (!buf)
return;
}
s += count - 1;
while (count) {
if (count > maxcnt)
cnt = maxcnt;
else
cnt = count;
image.height = vc->vc_font.width * cnt;
pitch = ((image.width + 7) >> 3) + scan_align;
pitch &= ~scan_align;
size = pitch * image.height + buf_align;
size &= ~buf_align;
dst = fb_get_buffer_offset(info, &info->pixmap, size);
image.data = dst;
ccw_putcs_aligned(vc, info, s, attribute, cnt, pitch,
width, cellsize, &image, buf, dst);
image.dy += image.height;
count -= cnt;
s -= cnt;
}
/* buf is always NULL except when in monochrome mode, so in this case
it's a gain to check buf against NULL even though kfree() handles
NULL pointers just fine */
if (unlikely(buf))
kfree(buf);
}
static void ccw_clear_margins(struct vc_data *vc, struct fb_info *info,
int color, int bottom_only)
{
unsigned int cw = vc->vc_font.width;
unsigned int ch = vc->vc_font.height;
unsigned int rw = info->var.yres - (vc->vc_cols*cw);
unsigned int bh = info->var.xres - (vc->vc_rows*ch);
unsigned int bs = vc->vc_rows*ch;
struct fb_fillrect region;
region.color = color;
region.rop = ROP_COPY;
if ((int) rw > 0 && !bottom_only) {
region.dx = 0;
region.dy = info->var.yoffset;
region.height = rw;
region.width = info->var.xres_virtual;
info->fbops->fb_fillrect(info, ®ion);
}
if ((int) bh > 0) {
region.dx = info->var.xoffset + bs;
region.dy = 0;
region.height = info->var.yres_virtual;
region.width = bh;
info->fbops->fb_fillrect(info, ®ion);
}
}
static void ccw_cursor(struct vc_data *vc, struct fb_info *info, int mode,
int fg, int bg)
{
struct fb_cursor cursor;
struct fbcon_ops *ops = info->fbcon_par;
unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
int w = (vc->vc_font.height + 7) >> 3, c;
int y = real_y(ops->p, vc->state.y);
int attribute, use_sw = vc->vc_cursor_type & CUR_SW;
int err = 1, dx, dy;
char *src;
u32 vyres = GETVYRES(ops->p, info);
if (!ops->fontbuffer)
return;
cursor.set = 0;
c = scr_readw((u16 *) vc->vc_pos);
attribute = get_attribute(info, c);
src = ops->fontbuffer + ((c & charmask) * (w * vc->vc_font.width));
if (ops->cursor_state.image.data != src ||
ops->cursor_reset) {
ops->cursor_state.image.data = src;
cursor.set |= FB_CUR_SETIMAGE;
}
if (attribute) {
u8 *dst;
dst = kmalloc_array(w, vc->vc_font.width, GFP_ATOMIC);
if (!dst)
return;
kfree(ops->cursor_data);
ops->cursor_data = dst;
ccw_update_attr(dst, src, attribute, vc);
src = dst;
}
if (ops->cursor_state.image.fg_color != fg ||
ops->cursor_state.image.bg_color != bg ||
ops->cursor_reset) {
ops->cursor_state.image.fg_color = fg;
ops->cursor_state.image.bg_color = bg;
cursor.set |= FB_CUR_SETCMAP;
}
if (ops->cursor_state.image.height != vc->vc_font.width ||
ops->cursor_state.image.width != vc->vc_font.height ||
ops->cursor_reset) {
ops->cursor_state.image.height = vc->vc_font.width;
ops->cursor_state.image.width = vc->vc_font.height;
cursor.set |= FB_CUR_SETSIZE;
}
dx = y * vc->vc_font.height;
dy = vyres - ((vc->state.x + 1) * vc->vc_font.width);
if (ops->cursor_state.image.dx != dx ||
ops->cursor_state.image.dy != dy ||
ops->cursor_reset) {
ops->cursor_state.image.dx = dx;
ops->cursor_state.image.dy = dy;
cursor.set |= FB_CUR_SETPOS;
}
if (ops->cursor_state.hot.x || ops->cursor_state.hot.y ||
ops->cursor_reset) {
ops->cursor_state.hot.x = cursor.hot.y = 0;
cursor.set |= FB_CUR_SETHOT;
}
if (cursor.set & FB_CUR_SETSIZE ||
vc->vc_cursor_type != ops->p->cursor_shape ||
ops->cursor_state.mask == NULL ||
ops->cursor_reset) {
char *tmp, *mask = kmalloc_array(w, vc->vc_font.width,
GFP_ATOMIC);
int cur_height, size, i = 0;
int width = (vc->vc_font.width + 7)/8;
if (!mask)
return;
tmp = kmalloc_array(width, vc->vc_font.height, GFP_ATOMIC);
if (!tmp) {
kfree(mask);
return;
}
kfree(ops->cursor_state.mask);
ops->cursor_state.mask = mask;
ops->p->cursor_shape = vc->vc_cursor_type;
cursor.set |= FB_CUR_SETSHAPE;
switch (CUR_SIZE(ops->p->cursor_shape)) {
case CUR_NONE:
cur_height = 0;
break;
case CUR_UNDERLINE:
cur_height = (vc->vc_font.height < 10) ? 1 : 2;
break;
case CUR_LOWER_THIRD:
cur_height = vc->vc_font.height/3;
break;
case CUR_LOWER_HALF:
cur_height = vc->vc_font.height >> 1;
break;
case CUR_TWO_THIRDS:
cur_height = (vc->vc_font.height << 1)/3;
break;
case CUR_BLOCK:
default:
cur_height = vc->vc_font.height;
break;
}
size = (vc->vc_font.height - cur_height) * width;
while (size--)
tmp[i++] = 0;
size = cur_height * width;
while (size--)
tmp[i++] = 0xff;
memset(mask, 0, w * vc->vc_font.width);
rotate_ccw(tmp, mask, vc->vc_font.width, vc->vc_font.height);
kfree(tmp);
}
switch (mode) {
case CM_ERASE:
ops->cursor_state.enable = 0;
break;
case CM_DRAW:
case CM_MOVE:
default:
ops->cursor_state.enable = (use_sw) ? 0 : 1;
break;
}
cursor.image.data = src;
cursor.image.fg_color = ops->cursor_state.image.fg_color;
cursor.image.bg_color = ops->cursor_state.image.bg_color;
cursor.image.dx = ops->cursor_state.image.dx;
cursor.image.dy = ops->cursor_state.image.dy;
cursor.image.height = ops->cursor_state.image.height;
cursor.image.width = ops->cursor_state.image.width;
cursor.hot.x = ops->cursor_state.hot.x;
cursor.hot.y = ops->cursor_state.hot.y;
cursor.mask = ops->cursor_state.mask;
cursor.enable = ops->cursor_state.enable;
cursor.image.depth = 1;
cursor.rop = ROP_XOR;
if (info->fbops->fb_cursor)
err = info->fbops->fb_cursor(info, &cursor);
if (err)
soft_cursor(info, &cursor);
ops->cursor_reset = 0;
}
static int ccw_update_start(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
u32 yoffset;
u32 vyres = GETVYRES(ops->p, info);
int err;
yoffset = (vyres - info->var.yres) - ops->var.xoffset;
ops->var.xoffset = ops->var.yoffset;
ops->var.yoffset = yoffset;
err = fb_pan_display(info, &ops->var);
ops->var.xoffset = info->var.xoffset;
ops->var.yoffset = info->var.yoffset;
ops->var.vmode = info->var.vmode;
return err;
}
void fbcon_rotate_ccw(struct fbcon_ops *ops)
{
ops->bmove = ccw_bmove;
ops->clear = ccw_clear;
ops->putcs = ccw_putcs;
ops->clear_margins = ccw_clear_margins;
ops->cursor = ccw_cursor;
ops->update_start = ccw_update_start;
}
| linux-master | drivers/video/fbdev/core/fbcon_ccw.c |
/*
* linux/drivers/video/fbmon.c
*
* Copyright (C) 2002 James Simmons <[email protected]>
*
* Credits:
*
* The EDID Parser is a conglomeration from the following sources:
*
* 1. SciTech SNAP Graphics Architecture
* Copyright (C) 1991-2002 SciTech Software, Inc. All rights reserved.
*
* 2. XFree86 4.3.0, interpret_edid.c
* Copyright 1998 by Egbert Eich <[email protected]>
*
* 3. John Fremlin <[email protected]> and
* Ani Joshi <[email protected]>
*
* Generalized Timing Formula is derived from:
*
* GTF Spreadsheet by Andy Morrish (1/5/97)
* available at https://www.vesa.org
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
*/
#include <linux/fb.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <video/edid.h>
#include <video/of_videomode.h>
#include <video/videomode.h>
#include "../edid.h"
/*
* EDID parser
*/
#undef DEBUG /* define this for verbose EDID parsing output */
#ifdef DEBUG
#define DPRINTK(fmt, args...) printk(fmt,## args)
#else
#define DPRINTK(fmt, args...) no_printk(fmt, ##args)
#endif
#define FBMON_FIX_HEADER 1
#define FBMON_FIX_INPUT 2
#define FBMON_FIX_TIMINGS 3
#ifdef CONFIG_FB_MODE_HELPERS
struct broken_edid {
u8 manufacturer[4];
u32 model;
u32 fix;
};
static const struct broken_edid brokendb[] = {
/* DEC FR-PCXAV-YZ */
{
.manufacturer = "DEC",
.model = 0x073a,
.fix = FBMON_FIX_HEADER,
},
/* ViewSonic PF775a */
{
.manufacturer = "VSC",
.model = 0x5a44,
.fix = FBMON_FIX_INPUT,
},
/* Sharp UXGA? */
{
.manufacturer = "SHP",
.model = 0x138e,
.fix = FBMON_FIX_TIMINGS,
},
};
static const unsigned char edid_v1_header[] = { 0x00, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0x00
};
static void copy_string(unsigned char *c, unsigned char *s)
{
int i;
c = c + 5;
for (i = 0; (i < 13 && *c != 0x0A); i++)
*(s++) = *(c++);
*s = 0;
while (i-- && (*--s == 0x20)) *s = 0;
}
static int edid_is_serial_block(unsigned char *block)
{
if ((block[0] == 0x00) && (block[1] == 0x00) &&
(block[2] == 0x00) && (block[3] == 0xff) &&
(block[4] == 0x00))
return 1;
else
return 0;
}
static int edid_is_ascii_block(unsigned char *block)
{
if ((block[0] == 0x00) && (block[1] == 0x00) &&
(block[2] == 0x00) && (block[3] == 0xfe) &&
(block[4] == 0x00))
return 1;
else
return 0;
}
static int edid_is_limits_block(unsigned char *block)
{
if ((block[0] == 0x00) && (block[1] == 0x00) &&
(block[2] == 0x00) && (block[3] == 0xfd) &&
(block[4] == 0x00))
return 1;
else
return 0;
}
static int edid_is_monitor_block(unsigned char *block)
{
if ((block[0] == 0x00) && (block[1] == 0x00) &&
(block[2] == 0x00) && (block[3] == 0xfc) &&
(block[4] == 0x00))
return 1;
else
return 0;
}
static int edid_is_timing_block(unsigned char *block)
{
if ((block[0] != 0x00) || (block[1] != 0x00) ||
(block[2] != 0x00) || (block[4] != 0x00))
return 1;
else
return 0;
}
static int check_edid(unsigned char *edid)
{
unsigned char *block = edid + ID_MANUFACTURER_NAME, manufacturer[4];
unsigned char *b;
u32 model;
int i, fix = 0, ret = 0;
manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@';
manufacturer[1] = ((block[0] & 0x03) << 3) +
((block[1] & 0xe0) >> 5) + '@';
manufacturer[2] = (block[1] & 0x1f) + '@';
manufacturer[3] = 0;
model = block[2] + (block[3] << 8);
for (i = 0; i < ARRAY_SIZE(brokendb); i++) {
if (!strncmp(manufacturer, brokendb[i].manufacturer, 4) &&
brokendb[i].model == model) {
fix = brokendb[i].fix;
break;
}
}
switch (fix) {
case FBMON_FIX_HEADER:
for (i = 0; i < 8; i++) {
if (edid[i] != edid_v1_header[i]) {
ret = fix;
break;
}
}
break;
case FBMON_FIX_INPUT:
b = edid + EDID_STRUCT_DISPLAY;
/* Only if display is GTF capable will
the input type be reset to analog */
if (b[4] & 0x01 && b[0] & 0x80)
ret = fix;
break;
case FBMON_FIX_TIMINGS:
b = edid + DETAILED_TIMING_DESCRIPTIONS_START;
ret = fix;
for (i = 0; i < 4; i++) {
if (edid_is_limits_block(b)) {
ret = 0;
break;
}
b += DETAILED_TIMING_DESCRIPTION_SIZE;
}
break;
}
if (ret)
printk("fbmon: The EDID Block of "
"Manufacturer: %s Model: 0x%x is known to "
"be broken,\n", manufacturer, model);
return ret;
}
static void fix_edid(unsigned char *edid, int fix)
{
int i;
unsigned char *b, csum = 0;
switch (fix) {
case FBMON_FIX_HEADER:
printk("fbmon: trying a header reconstruct\n");
memcpy(edid, edid_v1_header, 8);
break;
case FBMON_FIX_INPUT:
printk("fbmon: trying to fix input type\n");
b = edid + EDID_STRUCT_DISPLAY;
b[0] &= ~0x80;
edid[127] += 0x80;
break;
case FBMON_FIX_TIMINGS:
printk("fbmon: trying to fix monitor timings\n");
b = edid + DETAILED_TIMING_DESCRIPTIONS_START;
for (i = 0; i < 4; i++) {
if (!(edid_is_serial_block(b) ||
edid_is_ascii_block(b) ||
edid_is_monitor_block(b) ||
edid_is_timing_block(b))) {
b[0] = 0x00;
b[1] = 0x00;
b[2] = 0x00;
b[3] = 0xfd;
b[4] = 0x00;
b[5] = 60; /* vfmin */
b[6] = 60; /* vfmax */
b[7] = 30; /* hfmin */
b[8] = 75; /* hfmax */
b[9] = 17; /* pixclock - 170 MHz*/
b[10] = 0; /* GTF */
break;
}
b += DETAILED_TIMING_DESCRIPTION_SIZE;
}
for (i = 0; i < EDID_LENGTH - 1; i++)
csum += edid[i];
edid[127] = 256 - csum;
break;
}
}
static int edid_checksum(unsigned char *edid)
{
unsigned char csum = 0, all_null = 0;
int i, err = 0, fix = check_edid(edid);
if (fix)
fix_edid(edid, fix);
for (i = 0; i < EDID_LENGTH; i++) {
csum += edid[i];
all_null |= edid[i];
}
if (csum == 0x00 && all_null) {
/* checksum passed, everything's good */
err = 1;
}
return err;
}
static int edid_check_header(unsigned char *edid)
{
int i, err = 1, fix = check_edid(edid);
if (fix)
fix_edid(edid, fix);
for (i = 0; i < 8; i++) {
if (edid[i] != edid_v1_header[i])
err = 0;
}
return err;
}
static void parse_vendor_block(unsigned char *block, struct fb_monspecs *specs)
{
specs->manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@';
specs->manufacturer[1] = ((block[0] & 0x03) << 3) +
((block[1] & 0xe0) >> 5) + '@';
specs->manufacturer[2] = (block[1] & 0x1f) + '@';
specs->manufacturer[3] = 0;
specs->model = block[2] + (block[3] << 8);
specs->serial = block[4] + (block[5] << 8) +
(block[6] << 16) + (block[7] << 24);
specs->year = block[9] + 1990;
specs->week = block[8];
DPRINTK(" Manufacturer: %s\n", specs->manufacturer);
DPRINTK(" Model: %x\n", specs->model);
DPRINTK(" Serial#: %u\n", specs->serial);
DPRINTK(" Year: %u Week %u\n", specs->year, specs->week);
}
static void get_dpms_capabilities(unsigned char flags,
struct fb_monspecs *specs)
{
specs->dpms = 0;
if (flags & DPMS_ACTIVE_OFF)
specs->dpms |= FB_DPMS_ACTIVE_OFF;
if (flags & DPMS_SUSPEND)
specs->dpms |= FB_DPMS_SUSPEND;
if (flags & DPMS_STANDBY)
specs->dpms |= FB_DPMS_STANDBY;
DPRINTK(" DPMS: Active %s, Suspend %s, Standby %s\n",
(flags & DPMS_ACTIVE_OFF) ? "yes" : "no",
(flags & DPMS_SUSPEND) ? "yes" : "no",
(flags & DPMS_STANDBY) ? "yes" : "no");
}
static void get_chroma(unsigned char *block, struct fb_monspecs *specs)
{
int tmp;
DPRINTK(" Chroma\n");
/* Chromaticity data */
tmp = ((block[5] & (3 << 6)) >> 6) | (block[0x7] << 2);
tmp *= 1000;
tmp += 512;
specs->chroma.redx = tmp/1024;
DPRINTK(" RedX: 0.%03d ", specs->chroma.redx);
tmp = ((block[5] & (3 << 4)) >> 4) | (block[0x8] << 2);
tmp *= 1000;
tmp += 512;
specs->chroma.redy = tmp/1024;
DPRINTK("RedY: 0.%03d\n", specs->chroma.redy);
tmp = ((block[5] & (3 << 2)) >> 2) | (block[0x9] << 2);
tmp *= 1000;
tmp += 512;
specs->chroma.greenx = tmp/1024;
DPRINTK(" GreenX: 0.%03d ", specs->chroma.greenx);
tmp = (block[5] & 3) | (block[0xa] << 2);
tmp *= 1000;
tmp += 512;
specs->chroma.greeny = tmp/1024;
DPRINTK("GreenY: 0.%03d\n", specs->chroma.greeny);
tmp = ((block[6] & (3 << 6)) >> 6) | (block[0xb] << 2);
tmp *= 1000;
tmp += 512;
specs->chroma.bluex = tmp/1024;
DPRINTK(" BlueX: 0.%03d ", specs->chroma.bluex);
tmp = ((block[6] & (3 << 4)) >> 4) | (block[0xc] << 2);
tmp *= 1000;
tmp += 512;
specs->chroma.bluey = tmp/1024;
DPRINTK("BlueY: 0.%03d\n", specs->chroma.bluey);
tmp = ((block[6] & (3 << 2)) >> 2) | (block[0xd] << 2);
tmp *= 1000;
tmp += 512;
specs->chroma.whitex = tmp/1024;
DPRINTK(" WhiteX: 0.%03d ", specs->chroma.whitex);
tmp = (block[6] & 3) | (block[0xe] << 2);
tmp *= 1000;
tmp += 512;
specs->chroma.whitey = tmp/1024;
DPRINTK("WhiteY: 0.%03d\n", specs->chroma.whitey);
}
static void calc_mode_timings(int xres, int yres, int refresh,
struct fb_videomode *mode)
{
struct fb_var_screeninfo *var;
var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
if (var) {
var->xres = xres;
var->yres = yres;
fb_get_mode(FB_VSYNCTIMINGS | FB_IGNOREMON,
refresh, var, NULL);
mode->xres = xres;
mode->yres = yres;
mode->pixclock = var->pixclock;
mode->refresh = refresh;
mode->left_margin = var->left_margin;
mode->right_margin = var->right_margin;
mode->upper_margin = var->upper_margin;
mode->lower_margin = var->lower_margin;
mode->hsync_len = var->hsync_len;
mode->vsync_len = var->vsync_len;
mode->vmode = 0;
mode->sync = 0;
kfree(var);
}
}
static int get_est_timing(unsigned char *block, struct fb_videomode *mode)
{
int num = 0;
unsigned char c;
c = block[0];
if (c&0x80) {
calc_mode_timings(720, 400, 70, &mode[num]);
mode[num++].flag = FB_MODE_IS_CALCULATED;
DPRINTK(" 720x400@70Hz\n");
}
if (c&0x40) {
calc_mode_timings(720, 400, 88, &mode[num]);
mode[num++].flag = FB_MODE_IS_CALCULATED;
DPRINTK(" 720x400@88Hz\n");
}
if (c&0x20) {
mode[num++] = vesa_modes[3];
DPRINTK(" 640x480@60Hz\n");
}
if (c&0x10) {
calc_mode_timings(640, 480, 67, &mode[num]);
mode[num++].flag = FB_MODE_IS_CALCULATED;
DPRINTK(" 640x480@67Hz\n");
}
if (c&0x08) {
mode[num++] = vesa_modes[4];
DPRINTK(" 640x480@72Hz\n");
}
if (c&0x04) {
mode[num++] = vesa_modes[5];
DPRINTK(" 640x480@75Hz\n");
}
if (c&0x02) {
mode[num++] = vesa_modes[7];
DPRINTK(" 800x600@56Hz\n");
}
if (c&0x01) {
mode[num++] = vesa_modes[8];
DPRINTK(" 800x600@60Hz\n");
}
c = block[1];
if (c&0x80) {
mode[num++] = vesa_modes[9];
DPRINTK(" 800x600@72Hz\n");
}
if (c&0x40) {
mode[num++] = vesa_modes[10];
DPRINTK(" 800x600@75Hz\n");
}
if (c&0x20) {
calc_mode_timings(832, 624, 75, &mode[num]);
mode[num++].flag = FB_MODE_IS_CALCULATED;
DPRINTK(" 832x624@75Hz\n");
}
if (c&0x10) {
mode[num++] = vesa_modes[12];
DPRINTK(" 1024x768@87Hz Interlaced\n");
}
if (c&0x08) {
mode[num++] = vesa_modes[13];
DPRINTK(" 1024x768@60Hz\n");
}
if (c&0x04) {
mode[num++] = vesa_modes[14];
DPRINTK(" 1024x768@70Hz\n");
}
if (c&0x02) {
mode[num++] = vesa_modes[15];
DPRINTK(" 1024x768@75Hz\n");
}
if (c&0x01) {
mode[num++] = vesa_modes[21];
DPRINTK(" 1280x1024@75Hz\n");
}
c = block[2];
if (c&0x80) {
mode[num++] = vesa_modes[17];
DPRINTK(" 1152x870@75Hz\n");
}
DPRINTK(" Manufacturer's mask: %x\n",c&0x7F);
return num;
}
static int get_std_timing(unsigned char *block, struct fb_videomode *mode,
int ver, int rev, const struct fb_monspecs *specs)
{
int i;
for (i = 0; i < DMT_SIZE; i++) {
u32 std_2byte_code = block[0] << 8 | block[1];
if (std_2byte_code == dmt_modes[i].std_2byte_code)
break;
}
if (i < DMT_SIZE && dmt_modes[i].mode) {
/* DMT mode found */
*mode = *dmt_modes[i].mode;
mode->flag |= FB_MODE_IS_STANDARD;
DPRINTK(" DMT id=%d\n", dmt_modes[i].dmt_id);
} else {
int xres, yres = 0, refresh, ratio;
xres = (block[0] + 31) * 8;
if (xres <= 256)
return 0;
ratio = (block[1] & 0xc0) >> 6;
switch (ratio) {
case 0:
/* in EDID 1.3 the meaning of 0 changed to 16:10 (prior 1:1) */
if (ver < 1 || (ver == 1 && rev < 3))
yres = xres;
else
yres = (xres * 10)/16;
break;
case 1:
yres = (xres * 3)/4;
break;
case 2:
yres = (xres * 4)/5;
break;
case 3:
yres = (xres * 9)/16;
break;
}
refresh = (block[1] & 0x3f) + 60;
DPRINTK(" %dx%d@%dHz\n", xres, yres, refresh);
calc_mode_timings(xres, yres, refresh, mode);
}
/* Check the mode we got is within valid spec of the monitor */
if (specs && specs->dclkmax
&& PICOS2KHZ(mode->pixclock) * 1000 > specs->dclkmax) {
DPRINTK(" mode exceed max DCLK\n");
return 0;
}
return 1;
}
static int get_dst_timing(unsigned char *block, struct fb_videomode *mode,
int ver, int rev, const struct fb_monspecs *specs)
{
int j, num = 0;
for (j = 0; j < 6; j++, block += STD_TIMING_DESCRIPTION_SIZE)
num += get_std_timing(block, &mode[num], ver, rev, specs);
return num;
}
static void get_detailed_timing(unsigned char *block,
struct fb_videomode *mode)
{
mode->xres = H_ACTIVE;
mode->yres = V_ACTIVE;
mode->pixclock = PIXEL_CLOCK;
mode->pixclock /= 1000;
mode->pixclock = KHZ2PICOS(mode->pixclock);
mode->right_margin = H_SYNC_OFFSET;
mode->left_margin = (H_ACTIVE + H_BLANKING) -
(H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
mode->upper_margin = V_BLANKING - V_SYNC_OFFSET -
V_SYNC_WIDTH;
mode->lower_margin = V_SYNC_OFFSET;
mode->hsync_len = H_SYNC_WIDTH;
mode->vsync_len = V_SYNC_WIDTH;
if (HSYNC_POSITIVE)
mode->sync |= FB_SYNC_HOR_HIGH_ACT;
if (VSYNC_POSITIVE)
mode->sync |= FB_SYNC_VERT_HIGH_ACT;
mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) *
(V_ACTIVE + V_BLANKING));
if (INTERLACED) {
mode->yres *= 2;
mode->upper_margin *= 2;
mode->lower_margin *= 2;
mode->vsync_len *= 2;
mode->vmode |= FB_VMODE_INTERLACED;
}
mode->flag = FB_MODE_IS_DETAILED;
DPRINTK(" %d MHz ", PIXEL_CLOCK/1000000);
DPRINTK("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET,
H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING);
DPRINTK("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET,
V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING);
DPRINTK("%sHSync %sVSync\n\n", (HSYNC_POSITIVE) ? "+" : "-",
(VSYNC_POSITIVE) ? "+" : "-");
}
/**
* fb_create_modedb - create video mode database
* @edid: EDID data
* @dbsize: database size
* @specs: monitor specifications, may be NULL
*
* RETURNS: struct fb_videomode, @dbsize contains length of database
*
* DESCRIPTION:
* This function builds a mode database using the contents of the EDID
* data
*/
static struct fb_videomode *fb_create_modedb(unsigned char *edid, int *dbsize,
const struct fb_monspecs *specs)
{
struct fb_videomode *mode, *m;
unsigned char *block;
int num = 0, i, first = 1;
int ver, rev;
mode = kcalloc(50, sizeof(struct fb_videomode), GFP_KERNEL);
if (mode == NULL)
return NULL;
if (edid == NULL || !edid_checksum(edid) ||
!edid_check_header(edid)) {
kfree(mode);
return NULL;
}
ver = edid[EDID_STRUCT_VERSION];
rev = edid[EDID_STRUCT_REVISION];
*dbsize = 0;
DPRINTK(" Detailed Timings\n");
block = edid + DETAILED_TIMING_DESCRIPTIONS_START;
for (i = 0; i < 4; i++, block+= DETAILED_TIMING_DESCRIPTION_SIZE) {
if (!(block[0] == 0x00 && block[1] == 0x00)) {
get_detailed_timing(block, &mode[num]);
if (first) {
mode[num].flag |= FB_MODE_IS_FIRST;
first = 0;
}
num++;
}
}
DPRINTK(" Supported VESA Modes\n");
block = edid + ESTABLISHED_TIMING_1;
num += get_est_timing(block, &mode[num]);
DPRINTK(" Standard Timings\n");
block = edid + STD_TIMING_DESCRIPTIONS_START;
for (i = 0; i < STD_TIMING; i++, block += STD_TIMING_DESCRIPTION_SIZE)
num += get_std_timing(block, &mode[num], ver, rev, specs);
block = edid + DETAILED_TIMING_DESCRIPTIONS_START;
for (i = 0; i < 4; i++, block+= DETAILED_TIMING_DESCRIPTION_SIZE) {
if (block[0] == 0x00 && block[1] == 0x00 && block[3] == 0xfa)
num += get_dst_timing(block + 5, &mode[num],
ver, rev, specs);
}
/* Yikes, EDID data is totally useless */
if (!num) {
kfree(mode);
return NULL;
}
*dbsize = num;
m = kmalloc_array(num, sizeof(struct fb_videomode), GFP_KERNEL);
if (!m)
return mode;
memmove(m, mode, num * sizeof(struct fb_videomode));
kfree(mode);
return m;
}
/**
* fb_destroy_modedb - destroys mode database
* @modedb: mode database to destroy
*
* DESCRIPTION:
* Destroy mode database created by fb_create_modedb
*/
void fb_destroy_modedb(struct fb_videomode *modedb)
{
kfree(modedb);
}
static int fb_get_monitor_limits(unsigned char *edid, struct fb_monspecs *specs)
{
int i, retval = 1;
unsigned char *block;
block = edid + DETAILED_TIMING_DESCRIPTIONS_START;
DPRINTK(" Monitor Operating Limits: ");
for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) {
if (edid_is_limits_block(block)) {
specs->hfmin = H_MIN_RATE * 1000;
specs->hfmax = H_MAX_RATE * 1000;
specs->vfmin = V_MIN_RATE;
specs->vfmax = V_MAX_RATE;
specs->dclkmax = MAX_PIXEL_CLOCK * 1000000;
specs->gtf = (GTF_SUPPORT) ? 1 : 0;
retval = 0;
DPRINTK("From EDID\n");
break;
}
}
/* estimate monitor limits based on modes supported */
if (retval) {
struct fb_videomode *modes, *mode;
int num_modes, hz, hscan, pixclock;
int vtotal, htotal;
modes = fb_create_modedb(edid, &num_modes, specs);
if (!modes) {
DPRINTK("None Available\n");
return 1;
}
retval = 0;
for (i = 0; i < num_modes; i++) {
mode = &modes[i];
pixclock = PICOS2KHZ(modes[i].pixclock) * 1000;
htotal = mode->xres + mode->right_margin + mode->hsync_len
+ mode->left_margin;
vtotal = mode->yres + mode->lower_margin + mode->vsync_len
+ mode->upper_margin;
if (mode->vmode & FB_VMODE_INTERLACED)
vtotal /= 2;
if (mode->vmode & FB_VMODE_DOUBLE)
vtotal *= 2;
hscan = (pixclock + htotal / 2) / htotal;
hscan = (hscan + 500) / 1000 * 1000;
hz = (hscan + vtotal / 2) / vtotal;
if (specs->dclkmax == 0 || specs->dclkmax < pixclock)
specs->dclkmax = pixclock;
if (specs->dclkmin == 0 || specs->dclkmin > pixclock)
specs->dclkmin = pixclock;
if (specs->hfmax == 0 || specs->hfmax < hscan)
specs->hfmax = hscan;
if (specs->hfmin == 0 || specs->hfmin > hscan)
specs->hfmin = hscan;
if (specs->vfmax == 0 || specs->vfmax < hz)
specs->vfmax = hz;
if (specs->vfmin == 0 || specs->vfmin > hz)
specs->vfmin = hz;
}
DPRINTK("Extrapolated\n");
fb_destroy_modedb(modes);
}
DPRINTK(" H: %d-%dKHz V: %d-%dHz DCLK: %dMHz\n",
specs->hfmin/1000, specs->hfmax/1000, specs->vfmin,
specs->vfmax, specs->dclkmax/1000000);
return retval;
}
static void get_monspecs(unsigned char *edid, struct fb_monspecs *specs)
{
unsigned char c, *block;
block = edid + EDID_STRUCT_DISPLAY;
fb_get_monitor_limits(edid, specs);
c = block[0] & 0x80;
specs->input = 0;
if (c) {
specs->input |= FB_DISP_DDI;
DPRINTK(" Digital Display Input");
} else {
DPRINTK(" Analog Display Input: Input Voltage - ");
switch ((block[0] & 0x60) >> 5) {
case 0:
DPRINTK("0.700V/0.300V");
specs->input |= FB_DISP_ANA_700_300;
break;
case 1:
DPRINTK("0.714V/0.286V");
specs->input |= FB_DISP_ANA_714_286;
break;
case 2:
DPRINTK("1.000V/0.400V");
specs->input |= FB_DISP_ANA_1000_400;
break;
case 3:
DPRINTK("0.700V/0.000V");
specs->input |= FB_DISP_ANA_700_000;
break;
}
}
DPRINTK("\n Sync: ");
c = block[0] & 0x10;
if (c)
DPRINTK(" Configurable signal level\n");
c = block[0] & 0x0f;
specs->signal = 0;
if (c & 0x10) {
DPRINTK("Blank to Blank ");
specs->signal |= FB_SIGNAL_BLANK_BLANK;
}
if (c & 0x08) {
DPRINTK("Separate ");
specs->signal |= FB_SIGNAL_SEPARATE;
}
if (c & 0x04) {
DPRINTK("Composite ");
specs->signal |= FB_SIGNAL_COMPOSITE;
}
if (c & 0x02) {
DPRINTK("Sync on Green ");
specs->signal |= FB_SIGNAL_SYNC_ON_GREEN;
}
if (c & 0x01) {
DPRINTK("Serration on ");
specs->signal |= FB_SIGNAL_SERRATION_ON;
}
DPRINTK("\n");
specs->max_x = block[1];
specs->max_y = block[2];
DPRINTK(" Max H-size in cm: ");
if (specs->max_x)
DPRINTK("%d\n", specs->max_x);
else
DPRINTK("variable\n");
DPRINTK(" Max V-size in cm: ");
if (specs->max_y)
DPRINTK("%d\n", specs->max_y);
else
DPRINTK("variable\n");
c = block[3];
specs->gamma = c+100;
DPRINTK(" Gamma: ");
DPRINTK("%d.%d\n", specs->gamma/100, specs->gamma % 100);
get_dpms_capabilities(block[4], specs);
switch ((block[4] & 0x18) >> 3) {
case 0:
DPRINTK(" Monochrome/Grayscale\n");
specs->input |= FB_DISP_MONO;
break;
case 1:
DPRINTK(" RGB Color Display\n");
specs->input |= FB_DISP_RGB;
break;
case 2:
DPRINTK(" Non-RGB Multicolor Display\n");
specs->input |= FB_DISP_MULTI;
break;
default:
DPRINTK(" Unknown\n");
specs->input |= FB_DISP_UNKNOWN;
break;
}
get_chroma(block, specs);
specs->misc = 0;
c = block[4] & 0x7;
if (c & 0x04) {
DPRINTK(" Default color format is primary\n");
specs->misc |= FB_MISC_PRIM_COLOR;
}
if (c & 0x02) {
DPRINTK(" First DETAILED Timing is preferred\n");
specs->misc |= FB_MISC_1ST_DETAIL;
}
if (c & 0x01) {
printk(" Display is GTF capable\n");
specs->gtf = 1;
}
}
int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var)
{
int i;
unsigned char *block;
if (edid == NULL || var == NULL)
return 1;
if (!(edid_checksum(edid)))
return 1;
if (!(edid_check_header(edid)))
return 1;
block = edid + DETAILED_TIMING_DESCRIPTIONS_START;
for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) {
if (edid_is_timing_block(block)) {
var->xres = var->xres_virtual = H_ACTIVE;
var->yres = var->yres_virtual = V_ACTIVE;
var->height = var->width = 0;
var->right_margin = H_SYNC_OFFSET;
var->left_margin = (H_ACTIVE + H_BLANKING) -
(H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
var->upper_margin = V_BLANKING - V_SYNC_OFFSET -
V_SYNC_WIDTH;
var->lower_margin = V_SYNC_OFFSET;
var->hsync_len = H_SYNC_WIDTH;
var->vsync_len = V_SYNC_WIDTH;
var->pixclock = PIXEL_CLOCK;
var->pixclock /= 1000;
var->pixclock = KHZ2PICOS(var->pixclock);
if (HSYNC_POSITIVE)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (VSYNC_POSITIVE)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
return 0;
}
}
return 1;
}
void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs)
{
unsigned char *block;
int i, found = 0;
if (edid == NULL)
return;
if (!(edid_checksum(edid)))
return;
if (!(edid_check_header(edid)))
return;
memset(specs, 0, sizeof(struct fb_monspecs));
specs->version = edid[EDID_STRUCT_VERSION];
specs->revision = edid[EDID_STRUCT_REVISION];
DPRINTK("========================================\n");
DPRINTK("Display Information (EDID)\n");
DPRINTK("========================================\n");
DPRINTK(" EDID Version %d.%d\n", (int) specs->version,
(int) specs->revision);
parse_vendor_block(edid + ID_MANUFACTURER_NAME, specs);
block = edid + DETAILED_TIMING_DESCRIPTIONS_START;
for (i = 0; i < 4; i++, block += DETAILED_TIMING_DESCRIPTION_SIZE) {
if (edid_is_serial_block(block)) {
copy_string(block, specs->serial_no);
DPRINTK(" Serial Number: %s\n", specs->serial_no);
} else if (edid_is_ascii_block(block)) {
copy_string(block, specs->ascii);
DPRINTK(" ASCII Block: %s\n", specs->ascii);
} else if (edid_is_monitor_block(block)) {
copy_string(block, specs->monitor);
DPRINTK(" Monitor Name: %s\n", specs->monitor);
}
}
DPRINTK(" Display Characteristics:\n");
get_monspecs(edid, specs);
specs->modedb = fb_create_modedb(edid, &specs->modedb_len, specs);
if (!specs->modedb)
return;
/*
* Workaround for buggy EDIDs that sets that the first
* detailed timing is preferred but has not detailed
* timing specified
*/
for (i = 0; i < specs->modedb_len; i++) {
if (specs->modedb[i].flag & FB_MODE_IS_DETAILED) {
found = 1;
break;
}
}
if (!found)
specs->misc &= ~FB_MISC_1ST_DETAIL;
DPRINTK("========================================\n");
}
/*
* VESA Generalized Timing Formula (GTF)
*/
#define FLYBACK 550
#define V_FRONTPORCH 1
#define H_OFFSET 40
#define H_SCALEFACTOR 20
#define H_BLANKSCALE 128
#define H_GRADIENT 600
#define C_VAL 30
#define M_VAL 300
struct __fb_timings {
u32 dclk;
u32 hfreq;
u32 vfreq;
u32 hactive;
u32 vactive;
u32 hblank;
u32 vblank;
u32 htotal;
u32 vtotal;
};
/**
* fb_get_vblank - get vertical blank time
* @hfreq: horizontal freq
*
* DESCRIPTION:
* vblank = right_margin + vsync_len + left_margin
*
* given: right_margin = 1 (V_FRONTPORCH)
* vsync_len = 3
* flyback = 550
*
* flyback * hfreq
* left_margin = --------------- - vsync_len
* 1000000
*/
static u32 fb_get_vblank(u32 hfreq)
{
u32 vblank;
vblank = (hfreq * FLYBACK)/1000;
vblank = (vblank + 500)/1000;
return (vblank + V_FRONTPORCH);
}
/**
* fb_get_hblank_by_hfreq - get horizontal blank time given hfreq
* @hfreq: horizontal freq
* @xres: horizontal resolution in pixels
*
* DESCRIPTION:
*
* xres * duty_cycle
* hblank = ------------------
* 100 - duty_cycle
*
* duty cycle = percent of htotal assigned to inactive display
* duty cycle = C - (M/Hfreq)
*
* where: C = ((offset - scale factor) * blank_scale)
* -------------------------------------- + scale factor
* 256
* M = blank_scale * gradient
*
*/
static u32 fb_get_hblank_by_hfreq(u32 hfreq, u32 xres)
{
u32 c_val, m_val, duty_cycle, hblank;
c_val = (((H_OFFSET - H_SCALEFACTOR) * H_BLANKSCALE)/256 +
H_SCALEFACTOR) * 1000;
m_val = (H_BLANKSCALE * H_GRADIENT)/256;
m_val = (m_val * 1000000)/hfreq;
duty_cycle = c_val - m_val;
hblank = (xres * duty_cycle)/(100000 - duty_cycle);
return (hblank);
}
/**
* fb_get_hblank_by_dclk - get horizontal blank time given pixelclock
* @dclk: pixelclock in Hz
* @xres: horizontal resolution in pixels
*
* DESCRIPTION:
*
* xres * duty_cycle
* hblank = ------------------
* 100 - duty_cycle
*
* duty cycle = percent of htotal assigned to inactive display
* duty cycle = C - (M * h_period)
*
* where: h_period = SQRT(100 - C + (0.4 * xres * M)/dclk) + C - 100
* -----------------------------------------------
* 2 * M
* M = 300;
* C = 30;
*/
static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres)
{
u32 duty_cycle, h_period, hblank;
dclk /= 1000;
h_period = 100 - C_VAL;
h_period *= h_period;
h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk);
h_period *= 10000;
h_period = int_sqrt(h_period);
h_period -= (100 - C_VAL) * 100;
h_period *= 1000;
h_period /= 2 * M_VAL;
duty_cycle = C_VAL * 1000 - (M_VAL * h_period)/100;
hblank = (xres * duty_cycle)/(100000 - duty_cycle) + 8;
hblank &= ~15;
return (hblank);
}
/**
* fb_get_hfreq - estimate hsync
* @vfreq: vertical refresh rate
* @yres: vertical resolution
*
* DESCRIPTION:
*
* (yres + front_port) * vfreq * 1000000
* hfreq = -------------------------------------
* (1000000 - (vfreq * FLYBACK)
*
*/
static u32 fb_get_hfreq(u32 vfreq, u32 yres)
{
u32 divisor, hfreq;
divisor = (1000000 - (vfreq * FLYBACK))/1000;
hfreq = (yres + V_FRONTPORCH) * vfreq * 1000;
return (hfreq/divisor);
}
static void fb_timings_vfreq(struct __fb_timings *timings)
{
timings->hfreq = fb_get_hfreq(timings->vfreq, timings->vactive);
timings->vblank = fb_get_vblank(timings->hfreq);
timings->vtotal = timings->vactive + timings->vblank;
timings->hblank = fb_get_hblank_by_hfreq(timings->hfreq,
timings->hactive);
timings->htotal = timings->hactive + timings->hblank;
timings->dclk = timings->htotal * timings->hfreq;
}
static void fb_timings_hfreq(struct __fb_timings *timings)
{
timings->vblank = fb_get_vblank(timings->hfreq);
timings->vtotal = timings->vactive + timings->vblank;
timings->vfreq = timings->hfreq/timings->vtotal;
timings->hblank = fb_get_hblank_by_hfreq(timings->hfreq,
timings->hactive);
timings->htotal = timings->hactive + timings->hblank;
timings->dclk = timings->htotal * timings->hfreq;
}
static void fb_timings_dclk(struct __fb_timings *timings)
{
timings->hblank = fb_get_hblank_by_dclk(timings->dclk,
timings->hactive);
timings->htotal = timings->hactive + timings->hblank;
timings->hfreq = timings->dclk/timings->htotal;
timings->vblank = fb_get_vblank(timings->hfreq);
timings->vtotal = timings->vactive + timings->vblank;
timings->vfreq = timings->hfreq/timings->vtotal;
}
/*
* fb_get_mode - calculates video mode using VESA GTF
* @flags: if: 0 - maximize vertical refresh rate
* 1 - vrefresh-driven calculation;
* 2 - hscan-driven calculation;
* 3 - pixelclock-driven calculation;
* @val: depending on @flags, ignored, vrefresh, hsync or pixelclock
* @var: pointer to fb_var_screeninfo
* @info: pointer to fb_info
*
* DESCRIPTION:
* Calculates video mode based on monitor specs using VESA GTF.
* The GTF is best for VESA GTF compliant monitors but is
* specifically formulated to work for older monitors as well.
*
* If @flag==0, the function will attempt to maximize the
* refresh rate. Otherwise, it will calculate timings based on
* the flag and accompanying value.
*
* If FB_IGNOREMON bit is set in @flags, monitor specs will be
* ignored and @var will be filled with the calculated timings.
*
* All calculations are based on the VESA GTF Spreadsheet
* available at VESA's public ftp (https://www.vesa.org).
*
* NOTES:
* The timings generated by the GTF will be different from VESA
* DMT. It might be a good idea to keep a table of standard
* VESA modes as well. The GTF may also not work for some displays,
* such as, and especially, analog TV.
*
* REQUIRES:
* A valid info->monspecs, otherwise 'safe numbers' will be used.
*/
int fb_get_mode(int flags, u32 val, struct fb_var_screeninfo *var, struct fb_info *info)
{
struct __fb_timings *timings;
u32 interlace = 1, dscan = 1;
u32 hfmin, hfmax, vfmin, vfmax, dclkmin, dclkmax, err = 0;
timings = kzalloc(sizeof(struct __fb_timings), GFP_KERNEL);
if (!timings)
return -ENOMEM;
/*
* If monspecs are invalid, use values that are enough
* for 640x480@60
*/
if (!info || !info->monspecs.hfmax || !info->monspecs.vfmax ||
!info->monspecs.dclkmax ||
info->monspecs.hfmax < info->monspecs.hfmin ||
info->monspecs.vfmax < info->monspecs.vfmin ||
info->monspecs.dclkmax < info->monspecs.dclkmin) {
hfmin = 29000; hfmax = 30000;
vfmin = 60; vfmax = 60;
dclkmin = 0; dclkmax = 25000000;
} else {
hfmin = info->monspecs.hfmin;
hfmax = info->monspecs.hfmax;
vfmin = info->monspecs.vfmin;
vfmax = info->monspecs.vfmax;
dclkmin = info->monspecs.dclkmin;
dclkmax = info->monspecs.dclkmax;
}
timings->hactive = var->xres;
timings->vactive = var->yres;
if (var->vmode & FB_VMODE_INTERLACED) {
timings->vactive /= 2;
interlace = 2;
}
if (var->vmode & FB_VMODE_DOUBLE) {
timings->vactive *= 2;
dscan = 2;
}
switch (flags & ~FB_IGNOREMON) {
case FB_MAXTIMINGS: /* maximize refresh rate */
timings->hfreq = hfmax;
fb_timings_hfreq(timings);
if (timings->vfreq > vfmax) {
timings->vfreq = vfmax;
fb_timings_vfreq(timings);
}
if (timings->dclk > dclkmax) {
timings->dclk = dclkmax;
fb_timings_dclk(timings);
}
break;
case FB_VSYNCTIMINGS: /* vrefresh driven */
timings->vfreq = val;
fb_timings_vfreq(timings);
break;
case FB_HSYNCTIMINGS: /* hsync driven */
timings->hfreq = val;
fb_timings_hfreq(timings);
break;
case FB_DCLKTIMINGS: /* pixelclock driven */
timings->dclk = PICOS2KHZ(val) * 1000;
fb_timings_dclk(timings);
break;
default:
err = -EINVAL;
}
if (err || (!(flags & FB_IGNOREMON) &&
(timings->vfreq < vfmin || timings->vfreq > vfmax ||
timings->hfreq < hfmin || timings->hfreq > hfmax ||
timings->dclk < dclkmin || timings->dclk > dclkmax))) {
err = -EINVAL;
} else {
var->pixclock = KHZ2PICOS(timings->dclk/1000);
var->hsync_len = (timings->htotal * 8)/100;
var->right_margin = (timings->hblank/2) - var->hsync_len;
var->left_margin = timings->hblank - var->right_margin -
var->hsync_len;
var->vsync_len = (3 * interlace)/dscan;
var->lower_margin = (1 * interlace)/dscan;
var->upper_margin = (timings->vblank * interlace)/dscan -
(var->vsync_len + var->lower_margin);
}
kfree(timings);
return err;
}
#ifdef CONFIG_VIDEOMODE_HELPERS
int fb_videomode_from_videomode(const struct videomode *vm,
struct fb_videomode *fbmode)
{
unsigned int htotal, vtotal;
fbmode->xres = vm->hactive;
fbmode->left_margin = vm->hback_porch;
fbmode->right_margin = vm->hfront_porch;
fbmode->hsync_len = vm->hsync_len;
fbmode->yres = vm->vactive;
fbmode->upper_margin = vm->vback_porch;
fbmode->lower_margin = vm->vfront_porch;
fbmode->vsync_len = vm->vsync_len;
/* prevent division by zero in KHZ2PICOS macro */
fbmode->pixclock = vm->pixelclock ?
KHZ2PICOS(vm->pixelclock / 1000) : 0;
fbmode->sync = 0;
fbmode->vmode = 0;
if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
fbmode->sync |= FB_SYNC_HOR_HIGH_ACT;
if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
fbmode->sync |= FB_SYNC_VERT_HIGH_ACT;
if (vm->flags & DISPLAY_FLAGS_INTERLACED)
fbmode->vmode |= FB_VMODE_INTERLACED;
if (vm->flags & DISPLAY_FLAGS_DOUBLESCAN)
fbmode->vmode |= FB_VMODE_DOUBLE;
fbmode->flag = 0;
htotal = vm->hactive + vm->hfront_porch + vm->hback_porch +
vm->hsync_len;
vtotal = vm->vactive + vm->vfront_porch + vm->vback_porch +
vm->vsync_len;
/* prevent division by zero */
if (htotal && vtotal) {
fbmode->refresh = vm->pixelclock / (htotal * vtotal);
/* a mode must have htotal and vtotal != 0 or it is invalid */
} else {
fbmode->refresh = 0;
return -EINVAL;
}
return 0;
}
EXPORT_SYMBOL_GPL(fb_videomode_from_videomode);
#ifdef CONFIG_OF
static inline void dump_fb_videomode(const struct fb_videomode *m)
{
pr_debug("fb_videomode = %ux%u@%uHz (%ukHz) %u %u %u %u %u %u %u %u %u\n",
m->xres, m->yres, m->refresh, m->pixclock, m->left_margin,
m->right_margin, m->upper_margin, m->lower_margin,
m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
}
/**
* of_get_fb_videomode - get a fb_videomode from devicetree
* @np: device_node with the timing specification
* @fb: will be set to the return value
* @index: index into the list of display timings in devicetree
*
* DESCRIPTION:
* This function is expensive and should only be used, if only one mode is to be
* read from DT. To get multiple modes start with of_get_display_timings ond
* work with that instead.
*/
int of_get_fb_videomode(struct device_node *np, struct fb_videomode *fb,
int index)
{
struct videomode vm;
int ret;
ret = of_get_videomode(np, &vm, index);
if (ret)
return ret;
ret = fb_videomode_from_videomode(&vm, fb);
if (ret)
return ret;
pr_debug("%pOF: got %dx%d display mode\n",
np, vm.hactive, vm.vactive);
dump_fb_videomode(fb);
return 0;
}
EXPORT_SYMBOL_GPL(of_get_fb_videomode);
#endif /* CONFIG_OF */
#endif /* CONFIG_VIDEOMODE_HELPERS */
#else
int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var)
{
return 1;
}
void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs)
{
}
void fb_destroy_modedb(struct fb_videomode *modedb)
{
}
int fb_get_mode(int flags, u32 val, struct fb_var_screeninfo *var,
struct fb_info *info)
{
return -EINVAL;
}
#endif /* CONFIG_FB_MODE_HELPERS */
/*
* fb_validate_mode - validates var against monitor capabilities
* @var: pointer to fb_var_screeninfo
* @info: pointer to fb_info
*
* DESCRIPTION:
* Validates video mode against monitor capabilities specified in
* info->monspecs.
*
* REQUIRES:
* A valid info->monspecs.
*/
int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info)
{
u32 hfreq, vfreq, htotal, vtotal, pixclock;
u32 hfmin, hfmax, vfmin, vfmax, dclkmin, dclkmax;
/*
* If monspecs are invalid, use values that are enough
* for 640x480@60
*/
if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
!info->monspecs.dclkmax ||
info->monspecs.hfmax < info->monspecs.hfmin ||
info->monspecs.vfmax < info->monspecs.vfmin ||
info->monspecs.dclkmax < info->monspecs.dclkmin) {
hfmin = 29000; hfmax = 30000;
vfmin = 60; vfmax = 60;
dclkmin = 0; dclkmax = 25000000;
} else {
hfmin = info->monspecs.hfmin;
hfmax = info->monspecs.hfmax;
vfmin = info->monspecs.vfmin;
vfmax = info->monspecs.vfmax;
dclkmin = info->monspecs.dclkmin;
dclkmax = info->monspecs.dclkmax;
}
if (!var->pixclock)
return -EINVAL;
pixclock = PICOS2KHZ(var->pixclock) * 1000;
htotal = var->xres + var->right_margin + var->hsync_len +
var->left_margin;
vtotal = var->yres + var->lower_margin + var->vsync_len +
var->upper_margin;
if (var->vmode & FB_VMODE_INTERLACED)
vtotal /= 2;
if (var->vmode & FB_VMODE_DOUBLE)
vtotal *= 2;
hfreq = pixclock/htotal;
hfreq = (hfreq + 500) / 1000 * 1000;
vfreq = hfreq/vtotal;
return (vfreq < vfmin || vfreq > vfmax ||
hfreq < hfmin || hfreq > hfmax ||
pixclock < dclkmin || pixclock > dclkmax) ?
-EINVAL : 0;
}
#if defined(CONFIG_FIRMWARE_EDID) && defined(CONFIG_X86)
/*
* We need to ensure that the EDID block is only returned for
* the primary graphics adapter.
*/
const unsigned char *fb_firmware_edid(struct device *device)
{
struct pci_dev *dev = NULL;
struct resource *res = NULL;
unsigned char *edid = NULL;
if (device)
dev = to_pci_dev(device);
if (dev)
res = &dev->resource[PCI_ROM_RESOURCE];
if (res && res->flags & IORESOURCE_ROM_SHADOW)
edid = edid_info.dummy;
return edid;
}
#else
const unsigned char *fb_firmware_edid(struct device *device)
{
return NULL;
}
#endif
EXPORT_SYMBOL(fb_firmware_edid);
EXPORT_SYMBOL(fb_parse_edid);
EXPORT_SYMBOL(fb_edid_to_monspecs);
EXPORT_SYMBOL(fb_get_mode);
EXPORT_SYMBOL(fb_validate_mode);
EXPORT_SYMBOL(fb_destroy_modedb);
| linux-master | drivers/video/fbdev/core/fbmon.c |
/*
* Generic BitBLT function for frame buffer with packed pixels of any depth.
*
* Copyright (C) June 1999 James Simmons
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* NOTES:
*
* This function copys a image from system memory to video memory. The
* image can be a bitmap where each 0 represents the background color and
* each 1 represents the foreground color. Great for font handling. It can
* also be a color image. This is determined by image_depth. The color image
* must be laid out exactly in the same format as the framebuffer. Yes I know
* their are cards with hardware that coverts images of various depths to the
* framebuffer depth. But not every card has this. All images must be rounded
* up to the nearest byte. For example a bitmap 12 bits wide must be two
* bytes width.
*
* Tony:
* Incorporate mask tables similar to fbcon-cfb*.c in 2.4 API. This speeds
* up the code significantly.
*
* Code for depths not multiples of BITS_PER_LONG is still kludgy, which is
* still processed a bit at a time.
*
* Also need to add code to deal with cards endians that are different than
* the native cpu endians. I also need to deal with MSB position in the word.
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/types.h>
#include "fb_draw.h"
#define DEBUG
#ifdef DEBUG
#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt,__func__,## args)
#else
#define DPRINTK(fmt, args...)
#endif
static const u32 cfb_tab8_be[] = {
0x00000000,0x000000ff,0x0000ff00,0x0000ffff,
0x00ff0000,0x00ff00ff,0x00ffff00,0x00ffffff,
0xff000000,0xff0000ff,0xff00ff00,0xff00ffff,
0xffff0000,0xffff00ff,0xffffff00,0xffffffff
};
static const u32 cfb_tab8_le[] = {
0x00000000,0xff000000,0x00ff0000,0xffff0000,
0x0000ff00,0xff00ff00,0x00ffff00,0xffffff00,
0x000000ff,0xff0000ff,0x00ff00ff,0xffff00ff,
0x0000ffff,0xff00ffff,0x00ffffff,0xffffffff
};
static const u32 cfb_tab16_be[] = {
0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff
};
static const u32 cfb_tab16_le[] = {
0x00000000, 0xffff0000, 0x0000ffff, 0xffffffff
};
static const u32 cfb_tab32[] = {
0x00000000, 0xffffffff
};
#define FB_WRITEL fb_writel
#define FB_READL fb_readl
static inline void color_imageblit(const struct fb_image *image,
struct fb_info *p, u8 __iomem *dst1,
u32 start_index,
u32 pitch_index)
{
/* Draw the penguin */
u32 __iomem *dst, *dst2;
u32 color = 0, val, shift;
int i, n, bpp = p->var.bits_per_pixel;
u32 null_bits = 32 - bpp;
u32 *palette = (u32 *) p->pseudo_palette;
const u8 *src = image->data;
u32 bswapmask = fb_compute_bswapmask(p);
dst2 = (u32 __iomem *) dst1;
for (i = image->height; i--; ) {
n = image->width;
dst = (u32 __iomem *) dst1;
shift = 0;
val = 0;
if (start_index) {
u32 start_mask = ~fb_shifted_pixels_mask_u32(p,
start_index, bswapmask);
val = FB_READL(dst) & start_mask;
shift = start_index;
}
while (n--) {
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR )
color = palette[*src];
else
color = *src;
color <<= FB_LEFT_POS(p, bpp);
val |= FB_SHIFT_HIGH(p, color, shift ^ bswapmask);
if (shift >= null_bits) {
FB_WRITEL(val, dst++);
val = (shift == null_bits) ? 0 :
FB_SHIFT_LOW(p, color, 32 - shift);
}
shift += bpp;
shift &= (32 - 1);
src++;
}
if (shift) {
u32 end_mask = fb_shifted_pixels_mask_u32(p, shift,
bswapmask);
FB_WRITEL((FB_READL(dst) & end_mask) | val, dst);
}
dst1 += p->fix.line_length;
if (pitch_index) {
dst2 += p->fix.line_length;
dst1 = (u8 __iomem *)((long __force)dst2 & ~(sizeof(u32) - 1));
start_index += pitch_index;
start_index &= 32 - 1;
}
}
}
static inline void slow_imageblit(const struct fb_image *image, struct fb_info *p,
u8 __iomem *dst1, u32 fgcolor,
u32 bgcolor,
u32 start_index,
u32 pitch_index)
{
u32 shift, color = 0, bpp = p->var.bits_per_pixel;
u32 __iomem *dst, *dst2;
u32 val, pitch = p->fix.line_length;
u32 null_bits = 32 - bpp;
u32 spitch = (image->width+7)/8;
const u8 *src = image->data, *s;
u32 i, j, l;
u32 bswapmask = fb_compute_bswapmask(p);
dst2 = (u32 __iomem *) dst1;
fgcolor <<= FB_LEFT_POS(p, bpp);
bgcolor <<= FB_LEFT_POS(p, bpp);
for (i = image->height; i--; ) {
shift = val = 0;
l = 8;
j = image->width;
dst = (u32 __iomem *) dst1;
s = src;
/* write leading bits */
if (start_index) {
u32 start_mask = ~fb_shifted_pixels_mask_u32(p,
start_index, bswapmask);
val = FB_READL(dst) & start_mask;
shift = start_index;
}
while (j--) {
l--;
color = (*s & (1 << l)) ? fgcolor : bgcolor;
val |= FB_SHIFT_HIGH(p, color, shift ^ bswapmask);
/* Did the bitshift spill bits to the next long? */
if (shift >= null_bits) {
FB_WRITEL(val, dst++);
val = (shift == null_bits) ? 0 :
FB_SHIFT_LOW(p, color, 32 - shift);
}
shift += bpp;
shift &= (32 - 1);
if (!l) { l = 8; s++; }
}
/* write trailing bits */
if (shift) {
u32 end_mask = fb_shifted_pixels_mask_u32(p, shift,
bswapmask);
FB_WRITEL((FB_READL(dst) & end_mask) | val, dst);
}
dst1 += pitch;
src += spitch;
if (pitch_index) {
dst2 += pitch;
dst1 = (u8 __iomem *)((long __force)dst2 & ~(sizeof(u32) - 1));
start_index += pitch_index;
start_index &= 32 - 1;
}
}
}
/*
* fast_imageblit - optimized monochrome color expansion
*
* Only if: bits_per_pixel == 8, 16, or 32
* image->width is divisible by pixel/dword (ppw);
* fix->line_legth is divisible by 4;
* beginning and end of a scanline is dword aligned
*/
static inline void fast_imageblit(const struct fb_image *image, struct fb_info *p,
u8 __iomem *dst1, u32 fgcolor,
u32 bgcolor)
{
u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel;
u32 ppw = 32/bpp, spitch = (image->width + 7)/8;
u32 bit_mask, eorx, shift;
const char *s = image->data, *src;
u32 __iomem *dst;
const u32 *tab = NULL;
size_t tablen;
u32 colortab[16];
int i, j, k;
switch (bpp) {
case 8:
tab = fb_be_math(p) ? cfb_tab8_be : cfb_tab8_le;
tablen = 16;
break;
case 16:
tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le;
tablen = 4;
break;
case 32:
tab = cfb_tab32;
tablen = 2;
break;
default:
return;
}
for (i = ppw-1; i--; ) {
fgx <<= bpp;
bgx <<= bpp;
fgx |= fgcolor;
bgx |= bgcolor;
}
bit_mask = (1 << ppw) - 1;
eorx = fgx ^ bgx;
k = image->width/ppw;
for (i = 0; i < tablen; ++i)
colortab[i] = (tab[i] & eorx) ^ bgx;
for (i = image->height; i--; ) {
dst = (u32 __iomem *)dst1;
shift = 8;
src = s;
/*
* Manually unroll the per-line copying loop for better
* performance. This works until we processed the last
* completely filled source byte (inclusive).
*/
switch (ppw) {
case 4: /* 8 bpp */
for (j = k; j >= 2; j -= 2, ++src) {
FB_WRITEL(colortab[(*src >> 4) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 0) & bit_mask], dst++);
}
break;
case 2: /* 16 bpp */
for (j = k; j >= 4; j -= 4, ++src) {
FB_WRITEL(colortab[(*src >> 6) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 4) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 2) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 0) & bit_mask], dst++);
}
break;
case 1: /* 32 bpp */
for (j = k; j >= 8; j -= 8, ++src) {
FB_WRITEL(colortab[(*src >> 7) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 6) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 5) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 4) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 3) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 2) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 1) & bit_mask], dst++);
FB_WRITEL(colortab[(*src >> 0) & bit_mask], dst++);
}
break;
}
/*
* For image widths that are not a multiple of 8, there
* are trailing pixels left on the current line. Print
* them as well.
*/
for (; j--; ) {
shift -= ppw;
FB_WRITEL(colortab[(*src >> shift) & bit_mask], dst++);
if (!shift) {
shift = 8;
++src;
}
}
dst1 += p->fix.line_length;
s += spitch;
}
}
void cfb_imageblit(struct fb_info *p, const struct fb_image *image)
{
u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
u32 bpl = sizeof(u32), bpp = p->var.bits_per_pixel;
u32 width = image->width;
u32 dx = image->dx, dy = image->dy;
u8 __iomem *dst1;
if (p->state != FBINFO_STATE_RUNNING)
return;
bitstart = (dy * p->fix.line_length * 8) + (dx * bpp);
start_index = bitstart & (32 - 1);
pitch_index = (p->fix.line_length & (bpl - 1)) * 8;
bitstart /= 8;
bitstart &= ~(bpl - 1);
dst1 = p->screen_base + bitstart;
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
if (image->depth == 1) {
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR) {
fgcolor = ((u32*)(p->pseudo_palette))[image->fg_color];
bgcolor = ((u32*)(p->pseudo_palette))[image->bg_color];
} else {
fgcolor = image->fg_color;
bgcolor = image->bg_color;
}
if (32 % bpp == 0 && !start_index && !pitch_index &&
((width & (32/bpp-1)) == 0) &&
bpp >= 8 && bpp <= 32)
fast_imageblit(image, p, dst1, fgcolor, bgcolor);
else
slow_imageblit(image, p, dst1, fgcolor, bgcolor,
start_index, pitch_index);
} else
color_imageblit(image, p, dst1, start_index, pitch_index);
}
EXPORT_SYMBOL(cfb_imageblit);
MODULE_AUTHOR("James Simmons <[email protected]>");
MODULE_DESCRIPTION("Generic software accelerated imaging drawing");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/cfbimgblt.c |
/*
* linux/drivers/video/fbmem.c
*
* Copyright (C) 1994 Martin Schaller
*
* 2001 - Documented with DocBook
* - Brad Douglas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/mman.h>
#include <linux/vt.h>
#include <linux/init.h>
#include <linux/linux_logo.h>
#include <linux/platform_device.h>
#include <linux/console.h>
#include <linux/kmod.h>
#include <linux/err.h>
#include <linux/device.h>
#include <linux/efi.h>
#include <linux/fb.h>
#include <linux/fbcon.h>
#include <linux/mem_encrypt.h>
#include <linux/pci.h>
#include <video/nomodeset.h>
#include <video/vga.h>
#include "fb_internal.h"
/*
* Frame buffer device initialization and setup routines
*/
#define FBPIXMAPSIZE (1024 * 8)
struct class *fb_class;
DEFINE_MUTEX(registration_lock);
struct fb_info *registered_fb[FB_MAX] __read_mostly;
int num_registered_fb __read_mostly;
#define for_each_registered_fb(i) \
for (i = 0; i < FB_MAX; i++) \
if (!registered_fb[i]) {} else
bool fb_center_logo __read_mostly;
int fb_logo_count __read_mostly = -1;
struct fb_info *get_fb_info(unsigned int idx)
{
struct fb_info *fb_info;
if (idx >= FB_MAX)
return ERR_PTR(-ENODEV);
mutex_lock(®istration_lock);
fb_info = registered_fb[idx];
if (fb_info)
refcount_inc(&fb_info->count);
mutex_unlock(®istration_lock);
return fb_info;
}
void put_fb_info(struct fb_info *fb_info)
{
if (!refcount_dec_and_test(&fb_info->count))
return;
if (fb_info->fbops->fb_destroy)
fb_info->fbops->fb_destroy(fb_info);
}
/*
* Helpers
*/
int fb_get_color_depth(struct fb_var_screeninfo *var,
struct fb_fix_screeninfo *fix)
{
int depth = 0;
if (fix->visual == FB_VISUAL_MONO01 ||
fix->visual == FB_VISUAL_MONO10)
depth = 1;
else {
if (var->green.length == var->blue.length &&
var->green.length == var->red.length &&
var->green.offset == var->blue.offset &&
var->green.offset == var->red.offset)
depth = var->green.length;
else
depth = var->green.length + var->red.length +
var->blue.length;
}
return depth;
}
EXPORT_SYMBOL(fb_get_color_depth);
/*
* Data padding functions.
*/
void fb_pad_aligned_buffer(u8 *dst, u32 d_pitch, u8 *src, u32 s_pitch, u32 height)
{
__fb_pad_aligned_buffer(dst, d_pitch, src, s_pitch, height);
}
EXPORT_SYMBOL(fb_pad_aligned_buffer);
void fb_pad_unaligned_buffer(u8 *dst, u32 d_pitch, u8 *src, u32 idx, u32 height,
u32 shift_high, u32 shift_low, u32 mod)
{
u8 mask = (u8) (0xfff << shift_high), tmp;
int i, j;
for (i = height; i--; ) {
for (j = 0; j < idx; j++) {
tmp = dst[j];
tmp &= mask;
tmp |= *src >> shift_low;
dst[j] = tmp;
tmp = *src << shift_high;
dst[j+1] = tmp;
src++;
}
tmp = dst[idx];
tmp &= mask;
tmp |= *src >> shift_low;
dst[idx] = tmp;
if (shift_high < mod) {
tmp = *src << shift_high;
dst[idx+1] = tmp;
}
src++;
dst += d_pitch;
}
}
EXPORT_SYMBOL(fb_pad_unaligned_buffer);
/*
* we need to lock this section since fb_cursor
* may use fb_imageblit()
*/
char* fb_get_buffer_offset(struct fb_info *info, struct fb_pixmap *buf, u32 size)
{
u32 align = buf->buf_align - 1, offset;
char *addr = buf->addr;
/* If IO mapped, we need to sync before access, no sharing of
* the pixmap is done
*/
if (buf->flags & FB_PIXMAP_IO) {
if (info->fbops->fb_sync && (buf->flags & FB_PIXMAP_SYNC))
info->fbops->fb_sync(info);
return addr;
}
/* See if we fit in the remaining pixmap space */
offset = buf->offset + align;
offset &= ~align;
if (offset + size > buf->size) {
/* We do not fit. In order to be able to re-use the buffer,
* we must ensure no asynchronous DMA'ing or whatever operation
* is in progress, we sync for that.
*/
if (info->fbops->fb_sync && (buf->flags & FB_PIXMAP_SYNC))
info->fbops->fb_sync(info);
offset = 0;
}
buf->offset = offset + size;
addr += offset;
return addr;
}
EXPORT_SYMBOL(fb_get_buffer_offset);
#ifdef CONFIG_LOGO
static inline unsigned safe_shift(unsigned d, int n)
{
return n < 0 ? d >> -n : d << n;
}
static void fb_set_logocmap(struct fb_info *info,
const struct linux_logo *logo)
{
struct fb_cmap palette_cmap;
u16 palette_green[16];
u16 palette_blue[16];
u16 palette_red[16];
int i, j, n;
const unsigned char *clut = logo->clut;
palette_cmap.start = 0;
palette_cmap.len = 16;
palette_cmap.red = palette_red;
palette_cmap.green = palette_green;
palette_cmap.blue = palette_blue;
palette_cmap.transp = NULL;
for (i = 0; i < logo->clutsize; i += n) {
n = logo->clutsize - i;
/* palette_cmap provides space for only 16 colors at once */
if (n > 16)
n = 16;
palette_cmap.start = 32 + i;
palette_cmap.len = n;
for (j = 0; j < n; ++j) {
palette_cmap.red[j] = clut[0] << 8 | clut[0];
palette_cmap.green[j] = clut[1] << 8 | clut[1];
palette_cmap.blue[j] = clut[2] << 8 | clut[2];
clut += 3;
}
fb_set_cmap(&palette_cmap, info);
}
}
static void fb_set_logo_truepalette(struct fb_info *info,
const struct linux_logo *logo,
u32 *palette)
{
static const unsigned char mask[] = { 0,0x80,0xc0,0xe0,0xf0,0xf8,0xfc,0xfe,0xff };
unsigned char redmask, greenmask, bluemask;
int redshift, greenshift, blueshift;
int i;
const unsigned char *clut = logo->clut;
/*
* We have to create a temporary palette since console palette is only
* 16 colors long.
*/
/* Bug: Doesn't obey msb_right ... (who needs that?) */
redmask = mask[info->var.red.length < 8 ? info->var.red.length : 8];
greenmask = mask[info->var.green.length < 8 ? info->var.green.length : 8];
bluemask = mask[info->var.blue.length < 8 ? info->var.blue.length : 8];
redshift = info->var.red.offset - (8 - info->var.red.length);
greenshift = info->var.green.offset - (8 - info->var.green.length);
blueshift = info->var.blue.offset - (8 - info->var.blue.length);
for ( i = 0; i < logo->clutsize; i++) {
palette[i+32] = (safe_shift((clut[0] & redmask), redshift) |
safe_shift((clut[1] & greenmask), greenshift) |
safe_shift((clut[2] & bluemask), blueshift));
clut += 3;
}
}
static void fb_set_logo_directpalette(struct fb_info *info,
const struct linux_logo *logo,
u32 *palette)
{
int redshift, greenshift, blueshift;
int i;
redshift = info->var.red.offset;
greenshift = info->var.green.offset;
blueshift = info->var.blue.offset;
for (i = 32; i < 32 + logo->clutsize; i++)
palette[i] = i << redshift | i << greenshift | i << blueshift;
}
static void fb_set_logo(struct fb_info *info,
const struct linux_logo *logo, u8 *dst,
int depth)
{
int i, j, k;
const u8 *src = logo->data;
u8 xor = (info->fix.visual == FB_VISUAL_MONO01) ? 0xff : 0;
u8 fg = 1, d;
switch (fb_get_color_depth(&info->var, &info->fix)) {
case 1:
fg = 1;
break;
case 2:
fg = 3;
break;
default:
fg = 7;
break;
}
if (info->fix.visual == FB_VISUAL_MONO01 ||
info->fix.visual == FB_VISUAL_MONO10)
fg = ~((u8) (0xfff << info->var.green.length));
switch (depth) {
case 4:
for (i = 0; i < logo->height; i++)
for (j = 0; j < logo->width; src++) {
*dst++ = *src >> 4;
j++;
if (j < logo->width) {
*dst++ = *src & 0x0f;
j++;
}
}
break;
case 1:
for (i = 0; i < logo->height; i++) {
for (j = 0; j < logo->width; src++) {
d = *src ^ xor;
for (k = 7; k >= 0 && j < logo->width; k--) {
*dst++ = ((d >> k) & 1) ? fg : 0;
j++;
}
}
}
break;
}
}
/*
* Three (3) kinds of logo maps exist. linux_logo_clut224 (>16 colors),
* linux_logo_vga16 (16 colors) and linux_logo_mono (2 colors). Depending on
* the visual format and color depth of the framebuffer, the DAC, the
* pseudo_palette, and the logo data will be adjusted accordingly.
*
* Case 1 - linux_logo_clut224:
* Color exceeds the number of console colors (16), thus we set the hardware DAC
* using fb_set_cmap() appropriately. The "needs_cmapreset" flag will be set.
*
* For visuals that require color info from the pseudo_palette, we also construct
* one for temporary use. The "needs_directpalette" or "needs_truepalette" flags
* will be set.
*
* Case 2 - linux_logo_vga16:
* The number of colors just matches the console colors, thus there is no need
* to set the DAC or the pseudo_palette. However, the bitmap is packed, ie,
* each byte contains color information for two pixels (upper and lower nibble).
* To be consistent with fb_imageblit() usage, we therefore separate the two
* nibbles into separate bytes. The "depth" flag will be set to 4.
*
* Case 3 - linux_logo_mono:
* This is similar with Case 2. Each byte contains information for 8 pixels.
* We isolate each bit and expand each into a byte. The "depth" flag will
* be set to 1.
*/
static struct logo_data {
int depth;
int needs_directpalette;
int needs_truepalette;
int needs_cmapreset;
const struct linux_logo *logo;
} fb_logo __read_mostly;
static void fb_rotate_logo_ud(const u8 *in, u8 *out, u32 width, u32 height)
{
u32 size = width * height, i;
out += size - 1;
for (i = size; i--; )
*out-- = *in++;
}
static void fb_rotate_logo_cw(const u8 *in, u8 *out, u32 width, u32 height)
{
int i, j, h = height - 1;
for (i = 0; i < height; i++)
for (j = 0; j < width; j++)
out[height * j + h - i] = *in++;
}
static void fb_rotate_logo_ccw(const u8 *in, u8 *out, u32 width, u32 height)
{
int i, j, w = width - 1;
for (i = 0; i < height; i++)
for (j = 0; j < width; j++)
out[height * (w - j) + i] = *in++;
}
static void fb_rotate_logo(struct fb_info *info, u8 *dst,
struct fb_image *image, int rotate)
{
u32 tmp;
if (rotate == FB_ROTATE_UD) {
fb_rotate_logo_ud(image->data, dst, image->width,
image->height);
image->dx = info->var.xres - image->width - image->dx;
image->dy = info->var.yres - image->height - image->dy;
} else if (rotate == FB_ROTATE_CW) {
fb_rotate_logo_cw(image->data, dst, image->width,
image->height);
swap(image->width, image->height);
tmp = image->dy;
image->dy = image->dx;
image->dx = info->var.xres - image->width - tmp;
} else if (rotate == FB_ROTATE_CCW) {
fb_rotate_logo_ccw(image->data, dst, image->width,
image->height);
swap(image->width, image->height);
tmp = image->dx;
image->dx = image->dy;
image->dy = info->var.yres - image->height - tmp;
}
image->data = dst;
}
static void fb_do_show_logo(struct fb_info *info, struct fb_image *image,
int rotate, unsigned int num)
{
unsigned int x;
if (image->width > info->var.xres || image->height > info->var.yres)
return;
if (rotate == FB_ROTATE_UR) {
for (x = 0;
x < num && image->dx + image->width <= info->var.xres;
x++) {
info->fbops->fb_imageblit(info, image);
image->dx += image->width + 8;
}
} else if (rotate == FB_ROTATE_UD) {
u32 dx = image->dx;
for (x = 0; x < num && image->dx <= dx; x++) {
info->fbops->fb_imageblit(info, image);
image->dx -= image->width + 8;
}
} else if (rotate == FB_ROTATE_CW) {
for (x = 0;
x < num && image->dy + image->height <= info->var.yres;
x++) {
info->fbops->fb_imageblit(info, image);
image->dy += image->height + 8;
}
} else if (rotate == FB_ROTATE_CCW) {
u32 dy = image->dy;
for (x = 0; x < num && image->dy <= dy; x++) {
info->fbops->fb_imageblit(info, image);
image->dy -= image->height + 8;
}
}
}
static int fb_show_logo_line(struct fb_info *info, int rotate,
const struct linux_logo *logo, int y,
unsigned int n)
{
u32 *palette = NULL, *saved_pseudo_palette = NULL;
unsigned char *logo_new = NULL, *logo_rotate = NULL;
struct fb_image image;
/* Return if the frame buffer is not mapped or suspended */
if (logo == NULL || info->state != FBINFO_STATE_RUNNING ||
info->fbops->owner)
return 0;
image.depth = 8;
image.data = logo->data;
if (fb_logo.needs_cmapreset)
fb_set_logocmap(info, logo);
if (fb_logo.needs_truepalette ||
fb_logo.needs_directpalette) {
palette = kmalloc(256 * 4, GFP_KERNEL);
if (palette == NULL)
return 0;
if (fb_logo.needs_truepalette)
fb_set_logo_truepalette(info, logo, palette);
else
fb_set_logo_directpalette(info, logo, palette);
saved_pseudo_palette = info->pseudo_palette;
info->pseudo_palette = palette;
}
if (fb_logo.depth <= 4) {
logo_new = kmalloc_array(logo->width, logo->height,
GFP_KERNEL);
if (logo_new == NULL) {
kfree(palette);
if (saved_pseudo_palette)
info->pseudo_palette = saved_pseudo_palette;
return 0;
}
image.data = logo_new;
fb_set_logo(info, logo, logo_new, fb_logo.depth);
}
if (fb_center_logo) {
int xres = info->var.xres;
int yres = info->var.yres;
if (rotate == FB_ROTATE_CW || rotate == FB_ROTATE_CCW) {
xres = info->var.yres;
yres = info->var.xres;
}
while (n && (n * (logo->width + 8) - 8 > xres))
--n;
image.dx = (xres - (n * (logo->width + 8) - 8)) / 2;
image.dy = y ?: (yres - logo->height) / 2;
} else {
image.dx = 0;
image.dy = y;
}
image.width = logo->width;
image.height = logo->height;
if (rotate) {
logo_rotate = kmalloc_array(logo->width, logo->height,
GFP_KERNEL);
if (logo_rotate)
fb_rotate_logo(info, logo_rotate, &image, rotate);
}
fb_do_show_logo(info, &image, rotate, n);
kfree(palette);
if (saved_pseudo_palette != NULL)
info->pseudo_palette = saved_pseudo_palette;
kfree(logo_new);
kfree(logo_rotate);
return image.dy + logo->height;
}
#ifdef CONFIG_FB_LOGO_EXTRA
#define FB_LOGO_EX_NUM_MAX 10
static struct logo_data_extra {
const struct linux_logo *logo;
unsigned int n;
} fb_logo_ex[FB_LOGO_EX_NUM_MAX];
static unsigned int fb_logo_ex_num;
void fb_append_extra_logo(const struct linux_logo *logo, unsigned int n)
{
if (!n || fb_logo_ex_num == FB_LOGO_EX_NUM_MAX)
return;
fb_logo_ex[fb_logo_ex_num].logo = logo;
fb_logo_ex[fb_logo_ex_num].n = n;
fb_logo_ex_num++;
}
static int fb_prepare_extra_logos(struct fb_info *info, unsigned int height,
unsigned int yres)
{
unsigned int i;
/* FIXME: logo_ex supports only truecolor fb. */
if (info->fix.visual != FB_VISUAL_TRUECOLOR)
fb_logo_ex_num = 0;
for (i = 0; i < fb_logo_ex_num; i++) {
if (fb_logo_ex[i].logo->type != fb_logo.logo->type) {
fb_logo_ex[i].logo = NULL;
continue;
}
height += fb_logo_ex[i].logo->height;
if (height > yres) {
height -= fb_logo_ex[i].logo->height;
fb_logo_ex_num = i;
break;
}
}
return height;
}
static int fb_show_extra_logos(struct fb_info *info, int y, int rotate)
{
unsigned int i;
for (i = 0; i < fb_logo_ex_num; i++)
y = fb_show_logo_line(info, rotate,
fb_logo_ex[i].logo, y, fb_logo_ex[i].n);
return y;
}
#else /* !CONFIG_FB_LOGO_EXTRA */
static inline int fb_prepare_extra_logos(struct fb_info *info,
unsigned int height,
unsigned int yres)
{
return height;
}
static inline int fb_show_extra_logos(struct fb_info *info, int y, int rotate)
{
return y;
}
#endif /* CONFIG_FB_LOGO_EXTRA */
int fb_prepare_logo(struct fb_info *info, int rotate)
{
int depth = fb_get_color_depth(&info->var, &info->fix);
unsigned int yres;
int height;
memset(&fb_logo, 0, sizeof(struct logo_data));
if (info->flags & FBINFO_MISC_TILEBLITTING ||
info->fbops->owner || !fb_logo_count)
return 0;
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
depth = info->var.blue.length;
if (info->var.red.length < depth)
depth = info->var.red.length;
if (info->var.green.length < depth)
depth = info->var.green.length;
}
if (info->fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR && depth > 4) {
/* assume console colormap */
depth = 4;
}
/* Return if no suitable logo was found */
fb_logo.logo = fb_find_logo(depth);
if (!fb_logo.logo) {
return 0;
}
if (rotate == FB_ROTATE_UR || rotate == FB_ROTATE_UD)
yres = info->var.yres;
else
yres = info->var.xres;
if (fb_logo.logo->height > yres) {
fb_logo.logo = NULL;
return 0;
}
/* What depth we asked for might be different from what we get */
if (fb_logo.logo->type == LINUX_LOGO_CLUT224)
fb_logo.depth = 8;
else if (fb_logo.logo->type == LINUX_LOGO_VGA16)
fb_logo.depth = 4;
else
fb_logo.depth = 1;
if (fb_logo.depth > 4 && depth > 4) {
switch (info->fix.visual) {
case FB_VISUAL_TRUECOLOR:
fb_logo.needs_truepalette = 1;
break;
case FB_VISUAL_DIRECTCOLOR:
fb_logo.needs_directpalette = 1;
fb_logo.needs_cmapreset = 1;
break;
case FB_VISUAL_PSEUDOCOLOR:
fb_logo.needs_cmapreset = 1;
break;
}
}
height = fb_logo.logo->height;
if (fb_center_logo)
height += (yres - fb_logo.logo->height) / 2;
return fb_prepare_extra_logos(info, height, yres);
}
int fb_show_logo(struct fb_info *info, int rotate)
{
unsigned int count;
int y;
if (!fb_logo_count)
return 0;
count = fb_logo_count < 0 ? num_online_cpus() : fb_logo_count;
y = fb_show_logo_line(info, rotate, fb_logo.logo, 0, count);
y = fb_show_extra_logos(info, y, rotate);
return y;
}
#else
int fb_prepare_logo(struct fb_info *info, int rotate) { return 0; }
int fb_show_logo(struct fb_info *info, int rotate) { return 0; }
#endif /* CONFIG_LOGO */
EXPORT_SYMBOL(fb_prepare_logo);
EXPORT_SYMBOL(fb_show_logo);
int
fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
{
struct fb_fix_screeninfo *fix = &info->fix;
unsigned int yres = info->var.yres;
int err = 0;
if (var->yoffset > 0) {
if (var->vmode & FB_VMODE_YWRAP) {
if (!fix->ywrapstep || (var->yoffset % fix->ywrapstep))
err = -EINVAL;
else
yres = 0;
} else if (!fix->ypanstep || (var->yoffset % fix->ypanstep))
err = -EINVAL;
}
if (var->xoffset > 0 && (!fix->xpanstep ||
(var->xoffset % fix->xpanstep)))
err = -EINVAL;
if (err || !info->fbops->fb_pan_display ||
var->yoffset > info->var.yres_virtual - yres ||
var->xoffset > info->var.xres_virtual - info->var.xres)
return -EINVAL;
if ((err = info->fbops->fb_pan_display(var, info)))
return err;
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
if (var->vmode & FB_VMODE_YWRAP)
info->var.vmode |= FB_VMODE_YWRAP;
else
info->var.vmode &= ~FB_VMODE_YWRAP;
return 0;
}
EXPORT_SYMBOL(fb_pan_display);
static int fb_check_caps(struct fb_info *info, struct fb_var_screeninfo *var,
u32 activate)
{
struct fb_blit_caps caps, fbcaps;
int err = 0;
memset(&caps, 0, sizeof(caps));
memset(&fbcaps, 0, sizeof(fbcaps));
caps.flags = (activate & FB_ACTIVATE_ALL) ? 1 : 0;
fbcon_get_requirement(info, &caps);
info->fbops->fb_get_caps(info, &fbcaps, var);
if (((fbcaps.x ^ caps.x) & caps.x) ||
((fbcaps.y ^ caps.y) & caps.y) ||
(fbcaps.len < caps.len))
err = -EINVAL;
return err;
}
int
fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
{
int ret = 0;
u32 activate;
struct fb_var_screeninfo old_var;
struct fb_videomode mode;
struct fb_event event;
u32 unused;
if (var->activate & FB_ACTIVATE_INV_MODE) {
struct fb_videomode mode1, mode2;
fb_var_to_videomode(&mode1, var);
fb_var_to_videomode(&mode2, &info->var);
/* make sure we don't delete the videomode of current var */
ret = fb_mode_is_equal(&mode1, &mode2);
if (!ret) {
ret = fbcon_mode_deleted(info, &mode1);
if (!ret)
fb_delete_videomode(&mode1, &info->modelist);
}
return ret ? -EINVAL : 0;
}
if (!(var->activate & FB_ACTIVATE_FORCE) &&
!memcmp(&info->var, var, sizeof(struct fb_var_screeninfo)))
return 0;
activate = var->activate;
/* When using FOURCC mode, make sure the red, green, blue and
* transp fields are set to 0.
*/
if ((info->fix.capabilities & FB_CAP_FOURCC) &&
var->grayscale > 1) {
if (var->red.offset || var->green.offset ||
var->blue.offset || var->transp.offset ||
var->red.length || var->green.length ||
var->blue.length || var->transp.length ||
var->red.msb_right || var->green.msb_right ||
var->blue.msb_right || var->transp.msb_right)
return -EINVAL;
}
if (!info->fbops->fb_check_var) {
*var = info->var;
return 0;
}
/* bitfill_aligned() assumes that it's at least 8x8 */
if (var->xres < 8 || var->yres < 8)
return -EINVAL;
/* Too huge resolution causes multiplication overflow. */
if (check_mul_overflow(var->xres, var->yres, &unused) ||
check_mul_overflow(var->xres_virtual, var->yres_virtual, &unused))
return -EINVAL;
ret = info->fbops->fb_check_var(var, info);
if (ret)
return ret;
/* verify that virtual resolution >= physical resolution */
if (var->xres_virtual < var->xres ||
var->yres_virtual < var->yres) {
pr_warn("WARNING: fbcon: Driver '%s' missed to adjust virtual screen size (%ux%u vs. %ux%u)\n",
info->fix.id,
var->xres_virtual, var->yres_virtual,
var->xres, var->yres);
return -EINVAL;
}
if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW)
return 0;
if (info->fbops->fb_get_caps) {
ret = fb_check_caps(info, var, activate);
if (ret)
return ret;
}
old_var = info->var;
info->var = *var;
if (info->fbops->fb_set_par) {
ret = info->fbops->fb_set_par(info);
if (ret) {
info->var = old_var;
printk(KERN_WARNING "detected "
"fb_set_par error, "
"error code: %d\n", ret);
return ret;
}
}
fb_pan_display(info, &info->var);
fb_set_cmap(&info->cmap, info);
fb_var_to_videomode(&mode, &info->var);
if (info->modelist.prev && info->modelist.next &&
!list_empty(&info->modelist))
ret = fb_add_videomode(&mode, &info->modelist);
if (ret)
return ret;
event.info = info;
event.data = &mode;
fb_notifier_call_chain(FB_EVENT_MODE_CHANGE, &event);
return 0;
}
EXPORT_SYMBOL(fb_set_var);
int
fb_blank(struct fb_info *info, int blank)
{
struct fb_event event;
int ret = -EINVAL;
if (blank > FB_BLANK_POWERDOWN)
blank = FB_BLANK_POWERDOWN;
event.info = info;
event.data = ␣
if (info->fbops->fb_blank)
ret = info->fbops->fb_blank(blank, info);
if (!ret)
fb_notifier_call_chain(FB_EVENT_BLANK, &event);
return ret;
}
EXPORT_SYMBOL(fb_blank);
static int fb_check_foreignness(struct fb_info *fi)
{
const bool foreign_endian = fi->flags & FBINFO_FOREIGN_ENDIAN;
fi->flags &= ~FBINFO_FOREIGN_ENDIAN;
#ifdef __BIG_ENDIAN
fi->flags |= foreign_endian ? 0 : FBINFO_BE_MATH;
#else
fi->flags |= foreign_endian ? FBINFO_BE_MATH : 0;
#endif /* __BIG_ENDIAN */
if (fi->flags & FBINFO_BE_MATH && !fb_be_math(fi)) {
pr_err("%s: enable CONFIG_FB_BIG_ENDIAN to "
"support this framebuffer\n", fi->fix.id);
return -ENOSYS;
} else if (!(fi->flags & FBINFO_BE_MATH) && fb_be_math(fi)) {
pr_err("%s: enable CONFIG_FB_LITTLE_ENDIAN to "
"support this framebuffer\n", fi->fix.id);
return -ENOSYS;
}
return 0;
}
static int do_register_framebuffer(struct fb_info *fb_info)
{
int i;
struct fb_videomode mode;
if (fb_check_foreignness(fb_info))
return -ENOSYS;
if (num_registered_fb == FB_MAX)
return -ENXIO;
num_registered_fb++;
for (i = 0 ; i < FB_MAX; i++)
if (!registered_fb[i])
break;
fb_info->node = i;
refcount_set(&fb_info->count, 1);
mutex_init(&fb_info->lock);
mutex_init(&fb_info->mm_lock);
fb_device_create(fb_info);
if (fb_info->pixmap.addr == NULL) {
fb_info->pixmap.addr = kmalloc(FBPIXMAPSIZE, GFP_KERNEL);
if (fb_info->pixmap.addr) {
fb_info->pixmap.size = FBPIXMAPSIZE;
fb_info->pixmap.buf_align = 1;
fb_info->pixmap.scan_align = 1;
fb_info->pixmap.access_align = 32;
fb_info->pixmap.flags = FB_PIXMAP_DEFAULT;
}
}
fb_info->pixmap.offset = 0;
if (!fb_info->pixmap.blit_x)
fb_info->pixmap.blit_x = ~(u32)0;
if (!fb_info->pixmap.blit_y)
fb_info->pixmap.blit_y = ~(u32)0;
if (!fb_info->modelist.prev || !fb_info->modelist.next)
INIT_LIST_HEAD(&fb_info->modelist);
if (fb_info->skip_vt_switch)
pm_vt_switch_required(fb_info->device, false);
else
pm_vt_switch_required(fb_info->device, true);
fb_var_to_videomode(&mode, &fb_info->var);
fb_add_videomode(&mode, &fb_info->modelist);
registered_fb[i] = fb_info;
#ifdef CONFIG_GUMSTIX_AM200EPD
{
struct fb_event event;
event.info = fb_info;
fb_notifier_call_chain(FB_EVENT_FB_REGISTERED, &event);
}
#endif
return fbcon_fb_registered(fb_info);
}
static void unbind_console(struct fb_info *fb_info)
{
int i = fb_info->node;
if (WARN_ON(i < 0 || i >= FB_MAX || registered_fb[i] != fb_info))
return;
fbcon_fb_unbind(fb_info);
}
static void unlink_framebuffer(struct fb_info *fb_info)
{
int i;
i = fb_info->node;
if (WARN_ON(i < 0 || i >= FB_MAX || registered_fb[i] != fb_info))
return;
fb_device_destroy(fb_info);
pm_vt_switch_unregister(fb_info->device);
unbind_console(fb_info);
}
static void do_unregister_framebuffer(struct fb_info *fb_info)
{
unlink_framebuffer(fb_info);
if (fb_info->pixmap.addr &&
(fb_info->pixmap.flags & FB_PIXMAP_DEFAULT)) {
kfree(fb_info->pixmap.addr);
fb_info->pixmap.addr = NULL;
}
fb_destroy_modelist(&fb_info->modelist);
registered_fb[fb_info->node] = NULL;
num_registered_fb--;
#ifdef CONFIG_GUMSTIX_AM200EPD
{
struct fb_event event;
event.info = fb_info;
fb_notifier_call_chain(FB_EVENT_FB_UNREGISTERED, &event);
}
#endif
fbcon_fb_unregistered(fb_info);
/* this may free fb info */
put_fb_info(fb_info);
}
/**
* register_framebuffer - registers a frame buffer device
* @fb_info: frame buffer info structure
*
* Registers a frame buffer device @fb_info.
*
* Returns negative errno on error, or zero for success.
*
*/
int
register_framebuffer(struct fb_info *fb_info)
{
int ret;
mutex_lock(®istration_lock);
ret = do_register_framebuffer(fb_info);
mutex_unlock(®istration_lock);
return ret;
}
EXPORT_SYMBOL(register_framebuffer);
/**
* unregister_framebuffer - releases a frame buffer device
* @fb_info: frame buffer info structure
*
* Unregisters a frame buffer device @fb_info.
*
* Returns negative errno on error, or zero for success.
*
* This function will also notify the framebuffer console
* to release the driver.
*
* This is meant to be called within a driver's module_exit()
* function. If this is called outside module_exit(), ensure
* that the driver implements fb_open() and fb_release() to
* check that no processes are using the device.
*/
void
unregister_framebuffer(struct fb_info *fb_info)
{
mutex_lock(®istration_lock);
do_unregister_framebuffer(fb_info);
mutex_unlock(®istration_lock);
}
EXPORT_SYMBOL(unregister_framebuffer);
/**
* fb_set_suspend - low level driver signals suspend
* @info: framebuffer affected
* @state: 0 = resuming, !=0 = suspending
*
* This is meant to be used by low level drivers to
* signal suspend/resume to the core & clients.
* It must be called with the console semaphore held
*/
void fb_set_suspend(struct fb_info *info, int state)
{
WARN_CONSOLE_UNLOCKED();
if (state) {
fbcon_suspended(info);
info->state = FBINFO_STATE_SUSPENDED;
} else {
info->state = FBINFO_STATE_RUNNING;
fbcon_resumed(info);
}
}
EXPORT_SYMBOL(fb_set_suspend);
static int __init fbmem_init(void)
{
int ret;
fb_class = class_create("graphics");
if (IS_ERR(fb_class)) {
ret = PTR_ERR(fb_class);
pr_err("Unable to create fb class; errno = %d\n", ret);
goto err_fb_class;
}
ret = fb_init_procfs();
if (ret)
goto err_class_destroy;
ret = fb_register_chrdev();
if (ret)
goto err_fb_cleanup_procfs;
fb_console_init();
return 0;
err_fb_cleanup_procfs:
fb_cleanup_procfs();
err_class_destroy:
class_destroy(fb_class);
err_fb_class:
fb_class = NULL;
return ret;
}
#ifdef MODULE
static void __exit fbmem_exit(void)
{
fb_console_exit();
fb_unregister_chrdev();
fb_cleanup_procfs();
class_destroy(fb_class);
}
module_init(fbmem_init);
module_exit(fbmem_exit);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Framebuffer base");
#else
subsys_initcall(fbmem_init);
#endif
int fb_new_modelist(struct fb_info *info)
{
struct fb_var_screeninfo var = info->var;
struct list_head *pos, *n;
struct fb_modelist *modelist;
struct fb_videomode *m, mode;
int err;
list_for_each_safe(pos, n, &info->modelist) {
modelist = list_entry(pos, struct fb_modelist, list);
m = &modelist->mode;
fb_videomode_to_var(&var, m);
var.activate = FB_ACTIVATE_TEST;
err = fb_set_var(info, &var);
fb_var_to_videomode(&mode, &var);
if (err || !fb_mode_is_equal(m, &mode)) {
list_del(pos);
kfree(pos);
}
}
if (list_empty(&info->modelist))
return 1;
fbcon_new_modelist(info);
return 0;
}
#if defined(CONFIG_VIDEO_NOMODESET)
bool fb_modesetting_disabled(const char *drvname)
{
bool fwonly = video_firmware_drivers_only();
if (fwonly)
pr_warn("Driver %s not loading because of nomodeset parameter\n",
drvname);
return fwonly;
}
EXPORT_SYMBOL(fb_modesetting_disabled);
#endif
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/fbmem.c |
/*
* Generic Bit Block Transfer for frame buffers located in system RAM with
* packed pixels of any depth.
*
* Based almost entirely from cfbcopyarea.c (which is based almost entirely
* on Geert Uytterhoeven's copyarea routine)
*
* Copyright (C) 2007 Antonino Daplas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/types.h>
#include <asm/io.h>
#include "fb_draw.h"
/*
* Generic bitwise copy algorithm
*/
static void
bitcpy(struct fb_info *p, unsigned long *dst, unsigned dst_idx,
const unsigned long *src, unsigned src_idx, int bits, unsigned n)
{
unsigned long first, last;
int const shift = dst_idx-src_idx;
int left, right;
first = FB_SHIFT_HIGH(p, ~0UL, dst_idx);
last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits));
if (!shift) {
/* Same alignment for source and dest */
if (dst_idx+n <= bits) {
/* Single word */
if (last)
first &= last;
*dst = comp(*src, *dst, first);
} else {
/* Multiple destination words */
/* Leading bits */
if (first != ~0UL) {
*dst = comp(*src, *dst, first);
dst++;
src++;
n -= bits - dst_idx;
}
/* Main chunk */
n /= bits;
while (n >= 8) {
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
n -= 8;
}
while (n--)
*dst++ = *src++;
/* Trailing bits */
if (last)
*dst = comp(*src, *dst, last);
}
} else {
unsigned long d0, d1;
int m;
/* Different alignment for source and dest */
right = shift & (bits - 1);
left = -shift & (bits - 1);
if (dst_idx+n <= bits) {
/* Single destination word */
if (last)
first &= last;
if (shift > 0) {
/* Single source word */
*dst = comp(*src << left, *dst, first);
} else if (src_idx+n <= bits) {
/* Single source word */
*dst = comp(*src >> right, *dst, first);
} else {
/* 2 source words */
d0 = *src++;
d1 = *src;
*dst = comp(d0 >> right | d1 << left, *dst,
first);
}
} else {
/* Multiple destination words */
/** We must always remember the last value read,
because in case SRC and DST overlap bitwise (e.g.
when moving just one pixel in 1bpp), we always
collect one full long for DST and that might
overlap with the current long from SRC. We store
this value in 'd0'. */
d0 = *src++;
/* Leading bits */
if (shift > 0) {
/* Single source word */
*dst = comp(d0 << left, *dst, first);
dst++;
n -= bits - dst_idx;
} else {
/* 2 source words */
d1 = *src++;
*dst = comp(d0 >> right | d1 << left, *dst,
first);
d0 = d1;
dst++;
n -= bits - dst_idx;
}
/* Main chunk */
m = n % bits;
n /= bits;
while (n >= 4) {
d1 = *src++;
*dst++ = d0 >> right | d1 << left;
d0 = d1;
d1 = *src++;
*dst++ = d0 >> right | d1 << left;
d0 = d1;
d1 = *src++;
*dst++ = d0 >> right | d1 << left;
d0 = d1;
d1 = *src++;
*dst++ = d0 >> right | d1 << left;
d0 = d1;
n -= 4;
}
while (n--) {
d1 = *src++;
*dst++ = d0 >> right | d1 << left;
d0 = d1;
}
/* Trailing bits */
if (m) {
if (m <= bits - right) {
/* Single source word */
d0 >>= right;
} else {
/* 2 source words */
d1 = *src;
d0 = d0 >> right | d1 << left;
}
*dst = comp(d0, *dst, last);
}
}
}
}
/*
* Generic bitwise copy algorithm, operating backward
*/
static void
bitcpy_rev(struct fb_info *p, unsigned long *dst, unsigned dst_idx,
const unsigned long *src, unsigned src_idx, unsigned bits,
unsigned n)
{
unsigned long first, last;
int shift;
dst += (dst_idx + n - 1) / bits;
src += (src_idx + n - 1) / bits;
dst_idx = (dst_idx + n - 1) % bits;
src_idx = (src_idx + n - 1) % bits;
shift = dst_idx-src_idx;
first = ~FB_SHIFT_HIGH(p, ~0UL, (dst_idx + 1) % bits);
last = FB_SHIFT_HIGH(p, ~0UL, (bits + dst_idx + 1 - n) % bits);
if (!shift) {
/* Same alignment for source and dest */
if ((unsigned long)dst_idx+1 >= n) {
/* Single word */
if (first)
last &= first;
*dst = comp(*src, *dst, last);
} else {
/* Multiple destination words */
/* Leading bits */
if (first) {
*dst = comp(*src, *dst, first);
dst--;
src--;
n -= dst_idx+1;
}
/* Main chunk */
n /= bits;
while (n >= 8) {
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
*dst-- = *src--;
n -= 8;
}
while (n--)
*dst-- = *src--;
/* Trailing bits */
if (last != -1UL)
*dst = comp(*src, *dst, last);
}
} else {
/* Different alignment for source and dest */
int const left = shift & (bits-1);
int const right = -shift & (bits-1);
if ((unsigned long)dst_idx+1 >= n) {
/* Single destination word */
if (first)
last &= first;
if (shift < 0) {
/* Single source word */
*dst = comp(*src >> right, *dst, last);
} else if (1+(unsigned long)src_idx >= n) {
/* Single source word */
*dst = comp(*src << left, *dst, last);
} else {
/* 2 source words */
*dst = comp(*src << left | *(src-1) >> right,
*dst, last);
}
} else {
/* Multiple destination words */
/** We must always remember the last value read,
because in case SRC and DST overlap bitwise (e.g.
when moving just one pixel in 1bpp), we always
collect one full long for DST and that might
overlap with the current long from SRC. We store
this value in 'd0'. */
unsigned long d0, d1;
int m;
d0 = *src--;
/* Leading bits */
if (shift < 0) {
/* Single source word */
d1 = d0;
d0 >>= right;
} else {
/* 2 source words */
d1 = *src--;
d0 = d0 << left | d1 >> right;
}
if (!first)
*dst = d0;
else
*dst = comp(d0, *dst, first);
d0 = d1;
dst--;
n -= dst_idx+1;
/* Main chunk */
m = n % bits;
n /= bits;
while (n >= 4) {
d1 = *src--;
*dst-- = d0 << left | d1 >> right;
d0 = d1;
d1 = *src--;
*dst-- = d0 << left | d1 >> right;
d0 = d1;
d1 = *src--;
*dst-- = d0 << left | d1 >> right;
d0 = d1;
d1 = *src--;
*dst-- = d0 << left | d1 >> right;
d0 = d1;
n -= 4;
}
while (n--) {
d1 = *src--;
*dst-- = d0 << left | d1 >> right;
d0 = d1;
}
/* Trailing bits */
if (m) {
if (m <= bits - left) {
/* Single source word */
d0 <<= left;
} else {
/* 2 source words */
d1 = *src;
d0 = d0 << left | d1 >> right;
}
*dst = comp(d0, *dst, last);
}
}
}
}
void sys_copyarea(struct fb_info *p, const struct fb_copyarea *area)
{
u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
u32 height = area->height, width = area->width;
unsigned long const bits_per_line = p->fix.line_length*8u;
unsigned long *base = NULL;
int bits = BITS_PER_LONG, bytes = bits >> 3;
unsigned dst_idx = 0, src_idx = 0, rev_copy = 0;
if (p->state != FBINFO_STATE_RUNNING)
return;
/* if the beginning of the target area might overlap with the end of
the source area, be have to copy the area reverse. */
if ((dy == sy && dx > sx) || (dy > sy)) {
dy += height;
sy += height;
rev_copy = 1;
}
/* split the base of the framebuffer into a long-aligned address and
the index of the first bit */
base = (unsigned long *)((unsigned long)p->screen_base & ~(bytes-1));
dst_idx = src_idx = 8*((unsigned long)p->screen_base & (bytes-1));
/* add offset of source and target area */
dst_idx += dy*bits_per_line + dx*p->var.bits_per_pixel;
src_idx += sy*bits_per_line + sx*p->var.bits_per_pixel;
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
if (rev_copy) {
while (height--) {
dst_idx -= bits_per_line;
src_idx -= bits_per_line;
bitcpy_rev(p, base + (dst_idx / bits), dst_idx % bits,
base + (src_idx / bits), src_idx % bits, bits,
width*p->var.bits_per_pixel);
}
} else {
while (height--) {
bitcpy(p, base + (dst_idx / bits), dst_idx % bits,
base + (src_idx / bits), src_idx % bits, bits,
width*p->var.bits_per_pixel);
dst_idx += bits_per_line;
src_idx += bits_per_line;
}
}
}
EXPORT_SYMBOL(sys_copyarea);
MODULE_AUTHOR("Antonino Daplas <[email protected]>");
MODULE_DESCRIPTION("Generic copyarea (sys-to-sys)");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/syscopyarea.c |
/*
* Generic fillrect for frame buffers in system RAM with packed pixels of
* any depth.
*
* Based almost entirely from cfbfillrect.c (which is based almost entirely
* on Geert Uytterhoeven's fillrect routine)
*
* Copyright (C) 2007 Antonino Daplas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/types.h>
#include "fb_draw.h"
/*
* Aligned pattern fill using 32/64-bit memory accesses
*/
static void
bitfill_aligned(struct fb_info *p, unsigned long *dst, int dst_idx,
unsigned long pat, unsigned n, int bits)
{
unsigned long first, last;
if (!n)
return;
first = FB_SHIFT_HIGH(p, ~0UL, dst_idx);
last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
/* Single word */
if (last)
first &= last;
*dst = comp(pat, *dst, first);
} else {
/* Multiple destination words */
/* Leading bits */
if (first!= ~0UL) {
*dst = comp(pat, *dst, first);
dst++;
n -= bits - dst_idx;
}
/* Main chunk */
n /= bits;
memset_l(dst, pat, n);
dst += n;
/* Trailing bits */
if (last)
*dst = comp(pat, *dst, last);
}
}
/*
* Unaligned generic pattern fill using 32/64-bit memory accesses
* The pattern must have been expanded to a full 32/64-bit value
* Left/right are the appropriate shifts to convert to the pattern to be
* used for the next 32/64-bit word
*/
static void
bitfill_unaligned(struct fb_info *p, unsigned long *dst, int dst_idx,
unsigned long pat, int left, int right, unsigned n, int bits)
{
unsigned long first, last;
if (!n)
return;
first = FB_SHIFT_HIGH(p, ~0UL, dst_idx);
last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
/* Single word */
if (last)
first &= last;
*dst = comp(pat, *dst, first);
} else {
/* Multiple destination words */
/* Leading bits */
if (first) {
*dst = comp(pat, *dst, first);
dst++;
pat = pat << left | pat >> right;
n -= bits - dst_idx;
}
/* Main chunk */
n /= bits;
while (n >= 4) {
*dst++ = pat;
pat = pat << left | pat >> right;
*dst++ = pat;
pat = pat << left | pat >> right;
*dst++ = pat;
pat = pat << left | pat >> right;
*dst++ = pat;
pat = pat << left | pat >> right;
n -= 4;
}
while (n--) {
*dst++ = pat;
pat = pat << left | pat >> right;
}
/* Trailing bits */
if (last)
*dst = comp(pat, *dst, last);
}
}
/*
* Aligned pattern invert using 32/64-bit memory accesses
*/
static void
bitfill_aligned_rev(struct fb_info *p, unsigned long *dst, int dst_idx,
unsigned long pat, unsigned n, int bits)
{
unsigned long val = pat;
unsigned long first, last;
if (!n)
return;
first = FB_SHIFT_HIGH(p, ~0UL, dst_idx);
last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
/* Single word */
if (last)
first &= last;
*dst = comp(*dst ^ val, *dst, first);
} else {
/* Multiple destination words */
/* Leading bits */
if (first!=0UL) {
*dst = comp(*dst ^ val, *dst, first);
dst++;
n -= bits - dst_idx;
}
/* Main chunk */
n /= bits;
while (n >= 8) {
*dst++ ^= val;
*dst++ ^= val;
*dst++ ^= val;
*dst++ ^= val;
*dst++ ^= val;
*dst++ ^= val;
*dst++ ^= val;
*dst++ ^= val;
n -= 8;
}
while (n--)
*dst++ ^= val;
/* Trailing bits */
if (last)
*dst = comp(*dst ^ val, *dst, last);
}
}
/*
* Unaligned generic pattern invert using 32/64-bit memory accesses
* The pattern must have been expanded to a full 32/64-bit value
* Left/right are the appropriate shifts to convert to the pattern to be
* used for the next 32/64-bit word
*/
static void
bitfill_unaligned_rev(struct fb_info *p, unsigned long *dst, int dst_idx,
unsigned long pat, int left, int right, unsigned n,
int bits)
{
unsigned long first, last;
if (!n)
return;
first = FB_SHIFT_HIGH(p, ~0UL, dst_idx);
last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
/* Single word */
if (last)
first &= last;
*dst = comp(*dst ^ pat, *dst, first);
} else {
/* Multiple destination words */
/* Leading bits */
if (first != 0UL) {
*dst = comp(*dst ^ pat, *dst, first);
dst++;
pat = pat << left | pat >> right;
n -= bits - dst_idx;
}
/* Main chunk */
n /= bits;
while (n >= 4) {
*dst++ ^= pat;
pat = pat << left | pat >> right;
*dst++ ^= pat;
pat = pat << left | pat >> right;
*dst++ ^= pat;
pat = pat << left | pat >> right;
*dst++ ^= pat;
pat = pat << left | pat >> right;
n -= 4;
}
while (n--) {
*dst ^= pat;
pat = pat << left | pat >> right;
}
/* Trailing bits */
if (last)
*dst = comp(*dst ^ pat, *dst, last);
}
}
void sys_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
{
unsigned long pat, pat2, fg;
unsigned long width = rect->width, height = rect->height;
int bits = BITS_PER_LONG, bytes = bits >> 3;
u32 bpp = p->var.bits_per_pixel;
unsigned long *dst;
int dst_idx, left;
if (p->state != FBINFO_STATE_RUNNING)
return;
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR )
fg = ((u32 *) (p->pseudo_palette))[rect->color];
else
fg = rect->color;
pat = pixel_to_pat( bpp, fg);
dst = (unsigned long *)((unsigned long)p->screen_base & ~(bytes-1));
dst_idx = ((unsigned long)p->screen_base & (bytes - 1))*8;
dst_idx += rect->dy*p->fix.line_length*8+rect->dx*bpp;
/* FIXME For now we support 1-32 bpp only */
left = bits % bpp;
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
if (!left) {
void (*fill_op32)(struct fb_info *p, unsigned long *dst,
int dst_idx, unsigned long pat, unsigned n,
int bits) = NULL;
switch (rect->rop) {
case ROP_XOR:
fill_op32 = bitfill_aligned_rev;
break;
case ROP_COPY:
fill_op32 = bitfill_aligned;
break;
default:
printk( KERN_ERR "cfb_fillrect(): unknown rop, "
"defaulting to ROP_COPY\n");
fill_op32 = bitfill_aligned;
break;
}
while (height--) {
dst += dst_idx >> (ffs(bits) - 1);
dst_idx &= (bits - 1);
fill_op32(p, dst, dst_idx, pat, width*bpp, bits);
dst_idx += p->fix.line_length*8;
}
} else {
int right, r;
void (*fill_op)(struct fb_info *p, unsigned long *dst,
int dst_idx, unsigned long pat, int left,
int right, unsigned n, int bits) = NULL;
#ifdef __LITTLE_ENDIAN
right = left;
left = bpp - right;
#else
right = bpp - left;
#endif
switch (rect->rop) {
case ROP_XOR:
fill_op = bitfill_unaligned_rev;
break;
case ROP_COPY:
fill_op = bitfill_unaligned;
break;
default:
printk(KERN_ERR "sys_fillrect(): unknown rop, "
"defaulting to ROP_COPY\n");
fill_op = bitfill_unaligned;
break;
}
while (height--) {
dst += dst_idx / bits;
dst_idx &= (bits - 1);
r = dst_idx % bpp;
/* rotate pattern to the correct start position */
pat2 = le_long_to_cpu(rolx(cpu_to_le_long(pat), r, bpp));
fill_op(p, dst, dst_idx, pat2, left, right,
width*bpp, bits);
dst_idx += p->fix.line_length*8;
}
}
}
EXPORT_SYMBOL(sys_fillrect);
MODULE_AUTHOR("Antonino Daplas <[email protected]>");
MODULE_DESCRIPTION("Generic fill rectangle (sys-to-sys)");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/sysfillrect.c |
/*
* linux/drivers/video/fb_defio.c
*
* Copyright (C) 2006 Jaya Kumar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/list.h>
/* to support deferred IO */
#include <linux/rmap.h>
#include <linux/pagemap.h>
static struct page *fb_deferred_io_page(struct fb_info *info, unsigned long offs)
{
void *screen_base = (void __force *) info->screen_base;
struct page *page;
if (is_vmalloc_addr(screen_base + offs))
page = vmalloc_to_page(screen_base + offs);
else
page = pfn_to_page((info->fix.smem_start + offs) >> PAGE_SHIFT);
return page;
}
static struct fb_deferred_io_pageref *fb_deferred_io_pageref_get(struct fb_info *info,
unsigned long offset,
struct page *page)
{
struct fb_deferred_io *fbdefio = info->fbdefio;
struct list_head *pos = &fbdefio->pagereflist;
unsigned long pgoff = offset >> PAGE_SHIFT;
struct fb_deferred_io_pageref *pageref, *cur;
if (WARN_ON_ONCE(pgoff >= info->npagerefs))
return NULL; /* incorrect allocation size */
/* 1:1 mapping between pageref and page offset */
pageref = &info->pagerefs[pgoff];
/*
* This check is to catch the case where a new process could start
* writing to the same page through a new PTE. This new access
* can cause a call to .page_mkwrite even if the original process'
* PTE is marked writable.
*/
if (!list_empty(&pageref->list))
goto pageref_already_added;
pageref->page = page;
pageref->offset = pgoff << PAGE_SHIFT;
if (unlikely(fbdefio->sort_pagereflist)) {
/*
* We loop through the list of pagerefs before adding in
* order to keep the pagerefs sorted. This has significant
* overhead of O(n^2) with n being the number of written
* pages. If possible, drivers should try to work with
* unsorted page lists instead.
*/
list_for_each_entry(cur, &fbdefio->pagereflist, list) {
if (cur->offset > pageref->offset)
break;
}
pos = &cur->list;
}
list_add_tail(&pageref->list, pos);
pageref_already_added:
return pageref;
}
static void fb_deferred_io_pageref_put(struct fb_deferred_io_pageref *pageref,
struct fb_info *info)
{
list_del_init(&pageref->list);
}
/* this is to find and return the vmalloc-ed fb pages */
static vm_fault_t fb_deferred_io_fault(struct vm_fault *vmf)
{
unsigned long offset;
struct page *page;
struct fb_info *info = vmf->vma->vm_private_data;
offset = vmf->pgoff << PAGE_SHIFT;
if (offset >= info->fix.smem_len)
return VM_FAULT_SIGBUS;
page = fb_deferred_io_page(info, offset);
if (!page)
return VM_FAULT_SIGBUS;
get_page(page);
if (vmf->vma->vm_file)
page->mapping = vmf->vma->vm_file->f_mapping;
else
printk(KERN_ERR "no mapping available\n");
BUG_ON(!page->mapping);
page->index = vmf->pgoff; /* for page_mkclean() */
vmf->page = page;
return 0;
}
int fb_deferred_io_fsync(struct file *file, loff_t start, loff_t end, int datasync)
{
struct fb_info *info = file->private_data;
struct inode *inode = file_inode(file);
int err = file_write_and_wait_range(file, start, end);
if (err)
return err;
/* Skip if deferred io is compiled-in but disabled on this fbdev */
if (!info->fbdefio)
return 0;
inode_lock(inode);
/* Kill off the delayed work */
cancel_delayed_work_sync(&info->deferred_work);
/* Run it immediately */
schedule_delayed_work(&info->deferred_work, 0);
inode_unlock(inode);
return 0;
}
EXPORT_SYMBOL_GPL(fb_deferred_io_fsync);
/*
* Adds a page to the dirty list. Call this from struct
* vm_operations_struct.page_mkwrite.
*/
static vm_fault_t fb_deferred_io_track_page(struct fb_info *info, unsigned long offset,
struct page *page)
{
struct fb_deferred_io *fbdefio = info->fbdefio;
struct fb_deferred_io_pageref *pageref;
vm_fault_t ret;
/* protect against the workqueue changing the page list */
mutex_lock(&fbdefio->lock);
pageref = fb_deferred_io_pageref_get(info, offset, page);
if (WARN_ON_ONCE(!pageref)) {
ret = VM_FAULT_OOM;
goto err_mutex_unlock;
}
/*
* We want the page to remain locked from ->page_mkwrite until
* the PTE is marked dirty to avoid page_mkclean() being called
* before the PTE is updated, which would leave the page ignored
* by defio.
* Do this by locking the page here and informing the caller
* about it with VM_FAULT_LOCKED.
*/
lock_page(pageref->page);
mutex_unlock(&fbdefio->lock);
/* come back after delay to process the deferred IO */
schedule_delayed_work(&info->deferred_work, fbdefio->delay);
return VM_FAULT_LOCKED;
err_mutex_unlock:
mutex_unlock(&fbdefio->lock);
return ret;
}
/*
* fb_deferred_io_page_mkwrite - Mark a page as written for deferred I/O
* @fb_info: The fbdev info structure
* @vmf: The VM fault
*
* This is a callback we get when userspace first tries to
* write to the page. We schedule a workqueue. That workqueue
* will eventually mkclean the touched pages and execute the
* deferred framebuffer IO. Then if userspace touches a page
* again, we repeat the same scheme.
*
* Returns:
* VM_FAULT_LOCKED on success, or a VM_FAULT error otherwise.
*/
static vm_fault_t fb_deferred_io_page_mkwrite(struct fb_info *info, struct vm_fault *vmf)
{
unsigned long offset = vmf->address - vmf->vma->vm_start;
struct page *page = vmf->page;
file_update_time(vmf->vma->vm_file);
return fb_deferred_io_track_page(info, offset, page);
}
/* vm_ops->page_mkwrite handler */
static vm_fault_t fb_deferred_io_mkwrite(struct vm_fault *vmf)
{
struct fb_info *info = vmf->vma->vm_private_data;
return fb_deferred_io_page_mkwrite(info, vmf);
}
static const struct vm_operations_struct fb_deferred_io_vm_ops = {
.fault = fb_deferred_io_fault,
.page_mkwrite = fb_deferred_io_mkwrite,
};
static const struct address_space_operations fb_deferred_io_aops = {
.dirty_folio = noop_dirty_folio,
};
int fb_deferred_io_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
vma->vm_ops = &fb_deferred_io_vm_ops;
vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP);
if (!(info->flags & FBINFO_VIRTFB))
vm_flags_set(vma, VM_IO);
vma->vm_private_data = info;
return 0;
}
EXPORT_SYMBOL_GPL(fb_deferred_io_mmap);
/* workqueue callback */
static void fb_deferred_io_work(struct work_struct *work)
{
struct fb_info *info = container_of(work, struct fb_info, deferred_work.work);
struct fb_deferred_io_pageref *pageref, *next;
struct fb_deferred_io *fbdefio = info->fbdefio;
/* here we mkclean the pages, then do all deferred IO */
mutex_lock(&fbdefio->lock);
list_for_each_entry(pageref, &fbdefio->pagereflist, list) {
struct page *cur = pageref->page;
lock_page(cur);
page_mkclean(cur);
unlock_page(cur);
}
/* driver's callback with pagereflist */
fbdefio->deferred_io(info, &fbdefio->pagereflist);
/* clear the list */
list_for_each_entry_safe(pageref, next, &fbdefio->pagereflist, list)
fb_deferred_io_pageref_put(pageref, info);
mutex_unlock(&fbdefio->lock);
}
int fb_deferred_io_init(struct fb_info *info)
{
struct fb_deferred_io *fbdefio = info->fbdefio;
struct fb_deferred_io_pageref *pagerefs;
unsigned long npagerefs, i;
int ret;
BUG_ON(!fbdefio);
if (WARN_ON(!info->fix.smem_len))
return -EINVAL;
mutex_init(&fbdefio->lock);
INIT_DELAYED_WORK(&info->deferred_work, fb_deferred_io_work);
INIT_LIST_HEAD(&fbdefio->pagereflist);
if (fbdefio->delay == 0) /* set a default of 1 s */
fbdefio->delay = HZ;
npagerefs = DIV_ROUND_UP(info->fix.smem_len, PAGE_SIZE);
/* alloc a page ref for each page of the display memory */
pagerefs = kvcalloc(npagerefs, sizeof(*pagerefs), GFP_KERNEL);
if (!pagerefs) {
ret = -ENOMEM;
goto err;
}
for (i = 0; i < npagerefs; ++i)
INIT_LIST_HEAD(&pagerefs[i].list);
info->npagerefs = npagerefs;
info->pagerefs = pagerefs;
return 0;
err:
mutex_destroy(&fbdefio->lock);
return ret;
}
EXPORT_SYMBOL_GPL(fb_deferred_io_init);
void fb_deferred_io_open(struct fb_info *info,
struct inode *inode,
struct file *file)
{
struct fb_deferred_io *fbdefio = info->fbdefio;
file->f_mapping->a_ops = &fb_deferred_io_aops;
fbdefio->open_count++;
}
EXPORT_SYMBOL_GPL(fb_deferred_io_open);
static void fb_deferred_io_lastclose(struct fb_info *info)
{
struct page *page;
int i;
cancel_delayed_work_sync(&info->deferred_work);
/* clear out the mapping that we setup */
for (i = 0 ; i < info->fix.smem_len; i += PAGE_SIZE) {
page = fb_deferred_io_page(info, i);
page->mapping = NULL;
}
}
void fb_deferred_io_release(struct fb_info *info)
{
struct fb_deferred_io *fbdefio = info->fbdefio;
if (!--fbdefio->open_count)
fb_deferred_io_lastclose(info);
}
EXPORT_SYMBOL_GPL(fb_deferred_io_release);
void fb_deferred_io_cleanup(struct fb_info *info)
{
struct fb_deferred_io *fbdefio = info->fbdefio;
fb_deferred_io_lastclose(info);
kvfree(info->pagerefs);
mutex_destroy(&fbdefio->lock);
}
EXPORT_SYMBOL_GPL(fb_deferred_io_cleanup);
| linux-master | drivers/video/fbdev/core/fb_defio.c |
// SPDX-License-Identifier: GPL-2.0-or-later
#include <linux/export.h>
#include <linux/fb.h>
#include <linux/mutex.h>
#include <linux/slab.h>
/**
* framebuffer_alloc - creates a new frame buffer info structure
*
* @size: size of driver private data, can be zero
* @dev: pointer to the device for this fb, this can be NULL
*
* Creates a new frame buffer info structure. Also reserves @size bytes
* for driver private data (info->par). info->par (if any) will be
* aligned to sizeof(long). The new instances of struct fb_info and
* the driver private data are both cleared to zero.
*
* Returns the new structure, or NULL if an error occurred.
*
*/
struct fb_info *framebuffer_alloc(size_t size, struct device *dev)
{
#define BYTES_PER_LONG (BITS_PER_LONG/8)
#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
int fb_info_size = sizeof(struct fb_info);
struct fb_info *info;
char *p;
if (size)
fb_info_size += PADDING;
p = kzalloc(fb_info_size + size, GFP_KERNEL);
if (!p)
return NULL;
info = (struct fb_info *) p;
if (size)
info->par = p + fb_info_size;
info->device = dev;
info->fbcon_rotate_hint = -1;
#if IS_ENABLED(CONFIG_FB_BACKLIGHT)
mutex_init(&info->bl_curve_mutex);
#endif
return info;
#undef PADDING
#undef BYTES_PER_LONG
}
EXPORT_SYMBOL(framebuffer_alloc);
/**
* framebuffer_release - marks the structure available for freeing
*
* @info: frame buffer info structure
*
* Drop the reference count of the device embedded in the
* framebuffer info structure.
*
*/
void framebuffer_release(struct fb_info *info)
{
if (!info)
return;
if (WARN_ON(refcount_read(&info->count)))
return;
#if IS_ENABLED(CONFIG_FB_BACKLIGHT)
mutex_destroy(&info->bl_curve_mutex);
#endif
kfree(info);
}
EXPORT_SYMBOL(framebuffer_release);
| linux-master | drivers/video/fbdev/core/fb_info.c |
/*
* linux/drivers/video/console/tileblit.c -- Tile Blitting Operation
*
* Copyright (C) 2004 Antonino Daplas <adaplas @pol.net>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/vt_kern.h>
#include <linux/console.h>
#include <asm/types.h>
#include "fbcon.h"
static void tile_bmove(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int dy, int dx, int height, int width)
{
struct fb_tilearea area;
area.sx = sx;
area.sy = sy;
area.dx = dx;
area.dy = dy;
area.height = height;
area.width = width;
info->tileops->fb_tilecopy(info, &area);
}
static void tile_clear(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int height, int width)
{
struct fb_tilerect rect;
int bgshift = (vc->vc_hi_font_mask) ? 13 : 12;
int fgshift = (vc->vc_hi_font_mask) ? 9 : 8;
rect.index = vc->vc_video_erase_char &
((vc->vc_hi_font_mask) ? 0x1ff : 0xff);
rect.fg = attr_fgcol_ec(fgshift, vc, info);
rect.bg = attr_bgcol_ec(bgshift, vc, info);
rect.sx = sx;
rect.sy = sy;
rect.width = width;
rect.height = height;
rect.rop = ROP_COPY;
info->tileops->fb_tilefill(info, &rect);
}
static void tile_putcs(struct vc_data *vc, struct fb_info *info,
const unsigned short *s, int count, int yy, int xx,
int fg, int bg)
{
struct fb_tileblit blit;
unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
int size = sizeof(u32) * count, i;
blit.sx = xx;
blit.sy = yy;
blit.width = count;
blit.height = 1;
blit.fg = fg;
blit.bg = bg;
blit.length = count;
blit.indices = (u32 *) fb_get_buffer_offset(info, &info->pixmap, size);
for (i = 0; i < count; i++)
blit.indices[i] = (u32)(scr_readw(s++) & charmask);
info->tileops->fb_tileblit(info, &blit);
}
static void tile_clear_margins(struct vc_data *vc, struct fb_info *info,
int color, int bottom_only)
{
return;
}
static void tile_cursor(struct vc_data *vc, struct fb_info *info, int mode,
int fg, int bg)
{
struct fb_tilecursor cursor;
int use_sw = vc->vc_cursor_type & CUR_SW;
cursor.sx = vc->state.x;
cursor.sy = vc->state.y;
cursor.mode = (mode == CM_ERASE || use_sw) ? 0 : 1;
cursor.fg = fg;
cursor.bg = bg;
switch (vc->vc_cursor_type & 0x0f) {
case CUR_NONE:
cursor.shape = FB_TILE_CURSOR_NONE;
break;
case CUR_UNDERLINE:
cursor.shape = FB_TILE_CURSOR_UNDERLINE;
break;
case CUR_LOWER_THIRD:
cursor.shape = FB_TILE_CURSOR_LOWER_THIRD;
break;
case CUR_LOWER_HALF:
cursor.shape = FB_TILE_CURSOR_LOWER_HALF;
break;
case CUR_TWO_THIRDS:
cursor.shape = FB_TILE_CURSOR_TWO_THIRDS;
break;
case CUR_BLOCK:
default:
cursor.shape = FB_TILE_CURSOR_BLOCK;
break;
}
info->tileops->fb_tilecursor(info, &cursor);
}
static int tile_update_start(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
int err;
err = fb_pan_display(info, &ops->var);
ops->var.xoffset = info->var.xoffset;
ops->var.yoffset = info->var.yoffset;
ops->var.vmode = info->var.vmode;
return err;
}
void fbcon_set_tileops(struct vc_data *vc, struct fb_info *info)
{
struct fb_tilemap map;
struct fbcon_ops *ops = info->fbcon_par;
ops->bmove = tile_bmove;
ops->clear = tile_clear;
ops->putcs = tile_putcs;
ops->clear_margins = tile_clear_margins;
ops->cursor = tile_cursor;
ops->update_start = tile_update_start;
if (ops->p) {
map.width = vc->vc_font.width;
map.height = vc->vc_font.height;
map.depth = 1;
map.length = vc->vc_font.charcount;
map.data = ops->p->fontdata;
info->tileops->fb_settile(info, &map);
}
}
| linux-master | drivers/video/fbdev/core/tileblit.c |
/*
* Generic 1-bit or 8-bit source to 1-32 bit destination expansion
* for frame buffer located in system RAM with packed pixels of any depth.
*
* Based almost entirely on cfbimgblt.c
*
* Copyright (C) April 2007 Antonino Daplas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/types.h>
#define DEBUG
#ifdef DEBUG
#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt,__func__,## args)
#else
#define DPRINTK(fmt, args...)
#endif
static const u32 cfb_tab8_be[] = {
0x00000000,0x000000ff,0x0000ff00,0x0000ffff,
0x00ff0000,0x00ff00ff,0x00ffff00,0x00ffffff,
0xff000000,0xff0000ff,0xff00ff00,0xff00ffff,
0xffff0000,0xffff00ff,0xffffff00,0xffffffff
};
static const u32 cfb_tab8_le[] = {
0x00000000,0xff000000,0x00ff0000,0xffff0000,
0x0000ff00,0xff00ff00,0x00ffff00,0xffffff00,
0x000000ff,0xff0000ff,0x00ff00ff,0xffff00ff,
0x0000ffff,0xff00ffff,0x00ffffff,0xffffffff
};
static const u32 cfb_tab16_be[] = {
0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff
};
static const u32 cfb_tab16_le[] = {
0x00000000, 0xffff0000, 0x0000ffff, 0xffffffff
};
static const u32 cfb_tab32[] = {
0x00000000, 0xffffffff
};
static void color_imageblit(const struct fb_image *image, struct fb_info *p,
void *dst1, u32 start_index, u32 pitch_index)
{
/* Draw the penguin */
u32 *dst, *dst2;
u32 color = 0, val, shift;
int i, n, bpp = p->var.bits_per_pixel;
u32 null_bits = 32 - bpp;
u32 *palette = (u32 *) p->pseudo_palette;
const u8 *src = image->data;
dst2 = dst1;
for (i = image->height; i--; ) {
n = image->width;
dst = dst1;
shift = 0;
val = 0;
if (start_index) {
u32 start_mask = ~(FB_SHIFT_HIGH(p, ~(u32)0,
start_index));
val = *dst & start_mask;
shift = start_index;
}
while (n--) {
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR )
color = palette[*src];
else
color = *src;
color <<= FB_LEFT_POS(p, bpp);
val |= FB_SHIFT_HIGH(p, color, shift);
if (shift >= null_bits) {
*dst++ = val;
val = (shift == null_bits) ? 0 :
FB_SHIFT_LOW(p, color, 32 - shift);
}
shift += bpp;
shift &= (32 - 1);
src++;
}
if (shift) {
u32 end_mask = FB_SHIFT_HIGH(p, ~(u32)0, shift);
*dst &= end_mask;
*dst |= val;
}
dst1 += p->fix.line_length;
if (pitch_index) {
dst2 += p->fix.line_length;
dst1 = (u8 *)((long)dst2 & ~(sizeof(u32) - 1));
start_index += pitch_index;
start_index &= 32 - 1;
}
}
}
static void slow_imageblit(const struct fb_image *image, struct fb_info *p,
void *dst1, u32 fgcolor, u32 bgcolor,
u32 start_index, u32 pitch_index)
{
u32 shift, color = 0, bpp = p->var.bits_per_pixel;
u32 *dst, *dst2;
u32 val, pitch = p->fix.line_length;
u32 null_bits = 32 - bpp;
u32 spitch = (image->width+7)/8;
const u8 *src = image->data, *s;
u32 i, j, l;
dst2 = dst1;
fgcolor <<= FB_LEFT_POS(p, bpp);
bgcolor <<= FB_LEFT_POS(p, bpp);
for (i = image->height; i--; ) {
shift = val = 0;
l = 8;
j = image->width;
dst = dst1;
s = src;
/* write leading bits */
if (start_index) {
u32 start_mask = ~(FB_SHIFT_HIGH(p, ~(u32)0,
start_index));
val = *dst & start_mask;
shift = start_index;
}
while (j--) {
l--;
color = (*s & (1 << l)) ? fgcolor : bgcolor;
val |= FB_SHIFT_HIGH(p, color, shift);
/* Did the bitshift spill bits to the next long? */
if (shift >= null_bits) {
*dst++ = val;
val = (shift == null_bits) ? 0 :
FB_SHIFT_LOW(p, color, 32 - shift);
}
shift += bpp;
shift &= (32 - 1);
if (!l) { l = 8; s++; }
}
/* write trailing bits */
if (shift) {
u32 end_mask = FB_SHIFT_HIGH(p, ~(u32)0, shift);
*dst &= end_mask;
*dst |= val;
}
dst1 += pitch;
src += spitch;
if (pitch_index) {
dst2 += pitch;
dst1 = (u8 *)((long)dst2 & ~(sizeof(u32) - 1));
start_index += pitch_index;
start_index &= 32 - 1;
}
}
}
/*
* fast_imageblit - optimized monochrome color expansion
*
* Only if: bits_per_pixel == 8, 16, or 32
* image->width is divisible by pixel/dword (ppw);
* fix->line_legth is divisible by 4;
* beginning and end of a scanline is dword aligned
*/
static void fast_imageblit(const struct fb_image *image, struct fb_info *p,
void *dst1, u32 fgcolor, u32 bgcolor)
{
u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel;
u32 ppw = 32/bpp, spitch = (image->width + 7)/8;
u32 bit_mask, eorx, shift;
const u8 *s = image->data, *src;
u32 *dst;
const u32 *tab;
size_t tablen;
u32 colortab[16];
int i, j, k;
switch (bpp) {
case 8:
tab = fb_be_math(p) ? cfb_tab8_be : cfb_tab8_le;
tablen = 16;
break;
case 16:
tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le;
tablen = 4;
break;
case 32:
tab = cfb_tab32;
tablen = 2;
break;
default:
return;
}
for (i = ppw-1; i--; ) {
fgx <<= bpp;
bgx <<= bpp;
fgx |= fgcolor;
bgx |= bgcolor;
}
bit_mask = (1 << ppw) - 1;
eorx = fgx ^ bgx;
k = image->width/ppw;
for (i = 0; i < tablen; ++i)
colortab[i] = (tab[i] & eorx) ^ bgx;
for (i = image->height; i--; ) {
dst = dst1;
shift = 8;
src = s;
/*
* Manually unroll the per-line copying loop for better
* performance. This works until we processed the last
* completely filled source byte (inclusive).
*/
switch (ppw) {
case 4: /* 8 bpp */
for (j = k; j >= 2; j -= 2, ++src) {
*dst++ = colortab[(*src >> 4) & bit_mask];
*dst++ = colortab[(*src >> 0) & bit_mask];
}
break;
case 2: /* 16 bpp */
for (j = k; j >= 4; j -= 4, ++src) {
*dst++ = colortab[(*src >> 6) & bit_mask];
*dst++ = colortab[(*src >> 4) & bit_mask];
*dst++ = colortab[(*src >> 2) & bit_mask];
*dst++ = colortab[(*src >> 0) & bit_mask];
}
break;
case 1: /* 32 bpp */
for (j = k; j >= 8; j -= 8, ++src) {
*dst++ = colortab[(*src >> 7) & bit_mask];
*dst++ = colortab[(*src >> 6) & bit_mask];
*dst++ = colortab[(*src >> 5) & bit_mask];
*dst++ = colortab[(*src >> 4) & bit_mask];
*dst++ = colortab[(*src >> 3) & bit_mask];
*dst++ = colortab[(*src >> 2) & bit_mask];
*dst++ = colortab[(*src >> 1) & bit_mask];
*dst++ = colortab[(*src >> 0) & bit_mask];
}
break;
}
/*
* For image widths that are not a multiple of 8, there
* are trailing pixels left on the current line. Print
* them as well.
*/
for (; j--; ) {
shift -= ppw;
*dst++ = colortab[(*src >> shift) & bit_mask];
if (!shift) {
shift = 8;
++src;
}
}
dst1 += p->fix.line_length;
s += spitch;
}
}
void sys_imageblit(struct fb_info *p, const struct fb_image *image)
{
u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;
u32 bpl = sizeof(u32), bpp = p->var.bits_per_pixel;
u32 width = image->width;
u32 dx = image->dx, dy = image->dy;
void *dst1;
if (p->state != FBINFO_STATE_RUNNING)
return;
bitstart = (dy * p->fix.line_length * 8) + (dx * bpp);
start_index = bitstart & (32 - 1);
pitch_index = (p->fix.line_length & (bpl - 1)) * 8;
bitstart /= 8;
bitstart &= ~(bpl - 1);
dst1 = (void __force *)p->screen_base + bitstart;
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
if (image->depth == 1) {
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR) {
fgcolor = ((u32*)(p->pseudo_palette))[image->fg_color];
bgcolor = ((u32*)(p->pseudo_palette))[image->bg_color];
} else {
fgcolor = image->fg_color;
bgcolor = image->bg_color;
}
if (32 % bpp == 0 && !start_index && !pitch_index &&
((width & (32/bpp-1)) == 0) &&
bpp >= 8 && bpp <= 32)
fast_imageblit(image, p, dst1, fgcolor, bgcolor);
else
slow_imageblit(image, p, dst1, fgcolor, bgcolor,
start_index, pitch_index);
} else
color_imageblit(image, p, dst1, start_index, pitch_index);
}
EXPORT_SYMBOL(sys_imageblit);
MODULE_AUTHOR("Antonino Daplas <[email protected]>");
MODULE_DESCRIPTION("1-bit/8-bit to 1-32 bit color expansion (sys-to-sys)");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/sysimgblt.c |
/*
* linux/drivers/video/modedb.c -- Standard video mode database management
*
* Copyright (C) 1999 Geert Uytterhoeven
*
* 2001 - Documented with DocBook
* - Brad Douglas <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/kernel.h>
#undef DEBUG
#define name_matches(v, s, l) \
((v).name && !strncmp((s), (v).name, (l)) && strlen((v).name) == (l))
#define res_matches(v, x, y) \
((v).xres == (x) && (v).yres == (y))
#ifdef DEBUG
#define DPRINTK(fmt, args...) printk("modedb %s: " fmt, __func__ , ## args)
#else
#define DPRINTK(fmt, args...)
#endif
/*
* Standard video mode definitions (taken from XFree86)
*/
static const struct fb_videomode modedb[] = {
/* 640x400 @ 70 Hz, 31.5 kHz hsync */
{ NULL, 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2, 0,
FB_VMODE_NONINTERLACED },
/* 640x480 @ 60 Hz, 31.5 kHz hsync */
{ NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
FB_VMODE_NONINTERLACED },
/* 800x600 @ 56 Hz, 35.15 kHz hsync */
{ NULL, 56, 800, 600, 27777, 128, 24, 22, 1, 72, 2, 0,
FB_VMODE_NONINTERLACED },
/* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
{ NULL, 87, 1024, 768, 22271, 56, 24, 33, 8, 160, 8, 0,
FB_VMODE_INTERLACED },
/* 640x400 @ 85 Hz, 37.86 kHz hsync */
{ NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED },
/* 640x480 @ 72 Hz, 36.5 kHz hsync */
{ NULL, 72, 640, 480, 31746, 144, 40, 30, 8, 40, 3, 0,
FB_VMODE_NONINTERLACED },
/* 640x480 @ 75 Hz, 37.50 kHz hsync */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3, 0,
FB_VMODE_NONINTERLACED },
/* 800x600 @ 60 Hz, 37.8 kHz hsync */
{ NULL, 60, 800, 600, 25000, 88, 40, 23, 1, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 640x480 @ 85 Hz, 43.27 kHz hsync */
{ NULL, 85, 640, 480, 27777, 80, 56, 25, 1, 56, 3, 0,
FB_VMODE_NONINTERLACED },
/* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
{ NULL, 89, 1152, 864, 15384, 96, 16, 110, 1, 216, 10, 0,
FB_VMODE_INTERLACED },
/* 800x600 @ 72 Hz, 48.0 kHz hsync */
{ NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1024x768 @ 60 Hz, 48.4 kHz hsync */
{ NULL, 60, 1024, 768, 15384, 168, 8, 29, 3, 144, 6, 0,
FB_VMODE_NONINTERLACED },
/* 640x480 @ 100 Hz, 53.01 kHz hsync */
{ NULL, 100, 640, 480, 21834, 96, 32, 36, 8, 96, 6, 0,
FB_VMODE_NONINTERLACED },
/* 1152x864 @ 60 Hz, 53.5 kHz hsync */
{ NULL, 60, 1152, 864, 11123, 208, 64, 16, 4, 256, 8, 0,
FB_VMODE_NONINTERLACED },
/* 800x600 @ 85 Hz, 55.84 kHz hsync */
{ NULL, 85, 800, 600, 16460, 160, 64, 36, 16, 64, 5, 0,
FB_VMODE_NONINTERLACED },
/* 1024x768 @ 70 Hz, 56.5 kHz hsync */
{ NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6, 0,
FB_VMODE_NONINTERLACED },
/* 1280x1024 @ 87 Hz interlaced, 51 kHz hsync */
{ NULL, 87, 1280, 1024, 12500, 56, 16, 128, 1, 216, 12, 0,
FB_VMODE_INTERLACED },
/* 800x600 @ 100 Hz, 64.02 kHz hsync */
{ NULL, 100, 800, 600, 14357, 160, 64, 30, 4, 64, 6, 0,
FB_VMODE_NONINTERLACED },
/* 1024x768 @ 76 Hz, 62.5 kHz hsync */
{ NULL, 76, 1024, 768, 11764, 208, 8, 36, 16, 120, 3, 0,
FB_VMODE_NONINTERLACED },
/* 1152x864 @ 70 Hz, 62.4 kHz hsync */
{ NULL, 70, 1152, 864, 10869, 106, 56, 20, 1, 160, 10, 0,
FB_VMODE_NONINTERLACED },
/* 1280x1024 @ 61 Hz, 64.2 kHz hsync */
{ NULL, 61, 1280, 1024, 9090, 200, 48, 26, 1, 184, 3, 0,
FB_VMODE_NONINTERLACED },
/* 1400x1050 @ 60Hz, 63.9 kHz hsync */
{ NULL, 60, 1400, 1050, 9259, 136, 40, 13, 1, 112, 3, 0,
FB_VMODE_NONINTERLACED },
/* 1400x1050 @ 75,107 Hz, 82,392 kHz +hsync +vsync*/
{ NULL, 75, 1400, 1050, 7190, 120, 56, 23, 10, 112, 13,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1400x1050 @ 60 Hz, ? kHz +hsync +vsync*/
{ NULL, 60, 1400, 1050, 9259, 128, 40, 12, 0, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1024x768 @ 85 Hz, 70.24 kHz hsync */
{ NULL, 85, 1024, 768, 10111, 192, 32, 34, 14, 160, 6, 0,
FB_VMODE_NONINTERLACED },
/* 1152x864 @ 78 Hz, 70.8 kHz hsync */
{ NULL, 78, 1152, 864, 9090, 228, 88, 32, 0, 84, 12, 0,
FB_VMODE_NONINTERLACED },
/* 1280x1024 @ 70 Hz, 74.59 kHz hsync */
{ NULL, 70, 1280, 1024, 7905, 224, 32, 28, 8, 160, 8, 0,
FB_VMODE_NONINTERLACED },
/* 1600x1200 @ 60Hz, 75.00 kHz hsync */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1152x864 @ 84 Hz, 76.0 kHz hsync */
{ NULL, 84, 1152, 864, 7407, 184, 312, 32, 0, 128, 12, 0,
FB_VMODE_NONINTERLACED },
/* 1280x1024 @ 74 Hz, 78.85 kHz hsync */
{ NULL, 74, 1280, 1024, 7407, 256, 32, 34, 3, 144, 3, 0,
FB_VMODE_NONINTERLACED },
/* 1024x768 @ 100Hz, 80.21 kHz hsync */
{ NULL, 100, 1024, 768, 8658, 192, 32, 21, 3, 192, 10, 0,
FB_VMODE_NONINTERLACED },
/* 1280x1024 @ 76 Hz, 81.13 kHz hsync */
{ NULL, 76, 1280, 1024, 7407, 248, 32, 34, 3, 104, 3, 0,
FB_VMODE_NONINTERLACED },
/* 1600x1200 @ 70 Hz, 87.50 kHz hsync */
{ NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3, 0,
FB_VMODE_NONINTERLACED },
/* 1152x864 @ 100 Hz, 89.62 kHz hsync */
{ NULL, 100, 1152, 864, 7264, 224, 32, 17, 2, 128, 19, 0,
FB_VMODE_NONINTERLACED },
/* 1280x1024 @ 85 Hz, 91.15 kHz hsync */
{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1600x1200 @ 75 Hz, 93.75 kHz hsync */
{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1680x1050 @ 60 Hz, 65.191 kHz hsync */
{ NULL, 60, 1680, 1050, 6848, 280, 104, 30, 3, 176, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1600x1200 @ 85 Hz, 105.77 kHz hsync */
{ NULL, 85, 1600, 1200, 4545, 272, 16, 37, 4, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1280x1024 @ 100 Hz, 107.16 kHz hsync */
{ NULL, 100, 1280, 1024, 5502, 256, 32, 26, 7, 128, 15, 0,
FB_VMODE_NONINTERLACED },
/* 1800x1440 @ 64Hz, 96.15 kHz hsync */
{ NULL, 64, 1800, 1440, 4347, 304, 96, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1800x1440 @ 70Hz, 104.52 kHz hsync */
{ NULL, 70, 1800, 1440, 4000, 304, 96, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 512x384 @ 78 Hz, 31.50 kHz hsync */
{ NULL, 78, 512, 384, 49603, 48, 16, 16, 1, 64, 3, 0,
FB_VMODE_NONINTERLACED },
/* 512x384 @ 85 Hz, 34.38 kHz hsync */
{ NULL, 85, 512, 384, 45454, 48, 16, 16, 1, 64, 3, 0,
FB_VMODE_NONINTERLACED },
/* 320x200 @ 70 Hz, 31.5 kHz hsync, 8:5 aspect ratio */
{ NULL, 70, 320, 200, 79440, 16, 16, 20, 4, 48, 1, 0,
FB_VMODE_DOUBLE },
/* 320x240 @ 60 Hz, 31.5 kHz hsync, 4:3 aspect ratio */
{ NULL, 60, 320, 240, 79440, 16, 16, 16, 5, 48, 1, 0,
FB_VMODE_DOUBLE },
/* 320x240 @ 72 Hz, 36.5 kHz hsync */
{ NULL, 72, 320, 240, 63492, 16, 16, 16, 4, 48, 2, 0,
FB_VMODE_DOUBLE },
/* 400x300 @ 56 Hz, 35.2 kHz hsync, 4:3 aspect ratio */
{ NULL, 56, 400, 300, 55555, 64, 16, 10, 1, 32, 1, 0,
FB_VMODE_DOUBLE },
/* 400x300 @ 60 Hz, 37.8 kHz hsync */
{ NULL, 60, 400, 300, 50000, 48, 16, 11, 1, 64, 2, 0,
FB_VMODE_DOUBLE },
/* 400x300 @ 72 Hz, 48.0 kHz hsync */
{ NULL, 72, 400, 300, 40000, 32, 24, 11, 19, 64, 3, 0,
FB_VMODE_DOUBLE },
/* 480x300 @ 56 Hz, 35.2 kHz hsync, 8:5 aspect ratio */
{ NULL, 56, 480, 300, 46176, 80, 16, 10, 1, 40, 1, 0,
FB_VMODE_DOUBLE },
/* 480x300 @ 60 Hz, 37.8 kHz hsync */
{ NULL, 60, 480, 300, 41858, 56, 16, 11, 1, 80, 2, 0,
FB_VMODE_DOUBLE },
/* 480x300 @ 63 Hz, 39.6 kHz hsync */
{ NULL, 63, 480, 300, 40000, 56, 16, 11, 1, 80, 2, 0,
FB_VMODE_DOUBLE },
/* 480x300 @ 72 Hz, 48.0 kHz hsync */
{ NULL, 72, 480, 300, 33386, 40, 24, 11, 19, 80, 3, 0,
FB_VMODE_DOUBLE },
/* 1920x1080 @ 60 Hz, 67.3 kHz hsync */
{ NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5, 0,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1920x1200 @ 60 Hz, 74.5 Khz hsync */
{ NULL, 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1152x768, 60 Hz, PowerBook G4 Titanium I and II */
{ NULL, 60, 1152, 768, 14047, 158, 26, 29, 3, 136, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED },
/* 1366x768, 60 Hz, 47.403 kHz hsync, WXGA 16:9 aspect ratio */
{ NULL, 60, 1366, 768, 13806, 120, 10, 14, 3, 32, 5, 0,
FB_VMODE_NONINTERLACED },
/* 1280x800, 60 Hz, 47.403 kHz hsync, WXGA 16:10 aspect ratio */
{ NULL, 60, 1280, 800, 12048, 200, 64, 24, 1, 136, 3, 0,
FB_VMODE_NONINTERLACED },
/* 720x576i @ 50 Hz, 15.625 kHz hsync (PAL RGB) */
{ NULL, 50, 720, 576, 74074, 64, 16, 39, 5, 64, 5, 0,
FB_VMODE_INTERLACED },
/* 800x520i @ 50 Hz, 15.625 kHz hsync (PAL RGB) */
{ NULL, 50, 800, 520, 58823, 144, 64, 72, 28, 80, 5, 0,
FB_VMODE_INTERLACED },
/* 864x480 @ 60 Hz, 35.15 kHz hsync */
{ NULL, 60, 864, 480, 27777, 1, 1, 1, 1, 0, 0,
0, FB_VMODE_NONINTERLACED },
};
#ifdef CONFIG_FB_MODE_HELPERS
const struct fb_videomode vesa_modes[] = {
/* 0 640x350-85 VESA */
{ NULL, 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3,
FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA},
/* 1 640x400-85 VESA */
{ NULL, 85, 640, 400, 31746, 96, 32, 41, 01, 64, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 2 720x400-85 VESA */
{ NULL, 85, 721, 400, 28169, 108, 36, 42, 01, 72, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 3 640x480-60 VESA */
{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 4 640x480-72 VESA */
{ NULL, 72, 640, 480, 31746, 128, 24, 29, 9, 40, 2,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 5 640x480-75 VESA */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 6 640x480-85 VESA */
{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 7 800x600-56 VESA */
{ NULL, 56, 800, 600, 27777, 128, 24, 22, 01, 72, 2,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 8 800x600-60 VESA */
{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 9 800x600-72 VESA */
{ NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 10 800x600-75 VESA */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 11 800x600-85 VESA */
{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 12 1024x768i-43 VESA */
{ NULL, 43, 1024, 768, 22271, 56, 8, 41, 0, 176, 8,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_INTERLACED, FB_MODE_IS_VESA },
/* 13 1024x768-60 VESA */
{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 14 1024x768-70 VESA */
{ NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 15 1024x768-75 VESA */
{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 16 1024x768-85 VESA */
{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 17 1152x864-75 VESA */
{ NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 18 1280x960-60 VESA */
{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 19 1280x960-85 VESA */
{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 20 1280x1024-60 VESA */
{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 21 1280x1024-75 VESA */
{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 22 1280x1024-85 VESA */
{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 23 1600x1200-60 VESA */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 24 1600x1200-65 VESA */
{ NULL, 65, 1600, 1200, 5698, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 25 1600x1200-70 VESA */
{ NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 26 1600x1200-75 VESA */
{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 27 1600x1200-85 VESA */
{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 28 1792x1344-60 VESA */
{ NULL, 60, 1792, 1344, 4882, 328, 128, 46, 1, 200, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 29 1792x1344-75 VESA */
{ NULL, 75, 1792, 1344, 3831, 352, 96, 69, 1, 216, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 30 1856x1392-60 VESA */
{ NULL, 60, 1856, 1392, 4580, 352, 96, 43, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 31 1856x1392-75 VESA */
{ NULL, 75, 1856, 1392, 3472, 352, 128, 104, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 32 1920x1440-60 VESA */
{ NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 200, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 33 1920x1440-75 VESA */
{ NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 34 1920x1200-60 RB VESA */
{ NULL, 60, 1920, 1200, 6493, 80, 48, 26, 3, 32, 6,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 35 1920x1200-60 VESA */
{ NULL, 60, 1920, 1200, 5174, 336, 136, 36, 3, 200, 6,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 36 1920x1200-75 VESA */
{ NULL, 75, 1920, 1200, 4077, 344, 136, 46, 3, 208, 6,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 37 1920x1200-85 VESA */
{ NULL, 85, 1920, 1200, 3555, 352, 144, 53, 3, 208, 6,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 38 2560x1600-60 RB VESA */
{ NULL, 60, 2560, 1600, 3724, 80, 48, 37, 3, 32, 6,
FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 39 2560x1600-60 VESA */
{ NULL, 60, 2560, 1600, 2869, 472, 192, 49, 3, 280, 6,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 40 2560x1600-75 VESA */
{ NULL, 75, 2560, 1600, 2256, 488, 208, 63, 3, 280, 6,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 41 2560x1600-85 VESA */
{ NULL, 85, 2560, 1600, 1979, 488, 208, 73, 3, 280, 6,
FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 42 2560x1600-120 RB VESA */
{ NULL, 120, 2560, 1600, 1809, 80, 48, 85, 3, 32, 6,
FB_SYNC_HOR_HIGH_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
};
EXPORT_SYMBOL(vesa_modes);
const struct dmt_videomode dmt_modes[DMT_SIZE] = {
{ 0x01, 0x0000, 0x000000, &vesa_modes[0] },
{ 0x02, 0x3119, 0x000000, &vesa_modes[1] },
{ 0x03, 0x0000, 0x000000, &vesa_modes[2] },
{ 0x04, 0x3140, 0x000000, &vesa_modes[3] },
{ 0x05, 0x314c, 0x000000, &vesa_modes[4] },
{ 0x06, 0x314f, 0x000000, &vesa_modes[5] },
{ 0x07, 0x3159, 0x000000, &vesa_modes[6] },
{ 0x08, 0x0000, 0x000000, &vesa_modes[7] },
{ 0x09, 0x4540, 0x000000, &vesa_modes[8] },
{ 0x0a, 0x454c, 0x000000, &vesa_modes[9] },
{ 0x0b, 0x454f, 0x000000, &vesa_modes[10] },
{ 0x0c, 0x4559, 0x000000, &vesa_modes[11] },
{ 0x0d, 0x0000, 0x000000, NULL },
{ 0x0e, 0x0000, 0x000000, NULL },
{ 0x0f, 0x0000, 0x000000, &vesa_modes[12] },
{ 0x10, 0x6140, 0x000000, &vesa_modes[13] },
{ 0x11, 0x614a, 0x000000, &vesa_modes[14] },
{ 0x12, 0x614f, 0x000000, &vesa_modes[15] },
{ 0x13, 0x6159, 0x000000, &vesa_modes[16] },
{ 0x14, 0x0000, 0x000000, NULL },
{ 0x15, 0x714f, 0x000000, &vesa_modes[17] },
{ 0x16, 0x0000, 0x7f1c21, NULL },
{ 0x17, 0x0000, 0x7f1c28, NULL },
{ 0x18, 0x0000, 0x7f1c44, NULL },
{ 0x19, 0x0000, 0x7f1c62, NULL },
{ 0x1a, 0x0000, 0x000000, NULL },
{ 0x1b, 0x0000, 0x8f1821, NULL },
{ 0x1c, 0x8100, 0x8f1828, NULL },
{ 0x1d, 0x810f, 0x8f1844, NULL },
{ 0x1e, 0x8119, 0x8f1862, NULL },
{ 0x1f, 0x0000, 0x000000, NULL },
{ 0x20, 0x8140, 0x000000, &vesa_modes[18] },
{ 0x21, 0x8159, 0x000000, &vesa_modes[19] },
{ 0x22, 0x0000, 0x000000, NULL },
{ 0x23, 0x8180, 0x000000, &vesa_modes[20] },
{ 0x24, 0x818f, 0x000000, &vesa_modes[21] },
{ 0x25, 0x8199, 0x000000, &vesa_modes[22] },
{ 0x26, 0x0000, 0x000000, NULL },
{ 0x27, 0x0000, 0x000000, NULL },
{ 0x28, 0x0000, 0x000000, NULL },
{ 0x29, 0x0000, 0x0c2021, NULL },
{ 0x2a, 0x9040, 0x0c2028, NULL },
{ 0x2b, 0x904f, 0x0c2044, NULL },
{ 0x2c, 0x9059, 0x0c2062, NULL },
{ 0x2d, 0x0000, 0x000000, NULL },
{ 0x2e, 0x9500, 0xc11821, NULL },
{ 0x2f, 0x9500, 0xc11828, NULL },
{ 0x30, 0x950f, 0xc11844, NULL },
{ 0x31, 0x9519, 0xc11868, NULL },
{ 0x32, 0x0000, 0x000000, NULL },
{ 0x33, 0xa940, 0x000000, &vesa_modes[23] },
{ 0x34, 0xa945, 0x000000, &vesa_modes[24] },
{ 0x35, 0xa94a, 0x000000, &vesa_modes[25] },
{ 0x36, 0xa94f, 0x000000, &vesa_modes[26] },
{ 0x37, 0xa959, 0x000000, &vesa_modes[27] },
{ 0x38, 0x0000, 0x000000, NULL },
{ 0x39, 0x0000, 0x0c2821, NULL },
{ 0x3a, 0xb300, 0x0c2828, NULL },
{ 0x3b, 0xb30f, 0x0c2844, NULL },
{ 0x3c, 0xb319, 0x0c2868, NULL },
{ 0x3d, 0x0000, 0x000000, NULL },
{ 0x3e, 0xc140, 0x000000, &vesa_modes[28] },
{ 0x3f, 0xc14f, 0x000000, &vesa_modes[29] },
{ 0x40, 0x0000, 0x000000, NULL},
{ 0x41, 0xc940, 0x000000, &vesa_modes[30] },
{ 0x42, 0xc94f, 0x000000, &vesa_modes[31] },
{ 0x43, 0x0000, 0x000000, NULL },
{ 0x44, 0x0000, 0x572821, &vesa_modes[34] },
{ 0x45, 0xd100, 0x572828, &vesa_modes[35] },
{ 0x46, 0xd10f, 0x572844, &vesa_modes[36] },
{ 0x47, 0xd119, 0x572862, &vesa_modes[37] },
{ 0x48, 0x0000, 0x000000, NULL },
{ 0x49, 0xd140, 0x000000, &vesa_modes[32] },
{ 0x4a, 0xd14f, 0x000000, &vesa_modes[33] },
{ 0x4b, 0x0000, 0x000000, NULL },
{ 0x4c, 0x0000, 0x1f3821, &vesa_modes[38] },
{ 0x4d, 0x0000, 0x1f3828, &vesa_modes[39] },
{ 0x4e, 0x0000, 0x1f3844, &vesa_modes[40] },
{ 0x4f, 0x0000, 0x1f3862, &vesa_modes[41] },
{ 0x50, 0x0000, 0x000000, &vesa_modes[42] },
};
EXPORT_SYMBOL(dmt_modes);
#endif /* CONFIG_FB_MODE_HELPERS */
/**
* fb_try_mode - test a video mode
* @var: frame buffer user defined part of display
* @info: frame buffer info structure
* @mode: frame buffer video mode structure
* @bpp: color depth in bits per pixel
*
* Tries a video mode to test it's validity for device @info.
*
* Returns 1 on success.
*
*/
static int fb_try_mode(struct fb_var_screeninfo *var, struct fb_info *info,
const struct fb_videomode *mode, unsigned int bpp)
{
int err = 0;
DPRINTK("Trying mode %s %dx%d-%d@%d\n",
mode->name ? mode->name : "noname",
mode->xres, mode->yres, bpp, mode->refresh);
var->xres = mode->xres;
var->yres = mode->yres;
var->xres_virtual = mode->xres;
var->yres_virtual = mode->yres;
var->xoffset = 0;
var->yoffset = 0;
var->bits_per_pixel = bpp;
var->activate |= FB_ACTIVATE_TEST;
var->pixclock = mode->pixclock;
var->left_margin = mode->left_margin;
var->right_margin = mode->right_margin;
var->upper_margin = mode->upper_margin;
var->lower_margin = mode->lower_margin;
var->hsync_len = mode->hsync_len;
var->vsync_len = mode->vsync_len;
var->sync = mode->sync;
var->vmode = mode->vmode;
if (info->fbops->fb_check_var)
err = info->fbops->fb_check_var(var, info);
var->activate &= ~FB_ACTIVATE_TEST;
return err;
}
/**
* fb_find_mode - finds a valid video mode
* @var: frame buffer user defined part of display
* @info: frame buffer info structure
* @mode_option: string video mode to find
* @db: video mode database
* @dbsize: size of @db
* @default_mode: default video mode to fall back to
* @default_bpp: default color depth in bits per pixel
*
* Finds a suitable video mode, starting with the specified mode
* in @mode_option with fallback to @default_mode. If
* @default_mode fails, all modes in the video mode database will
* be tried.
*
* Valid mode specifiers for @mode_option::
*
* <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][p][m]
*
* or ::
*
* <name>[-<bpp>][@<refresh>]
*
* with <xres>, <yres>, <bpp> and <refresh> decimal numbers and
* <name> a string.
*
* If 'M' is present after yres (and before refresh/bpp if present),
* the function will compute the timings using VESA(tm) Coordinated
* Video Timings (CVT). If 'R' is present after 'M', will compute with
* reduced blanking (for flatpanels). If 'i' or 'p' are present, compute
* interlaced or progressive mode. If 'm' is present, add margins equal
* to 1.8% of xres rounded down to 8 pixels, and 1.8% of yres. The char
* 'i', 'p' and 'm' must be after 'M' and 'R'. Example::
*
* 1024x768MR-8@60m - Reduced blank with margins at 60Hz.
*
* NOTE: The passed struct @var is _not_ cleared! This allows you
* to supply values for e.g. the grayscale and accel_flags fields.
*
* Returns zero for failure, 1 if using specified @mode_option,
* 2 if using specified @mode_option with an ignored refresh rate,
* 3 if default mode is used, 4 if fall back to any valid mode.
*/
int fb_find_mode(struct fb_var_screeninfo *var,
struct fb_info *info, const char *mode_option,
const struct fb_videomode *db, unsigned int dbsize,
const struct fb_videomode *default_mode,
unsigned int default_bpp)
{
char *mode_option_buf = NULL;
int i;
/* Set up defaults */
if (!db) {
db = modedb;
dbsize = ARRAY_SIZE(modedb);
}
if (!default_mode)
default_mode = &db[0];
if (!default_bpp)
default_bpp = 8;
/* Did the user specify a video mode? */
if (!mode_option) {
fb_get_options(NULL, &mode_option_buf);
mode_option = mode_option_buf;
}
if (mode_option) {
const char *name = mode_option;
unsigned int namelen = strlen(name);
int res_specified = 0, bpp_specified = 0, refresh_specified = 0;
unsigned int xres = 0, yres = 0, bpp = default_bpp, refresh = 0;
int yres_specified = 0, cvt = 0, rb = 0;
int interlace_specified = 0, interlace = 0;
int margins = 0;
u32 best, diff, tdiff;
for (i = namelen-1; i >= 0; i--) {
switch (name[i]) {
case '@':
namelen = i;
if (!refresh_specified && !bpp_specified &&
!yres_specified) {
refresh = simple_strtol(&name[i+1], NULL,
10);
refresh_specified = 1;
if (cvt || rb)
cvt = 0;
} else
goto done;
break;
case '-':
namelen = i;
if (!bpp_specified && !yres_specified) {
bpp = simple_strtol(&name[i+1], NULL,
10);
bpp_specified = 1;
if (cvt || rb)
cvt = 0;
} else
goto done;
break;
case 'x':
if (!yres_specified) {
yres = simple_strtol(&name[i+1], NULL,
10);
yres_specified = 1;
} else
goto done;
break;
case '0' ... '9':
break;
case 'M':
if (!yres_specified)
cvt = 1;
break;
case 'R':
if (!cvt)
rb = 1;
break;
case 'm':
if (!cvt)
margins = 1;
break;
case 'p':
if (!cvt) {
interlace = 0;
interlace_specified = 1;
}
break;
case 'i':
if (!cvt) {
interlace = 1;
interlace_specified = 1;
}
break;
default:
goto done;
}
}
if (i < 0 && yres_specified) {
xres = simple_strtol(name, NULL, 10);
res_specified = 1;
}
done:
kfree(mode_option_buf);
if (cvt) {
struct fb_videomode cvt_mode;
int ret;
DPRINTK("CVT mode %dx%d@%dHz%s%s%s\n", xres, yres,
(refresh) ? refresh : 60,
(rb) ? " reduced blanking" : "",
(margins) ? " with margins" : "",
(interlace) ? " interlaced" : "");
memset(&cvt_mode, 0, sizeof(cvt_mode));
cvt_mode.xres = xres;
cvt_mode.yres = yres;
cvt_mode.refresh = (refresh) ? refresh : 60;
if (interlace)
cvt_mode.vmode |= FB_VMODE_INTERLACED;
else
cvt_mode.vmode &= ~FB_VMODE_INTERLACED;
ret = fb_find_mode_cvt(&cvt_mode, margins, rb);
if (!ret && !fb_try_mode(var, info, &cvt_mode, bpp)) {
DPRINTK("modedb CVT: CVT mode ok\n");
return 1;
}
DPRINTK("CVT mode invalid, getting mode from database\n");
}
DPRINTK("Trying specified video mode%s %ix%i\n",
refresh_specified ? "" : " (ignoring refresh rate)",
xres, yres);
if (!refresh_specified) {
/*
* If the caller has provided a custom mode database and
* a valid monspecs structure, we look for the mode with
* the highest refresh rate. Otherwise we play it safe
* it and try to find a mode with a refresh rate closest
* to the standard 60 Hz.
*/
if (db != modedb &&
info->monspecs.vfmin && info->monspecs.vfmax &&
info->monspecs.hfmin && info->monspecs.hfmax &&
info->monspecs.dclkmax) {
refresh = 1000;
} else {
refresh = 60;
}
}
diff = -1;
best = -1;
for (i = 0; i < dbsize; i++) {
if ((name_matches(db[i], name, namelen) ||
(res_specified && res_matches(db[i], xres, yres))) &&
!fb_try_mode(var, info, &db[i], bpp)) {
const int db_interlace = (db[i].vmode &
FB_VMODE_INTERLACED ? 1 : 0);
int score = abs(db[i].refresh - refresh);
if (interlace_specified)
score += abs(db_interlace - interlace);
if (!interlace_specified ||
db_interlace == interlace)
if (refresh_specified &&
db[i].refresh == refresh)
return 1;
if (score < diff) {
diff = score;
best = i;
}
}
}
if (best != -1) {
fb_try_mode(var, info, &db[best], bpp);
return (refresh_specified) ? 2 : 1;
}
diff = 2 * (xres + yres);
best = -1;
DPRINTK("Trying best-fit modes\n");
for (i = 0; i < dbsize; i++) {
DPRINTK("Trying %ix%i\n", db[i].xres, db[i].yres);
if (!fb_try_mode(var, info, &db[i], bpp)) {
tdiff = abs(db[i].xres - xres) +
abs(db[i].yres - yres);
/*
* Penalize modes with resolutions smaller
* than requested.
*/
if (xres > db[i].xres || yres > db[i].yres)
tdiff += xres + yres;
if (diff > tdiff) {
diff = tdiff;
best = i;
}
}
}
if (best != -1) {
fb_try_mode(var, info, &db[best], bpp);
return 5;
}
}
DPRINTK("Trying default video mode\n");
if (!fb_try_mode(var, info, default_mode, default_bpp))
return 3;
DPRINTK("Trying all modes\n");
for (i = 0; i < dbsize; i++)
if (!fb_try_mode(var, info, &db[i], default_bpp))
return 4;
DPRINTK("No valid mode found\n");
return 0;
}
/**
* fb_var_to_videomode - convert fb_var_screeninfo to fb_videomode
* @mode: pointer to struct fb_videomode
* @var: pointer to struct fb_var_screeninfo
*/
void fb_var_to_videomode(struct fb_videomode *mode,
const struct fb_var_screeninfo *var)
{
u32 pixclock, hfreq, htotal, vtotal;
mode->name = NULL;
mode->xres = var->xres;
mode->yres = var->yres;
mode->pixclock = var->pixclock;
mode->hsync_len = var->hsync_len;
mode->vsync_len = var->vsync_len;
mode->left_margin = var->left_margin;
mode->right_margin = var->right_margin;
mode->upper_margin = var->upper_margin;
mode->lower_margin = var->lower_margin;
mode->sync = var->sync;
mode->vmode = var->vmode & FB_VMODE_MASK;
mode->flag = FB_MODE_IS_FROM_VAR;
mode->refresh = 0;
if (!var->pixclock)
return;
pixclock = PICOS2KHZ(var->pixclock) * 1000;
htotal = var->xres + var->right_margin + var->hsync_len +
var->left_margin;
vtotal = var->yres + var->lower_margin + var->vsync_len +
var->upper_margin;
if (var->vmode & FB_VMODE_INTERLACED)
vtotal /= 2;
if (var->vmode & FB_VMODE_DOUBLE)
vtotal *= 2;
if (!htotal || !vtotal)
return;
hfreq = pixclock/htotal;
mode->refresh = hfreq/vtotal;
}
/**
* fb_videomode_to_var - convert fb_videomode to fb_var_screeninfo
* @var: pointer to struct fb_var_screeninfo
* @mode: pointer to struct fb_videomode
*/
void fb_videomode_to_var(struct fb_var_screeninfo *var,
const struct fb_videomode *mode)
{
var->xres = mode->xres;
var->yres = mode->yres;
var->xres_virtual = mode->xres;
var->yres_virtual = mode->yres;
var->xoffset = 0;
var->yoffset = 0;
var->pixclock = mode->pixclock;
var->left_margin = mode->left_margin;
var->right_margin = mode->right_margin;
var->upper_margin = mode->upper_margin;
var->lower_margin = mode->lower_margin;
var->hsync_len = mode->hsync_len;
var->vsync_len = mode->vsync_len;
var->sync = mode->sync;
var->vmode = mode->vmode & FB_VMODE_MASK;
}
/**
* fb_mode_is_equal - compare 2 videomodes
* @mode1: first videomode
* @mode2: second videomode
*
* RETURNS:
* 1 if equal, 0 if not
*/
int fb_mode_is_equal(const struct fb_videomode *mode1,
const struct fb_videomode *mode2)
{
return (mode1->xres == mode2->xres &&
mode1->yres == mode2->yres &&
mode1->pixclock == mode2->pixclock &&
mode1->hsync_len == mode2->hsync_len &&
mode1->vsync_len == mode2->vsync_len &&
mode1->left_margin == mode2->left_margin &&
mode1->right_margin == mode2->right_margin &&
mode1->upper_margin == mode2->upper_margin &&
mode1->lower_margin == mode2->lower_margin &&
mode1->sync == mode2->sync &&
mode1->vmode == mode2->vmode);
}
/**
* fb_find_best_mode - find best matching videomode
* @var: pointer to struct fb_var_screeninfo
* @head: pointer to struct list_head of modelist
*
* RETURNS:
* struct fb_videomode, NULL if none found
*
* IMPORTANT:
* This function assumes that all modelist entries in
* info->modelist are valid.
*
* NOTES:
* Finds best matching videomode which has an equal or greater dimension than
* var->xres and var->yres. If more than 1 videomode is found, will return
* the videomode with the highest refresh rate
*/
const struct fb_videomode *fb_find_best_mode(const struct fb_var_screeninfo *var,
struct list_head *head)
{
struct fb_modelist *modelist;
struct fb_videomode *mode, *best = NULL;
u32 diff = -1;
list_for_each_entry(modelist, head, list) {
u32 d;
mode = &modelist->mode;
if (mode->xres >= var->xres && mode->yres >= var->yres) {
d = (mode->xres - var->xres) +
(mode->yres - var->yres);
if (diff > d) {
diff = d;
best = mode;
} else if (diff == d && best &&
mode->refresh > best->refresh)
best = mode;
}
}
return best;
}
/**
* fb_find_nearest_mode - find closest videomode
*
* @mode: pointer to struct fb_videomode
* @head: pointer to modelist
*
* Finds best matching videomode, smaller or greater in dimension.
* If more than 1 videomode is found, will return the videomode with
* the closest refresh rate.
*/
const struct fb_videomode *fb_find_nearest_mode(const struct fb_videomode *mode,
struct list_head *head)
{
struct fb_modelist *modelist;
struct fb_videomode *cmode, *best = NULL;
u32 diff = -1, diff_refresh = -1;
list_for_each_entry(modelist, head, list) {
u32 d;
cmode = &modelist->mode;
d = abs(cmode->xres - mode->xres) +
abs(cmode->yres - mode->yres);
if (diff > d) {
diff = d;
diff_refresh = abs(cmode->refresh - mode->refresh);
best = cmode;
} else if (diff == d) {
d = abs(cmode->refresh - mode->refresh);
if (diff_refresh > d) {
diff_refresh = d;
best = cmode;
}
}
}
return best;
}
/**
* fb_match_mode - find a videomode which exactly matches the timings in var
* @var: pointer to struct fb_var_screeninfo
* @head: pointer to struct list_head of modelist
*
* RETURNS:
* struct fb_videomode, NULL if none found
*/
const struct fb_videomode *fb_match_mode(const struct fb_var_screeninfo *var,
struct list_head *head)
{
struct fb_modelist *modelist;
struct fb_videomode *m, mode;
fb_var_to_videomode(&mode, var);
list_for_each_entry(modelist, head, list) {
m = &modelist->mode;
if (fb_mode_is_equal(m, &mode))
return m;
}
return NULL;
}
/**
* fb_add_videomode - adds videomode entry to modelist
* @mode: videomode to add
* @head: struct list_head of modelist
*
* NOTES:
* Will only add unmatched mode entries
*/
int fb_add_videomode(const struct fb_videomode *mode, struct list_head *head)
{
struct fb_modelist *modelist;
struct fb_videomode *m;
int found = 0;
list_for_each_entry(modelist, head, list) {
m = &modelist->mode;
if (fb_mode_is_equal(m, mode)) {
found = 1;
break;
}
}
if (!found) {
modelist = kmalloc(sizeof(struct fb_modelist),
GFP_KERNEL);
if (!modelist)
return -ENOMEM;
modelist->mode = *mode;
list_add(&modelist->list, head);
}
return 0;
}
/**
* fb_delete_videomode - removed videomode entry from modelist
* @mode: videomode to remove
* @head: struct list_head of modelist
*
* NOTES:
* Will remove all matching mode entries
*/
void fb_delete_videomode(const struct fb_videomode *mode,
struct list_head *head)
{
struct list_head *pos, *n;
struct fb_modelist *modelist;
struct fb_videomode *m;
list_for_each_safe(pos, n, head) {
modelist = list_entry(pos, struct fb_modelist, list);
m = &modelist->mode;
if (fb_mode_is_equal(m, mode)) {
list_del(pos);
kfree(pos);
}
}
}
/**
* fb_destroy_modelist - destroy modelist
* @head: struct list_head of modelist
*/
void fb_destroy_modelist(struct list_head *head)
{
struct list_head *pos, *n;
list_for_each_safe(pos, n, head) {
list_del(pos);
kfree(pos);
}
}
EXPORT_SYMBOL_GPL(fb_destroy_modelist);
/**
* fb_videomode_to_modelist - convert mode array to mode list
* @modedb: array of struct fb_videomode
* @num: number of entries in array
* @head: struct list_head of modelist
*/
void fb_videomode_to_modelist(const struct fb_videomode *modedb, int num,
struct list_head *head)
{
int i;
INIT_LIST_HEAD(head);
for (i = 0; i < num; i++) {
if (fb_add_videomode(&modedb[i], head))
return;
}
}
const struct fb_videomode *fb_find_best_display(const struct fb_monspecs *specs,
struct list_head *head)
{
struct fb_modelist *modelist;
const struct fb_videomode *m, *m1 = NULL, *md = NULL, *best = NULL;
int first = 0;
if (!head->prev || !head->next || list_empty(head))
goto finished;
/* get the first detailed mode and the very first mode */
list_for_each_entry(modelist, head, list) {
m = &modelist->mode;
if (!first) {
m1 = m;
first = 1;
}
if (m->flag & FB_MODE_IS_FIRST) {
md = m;
break;
}
}
/* first detailed timing is preferred */
if (specs->misc & FB_MISC_1ST_DETAIL) {
best = md;
goto finished;
}
/* find best mode based on display width and height */
if (specs->max_x && specs->max_y) {
struct fb_var_screeninfo var;
memset(&var, 0, sizeof(struct fb_var_screeninfo));
var.xres = (specs->max_x * 7200)/254;
var.yres = (specs->max_y * 7200)/254;
m = fb_find_best_mode(&var, head);
if (m) {
best = m;
goto finished;
}
}
/* use first detailed mode */
if (md) {
best = md;
goto finished;
}
/* last resort, use the very first mode */
best = m1;
finished:
return best;
}
EXPORT_SYMBOL(fb_find_best_display);
EXPORT_SYMBOL(fb_videomode_to_var);
EXPORT_SYMBOL(fb_var_to_videomode);
EXPORT_SYMBOL(fb_mode_is_equal);
EXPORT_SYMBOL(fb_add_videomode);
EXPORT_SYMBOL(fb_match_mode);
EXPORT_SYMBOL(fb_find_best_mode);
EXPORT_SYMBOL(fb_find_nearest_mode);
EXPORT_SYMBOL(fb_videomode_to_modelist);
EXPORT_SYMBOL(fb_find_mode);
EXPORT_SYMBOL(fb_find_mode_cvt);
| linux-master | drivers/video/fbdev/core/modedb.c |
/*
* linux/drivers/video/console/fbcon_ud.c -- Software Rotation - 90 degrees
*
* Copyright (C) 2005 Antonino Daplas <adaplas @pol.net>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/vt_kern.h>
#include <linux/console.h>
#include <asm/types.h>
#include "fbcon.h"
#include "fbcon_rotate.h"
/*
* Rotation 90 degrees
*/
static void cw_update_attr(u8 *dst, u8 *src, int attribute,
struct vc_data *vc)
{
int i, j, offset = (vc->vc_font.height < 10) ? 1 : 2;
int width = (vc->vc_font.height + 7) >> 3;
u8 c, msk = ~(0xff >> offset);
for (i = 0; i < vc->vc_font.width; i++) {
for (j = 0; j < width; j++) {
c = *src;
if (attribute & FBCON_ATTRIBUTE_UNDERLINE && !j)
c |= msk;
if (attribute & FBCON_ATTRIBUTE_BOLD && i)
c |= *(src-width);
if (attribute & FBCON_ATTRIBUTE_REVERSE)
c = ~c;
src++;
*dst++ = c;
}
}
}
static void cw_bmove(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int dy, int dx, int height, int width)
{
struct fbcon_ops *ops = info->fbcon_par;
struct fb_copyarea area;
u32 vxres = GETVXRES(ops->p, info);
area.sx = vxres - ((sy + height) * vc->vc_font.height);
area.sy = sx * vc->vc_font.width;
area.dx = vxres - ((dy + height) * vc->vc_font.height);
area.dy = dx * vc->vc_font.width;
area.width = height * vc->vc_font.height;
area.height = width * vc->vc_font.width;
info->fbops->fb_copyarea(info, &area);
}
static void cw_clear(struct vc_data *vc, struct fb_info *info, int sy,
int sx, int height, int width)
{
struct fbcon_ops *ops = info->fbcon_par;
struct fb_fillrect region;
int bgshift = (vc->vc_hi_font_mask) ? 13 : 12;
u32 vxres = GETVXRES(ops->p, info);
region.color = attr_bgcol_ec(bgshift,vc,info);
region.dx = vxres - ((sy + height) * vc->vc_font.height);
region.dy = sx * vc->vc_font.width;
region.height = width * vc->vc_font.width;
region.width = height * vc->vc_font.height;
region.rop = ROP_COPY;
info->fbops->fb_fillrect(info, ®ion);
}
static inline void cw_putcs_aligned(struct vc_data *vc, struct fb_info *info,
const u16 *s, u32 attr, u32 cnt,
u32 d_pitch, u32 s_pitch, u32 cellsize,
struct fb_image *image, u8 *buf, u8 *dst)
{
struct fbcon_ops *ops = info->fbcon_par;
u16 charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
u32 idx = (vc->vc_font.height + 7) >> 3;
u8 *src;
while (cnt--) {
src = ops->fontbuffer + (scr_readw(s++) & charmask)*cellsize;
if (attr) {
cw_update_attr(buf, src, attr, vc);
src = buf;
}
if (likely(idx == 1))
__fb_pad_aligned_buffer(dst, d_pitch, src, idx,
vc->vc_font.width);
else
fb_pad_aligned_buffer(dst, d_pitch, src, idx,
vc->vc_font.width);
dst += d_pitch * vc->vc_font.width;
}
info->fbops->fb_imageblit(info, image);
}
static void cw_putcs(struct vc_data *vc, struct fb_info *info,
const unsigned short *s, int count, int yy, int xx,
int fg, int bg)
{
struct fb_image image;
struct fbcon_ops *ops = info->fbcon_par;
u32 width = (vc->vc_font.height + 7)/8;
u32 cellsize = width * vc->vc_font.width;
u32 maxcnt = info->pixmap.size/cellsize;
u32 scan_align = info->pixmap.scan_align - 1;
u32 buf_align = info->pixmap.buf_align - 1;
u32 cnt, pitch, size;
u32 attribute = get_attribute(info, scr_readw(s));
u8 *dst, *buf = NULL;
u32 vxres = GETVXRES(ops->p, info);
if (!ops->fontbuffer)
return;
image.fg_color = fg;
image.bg_color = bg;
image.dx = vxres - ((yy + 1) * vc->vc_font.height);
image.dy = xx * vc->vc_font.width;
image.width = vc->vc_font.height;
image.depth = 1;
if (attribute) {
buf = kmalloc(cellsize, GFP_KERNEL);
if (!buf)
return;
}
while (count) {
if (count > maxcnt)
cnt = maxcnt;
else
cnt = count;
image.height = vc->vc_font.width * cnt;
pitch = ((image.width + 7) >> 3) + scan_align;
pitch &= ~scan_align;
size = pitch * image.height + buf_align;
size &= ~buf_align;
dst = fb_get_buffer_offset(info, &info->pixmap, size);
image.data = dst;
cw_putcs_aligned(vc, info, s, attribute, cnt, pitch,
width, cellsize, &image, buf, dst);
image.dy += image.height;
count -= cnt;
s += cnt;
}
/* buf is always NULL except when in monochrome mode, so in this case
it's a gain to check buf against NULL even though kfree() handles
NULL pointers just fine */
if (unlikely(buf))
kfree(buf);
}
static void cw_clear_margins(struct vc_data *vc, struct fb_info *info,
int color, int bottom_only)
{
unsigned int cw = vc->vc_font.width;
unsigned int ch = vc->vc_font.height;
unsigned int rw = info->var.yres - (vc->vc_cols*cw);
unsigned int bh = info->var.xres - (vc->vc_rows*ch);
unsigned int rs = info->var.yres - rw;
struct fb_fillrect region;
region.color = color;
region.rop = ROP_COPY;
if ((int) rw > 0 && !bottom_only) {
region.dx = 0;
region.dy = info->var.yoffset + rs;
region.height = rw;
region.width = info->var.xres_virtual;
info->fbops->fb_fillrect(info, ®ion);
}
if ((int) bh > 0) {
region.dx = info->var.xoffset;
region.dy = info->var.yoffset;
region.height = info->var.yres;
region.width = bh;
info->fbops->fb_fillrect(info, ®ion);
}
}
static void cw_cursor(struct vc_data *vc, struct fb_info *info, int mode,
int fg, int bg)
{
struct fb_cursor cursor;
struct fbcon_ops *ops = info->fbcon_par;
unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
int w = (vc->vc_font.height + 7) >> 3, c;
int y = real_y(ops->p, vc->state.y);
int attribute, use_sw = vc->vc_cursor_type & CUR_SW;
int err = 1, dx, dy;
char *src;
u32 vxres = GETVXRES(ops->p, info);
if (!ops->fontbuffer)
return;
cursor.set = 0;
c = scr_readw((u16 *) vc->vc_pos);
attribute = get_attribute(info, c);
src = ops->fontbuffer + ((c & charmask) * (w * vc->vc_font.width));
if (ops->cursor_state.image.data != src ||
ops->cursor_reset) {
ops->cursor_state.image.data = src;
cursor.set |= FB_CUR_SETIMAGE;
}
if (attribute) {
u8 *dst;
dst = kmalloc_array(w, vc->vc_font.width, GFP_ATOMIC);
if (!dst)
return;
kfree(ops->cursor_data);
ops->cursor_data = dst;
cw_update_attr(dst, src, attribute, vc);
src = dst;
}
if (ops->cursor_state.image.fg_color != fg ||
ops->cursor_state.image.bg_color != bg ||
ops->cursor_reset) {
ops->cursor_state.image.fg_color = fg;
ops->cursor_state.image.bg_color = bg;
cursor.set |= FB_CUR_SETCMAP;
}
if (ops->cursor_state.image.height != vc->vc_font.width ||
ops->cursor_state.image.width != vc->vc_font.height ||
ops->cursor_reset) {
ops->cursor_state.image.height = vc->vc_font.width;
ops->cursor_state.image.width = vc->vc_font.height;
cursor.set |= FB_CUR_SETSIZE;
}
dx = vxres - ((y * vc->vc_font.height) + vc->vc_font.height);
dy = vc->state.x * vc->vc_font.width;
if (ops->cursor_state.image.dx != dx ||
ops->cursor_state.image.dy != dy ||
ops->cursor_reset) {
ops->cursor_state.image.dx = dx;
ops->cursor_state.image.dy = dy;
cursor.set |= FB_CUR_SETPOS;
}
if (ops->cursor_state.hot.x || ops->cursor_state.hot.y ||
ops->cursor_reset) {
ops->cursor_state.hot.x = cursor.hot.y = 0;
cursor.set |= FB_CUR_SETHOT;
}
if (cursor.set & FB_CUR_SETSIZE ||
vc->vc_cursor_type != ops->p->cursor_shape ||
ops->cursor_state.mask == NULL ||
ops->cursor_reset) {
char *tmp, *mask = kmalloc_array(w, vc->vc_font.width,
GFP_ATOMIC);
int cur_height, size, i = 0;
int width = (vc->vc_font.width + 7)/8;
if (!mask)
return;
tmp = kmalloc_array(width, vc->vc_font.height, GFP_ATOMIC);
if (!tmp) {
kfree(mask);
return;
}
kfree(ops->cursor_state.mask);
ops->cursor_state.mask = mask;
ops->p->cursor_shape = vc->vc_cursor_type;
cursor.set |= FB_CUR_SETSHAPE;
switch (CUR_SIZE(ops->p->cursor_shape)) {
case CUR_NONE:
cur_height = 0;
break;
case CUR_UNDERLINE:
cur_height = (vc->vc_font.height < 10) ? 1 : 2;
break;
case CUR_LOWER_THIRD:
cur_height = vc->vc_font.height/3;
break;
case CUR_LOWER_HALF:
cur_height = vc->vc_font.height >> 1;
break;
case CUR_TWO_THIRDS:
cur_height = (vc->vc_font.height << 1)/3;
break;
case CUR_BLOCK:
default:
cur_height = vc->vc_font.height;
break;
}
size = (vc->vc_font.height - cur_height) * width;
while (size--)
tmp[i++] = 0;
size = cur_height * width;
while (size--)
tmp[i++] = 0xff;
memset(mask, 0, w * vc->vc_font.width);
rotate_cw(tmp, mask, vc->vc_font.width, vc->vc_font.height);
kfree(tmp);
}
switch (mode) {
case CM_ERASE:
ops->cursor_state.enable = 0;
break;
case CM_DRAW:
case CM_MOVE:
default:
ops->cursor_state.enable = (use_sw) ? 0 : 1;
break;
}
cursor.image.data = src;
cursor.image.fg_color = ops->cursor_state.image.fg_color;
cursor.image.bg_color = ops->cursor_state.image.bg_color;
cursor.image.dx = ops->cursor_state.image.dx;
cursor.image.dy = ops->cursor_state.image.dy;
cursor.image.height = ops->cursor_state.image.height;
cursor.image.width = ops->cursor_state.image.width;
cursor.hot.x = ops->cursor_state.hot.x;
cursor.hot.y = ops->cursor_state.hot.y;
cursor.mask = ops->cursor_state.mask;
cursor.enable = ops->cursor_state.enable;
cursor.image.depth = 1;
cursor.rop = ROP_XOR;
if (info->fbops->fb_cursor)
err = info->fbops->fb_cursor(info, &cursor);
if (err)
soft_cursor(info, &cursor);
ops->cursor_reset = 0;
}
static int cw_update_start(struct fb_info *info)
{
struct fbcon_ops *ops = info->fbcon_par;
u32 vxres = GETVXRES(ops->p, info);
u32 xoffset;
int err;
xoffset = vxres - (info->var.xres + ops->var.yoffset);
ops->var.yoffset = ops->var.xoffset;
ops->var.xoffset = xoffset;
err = fb_pan_display(info, &ops->var);
ops->var.xoffset = info->var.xoffset;
ops->var.yoffset = info->var.yoffset;
ops->var.vmode = info->var.vmode;
return err;
}
void fbcon_rotate_cw(struct fbcon_ops *ops)
{
ops->bmove = cw_bmove;
ops->clear = cw_clear;
ops->putcs = cw_putcs;
ops->clear_margins = cw_clear_margins;
ops->cursor = cw_cursor;
ops->update_start = cw_update_start;
}
| linux-master | drivers/video/fbdev/core/fbcon_cw.c |
/*
* Generic fillrect for frame buffers with packed pixels of any depth.
*
* Copyright (C) 2000 James Simmons ([email protected])
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* NOTES:
*
* Also need to add code to deal with cards endians that are different than
* the native cpu endians. I also need to deal with MSB position in the word.
*
*/
#include <linux/module.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/types.h>
#include "fb_draw.h"
#if BITS_PER_LONG == 32
# define FB_WRITEL fb_writel
# define FB_READL fb_readl
#else
# define FB_WRITEL fb_writeq
# define FB_READL fb_readq
#endif
/*
* Aligned pattern fill using 32/64-bit memory accesses
*/
static void
bitfill_aligned(struct fb_info *p, unsigned long __iomem *dst, int dst_idx,
unsigned long pat, unsigned n, int bits, u32 bswapmask)
{
unsigned long first, last;
if (!n)
return;
first = fb_shifted_pixels_mask_long(p, dst_idx, bswapmask);
last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask);
if (dst_idx+n <= bits) {
// Single word
if (last)
first &= last;
FB_WRITEL(comp(pat, FB_READL(dst), first), dst);
} else {
// Multiple destination words
// Leading bits
if (first!= ~0UL) {
FB_WRITEL(comp(pat, FB_READL(dst), first), dst);
dst++;
n -= bits - dst_idx;
}
// Main chunk
n /= bits;
while (n >= 8) {
FB_WRITEL(pat, dst++);
FB_WRITEL(pat, dst++);
FB_WRITEL(pat, dst++);
FB_WRITEL(pat, dst++);
FB_WRITEL(pat, dst++);
FB_WRITEL(pat, dst++);
FB_WRITEL(pat, dst++);
FB_WRITEL(pat, dst++);
n -= 8;
}
while (n--)
FB_WRITEL(pat, dst++);
// Trailing bits
if (last)
FB_WRITEL(comp(pat, FB_READL(dst), last), dst);
}
}
/*
* Unaligned generic pattern fill using 32/64-bit memory accesses
* The pattern must have been expanded to a full 32/64-bit value
* Left/right are the appropriate shifts to convert to the pattern to be
* used for the next 32/64-bit word
*/
static void
bitfill_unaligned(struct fb_info *p, unsigned long __iomem *dst, int dst_idx,
unsigned long pat, int left, int right, unsigned n, int bits)
{
unsigned long first, last;
if (!n)
return;
first = FB_SHIFT_HIGH(p, ~0UL, dst_idx);
last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
// Single word
if (last)
first &= last;
FB_WRITEL(comp(pat, FB_READL(dst), first), dst);
} else {
// Multiple destination words
// Leading bits
if (first) {
FB_WRITEL(comp(pat, FB_READL(dst), first), dst);
dst++;
pat = pat << left | pat >> right;
n -= bits - dst_idx;
}
// Main chunk
n /= bits;
while (n >= 4) {
FB_WRITEL(pat, dst++);
pat = pat << left | pat >> right;
FB_WRITEL(pat, dst++);
pat = pat << left | pat >> right;
FB_WRITEL(pat, dst++);
pat = pat << left | pat >> right;
FB_WRITEL(pat, dst++);
pat = pat << left | pat >> right;
n -= 4;
}
while (n--) {
FB_WRITEL(pat, dst++);
pat = pat << left | pat >> right;
}
// Trailing bits
if (last)
FB_WRITEL(comp(pat, FB_READL(dst), last), dst);
}
}
/*
* Aligned pattern invert using 32/64-bit memory accesses
*/
static void
bitfill_aligned_rev(struct fb_info *p, unsigned long __iomem *dst,
int dst_idx, unsigned long pat, unsigned n, int bits,
u32 bswapmask)
{
unsigned long val = pat, dat;
unsigned long first, last;
if (!n)
return;
first = fb_shifted_pixels_mask_long(p, dst_idx, bswapmask);
last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask);
if (dst_idx+n <= bits) {
// Single word
if (last)
first &= last;
dat = FB_READL(dst);
FB_WRITEL(comp(dat ^ val, dat, first), dst);
} else {
// Multiple destination words
// Leading bits
if (first!=0UL) {
dat = FB_READL(dst);
FB_WRITEL(comp(dat ^ val, dat, first), dst);
dst++;
n -= bits - dst_idx;
}
// Main chunk
n /= bits;
while (n >= 8) {
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
n -= 8;
}
while (n--) {
FB_WRITEL(FB_READL(dst) ^ val, dst);
dst++;
}
// Trailing bits
if (last) {
dat = FB_READL(dst);
FB_WRITEL(comp(dat ^ val, dat, last), dst);
}
}
}
/*
* Unaligned generic pattern invert using 32/64-bit memory accesses
* The pattern must have been expanded to a full 32/64-bit value
* Left/right are the appropriate shifts to convert to the pattern to be
* used for the next 32/64-bit word
*/
static void
bitfill_unaligned_rev(struct fb_info *p, unsigned long __iomem *dst,
int dst_idx, unsigned long pat, int left, int right,
unsigned n, int bits)
{
unsigned long first, last, dat;
if (!n)
return;
first = FB_SHIFT_HIGH(p, ~0UL, dst_idx);
last = ~(FB_SHIFT_HIGH(p, ~0UL, (dst_idx+n) % bits));
if (dst_idx+n <= bits) {
// Single word
if (last)
first &= last;
dat = FB_READL(dst);
FB_WRITEL(comp(dat ^ pat, dat, first), dst);
} else {
// Multiple destination words
// Leading bits
if (first != 0UL) {
dat = FB_READL(dst);
FB_WRITEL(comp(dat ^ pat, dat, first), dst);
dst++;
pat = pat << left | pat >> right;
n -= bits - dst_idx;
}
// Main chunk
n /= bits;
while (n >= 4) {
FB_WRITEL(FB_READL(dst) ^ pat, dst);
dst++;
pat = pat << left | pat >> right;
FB_WRITEL(FB_READL(dst) ^ pat, dst);
dst++;
pat = pat << left | pat >> right;
FB_WRITEL(FB_READL(dst) ^ pat, dst);
dst++;
pat = pat << left | pat >> right;
FB_WRITEL(FB_READL(dst) ^ pat, dst);
dst++;
pat = pat << left | pat >> right;
n -= 4;
}
while (n--) {
FB_WRITEL(FB_READL(dst) ^ pat, dst);
dst++;
pat = pat << left | pat >> right;
}
// Trailing bits
if (last) {
dat = FB_READL(dst);
FB_WRITEL(comp(dat ^ pat, dat, last), dst);
}
}
}
void cfb_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
{
unsigned long pat, pat2, fg;
unsigned long width = rect->width, height = rect->height;
int bits = BITS_PER_LONG, bytes = bits >> 3;
u32 bpp = p->var.bits_per_pixel;
unsigned long __iomem *dst;
int dst_idx, left;
if (p->state != FBINFO_STATE_RUNNING)
return;
if (p->fix.visual == FB_VISUAL_TRUECOLOR ||
p->fix.visual == FB_VISUAL_DIRECTCOLOR )
fg = ((u32 *) (p->pseudo_palette))[rect->color];
else
fg = rect->color;
pat = pixel_to_pat(bpp, fg);
dst = (unsigned long __iomem *)((unsigned long)p->screen_base & ~(bytes-1));
dst_idx = ((unsigned long)p->screen_base & (bytes - 1))*8;
dst_idx += rect->dy*p->fix.line_length*8+rect->dx*bpp;
/* FIXME For now we support 1-32 bpp only */
left = bits % bpp;
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
if (!left) {
u32 bswapmask = fb_compute_bswapmask(p);
void (*fill_op32)(struct fb_info *p,
unsigned long __iomem *dst, int dst_idx,
unsigned long pat, unsigned n, int bits,
u32 bswapmask) = NULL;
switch (rect->rop) {
case ROP_XOR:
fill_op32 = bitfill_aligned_rev;
break;
case ROP_COPY:
fill_op32 = bitfill_aligned;
break;
default:
printk( KERN_ERR "cfb_fillrect(): unknown rop, defaulting to ROP_COPY\n");
fill_op32 = bitfill_aligned;
break;
}
while (height--) {
dst += dst_idx >> (ffs(bits) - 1);
dst_idx &= (bits - 1);
fill_op32(p, dst, dst_idx, pat, width*bpp, bits,
bswapmask);
dst_idx += p->fix.line_length*8;
}
} else {
int right, r;
void (*fill_op)(struct fb_info *p, unsigned long __iomem *dst,
int dst_idx, unsigned long pat, int left,
int right, unsigned n, int bits) = NULL;
#ifdef __LITTLE_ENDIAN
right = left;
left = bpp - right;
#else
right = bpp - left;
#endif
switch (rect->rop) {
case ROP_XOR:
fill_op = bitfill_unaligned_rev;
break;
case ROP_COPY:
fill_op = bitfill_unaligned;
break;
default:
printk(KERN_ERR "cfb_fillrect(): unknown rop, defaulting to ROP_COPY\n");
fill_op = bitfill_unaligned;
break;
}
while (height--) {
dst += dst_idx / bits;
dst_idx &= (bits - 1);
r = dst_idx % bpp;
/* rotate pattern to the correct start position */
pat2 = le_long_to_cpu(rolx(cpu_to_le_long(pat), r, bpp));
fill_op(p, dst, dst_idx, pat2, left, right,
width*bpp, bits);
dst_idx += p->fix.line_length*8;
}
}
}
EXPORT_SYMBOL(cfb_fillrect);
MODULE_AUTHOR("James Simmons <[email protected]>");
MODULE_DESCRIPTION("Generic software accelerated fill rectangle");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/cfbfillrect.c |
/*
* linux/drivers/video/console/fbcon_rotate.c -- Software Rotation
*
* Copyright (C) 2005 Antonino Daplas <adaplas @pol.net>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <linux/vt_kern.h>
#include <linux/console.h>
#include <asm/types.h>
#include "fbcon.h"
#include "fbcon_rotate.h"
static int fbcon_rotate_font(struct fb_info *info, struct vc_data *vc)
{
struct fbcon_ops *ops = info->fbcon_par;
int len, err = 0;
int s_cellsize, d_cellsize, i;
const u8 *src;
u8 *dst;
if (vc->vc_font.data == ops->fontdata &&
ops->p->con_rotate == ops->cur_rotate)
goto finished;
src = ops->fontdata = vc->vc_font.data;
ops->cur_rotate = ops->p->con_rotate;
len = vc->vc_font.charcount;
s_cellsize = ((vc->vc_font.width + 7)/8) *
vc->vc_font.height;
d_cellsize = s_cellsize;
if (ops->rotate == FB_ROTATE_CW ||
ops->rotate == FB_ROTATE_CCW)
d_cellsize = ((vc->vc_font.height + 7)/8) *
vc->vc_font.width;
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
if (ops->fd_size < d_cellsize * len) {
dst = kmalloc_array(len, d_cellsize, GFP_KERNEL);
if (dst == NULL) {
err = -ENOMEM;
goto finished;
}
ops->fd_size = d_cellsize * len;
kfree(ops->fontbuffer);
ops->fontbuffer = dst;
}
dst = ops->fontbuffer;
memset(dst, 0, ops->fd_size);
switch (ops->rotate) {
case FB_ROTATE_UD:
for (i = len; i--; ) {
rotate_ud(src, dst, vc->vc_font.width,
vc->vc_font.height);
src += s_cellsize;
dst += d_cellsize;
}
break;
case FB_ROTATE_CW:
for (i = len; i--; ) {
rotate_cw(src, dst, vc->vc_font.width,
vc->vc_font.height);
src += s_cellsize;
dst += d_cellsize;
}
break;
case FB_ROTATE_CCW:
for (i = len; i--; ) {
rotate_ccw(src, dst, vc->vc_font.width,
vc->vc_font.height);
src += s_cellsize;
dst += d_cellsize;
}
break;
}
finished:
return err;
}
void fbcon_set_rotate(struct fbcon_ops *ops)
{
ops->rotate_font = fbcon_rotate_font;
switch(ops->rotate) {
case FB_ROTATE_CW:
fbcon_rotate_cw(ops);
break;
case FB_ROTATE_UD:
fbcon_rotate_ud(ops);
break;
case FB_ROTATE_CCW:
fbcon_rotate_ccw(ops);
break;
}
}
| linux-master | drivers/video/fbdev/core/fbcon_rotate.c |
/*
* Generic function for frame buffer with packed pixels of any depth.
*
* Copyright (C) 1999-2005 James Simmons <[email protected]>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* NOTES:
*
* This is for cfb packed pixels. Iplan and such are incorporated in the
* drivers that need them.
*
* FIXME
*
* Also need to add code to deal with cards endians that are different than
* the native cpu endians. I also need to deal with MSB position in the word.
*
* The two functions or copying forward and backward could be split up like
* the ones for filling, i.e. in aligned and unaligned versions. This would
* help moving some redundant computations and branches out of the loop, too.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/fb.h>
#include <asm/types.h>
#include <asm/io.h>
#include "fb_draw.h"
#if BITS_PER_LONG == 32
# define FB_WRITEL fb_writel
# define FB_READL fb_readl
#else
# define FB_WRITEL fb_writeq
# define FB_READL fb_readq
#endif
/*
* Generic bitwise copy algorithm
*/
static void
bitcpy(struct fb_info *p, unsigned long __iomem *dst, unsigned dst_idx,
const unsigned long __iomem *src, unsigned src_idx, int bits,
unsigned n, u32 bswapmask)
{
unsigned long first, last;
int const shift = dst_idx-src_idx;
#if 0
/*
* If you suspect bug in this function, compare it with this simple
* memmove implementation.
*/
memmove((char *)dst + ((dst_idx & (bits - 1))) / 8,
(char *)src + ((src_idx & (bits - 1))) / 8, n / 8);
return;
#endif
first = fb_shifted_pixels_mask_long(p, dst_idx, bswapmask);
last = ~fb_shifted_pixels_mask_long(p, (dst_idx+n) % bits, bswapmask);
if (!shift) {
// Same alignment for source and dest
if (dst_idx+n <= bits) {
// Single word
if (last)
first &= last;
FB_WRITEL( comp( FB_READL(src), FB_READL(dst), first), dst);
} else {
// Multiple destination words
// Leading bits
if (first != ~0UL) {
FB_WRITEL( comp( FB_READL(src), FB_READL(dst), first), dst);
dst++;
src++;
n -= bits - dst_idx;
}
// Main chunk
n /= bits;
while (n >= 8) {
FB_WRITEL(FB_READL(src++), dst++);
FB_WRITEL(FB_READL(src++), dst++);
FB_WRITEL(FB_READL(src++), dst++);
FB_WRITEL(FB_READL(src++), dst++);
FB_WRITEL(FB_READL(src++), dst++);
FB_WRITEL(FB_READL(src++), dst++);
FB_WRITEL(FB_READL(src++), dst++);
FB_WRITEL(FB_READL(src++), dst++);
n -= 8;
}
while (n--)
FB_WRITEL(FB_READL(src++), dst++);
// Trailing bits
if (last)
FB_WRITEL( comp( FB_READL(src), FB_READL(dst), last), dst);
}
} else {
/* Different alignment for source and dest */
unsigned long d0, d1;
int m;
int const left = shift & (bits - 1);
int const right = -shift & (bits - 1);
if (dst_idx+n <= bits) {
// Single destination word
if (last)
first &= last;
d0 = FB_READL(src);
d0 = fb_rev_pixels_in_long(d0, bswapmask);
if (shift > 0) {
// Single source word
d0 <<= left;
} else if (src_idx+n <= bits) {
// Single source word
d0 >>= right;
} else {
// 2 source words
d1 = FB_READL(src + 1);
d1 = fb_rev_pixels_in_long(d1, bswapmask);
d0 = d0 >> right | d1 << left;
}
d0 = fb_rev_pixels_in_long(d0, bswapmask);
FB_WRITEL(comp(d0, FB_READL(dst), first), dst);
} else {
// Multiple destination words
/** We must always remember the last value read, because in case
SRC and DST overlap bitwise (e.g. when moving just one pixel in
1bpp), we always collect one full long for DST and that might
overlap with the current long from SRC. We store this value in
'd0'. */
d0 = FB_READL(src++);
d0 = fb_rev_pixels_in_long(d0, bswapmask);
// Leading bits
if (shift > 0) {
// Single source word
d1 = d0;
d0 <<= left;
n -= bits - dst_idx;
} else {
// 2 source words
d1 = FB_READL(src++);
d1 = fb_rev_pixels_in_long(d1, bswapmask);
d0 = d0 >> right | d1 << left;
n -= bits - dst_idx;
}
d0 = fb_rev_pixels_in_long(d0, bswapmask);
FB_WRITEL(comp(d0, FB_READL(dst), first), dst);
d0 = d1;
dst++;
// Main chunk
m = n % bits;
n /= bits;
while ((n >= 4) && !bswapmask) {
d1 = FB_READL(src++);
FB_WRITEL(d0 >> right | d1 << left, dst++);
d0 = d1;
d1 = FB_READL(src++);
FB_WRITEL(d0 >> right | d1 << left, dst++);
d0 = d1;
d1 = FB_READL(src++);
FB_WRITEL(d0 >> right | d1 << left, dst++);
d0 = d1;
d1 = FB_READL(src++);
FB_WRITEL(d0 >> right | d1 << left, dst++);
d0 = d1;
n -= 4;
}
while (n--) {
d1 = FB_READL(src++);
d1 = fb_rev_pixels_in_long(d1, bswapmask);
d0 = d0 >> right | d1 << left;
d0 = fb_rev_pixels_in_long(d0, bswapmask);
FB_WRITEL(d0, dst++);
d0 = d1;
}
// Trailing bits
if (m) {
if (m <= bits - right) {
// Single source word
d0 >>= right;
} else {
// 2 source words
d1 = FB_READL(src);
d1 = fb_rev_pixels_in_long(d1,
bswapmask);
d0 = d0 >> right | d1 << left;
}
d0 = fb_rev_pixels_in_long(d0, bswapmask);
FB_WRITEL(comp(d0, FB_READL(dst), last), dst);
}
}
}
}
/*
* Generic bitwise copy algorithm, operating backward
*/
static void
bitcpy_rev(struct fb_info *p, unsigned long __iomem *dst, unsigned dst_idx,
const unsigned long __iomem *src, unsigned src_idx, int bits,
unsigned n, u32 bswapmask)
{
unsigned long first, last;
int shift;
#if 0
/*
* If you suspect bug in this function, compare it with this simple
* memmove implementation.
*/
memmove((char *)dst + ((dst_idx & (bits - 1))) / 8,
(char *)src + ((src_idx & (bits - 1))) / 8, n / 8);
return;
#endif
dst += (dst_idx + n - 1) / bits;
src += (src_idx + n - 1) / bits;
dst_idx = (dst_idx + n - 1) % bits;
src_idx = (src_idx + n - 1) % bits;
shift = dst_idx-src_idx;
first = ~fb_shifted_pixels_mask_long(p, (dst_idx + 1) % bits, bswapmask);
last = fb_shifted_pixels_mask_long(p, (bits + dst_idx + 1 - n) % bits, bswapmask);
if (!shift) {
// Same alignment for source and dest
if ((unsigned long)dst_idx+1 >= n) {
// Single word
if (first)
last &= first;
FB_WRITEL( comp( FB_READL(src), FB_READL(dst), last), dst);
} else {
// Multiple destination words
// Leading bits
if (first) {
FB_WRITEL( comp( FB_READL(src), FB_READL(dst), first), dst);
dst--;
src--;
n -= dst_idx+1;
}
// Main chunk
n /= bits;
while (n >= 8) {
FB_WRITEL(FB_READL(src--), dst--);
FB_WRITEL(FB_READL(src--), dst--);
FB_WRITEL(FB_READL(src--), dst--);
FB_WRITEL(FB_READL(src--), dst--);
FB_WRITEL(FB_READL(src--), dst--);
FB_WRITEL(FB_READL(src--), dst--);
FB_WRITEL(FB_READL(src--), dst--);
FB_WRITEL(FB_READL(src--), dst--);
n -= 8;
}
while (n--)
FB_WRITEL(FB_READL(src--), dst--);
// Trailing bits
if (last != -1UL)
FB_WRITEL( comp( FB_READL(src), FB_READL(dst), last), dst);
}
} else {
// Different alignment for source and dest
unsigned long d0, d1;
int m;
int const left = shift & (bits-1);
int const right = -shift & (bits-1);
if ((unsigned long)dst_idx+1 >= n) {
// Single destination word
if (first)
last &= first;
d0 = FB_READL(src);
if (shift < 0) {
// Single source word
d0 >>= right;
} else if (1+(unsigned long)src_idx >= n) {
// Single source word
d0 <<= left;
} else {
// 2 source words
d1 = FB_READL(src - 1);
d1 = fb_rev_pixels_in_long(d1, bswapmask);
d0 = d0 << left | d1 >> right;
}
d0 = fb_rev_pixels_in_long(d0, bswapmask);
FB_WRITEL(comp(d0, FB_READL(dst), last), dst);
} else {
// Multiple destination words
/** We must always remember the last value read, because in case
SRC and DST overlap bitwise (e.g. when moving just one pixel in
1bpp), we always collect one full long for DST and that might
overlap with the current long from SRC. We store this value in
'd0'. */
d0 = FB_READL(src--);
d0 = fb_rev_pixels_in_long(d0, bswapmask);
// Leading bits
if (shift < 0) {
// Single source word
d1 = d0;
d0 >>= right;
} else {
// 2 source words
d1 = FB_READL(src--);
d1 = fb_rev_pixels_in_long(d1, bswapmask);
d0 = d0 << left | d1 >> right;
}
d0 = fb_rev_pixels_in_long(d0, bswapmask);
if (!first)
FB_WRITEL(d0, dst);
else
FB_WRITEL(comp(d0, FB_READL(dst), first), dst);
d0 = d1;
dst--;
n -= dst_idx+1;
// Main chunk
m = n % bits;
n /= bits;
while ((n >= 4) && !bswapmask) {
d1 = FB_READL(src--);
FB_WRITEL(d0 << left | d1 >> right, dst--);
d0 = d1;
d1 = FB_READL(src--);
FB_WRITEL(d0 << left | d1 >> right, dst--);
d0 = d1;
d1 = FB_READL(src--);
FB_WRITEL(d0 << left | d1 >> right, dst--);
d0 = d1;
d1 = FB_READL(src--);
FB_WRITEL(d0 << left | d1 >> right, dst--);
d0 = d1;
n -= 4;
}
while (n--) {
d1 = FB_READL(src--);
d1 = fb_rev_pixels_in_long(d1, bswapmask);
d0 = d0 << left | d1 >> right;
d0 = fb_rev_pixels_in_long(d0, bswapmask);
FB_WRITEL(d0, dst--);
d0 = d1;
}
// Trailing bits
if (m) {
if (m <= bits - left) {
// Single source word
d0 <<= left;
} else {
// 2 source words
d1 = FB_READL(src);
d1 = fb_rev_pixels_in_long(d1,
bswapmask);
d0 = d0 << left | d1 >> right;
}
d0 = fb_rev_pixels_in_long(d0, bswapmask);
FB_WRITEL(comp(d0, FB_READL(dst), last), dst);
}
}
}
}
void cfb_copyarea(struct fb_info *p, const struct fb_copyarea *area)
{
u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
u32 height = area->height, width = area->width;
unsigned long const bits_per_line = p->fix.line_length*8u;
unsigned long __iomem *base = NULL;
int bits = BITS_PER_LONG, bytes = bits >> 3;
unsigned dst_idx = 0, src_idx = 0, rev_copy = 0;
u32 bswapmask = fb_compute_bswapmask(p);
if (p->state != FBINFO_STATE_RUNNING)
return;
/* if the beginning of the target area might overlap with the end of
the source area, be have to copy the area reverse. */
if ((dy == sy && dx > sx) || (dy > sy)) {
dy += height;
sy += height;
rev_copy = 1;
}
// split the base of the framebuffer into a long-aligned address and the
// index of the first bit
base = (unsigned long __iomem *)((unsigned long)p->screen_base & ~(bytes-1));
dst_idx = src_idx = 8*((unsigned long)p->screen_base & (bytes-1));
// add offset of source and target area
dst_idx += dy*bits_per_line + dx*p->var.bits_per_pixel;
src_idx += sy*bits_per_line + sx*p->var.bits_per_pixel;
if (p->fbops->fb_sync)
p->fbops->fb_sync(p);
if (rev_copy) {
while (height--) {
dst_idx -= bits_per_line;
src_idx -= bits_per_line;
bitcpy_rev(p, base + (dst_idx / bits), dst_idx % bits,
base + (src_idx / bits), src_idx % bits, bits,
width*p->var.bits_per_pixel, bswapmask);
}
} else {
while (height--) {
bitcpy(p, base + (dst_idx / bits), dst_idx % bits,
base + (src_idx / bits), src_idx % bits, bits,
width*p->var.bits_per_pixel, bswapmask);
dst_idx += bits_per_line;
src_idx += bits_per_line;
}
}
}
EXPORT_SYMBOL(cfb_copyarea);
MODULE_AUTHOR("James Simmons <[email protected]>");
MODULE_DESCRIPTION("Generic software accelerated copyarea");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/core/cfbcopyarea.c |
// SPDX-License-Identifier: GPL-2.0
#include <linux/fb.h>
#include <linux/module.h>
#include <linux/uaccess.h>
ssize_t fb_io_read(struct fb_info *info, char __user *buf, size_t count, loff_t *ppos)
{
unsigned long p = *ppos;
u8 *buffer, *dst;
u8 __iomem *src;
int c, cnt = 0, err = 0;
unsigned long total_size, trailing;
if (!info->screen_base)
return -ENODEV;
total_size = info->screen_size;
if (total_size == 0)
total_size = info->fix.smem_len;
if (p >= total_size)
return 0;
if (count >= total_size)
count = total_size;
if (count + p > total_size)
count = total_size - p;
buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count,
GFP_KERNEL);
if (!buffer)
return -ENOMEM;
src = (u8 __iomem *) (info->screen_base + p);
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
while (count) {
c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
dst = buffer;
fb_memcpy_fromio(dst, src, c);
dst += c;
src += c;
trailing = copy_to_user(buf, buffer, c);
if (trailing == c) {
err = -EFAULT;
break;
}
c -= trailing;
*ppos += c;
buf += c;
cnt += c;
count -= c;
}
kfree(buffer);
return cnt ? cnt : err;
}
EXPORT_SYMBOL(fb_io_read);
ssize_t fb_io_write(struct fb_info *info, const char __user *buf, size_t count, loff_t *ppos)
{
unsigned long p = *ppos;
u8 *buffer, *src;
u8 __iomem *dst;
int c, cnt = 0, err = 0;
unsigned long total_size, trailing;
if (!info->screen_base)
return -ENODEV;
total_size = info->screen_size;
if (total_size == 0)
total_size = info->fix.smem_len;
if (p > total_size)
return -EFBIG;
if (count > total_size) {
err = -EFBIG;
count = total_size;
}
if (count + p > total_size) {
if (!err)
err = -ENOSPC;
count = total_size - p;
}
buffer = kmalloc((count > PAGE_SIZE) ? PAGE_SIZE : count,
GFP_KERNEL);
if (!buffer)
return -ENOMEM;
dst = (u8 __iomem *) (info->screen_base + p);
if (info->fbops->fb_sync)
info->fbops->fb_sync(info);
while (count) {
c = (count > PAGE_SIZE) ? PAGE_SIZE : count;
src = buffer;
trailing = copy_from_user(src, buf, c);
if (trailing == c) {
err = -EFAULT;
break;
}
c -= trailing;
fb_memcpy_toio(dst, src, c);
dst += c;
src += c;
*ppos += c;
buf += c;
cnt += c;
count -= c;
}
kfree(buffer);
return (cnt) ? cnt : err;
}
EXPORT_SYMBOL(fb_io_write);
| linux-master | drivers/video/fbdev/core/fb_io_fops.c |
// SPDX-License-Identifier: GPL-2.0-or-later
#include <linux/export.h>
#include <linux/fb.h>
#include <linux/mutex.h>
#if IS_ENABLED(CONFIG_FB_BACKLIGHT)
/*
* This function generates a linear backlight curve
*
* 0: off
* 1-7: min
* 8-127: linear from min to max
*/
void fb_bl_default_curve(struct fb_info *fb_info, u8 off, u8 min, u8 max)
{
unsigned int i, flat, count, range = (max - min);
mutex_lock(&fb_info->bl_curve_mutex);
fb_info->bl_curve[0] = off;
for (flat = 1; flat < (FB_BACKLIGHT_LEVELS / 16); ++flat)
fb_info->bl_curve[flat] = min;
count = FB_BACKLIGHT_LEVELS * 15 / 16;
for (i = 0; i < count; ++i)
fb_info->bl_curve[flat + i] = min + (range * (i + 1) / count);
mutex_unlock(&fb_info->bl_curve_mutex);
}
EXPORT_SYMBOL_GPL(fb_bl_default_curve);
#endif
| linux-master | drivers/video/fbdev/core/fb_backlight.c |
/*
* linux/drivers/video/fbcvt.c - VESA(TM) Coordinated Video Timings
*
* Copyright (C) 2005 Antonino Daplas <[email protected]>
*
* Based from the VESA(TM) Coordinated Video Timing Generator by
* Graham Loveridge April 9, 2003 available at
* http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
*/
#include <linux/fb.h>
#include <linux/slab.h>
#define FB_CVT_CELLSIZE 8
#define FB_CVT_GTF_C 40
#define FB_CVT_GTF_J 20
#define FB_CVT_GTF_K 128
#define FB_CVT_GTF_M 600
#define FB_CVT_MIN_VSYNC_BP 550
#define FB_CVT_MIN_VPORCH 3
#define FB_CVT_MIN_BPORCH 6
#define FB_CVT_RB_MIN_VBLANK 460
#define FB_CVT_RB_HBLANK 160
#define FB_CVT_RB_V_FPORCH 3
#define FB_CVT_FLAG_REDUCED_BLANK 1
#define FB_CVT_FLAG_MARGINS 2
#define FB_CVT_FLAG_INTERLACED 4
struct fb_cvt_data {
u32 xres;
u32 yres;
u32 refresh;
u32 f_refresh;
u32 pixclock;
u32 hperiod;
u32 hblank;
u32 hfreq;
u32 htotal;
u32 vtotal;
u32 vsync;
u32 hsync;
u32 h_front_porch;
u32 h_back_porch;
u32 v_front_porch;
u32 v_back_porch;
u32 h_margin;
u32 v_margin;
u32 interlace;
u32 aspect_ratio;
u32 active_pixels;
u32 flags;
u32 status;
};
static const unsigned char fb_cvt_vbi_tab[] = {
4, /* 4:3 */
5, /* 16:9 */
6, /* 16:10 */
7, /* 5:4 */
7, /* 15:9 */
8, /* reserved */
9, /* reserved */
10 /* custom */
};
/* returns hperiod * 1000 */
static u32 fb_cvt_hperiod(struct fb_cvt_data *cvt)
{
u32 num = 1000000000/cvt->f_refresh;
u32 den;
if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK) {
num -= FB_CVT_RB_MIN_VBLANK * 1000;
den = 2 * (cvt->yres/cvt->interlace + 2 * cvt->v_margin);
} else {
num -= FB_CVT_MIN_VSYNC_BP * 1000;
den = 2 * (cvt->yres/cvt->interlace + cvt->v_margin * 2
+ FB_CVT_MIN_VPORCH + cvt->interlace/2);
}
return 2 * (num/den);
}
/* returns ideal duty cycle * 1000 */
static u32 fb_cvt_ideal_duty_cycle(struct fb_cvt_data *cvt)
{
u32 c_prime = (FB_CVT_GTF_C - FB_CVT_GTF_J) *
(FB_CVT_GTF_K) + 256 * FB_CVT_GTF_J;
u32 m_prime = (FB_CVT_GTF_K * FB_CVT_GTF_M);
u32 h_period_est = cvt->hperiod;
return (1000 * c_prime - ((m_prime * h_period_est)/1000))/256;
}
static u32 fb_cvt_hblank(struct fb_cvt_data *cvt)
{
u32 hblank = 0;
if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK)
hblank = FB_CVT_RB_HBLANK;
else {
u32 ideal_duty_cycle = fb_cvt_ideal_duty_cycle(cvt);
u32 active_pixels = cvt->active_pixels;
if (ideal_duty_cycle < 20000)
hblank = (active_pixels * 20000)/
(100000 - 20000);
else {
hblank = (active_pixels * ideal_duty_cycle)/
(100000 - ideal_duty_cycle);
}
}
hblank &= ~((2 * FB_CVT_CELLSIZE) - 1);
return hblank;
}
static u32 fb_cvt_hsync(struct fb_cvt_data *cvt)
{
u32 hsync;
if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK)
hsync = 32;
else
hsync = (FB_CVT_CELLSIZE * cvt->htotal)/100;
hsync &= ~(FB_CVT_CELLSIZE - 1);
return hsync;
}
static u32 fb_cvt_vbi_lines(struct fb_cvt_data *cvt)
{
u32 vbi_lines, min_vbi_lines, act_vbi_lines;
if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK) {
vbi_lines = (1000 * FB_CVT_RB_MIN_VBLANK)/cvt->hperiod + 1;
min_vbi_lines = FB_CVT_RB_V_FPORCH + cvt->vsync +
FB_CVT_MIN_BPORCH;
} else {
vbi_lines = (FB_CVT_MIN_VSYNC_BP * 1000)/cvt->hperiod + 1 +
FB_CVT_MIN_VPORCH;
min_vbi_lines = cvt->vsync + FB_CVT_MIN_BPORCH +
FB_CVT_MIN_VPORCH;
}
if (vbi_lines < min_vbi_lines)
act_vbi_lines = min_vbi_lines;
else
act_vbi_lines = vbi_lines;
return act_vbi_lines;
}
static u32 fb_cvt_vtotal(struct fb_cvt_data *cvt)
{
u32 vtotal = cvt->yres/cvt->interlace;
vtotal += 2 * cvt->v_margin + cvt->interlace/2 + fb_cvt_vbi_lines(cvt);
vtotal |= cvt->interlace/2;
return vtotal;
}
static u32 fb_cvt_pixclock(struct fb_cvt_data *cvt)
{
u32 pixclock;
if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK)
pixclock = (cvt->f_refresh * cvt->vtotal * cvt->htotal)/1000;
else
pixclock = (cvt->htotal * 1000000)/cvt->hperiod;
pixclock /= 250;
pixclock *= 250;
pixclock *= 1000;
return pixclock;
}
static u32 fb_cvt_aspect_ratio(struct fb_cvt_data *cvt)
{
u32 xres = cvt->xres;
u32 yres = cvt->yres;
u32 aspect = -1;
if (xres == (yres * 4)/3 && !((yres * 4) % 3))
aspect = 0;
else if (xres == (yres * 16)/9 && !((yres * 16) % 9))
aspect = 1;
else if (xres == (yres * 16)/10 && !((yres * 16) % 10))
aspect = 2;
else if (xres == (yres * 5)/4 && !((yres * 5) % 4))
aspect = 3;
else if (xres == (yres * 15)/9 && !((yres * 15) % 9))
aspect = 4;
else {
printk(KERN_INFO "fbcvt: Aspect ratio not CVT "
"standard\n");
aspect = 7;
cvt->status = 1;
}
return aspect;
}
static void fb_cvt_print_name(struct fb_cvt_data *cvt)
{
u32 pixcount, pixcount_mod;
int size = 256;
int off = 0;
u8 *buf;
buf = kzalloc(size, GFP_KERNEL);
if (!buf)
return;
pixcount = (cvt->xres * (cvt->yres/cvt->interlace))/1000000;
pixcount_mod = (cvt->xres * (cvt->yres/cvt->interlace)) % 1000000;
pixcount_mod /= 1000;
off += scnprintf(buf + off, size - off, "fbcvt: %dx%d@%d: CVT Name - ",
cvt->xres, cvt->yres, cvt->refresh);
if (cvt->status) {
off += scnprintf(buf + off, size - off,
"Not a CVT standard - %d.%03d Mega Pixel Image\n",
pixcount, pixcount_mod);
} else {
if (pixcount)
off += scnprintf(buf + off, size - off, "%d", pixcount);
off += scnprintf(buf + off, size - off, ".%03dM", pixcount_mod);
if (cvt->aspect_ratio == 0)
off += scnprintf(buf + off, size - off, "3");
else if (cvt->aspect_ratio == 3)
off += scnprintf(buf + off, size - off, "4");
else if (cvt->aspect_ratio == 1 || cvt->aspect_ratio == 4)
off += scnprintf(buf + off, size - off, "9");
else if (cvt->aspect_ratio == 2)
off += scnprintf(buf + off, size - off, "A");
if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK)
off += scnprintf(buf + off, size - off, "-R");
}
printk(KERN_INFO "%s\n", buf);
kfree(buf);
}
static void fb_cvt_convert_to_mode(struct fb_cvt_data *cvt,
struct fb_videomode *mode)
{
mode->refresh = cvt->f_refresh;
mode->pixclock = KHZ2PICOS(cvt->pixclock/1000);
mode->left_margin = cvt->h_back_porch;
mode->right_margin = cvt->h_front_porch;
mode->hsync_len = cvt->hsync;
mode->upper_margin = cvt->v_back_porch;
mode->lower_margin = cvt->v_front_porch;
mode->vsync_len = cvt->vsync;
mode->sync &= ~(FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK)
mode->sync |= FB_SYNC_HOR_HIGH_ACT;
else
mode->sync |= FB_SYNC_VERT_HIGH_ACT;
}
/*
* fb_find_mode_cvt - calculate mode using VESA(TM) CVT
* @mode: pointer to fb_videomode; xres, yres, refresh and vmode must be
* pre-filled with the desired values
* @margins: add margin to calculation (1.8% of xres and yres)
* @rb: compute with reduced blanking (for flatpanels)
*
* RETURNS:
* 0 for success
* @mode is filled with computed values. If interlaced, the refresh field
* will be filled with the field rate (2x the frame rate)
*
* DESCRIPTION:
* Computes video timings using VESA(TM) Coordinated Video Timings
*/
int fb_find_mode_cvt(struct fb_videomode *mode, int margins, int rb)
{
struct fb_cvt_data cvt;
memset(&cvt, 0, sizeof(cvt));
if (margins)
cvt.flags |= FB_CVT_FLAG_MARGINS;
if (rb)
cvt.flags |= FB_CVT_FLAG_REDUCED_BLANK;
if (mode->vmode & FB_VMODE_INTERLACED)
cvt.flags |= FB_CVT_FLAG_INTERLACED;
cvt.xres = mode->xres;
cvt.yres = mode->yres;
cvt.refresh = mode->refresh;
cvt.f_refresh = cvt.refresh;
cvt.interlace = 1;
if (!cvt.xres || !cvt.yres || !cvt.refresh) {
printk(KERN_INFO "fbcvt: Invalid input parameters\n");
return 1;
}
if (!(cvt.refresh == 50 || cvt.refresh == 60 || cvt.refresh == 70 ||
cvt.refresh == 85)) {
printk(KERN_INFO "fbcvt: Refresh rate not CVT "
"standard\n");
cvt.status = 1;
}
cvt.xres &= ~(FB_CVT_CELLSIZE - 1);
if (cvt.flags & FB_CVT_FLAG_INTERLACED) {
cvt.interlace = 2;
cvt.f_refresh *= 2;
}
if (cvt.flags & FB_CVT_FLAG_REDUCED_BLANK) {
if (cvt.refresh != 60) {
printk(KERN_INFO "fbcvt: 60Hz refresh rate "
"advised for reduced blanking\n");
cvt.status = 1;
}
}
if (cvt.flags & FB_CVT_FLAG_MARGINS) {
cvt.h_margin = (cvt.xres * 18)/1000;
cvt.h_margin &= ~(FB_CVT_CELLSIZE - 1);
cvt.v_margin = ((cvt.yres/cvt.interlace)* 18)/1000;
}
cvt.aspect_ratio = fb_cvt_aspect_ratio(&cvt);
cvt.active_pixels = cvt.xres + 2 * cvt.h_margin;
cvt.hperiod = fb_cvt_hperiod(&cvt);
cvt.vsync = fb_cvt_vbi_tab[cvt.aspect_ratio];
cvt.vtotal = fb_cvt_vtotal(&cvt);
cvt.hblank = fb_cvt_hblank(&cvt);
cvt.htotal = cvt.active_pixels + cvt.hblank;
cvt.hsync = fb_cvt_hsync(&cvt);
cvt.pixclock = fb_cvt_pixclock(&cvt);
cvt.hfreq = cvt.pixclock/cvt.htotal;
cvt.h_back_porch = cvt.hblank/2 + cvt.h_margin;
cvt.h_front_porch = cvt.hblank - cvt.hsync - cvt.h_back_porch +
2 * cvt.h_margin;
cvt.v_front_porch = 3 + cvt.v_margin;
cvt.v_back_porch = cvt.vtotal - cvt.yres/cvt.interlace -
cvt.v_front_porch - cvt.vsync;
fb_cvt_print_name(&cvt);
fb_cvt_convert_to_mode(&cvt, mode);
return 0;
}
| linux-master | drivers/video/fbdev/core/fbcvt.c |
/* $XFree86$ */
/* $XdotOrg$ */
/*
* Mode initializing code (CRT1 section) for
* for SiS 300/305/540/630/730,
* SiS 315/550/[M]650/651/[M]661[FGM]X/[M]74x[GX]/330/[M]76x[GX],
* XGI Volari V3XT/V5/V8, Z7
* (Universal module for Linux kernel framebuffer and X.org/XFree86 4.x)
*
* Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
*
* If distributed as part of the Linux kernel, the following license terms
* apply:
*
* * This program is free software; you can redistribute it and/or modify
* * it under the terms of the GNU General Public License as published by
* * the Free Software Foundation; either version 2 of the named License,
* * or any later version.
* *
* * This program is distributed in the hope that it will be useful,
* * but WITHOUT ANY WARRANTY; without even the implied warranty of
* * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* * GNU General Public License for more details.
* *
* * You should have received a copy of the GNU General Public License
* * along with this program; if not, write to the Free Software
* * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
*
* Otherwise, the following license terms apply:
*
* * Redistribution and use in source and binary forms, with or without
* * modification, are permitted provided that the following conditions
* * are met:
* * 1) Redistributions of source code must retain the above copyright
* * notice, this list of conditions and the following disclaimer.
* * 2) Redistributions in binary form must reproduce the above copyright
* * notice, this list of conditions and the following disclaimer in the
* * documentation and/or other materials provided with the distribution.
* * 3) The name of the author may not be used to endorse or promote products
* * derived from this software without specific prior written permission.
* *
* * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Thomas Winischhofer <[email protected]>
*
* Formerly based on non-functional code-fragements for 300 series by SiS, Inc.
* Used by permission.
*/
#include "init.h"
#ifdef CONFIG_FB_SIS_300
#include "300vtbl.h"
#endif
#ifdef CONFIG_FB_SIS_315
#include "310vtbl.h"
#endif
#if defined(ALLOC_PRAGMA)
#pragma alloc_text(PAGE,SiSSetMode)
#endif
/*********************************************/
/* POINTER INITIALIZATION */
/*********************************************/
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
static void
InitCommonPointer(struct SiS_Private *SiS_Pr)
{
SiS_Pr->SiS_SModeIDTable = SiS_SModeIDTable;
SiS_Pr->SiS_StResInfo = SiS_StResInfo;
SiS_Pr->SiS_ModeResInfo = SiS_ModeResInfo;
SiS_Pr->SiS_StandTable = SiS_StandTable;
SiS_Pr->SiS_NTSCTiming = SiS_NTSCTiming;
SiS_Pr->SiS_PALTiming = SiS_PALTiming;
SiS_Pr->SiS_HiTVSt1Timing = SiS_HiTVSt1Timing;
SiS_Pr->SiS_HiTVSt2Timing = SiS_HiTVSt2Timing;
SiS_Pr->SiS_HiTVExtTiming = SiS_HiTVExtTiming;
SiS_Pr->SiS_HiTVGroup3Data = SiS_HiTVGroup3Data;
SiS_Pr->SiS_HiTVGroup3Simu = SiS_HiTVGroup3Simu;
#if 0
SiS_Pr->SiS_HiTVTextTiming = SiS_HiTVTextTiming;
SiS_Pr->SiS_HiTVGroup3Text = SiS_HiTVGroup3Text;
#endif
SiS_Pr->SiS_StPALData = SiS_StPALData;
SiS_Pr->SiS_ExtPALData = SiS_ExtPALData;
SiS_Pr->SiS_StNTSCData = SiS_StNTSCData;
SiS_Pr->SiS_ExtNTSCData = SiS_ExtNTSCData;
SiS_Pr->SiS_St1HiTVData = SiS_StHiTVData;
SiS_Pr->SiS_St2HiTVData = SiS_St2HiTVData;
SiS_Pr->SiS_ExtHiTVData = SiS_ExtHiTVData;
SiS_Pr->SiS_St525iData = SiS_StNTSCData;
SiS_Pr->SiS_St525pData = SiS_St525pData;
SiS_Pr->SiS_St750pData = SiS_St750pData;
SiS_Pr->SiS_Ext525iData = SiS_ExtNTSCData;
SiS_Pr->SiS_Ext525pData = SiS_ExtNTSCData;
SiS_Pr->SiS_Ext750pData = SiS_Ext750pData;
SiS_Pr->pSiS_OutputSelect = &SiS_OutputSelect;
SiS_Pr->pSiS_SoftSetting = &SiS_SoftSetting;
SiS_Pr->SiS_LCD1280x720Data = SiS_LCD1280x720Data;
SiS_Pr->SiS_StLCD1280x768_2Data = SiS_StLCD1280x768_2Data;
SiS_Pr->SiS_ExtLCD1280x768_2Data = SiS_ExtLCD1280x768_2Data;
SiS_Pr->SiS_LCD1280x800Data = SiS_LCD1280x800Data;
SiS_Pr->SiS_LCD1280x800_2Data = SiS_LCD1280x800_2Data;
SiS_Pr->SiS_LCD1280x854Data = SiS_LCD1280x854Data;
SiS_Pr->SiS_LCD1280x960Data = SiS_LCD1280x960Data;
SiS_Pr->SiS_StLCD1400x1050Data = SiS_StLCD1400x1050Data;
SiS_Pr->SiS_ExtLCD1400x1050Data = SiS_ExtLCD1400x1050Data;
SiS_Pr->SiS_LCD1680x1050Data = SiS_LCD1680x1050Data;
SiS_Pr->SiS_StLCD1600x1200Data = SiS_StLCD1600x1200Data;
SiS_Pr->SiS_ExtLCD1600x1200Data = SiS_ExtLCD1600x1200Data;
SiS_Pr->SiS_NoScaleData = SiS_NoScaleData;
SiS_Pr->SiS_LVDS320x240Data_1 = SiS_LVDS320x240Data_1;
SiS_Pr->SiS_LVDS320x240Data_2 = SiS_LVDS320x240Data_2;
SiS_Pr->SiS_LVDS640x480Data_1 = SiS_LVDS640x480Data_1;
SiS_Pr->SiS_LVDS800x600Data_1 = SiS_LVDS800x600Data_1;
SiS_Pr->SiS_LVDS1024x600Data_1 = SiS_LVDS1024x600Data_1;
SiS_Pr->SiS_LVDS1024x768Data_1 = SiS_LVDS1024x768Data_1;
SiS_Pr->SiS_LVDSCRT1320x240_1 = SiS_LVDSCRT1320x240_1;
SiS_Pr->SiS_LVDSCRT1320x240_2 = SiS_LVDSCRT1320x240_2;
SiS_Pr->SiS_LVDSCRT1320x240_2_H = SiS_LVDSCRT1320x240_2_H;
SiS_Pr->SiS_LVDSCRT1320x240_3 = SiS_LVDSCRT1320x240_3;
SiS_Pr->SiS_LVDSCRT1320x240_3_H = SiS_LVDSCRT1320x240_3_H;
SiS_Pr->SiS_LVDSCRT1640x480_1 = SiS_LVDSCRT1640x480_1;
SiS_Pr->SiS_LVDSCRT1640x480_1_H = SiS_LVDSCRT1640x480_1_H;
#if 0
SiS_Pr->SiS_LVDSCRT11024x600_1 = SiS_LVDSCRT11024x600_1;
SiS_Pr->SiS_LVDSCRT11024x600_1_H = SiS_LVDSCRT11024x600_1_H;
SiS_Pr->SiS_LVDSCRT11024x600_2 = SiS_LVDSCRT11024x600_2;
SiS_Pr->SiS_LVDSCRT11024x600_2_H = SiS_LVDSCRT11024x600_2_H;
#endif
SiS_Pr->SiS_CHTVUNTSCData = SiS_CHTVUNTSCData;
SiS_Pr->SiS_CHTVONTSCData = SiS_CHTVONTSCData;
SiS_Pr->SiS_PanelMinLVDS = Panel_800x600; /* lowest value LVDS/LCDA */
SiS_Pr->SiS_PanelMin301 = Panel_1024x768; /* lowest value 301 */
}
#endif
#ifdef CONFIG_FB_SIS_300
static void
InitTo300Pointer(struct SiS_Private *SiS_Pr)
{
InitCommonPointer(SiS_Pr);
SiS_Pr->SiS_VBModeIDTable = SiS300_VBModeIDTable;
SiS_Pr->SiS_EModeIDTable = SiS300_EModeIDTable;
SiS_Pr->SiS_RefIndex = SiS300_RefIndex;
SiS_Pr->SiS_CRT1Table = SiS300_CRT1Table;
if(SiS_Pr->ChipType == SIS_300) {
SiS_Pr->SiS_MCLKData_0 = SiS300_MCLKData_300; /* 300 */
} else {
SiS_Pr->SiS_MCLKData_0 = SiS300_MCLKData_630; /* 630, 730 */
}
SiS_Pr->SiS_VCLKData = SiS300_VCLKData;
SiS_Pr->SiS_VBVCLKData = (struct SiS_VBVCLKData *)SiS300_VCLKData;
SiS_Pr->SiS_SR15 = SiS300_SR15;
SiS_Pr->SiS_PanelDelayTbl = SiS300_PanelDelayTbl;
SiS_Pr->SiS_PanelDelayTblLVDS = SiS300_PanelDelayTbl;
SiS_Pr->SiS_ExtLCD1024x768Data = SiS300_ExtLCD1024x768Data;
SiS_Pr->SiS_St2LCD1024x768Data = SiS300_St2LCD1024x768Data;
SiS_Pr->SiS_ExtLCD1280x1024Data = SiS300_ExtLCD1280x1024Data;
SiS_Pr->SiS_St2LCD1280x1024Data = SiS300_St2LCD1280x1024Data;
SiS_Pr->SiS_CRT2Part2_1024x768_1 = SiS300_CRT2Part2_1024x768_1;
SiS_Pr->SiS_CRT2Part2_1024x768_2 = SiS300_CRT2Part2_1024x768_2;
SiS_Pr->SiS_CRT2Part2_1024x768_3 = SiS300_CRT2Part2_1024x768_3;
SiS_Pr->SiS_CHTVUPALData = SiS300_CHTVUPALData;
SiS_Pr->SiS_CHTVOPALData = SiS300_CHTVOPALData;
SiS_Pr->SiS_CHTVUPALMData = SiS_CHTVUNTSCData; /* not supported on 300 series */
SiS_Pr->SiS_CHTVOPALMData = SiS_CHTVONTSCData; /* not supported on 300 series */
SiS_Pr->SiS_CHTVUPALNData = SiS300_CHTVUPALData; /* not supported on 300 series */
SiS_Pr->SiS_CHTVOPALNData = SiS300_CHTVOPALData; /* not supported on 300 series */
SiS_Pr->SiS_CHTVSOPALData = SiS300_CHTVSOPALData;
SiS_Pr->SiS_LVDS848x480Data_1 = SiS300_LVDS848x480Data_1;
SiS_Pr->SiS_LVDS848x480Data_2 = SiS300_LVDS848x480Data_2;
SiS_Pr->SiS_LVDSBARCO1024Data_1 = SiS300_LVDSBARCO1024Data_1;
SiS_Pr->SiS_LVDSBARCO1366Data_1 = SiS300_LVDSBARCO1366Data_1;
SiS_Pr->SiS_LVDSBARCO1366Data_2 = SiS300_LVDSBARCO1366Data_2;
SiS_Pr->SiS_PanelType04_1a = SiS300_PanelType04_1a;
SiS_Pr->SiS_PanelType04_2a = SiS300_PanelType04_2a;
SiS_Pr->SiS_PanelType04_1b = SiS300_PanelType04_1b;
SiS_Pr->SiS_PanelType04_2b = SiS300_PanelType04_2b;
SiS_Pr->SiS_CHTVCRT1UNTSC = SiS300_CHTVCRT1UNTSC;
SiS_Pr->SiS_CHTVCRT1ONTSC = SiS300_CHTVCRT1ONTSC;
SiS_Pr->SiS_CHTVCRT1UPAL = SiS300_CHTVCRT1UPAL;
SiS_Pr->SiS_CHTVCRT1OPAL = SiS300_CHTVCRT1OPAL;
SiS_Pr->SiS_CHTVCRT1SOPAL = SiS300_CHTVCRT1SOPAL;
SiS_Pr->SiS_CHTVReg_UNTSC = SiS300_CHTVReg_UNTSC;
SiS_Pr->SiS_CHTVReg_ONTSC = SiS300_CHTVReg_ONTSC;
SiS_Pr->SiS_CHTVReg_UPAL = SiS300_CHTVReg_UPAL;
SiS_Pr->SiS_CHTVReg_OPAL = SiS300_CHTVReg_OPAL;
SiS_Pr->SiS_CHTVReg_UPALM = SiS300_CHTVReg_UNTSC; /* not supported on 300 series */
SiS_Pr->SiS_CHTVReg_OPALM = SiS300_CHTVReg_ONTSC; /* not supported on 300 series */
SiS_Pr->SiS_CHTVReg_UPALN = SiS300_CHTVReg_UPAL; /* not supported on 300 series */
SiS_Pr->SiS_CHTVReg_OPALN = SiS300_CHTVReg_OPAL; /* not supported on 300 series */
SiS_Pr->SiS_CHTVReg_SOPAL = SiS300_CHTVReg_SOPAL;
SiS_Pr->SiS_CHTVVCLKUNTSC = SiS300_CHTVVCLKUNTSC;
SiS_Pr->SiS_CHTVVCLKONTSC = SiS300_CHTVVCLKONTSC;
SiS_Pr->SiS_CHTVVCLKUPAL = SiS300_CHTVVCLKUPAL;
SiS_Pr->SiS_CHTVVCLKOPAL = SiS300_CHTVVCLKOPAL;
SiS_Pr->SiS_CHTVVCLKUPALM = SiS300_CHTVVCLKUNTSC; /* not supported on 300 series */
SiS_Pr->SiS_CHTVVCLKOPALM = SiS300_CHTVVCLKONTSC; /* not supported on 300 series */
SiS_Pr->SiS_CHTVVCLKUPALN = SiS300_CHTVVCLKUPAL; /* not supported on 300 series */
SiS_Pr->SiS_CHTVVCLKOPALN = SiS300_CHTVVCLKOPAL; /* not supported on 300 series */
SiS_Pr->SiS_CHTVVCLKSOPAL = SiS300_CHTVVCLKSOPAL;
}
#endif
#ifdef CONFIG_FB_SIS_315
static void
InitTo310Pointer(struct SiS_Private *SiS_Pr)
{
InitCommonPointer(SiS_Pr);
SiS_Pr->SiS_EModeIDTable = SiS310_EModeIDTable;
SiS_Pr->SiS_RefIndex = SiS310_RefIndex;
SiS_Pr->SiS_CRT1Table = SiS310_CRT1Table;
if(SiS_Pr->ChipType >= SIS_340) {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_340; /* 340 + XGI */
} else if(SiS_Pr->ChipType >= SIS_761) {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_761; /* 761 - preliminary */
} else if(SiS_Pr->ChipType >= SIS_760) {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_760; /* 760 */
} else if(SiS_Pr->ChipType >= SIS_661) {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_660; /* 661/741 */
} else if(SiS_Pr->ChipType == SIS_330) {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_330; /* 330 */
} else if(SiS_Pr->ChipType > SIS_315PRO) {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_650; /* 550, 650, 740 */
} else {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_315; /* 315 */
}
if(SiS_Pr->ChipType >= SIS_340) {
SiS_Pr->SiS_MCLKData_1 = SiS310_MCLKData_1_340;
} else {
SiS_Pr->SiS_MCLKData_1 = SiS310_MCLKData_1;
}
SiS_Pr->SiS_VCLKData = SiS310_VCLKData;
SiS_Pr->SiS_VBVCLKData = SiS310_VBVCLKData;
SiS_Pr->SiS_SR15 = SiS310_SR15;
SiS_Pr->SiS_PanelDelayTbl = SiS310_PanelDelayTbl;
SiS_Pr->SiS_PanelDelayTblLVDS = SiS310_PanelDelayTblLVDS;
SiS_Pr->SiS_St2LCD1024x768Data = SiS310_St2LCD1024x768Data;
SiS_Pr->SiS_ExtLCD1024x768Data = SiS310_ExtLCD1024x768Data;
SiS_Pr->SiS_St2LCD1280x1024Data = SiS310_St2LCD1280x1024Data;
SiS_Pr->SiS_ExtLCD1280x1024Data = SiS310_ExtLCD1280x1024Data;
SiS_Pr->SiS_CRT2Part2_1024x768_1 = SiS310_CRT2Part2_1024x768_1;
SiS_Pr->SiS_CHTVUPALData = SiS310_CHTVUPALData;
SiS_Pr->SiS_CHTVOPALData = SiS310_CHTVOPALData;
SiS_Pr->SiS_CHTVUPALMData = SiS310_CHTVUPALMData;
SiS_Pr->SiS_CHTVOPALMData = SiS310_CHTVOPALMData;
SiS_Pr->SiS_CHTVUPALNData = SiS310_CHTVUPALNData;
SiS_Pr->SiS_CHTVOPALNData = SiS310_CHTVOPALNData;
SiS_Pr->SiS_CHTVSOPALData = SiS310_CHTVSOPALData;
SiS_Pr->SiS_CHTVCRT1UNTSC = SiS310_CHTVCRT1UNTSC;
SiS_Pr->SiS_CHTVCRT1ONTSC = SiS310_CHTVCRT1ONTSC;
SiS_Pr->SiS_CHTVCRT1UPAL = SiS310_CHTVCRT1UPAL;
SiS_Pr->SiS_CHTVCRT1OPAL = SiS310_CHTVCRT1OPAL;
SiS_Pr->SiS_CHTVCRT1SOPAL = SiS310_CHTVCRT1OPAL;
SiS_Pr->SiS_CHTVReg_UNTSC = SiS310_CHTVReg_UNTSC;
SiS_Pr->SiS_CHTVReg_ONTSC = SiS310_CHTVReg_ONTSC;
SiS_Pr->SiS_CHTVReg_UPAL = SiS310_CHTVReg_UPAL;
SiS_Pr->SiS_CHTVReg_OPAL = SiS310_CHTVReg_OPAL;
SiS_Pr->SiS_CHTVReg_UPALM = SiS310_CHTVReg_UPALM;
SiS_Pr->SiS_CHTVReg_OPALM = SiS310_CHTVReg_OPALM;
SiS_Pr->SiS_CHTVReg_UPALN = SiS310_CHTVReg_UPALN;
SiS_Pr->SiS_CHTVReg_OPALN = SiS310_CHTVReg_OPALN;
SiS_Pr->SiS_CHTVReg_SOPAL = SiS310_CHTVReg_OPAL;
SiS_Pr->SiS_CHTVVCLKUNTSC = SiS310_CHTVVCLKUNTSC;
SiS_Pr->SiS_CHTVVCLKONTSC = SiS310_CHTVVCLKONTSC;
SiS_Pr->SiS_CHTVVCLKUPAL = SiS310_CHTVVCLKUPAL;
SiS_Pr->SiS_CHTVVCLKOPAL = SiS310_CHTVVCLKOPAL;
SiS_Pr->SiS_CHTVVCLKUPALM = SiS310_CHTVVCLKUPALM;
SiS_Pr->SiS_CHTVVCLKOPALM = SiS310_CHTVVCLKOPALM;
SiS_Pr->SiS_CHTVVCLKUPALN = SiS310_CHTVVCLKUPALN;
SiS_Pr->SiS_CHTVVCLKOPALN = SiS310_CHTVVCLKOPALN;
SiS_Pr->SiS_CHTVVCLKSOPAL = SiS310_CHTVVCLKOPAL;
}
#endif
bool
SiSInitPtr(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
InitTo300Pointer(SiS_Pr);
#else
return false;
#endif
} else {
#ifdef CONFIG_FB_SIS_315
InitTo310Pointer(SiS_Pr);
#else
return false;
#endif
}
return true;
}
/*********************************************/
/* HELPER: Get ModeID */
/*********************************************/
static
unsigned short
SiS_GetModeID(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay,
int Depth, bool FSTN, int LCDwidth, int LCDheight)
{
unsigned short ModeIndex = 0;
switch(HDisplay)
{
case 320:
if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
else if(VDisplay == 240) {
if((VBFlags & CRT2_LCD) && (FSTN))
ModeIndex = ModeIndex_320x240_FSTN[Depth];
else
ModeIndex = ModeIndex_320x240[Depth];
}
break;
case 400:
if((!(VBFlags & CRT1_LCDA)) || ((LCDwidth >= 800) && (LCDheight >= 600))) {
if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
}
break;
case 512:
if((!(VBFlags & CRT1_LCDA)) || ((LCDwidth >= 1024) && (LCDheight >= 768))) {
if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
}
break;
case 640:
if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
break;
case 720:
if(VDisplay == 480) ModeIndex = ModeIndex_720x480[Depth];
else if(VDisplay == 576) ModeIndex = ModeIndex_720x576[Depth];
break;
case 768:
if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
break;
case 800:
if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
else if(VDisplay == 480) ModeIndex = ModeIndex_800x480[Depth];
break;
case 848:
if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
break;
case 856:
if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
break;
case 960:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 540) ModeIndex = ModeIndex_960x540[Depth];
else if(VDisplay == 600) ModeIndex = ModeIndex_960x600[Depth];
}
break;
case 1024:
if(VDisplay == 576) ModeIndex = ModeIndex_1024x576[Depth];
else if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
else if(VGAEngine == SIS_300_VGA) {
if(VDisplay == 600) ModeIndex = ModeIndex_1024x600[Depth];
}
break;
case 1152:
if(VDisplay == 864) ModeIndex = ModeIndex_1152x864[Depth];
if(VGAEngine == SIS_300_VGA) {
if(VDisplay == 768) ModeIndex = ModeIndex_1152x768[Depth];
}
break;
case 1280:
switch(VDisplay) {
case 720:
ModeIndex = ModeIndex_1280x720[Depth];
break;
case 768:
if(VGAEngine == SIS_300_VGA) {
ModeIndex = ModeIndex_300_1280x768[Depth];
} else {
ModeIndex = ModeIndex_310_1280x768[Depth];
}
break;
case 800:
if(VGAEngine == SIS_315_VGA) {
ModeIndex = ModeIndex_1280x800[Depth];
}
break;
case 854:
if(VGAEngine == SIS_315_VGA) {
ModeIndex = ModeIndex_1280x854[Depth];
}
break;
case 960:
ModeIndex = ModeIndex_1280x960[Depth];
break;
case 1024:
ModeIndex = ModeIndex_1280x1024[Depth];
break;
}
break;
case 1360:
if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
if(VGAEngine == SIS_300_VGA) {
if(VDisplay == 1024) ModeIndex = ModeIndex_300_1360x1024[Depth];
}
break;
case 1400:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 1050) {
ModeIndex = ModeIndex_1400x1050[Depth];
}
}
break;
case 1600:
if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
break;
case 1680:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 1050) ModeIndex = ModeIndex_1680x1050[Depth];
}
break;
case 1920:
if(VDisplay == 1440) ModeIndex = ModeIndex_1920x1440[Depth];
else if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 1080) ModeIndex = ModeIndex_1920x1080[Depth];
}
break;
case 2048:
if(VDisplay == 1536) {
if(VGAEngine == SIS_300_VGA) {
ModeIndex = ModeIndex_300_2048x1536[Depth];
} else {
ModeIndex = ModeIndex_310_2048x1536[Depth];
}
}
break;
}
return ModeIndex;
}
unsigned short
SiS_GetModeID_LCD(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay,
int Depth, bool FSTN, unsigned short CustomT, int LCDwidth, int LCDheight,
unsigned int VBFlags2)
{
unsigned short ModeIndex = 0;
if(VBFlags2 & (VB2_LVDS | VB2_30xBDH)) {
switch(HDisplay)
{
case 320:
if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
if(VDisplay == 200) {
if(!FSTN) ModeIndex = ModeIndex_320x200[Depth];
} else if(VDisplay == 240) {
if(!FSTN) ModeIndex = ModeIndex_320x240[Depth];
else if(VGAEngine == SIS_315_VGA) {
ModeIndex = ModeIndex_320x240_FSTN[Depth];
}
}
}
break;
case 400:
if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
if(!((VGAEngine == SIS_300_VGA) && (VBFlags2 & VB2_TRUMPION))) {
if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
}
}
break;
case 512:
if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
if(!((VGAEngine == SIS_300_VGA) && (VBFlags2 & VB2_TRUMPION))) {
if(LCDwidth >= 1024 && LCDwidth != 1152 && LCDheight >= 768) {
if(VDisplay == 384) {
ModeIndex = ModeIndex_512x384[Depth];
}
}
}
}
break;
case 640:
if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
else if(VDisplay == 400) {
if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856))
ModeIndex = ModeIndex_640x400[Depth];
}
break;
case 800:
if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
break;
case 848:
if(CustomT == CUT_PANEL848) {
if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
}
break;
case 856:
if(CustomT == CUT_PANEL856) {
if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
}
break;
case 1024:
if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
else if(VGAEngine == SIS_300_VGA) {
if((VDisplay == 600) && (LCDheight == 600)) {
ModeIndex = ModeIndex_1024x600[Depth];
}
}
break;
case 1152:
if(VGAEngine == SIS_300_VGA) {
if((VDisplay == 768) && (LCDheight == 768)) {
ModeIndex = ModeIndex_1152x768[Depth];
}
}
break;
case 1280:
if(VDisplay == 1024) ModeIndex = ModeIndex_1280x1024[Depth];
else if(VGAEngine == SIS_315_VGA) {
if((VDisplay == 768) && (LCDheight == 768)) {
ModeIndex = ModeIndex_310_1280x768[Depth];
}
}
break;
case 1360:
if(VGAEngine == SIS_300_VGA) {
if(CustomT == CUT_BARCO1366) {
if(VDisplay == 1024) ModeIndex = ModeIndex_300_1360x1024[Depth];
}
}
if(CustomT == CUT_PANEL848) {
if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
}
break;
case 1400:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 1050) ModeIndex = ModeIndex_1400x1050[Depth];
}
break;
case 1600:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
}
break;
}
} else if(VBFlags2 & VB2_SISBRIDGE) {
switch(HDisplay)
{
case 320:
if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
else if(VDisplay == 240) ModeIndex = ModeIndex_320x240[Depth];
break;
case 400:
if(LCDwidth >= 800 && LCDheight >= 600) {
if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
}
break;
case 512:
if(LCDwidth >= 1024 && LCDheight >= 768 && LCDwidth != 1152) {
if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
}
break;
case 640:
if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
break;
case 720:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 480) ModeIndex = ModeIndex_720x480[Depth];
else if(VDisplay == 576) ModeIndex = ModeIndex_720x576[Depth];
}
break;
case 768:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
}
break;
case 800:
if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 480) ModeIndex = ModeIndex_800x480[Depth];
}
break;
case 848:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
}
break;
case 856:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
}
break;
case 960:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 540) ModeIndex = ModeIndex_960x540[Depth];
else if(VDisplay == 600) ModeIndex = ModeIndex_960x600[Depth];
}
break;
case 1024:
if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 576) ModeIndex = ModeIndex_1024x576[Depth];
}
break;
case 1152:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 864) ModeIndex = ModeIndex_1152x864[Depth];
}
break;
case 1280:
switch(VDisplay) {
case 720:
ModeIndex = ModeIndex_1280x720[Depth];
break;
case 768:
if(VGAEngine == SIS_300_VGA) {
ModeIndex = ModeIndex_300_1280x768[Depth];
} else {
ModeIndex = ModeIndex_310_1280x768[Depth];
}
break;
case 800:
if(VGAEngine == SIS_315_VGA) {
ModeIndex = ModeIndex_1280x800[Depth];
}
break;
case 854:
if(VGAEngine == SIS_315_VGA) {
ModeIndex = ModeIndex_1280x854[Depth];
}
break;
case 960:
ModeIndex = ModeIndex_1280x960[Depth];
break;
case 1024:
ModeIndex = ModeIndex_1280x1024[Depth];
break;
}
break;
case 1360:
if(VGAEngine == SIS_315_VGA) { /* OVER1280 only? */
if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
}
break;
case 1400:
if(VGAEngine == SIS_315_VGA) {
if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
if(VDisplay == 1050) ModeIndex = ModeIndex_1400x1050[Depth];
}
}
break;
case 1600:
if(VGAEngine == SIS_315_VGA) {
if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
}
}
break;
#ifndef VB_FORBID_CRT2LCD_OVER_1600
case 1680:
if(VGAEngine == SIS_315_VGA) {
if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
if(VDisplay == 1050) ModeIndex = ModeIndex_1680x1050[Depth];
}
}
break;
case 1920:
if(VGAEngine == SIS_315_VGA) {
if(VBFlags2 & VB2_LCDOVER1600BRIDGE) {
if(VDisplay == 1440) ModeIndex = ModeIndex_1920x1440[Depth];
}
}
break;
case 2048:
if(VGAEngine == SIS_315_VGA) {
if(VBFlags2 & VB2_LCDOVER1600BRIDGE) {
if(VDisplay == 1536) ModeIndex = ModeIndex_310_2048x1536[Depth];
}
}
break;
#endif
}
}
return ModeIndex;
}
unsigned short
SiS_GetModeID_TV(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay, int Depth,
unsigned int VBFlags2)
{
unsigned short ModeIndex = 0;
if(VBFlags2 & VB2_CHRONTEL) {
switch(HDisplay)
{
case 512:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
}
break;
case 640:
if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
break;
case 800:
if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
break;
case 1024:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
}
break;
}
} else if(VBFlags2 & VB2_SISTVBRIDGE) {
switch(HDisplay)
{
case 320:
if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
else if(VDisplay == 240) ModeIndex = ModeIndex_320x240[Depth];
break;
case 400:
if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
break;
case 512:
if( ((VBFlags & TV_YPBPR) && (VBFlags & (TV_YPBPR750P | TV_YPBPR1080I))) ||
(VBFlags & TV_HIVISION) ||
((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL)) ) {
if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
}
break;
case 640:
if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
break;
case 720:
if((!(VBFlags & TV_HIVISION)) && (!((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I)))) {
if(VDisplay == 480) {
ModeIndex = ModeIndex_720x480[Depth];
} else if(VDisplay == 576) {
if( ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR750P)) ||
((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL)) )
ModeIndex = ModeIndex_720x576[Depth];
}
}
break;
case 768:
if((!(VBFlags & TV_HIVISION)) && (!((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I)))) {
if( ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR750P)) ||
((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL)) ) {
if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
}
}
break;
case 800:
if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
else if(VDisplay == 480) {
if(!((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR750P))) {
ModeIndex = ModeIndex_800x480[Depth];
}
}
break;
case 960:
if(VGAEngine == SIS_315_VGA) {
if(VDisplay == 600) {
if((VBFlags & TV_HIVISION) || ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I))) {
ModeIndex = ModeIndex_960x600[Depth];
}
}
}
break;
case 1024:
if(VDisplay == 768) {
if(VBFlags2 & VB2_30xBLV) {
ModeIndex = ModeIndex_1024x768[Depth];
}
} else if(VDisplay == 576) {
if( (VBFlags & TV_HIVISION) ||
((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I)) ||
((VBFlags2 & VB2_30xBLV) &&
((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL))) ) {
ModeIndex = ModeIndex_1024x576[Depth];
}
}
break;
case 1280:
if(VDisplay == 720) {
if((VBFlags & TV_HIVISION) ||
((VBFlags & TV_YPBPR) && (VBFlags & (TV_YPBPR1080I | TV_YPBPR750P)))) {
ModeIndex = ModeIndex_1280x720[Depth];
}
} else if(VDisplay == 1024) {
if((VBFlags & TV_HIVISION) ||
((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I))) {
ModeIndex = ModeIndex_1280x1024[Depth];
}
}
break;
}
}
return ModeIndex;
}
unsigned short
SiS_GetModeID_VGA2(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay, int Depth,
unsigned int VBFlags2)
{
if(!(VBFlags2 & VB2_SISVGA2BRIDGE)) return 0;
if(HDisplay >= 1920) return 0;
switch(HDisplay)
{
case 1600:
if(VDisplay == 1200) {
if(VGAEngine != SIS_315_VGA) return 0;
if(!(VBFlags2 & VB2_30xB)) return 0;
}
break;
case 1680:
if(VDisplay == 1050) {
if(VGAEngine != SIS_315_VGA) return 0;
if(!(VBFlags2 & VB2_30xB)) return 0;
}
break;
}
return SiS_GetModeID(VGAEngine, 0, HDisplay, VDisplay, Depth, false, 0, 0);
}
/*********************************************/
/* HELPER: SetReg, GetReg */
/*********************************************/
void
SiS_SetReg(SISIOADDRESS port, u8 index, u8 data)
{
outb(index, port);
outb(data, port + 1);
}
void
SiS_SetRegByte(SISIOADDRESS port, u8 data)
{
outb(data, port);
}
void
SiS_SetRegShort(SISIOADDRESS port, u16 data)
{
outw(data, port);
}
void
SiS_SetRegLong(SISIOADDRESS port, u32 data)
{
outl(data, port);
}
u8
SiS_GetReg(SISIOADDRESS port, u8 index)
{
outb(index, port);
return inb(port + 1);
}
u8
SiS_GetRegByte(SISIOADDRESS port)
{
return inb(port);
}
u16
SiS_GetRegShort(SISIOADDRESS port)
{
return inw(port);
}
u32
SiS_GetRegLong(SISIOADDRESS port)
{
return inl(port);
}
void
SiS_SetRegANDOR(SISIOADDRESS Port, u8 Index, u8 DataAND, u8 DataOR)
{
u8 temp;
temp = SiS_GetReg(Port, Index);
temp = (temp & (DataAND)) | DataOR;
SiS_SetReg(Port, Index, temp);
}
void
SiS_SetRegAND(SISIOADDRESS Port, u8 Index, u8 DataAND)
{
u8 temp;
temp = SiS_GetReg(Port, Index);
temp &= DataAND;
SiS_SetReg(Port, Index, temp);
}
void
SiS_SetRegOR(SISIOADDRESS Port, u8 Index, u8 DataOR)
{
u8 temp;
temp = SiS_GetReg(Port, Index);
temp |= DataOR;
SiS_SetReg(Port, Index, temp);
}
/*********************************************/
/* HELPER: DisplayOn, DisplayOff */
/*********************************************/
void
SiS_DisplayOn(struct SiS_Private *SiS_Pr)
{
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x01,0xDF);
}
void
SiS_DisplayOff(struct SiS_Private *SiS_Pr)
{
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x01,0x20);
}
/*********************************************/
/* HELPER: Init Port Addresses */
/*********************************************/
void
SiSRegInit(struct SiS_Private *SiS_Pr, SISIOADDRESS BaseAddr)
{
SiS_Pr->SiS_P3c4 = BaseAddr + 0x14;
SiS_Pr->SiS_P3d4 = BaseAddr + 0x24;
SiS_Pr->SiS_P3c0 = BaseAddr + 0x10;
SiS_Pr->SiS_P3ce = BaseAddr + 0x1e;
SiS_Pr->SiS_P3c2 = BaseAddr + 0x12;
SiS_Pr->SiS_P3ca = BaseAddr + 0x1a;
SiS_Pr->SiS_P3c6 = BaseAddr + 0x16;
SiS_Pr->SiS_P3c7 = BaseAddr + 0x17;
SiS_Pr->SiS_P3c8 = BaseAddr + 0x18;
SiS_Pr->SiS_P3c9 = BaseAddr + 0x19;
SiS_Pr->SiS_P3cb = BaseAddr + 0x1b;
SiS_Pr->SiS_P3cc = BaseAddr + 0x1c;
SiS_Pr->SiS_P3cd = BaseAddr + 0x1d;
SiS_Pr->SiS_P3da = BaseAddr + 0x2a;
SiS_Pr->SiS_Part1Port = BaseAddr + SIS_CRT2_PORT_04;
SiS_Pr->SiS_Part2Port = BaseAddr + SIS_CRT2_PORT_10;
SiS_Pr->SiS_Part3Port = BaseAddr + SIS_CRT2_PORT_12;
SiS_Pr->SiS_Part4Port = BaseAddr + SIS_CRT2_PORT_14;
SiS_Pr->SiS_Part5Port = BaseAddr + SIS_CRT2_PORT_14 + 2;
SiS_Pr->SiS_DDC_Port = BaseAddr + 0x14;
SiS_Pr->SiS_VidCapt = BaseAddr + SIS_VIDEO_CAPTURE;
SiS_Pr->SiS_VidPlay = BaseAddr + SIS_VIDEO_PLAYBACK;
}
/*********************************************/
/* HELPER: GetSysFlags */
/*********************************************/
static void
SiS_GetSysFlags(struct SiS_Private *SiS_Pr)
{
unsigned char cr5f, temp1, temp2;
/* 661 and newer: NEVER write non-zero to SR11[7:4] */
/* (SR11 is used for DDC and in enable/disablebridge) */
SiS_Pr->SiS_SensibleSR11 = false;
SiS_Pr->SiS_MyCR63 = 0x63;
if(SiS_Pr->ChipType >= SIS_330) {
SiS_Pr->SiS_MyCR63 = 0x53;
if(SiS_Pr->ChipType >= SIS_661) {
SiS_Pr->SiS_SensibleSR11 = true;
}
}
/* You should use the macros, not these flags directly */
SiS_Pr->SiS_SysFlags = 0;
if(SiS_Pr->ChipType == SIS_650) {
cr5f = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0xf0;
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x5c,0x07);
temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x5c,0xf8);
temp2 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
if((!temp1) || (temp2)) {
switch(cr5f) {
case 0x80:
case 0x90:
case 0xc0:
SiS_Pr->SiS_SysFlags |= SF_IsM650;
break;
case 0xa0:
case 0xb0:
case 0xe0:
SiS_Pr->SiS_SysFlags |= SF_Is651;
break;
}
} else {
switch(cr5f) {
case 0x90:
temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
switch(temp1) {
case 0x00: SiS_Pr->SiS_SysFlags |= SF_IsM652; break;
case 0x40: SiS_Pr->SiS_SysFlags |= SF_IsM653; break;
default: SiS_Pr->SiS_SysFlags |= SF_IsM650; break;
}
break;
case 0xb0:
SiS_Pr->SiS_SysFlags |= SF_Is652;
break;
default:
SiS_Pr->SiS_SysFlags |= SF_IsM650;
break;
}
}
}
if(SiS_Pr->ChipType >= SIS_760 && SiS_Pr->ChipType <= SIS_761) {
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0x30) {
SiS_Pr->SiS_SysFlags |= SF_760LFB;
}
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x79) & 0xf0) {
SiS_Pr->SiS_SysFlags |= SF_760UMA;
}
}
}
/*********************************************/
/* HELPER: Init PCI & Engines */
/*********************************************/
static void
SiSInitPCIetc(struct SiS_Private *SiS_Pr)
{
switch(SiS_Pr->ChipType) {
#ifdef CONFIG_FB_SIS_300
case SIS_300:
case SIS_540:
case SIS_630:
case SIS_730:
/* Set - PCI LINEAR ADDRESSING ENABLE (0x80)
* - RELOCATED VGA IO ENABLED (0x20)
* - MMIO ENABLED (0x01)
* Leave other bits untouched.
*/
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
/* - Enable 2D (0x40)
* - Enable 3D (0x02)
* - Enable 3D Vertex command fetch (0x10) ?
* - Enable 3D command parser (0x08) ?
*/
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x5A);
break;
#endif
#ifdef CONFIG_FB_SIS_315
case SIS_315H:
case SIS_315:
case SIS_315PRO:
case SIS_650:
case SIS_740:
case SIS_330:
case SIS_661:
case SIS_741:
case SIS_660:
case SIS_760:
case SIS_761:
case SIS_340:
case XGI_40:
/* See above */
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
/* - Enable 3D G/L transformation engine (0x80)
* - Enable 2D (0x40)
* - Enable 3D vertex command fetch (0x10)
* - Enable 3D command parser (0x08)
* - Enable 3D (0x02)
*/
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0xDA);
break;
case XGI_20:
case SIS_550:
/* See above */
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
/* No 3D engine ! */
/* - Enable 2D (0x40)
* - disable 3D
*/
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x1E,0x60,0x40);
break;
#endif
default:
break;
}
}
/*********************************************/
/* HELPER: SetLVDSetc */
/*********************************************/
static
void
SiSSetLVDSetc(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
SiS_Pr->SiS_IF_DEF_LVDS = 0;
SiS_Pr->SiS_IF_DEF_TRUMPION = 0;
SiS_Pr->SiS_IF_DEF_CH70xx = 0;
SiS_Pr->SiS_IF_DEF_CONEX = 0;
SiS_Pr->SiS_ChrontelInit = 0;
if(SiS_Pr->ChipType == XGI_20) return;
/* Check for SiS30x first */
temp = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x00);
if((temp == 1) || (temp == 2)) return;
switch(SiS_Pr->ChipType) {
#ifdef CONFIG_FB_SIS_300
case SIS_540:
case SIS_630:
case SIS_730:
temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x37) & 0x0e) >> 1;
if((temp >= 2) && (temp <= 5)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
if(temp == 3) SiS_Pr->SiS_IF_DEF_TRUMPION = 1;
if((temp == 4) || (temp == 5)) {
/* Save power status (and error check) - UNUSED */
SiS_Pr->SiS_Backup70xx = SiS_GetCH700x(SiS_Pr, 0x0e);
SiS_Pr->SiS_IF_DEF_CH70xx = 1;
}
break;
#endif
#ifdef CONFIG_FB_SIS_315
case SIS_550:
case SIS_650:
case SIS_740:
case SIS_330:
temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x37) & 0x0e) >> 1;
if((temp >= 2) && (temp <= 3)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
if(temp == 3) SiS_Pr->SiS_IF_DEF_CH70xx = 2;
break;
case SIS_661:
case SIS_741:
case SIS_660:
case SIS_760:
case SIS_761:
case SIS_340:
case XGI_20:
case XGI_40:
temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x38) & 0xe0) >> 5;
if((temp >= 2) && (temp <= 3)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
if(temp == 3) SiS_Pr->SiS_IF_DEF_CH70xx = 2;
if(temp == 4) SiS_Pr->SiS_IF_DEF_CONEX = 1; /* Not yet supported */
break;
#endif
default:
break;
}
}
/*********************************************/
/* HELPER: Enable DSTN/FSTN */
/*********************************************/
void
SiS_SetEnableDstn(struct SiS_Private *SiS_Pr, int enable)
{
SiS_Pr->SiS_IF_DEF_DSTN = enable ? 1 : 0;
}
void
SiS_SetEnableFstn(struct SiS_Private *SiS_Pr, int enable)
{
SiS_Pr->SiS_IF_DEF_FSTN = enable ? 1 : 0;
}
/*********************************************/
/* HELPER: Get modeflag */
/*********************************************/
unsigned short
SiS_GetModeFlag(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex)
{
if(SiS_Pr->UseCustomMode) {
return SiS_Pr->CModeFlag;
} else if(ModeNo <= 0x13) {
return SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
} else {
return SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
}
/*********************************************/
/* HELPER: Determine ROM usage */
/*********************************************/
bool
SiSDetermineROMLayout661(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romversoffs, romvmaj = 1, romvmin = 0;
if(SiS_Pr->ChipType >= XGI_20) {
/* XGI ROMs don't qualify */
return false;
} else if(SiS_Pr->ChipType >= SIS_761) {
/* I very much assume 761, 340 and newer will use new layout */
return true;
} else if(SiS_Pr->ChipType >= SIS_661) {
if((ROMAddr[0x1a] == 'N') &&
(ROMAddr[0x1b] == 'e') &&
(ROMAddr[0x1c] == 'w') &&
(ROMAddr[0x1d] == 'V')) {
return true;
}
romversoffs = ROMAddr[0x16] | (ROMAddr[0x17] << 8);
if(romversoffs) {
if((ROMAddr[romversoffs+1] == '.') || (ROMAddr[romversoffs+4] == '.')) {
romvmaj = ROMAddr[romversoffs] - '0';
romvmin = ((ROMAddr[romversoffs+2] -'0') * 10) + (ROMAddr[romversoffs+3] - '0');
}
}
if((romvmaj != 0) || (romvmin >= 92)) {
return true;
}
} else if(IS_SIS650740) {
if((ROMAddr[0x1a] == 'N') &&
(ROMAddr[0x1b] == 'e') &&
(ROMAddr[0x1c] == 'w') &&
(ROMAddr[0x1d] == 'V')) {
return true;
}
}
return false;
}
static void
SiSDetermineROMUsage(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romptr = 0;
SiS_Pr->SiS_UseROM = false;
SiS_Pr->SiS_ROMNew = false;
SiS_Pr->SiS_PWDOffset = 0;
if(SiS_Pr->ChipType >= XGI_20) return;
if((ROMAddr) && (SiS_Pr->UseROM)) {
if(SiS_Pr->ChipType == SIS_300) {
/* 300: We check if the code starts below 0x220 by
* checking the jmp instruction at the beginning
* of the BIOS image.
*/
if((ROMAddr[3] == 0xe9) && ((ROMAddr[5] << 8) | ROMAddr[4]) > 0x21a)
SiS_Pr->SiS_UseROM = true;
} else if(SiS_Pr->ChipType < SIS_315H) {
/* Sony's VAIO BIOS 1.09 follows the standard, so perhaps
* the others do as well
*/
SiS_Pr->SiS_UseROM = true;
} else {
/* 315/330 series stick to the standard(s) */
SiS_Pr->SiS_UseROM = true;
if((SiS_Pr->SiS_ROMNew = SiSDetermineROMLayout661(SiS_Pr))) {
SiS_Pr->SiS_EMIOffset = 14;
SiS_Pr->SiS_PWDOffset = 17;
SiS_Pr->SiS661LCD2TableSize = 36;
/* Find out about LCD data table entry size */
if((romptr = SISGETROMW(0x0102))) {
if(ROMAddr[romptr + (32 * 16)] == 0xff)
SiS_Pr->SiS661LCD2TableSize = 32;
else if(ROMAddr[romptr + (34 * 16)] == 0xff)
SiS_Pr->SiS661LCD2TableSize = 34;
else if(ROMAddr[romptr + (36 * 16)] == 0xff) /* 0.94, 2.05.00+ */
SiS_Pr->SiS661LCD2TableSize = 36;
else if( (ROMAddr[romptr + (38 * 16)] == 0xff) || /* 2.00.00 - 2.02.00 */
(ROMAddr[0x6F] & 0x01) ) { /* 2.03.00 - <2.05.00 */
SiS_Pr->SiS661LCD2TableSize = 38; /* UMC data layout abandoned at 2.05.00 */
SiS_Pr->SiS_EMIOffset = 16;
SiS_Pr->SiS_PWDOffset = 19;
}
}
}
}
}
}
/*********************************************/
/* HELPER: SET SEGMENT REGISTERS */
/*********************************************/
static void
SiS_SetSegRegLower(struct SiS_Private *SiS_Pr, unsigned short value)
{
unsigned short temp;
value &= 0x00ff;
temp = SiS_GetRegByte(SiS_Pr->SiS_P3cb) & 0xf0;
temp |= (value >> 4);
SiS_SetRegByte(SiS_Pr->SiS_P3cb, temp);
temp = SiS_GetRegByte(SiS_Pr->SiS_P3cd) & 0xf0;
temp |= (value & 0x0f);
SiS_SetRegByte(SiS_Pr->SiS_P3cd, temp);
}
static void
SiS_SetSegRegUpper(struct SiS_Private *SiS_Pr, unsigned short value)
{
unsigned short temp;
value &= 0x00ff;
temp = SiS_GetRegByte(SiS_Pr->SiS_P3cb) & 0x0f;
temp |= (value & 0xf0);
SiS_SetRegByte(SiS_Pr->SiS_P3cb, temp);
temp = SiS_GetRegByte(SiS_Pr->SiS_P3cd) & 0x0f;
temp |= (value << 4);
SiS_SetRegByte(SiS_Pr->SiS_P3cd, temp);
}
static void
SiS_SetSegmentReg(struct SiS_Private *SiS_Pr, unsigned short value)
{
SiS_SetSegRegLower(SiS_Pr, value);
SiS_SetSegRegUpper(SiS_Pr, value);
}
static void
SiS_ResetSegmentReg(struct SiS_Private *SiS_Pr)
{
SiS_SetSegmentReg(SiS_Pr, 0);
}
static void
SiS_SetSegmentRegOver(struct SiS_Private *SiS_Pr, unsigned short value)
{
unsigned short temp = value >> 8;
temp &= 0x07;
temp |= (temp << 4);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x1d,temp);
SiS_SetSegmentReg(SiS_Pr, value);
}
static void
SiS_ResetSegmentRegOver(struct SiS_Private *SiS_Pr)
{
SiS_SetSegmentRegOver(SiS_Pr, 0);
}
static void
SiS_ResetSegmentRegisters(struct SiS_Private *SiS_Pr)
{
if((IS_SIS65x) || (SiS_Pr->ChipType >= SIS_661)) {
SiS_ResetSegmentReg(SiS_Pr);
SiS_ResetSegmentRegOver(SiS_Pr);
}
}
/*********************************************/
/* HELPER: GetVBType */
/*********************************************/
static
void
SiS_GetVBType(struct SiS_Private *SiS_Pr)
{
unsigned short flag = 0, rev = 0, nolcd = 0;
unsigned short p4_0f, p4_25, p4_27;
SiS_Pr->SiS_VBType = 0;
if((SiS_Pr->SiS_IF_DEF_LVDS) || (SiS_Pr->SiS_IF_DEF_CONEX))
return;
if(SiS_Pr->ChipType == XGI_20)
return;
flag = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x00);
if(flag > 3)
return;
rev = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x01);
if(flag >= 2) {
SiS_Pr->SiS_VBType = VB_SIS302B;
} else if(flag == 1) {
if(rev >= 0xC0) {
SiS_Pr->SiS_VBType = VB_SIS301C;
} else if(rev >= 0xB0) {
SiS_Pr->SiS_VBType = VB_SIS301B;
/* Check if 30xB DH version (no LCD support, use Panel Link instead) */
nolcd = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x23);
if(!(nolcd & 0x02)) SiS_Pr->SiS_VBType |= VB_NoLCD;
} else {
SiS_Pr->SiS_VBType = VB_SIS301;
}
}
if(SiS_Pr->SiS_VBType & (VB_SIS301B | VB_SIS301C | VB_SIS302B)) {
if(rev >= 0xE0) {
flag = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x39);
if(flag == 0xff) SiS_Pr->SiS_VBType = VB_SIS302LV;
else SiS_Pr->SiS_VBType = VB_SIS301C; /* VB_SIS302ELV; */
} else if(rev >= 0xD0) {
SiS_Pr->SiS_VBType = VB_SIS301LV;
}
}
if(SiS_Pr->SiS_VBType & (VB_SIS301C | VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV)) {
p4_0f = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x0f);
p4_25 = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x25);
p4_27 = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x27);
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x0f,0x7f);
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x25,0x08);
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x27,0xfd);
if(SiS_GetReg(SiS_Pr->SiS_Part4Port,0x26) & 0x08) {
SiS_Pr->SiS_VBType |= VB_UMC;
}
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x27,p4_27);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x25,p4_25);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0f,p4_0f);
}
}
/*********************************************/
/* HELPER: Check RAM size */
/*********************************************/
static bool
SiS_CheckMemorySize(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex)
{
unsigned short AdapterMemSize = SiS_Pr->VideoMemorySize / (1024*1024);
unsigned short modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
unsigned short memorysize = ((modeflag & MemoryInfoFlag) >> MemorySizeShift) + 1;
if(!AdapterMemSize) return true;
if(AdapterMemSize < memorysize) return false;
return true;
}
/*********************************************/
/* HELPER: Get DRAM type */
/*********************************************/
#ifdef CONFIG_FB_SIS_315
static unsigned char
SiS_Get310DRAMType(struct SiS_Private *SiS_Pr)
{
unsigned char data;
if((*SiS_Pr->pSiS_SoftSetting) & SoftDRAMType) {
data = (*SiS_Pr->pSiS_SoftSetting) & 0x03;
} else {
if(SiS_Pr->ChipType >= XGI_20) {
/* Do I need this? SR17 seems to be zero anyway... */
data = 0;
} else if(SiS_Pr->ChipType >= SIS_340) {
/* TODO */
data = 0;
} else if(SiS_Pr->ChipType >= SIS_661) {
if(SiS_Pr->SiS_ROMNew) {
data = ((SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0xc0) >> 6);
} else {
data = SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0x07;
}
} else if(IS_SIS550650740) {
data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x13) & 0x07;
} else { /* 315, 330 */
data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x3a) & 0x03;
if(SiS_Pr->ChipType == SIS_330) {
if(data > 1) {
switch(SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0x30) {
case 0x00: data = 1; break;
case 0x10: data = 3; break;
case 0x20: data = 3; break;
case 0x30: data = 2; break;
}
} else {
data = 0;
}
}
}
}
return data;
}
static unsigned short
SiS_GetMCLK(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index;
index = SiS_Get310DRAMType(SiS_Pr);
if(SiS_Pr->ChipType >= SIS_661) {
if(SiS_Pr->SiS_ROMNew) {
return((unsigned short)(SISGETROMW((0x90 + (index * 5) + 3))));
}
return(SiS_Pr->SiS_MCLKData_0[index].CLOCK);
} else if(index >= 4) {
return(SiS_Pr->SiS_MCLKData_1[index - 4].CLOCK);
} else {
return(SiS_Pr->SiS_MCLKData_0[index].CLOCK);
}
}
#endif
/*********************************************/
/* HELPER: ClearBuffer */
/*********************************************/
static void
SiS_ClearBuffer(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
unsigned char SISIOMEMTYPE *memaddr = SiS_Pr->VideoMemoryAddress;
unsigned int memsize = SiS_Pr->VideoMemorySize;
unsigned short SISIOMEMTYPE *pBuffer;
int i;
if(!memaddr || !memsize) return;
if(SiS_Pr->SiS_ModeType >= ModeEGA) {
if(ModeNo > 0x13) {
memset_io(memaddr, 0, memsize);
} else {
pBuffer = (unsigned short SISIOMEMTYPE *)memaddr;
for(i = 0; i < 0x4000; i++) writew(0x0000, &pBuffer[i]);
}
} else if(SiS_Pr->SiS_ModeType < ModeCGA) {
pBuffer = (unsigned short SISIOMEMTYPE *)memaddr;
for(i = 0; i < 0x4000; i++) writew(0x0720, &pBuffer[i]);
} else {
memset_io(memaddr, 0, 0x8000);
}
}
/*********************************************/
/* HELPER: SearchModeID */
/*********************************************/
bool
SiS_SearchModeID(struct SiS_Private *SiS_Pr, unsigned short *ModeNo,
unsigned short *ModeIdIndex)
{
unsigned char VGAINFO = SiS_Pr->SiS_VGAINFO;
if((*ModeNo) <= 0x13) {
if((*ModeNo) <= 0x05) (*ModeNo) |= 0x01;
for((*ModeIdIndex) = 0; ;(*ModeIdIndex)++) {
if(SiS_Pr->SiS_SModeIDTable[(*ModeIdIndex)].St_ModeID == (*ModeNo)) break;
if(SiS_Pr->SiS_SModeIDTable[(*ModeIdIndex)].St_ModeID == 0xFF) return false;
}
if((*ModeNo) == 0x07) {
if(VGAINFO & 0x10) (*ModeIdIndex)++; /* 400 lines */
/* else 350 lines */
}
if((*ModeNo) <= 0x03) {
if(!(VGAINFO & 0x80)) (*ModeIdIndex)++;
if(VGAINFO & 0x10) (*ModeIdIndex)++; /* 400 lines */
/* else 350 lines */
}
/* else 200 lines */
} else {
for((*ModeIdIndex) = 0; ;(*ModeIdIndex)++) {
if(SiS_Pr->SiS_EModeIDTable[(*ModeIdIndex)].Ext_ModeID == (*ModeNo)) break;
if(SiS_Pr->SiS_EModeIDTable[(*ModeIdIndex)].Ext_ModeID == 0xFF) return false;
}
}
return true;
}
/*********************************************/
/* HELPER: GetModePtr */
/*********************************************/
unsigned short
SiS_GetModePtr(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short index;
if(ModeNo <= 0x13) {
index = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_StTableIndex;
} else {
if(SiS_Pr->SiS_ModeType <= ModeEGA) index = 0x1B;
else index = 0x0F;
}
return index;
}
/*********************************************/
/* HELPERS: Get some indices */
/*********************************************/
unsigned short
SiS_GetRefCRTVCLK(struct SiS_Private *SiS_Pr, unsigned short Index, int UseWide)
{
if(SiS_Pr->SiS_RefIndex[Index].Ext_InfoFlag & HaveWideTiming) {
if(UseWide == 1) {
return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK_WIDE;
} else {
return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK_NORM;
}
} else {
return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK;
}
}
unsigned short
SiS_GetRefCRT1CRTC(struct SiS_Private *SiS_Pr, unsigned short Index, int UseWide)
{
if(SiS_Pr->SiS_RefIndex[Index].Ext_InfoFlag & HaveWideTiming) {
if(UseWide == 1) {
return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC_WIDE;
} else {
return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC_NORM;
}
} else {
return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC;
}
}
/*********************************************/
/* HELPER: LowModeTests */
/*********************************************/
static bool
SiS_DoLowModeTest(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
unsigned short temp, temp1, temp2;
if((ModeNo != 0x03) && (ModeNo != 0x10) && (ModeNo != 0x12))
return true;
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x11);
SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x11,0x80);
temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x00);
SiS_SetReg(SiS_Pr->SiS_P3d4,0x00,0x55);
temp2 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x00);
SiS_SetReg(SiS_Pr->SiS_P3d4,0x00,temp1);
SiS_SetReg(SiS_Pr->SiS_P3d4,0x11,temp);
if((SiS_Pr->ChipType >= SIS_315H) ||
(SiS_Pr->ChipType == SIS_300)) {
if(temp2 == 0x55) return false;
else return true;
} else {
if(temp2 != 0x55) return true;
else {
SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x35,0x01);
return false;
}
}
}
static void
SiS_SetLowModeTest(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
if(SiS_DoLowModeTest(SiS_Pr, ModeNo)) {
SiS_Pr->SiS_SetFlag |= LowModeTests;
}
}
/*********************************************/
/* HELPER: OPEN/CLOSE CRT1 CRTC */
/*********************************************/
static void
SiS_OpenCRTC(struct SiS_Private *SiS_Pr)
{
if(IS_SIS650) {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x51,0x1f);
if(IS_SIS651) SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x51,0x20);
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x56,0xe7);
} else if(IS_SIS661741660760) {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x61,0xf7);
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x51,0x1f);
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x56,0xe7);
if(!SiS_Pr->SiS_ROMNew) {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x3a,0xef);
}
}
}
static void
SiS_CloseCRTC(struct SiS_Private *SiS_Pr)
{
#if 0 /* This locks some CRTC registers. We don't want that. */
unsigned short temp1 = 0, temp2 = 0;
if(IS_SIS661741660760) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
temp1 = 0xa0; temp2 = 0x08;
}
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x51,0x1f,temp1);
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x56,0xe7,temp2);
}
#endif
}
static void
SiS_HandleCRT1(struct SiS_Private *SiS_Pr)
{
/* Enable CRT1 gating */
SiS_SetRegAND(SiS_Pr->SiS_P3d4,SiS_Pr->SiS_MyCR63,0xbf);
#if 0
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x15) & 0x01)) {
if((SiS_GetReg(SiS_Pr->SiS_P3c4,0x15) & 0x0a) ||
(SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) & 0x01)) {
SiS_SetRegOR(SiS_Pr->SiS_P3d4,SiS_Pr->SiS_MyCR63,0x40);
}
}
#endif
}
/*********************************************/
/* HELPER: GetColorDepth */
/*********************************************/
unsigned short
SiS_GetColorDepth(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex)
{
static const unsigned short ColorDepth[6] = { 1, 2, 4, 4, 6, 8 };
unsigned short modeflag;
short index;
/* Do NOT check UseCustomMode, will skrew up FIFO */
if(ModeNo == 0xfe) {
modeflag = SiS_Pr->CModeFlag;
} else if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
index = (modeflag & ModeTypeMask) - ModeEGA;
if(index < 0) index = 0;
return ColorDepth[index];
}
/*********************************************/
/* HELPER: GetOffset */
/*********************************************/
unsigned short
SiS_GetOffset(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, unsigned short RRTI)
{
unsigned short xres, temp, colordepth, infoflag;
if(SiS_Pr->UseCustomMode) {
infoflag = SiS_Pr->CInfoFlag;
xres = SiS_Pr->CHDisplay;
} else {
infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
xres = SiS_Pr->SiS_RefIndex[RRTI].XRes;
}
colordepth = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex);
temp = xres / 16;
if(infoflag & InterlaceMode) temp <<= 1;
temp *= colordepth;
if(xres % 16) temp += (colordepth >> 1);
return temp;
}
/*********************************************/
/* SEQ */
/*********************************************/
static void
SiS_SetSeqRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
{
unsigned char SRdata;
int i;
SiS_SetReg(SiS_Pr->SiS_P3c4,0x00,0x03);
/* or "display off" */
SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[0] | 0x20;
/* determine whether to force x8 dotclock */
if((SiS_Pr->SiS_VBType & VB_SISVB) || (SiS_Pr->SiS_IF_DEF_LVDS)) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) SRdata |= 0x01;
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) SRdata |= 0x01;
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x01,SRdata);
for(i = 2; i <= 4; i++) {
SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[i - 1];
SiS_SetReg(SiS_Pr->SiS_P3c4,i,SRdata);
}
}
/*********************************************/
/* MISC */
/*********************************************/
static void
SiS_SetMiscRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
{
unsigned char Miscdata;
Miscdata = SiS_Pr->SiS_StandTable[StandTableIndex].MISC;
if(SiS_Pr->ChipType < SIS_661) {
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
Miscdata |= 0x0C;
}
}
}
SiS_SetRegByte(SiS_Pr->SiS_P3c2,Miscdata);
}
/*********************************************/
/* CRTC */
/*********************************************/
static void
SiS_SetCRTCRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
{
unsigned char CRTCdata;
unsigned short i;
/* Unlock CRTC */
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
for(i = 0; i <= 0x18; i++) {
CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i];
SiS_SetReg(SiS_Pr->SiS_P3d4,i,CRTCdata);
}
if(SiS_Pr->ChipType >= SIS_661) {
SiS_OpenCRTC(SiS_Pr);
for(i = 0x13; i <= 0x14; i++) {
CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i];
SiS_SetReg(SiS_Pr->SiS_P3d4,i,CRTCdata);
}
} else if( ( (SiS_Pr->ChipType == SIS_630) ||
(SiS_Pr->ChipType == SIS_730) ) &&
(SiS_Pr->ChipRevision >= 0x30) ) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) {
SiS_SetReg(SiS_Pr->SiS_P3d4,0x18,0xFE);
}
}
}
}
/*********************************************/
/* ATT */
/*********************************************/
static void
SiS_SetATTRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
{
unsigned char ARdata;
unsigned short i;
for(i = 0; i <= 0x13; i++) {
ARdata = SiS_Pr->SiS_StandTable[StandTableIndex].ATTR[i];
if(i == 0x13) {
/* Pixel shift. If screen on LCD or TV is shifted left or right,
* this might be the cause.
*/
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) ARdata = 0;
}
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
}
}
}
if(SiS_Pr->ChipType >= SIS_661) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToTV | SetCRT2ToLCD)) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->ChipType >= SIS_315H) {
if(IS_SIS550650740660) {
/* 315, 330 don't do this */
if(SiS_Pr->SiS_VBType & VB_SIS30xB) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
} else {
ARdata = 0;
}
}
} else {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
}
}
}
SiS_GetRegByte(SiS_Pr->SiS_P3da); /* reset 3da */
SiS_SetRegByte(SiS_Pr->SiS_P3c0,i); /* set index */
SiS_SetRegByte(SiS_Pr->SiS_P3c0,ARdata); /* set data */
}
SiS_GetRegByte(SiS_Pr->SiS_P3da); /* reset 3da */
SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x14); /* set index */
SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x00); /* set data */
SiS_GetRegByte(SiS_Pr->SiS_P3da);
SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x20); /* Enable Attribute */
SiS_GetRegByte(SiS_Pr->SiS_P3da);
}
/*********************************************/
/* GRC */
/*********************************************/
static void
SiS_SetGRCRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
{
unsigned char GRdata;
unsigned short i;
for(i = 0; i <= 0x08; i++) {
GRdata = SiS_Pr->SiS_StandTable[StandTableIndex].GRC[i];
SiS_SetReg(SiS_Pr->SiS_P3ce,i,GRdata);
}
if(SiS_Pr->SiS_ModeType > ModeVGA) {
/* 256 color disable */
SiS_SetRegAND(SiS_Pr->SiS_P3ce,0x05,0xBF);
}
}
/*********************************************/
/* CLEAR EXTENDED REGISTERS */
/*********************************************/
static void
SiS_ClearExt1Regs(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
unsigned short i;
for(i = 0x0A; i <= 0x0E; i++) {
SiS_SetReg(SiS_Pr->SiS_P3c4,i,0x00);
}
if(SiS_Pr->ChipType >= SIS_315H) {
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x37,0xFE);
if(ModeNo <= 0x13) {
if(ModeNo == 0x06 || ModeNo >= 0x0e) {
SiS_SetReg(SiS_Pr->SiS_P3c4,0x0e,0x20);
}
}
}
}
/*********************************************/
/* RESET VCLK */
/*********************************************/
static void
SiS_ResetCRT1VCLK(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->ChipType < SIS_661) {
if(SiS_Pr->SiS_IF_DEF_LVDS == 0) return;
}
} else {
if((SiS_Pr->SiS_IF_DEF_LVDS == 0) &&
(!(SiS_Pr->SiS_VBType & VB_SIS30xBLV)) ) {
return;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x31,0xcf,0x20);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2B,SiS_Pr->SiS_VCLKData[1].SR2B);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2C,SiS_Pr->SiS_VCLKData[1].SR2C);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x31,0xcf,0x10);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2B,SiS_Pr->SiS_VCLKData[0].SR2B);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2C,SiS_Pr->SiS_VCLKData[0].SR2C);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
}
/*********************************************/
/* SYNC */
/*********************************************/
static void
SiS_SetCRT1Sync(struct SiS_Private *SiS_Pr, unsigned short RRTI)
{
unsigned short sync;
if(SiS_Pr->UseCustomMode) {
sync = SiS_Pr->CInfoFlag >> 8;
} else {
sync = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag >> 8;
}
sync &= 0xC0;
sync |= 0x2f;
SiS_SetRegByte(SiS_Pr->SiS_P3c2,sync);
}
/*********************************************/
/* CRTC/2 */
/*********************************************/
static void
SiS_SetCRT1CRTC(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, unsigned short RRTI)
{
unsigned short temp, i, j, modeflag;
unsigned char *crt1data = NULL;
modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
if(SiS_Pr->UseCustomMode) {
crt1data = &SiS_Pr->CCRT1CRTC[0];
} else {
temp = SiS_GetRefCRT1CRTC(SiS_Pr, RRTI, SiS_Pr->SiS_UseWide);
/* Alternate for 1600x1200 LCDA */
if((temp == 0x20) && (SiS_Pr->Alternate1600x1200)) temp = 0x57;
crt1data = (unsigned char *)&SiS_Pr->SiS_CRT1Table[temp].CR[0];
}
/* unlock cr0-7 */
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
for(i = 0, j = 0; i <= 7; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
}
for(j = 0x10; i <= 10; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
}
for(j = 0x15; i <= 12; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
}
for(j = 0x0A; i <= 15; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_P3c4,j,crt1data[i]);
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x0E,crt1data[16] & 0xE0);
temp = (crt1data[16] & 0x01) << 5;
if(modeflag & DoubleScanMode) temp |= 0x80;
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x09,0x5F,temp);
if(SiS_Pr->SiS_ModeType > ModeVGA) {
SiS_SetReg(SiS_Pr->SiS_P3d4,0x14,0x4F);
}
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType == XGI_20) {
SiS_SetReg(SiS_Pr->SiS_P3d4,0x04,crt1data[4] - 1);
if(!(temp = crt1data[5] & 0x1f)) {
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x0c,0xfb);
}
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x05,0xe0,((temp - 1) & 0x1f));
temp = (crt1data[16] >> 5) + 3;
if(temp > 7) temp -= 7;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0e,0x1f,(temp << 5));
}
#endif
}
/*********************************************/
/* OFFSET & PITCH */
/*********************************************/
/* (partly overruled by SetPitch() in XF86) */
/*********************************************/
static void
SiS_SetCRT1Offset(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, unsigned short RRTI)
{
unsigned short temp, DisplayUnit, infoflag;
if(SiS_Pr->UseCustomMode) {
infoflag = SiS_Pr->CInfoFlag;
} else {
infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
}
DisplayUnit = SiS_GetOffset(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
temp = (DisplayUnit >> 8) & 0x0f;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0E,0xF0,temp);
SiS_SetReg(SiS_Pr->SiS_P3d4,0x13,DisplayUnit & 0xFF);
if(infoflag & InterlaceMode) DisplayUnit >>= 1;
DisplayUnit <<= 5;
temp = (DisplayUnit >> 8) + 1;
if(DisplayUnit & 0xff) temp++;
if(SiS_Pr->ChipType == XGI_20) {
if(ModeNo == 0x4a || ModeNo == 0x49) temp--;
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x10,temp);
}
/*********************************************/
/* VCLK */
/*********************************************/
static void
SiS_SetCRT1VCLK(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, unsigned short RRTI)
{
unsigned short index = 0, clka, clkb;
if(SiS_Pr->UseCustomMode) {
clka = SiS_Pr->CSR2B;
clkb = SiS_Pr->CSR2C;
} else {
index = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
if((SiS_Pr->SiS_VBType & VB_SIS30xBLV) &&
(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
/* Alternate for 1600x1200 LCDA */
if((index == 0x21) && (SiS_Pr->Alternate1600x1200)) index = 0x72;
clka = SiS_Pr->SiS_VBVCLKData[index].Part4_A;
clkb = SiS_Pr->SiS_VBVCLKData[index].Part4_B;
} else {
clka = SiS_Pr->SiS_VCLKData[index].SR2B;
clkb = SiS_Pr->SiS_VCLKData[index].SR2C;
}
}
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x31,0xCF);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,clka);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,clkb);
if(SiS_Pr->ChipType >= SIS_315H) {
#ifdef CONFIG_FB_SIS_315
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x01);
if(SiS_Pr->ChipType == XGI_20) {
unsigned short mf = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
if(mf & HalfDCLK) {
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,SiS_GetReg(SiS_Pr->SiS_P3c4,0x2b));
clkb = SiS_GetReg(SiS_Pr->SiS_P3c4,0x2c);
clkb = (((clkb & 0x1f) << 1) + 1) | (clkb & 0xe0);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,clkb);
}
}
#endif
} else {
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
}
}
/*********************************************/
/* FIFO */
/*********************************************/
#ifdef CONFIG_FB_SIS_300
void
SiS_GetFIFOThresholdIndex300(struct SiS_Private *SiS_Pr, unsigned short *idx1,
unsigned short *idx2)
{
unsigned short temp1, temp2;
static const unsigned char ThTiming[8] = {
1, 2, 2, 3, 0, 1, 1, 2
};
temp1 = temp2 = (SiS_GetReg(SiS_Pr->SiS_P3c4,0x18) & 0x62) >> 1;
(*idx2) = (unsigned short)(ThTiming[((temp2 >> 3) | temp1) & 0x07]);
(*idx1) = (unsigned short)(SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) >> 6) & 0x03;
(*idx1) |= (unsigned short)(((SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) >> 4) & 0x0c));
(*idx1) <<= 1;
}
static unsigned short
SiS_GetFIFOThresholdA300(unsigned short idx1, unsigned short idx2)
{
static const unsigned char ThLowA[8 * 3] = {
61, 3,52, 5,68, 7,100,11,
43, 3,42, 5,54, 7, 78,11,
34, 3,37, 5,47, 7, 67,11
};
return (unsigned short)((ThLowA[idx1 + 1] * idx2) + ThLowA[idx1]);
}
unsigned short
SiS_GetFIFOThresholdB300(unsigned short idx1, unsigned short idx2)
{
static const unsigned char ThLowB[8 * 3] = {
81, 4,72, 6,88, 8,120,12,
55, 4,54, 6,66, 8, 90,12,
42, 4,45, 6,55, 8, 75,12
};
return (unsigned short)((ThLowB[idx1 + 1] * idx2) + ThLowB[idx1]);
}
static unsigned short
SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK,
unsigned short colordepth, unsigned short key)
{
unsigned short idx1, idx2;
unsigned int longtemp = VCLK * colordepth;
SiS_GetFIFOThresholdIndex300(SiS_Pr, &idx1, &idx2);
if(key == 0) {
longtemp *= SiS_GetFIFOThresholdA300(idx1, idx2);
} else {
longtemp *= SiS_GetFIFOThresholdB300(idx1, idx2);
}
idx1 = longtemp % (MCLK * 16);
longtemp /= (MCLK * 16);
if(idx1) longtemp++;
return (unsigned short)longtemp;
}
static unsigned short
SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK,
unsigned short colordepth, unsigned short MCLK)
{
unsigned short temp1, temp2;
temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0);
temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1);
if(temp1 < 4) temp1 = 4;
temp1 -= 4;
if(temp2 < temp1) temp2 = temp1;
return temp2;
}
static void
SiS_SetCRT1FIFO_300(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short RefreshRateTableIndex)
{
unsigned short ThresholdLow = 0;
unsigned short temp, index, VCLK, MCLK, colorth;
static const unsigned short colortharray[6] = { 1, 1, 2, 2, 3, 4 };
if(ModeNo > 0x13) {
/* Get VCLK */
if(SiS_Pr->UseCustomMode) {
VCLK = SiS_Pr->CSRClock;
} else {
index = SiS_GetRefCRTVCLK(SiS_Pr, RefreshRateTableIndex, SiS_Pr->SiS_UseWide);
VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK;
}
/* Get half colordepth */
colorth = colortharray[(SiS_Pr->SiS_ModeType - ModeEGA)];
/* Get MCLK */
index = SiS_GetReg(SiS_Pr->SiS_P3c4,0x3A) & 0x07;
MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK;
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35) & 0xc3;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x16,0x3c,temp);
do {
ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1;
if(ThresholdLow < 0x13) break;
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x16,0xfc);
ThresholdLow = 0x13;
temp = SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) >> 6;
if(!temp) break;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x16,0x3f,((temp - 1) << 6));
} while(0);
} else ThresholdLow = 2;
/* Write CRT/CPU threshold low, CRT/Engine threshold high */
temp = (ThresholdLow << 4) | 0x0f;
SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,temp);
temp = (ThresholdLow & 0x10) << 1;
if(ModeNo > 0x13) temp |= 0x40;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0f,0x9f,temp);
/* What is this? */
SiS_SetReg(SiS_Pr->SiS_P3c4,0x3B,0x09);
/* Write CRT/CPU threshold high */
temp = ThresholdLow + 3;
if(temp > 0x0f) temp = 0x0f;
SiS_SetReg(SiS_Pr->SiS_P3c4,0x09,temp);
}
unsigned short
SiS_GetLatencyFactor630(struct SiS_Private *SiS_Pr, unsigned short index)
{
static const unsigned char LatencyFactor[] = {
97, 88, 86, 79, 77, 0, /* 64 bit BQ=2 */
0, 87, 85, 78, 76, 54, /* 64 bit BQ=1 */
97, 88, 86, 79, 77, 0, /* 128 bit BQ=2 */
0, 79, 77, 70, 68, 48, /* 128 bit BQ=1 */
80, 72, 69, 63, 61, 0, /* 64 bit BQ=2 */
0, 70, 68, 61, 59, 37, /* 64 bit BQ=1 */
86, 77, 75, 68, 66, 0, /* 128 bit BQ=2 */
0, 68, 66, 59, 57, 37 /* 128 bit BQ=1 */
};
static const unsigned char LatencyFactor730[] = {
69, 63, 61,
86, 79, 77,
103, 96, 94,
120,113,111,
137,130,128
};
if(SiS_Pr->ChipType == SIS_730) {
return (unsigned short)LatencyFactor730[index];
} else {
return (unsigned short)LatencyFactor[index];
}
}
static unsigned short
SiS_CalcDelay2(struct SiS_Private *SiS_Pr, unsigned char key)
{
unsigned short index;
if(SiS_Pr->ChipType == SIS_730) {
index = ((key & 0x0f) * 3) + ((key & 0xc0) >> 6);
} else {
index = (key & 0xe0) >> 5;
if(key & 0x10) index += 6;
if(!(key & 0x01)) index += 24;
if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) & 0x80) index += 12;
}
return SiS_GetLatencyFactor630(SiS_Pr, index);
}
static void
SiS_SetCRT1FIFO_630(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short RefreshRateTableIndex)
{
unsigned short ThresholdLow = 0;
unsigned short i, data, VCLK, MCLK16, colorth = 0;
unsigned int templ, datal;
const unsigned char *queuedata = NULL;
static const unsigned char FQBQData[21] = {
0x01,0x21,0x41,0x61,0x81,
0x31,0x51,0x71,0x91,0xb1,
0x00,0x20,0x40,0x60,0x80,
0x30,0x50,0x70,0x90,0xb0,
0xff
};
static const unsigned char FQBQData730[16] = {
0x34,0x74,0xb4,
0x23,0x63,0xa3,
0x12,0x52,0x92,
0x01,0x41,0x81,
0x00,0x40,0x80,
0xff
};
static const unsigned short colortharray[6] = {
1, 1, 2, 2, 3, 4
};
i = 0;
if (SiS_Pr->ChipType == SIS_730)
queuedata = &FQBQData730[0];
else
queuedata = &FQBQData[0];
if(ModeNo > 0x13) {
/* Get VCLK */
if(SiS_Pr->UseCustomMode) {
VCLK = SiS_Pr->CSRClock;
} else {
data = SiS_GetRefCRTVCLK(SiS_Pr, RefreshRateTableIndex, SiS_Pr->SiS_UseWide);
VCLK = SiS_Pr->SiS_VCLKData[data].CLOCK;
}
/* Get MCLK * 16 */
data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x1A) & 0x07;
MCLK16 = SiS_Pr->SiS_MCLKData_0[data].CLOCK * 16;
/* Get half colordepth */
colorth = colortharray[(SiS_Pr->SiS_ModeType - ModeEGA)];
do {
templ = SiS_CalcDelay2(SiS_Pr, queuedata[i]) * VCLK * colorth;
datal = templ % MCLK16;
templ = (templ / MCLK16) + 1;
if(datal) templ++;
if(templ > 0x13) {
if(queuedata[i + 1] == 0xFF) {
ThresholdLow = 0x13;
break;
}
i++;
} else {
ThresholdLow = templ;
break;
}
} while(queuedata[i] != 0xFF);
} else {
if(SiS_Pr->ChipType != SIS_730) i = 9;
ThresholdLow = 0x02;
}
/* Write CRT/CPU threshold low, CRT/Engine threshold high */
data = ((ThresholdLow & 0x0f) << 4) | 0x0f;
SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,data);
data = (ThresholdLow & 0x10) << 1;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xDF,data);
/* What is this? */
SiS_SetReg(SiS_Pr->SiS_P3c4,0x3B,0x09);
/* Write CRT/CPU threshold high (gap = 3) */
data = ThresholdLow + 3;
if(data > 0x0f) data = 0x0f;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x09,0x80,data);
/* Write foreground and background queue */
templ = sisfb_read_nbridge_pci_dword(SiS_Pr, 0x50);
if(SiS_Pr->ChipType == SIS_730) {
templ &= 0xfffff9ff;
templ |= ((queuedata[i] & 0xc0) << 3);
} else {
templ &= 0xf0ffffff;
if( (ModeNo <= 0x13) &&
(SiS_Pr->ChipType == SIS_630) &&
(SiS_Pr->ChipRevision >= 0x30) ) {
templ |= 0x0b000000;
} else {
templ |= ((queuedata[i] & 0xf0) << 20);
}
}
sisfb_write_nbridge_pci_dword(SiS_Pr, 0x50, templ);
templ = sisfb_read_nbridge_pci_dword(SiS_Pr, 0xA0);
/* GUI grant timer (PCI config 0xA3) */
if(SiS_Pr->ChipType == SIS_730) {
templ &= 0x00ffffff;
datal = queuedata[i] << 8;
templ |= (((datal & 0x0f00) | ((datal & 0x3000) >> 8)) << 20);
} else {
templ &= 0xf0ffffff;
templ |= ((queuedata[i] & 0x0f) << 24);
}
sisfb_write_nbridge_pci_dword(SiS_Pr, 0xA0, templ);
}
#endif /* CONFIG_FB_SIS_300 */
#ifdef CONFIG_FB_SIS_315
static void
SiS_SetCRT1FIFO_310(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short modeflag;
/* disable auto-threshold */
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x3D,0xFE);
modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0xAE);
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x09,0xF0);
if(ModeNo > 0x13) {
if(SiS_Pr->ChipType >= XGI_20) {
SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
} else if(SiS_Pr->ChipType >= SIS_661) {
if(!(modeflag & HalfDCLK)) {
SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
}
} else {
if((!(modeflag & DoubleScanMode)) || (!(modeflag & HalfDCLK))) {
SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
}
}
}
}
#endif
/*********************************************/
/* MODE REGISTERS */
/*********************************************/
static void
SiS_SetVCLKState(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short RefreshRateTableIndex, unsigned short ModeIdIndex)
{
unsigned short data = 0, VCLK = 0, index = 0;
if(ModeNo > 0x13) {
if(SiS_Pr->UseCustomMode) {
VCLK = SiS_Pr->CSRClock;
} else {
index = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK;
}
}
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
if(VCLK > 150) data |= 0x80;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0x7B,data);
data = 0x00;
if(VCLK >= 150) data |= 0x08;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xF7,data);
#endif
} else if(SiS_Pr->ChipType < XGI_20) {
#ifdef CONFIG_FB_SIS_315
if(VCLK >= 166) data |= 0x0c;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xf3,data);
if(VCLK >= 166) {
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1f,0xe7);
}
#endif
} else {
#ifdef CONFIG_FB_SIS_315
if(VCLK >= 200) data |= 0x0c;
if(SiS_Pr->ChipType == XGI_20) data &= ~0x04;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xf3,data);
if(SiS_Pr->ChipType != XGI_20) {
data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x1f) & 0xe7;
if(VCLK < 200) data |= 0x10;
SiS_SetReg(SiS_Pr->SiS_P3c4,0x1f,data);
}
#endif
}
/* DAC speed */
if(SiS_Pr->ChipType >= SIS_661) {
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xE8,0x10);
} else {
data = 0x03;
if(VCLK >= 260) data = 0x00;
else if(VCLK >= 160) data = 0x01;
else if(VCLK >= 135) data = 0x02;
if(SiS_Pr->ChipType == SIS_540) {
/* Was == 203 or < 234 which made no sense */
if (VCLK < 234) data = 0x02;
}
if(SiS_Pr->ChipType < SIS_315H) {
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xFC,data);
} else {
if(SiS_Pr->ChipType > SIS_315PRO) {
if(ModeNo > 0x13) data &= 0xfc;
}
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xF8,data);
}
}
}
static void
SiS_SetCRT1ModeRegs(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, unsigned short RRTI)
{
unsigned short data, infoflag = 0, modeflag;
#ifdef CONFIG_FB_SIS_315
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short data2, data3;
#endif
modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
if(SiS_Pr->UseCustomMode) {
infoflag = SiS_Pr->CInfoFlag;
} else {
if(ModeNo > 0x13) {
infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
}
}
/* Disable DPMS */
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1F,0x3F);
data = 0;
if(ModeNo > 0x13) {
if(SiS_Pr->SiS_ModeType > ModeEGA) {
data |= 0x02;
data |= ((SiS_Pr->SiS_ModeType - ModeVGA) << 2);
}
if(infoflag & InterlaceMode) data |= 0x20;
}
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x06,0xC0,data);
if(SiS_Pr->ChipType != SIS_300) {
data = 0;
if(infoflag & InterlaceMode) {
/* data = (Hsync / 8) - ((Htotal / 8) / 2) + 3 */
int hrs = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x04) |
((SiS_GetReg(SiS_Pr->SiS_P3c4,0x0b) & 0xc0) << 2)) - 3;
int hto = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x00) |
((SiS_GetReg(SiS_Pr->SiS_P3c4,0x0b) & 0x03) << 8)) + 5;
data = hrs - (hto >> 1) + 3;
}
SiS_SetReg(SiS_Pr->SiS_P3d4,0x19,data);
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x1a,0xFC,((data >> 8) & 0x03));
}
if(modeflag & HalfDCLK) {
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x01,0x08);
}
data = 0;
if(modeflag & LineCompareOff) data = 0x08;
if(SiS_Pr->ChipType == SIS_300) {
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xF7,data);
} else {
if(SiS_Pr->ChipType >= XGI_20) data |= 0x20;
if(SiS_Pr->SiS_ModeType == ModeEGA) {
if(ModeNo > 0x13) {
data |= 0x40;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xB7,data);
}
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_315H) {
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x31,0xfb);
}
if(SiS_Pr->ChipType == SIS_315PRO) {
data = SiS_Pr->SiS_SR15[(2 * 4) + SiS_Get310DRAMType(SiS_Pr)];
if(SiS_Pr->SiS_ModeType == ModeText) {
data &= 0xc7;
} else {
data2 = SiS_GetOffset(SiS_Pr, ModeNo, ModeIdIndex, RRTI) >> 1;
if(infoflag & InterlaceMode) data2 >>= 1;
data3 = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex) >> 1;
if(data3) data2 /= data3;
if(data2 >= 0x50) {
data &= 0x0f;
data |= 0x50;
}
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x17,data);
} else if((SiS_Pr->ChipType == SIS_330) || (SiS_Pr->SiS_SysFlags & SF_760LFB)) {
data = SiS_Get310DRAMType(SiS_Pr);
if(SiS_Pr->ChipType == SIS_330) {
data = SiS_Pr->SiS_SR15[(2 * 4) + data];
} else {
if(SiS_Pr->SiS_ROMNew) data = ROMAddr[0xf6];
else if(SiS_Pr->SiS_UseROM) data = ROMAddr[0x100 + data];
else data = 0xba;
}
if(SiS_Pr->SiS_ModeType <= ModeEGA) {
data &= 0xc7;
} else {
if(SiS_Pr->UseCustomMode) {
data2 = SiS_Pr->CSRClock;
} else {
data2 = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
data2 = SiS_Pr->SiS_VCLKData[data2].CLOCK;
}
data3 = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex) >> 1;
if(data3) data2 *= data3;
data2 = ((unsigned int)(SiS_GetMCLK(SiS_Pr) * 1024)) / data2;
if(SiS_Pr->ChipType == SIS_330) {
if(SiS_Pr->SiS_ModeType != Mode16Bpp) {
if (data2 >= 0x19c) data = 0xba;
else if(data2 >= 0x140) data = 0x7a;
else if(data2 >= 0x101) data = 0x3a;
else if(data2 >= 0xf5) data = 0x32;
else if(data2 >= 0xe2) data = 0x2a;
else if(data2 >= 0xc4) data = 0x22;
else if(data2 >= 0xac) data = 0x1a;
else if(data2 >= 0x9e) data = 0x12;
else if(data2 >= 0x8e) data = 0x0a;
else data = 0x02;
} else {
if(data2 >= 0x127) data = 0xba;
else data = 0x7a;
}
} else { /* 76x+LFB */
if (data2 >= 0x190) data = 0xba;
else if(data2 >= 0xff) data = 0x7a;
else if(data2 >= 0xd3) data = 0x3a;
else if(data2 >= 0xa9) data = 0x1a;
else if(data2 >= 0x93) data = 0x0a;
else data = 0x02;
}
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x17,data);
}
/* XGI: Nothing. */
/* TODO: Check SiS340 */
#endif
data = 0x60;
if(SiS_Pr->SiS_ModeType != ModeText) {
data ^= 0x60;
if(SiS_Pr->SiS_ModeType != ModeEGA) {
data ^= 0xA0;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x21,0x1F,data);
SiS_SetVCLKState(SiS_Pr, ModeNo, RRTI, ModeIdIndex);
#ifdef CONFIG_FB_SIS_315
if(((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->ChipType < SIS_661)) ||
(SiS_Pr->ChipType == XGI_40)) {
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x2c);
} else {
SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x6c);
}
} else if(SiS_Pr->ChipType == XGI_20) {
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x33);
} else {
SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x73);
}
SiS_SetReg(SiS_Pr->SiS_P3d4,0x51,0x02);
}
#endif
}
#ifdef CONFIG_FB_SIS_315
static void
SiS_SetupDualChip(struct SiS_Private *SiS_Pr)
{
#if 0
/* TODO: Find out about IOAddress2 */
SISIOADDRESS P2_3c2 = SiS_Pr->IOAddress2 + 0x12;
SISIOADDRESS P2_3c4 = SiS_Pr->IOAddress2 + 0x14;
SISIOADDRESS P2_3ce = SiS_Pr->IOAddress2 + 0x1e;
int i;
if((SiS_Pr->ChipRevision != 0) ||
(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x3a) & 0x04)))
return;
for(i = 0; i <= 4; i++) { /* SR00 - SR04 */
SiS_SetReg(P2_3c4,i,SiS_GetReg(SiS_Pr->SiS_P3c4,i));
}
for(i = 0; i <= 8; i++) { /* GR00 - GR08 */
SiS_SetReg(P2_3ce,i,SiS_GetReg(SiS_Pr->SiS_P3ce,i));
}
SiS_SetReg(P2_3c4,0x05,0x86);
SiS_SetReg(P2_3c4,0x06,SiS_GetReg(SiS_Pr->SiS_P3c4,0x06)); /* SR06 */
SiS_SetReg(P2_3c4,0x21,SiS_GetReg(SiS_Pr->SiS_P3c4,0x21)); /* SR21 */
SiS_SetRegByte(P2_3c2,SiS_GetRegByte(SiS_Pr->SiS_P3cc)); /* MISC */
SiS_SetReg(P2_3c4,0x05,0x00);
#endif
}
#endif
/*********************************************/
/* LOAD DAC */
/*********************************************/
static void
SiS_WriteDAC(struct SiS_Private *SiS_Pr, SISIOADDRESS DACData, unsigned short shiftflag,
unsigned short dl, unsigned short ah, unsigned short al, unsigned short dh)
{
unsigned short d1, d2, d3;
switch(dl) {
case 0: d1 = dh; d2 = ah; d3 = al; break;
case 1: d1 = ah; d2 = al; d3 = dh; break;
default: d1 = al; d2 = dh; d3 = ah;
}
SiS_SetRegByte(DACData, (d1 << shiftflag));
SiS_SetRegByte(DACData, (d2 << shiftflag));
SiS_SetRegByte(DACData, (d3 << shiftflag));
}
void
SiS_LoadDAC(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short data, data2, time, i, j, k, m, n, o;
unsigned short si, di, bx, sf;
SISIOADDRESS DACAddr, DACData;
const unsigned char *table = NULL;
data = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex) & DACInfoFlag;
j = time = 64;
if(data == 0x00) table = SiS_MDA_DAC;
else if(data == 0x08) table = SiS_CGA_DAC;
else if(data == 0x10) table = SiS_EGA_DAC;
else if(data == 0x18) {
j = 16;
time = 256;
table = SiS_VGA_DAC;
}
if( ( (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) && /* 301B-DH LCD */
(SiS_Pr->SiS_VBType & VB_NoLCD) ) ||
(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) || /* LCDA */
(!(SiS_Pr->SiS_SetFlag & ProgrammingCRT2)) ) { /* Programming CRT1 */
SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xFF);
DACAddr = SiS_Pr->SiS_P3c8;
DACData = SiS_Pr->SiS_P3c9;
sf = 0;
} else {
DACAddr = SiS_Pr->SiS_Part5Port;
DACData = SiS_Pr->SiS_Part5Port + 1;
sf = 2;
}
SiS_SetRegByte(DACAddr,0x00);
for(i = 0; i < j; i++) {
data = table[i];
for(k = 0; k < 3; k++) {
data2 = 0;
if(data & 0x01) data2 += 0x2A;
if(data & 0x02) data2 += 0x15;
SiS_SetRegByte(DACData, (data2 << sf));
data >>= 2;
}
}
if(time == 256) {
for(i = 16; i < 32; i++) {
data = table[i] << sf;
for(k = 0; k < 3; k++) SiS_SetRegByte(DACData, data);
}
si = 32;
for(m = 0; m < 9; m++) {
di = si;
bx = si + 4;
for(n = 0; n < 3; n++) {
for(o = 0; o < 5; o++) {
SiS_WriteDAC(SiS_Pr, DACData, sf, n, table[di], table[bx], table[si]);
si++;
}
si -= 2;
for(o = 0; o < 3; o++) {
SiS_WriteDAC(SiS_Pr, DACData, sf, n, table[di], table[si], table[bx]);
si--;
}
} /* for n < 3 */
si += 5;
} /* for m < 9 */
}
}
/*********************************************/
/* SET CRT1 REGISTER GROUP */
/*********************************************/
static void
SiS_SetCRT1Group(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short StandTableIndex, RefreshRateTableIndex;
SiS_Pr->SiS_CRT1Mode = ModeNo;
StandTableIndex = SiS_GetModePtr(SiS_Pr, ModeNo, ModeIdIndex);
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
if(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2)) {
SiS_DisableBridge(SiS_Pr);
}
}
SiS_ResetSegmentRegisters(SiS_Pr);
SiS_SetSeqRegs(SiS_Pr, StandTableIndex);
SiS_SetMiscRegs(SiS_Pr, StandTableIndex);
SiS_SetCRTCRegs(SiS_Pr, StandTableIndex);
SiS_SetATTRegs(SiS_Pr, StandTableIndex);
SiS_SetGRCRegs(SiS_Pr, StandTableIndex);
SiS_ClearExt1Regs(SiS_Pr, ModeNo);
SiS_ResetCRT1VCLK(SiS_Pr);
SiS_Pr->SiS_SelectCRT2Rate = 0;
SiS_Pr->SiS_SetFlag &= (~ProgrammingCRT2);
if(SiS_Pr->SiS_VBInfo & SetSimuScanMode) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
}
RefreshRateTableIndex = SiS_GetRatePtr(SiS_Pr, ModeNo, ModeIdIndex);
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
SiS_Pr->SiS_SetFlag &= ~ProgrammingCRT2;
}
if(RefreshRateTableIndex != 0xFFFF) {
SiS_SetCRT1Sync(SiS_Pr, RefreshRateTableIndex);
SiS_SetCRT1CRTC(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
SiS_SetCRT1Offset(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
SiS_SetCRT1VCLK(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
switch(SiS_Pr->ChipType) {
#ifdef CONFIG_FB_SIS_300
case SIS_300:
SiS_SetCRT1FIFO_300(SiS_Pr, ModeNo, RefreshRateTableIndex);
break;
case SIS_540:
case SIS_630:
case SIS_730:
SiS_SetCRT1FIFO_630(SiS_Pr, ModeNo, RefreshRateTableIndex);
break;
#endif
default:
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType == XGI_20) {
unsigned char sr2b = 0, sr2c = 0;
switch(ModeNo) {
case 0x00:
case 0x01: sr2b = 0x4e; sr2c = 0xe9; break;
case 0x04:
case 0x05:
case 0x0d: sr2b = 0x1b; sr2c = 0xe3; break;
}
if(sr2b) {
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,sr2b);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,sr2c);
SiS_SetRegByte(SiS_Pr->SiS_P3c2,(SiS_GetRegByte(SiS_Pr->SiS_P3cc) | 0x0c));
}
}
SiS_SetCRT1FIFO_310(SiS_Pr, ModeNo, ModeIdIndex);
#endif
break;
}
SiS_SetCRT1ModeRegs(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType == XGI_40) {
SiS_SetupDualChip(SiS_Pr);
}
#endif
SiS_LoadDAC(SiS_Pr, ModeNo, ModeIdIndex);
if(SiS_Pr->SiS_flag_clearbuffer) {
SiS_ClearBuffer(SiS_Pr, ModeNo);
}
if(!(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2 | SetCRT2ToLCDA))) {
SiS_WaitRetrace1(SiS_Pr);
SiS_DisplayOn(SiS_Pr);
}
}
/*********************************************/
/* HELPER: VIDEO BRIDGE PROG CLK */
/*********************************************/
static void
SiS_InitVB(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
SiS_Pr->Init_P4_0E = 0;
if(SiS_Pr->SiS_ROMNew) {
SiS_Pr->Init_P4_0E = ROMAddr[0x82];
} else if(SiS_Pr->ChipType >= XGI_40) {
if(SiS_Pr->SiS_XGIROM) {
SiS_Pr->Init_P4_0E = ROMAddr[0x80];
}
}
}
static void
SiS_ResetVB(struct SiS_Private *SiS_Pr)
{
#ifdef CONFIG_FB_SIS_315
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short temp;
/* VB programming clock */
if(SiS_Pr->SiS_UseROM) {
if(SiS_Pr->ChipType < SIS_330) {
temp = ROMAddr[VB310Data_1_2_Offset] | 0x40;
if(SiS_Pr->SiS_ROMNew) temp = ROMAddr[0x80] | 0x40;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
} else if(SiS_Pr->ChipType >= SIS_661 && SiS_Pr->ChipType < XGI_20) {
temp = ROMAddr[0x7e] | 0x40;
if(SiS_Pr->SiS_ROMNew) temp = ROMAddr[0x80] | 0x40;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
}
} else if(SiS_Pr->ChipType >= XGI_40) {
temp = 0x40;
if(SiS_Pr->SiS_XGIROM) temp |= ROMAddr[0x7e];
/* Can we do this on any chipset? */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
}
#endif
}
/*********************************************/
/* HELPER: SET VIDEO/CAPTURE REGISTERS */
/*********************************************/
static void
SiS_StrangeStuff(struct SiS_Private *SiS_Pr)
{
/* SiS65x and XGI set up some sort of "lock mode" for text
* which locks CRT2 in some way to CRT1 timing. Disable
* this here.
*/
#ifdef CONFIG_FB_SIS_315
if((IS_SIS651) || (IS_SISM650) ||
SiS_Pr->ChipType == SIS_340 ||
SiS_Pr->ChipType == XGI_40) {
SiS_SetReg(SiS_Pr->SiS_VidCapt, 0x3f, 0x00); /* Fiddle with capture regs */
SiS_SetReg(SiS_Pr->SiS_VidCapt, 0x00, 0x00);
SiS_SetReg(SiS_Pr->SiS_VidPlay, 0x00, 0x86); /* (BIOS does NOT unlock) */
SiS_SetRegAND(SiS_Pr->SiS_VidPlay, 0x30, 0xfe); /* Fiddle with video regs */
SiS_SetRegAND(SiS_Pr->SiS_VidPlay, 0x3f, 0xef);
}
/* !!! This does not support modes < 0x13 !!! */
#endif
}
/*********************************************/
/* HELPER: SET AGP TIMING FOR SiS760 */
/*********************************************/
static void
SiS_Handle760(struct SiS_Private *SiS_Pr)
{
#ifdef CONFIG_FB_SIS_315
unsigned int somebase;
unsigned char temp1, temp2, temp3;
if( (SiS_Pr->ChipType != SIS_760) ||
((SiS_GetReg(SiS_Pr->SiS_P3d4, 0x5c) & 0xf8) != 0x80) ||
(!(SiS_Pr->SiS_SysFlags & SF_760LFB)) ||
(!(SiS_Pr->SiS_SysFlags & SF_760UMA)) )
return;
somebase = sisfb_read_mio_pci_word(SiS_Pr, 0x74);
somebase &= 0xffff;
if(somebase == 0) return;
temp3 = SiS_GetRegByte((somebase + 0x85)) & 0xb7;
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
temp1 = 0x21;
temp2 = 0x03;
temp3 |= 0x08;
} else {
temp1 = 0x25;
temp2 = 0x0b;
}
sisfb_write_nbridge_pci_byte(SiS_Pr, 0x7e, temp1);
sisfb_write_nbridge_pci_byte(SiS_Pr, 0x8d, temp2);
SiS_SetRegByte((somebase + 0x85), temp3);
#endif
}
/*********************************************/
/* SiSSetMode() */
/*********************************************/
bool
SiSSetMode(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
SISIOADDRESS BaseAddr = SiS_Pr->IOAddress;
unsigned short RealModeNo, ModeIdIndex;
unsigned char backupreg = 0;
unsigned short KeepLockReg;
SiS_Pr->UseCustomMode = false;
SiS_Pr->CRT1UsesCustomMode = false;
SiS_Pr->SiS_flag_clearbuffer = 0;
if(SiS_Pr->UseCustomMode) {
ModeNo = 0xfe;
} else {
if(!(ModeNo & 0x80)) SiS_Pr->SiS_flag_clearbuffer = 1;
ModeNo &= 0x7f;
}
/* Don't use FSTN mode for CRT1 */
RealModeNo = ModeNo;
if(ModeNo == 0x5b) ModeNo = 0x56;
SiSInitPtr(SiS_Pr);
SiSRegInit(SiS_Pr, BaseAddr);
SiS_GetSysFlags(SiS_Pr);
SiS_Pr->SiS_VGAINFO = 0x11;
KeepLockReg = SiS_GetReg(SiS_Pr->SiS_P3c4,0x05);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x05,0x86);
SiSInitPCIetc(SiS_Pr);
SiSSetLVDSetc(SiS_Pr);
SiSDetermineROMUsage(SiS_Pr);
SiS_UnLockCRT2(SiS_Pr);
if(!SiS_Pr->UseCustomMode) {
if(!(SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex))) return false;
} else {
ModeIdIndex = 0;
}
SiS_GetVBType(SiS_Pr);
/* Init/restore some VB registers */
SiS_InitVB(SiS_Pr);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(SiS_Pr->ChipType >= SIS_315H) {
SiS_ResetVB(SiS_Pr);
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x32,0x10);
SiS_SetRegOR(SiS_Pr->SiS_Part2Port,0x00,0x0c);
backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
} else {
backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
}
}
/* Get VB information (connectors, connected devices) */
SiS_GetVBInfo(SiS_Pr, ModeNo, ModeIdIndex, (SiS_Pr->UseCustomMode) ? 0 : 1);
SiS_SetYPbPr(SiS_Pr);
SiS_SetTVMode(SiS_Pr, ModeNo, ModeIdIndex);
SiS_GetLCDResInfo(SiS_Pr, ModeNo, ModeIdIndex);
SiS_SetLowModeTest(SiS_Pr, ModeNo);
/* Check memory size (kernel framebuffer driver only) */
if(!SiS_CheckMemorySize(SiS_Pr, ModeNo, ModeIdIndex)) {
return false;
}
SiS_OpenCRTC(SiS_Pr);
if(SiS_Pr->UseCustomMode) {
SiS_Pr->CRT1UsesCustomMode = true;
SiS_Pr->CSRClock_CRT1 = SiS_Pr->CSRClock;
SiS_Pr->CModeFlag_CRT1 = SiS_Pr->CModeFlag;
} else {
SiS_Pr->CRT1UsesCustomMode = false;
}
/* Set mode on CRT1 */
if( (SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SetCRT2ToLCDA)) ||
(!(SiS_Pr->SiS_VBInfo & SwitchCRT2)) ) {
SiS_SetCRT1Group(SiS_Pr, ModeNo, ModeIdIndex);
}
/* Set mode on CRT2 */
if(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2 | SetCRT2ToLCDA)) {
if( (SiS_Pr->SiS_VBType & VB_SISVB) ||
(SiS_Pr->SiS_IF_DEF_LVDS == 1) ||
(SiS_Pr->SiS_IF_DEF_CH70xx != 0) ||
(SiS_Pr->SiS_IF_DEF_TRUMPION != 0) ) {
SiS_SetCRT2Group(SiS_Pr, RealModeNo);
}
}
SiS_HandleCRT1(SiS_Pr);
SiS_StrangeStuff(SiS_Pr);
SiS_DisplayOn(SiS_Pr);
SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xFF);
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if(!(SiS_IsDualEdge(SiS_Pr))) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xfb);
}
}
}
#endif
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(SiS_Pr->ChipType >= SIS_315H) {
#ifdef CONFIG_FB_SIS_315
if(!SiS_Pr->SiS_ROMNew) {
if(SiS_IsVAMode(SiS_Pr)) {
SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x35,0x01);
} else {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x35,0xFE);
}
}
SiS_SetReg(SiS_Pr->SiS_P3d4,0x38,backupreg);
if((IS_SIS650) && (SiS_GetReg(SiS_Pr->SiS_P3d4,0x30) & 0xfc)) {
if((ModeNo == 0x03) || (ModeNo == 0x10)) {
SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x51,0x80);
SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x56,0x08);
}
}
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x30) & SetCRT2ToLCD) {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x38,0xfc);
}
#endif
} else if((SiS_Pr->ChipType == SIS_630) ||
(SiS_Pr->ChipType == SIS_730)) {
SiS_SetReg(SiS_Pr->SiS_P3d4,0x35,backupreg);
}
}
SiS_CloseCRTC(SiS_Pr);
SiS_Handle760(SiS_Pr);
/* We never lock registers in XF86 */
if(KeepLockReg != 0xA1) SiS_SetReg(SiS_Pr->SiS_P3c4,0x05,0x00);
return true;
}
#ifndef GETBITSTR
#define GENBITSMASK(mask) GENMASK(1?mask,0?mask)
#define GETBITS(var,mask) (((var) & GENBITSMASK(mask)) >> (0?mask))
#define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to))
#endif
void
SiS_CalcCRRegisters(struct SiS_Private *SiS_Pr, int depth)
{
int x = 1; /* Fix sync */
SiS_Pr->CCRT1CRTC[0] = ((SiS_Pr->CHTotal >> 3) - 5) & 0xff; /* CR0 */
SiS_Pr->CCRT1CRTC[1] = (SiS_Pr->CHDisplay >> 3) - 1; /* CR1 */
SiS_Pr->CCRT1CRTC[2] = (SiS_Pr->CHBlankStart >> 3) - 1; /* CR2 */
SiS_Pr->CCRT1CRTC[3] = (((SiS_Pr->CHBlankEnd >> 3) - 1) & 0x1F) | 0x80; /* CR3 */
SiS_Pr->CCRT1CRTC[4] = (SiS_Pr->CHSyncStart >> 3) + 3; /* CR4 */
SiS_Pr->CCRT1CRTC[5] = ((((SiS_Pr->CHBlankEnd >> 3) - 1) & 0x20) << 2) | /* CR5 */
(((SiS_Pr->CHSyncEnd >> 3) + 3) & 0x1F);
SiS_Pr->CCRT1CRTC[6] = (SiS_Pr->CVTotal - 2) & 0xFF; /* CR6 */
SiS_Pr->CCRT1CRTC[7] = (((SiS_Pr->CVTotal - 2) & 0x100) >> 8) /* CR7 */
| (((SiS_Pr->CVDisplay - 1) & 0x100) >> 7)
| (((SiS_Pr->CVSyncStart - x) & 0x100) >> 6)
| (((SiS_Pr->CVBlankStart- 1) & 0x100) >> 5)
| 0x10
| (((SiS_Pr->CVTotal - 2) & 0x200) >> 4)
| (((SiS_Pr->CVDisplay - 1) & 0x200) >> 3)
| (((SiS_Pr->CVSyncStart - x) & 0x200) >> 2);
SiS_Pr->CCRT1CRTC[16] = ((((SiS_Pr->CVBlankStart - 1) & 0x200) >> 4) >> 5); /* CR9 */
if(depth != 8) {
if(SiS_Pr->CHDisplay >= 1600) SiS_Pr->CCRT1CRTC[16] |= 0x60; /* SRE */
else if(SiS_Pr->CHDisplay >= 640) SiS_Pr->CCRT1CRTC[16] |= 0x40;
}
SiS_Pr->CCRT1CRTC[8] = (SiS_Pr->CVSyncStart - x) & 0xFF; /* CR10 */
SiS_Pr->CCRT1CRTC[9] = ((SiS_Pr->CVSyncEnd - x) & 0x0F) | 0x80; /* CR11 */
SiS_Pr->CCRT1CRTC[10] = (SiS_Pr->CVDisplay - 1) & 0xFF; /* CR12 */
SiS_Pr->CCRT1CRTC[11] = (SiS_Pr->CVBlankStart - 1) & 0xFF; /* CR15 */
SiS_Pr->CCRT1CRTC[12] = (SiS_Pr->CVBlankEnd - 1) & 0xFF; /* CR16 */
SiS_Pr->CCRT1CRTC[13] = /* SRA */
GETBITSTR((SiS_Pr->CVTotal -2), 10:10, 0:0) |
GETBITSTR((SiS_Pr->CVDisplay -1), 10:10, 1:1) |
GETBITSTR((SiS_Pr->CVBlankStart-1), 10:10, 2:2) |
GETBITSTR((SiS_Pr->CVSyncStart -x), 10:10, 3:3) |
GETBITSTR((SiS_Pr->CVBlankEnd -1), 8:8, 4:4) |
GETBITSTR((SiS_Pr->CVSyncEnd ), 4:4, 5:5) ;
SiS_Pr->CCRT1CRTC[14] = /* SRB */
GETBITSTR((SiS_Pr->CHTotal >> 3) - 5, 9:8, 1:0) |
GETBITSTR((SiS_Pr->CHDisplay >> 3) - 1, 9:8, 3:2) |
GETBITSTR((SiS_Pr->CHBlankStart >> 3) - 1, 9:8, 5:4) |
GETBITSTR((SiS_Pr->CHSyncStart >> 3) + 3, 9:8, 7:6) ;
SiS_Pr->CCRT1CRTC[15] = /* SRC */
GETBITSTR((SiS_Pr->CHBlankEnd >> 3) - 1, 7:6, 1:0) |
GETBITSTR((SiS_Pr->CHSyncEnd >> 3) + 3, 5:5, 2:2) ;
}
void
SiS_CalcLCDACRT1Timing(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex)
{
unsigned short modeflag, tempax, tempbx = 0, remaining = 0;
unsigned short VGAHDE = SiS_Pr->SiS_VGAHDE;
int i, j;
/* 1:1 data: use data set by setcrt1crtc() */
if(SiS_Pr->SiS_LCDInfo & LCDPass11) return;
modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
if(modeflag & HalfDCLK) VGAHDE >>= 1;
SiS_Pr->CHDisplay = VGAHDE;
SiS_Pr->CHBlankStart = VGAHDE;
SiS_Pr->CVDisplay = SiS_Pr->SiS_VGAVDE;
SiS_Pr->CVBlankStart = SiS_Pr->SiS_VGAVDE;
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
tempbx = SiS_Pr->SiS_VGAHT;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
tempbx = SiS_Pr->PanelHT;
}
if(modeflag & HalfDCLK) tempbx >>= 1;
remaining = tempbx % 8;
#endif
} else {
#ifdef CONFIG_FB_SIS_315
/* OK for LCDA, LVDS */
tempbx = SiS_Pr->PanelHT - SiS_Pr->PanelXRes;
tempax = SiS_Pr->SiS_VGAHDE; /* not /2 ! */
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
tempax = SiS_Pr->PanelXRes;
}
tempbx += tempax;
if(modeflag & HalfDCLK) tempbx -= VGAHDE;
#endif
}
SiS_Pr->CHTotal = SiS_Pr->CHBlankEnd = tempbx;
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->SiS_VGAHDE == SiS_Pr->PanelXRes) {
SiS_Pr->CHSyncStart = SiS_Pr->SiS_VGAHDE + ((SiS_Pr->PanelHRS + 1) & ~1);
SiS_Pr->CHSyncEnd = SiS_Pr->CHSyncStart + SiS_Pr->PanelHRE;
if(modeflag & HalfDCLK) {
SiS_Pr->CHSyncStart >>= 1;
SiS_Pr->CHSyncEnd >>= 1;
}
} else if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
tempax = (SiS_Pr->PanelXRes - SiS_Pr->SiS_VGAHDE) >> 1;
tempbx = (SiS_Pr->PanelHRS + 1) & ~1;
if(modeflag & HalfDCLK) {
tempax >>= 1;
tempbx >>= 1;
}
SiS_Pr->CHSyncStart = (VGAHDE + tempax + tempbx + 7) & ~7;
tempax = SiS_Pr->PanelHRE + 7;
if(modeflag & HalfDCLK) tempax >>= 1;
SiS_Pr->CHSyncEnd = (SiS_Pr->CHSyncStart + tempax) & ~7;
} else {
SiS_Pr->CHSyncStart = SiS_Pr->SiS_VGAHDE;
if(modeflag & HalfDCLK) {
SiS_Pr->CHSyncStart >>= 1;
tempax = ((SiS_Pr->CHTotal - SiS_Pr->CHSyncStart) / 3) << 1;
SiS_Pr->CHSyncEnd = SiS_Pr->CHSyncStart + tempax;
} else {
SiS_Pr->CHSyncEnd = (SiS_Pr->CHSyncStart + (SiS_Pr->CHTotal / 10) + 7) & ~7;
SiS_Pr->CHSyncStart += 8;
}
}
#endif
} else {
#ifdef CONFIG_FB_SIS_315
tempax = VGAHDE;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
tempbx = SiS_Pr->PanelXRes;
if(modeflag & HalfDCLK) tempbx >>= 1;
tempax += ((tempbx - tempax) >> 1);
}
tempax += SiS_Pr->PanelHRS;
SiS_Pr->CHSyncStart = tempax;
tempax += SiS_Pr->PanelHRE;
SiS_Pr->CHSyncEnd = tempax;
#endif
}
tempbx = SiS_Pr->PanelVT - SiS_Pr->PanelYRes;
tempax = SiS_Pr->SiS_VGAVDE;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
tempax = SiS_Pr->PanelYRes;
} else if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
/* Stupid hack for 640x400/320x200 */
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if((tempax + tempbx) == 438) tempbx += 16;
} else if((SiS_Pr->SiS_LCDResInfo == Panel_800x600) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1024x600)) {
tempax = 0;
tempbx = SiS_Pr->SiS_VGAVT;
}
#endif
}
SiS_Pr->CVTotal = SiS_Pr->CVBlankEnd = tempbx + tempax;
tempax = SiS_Pr->SiS_VGAVDE;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
tempax += (SiS_Pr->PanelYRes - tempax) >> 1;
}
tempax += SiS_Pr->PanelVRS;
SiS_Pr->CVSyncStart = tempax;
tempax += SiS_Pr->PanelVRE;
SiS_Pr->CVSyncEnd = tempax;
if(SiS_Pr->ChipType < SIS_315H) {
SiS_Pr->CVSyncStart--;
SiS_Pr->CVSyncEnd--;
}
SiS_CalcCRRegisters(SiS_Pr, 8);
SiS_Pr->CCRT1CRTC[15] &= ~0xF8;
SiS_Pr->CCRT1CRTC[15] |= (remaining << 4);
SiS_Pr->CCRT1CRTC[16] &= ~0xE0;
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
for(i = 0, j = 0; i <= 7; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
}
for(j = 0x10; i <= 10; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
}
for(j = 0x15; i <= 12; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
}
for(j = 0x0A; i <= 15; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_P3c4,j,SiS_Pr->CCRT1CRTC[i]);
}
tempax = SiS_Pr->CCRT1CRTC[16] & 0xE0;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0E,0x1F,tempax);
tempax = (SiS_Pr->CCRT1CRTC[16] & 0x01) << 5;
if(modeflag & DoubleScanMode) tempax |= 0x80;
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x09,0x5F,tempax);
}
void
SiS_Generic_ConvertCRData(struct SiS_Private *SiS_Pr, unsigned char *crdata,
int xres, int yres,
struct fb_var_screeninfo *var, bool writeres
)
{
unsigned short HRE, HBE, HRS, HDE;
unsigned short VRE, VBE, VRS, VDE;
unsigned char sr_data, cr_data;
int B, C, D, E, F, temp;
sr_data = crdata[14];
/* Horizontal display enable end */
HDE = crdata[1] | ((unsigned short)(sr_data & 0x0C) << 6);
E = HDE + 1;
/* Horizontal retrace (=sync) start */
HRS = crdata[4] | ((unsigned short)(sr_data & 0xC0) << 2);
F = HRS - E - 3;
sr_data = crdata[15];
cr_data = crdata[5];
/* Horizontal blank end */
HBE = (crdata[3] & 0x1f) |
((unsigned short)(cr_data & 0x80) >> 2) |
((unsigned short)(sr_data & 0x03) << 6);
/* Horizontal retrace (=sync) end */
HRE = (cr_data & 0x1f) | ((sr_data & 0x04) << 3);
temp = HBE - ((E - 1) & 255);
B = (temp > 0) ? temp : (temp + 256);
temp = HRE - ((E + F + 3) & 63);
C = (temp > 0) ? temp : (temp + 64);
D = B - F - C;
if(writeres) var->xres = xres = E * 8;
var->left_margin = D * 8;
var->right_margin = F * 8;
var->hsync_len = C * 8;
/* Vertical */
sr_data = crdata[13];
cr_data = crdata[7];
/* Vertical display enable end */
VDE = crdata[10] |
((unsigned short)(cr_data & 0x02) << 7) |
((unsigned short)(cr_data & 0x40) << 3) |
((unsigned short)(sr_data & 0x02) << 9);
E = VDE + 1;
/* Vertical retrace (=sync) start */
VRS = crdata[8] |
((unsigned short)(cr_data & 0x04) << 6) |
((unsigned short)(cr_data & 0x80) << 2) |
((unsigned short)(sr_data & 0x08) << 7);
F = VRS + 1 - E;
/* Vertical blank end */
VBE = crdata[12] | ((unsigned short)(sr_data & 0x10) << 4);
temp = VBE - ((E - 1) & 511);
B = (temp > 0) ? temp : (temp + 512);
/* Vertical retrace (=sync) end */
VRE = (crdata[9] & 0x0f) | ((sr_data & 0x20) >> 1);
temp = VRE - ((E + F - 1) & 31);
C = (temp > 0) ? temp : (temp + 32);
D = B - F - C;
if(writeres) var->yres = yres = E;
var->upper_margin = D;
var->lower_margin = F;
var->vsync_len = C;
if((xres == 320) && ((yres == 200) || (yres == 240))) {
/* Terrible hack, but correct CRTC data for
* these modes only produces a black screen...
* (HRE is 0, leading into a too large C and
* a negative D. The CRT controller does not
* seem to like correcting HRE to 50)
*/
var->left_margin = (400 - 376);
var->right_margin = (328 - 320);
var->hsync_len = (376 - 328);
}
}
| linux-master | drivers/video/fbdev/sis/init.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SiS 300/540/630[S]/730[S]
* SiS 315[E|PRO]/550/[M]65x/[M]66x[F|M|G]X/[M]74x[GX]/330/[M]76x[GX]
* XGI V3XT/V5/V8, Z7
* frame buffer driver for Linux kernels >= 2.4.14 and >=2.6.3
*
* Linux kernel specific extensions to init.c/init301.c
*
* Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
*
* Author: Thomas Winischhofer <[email protected]>
*/
#include "initdef.h"
#include "vgatypes.h"
#include "vstruct.h"
#include <linux/types.h>
#include <linux/fb.h>
int sisfb_mode_rate_to_dclock(struct SiS_Private *SiS_Pr,
unsigned char modeno, unsigned char rateindex);
int sisfb_mode_rate_to_ddata(struct SiS_Private *SiS_Pr, unsigned char modeno,
unsigned char rateindex, struct fb_var_screeninfo *var);
bool sisfb_gettotalfrommode(struct SiS_Private *SiS_Pr, unsigned char modeno,
int *htotal, int *vtotal, unsigned char rateindex);
extern bool SiSInitPtr(struct SiS_Private *SiS_Pr);
extern bool SiS_SearchModeID(struct SiS_Private *SiS_Pr, unsigned short *ModeNo,
unsigned short *ModeIdIndex);
extern void SiS_Generic_ConvertCRData(struct SiS_Private *SiS_Pr, unsigned char *crdata,
int xres, int yres, struct fb_var_screeninfo *var, bool writeres);
int
sisfb_mode_rate_to_dclock(struct SiS_Private *SiS_Pr, unsigned char modeno,
unsigned char rateindex)
{
unsigned short ModeNo = modeno;
unsigned short ModeIdIndex = 0, ClockIndex = 0;
unsigned short RRTI = 0;
int Clock;
if(!SiSInitPtr(SiS_Pr)) return 65000;
if(rateindex > 0) rateindex--;
#ifdef CONFIG_FB_SIS_315
switch(ModeNo) {
case 0x5a: ModeNo = 0x50; break;
case 0x5b: ModeNo = 0x56;
}
#endif
if(!(SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex))) {
printk(KERN_ERR "Could not find mode %x\n", ModeNo);
return 65000;
}
RRTI = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].REFindex;
if(SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag & HaveWideTiming) {
if(SiS_Pr->SiS_UseWide == 1) {
/* Wide screen: Ignore rateindex */
ClockIndex = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRTVCLK_WIDE;
} else {
RRTI += rateindex;
ClockIndex = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRTVCLK_NORM;
}
} else {
RRTI += rateindex;
ClockIndex = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRTVCLK;
}
Clock = SiS_Pr->SiS_VCLKData[ClockIndex].CLOCK * 1000;
return Clock;
}
int
sisfb_mode_rate_to_ddata(struct SiS_Private *SiS_Pr, unsigned char modeno,
unsigned char rateindex, struct fb_var_screeninfo *var)
{
unsigned short ModeNo = modeno;
unsigned short ModeIdIndex = 0, index = 0, RRTI = 0;
int j;
if(!SiSInitPtr(SiS_Pr)) return 0;
if(rateindex > 0) rateindex--;
#ifdef CONFIG_FB_SIS_315
switch(ModeNo) {
case 0x5a: ModeNo = 0x50; break;
case 0x5b: ModeNo = 0x56;
}
#endif
if(!(SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex))) return 0;
RRTI = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].REFindex;
if(SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag & HaveWideTiming) {
if(SiS_Pr->SiS_UseWide == 1) {
/* Wide screen: Ignore rateindex */
index = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRT1CRTC_WIDE;
} else {
RRTI += rateindex;
index = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRT1CRTC_NORM;
}
} else {
RRTI += rateindex;
index = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRT1CRTC;
}
SiS_Generic_ConvertCRData(SiS_Pr,
(unsigned char *)&SiS_Pr->SiS_CRT1Table[index].CR[0],
SiS_Pr->SiS_RefIndex[RRTI].XRes,
SiS_Pr->SiS_RefIndex[RRTI].YRes,
var, false);
if(SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag & 0x8000)
var->sync &= ~FB_SYNC_VERT_HIGH_ACT;
else
var->sync |= FB_SYNC_VERT_HIGH_ACT;
if(SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag & 0x4000)
var->sync &= ~FB_SYNC_HOR_HIGH_ACT;
else
var->sync |= FB_SYNC_HOR_HIGH_ACT;
var->vmode = FB_VMODE_NONINTERLACED;
if(SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag & 0x0080)
var->vmode = FB_VMODE_INTERLACED;
else {
j = 0;
while(SiS_Pr->SiS_EModeIDTable[j].Ext_ModeID != 0xff) {
if(SiS_Pr->SiS_EModeIDTable[j].Ext_ModeID ==
SiS_Pr->SiS_RefIndex[RRTI].ModeID) {
if(SiS_Pr->SiS_EModeIDTable[j].Ext_ModeFlag & DoubleScanMode) {
var->vmode = FB_VMODE_DOUBLE;
}
break;
}
j++;
}
}
if((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
#if 0 /* Do this? */
var->upper_margin <<= 1;
var->lower_margin <<= 1;
var->vsync_len <<= 1;
#endif
} else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
var->upper_margin >>= 1;
var->lower_margin >>= 1;
var->vsync_len >>= 1;
}
return 1;
}
bool
sisfb_gettotalfrommode(struct SiS_Private *SiS_Pr, unsigned char modeno, int *htotal,
int *vtotal, unsigned char rateindex)
{
unsigned short ModeNo = modeno;
unsigned short ModeIdIndex = 0, CRT1Index = 0;
unsigned short RRTI = 0;
unsigned char sr_data, cr_data, cr_data2;
if(!SiSInitPtr(SiS_Pr)) return false;
if(rateindex > 0) rateindex--;
#ifdef CONFIG_FB_SIS_315
switch(ModeNo) {
case 0x5a: ModeNo = 0x50; break;
case 0x5b: ModeNo = 0x56;
}
#endif
if(!(SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex))) return false;
RRTI = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].REFindex;
if(SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag & HaveWideTiming) {
if(SiS_Pr->SiS_UseWide == 1) {
/* Wide screen: Ignore rateindex */
CRT1Index = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRT1CRTC_WIDE;
} else {
RRTI += rateindex;
CRT1Index = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRT1CRTC_NORM;
}
} else {
RRTI += rateindex;
CRT1Index = SiS_Pr->SiS_RefIndex[RRTI].Ext_CRT1CRTC;
}
sr_data = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[14];
cr_data = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[0];
*htotal = (((cr_data & 0xff) | ((unsigned short) (sr_data & 0x03) << 8)) + 5) * 8;
sr_data = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[13];
cr_data = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[6];
cr_data2 = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[7];
*vtotal = ((cr_data & 0xFF) |
((unsigned short)(cr_data2 & 0x01) << 8) |
((unsigned short)(cr_data2 & 0x20) << 4) |
((unsigned short)(sr_data & 0x01) << 10)) + 2;
if(SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag & InterlaceMode)
*vtotal *= 2;
return true;
}
| linux-master | drivers/video/fbdev/sis/initextlfb.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SiS 300/540/630[S]/730[S],
* SiS 315[E|PRO]/550/[M]650/651/[M]661[F|M]X/740/[M]741[GX]/330/[M]760[GX],
* XGI V3XT/V5/V8, Z7
* frame buffer driver for Linux kernels >= 2.4.14 and >=2.6.3
*
* 2D acceleration part
*
* Based on the XFree86/X.org driver which is
* Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
*
* Author: Thomas Winischhofer <[email protected]>
* (see http://www.winischhofer.net/
* for more information and updates)
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/types.h>
#include <asm/io.h>
#include "sis.h"
#include "sis_accel.h"
static const u8 sisALUConv[] =
{
0x00, /* dest = 0; 0, GXclear, 0 */
0x88, /* dest &= src; DSa, GXand, 0x1 */
0x44, /* dest = src & ~dest; SDna, GXandReverse, 0x2 */
0xCC, /* dest = src; S, GXcopy, 0x3 */
0x22, /* dest &= ~src; DSna, GXandInverted, 0x4 */
0xAA, /* dest = dest; D, GXnoop, 0x5 */
0x66, /* dest = ^src; DSx, GXxor, 0x6 */
0xEE, /* dest |= src; DSo, GXor, 0x7 */
0x11, /* dest = ~src & ~dest; DSon, GXnor, 0x8 */
0x99, /* dest ^= ~src ; DSxn, GXequiv, 0x9 */
0x55, /* dest = ~dest; Dn, GXInvert, 0xA */
0xDD, /* dest = src|~dest ; SDno, GXorReverse, 0xB */
0x33, /* dest = ~src; Sn, GXcopyInverted, 0xC */
0xBB, /* dest |= ~src; DSno, GXorInverted, 0xD */
0x77, /* dest = ~src|~dest; DSan, GXnand, 0xE */
0xFF, /* dest = 0xFF; 1, GXset, 0xF */
};
/* same ROP but with Pattern as Source */
static const u8 sisPatALUConv[] =
{
0x00, /* dest = 0; 0, GXclear, 0 */
0xA0, /* dest &= src; DPa, GXand, 0x1 */
0x50, /* dest = src & ~dest; PDna, GXandReverse, 0x2 */
0xF0, /* dest = src; P, GXcopy, 0x3 */
0x0A, /* dest &= ~src; DPna, GXandInverted, 0x4 */
0xAA, /* dest = dest; D, GXnoop, 0x5 */
0x5A, /* dest = ^src; DPx, GXxor, 0x6 */
0xFA, /* dest |= src; DPo, GXor, 0x7 */
0x05, /* dest = ~src & ~dest; DPon, GXnor, 0x8 */
0xA5, /* dest ^= ~src ; DPxn, GXequiv, 0x9 */
0x55, /* dest = ~dest; Dn, GXInvert, 0xA */
0xF5, /* dest = src|~dest ; PDno, GXorReverse, 0xB */
0x0F, /* dest = ~src; Pn, GXcopyInverted, 0xC */
0xAF, /* dest |= ~src; DPno, GXorInverted, 0xD */
0x5F, /* dest = ~src|~dest; DPan, GXnand, 0xE */
0xFF, /* dest = 0xFF; 1, GXset, 0xF */
};
static const int myrops[] = {
3, 10, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3
};
/* 300 series ----------------------------------------------------- */
#ifdef CONFIG_FB_SIS_300
static void
SiS300Sync(struct sis_video_info *ivideo)
{
SiS300Idle
}
static void
SiS300SetupForScreenToScreenCopy(struct sis_video_info *ivideo, int xdir, int ydir,
int rop, int trans_color)
{
SiS300SetupDSTColorDepth(ivideo->DstColor);
SiS300SetupSRCPitch(ivideo->video_linelength)
SiS300SetupDSTRect(ivideo->video_linelength, 0xffff)
if(trans_color != -1) {
SiS300SetupROP(0x0A)
SiS300SetupSRCTrans(trans_color)
SiS300SetupCMDFlag(TRANSPARENT_BITBLT)
} else {
SiS300SetupROP(sisALUConv[rop])
}
if(xdir > 0) {
SiS300SetupCMDFlag(X_INC)
}
if(ydir > 0) {
SiS300SetupCMDFlag(Y_INC)
}
}
static void
SiS300SubsequentScreenToScreenCopy(struct sis_video_info *ivideo, int src_x,
int src_y, int dst_x, int dst_y, int width, int height)
{
u32 srcbase = 0, dstbase = 0;
if(src_y >= 2048) {
srcbase = ivideo->video_linelength * src_y;
src_y = 0;
}
if(dst_y >= 2048) {
dstbase = ivideo->video_linelength * dst_y;
dst_y = 0;
}
SiS300SetupSRCBase(srcbase);
SiS300SetupDSTBase(dstbase);
if(!(ivideo->CommandReg & X_INC)) {
src_x += width-1;
dst_x += width-1;
}
if(!(ivideo->CommandReg & Y_INC)) {
src_y += height-1;
dst_y += height-1;
}
SiS300SetupRect(width, height)
SiS300SetupSRCXY(src_x, src_y)
SiS300SetupDSTXY(dst_x, dst_y)
SiS300DoCMD
}
static void
SiS300SetupForSolidFill(struct sis_video_info *ivideo, u32 color, int rop)
{
SiS300SetupPATFG(color)
SiS300SetupDSTRect(ivideo->video_linelength, 0xffff)
SiS300SetupDSTColorDepth(ivideo->DstColor);
SiS300SetupROP(sisPatALUConv[rop])
SiS300SetupCMDFlag(PATFG)
}
static void
SiS300SubsequentSolidFillRect(struct sis_video_info *ivideo, int x, int y, int w, int h)
{
u32 dstbase = 0;
if(y >= 2048) {
dstbase = ivideo->video_linelength * y;
y = 0;
}
SiS300SetupDSTBase(dstbase)
SiS300SetupDSTXY(x,y)
SiS300SetupRect(w,h)
SiS300SetupCMDFlag(X_INC | Y_INC | BITBLT)
SiS300DoCMD
}
#endif
/* 315/330/340 series ---------------------------------------------- */
#ifdef CONFIG_FB_SIS_315
static void
SiS310Sync(struct sis_video_info *ivideo)
{
SiS310Idle
}
static void
SiS310SetupForScreenToScreenCopy(struct sis_video_info *ivideo, int rop, int trans_color)
{
SiS310SetupDSTColorDepth(ivideo->DstColor);
SiS310SetupSRCPitch(ivideo->video_linelength)
SiS310SetupDSTRect(ivideo->video_linelength, 0x0fff)
if(trans_color != -1) {
SiS310SetupROP(0x0A)
SiS310SetupSRCTrans(trans_color)
SiS310SetupCMDFlag(TRANSPARENT_BITBLT)
} else {
SiS310SetupROP(sisALUConv[rop])
/* Set command - not needed, both 0 */
/* SiSSetupCMDFlag(BITBLT | SRCVIDEO) */
}
SiS310SetupCMDFlag(ivideo->SiS310_AccelDepth)
/* The chip is smart enough to know the direction */
}
static void
SiS310SubsequentScreenToScreenCopy(struct sis_video_info *ivideo, int src_x, int src_y,
int dst_x, int dst_y, int width, int height)
{
u32 srcbase = 0, dstbase = 0;
int mymin = min(src_y, dst_y);
int mymax = max(src_y, dst_y);
/* Although the chip knows the direction to use
* if the source and destination areas overlap,
* that logic fails if we fiddle with the bitmap
* addresses. Therefore, we check if the source
* and destination blitting areas overlap and
* adapt the bitmap addresses synchronously
* if the coordinates exceed the valid range.
* The areas do not overlap, we do our
* normal check.
*/
if((mymax - mymin) < height) {
if((src_y >= 2048) || (dst_y >= 2048)) {
srcbase = ivideo->video_linelength * mymin;
dstbase = ivideo->video_linelength * mymin;
src_y -= mymin;
dst_y -= mymin;
}
} else {
if(src_y >= 2048) {
srcbase = ivideo->video_linelength * src_y;
src_y = 0;
}
if(dst_y >= 2048) {
dstbase = ivideo->video_linelength * dst_y;
dst_y = 0;
}
}
srcbase += ivideo->video_offset;
dstbase += ivideo->video_offset;
SiS310SetupSRCBase(srcbase);
SiS310SetupDSTBase(dstbase);
SiS310SetupRect(width, height)
SiS310SetupSRCXY(src_x, src_y)
SiS310SetupDSTXY(dst_x, dst_y)
SiS310DoCMD
}
static void
SiS310SetupForSolidFill(struct sis_video_info *ivideo, u32 color, int rop)
{
SiS310SetupPATFG(color)
SiS310SetupDSTRect(ivideo->video_linelength, 0x0fff)
SiS310SetupDSTColorDepth(ivideo->DstColor);
SiS310SetupROP(sisPatALUConv[rop])
SiS310SetupCMDFlag(PATFG | ivideo->SiS310_AccelDepth)
}
static void
SiS310SubsequentSolidFillRect(struct sis_video_info *ivideo, int x, int y, int w, int h)
{
u32 dstbase = 0;
if(y >= 2048) {
dstbase = ivideo->video_linelength * y;
y = 0;
}
dstbase += ivideo->video_offset;
SiS310SetupDSTBase(dstbase)
SiS310SetupDSTXY(x,y)
SiS310SetupRect(w,h)
SiS310SetupCMDFlag(BITBLT)
SiS310DoCMD
}
#endif
/* --------------------------------------------------------------------- */
/* The exported routines */
int sisfb_initaccel(struct sis_video_info *ivideo)
{
#ifdef SISFB_USE_SPINLOCKS
spin_lock_init(&ivideo->lockaccel);
#endif
return 0;
}
void sisfb_syncaccel(struct sis_video_info *ivideo)
{
if(ivideo->sisvga_engine == SIS_300_VGA) {
#ifdef CONFIG_FB_SIS_300
SiS300Sync(ivideo);
#endif
} else {
#ifdef CONFIG_FB_SIS_315
SiS310Sync(ivideo);
#endif
}
}
int fbcon_sis_sync(struct fb_info *info)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
CRITFLAGS
if((!ivideo->accel) || (!ivideo->engineok))
return 0;
CRITBEGIN
sisfb_syncaccel(ivideo);
CRITEND
return 0;
}
void fbcon_sis_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
u32 col = 0;
u32 vxres = info->var.xres_virtual;
u32 vyres = info->var.yres_virtual;
int width, height;
CRITFLAGS
if(info->state != FBINFO_STATE_RUNNING)
return;
if((!ivideo->accel) || (!ivideo->engineok)) {
cfb_fillrect(info, rect);
return;
}
if(!rect->width || !rect->height || rect->dx >= vxres || rect->dy >= vyres)
return;
/* Clipping */
width = ((rect->dx + rect->width) > vxres) ? (vxres - rect->dx) : rect->width;
height = ((rect->dy + rect->height) > vyres) ? (vyres - rect->dy) : rect->height;
switch(info->var.bits_per_pixel) {
case 8: col = rect->color;
break;
case 16:
case 32: col = ((u32 *)(info->pseudo_palette))[rect->color];
break;
}
if(ivideo->sisvga_engine == SIS_300_VGA) {
#ifdef CONFIG_FB_SIS_300
CRITBEGIN
SiS300SetupForSolidFill(ivideo, col, myrops[rect->rop]);
SiS300SubsequentSolidFillRect(ivideo, rect->dx, rect->dy, width, height);
CRITEND
#endif
} else {
#ifdef CONFIG_FB_SIS_315
CRITBEGIN
SiS310SetupForSolidFill(ivideo, col, myrops[rect->rop]);
SiS310SubsequentSolidFillRect(ivideo, rect->dx, rect->dy, width, height);
CRITEND
#endif
}
sisfb_syncaccel(ivideo);
}
void fbcon_sis_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
u32 vxres = info->var.xres_virtual;
u32 vyres = info->var.yres_virtual;
int width = area->width;
int height = area->height;
CRITFLAGS
if(info->state != FBINFO_STATE_RUNNING)
return;
if((!ivideo->accel) || (!ivideo->engineok)) {
cfb_copyarea(info, area);
return;
}
if(!width || !height ||
area->sx >= vxres || area->sy >= vyres ||
area->dx >= vxres || area->dy >= vyres)
return;
/* Clipping */
if((area->sx + width) > vxres) width = vxres - area->sx;
if((area->dx + width) > vxres) width = vxres - area->dx;
if((area->sy + height) > vyres) height = vyres - area->sy;
if((area->dy + height) > vyres) height = vyres - area->dy;
if(ivideo->sisvga_engine == SIS_300_VGA) {
#ifdef CONFIG_FB_SIS_300
int xdir, ydir;
if(area->sx < area->dx) xdir = 0;
else xdir = 1;
if(area->sy < area->dy) ydir = 0;
else ydir = 1;
CRITBEGIN
SiS300SetupForScreenToScreenCopy(ivideo, xdir, ydir, 3, -1);
SiS300SubsequentScreenToScreenCopy(ivideo, area->sx, area->sy,
area->dx, area->dy, width, height);
CRITEND
#endif
} else {
#ifdef CONFIG_FB_SIS_315
CRITBEGIN
SiS310SetupForScreenToScreenCopy(ivideo, 3, -1);
SiS310SubsequentScreenToScreenCopy(ivideo, area->sx, area->sy,
area->dx, area->dy, width, height);
CRITEND
#endif
}
sisfb_syncaccel(ivideo);
}
| linux-master | drivers/video/fbdev/sis/sis_accel.c |
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* SiS 300/540/630[S]/730[S],
* SiS 315[E|PRO]/550/[M]65x/[M]66x[F|M|G]X/[M]74x[GX]/330/[M]76x[GX],
* XGI V3XT/V5/V8, Z7
* frame buffer driver for Linux kernels >= 2.4.14 and >=2.6.3
*
* Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
*
* Author: Thomas Winischhofer <[email protected]>
*
* Author of (practically wiped) code base:
* SiS (www.sis.com)
* Copyright (C) 1999 Silicon Integrated Systems, Inc.
*
* See http://www.winischhofer.net/ for more information and updates
*
* Originally based on the VBE 2.0 compliant graphic boards framebuffer driver,
* which is (c) 1998 Gerd Knorr <[email protected]>
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/screen_info.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include <linux/selection.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <linux/capability.h>
#include <linux/fs.h>
#include <linux/types.h>
#include <linux/uaccess.h>
#include <asm/io.h>
#include "sis.h"
#include "sis_main.h"
#include "init301.h"
#if !defined(CONFIG_FB_SIS_300) && !defined(CONFIG_FB_SIS_315)
#warning Neither CONFIG_FB_SIS_300 nor CONFIG_FB_SIS_315 is set
#warning sisfb will not work!
#endif
/* ---------------------- Prototypes ------------------------- */
/* Interface used by the world */
#ifndef MODULE
static int sisfb_setup(char *options);
#endif
/* Interface to the low level console driver */
static int sisfb_init(void);
/* fbdev routines */
static int sisfb_get_fix(struct fb_fix_screeninfo *fix, int con,
struct fb_info *info);
static int sisfb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg);
static int sisfb_set_par(struct fb_info *info);
static int sisfb_blank(int blank,
struct fb_info *info);
static void sisfb_handle_command(struct sis_video_info *ivideo,
struct sisfb_cmd *sisfb_command);
static void sisfb_search_mode(char *name, bool quiet);
static int sisfb_validate_mode(struct sis_video_info *ivideo, int modeindex, u32 vbflags);
static u8 sisfb_search_refresh_rate(struct sis_video_info *ivideo, unsigned int rate,
int index);
static int sisfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *fb_info);
static int sisfb_do_set_var(struct fb_var_screeninfo *var, int isactive,
struct fb_info *info);
static void sisfb_pre_setmode(struct sis_video_info *ivideo);
static void sisfb_post_setmode(struct sis_video_info *ivideo);
static bool sisfb_CheckVBRetrace(struct sis_video_info *ivideo);
static bool sisfbcheckvretracecrt2(struct sis_video_info *ivideo);
static bool sisfbcheckvretracecrt1(struct sis_video_info *ivideo);
static bool sisfb_bridgeisslave(struct sis_video_info *ivideo);
static void sisfb_detect_VB_connect(struct sis_video_info *ivideo);
static void sisfb_get_VB_type(struct sis_video_info *ivideo);
static void sisfb_set_TVxposoffset(struct sis_video_info *ivideo, int val);
static void sisfb_set_TVyposoffset(struct sis_video_info *ivideo, int val);
/* Internal heap routines */
static int sisfb_heap_init(struct sis_video_info *ivideo);
static struct SIS_OH * sisfb_poh_new_node(struct SIS_HEAP *memheap);
static struct SIS_OH * sisfb_poh_allocate(struct SIS_HEAP *memheap, u32 size);
static void sisfb_delete_node(struct SIS_OH *poh);
static void sisfb_insert_node(struct SIS_OH *pohList, struct SIS_OH *poh);
static struct SIS_OH * sisfb_poh_free(struct SIS_HEAP *memheap, u32 base);
static void sisfb_free_node(struct SIS_HEAP *memheap, struct SIS_OH *poh);
/* ------------------ Internal helper routines ----------------- */
static void __init
sisfb_setdefaultparms(void)
{
sisfb_off = 0;
sisfb_parm_mem = 0;
sisfb_accel = -1;
sisfb_ypan = -1;
sisfb_max = -1;
sisfb_userom = -1;
sisfb_useoem = -1;
sisfb_mode_idx = -1;
sisfb_parm_rate = -1;
sisfb_crt1off = 0;
sisfb_forcecrt1 = -1;
sisfb_crt2type = -1;
sisfb_crt2flags = 0;
sisfb_pdc = 0xff;
sisfb_pdca = 0xff;
sisfb_scalelcd = -1;
sisfb_specialtiming = CUT_NONE;
sisfb_lvdshl = -1;
sisfb_dstn = 0;
sisfb_fstn = 0;
sisfb_tvplug = -1;
sisfb_tvstd = -1;
sisfb_tvxposoffset = 0;
sisfb_tvyposoffset = 0;
sisfb_nocrt2rate = 0;
#if !defined(__i386__) && !defined(__x86_64__)
sisfb_resetcard = 0;
sisfb_videoram = 0;
#endif
}
/* ------------- Parameter parsing -------------- */
static void sisfb_search_vesamode(unsigned int vesamode, bool quiet)
{
int i = 0, j = 0;
/* We don't know the hardware specs yet and there is no ivideo */
if(vesamode == 0) {
if(!quiet)
printk(KERN_ERR "sisfb: Invalid mode. Using default.\n");
sisfb_mode_idx = DEFAULT_MODE;
return;
}
vesamode &= 0x1dff; /* Clean VESA mode number from other flags */
while(sisbios_mode[i++].mode_no[0] != 0) {
if( (sisbios_mode[i-1].vesa_mode_no_1 == vesamode) ||
(sisbios_mode[i-1].vesa_mode_no_2 == vesamode) ) {
if(sisfb_fstn) {
if(sisbios_mode[i-1].mode_no[1] == 0x50 ||
sisbios_mode[i-1].mode_no[1] == 0x56 ||
sisbios_mode[i-1].mode_no[1] == 0x53)
continue;
} else {
if(sisbios_mode[i-1].mode_no[1] == 0x5a ||
sisbios_mode[i-1].mode_no[1] == 0x5b)
continue;
}
sisfb_mode_idx = i - 1;
j = 1;
break;
}
}
if((!j) && !quiet)
printk(KERN_ERR "sisfb: Invalid VESA mode 0x%x'\n", vesamode);
}
static void sisfb_search_mode(char *name, bool quiet)
{
unsigned int j = 0, xres = 0, yres = 0, depth = 0, rate = 0;
int i = 0;
char strbuf[16], strbuf1[20];
char *nameptr = name;
/* We don't know the hardware specs yet and there is no ivideo */
if(name == NULL) {
if(!quiet)
printk(KERN_ERR "sisfb: Internal error, using default mode.\n");
sisfb_mode_idx = DEFAULT_MODE;
return;
}
if(!strncasecmp(name, sisbios_mode[MODE_INDEX_NONE].name, strlen(name))) {
if(!quiet)
printk(KERN_ERR "sisfb: Mode 'none' not supported anymore. Using default.\n");
sisfb_mode_idx = DEFAULT_MODE;
return;
}
if(strlen(name) <= 19) {
strcpy(strbuf1, name);
for(i = 0; i < strlen(strbuf1); i++) {
if(strbuf1[i] < '0' || strbuf1[i] > '9') strbuf1[i] = ' ';
}
/* This does some fuzzy mode naming detection */
if(sscanf(strbuf1, "%u %u %u %u", &xres, &yres, &depth, &rate) == 4) {
if((rate <= 32) || (depth > 32)) {
swap(rate, depth);
}
sprintf(strbuf, "%ux%ux%u", xres, yres, depth);
nameptr = strbuf;
sisfb_parm_rate = rate;
} else if(sscanf(strbuf1, "%u %u %u", &xres, &yres, &depth) == 3) {
sprintf(strbuf, "%ux%ux%u", xres, yres, depth);
nameptr = strbuf;
} else {
xres = 0;
if((sscanf(strbuf1, "%u %u", &xres, &yres) == 2) && (xres != 0)) {
sprintf(strbuf, "%ux%ux8", xres, yres);
nameptr = strbuf;
} else {
sisfb_search_vesamode(simple_strtoul(name, NULL, 0), quiet);
return;
}
}
}
i = 0; j = 0;
while(sisbios_mode[i].mode_no[0] != 0) {
if(!strncasecmp(nameptr, sisbios_mode[i++].name, strlen(nameptr))) {
if(sisfb_fstn) {
if(sisbios_mode[i-1].mode_no[1] == 0x50 ||
sisbios_mode[i-1].mode_no[1] == 0x56 ||
sisbios_mode[i-1].mode_no[1] == 0x53)
continue;
} else {
if(sisbios_mode[i-1].mode_no[1] == 0x5a ||
sisbios_mode[i-1].mode_no[1] == 0x5b)
continue;
}
sisfb_mode_idx = i - 1;
j = 1;
break;
}
}
if((!j) && !quiet)
printk(KERN_ERR "sisfb: Invalid mode '%s'\n", nameptr);
}
#ifndef MODULE
static void sisfb_get_vga_mode_from_kernel(void)
{
#ifdef CONFIG_X86
char mymode[32];
int mydepth = screen_info.lfb_depth;
if(screen_info.orig_video_isVGA != VIDEO_TYPE_VLFB) return;
if( (screen_info.lfb_width >= 320) && (screen_info.lfb_width <= 2048) &&
(screen_info.lfb_height >= 200) && (screen_info.lfb_height <= 1536) &&
(mydepth >= 8) && (mydepth <= 32) ) {
if(mydepth == 24) mydepth = 32;
sprintf(mymode, "%ux%ux%u", screen_info.lfb_width,
screen_info.lfb_height,
mydepth);
printk(KERN_DEBUG
"sisfb: Using vga mode %s pre-set by kernel as default\n",
mymode);
sisfb_search_mode(mymode, true);
}
#endif
return;
}
#endif
static void __init
sisfb_search_crt2type(const char *name)
{
int i = 0;
/* We don't know the hardware specs yet and there is no ivideo */
if(name == NULL) return;
while(sis_crt2type[i].type_no != -1) {
if(!strncasecmp(name, sis_crt2type[i].name, strlen(sis_crt2type[i].name))) {
sisfb_crt2type = sis_crt2type[i].type_no;
sisfb_tvplug = sis_crt2type[i].tvplug_no;
sisfb_crt2flags = sis_crt2type[i].flags;
break;
}
i++;
}
sisfb_dstn = (sisfb_crt2flags & FL_550_DSTN) ? 1 : 0;
sisfb_fstn = (sisfb_crt2flags & FL_550_FSTN) ? 1 : 0;
if(sisfb_crt2type < 0)
printk(KERN_ERR "sisfb: Invalid CRT2 type: %s\n", name);
}
static void __init
sisfb_search_tvstd(const char *name)
{
int i = 0;
/* We don't know the hardware specs yet and there is no ivideo */
if(name == NULL)
return;
while(sis_tvtype[i].type_no != -1) {
if(!strncasecmp(name, sis_tvtype[i].name, strlen(sis_tvtype[i].name))) {
sisfb_tvstd = sis_tvtype[i].type_no;
break;
}
i++;
}
}
static void __init
sisfb_search_specialtiming(const char *name)
{
int i = 0;
bool found = false;
/* We don't know the hardware specs yet and there is no ivideo */
if(name == NULL)
return;
if(!strncasecmp(name, "none", 4)) {
sisfb_specialtiming = CUT_FORCENONE;
printk(KERN_DEBUG "sisfb: Special timing disabled\n");
} else {
while(mycustomttable[i].chipID != 0) {
if(!strncasecmp(name,mycustomttable[i].optionName,
strlen(mycustomttable[i].optionName))) {
sisfb_specialtiming = mycustomttable[i].SpecialID;
found = true;
printk(KERN_INFO "sisfb: Special timing for %s %s forced (\"%s\")\n",
mycustomttable[i].vendorName,
mycustomttable[i].cardName,
mycustomttable[i].optionName);
break;
}
i++;
}
if(!found) {
printk(KERN_WARNING "sisfb: Invalid SpecialTiming parameter, valid are:");
printk(KERN_WARNING "\t\"none\" (to disable special timings)\n");
i = 0;
while(mycustomttable[i].chipID != 0) {
printk(KERN_WARNING "\t\"%s\" (for %s %s)\n",
mycustomttable[i].optionName,
mycustomttable[i].vendorName,
mycustomttable[i].cardName);
i++;
}
}
}
}
/* ----------- Various detection routines ----------- */
static void sisfb_detect_custom_timing(struct sis_video_info *ivideo)
{
unsigned char *biosver = NULL;
unsigned char *biosdate = NULL;
bool footprint;
u32 chksum = 0;
int i, j;
if(ivideo->SiS_Pr.UseROM) {
biosver = ivideo->SiS_Pr.VirtualRomBase + 0x06;
biosdate = ivideo->SiS_Pr.VirtualRomBase + 0x2c;
for(i = 0; i < 32768; i++)
chksum += ivideo->SiS_Pr.VirtualRomBase[i];
}
i = 0;
do {
if( (mycustomttable[i].chipID == ivideo->chip) &&
((!strlen(mycustomttable[i].biosversion)) ||
(ivideo->SiS_Pr.UseROM &&
(!strncmp(mycustomttable[i].biosversion, biosver,
strlen(mycustomttable[i].biosversion))))) &&
((!strlen(mycustomttable[i].biosdate)) ||
(ivideo->SiS_Pr.UseROM &&
(!strncmp(mycustomttable[i].biosdate, biosdate,
strlen(mycustomttable[i].biosdate))))) &&
((!mycustomttable[i].bioschksum) ||
(ivideo->SiS_Pr.UseROM &&
(mycustomttable[i].bioschksum == chksum))) &&
(mycustomttable[i].pcisubsysvendor == ivideo->subsysvendor) &&
(mycustomttable[i].pcisubsyscard == ivideo->subsysdevice) ) {
footprint = true;
for(j = 0; j < 5; j++) {
if(mycustomttable[i].biosFootprintAddr[j]) {
if(ivideo->SiS_Pr.UseROM) {
if(ivideo->SiS_Pr.VirtualRomBase[mycustomttable[i].biosFootprintAddr[j]] !=
mycustomttable[i].biosFootprintData[j]) {
footprint = false;
}
} else
footprint = false;
}
}
if(footprint) {
ivideo->SiS_Pr.SiS_CustomT = mycustomttable[i].SpecialID;
printk(KERN_DEBUG "sisfb: Identified [%s %s], special timing applies\n",
mycustomttable[i].vendorName,
mycustomttable[i].cardName);
printk(KERN_DEBUG "sisfb: [specialtiming parameter name: %s]\n",
mycustomttable[i].optionName);
break;
}
}
i++;
} while(mycustomttable[i].chipID);
}
static bool sisfb_interpret_edid(struct sisfb_monitor *monitor, u8 *buffer)
{
int i, j, xres, yres, refresh, index;
u32 emodes;
if(buffer[0] != 0x00 || buffer[1] != 0xff ||
buffer[2] != 0xff || buffer[3] != 0xff ||
buffer[4] != 0xff || buffer[5] != 0xff ||
buffer[6] != 0xff || buffer[7] != 0x00) {
printk(KERN_DEBUG "sisfb: Bad EDID header\n");
return false;
}
if(buffer[0x12] != 0x01) {
printk(KERN_INFO "sisfb: EDID version %d not supported\n",
buffer[0x12]);
return false;
}
monitor->feature = buffer[0x18];
if(!(buffer[0x14] & 0x80)) {
if(!(buffer[0x14] & 0x08)) {
printk(KERN_INFO
"sisfb: WARNING: Monitor does not support separate syncs\n");
}
}
if(buffer[0x13] >= 0x01) {
/* EDID V1 rev 1 and 2: Search for monitor descriptor
* to extract ranges
*/
j = 0x36;
for(i=0; i<4; i++) {
if(buffer[j] == 0x00 && buffer[j + 1] == 0x00 &&
buffer[j + 2] == 0x00 && buffer[j + 3] == 0xfd &&
buffer[j + 4] == 0x00) {
monitor->hmin = buffer[j + 7];
monitor->hmax = buffer[j + 8];
monitor->vmin = buffer[j + 5];
monitor->vmax = buffer[j + 6];
monitor->dclockmax = buffer[j + 9] * 10 * 1000;
monitor->datavalid = true;
break;
}
j += 18;
}
}
if(!monitor->datavalid) {
/* Otherwise: Get a range from the list of supported
* Estabished Timings. This is not entirely accurate,
* because fixed frequency monitors are not supported
* that way.
*/
monitor->hmin = 65535; monitor->hmax = 0;
monitor->vmin = 65535; monitor->vmax = 0;
monitor->dclockmax = 0;
emodes = buffer[0x23] | (buffer[0x24] << 8) | (buffer[0x25] << 16);
for(i = 0; i < 13; i++) {
if(emodes & sisfb_ddcsmodes[i].mask) {
if(monitor->hmin > sisfb_ddcsmodes[i].h) monitor->hmin = sisfb_ddcsmodes[i].h;
if(monitor->hmax < sisfb_ddcsmodes[i].h) monitor->hmax = sisfb_ddcsmodes[i].h + 1;
if(monitor->vmin > sisfb_ddcsmodes[i].v) monitor->vmin = sisfb_ddcsmodes[i].v;
if(monitor->vmax < sisfb_ddcsmodes[i].v) monitor->vmax = sisfb_ddcsmodes[i].v;
if(monitor->dclockmax < sisfb_ddcsmodes[i].d) monitor->dclockmax = sisfb_ddcsmodes[i].d;
}
}
index = 0x26;
for(i = 0; i < 8; i++) {
xres = (buffer[index] + 31) * 8;
switch(buffer[index + 1] & 0xc0) {
case 0xc0: yres = (xres * 9) / 16; break;
case 0x80: yres = (xres * 4) / 5; break;
case 0x40: yres = (xres * 3) / 4; break;
default: yres = xres; break;
}
refresh = (buffer[index + 1] & 0x3f) + 60;
if((xres >= 640) && (yres >= 480)) {
for(j = 0; j < 8; j++) {
if((xres == sisfb_ddcfmodes[j].x) &&
(yres == sisfb_ddcfmodes[j].y) &&
(refresh == sisfb_ddcfmodes[j].v)) {
if(monitor->hmin > sisfb_ddcfmodes[j].h) monitor->hmin = sisfb_ddcfmodes[j].h;
if(monitor->hmax < sisfb_ddcfmodes[j].h) monitor->hmax = sisfb_ddcfmodes[j].h + 1;
if(monitor->vmin > sisfb_ddcsmodes[j].v) monitor->vmin = sisfb_ddcsmodes[j].v;
if(monitor->vmax < sisfb_ddcsmodes[j].v) monitor->vmax = sisfb_ddcsmodes[j].v;
if(monitor->dclockmax < sisfb_ddcsmodes[j].d) monitor->dclockmax = sisfb_ddcsmodes[j].d;
}
}
}
index += 2;
}
if((monitor->hmin <= monitor->hmax) && (monitor->vmin <= monitor->vmax)) {
monitor->datavalid = true;
}
}
return monitor->datavalid;
}
static void sisfb_handle_ddc(struct sis_video_info *ivideo,
struct sisfb_monitor *monitor, int crtno)
{
unsigned short temp, i, realcrtno = crtno;
unsigned char buffer[256];
monitor->datavalid = false;
if(crtno) {
if(ivideo->vbflags & CRT2_LCD) realcrtno = 1;
else if(ivideo->vbflags & CRT2_VGA) realcrtno = 2;
else return;
}
if((ivideo->sisfb_crt1off) && (!crtno))
return;
temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags, ivideo->sisvga_engine,
realcrtno, 0, &buffer[0], ivideo->vbflags2);
if((!temp) || (temp == 0xffff)) {
printk(KERN_INFO "sisfb: CRT%d DDC probing failed\n", crtno + 1);
return;
} else {
printk(KERN_INFO "sisfb: CRT%d DDC supported\n", crtno + 1);
printk(KERN_INFO "sisfb: CRT%d DDC level: %s%s%s%s\n",
crtno + 1,
(temp & 0x1a) ? "" : "[none of the supported]",
(temp & 0x02) ? "2 " : "",
(temp & 0x08) ? "D&P" : "",
(temp & 0x10) ? "FPDI-2" : "");
if(temp & 0x02) {
i = 3; /* Number of retrys */
do {
temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags, ivideo->sisvga_engine,
realcrtno, 1, &buffer[0], ivideo->vbflags2);
} while((temp) && i--);
if(!temp) {
if(sisfb_interpret_edid(monitor, &buffer[0])) {
printk(KERN_INFO "sisfb: Monitor range H %d-%dKHz, V %d-%dHz, Max. dotclock %dMHz\n",
monitor->hmin, monitor->hmax, monitor->vmin, monitor->vmax,
monitor->dclockmax / 1000);
} else {
printk(KERN_INFO "sisfb: CRT%d DDC EDID corrupt\n", crtno + 1);
}
} else {
printk(KERN_INFO "sisfb: CRT%d DDC reading failed\n", crtno + 1);
}
} else {
printk(KERN_INFO "sisfb: VESA D&P and FPDI-2 not supported yet\n");
}
}
}
/* -------------- Mode validation --------------- */
static bool
sisfb_verify_rate(struct sis_video_info *ivideo, struct sisfb_monitor *monitor,
int mode_idx, int rate_idx, int rate)
{
int htotal, vtotal;
unsigned int dclock, hsync;
if(!monitor->datavalid)
return true;
if(mode_idx < 0)
return false;
/* Skip for 320x200, 320x240, 640x400 */
switch(sisbios_mode[mode_idx].mode_no[ivideo->mni]) {
case 0x59:
case 0x41:
case 0x4f:
case 0x50:
case 0x56:
case 0x53:
case 0x2f:
case 0x5d:
case 0x5e:
return true;
#ifdef CONFIG_FB_SIS_315
case 0x5a:
case 0x5b:
if(ivideo->sisvga_engine == SIS_315_VGA) return true;
#endif
}
if(rate < (monitor->vmin - 1))
return false;
if(rate > (monitor->vmax + 1))
return false;
if(sisfb_gettotalfrommode(&ivideo->SiS_Pr,
sisbios_mode[mode_idx].mode_no[ivideo->mni],
&htotal, &vtotal, rate_idx)) {
dclock = (htotal * vtotal * rate) / 1000;
if(dclock > (monitor->dclockmax + 1000))
return false;
hsync = dclock / htotal;
if(hsync < (monitor->hmin - 1))
return false;
if(hsync > (monitor->hmax + 1))
return false;
} else {
return false;
}
return true;
}
static int
sisfb_validate_mode(struct sis_video_info *ivideo, int myindex, u32 vbflags)
{
u16 xres=0, yres, myres;
#ifdef CONFIG_FB_SIS_300
if (ivideo->sisvga_engine == SIS_300_VGA) {
if (!(sisbios_mode[myindex].chipset & MD_SIS300))
return -1 ;
}
#endif
#ifdef CONFIG_FB_SIS_315
if (ivideo->sisvga_engine == SIS_315_VGA) {
if (!(sisbios_mode[myindex].chipset & MD_SIS315))
return -1;
}
#endif
myres = sisbios_mode[myindex].yres;
switch (vbflags & VB_DISPTYPE_DISP2) {
case CRT2_LCD:
xres = ivideo->lcdxres; yres = ivideo->lcdyres;
if ((ivideo->SiS_Pr.SiS_CustomT != CUT_PANEL848) &&
(ivideo->SiS_Pr.SiS_CustomT != CUT_PANEL856)) {
if (sisbios_mode[myindex].xres > xres)
return -1;
if (myres > yres)
return -1;
}
if (ivideo->sisfb_fstn) {
if (sisbios_mode[myindex].xres == 320) {
if (myres == 240) {
switch (sisbios_mode[myindex].mode_no[1]) {
case 0x50: myindex = MODE_FSTN_8; break;
case 0x56: myindex = MODE_FSTN_16; break;
case 0x53: return -1;
}
}
}
}
if (SiS_GetModeID_LCD(ivideo->sisvga_engine, vbflags, sisbios_mode[myindex].xres,
sisbios_mode[myindex].yres, 0, ivideo->sisfb_fstn,
ivideo->SiS_Pr.SiS_CustomT, xres, yres, ivideo->vbflags2) < 0x14) {
return -1;
}
break;
case CRT2_TV:
if (SiS_GetModeID_TV(ivideo->sisvga_engine, vbflags, sisbios_mode[myindex].xres,
sisbios_mode[myindex].yres, 0, ivideo->vbflags2) < 0x14) {
return -1;
}
break;
case CRT2_VGA:
if (SiS_GetModeID_VGA2(ivideo->sisvga_engine, vbflags, sisbios_mode[myindex].xres,
sisbios_mode[myindex].yres, 0, ivideo->vbflags2) < 0x14) {
return -1;
}
break;
}
return myindex;
}
static u8
sisfb_search_refresh_rate(struct sis_video_info *ivideo, unsigned int rate, int mode_idx)
{
int i = 0;
u16 xres = sisbios_mode[mode_idx].xres;
u16 yres = sisbios_mode[mode_idx].yres;
ivideo->rate_idx = 0;
while((sisfb_vrate[i].idx != 0) && (sisfb_vrate[i].xres <= xres)) {
if((sisfb_vrate[i].xres == xres) && (sisfb_vrate[i].yres == yres)) {
if(sisfb_vrate[i].refresh == rate) {
ivideo->rate_idx = sisfb_vrate[i].idx;
break;
} else if(sisfb_vrate[i].refresh > rate) {
if((sisfb_vrate[i].refresh - rate) <= 3) {
DPRINTK("sisfb: Adjusting rate from %d up to %d\n",
rate, sisfb_vrate[i].refresh);
ivideo->rate_idx = sisfb_vrate[i].idx;
ivideo->refresh_rate = sisfb_vrate[i].refresh;
} else if((sisfb_vrate[i].idx != 1) &&
((rate - sisfb_vrate[i-1].refresh) <= 2)) {
DPRINTK("sisfb: Adjusting rate from %d down to %d\n",
rate, sisfb_vrate[i-1].refresh);
ivideo->rate_idx = sisfb_vrate[i-1].idx;
ivideo->refresh_rate = sisfb_vrate[i-1].refresh;
}
break;
} else if((rate - sisfb_vrate[i].refresh) <= 2) {
DPRINTK("sisfb: Adjusting rate from %d down to %d\n",
rate, sisfb_vrate[i].refresh);
ivideo->rate_idx = sisfb_vrate[i].idx;
break;
}
}
i++;
}
if(ivideo->rate_idx > 0) {
return ivideo->rate_idx;
} else {
printk(KERN_INFO "sisfb: Unsupported rate %d for %dx%d\n",
rate, xres, yres);
return 0;
}
}
static bool
sisfb_bridgeisslave(struct sis_video_info *ivideo)
{
unsigned char P1_00;
if(!(ivideo->vbflags2 & VB2_VIDEOBRIDGE))
return false;
P1_00 = SiS_GetReg(SISPART1, 0x00);
if( ((ivideo->sisvga_engine == SIS_300_VGA) && (P1_00 & 0xa0) == 0x20) ||
((ivideo->sisvga_engine == SIS_315_VGA) && (P1_00 & 0x50) == 0x10) ) {
return true;
} else {
return false;
}
}
static bool
sisfballowretracecrt1(struct sis_video_info *ivideo)
{
u8 temp;
temp = SiS_GetReg(SISCR, 0x17);
if(!(temp & 0x80))
return false;
temp = SiS_GetReg(SISSR, 0x1f);
if(temp & 0xc0)
return false;
return true;
}
static bool
sisfbcheckvretracecrt1(struct sis_video_info *ivideo)
{
if(!sisfballowretracecrt1(ivideo))
return false;
if (SiS_GetRegByte(SISINPSTAT) & 0x08)
return true;
else
return false;
}
static void
sisfbwaitretracecrt1(struct sis_video_info *ivideo)
{
int watchdog;
if(!sisfballowretracecrt1(ivideo))
return;
watchdog = 65536;
while ((!(SiS_GetRegByte(SISINPSTAT) & 0x08)) && --watchdog);
watchdog = 65536;
while ((SiS_GetRegByte(SISINPSTAT) & 0x08) && --watchdog);
}
static bool
sisfbcheckvretracecrt2(struct sis_video_info *ivideo)
{
unsigned char temp, reg;
switch(ivideo->sisvga_engine) {
case SIS_300_VGA: reg = 0x25; break;
case SIS_315_VGA: reg = 0x30; break;
default: return false;
}
temp = SiS_GetReg(SISPART1, reg);
if(temp & 0x02)
return true;
else
return false;
}
static bool
sisfb_CheckVBRetrace(struct sis_video_info *ivideo)
{
if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
if(!sisfb_bridgeisslave(ivideo)) {
return sisfbcheckvretracecrt2(ivideo);
}
}
return sisfbcheckvretracecrt1(ivideo);
}
static u32
sisfb_setupvbblankflags(struct sis_video_info *ivideo, u32 *vcount, u32 *hcount)
{
u8 idx, reg1, reg2, reg3, reg4;
u32 ret = 0;
(*vcount) = (*hcount) = 0;
if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!(sisfb_bridgeisslave(ivideo)))) {
ret |= (FB_VBLANK_HAVE_VSYNC |
FB_VBLANK_HAVE_HBLANK |
FB_VBLANK_HAVE_VBLANK |
FB_VBLANK_HAVE_VCOUNT |
FB_VBLANK_HAVE_HCOUNT);
switch(ivideo->sisvga_engine) {
case SIS_300_VGA: idx = 0x25; break;
default:
case SIS_315_VGA: idx = 0x30; break;
}
reg1 = SiS_GetReg(SISPART1, (idx+0)); /* 30 */
reg2 = SiS_GetReg(SISPART1, (idx+1)); /* 31 */
reg3 = SiS_GetReg(SISPART1, (idx+2)); /* 32 */
reg4 = SiS_GetReg(SISPART1, (idx+3)); /* 33 */
if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING;
if(reg1 & 0x02) ret |= FB_VBLANK_VSYNCING;
if(reg4 & 0x80) ret |= FB_VBLANK_HBLANKING;
(*vcount) = reg3 | ((reg4 & 0x70) << 4);
(*hcount) = reg2 | ((reg4 & 0x0f) << 8);
} else if(sisfballowretracecrt1(ivideo)) {
ret |= (FB_VBLANK_HAVE_VSYNC |
FB_VBLANK_HAVE_VBLANK |
FB_VBLANK_HAVE_VCOUNT |
FB_VBLANK_HAVE_HCOUNT);
reg1 = SiS_GetRegByte(SISINPSTAT);
if(reg1 & 0x08) ret |= FB_VBLANK_VSYNCING;
if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING;
reg1 = SiS_GetReg(SISCR, 0x20);
reg1 = SiS_GetReg(SISCR, 0x1b);
reg2 = SiS_GetReg(SISCR, 0x1c);
reg3 = SiS_GetReg(SISCR, 0x1d);
(*vcount) = reg2 | ((reg3 & 0x07) << 8);
(*hcount) = (reg1 | ((reg3 & 0x10) << 4)) << 3;
}
return ret;
}
static int
sisfb_myblank(struct sis_video_info *ivideo, int blank)
{
u8 sr01, sr11, sr1f, cr63=0, p2_0, p1_13;
bool backlight = true;
switch(blank) {
case FB_BLANK_UNBLANK: /* on */
sr01 = 0x00;
sr11 = 0x00;
sr1f = 0x00;
cr63 = 0x00;
p2_0 = 0x20;
p1_13 = 0x00;
backlight = true;
break;
case FB_BLANK_NORMAL: /* blank */
sr01 = 0x20;
sr11 = 0x00;
sr1f = 0x00;
cr63 = 0x00;
p2_0 = 0x20;
p1_13 = 0x00;
backlight = true;
break;
case FB_BLANK_VSYNC_SUSPEND: /* no vsync */
sr01 = 0x20;
sr11 = 0x08;
sr1f = 0x80;
cr63 = 0x40;
p2_0 = 0x40;
p1_13 = 0x80;
backlight = false;
break;
case FB_BLANK_HSYNC_SUSPEND: /* no hsync */
sr01 = 0x20;
sr11 = 0x08;
sr1f = 0x40;
cr63 = 0x40;
p2_0 = 0x80;
p1_13 = 0x40;
backlight = false;
break;
case FB_BLANK_POWERDOWN: /* off */
sr01 = 0x20;
sr11 = 0x08;
sr1f = 0xc0;
cr63 = 0x40;
p2_0 = 0xc0;
p1_13 = 0xc0;
backlight = false;
break;
default:
return 1;
}
if(ivideo->currentvbflags & VB_DISPTYPE_CRT1) {
if( (!ivideo->sisfb_thismonitor.datavalid) ||
((ivideo->sisfb_thismonitor.datavalid) &&
(ivideo->sisfb_thismonitor.feature & 0xe0))) {
if(ivideo->sisvga_engine == SIS_315_VGA) {
SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xbf, cr63);
}
if(!(sisfb_bridgeisslave(ivideo))) {
SiS_SetRegANDOR(SISSR, 0x01, ~0x20, sr01);
SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, sr1f);
}
}
}
if(ivideo->currentvbflags & CRT2_LCD) {
if(ivideo->vbflags2 & VB2_SISLVDSBRIDGE) {
if(backlight) {
SiS_SiS30xBLOn(&ivideo->SiS_Pr);
} else {
SiS_SiS30xBLOff(&ivideo->SiS_Pr);
}
} else if(ivideo->sisvga_engine == SIS_315_VGA) {
#ifdef CONFIG_FB_SIS_315
if(ivideo->vbflags2 & VB2_CHRONTEL) {
if(backlight) {
SiS_Chrontel701xBLOn(&ivideo->SiS_Pr);
} else {
SiS_Chrontel701xBLOff(&ivideo->SiS_Pr);
}
}
#endif
}
if(((ivideo->sisvga_engine == SIS_300_VGA) &&
(ivideo->vbflags2 & (VB2_301|VB2_30xBDH|VB2_LVDS))) ||
((ivideo->sisvga_engine == SIS_315_VGA) &&
((ivideo->vbflags2 & (VB2_LVDS | VB2_CHRONTEL)) == VB2_LVDS))) {
SiS_SetRegANDOR(SISSR, 0x11, ~0x0c, sr11);
}
if(ivideo->sisvga_engine == SIS_300_VGA) {
if((ivideo->vbflags2 & VB2_30xB) &&
(!(ivideo->vbflags2 & VB2_30xBDH))) {
SiS_SetRegANDOR(SISPART1, 0x13, 0x3f, p1_13);
}
} else if(ivideo->sisvga_engine == SIS_315_VGA) {
if((ivideo->vbflags2 & VB2_30xB) &&
(!(ivideo->vbflags2 & VB2_30xBDH))) {
SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0);
}
}
} else if(ivideo->currentvbflags & CRT2_VGA) {
if(ivideo->vbflags2 & VB2_30xB) {
SiS_SetRegANDOR(SISPART2, 0x00, 0x1f, p2_0);
}
}
return 0;
}
/* ------------- Callbacks from init.c/init301.c -------------- */
#ifdef CONFIG_FB_SIS_300
unsigned int
sisfb_read_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg)
{
struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
u32 val = 0;
pci_read_config_dword(ivideo->nbridge, reg, &val);
return (unsigned int)val;
}
void
sisfb_write_nbridge_pci_dword(struct SiS_Private *SiS_Pr, int reg, unsigned int val)
{
struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
pci_write_config_dword(ivideo->nbridge, reg, (u32)val);
}
unsigned int
sisfb_read_lpc_pci_dword(struct SiS_Private *SiS_Pr, int reg)
{
struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
u32 val = 0;
if(!ivideo->lpcdev) return 0;
pci_read_config_dword(ivideo->lpcdev, reg, &val);
return (unsigned int)val;
}
#endif
#ifdef CONFIG_FB_SIS_315
void
sisfb_write_nbridge_pci_byte(struct SiS_Private *SiS_Pr, int reg, unsigned char val)
{
struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
pci_write_config_byte(ivideo->nbridge, reg, (u8)val);
}
unsigned int
sisfb_read_mio_pci_word(struct SiS_Private *SiS_Pr, int reg)
{
struct sis_video_info *ivideo = (struct sis_video_info *)SiS_Pr->ivideo;
u16 val = 0;
if(!ivideo->lpcdev) return 0;
pci_read_config_word(ivideo->lpcdev, reg, &val);
return (unsigned int)val;
}
#endif
/* ----------- FBDev related routines for all series ----------- */
static int
sisfb_get_cmap_len(const struct fb_var_screeninfo *var)
{
return (var->bits_per_pixel == 8) ? 256 : 16;
}
static void
sisfb_set_vparms(struct sis_video_info *ivideo)
{
switch(ivideo->video_bpp) {
case 8:
ivideo->DstColor = 0x0000;
ivideo->SiS310_AccelDepth = 0x00000000;
ivideo->video_cmap_len = 256;
break;
case 16:
ivideo->DstColor = 0x8000;
ivideo->SiS310_AccelDepth = 0x00010000;
ivideo->video_cmap_len = 16;
break;
case 32:
ivideo->DstColor = 0xC000;
ivideo->SiS310_AccelDepth = 0x00020000;
ivideo->video_cmap_len = 16;
break;
default:
ivideo->video_cmap_len = 16;
printk(KERN_ERR "sisfb: Unsupported depth %d", ivideo->video_bpp);
ivideo->accel = 0;
}
}
static int
sisfb_calc_maxyres(struct sis_video_info *ivideo, struct fb_var_screeninfo *var)
{
int maxyres = ivideo->sisfb_mem / (var->xres_virtual * (var->bits_per_pixel >> 3));
if(maxyres > 32767) maxyres = 32767;
return maxyres;
}
static void
sisfb_calc_pitch(struct sis_video_info *ivideo, struct fb_var_screeninfo *var)
{
ivideo->video_linelength = var->xres_virtual * (var->bits_per_pixel >> 3);
ivideo->scrnpitchCRT1 = ivideo->video_linelength;
if(!(ivideo->currentvbflags & CRT1_LCDA)) {
if((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
ivideo->scrnpitchCRT1 <<= 1;
}
}
}
static void
sisfb_set_pitch(struct sis_video_info *ivideo)
{
bool isslavemode = false;
unsigned short HDisplay1 = ivideo->scrnpitchCRT1 >> 3;
unsigned short HDisplay2 = ivideo->video_linelength >> 3;
if(sisfb_bridgeisslave(ivideo)) isslavemode = true;
/* We need to set pitch for CRT1 if bridge is in slave mode, too */
if((ivideo->currentvbflags & VB_DISPTYPE_DISP1) || (isslavemode)) {
SiS_SetReg(SISCR, 0x13, (HDisplay1 & 0xFF));
SiS_SetRegANDOR(SISSR, 0x0E, 0xF0, (HDisplay1 >> 8));
}
/* We must not set the pitch for CRT2 if bridge is in slave mode */
if((ivideo->currentvbflags & VB_DISPTYPE_DISP2) && (!isslavemode)) {
SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01);
SiS_SetReg(SISPART1, 0x07, (HDisplay2 & 0xFF));
SiS_SetRegANDOR(SISPART1, 0x09, 0xF0, (HDisplay2 >> 8));
}
}
static void
sisfb_bpp_to_var(struct sis_video_info *ivideo, struct fb_var_screeninfo *var)
{
ivideo->video_cmap_len = sisfb_get_cmap_len(var);
switch(var->bits_per_pixel) {
case 8:
var->red.offset = var->green.offset = var->blue.offset = 0;
var->red.length = var->green.length = var->blue.length = 8;
break;
case 16:
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 32:
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
}
}
static int
sisfb_set_mode(struct sis_video_info *ivideo, int clrscrn)
{
unsigned short modeno = ivideo->mode_no;
/* >=2.6.12's fbcon clears the screen anyway */
modeno |= 0x80;
SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
sisfb_pre_setmode(ivideo);
if(!SiSSetMode(&ivideo->SiS_Pr, modeno)) {
printk(KERN_ERR "sisfb: Setting mode[0x%x] failed\n", ivideo->mode_no);
return -EINVAL;
}
SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
sisfb_post_setmode(ivideo);
return 0;
}
static int
sisfb_do_set_var(struct fb_var_screeninfo *var, int isactive, struct fb_info *info)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
unsigned int htotal = 0, vtotal = 0;
unsigned int drate = 0, hrate = 0;
int found_mode = 0, ret;
int old_mode;
u32 pixclock;
htotal = var->left_margin + var->xres + var->right_margin + var->hsync_len;
vtotal = var->upper_margin + var->lower_margin + var->vsync_len;
pixclock = var->pixclock;
if((var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED) {
vtotal += var->yres;
vtotal <<= 1;
} else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
vtotal += var->yres;
vtotal <<= 2;
} else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
vtotal += var->yres;
vtotal <<= 1;
} else vtotal += var->yres;
if(!(htotal) || !(vtotal)) {
DPRINTK("sisfb: Invalid 'var' information\n");
return -EINVAL;
}
if(pixclock && htotal && vtotal) {
drate = 1000000000 / pixclock;
hrate = (drate * 1000) / htotal;
ivideo->refresh_rate = (unsigned int) (hrate * 2 / vtotal);
} else {
ivideo->refresh_rate = 60;
}
old_mode = ivideo->sisfb_mode_idx;
ivideo->sisfb_mode_idx = 0;
while( (sisbios_mode[ivideo->sisfb_mode_idx].mode_no[0] != 0) &&
(sisbios_mode[ivideo->sisfb_mode_idx].xres <= var->xres) ) {
if( (sisbios_mode[ivideo->sisfb_mode_idx].xres == var->xres) &&
(sisbios_mode[ivideo->sisfb_mode_idx].yres == var->yres) &&
(sisbios_mode[ivideo->sisfb_mode_idx].bpp == var->bits_per_pixel)) {
ivideo->mode_no = sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni];
found_mode = 1;
break;
}
ivideo->sisfb_mode_idx++;
}
if(found_mode) {
ivideo->sisfb_mode_idx = sisfb_validate_mode(ivideo,
ivideo->sisfb_mode_idx, ivideo->currentvbflags);
} else {
ivideo->sisfb_mode_idx = -1;
}
if(ivideo->sisfb_mode_idx < 0) {
printk(KERN_ERR "sisfb: Mode %dx%dx%d not supported\n", var->xres,
var->yres, var->bits_per_pixel);
ivideo->sisfb_mode_idx = old_mode;
return -EINVAL;
}
ivideo->mode_no = sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni];
if(sisfb_search_refresh_rate(ivideo, ivideo->refresh_rate, ivideo->sisfb_mode_idx) == 0) {
ivideo->rate_idx = sisbios_mode[ivideo->sisfb_mode_idx].rate_idx;
ivideo->refresh_rate = 60;
}
if(isactive) {
/* If acceleration to be used? Need to know
* before pre/post_set_mode()
*/
ivideo->accel = 0;
#if defined(FBINFO_HWACCEL_DISABLED) && defined(FBINFO_HWACCEL_XPAN)
#ifdef STUPID_ACCELF_TEXT_SHIT
if(var->accel_flags & FB_ACCELF_TEXT) {
info->flags &= ~FBINFO_HWACCEL_DISABLED;
} else {
info->flags |= FBINFO_HWACCEL_DISABLED;
}
#endif
if(!(info->flags & FBINFO_HWACCEL_DISABLED)) ivideo->accel = -1;
#else
if(var->accel_flags & FB_ACCELF_TEXT) ivideo->accel = -1;
#endif
if((ret = sisfb_set_mode(ivideo, 1))) {
return ret;
}
ivideo->video_bpp = sisbios_mode[ivideo->sisfb_mode_idx].bpp;
ivideo->video_width = sisbios_mode[ivideo->sisfb_mode_idx].xres;
ivideo->video_height = sisbios_mode[ivideo->sisfb_mode_idx].yres;
sisfb_calc_pitch(ivideo, var);
sisfb_set_pitch(ivideo);
sisfb_set_vparms(ivideo);
ivideo->current_width = ivideo->video_width;
ivideo->current_height = ivideo->video_height;
ivideo->current_bpp = ivideo->video_bpp;
ivideo->current_htotal = htotal;
ivideo->current_vtotal = vtotal;
ivideo->current_linelength = ivideo->video_linelength;
ivideo->current_pixclock = var->pixclock;
ivideo->current_refresh_rate = ivideo->refresh_rate;
ivideo->sisfb_lastrates[ivideo->mode_no] = ivideo->refresh_rate;
}
return 0;
}
static void
sisfb_set_base_CRT1(struct sis_video_info *ivideo, unsigned int base)
{
SiS_SetReg(SISSR, IND_SIS_PASSWORD, SIS_PASSWORD);
SiS_SetReg(SISCR, 0x0D, base & 0xFF);
SiS_SetReg(SISCR, 0x0C, (base >> 8) & 0xFF);
SiS_SetReg(SISSR, 0x0D, (base >> 16) & 0xFF);
if(ivideo->sisvga_engine == SIS_315_VGA) {
SiS_SetRegANDOR(SISSR, 0x37, 0xFE, (base >> 24) & 0x01);
}
}
static void
sisfb_set_base_CRT2(struct sis_video_info *ivideo, unsigned int base)
{
if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
SiS_SetRegOR(SISPART1, ivideo->CRT2_write_enable, 0x01);
SiS_SetReg(SISPART1, 0x06, (base & 0xFF));
SiS_SetReg(SISPART1, 0x05, ((base >> 8) & 0xFF));
SiS_SetReg(SISPART1, 0x04, ((base >> 16) & 0xFF));
if(ivideo->sisvga_engine == SIS_315_VGA) {
SiS_SetRegANDOR(SISPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7);
}
}
}
static int
sisfb_pan_var(struct sis_video_info *ivideo, struct fb_info *info,
struct fb_var_screeninfo *var)
{
ivideo->current_base = var->yoffset * info->var.xres_virtual
+ var->xoffset;
/* calculate base bpp dep. */
switch (info->var.bits_per_pixel) {
case 32:
break;
case 16:
ivideo->current_base >>= 1;
break;
case 8:
default:
ivideo->current_base >>= 2;
break;
}
ivideo->current_base += (ivideo->video_offset >> 2);
sisfb_set_base_CRT1(ivideo, ivideo->current_base);
sisfb_set_base_CRT2(ivideo, ivideo->current_base);
return 0;
}
static int
sisfb_open(struct fb_info *info, int user)
{
return 0;
}
static int
sisfb_release(struct fb_info *info, int user)
{
return 0;
}
static int
sisfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
unsigned transp, struct fb_info *info)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
if(regno >= sisfb_get_cmap_len(&info->var))
return 1;
switch(info->var.bits_per_pixel) {
case 8:
SiS_SetRegByte(SISDACA, regno);
SiS_SetRegByte(SISDACD, (red >> 10));
SiS_SetRegByte(SISDACD, (green >> 10));
SiS_SetRegByte(SISDACD, (blue >> 10));
if(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
SiS_SetRegByte(SISDAC2A, regno);
SiS_SetRegByte(SISDAC2D, (red >> 8));
SiS_SetRegByte(SISDAC2D, (green >> 8));
SiS_SetRegByte(SISDAC2D, (blue >> 8));
}
break;
case 16:
if (regno >= 16)
break;
((u32 *)(info->pseudo_palette))[regno] =
(red & 0xf800) |
((green & 0xfc00) >> 5) |
((blue & 0xf800) >> 11);
break;
case 32:
if (regno >= 16)
break;
red >>= 8;
green >>= 8;
blue >>= 8;
((u32 *)(info->pseudo_palette))[regno] =
(red << 16) | (green << 8) | (blue);
break;
}
return 0;
}
static int
sisfb_set_par(struct fb_info *info)
{
int err;
if((err = sisfb_do_set_var(&info->var, 1, info)))
return err;
sisfb_get_fix(&info->fix, -1, info);
return 0;
}
static int
sisfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
unsigned int htotal = 0, vtotal = 0, myrateindex = 0;
unsigned int drate = 0, hrate = 0, maxyres;
int found_mode = 0;
int refresh_rate, search_idx, tidx;
bool recalc_clock = false;
u32 pixclock;
htotal = var->left_margin + var->xres + var->right_margin + var->hsync_len;
vtotal = var->upper_margin + var->lower_margin + var->vsync_len;
pixclock = var->pixclock;
if((var->vmode & FB_VMODE_MASK) == FB_VMODE_NONINTERLACED) {
vtotal += var->yres;
vtotal <<= 1;
} else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
vtotal += var->yres;
vtotal <<= 2;
} else if((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
vtotal += var->yres;
vtotal <<= 1;
} else
vtotal += var->yres;
if(!(htotal) || !(vtotal)) {
SISFAIL("sisfb: no valid timing data");
}
search_idx = 0;
while( (sisbios_mode[search_idx].mode_no[0] != 0) &&
(sisbios_mode[search_idx].xres <= var->xres) ) {
if( (sisbios_mode[search_idx].xres == var->xres) &&
(sisbios_mode[search_idx].yres == var->yres) &&
(sisbios_mode[search_idx].bpp == var->bits_per_pixel)) {
if((tidx = sisfb_validate_mode(ivideo, search_idx,
ivideo->currentvbflags)) > 0) {
found_mode = 1;
search_idx = tidx;
break;
}
}
search_idx++;
}
if(!found_mode) {
search_idx = 0;
while(sisbios_mode[search_idx].mode_no[0] != 0) {
if( (var->xres <= sisbios_mode[search_idx].xres) &&
(var->yres <= sisbios_mode[search_idx].yres) &&
(var->bits_per_pixel == sisbios_mode[search_idx].bpp) ) {
if((tidx = sisfb_validate_mode(ivideo,search_idx,
ivideo->currentvbflags)) > 0) {
found_mode = 1;
search_idx = tidx;
break;
}
}
search_idx++;
}
if(found_mode) {
printk(KERN_DEBUG
"sisfb: Adapted from %dx%dx%d to %dx%dx%d\n",
var->xres, var->yres, var->bits_per_pixel,
sisbios_mode[search_idx].xres,
sisbios_mode[search_idx].yres,
var->bits_per_pixel);
var->xres = sisbios_mode[search_idx].xres;
var->yres = sisbios_mode[search_idx].yres;
} else {
printk(KERN_ERR
"sisfb: Failed to find supported mode near %dx%dx%d\n",
var->xres, var->yres, var->bits_per_pixel);
return -EINVAL;
}
}
if( ((ivideo->vbflags2 & VB2_LVDS) ||
((ivideo->vbflags2 & VB2_30xBDH) && (ivideo->currentvbflags & CRT2_LCD))) &&
(var->bits_per_pixel == 8) ) {
/* Slave modes on LVDS and 301B-DH */
refresh_rate = 60;
recalc_clock = true;
} else if( (ivideo->current_htotal == htotal) &&
(ivideo->current_vtotal == vtotal) &&
(ivideo->current_pixclock == pixclock) ) {
/* x=x & y=y & c=c -> assume depth change */
drate = 1000000000 / pixclock;
hrate = (drate * 1000) / htotal;
refresh_rate = (unsigned int) (hrate * 2 / vtotal);
} else if( ( (ivideo->current_htotal != htotal) ||
(ivideo->current_vtotal != vtotal) ) &&
(ivideo->current_pixclock == var->pixclock) ) {
/* x!=x | y!=y & c=c -> invalid pixclock */
if(ivideo->sisfb_lastrates[sisbios_mode[search_idx].mode_no[ivideo->mni]]) {
refresh_rate =
ivideo->sisfb_lastrates[sisbios_mode[search_idx].mode_no[ivideo->mni]];
} else if(ivideo->sisfb_parm_rate != -1) {
/* Sic, sisfb_parm_rate - want to know originally desired rate here */
refresh_rate = ivideo->sisfb_parm_rate;
} else {
refresh_rate = 60;
}
recalc_clock = true;
} else if((pixclock) && (htotal) && (vtotal)) {
drate = 1000000000 / pixclock;
hrate = (drate * 1000) / htotal;
refresh_rate = (unsigned int) (hrate * 2 / vtotal);
} else if(ivideo->current_refresh_rate) {
refresh_rate = ivideo->current_refresh_rate;
recalc_clock = true;
} else {
refresh_rate = 60;
recalc_clock = true;
}
myrateindex = sisfb_search_refresh_rate(ivideo, refresh_rate, search_idx);
/* Eventually recalculate timing and clock */
if(recalc_clock) {
if(!myrateindex) myrateindex = sisbios_mode[search_idx].rate_idx;
var->pixclock = (u32) (1000000000 / sisfb_mode_rate_to_dclock(&ivideo->SiS_Pr,
sisbios_mode[search_idx].mode_no[ivideo->mni],
myrateindex));
sisfb_mode_rate_to_ddata(&ivideo->SiS_Pr,
sisbios_mode[search_idx].mode_no[ivideo->mni],
myrateindex, var);
if((var->vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
var->pixclock <<= 1;
}
}
if(ivideo->sisfb_thismonitor.datavalid) {
if(!sisfb_verify_rate(ivideo, &ivideo->sisfb_thismonitor, search_idx,
myrateindex, refresh_rate)) {
printk(KERN_INFO
"sisfb: WARNING: Refresh rate exceeds monitor specs!\n");
}
}
/* Adapt RGB settings */
sisfb_bpp_to_var(ivideo, var);
if(var->xres > var->xres_virtual)
var->xres_virtual = var->xres;
if(ivideo->sisfb_ypan) {
maxyres = sisfb_calc_maxyres(ivideo, var);
if(ivideo->sisfb_max) {
var->yres_virtual = maxyres;
} else {
if(var->yres_virtual > maxyres) {
var->yres_virtual = maxyres;
}
}
if(var->yres_virtual <= var->yres) {
var->yres_virtual = var->yres;
}
} else {
if(var->yres != var->yres_virtual) {
var->yres_virtual = var->yres;
}
var->xoffset = 0;
var->yoffset = 0;
}
/* Truncate offsets to maximum if too high */
if(var->xoffset > var->xres_virtual - var->xres) {
var->xoffset = var->xres_virtual - var->xres - 1;
}
if(var->yoffset > var->yres_virtual - var->yres) {
var->yoffset = var->yres_virtual - var->yres - 1;
}
/* Set everything else to 0 */
var->red.msb_right =
var->green.msb_right =
var->blue.msb_right =
var->transp.offset =
var->transp.length =
var->transp.msb_right = 0;
return 0;
}
static int
sisfb_pan_display(struct fb_var_screeninfo *var, struct fb_info* info)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
int err;
if (var->vmode & FB_VMODE_YWRAP)
return -EINVAL;
if (var->xoffset + info->var.xres > info->var.xres_virtual ||
var->yoffset + info->var.yres > info->var.yres_virtual)
return -EINVAL;
err = sisfb_pan_var(ivideo, info, var);
if (err < 0)
return err;
info->var.xoffset = var->xoffset;
info->var.yoffset = var->yoffset;
return 0;
}
static int
sisfb_blank(int blank, struct fb_info *info)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
return sisfb_myblank(ivideo, blank);
}
/* ----------- FBDev related routines for all series ---------- */
static int sisfb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
struct sis_memreq sismemreq;
struct fb_vblank sisvbblank;
u32 gpu32 = 0;
#ifndef __user
#define __user
#endif
u32 __user *argp = (u32 __user *)arg;
switch(cmd) {
case FBIO_ALLOC:
if(!capable(CAP_SYS_RAWIO))
return -EPERM;
if(copy_from_user(&sismemreq, (void __user *)arg, sizeof(sismemreq)))
return -EFAULT;
sis_malloc(&sismemreq);
if(copy_to_user((void __user *)arg, &sismemreq, sizeof(sismemreq))) {
sis_free((u32)sismemreq.offset);
return -EFAULT;
}
break;
case FBIO_FREE:
if(!capable(CAP_SYS_RAWIO))
return -EPERM;
if(get_user(gpu32, argp))
return -EFAULT;
sis_free(gpu32);
break;
case FBIOGET_VBLANK:
memset(&sisvbblank, 0, sizeof(struct fb_vblank));
sisvbblank.count = 0;
sisvbblank.flags = sisfb_setupvbblankflags(ivideo, &sisvbblank.vcount, &sisvbblank.hcount);
if(copy_to_user((void __user *)arg, &sisvbblank, sizeof(sisvbblank)))
return -EFAULT;
break;
case SISFB_GET_INFO_SIZE:
return put_user(sizeof(struct sisfb_info), argp);
case SISFB_GET_INFO_OLD:
if(ivideo->warncount++ < 10)
printk(KERN_INFO
"sisfb: Deprecated ioctl call received - update your application!\n");
fallthrough;
case SISFB_GET_INFO: /* For communication with X driver */
ivideo->sisfb_infoblock.sisfb_id = SISFB_ID;
ivideo->sisfb_infoblock.sisfb_version = VER_MAJOR;
ivideo->sisfb_infoblock.sisfb_revision = VER_MINOR;
ivideo->sisfb_infoblock.sisfb_patchlevel = VER_LEVEL;
ivideo->sisfb_infoblock.chip_id = ivideo->chip_id;
ivideo->sisfb_infoblock.sisfb_pci_vendor = ivideo->chip_vendor;
ivideo->sisfb_infoblock.memory = ivideo->video_size / 1024;
ivideo->sisfb_infoblock.heapstart = ivideo->heapstart / 1024;
if(ivideo->modechanged) {
ivideo->sisfb_infoblock.fbvidmode = ivideo->mode_no;
} else {
ivideo->sisfb_infoblock.fbvidmode = ivideo->modeprechange;
}
ivideo->sisfb_infoblock.sisfb_caps = ivideo->caps;
ivideo->sisfb_infoblock.sisfb_tqlen = ivideo->cmdQueueSize / 1024;
ivideo->sisfb_infoblock.sisfb_pcibus = ivideo->pcibus;
ivideo->sisfb_infoblock.sisfb_pcislot = ivideo->pcislot;
ivideo->sisfb_infoblock.sisfb_pcifunc = ivideo->pcifunc;
ivideo->sisfb_infoblock.sisfb_lcdpdc = ivideo->detectedpdc;
ivideo->sisfb_infoblock.sisfb_lcdpdca = ivideo->detectedpdca;
ivideo->sisfb_infoblock.sisfb_lcda = ivideo->detectedlcda;
ivideo->sisfb_infoblock.sisfb_vbflags = ivideo->vbflags;
ivideo->sisfb_infoblock.sisfb_currentvbflags = ivideo->currentvbflags;
ivideo->sisfb_infoblock.sisfb_scalelcd = ivideo->SiS_Pr.UsePanelScaler;
ivideo->sisfb_infoblock.sisfb_specialtiming = ivideo->SiS_Pr.SiS_CustomT;
ivideo->sisfb_infoblock.sisfb_haveemi = ivideo->SiS_Pr.HaveEMI ? 1 : 0;
ivideo->sisfb_infoblock.sisfb_haveemilcd = ivideo->SiS_Pr.HaveEMILCD ? 1 : 0;
ivideo->sisfb_infoblock.sisfb_emi30 = ivideo->SiS_Pr.EMI_30;
ivideo->sisfb_infoblock.sisfb_emi31 = ivideo->SiS_Pr.EMI_31;
ivideo->sisfb_infoblock.sisfb_emi32 = ivideo->SiS_Pr.EMI_32;
ivideo->sisfb_infoblock.sisfb_emi33 = ivideo->SiS_Pr.EMI_33;
ivideo->sisfb_infoblock.sisfb_tvxpos = (u16)(ivideo->tvxpos + 32);
ivideo->sisfb_infoblock.sisfb_tvypos = (u16)(ivideo->tvypos + 32);
ivideo->sisfb_infoblock.sisfb_heapsize = ivideo->sisfb_heap_size / 1024;
ivideo->sisfb_infoblock.sisfb_videooffset = ivideo->video_offset;
ivideo->sisfb_infoblock.sisfb_curfstn = ivideo->curFSTN;
ivideo->sisfb_infoblock.sisfb_curdstn = ivideo->curDSTN;
ivideo->sisfb_infoblock.sisfb_vbflags2 = ivideo->vbflags2;
ivideo->sisfb_infoblock.sisfb_can_post = ivideo->sisfb_can_post ? 1 : 0;
ivideo->sisfb_infoblock.sisfb_card_posted = ivideo->sisfb_card_posted ? 1 : 0;
ivideo->sisfb_infoblock.sisfb_was_boot_device = ivideo->sisfb_was_boot_device ? 1 : 0;
if(copy_to_user((void __user *)arg, &ivideo->sisfb_infoblock,
sizeof(ivideo->sisfb_infoblock)))
return -EFAULT;
break;
case SISFB_GET_VBRSTATUS_OLD:
if(ivideo->warncount++ < 10)
printk(KERN_INFO
"sisfb: Deprecated ioctl call received - update your application!\n");
fallthrough;
case SISFB_GET_VBRSTATUS:
if(sisfb_CheckVBRetrace(ivideo))
return put_user((u32)1, argp);
else
return put_user((u32)0, argp);
case SISFB_GET_AUTOMAXIMIZE_OLD:
if(ivideo->warncount++ < 10)
printk(KERN_INFO
"sisfb: Deprecated ioctl call received - update your application!\n");
fallthrough;
case SISFB_GET_AUTOMAXIMIZE:
if(ivideo->sisfb_max)
return put_user((u32)1, argp);
else
return put_user((u32)0, argp);
case SISFB_SET_AUTOMAXIMIZE_OLD:
if(ivideo->warncount++ < 10)
printk(KERN_INFO
"sisfb: Deprecated ioctl call received - update your application!\n");
fallthrough;
case SISFB_SET_AUTOMAXIMIZE:
if(get_user(gpu32, argp))
return -EFAULT;
ivideo->sisfb_max = (gpu32) ? 1 : 0;
break;
case SISFB_SET_TVPOSOFFSET:
if(get_user(gpu32, argp))
return -EFAULT;
sisfb_set_TVxposoffset(ivideo, ((int)(gpu32 >> 16)) - 32);
sisfb_set_TVyposoffset(ivideo, ((int)(gpu32 & 0xffff)) - 32);
break;
case SISFB_GET_TVPOSOFFSET:
return put_user((u32)(((ivideo->tvxpos+32)<<16)|((ivideo->tvypos+32)&0xffff)),
argp);
case SISFB_COMMAND:
if(copy_from_user(&ivideo->sisfb_command, (void __user *)arg,
sizeof(struct sisfb_cmd)))
return -EFAULT;
sisfb_handle_command(ivideo, &ivideo->sisfb_command);
if(copy_to_user((void __user *)arg, &ivideo->sisfb_command,
sizeof(struct sisfb_cmd)))
return -EFAULT;
break;
case SISFB_SET_LOCK:
if(get_user(gpu32, argp))
return -EFAULT;
ivideo->sisfblocked = (gpu32) ? 1 : 0;
break;
default:
#ifdef SIS_NEW_CONFIG_COMPAT
return -ENOIOCTLCMD;
#else
return -EINVAL;
#endif
}
return 0;
}
static int
sisfb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *info)
{
struct sis_video_info *ivideo = (struct sis_video_info *)info->par;
memset(fix, 0, sizeof(struct fb_fix_screeninfo));
strscpy(fix->id, ivideo->myid, sizeof(fix->id));
mutex_lock(&info->mm_lock);
fix->smem_start = ivideo->video_base + ivideo->video_offset;
fix->smem_len = ivideo->sisfb_mem;
mutex_unlock(&info->mm_lock);
fix->type = FB_TYPE_PACKED_PIXELS;
fix->type_aux = 0;
fix->visual = (ivideo->video_bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
fix->xpanstep = 1;
fix->ypanstep = (ivideo->sisfb_ypan) ? 1 : 0;
fix->ywrapstep = 0;
fix->line_length = ivideo->video_linelength;
fix->mmio_start = ivideo->mmio_base;
fix->mmio_len = ivideo->mmio_size;
if(ivideo->sisvga_engine == SIS_300_VGA) {
fix->accel = FB_ACCEL_SIS_GLAMOUR;
} else if((ivideo->chip == SIS_330) ||
(ivideo->chip == SIS_760) ||
(ivideo->chip == SIS_761)) {
fix->accel = FB_ACCEL_SIS_XABRE;
} else if(ivideo->chip == XGI_20) {
fix->accel = FB_ACCEL_XGI_VOLARI_Z;
} else if(ivideo->chip >= XGI_40) {
fix->accel = FB_ACCEL_XGI_VOLARI_V;
} else {
fix->accel = FB_ACCEL_SIS_GLAMOUR_2;
}
return 0;
}
/* ---------------- fb_ops structures ----------------- */
static const struct fb_ops sisfb_ops = {
.owner = THIS_MODULE,
.fb_open = sisfb_open,
.fb_release = sisfb_release,
.fb_check_var = sisfb_check_var,
.fb_set_par = sisfb_set_par,
.fb_setcolreg = sisfb_setcolreg,
.fb_pan_display = sisfb_pan_display,
.fb_blank = sisfb_blank,
.fb_fillrect = fbcon_sis_fillrect,
.fb_copyarea = fbcon_sis_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_sync = fbcon_sis_sync,
#ifdef SIS_NEW_CONFIG_COMPAT
.fb_compat_ioctl= sisfb_ioctl,
#endif
.fb_ioctl = sisfb_ioctl
};
/* ---------------- Chip generation dependent routines ---------------- */
static struct pci_dev *sisfb_get_northbridge(int basechipid)
{
struct pci_dev *pdev = NULL;
int nbridgenum, nbridgeidx, i;
static const unsigned short nbridgeids[] = {
PCI_DEVICE_ID_SI_540, /* for SiS 540 VGA */
PCI_DEVICE_ID_SI_630, /* for SiS 630/730 VGA */
PCI_DEVICE_ID_SI_730,
PCI_DEVICE_ID_SI_550, /* for SiS 550 VGA */
PCI_DEVICE_ID_SI_650, /* for SiS 650/651/740 VGA */
PCI_DEVICE_ID_SI_651,
PCI_DEVICE_ID_SI_740,
PCI_DEVICE_ID_SI_661, /* for SiS 661/741/660/760/761 VGA */
PCI_DEVICE_ID_SI_741,
PCI_DEVICE_ID_SI_660,
PCI_DEVICE_ID_SI_760,
PCI_DEVICE_ID_SI_761
};
switch(basechipid) {
#ifdef CONFIG_FB_SIS_300
case SIS_540: nbridgeidx = 0; nbridgenum = 1; break;
case SIS_630: nbridgeidx = 1; nbridgenum = 2; break;
#endif
#ifdef CONFIG_FB_SIS_315
case SIS_550: nbridgeidx = 3; nbridgenum = 1; break;
case SIS_650: nbridgeidx = 4; nbridgenum = 3; break;
case SIS_660: nbridgeidx = 7; nbridgenum = 5; break;
#endif
default: return NULL;
}
for(i = 0; i < nbridgenum; i++) {
if((pdev = pci_get_device(PCI_VENDOR_ID_SI,
nbridgeids[nbridgeidx+i], NULL)))
break;
}
return pdev;
}
static int sisfb_get_dram_size(struct sis_video_info *ivideo)
{
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
u8 reg;
#endif
ivideo->video_size = 0;
ivideo->UMAsize = ivideo->LFBsize = 0;
switch(ivideo->chip) {
#ifdef CONFIG_FB_SIS_300
case SIS_300:
reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = ((reg & 0x3F) + 1) << 20;
break;
case SIS_540:
case SIS_630:
case SIS_730:
if(!ivideo->nbridge)
return -1;
pci_read_config_byte(ivideo->nbridge, 0x63, ®);
ivideo->video_size = 1 << (((reg & 0x70) >> 4) + 21);
break;
#endif
#ifdef CONFIG_FB_SIS_315
case SIS_315H:
case SIS_315PRO:
case SIS_315:
reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
switch((reg >> 2) & 0x03) {
case 0x01:
case 0x03:
ivideo->video_size <<= 1;
break;
case 0x02:
ivideo->video_size += (ivideo->video_size/2);
}
break;
case SIS_330:
reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
if(reg & 0x0c) ivideo->video_size <<= 1;
break;
case SIS_550:
case SIS_650:
case SIS_740:
reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (((reg & 0x3f) + 1) << 2) << 20;
break;
case SIS_661:
case SIS_741:
reg = SiS_GetReg(SISCR, 0x79);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
break;
case SIS_660:
case SIS_760:
case SIS_761:
reg = SiS_GetReg(SISCR, 0x79);
reg = (reg & 0xf0) >> 4;
if(reg) {
ivideo->video_size = (1 << reg) << 20;
ivideo->UMAsize = ivideo->video_size;
}
reg = SiS_GetReg(SISCR, 0x78);
reg &= 0x30;
if(reg) {
if(reg == 0x10) {
ivideo->LFBsize = (32 << 20);
} else {
ivideo->LFBsize = (64 << 20);
}
ivideo->video_size += ivideo->LFBsize;
}
break;
case SIS_340:
case XGI_20:
case XGI_40:
reg = SiS_GetReg(SISSR, 0x14);
ivideo->video_size = (1 << ((reg & 0xf0) >> 4)) << 20;
if(ivideo->chip != XGI_20) {
reg = (reg & 0x0c) >> 2;
if(ivideo->revision_id == 2) {
if(reg & 0x01) reg = 0x02;
else reg = 0x00;
}
if(reg == 0x02) ivideo->video_size <<= 1;
else if(reg == 0x03) ivideo->video_size <<= 2;
}
break;
#endif
default:
return -1;
}
return 0;
}
/* -------------- video bridge device detection --------------- */
static void sisfb_detect_VB_connect(struct sis_video_info *ivideo)
{
u8 cr32, temp;
/* No CRT2 on XGI Z7 */
if(ivideo->chip == XGI_20) {
ivideo->sisfb_crt1off = 0;
return;
}
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
temp = SiS_GetReg(SISSR, 0x17);
if((temp & 0x0F) && (ivideo->chip != SIS_300)) {
/* PAL/NTSC is stored on SR16 on such machines */
if(!(ivideo->vbflags & (TV_PAL | TV_NTSC | TV_PALM | TV_PALN))) {
temp = SiS_GetReg(SISSR, 0x16);
if(temp & 0x20)
ivideo->vbflags |= TV_PAL;
else
ivideo->vbflags |= TV_NTSC;
}
}
}
#endif
cr32 = SiS_GetReg(SISCR, 0x32);
if(cr32 & SIS_CRT1) {
ivideo->sisfb_crt1off = 0;
} else {
ivideo->sisfb_crt1off = (cr32 & 0xDF) ? 1 : 0;
}
ivideo->vbflags &= ~(CRT2_TV | CRT2_LCD | CRT2_VGA);
if(cr32 & SIS_VB_TV) ivideo->vbflags |= CRT2_TV;
if(cr32 & SIS_VB_LCD) ivideo->vbflags |= CRT2_LCD;
if(cr32 & SIS_VB_CRT2) ivideo->vbflags |= CRT2_VGA;
/* Check given parms for hardware compatibility.
* (Cannot do this in the search_xx routines since we don't
* know what hardware we are running on then)
*/
if(ivideo->chip != SIS_550) {
ivideo->sisfb_dstn = ivideo->sisfb_fstn = 0;
}
if(ivideo->sisfb_tvplug != -1) {
if( (ivideo->sisvga_engine != SIS_315_VGA) ||
(!(ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) ) {
if(ivideo->sisfb_tvplug & TV_YPBPR) {
ivideo->sisfb_tvplug = -1;
printk(KERN_ERR "sisfb: YPbPr not supported\n");
}
}
}
if(ivideo->sisfb_tvplug != -1) {
if( (ivideo->sisvga_engine != SIS_315_VGA) ||
(!(ivideo->vbflags2 & VB2_SISHIVISIONBRIDGE)) ) {
if(ivideo->sisfb_tvplug & TV_HIVISION) {
ivideo->sisfb_tvplug = -1;
printk(KERN_ERR "sisfb: HiVision not supported\n");
}
}
}
if(ivideo->sisfb_tvstd != -1) {
if( (!(ivideo->vbflags2 & VB2_SISBRIDGE)) &&
(!((ivideo->sisvga_engine == SIS_315_VGA) &&
(ivideo->vbflags2 & VB2_CHRONTEL))) ) {
if(ivideo->sisfb_tvstd & (TV_PALM | TV_PALN | TV_NTSCJ)) {
ivideo->sisfb_tvstd = -1;
printk(KERN_ERR "sisfb: PALM/PALN/NTSCJ not supported\n");
}
}
}
/* Detect/set TV plug & type */
if(ivideo->sisfb_tvplug != -1) {
ivideo->vbflags |= ivideo->sisfb_tvplug;
} else {
if(cr32 & SIS_VB_YPBPR) ivideo->vbflags |= (TV_YPBPR|TV_YPBPR525I); /* default: 480i */
else if(cr32 & SIS_VB_HIVISION) ivideo->vbflags |= TV_HIVISION;
else if(cr32 & SIS_VB_SCART) ivideo->vbflags |= TV_SCART;
else {
if(cr32 & SIS_VB_SVIDEO) ivideo->vbflags |= TV_SVIDEO;
if(cr32 & SIS_VB_COMPOSITE) ivideo->vbflags |= TV_AVIDEO;
}
}
if(!(ivideo->vbflags & (TV_YPBPR | TV_HIVISION))) {
if(ivideo->sisfb_tvstd != -1) {
ivideo->vbflags &= ~(TV_NTSC | TV_PAL | TV_PALM | TV_PALN | TV_NTSCJ);
ivideo->vbflags |= ivideo->sisfb_tvstd;
}
if(ivideo->vbflags & TV_SCART) {
ivideo->vbflags &= ~(TV_NTSC | TV_PALM | TV_PALN | TV_NTSCJ);
ivideo->vbflags |= TV_PAL;
}
if(!(ivideo->vbflags & (TV_PAL | TV_NTSC | TV_PALM | TV_PALN | TV_NTSCJ))) {
if(ivideo->sisvga_engine == SIS_300_VGA) {
temp = SiS_GetReg(SISSR, 0x38);
if(temp & 0x01) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
} else if((ivideo->chip <= SIS_315PRO) || (ivideo->chip >= SIS_330)) {
temp = SiS_GetReg(SISSR, 0x38);
if(temp & 0x01) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
} else {
temp = SiS_GetReg(SISCR, 0x79);
if(temp & 0x20) ivideo->vbflags |= TV_PAL;
else ivideo->vbflags |= TV_NTSC;
}
}
}
/* Copy forceCRT1 option to CRT1off if option is given */
if(ivideo->sisfb_forcecrt1 != -1) {
ivideo->sisfb_crt1off = (ivideo->sisfb_forcecrt1) ? 0 : 1;
}
}
/* ------------------ Sensing routines ------------------ */
static bool sisfb_test_DDC1(struct sis_video_info *ivideo)
{
unsigned short old;
int count = 48;
old = SiS_ReadDDC1Bit(&ivideo->SiS_Pr);
do {
if(old != SiS_ReadDDC1Bit(&ivideo->SiS_Pr)) break;
} while(count--);
return (count != -1);
}
static void sisfb_sense_crt1(struct sis_video_info *ivideo)
{
bool mustwait = false;
u8 sr1F, cr17;
#ifdef CONFIG_FB_SIS_315
u8 cr63 = 0;
#endif
u16 temp = 0xffff;
int i;
sr1F = SiS_GetReg(SISSR, 0x1F);
SiS_SetRegOR(SISSR, 0x1F, 0x04);
SiS_SetRegAND(SISSR, 0x1F, 0x3F);
if (sr1F & 0xc0)
mustwait = true;
#ifdef CONFIG_FB_SIS_315
if (ivideo->sisvga_engine == SIS_315_VGA) {
cr63 = SiS_GetReg(SISCR, ivideo->SiS_Pr.SiS_MyCR63);
cr63 &= 0x40;
SiS_SetRegAND(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF);
}
#endif
cr17 = SiS_GetReg(SISCR, 0x17);
cr17 &= 0x80;
if (!cr17) {
SiS_SetRegOR(SISCR, 0x17, 0x80);
mustwait = true;
SiS_SetReg(SISSR, 0x00, 0x01);
SiS_SetReg(SISSR, 0x00, 0x03);
}
if (mustwait) {
for (i = 0; i < 10; i++)
sisfbwaitretracecrt1(ivideo);
}
#ifdef CONFIG_FB_SIS_315
if (ivideo->chip >= SIS_330) {
SiS_SetRegAND(SISCR, 0x32, ~0x20);
if (ivideo->chip >= SIS_340)
SiS_SetReg(SISCR, 0x57, 0x4a);
else
SiS_SetReg(SISCR, 0x57, 0x5f);
SiS_SetRegOR(SISCR, 0x53, 0x02);
while ((SiS_GetRegByte(SISINPSTAT)) & 0x01)
break;
while (!((SiS_GetRegByte(SISINPSTAT)) & 0x01))
break;
if ((SiS_GetRegByte(SISMISCW)) & 0x10)
temp = 1;
SiS_SetRegAND(SISCR, 0x53, 0xfd);
SiS_SetRegAND(SISCR, 0x57, 0x00);
}
#endif
if (temp == 0xffff) {
i = 3;
do {
temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags,
ivideo->sisvga_engine, 0, 0, NULL, ivideo->vbflags2);
} while (((temp == 0) || (temp == 0xffff)) && i--);
if ((temp == 0) || (temp == 0xffff)) {
if (sisfb_test_DDC1(ivideo))
temp = 1;
}
}
if ((temp) && (temp != 0xffff))
SiS_SetRegOR(SISCR, 0x32, 0x20);
#ifdef CONFIG_FB_SIS_315
if (ivideo->sisvga_engine == SIS_315_VGA)
SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF, cr63);
#endif
SiS_SetRegANDOR(SISCR, 0x17, 0x7F, cr17);
SiS_SetReg(SISSR, 0x1F, sr1F);
}
/* Determine and detect attached devices on SiS30x */
static void SiS_SenseLCD(struct sis_video_info *ivideo)
{
unsigned char buffer[256];
unsigned short temp, realcrtno, i;
u8 reg, cr37 = 0, paneltype = 0;
u16 xres, yres;
ivideo->SiS_Pr.PanelSelfDetected = false;
/* LCD detection only for TMDS bridges */
if (!(ivideo->vbflags2 & VB2_SISTMDSBRIDGE))
return;
if (ivideo->vbflags2 & VB2_30xBDH)
return;
/* If LCD already set up by BIOS, skip it */
reg = SiS_GetReg(SISCR, 0x32);
if (reg & 0x08)
return;
realcrtno = 1;
if (ivideo->SiS_Pr.DDCPortMixup)
realcrtno = 0;
/* Check DDC capabilities */
temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags, ivideo->sisvga_engine,
realcrtno, 0, &buffer[0], ivideo->vbflags2);
if ((!temp) || (temp == 0xffff) || (!(temp & 0x02)))
return;
/* Read DDC data */
i = 3; /* Number of retrys */
do {
temp = SiS_HandleDDC(&ivideo->SiS_Pr, ivideo->vbflags,
ivideo->sisvga_engine, realcrtno, 1,
&buffer[0], ivideo->vbflags2);
} while ((temp) && i--);
if (temp)
return;
/* No digital device */
if (!(buffer[0x14] & 0x80))
return;
/* First detailed timing preferred timing? */
if (!(buffer[0x18] & 0x02))
return;
xres = buffer[0x38] | ((buffer[0x3a] & 0xf0) << 4);
yres = buffer[0x3b] | ((buffer[0x3d] & 0xf0) << 4);
switch(xres) {
case 1024:
if (yres == 768)
paneltype = 0x02;
break;
case 1280:
if (yres == 1024)
paneltype = 0x03;
break;
case 1600:
if ((yres == 1200) && (ivideo->vbflags2 & VB2_30xC))
paneltype = 0x0b;
break;
}
if (!paneltype)
return;
if (buffer[0x23])
cr37 |= 0x10;
if ((buffer[0x47] & 0x18) == 0x18)
cr37 |= ((((buffer[0x47] & 0x06) ^ 0x06) << 5) | 0x20);
else
cr37 |= 0xc0;
SiS_SetReg(SISCR, 0x36, paneltype);
cr37 &= 0xf1;
SiS_SetRegANDOR(SISCR, 0x37, 0x0c, cr37);
SiS_SetRegOR(SISCR, 0x32, 0x08);
ivideo->SiS_Pr.PanelSelfDetected = true;
}
static int SISDoSense(struct sis_video_info *ivideo, u16 type, u16 test)
{
int temp, mytest, result, i, j;
for (j = 0; j < 10; j++) {
result = 0;
for (i = 0; i < 3; i++) {
mytest = test;
SiS_SetReg(SISPART4, 0x11, (type & 0x00ff));
temp = (type >> 8) | (mytest & 0x00ff);
SiS_SetRegANDOR(SISPART4, 0x10, 0xe0, temp);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1500);
mytest >>= 8;
mytest &= 0x7f;
temp = SiS_GetReg(SISPART4, 0x03);
temp ^= 0x0e;
temp &= mytest;
if (temp == mytest)
result++;
#if 1
SiS_SetReg(SISPART4, 0x11, 0x00);
SiS_SetRegAND(SISPART4, 0x10, 0xe0);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1000);
#endif
}
if ((result == 0) || (result >= 2))
break;
}
return result;
}
static void SiS_Sense30x(struct sis_video_info *ivideo)
{
u8 backupP4_0d,backupP2_00,backupP2_4d,backupSR_1e,biosflag=0;
u16 svhs=0, svhs_c=0;
u16 cvbs=0, cvbs_c=0;
u16 vga2=0, vga2_c=0;
int myflag, result;
char stdstr[] = "sisfb: Detected";
char tvstr[] = "TV connected to";
if(ivideo->vbflags2 & VB2_301) {
svhs = 0x00b9; cvbs = 0x00b3; vga2 = 0x00d1;
myflag = SiS_GetReg(SISPART4, 0x01);
if(myflag & 0x04) {
svhs = 0x00dd; cvbs = 0x00ee; vga2 = 0x00fd;
}
} else if(ivideo->vbflags2 & (VB2_301B | VB2_302B)) {
svhs = 0x016b; cvbs = 0x0174; vga2 = 0x0190;
} else if(ivideo->vbflags2 & (VB2_301LV | VB2_302LV)) {
svhs = 0x0200; cvbs = 0x0100;
} else if(ivideo->vbflags2 & (VB2_301C | VB2_302ELV | VB2_307T | VB2_307LV)) {
svhs = 0x016b; cvbs = 0x0110; vga2 = 0x0190;
} else
return;
vga2_c = 0x0e08; svhs_c = 0x0404; cvbs_c = 0x0804;
if(ivideo->vbflags & (VB2_301LV|VB2_302LV|VB2_302ELV|VB2_307LV)) {
svhs_c = 0x0408; cvbs_c = 0x0808;
}
biosflag = 2;
if(ivideo->haveXGIROM) {
biosflag = ivideo->bios_abase[0x58] & 0x03;
} else if(ivideo->newrom) {
if(ivideo->bios_abase[0x5d] & 0x04) biosflag |= 0x01;
} else if(ivideo->sisvga_engine == SIS_300_VGA) {
if(ivideo->bios_abase) {
biosflag = ivideo->bios_abase[0xfe] & 0x03;
}
}
if(ivideo->chip == SIS_300) {
myflag = SiS_GetReg(SISSR, 0x3b);
if(!(myflag & 0x01)) vga2 = vga2_c = 0;
}
if(!(ivideo->vbflags2 & VB2_SISVGA2BRIDGE)) {
vga2 = vga2_c = 0;
}
backupSR_1e = SiS_GetReg(SISSR, 0x1e);
SiS_SetRegOR(SISSR, 0x1e, 0x20);
backupP4_0d = SiS_GetReg(SISPART4, 0x0d);
if(ivideo->vbflags2 & VB2_30xC) {
SiS_SetRegANDOR(SISPART4, 0x0d, ~0x07, 0x01);
} else {
SiS_SetRegOR(SISPART4, 0x0d, 0x04);
}
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
backupP2_00 = SiS_GetReg(SISPART2, 0x00);
SiS_SetReg(SISPART2, 0x00, ((backupP2_00 | 0x1c) & 0xfc));
backupP2_4d = SiS_GetReg(SISPART2, 0x4d);
if(ivideo->vbflags2 & VB2_SISYPBPRBRIDGE) {
SiS_SetReg(SISPART2, 0x4d, (backupP2_4d & ~0x10));
}
if(!(ivideo->vbflags2 & VB2_30xCLV)) {
SISDoSense(ivideo, 0, 0);
}
SiS_SetRegAND(SISCR, 0x32, ~0x14);
if(vga2_c || vga2) {
if(SISDoSense(ivideo, vga2, vga2_c)) {
if(biosflag & 0x01) {
printk(KERN_INFO "%s %s SCART output\n", stdstr, tvstr);
SiS_SetRegOR(SISCR, 0x32, 0x04);
} else {
printk(KERN_INFO "%s secondary VGA connection\n", stdstr);
SiS_SetRegOR(SISCR, 0x32, 0x10);
}
}
}
SiS_SetRegAND(SISCR, 0x32, 0x3f);
if(ivideo->vbflags2 & VB2_30xCLV) {
SiS_SetRegOR(SISPART4, 0x0d, 0x04);
}
if((ivideo->sisvga_engine == SIS_315_VGA) && (ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) {
SiS_SetReg(SISPART2, 0x4d, (backupP2_4d | 0x10));
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x2000);
if((result = SISDoSense(ivideo, svhs, 0x0604))) {
if((result = SISDoSense(ivideo, cvbs, 0x0804))) {
printk(KERN_INFO "%s %s YPbPr component output\n", stdstr, tvstr);
SiS_SetRegOR(SISCR, 0x32, 0x80);
}
}
SiS_SetReg(SISPART2, 0x4d, backupP2_4d);
}
SiS_SetRegAND(SISCR, 0x32, ~0x03);
if(!(ivideo->vbflags & TV_YPBPR)) {
if((result = SISDoSense(ivideo, svhs, svhs_c))) {
printk(KERN_INFO "%s %s SVIDEO output\n", stdstr, tvstr);
SiS_SetRegOR(SISCR, 0x32, 0x02);
}
if((biosflag & 0x02) || (!result)) {
if(SISDoSense(ivideo, cvbs, cvbs_c)) {
printk(KERN_INFO "%s %s COMPOSITE output\n", stdstr, tvstr);
SiS_SetRegOR(SISCR, 0x32, 0x01);
}
}
}
SISDoSense(ivideo, 0, 0);
SiS_SetReg(SISPART2, 0x00, backupP2_00);
SiS_SetReg(SISPART4, 0x0d, backupP4_0d);
SiS_SetReg(SISSR, 0x1e, backupSR_1e);
if(ivideo->vbflags2 & VB2_30xCLV) {
biosflag = SiS_GetReg(SISPART2, 0x00);
if(biosflag & 0x20) {
for(myflag = 2; myflag > 0; myflag--) {
biosflag ^= 0x20;
SiS_SetReg(SISPART2, 0x00, biosflag);
}
}
}
SiS_SetReg(SISPART2, 0x00, backupP2_00);
}
/* Determine and detect attached TV's on Chrontel */
static void SiS_SenseCh(struct sis_video_info *ivideo)
{
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
u8 temp1, temp2;
char stdstr[] = "sisfb: Chrontel: Detected TV connected to";
#endif
#ifdef CONFIG_FB_SIS_300
unsigned char test[3];
int i;
#endif
if(ivideo->chip < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
ivideo->SiS_Pr.SiS_IF_DEF_CH70xx = 1; /* Chrontel 700x */
SiS_SetChrontelGPIO(&ivideo->SiS_Pr, 0x9c); /* Set general purpose IO for Chrontel communication */
SiS_DDC2Delay(&ivideo->SiS_Pr, 1000);
temp1 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x25);
/* See Chrontel TB31 for explanation */
temp2 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0e);
if(((temp2 & 0x07) == 0x01) || (temp2 & 0x04)) {
SiS_SetCH700x(&ivideo->SiS_Pr, 0x0e, 0x0b);
SiS_DDC2Delay(&ivideo->SiS_Pr, 300);
}
temp2 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x25);
if(temp2 != temp1) temp1 = temp2;
if((temp1 >= 0x22) && (temp1 <= 0x50)) {
/* Read power status */
temp1 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0e);
if((temp1 & 0x03) != 0x03) {
/* Power all outputs */
SiS_SetCH700x(&ivideo->SiS_Pr, 0x0e,0x0b);
SiS_DDC2Delay(&ivideo->SiS_Pr, 300);
}
/* Sense connected TV devices */
for(i = 0; i < 3; i++) {
SiS_SetCH700x(&ivideo->SiS_Pr, 0x10, 0x01);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
SiS_SetCH700x(&ivideo->SiS_Pr, 0x10, 0x00);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
temp1 = SiS_GetCH700x(&ivideo->SiS_Pr, 0x10);
if(!(temp1 & 0x08)) test[i] = 0x02;
else if(!(temp1 & 0x02)) test[i] = 0x01;
else test[i] = 0;
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
}
if(test[0] == test[1]) temp1 = test[0];
else if(test[0] == test[2]) temp1 = test[0];
else if(test[1] == test[2]) temp1 = test[1];
else {
printk(KERN_INFO
"sisfb: TV detection unreliable - test results varied\n");
temp1 = test[2];
}
if(temp1 == 0x02) {
printk(KERN_INFO "%s SVIDEO output\n", stdstr);
ivideo->vbflags |= TV_SVIDEO;
SiS_SetRegOR(SISCR, 0x32, 0x02);
SiS_SetRegAND(SISCR, 0x32, ~0x05);
} else if (temp1 == 0x01) {
printk(KERN_INFO "%s CVBS output\n", stdstr);
ivideo->vbflags |= TV_AVIDEO;
SiS_SetRegOR(SISCR, 0x32, 0x01);
SiS_SetRegAND(SISCR, 0x32, ~0x06);
} else {
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8);
SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
} else if(temp1 == 0) {
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8);
SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
/* Set general purpose IO for Chrontel communication */
SiS_SetChrontelGPIO(&ivideo->SiS_Pr, 0x00);
#endif
} else {
#ifdef CONFIG_FB_SIS_315
ivideo->SiS_Pr.SiS_IF_DEF_CH70xx = 2; /* Chrontel 7019 */
temp1 = SiS_GetCH701x(&ivideo->SiS_Pr, 0x49);
SiS_SetCH701x(&ivideo->SiS_Pr, 0x49, 0x20);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
temp2 = SiS_GetCH701x(&ivideo->SiS_Pr, 0x20);
temp2 |= 0x01;
SiS_SetCH701x(&ivideo->SiS_Pr, 0x20, temp2);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
temp2 ^= 0x01;
SiS_SetCH701x(&ivideo->SiS_Pr, 0x20, temp2);
SiS_DDC2Delay(&ivideo->SiS_Pr, 0x96);
temp2 = SiS_GetCH701x(&ivideo->SiS_Pr, 0x20);
SiS_SetCH701x(&ivideo->SiS_Pr, 0x49, temp1);
temp1 = 0;
if(temp2 & 0x02) temp1 |= 0x01;
if(temp2 & 0x10) temp1 |= 0x01;
if(temp2 & 0x04) temp1 |= 0x02;
if( (temp1 & 0x01) && (temp1 & 0x02) ) temp1 = 0x04;
switch(temp1) {
case 0x01:
printk(KERN_INFO "%s CVBS output\n", stdstr);
ivideo->vbflags |= TV_AVIDEO;
SiS_SetRegOR(SISCR, 0x32, 0x01);
SiS_SetRegAND(SISCR, 0x32, ~0x06);
break;
case 0x02:
printk(KERN_INFO "%s SVIDEO output\n", stdstr);
ivideo->vbflags |= TV_SVIDEO;
SiS_SetRegOR(SISCR, 0x32, 0x02);
SiS_SetRegAND(SISCR, 0x32, ~0x05);
break;
case 0x04:
printk(KERN_INFO "%s SCART output\n", stdstr);
SiS_SetRegOR(SISCR, 0x32, 0x04);
SiS_SetRegAND(SISCR, 0x32, ~0x03);
break;
default:
SiS_SetRegAND(SISCR, 0x32, ~0x07);
}
#endif
}
}
static void sisfb_get_VB_type(struct sis_video_info *ivideo)
{
char stdstr[] = "sisfb: Detected";
char bridgestr[] = "video bridge";
u8 vb_chipid;
u8 reg;
/* No CRT2 on XGI Z7 */
if(ivideo->chip == XGI_20)
return;
vb_chipid = SiS_GetReg(SISPART4, 0x00);
switch(vb_chipid) {
case 0x01:
reg = SiS_GetReg(SISPART4, 0x01);
if(reg < 0xb0) {
ivideo->vbflags |= VB_301; /* Deprecated */
ivideo->vbflags2 |= VB2_301;
printk(KERN_INFO "%s SiS301 %s\n", stdstr, bridgestr);
} else if(reg < 0xc0) {
ivideo->vbflags |= VB_301B; /* Deprecated */
ivideo->vbflags2 |= VB2_301B;
reg = SiS_GetReg(SISPART4, 0x23);
if(!(reg & 0x02)) {
ivideo->vbflags |= VB_30xBDH; /* Deprecated */
ivideo->vbflags2 |= VB2_30xBDH;
printk(KERN_INFO "%s SiS301B-DH %s\n", stdstr, bridgestr);
} else {
printk(KERN_INFO "%s SiS301B %s\n", stdstr, bridgestr);
}
} else if(reg < 0xd0) {
ivideo->vbflags |= VB_301C; /* Deprecated */
ivideo->vbflags2 |= VB2_301C;
printk(KERN_INFO "%s SiS301C %s\n", stdstr, bridgestr);
} else if(reg < 0xe0) {
ivideo->vbflags |= VB_301LV; /* Deprecated */
ivideo->vbflags2 |= VB2_301LV;
printk(KERN_INFO "%s SiS301LV %s\n", stdstr, bridgestr);
} else if(reg <= 0xe1) {
reg = SiS_GetReg(SISPART4, 0x39);
if(reg == 0xff) {
ivideo->vbflags |= VB_302LV; /* Deprecated */
ivideo->vbflags2 |= VB2_302LV;
printk(KERN_INFO "%s SiS302LV %s\n", stdstr, bridgestr);
} else {
ivideo->vbflags |= VB_301C; /* Deprecated */
ivideo->vbflags2 |= VB2_301C;
printk(KERN_INFO "%s SiS301C(P4) %s\n", stdstr, bridgestr);
#if 0
ivideo->vbflags |= VB_302ELV; /* Deprecated */
ivideo->vbflags2 |= VB2_302ELV;
printk(KERN_INFO "%s SiS302ELV %s\n", stdstr, bridgestr);
#endif
}
}
break;
case 0x02:
ivideo->vbflags |= VB_302B; /* Deprecated */
ivideo->vbflags2 |= VB2_302B;
printk(KERN_INFO "%s SiS302B %s\n", stdstr, bridgestr);
break;
}
if((!(ivideo->vbflags2 & VB2_VIDEOBRIDGE)) && (ivideo->chip != SIS_300)) {
reg = SiS_GetReg(SISCR, 0x37);
reg &= SIS_EXTERNAL_CHIP_MASK;
reg >>= 1;
if(ivideo->sisvga_engine == SIS_300_VGA) {
#ifdef CONFIG_FB_SIS_300
switch(reg) {
case SIS_EXTERNAL_CHIP_LVDS:
ivideo->vbflags |= VB_LVDS; /* Deprecated */
ivideo->vbflags2 |= VB2_LVDS;
break;
case SIS_EXTERNAL_CHIP_TRUMPION:
ivideo->vbflags |= (VB_LVDS | VB_TRUMPION); /* Deprecated */
ivideo->vbflags2 |= (VB2_LVDS | VB2_TRUMPION);
break;
case SIS_EXTERNAL_CHIP_CHRONTEL:
ivideo->vbflags |= VB_CHRONTEL; /* Deprecated */
ivideo->vbflags2 |= VB2_CHRONTEL;
break;
case SIS_EXTERNAL_CHIP_LVDS_CHRONTEL:
ivideo->vbflags |= (VB_LVDS | VB_CHRONTEL); /* Deprecated */
ivideo->vbflags2 |= (VB2_LVDS | VB2_CHRONTEL);
break;
}
if(ivideo->vbflags2 & VB2_CHRONTEL) ivideo->chronteltype = 1;
#endif
} else if(ivideo->chip < SIS_661) {
#ifdef CONFIG_FB_SIS_315
switch (reg) {
case SIS310_EXTERNAL_CHIP_LVDS:
ivideo->vbflags |= VB_LVDS; /* Deprecated */
ivideo->vbflags2 |= VB2_LVDS;
break;
case SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL:
ivideo->vbflags |= (VB_LVDS | VB_CHRONTEL); /* Deprecated */
ivideo->vbflags2 |= (VB2_LVDS | VB2_CHRONTEL);
break;
}
if(ivideo->vbflags2 & VB2_CHRONTEL) ivideo->chronteltype = 2;
#endif
} else if(ivideo->chip >= SIS_661) {
#ifdef CONFIG_FB_SIS_315
reg = SiS_GetReg(SISCR, 0x38);
reg >>= 5;
switch(reg) {
case 0x02:
ivideo->vbflags |= VB_LVDS; /* Deprecated */
ivideo->vbflags2 |= VB2_LVDS;
break;
case 0x03:
ivideo->vbflags |= (VB_LVDS | VB_CHRONTEL); /* Deprecated */
ivideo->vbflags2 |= (VB2_LVDS | VB2_CHRONTEL);
break;
case 0x04:
ivideo->vbflags |= (VB_LVDS | VB_CONEXANT); /* Deprecated */
ivideo->vbflags2 |= (VB2_LVDS | VB2_CONEXANT);
break;
}
if(ivideo->vbflags2 & VB2_CHRONTEL) ivideo->chronteltype = 2;
#endif
}
if(ivideo->vbflags2 & VB2_LVDS) {
printk(KERN_INFO "%s LVDS transmitter\n", stdstr);
}
if((ivideo->sisvga_engine == SIS_300_VGA) && (ivideo->vbflags2 & VB2_TRUMPION)) {
printk(KERN_INFO "%s Trumpion Zurac LCD scaler\n", stdstr);
}
if(ivideo->vbflags2 & VB2_CHRONTEL) {
printk(KERN_INFO "%s Chrontel TV encoder\n", stdstr);
}
if((ivideo->chip >= SIS_661) && (ivideo->vbflags2 & VB2_CONEXANT)) {
printk(KERN_INFO "%s Conexant external device\n", stdstr);
}
}
if(ivideo->vbflags2 & VB2_SISBRIDGE) {
SiS_SenseLCD(ivideo);
SiS_Sense30x(ivideo);
} else if(ivideo->vbflags2 & VB2_CHRONTEL) {
SiS_SenseCh(ivideo);
}
}
/* ---------- Engine initialization routines ------------ */
static void
sisfb_engine_init(struct sis_video_info *ivideo)
{
/* Initialize command queue (we use MMIO only) */
/* BEFORE THIS IS CALLED, THE ENGINES *MUST* BE SYNC'ED */
ivideo->caps &= ~(TURBO_QUEUE_CAP |
MMIO_CMD_QUEUE_CAP |
VM_CMD_QUEUE_CAP |
AGP_CMD_QUEUE_CAP);
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
u32 tqueue_pos;
u8 tq_state;
tqueue_pos = (ivideo->video_size - ivideo->cmdQueueSize) / (64 * 1024);
tq_state = SiS_GetReg(SISSR, IND_SIS_TURBOQUEUE_SET);
tq_state |= 0xf0;
tq_state &= 0xfc;
tq_state |= (u8)(tqueue_pos >> 8);
SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_SET, tq_state);
SiS_SetReg(SISSR, IND_SIS_TURBOQUEUE_ADR, (u8)(tqueue_pos & 0xff));
ivideo->caps |= TURBO_QUEUE_CAP;
}
#endif
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
u32 tempq = 0, templ;
u8 temp;
if(ivideo->chip == XGI_20) {
switch(ivideo->cmdQueueSize) {
case (64 * 1024):
temp = SIS_CMD_QUEUE_SIZE_Z7_64k;
break;
case (128 * 1024):
default:
temp = SIS_CMD_QUEUE_SIZE_Z7_128k;
}
} else {
switch(ivideo->cmdQueueSize) {
case (4 * 1024 * 1024):
temp = SIS_CMD_QUEUE_SIZE_4M;
break;
case (2 * 1024 * 1024):
temp = SIS_CMD_QUEUE_SIZE_2M;
break;
case (1 * 1024 * 1024):
temp = SIS_CMD_QUEUE_SIZE_1M;
break;
default:
case (512 * 1024):
temp = SIS_CMD_QUEUE_SIZE_512k;
}
}
SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_THRESHOLD, COMMAND_QUEUE_THRESHOLD);
SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
if((ivideo->chip >= XGI_40) && ivideo->modechanged) {
/* Must disable dual pipe on XGI_40. Can't do
* this in MMIO mode, because it requires
* setting/clearing a bit in the MMIO fire trigger
* register.
*/
if(!((templ = MMIO_IN32(ivideo->mmio_vbase, 0x8240)) & (1 << 10))) {
MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, 0);
SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, (temp | SIS_VRAM_CMDQUEUE_ENABLE));
tempq = MMIO_IN32(ivideo->mmio_vbase, Q_READ_PTR);
MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, tempq);
tempq = (u32)(ivideo->video_size - ivideo->cmdQueueSize);
MMIO_OUT32(ivideo->mmio_vbase, Q_BASE_ADDR, tempq);
writel(0x16800000 + 0x8240, ivideo->video_vbase + tempq);
writel(templ | (1 << 10), ivideo->video_vbase + tempq + 4);
writel(0x168F0000, ivideo->video_vbase + tempq + 8);
writel(0x168F0000, ivideo->video_vbase + tempq + 12);
MMIO_OUT32(ivideo->mmio_vbase, Q_WRITE_PTR, (tempq + 16));
sisfb_syncaccel(ivideo);
SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, SIS_CMD_QUEUE_RESET);
}
}
tempq = MMIO_IN32(ivideo->mmio_vbase, MMIO_QUEUE_READPORT);
MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_WRITEPORT, tempq);
temp |= (SIS_MMIO_CMD_ENABLE | SIS_CMD_AUTO_CORR);
SiS_SetReg(SISSR, IND_SIS_CMDQUEUE_SET, temp);
tempq = (u32)(ivideo->video_size - ivideo->cmdQueueSize);
MMIO_OUT32(ivideo->mmio_vbase, MMIO_QUEUE_PHYBASE, tempq);
ivideo->caps |= MMIO_CMD_QUEUE_CAP;
}
#endif
ivideo->engineok = 1;
}
static void sisfb_detect_lcd_type(struct sis_video_info *ivideo)
{
u8 reg;
int i;
reg = SiS_GetReg(SISCR, 0x36);
reg &= 0x0f;
if(ivideo->sisvga_engine == SIS_300_VGA) {
ivideo->CRT2LCDType = sis300paneltype[reg];
} else if(ivideo->chip >= SIS_661) {
ivideo->CRT2LCDType = sis661paneltype[reg];
} else {
ivideo->CRT2LCDType = sis310paneltype[reg];
if((ivideo->chip == SIS_550) && (sisfb_fstn)) {
if((ivideo->CRT2LCDType != LCD_320x240_2) &&
(ivideo->CRT2LCDType != LCD_320x240_3)) {
ivideo->CRT2LCDType = LCD_320x240;
}
}
}
if(ivideo->CRT2LCDType == LCD_UNKNOWN) {
/* For broken BIOSes: Assume 1024x768, RGB18 */
ivideo->CRT2LCDType = LCD_1024x768;
SiS_SetRegANDOR(SISCR, 0x36, 0xf0, 0x02);
SiS_SetRegANDOR(SISCR, 0x37, 0xee, 0x01);
printk(KERN_DEBUG "sisfb: Invalid panel ID (%02x), assuming 1024x768, RGB18\n", reg);
}
for(i = 0; i < SIS_LCD_NUMBER; i++) {
if(ivideo->CRT2LCDType == sis_lcd_data[i].lcdtype) {
ivideo->lcdxres = sis_lcd_data[i].xres;
ivideo->lcdyres = sis_lcd_data[i].yres;
ivideo->lcddefmodeidx = sis_lcd_data[i].default_mode_idx;
break;
}
}
#ifdef CONFIG_FB_SIS_300
if(ivideo->SiS_Pr.SiS_CustomT == CUT_BARCO1366) {
ivideo->lcdxres = 1360; ivideo->lcdyres = 1024;
ivideo->lcddefmodeidx = DEFAULT_MODE_1360;
} else if(ivideo->SiS_Pr.SiS_CustomT == CUT_PANEL848) {
ivideo->lcdxres = 848; ivideo->lcdyres = 480;
ivideo->lcddefmodeidx = DEFAULT_MODE_848;
} else if(ivideo->SiS_Pr.SiS_CustomT == CUT_PANEL856) {
ivideo->lcdxres = 856; ivideo->lcdyres = 480;
ivideo->lcddefmodeidx = DEFAULT_MODE_856;
}
#endif
printk(KERN_DEBUG "sisfb: Detected %dx%d flat panel\n",
ivideo->lcdxres, ivideo->lcdyres);
}
static void sisfb_save_pdc_emi(struct sis_video_info *ivideo)
{
#ifdef CONFIG_FB_SIS_300
/* Save the current PanelDelayCompensation if the LCD is currently used */
if(ivideo->sisvga_engine == SIS_300_VGA) {
if(ivideo->vbflags2 & (VB2_LVDS | VB2_30xBDH)) {
int tmp;
tmp = SiS_GetReg(SISCR, 0x30);
if(tmp & 0x20) {
/* Currently on LCD? If yes, read current pdc */
ivideo->detectedpdc = SiS_GetReg(SISPART1, 0x13);
ivideo->detectedpdc &= 0x3c;
if(ivideo->SiS_Pr.PDC == -1) {
/* Let option override detection */
ivideo->SiS_Pr.PDC = ivideo->detectedpdc;
}
printk(KERN_INFO "sisfb: Detected LCD PDC 0x%02x\n",
ivideo->detectedpdc);
}
if((ivideo->SiS_Pr.PDC != -1) &&
(ivideo->SiS_Pr.PDC != ivideo->detectedpdc)) {
printk(KERN_INFO "sisfb: Using LCD PDC 0x%02x\n",
ivideo->SiS_Pr.PDC);
}
}
}
#endif
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
/* Try to find about LCDA */
if(ivideo->vbflags2 & VB2_SISLCDABRIDGE) {
int tmp;
tmp = SiS_GetReg(SISPART1, 0x13);
if(tmp & 0x04) {
ivideo->SiS_Pr.SiS_UseLCDA = true;
ivideo->detectedlcda = 0x03;
}
}
/* Save PDC */
if(ivideo->vbflags2 & VB2_SISLVDSBRIDGE) {
int tmp;
tmp = SiS_GetReg(SISCR, 0x30);
if((tmp & 0x20) || (ivideo->detectedlcda != 0xff)) {
/* Currently on LCD? If yes, read current pdc */
u8 pdc;
pdc = SiS_GetReg(SISPART1, 0x2D);
ivideo->detectedpdc = (pdc & 0x0f) << 1;
ivideo->detectedpdca = (pdc & 0xf0) >> 3;
pdc = SiS_GetReg(SISPART1, 0x35);
ivideo->detectedpdc |= ((pdc >> 7) & 0x01);
pdc = SiS_GetReg(SISPART1, 0x20);
ivideo->detectedpdca |= ((pdc >> 6) & 0x01);
if(ivideo->newrom) {
/* New ROM invalidates other PDC resp. */
if(ivideo->detectedlcda != 0xff) {
ivideo->detectedpdc = 0xff;
} else {
ivideo->detectedpdca = 0xff;
}
}
if(ivideo->SiS_Pr.PDC == -1) {
if(ivideo->detectedpdc != 0xff) {
ivideo->SiS_Pr.PDC = ivideo->detectedpdc;
}
}
if(ivideo->SiS_Pr.PDCA == -1) {
if(ivideo->detectedpdca != 0xff) {
ivideo->SiS_Pr.PDCA = ivideo->detectedpdca;
}
}
if(ivideo->detectedpdc != 0xff) {
printk(KERN_INFO
"sisfb: Detected LCD PDC 0x%02x (for LCD=CRT2)\n",
ivideo->detectedpdc);
}
if(ivideo->detectedpdca != 0xff) {
printk(KERN_INFO
"sisfb: Detected LCD PDC1 0x%02x (for LCD=CRT1)\n",
ivideo->detectedpdca);
}
}
/* Save EMI */
if(ivideo->vbflags2 & VB2_SISEMIBRIDGE) {
ivideo->SiS_Pr.EMI_30 = SiS_GetReg(SISPART4, 0x30);
ivideo->SiS_Pr.EMI_31 = SiS_GetReg(SISPART4, 0x31);
ivideo->SiS_Pr.EMI_32 = SiS_GetReg(SISPART4, 0x32);
ivideo->SiS_Pr.EMI_33 = SiS_GetReg(SISPART4, 0x33);
ivideo->SiS_Pr.HaveEMI = true;
if((tmp & 0x20) || (ivideo->detectedlcda != 0xff)) {
ivideo->SiS_Pr.HaveEMILCD = true;
}
}
}
/* Let user override detected PDCs (all bridges) */
if(ivideo->vbflags2 & VB2_30xBLV) {
if((ivideo->SiS_Pr.PDC != -1) &&
(ivideo->SiS_Pr.PDC != ivideo->detectedpdc)) {
printk(KERN_INFO "sisfb: Using LCD PDC 0x%02x (for LCD=CRT2)\n",
ivideo->SiS_Pr.PDC);
}
if((ivideo->SiS_Pr.PDCA != -1) &&
(ivideo->SiS_Pr.PDCA != ivideo->detectedpdca)) {
printk(KERN_INFO "sisfb: Using LCD PDC1 0x%02x (for LCD=CRT1)\n",
ivideo->SiS_Pr.PDCA);
}
}
}
#endif
}
/* -------------------- Memory manager routines ---------------------- */
static u32 sisfb_getheapstart(struct sis_video_info *ivideo)
{
u32 ret = ivideo->sisfb_parm_mem * 1024;
u32 maxoffs = ivideo->video_size - ivideo->hwcursor_size - ivideo->cmdQueueSize;
u32 def;
/* Calculate heap start = end of memory for console
*
* CCCCCCCCDDDDDDDDDDDDDDDDDDDDDDDDDDDDHHHHQQQQQQQQQQ
* C = console, D = heap, H = HWCursor, Q = cmd-queue
*
* On 76x in UMA+LFB mode, the layout is as follows:
* DDDDDDDDDDDCCCCCCCCCCCCCCCCCCCCCCCCHHHHQQQQQQQQQQQ
* where the heap is the entire UMA area, eventually
* into the LFB area if the given mem parameter is
* higher than the size of the UMA memory.
*
* Basically given by "mem" parameter
*
* maximum = videosize - cmd_queue - hwcursor
* (results in a heap of size 0)
* default = SiS 300: depends on videosize
* SiS 315/330/340/XGI: 32k below max
*/
if(ivideo->sisvga_engine == SIS_300_VGA) {
if(ivideo->video_size > 0x1000000) {
def = 0xc00000;
} else if(ivideo->video_size > 0x800000) {
def = 0x800000;
} else {
def = 0x400000;
}
} else if(ivideo->UMAsize && ivideo->LFBsize) {
ret = def = 0;
} else {
def = maxoffs - 0x8000;
}
/* Use default for secondary card for now (FIXME) */
if((!ret) || (ret > maxoffs) || (ivideo->cardnumber != 0))
ret = def;
return ret;
}
static u32 sisfb_getheapsize(struct sis_video_info *ivideo)
{
u32 max = ivideo->video_size - ivideo->hwcursor_size - ivideo->cmdQueueSize;
u32 ret = 0;
if(ivideo->UMAsize && ivideo->LFBsize) {
if( (!ivideo->sisfb_parm_mem) ||
((ivideo->sisfb_parm_mem * 1024) > max) ||
((max - (ivideo->sisfb_parm_mem * 1024)) < ivideo->UMAsize) ) {
ret = ivideo->UMAsize;
max -= ivideo->UMAsize;
} else {
ret = max - (ivideo->sisfb_parm_mem * 1024);
max = ivideo->sisfb_parm_mem * 1024;
}
ivideo->video_offset = ret;
ivideo->sisfb_mem = max;
} else {
ret = max - ivideo->heapstart;
ivideo->sisfb_mem = ivideo->heapstart;
}
return ret;
}
static int sisfb_heap_init(struct sis_video_info *ivideo)
{
struct SIS_OH *poh;
ivideo->video_offset = 0;
if(ivideo->sisfb_parm_mem) {
if( (ivideo->sisfb_parm_mem < (2 * 1024 * 1024)) ||
(ivideo->sisfb_parm_mem > ivideo->video_size) ) {
ivideo->sisfb_parm_mem = 0;
}
}
ivideo->heapstart = sisfb_getheapstart(ivideo);
ivideo->sisfb_heap_size = sisfb_getheapsize(ivideo);
ivideo->sisfb_heap_start = ivideo->video_vbase + ivideo->heapstart;
ivideo->sisfb_heap_end = ivideo->sisfb_heap_start + ivideo->sisfb_heap_size;
printk(KERN_INFO "sisfb: Memory heap starting at %dK, size %dK\n",
(int)(ivideo->heapstart / 1024), (int)(ivideo->sisfb_heap_size / 1024));
ivideo->sisfb_heap.vinfo = ivideo;
ivideo->sisfb_heap.poha_chain = NULL;
ivideo->sisfb_heap.poh_freelist = NULL;
poh = sisfb_poh_new_node(&ivideo->sisfb_heap);
if(poh == NULL)
return 1;
poh->poh_next = &ivideo->sisfb_heap.oh_free;
poh->poh_prev = &ivideo->sisfb_heap.oh_free;
poh->size = ivideo->sisfb_heap_size;
poh->offset = ivideo->heapstart;
ivideo->sisfb_heap.oh_free.poh_next = poh;
ivideo->sisfb_heap.oh_free.poh_prev = poh;
ivideo->sisfb_heap.oh_free.size = 0;
ivideo->sisfb_heap.max_freesize = poh->size;
ivideo->sisfb_heap.oh_used.poh_next = &ivideo->sisfb_heap.oh_used;
ivideo->sisfb_heap.oh_used.poh_prev = &ivideo->sisfb_heap.oh_used;
ivideo->sisfb_heap.oh_used.size = SENTINEL;
if(ivideo->cardnumber == 0) {
/* For the first card, make this heap the "global" one
* for old DRM (which could handle only one card)
*/
sisfb_heap = &ivideo->sisfb_heap;
}
return 0;
}
static struct SIS_OH *
sisfb_poh_new_node(struct SIS_HEAP *memheap)
{
struct SIS_OHALLOC *poha;
struct SIS_OH *poh;
unsigned long cOhs;
int i;
if(memheap->poh_freelist == NULL) {
poha = kmalloc(SIS_OH_ALLOC_SIZE, GFP_KERNEL);
if(!poha)
return NULL;
poha->poha_next = memheap->poha_chain;
memheap->poha_chain = poha;
cOhs = (SIS_OH_ALLOC_SIZE - sizeof(struct SIS_OHALLOC)) / sizeof(struct SIS_OH) + 1;
poh = &poha->aoh[0];
for(i = cOhs - 1; i != 0; i--) {
poh->poh_next = poh + 1;
poh = poh + 1;
}
poh->poh_next = NULL;
memheap->poh_freelist = &poha->aoh[0];
}
poh = memheap->poh_freelist;
memheap->poh_freelist = poh->poh_next;
return poh;
}
static struct SIS_OH *
sisfb_poh_allocate(struct SIS_HEAP *memheap, u32 size)
{
struct SIS_OH *pohThis;
struct SIS_OH *pohRoot;
int bAllocated = 0;
if(size > memheap->max_freesize) {
DPRINTK("sisfb: Can't allocate %dk video memory\n",
(unsigned int) size / 1024);
return NULL;
}
pohThis = memheap->oh_free.poh_next;
while(pohThis != &memheap->oh_free) {
if(size <= pohThis->size) {
bAllocated = 1;
break;
}
pohThis = pohThis->poh_next;
}
if(!bAllocated) {
DPRINTK("sisfb: Can't allocate %dk video memory\n",
(unsigned int) size / 1024);
return NULL;
}
if(size == pohThis->size) {
pohRoot = pohThis;
sisfb_delete_node(pohThis);
} else {
pohRoot = sisfb_poh_new_node(memheap);
if(pohRoot == NULL)
return NULL;
pohRoot->offset = pohThis->offset;
pohRoot->size = size;
pohThis->offset += size;
pohThis->size -= size;
}
memheap->max_freesize -= size;
pohThis = &memheap->oh_used;
sisfb_insert_node(pohThis, pohRoot);
return pohRoot;
}
static void
sisfb_delete_node(struct SIS_OH *poh)
{
poh->poh_prev->poh_next = poh->poh_next;
poh->poh_next->poh_prev = poh->poh_prev;
}
static void
sisfb_insert_node(struct SIS_OH *pohList, struct SIS_OH *poh)
{
struct SIS_OH *pohTemp = pohList->poh_next;
pohList->poh_next = poh;
pohTemp->poh_prev = poh;
poh->poh_prev = pohList;
poh->poh_next = pohTemp;
}
static struct SIS_OH *
sisfb_poh_free(struct SIS_HEAP *memheap, u32 base)
{
struct SIS_OH *pohThis;
struct SIS_OH *poh_freed;
struct SIS_OH *poh_prev;
struct SIS_OH *poh_next;
u32 ulUpper;
u32 ulLower;
int foundNode = 0;
poh_freed = memheap->oh_used.poh_next;
while(poh_freed != &memheap->oh_used) {
if(poh_freed->offset == base) {
foundNode = 1;
break;
}
poh_freed = poh_freed->poh_next;
}
if(!foundNode)
return NULL;
memheap->max_freesize += poh_freed->size;
poh_prev = poh_next = NULL;
ulUpper = poh_freed->offset + poh_freed->size;
ulLower = poh_freed->offset;
pohThis = memheap->oh_free.poh_next;
while(pohThis != &memheap->oh_free) {
if(pohThis->offset == ulUpper) {
poh_next = pohThis;
} else if((pohThis->offset + pohThis->size) == ulLower) {
poh_prev = pohThis;
}
pohThis = pohThis->poh_next;
}
sisfb_delete_node(poh_freed);
if(poh_prev && poh_next) {
poh_prev->size += (poh_freed->size + poh_next->size);
sisfb_delete_node(poh_next);
sisfb_free_node(memheap, poh_freed);
sisfb_free_node(memheap, poh_next);
return poh_prev;
}
if(poh_prev) {
poh_prev->size += poh_freed->size;
sisfb_free_node(memheap, poh_freed);
return poh_prev;
}
if(poh_next) {
poh_next->size += poh_freed->size;
poh_next->offset = poh_freed->offset;
sisfb_free_node(memheap, poh_freed);
return poh_next;
}
sisfb_insert_node(&memheap->oh_free, poh_freed);
return poh_freed;
}
static void
sisfb_free_node(struct SIS_HEAP *memheap, struct SIS_OH *poh)
{
if(poh == NULL)
return;
poh->poh_next = memheap->poh_freelist;
memheap->poh_freelist = poh;
}
static void
sis_int_malloc(struct sis_video_info *ivideo, struct sis_memreq *req)
{
struct SIS_OH *poh = NULL;
if((ivideo) && (ivideo->sisfb_id == SISFB_ID) && (!ivideo->havenoheap))
poh = sisfb_poh_allocate(&ivideo->sisfb_heap, (u32)req->size);
if(poh == NULL) {
req->offset = req->size = 0;
DPRINTK("sisfb: Video RAM allocation failed\n");
} else {
req->offset = poh->offset;
req->size = poh->size;
DPRINTK("sisfb: Video RAM allocation succeeded: 0x%lx\n",
(poh->offset + ivideo->video_vbase));
}
}
void
sis_malloc(struct sis_memreq *req)
{
struct sis_video_info *ivideo = sisfb_heap->vinfo;
if(&ivideo->sisfb_heap == sisfb_heap)
sis_int_malloc(ivideo, req);
else
req->offset = req->size = 0;
}
void
sis_malloc_new(struct pci_dev *pdev, struct sis_memreq *req)
{
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
sis_int_malloc(ivideo, req);
}
/* sis_free: u32 because "base" is offset inside video ram, can never be >4GB */
static void
sis_int_free(struct sis_video_info *ivideo, u32 base)
{
struct SIS_OH *poh;
if((!ivideo) || (ivideo->sisfb_id != SISFB_ID) || (ivideo->havenoheap))
return;
poh = sisfb_poh_free(&ivideo->sisfb_heap, base);
if(poh == NULL) {
DPRINTK("sisfb: sisfb_poh_free() failed at base 0x%x\n",
(unsigned int) base);
}
}
void
sis_free(u32 base)
{
struct sis_video_info *ivideo = sisfb_heap->vinfo;
sis_int_free(ivideo, base);
}
void
sis_free_new(struct pci_dev *pdev, u32 base)
{
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
sis_int_free(ivideo, base);
}
/* --------------------- SetMode routines ------------------------- */
static void
sisfb_check_engine_and_sync(struct sis_video_info *ivideo)
{
u8 cr30, cr31;
/* Check if MMIO and engines are enabled,
* and sync in case they are. Can't use
* ivideo->accel here, as this might have
* been changed before this is called.
*/
cr30 = SiS_GetReg(SISSR, IND_SIS_PCI_ADDRESS_SET);
cr31 = SiS_GetReg(SISSR, IND_SIS_MODULE_ENABLE);
/* MMIO and 2D/3D engine enabled? */
if((cr30 & SIS_MEM_MAP_IO_ENABLE) && (cr31 & 0x42)) {
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
/* Don't care about TurboQueue. It's
* enough to know that the engines
* are enabled
*/
sisfb_syncaccel(ivideo);
}
#endif
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
/* Check that any queue mode is
* enabled, and that the queue
* is not in the state of "reset"
*/
cr30 = SiS_GetReg(SISSR, 0x26);
if((cr30 & 0xe0) && (!(cr30 & 0x01))) {
sisfb_syncaccel(ivideo);
}
}
#endif
}
}
static void
sisfb_pre_setmode(struct sis_video_info *ivideo)
{
u8 cr30 = 0, cr31 = 0, cr33 = 0, cr35 = 0, cr38 = 0;
int tvregnum = 0;
ivideo->currentvbflags &= (VB_VIDEOBRIDGE | VB_DISPTYPE_DISP2);
SiS_SetReg(SISSR, 0x05, 0x86);
cr31 = SiS_GetReg(SISCR, 0x31);
cr31 &= ~0x60;
cr31 |= 0x04;
cr33 = ivideo->rate_idx & 0x0F;
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
if(ivideo->chip >= SIS_661) {
cr38 = SiS_GetReg(SISCR, 0x38);
cr38 &= ~0x07; /* Clear LCDA/DualEdge and YPbPr bits */
} else {
tvregnum = 0x38;
cr38 = SiS_GetReg(SISCR, tvregnum);
cr38 &= ~0x3b; /* Clear LCDA/DualEdge and YPbPr bits */
}
}
#endif
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
tvregnum = 0x35;
cr38 = SiS_GetReg(SISCR, tvregnum);
}
#endif
SiS_SetEnableDstn(&ivideo->SiS_Pr, false);
SiS_SetEnableFstn(&ivideo->SiS_Pr, false);
ivideo->curFSTN = ivideo->curDSTN = 0;
switch(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
case CRT2_TV:
cr38 &= ~0xc0; /* Clear PAL-M / PAL-N bits */
if((ivideo->vbflags & TV_YPBPR) && (ivideo->vbflags2 & VB2_SISYPBPRBRIDGE)) {
#ifdef CONFIG_FB_SIS_315
if(ivideo->chip >= SIS_661) {
cr38 |= 0x04;
if(ivideo->vbflags & TV_YPBPR525P) cr35 |= 0x20;
else if(ivideo->vbflags & TV_YPBPR750P) cr35 |= 0x40;
else if(ivideo->vbflags & TV_YPBPR1080I) cr35 |= 0x60;
cr30 |= SIS_SIMULTANEOUS_VIEW_ENABLE;
cr35 &= ~0x01;
ivideo->currentvbflags |= (TV_YPBPR | (ivideo->vbflags & TV_YPBPRALL));
} else if(ivideo->sisvga_engine == SIS_315_VGA) {
cr30 |= (0x80 | SIS_SIMULTANEOUS_VIEW_ENABLE);
cr38 |= 0x08;
if(ivideo->vbflags & TV_YPBPR525P) cr38 |= 0x10;
else if(ivideo->vbflags & TV_YPBPR750P) cr38 |= 0x20;
else if(ivideo->vbflags & TV_YPBPR1080I) cr38 |= 0x30;
cr31 &= ~0x01;
ivideo->currentvbflags |= (TV_YPBPR | (ivideo->vbflags & TV_YPBPRALL));
}
#endif
} else if((ivideo->vbflags & TV_HIVISION) &&
(ivideo->vbflags2 & VB2_SISHIVISIONBRIDGE)) {
if(ivideo->chip >= SIS_661) {
cr38 |= 0x04;
cr35 |= 0x60;
} else {
cr30 |= 0x80;
}
cr30 |= SIS_SIMULTANEOUS_VIEW_ENABLE;
cr31 |= 0x01;
cr35 |= 0x01;
ivideo->currentvbflags |= TV_HIVISION;
} else if(ivideo->vbflags & TV_SCART) {
cr30 = (SIS_VB_OUTPUT_SCART | SIS_SIMULTANEOUS_VIEW_ENABLE);
cr31 |= 0x01;
cr35 |= 0x01;
ivideo->currentvbflags |= TV_SCART;
} else {
if(ivideo->vbflags & TV_SVIDEO) {
cr30 = (SIS_VB_OUTPUT_SVIDEO | SIS_SIMULTANEOUS_VIEW_ENABLE);
ivideo->currentvbflags |= TV_SVIDEO;
}
if(ivideo->vbflags & TV_AVIDEO) {
cr30 = (SIS_VB_OUTPUT_COMPOSITE | SIS_SIMULTANEOUS_VIEW_ENABLE);
ivideo->currentvbflags |= TV_AVIDEO;
}
}
cr31 |= SIS_DRIVER_MODE;
if(ivideo->vbflags & (TV_AVIDEO | TV_SVIDEO)) {
if(ivideo->vbflags & TV_PAL) {
cr31 |= 0x01; cr35 |= 0x01;
ivideo->currentvbflags |= TV_PAL;
if(ivideo->vbflags & TV_PALM) {
cr38 |= 0x40; cr35 |= 0x04;
ivideo->currentvbflags |= TV_PALM;
} else if(ivideo->vbflags & TV_PALN) {
cr38 |= 0x80; cr35 |= 0x08;
ivideo->currentvbflags |= TV_PALN;
}
} else {
cr31 &= ~0x01; cr35 &= ~0x01;
ivideo->currentvbflags |= TV_NTSC;
if(ivideo->vbflags & TV_NTSCJ) {
cr38 |= 0x40; cr35 |= 0x02;
ivideo->currentvbflags |= TV_NTSCJ;
}
}
}
break;
case CRT2_LCD:
cr30 = (SIS_VB_OUTPUT_LCD | SIS_SIMULTANEOUS_VIEW_ENABLE);
cr31 |= SIS_DRIVER_MODE;
SiS_SetEnableDstn(&ivideo->SiS_Pr, ivideo->sisfb_dstn);
SiS_SetEnableFstn(&ivideo->SiS_Pr, ivideo->sisfb_fstn);
ivideo->curFSTN = ivideo->sisfb_fstn;
ivideo->curDSTN = ivideo->sisfb_dstn;
break;
case CRT2_VGA:
cr30 = (SIS_VB_OUTPUT_CRT2 | SIS_SIMULTANEOUS_VIEW_ENABLE);
cr31 |= SIS_DRIVER_MODE;
if(ivideo->sisfb_nocrt2rate) {
cr33 |= (sisbios_mode[ivideo->sisfb_mode_idx].rate_idx << 4);
} else {
cr33 |= ((ivideo->rate_idx & 0x0F) << 4);
}
break;
default: /* disable CRT2 */
cr30 = 0x00;
cr31 |= (SIS_DRIVER_MODE | SIS_VB_OUTPUT_DISABLE);
}
SiS_SetReg(SISCR, 0x30, cr30);
SiS_SetReg(SISCR, 0x33, cr33);
if(ivideo->chip >= SIS_661) {
#ifdef CONFIG_FB_SIS_315
cr31 &= ~0x01; /* Clear PAL flag (now in CR35) */
SiS_SetRegANDOR(SISCR, 0x35, ~0x10, cr35); /* Leave overscan bit alone */
cr38 &= 0x07; /* Use only LCDA and HiVision/YPbPr bits */
SiS_SetRegANDOR(SISCR, 0x38, 0xf8, cr38);
#endif
} else if(ivideo->chip != SIS_300) {
SiS_SetReg(SISCR, tvregnum, cr38);
}
SiS_SetReg(SISCR, 0x31, cr31);
ivideo->SiS_Pr.SiS_UseOEM = ivideo->sisfb_useoem;
sisfb_check_engine_and_sync(ivideo);
}
/* Fix SR11 for 661 and later */
#ifdef CONFIG_FB_SIS_315
static void
sisfb_fixup_SR11(struct sis_video_info *ivideo)
{
u8 tmpreg;
if(ivideo->chip >= SIS_661) {
tmpreg = SiS_GetReg(SISSR, 0x11);
if(tmpreg & 0x20) {
tmpreg = SiS_GetReg(SISSR, 0x3e);
tmpreg = (tmpreg + 1) & 0xff;
SiS_SetReg(SISSR, 0x3e, tmpreg);
tmpreg = SiS_GetReg(SISSR, 0x11);
}
if(tmpreg & 0xf0) {
SiS_SetRegAND(SISSR, 0x11, 0x0f);
}
}
}
#endif
static void
sisfb_set_TVxposoffset(struct sis_video_info *ivideo, int val)
{
if(val > 32) val = 32;
if(val < -32) val = -32;
ivideo->tvxpos = val;
if(ivideo->sisfblocked) return;
if(!ivideo->modechanged) return;
if(ivideo->currentvbflags & CRT2_TV) {
if(ivideo->vbflags2 & VB2_CHRONTEL) {
int x = ivideo->tvx;
switch(ivideo->chronteltype) {
case 1:
x += val;
if(x < 0) x = 0;
SiS_SetReg(SISSR, 0x05, 0x86);
SiS_SetCH700x(&ivideo->SiS_Pr, 0x0a, (x & 0xff));
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((x & 0x0100) >> 7), 0xFD);
break;
case 2:
/* Not supported by hardware */
break;
}
} else if(ivideo->vbflags2 & VB2_SISBRIDGE) {
u8 p2_1f,p2_20,p2_2b,p2_42,p2_43;
unsigned short temp;
p2_1f = ivideo->p2_1f;
p2_20 = ivideo->p2_20;
p2_2b = ivideo->p2_2b;
p2_42 = ivideo->p2_42;
p2_43 = ivideo->p2_43;
temp = p2_1f | ((p2_20 & 0xf0) << 4);
temp += (val * 2);
p2_1f = temp & 0xff;
p2_20 = (temp & 0xf00) >> 4;
p2_2b = ((p2_2b & 0x0f) + (val * 2)) & 0x0f;
temp = p2_43 | ((p2_42 & 0xf0) << 4);
temp += (val * 2);
p2_43 = temp & 0xff;
p2_42 = (temp & 0xf00) >> 4;
SiS_SetReg(SISPART2, 0x1f, p2_1f);
SiS_SetRegANDOR(SISPART2, 0x20, 0x0F, p2_20);
SiS_SetRegANDOR(SISPART2, 0x2b, 0xF0, p2_2b);
SiS_SetRegANDOR(SISPART2, 0x42, 0x0F, p2_42);
SiS_SetReg(SISPART2, 0x43, p2_43);
}
}
}
static void
sisfb_set_TVyposoffset(struct sis_video_info *ivideo, int val)
{
if(val > 32) val = 32;
if(val < -32) val = -32;
ivideo->tvypos = val;
if(ivideo->sisfblocked) return;
if(!ivideo->modechanged) return;
if(ivideo->currentvbflags & CRT2_TV) {
if(ivideo->vbflags2 & VB2_CHRONTEL) {
int y = ivideo->tvy;
switch(ivideo->chronteltype) {
case 1:
y -= val;
if(y < 0) y = 0;
SiS_SetReg(SISSR, 0x05, 0x86);
SiS_SetCH700x(&ivideo->SiS_Pr, 0x0b, (y & 0xff));
SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x08, ((y & 0x0100) >> 8), 0xFE);
break;
case 2:
/* Not supported by hardware */
break;
}
} else if(ivideo->vbflags2 & VB2_SISBRIDGE) {
char p2_01, p2_02;
val /= 2;
p2_01 = ivideo->p2_01;
p2_02 = ivideo->p2_02;
p2_01 += val;
p2_02 += val;
if(!(ivideo->currentvbflags & (TV_HIVISION | TV_YPBPR))) {
while((p2_01 <= 0) || (p2_02 <= 0)) {
p2_01 += 2;
p2_02 += 2;
}
}
SiS_SetReg(SISPART2, 0x01, p2_01);
SiS_SetReg(SISPART2, 0x02, p2_02);
}
}
}
static void
sisfb_post_setmode(struct sis_video_info *ivideo)
{
bool crt1isoff = false;
bool doit = true;
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
u8 reg;
#endif
#ifdef CONFIG_FB_SIS_315
u8 reg1;
#endif
SiS_SetReg(SISSR, 0x05, 0x86);
#ifdef CONFIG_FB_SIS_315
sisfb_fixup_SR11(ivideo);
#endif
/* Now we actually HAVE changed the display mode */
ivideo->modechanged = 1;
/* We can't switch off CRT1 if bridge is in slave mode */
if(ivideo->vbflags2 & VB2_VIDEOBRIDGE) {
if(sisfb_bridgeisslave(ivideo)) doit = false;
} else
ivideo->sisfb_crt1off = 0;
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
if((ivideo->sisfb_crt1off) && (doit)) {
crt1isoff = true;
reg = 0x00;
} else {
crt1isoff = false;
reg = 0x80;
}
SiS_SetRegANDOR(SISCR, 0x17, 0x7f, reg);
}
#endif
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
if((ivideo->sisfb_crt1off) && (doit)) {
crt1isoff = true;
reg = 0x40;
reg1 = 0xc0;
} else {
crt1isoff = false;
reg = 0x00;
reg1 = 0x00;
}
SiS_SetRegANDOR(SISCR, ivideo->SiS_Pr.SiS_MyCR63, ~0x40, reg);
SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, reg1);
}
#endif
if(crt1isoff) {
ivideo->currentvbflags &= ~VB_DISPTYPE_CRT1;
ivideo->currentvbflags |= VB_SINGLE_MODE;
} else {
ivideo->currentvbflags |= VB_DISPTYPE_CRT1;
if(ivideo->currentvbflags & VB_DISPTYPE_CRT2) {
ivideo->currentvbflags |= VB_MIRROR_MODE;
} else {
ivideo->currentvbflags |= VB_SINGLE_MODE;
}
}
SiS_SetRegAND(SISSR, IND_SIS_RAMDAC_CONTROL, ~0x04);
if(ivideo->currentvbflags & CRT2_TV) {
if(ivideo->vbflags2 & VB2_SISBRIDGE) {
ivideo->p2_1f = SiS_GetReg(SISPART2, 0x1f);
ivideo->p2_20 = SiS_GetReg(SISPART2, 0x20);
ivideo->p2_2b = SiS_GetReg(SISPART2, 0x2b);
ivideo->p2_42 = SiS_GetReg(SISPART2, 0x42);
ivideo->p2_43 = SiS_GetReg(SISPART2, 0x43);
ivideo->p2_01 = SiS_GetReg(SISPART2, 0x01);
ivideo->p2_02 = SiS_GetReg(SISPART2, 0x02);
} else if(ivideo->vbflags2 & VB2_CHRONTEL) {
if(ivideo->chronteltype == 1) {
ivideo->tvx = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0a);
ivideo->tvx |= (((SiS_GetCH700x(&ivideo->SiS_Pr, 0x08) & 0x02) >> 1) << 8);
ivideo->tvy = SiS_GetCH700x(&ivideo->SiS_Pr, 0x0b);
ivideo->tvy |= ((SiS_GetCH700x(&ivideo->SiS_Pr, 0x08) & 0x01) << 8);
}
}
}
if(ivideo->tvxpos) {
sisfb_set_TVxposoffset(ivideo, ivideo->tvxpos);
}
if(ivideo->tvypos) {
sisfb_set_TVyposoffset(ivideo, ivideo->tvypos);
}
/* Eventually sync engines */
sisfb_check_engine_and_sync(ivideo);
/* (Re-)Initialize chip engines */
if(ivideo->accel) {
sisfb_engine_init(ivideo);
} else {
ivideo->engineok = 0;
}
}
static int
sisfb_reset_mode(struct sis_video_info *ivideo)
{
if(sisfb_set_mode(ivideo, 0))
return 1;
sisfb_set_pitch(ivideo);
sisfb_set_base_CRT1(ivideo, ivideo->current_base);
sisfb_set_base_CRT2(ivideo, ivideo->current_base);
return 0;
}
static void
sisfb_handle_command(struct sis_video_info *ivideo, struct sisfb_cmd *sisfb_command)
{
int mycrt1off;
switch(sisfb_command->sisfb_cmd) {
case SISFB_CMD_GETVBFLAGS:
if(!ivideo->modechanged) {
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_EARLY;
} else {
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_OK;
sisfb_command->sisfb_result[1] = ivideo->currentvbflags;
sisfb_command->sisfb_result[2] = ivideo->vbflags2;
}
break;
case SISFB_CMD_SWITCHCRT1:
/* arg[0]: 0 = off, 1 = on, 99 = query */
if(!ivideo->modechanged) {
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_EARLY;
} else if(sisfb_command->sisfb_arg[0] == 99) {
/* Query */
sisfb_command->sisfb_result[1] = ivideo->sisfb_crt1off ? 0 : 1;
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_OK;
} else if(ivideo->sisfblocked) {
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_LOCKED;
} else if((!(ivideo->currentvbflags & CRT2_ENABLE)) &&
(sisfb_command->sisfb_arg[0] == 0)) {
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_NOCRT2;
} else {
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_OK;
mycrt1off = sisfb_command->sisfb_arg[0] ? 0 : 1;
if( ((ivideo->currentvbflags & VB_DISPTYPE_CRT1) && mycrt1off) ||
((!(ivideo->currentvbflags & VB_DISPTYPE_CRT1)) && !mycrt1off) ) {
ivideo->sisfb_crt1off = mycrt1off;
if(sisfb_reset_mode(ivideo)) {
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_OTHER;
}
}
sisfb_command->sisfb_result[1] = ivideo->sisfb_crt1off ? 0 : 1;
}
break;
/* more to come */
default:
sisfb_command->sisfb_result[0] = SISFB_CMD_ERR_UNKNOWN;
printk(KERN_ERR "sisfb: Unknown command 0x%x\n",
sisfb_command->sisfb_cmd);
}
}
#ifndef MODULE
static int __init sisfb_setup(char *options)
{
char *this_opt;
sisfb_setdefaultparms();
if(!options || !(*options))
return 0;
while((this_opt = strsep(&options, ",")) != NULL) {
if(!(*this_opt)) continue;
if(!strncasecmp(this_opt, "off", 3)) {
sisfb_off = 1;
} else if(!strncasecmp(this_opt, "forcecrt2type:", 14)) {
/* Need to check crt2 type first for fstn/dstn */
sisfb_search_crt2type(this_opt + 14);
} else if(!strncasecmp(this_opt, "tvmode:",7)) {
sisfb_search_tvstd(this_opt + 7);
} else if(!strncasecmp(this_opt, "tvstandard:",11)) {
sisfb_search_tvstd(this_opt + 11);
} else if(!strncasecmp(this_opt, "mode:", 5)) {
sisfb_search_mode(this_opt + 5, false);
} else if(!strncasecmp(this_opt, "vesa:", 5)) {
sisfb_search_vesamode(simple_strtoul(this_opt + 5, NULL, 0), false);
} else if(!strncasecmp(this_opt, "rate:", 5)) {
sisfb_parm_rate = simple_strtoul(this_opt + 5, NULL, 0);
} else if(!strncasecmp(this_opt, "forcecrt1:", 10)) {
sisfb_forcecrt1 = (int)simple_strtoul(this_opt + 10, NULL, 0);
} else if(!strncasecmp(this_opt, "mem:",4)) {
sisfb_parm_mem = simple_strtoul(this_opt + 4, NULL, 0);
} else if(!strncasecmp(this_opt, "pdc:", 4)) {
sisfb_pdc = simple_strtoul(this_opt + 4, NULL, 0);
} else if(!strncasecmp(this_opt, "pdc1:", 5)) {
sisfb_pdca = simple_strtoul(this_opt + 5, NULL, 0);
} else if(!strncasecmp(this_opt, "noaccel", 7)) {
sisfb_accel = 0;
} else if(!strncasecmp(this_opt, "accel", 5)) {
sisfb_accel = -1;
} else if(!strncasecmp(this_opt, "noypan", 6)) {
sisfb_ypan = 0;
} else if(!strncasecmp(this_opt, "ypan", 4)) {
sisfb_ypan = -1;
} else if(!strncasecmp(this_opt, "nomax", 5)) {
sisfb_max = 0;
} else if(!strncasecmp(this_opt, "max", 3)) {
sisfb_max = -1;
} else if(!strncasecmp(this_opt, "userom:", 7)) {
sisfb_userom = (int)simple_strtoul(this_opt + 7, NULL, 0);
} else if(!strncasecmp(this_opt, "useoem:", 7)) {
sisfb_useoem = (int)simple_strtoul(this_opt + 7, NULL, 0);
} else if(!strncasecmp(this_opt, "nocrt2rate", 10)) {
sisfb_nocrt2rate = 1;
} else if(!strncasecmp(this_opt, "scalelcd:", 9)) {
unsigned long temp = 2;
temp = simple_strtoul(this_opt + 9, NULL, 0);
if((temp == 0) || (temp == 1)) {
sisfb_scalelcd = temp ^ 1;
}
} else if(!strncasecmp(this_opt, "tvxposoffset:", 13)) {
int temp = 0;
temp = (int)simple_strtol(this_opt + 13, NULL, 0);
if((temp >= -32) && (temp <= 32)) {
sisfb_tvxposoffset = temp;
}
} else if(!strncasecmp(this_opt, "tvyposoffset:", 13)) {
int temp = 0;
temp = (int)simple_strtol(this_opt + 13, NULL, 0);
if((temp >= -32) && (temp <= 32)) {
sisfb_tvyposoffset = temp;
}
} else if(!strncasecmp(this_opt, "specialtiming:", 14)) {
sisfb_search_specialtiming(this_opt + 14);
} else if(!strncasecmp(this_opt, "lvdshl:", 7)) {
int temp = 4;
temp = simple_strtoul(this_opt + 7, NULL, 0);
if((temp >= 0) && (temp <= 3)) {
sisfb_lvdshl = temp;
}
} else if(this_opt[0] >= '0' && this_opt[0] <= '9') {
sisfb_search_mode(this_opt, true);
#if !defined(__i386__) && !defined(__x86_64__)
} else if(!strncasecmp(this_opt, "resetcard", 9)) {
sisfb_resetcard = 1;
} else if(!strncasecmp(this_opt, "videoram:", 9)) {
sisfb_videoram = simple_strtoul(this_opt + 9, NULL, 0);
#endif
} else {
printk(KERN_INFO "sisfb: Invalid option %s\n", this_opt);
}
}
return 0;
}
#endif
static int sisfb_check_rom(void __iomem *rom_base,
struct sis_video_info *ivideo)
{
void __iomem *rom;
int romptr;
if((readb(rom_base) != 0x55) || (readb(rom_base + 1) != 0xaa))
return 0;
romptr = (readb(rom_base + 0x18) | (readb(rom_base + 0x19) << 8));
if(romptr > (0x10000 - 8))
return 0;
rom = rom_base + romptr;
if((readb(rom) != 'P') || (readb(rom + 1) != 'C') ||
(readb(rom + 2) != 'I') || (readb(rom + 3) != 'R'))
return 0;
if((readb(rom + 4) | (readb(rom + 5) << 8)) != ivideo->chip_vendor)
return 0;
if((readb(rom + 6) | (readb(rom + 7) << 8)) != ivideo->chip_id)
return 0;
return 1;
}
static unsigned char *sisfb_find_rom(struct pci_dev *pdev)
{
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
void __iomem *rom_base;
unsigned char *myrombase = NULL;
size_t romsize;
/* First, try the official pci ROM functions (except
* on integrated chipsets which have no ROM).
*/
if(!ivideo->nbridge) {
if((rom_base = pci_map_rom(pdev, &romsize))) {
if(sisfb_check_rom(rom_base, ivideo)) {
if((myrombase = vmalloc(65536))) {
memcpy_fromio(myrombase, rom_base,
(romsize > 65536) ? 65536 : romsize);
}
}
pci_unmap_rom(pdev, rom_base);
}
}
if(myrombase) return myrombase;
/* Otherwise do it the conventional way. */
#if defined(__i386__) || defined(__x86_64__)
{
u32 temp;
for (temp = 0x000c0000; temp < 0x000f0000; temp += 0x00001000) {
rom_base = ioremap(temp, 65536);
if (!rom_base)
continue;
if (!sisfb_check_rom(rom_base, ivideo)) {
iounmap(rom_base);
continue;
}
if ((myrombase = vmalloc(65536)))
memcpy_fromio(myrombase, rom_base, 65536);
iounmap(rom_base);
break;
}
}
#endif
return myrombase;
}
static void sisfb_post_map_vram(struct sis_video_info *ivideo,
unsigned int *mapsize, unsigned int min)
{
if (*mapsize < (min << 20))
return;
ivideo->video_vbase = ioremap_wc(ivideo->video_base, (*mapsize));
if(!ivideo->video_vbase) {
printk(KERN_ERR
"sisfb: Unable to map maximum video RAM for size detection\n");
(*mapsize) >>= 1;
while((!(ivideo->video_vbase = ioremap_wc(ivideo->video_base, (*mapsize))))) {
(*mapsize) >>= 1;
if((*mapsize) < (min << 20))
break;
}
if(ivideo->video_vbase) {
printk(KERN_ERR
"sisfb: Video RAM size detection limited to %dMB\n",
(int)((*mapsize) >> 20));
}
}
}
#ifdef CONFIG_FB_SIS_300
static int sisfb_post_300_buswidth(struct sis_video_info *ivideo)
{
void __iomem *FBAddress = ivideo->video_vbase;
unsigned short temp;
unsigned char reg;
int i, j;
SiS_SetRegAND(SISSR, 0x15, 0xFB);
SiS_SetRegOR(SISSR, 0x15, 0x04);
SiS_SetReg(SISSR, 0x13, 0x00);
SiS_SetReg(SISSR, 0x14, 0xBF);
for(i = 0; i < 2; i++) {
temp = 0x1234;
for(j = 0; j < 4; j++) {
writew(temp, FBAddress);
if(readw(FBAddress) == temp)
break;
SiS_SetRegOR(SISSR, 0x3c, 0x01);
reg = SiS_GetReg(SISSR, 0x05);
reg = SiS_GetReg(SISSR, 0x05);
SiS_SetRegAND(SISSR, 0x3c, 0xfe);
reg = SiS_GetReg(SISSR, 0x05);
reg = SiS_GetReg(SISSR, 0x05);
temp++;
}
}
writel(0x01234567L, FBAddress);
writel(0x456789ABL, (FBAddress + 4));
writel(0x89ABCDEFL, (FBAddress + 8));
writel(0xCDEF0123L, (FBAddress + 12));
reg = SiS_GetReg(SISSR, 0x3b);
if(reg & 0x01) {
if(readl((FBAddress + 12)) == 0xCDEF0123L)
return 4; /* Channel A 128bit */
}
if(readl((FBAddress + 4)) == 0x456789ABL)
return 2; /* Channel B 64bit */
return 1; /* 32bit */
}
static const unsigned short SiS_DRAMType[17][5] = {
{0x0C,0x0A,0x02,0x40,0x39},
{0x0D,0x0A,0x01,0x40,0x48},
{0x0C,0x09,0x02,0x20,0x35},
{0x0D,0x09,0x01,0x20,0x44},
{0x0C,0x08,0x02,0x10,0x31},
{0x0D,0x08,0x01,0x10,0x40},
{0x0C,0x0A,0x01,0x20,0x34},
{0x0C,0x09,0x01,0x08,0x32},
{0x0B,0x08,0x02,0x08,0x21},
{0x0C,0x08,0x01,0x08,0x30},
{0x0A,0x08,0x02,0x04,0x11},
{0x0B,0x0A,0x01,0x10,0x28},
{0x09,0x08,0x02,0x02,0x01},
{0x0B,0x09,0x01,0x08,0x24},
{0x0B,0x08,0x01,0x04,0x20},
{0x0A,0x08,0x01,0x02,0x10},
{0x09,0x08,0x01,0x01,0x00}
};
static int sisfb_post_300_rwtest(struct sis_video_info *ivideo, int iteration,
int buswidth, int PseudoRankCapacity,
int PseudoAdrPinCount, unsigned int mapsize)
{
void __iomem *FBAddr = ivideo->video_vbase;
unsigned short sr14;
unsigned int k, RankCapacity, PageCapacity, BankNumHigh, BankNumMid;
unsigned int PhysicalAdrOtherPage, PhysicalAdrHigh, PhysicalAdrHalfPage;
for (k = 0; k < ARRAY_SIZE(SiS_DRAMType); k++) {
RankCapacity = buswidth * SiS_DRAMType[k][3];
if (RankCapacity != PseudoRankCapacity)
continue;
if ((SiS_DRAMType[k][2] + SiS_DRAMType[k][0]) > PseudoAdrPinCount)
continue;
BankNumHigh = RankCapacity * 16 * iteration - 1;
if (iteration == 3) { /* Rank No */
BankNumMid = RankCapacity * 16 - 1;
} else {
BankNumMid = RankCapacity * 16 * iteration / 2 - 1;
}
PageCapacity = (1 << SiS_DRAMType[k][1]) * buswidth * 4;
PhysicalAdrHigh = BankNumHigh;
PhysicalAdrHalfPage = (PageCapacity / 2 + PhysicalAdrHigh) % PageCapacity;
PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh;
SiS_SetRegAND(SISSR, 0x15, 0xFB); /* Test */
SiS_SetRegOR(SISSR, 0x15, 0x04); /* Test */
sr14 = (SiS_DRAMType[k][3] * buswidth) - 1;
if (buswidth == 4)
sr14 |= 0x80;
else if (buswidth == 2)
sr14 |= 0x40;
SiS_SetReg(SISSR, 0x13, SiS_DRAMType[k][4]);
SiS_SetReg(SISSR, 0x14, sr14);
BankNumHigh <<= 16;
BankNumMid <<= 16;
if ((BankNumHigh + PhysicalAdrHigh >= mapsize) ||
(BankNumMid + PhysicalAdrHigh >= mapsize) ||
(BankNumHigh + PhysicalAdrHalfPage >= mapsize) ||
(BankNumHigh + PhysicalAdrOtherPage >= mapsize))
continue;
/* Write data */
writew(((unsigned short)PhysicalAdrHigh),
(FBAddr + BankNumHigh + PhysicalAdrHigh));
writew(((unsigned short)BankNumMid),
(FBAddr + BankNumMid + PhysicalAdrHigh));
writew(((unsigned short)PhysicalAdrHalfPage),
(FBAddr + BankNumHigh + PhysicalAdrHalfPage));
writew(((unsigned short)PhysicalAdrOtherPage),
(FBAddr + BankNumHigh + PhysicalAdrOtherPage));
/* Read data */
if (readw(FBAddr + BankNumHigh + PhysicalAdrHigh) == PhysicalAdrHigh)
return 1;
}
return 0;
}
static void sisfb_post_300_ramsize(struct pci_dev *pdev, unsigned int mapsize)
{
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
int i, j, buswidth;
int PseudoRankCapacity, PseudoAdrPinCount;
buswidth = sisfb_post_300_buswidth(ivideo);
for(i = 6; i >= 0; i--) {
PseudoRankCapacity = 1 << i;
for(j = 4; j >= 1; j--) {
PseudoAdrPinCount = 15 - j;
if((PseudoRankCapacity * j) <= 64) {
if(sisfb_post_300_rwtest(ivideo,
j,
buswidth,
PseudoRankCapacity,
PseudoAdrPinCount,
mapsize))
return;
}
}
}
}
static void sisfb_post_sis300(struct pci_dev *pdev)
{
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
unsigned char *bios = ivideo->SiS_Pr.VirtualRomBase;
u8 reg, v1, v2, v3, v4, v5, v6, v7, v8;
u16 index, rindex, memtype = 0;
unsigned int mapsize;
if(!ivideo->SiS_Pr.UseROM)
bios = NULL;
SiS_SetReg(SISSR, 0x05, 0x86);
if(bios) {
if(bios[0x52] & 0x80) {
memtype = bios[0x52];
} else {
memtype = SiS_GetReg(SISSR, 0x3a);
}
memtype &= 0x07;
}
v3 = 0x80; v6 = 0x80;
if(ivideo->revision_id <= 0x13) {
v1 = 0x44; v2 = 0x42;
v4 = 0x44; v5 = 0x42;
} else {
v1 = 0x68; v2 = 0x43; /* Assume 125Mhz MCLK */
v4 = 0x68; v5 = 0x43; /* Assume 125Mhz ECLK */
if(bios) {
index = memtype * 5;
rindex = index + 0x54;
v1 = bios[rindex++];
v2 = bios[rindex++];
v3 = bios[rindex++];
rindex = index + 0x7c;
v4 = bios[rindex++];
v5 = bios[rindex++];
v6 = bios[rindex++];
}
}
SiS_SetReg(SISSR, 0x28, v1);
SiS_SetReg(SISSR, 0x29, v2);
SiS_SetReg(SISSR, 0x2a, v3);
SiS_SetReg(SISSR, 0x2e, v4);
SiS_SetReg(SISSR, 0x2f, v5);
SiS_SetReg(SISSR, 0x30, v6);
v1 = 0x10;
if(bios)
v1 = bios[0xa4];
SiS_SetReg(SISSR, 0x07, v1); /* DAC speed */
SiS_SetReg(SISSR, 0x11, 0x0f); /* DDC, power save */
v1 = 0x01; v2 = 0x43; v3 = 0x1e; v4 = 0x2a;
v5 = 0x06; v6 = 0x00; v7 = 0x00; v8 = 0x00;
if(bios) {
memtype += 0xa5;
v1 = bios[memtype];
v2 = bios[memtype + 8];
v3 = bios[memtype + 16];
v4 = bios[memtype + 24];
v5 = bios[memtype + 32];
v6 = bios[memtype + 40];
v7 = bios[memtype + 48];
v8 = bios[memtype + 56];
}
if(ivideo->revision_id >= 0x80)
v3 &= 0xfd;
SiS_SetReg(SISSR, 0x15, v1); /* Ram type (assuming 0, BIOS 0xa5 step 8) */
SiS_SetReg(SISSR, 0x16, v2);
SiS_SetReg(SISSR, 0x17, v3);
SiS_SetReg(SISSR, 0x18, v4);
SiS_SetReg(SISSR, 0x19, v5);
SiS_SetReg(SISSR, 0x1a, v6);
SiS_SetReg(SISSR, 0x1b, v7);
SiS_SetReg(SISSR, 0x1c, v8); /* ---- */
SiS_SetRegAND(SISSR, 0x15, 0xfb);
SiS_SetRegOR(SISSR, 0x15, 0x04);
if(bios) {
if(bios[0x53] & 0x02) {
SiS_SetRegOR(SISSR, 0x19, 0x20);
}
}
v1 = 0x04; /* DAC pedestal (BIOS 0xe5) */
if(ivideo->revision_id >= 0x80)
v1 |= 0x01;
SiS_SetReg(SISSR, 0x1f, v1);
SiS_SetReg(SISSR, 0x20, 0xa4); /* linear & relocated io & disable a0000 */
v1 = 0xf6; v2 = 0x0d; v3 = 0x00;
if(bios) {
v1 = bios[0xe8];
v2 = bios[0xe9];
v3 = bios[0xea];
}
SiS_SetReg(SISSR, 0x23, v1);
SiS_SetReg(SISSR, 0x24, v2);
SiS_SetReg(SISSR, 0x25, v3);
SiS_SetReg(SISSR, 0x21, 0x84);
SiS_SetReg(SISSR, 0x22, 0x00);
SiS_SetReg(SISCR, 0x37, 0x00);
SiS_SetRegOR(SISPART1, 0x24, 0x01); /* unlock crt2 */
SiS_SetReg(SISPART1, 0x00, 0x00);
v1 = 0x40; v2 = 0x11;
if(bios) {
v1 = bios[0xec];
v2 = bios[0xeb];
}
SiS_SetReg(SISPART1, 0x02, v1);
if(ivideo->revision_id >= 0x80)
v2 &= ~0x01;
reg = SiS_GetReg(SISPART4, 0x00);
if((reg == 1) || (reg == 2)) {
SiS_SetReg(SISCR, 0x37, 0x02);
SiS_SetReg(SISPART2, 0x00, 0x1c);
v4 = 0x00; v5 = 0x00; v6 = 0x10;
if (ivideo->SiS_Pr.UseROM && bios) {
v4 = bios[0xf5];
v5 = bios[0xf6];
v6 = bios[0xf7];
}
SiS_SetReg(SISPART4, 0x0d, v4);
SiS_SetReg(SISPART4, 0x0e, v5);
SiS_SetReg(SISPART4, 0x10, v6);
SiS_SetReg(SISPART4, 0x0f, 0x3f);
reg = SiS_GetReg(SISPART4, 0x01);
if(reg >= 0xb0) {
reg = SiS_GetReg(SISPART4, 0x23);
reg &= 0x20;
reg <<= 1;
SiS_SetReg(SISPART4, 0x23, reg);
}
} else {
v2 &= ~0x10;
}
SiS_SetReg(SISSR, 0x32, v2);
SiS_SetRegAND(SISPART1, 0x24, 0xfe); /* Lock CRT2 */
reg = SiS_GetReg(SISSR, 0x16);
reg &= 0xc3;
SiS_SetReg(SISCR, 0x35, reg);
SiS_SetReg(SISCR, 0x83, 0x00);
#if !defined(__i386__) && !defined(__x86_64__)
if(sisfb_videoram) {
SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
reg = ((sisfb_videoram >> 10) - 1) | 0x40;
SiS_SetReg(SISSR, 0x14, reg);
} else {
#endif
/* Need to map max FB size for finding out about RAM size */
mapsize = ivideo->video_size;
sisfb_post_map_vram(ivideo, &mapsize, 4);
if(ivideo->video_vbase) {
sisfb_post_300_ramsize(pdev, mapsize);
iounmap(ivideo->video_vbase);
} else {
printk(KERN_DEBUG
"sisfb: Failed to map memory for size detection, assuming 8MB\n");
SiS_SetReg(SISSR, 0x13, 0x28); /* ? */
SiS_SetReg(SISSR, 0x14, 0x47); /* 8MB, 64bit default */
}
#if !defined(__i386__) && !defined(__x86_64__)
}
#endif
if(bios) {
v1 = bios[0xe6];
v2 = bios[0xe7];
} else {
reg = SiS_GetReg(SISSR, 0x3a);
if((reg & 0x30) == 0x30) {
v1 = 0x04; /* PCI */
v2 = 0x92;
} else {
v1 = 0x14; /* AGP */
v2 = 0xb2;
}
}
SiS_SetReg(SISSR, 0x21, v1);
SiS_SetReg(SISSR, 0x22, v2);
/* Sense CRT1 */
sisfb_sense_crt1(ivideo);
/* Set default mode, don't clear screen */
ivideo->SiS_Pr.SiS_UseOEM = false;
SiS_SetEnableDstn(&ivideo->SiS_Pr, false);
SiS_SetEnableFstn(&ivideo->SiS_Pr, false);
ivideo->curFSTN = ivideo->curDSTN = 0;
ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
SiS_SetReg(SISSR, 0x05, 0x86);
/* Display off */
SiS_SetRegOR(SISSR, 0x01, 0x20);
/* Save mode number in CR34 */
SiS_SetReg(SISCR, 0x34, 0x2e);
/* Let everyone know what the current mode is */
ivideo->modeprechange = 0x2e;
}
#endif
#ifdef CONFIG_FB_SIS_315
#if 0
static void sisfb_post_sis315330(struct pci_dev *pdev)
{
/* TODO */
}
#endif
static inline int sisfb_xgi_is21(struct sis_video_info *ivideo)
{
return ivideo->chip_real_id == XGI_21;
}
static void sisfb_post_xgi_delay(struct sis_video_info *ivideo, int delay)
{
unsigned int i;
u8 reg;
for(i = 0; i <= (delay * 10 * 36); i++) {
reg = SiS_GetReg(SISSR, 0x05);
reg++;
}
}
static int sisfb_find_host_bridge(struct sis_video_info *ivideo,
struct pci_dev *mypdev,
unsigned short pcivendor)
{
struct pci_dev *pdev = NULL;
unsigned short temp;
int ret = 0;
while((pdev = pci_get_class(PCI_CLASS_BRIDGE_HOST, pdev))) {
temp = pdev->vendor;
if(temp == pcivendor) {
ret = 1;
pci_dev_put(pdev);
break;
}
}
return ret;
}
static int sisfb_post_xgi_rwtest(struct sis_video_info *ivideo, int starta,
unsigned int enda, unsigned int mapsize)
{
unsigned int pos;
int i;
writel(0, ivideo->video_vbase);
for(i = starta; i <= enda; i++) {
pos = 1 << i;
if(pos < mapsize)
writel(pos, ivideo->video_vbase + pos);
}
sisfb_post_xgi_delay(ivideo, 150);
if(readl(ivideo->video_vbase) != 0)
return 0;
for(i = starta; i <= enda; i++) {
pos = 1 << i;
if(pos < mapsize) {
if(readl(ivideo->video_vbase + pos) != pos)
return 0;
} else
return 0;
}
return 1;
}
static int sisfb_post_xgi_ramsize(struct sis_video_info *ivideo)
{
unsigned int buswidth, ranksize, channelab, mapsize;
int i, j, k, l, status;
u8 reg, sr14;
static const u8 dramsr13[12 * 5] = {
0x02, 0x0e, 0x0b, 0x80, 0x5d,
0x02, 0x0e, 0x0a, 0x40, 0x59,
0x02, 0x0d, 0x0b, 0x40, 0x4d,
0x02, 0x0e, 0x09, 0x20, 0x55,
0x02, 0x0d, 0x0a, 0x20, 0x49,
0x02, 0x0c, 0x0b, 0x20, 0x3d,
0x02, 0x0e, 0x08, 0x10, 0x51,
0x02, 0x0d, 0x09, 0x10, 0x45,
0x02, 0x0c, 0x0a, 0x10, 0x39,
0x02, 0x0d, 0x08, 0x08, 0x41,
0x02, 0x0c, 0x09, 0x08, 0x35,
0x02, 0x0c, 0x08, 0x04, 0x31
};
static const u8 dramsr13_4[4 * 5] = {
0x02, 0x0d, 0x09, 0x40, 0x45,
0x02, 0x0c, 0x09, 0x20, 0x35,
0x02, 0x0c, 0x08, 0x10, 0x31,
0x02, 0x0b, 0x08, 0x08, 0x21
};
/* Enable linear mode, disable 0xa0000 address decoding */
/* We disable a0000 address decoding, because
* - if running on x86, if the card is disabled, it means
* that another card is in the system. We don't want
* to interphere with that primary card's textmode.
* - if running on non-x86, there usually is no VGA window
* at a0000.
*/
SiS_SetRegOR(SISSR, 0x20, (0x80 | 0x04));
/* Need to map max FB size for finding out about RAM size */
mapsize = ivideo->video_size;
sisfb_post_map_vram(ivideo, &mapsize, 32);
if(!ivideo->video_vbase) {
printk(KERN_ERR "sisfb: Unable to detect RAM size. Setting default.\n");
SiS_SetReg(SISSR, 0x13, 0x35);
SiS_SetReg(SISSR, 0x14, 0x41);
/* TODO */
return -ENOMEM;
}
/* Non-interleaving */
SiS_SetReg(SISSR, 0x15, 0x00);
/* No tiling */
SiS_SetReg(SISSR, 0x1c, 0x00);
if(ivideo->chip == XGI_20) {
channelab = 1;
reg = SiS_GetReg(SISCR, 0x97);
if(!(reg & 0x01)) { /* Single 32/16 */
buswidth = 32;
SiS_SetReg(SISSR, 0x13, 0xb1);
SiS_SetReg(SISSR, 0x14, 0x52);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x02;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
SiS_SetReg(SISSR, 0x13, 0x31);
SiS_SetReg(SISSR, 0x14, 0x42);
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 23, mapsize))
goto bail_out;
buswidth = 16;
SiS_SetReg(SISSR, 0x13, 0xb1);
SiS_SetReg(SISSR, 0x14, 0x41);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x01;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
else
SiS_SetReg(SISSR, 0x13, 0x31);
} else { /* Dual 16/8 */
buswidth = 16;
SiS_SetReg(SISSR, 0x13, 0xb1);
SiS_SetReg(SISSR, 0x14, 0x41);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x01;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
SiS_SetReg(SISSR, 0x13, 0x31);
SiS_SetReg(SISSR, 0x14, 0x31);
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 22, 22, mapsize))
goto bail_out;
buswidth = 8;
SiS_SetReg(SISSR, 0x13, 0xb1);
SiS_SetReg(SISSR, 0x14, 0x30);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x00;
if(sisfb_post_xgi_rwtest(ivideo, 21, 22, mapsize))
goto bail_out;
else
SiS_SetReg(SISSR, 0x13, 0x31);
}
} else { /* XGI_40 */
reg = SiS_GetReg(SISCR, 0x97);
if(!(reg & 0x10)) {
reg = SiS_GetReg(SISSR, 0x39);
reg >>= 1;
}
if(reg & 0x01) { /* DDRII */
buswidth = 32;
if(ivideo->revision_id == 2) {
channelab = 2;
SiS_SetReg(SISSR, 0x13, 0xa1);
SiS_SetReg(SISSR, 0x14, 0x44);
sr14 = 0x04;
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
SiS_SetReg(SISSR, 0x13, 0x21);
SiS_SetReg(SISSR, 0x14, 0x34);
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
channelab = 1;
SiS_SetReg(SISSR, 0x13, 0xa1);
SiS_SetReg(SISSR, 0x14, 0x40);
sr14 = 0x00;
if(sisfb_post_xgi_rwtest(ivideo, 22, 23, mapsize))
goto bail_out;
SiS_SetReg(SISSR, 0x13, 0x21);
SiS_SetReg(SISSR, 0x14, 0x30);
} else {
channelab = 3;
SiS_SetReg(SISSR, 0x13, 0xa1);
SiS_SetReg(SISSR, 0x14, 0x4c);
sr14 = 0x0c;
sisfb_post_xgi_delay(ivideo, 1);
if(sisfb_post_xgi_rwtest(ivideo, 23, 25, mapsize))
goto bail_out;
channelab = 2;
SiS_SetReg(SISSR, 0x14, 0x48);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x08;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
SiS_SetReg(SISSR, 0x13, 0x21);
SiS_SetReg(SISSR, 0x14, 0x3c);
sr14 = 0x0c;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize)) {
channelab = 3;
} else {
channelab = 2;
SiS_SetReg(SISSR, 0x14, 0x38);
sr14 = 0x08;
}
}
sisfb_post_xgi_delay(ivideo, 1);
} else { /* DDR */
buswidth = 64;
if(ivideo->revision_id == 2) {
channelab = 1;
SiS_SetReg(SISSR, 0x13, 0xa1);
SiS_SetReg(SISSR, 0x14, 0x52);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x02;
if(sisfb_post_xgi_rwtest(ivideo, 23, 24, mapsize))
goto bail_out;
SiS_SetReg(SISSR, 0x13, 0x21);
SiS_SetReg(SISSR, 0x14, 0x42);
} else {
channelab = 2;
SiS_SetReg(SISSR, 0x13, 0xa1);
SiS_SetReg(SISSR, 0x14, 0x5a);
sisfb_post_xgi_delay(ivideo, 1);
sr14 = 0x0a;
if(sisfb_post_xgi_rwtest(ivideo, 24, 25, mapsize))
goto bail_out;
SiS_SetReg(SISSR, 0x13, 0x21);
SiS_SetReg(SISSR, 0x14, 0x4a);
}
sisfb_post_xgi_delay(ivideo, 1);
}
}
bail_out:
SiS_SetRegANDOR(SISSR, 0x14, 0xf0, sr14);
sisfb_post_xgi_delay(ivideo, 1);
j = (ivideo->chip == XGI_20) ? 5 : 9;
k = (ivideo->chip == XGI_20) ? 12 : 4;
status = -EIO;
for(i = 0; i < k; i++) {
reg = (ivideo->chip == XGI_20) ?
dramsr13[(i * 5) + 4] : dramsr13_4[(i * 5) + 4];
SiS_SetRegANDOR(SISSR, 0x13, 0x80, reg);
sisfb_post_xgi_delay(ivideo, 50);
ranksize = (ivideo->chip == XGI_20) ?
dramsr13[(i * 5) + 3] : dramsr13_4[(i * 5) + 3];
reg = SiS_GetReg(SISSR, 0x13);
if(reg & 0x80) ranksize <<= 1;
if(ivideo->chip == XGI_20) {
if(buswidth == 16) ranksize <<= 1;
else if(buswidth == 32) ranksize <<= 2;
} else {
if(buswidth == 64) ranksize <<= 1;
}
reg = 0;
l = channelab;
if(l == 3) l = 4;
if((ranksize * l) <= 256) {
while((ranksize >>= 1)) reg += 0x10;
}
if(!reg) continue;
SiS_SetRegANDOR(SISSR, 0x14, 0x0f, (reg & 0xf0));
sisfb_post_xgi_delay(ivideo, 1);
if (sisfb_post_xgi_rwtest(ivideo, j, ((reg >> 4) + channelab - 2 + 20), mapsize)) {
status = 0;
break;
}
}
iounmap(ivideo->video_vbase);
return status;
}
static void sisfb_post_xgi_setclocks(struct sis_video_info *ivideo, u8 regb)
{
u8 v1, v2, v3;
int index;
static const u8 cs90[8 * 3] = {
0x16, 0x01, 0x01,
0x3e, 0x03, 0x01,
0x7c, 0x08, 0x01,
0x79, 0x06, 0x01,
0x29, 0x01, 0x81,
0x5c, 0x23, 0x01,
0x5c, 0x23, 0x01,
0x5c, 0x23, 0x01
};
static const u8 csb8[8 * 3] = {
0x5c, 0x23, 0x01,
0x29, 0x01, 0x01,
0x7c, 0x08, 0x01,
0x79, 0x06, 0x01,
0x29, 0x01, 0x81,
0x5c, 0x23, 0x01,
0x5c, 0x23, 0x01,
0x5c, 0x23, 0x01
};
regb = 0; /* ! */
index = regb * 3;
v1 = cs90[index]; v2 = cs90[index + 1]; v3 = cs90[index + 2];
if(ivideo->haveXGIROM) {
v1 = ivideo->bios_abase[0x90 + index];
v2 = ivideo->bios_abase[0x90 + index + 1];
v3 = ivideo->bios_abase[0x90 + index + 2];
}
SiS_SetReg(SISSR, 0x28, v1);
SiS_SetReg(SISSR, 0x29, v2);
SiS_SetReg(SISSR, 0x2a, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
index = regb * 3;
v1 = csb8[index]; v2 = csb8[index + 1]; v3 = csb8[index + 2];
if(ivideo->haveXGIROM) {
v1 = ivideo->bios_abase[0xb8 + index];
v2 = ivideo->bios_abase[0xb8 + index + 1];
v3 = ivideo->bios_abase[0xb8 + index + 2];
}
SiS_SetReg(SISSR, 0x2e, v1);
SiS_SetReg(SISSR, 0x2f, v2);
SiS_SetReg(SISSR, 0x30, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
}
static void sisfb_post_xgi_ddr2_mrs_default(struct sis_video_info *ivideo,
u8 regb)
{
unsigned char *bios = ivideo->bios_abase;
u8 v1;
SiS_SetReg(SISSR, 0x28, 0x64);
SiS_SetReg(SISSR, 0x29, 0x63);
sisfb_post_xgi_delay(ivideo, 15);
SiS_SetReg(SISSR, 0x18, 0x00);
SiS_SetReg(SISSR, 0x19, 0x20);
SiS_SetReg(SISSR, 0x16, 0x00);
SiS_SetReg(SISSR, 0x16, 0x80);
SiS_SetReg(SISSR, 0x18, 0xc5);
SiS_SetReg(SISSR, 0x19, 0x23);
SiS_SetReg(SISSR, 0x16, 0x00);
SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 1);
SiS_SetReg(SISCR, 0x97, 0x11);
sisfb_post_xgi_setclocks(ivideo, regb);
sisfb_post_xgi_delay(ivideo, 0x46);
SiS_SetReg(SISSR, 0x18, 0xc5);
SiS_SetReg(SISSR, 0x19, 0x23);
SiS_SetReg(SISSR, 0x16, 0x00);
SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 1);
SiS_SetReg(SISSR, 0x1b, 0x04);
sisfb_post_xgi_delay(ivideo, 1);
SiS_SetReg(SISSR, 0x1b, 0x00);
sisfb_post_xgi_delay(ivideo, 1);
v1 = 0x31;
if (ivideo->haveXGIROM) {
v1 = bios[0xf0];
}
SiS_SetReg(SISSR, 0x18, v1);
SiS_SetReg(SISSR, 0x19, 0x06);
SiS_SetReg(SISSR, 0x16, 0x04);
SiS_SetReg(SISSR, 0x16, 0x84);
sisfb_post_xgi_delay(ivideo, 1);
}
static void sisfb_post_xgi_ddr2_mrs_xg21(struct sis_video_info *ivideo)
{
sisfb_post_xgi_setclocks(ivideo, 1);
SiS_SetReg(SISCR, 0x97, 0x11);
sisfb_post_xgi_delay(ivideo, 0x46);
SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS2 */
SiS_SetReg(SISSR, 0x19, 0x80);
SiS_SetReg(SISSR, 0x16, 0x05);
SiS_SetReg(SISSR, 0x16, 0x85);
SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS3 */
SiS_SetReg(SISSR, 0x19, 0xc0);
SiS_SetReg(SISSR, 0x16, 0x05);
SiS_SetReg(SISSR, 0x16, 0x85);
SiS_SetReg(SISSR, 0x18, 0x00); /* EMRS1 */
SiS_SetReg(SISSR, 0x19, 0x40);
SiS_SetReg(SISSR, 0x16, 0x05);
SiS_SetReg(SISSR, 0x16, 0x85);
SiS_SetReg(SISSR, 0x18, 0x42); /* MRS1 */
SiS_SetReg(SISSR, 0x19, 0x02);
SiS_SetReg(SISSR, 0x16, 0x05);
SiS_SetReg(SISSR, 0x16, 0x85);
sisfb_post_xgi_delay(ivideo, 1);
SiS_SetReg(SISSR, 0x1b, 0x04);
sisfb_post_xgi_delay(ivideo, 1);
SiS_SetReg(SISSR, 0x1b, 0x00);
sisfb_post_xgi_delay(ivideo, 1);
SiS_SetReg(SISSR, 0x18, 0x42); /* MRS1 */
SiS_SetReg(SISSR, 0x19, 0x00);
SiS_SetReg(SISSR, 0x16, 0x05);
SiS_SetReg(SISSR, 0x16, 0x85);
sisfb_post_xgi_delay(ivideo, 1);
}
static void sisfb_post_xgi_ddr2(struct sis_video_info *ivideo, u8 regb)
{
unsigned char *bios = ivideo->bios_abase;
static const u8 cs158[8] = {
0x88, 0xaa, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs160[8] = {
0x44, 0x77, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs168[8] = {
0x48, 0x78, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00
};
u8 v1;
u8 v2;
u8 v3;
SiS_SetReg(SISCR, 0xb0, 0x80); /* DDR2 dual frequency mode */
SiS_SetReg(SISCR, 0x82, 0x77);
SiS_SetReg(SISCR, 0x86, 0x00);
SiS_GetReg(SISCR, 0x86);
SiS_SetReg(SISCR, 0x86, 0x88);
SiS_GetReg(SISCR, 0x86);
v1 = cs168[regb]; v2 = cs160[regb]; v3 = cs158[regb];
if (ivideo->haveXGIROM) {
v1 = bios[regb + 0x168];
v2 = bios[regb + 0x160];
v3 = bios[regb + 0x158];
}
SiS_SetReg(SISCR, 0x86, v1);
SiS_SetReg(SISCR, 0x82, 0x77);
SiS_SetReg(SISCR, 0x85, 0x00);
SiS_GetReg(SISCR, 0x85);
SiS_SetReg(SISCR, 0x85, 0x88);
SiS_GetReg(SISCR, 0x85);
SiS_SetReg(SISCR, 0x85, v2);
SiS_SetReg(SISCR, 0x82, v3);
SiS_SetReg(SISCR, 0x98, 0x01);
SiS_SetReg(SISCR, 0x9a, 0x02);
if (sisfb_xgi_is21(ivideo))
sisfb_post_xgi_ddr2_mrs_xg21(ivideo);
else
sisfb_post_xgi_ddr2_mrs_default(ivideo, regb);
}
static u8 sisfb_post_xgi_ramtype(struct sis_video_info *ivideo)
{
unsigned char *bios = ivideo->bios_abase;
u8 ramtype;
u8 reg;
u8 v1;
ramtype = 0x00; v1 = 0x10;
if (ivideo->haveXGIROM) {
ramtype = bios[0x62];
v1 = bios[0x1d2];
}
if (!(ramtype & 0x80)) {
if (sisfb_xgi_is21(ivideo)) {
SiS_SetRegAND(SISCR, 0xb4, 0xfd); /* GPIO control */
SiS_SetRegOR(SISCR, 0x4a, 0x80); /* GPIOH EN */
reg = SiS_GetReg(SISCR, 0x48);
SiS_SetRegOR(SISCR, 0xb4, 0x02);
ramtype = reg & 0x01; /* GPIOH */
} else if (ivideo->chip == XGI_20) {
SiS_SetReg(SISCR, 0x97, v1);
reg = SiS_GetReg(SISCR, 0x97);
if (reg & 0x10) {
ramtype = (reg & 0x01) << 1;
}
} else {
reg = SiS_GetReg(SISSR, 0x39);
ramtype = reg & 0x02;
if (!(ramtype)) {
reg = SiS_GetReg(SISSR, 0x3a);
ramtype = (reg >> 1) & 0x01;
}
}
}
ramtype &= 0x07;
return ramtype;
}
static int sisfb_post_xgi(struct pci_dev *pdev)
{
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
unsigned char *bios = ivideo->bios_abase;
struct pci_dev *mypdev = NULL;
const u8 *ptr, *ptr2;
u8 v1, v2, v3, v4, v5, reg, ramtype;
u32 rega, regb, regd;
int i, j, k, index;
static const u8 cs78[3] = { 0xf6, 0x0d, 0x00 };
static const u8 cs76[2] = { 0xa3, 0xfb };
static const u8 cs7b[3] = { 0xc0, 0x11, 0x00 };
static const u8 cs158[8] = {
0x88, 0xaa, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs160[8] = {
0x44, 0x77, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs168[8] = {
0x48, 0x78, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs128[3 * 8] = {
0x90, 0x28, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00,
0x77, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
0x77, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs148[2 * 8] = {
0x55, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs31a[8 * 4] = {
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs33a[8 * 4] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs45a[8 * 2] = {
0x00, 0x00, 0xa0, 0x00, 0xa0, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs170[7 * 8] = {
0x54, 0x32, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
0x54, 0x43, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0a, 0x05, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
0x44, 0x34, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
0x10, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00,
0x11, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00,
0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs1a8[3 * 8] = {
0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00,
0x05, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static const u8 cs100[2 * 8] = {
0xc4, 0x04, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00,
0xc4, 0x04, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00
};
/* VGA enable */
reg = SiS_GetRegByte(SISVGAENABLE) | 0x01;
SiS_SetRegByte(SISVGAENABLE, reg);
/* Misc */
reg = SiS_GetRegByte(SISMISCR) | 0x01;
SiS_SetRegByte(SISMISCW, reg);
/* Unlock SR */
SiS_SetReg(SISSR, 0x05, 0x86);
reg = SiS_GetReg(SISSR, 0x05);
if(reg != 0xa1)
return 0;
/* Clear some regs */
for(i = 0; i < 0x22; i++) {
if(0x06 + i == 0x20) continue;
SiS_SetReg(SISSR, 0x06 + i, 0x00);
}
for(i = 0; i < 0x0b; i++) {
SiS_SetReg(SISSR, 0x31 + i, 0x00);
}
for(i = 0; i < 0x10; i++) {
SiS_SetReg(SISCR, 0x30 + i, 0x00);
}
ptr = cs78;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x78];
}
for(i = 0; i < 3; i++) {
SiS_SetReg(SISSR, 0x23 + i, ptr[i]);
}
ptr = cs76;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x76];
}
for(i = 0; i < 2; i++) {
SiS_SetReg(SISSR, 0x21 + i, ptr[i]);
}
v1 = 0x18; v2 = 0x00;
if(ivideo->haveXGIROM) {
v1 = bios[0x74];
v2 = bios[0x75];
}
SiS_SetReg(SISSR, 0x07, v1);
SiS_SetReg(SISSR, 0x11, 0x0f);
SiS_SetReg(SISSR, 0x1f, v2);
/* PCI linear mode, RelIO enabled, A0000 decoding disabled */
SiS_SetReg(SISSR, 0x20, 0x80 | 0x20 | 0x04);
SiS_SetReg(SISSR, 0x27, 0x74);
ptr = cs7b;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x7b];
}
for(i = 0; i < 3; i++) {
SiS_SetReg(SISSR, 0x31 + i, ptr[i]);
}
if(ivideo->chip == XGI_40) {
if(ivideo->revision_id == 2) {
SiS_SetRegANDOR(SISSR, 0x3b, 0x3f, 0xc0);
}
SiS_SetReg(SISCR, 0x7d, 0xfe);
SiS_SetReg(SISCR, 0x7e, 0x0f);
}
if(ivideo->revision_id == 0) { /* 40 *and* 20? */
SiS_SetRegAND(SISCR, 0x58, 0xd7);
reg = SiS_GetReg(SISCR, 0xcb);
if(reg & 0x20) {
SiS_SetRegANDOR(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */
}
}
reg = (ivideo->chip == XGI_40) ? 0x20 : 0x00;
SiS_SetRegANDOR(SISCR, 0x38, 0x1f, reg);
if(ivideo->chip == XGI_20) {
SiS_SetReg(SISSR, 0x36, 0x70);
} else {
SiS_SetReg(SISVID, 0x00, 0x86);
SiS_SetReg(SISVID, 0x32, 0x00);
SiS_SetReg(SISVID, 0x30, 0x00);
SiS_SetReg(SISVID, 0x32, 0x01);
SiS_SetReg(SISVID, 0x30, 0x00);
SiS_SetRegAND(SISVID, 0x2f, 0xdf);
SiS_SetRegAND(SISCAP, 0x00, 0x3f);
SiS_SetReg(SISPART1, 0x2f, 0x01);
SiS_SetReg(SISPART1, 0x00, 0x00);
SiS_SetReg(SISPART1, 0x02, bios[0x7e]);
SiS_SetReg(SISPART1, 0x2e, 0x08);
SiS_SetRegAND(SISPART1, 0x35, 0x7f);
SiS_SetRegAND(SISPART1, 0x50, 0xfe);
reg = SiS_GetReg(SISPART4, 0x00);
if(reg == 1 || reg == 2) {
SiS_SetReg(SISPART2, 0x00, 0x1c);
SiS_SetReg(SISPART4, 0x0d, bios[0x7f]);
SiS_SetReg(SISPART4, 0x0e, bios[0x80]);
SiS_SetReg(SISPART4, 0x10, bios[0x81]);
SiS_SetRegAND(SISPART4, 0x0f, 0x3f);
reg = SiS_GetReg(SISPART4, 0x01);
if((reg & 0xf0) >= 0xb0) {
reg = SiS_GetReg(SISPART4, 0x23);
if(reg & 0x20) reg |= 0x40;
SiS_SetReg(SISPART4, 0x23, reg);
reg = (reg & 0x20) ? 0x02 : 0x00;
SiS_SetRegANDOR(SISPART1, 0x1e, 0xfd, reg);
}
}
v1 = bios[0x77];
reg = SiS_GetReg(SISSR, 0x3b);
if(reg & 0x02) {
reg = SiS_GetReg(SISSR, 0x3a);
v2 = (reg & 0x30) >> 3;
if(!(v2 & 0x04)) v2 ^= 0x02;
reg = SiS_GetReg(SISSR, 0x39);
if(reg & 0x80) v2 |= 0x80;
v2 |= 0x01;
if((mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0730, NULL))) {
pci_dev_put(mypdev);
if(((v2 & 0x06) == 2) || ((v2 & 0x06) == 4))
v2 &= 0xf9;
v2 |= 0x08;
v1 &= 0xfe;
} else {
mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0735, NULL);
if(!mypdev)
mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0645, NULL);
if(!mypdev)
mypdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0650, NULL);
if(mypdev) {
pci_read_config_dword(mypdev, 0x94, ®d);
regd &= 0xfffffeff;
pci_write_config_dword(mypdev, 0x94, regd);
v1 &= 0xfe;
pci_dev_put(mypdev);
} else if(sisfb_find_host_bridge(ivideo, pdev, PCI_VENDOR_ID_SI)) {
v1 &= 0xfe;
} else if(sisfb_find_host_bridge(ivideo, pdev, 0x1106) ||
sisfb_find_host_bridge(ivideo, pdev, 0x1022) ||
sisfb_find_host_bridge(ivideo, pdev, 0x700e) ||
sisfb_find_host_bridge(ivideo, pdev, 0x10de)) {
if((v2 & 0x06) == 4)
v2 ^= 0x06;
v2 |= 0x08;
}
}
SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, v2);
}
SiS_SetReg(SISSR, 0x22, v1);
if(ivideo->revision_id == 2) {
v1 = SiS_GetReg(SISSR, 0x3b);
v2 = SiS_GetReg(SISSR, 0x3a);
regd = bios[0x90 + 3] | (bios[0x90 + 4] << 8);
if( (!(v1 & 0x02)) && (v2 & 0x30) && (regd < 0xcf) )
SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01);
if((mypdev = pci_get_device(0x10de, 0x01e0, NULL))) {
/* TODO: set CR5f &0xf1 | 0x01 for version 6570
* of nforce 2 ROM
*/
if(0)
SiS_SetRegANDOR(SISCR, 0x5f, 0xf1, 0x01);
pci_dev_put(mypdev);
}
}
v1 = 0x30;
reg = SiS_GetReg(SISSR, 0x3b);
v2 = SiS_GetReg(SISCR, 0x5f);
if((!(reg & 0x02)) && (v2 & 0x0e))
v1 |= 0x08;
SiS_SetReg(SISSR, 0x27, v1);
if(bios[0x64] & 0x01) {
SiS_SetRegANDOR(SISCR, 0x5f, 0xf0, bios[0x64]);
}
v1 = bios[0x4f7];
pci_read_config_dword(pdev, 0x50, ®d);
regd = (regd >> 20) & 0x0f;
if(regd == 1) {
v1 &= 0xfc;
SiS_SetRegOR(SISCR, 0x5f, 0x08);
}
SiS_SetReg(SISCR, 0x48, v1);
SiS_SetRegANDOR(SISCR, 0x47, 0x04, bios[0x4f6] & 0xfb);
SiS_SetRegANDOR(SISCR, 0x49, 0xf0, bios[0x4f8] & 0x0f);
SiS_SetRegANDOR(SISCR, 0x4a, 0x60, bios[0x4f9] & 0x9f);
SiS_SetRegANDOR(SISCR, 0x4b, 0x08, bios[0x4fa] & 0xf7);
SiS_SetRegANDOR(SISCR, 0x4c, 0x80, bios[0x4fb] & 0x7f);
SiS_SetReg(SISCR, 0x70, bios[0x4fc]);
SiS_SetRegANDOR(SISCR, 0x71, 0xf0, bios[0x4fd] & 0x0f);
SiS_SetReg(SISCR, 0x74, 0xd0);
SiS_SetRegANDOR(SISCR, 0x74, 0xcf, bios[0x4fe] & 0x30);
SiS_SetRegANDOR(SISCR, 0x75, 0xe0, bios[0x4ff] & 0x1f);
SiS_SetRegANDOR(SISCR, 0x76, 0xe0, bios[0x500] & 0x1f);
v1 = bios[0x501];
if((mypdev = pci_get_device(0x8086, 0x2530, NULL))) {
v1 = 0xf0;
pci_dev_put(mypdev);
}
SiS_SetReg(SISCR, 0x77, v1);
}
/* RAM type:
*
* 0 == DDR1, 1 == DDR2, 2..7 == reserved?
*
* The code seems to written so that regb should equal ramtype,
* however, so far it has been hardcoded to 0. Enable other values only
* on XGI Z9, as it passes the POST, and add a warning for others.
*/
ramtype = sisfb_post_xgi_ramtype(ivideo);
if (!sisfb_xgi_is21(ivideo) && ramtype) {
dev_warn(&pdev->dev,
"RAM type something else than expected: %d\n",
ramtype);
regb = 0;
} else {
regb = ramtype;
}
v1 = 0xff;
if(ivideo->haveXGIROM) {
v1 = bios[0x140 + regb];
}
SiS_SetReg(SISCR, 0x6d, v1);
ptr = cs128;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x128];
}
for(i = 0, j = 0; i < 3; i++, j += 8) {
SiS_SetReg(SISCR, 0x68 + i, ptr[j + regb]);
}
ptr = cs31a;
ptr2 = cs33a;
if(ivideo->haveXGIROM) {
index = (ivideo->chip == XGI_20) ? 0x31a : 0x3a6;
ptr = (const u8 *)&bios[index];
ptr2 = (const u8 *)&bios[index + 0x20];
}
for(i = 0; i < 2; i++) {
if(i == 0) {
regd = le32_to_cpu(((u32 *)ptr)[regb]);
rega = 0x6b;
} else {
regd = le32_to_cpu(((u32 *)ptr2)[regb]);
rega = 0x6e;
}
reg = 0x00;
for(j = 0; j < 16; j++) {
reg &= 0xf3;
if(regd & 0x01) reg |= 0x04;
if(regd & 0x02) reg |= 0x08;
regd >>= 2;
SiS_SetReg(SISCR, rega, reg);
reg = SiS_GetReg(SISCR, rega);
reg = SiS_GetReg(SISCR, rega);
reg += 0x10;
}
}
SiS_SetRegAND(SISCR, 0x6e, 0xfc);
ptr = NULL;
if(ivideo->haveXGIROM) {
index = (ivideo->chip == XGI_20) ? 0x35a : 0x3e6;
ptr = (const u8 *)&bios[index];
}
for(i = 0; i < 4; i++) {
SiS_SetRegANDOR(SISCR, 0x6e, 0xfc, i);
reg = 0x00;
for(j = 0; j < 2; j++) {
regd = 0;
if(ptr) {
regd = le32_to_cpu(((u32 *)ptr)[regb * 8]);
ptr += 4;
}
/* reg = 0x00; */
for(k = 0; k < 16; k++) {
reg &= 0xfc;
if(regd & 0x01) reg |= 0x01;
if(regd & 0x02) reg |= 0x02;
regd >>= 2;
SiS_SetReg(SISCR, 0x6f, reg);
reg = SiS_GetReg(SISCR, 0x6f);
reg = SiS_GetReg(SISCR, 0x6f);
reg += 0x08;
}
}
}
ptr = cs148;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x148];
}
for(i = 0, j = 0; i < 2; i++, j += 8) {
SiS_SetReg(SISCR, 0x80 + i, ptr[j + regb]);
}
SiS_SetRegAND(SISCR, 0x89, 0x8f);
ptr = cs45a;
if(ivideo->haveXGIROM) {
index = (ivideo->chip == XGI_20) ? 0x45a : 0x4e6;
ptr = (const u8 *)&bios[index];
}
regd = le16_to_cpu(((const u16 *)ptr)[regb]);
reg = 0x80;
for(i = 0; i < 5; i++) {
reg &= 0xfc;
if(regd & 0x01) reg |= 0x01;
if(regd & 0x02) reg |= 0x02;
regd >>= 2;
SiS_SetReg(SISCR, 0x89, reg);
reg = SiS_GetReg(SISCR, 0x89);
reg = SiS_GetReg(SISCR, 0x89);
reg += 0x10;
}
v1 = 0xb5; v2 = 0x20; v3 = 0xf0; v4 = 0x13;
if(ivideo->haveXGIROM) {
v1 = bios[0x118 + regb];
v2 = bios[0xf8 + regb];
v3 = bios[0x120 + regb];
v4 = bios[0x1ca];
}
SiS_SetReg(SISCR, 0x45, v1 & 0x0f);
SiS_SetReg(SISCR, 0x99, (v1 >> 4) & 0x07);
SiS_SetRegOR(SISCR, 0x40, v1 & 0x80);
SiS_SetReg(SISCR, 0x41, v2);
ptr = cs170;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x170];
}
for(i = 0, j = 0; i < 7; i++, j += 8) {
SiS_SetReg(SISCR, 0x90 + i, ptr[j + regb]);
}
SiS_SetReg(SISCR, 0x59, v3);
ptr = cs1a8;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x1a8];
}
for(i = 0, j = 0; i < 3; i++, j += 8) {
SiS_SetReg(SISCR, 0xc3 + i, ptr[j + regb]);
}
ptr = cs100;
if(ivideo->haveXGIROM) {
ptr = (const u8 *)&bios[0x100];
}
for(i = 0, j = 0; i < 2; i++, j += 8) {
SiS_SetReg(SISCR, 0x8a + i, ptr[j + regb]);
}
SiS_SetReg(SISCR, 0xcf, v4);
SiS_SetReg(SISCR, 0x83, 0x09);
SiS_SetReg(SISCR, 0x87, 0x00);
if(ivideo->chip == XGI_40) {
if( (ivideo->revision_id == 1) ||
(ivideo->revision_id == 2) ) {
SiS_SetReg(SISCR, 0x8c, 0x87);
}
}
if (regb == 1)
SiS_SetReg(SISSR, 0x17, 0x80); /* DDR2 */
else
SiS_SetReg(SISSR, 0x17, 0x00); /* DDR1 */
SiS_SetReg(SISSR, 0x1a, 0x87);
if(ivideo->chip == XGI_20) {
SiS_SetReg(SISSR, 0x15, 0x00);
SiS_SetReg(SISSR, 0x1c, 0x00);
}
switch(ramtype) {
case 0:
sisfb_post_xgi_setclocks(ivideo, regb);
if((ivideo->chip == XGI_20) ||
(ivideo->revision_id == 1) ||
(ivideo->revision_id == 2)) {
v1 = cs158[regb]; v2 = cs160[regb]; v3 = cs168[regb];
if(ivideo->haveXGIROM) {
v1 = bios[regb + 0x158];
v2 = bios[regb + 0x160];
v3 = bios[regb + 0x168];
}
SiS_SetReg(SISCR, 0x82, v1);
SiS_SetReg(SISCR, 0x85, v2);
SiS_SetReg(SISCR, 0x86, v3);
} else {
SiS_SetReg(SISCR, 0x82, 0x88);
SiS_SetReg(SISCR, 0x86, 0x00);
reg = SiS_GetReg(SISCR, 0x86);
SiS_SetReg(SISCR, 0x86, 0x88);
reg = SiS_GetReg(SISCR, 0x86);
SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
SiS_SetReg(SISCR, 0x82, 0x77);
SiS_SetReg(SISCR, 0x85, 0x00);
reg = SiS_GetReg(SISCR, 0x85);
SiS_SetReg(SISCR, 0x85, 0x88);
reg = SiS_GetReg(SISCR, 0x85);
SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
}
if(ivideo->chip == XGI_40) {
SiS_SetReg(SISCR, 0x97, 0x00);
}
SiS_SetReg(SISCR, 0x98, 0x01);
SiS_SetReg(SISCR, 0x9a, 0x02);
SiS_SetReg(SISSR, 0x18, 0x01);
if((ivideo->chip == XGI_20) ||
(ivideo->revision_id == 2)) {
SiS_SetReg(SISSR, 0x19, 0x40);
} else {
SiS_SetReg(SISSR, 0x19, 0x20);
}
SiS_SetReg(SISSR, 0x16, 0x00);
SiS_SetReg(SISSR, 0x16, 0x80);
if((ivideo->chip == XGI_20) || (bios[0x1cb] != 0x0c)) {
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
SiS_SetReg(SISSR, 0x18, 0x00);
if((ivideo->chip == XGI_20) ||
(ivideo->revision_id == 2)) {
SiS_SetReg(SISSR, 0x19, 0x40);
} else {
SiS_SetReg(SISSR, 0x19, 0x20);
}
} else if((ivideo->chip == XGI_40) && (bios[0x1cb] == 0x0c)) {
/* SiS_SetReg(SISSR, 0x16, 0x0c); */ /* ? */
}
SiS_SetReg(SISSR, 0x16, 0x00);
SiS_SetReg(SISSR, 0x16, 0x80);
sisfb_post_xgi_delay(ivideo, 4);
v1 = 0x31; v2 = 0x03; v3 = 0x83; v4 = 0x03; v5 = 0x83;
if(ivideo->haveXGIROM) {
v1 = bios[0xf0];
index = (ivideo->chip == XGI_20) ? 0x4b2 : 0x53e;
v2 = bios[index];
v3 = bios[index + 1];
v4 = bios[index + 2];
v5 = bios[index + 3];
}
SiS_SetReg(SISSR, 0x18, v1);
SiS_SetReg(SISSR, 0x19, ((ivideo->chip == XGI_20) ? 0x02 : 0x01));
SiS_SetReg(SISSR, 0x16, v2);
SiS_SetReg(SISSR, 0x16, v3);
sisfb_post_xgi_delay(ivideo, 0x43);
SiS_SetReg(SISSR, 0x1b, 0x03);
sisfb_post_xgi_delay(ivideo, 0x22);
SiS_SetReg(SISSR, 0x18, v1);
SiS_SetReg(SISSR, 0x19, 0x00);
SiS_SetReg(SISSR, 0x16, v4);
SiS_SetReg(SISSR, 0x16, v5);
SiS_SetReg(SISSR, 0x1b, 0x00);
break;
case 1:
sisfb_post_xgi_ddr2(ivideo, regb);
break;
default:
sisfb_post_xgi_setclocks(ivideo, regb);
if((ivideo->chip == XGI_40) &&
((ivideo->revision_id == 1) ||
(ivideo->revision_id == 2))) {
SiS_SetReg(SISCR, 0x82, bios[regb + 0x158]);
SiS_SetReg(SISCR, 0x85, bios[regb + 0x160]);
SiS_SetReg(SISCR, 0x86, bios[regb + 0x168]);
} else {
SiS_SetReg(SISCR, 0x82, 0x88);
SiS_SetReg(SISCR, 0x86, 0x00);
reg = SiS_GetReg(SISCR, 0x86);
SiS_SetReg(SISCR, 0x86, 0x88);
SiS_SetReg(SISCR, 0x82, 0x77);
SiS_SetReg(SISCR, 0x85, 0x00);
reg = SiS_GetReg(SISCR, 0x85);
SiS_SetReg(SISCR, 0x85, 0x88);
reg = SiS_GetReg(SISCR, 0x85);
v1 = cs160[regb]; v2 = cs158[regb];
if(ivideo->haveXGIROM) {
v1 = bios[regb + 0x160];
v2 = bios[regb + 0x158];
}
SiS_SetReg(SISCR, 0x85, v1);
SiS_SetReg(SISCR, 0x82, v2);
}
if(ivideo->chip == XGI_40) {
SiS_SetReg(SISCR, 0x97, 0x11);
}
if((ivideo->chip == XGI_40) && (ivideo->revision_id == 2)) {
SiS_SetReg(SISCR, 0x98, 0x01);
} else {
SiS_SetReg(SISCR, 0x98, 0x03);
}
SiS_SetReg(SISCR, 0x9a, 0x02);
if(ivideo->chip == XGI_40) {
SiS_SetReg(SISSR, 0x18, 0x01);
} else {
SiS_SetReg(SISSR, 0x18, 0x00);
}
SiS_SetReg(SISSR, 0x19, 0x40);
SiS_SetReg(SISSR, 0x16, 0x00);
SiS_SetReg(SISSR, 0x16, 0x80);
if((ivideo->chip == XGI_40) && (bios[0x1cb] != 0x0c)) {
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
sisfb_post_xgi_delay(ivideo, 0x43);
SiS_SetReg(SISSR, 0x18, 0x00);
SiS_SetReg(SISSR, 0x19, 0x40);
SiS_SetReg(SISSR, 0x16, 0x00);
SiS_SetReg(SISSR, 0x16, 0x80);
}
sisfb_post_xgi_delay(ivideo, 4);
v1 = 0x31;
if(ivideo->haveXGIROM) {
v1 = bios[0xf0];
}
SiS_SetReg(SISSR, 0x18, v1);
SiS_SetReg(SISSR, 0x19, 0x01);
if(ivideo->chip == XGI_40) {
SiS_SetReg(SISSR, 0x16, bios[0x53e]);
SiS_SetReg(SISSR, 0x16, bios[0x53f]);
} else {
SiS_SetReg(SISSR, 0x16, 0x05);
SiS_SetReg(SISSR, 0x16, 0x85);
}
sisfb_post_xgi_delay(ivideo, 0x43);
if(ivideo->chip == XGI_40) {
SiS_SetReg(SISSR, 0x1b, 0x01);
} else {
SiS_SetReg(SISSR, 0x1b, 0x03);
}
sisfb_post_xgi_delay(ivideo, 0x22);
SiS_SetReg(SISSR, 0x18, v1);
SiS_SetReg(SISSR, 0x19, 0x00);
if(ivideo->chip == XGI_40) {
SiS_SetReg(SISSR, 0x16, bios[0x540]);
SiS_SetReg(SISSR, 0x16, bios[0x541]);
} else {
SiS_SetReg(SISSR, 0x16, 0x05);
SiS_SetReg(SISSR, 0x16, 0x85);
}
SiS_SetReg(SISSR, 0x1b, 0x00);
}
regb = 0; /* ! */
v1 = 0x03;
if(ivideo->haveXGIROM) {
v1 = bios[0x110 + regb];
}
SiS_SetReg(SISSR, 0x1b, v1);
/* RAM size */
v1 = 0x00; v2 = 0x00;
if(ivideo->haveXGIROM) {
v1 = bios[0x62];
v2 = bios[0x63];
}
regb = 0; /* ! */
regd = 1 << regb;
if((v1 & 0x40) && (v2 & regd) && ivideo->haveXGIROM) {
SiS_SetReg(SISSR, 0x13, bios[regb + 0xe0]);
SiS_SetReg(SISSR, 0x14, bios[regb + 0xe0 + 8]);
} else {
int err;
/* Set default mode, don't clear screen */
ivideo->SiS_Pr.SiS_UseOEM = false;
SiS_SetEnableDstn(&ivideo->SiS_Pr, false);
SiS_SetEnableFstn(&ivideo->SiS_Pr, false);
ivideo->curFSTN = ivideo->curDSTN = 0;
ivideo->SiS_Pr.VideoMemorySize = 8 << 20;
SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
SiS_SetReg(SISSR, 0x05, 0x86);
/* Disable read-cache */
SiS_SetRegAND(SISSR, 0x21, 0xdf);
err = sisfb_post_xgi_ramsize(ivideo);
/* Enable read-cache */
SiS_SetRegOR(SISSR, 0x21, 0x20);
if (err) {
dev_err(&pdev->dev,
"%s: RAM size detection failed: %d\n",
__func__, err);
return 0;
}
}
#if 0
printk(KERN_DEBUG "-----------------\n");
for(i = 0; i < 0xff; i++) {
reg = SiS_GetReg(SISCR, i);
printk(KERN_DEBUG "CR%02x(%x) = 0x%02x\n", i, SISCR, reg);
}
for(i = 0; i < 0x40; i++) {
reg = SiS_GetReg(SISSR, i);
printk(KERN_DEBUG "SR%02x(%x) = 0x%02x\n", i, SISSR, reg);
}
printk(KERN_DEBUG "-----------------\n");
#endif
/* Sense CRT1 */
if(ivideo->chip == XGI_20) {
SiS_SetRegOR(SISCR, 0x32, 0x20);
} else {
reg = SiS_GetReg(SISPART4, 0x00);
if((reg == 1) || (reg == 2)) {
sisfb_sense_crt1(ivideo);
} else {
SiS_SetRegOR(SISCR, 0x32, 0x20);
}
}
/* Set default mode, don't clear screen */
ivideo->SiS_Pr.SiS_UseOEM = false;
SiS_SetEnableDstn(&ivideo->SiS_Pr, false);
SiS_SetEnableFstn(&ivideo->SiS_Pr, false);
ivideo->curFSTN = ivideo->curDSTN = 0;
SiSSetMode(&ivideo->SiS_Pr, 0x2e | 0x80);
SiS_SetReg(SISSR, 0x05, 0x86);
/* Display off */
SiS_SetRegOR(SISSR, 0x01, 0x20);
/* Save mode number in CR34 */
SiS_SetReg(SISCR, 0x34, 0x2e);
/* Let everyone know what the current mode is */
ivideo->modeprechange = 0x2e;
if(ivideo->chip == XGI_40) {
reg = SiS_GetReg(SISCR, 0xca);
v1 = SiS_GetReg(SISCR, 0xcc);
if((reg & 0x10) && (!(v1 & 0x04))) {
printk(KERN_ERR
"sisfb: Please connect power to the card.\n");
return 0;
}
}
return 1;
}
#endif
static int sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct sisfb_chip_info *chipinfo = &sisfb_chip_info[ent->driver_data];
struct sis_video_info *ivideo = NULL;
struct fb_info *sis_fb_info = NULL;
u16 reg16;
u8 reg;
int i, ret;
if(sisfb_off)
return -ENXIO;
ret = aperture_remove_conflicting_pci_devices(pdev, "sisfb");
if (ret)
return ret;
sis_fb_info = framebuffer_alloc(sizeof(*ivideo), &pdev->dev);
if(!sis_fb_info)
return -ENOMEM;
ivideo = (struct sis_video_info *)sis_fb_info->par;
ivideo->memyselfandi = sis_fb_info;
ivideo->sisfb_id = SISFB_ID;
if(card_list == NULL) {
ivideo->cardnumber = 0;
} else {
struct sis_video_info *countvideo = card_list;
ivideo->cardnumber = 1;
while((countvideo = countvideo->next) != NULL)
ivideo->cardnumber++;
}
strscpy(ivideo->myid, chipinfo->chip_name, sizeof(ivideo->myid));
ivideo->warncount = 0;
ivideo->chip_id = pdev->device;
ivideo->chip_vendor = pdev->vendor;
ivideo->revision_id = pdev->revision;
ivideo->SiS_Pr.ChipRevision = ivideo->revision_id;
pci_read_config_word(pdev, PCI_COMMAND, ®16);
ivideo->sisvga_enabled = reg16 & 0x01;
ivideo->pcibus = pdev->bus->number;
ivideo->pcislot = PCI_SLOT(pdev->devfn);
ivideo->pcifunc = PCI_FUNC(pdev->devfn);
ivideo->subsysvendor = pdev->subsystem_vendor;
ivideo->subsysdevice = pdev->subsystem_device;
#ifndef MODULE
if(sisfb_mode_idx == -1) {
sisfb_get_vga_mode_from_kernel();
}
#endif
ivideo->chip = chipinfo->chip;
ivideo->chip_real_id = chipinfo->chip;
ivideo->sisvga_engine = chipinfo->vgaengine;
ivideo->hwcursor_size = chipinfo->hwcursor_size;
ivideo->CRT2_write_enable = chipinfo->CRT2_write_enable;
ivideo->mni = chipinfo->mni;
ivideo->detectedpdc = 0xff;
ivideo->detectedpdca = 0xff;
ivideo->detectedlcda = 0xff;
ivideo->sisfb_thismonitor.datavalid = false;
ivideo->current_base = 0;
ivideo->engineok = 0;
ivideo->sisfb_was_boot_device = 0;
if(pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW) {
if(ivideo->sisvga_enabled)
ivideo->sisfb_was_boot_device = 1;
else {
printk(KERN_DEBUG "sisfb: PCI device is disabled, "
"but marked as boot video device ???\n");
printk(KERN_DEBUG "sisfb: I will not accept this "
"as the primary VGA device\n");
}
}
ivideo->sisfb_parm_mem = sisfb_parm_mem;
ivideo->sisfb_accel = sisfb_accel;
ivideo->sisfb_ypan = sisfb_ypan;
ivideo->sisfb_max = sisfb_max;
ivideo->sisfb_userom = sisfb_userom;
ivideo->sisfb_useoem = sisfb_useoem;
ivideo->sisfb_mode_idx = sisfb_mode_idx;
ivideo->sisfb_parm_rate = sisfb_parm_rate;
ivideo->sisfb_crt1off = sisfb_crt1off;
ivideo->sisfb_forcecrt1 = sisfb_forcecrt1;
ivideo->sisfb_crt2type = sisfb_crt2type;
ivideo->sisfb_crt2flags = sisfb_crt2flags;
/* pdc(a), scalelcd, special timing, lvdshl handled below */
ivideo->sisfb_dstn = sisfb_dstn;
ivideo->sisfb_fstn = sisfb_fstn;
ivideo->sisfb_tvplug = sisfb_tvplug;
ivideo->sisfb_tvstd = sisfb_tvstd;
ivideo->tvxpos = sisfb_tvxposoffset;
ivideo->tvypos = sisfb_tvyposoffset;
ivideo->sisfb_nocrt2rate = sisfb_nocrt2rate;
ivideo->refresh_rate = 0;
if(ivideo->sisfb_parm_rate != -1) {
ivideo->refresh_rate = ivideo->sisfb_parm_rate;
}
ivideo->SiS_Pr.UsePanelScaler = sisfb_scalelcd;
ivideo->SiS_Pr.CenterScreen = -1;
ivideo->SiS_Pr.SiS_CustomT = sisfb_specialtiming;
ivideo->SiS_Pr.LVDSHL = sisfb_lvdshl;
ivideo->SiS_Pr.SiS_Backup70xx = 0xff;
ivideo->SiS_Pr.SiS_CHOverScan = -1;
ivideo->SiS_Pr.SiS_ChSW = false;
ivideo->SiS_Pr.SiS_UseLCDA = false;
ivideo->SiS_Pr.HaveEMI = false;
ivideo->SiS_Pr.HaveEMILCD = false;
ivideo->SiS_Pr.OverruleEMI = false;
ivideo->SiS_Pr.SiS_SensibleSR11 = false;
ivideo->SiS_Pr.SiS_MyCR63 = 0x63;
ivideo->SiS_Pr.PDC = -1;
ivideo->SiS_Pr.PDCA = -1;
ivideo->SiS_Pr.DDCPortMixup = false;
#ifdef CONFIG_FB_SIS_315
if(ivideo->chip >= SIS_330) {
ivideo->SiS_Pr.SiS_MyCR63 = 0x53;
if(ivideo->chip >= SIS_661) {
ivideo->SiS_Pr.SiS_SensibleSR11 = true;
}
}
#endif
memcpy(&ivideo->default_var, &my_default_var, sizeof(my_default_var));
pci_set_drvdata(pdev, ivideo);
/* Patch special cases */
if((ivideo->nbridge = sisfb_get_northbridge(ivideo->chip))) {
switch(ivideo->nbridge->device) {
#ifdef CONFIG_FB_SIS_300
case PCI_DEVICE_ID_SI_730:
ivideo->chip = SIS_730;
strcpy(ivideo->myid, "SiS 730");
break;
#endif
#ifdef CONFIG_FB_SIS_315
case PCI_DEVICE_ID_SI_651:
/* ivideo->chip is ok */
strcpy(ivideo->myid, "SiS 651");
break;
case PCI_DEVICE_ID_SI_740:
ivideo->chip = SIS_740;
strcpy(ivideo->myid, "SiS 740");
break;
case PCI_DEVICE_ID_SI_661:
ivideo->chip = SIS_661;
strcpy(ivideo->myid, "SiS 661");
break;
case PCI_DEVICE_ID_SI_741:
ivideo->chip = SIS_741;
strcpy(ivideo->myid, "SiS 741");
break;
case PCI_DEVICE_ID_SI_760:
ivideo->chip = SIS_760;
strcpy(ivideo->myid, "SiS 760");
break;
case PCI_DEVICE_ID_SI_761:
ivideo->chip = SIS_761;
strcpy(ivideo->myid, "SiS 761");
break;
#endif
default:
break;
}
}
ivideo->SiS_Pr.ChipType = ivideo->chip;
ivideo->SiS_Pr.ivideo = (void *)ivideo;
#ifdef CONFIG_FB_SIS_315
if((ivideo->SiS_Pr.ChipType == SIS_315PRO) ||
(ivideo->SiS_Pr.ChipType == SIS_315)) {
ivideo->SiS_Pr.ChipType = SIS_315H;
}
#endif
if(!ivideo->sisvga_enabled) {
if(pci_enable_device(pdev)) {
pci_dev_put(ivideo->nbridge);
framebuffer_release(sis_fb_info);
return -EIO;
}
}
ivideo->video_base = pci_resource_start(pdev, 0);
ivideo->video_size = pci_resource_len(pdev, 0);
ivideo->mmio_base = pci_resource_start(pdev, 1);
ivideo->mmio_size = pci_resource_len(pdev, 1);
ivideo->SiS_Pr.RelIO = pci_resource_start(pdev, 2) + 0x30;
ivideo->SiS_Pr.IOAddress = ivideo->vga_base = ivideo->SiS_Pr.RelIO;
SiSRegInit(&ivideo->SiS_Pr, ivideo->SiS_Pr.IOAddress);
#ifdef CONFIG_FB_SIS_300
/* Find PCI systems for Chrontel/GPIO communication setup */
if(ivideo->chip == SIS_630) {
i = 0;
do {
if(mychswtable[i].subsysVendor == ivideo->subsysvendor &&
mychswtable[i].subsysCard == ivideo->subsysdevice) {
ivideo->SiS_Pr.SiS_ChSW = true;
printk(KERN_DEBUG "sisfb: Identified [%s %s] "
"requiring Chrontel/GPIO setup\n",
mychswtable[i].vendorName,
mychswtable[i].cardName);
ivideo->lpcdev = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, NULL);
break;
}
i++;
} while(mychswtable[i].subsysVendor != 0);
}
#endif
#ifdef CONFIG_FB_SIS_315
if((ivideo->chip == SIS_760) && (ivideo->nbridge)) {
ivideo->lpcdev = pci_get_slot(ivideo->nbridge->bus, (2 << 3));
}
#endif
SiS_SetReg(SISSR, 0x05, 0x86);
if( (!ivideo->sisvga_enabled)
#if !defined(__i386__) && !defined(__x86_64__)
|| (sisfb_resetcard)
#endif
) {
for(i = 0x30; i <= 0x3f; i++) {
SiS_SetReg(SISCR, i, 0x00);
}
}
/* Find out about current video mode */
ivideo->modeprechange = 0x03;
reg = SiS_GetReg(SISCR, 0x34);
if(reg & 0x7f) {
ivideo->modeprechange = reg & 0x7f;
} else if(ivideo->sisvga_enabled) {
#if defined(__i386__) || defined(__x86_64__)
unsigned char __iomem *tt = ioremap(0x400, 0x100);
if(tt) {
ivideo->modeprechange = readb(tt + 0x49);
iounmap(tt);
}
#endif
}
/* Search and copy ROM image */
ivideo->bios_abase = NULL;
ivideo->SiS_Pr.VirtualRomBase = NULL;
ivideo->SiS_Pr.UseROM = false;
ivideo->haveXGIROM = ivideo->SiS_Pr.SiS_XGIROM = false;
if(ivideo->sisfb_userom) {
ivideo->SiS_Pr.VirtualRomBase = sisfb_find_rom(pdev);
ivideo->bios_abase = ivideo->SiS_Pr.VirtualRomBase;
ivideo->SiS_Pr.UseROM = (bool)(ivideo->SiS_Pr.VirtualRomBase);
printk(KERN_INFO "sisfb: Video ROM %sfound\n",
ivideo->SiS_Pr.UseROM ? "" : "not ");
if((ivideo->SiS_Pr.UseROM) && (ivideo->chip >= XGI_20)) {
ivideo->SiS_Pr.UseROM = false;
ivideo->haveXGIROM = ivideo->SiS_Pr.SiS_XGIROM = true;
if( (ivideo->revision_id == 2) &&
(!(ivideo->bios_abase[0x1d1] & 0x01)) ) {
ivideo->SiS_Pr.DDCPortMixup = true;
}
}
} else {
printk(KERN_INFO "sisfb: Video ROM usage disabled\n");
}
/* Find systems for special custom timing */
if(ivideo->SiS_Pr.SiS_CustomT == CUT_NONE) {
sisfb_detect_custom_timing(ivideo);
}
#ifdef CONFIG_FB_SIS_315
if (ivideo->chip == XGI_20) {
/* Check if our Z7 chip is actually Z9 */
SiS_SetRegOR(SISCR, 0x4a, 0x40); /* GPIOG EN */
reg = SiS_GetReg(SISCR, 0x48);
if (reg & 0x02) { /* GPIOG */
ivideo->chip_real_id = XGI_21;
dev_info(&pdev->dev, "Z9 detected\n");
}
}
#endif
/* POST card in case this has not been done by the BIOS */
if( (!ivideo->sisvga_enabled)
#if !defined(__i386__) && !defined(__x86_64__)
|| (sisfb_resetcard)
#endif
) {
#ifdef CONFIG_FB_SIS_300
if(ivideo->sisvga_engine == SIS_300_VGA) {
if(ivideo->chip == SIS_300) {
sisfb_post_sis300(pdev);
ivideo->sisfb_can_post = 1;
}
}
#endif
#ifdef CONFIG_FB_SIS_315
if (ivideo->sisvga_engine == SIS_315_VGA) {
int result = 1;
if (ivideo->chip == XGI_20) {
result = sisfb_post_xgi(pdev);
ivideo->sisfb_can_post = 1;
} else if ((ivideo->chip == XGI_40) && ivideo->haveXGIROM) {
result = sisfb_post_xgi(pdev);
ivideo->sisfb_can_post = 1;
} else {
printk(KERN_INFO "sisfb: Card is not "
"POSTed and sisfb can't do this either.\n");
}
if (!result) {
printk(KERN_ERR "sisfb: Failed to POST card\n");
ret = -ENODEV;
goto error_3;
}
}
#endif
}
ivideo->sisfb_card_posted = 1;
/* Find out about RAM size */
if(sisfb_get_dram_size(ivideo)) {
printk(KERN_INFO "sisfb: Fatal error: Unable to determine VRAM size.\n");
ret = -ENODEV;
goto error_3;
}
/* Enable PCI addressing and MMIO */
if((ivideo->sisfb_mode_idx < 0) ||
((sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni]) != 0xFF)) {
/* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */
SiS_SetRegOR(SISSR, IND_SIS_PCI_ADDRESS_SET, (SIS_PCI_ADDR_ENABLE | SIS_MEM_MAP_IO_ENABLE));
/* Enable 2D accelerator engine */
SiS_SetRegOR(SISSR, IND_SIS_MODULE_ENABLE, SIS_ENABLE_2D);
}
if(sisfb_pdc != 0xff) {
if(ivideo->sisvga_engine == SIS_300_VGA)
sisfb_pdc &= 0x3c;
else
sisfb_pdc &= 0x1f;
ivideo->SiS_Pr.PDC = sisfb_pdc;
}
#ifdef CONFIG_FB_SIS_315
if(ivideo->sisvga_engine == SIS_315_VGA) {
if(sisfb_pdca != 0xff)
ivideo->SiS_Pr.PDCA = sisfb_pdca & 0x1f;
}
#endif
if(!request_mem_region(ivideo->video_base, ivideo->video_size, "sisfb FB")) {
printk(KERN_ERR "sisfb: Fatal error: Unable to reserve %dMB framebuffer memory\n",
(int)(ivideo->video_size >> 20));
printk(KERN_ERR "sisfb: Is there another framebuffer driver active?\n");
ret = -ENODEV;
goto error_3;
}
if(!request_mem_region(ivideo->mmio_base, ivideo->mmio_size, "sisfb MMIO")) {
printk(KERN_ERR "sisfb: Fatal error: Unable to reserve MMIO region\n");
ret = -ENODEV;
goto error_2;
}
ivideo->video_vbase = ioremap_wc(ivideo->video_base, ivideo->video_size);
ivideo->SiS_Pr.VideoMemoryAddress = ivideo->video_vbase;
if(!ivideo->video_vbase) {
printk(KERN_ERR "sisfb: Fatal error: Unable to map framebuffer memory\n");
ret = -ENODEV;
goto error_1;
}
ivideo->mmio_vbase = ioremap(ivideo->mmio_base, ivideo->mmio_size);
if(!ivideo->mmio_vbase) {
printk(KERN_ERR "sisfb: Fatal error: Unable to map MMIO region\n");
ret = -ENODEV;
error_0: iounmap(ivideo->video_vbase);
error_1: release_mem_region(ivideo->video_base, ivideo->video_size);
error_2: release_mem_region(ivideo->mmio_base, ivideo->mmio_size);
error_3: vfree(ivideo->bios_abase);
pci_dev_put(ivideo->lpcdev);
pci_dev_put(ivideo->nbridge);
if(!ivideo->sisvga_enabled)
pci_disable_device(pdev);
framebuffer_release(sis_fb_info);
return ret;
}
printk(KERN_INFO "sisfb: Video RAM at 0x%lx, mapped to 0x%lx, size %ldk\n",
ivideo->video_base, (unsigned long)ivideo->video_vbase, ivideo->video_size / 1024);
if(ivideo->video_offset) {
printk(KERN_INFO "sisfb: Viewport offset %ldk\n",
ivideo->video_offset / 1024);
}
printk(KERN_INFO "sisfb: MMIO at 0x%lx, mapped to 0x%lx, size %ldk\n",
ivideo->mmio_base, (unsigned long)ivideo->mmio_vbase, ivideo->mmio_size / 1024);
/* Determine the size of the command queue */
if(ivideo->sisvga_engine == SIS_300_VGA) {
ivideo->cmdQueueSize = TURBO_QUEUE_AREA_SIZE;
} else {
if(ivideo->chip == XGI_20) {
ivideo->cmdQueueSize = COMMAND_QUEUE_AREA_SIZE_Z7;
} else {
ivideo->cmdQueueSize = COMMAND_QUEUE_AREA_SIZE;
}
}
/* Engines are no longer initialized here; this is
* now done after the first mode-switch (if the
* submitted var has its acceleration flags set).
*/
/* Calculate the base of the (unused) hw cursor */
ivideo->hwcursor_vbase = ivideo->video_vbase
+ ivideo->video_size
- ivideo->cmdQueueSize
- ivideo->hwcursor_size;
ivideo->caps |= HW_CURSOR_CAP;
/* Initialize offscreen memory manager */
if((ivideo->havenoheap = sisfb_heap_init(ivideo))) {
printk(KERN_WARNING "sisfb: Failed to initialize offscreen memory heap\n");
}
/* Used for clearing the screen only, therefore respect our mem limit */
ivideo->SiS_Pr.VideoMemoryAddress += ivideo->video_offset;
ivideo->SiS_Pr.VideoMemorySize = ivideo->sisfb_mem;
ivideo->vbflags = 0;
ivideo->lcddefmodeidx = DEFAULT_LCDMODE;
ivideo->tvdefmodeidx = DEFAULT_TVMODE;
ivideo->defmodeidx = DEFAULT_MODE;
ivideo->newrom = 0;
if(ivideo->chip < XGI_20) {
if(ivideo->bios_abase) {
ivideo->newrom = SiSDetermineROMLayout661(&ivideo->SiS_Pr);
}
}
if((ivideo->sisfb_mode_idx < 0) ||
((sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni]) != 0xFF)) {
sisfb_sense_crt1(ivideo);
sisfb_get_VB_type(ivideo);
if(ivideo->vbflags2 & VB2_VIDEOBRIDGE) {
sisfb_detect_VB_connect(ivideo);
}
ivideo->currentvbflags = ivideo->vbflags & (VB_VIDEOBRIDGE | TV_STANDARD);
/* Decide on which CRT2 device to use */
if(ivideo->vbflags2 & VB2_VIDEOBRIDGE) {
if(ivideo->sisfb_crt2type != -1) {
if((ivideo->sisfb_crt2type == CRT2_LCD) &&
(ivideo->vbflags & CRT2_LCD)) {
ivideo->currentvbflags |= CRT2_LCD;
} else if(ivideo->sisfb_crt2type != CRT2_LCD) {
ivideo->currentvbflags |= ivideo->sisfb_crt2type;
}
} else {
/* Chrontel 700x TV detection often unreliable, therefore
* use a different default order on such machines
*/
if((ivideo->sisvga_engine == SIS_300_VGA) &&
(ivideo->vbflags2 & VB2_CHRONTEL)) {
if(ivideo->vbflags & CRT2_LCD)
ivideo->currentvbflags |= CRT2_LCD;
else if(ivideo->vbflags & CRT2_TV)
ivideo->currentvbflags |= CRT2_TV;
else if(ivideo->vbflags & CRT2_VGA)
ivideo->currentvbflags |= CRT2_VGA;
} else {
if(ivideo->vbflags & CRT2_TV)
ivideo->currentvbflags |= CRT2_TV;
else if(ivideo->vbflags & CRT2_LCD)
ivideo->currentvbflags |= CRT2_LCD;
else if(ivideo->vbflags & CRT2_VGA)
ivideo->currentvbflags |= CRT2_VGA;
}
}
}
if(ivideo->vbflags & CRT2_LCD) {
sisfb_detect_lcd_type(ivideo);
}
sisfb_save_pdc_emi(ivideo);
if(!ivideo->sisfb_crt1off) {
sisfb_handle_ddc(ivideo, &ivideo->sisfb_thismonitor, 0);
} else {
if((ivideo->vbflags2 & VB2_SISTMDSBRIDGE) &&
(ivideo->vbflags & (CRT2_VGA | CRT2_LCD))) {
sisfb_handle_ddc(ivideo, &ivideo->sisfb_thismonitor, 1);
}
}
if(ivideo->sisfb_mode_idx >= 0) {
int bu = ivideo->sisfb_mode_idx;
ivideo->sisfb_mode_idx = sisfb_validate_mode(ivideo,
ivideo->sisfb_mode_idx, ivideo->currentvbflags);
if(bu != ivideo->sisfb_mode_idx) {
printk(KERN_ERR "Mode %dx%dx%d failed validation\n",
sisbios_mode[bu].xres,
sisbios_mode[bu].yres,
sisbios_mode[bu].bpp);
}
}
if(ivideo->sisfb_mode_idx < 0) {
switch(ivideo->currentvbflags & VB_DISPTYPE_DISP2) {
case CRT2_LCD:
ivideo->sisfb_mode_idx = ivideo->lcddefmodeidx;
break;
case CRT2_TV:
ivideo->sisfb_mode_idx = ivideo->tvdefmodeidx;
break;
default:
ivideo->sisfb_mode_idx = ivideo->defmodeidx;
break;
}
}
ivideo->mode_no = sisbios_mode[ivideo->sisfb_mode_idx].mode_no[ivideo->mni];
if(ivideo->refresh_rate != 0) {
sisfb_search_refresh_rate(ivideo, ivideo->refresh_rate,
ivideo->sisfb_mode_idx);
}
if(ivideo->rate_idx == 0) {
ivideo->rate_idx = sisbios_mode[ivideo->sisfb_mode_idx].rate_idx;
ivideo->refresh_rate = 60;
}
if(ivideo->sisfb_thismonitor.datavalid) {
if(!sisfb_verify_rate(ivideo, &ivideo->sisfb_thismonitor,
ivideo->sisfb_mode_idx,
ivideo->rate_idx,
ivideo->refresh_rate)) {
printk(KERN_INFO "sisfb: WARNING: Refresh rate "
"exceeds monitor specs!\n");
}
}
ivideo->video_bpp = sisbios_mode[ivideo->sisfb_mode_idx].bpp;
ivideo->video_width = sisbios_mode[ivideo->sisfb_mode_idx].xres;
ivideo->video_height = sisbios_mode[ivideo->sisfb_mode_idx].yres;
sisfb_set_vparms(ivideo);
printk(KERN_INFO "sisfb: Default mode is %dx%dx%d (%dHz)\n",
ivideo->video_width, ivideo->video_height, ivideo->video_bpp,
ivideo->refresh_rate);
/* Set up the default var according to chosen default display mode */
ivideo->default_var.xres = ivideo->default_var.xres_virtual = ivideo->video_width;
ivideo->default_var.yres = ivideo->default_var.yres_virtual = ivideo->video_height;
ivideo->default_var.bits_per_pixel = ivideo->video_bpp;
sisfb_bpp_to_var(ivideo, &ivideo->default_var);
ivideo->default_var.pixclock = (u32) (1000000000 /
sisfb_mode_rate_to_dclock(&ivideo->SiS_Pr, ivideo->mode_no, ivideo->rate_idx));
if(sisfb_mode_rate_to_ddata(&ivideo->SiS_Pr, ivideo->mode_no,
ivideo->rate_idx, &ivideo->default_var)) {
if((ivideo->default_var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
ivideo->default_var.pixclock <<= 1;
}
}
if(ivideo->sisfb_ypan) {
/* Maximize regardless of sisfb_max at startup */
ivideo->default_var.yres_virtual =
sisfb_calc_maxyres(ivideo, &ivideo->default_var);
if(ivideo->default_var.yres_virtual < ivideo->default_var.yres) {
ivideo->default_var.yres_virtual = ivideo->default_var.yres;
}
}
sisfb_calc_pitch(ivideo, &ivideo->default_var);
ivideo->accel = 0;
if(ivideo->sisfb_accel) {
ivideo->accel = -1;
#ifdef STUPID_ACCELF_TEXT_SHIT
ivideo->default_var.accel_flags |= FB_ACCELF_TEXT;
#endif
}
sisfb_initaccel(ivideo);
#if defined(FBINFO_HWACCEL_DISABLED) && defined(FBINFO_HWACCEL_XPAN)
sis_fb_info->flags = FBINFO_HWACCEL_YPAN |
FBINFO_HWACCEL_XPAN |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT |
((ivideo->accel) ? 0 : FBINFO_HWACCEL_DISABLED);
#endif
sis_fb_info->var = ivideo->default_var;
sis_fb_info->fix = ivideo->sisfb_fix;
sis_fb_info->screen_base = ivideo->video_vbase + ivideo->video_offset;
sis_fb_info->fbops = &sisfb_ops;
sis_fb_info->pseudo_palette = ivideo->pseudo_palette;
fb_alloc_cmap(&sis_fb_info->cmap, 256 , 0);
printk(KERN_DEBUG "sisfb: Initial vbflags 0x%x\n", (int)ivideo->vbflags);
ivideo->wc_cookie = arch_phys_wc_add(ivideo->video_base,
ivideo->video_size);
if(register_framebuffer(sis_fb_info) < 0) {
printk(KERN_ERR "sisfb: Fatal error: Failed to register framebuffer\n");
ret = -EINVAL;
iounmap(ivideo->mmio_vbase);
goto error_0;
}
ivideo->registered = 1;
/* Enlist us */
ivideo->next = card_list;
card_list = ivideo;
printk(KERN_INFO "sisfb: 2D acceleration is %s, y-panning %s\n",
ivideo->sisfb_accel ? "enabled" : "disabled",
ivideo->sisfb_ypan ?
(ivideo->sisfb_max ? "enabled (auto-max)" :
"enabled (no auto-max)") :
"disabled");
fb_info(sis_fb_info, "%s frame buffer device version %d.%d.%d\n",
ivideo->myid, VER_MAJOR, VER_MINOR, VER_LEVEL);
printk(KERN_INFO "sisfb: Copyright (C) 2001-2005 Thomas Winischhofer\n");
} /* if mode = "none" */
return 0;
}
/*****************************************************/
/* PCI DEVICE HANDLING */
/*****************************************************/
static void sisfb_remove(struct pci_dev *pdev)
{
struct sis_video_info *ivideo = pci_get_drvdata(pdev);
struct fb_info *sis_fb_info = ivideo->memyselfandi;
int registered = ivideo->registered;
int modechanged = ivideo->modechanged;
/* Unmap */
iounmap(ivideo->mmio_vbase);
iounmap(ivideo->video_vbase);
/* Release mem regions */
release_mem_region(ivideo->video_base, ivideo->video_size);
release_mem_region(ivideo->mmio_base, ivideo->mmio_size);
vfree(ivideo->bios_abase);
pci_dev_put(ivideo->lpcdev);
pci_dev_put(ivideo->nbridge);
arch_phys_wc_del(ivideo->wc_cookie);
/* If device was disabled when starting, disable
* it when quitting.
*/
if(!ivideo->sisvga_enabled)
pci_disable_device(pdev);
/* Unregister the framebuffer */
if(ivideo->registered) {
unregister_framebuffer(sis_fb_info);
framebuffer_release(sis_fb_info);
}
/* OK, our ivideo is gone for good from here. */
/* TODO: Restore the initial mode
* This sounds easy but is as good as impossible
* on many machines with SiS chip and video bridge
* since text modes are always set up differently
* from machine to machine. Depends on the type
* of integration between chipset and bridge.
*/
if(registered && modechanged)
printk(KERN_INFO
"sisfb: Restoring of text mode not supported yet\n");
};
static struct pci_driver sisfb_driver = {
.name = "sisfb",
.id_table = sisfb_pci_table,
.probe = sisfb_probe,
.remove = sisfb_remove,
};
static int __init sisfb_init(void)
{
#ifndef MODULE
char *options = NULL;
#endif
if (fb_modesetting_disabled("sisfb"))
return -ENODEV;
#ifndef MODULE
if(fb_get_options("sisfb", &options))
return -ENODEV;
sisfb_setup(options);
#endif
return pci_register_driver(&sisfb_driver);
}
#ifndef MODULE
module_init(sisfb_init);
#endif
/*****************************************************/
/* MODULE */
/*****************************************************/
#ifdef MODULE
static char *mode = NULL;
static int vesa = -1;
static unsigned int rate = 0;
static unsigned int crt1off = 1;
static unsigned int mem = 0;
static char *forcecrt2type = NULL;
static int forcecrt1 = -1;
static int pdc = -1;
static int pdc1 = -1;
static int noaccel = -1;
static int noypan = -1;
static int nomax = -1;
static int userom = -1;
static int useoem = -1;
static char *tvstandard = NULL;
static int nocrt2rate = 0;
static int scalelcd = -1;
static char *specialtiming = NULL;
static int lvdshl = -1;
static int tvxposoffset = 0, tvyposoffset = 0;
#if !defined(__i386__) && !defined(__x86_64__)
static int resetcard = 0;
static int videoram = 0;
#endif
static int __init sisfb_init_module(void)
{
sisfb_setdefaultparms();
if(rate)
sisfb_parm_rate = rate;
if((scalelcd == 0) || (scalelcd == 1))
sisfb_scalelcd = scalelcd ^ 1;
/* Need to check crt2 type first for fstn/dstn */
if(forcecrt2type)
sisfb_search_crt2type(forcecrt2type);
if(tvstandard)
sisfb_search_tvstd(tvstandard);
if(mode)
sisfb_search_mode(mode, false);
else if(vesa != -1)
sisfb_search_vesamode(vesa, false);
sisfb_crt1off = (crt1off == 0) ? 1 : 0;
sisfb_forcecrt1 = forcecrt1;
if(forcecrt1 == 1)
sisfb_crt1off = 0;
else if(forcecrt1 == 0)
sisfb_crt1off = 1;
if(noaccel == 1)
sisfb_accel = 0;
else if(noaccel == 0)
sisfb_accel = 1;
if(noypan == 1)
sisfb_ypan = 0;
else if(noypan == 0)
sisfb_ypan = 1;
if(nomax == 1)
sisfb_max = 0;
else if(nomax == 0)
sisfb_max = 1;
if(mem)
sisfb_parm_mem = mem;
if(userom != -1)
sisfb_userom = userom;
if(useoem != -1)
sisfb_useoem = useoem;
if(pdc != -1)
sisfb_pdc = (pdc & 0x7f);
if(pdc1 != -1)
sisfb_pdca = (pdc1 & 0x1f);
sisfb_nocrt2rate = nocrt2rate;
if(specialtiming)
sisfb_search_specialtiming(specialtiming);
if((lvdshl >= 0) && (lvdshl <= 3))
sisfb_lvdshl = lvdshl;
sisfb_tvxposoffset = tvxposoffset;
sisfb_tvyposoffset = tvyposoffset;
#if !defined(__i386__) && !defined(__x86_64__)
sisfb_resetcard = (resetcard) ? 1 : 0;
if(videoram)
sisfb_videoram = videoram;
#endif
return sisfb_init();
}
static void __exit sisfb_remove_module(void)
{
pci_unregister_driver(&sisfb_driver);
printk(KERN_DEBUG "sisfb: Module unloaded\n");
}
module_init(sisfb_init_module);
module_exit(sisfb_remove_module);
MODULE_DESCRIPTION("SiS 300/540/630/730/315/55x/65x/661/74x/330/76x/34x, XGI V3XT/V5/V8/Z7 framebuffer device driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Thomas Winischhofer <[email protected]>, Others");
module_param(mem, int, 0);
module_param(noaccel, int, 0);
module_param(noypan, int, 0);
module_param(nomax, int, 0);
module_param(userom, int, 0);
module_param(useoem, int, 0);
module_param(mode, charp, 0);
module_param(vesa, int, 0);
module_param(rate, int, 0);
module_param(forcecrt1, int, 0);
module_param(forcecrt2type, charp, 0);
module_param(scalelcd, int, 0);
module_param(pdc, int, 0);
module_param(pdc1, int, 0);
module_param(specialtiming, charp, 0);
module_param(lvdshl, int, 0);
module_param(tvstandard, charp, 0);
module_param(tvxposoffset, int, 0);
module_param(tvyposoffset, int, 0);
module_param(nocrt2rate, int, 0);
#if !defined(__i386__) && !defined(__x86_64__)
module_param(resetcard, int, 0);
module_param(videoram, int, 0);
#endif
MODULE_PARM_DESC(mem,
"\nDetermines the beginning of the video memory heap in KB. This heap is used\n"
"for video RAM management for eg. DRM/DRI. On 300 series, the default depends\n"
"on the amount of video RAM available. If 8MB of video RAM or less is available,\n"
"the heap starts at 4096KB, if between 8 and 16MB are available at 8192KB,\n"
"otherwise at 12288KB. On 315/330/340 series, the heap size is 32KB by default.\n"
"The value is to be specified without 'KB'.\n");
MODULE_PARM_DESC(noaccel,
"\nIf set to anything other than 0, 2D acceleration will be disabled.\n"
"(default: 0)\n");
MODULE_PARM_DESC(noypan,
"\nIf set to anything other than 0, y-panning will be disabled and scrolling\n"
"will be performed by redrawing the screen. (default: 0)\n");
MODULE_PARM_DESC(nomax,
"\nIf y-panning is enabled, sisfb will by default use the entire available video\n"
"memory for the virtual screen in order to optimize scrolling performance. If\n"
"this is set to anything other than 0, sisfb will not do this and thereby \n"
"enable the user to positively specify a virtual Y size of the screen using\n"
"fbset. (default: 0)\n");
MODULE_PARM_DESC(mode,
"\nSelects the desired default display mode in the format XxYxDepth,\n"
"eg. 1024x768x16. Other formats supported include XxY-Depth and\n"
"XxY-Depth@Rate. If the parameter is only one (decimal or hexadecimal)\n"
"number, it will be interpreted as a VESA mode number. (default: 800x600x8)\n");
MODULE_PARM_DESC(vesa,
"\nSelects the desired default display mode by VESA defined mode number, eg.\n"
"0x117 (default: 0x0103)\n");
MODULE_PARM_DESC(rate,
"\nSelects the desired vertical refresh rate for CRT1 (external VGA) in Hz.\n"
"If the mode is specified in the format XxY-Depth@Rate, this parameter\n"
"will be ignored (default: 60)\n");
MODULE_PARM_DESC(forcecrt1,
"\nNormally, the driver autodetects whether or not CRT1 (external VGA) is \n"
"connected. With this option, the detection can be overridden (1=CRT1 ON,\n"
"0=CRT1 OFF) (default: [autodetected])\n");
MODULE_PARM_DESC(forcecrt2type,
"\nIf this option is omitted, the driver autodetects CRT2 output devices, such as\n"
"LCD, TV or secondary VGA. With this option, this autodetection can be\n"
"overridden. Possible parameters are LCD, TV, VGA or NONE. NONE disables CRT2.\n"
"On systems with a SiS video bridge, parameters SVIDEO, COMPOSITE or SCART can\n"
"be used instead of TV to override the TV detection. Furthermore, on systems\n"
"with a SiS video bridge, SVIDEO+COMPOSITE, HIVISION, YPBPR480I, YPBPR480P,\n"
"YPBPR720P and YPBPR1080I are understood. However, whether or not these work\n"
"depends on the very hardware in use. (default: [autodetected])\n");
MODULE_PARM_DESC(scalelcd,
"\nSetting this to 1 will force the driver to scale the LCD image to the panel's\n"
"native resolution. Setting it to 0 will disable scaling; LVDS panels will\n"
"show black bars around the image, TMDS panels will probably do the scaling\n"
"themselves. Default: 1 on LVDS panels, 0 on TMDS panels\n");
MODULE_PARM_DESC(pdc,
"\nThis is for manually selecting the LCD panel delay compensation. The driver\n"
"should detect this correctly in most cases; however, sometimes this is not\n"
"possible. If you see 'small waves' on the LCD, try setting this to 4, 32 or 24\n"
"on a 300 series chipset; 6 on other chipsets. If the problem persists, try\n"
"other values (on 300 series: between 4 and 60 in steps of 4; otherwise: any\n"
"value from 0 to 31). (default: autodetected, if LCD is active during start)\n");
#ifdef CONFIG_FB_SIS_315
MODULE_PARM_DESC(pdc1,
"\nThis is same as pdc, but for LCD-via CRT1. Hence, this is for the 315/330/340\n"
"series only. (default: autodetected if LCD is in LCD-via-CRT1 mode during\n"
"startup) - Note: currently, this has no effect because LCD-via-CRT1 is not\n"
"implemented yet.\n");
#endif
MODULE_PARM_DESC(specialtiming,
"\nPlease refer to documentation for more information on this option.\n");
MODULE_PARM_DESC(lvdshl,
"\nPlease refer to documentation for more information on this option.\n");
MODULE_PARM_DESC(tvstandard,
"\nThis allows overriding the BIOS default for the TV standard. Valid choices are\n"
"pal, ntsc, palm and paln. (default: [auto; pal or ntsc only])\n");
MODULE_PARM_DESC(tvxposoffset,
"\nRelocate TV output horizontally. Possible parameters: -32 through 32.\n"
"Default: 0\n");
MODULE_PARM_DESC(tvyposoffset,
"\nRelocate TV output vertically. Possible parameters: -32 through 32.\n"
"Default: 0\n");
MODULE_PARM_DESC(nocrt2rate,
"\nSetting this to 1 will force the driver to use the default refresh rate for\n"
"CRT2 if CRT2 type is VGA. (default: 0, use same rate as CRT1)\n");
#if !defined(__i386__) && !defined(__x86_64__)
#ifdef CONFIG_FB_SIS_300
MODULE_PARM_DESC(resetcard,
"\nSet this to 1 in order to reset (POST) the card on non-x86 machines where\n"
"the BIOS did not POST the card (only supported for SiS 300/305 and XGI cards\n"
"currently). Default: 0\n");
MODULE_PARM_DESC(videoram,
"\nSet this to the amount of video RAM (in kilobyte) the card has. Required on\n"
"some non-x86 architectures where the memory auto detection fails. Only\n"
"relevant if resetcard is set, too. SiS300/305 only. Default: [auto-detect]\n");
#endif
#endif
#endif /* /MODULE */
/* _GPL only for new symbols. */
EXPORT_SYMBOL(sis_malloc);
EXPORT_SYMBOL(sis_free);
EXPORT_SYMBOL_GPL(sis_malloc_new);
EXPORT_SYMBOL_GPL(sis_free_new);
| linux-master | drivers/video/fbdev/sis/sis_main.c |
/* $XFree86$ */
/* $XdotOrg$ */
/*
* Mode initializing code (CRT2 section)
* for SiS 300/305/540/630/730,
* SiS 315/550/[M]650/651/[M]661[FGM]X/[M]74x[GX]/330/[M]76x[GX],
* XGI V3XT/V5/V8, Z7
* (Universal module for Linux kernel framebuffer and X.org/XFree86 4.x)
*
* Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
*
* If distributed as part of the Linux kernel, the following license terms
* apply:
*
* * This program is free software; you can redistribute it and/or modify
* * it under the terms of the GNU General Public License as published by
* * the Free Software Foundation; either version 2 of the named License,
* * or any later version.
* *
* * This program is distributed in the hope that it will be useful,
* * but WITHOUT ANY WARRANTY; without even the implied warranty of
* * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* * GNU General Public License for more details.
* *
* * You should have received a copy of the GNU General Public License
* * along with this program; if not, write to the Free Software
* * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
*
* Otherwise, the following license terms apply:
*
* * Redistribution and use in source and binary forms, with or without
* * modification, are permitted provided that the following conditions
* * are met:
* * 1) Redistributions of source code must retain the above copyright
* * notice, this list of conditions and the following disclaimer.
* * 2) Redistributions in binary form must reproduce the above copyright
* * notice, this list of conditions and the following disclaimer in the
* * documentation and/or other materials provided with the distribution.
* * 3) The name of the author may not be used to endorse or promote products
* * derived from this software without specific prior written permission.
* *
* * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Thomas Winischhofer <[email protected]>
*
* Formerly based on non-functional code-fragements for 300 series by SiS, Inc.
* Used by permission.
*
*/
#if 1
#define SET_EMI /* 302LV/ELV: Set EMI values */
#endif
#if 1
#define SET_PWD /* 301/302LV: Set PWD */
#endif
#define COMPAL_HACK /* Needed for Compal 1400x1050 (EMI) */
#define COMPAQ_HACK /* Needed for Inventec/Compaq 1280x1024 (EMI) */
#define ASUS_HACK /* Needed for Asus A2H 1024x768 (EMI) */
#include "init301.h"
#ifdef CONFIG_FB_SIS_300
#include "oem300.h"
#endif
#ifdef CONFIG_FB_SIS_315
#include "oem310.h"
#endif
#define SiS_I2CDELAY 1000
#define SiS_I2CDELAYSHORT 150
static const unsigned char SiS_YPbPrTable[3][64] = {
{
0x17,0x1d,0x03,0x09,0x05,0x06,0x0c,0x0c,
0x94,0x49,0x01,0x0a,0x06,0x0d,0x04,0x0a,
0x06,0x14,0x0d,0x04,0x0a,0x00,0x85,0x1b,
0x0c,0x50,0x00,0x97,0x00,0xda,0x4a,0x17,
0x7d,0x05,0x4b,0x00,0x00,0xe2,0x00,0x02,
0x03,0x0a,0x65,0x9d /*0x8d*/,0x08,0x92,0x8f,0x40,
0x60,0x80,0x14,0x90,0x8c,0x60,0x14,0x53 /*0x50*/,
0x00,0x40,0x44,0x00,0xdb,0x02,0x3b,0x00
},
{
0x33,0x06,0x06,0x09,0x0b,0x0c,0x0c,0x0c,
0x98,0x0a,0x01,0x0d,0x06,0x0d,0x04,0x0a,
0x06,0x14,0x0d,0x04,0x0a,0x00,0x85,0x3f,
0x0c,0x50,0xb2,0x9f,0x16,0x59,0x4f,0x13,
0xad,0x11,0xad,0x1d,0x40,0x8a,0x3d,0xb8,
0x51,0x5e,0x60,0x49,0x7d,0x92,0x0f,0x40,
0x60,0x80,0x14,0x90,0x8c,0x60,0x14,0x4e,
0x43,0x41,0x11,0x00,0xfc,0xff,0x32,0x00
},
{
#if 0 /* OK, but sticks to left edge */
0x13,0x1d,0xe8,0x09,0x09,0xed,0x0c,0x0c,
0x98,0x0a,0x01,0x0c,0x06,0x0d,0x04,0x0a,
0x06,0x14,0x0d,0x04,0x0a,0x00,0x85,0x3f,
0xed,0x50,0x70,0x9f,0x16,0x59,0x21 /*0x2b*/,0x13,
0x27,0x0b,0x27,0xfc,0x30,0x27,0x1c,0xb0,
0x4b,0x4b,0x65 /*0x6f*/,0x2f,0x63,0x92,0x0f,0x40,
0x60,0x80,0x14,0x90,0x8c,0x60,0x14,0x27,
0x00,0x40,0x11,0x00,0xfc,0xff,0x32,0x00
#endif
#if 1 /* Perfect */
0x23,0x2d,0xe8,0x09,0x09,0xed,0x0c,0x0c,
0x98,0x0a,0x01,0x0c,0x06,0x0d,0x04,0x0a,
0x06,0x14,0x0d,0x04,0x0a,0x00,0x85,0x3f,
0xed,0x50,0x70,0x9f,0x16,0x59,0x60,0x13,
0x27,0x0b,0x27,0xfc,0x30,0x27,0x1c,0xb0,
0x4b,0x4b,0x6f,0x2f,0x63,0x92,0x0f,0x40,
0x60,0x80,0x14,0x90,0x8c,0x60,0x14,0x73,
0x00,0x40,0x11,0x00,0xfc,0xff,0x32,0x00
#endif
}
};
static const unsigned char SiS_TVPhase[] =
{
0x21,0xED,0xBA,0x08, /* 0x00 SiS_NTSCPhase */
0x2A,0x05,0xE3,0x00, /* 0x01 SiS_PALPhase */
0x21,0xE4,0x2E,0x9B, /* 0x02 SiS_PALMPhase */
0x21,0xF4,0x3E,0xBA, /* 0x03 SiS_PALNPhase */
0x1E,0x8B,0xA2,0xA7,
0x1E,0x83,0x0A,0xE0, /* 0x05 SiS_SpecialPhaseM */
0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,
0x21,0xF0,0x7B,0xD6, /* 0x08 SiS_NTSCPhase2 */
0x2A,0x09,0x86,0xE9, /* 0x09 SiS_PALPhase2 */
0x21,0xE6,0xEF,0xA4, /* 0x0a SiS_PALMPhase2 */
0x21,0xF6,0x94,0x46, /* 0x0b SiS_PALNPhase2 */
0x1E,0x8B,0xA2,0xA7,
0x1E,0x83,0x0A,0xE0, /* 0x0d SiS_SpecialPhaseM */
0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,
0x1e,0x8c,0x5c,0x7a, /* 0x10 SiS_SpecialPhase */
0x25,0xd4,0xfd,0x5e /* 0x11 SiS_SpecialPhaseJ */
};
static const unsigned char SiS_HiTVGroup3_1[] = {
0x00, 0x14, 0x15, 0x25, 0x55, 0x15, 0x0b, 0x13,
0xb1, 0x41, 0x62, 0x62, 0xff, 0xf4, 0x45, 0xa6,
0x25, 0x2f, 0x67, 0xf6, 0xbf, 0xff, 0x8e, 0x20,
0xac, 0xda, 0x60, 0xfe, 0x6a, 0x9a, 0x06, 0x10,
0xd1, 0x04, 0x18, 0x0a, 0xff, 0x80, 0x00, 0x80,
0x3b, 0x77, 0x00, 0xef, 0xe0, 0x10, 0xb0, 0xe0,
0x10, 0x4f, 0x0f, 0x0f, 0x05, 0x0f, 0x08, 0x6e,
0x1a, 0x1f, 0x25, 0x2a, 0x4c, 0xaa, 0x01
};
static const unsigned char SiS_HiTVGroup3_2[] = {
0x00, 0x14, 0x15, 0x25, 0x55, 0x15, 0x0b, 0x7a,
0x54, 0x41, 0xe7, 0xe7, 0xff, 0xf4, 0x45, 0xa6,
0x25, 0x2f, 0x67, 0xf6, 0xbf, 0xff, 0x8e, 0x20,
0xac, 0x6a, 0x60, 0x2b, 0x52, 0xcd, 0x61, 0x10,
0x51, 0x04, 0x18, 0x0a, 0x1f, 0x80, 0x00, 0x80,
0xff, 0xa4, 0x04, 0x2b, 0x94, 0x21, 0x72, 0x94,
0x26, 0x05, 0x01, 0x0f, 0xed, 0x0f, 0x0a, 0x64,
0x18, 0x1d, 0x23, 0x28, 0x4c, 0xaa, 0x01
};
/* 301C / 302ELV extended Part2 TV registers (4 tap scaler) */
static const unsigned char SiS_Part2CLVX_1[] = {
0x00,0x00,
0x00,0x20,0x00,0x00,0x7F,0x20,0x02,0x7F,0x7D,0x20,0x04,0x7F,0x7D,0x1F,0x06,0x7E,
0x7C,0x1D,0x09,0x7E,0x7C,0x1B,0x0B,0x7E,0x7C,0x19,0x0E,0x7D,0x7C,0x17,0x11,0x7C,
0x7C,0x14,0x14,0x7C,0x7C,0x11,0x17,0x7C,0x7D,0x0E,0x19,0x7C,0x7E,0x0B,0x1B,0x7C,
0x7E,0x09,0x1D,0x7C,0x7F,0x06,0x1F,0x7C,0x7F,0x04,0x20,0x7D,0x00,0x02,0x20,0x7E
};
static const unsigned char SiS_Part2CLVX_2[] = {
0x00,0x00,
0x00,0x20,0x00,0x00,0x7F,0x20,0x02,0x7F,0x7D,0x20,0x04,0x7F,0x7D,0x1F,0x06,0x7E,
0x7C,0x1D,0x09,0x7E,0x7C,0x1B,0x0B,0x7E,0x7C,0x19,0x0E,0x7D,0x7C,0x17,0x11,0x7C,
0x7C,0x14,0x14,0x7C,0x7C,0x11,0x17,0x7C,0x7D,0x0E,0x19,0x7C,0x7E,0x0B,0x1B,0x7C,
0x7E,0x09,0x1D,0x7C,0x7F,0x06,0x1F,0x7C,0x7F,0x04,0x20,0x7D,0x00,0x02,0x20,0x7E
};
static const unsigned char SiS_Part2CLVX_3[] = { /* NTSC, 525i, 525p */
0xE0,0x01,
0x04,0x1A,0x04,0x7E,0x03,0x1A,0x06,0x7D,0x01,0x1A,0x08,0x7D,0x00,0x19,0x0A,0x7D,
0x7F,0x19,0x0C,0x7C,0x7E,0x18,0x0E,0x7C,0x7E,0x17,0x10,0x7B,0x7D,0x15,0x12,0x7C,
0x7D,0x13,0x13,0x7D,0x7C,0x12,0x15,0x7D,0x7C,0x10,0x17,0x7D,0x7C,0x0E,0x18,0x7E,
0x7D,0x0C,0x19,0x7E,0x7D,0x0A,0x19,0x00,0x7D,0x08,0x1A,0x01,0x7E,0x06,0x1A,0x02,
0x58,0x02,
0x07,0x14,0x07,0x7E,0x06,0x14,0x09,0x7D,0x05,0x14,0x0A,0x7D,0x04,0x13,0x0B,0x7E,
0x03,0x13,0x0C,0x7E,0x02,0x12,0x0D,0x7F,0x01,0x12,0x0E,0x7F,0x01,0x11,0x0F,0x7F,
0x00,0x10,0x10,0x00,0x7F,0x0F,0x11,0x01,0x7F,0x0E,0x12,0x01,0x7E,0x0D,0x12,0x03,
0x7E,0x0C,0x13,0x03,0x7E,0x0B,0x13,0x04,0x7E,0x0A,0x14,0x04,0x7D,0x09,0x14,0x06,
0x00,0x03,
0x09,0x0F,0x09,0x7F,0x08,0x0F,0x09,0x00,0x07,0x0F,0x0A,0x00,0x06,0x0F,0x0A,0x01,
0x06,0x0E,0x0B,0x01,0x05,0x0E,0x0B,0x02,0x04,0x0E,0x0C,0x02,0x04,0x0D,0x0C,0x03,
0x03,0x0D,0x0D,0x03,0x02,0x0C,0x0D,0x05,0x02,0x0C,0x0E,0x04,0x01,0x0B,0x0E,0x06,
0x01,0x0B,0x0E,0x06,0x00,0x0A,0x0F,0x07,0x00,0x0A,0x0F,0x07,0x00,0x09,0x0F,0x08,
0xFF,0xFF
};
static const unsigned char SiS_Part2CLVX_4[] = { /* PAL */
0x58,0x02,
0x05,0x19,0x05,0x7D,0x03,0x19,0x06,0x7E,0x02,0x19,0x08,0x7D,0x01,0x18,0x0A,0x7D,
0x00,0x18,0x0C,0x7C,0x7F,0x17,0x0E,0x7C,0x7E,0x16,0x0F,0x7D,0x7E,0x14,0x11,0x7D,
0x7D,0x13,0x13,0x7D,0x7D,0x11,0x14,0x7E,0x7D,0x0F,0x16,0x7E,0x7D,0x0E,0x17,0x7E,
0x7D,0x0C,0x18,0x7F,0x7D,0x0A,0x18,0x01,0x7D,0x08,0x19,0x02,0x7D,0x06,0x19,0x04,
0x00,0x03,
0x08,0x12,0x08,0x7E,0x07,0x12,0x09,0x7E,0x06,0x12,0x0A,0x7E,0x05,0x11,0x0B,0x7F,
0x04,0x11,0x0C,0x7F,0x03,0x11,0x0C,0x00,0x03,0x10,0x0D,0x00,0x02,0x0F,0x0E,0x01,
0x01,0x0F,0x0F,0x01,0x01,0x0E,0x0F,0x02,0x00,0x0D,0x10,0x03,0x7F,0x0C,0x11,0x04,
0x7F,0x0C,0x11,0x04,0x7F,0x0B,0x11,0x05,0x7E,0x0A,0x12,0x06,0x7E,0x09,0x12,0x07,
0x40,0x02,
0x04,0x1A,0x04,0x7E,0x02,0x1B,0x05,0x7E,0x01,0x1A,0x07,0x7E,0x00,0x1A,0x09,0x7D,
0x7F,0x19,0x0B,0x7D,0x7E,0x18,0x0D,0x7D,0x7D,0x17,0x10,0x7C,0x7D,0x15,0x12,0x7C,
0x7C,0x14,0x14,0x7C,0x7C,0x12,0x15,0x7D,0x7C,0x10,0x17,0x7D,0x7C,0x0D,0x18,0x7F,
0x7D,0x0B,0x19,0x7F,0x7D,0x09,0x1A,0x00,0x7D,0x07,0x1A,0x02,0x7E,0x05,0x1B,0x02,
0xFF,0xFF
};
static const unsigned char SiS_Part2CLVX_5[] = { /* 750p */
0x00,0x03,
0x05,0x19,0x05,0x7D,0x03,0x19,0x06,0x7E,0x02,0x19,0x08,0x7D,0x01,0x18,0x0A,0x7D,
0x00,0x18,0x0C,0x7C,0x7F,0x17,0x0E,0x7C,0x7E,0x16,0x0F,0x7D,0x7E,0x14,0x11,0x7D,
0x7D,0x13,0x13,0x7D,0x7D,0x11,0x14,0x7E,0x7D,0x0F,0x16,0x7E,0x7D,0x0E,0x17,0x7E,
0x7D,0x0C,0x18,0x7F,0x7D,0x0A,0x18,0x01,0x7D,0x08,0x19,0x02,0x7D,0x06,0x19,0x04,
0xFF,0xFF
};
static const unsigned char SiS_Part2CLVX_6[] = { /* 1080i */
0x00,0x04,
0x04,0x1A,0x04,0x7E,0x02,0x1B,0x05,0x7E,0x01,0x1A,0x07,0x7E,0x00,0x1A,0x09,0x7D,
0x7F,0x19,0x0B,0x7D,0x7E,0x18,0x0D,0x7D,0x7D,0x17,0x10,0x7C,0x7D,0x15,0x12,0x7C,
0x7C,0x14,0x14,0x7C,0x7C,0x12,0x15,0x7D,0x7C,0x10,0x17,0x7D,0x7C,0x0D,0x18,0x7F,
0x7D,0x0B,0x19,0x7F,0x7D,0x09,0x1A,0x00,0x7D,0x07,0x1A,0x02,0x7E,0x05,0x1B,0x02,
0xFF,0xFF,
};
#ifdef CONFIG_FB_SIS_315
/* 661 et al LCD data structure (2.03.00) */
static const unsigned char SiS_LCDStruct661[] = {
/* 1024x768 */
/* type|CR37| HDE | VDE | HT | VT | hss | hse */
0x02,0xC0,0x00,0x04,0x00,0x03,0x40,0x05,0x26,0x03,0x10,0x00,0x88,
0x00,0x02,0x00,0x06,0x00,0x41,0x5A,0x64,0x00,0x00,0x00,0x00,0x04,
/* | vss | vse |clck| clock |CRT2DataP|CRT2DataP|idx */
/* VESA non-VESA noscale */
/* 1280x1024 */
0x03,0xC0,0x00,0x05,0x00,0x04,0x98,0x06,0x2A,0x04,0x30,0x00,0x70,
0x00,0x01,0x00,0x03,0x00,0x6C,0xF8,0x2F,0x00,0x00,0x00,0x00,0x08,
/* 1400x1050 */
0x09,0x20,0x78,0x05,0x1A,0x04,0x98,0x06,0x2A,0x04,0x18,0x00,0x38,
0x00,0x01,0x00,0x03,0x00,0x6C,0xF8,0x2F,0x00,0x00,0x00,0x00,0x09,
/* 1600x1200 */
0x0B,0xE0,0x40,0x06,0xB0,0x04,0x70,0x08,0xE2,0x04,0x40,0x00,0xC0,
0x00,0x01,0x00,0x03,0x00,0xA2,0x70,0x24,0x00,0x00,0x00,0x00,0x0A,
/* 1280x768 (_2) */
0x0A,0xE0,0x00,0x05,0x00,0x03,0x7C,0x06,0x26,0x03,0x30,0x00,0x70,
0x00,0x03,0x00,0x06,0x00,0x4D,0xC8,0x48,0x00,0x00,0x00,0x00,0x06,
/* 1280x720 */
0x0E,0xE0,0x00,0x05,0xD0,0x02,0x80,0x05,0x26,0x03,0x10,0x00,0x20,
0x00,0x01,0x00,0x06,0x00,0x45,0x9C,0x62,0x00,0x00,0x00,0x00,0x05,
/* 1280x800 (_2) */
0x0C,0xE0,0x00,0x05,0x20,0x03,0x10,0x06,0x2C,0x03,0x30,0x00,0x70,
0x00,0x04,0x00,0x03,0x00,0x49,0xCE,0x1E,0x00,0x00,0x00,0x00,0x09,
/* 1680x1050 */
0x0D,0xE0,0x90,0x06,0x1A,0x04,0x6C,0x07,0x2A,0x04,0x1A,0x00,0x4C,
0x00,0x03,0x00,0x06,0x00,0x79,0xBE,0x44,0x00,0x00,0x00,0x00,0x06,
/* 1280x800_3 */
0x0C,0xE0,0x00,0x05,0x20,0x03,0xAA,0x05,0x2E,0x03,0x30,0x00,0x50,
0x00,0x04,0x00,0x03,0x00,0x47,0xA9,0x10,0x00,0x00,0x00,0x00,0x07,
/* 800x600 */
0x01,0xC0,0x20,0x03,0x58,0x02,0x20,0x04,0x74,0x02,0x2A,0x00,0x80,
0x00,0x06,0x00,0x04,0x00,0x28,0x63,0x4B,0x00,0x00,0x00,0x00,0x00,
/* 1280x854 */
0x08,0xE0,0x00,0x05,0x56,0x03,0x80,0x06,0x5d,0x03,0x10,0x00,0x70,
0x00,0x01,0x00,0x03,0x00,0x54,0x75,0x13,0x00,0x00,0x00,0x00,0x08
};
#endif
#ifdef CONFIG_FB_SIS_300
static unsigned char SiS300_TrumpionData[14][80] = {
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x0D,0x00,0x0D,0x10,0x7F,0x00,0x80,0x02,
0x20,0x03,0x0B,0x00,0x90,0x01,0xC1,0x01,0x60,0x0C,0x30,0x10,0x00,0x00,0x04,0x23,
0x00,0x00,0x03,0x28,0x03,0x10,0x05,0x08,0x40,0x10,0x00,0x10,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xBC,0x01,0xFF,0x03,0xFF,0x19,0x01,0x00,0x05,0x09,0x04,0x04,0x05,
0x04,0x0C,0x09,0x05,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x5A,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x0D,0x00,0x0D,0x10,0x27,0x00,0x80,0x02,
0x20,0x03,0x07,0x00,0x5E,0x01,0x0D,0x02,0x60,0x0C,0x30,0x11,0x00,0x00,0x04,0x23,
0x00,0x00,0x03,0x80,0x03,0x28,0x06,0x08,0x40,0x11,0x00,0x11,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0x90,0x01,0xFF,0x0F,0xF4,0x19,0x01,0x00,0x05,0x01,0x00,0x04,0x05,
0x04,0x0C,0x02,0x01,0x02,0xB0,0x00,0x00,0x02,0xBA,0xEC,0x57,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x0D,0x00,0x0D,0x10,0x8A,0x00,0xD8,0x02,
0x84,0x03,0x16,0x00,0x90,0x01,0xC1,0x01,0x60,0x0C,0x30,0x1C,0x00,0x20,0x04,0x23,
0x00,0x01,0x03,0x53,0x03,0x28,0x06,0x08,0x40,0x1C,0x00,0x16,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xD9,0x01,0xFF,0x0F,0xF4,0x18,0x07,0x05,0x05,0x13,0x04,0x04,0x05,
0x01,0x0B,0x13,0x0A,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x59,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x0D,0x00,0x0D,0x10,0x72,0x00,0xD8,0x02,
0x84,0x03,0x16,0x00,0x90,0x01,0xC1,0x01,0x60,0x0C,0x30,0x1C,0x00,0x20,0x04,0x23,
0x00,0x01,0x03,0x53,0x03,0x28,0x06,0x08,0x40,0x1C,0x00,0x16,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xDA,0x01,0xFF,0x0F,0xF4,0x18,0x07,0x05,0x05,0x13,0x04,0x04,0x05,
0x01,0x0B,0x13,0x0A,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x55,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x02,0x00,0x04,0x01,0x00,0x03,0x0D,0x00,0x0D,0x10,0x7F,0x00,0x80,0x02,
0x20,0x03,0x16,0x00,0xE0,0x01,0x0D,0x02,0x60,0x0C,0x30,0x98,0x00,0x00,0x04,0x23,
0x00,0x01,0x03,0x45,0x03,0x48,0x06,0x08,0x40,0x98,0x00,0x98,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xF4,0x01,0xFF,0x0F,0xF4,0x18,0x01,0x00,0x05,0x01,0x00,0x05,0x05,
0x04,0x0C,0x08,0x05,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x5B,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x02,0x01,0x04,0x01,0x00,0x03,0x0D,0x00,0x0D,0x10,0xBF,0x00,0x20,0x03,
0x20,0x04,0x0D,0x00,0x58,0x02,0x71,0x02,0x80,0x0C,0x30,0x9A,0x00,0xFA,0x03,0x1D,
0x00,0x01,0x03,0x22,0x03,0x28,0x06,0x08,0x40,0x98,0x00,0x98,0x04,0x1D,0x00,0x1D,
0x03,0x11,0x60,0x39,0x03,0x40,0x05,0xF4,0x18,0x07,0x02,0x06,0x04,0x01,0x06,0x0B,
0x02,0x0A,0x20,0x19,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x5B,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x0D,0x00,0x0D,0x10,0xEF,0x00,0x00,0x04,
0x40,0x05,0x13,0x00,0x00,0x03,0x26,0x03,0x88,0x0C,0x30,0x90,0x00,0x00,0x04,0x23,
0x00,0x01,0x03,0x24,0x03,0x28,0x06,0x08,0x40,0x90,0x00,0x90,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0x40,0x05,0xFF,0x0F,0xF4,0x18,0x01,0x00,0x08,0x01,0x00,0x08,0x01,
0x00,0x08,0x01,0x01,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x5B,0x01,0xBE,0x01,0x00 },
/* variant 2 */
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x11,0x00,0x0D,0x10,0x7F,0x00,0x80,0x02,
0x20,0x03,0x15,0x00,0x90,0x01,0xC1,0x01,0x60,0x0C,0x30,0x18,0x00,0x00,0x04,0x23,
0x00,0x01,0x03,0x44,0x03,0x28,0x06,0x08,0x40,0x18,0x00,0x18,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xA6,0x01,0xFF,0x03,0xFF,0x19,0x01,0x00,0x05,0x13,0x04,0x04,0x05,
0x04,0x0C,0x13,0x0A,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x55,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x11,0x00,0x0D,0x10,0x7F,0x00,0x80,0x02,
0x20,0x03,0x15,0x00,0x90,0x01,0xC1,0x01,0x60,0x0C,0x30,0x18,0x00,0x00,0x04,0x23,
0x00,0x01,0x03,0x44,0x03,0x28,0x06,0x08,0x40,0x18,0x00,0x18,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xA6,0x01,0xFF,0x03,0xFF,0x19,0x01,0x00,0x05,0x13,0x04,0x04,0x05,
0x04,0x0C,0x13,0x0A,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x55,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x11,0x00,0x0D,0x10,0x8A,0x00,0xD8,0x02,
0x84,0x03,0x16,0x00,0x90,0x01,0xC1,0x01,0x60,0x0C,0x30,0x1C,0x00,0x20,0x04,0x23,
0x00,0x01,0x03,0x53,0x03,0x28,0x06,0x08,0x40,0x1C,0x00,0x16,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xDA,0x01,0xFF,0x0F,0xF4,0x18,0x07,0x05,0x05,0x13,0x04,0x04,0x05,
0x01,0x0B,0x13,0x0A,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x55,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x11,0x00,0x0D,0x10,0x72,0x00,0xD8,0x02,
0x84,0x03,0x16,0x00,0x90,0x01,0xC1,0x01,0x60,0x0C,0x30,0x1C,0x00,0x20,0x04,0x23,
0x00,0x01,0x03,0x53,0x03,0x28,0x06,0x08,0x40,0x1C,0x00,0x16,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xDA,0x01,0xFF,0x0F,0xF4,0x18,0x07,0x05,0x05,0x13,0x04,0x04,0x05,
0x01,0x0B,0x13,0x0A,0x02,0xB0,0x00,0x00,0x02,0xBA,0xF0,0x55,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x02,0x00,0x04,0x01,0x00,0x03,0x11,0x00,0x0D,0x10,0x7F,0x00,0x80,0x02,
0x20,0x03,0x16,0x00,0xE0,0x01,0x0D,0x02,0x60,0x0C,0x30,0x98,0x00,0x00,0x04,0x23,
0x00,0x01,0x03,0x45,0x03,0x48,0x06,0x08,0x40,0x98,0x00,0x98,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0xF4,0x01,0xFF,0x0F,0xF4,0x18,0x01,0x00,0x05,0x01,0x00,0x05,0x05,
0x04,0x0C,0x08,0x05,0x02,0xB0,0x00,0x00,0x02,0xBA,0xEA,0x58,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x02,0x01,0x04,0x01,0x00,0x03,0x11,0x00,0x0D,0x10,0xBF,0x00,0x20,0x03,
0x20,0x04,0x0D,0x00,0x58,0x02,0x71,0x02,0x80,0x0C,0x30,0x9A,0x00,0xFA,0x03,0x1D,
0x00,0x01,0x03,0x22,0x03,0x28,0x06,0x08,0x40,0x98,0x00,0x98,0x04,0x1D,0x00,0x1D,
0x03,0x11,0x60,0x39,0x03,0x40,0x05,0xF4,0x18,0x07,0x02,0x06,0x04,0x01,0x06,0x0B,
0x02,0x0A,0x20,0x19,0x02,0xB0,0x00,0x00,0x02,0xBA,0xEA,0x58,0x01,0xBE,0x01,0x00 },
{ 0x02,0x0A,0x0A,0x01,0x04,0x01,0x00,0x03,0x11,0x00,0x0D,0x10,0xEF,0x00,0x00,0x04,
0x40,0x05,0x13,0x00,0x00,0x03,0x26,0x03,0x88,0x0C,0x30,0x90,0x00,0x00,0x04,0x23,
0x00,0x01,0x03,0x24,0x03,0x28,0x06,0x08,0x40,0x90,0x00,0x90,0x04,0x23,0x00,0x23,
0x03,0x11,0x60,0x40,0x05,0xFF,0x0F,0xF4,0x18,0x01,0x00,0x08,0x01,0x00,0x08,0x01,
0x00,0x08,0x01,0x01,0x02,0xB0,0x00,0x00,0x02,0xBA,0xEA,0x58,0x01,0xBE,0x01,0x00 }
};
#endif
#ifdef CONFIG_FB_SIS_315
static void SiS_Chrontel701xOn(struct SiS_Private *SiS_Pr);
static void SiS_Chrontel701xOff(struct SiS_Private *SiS_Pr);
static void SiS_ChrontelInitTVVSync(struct SiS_Private *SiS_Pr);
static void SiS_ChrontelDoSomething1(struct SiS_Private *SiS_Pr);
#endif /* 315 */
#ifdef CONFIG_FB_SIS_300
static bool SiS_SetTrumpionBlock(struct SiS_Private *SiS_Pr, unsigned char *dataptr);
#endif
static unsigned short SiS_InitDDCRegs(struct SiS_Private *SiS_Pr, unsigned int VBFlags,
int VGAEngine, unsigned short adaptnum, unsigned short DDCdatatype,
bool checkcr32, unsigned int VBFlags2);
static unsigned short SiS_ProbeDDC(struct SiS_Private *SiS_Pr);
static unsigned short SiS_ReadDDC(struct SiS_Private *SiS_Pr, unsigned short DDCdatatype,
unsigned char *buffer);
static void SiS_SetSwitchDDC2(struct SiS_Private *SiS_Pr);
static unsigned short SiS_SetStart(struct SiS_Private *SiS_Pr);
static unsigned short SiS_SetStop(struct SiS_Private *SiS_Pr);
static unsigned short SiS_SetSCLKLow(struct SiS_Private *SiS_Pr);
static unsigned short SiS_SetSCLKHigh(struct SiS_Private *SiS_Pr);
static unsigned short SiS_ReadDDC2Data(struct SiS_Private *SiS_Pr);
static unsigned short SiS_WriteDDC2Data(struct SiS_Private *SiS_Pr, unsigned short tempax);
static unsigned short SiS_CheckACK(struct SiS_Private *SiS_Pr);
static unsigned short SiS_WriteDABDDC(struct SiS_Private *SiS_Pr);
static unsigned short SiS_PrepareReadDDC(struct SiS_Private *SiS_Pr);
static unsigned short SiS_PrepareDDC(struct SiS_Private *SiS_Pr);
static void SiS_SendACK(struct SiS_Private *SiS_Pr, unsigned short yesno);
static unsigned short SiS_DoProbeDDC(struct SiS_Private *SiS_Pr);
#ifdef CONFIG_FB_SIS_300
static void SiS_OEM300Setting(struct SiS_Private *SiS_Pr,
unsigned short ModeNo, unsigned short ModeIdIndex, unsigned short RefTabindex);
static void SetOEMLCDData2(struct SiS_Private *SiS_Pr,
unsigned short ModeNo, unsigned short ModeIdIndex,unsigned short RefTableIndex);
#endif
#ifdef CONFIG_FB_SIS_315
static void SiS_OEM310Setting(struct SiS_Private *SiS_Pr,
unsigned short ModeNo,unsigned short ModeIdIndex, unsigned short RRTI);
static void SiS_OEM661Setting(struct SiS_Private *SiS_Pr,
unsigned short ModeNo,unsigned short ModeIdIndex, unsigned short RRTI);
static void SiS_FinalizeLCD(struct SiS_Private *, unsigned short, unsigned short);
#endif
static unsigned short SiS_GetBIOSLCDResInfo(struct SiS_Private *SiS_Pr);
static void SiS_SetCH70xx(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val);
/*********************************************/
/* HELPER: Lock/Unlock CRT2 */
/*********************************************/
void
SiS_UnLockCRT2(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType == XGI_20)
return;
else if(SiS_Pr->ChipType >= SIS_315H)
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2f,0x01);
else
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x24,0x01);
}
static
void
SiS_LockCRT2(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType == XGI_20)
return;
else if(SiS_Pr->ChipType >= SIS_315H)
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2F,0xFE);
else
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x24,0xFE);
}
/*********************************************/
/* HELPER: Write SR11 */
/*********************************************/
static void
SiS_SetRegSR11ANDOR(struct SiS_Private *SiS_Pr, unsigned short DataAND, unsigned short DataOR)
{
if(SiS_Pr->ChipType >= SIS_661) {
DataAND &= 0x0f;
DataOR &= 0x0f;
}
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x11,DataAND,DataOR);
}
/*********************************************/
/* HELPER: Get Pointer to LCD structure */
/*********************************************/
#ifdef CONFIG_FB_SIS_315
static unsigned char *
GetLCDStructPtr661(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned char *myptr = NULL;
unsigned short romindex = 0, reg = 0, idx = 0;
/* Use the BIOS tables only for LVDS panels; TMDS is unreliable
* due to the variaty of panels the BIOS doesn't know about.
* Exception: If the BIOS has better knowledge (such as in case
* of machines with a 301C and a panel that does not support DDC)
* use the BIOS data as well.
*/
if((SiS_Pr->SiS_ROMNew) &&
((SiS_Pr->SiS_VBType & VB_SISLVDS) || (!SiS_Pr->PanelSelfDetected))) {
if(SiS_Pr->ChipType < SIS_661) reg = 0x3c;
else reg = 0x7d;
idx = (SiS_GetReg(SiS_Pr->SiS_P3d4,reg) & 0x1f) * 26;
if(idx < (8*26)) {
myptr = (unsigned char *)&SiS_LCDStruct661[idx];
}
romindex = SISGETROMW(0x100);
if(romindex) {
romindex += idx;
myptr = &ROMAddr[romindex];
}
}
return myptr;
}
static unsigned short
GetLCDStructPtr661_2(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romptr = 0;
/* Use the BIOS tables only for LVDS panels; TMDS is unreliable
* due to the variaty of panels the BIOS doesn't know about.
* Exception: If the BIOS has better knowledge (such as in case
* of machines with a 301C and a panel that does not support DDC)
* use the BIOS data as well.
*/
if((SiS_Pr->SiS_ROMNew) &&
((SiS_Pr->SiS_VBType & VB_SISLVDS) || (!SiS_Pr->PanelSelfDetected))) {
romptr = SISGETROMW(0x102);
romptr += ((SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) >> 4) * SiS_Pr->SiS661LCD2TableSize);
}
return romptr;
}
#endif
/*********************************************/
/* Adjust Rate for CRT2 */
/*********************************************/
static bool
SiS_AdjustCRT2Rate(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RRTI, unsigned short *i)
{
unsigned short checkmask=0, modeid, infoflag;
modeid = SiS_Pr->SiS_RefIndex[RRTI + (*i)].ModeID;
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC) {
checkmask |= SupportRAMDAC2;
if(SiS_Pr->ChipType >= SIS_315H) {
checkmask |= SupportRAMDAC2_135;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
checkmask |= SupportRAMDAC2_162;
if(SiS_Pr->SiS_VBType & VB_SISRAMDAC202) {
checkmask |= SupportRAMDAC2_202;
}
}
}
} else if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
checkmask |= SupportLCD;
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (SiS_Pr->SiS_LCDInfo & LCDPass11)) {
if(modeid == 0x2e) checkmask |= Support64048060Hz;
}
}
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
checkmask |= SupportHiVision;
} else if(SiS_Pr->SiS_VBInfo & (SetCRT2ToYPbPr525750|SetCRT2ToAVIDEO|SetCRT2ToSVIDEO|SetCRT2ToSCART)) {
checkmask |= SupportTV;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
checkmask |= SupportTV1024;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) {
checkmask |= SupportYPbPr750p;
}
}
}
}
} else { /* LVDS */
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
checkmask |= SupportCHTV;
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
checkmask |= SupportLCD;
}
}
/* Look backwards in table for matching CRT2 mode */
for(; SiS_Pr->SiS_RefIndex[RRTI + (*i)].ModeID == modeid; (*i)--) {
infoflag = SiS_Pr->SiS_RefIndex[RRTI + (*i)].Ext_InfoFlag;
if(infoflag & checkmask) return true;
if((*i) == 0) break;
}
/* Look through the whole mode-section of the table from the beginning
* for a matching CRT2 mode if no mode was found yet.
*/
for((*i) = 0; ; (*i)++) {
if(SiS_Pr->SiS_RefIndex[RRTI + (*i)].ModeID != modeid) break;
infoflag = SiS_Pr->SiS_RefIndex[RRTI + (*i)].Ext_InfoFlag;
if(infoflag & checkmask) return true;
}
return false;
}
/*********************************************/
/* Get rate index */
/*********************************************/
unsigned short
SiS_GetRatePtr(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short RRTI,i,backup_i;
unsigned short modeflag,index,temp,backupindex;
static const unsigned short LCDRefreshIndex[] = {
0x00, 0x00, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01,
0x00, 0x00, 0x00, 0x00
};
/* Do NOT check for UseCustomMode here, will skrew up FIFO */
if(ModeNo == 0xfe) return 0;
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(modeflag & HalfDCLK) return 0;
}
}
if(ModeNo < 0x14) return 0xFFFF;
index = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x33) >> SiS_Pr->SiS_SelectCRT2Rate) & 0x0F;
backupindex = index;
if(index > 0) index--;
if(SiS_Pr->SiS_SetFlag & ProgrammingCRT2) {
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->SiS_VBType & VB_NoLCD) index = 0;
else if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) index = backupindex = 0;
}
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_VBType & VB_NoLCD)) {
temp = LCDRefreshIndex[SiS_GetBIOSLCDResInfo(SiS_Pr)];
if(index > temp) index = temp;
}
}
} else {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) index = 0;
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) index = 0;
}
}
}
RRTI = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].REFindex;
ModeNo = SiS_Pr->SiS_RefIndex[RRTI].ModeID;
if(SiS_Pr->ChipType >= SIS_315H) {
if(!(SiS_Pr->SiS_VBInfo & DriverMode)) {
if( (SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_VESAID == 0x105) ||
(SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_VESAID == 0x107) ) {
if(backupindex <= 1) RRTI++;
}
}
}
i = 0;
do {
if(SiS_Pr->SiS_RefIndex[RRTI + i].ModeID != ModeNo) break;
temp = SiS_Pr->SiS_RefIndex[RRTI + i].Ext_InfoFlag;
temp &= ModeTypeMask;
if(temp < SiS_Pr->SiS_ModeType) break;
i++;
index--;
} while(index != 0xFFFF);
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC)) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
temp = SiS_Pr->SiS_RefIndex[RRTI + i - 1].Ext_InfoFlag;
if(temp & InterlaceMode) i++;
}
}
i--;
if((SiS_Pr->SiS_SetFlag & ProgrammingCRT2) && (!(SiS_Pr->SiS_VBInfo & DisableCRT2Display))) {
backup_i = i;
if(!(SiS_AdjustCRT2Rate(SiS_Pr, ModeNo, ModeIdIndex, RRTI, &i))) {
i = backup_i;
}
}
return (RRTI + i);
}
/*********************************************/
/* STORE CRT2 INFO in CR34 */
/*********************************************/
static void
SiS_SaveCRT2Info(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
unsigned short temp1, temp2;
/* Store CRT1 ModeNo in CR34 */
SiS_SetReg(SiS_Pr->SiS_P3d4,0x34,ModeNo);
temp1 = (SiS_Pr->SiS_VBInfo & SetInSlaveMode) >> 8;
temp2 = ~(SetInSlaveMode >> 8);
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x31,temp2,temp1);
}
/*********************************************/
/* HELPER: GET SOME DATA FROM BIOS ROM */
/*********************************************/
#ifdef CONFIG_FB_SIS_300
static bool
SiS_CR36BIOSWord23b(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short temp,temp1;
if(SiS_Pr->SiS_UseROM) {
if((ROMAddr[0x233] == 0x12) && (ROMAddr[0x234] == 0x34)) {
temp = 1 << ((SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) >> 4) & 0x0f);
temp1 = SISGETROMW(0x23b);
if(temp1 & temp) return true;
}
}
return false;
}
static bool
SiS_CR36BIOSWord23d(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short temp,temp1;
if(SiS_Pr->SiS_UseROM) {
if((ROMAddr[0x233] == 0x12) && (ROMAddr[0x234] == 0x34)) {
temp = 1 << ((SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) >> 4) & 0x0f);
temp1 = SISGETROMW(0x23d);
if(temp1 & temp) return true;
}
}
return false;
}
#endif
/*********************************************/
/* HELPER: DELAY FUNCTIONS */
/*********************************************/
void
SiS_DDC2Delay(struct SiS_Private *SiS_Pr, unsigned int delaytime)
{
while (delaytime-- > 0)
SiS_GetReg(SiS_Pr->SiS_P3c4, 0x05);
}
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
static void
SiS_GenericDelay(struct SiS_Private *SiS_Pr, unsigned short delay)
{
SiS_DDC2Delay(SiS_Pr, delay * 36);
}
#endif
#ifdef CONFIG_FB_SIS_315
static void
SiS_LongDelay(struct SiS_Private *SiS_Pr, unsigned short delay)
{
while(delay--) {
SiS_GenericDelay(SiS_Pr, 6623);
}
}
#endif
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
static void
SiS_ShortDelay(struct SiS_Private *SiS_Pr, unsigned short delay)
{
while(delay--) {
SiS_GenericDelay(SiS_Pr, 66);
}
}
#endif
static void
SiS_PanelDelay(struct SiS_Private *SiS_Pr, unsigned short DelayTime)
{
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short PanelID, DelayIndex, Delay=0;
#endif
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
PanelID = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36);
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBType & VB_SIS301) PanelID &= 0xf7;
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x18) & 0x10)) PanelID = 0x12;
}
DelayIndex = PanelID >> 4;
if((DelayTime >= 2) && ((PanelID & 0x0f) == 1)) {
Delay = 3;
} else {
if(DelayTime >= 2) DelayTime -= 2;
if(!(DelayTime & 0x01)) {
Delay = SiS_Pr->SiS_PanelDelayTbl[DelayIndex].timer[0];
} else {
Delay = SiS_Pr->SiS_PanelDelayTbl[DelayIndex].timer[1];
}
if(SiS_Pr->SiS_UseROM) {
if(ROMAddr[0x220] & 0x40) {
if(!(DelayTime & 0x01)) Delay = (unsigned short)ROMAddr[0x225];
else Delay = (unsigned short)ROMAddr[0x226];
}
}
}
SiS_ShortDelay(SiS_Pr, Delay);
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315
if((SiS_Pr->ChipType >= SIS_661) ||
(SiS_Pr->ChipType <= SIS_315PRO) ||
(SiS_Pr->ChipType == SIS_330) ||
(SiS_Pr->SiS_ROMNew)) {
if(!(DelayTime & 0x01)) {
SiS_DDC2Delay(SiS_Pr, 0x1000);
} else {
SiS_DDC2Delay(SiS_Pr, 0x4000);
}
} else if (SiS_Pr->SiS_IF_DEF_LVDS == 1) { /* 315 series, LVDS; Special */
if(SiS_Pr->SiS_IF_DEF_CH70xx == 0) {
PanelID = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36);
if(SiS_Pr->SiS_CustomT == CUT_CLEVO1400) {
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x1b) & 0x10)) PanelID = 0x12;
}
if(SiS_Pr->SiS_CustomT == CUT_COMPAQ1280) {
DelayIndex = PanelID & 0x0f;
} else {
DelayIndex = PanelID >> 4;
}
if((DelayTime >= 2) && ((PanelID & 0x0f) == 1)) {
Delay = 3;
} else {
if(DelayTime >= 2) DelayTime -= 2;
if(!(DelayTime & 0x01)) {
Delay = SiS_Pr->SiS_PanelDelayTblLVDS[DelayIndex].timer[0];
} else {
Delay = SiS_Pr->SiS_PanelDelayTblLVDS[DelayIndex].timer[1];
}
if((SiS_Pr->SiS_UseROM) && (!(SiS_Pr->SiS_ROMNew))) {
if(ROMAddr[0x13c] & 0x40) {
if(!(DelayTime & 0x01)) {
Delay = (unsigned short)ROMAddr[0x17e];
} else {
Delay = (unsigned short)ROMAddr[0x17f];
}
}
}
}
SiS_ShortDelay(SiS_Pr, Delay);
}
} else if(SiS_Pr->SiS_VBType & VB_SISVB) { /* 315 series, all bridges */
DelayIndex = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) >> 4;
if(!(DelayTime & 0x01)) {
Delay = SiS_Pr->SiS_PanelDelayTbl[DelayIndex].timer[0];
} else {
Delay = SiS_Pr->SiS_PanelDelayTbl[DelayIndex].timer[1];
}
Delay <<= 8;
SiS_DDC2Delay(SiS_Pr, Delay);
}
#endif /* CONFIG_FB_SIS_315 */
}
}
#ifdef CONFIG_FB_SIS_315
static void
SiS_PanelDelayLoop(struct SiS_Private *SiS_Pr, unsigned short DelayTime, unsigned short DelayLoop)
{
int i;
for(i = 0; i < DelayLoop; i++) {
SiS_PanelDelay(SiS_Pr, DelayTime);
}
}
#endif
/*********************************************/
/* HELPER: WAIT-FOR-RETRACE FUNCTIONS */
/*********************************************/
void
SiS_WaitRetrace1(struct SiS_Private *SiS_Pr)
{
unsigned short watchdog;
if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x1f) & 0xc0) return;
if(!(SiS_GetReg(SiS_Pr->SiS_P3d4,0x17) & 0x80)) return;
watchdog = 65535;
while((SiS_GetRegByte(SiS_Pr->SiS_P3da) & 0x08) && --watchdog);
watchdog = 65535;
while((!(SiS_GetRegByte(SiS_Pr->SiS_P3da) & 0x08)) && --watchdog);
}
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
static void
SiS_WaitRetrace2(struct SiS_Private *SiS_Pr, unsigned short reg)
{
unsigned short watchdog;
watchdog = 65535;
while((SiS_GetReg(SiS_Pr->SiS_Part1Port,reg) & 0x02) && --watchdog);
watchdog = 65535;
while((!(SiS_GetReg(SiS_Pr->SiS_Part1Port,reg) & 0x02)) && --watchdog);
}
#endif
static void
SiS_WaitVBRetrace(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(!(SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0x20)) return;
}
if(!(SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0x80)) {
SiS_WaitRetrace1(SiS_Pr);
} else {
SiS_WaitRetrace2(SiS_Pr, 0x25);
}
#endif
} else {
#ifdef CONFIG_FB_SIS_315
if(!(SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0x40)) {
SiS_WaitRetrace1(SiS_Pr);
} else {
SiS_WaitRetrace2(SiS_Pr, 0x30);
}
#endif
}
}
static void
SiS_VBWait(struct SiS_Private *SiS_Pr)
{
unsigned short tempal,temp,i,j;
temp = 0;
for(i = 0; i < 3; i++) {
for(j = 0; j < 100; j++) {
tempal = SiS_GetRegByte(SiS_Pr->SiS_P3da);
if(temp & 0x01) {
if((tempal & 0x08)) continue;
else break;
} else {
if(!(tempal & 0x08)) continue;
else break;
}
}
temp ^= 0x01;
}
}
static void
SiS_VBLongWait(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
SiS_VBWait(SiS_Pr);
} else {
SiS_WaitRetrace1(SiS_Pr);
}
}
/*********************************************/
/* HELPER: MISC */
/*********************************************/
#ifdef CONFIG_FB_SIS_300
static bool
SiS_Is301B(struct SiS_Private *SiS_Pr)
{
if(SiS_GetReg(SiS_Pr->SiS_Part4Port,0x01) >= 0xb0) return true;
return false;
}
#endif
static bool
SiS_CRT2IsLCD(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType == SIS_730) {
if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x13) & 0x20) return true;
}
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x30) & 0x20) return true;
return false;
}
bool
SiS_IsDualEdge(struct SiS_Private *SiS_Pr)
{
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_315H) {
if((SiS_Pr->ChipType != SIS_650) || (SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0xf0)) {
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x38) & EnableDualEdge) return true;
}
}
#endif
return false;
}
bool
SiS_IsVAMode(struct SiS_Private *SiS_Pr)
{
#ifdef CONFIG_FB_SIS_315
unsigned short flag;
if(SiS_Pr->ChipType >= SIS_315H) {
flag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
if((flag & EnableDualEdge) && (flag & SetToLCDA)) return true;
}
#endif
return false;
}
#ifdef CONFIG_FB_SIS_315
static bool
SiS_IsVAorLCD(struct SiS_Private *SiS_Pr)
{
if(SiS_IsVAMode(SiS_Pr)) return true;
if(SiS_CRT2IsLCD(SiS_Pr)) return true;
return false;
}
#endif
static bool
SiS_IsDualLink(struct SiS_Private *SiS_Pr)
{
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_315H) {
if((SiS_CRT2IsLCD(SiS_Pr)) ||
(SiS_IsVAMode(SiS_Pr))) {
if(SiS_Pr->SiS_LCDInfo & LCDDualLink) return true;
}
}
#endif
return false;
}
#ifdef CONFIG_FB_SIS_315
static bool
SiS_TVEnabled(struct SiS_Private *SiS_Pr)
{
if((SiS_GetReg(SiS_Pr->SiS_Part2Port,0x00) & 0x0f) != 0x0c) return true;
if(SiS_Pr->SiS_VBType & VB_SISYPBPR) {
if(SiS_GetReg(SiS_Pr->SiS_Part2Port,0x4d) & 0x10) return true;
}
return false;
}
#endif
#ifdef CONFIG_FB_SIS_315
static bool
SiS_LCDAEnabled(struct SiS_Private *SiS_Pr)
{
if(SiS_GetReg(SiS_Pr->SiS_Part1Port,0x13) & 0x04) return true;
return false;
}
#endif
#ifdef CONFIG_FB_SIS_315
static bool
SiS_WeHaveBacklightCtrl(struct SiS_Private *SiS_Pr)
{
if((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->ChipType < SIS_661)) {
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x79) & 0x10) return true;
}
return false;
}
#endif
#ifdef CONFIG_FB_SIS_315
static bool
SiS_IsNotM650orLater(struct SiS_Private *SiS_Pr)
{
unsigned short flag;
if(SiS_Pr->ChipType == SIS_650) {
flag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0xf0;
/* Check for revision != A0 only */
if((flag == 0xe0) || (flag == 0xc0) ||
(flag == 0xb0) || (flag == 0x90)) return false;
} else if(SiS_Pr->ChipType >= SIS_661) return false;
return true;
}
#endif
#ifdef CONFIG_FB_SIS_315
static bool
SiS_IsYPbPr(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType >= SIS_315H) {
/* YPrPb = 0x08 */
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x38) & EnableCHYPbPr) return true;
}
return false;
}
#endif
#ifdef CONFIG_FB_SIS_315
static bool
SiS_IsChScart(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType >= SIS_315H) {
/* Scart = 0x04 */
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x38) & EnableCHScart) return true;
}
return false;
}
#endif
#ifdef CONFIG_FB_SIS_315
static bool
SiS_IsTVOrYPbPrOrScart(struct SiS_Private *SiS_Pr)
{
unsigned short flag;
if(SiS_Pr->ChipType >= SIS_315H) {
flag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
if(flag & SetCRT2ToTV) return true;
flag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
if(flag & EnableCHYPbPr) return true; /* = YPrPb = 0x08 */
if(flag & EnableCHScart) return true; /* = Scart = 0x04 - TW */
} else {
flag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
if(flag & SetCRT2ToTV) return true;
}
return false;
}
#endif
#ifdef CONFIG_FB_SIS_315
static bool
SiS_IsLCDOrLCDA(struct SiS_Private *SiS_Pr)
{
unsigned short flag;
if(SiS_Pr->ChipType >= SIS_315H) {
flag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
if(flag & SetCRT2ToLCD) return true;
flag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
if(flag & SetToLCDA) return true;
} else {
flag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
if(flag & SetCRT2ToLCD) return true;
}
return false;
}
#endif
static bool
SiS_HaveBridge(struct SiS_Private *SiS_Pr)
{
unsigned short flag;
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
return true;
} else if(SiS_Pr->SiS_VBType & VB_SISVB) {
flag = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x00);
if((flag == 1) || (flag == 2)) return true;
}
return false;
}
static bool
SiS_BridgeIsEnabled(struct SiS_Private *SiS_Pr)
{
unsigned short flag;
if(SiS_HaveBridge(SiS_Pr)) {
flag = SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00);
if(SiS_Pr->ChipType < SIS_315H) {
flag &= 0xa0;
if((flag == 0x80) || (flag == 0x20)) return true;
} else {
flag &= 0x50;
if((flag == 0x40) || (flag == 0x10)) return true;
}
}
return false;
}
static bool
SiS_BridgeInSlavemode(struct SiS_Private *SiS_Pr)
{
unsigned short flag1;
flag1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x31);
if(flag1 & (SetInSlaveMode >> 8)) return true;
return false;
}
/*********************************************/
/* GET VIDEO BRIDGE CONFIG INFO */
/*********************************************/
/* Setup general purpose IO for Chrontel communication */
#ifdef CONFIG_FB_SIS_300
void
SiS_SetChrontelGPIO(struct SiS_Private *SiS_Pr, unsigned short myvbinfo)
{
unsigned int acpibase;
unsigned short temp;
if(!(SiS_Pr->SiS_ChSW)) return;
acpibase = sisfb_read_lpc_pci_dword(SiS_Pr, 0x74);
acpibase &= 0xFFFF;
if(!acpibase) return;
temp = SiS_GetRegShort((acpibase + 0x3c)); /* ACPI register 0x3c: GP Event 1 I/O mode select */
temp &= 0xFEFF;
SiS_SetRegShort((acpibase + 0x3c), temp);
temp = SiS_GetRegShort((acpibase + 0x3c));
temp = SiS_GetRegShort((acpibase + 0x3a)); /* ACPI register 0x3a: GP Pin Level (low/high) */
temp &= 0xFEFF;
if(!(myvbinfo & SetCRT2ToTV)) temp |= 0x0100;
SiS_SetRegShort((acpibase + 0x3a), temp);
temp = SiS_GetRegShort((acpibase + 0x3a));
}
#endif
void
SiS_GetVBInfo(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, int checkcrt2mode)
{
unsigned short tempax, tempbx, temp;
unsigned short modeflag, resinfo = 0;
SiS_Pr->SiS_SetFlag = 0;
modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
SiS_Pr->SiS_ModeType = modeflag & ModeTypeMask;
if((ModeNo > 0x13) && (!SiS_Pr->UseCustomMode)) {
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
tempbx = 0;
if(SiS_HaveBridge(SiS_Pr)) {
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
tempbx |= temp;
tempax = SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) << 8;
tempax &= (DriverMode | LoadDACFlag | SetNotSimuMode | SetPALTV);
tempbx |= tempax;
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_VBType & VB_SISLCDA) {
if(ModeNo == 0x03) {
/* Mode 0x03 is never in driver mode */
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x31,0xbf);
}
if(!(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & (DriverMode >> 8))) {
/* Reset LCDA setting if not driver mode */
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x38,0xfc);
}
if(IS_SIS650) {
if(SiS_Pr->SiS_UseLCDA) {
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0xF0) {
if((ModeNo <= 0x13) || (!(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & (DriverMode >> 8)))) {
SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x38,(EnableDualEdge | SetToLCDA));
}
}
}
}
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
if((temp & (EnableDualEdge | SetToLCDA)) == (EnableDualEdge | SetToLCDA)) {
tempbx |= SetCRT2ToLCDA;
}
}
if(SiS_Pr->ChipType >= SIS_661) { /* New CR layout */
tempbx &= ~(SetCRT2ToYPbPr525750 | SetCRT2ToHiVision);
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x38) & 0x04) {
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35) & 0xe0;
if(temp == 0x60) tempbx |= SetCRT2ToHiVision;
else if(SiS_Pr->SiS_VBType & VB_SISYPBPR) {
tempbx |= SetCRT2ToYPbPr525750;
}
}
}
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
if(temp & SetToLCDA) {
tempbx |= SetCRT2ToLCDA;
}
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(temp & EnableCHYPbPr) {
tempbx |= SetCRT2ToCHYPbPr;
}
}
}
}
#endif /* CONFIG_FB_SIS_315 */
if(!(SiS_Pr->SiS_VBType & VB_SISVGA2)) {
tempbx &= ~(SetCRT2ToRAMDAC);
}
if(SiS_Pr->SiS_VBType & VB_SISVB) {
temp = SetCRT2ToSVIDEO |
SetCRT2ToAVIDEO |
SetCRT2ToSCART |
SetCRT2ToLCDA |
SetCRT2ToLCD |
SetCRT2ToRAMDAC |
SetCRT2ToHiVision |
SetCRT2ToYPbPr525750;
} else {
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
temp = SetCRT2ToAVIDEO |
SetCRT2ToSVIDEO |
SetCRT2ToSCART |
SetCRT2ToLCDA |
SetCRT2ToLCD |
SetCRT2ToCHYPbPr;
} else {
temp = SetCRT2ToLCDA |
SetCRT2ToLCD;
}
} else {
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
temp = SetCRT2ToTV | SetCRT2ToLCD;
} else {
temp = SetCRT2ToLCD;
}
}
}
if(!(tempbx & temp)) {
tempax = DisableCRT2Display;
tempbx = 0;
}
if(SiS_Pr->SiS_VBType & VB_SISVB) {
unsigned short clearmask = ( DriverMode |
DisableCRT2Display |
LoadDACFlag |
SetNotSimuMode |
SetInSlaveMode |
SetPALTV |
SwitchCRT2 |
SetSimuScanMode );
if(tempbx & SetCRT2ToLCDA) tempbx &= (clearmask | SetCRT2ToLCDA);
if(tempbx & SetCRT2ToRAMDAC) tempbx &= (clearmask | SetCRT2ToRAMDAC);
if(tempbx & SetCRT2ToLCD) tempbx &= (clearmask | SetCRT2ToLCD);
if(tempbx & SetCRT2ToSCART) tempbx &= (clearmask | SetCRT2ToSCART);
if(tempbx & SetCRT2ToHiVision) tempbx &= (clearmask | SetCRT2ToHiVision);
if(tempbx & SetCRT2ToYPbPr525750) tempbx &= (clearmask | SetCRT2ToYPbPr525750);
} else {
if(SiS_Pr->ChipType >= SIS_315H) {
if(tempbx & SetCRT2ToLCDA) {
tempbx &= (0xFF00|SwitchCRT2|SetSimuScanMode);
}
}
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(tempbx & SetCRT2ToTV) {
tempbx &= (0xFF00|SetCRT2ToTV|SwitchCRT2|SetSimuScanMode);
}
}
if(tempbx & SetCRT2ToLCD) {
tempbx &= (0xFF00|SetCRT2ToLCD|SwitchCRT2|SetSimuScanMode);
}
if(SiS_Pr->ChipType >= SIS_315H) {
if(tempbx & SetCRT2ToLCDA) {
tempbx |= SetCRT2ToLCD;
}
}
}
if(tempax & DisableCRT2Display) {
if(!(tempbx & (SwitchCRT2 | SetSimuScanMode))) {
tempbx = SetSimuScanMode | DisableCRT2Display;
}
}
if(!(tempbx & DriverMode)) tempbx |= SetSimuScanMode;
/* LVDS/CHRONTEL (LCD/TV) and 301BDH (LCD) can only be slave in 8bpp modes */
if(SiS_Pr->SiS_ModeType <= ModeVGA) {
if( (SiS_Pr->SiS_IF_DEF_LVDS == 1) ||
((SiS_Pr->SiS_VBType & VB_NoLCD) && (tempbx & SetCRT2ToLCD)) ) {
modeflag &= (~CRT2Mode);
}
}
if(!(tempbx & SetSimuScanMode)) {
if(tempbx & SwitchCRT2) {
if((!(modeflag & CRT2Mode)) && (checkcrt2mode)) {
if(resinfo != SIS_RI_1600x1200) {
tempbx |= SetSimuScanMode;
}
}
} else {
if(SiS_BridgeIsEnabled(SiS_Pr)) {
if(!(tempbx & DriverMode)) {
if(SiS_BridgeInSlavemode(SiS_Pr)) {
tempbx |= SetSimuScanMode;
}
}
}
}
}
if(!(tempbx & DisableCRT2Display)) {
if(tempbx & DriverMode) {
if(tempbx & SetSimuScanMode) {
if((!(modeflag & CRT2Mode)) && (checkcrt2mode)) {
if(resinfo != SIS_RI_1600x1200) {
tempbx |= SetInSlaveMode;
}
}
}
} else {
tempbx |= SetInSlaveMode;
}
}
}
SiS_Pr->SiS_VBInfo = tempbx;
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->ChipType == SIS_630) {
SiS_SetChrontelGPIO(SiS_Pr, SiS_Pr->SiS_VBInfo);
}
#endif
#if 0
printk(KERN_DEBUG "sisfb: (init301: VBInfo= 0x%04x, SetFlag=0x%04x)\n",
SiS_Pr->SiS_VBInfo, SiS_Pr->SiS_SetFlag);
#endif
}
/*********************************************/
/* DETERMINE YPbPr MODE */
/*********************************************/
void
SiS_SetYPbPr(struct SiS_Private *SiS_Pr)
{
unsigned char temp;
/* Note: This variable is only used on 30xLV systems.
* CR38 has a different meaning on LVDS/CH7019 systems.
* On 661 and later, these bits moved to CR35.
*
* On 301, 301B, only HiVision 1080i is supported.
* On 30xLV, 301C, only YPbPr 1080i is supported.
*/
SiS_Pr->SiS_YPbPr = 0;
if(SiS_Pr->ChipType >= SIS_661) return;
if(SiS_Pr->SiS_VBType) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
SiS_Pr->SiS_YPbPr = YPbPrHiVision;
}
}
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_VBType & VB_SISYPBPR) {
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
if(temp & 0x08) {
switch((temp >> 4)) {
case 0x00: SiS_Pr->SiS_YPbPr = YPbPr525i; break;
case 0x01: SiS_Pr->SiS_YPbPr = YPbPr525p; break;
case 0x02: SiS_Pr->SiS_YPbPr = YPbPr750p; break;
case 0x03: SiS_Pr->SiS_YPbPr = YPbPrHiVision; break;
}
}
}
}
}
/*********************************************/
/* DETERMINE TVMode flag */
/*********************************************/
void
SiS_SetTVMode(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short temp, temp1, resinfo = 0, romindex = 0;
unsigned char OutputSelect = *SiS_Pr->pSiS_OutputSelect;
SiS_Pr->SiS_TVMode = 0;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) return;
if(SiS_Pr->UseCustomMode) return;
if(ModeNo > 0x13) {
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
if(SiS_Pr->ChipType < SIS_661) {
if(SiS_Pr->SiS_VBInfo & SetPALTV) SiS_Pr->SiS_TVMode |= TVSetPAL;
if(SiS_Pr->SiS_VBType & VB_SISVB) {
temp = 0;
if((SiS_Pr->ChipType == SIS_630) ||
(SiS_Pr->ChipType == SIS_730)) {
temp = 0x35;
romindex = 0xfe;
} else if(SiS_Pr->ChipType >= SIS_315H) {
temp = 0x38;
if(SiS_Pr->ChipType < XGI_20) {
romindex = 0xf3;
if(SiS_Pr->ChipType >= SIS_330) romindex = 0x11b;
}
}
if(temp) {
if(romindex && SiS_Pr->SiS_UseROM && (!(SiS_Pr->SiS_ROMNew))) {
OutputSelect = ROMAddr[romindex];
if(!(OutputSelect & EnablePALMN)) {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,temp,0x3F);
}
}
temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,temp);
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
if(temp1 & EnablePALM) { /* 0x40 */
SiS_Pr->SiS_TVMode |= TVSetPALM;
SiS_Pr->SiS_TVMode &= ~TVSetPAL;
} else if(temp1 & EnablePALN) { /* 0x80 */
SiS_Pr->SiS_TVMode |= TVSetPALN;
}
} else {
if(temp1 & EnableNTSCJ) { /* 0x40 */
SiS_Pr->SiS_TVMode |= TVSetNTSCJ;
}
}
}
/* Translate HiVision/YPbPr to our new flags */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
if(SiS_Pr->SiS_YPbPr == YPbPr750p) SiS_Pr->SiS_TVMode |= TVSetYPbPr750p;
else if(SiS_Pr->SiS_YPbPr == YPbPr525p) SiS_Pr->SiS_TVMode |= TVSetYPbPr525p;
else if(SiS_Pr->SiS_YPbPr == YPbPrHiVision) SiS_Pr->SiS_TVMode |= TVSetHiVision;
else SiS_Pr->SiS_TVMode |= TVSetYPbPr525i;
if(SiS_Pr->SiS_TVMode & (TVSetYPbPr750p | TVSetYPbPr525p | TVSetYPbPr525i)) {
SiS_Pr->SiS_VBInfo &= ~SetCRT2ToHiVision;
SiS_Pr->SiS_VBInfo |= SetCRT2ToYPbPr525750;
} else if(SiS_Pr->SiS_TVMode & TVSetHiVision) {
SiS_Pr->SiS_TVMode |= TVSetPAL;
}
}
} else if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_Pr->SiS_CHOverScan) {
if(SiS_Pr->SiS_IF_DEF_CH70xx == 1) {
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
if((temp & TVOverScan) || (SiS_Pr->SiS_CHOverScan == 1)) {
SiS_Pr->SiS_TVMode |= TVSetCHOverScan;
}
} else if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x79);
if((temp & 0x80) || (SiS_Pr->SiS_CHOverScan == 1)) {
SiS_Pr->SiS_TVMode |= TVSetCHOverScan;
}
}
if(SiS_Pr->SiS_CHSOverScan) {
SiS_Pr->SiS_TVMode |= TVSetCHOverScan;
}
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
if(temp & EnablePALM) SiS_Pr->SiS_TVMode |= TVSetPALM;
else if(temp & EnablePALN) SiS_Pr->SiS_TVMode |= TVSetPALN;
} else {
if(temp & EnableNTSCJ) {
SiS_Pr->SiS_TVMode |= TVSetNTSCJ;
}
}
}
}
} else { /* 661 and later */
temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
if(temp1 & 0x01) {
SiS_Pr->SiS_TVMode |= TVSetPAL;
if(temp1 & 0x08) {
SiS_Pr->SiS_TVMode |= TVSetPALN;
} else if(temp1 & 0x04) {
if(SiS_Pr->SiS_VBType & VB_SISVB) {
SiS_Pr->SiS_TVMode &= ~TVSetPAL;
}
SiS_Pr->SiS_TVMode |= TVSetPALM;
}
} else {
if(temp1 & 0x02) {
SiS_Pr->SiS_TVMode |= TVSetNTSCJ;
}
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
if(SiS_Pr->SiS_CHOverScan) {
if((temp1 & 0x10) || (SiS_Pr->SiS_CHOverScan == 1)) {
SiS_Pr->SiS_TVMode |= TVSetCHOverScan;
}
}
}
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
temp1 &= 0xe0;
if(temp1 == 0x00) SiS_Pr->SiS_TVMode |= TVSetYPbPr525i;
else if(temp1 == 0x20) SiS_Pr->SiS_TVMode |= TVSetYPbPr525p;
else if(temp1 == 0x40) SiS_Pr->SiS_TVMode |= TVSetYPbPr750p;
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
SiS_Pr->SiS_TVMode |= (TVSetHiVision | TVSetPAL);
}
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToYPbPr525750 | SetCRT2ToHiVision)) {
if(resinfo == SIS_RI_800x480 || resinfo == SIS_RI_1024x576 || resinfo == SIS_RI_1280x720) {
SiS_Pr->SiS_TVMode |= TVAspect169;
} else {
temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x39);
if(temp1 & 0x02) {
if(SiS_Pr->SiS_TVMode & (TVSetYPbPr750p | TVSetHiVision)) {
SiS_Pr->SiS_TVMode |= TVAspect169;
} else {
SiS_Pr->SiS_TVMode |= TVAspect43LB;
}
} else {
SiS_Pr->SiS_TVMode |= TVAspect43;
}
}
}
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToSCART) SiS_Pr->SiS_TVMode |= TVSetPAL;
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
SiS_Pr->SiS_TVMode |= TVSetPAL;
SiS_Pr->SiS_TVMode &= ~(TVSetPALM | TVSetPALN | TVSetNTSCJ);
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(SiS_Pr->SiS_TVMode & (TVSetYPbPr525i | TVSetYPbPr525p | TVSetYPbPr750p)) {
SiS_Pr->SiS_TVMode &= ~(TVSetPAL | TVSetNTSCJ | TVSetPALM | TVSetPALN);
}
}
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
if(!(SiS_Pr->SiS_VBInfo & SetNotSimuMode)) {
SiS_Pr->SiS_TVMode |= TVSetTVSimuMode;
}
}
if(!(SiS_Pr->SiS_TVMode & TVSetPAL)) {
if(resinfo == SIS_RI_1024x768) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) {
SiS_Pr->SiS_TVMode |= TVSet525p1024;
} else if(!(SiS_Pr->SiS_TVMode & (TVSetHiVision | TVSetYPbPr750p))) {
SiS_Pr->SiS_TVMode |= TVSetNTSC1024;
}
}
}
SiS_Pr->SiS_TVMode |= TVRPLLDIV2XO;
if((SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) &&
(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) {
SiS_Pr->SiS_TVMode &= ~TVRPLLDIV2XO;
} else if(SiS_Pr->SiS_TVMode & (TVSetYPbPr525p | TVSetYPbPr750p)) {
SiS_Pr->SiS_TVMode &= ~TVRPLLDIV2XO;
} else if(!(SiS_Pr->SiS_VBType & VB_SIS30xBLV)) {
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) {
SiS_Pr->SiS_TVMode &= ~TVRPLLDIV2XO;
}
}
}
SiS_Pr->SiS_VBInfo &= ~SetPALTV;
}
/*********************************************/
/* GET LCD INFO */
/*********************************************/
static unsigned short
SiS_GetBIOSLCDResInfo(struct SiS_Private *SiS_Pr)
{
unsigned short temp = SiS_Pr->SiS_LCDResInfo;
/* Translate my LCDResInfo to BIOS value */
switch(temp) {
case Panel_1280x768_2: temp = Panel_1280x768; break;
case Panel_1280x800_2: temp = Panel_1280x800; break;
case Panel_1280x854: temp = Panel661_1280x854; break;
}
return temp;
}
static void
SiS_GetLCDInfoBIOS(struct SiS_Private *SiS_Pr)
{
#ifdef CONFIG_FB_SIS_315
unsigned char *ROMAddr;
unsigned short temp;
if((ROMAddr = GetLCDStructPtr661(SiS_Pr))) {
if((temp = SISGETROMW(6)) != SiS_Pr->PanelHT) {
SiS_Pr->SiS_NeedRomModeData = true;
SiS_Pr->PanelHT = temp;
}
if((temp = SISGETROMW(8)) != SiS_Pr->PanelVT) {
SiS_Pr->SiS_NeedRomModeData = true;
SiS_Pr->PanelVT = temp;
}
SiS_Pr->PanelHRS = SISGETROMW(10);
SiS_Pr->PanelHRE = SISGETROMW(12);
SiS_Pr->PanelVRS = SISGETROMW(14);
SiS_Pr->PanelVRE = SISGETROMW(16);
SiS_Pr->PanelVCLKIdx315 = VCLK_CUSTOM_315;
SiS_Pr->SiS_VCLKData[VCLK_CUSTOM_315].CLOCK =
SiS_Pr->SiS_VBVCLKData[VCLK_CUSTOM_315].CLOCK = (unsigned short)((unsigned char)ROMAddr[18]);
SiS_Pr->SiS_VCLKData[VCLK_CUSTOM_315].SR2B =
SiS_Pr->SiS_VBVCLKData[VCLK_CUSTOM_315].Part4_A = ROMAddr[19];
SiS_Pr->SiS_VCLKData[VCLK_CUSTOM_315].SR2C =
SiS_Pr->SiS_VBVCLKData[VCLK_CUSTOM_315].Part4_B = ROMAddr[20];
}
#endif
}
static void
SiS_CheckScaling(struct SiS_Private *SiS_Pr, unsigned short resinfo,
const unsigned char *nonscalingmodes)
{
int i = 0;
while(nonscalingmodes[i] != 0xff) {
if(nonscalingmodes[i++] == resinfo) {
if((SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) ||
(SiS_Pr->UsePanelScaler == -1)) {
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
}
break;
}
}
}
void
SiS_GetLCDResInfo(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short temp,modeflag,resinfo=0,modexres=0,modeyres=0;
bool panelcanscale = false;
#ifdef CONFIG_FB_SIS_300
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
static const unsigned char SiS300SeriesLCDRes[] =
{ 0, 1, 2, 3, 7, 4, 5, 8,
0, 0, 10, 0, 0, 0, 0, 15 };
#endif
#ifdef CONFIG_FB_SIS_315
unsigned char *myptr = NULL;
#endif
SiS_Pr->SiS_LCDResInfo = 0;
SiS_Pr->SiS_LCDTypeInfo = 0;
SiS_Pr->SiS_LCDInfo = 0;
SiS_Pr->PanelHRS = 999; /* HSync start */
SiS_Pr->PanelHRE = 999; /* HSync end */
SiS_Pr->PanelVRS = 999; /* VSync start */
SiS_Pr->PanelVRE = 999; /* VSync end */
SiS_Pr->SiS_NeedRomModeData = false;
/* Alternative 1600x1200@60 timing for 1600x1200 LCDA */
SiS_Pr->Alternate1600x1200 = false;
if(!(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA))) return;
modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
if((ModeNo > 0x13) && (!SiS_Pr->UseCustomMode)) {
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
modexres = SiS_Pr->SiS_ModeResInfo[resinfo].HTotal;
modeyres = SiS_Pr->SiS_ModeResInfo[resinfo].VTotal;
}
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36);
/* For broken BIOSes: Assume 1024x768 */
if(temp == 0) temp = 0x02;
if((SiS_Pr->ChipType >= SIS_661) || (SiS_Pr->SiS_ROMNew)) {
SiS_Pr->SiS_LCDTypeInfo = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x39) & 0x7c) >> 2;
} else if((SiS_Pr->ChipType < SIS_315H) || (SiS_Pr->ChipType >= SIS_661)) {
SiS_Pr->SiS_LCDTypeInfo = temp >> 4;
} else {
SiS_Pr->SiS_LCDTypeInfo = (temp & 0x0F) - 1;
}
temp &= 0x0f;
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->ChipType < SIS_315H) {
/* Very old BIOSes only know 7 sizes (NetVista 2179, 1.01g) */
if(SiS_Pr->SiS_VBType & VB_SIS301) {
if(temp < 0x0f) temp &= 0x07;
}
/* Translate 300 series LCDRes to 315 series for unified usage */
temp = SiS300SeriesLCDRes[temp];
}
#endif
/* Translate to our internal types */
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType == SIS_550) {
if (temp == Panel310_1152x768) temp = Panel_320x240_2; /* Verified working */
else if(temp == Panel310_320x240_2) temp = Panel_320x240_2;
else if(temp == Panel310_320x240_3) temp = Panel_320x240_3;
} else if(SiS_Pr->ChipType >= SIS_661) {
if(temp == Panel661_1280x854) temp = Panel_1280x854;
}
#endif
if(SiS_Pr->SiS_VBType & VB_SISLVDS) { /* SiS LVDS */
if(temp == Panel310_1280x768) {
temp = Panel_1280x768_2;
}
if(SiS_Pr->SiS_ROMNew) {
if(temp == Panel661_1280x800) {
temp = Panel_1280x800_2;
}
}
}
SiS_Pr->SiS_LCDResInfo = temp;
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if(SiS_Pr->SiS_CustomT == CUT_BARCO1366) {
SiS_Pr->SiS_LCDResInfo = Panel_Barco1366;
} else if(SiS_Pr->SiS_CustomT == CUT_PANEL848) {
SiS_Pr->SiS_LCDResInfo = Panel_848x480;
} else if(SiS_Pr->SiS_CustomT == CUT_PANEL856) {
SiS_Pr->SiS_LCDResInfo = Panel_856x480;
}
}
#endif
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_LCDResInfo < SiS_Pr->SiS_PanelMin301)
SiS_Pr->SiS_LCDResInfo = SiS_Pr->SiS_PanelMin301;
} else {
if(SiS_Pr->SiS_LCDResInfo < SiS_Pr->SiS_PanelMinLVDS)
SiS_Pr->SiS_LCDResInfo = SiS_Pr->SiS_PanelMinLVDS;
}
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x37);
SiS_Pr->SiS_LCDInfo = temp & ~0x000e;
/* Need temp below! */
/* These must/can't scale no matter what */
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_320x240_1:
case Panel_320x240_2:
case Panel_320x240_3:
case Panel_1280x960:
SiS_Pr->SiS_LCDInfo &= ~DontExpandLCD;
break;
case Panel_640x480:
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
}
panelcanscale = (bool)(SiS_Pr->SiS_LCDInfo & DontExpandLCD);
if(!SiS_Pr->UsePanelScaler) SiS_Pr->SiS_LCDInfo &= ~DontExpandLCD;
else if(SiS_Pr->UsePanelScaler == 1) SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
/* Dual link, Pass 1:1 BIOS default, etc. */
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_661) {
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
if(temp & 0x08) SiS_Pr->SiS_LCDInfo |= LCDPass11;
}
if(SiS_Pr->SiS_VBType & VB_SISDUALLINK) {
if(SiS_Pr->SiS_ROMNew) {
if(temp & 0x02) SiS_Pr->SiS_LCDInfo |= LCDDualLink;
} else if((myptr = GetLCDStructPtr661(SiS_Pr))) {
if(myptr[2] & 0x01) SiS_Pr->SiS_LCDInfo |= LCDDualLink;
}
}
} else if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x39) & 0x01) SiS_Pr->SiS_LCDInfo |= LCDPass11;
}
if((SiS_Pr->SiS_ROMNew) && (!(SiS_Pr->PanelSelfDetected))) {
SiS_Pr->SiS_LCDInfo &= ~(LCDRGB18Bit);
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
if(temp & 0x01) SiS_Pr->SiS_LCDInfo |= LCDRGB18Bit;
if(SiS_Pr->SiS_VBType & VB_SISDUALLINK) {
if(temp & 0x02) SiS_Pr->SiS_LCDInfo |= LCDDualLink;
}
} else if(!(SiS_Pr->SiS_ROMNew)) {
if(SiS_Pr->SiS_VBType & VB_SISDUALLINK) {
if((SiS_Pr->SiS_CustomT == CUT_CLEVO1024) &&
(SiS_Pr->SiS_LCDResInfo == Panel_1024x768)) {
SiS_Pr->SiS_LCDInfo |= LCDDualLink;
}
if((SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1680x1050)) {
SiS_Pr->SiS_LCDInfo |= LCDDualLink;
}
}
}
}
#endif
/* Pass 1:1 */
if((SiS_Pr->SiS_IF_DEF_LVDS == 1) || (SiS_Pr->SiS_VBType & VB_NoLCD)) {
/* Always center screen on LVDS (if scaling is disabled) */
SiS_Pr->SiS_LCDInfo &= ~LCDPass11;
} else if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
/* Always center screen on SiS LVDS (if scaling is disabled) */
SiS_Pr->SiS_LCDInfo &= ~LCDPass11;
} else {
/* By default, pass 1:1 on SiS TMDS (if scaling is supported) */
if(panelcanscale) SiS_Pr->SiS_LCDInfo |= LCDPass11;
if(SiS_Pr->CenterScreen == 1) SiS_Pr->SiS_LCDInfo &= ~LCDPass11;
}
}
SiS_Pr->PanelVCLKIdx300 = VCLK65_300;
SiS_Pr->PanelVCLKIdx315 = VCLK108_2_315;
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_320x240_1:
case Panel_320x240_2:
case Panel_320x240_3: SiS_Pr->PanelXRes = 640; SiS_Pr->PanelYRes = 480;
SiS_Pr->PanelVRS = 24; SiS_Pr->PanelVRE = 3;
SiS_Pr->PanelVCLKIdx300 = VCLK28;
SiS_Pr->PanelVCLKIdx315 = VCLK28;
break;
case Panel_640x480: SiS_Pr->PanelXRes = 640; SiS_Pr->PanelYRes = 480;
SiS_Pr->PanelVRE = 3;
SiS_Pr->PanelVCLKIdx300 = VCLK28;
SiS_Pr->PanelVCLKIdx315 = VCLK28;
break;
case Panel_800x600: SiS_Pr->PanelXRes = 800; SiS_Pr->PanelYRes = 600;
SiS_Pr->PanelHT = 1056; SiS_Pr->PanelVT = 628;
SiS_Pr->PanelHRS = 40; SiS_Pr->PanelHRE = 128;
SiS_Pr->PanelVRS = 1; SiS_Pr->PanelVRE = 4;
SiS_Pr->PanelVCLKIdx300 = VCLK40;
SiS_Pr->PanelVCLKIdx315 = VCLK40;
break;
case Panel_1024x600: SiS_Pr->PanelXRes = 1024; SiS_Pr->PanelYRes = 600;
SiS_Pr->PanelHT = 1344; SiS_Pr->PanelVT = 800;
SiS_Pr->PanelHRS = 24; SiS_Pr->PanelHRE = 136;
SiS_Pr->PanelVRS = 2 /* 88 */ ; SiS_Pr->PanelVRE = 6;
SiS_Pr->PanelVCLKIdx300 = VCLK65_300;
SiS_Pr->PanelVCLKIdx315 = VCLK65_315;
break;
case Panel_1024x768: SiS_Pr->PanelXRes = 1024; SiS_Pr->PanelYRes = 768;
SiS_Pr->PanelHT = 1344; SiS_Pr->PanelVT = 806;
SiS_Pr->PanelHRS = 24; SiS_Pr->PanelHRE = 136;
SiS_Pr->PanelVRS = 3; SiS_Pr->PanelVRE = 6;
if(SiS_Pr->ChipType < SIS_315H) {
SiS_Pr->PanelHRS = 23;
SiS_Pr->PanelVRE = 5;
}
SiS_Pr->PanelVCLKIdx300 = VCLK65_300;
SiS_Pr->PanelVCLKIdx315 = VCLK65_315;
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1152x768: SiS_Pr->PanelXRes = 1152; SiS_Pr->PanelYRes = 768;
SiS_Pr->PanelHT = 1344; SiS_Pr->PanelVT = 806;
SiS_Pr->PanelHRS = 24; SiS_Pr->PanelHRE = 136;
SiS_Pr->PanelVRS = 3; SiS_Pr->PanelVRE = 6;
if(SiS_Pr->ChipType < SIS_315H) {
SiS_Pr->PanelHRS = 23;
SiS_Pr->PanelVRE = 5;
}
SiS_Pr->PanelVCLKIdx300 = VCLK65_300;
SiS_Pr->PanelVCLKIdx315 = VCLK65_315;
break;
case Panel_1152x864: SiS_Pr->PanelXRes = 1152; SiS_Pr->PanelYRes = 864;
break;
case Panel_1280x720: SiS_Pr->PanelXRes = 1280; SiS_Pr->PanelYRes = 720;
SiS_Pr->PanelHT = 1650; SiS_Pr->PanelVT = 750;
SiS_Pr->PanelHRS = 110; SiS_Pr->PanelHRE = 40;
SiS_Pr->PanelVRS = 5; SiS_Pr->PanelVRE = 5;
SiS_Pr->PanelVCLKIdx315 = VCLK_1280x720;
/* Data above for TMDS (projector); get from BIOS for LVDS */
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1280x768: SiS_Pr->PanelXRes = 1280; SiS_Pr->PanelYRes = 768;
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
SiS_Pr->PanelHT = 1408; SiS_Pr->PanelVT = 806;
SiS_Pr->PanelVCLKIdx300 = VCLK81_300; /* ? */
SiS_Pr->PanelVCLKIdx315 = VCLK81_315; /* ? */
} else {
SiS_Pr->PanelHT = 1688; SiS_Pr->PanelVT = 802;
SiS_Pr->PanelHRS = 48; SiS_Pr->PanelHRE = 112;
SiS_Pr->PanelVRS = 3; SiS_Pr->PanelVRE = 6;
SiS_Pr->PanelVCLKIdx300 = VCLK81_300;
SiS_Pr->PanelVCLKIdx315 = VCLK81_315;
}
break;
case Panel_1280x768_2: SiS_Pr->PanelXRes = 1280; SiS_Pr->PanelYRes = 768;
SiS_Pr->PanelHT = 1660; SiS_Pr->PanelVT = 806;
SiS_Pr->PanelHRS = 48; SiS_Pr->PanelHRE = 112;
SiS_Pr->PanelVRS = 3; SiS_Pr->PanelVRE = 6;
SiS_Pr->PanelVCLKIdx315 = VCLK_1280x768_2;
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1280x800: SiS_Pr->PanelXRes = 1280; SiS_Pr->PanelYRes = 800;
SiS_Pr->PanelHT = 1408; SiS_Pr->PanelVT = 816;
SiS_Pr->PanelHRS = 21; SiS_Pr->PanelHRE = 24;
SiS_Pr->PanelVRS = 4; SiS_Pr->PanelVRE = 3;
SiS_Pr->PanelVCLKIdx315 = VCLK_1280x800_315;
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1280x800_2: SiS_Pr->PanelXRes = 1280; SiS_Pr->PanelYRes = 800;
SiS_Pr->PanelHT = 1552; SiS_Pr->PanelVT = 812;
SiS_Pr->PanelHRS = 48; SiS_Pr->PanelHRE = 112;
SiS_Pr->PanelVRS = 4; SiS_Pr->PanelVRE = 3;
SiS_Pr->PanelVCLKIdx315 = VCLK_1280x800_315_2;
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1280x854: SiS_Pr->PanelXRes = 1280; SiS_Pr->PanelYRes = 854;
SiS_Pr->PanelHT = 1664; SiS_Pr->PanelVT = 861;
SiS_Pr->PanelHRS = 16; SiS_Pr->PanelHRE = 112;
SiS_Pr->PanelVRS = 1; SiS_Pr->PanelVRE = 3;
SiS_Pr->PanelVCLKIdx315 = VCLK_1280x854;
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1280x960: SiS_Pr->PanelXRes = 1280; SiS_Pr->PanelYRes = 960;
SiS_Pr->PanelHT = 1800; SiS_Pr->PanelVT = 1000;
SiS_Pr->PanelVCLKIdx300 = VCLK108_3_300;
SiS_Pr->PanelVCLKIdx315 = VCLK108_3_315;
if(resinfo == SIS_RI_1280x1024) {
SiS_Pr->PanelVCLKIdx300 = VCLK100_300;
SiS_Pr->PanelVCLKIdx315 = VCLK100_315;
}
break;
case Panel_1280x1024: SiS_Pr->PanelXRes = 1280; SiS_Pr->PanelYRes = 1024;
SiS_Pr->PanelHT = 1688; SiS_Pr->PanelVT = 1066;
SiS_Pr->PanelHRS = 48; SiS_Pr->PanelHRE = 112;
SiS_Pr->PanelVRS = 1; SiS_Pr->PanelVRE = 3;
SiS_Pr->PanelVCLKIdx300 = VCLK108_3_300;
SiS_Pr->PanelVCLKIdx315 = VCLK108_2_315;
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1400x1050: SiS_Pr->PanelXRes = 1400; SiS_Pr->PanelYRes = 1050;
SiS_Pr->PanelHT = 1688; SiS_Pr->PanelVT = 1066;
SiS_Pr->PanelHRS = 48; SiS_Pr->PanelHRE = 112;
SiS_Pr->PanelVRS = 1; SiS_Pr->PanelVRE = 3;
SiS_Pr->PanelVCLKIdx315 = VCLK108_2_315;
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1600x1200: SiS_Pr->PanelXRes = 1600; SiS_Pr->PanelYRes = 1200;
SiS_Pr->PanelHT = 2160; SiS_Pr->PanelVT = 1250;
SiS_Pr->PanelHRS = 64; SiS_Pr->PanelHRE = 192;
SiS_Pr->PanelVRS = 1; SiS_Pr->PanelVRE = 3;
SiS_Pr->PanelVCLKIdx315 = VCLK162_315;
if(SiS_Pr->SiS_VBType & VB_SISTMDSLCDA) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_Pr->PanelHT = 1760; SiS_Pr->PanelVT = 1235;
SiS_Pr->PanelHRS = 48; SiS_Pr->PanelHRE = 32;
SiS_Pr->PanelVRS = 2; SiS_Pr->PanelVRE = 4;
SiS_Pr->PanelVCLKIdx315 = VCLK130_315;
SiS_Pr->Alternate1600x1200 = true;
}
} else if(SiS_Pr->SiS_IF_DEF_LVDS) {
SiS_Pr->PanelHT = 2048; SiS_Pr->PanelVT = 1320;
SiS_Pr->PanelHRS = SiS_Pr->PanelHRE = 999;
SiS_Pr->PanelVRS = SiS_Pr->PanelVRE = 999;
}
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_1680x1050: SiS_Pr->PanelXRes = 1680; SiS_Pr->PanelYRes = 1050;
SiS_Pr->PanelHT = 1900; SiS_Pr->PanelVT = 1066;
SiS_Pr->PanelHRS = 26; SiS_Pr->PanelHRE = 76;
SiS_Pr->PanelVRS = 3; SiS_Pr->PanelVRE = 6;
SiS_Pr->PanelVCLKIdx315 = VCLK121_315;
SiS_GetLCDInfoBIOS(SiS_Pr);
break;
case Panel_Barco1366: SiS_Pr->PanelXRes = 1360; SiS_Pr->PanelYRes = 1024;
SiS_Pr->PanelHT = 1688; SiS_Pr->PanelVT = 1066;
break;
case Panel_848x480: SiS_Pr->PanelXRes = 848; SiS_Pr->PanelYRes = 480;
SiS_Pr->PanelHT = 1088; SiS_Pr->PanelVT = 525;
break;
case Panel_856x480: SiS_Pr->PanelXRes = 856; SiS_Pr->PanelYRes = 480;
SiS_Pr->PanelHT = 1088; SiS_Pr->PanelVT = 525;
break;
case Panel_Custom: SiS_Pr->PanelXRes = SiS_Pr->CP_MaxX;
SiS_Pr->PanelYRes = SiS_Pr->CP_MaxY;
SiS_Pr->PanelHT = SiS_Pr->CHTotal;
SiS_Pr->PanelVT = SiS_Pr->CVTotal;
if(SiS_Pr->CP_PreferredIndex != -1) {
SiS_Pr->PanelXRes = SiS_Pr->CP_HDisplay[SiS_Pr->CP_PreferredIndex];
SiS_Pr->PanelYRes = SiS_Pr->CP_VDisplay[SiS_Pr->CP_PreferredIndex];
SiS_Pr->PanelHT = SiS_Pr->CP_HTotal[SiS_Pr->CP_PreferredIndex];
SiS_Pr->PanelVT = SiS_Pr->CP_VTotal[SiS_Pr->CP_PreferredIndex];
SiS_Pr->PanelHRS = SiS_Pr->CP_HSyncStart[SiS_Pr->CP_PreferredIndex];
SiS_Pr->PanelHRE = SiS_Pr->CP_HSyncEnd[SiS_Pr->CP_PreferredIndex];
SiS_Pr->PanelVRS = SiS_Pr->CP_VSyncStart[SiS_Pr->CP_PreferredIndex];
SiS_Pr->PanelVRE = SiS_Pr->CP_VSyncEnd[SiS_Pr->CP_PreferredIndex];
SiS_Pr->PanelHRS -= SiS_Pr->PanelXRes;
SiS_Pr->PanelHRE -= SiS_Pr->PanelHRS;
SiS_Pr->PanelVRS -= SiS_Pr->PanelYRes;
SiS_Pr->PanelVRE -= SiS_Pr->PanelVRS;
if(SiS_Pr->CP_PrefClock) {
int idx;
SiS_Pr->PanelVCLKIdx315 = VCLK_CUSTOM_315;
SiS_Pr->PanelVCLKIdx300 = VCLK_CUSTOM_300;
if(SiS_Pr->ChipType < SIS_315H) idx = VCLK_CUSTOM_300;
else idx = VCLK_CUSTOM_315;
SiS_Pr->SiS_VCLKData[idx].CLOCK =
SiS_Pr->SiS_VBVCLKData[idx].CLOCK = SiS_Pr->CP_PrefClock;
SiS_Pr->SiS_VCLKData[idx].SR2B =
SiS_Pr->SiS_VBVCLKData[idx].Part4_A = SiS_Pr->CP_PrefSR2B;
SiS_Pr->SiS_VCLKData[idx].SR2C =
SiS_Pr->SiS_VBVCLKData[idx].Part4_B = SiS_Pr->CP_PrefSR2C;
}
}
break;
default: SiS_Pr->PanelXRes = 1024; SiS_Pr->PanelYRes = 768;
SiS_Pr->PanelHT = 1344; SiS_Pr->PanelVT = 806;
break;
}
/* Special cases */
if( (SiS_Pr->SiS_IF_DEF_FSTN) ||
(SiS_Pr->SiS_IF_DEF_DSTN) ||
(SiS_Pr->SiS_CustomT == CUT_BARCO1366) ||
(SiS_Pr->SiS_CustomT == CUT_BARCO1024) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL848) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL856) ) {
SiS_Pr->PanelHRS = 999;
SiS_Pr->PanelHRE = 999;
}
if( (SiS_Pr->SiS_CustomT == CUT_BARCO1366) ||
(SiS_Pr->SiS_CustomT == CUT_BARCO1024) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL848) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL856) ) {
SiS_Pr->PanelVRS = 999;
SiS_Pr->PanelVRE = 999;
}
/* DontExpand overrule */
if((SiS_Pr->SiS_VBType & VB_SISVB) && (!(SiS_Pr->SiS_VBType & VB_NoLCD))) {
if((SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) && (modeflag & NoSupportLCDScale)) {
/* No scaling for this mode on any panel (LCD=CRT2)*/
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
}
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_Custom:
case Panel_1152x864:
case Panel_1280x768: /* TMDS only */
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
break;
case Panel_800x600: {
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, 0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
break;
}
case Panel_1024x768: {
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
break;
}
case Panel_1280x720: {
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
if(SiS_Pr->PanelHT == 1650) {
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
}
break;
}
case Panel_1280x768_2: { /* LVDS only */
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
switch(resinfo) {
case SIS_RI_1280x720: if(SiS_Pr->UsePanelScaler == -1) {
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
}
break;
}
break;
}
case Panel_1280x800: { /* SiS TMDS special (Averatec 6200 series) */
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,SIS_RI_1280x720,SIS_RI_1280x768,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
break;
}
case Panel_1280x800_2: { /* SiS LVDS */
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
switch(resinfo) {
case SIS_RI_1280x720:
case SIS_RI_1280x768: if(SiS_Pr->UsePanelScaler == -1) {
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
}
break;
}
break;
}
case Panel_1280x854: { /* SiS LVDS */
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
switch(resinfo) {
case SIS_RI_1280x720:
case SIS_RI_1280x768:
case SIS_RI_1280x800: if(SiS_Pr->UsePanelScaler == -1) {
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
}
break;
}
break;
}
case Panel_1280x960: {
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,SIS_RI_1152x864,SIS_RI_1280x720,SIS_RI_1280x768,SIS_RI_1280x800,
SIS_RI_1280x854,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
break;
}
case Panel_1280x1024: {
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,SIS_RI_1152x864,SIS_RI_1280x720,SIS_RI_1280x768,SIS_RI_1280x800,
SIS_RI_1280x854,SIS_RI_1280x960,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
break;
}
case Panel_1400x1050: {
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,SIS_RI_1152x864,SIS_RI_1280x768,SIS_RI_1280x800,SIS_RI_1280x854,
SIS_RI_1280x960,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
switch(resinfo) {
case SIS_RI_1280x720: if(SiS_Pr->UsePanelScaler == -1) {
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
}
break;
case SIS_RI_1280x1024: SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
break;
}
break;
}
case Panel_1600x1200: {
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,SIS_RI_1152x864,SIS_RI_1280x720,SIS_RI_1280x768,SIS_RI_1280x800,
SIS_RI_1280x854,SIS_RI_1280x960,SIS_RI_1360x768,SIS_RI_1360x1024,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
break;
}
case Panel_1680x1050: {
static const unsigned char nonscalingmodes[] = {
SIS_RI_720x480, SIS_RI_720x576, SIS_RI_768x576, SIS_RI_800x480, SIS_RI_848x480,
SIS_RI_856x480, SIS_RI_960x540, SIS_RI_960x600, SIS_RI_1024x576,SIS_RI_1024x600,
SIS_RI_1152x768,SIS_RI_1152x864,SIS_RI_1280x854,SIS_RI_1280x960,SIS_RI_1360x768,
SIS_RI_1360x1024,0xff
};
SiS_CheckScaling(SiS_Pr, resinfo, nonscalingmodes);
break;
}
}
}
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if(SiS_Pr->SiS_CustomT == CUT_PANEL848 || SiS_Pr->SiS_CustomT == CUT_PANEL856) {
SiS_Pr->SiS_LCDInfo = 0x80 | 0x40 | 0x20; /* neg h/v sync, RGB24(D0 = 0) */
}
}
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if(SiS_Pr->SiS_UseROM) {
if((ROMAddr[0x233] == 0x12) && (ROMAddr[0x234] == 0x34)) {
if(!(ROMAddr[0x235] & 0x02)) {
SiS_Pr->SiS_LCDInfo &= (~DontExpandLCD);
}
}
}
} else if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if((SiS_Pr->SiS_SetFlag & SetDOSMode) && ((ModeNo == 0x03) || (ModeNo == 0x10))) {
SiS_Pr->SiS_LCDInfo &= (~DontExpandLCD);
}
}
}
#endif
/* Special cases */
if(modexres == SiS_Pr->PanelXRes && modeyres == SiS_Pr->PanelYRes) {
SiS_Pr->SiS_LCDInfo &= ~LCDPass11;
}
if(SiS_Pr->SiS_IF_DEF_TRUMPION) {
SiS_Pr->SiS_LCDInfo |= (DontExpandLCD | LCDPass11);
}
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_640x480:
SiS_Pr->SiS_LCDInfo |= (DontExpandLCD | LCDPass11);
break;
case Panel_1280x800:
/* Don't pass 1:1 by default (TMDS special) */
if(SiS_Pr->CenterScreen == -1) SiS_Pr->SiS_LCDInfo &= ~LCDPass11;
break;
case Panel_1280x960:
SiS_Pr->SiS_LCDInfo &= ~LCDPass11;
break;
case Panel_Custom:
if((!SiS_Pr->CP_PrefClock) ||
(modexres > SiS_Pr->PanelXRes) || (modeyres > SiS_Pr->PanelYRes)) {
SiS_Pr->SiS_LCDInfo |= LCDPass11;
}
break;
}
if((SiS_Pr->UseCustomMode) || (SiS_Pr->SiS_CustomT == CUT_UNKNOWNLCD)) {
SiS_Pr->SiS_LCDInfo |= (DontExpandLCD | LCDPass11);
}
/* (In)validate LCDPass11 flag */
if(!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) {
SiS_Pr->SiS_LCDInfo &= ~LCDPass11;
}
/* LVDS DDA */
if(!((SiS_Pr->ChipType < SIS_315H) && (SiS_Pr->SiS_SetFlag & SetDOSMode))) {
if((SiS_Pr->SiS_IF_DEF_LVDS == 1) || (SiS_Pr->SiS_VBType & VB_NoLCD)) {
if(SiS_Pr->SiS_IF_DEF_TRUMPION == 0) {
if(ModeNo == 0x12) {
if(SiS_Pr->SiS_LCDInfo & LCDPass11) {
SiS_Pr->SiS_SetFlag |= EnableLVDSDDA;
}
} else if(ModeNo > 0x13) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x600) {
if(!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) {
if((resinfo == SIS_RI_800x600) || (resinfo == SIS_RI_400x300)) {
SiS_Pr->SiS_SetFlag |= EnableLVDSDDA;
}
}
}
}
}
}
if(modeflag & HalfDCLK) {
if(SiS_Pr->SiS_IF_DEF_TRUMPION == 1) {
SiS_Pr->SiS_SetFlag |= EnableLVDSDDA;
} else if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
SiS_Pr->SiS_SetFlag |= EnableLVDSDDA;
} else if(SiS_Pr->SiS_LCDResInfo == Panel_640x480) {
SiS_Pr->SiS_SetFlag |= EnableLVDSDDA;
} else if(ModeNo > 0x13) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(resinfo == SIS_RI_512x384) SiS_Pr->SiS_SetFlag |= EnableLVDSDDA;
} else if(SiS_Pr->SiS_LCDResInfo == Panel_800x600) {
if(resinfo == SIS_RI_400x300) SiS_Pr->SiS_SetFlag |= EnableLVDSDDA;
}
}
}
}
/* VESA timing */
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
if(SiS_Pr->SiS_VBInfo & SetNotSimuMode) {
SiS_Pr->SiS_SetFlag |= LCDVESATiming;
}
} else {
SiS_Pr->SiS_SetFlag |= LCDVESATiming;
}
#if 0
printk(KERN_DEBUG "sisfb: (LCDInfo=0x%04x LCDResInfo=0x%02x LCDTypeInfo=0x%02x)\n",
SiS_Pr->SiS_LCDInfo, SiS_Pr->SiS_LCDResInfo, SiS_Pr->SiS_LCDTypeInfo);
#endif
}
/*********************************************/
/* GET VCLK */
/*********************************************/
unsigned short
SiS_GetVCLK2Ptr(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short CRT2Index, VCLKIndex = 0, VCLKIndexGEN = 0, VCLKIndexGENCRT = 0;
unsigned short resinfo, tempbx;
const unsigned char *CHTVVCLKPtr = NULL;
if(ModeNo <= 0x13) {
resinfo = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ResInfo;
CRT2Index = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
VCLKIndexGEN = (SiS_GetRegByte((SiS_Pr->SiS_P3ca+0x02)) >> 2) & 0x03;
VCLKIndexGENCRT = VCLKIndexGEN;
} else {
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
CRT2Index = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
VCLKIndexGEN = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRTVCLK;
VCLKIndexGENCRT = SiS_GetRefCRTVCLK(SiS_Pr, RefreshRateTableIndex,
(SiS_Pr->SiS_SetFlag & ProgrammingCRT2) ? SiS_Pr->SiS_UseWideCRT2 : SiS_Pr->SiS_UseWide);
}
if(SiS_Pr->SiS_VBType & VB_SISVB) { /* 30x/B/LV */
if(SiS_Pr->SiS_SetFlag & ProgrammingCRT2) {
CRT2Index >>= 6;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) { /* LCD */
if(SiS_Pr->ChipType < SIS_315H) {
VCLKIndex = SiS_Pr->PanelVCLKIdx300;
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (SiS_Pr->SiS_LCDInfo & LCDPass11)) {
VCLKIndex = VCLKIndexGEN;
}
} else {
VCLKIndex = SiS_Pr->PanelVCLKIdx315;
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (SiS_Pr->SiS_LCDInfo & LCDPass11)) {
switch(resinfo) {
/* Correct those whose IndexGEN doesn't match VBVCLK array */
case SIS_RI_720x480: VCLKIndex = VCLK_720x480; break;
case SIS_RI_720x576: VCLKIndex = VCLK_720x576; break;
case SIS_RI_768x576: VCLKIndex = VCLK_768x576; break;
case SIS_RI_848x480: VCLKIndex = VCLK_848x480; break;
case SIS_RI_856x480: VCLKIndex = VCLK_856x480; break;
case SIS_RI_800x480: VCLKIndex = VCLK_800x480; break;
case SIS_RI_1024x576: VCLKIndex = VCLK_1024x576; break;
case SIS_RI_1152x864: VCLKIndex = VCLK_1152x864; break;
case SIS_RI_1280x720: VCLKIndex = VCLK_1280x720; break;
case SIS_RI_1360x768: VCLKIndex = VCLK_1360x768; break;
default: VCLKIndex = VCLKIndexGEN;
}
if(ModeNo <= 0x13) {
if(SiS_Pr->ChipType <= SIS_315PRO) {
if(SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC == 1) VCLKIndex = 0x42;
} else {
if(SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC == 1) VCLKIndex = 0x00;
}
}
if(SiS_Pr->ChipType <= SIS_315PRO) {
if(VCLKIndex == 0) VCLKIndex = 0x41;
if(VCLKIndex == 1) VCLKIndex = 0x43;
if(VCLKIndex == 4) VCLKIndex = 0x44;
}
}
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) { /* TV */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
if(SiS_Pr->SiS_TVMode & TVRPLLDIV2XO) VCLKIndex = HiTVVCLKDIV2;
else VCLKIndex = HiTVVCLK;
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) VCLKIndex = HiTVSimuVCLK;
} else if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) VCLKIndex = YPbPr750pVCLK;
else if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) VCLKIndex = TVVCLKDIV2;
else if(SiS_Pr->SiS_TVMode & TVRPLLDIV2XO) VCLKIndex = TVVCLKDIV2;
else VCLKIndex = TVVCLK;
if(SiS_Pr->ChipType < SIS_315H) VCLKIndex += TVCLKBASE_300;
else VCLKIndex += TVCLKBASE_315;
} else { /* VGA2 */
VCLKIndex = VCLKIndexGENCRT;
if(SiS_Pr->ChipType < SIS_315H) {
if(ModeNo > 0x13) {
if( (SiS_Pr->ChipType == SIS_630) &&
(SiS_Pr->ChipRevision >= 0x30)) {
if(VCLKIndex == 0x14) VCLKIndex = 0x34;
}
/* Better VGA2 clock for 1280x1024@75 */
if(VCLKIndex == 0x17) VCLKIndex = 0x45;
}
}
}
} else { /* If not programming CRT2 */
VCLKIndex = VCLKIndexGENCRT;
if(SiS_Pr->ChipType < SIS_315H) {
if(ModeNo > 0x13) {
if( (SiS_Pr->ChipType != SIS_630) &&
(SiS_Pr->ChipType != SIS_300) ) {
if(VCLKIndex == 0x1b) VCLKIndex = 0x48;
}
}
}
}
} else { /* LVDS */
VCLKIndex = CRT2Index;
if(SiS_Pr->SiS_SetFlag & ProgrammingCRT2) {
if( (SiS_Pr->SiS_IF_DEF_CH70xx != 0) && (SiS_Pr->SiS_VBInfo & SetCRT2ToTV) ) {
VCLKIndex &= 0x1f;
tempbx = 0;
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) tempbx += 1;
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
tempbx += 2;
if(SiS_Pr->SiS_ModeType > ModeVGA) {
if(SiS_Pr->SiS_CHSOverScan) tempbx = 8;
}
if(SiS_Pr->SiS_TVMode & TVSetPALM) {
tempbx = 4;
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) tempbx += 1;
} else if(SiS_Pr->SiS_TVMode & TVSetPALN) {
tempbx = 6;
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) tempbx += 1;
}
}
switch(tempbx) {
case 0: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKUNTSC; break;
case 1: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKONTSC; break;
case 2: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKUPAL; break;
case 3: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKOPAL; break;
case 4: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKUPALM; break;
case 5: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKOPALM; break;
case 6: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKUPALN; break;
case 7: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKOPALN; break;
case 8: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKSOPAL; break;
default: CHTVVCLKPtr = SiS_Pr->SiS_CHTVVCLKOPAL; break;
}
VCLKIndex = CHTVVCLKPtr[VCLKIndex];
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->ChipType < SIS_315H) {
VCLKIndex = SiS_Pr->PanelVCLKIdx300;
} else {
VCLKIndex = SiS_Pr->PanelVCLKIdx315;
}
#ifdef CONFIG_FB_SIS_300
/* Special Timing: Barco iQ Pro R series */
if(SiS_Pr->SiS_CustomT == CUT_BARCO1366) VCLKIndex = 0x44;
/* Special Timing: 848x480 and 856x480 parallel lvds panels */
if(SiS_Pr->SiS_CustomT == CUT_PANEL848 || SiS_Pr->SiS_CustomT == CUT_PANEL856) {
if(SiS_Pr->ChipType < SIS_315H) {
VCLKIndex = VCLK34_300;
/* if(resinfo == SIS_RI_1360x768) VCLKIndex = ?; */
} else {
VCLKIndex = VCLK34_315;
/* if(resinfo == SIS_RI_1360x768) VCLKIndex = ?; */
}
}
#endif
} else {
VCLKIndex = VCLKIndexGENCRT;
if(SiS_Pr->ChipType < SIS_315H) {
if(ModeNo > 0x13) {
if( (SiS_Pr->ChipType == SIS_630) &&
(SiS_Pr->ChipRevision >= 0x30) ) {
if(VCLKIndex == 0x14) VCLKIndex = 0x2e;
}
}
}
}
} else { /* if not programming CRT2 */
VCLKIndex = VCLKIndexGENCRT;
if(SiS_Pr->ChipType < SIS_315H) {
if(ModeNo > 0x13) {
if( (SiS_Pr->ChipType != SIS_630) &&
(SiS_Pr->ChipType != SIS_300) ) {
if(VCLKIndex == 0x1b) VCLKIndex = 0x48;
}
#if 0
if(SiS_Pr->ChipType == SIS_730) {
if(VCLKIndex == 0x0b) VCLKIndex = 0x40; /* 1024x768-70 */
if(VCLKIndex == 0x0d) VCLKIndex = 0x41; /* 1024x768-75 */
}
#endif
}
}
}
}
return VCLKIndex;
}
/*********************************************/
/* SET CRT2 MODE TYPE REGISTERS */
/*********************************************/
static void
SiS_SetCRT2ModeRegs(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short i, j, modeflag, tempah=0;
short tempcl;
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
unsigned short tempbl;
#endif
#ifdef CONFIG_FB_SIS_315
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short tempah2, tempbl2;
#endif
modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x00,0xAF,0x40);
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2E,0xF7);
} else {
for(i=0,j=4; i<3; i++,j++) SiS_SetReg(SiS_Pr->SiS_Part1Port,j,0);
if(SiS_Pr->ChipType >= SIS_315H) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x02,0x7F);
}
tempcl = SiS_Pr->SiS_ModeType;
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300 /* ---- 300 series ---- */
/* For 301BDH: (with LCD via LVDS) */
if(SiS_Pr->SiS_VBType & VB_NoLCD) {
tempbl = SiS_GetReg(SiS_Pr->SiS_P3c4,0x32);
tempbl &= 0xef;
tempbl |= 0x02;
if((SiS_Pr->SiS_VBInfo & SetCRT2ToTV) || (SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC)) {
tempbl |= 0x10;
tempbl &= 0xfd;
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x32,tempbl);
}
if(ModeNo > 0x13) {
tempcl -= ModeVGA;
if(tempcl >= 0) {
tempah = ((0x10 >> tempcl) | 0x80);
}
} else tempah = 0x80;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) tempah ^= 0xA0;
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* ------- 315/330 series ------ */
if(ModeNo > 0x13) {
tempcl -= ModeVGA;
if(tempcl >= 0) {
tempah = (0x08 >> tempcl);
if (tempah == 0) tempah = 1;
tempah |= 0x40;
}
} else tempah = 0x40;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) tempah ^= 0x50;
#endif /* CONFIG_FB_SIS_315 */
}
if(SiS_Pr->SiS_VBInfo & DisableCRT2Display) tempah = 0;
if(SiS_Pr->ChipType < SIS_315H) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x00,tempah);
} else {
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x00,0xa0,tempah);
} else if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(IS_SIS740) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x00,tempah);
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x00,0xa0,tempah);
}
}
#endif
}
if(SiS_Pr->SiS_VBType & VB_SISVB) {
tempah = 0x01;
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) {
tempah |= 0x02;
}
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC)) {
tempah ^= 0x05;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD)) {
tempah ^= 0x01;
}
}
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_VBInfo & DisableCRT2Display) tempah = 0;
tempah = (tempah << 5) & 0xFF;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x01,tempah);
tempah = (tempah >> 5) & 0xFF;
} else {
if(SiS_Pr->SiS_VBInfo & DisableCRT2Display) tempah = 0x08;
else if(!(SiS_IsDualEdge(SiS_Pr))) tempah |= 0x08;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2E,0xF0,tempah);
tempah &= ~0x08;
}
if((SiS_Pr->SiS_ModeType == ModeVGA) && (!(SiS_Pr->SiS_VBInfo & SetInSlaveMode))) {
tempah |= 0x10;
}
tempah |= 0x80;
if(SiS_Pr->SiS_VBType & VB_SIS301) {
if(SiS_Pr->PanelXRes < 1280 && SiS_Pr->PanelYRes < 960) tempah &= ~0x80;
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(!(SiS_Pr->SiS_TVMode & (TVSetYPbPr750p | TVSetYPbPr525p))) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
tempah |= 0x20;
}
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x0D,0x40,tempah);
tempah = 0x80;
if(SiS_Pr->SiS_VBType & VB_SIS301) {
if(SiS_Pr->PanelXRes < 1280 && SiS_Pr->PanelYRes < 960) tempah = 0;
}
if(SiS_IsDualLink(SiS_Pr)) tempah |= 0x40;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(SiS_Pr->SiS_TVMode & TVRPLLDIV2XO) {
tempah |= 0x40;
}
}
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0C,tempah);
} else { /* LVDS */
if(SiS_Pr->ChipType >= SIS_315H) {
#ifdef CONFIG_FB_SIS_315
/* LVDS can only be slave in 8bpp modes */
tempah = 0x80;
if((modeflag & CRT2Mode) && (SiS_Pr->SiS_ModeType > ModeVGA)) {
if(SiS_Pr->SiS_VBInfo & DriverMode) {
tempah |= 0x02;
}
}
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) tempah |= 0x02;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) tempah ^= 0x01;
if(SiS_Pr->SiS_VBInfo & DisableCRT2Display) tempah = 1;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2e,0xF0,tempah);
#endif
} else {
#ifdef CONFIG_FB_SIS_300
tempah = 0;
if( (!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) && (SiS_Pr->SiS_ModeType > ModeVGA) ) {
tempah |= 0x02;
}
tempah <<= 5;
if(SiS_Pr->SiS_VBInfo & DisableCRT2Display) tempah = 0;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x01,tempah);
#endif
}
}
} /* LCDA */
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->ChipType >= SIS_315H) {
#ifdef CONFIG_FB_SIS_315
/* unsigned char bridgerev = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x01); */
/* The following is nearly unpreditable and varies from machine
* to machine. Especially the 301DH seems to be a real trouble
* maker. Some BIOSes simply set the registers (like in the
* NoLCD-if-statements here), some set them according to the
* LCDA stuff. It is very likely that some machines are not
* treated correctly in the following, very case-orientated
* code. What do I do then...?
*/
/* 740 variants match for 30xB, 301B-DH, 30xLV */
if(!(IS_SIS740)) {
tempah = 0x04; /* For all bridges */
tempbl = 0xfb;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
tempah = 0x00;
if(SiS_IsDualEdge(SiS_Pr)) {
tempbl = 0xff;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,tempbl,tempah);
}
/* The following two are responsible for eventually wrong colors
* in TV output. The DH (VB_NoLCD) conditions are unknown; the
* b0 was found in some 651 machine (Pim; P4_23=0xe5); the b1 version
* in a 650 box (Jake). What is the criteria?
* Addendum: Another combination 651+301B-DH(b1) (Rapo) needs same
* treatment like the 651+301B-DH(b0) case. Seems more to be the
* chipset than the bridge revision.
*/
if((IS_SIS740) || (SiS_Pr->ChipType >= SIS_661) || (SiS_Pr->SiS_ROMNew)) {
tempah = 0x30;
tempbl = 0xc0;
if((SiS_Pr->SiS_VBInfo & DisableCRT2Display) ||
((SiS_Pr->SiS_ROMNew) && (!(ROMAddr[0x5b] & 0x04)))) {
tempah = 0x00;
tempbl = 0x00;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2c,0xcf,tempah);
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x21,0x3f,tempbl);
} else if(SiS_Pr->SiS_VBType & VB_SIS301) {
/* Fixes "TV-blue-bug" on 315+301 */
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2c,0xcf); /* For 301 */
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x21,0x3f);
} else if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2c,0x30); /* For 30xLV */
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x21,0xc0);
} else if(SiS_Pr->SiS_VBType & VB_NoLCD) { /* For 301B-DH */
tempah = 0x30; tempah2 = 0xc0;
tempbl = 0xcf; tempbl2 = 0x3f;
if(SiS_Pr->SiS_TVBlue == 0) {
tempah = tempah2 = 0x00;
} else if(SiS_Pr->SiS_TVBlue == -1) {
/* Set on 651/M650, clear on 315/650 */
if(!(IS_SIS65x)) /* (bridgerev != 0xb0) */ {
tempah = tempah2 = 0x00;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2c,tempbl,tempah);
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x21,tempbl2,tempah2);
} else {
tempah = 0x30; tempah2 = 0xc0; /* For 30xB, 301C */
tempbl = 0xcf; tempbl2 = 0x3f;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
tempah = tempah2 = 0x00;
if(SiS_IsDualEdge(SiS_Pr)) {
tempbl = tempbl2 = 0xff;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2c,tempbl,tempah);
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x21,tempbl2,tempah2);
}
if(IS_SIS740) {
tempah = 0x80;
if(SiS_Pr->SiS_VBInfo & DisableCRT2Display) tempah = 0x00;
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x23,0x7f,tempah);
} else {
tempah = 0x00;
tempbl = 0x7f;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
tempbl = 0xff;
if(!(SiS_IsDualEdge(SiS_Pr))) tempah = 0x80;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x23,tempbl,tempah);
}
#endif /* CONFIG_FB_SIS_315 */
} else if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
#ifdef CONFIG_FB_SIS_300
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x21,0x3f);
if((SiS_Pr->SiS_VBInfo & DisableCRT2Display) ||
((SiS_Pr->SiS_VBType & VB_NoLCD) &&
(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD))) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x23,0x7F);
} else {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x23,0x80);
}
#endif
}
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x0D,0x80);
if(SiS_Pr->SiS_VBType & VB_SIS30xCLV) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x3A,0xC0);
}
}
} else { /* LVDS */
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
tempah = 0x04;
tempbl = 0xfb;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
tempah = 0x00;
if(SiS_IsDualEdge(SiS_Pr)) tempbl = 0xff;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,tempbl,tempah);
if(SiS_Pr->SiS_VBInfo & DisableCRT2Display) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xfb);
}
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2c,0x30);
} else if(SiS_Pr->ChipType == SIS_550) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xfb);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2c,0x30);
}
}
#endif
}
}
/*********************************************/
/* GET RESOLUTION DATA */
/*********************************************/
unsigned short
SiS_GetResInfo(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
if(ModeNo <= 0x13)
return ((unsigned short)SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ResInfo);
else
return ((unsigned short)SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO);
}
static void
SiS_GetCRT2ResInfo(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short xres, yres, modeflag=0, resindex;
if(SiS_Pr->UseCustomMode) {
xres = SiS_Pr->CHDisplay;
if(SiS_Pr->CModeFlag & HalfDCLK) xres <<= 1;
SiS_Pr->SiS_VGAHDE = SiS_Pr->SiS_HDE = xres;
/* DoubleScanMode-check done in CheckCalcCustomMode()! */
SiS_Pr->SiS_VGAVDE = SiS_Pr->SiS_VDE = SiS_Pr->CVDisplay;
return;
}
resindex = SiS_GetResInfo(SiS_Pr,ModeNo,ModeIdIndex);
if(ModeNo <= 0x13) {
xres = SiS_Pr->SiS_StResInfo[resindex].HTotal;
yres = SiS_Pr->SiS_StResInfo[resindex].VTotal;
} else {
xres = SiS_Pr->SiS_ModeResInfo[resindex].HTotal;
yres = SiS_Pr->SiS_ModeResInfo[resindex].VTotal;
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
if(!SiS_Pr->SiS_IF_DEF_DSTN && !SiS_Pr->SiS_IF_DEF_FSTN) {
if((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->SiS_IF_DEF_LVDS == 1)) {
if((ModeNo != 0x03) && (SiS_Pr->SiS_SetFlag & SetDOSMode)) {
if(yres == 350) yres = 400;
}
if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x3a) & 0x01) {
if(ModeNo == 0x12) yres = 400;
}
}
if(modeflag & HalfDCLK) xres <<= 1;
if(modeflag & DoubleScanMode) yres <<= 1;
}
if((SiS_Pr->SiS_VBType & VB_SISVB) && (!(SiS_Pr->SiS_VBType & VB_NoLCD))) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_1024x768:
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) {
if(!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) {
if(yres == 350) yres = 357;
if(yres == 400) yres = 420;
if(yres == 480) yres = 525;
}
}
break;
case Panel_1280x1024:
if(!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) {
/* BIOS bug - does this regardless of scaling */
if(yres == 400) yres = 405;
}
if(yres == 350) yres = 360;
if(SiS_Pr->SiS_SetFlag & LCDVESATiming) {
if(yres == 360) yres = 375;
}
break;
case Panel_1600x1200:
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) {
if(yres == 1024) yres = 1056;
}
break;
}
}
} else {
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToHiVision)) {
if(xres == 720) xres = 640;
}
} else if(xres == 720) xres = 640;
if(SiS_Pr->SiS_SetFlag & SetDOSMode) {
yres = 400;
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x17) & 0x80) yres = 480;
} else {
if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x13) & 0x80) yres = 480;
}
if(SiS_Pr->SiS_IF_DEF_DSTN || SiS_Pr->SiS_IF_DEF_FSTN) yres = 480;
}
}
SiS_Pr->SiS_VGAHDE = SiS_Pr->SiS_HDE = xres;
SiS_Pr->SiS_VGAVDE = SiS_Pr->SiS_VDE = yres;
}
/*********************************************/
/* GET CRT2 TIMING DATA */
/*********************************************/
static void
SiS_GetCRT2Ptr(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex, unsigned short *CRT2Index,
unsigned short *ResIndex)
{
unsigned short tempbx=0, tempal=0, resinfo=0;
if(ModeNo <= 0x13) {
tempal = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else {
tempal = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
if((SiS_Pr->SiS_VBType & VB_SISVB) && (SiS_Pr->SiS_IF_DEF_LVDS == 0)) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) { /* LCD */
tempbx = SiS_Pr->SiS_LCDResInfo;
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) tempbx += 32;
/* patch index */
if(SiS_Pr->SiS_LCDResInfo == Panel_1680x1050) {
if (resinfo == SIS_RI_1280x800) tempal = 9;
else if(resinfo == SIS_RI_1400x1050) tempal = 11;
} else if((SiS_Pr->SiS_LCDResInfo == Panel_1280x800) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1280x800_2) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1280x854)) {
if (resinfo == SIS_RI_1280x768) tempal = 9;
}
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
/* Pass 1:1 only (center-screen handled outside) */
/* This is never called for the panel's native resolution */
/* since Pass1:1 will not be set in this case */
tempbx = 100;
if(ModeNo >= 0x13) {
tempal = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC_NS;
}
}
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->SiS_CustomT == CUT_COMPAQ1280) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) {
if(!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) {
tempbx = 200;
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) tempbx++;
}
}
}
#endif
} else { /* TV */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
/* if(SiS_Pr->SiS_VGAVDE > 480) SiS_Pr->SiS_TVMode &= (~TVSetTVSimuMode); */
tempbx = 2;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
tempbx = 13;
if(!(SiS_Pr->SiS_TVMode & TVSetTVSimuMode)) tempbx = 14;
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) tempbx = 7;
else if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) tempbx = 6;
else tempbx = 5;
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) tempbx += 5;
} else {
if(SiS_Pr->SiS_TVMode & TVSetPAL) tempbx = 3;
else tempbx = 4;
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) tempbx += 5;
}
}
tempal &= 0x3F;
if(ModeNo > 0x13) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTVNoHiVision) {
switch(resinfo) {
case SIS_RI_720x480:
tempal = 6;
if(SiS_Pr->SiS_TVMode & (TVSetPAL | TVSetPALN)) tempal = 9;
break;
case SIS_RI_720x576:
case SIS_RI_768x576:
case SIS_RI_1024x576: /* Not in NTSC or YPBPR mode (except 1080i)! */
tempal = 6;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) tempal = 8;
}
break;
case SIS_RI_800x480:
tempal = 4;
break;
case SIS_RI_512x384:
case SIS_RI_1024x768:
tempal = 7;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) tempal = 8;
}
break;
case SIS_RI_1280x720:
if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) tempal = 9;
}
break;
}
}
}
*CRT2Index = tempbx;
*ResIndex = tempal;
} else { /* LVDS, 301B-DH (if running on LCD) */
tempbx = 0;
if((SiS_Pr->SiS_IF_DEF_CH70xx) && (SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) {
tempbx = 90;
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
tempbx = 92;
if(SiS_Pr->SiS_ModeType > ModeVGA) {
if(SiS_Pr->SiS_CHSOverScan) tempbx = 99;
}
if(SiS_Pr->SiS_TVMode & TVSetPALM) tempbx = 94;
else if(SiS_Pr->SiS_TVMode & TVSetPALN) tempbx = 96;
}
if(tempbx != 99) {
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) tempbx++;
}
} else {
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_640x480: tempbx = 12; break;
case Panel_320x240_1: tempbx = 10; break;
case Panel_320x240_2:
case Panel_320x240_3: tempbx = 14; break;
case Panel_800x600: tempbx = 16; break;
case Panel_1024x600: tempbx = 18; break;
case Panel_1152x768:
case Panel_1024x768: tempbx = 20; break;
case Panel_1280x768: tempbx = 22; break;
case Panel_1280x1024: tempbx = 24; break;
case Panel_1400x1050: tempbx = 26; break;
case Panel_1600x1200: tempbx = 28; break;
#ifdef CONFIG_FB_SIS_300
case Panel_Barco1366: tempbx = 80; break;
#endif
}
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_320x240_1:
case Panel_320x240_2:
case Panel_320x240_3:
case Panel_640x480:
break;
default:
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) tempbx++;
}
if(SiS_Pr->SiS_LCDInfo & LCDPass11) tempbx = 30;
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->SiS_CustomT == CUT_BARCO1024) {
tempbx = 82;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) tempbx++;
} else if(SiS_Pr->SiS_CustomT == CUT_PANEL848 || SiS_Pr->SiS_CustomT == CUT_PANEL856) {
tempbx = 84;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) tempbx++;
}
#endif
}
(*CRT2Index) = tempbx;
(*ResIndex) = tempal & 0x1F;
}
}
static void
SiS_GetRAMDAC2DATA(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short tempax=0, tempbx=0, index, dotclock;
unsigned short temp1=0, modeflag=0, tempcx=0;
SiS_Pr->SiS_RVBHCMAX = 1;
SiS_Pr->SiS_RVBHCFACT = 1;
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
index = SiS_GetModePtr(SiS_Pr,ModeNo,ModeIdIndex);
tempax = SiS_Pr->SiS_StandTable[index].CRTC[0];
tempbx = SiS_Pr->SiS_StandTable[index].CRTC[6];
temp1 = SiS_Pr->SiS_StandTable[index].CRTC[7];
dotclock = (modeflag & Charx8Dot) ? 8 : 9;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
index = SiS_GetRefCRT1CRTC(SiS_Pr, RefreshRateTableIndex, SiS_Pr->SiS_UseWideCRT2);
tempax = SiS_Pr->SiS_CRT1Table[index].CR[0];
tempax |= (SiS_Pr->SiS_CRT1Table[index].CR[14] << 8);
tempax &= 0x03FF;
tempbx = SiS_Pr->SiS_CRT1Table[index].CR[6];
tempcx = SiS_Pr->SiS_CRT1Table[index].CR[13] << 8;
tempcx &= 0x0100;
tempcx <<= 2;
tempbx |= tempcx;
temp1 = SiS_Pr->SiS_CRT1Table[index].CR[7];
dotclock = 8;
}
if(temp1 & 0x01) tempbx |= 0x0100;
if(temp1 & 0x20) tempbx |= 0x0200;
tempax += 5;
tempax *= dotclock;
if(modeflag & HalfDCLK) tempax <<= 1;
tempbx++;
SiS_Pr->SiS_VGAHT = SiS_Pr->SiS_HT = tempax;
SiS_Pr->SiS_VGAVT = SiS_Pr->SiS_VT = tempbx;
}
static void
SiS_CalcPanelLinkTiming(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, unsigned short RefreshRateTableIndex)
{
unsigned short ResIndex;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
if(SiS_Pr->SiS_LCDInfo & LCDPass11) {
if(SiS_Pr->UseCustomMode) {
ResIndex = SiS_Pr->CHTotal;
if(SiS_Pr->CModeFlag & HalfDCLK) ResIndex <<= 1;
SiS_Pr->SiS_VGAHT = SiS_Pr->SiS_HT = ResIndex;
SiS_Pr->SiS_VGAVT = SiS_Pr->SiS_VT = SiS_Pr->CVTotal;
} else {
if(ModeNo < 0x13) {
ResIndex = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else {
ResIndex = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC_NS;
}
if(ResIndex == 0x09) {
if(SiS_Pr->Alternate1600x1200) ResIndex = 0x20; /* 1600x1200 LCDA */
else if(SiS_Pr->SiS_IF_DEF_LVDS == 1) ResIndex = 0x21; /* 1600x1200 LVDS */
}
SiS_Pr->SiS_VGAHT = SiS_Pr->SiS_NoScaleData[ResIndex].VGAHT;
SiS_Pr->SiS_VGAVT = SiS_Pr->SiS_NoScaleData[ResIndex].VGAVT;
SiS_Pr->SiS_HT = SiS_Pr->SiS_NoScaleData[ResIndex].LCDHT;
SiS_Pr->SiS_VT = SiS_Pr->SiS_NoScaleData[ResIndex].LCDVT;
}
} else {
SiS_Pr->SiS_VGAHT = SiS_Pr->SiS_HT = SiS_Pr->PanelHT;
SiS_Pr->SiS_VGAVT = SiS_Pr->SiS_VT = SiS_Pr->PanelVT;
}
} else {
/* This handles custom modes and custom panels */
SiS_Pr->SiS_HDE = SiS_Pr->PanelXRes;
SiS_Pr->SiS_VDE = SiS_Pr->PanelYRes;
SiS_Pr->SiS_HT = SiS_Pr->PanelHT;
SiS_Pr->SiS_VT = SiS_Pr->PanelVT;
SiS_Pr->SiS_VGAHT = SiS_Pr->PanelHT - (SiS_Pr->PanelXRes - SiS_Pr->SiS_VGAHDE);
SiS_Pr->SiS_VGAVT = SiS_Pr->PanelVT - (SiS_Pr->PanelYRes - SiS_Pr->SiS_VGAVDE);
}
}
static void
SiS_GetCRT2DataLVDS(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short CRT2Index, ResIndex, backup;
const struct SiS_LVDSData *LVDSData = NULL;
SiS_GetCRT2ResInfo(SiS_Pr, ModeNo, ModeIdIndex);
if(SiS_Pr->SiS_VBType & VB_SISVB) {
SiS_Pr->SiS_RVBHCMAX = 1;
SiS_Pr->SiS_RVBHCFACT = 1;
SiS_Pr->SiS_NewFlickerMode = 0;
SiS_Pr->SiS_RVBHRS = 50;
SiS_Pr->SiS_RY1COE = 0;
SiS_Pr->SiS_RY2COE = 0;
SiS_Pr->SiS_RY3COE = 0;
SiS_Pr->SiS_RY4COE = 0;
SiS_Pr->SiS_RVBHRS2 = 0;
}
if((SiS_Pr->SiS_VBType & VB_SISVB) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
#ifdef CONFIG_FB_SIS_315
SiS_CalcPanelLinkTiming(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
SiS_CalcLCDACRT1Timing(SiS_Pr, ModeNo, ModeIdIndex);
#endif
} else {
/* 301BDH needs LVDS Data */
backup = SiS_Pr->SiS_IF_DEF_LVDS;
if((SiS_Pr->SiS_VBType & VB_NoLCD) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD)) {
SiS_Pr->SiS_IF_DEF_LVDS = 1;
}
SiS_GetCRT2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex,
&CRT2Index, &ResIndex);
SiS_Pr->SiS_IF_DEF_LVDS = backup;
switch(CRT2Index) {
case 10: LVDSData = SiS_Pr->SiS_LVDS320x240Data_1; break;
case 14: LVDSData = SiS_Pr->SiS_LVDS320x240Data_2; break;
case 12: LVDSData = SiS_Pr->SiS_LVDS640x480Data_1; break;
case 16: LVDSData = SiS_Pr->SiS_LVDS800x600Data_1; break;
case 18: LVDSData = SiS_Pr->SiS_LVDS1024x600Data_1; break;
case 20: LVDSData = SiS_Pr->SiS_LVDS1024x768Data_1; break;
#ifdef CONFIG_FB_SIS_300
case 80: LVDSData = SiS_Pr->SiS_LVDSBARCO1366Data_1; break;
case 81: LVDSData = SiS_Pr->SiS_LVDSBARCO1366Data_2; break;
case 82: LVDSData = SiS_Pr->SiS_LVDSBARCO1024Data_1; break;
case 84: LVDSData = SiS_Pr->SiS_LVDS848x480Data_1; break;
case 85: LVDSData = SiS_Pr->SiS_LVDS848x480Data_2; break;
#endif
case 90: LVDSData = SiS_Pr->SiS_CHTVUNTSCData; break;
case 91: LVDSData = SiS_Pr->SiS_CHTVONTSCData; break;
case 92: LVDSData = SiS_Pr->SiS_CHTVUPALData; break;
case 93: LVDSData = SiS_Pr->SiS_CHTVOPALData; break;
case 94: LVDSData = SiS_Pr->SiS_CHTVUPALMData; break;
case 95: LVDSData = SiS_Pr->SiS_CHTVOPALMData; break;
case 96: LVDSData = SiS_Pr->SiS_CHTVUPALNData; break;
case 97: LVDSData = SiS_Pr->SiS_CHTVOPALNData; break;
case 99: LVDSData = SiS_Pr->SiS_CHTVSOPALData; break;
}
if(LVDSData) {
SiS_Pr->SiS_VGAHT = (LVDSData+ResIndex)->VGAHT;
SiS_Pr->SiS_VGAVT = (LVDSData+ResIndex)->VGAVT;
SiS_Pr->SiS_HT = (LVDSData+ResIndex)->LCDHT;
SiS_Pr->SiS_VT = (LVDSData+ResIndex)->LCDVT;
} else {
SiS_CalcPanelLinkTiming(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
if( (!(SiS_Pr->SiS_VBType & VB_SISVB)) &&
(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) &&
(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) ) {
if( (!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) ||
(SiS_Pr->SiS_SetFlag & SetDOSMode) ) {
SiS_Pr->SiS_HDE = SiS_Pr->PanelXRes;
SiS_Pr->SiS_VDE = SiS_Pr->PanelYRes;
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->SiS_CustomT == CUT_BARCO1366) {
if(ResIndex < 0x08) {
SiS_Pr->SiS_HDE = 1280;
SiS_Pr->SiS_VDE = 1024;
}
}
#endif
}
}
}
}
static void
SiS_GetCRT2Data301(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned char *ROMAddr = NULL;
unsigned short tempax, tempbx, modeflag, romptr=0;
unsigned short resinfo, CRT2Index, ResIndex;
const struct SiS_LCDData *LCDPtr = NULL;
const struct SiS_TVData *TVPtr = NULL;
#ifdef CONFIG_FB_SIS_315
short resinfo661;
#endif
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
resinfo = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ResInfo;
} else if(SiS_Pr->UseCustomMode) {
modeflag = SiS_Pr->CModeFlag;
resinfo = 0;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
#ifdef CONFIG_FB_SIS_315
resinfo661 = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].ROMMODEIDX661;
if( (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) &&
(SiS_Pr->SiS_SetFlag & LCDVESATiming) &&
(resinfo661 >= 0) &&
(SiS_Pr->SiS_NeedRomModeData) ) {
if((ROMAddr = GetLCDStructPtr661(SiS_Pr))) {
if((romptr = (SISGETROMW(21)))) {
romptr += (resinfo661 * 10);
ROMAddr = SiS_Pr->VirtualRomBase;
}
}
}
#endif
}
SiS_Pr->SiS_NewFlickerMode = 0;
SiS_Pr->SiS_RVBHRS = 50;
SiS_Pr->SiS_RY1COE = 0;
SiS_Pr->SiS_RY2COE = 0;
SiS_Pr->SiS_RY3COE = 0;
SiS_Pr->SiS_RY4COE = 0;
SiS_Pr->SiS_RVBHRS2 = 0;
SiS_GetCRT2ResInfo(SiS_Pr,ModeNo,ModeIdIndex);
if(SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC) {
if(SiS_Pr->UseCustomMode) {
SiS_Pr->SiS_RVBHCMAX = 1;
SiS_Pr->SiS_RVBHCFACT = 1;
SiS_Pr->SiS_HDE = SiS_Pr->SiS_VGAHDE;
SiS_Pr->SiS_VDE = SiS_Pr->SiS_VGAVDE;
tempax = SiS_Pr->CHTotal;
if(modeflag & HalfDCLK) tempax <<= 1;
SiS_Pr->SiS_VGAHT = SiS_Pr->SiS_HT = tempax;
SiS_Pr->SiS_VGAVT = SiS_Pr->SiS_VT = SiS_Pr->CVTotal;
} else {
SiS_GetRAMDAC2DATA(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
SiS_GetCRT2Ptr(SiS_Pr,ModeNo,ModeIdIndex,RefreshRateTableIndex,
&CRT2Index,&ResIndex);
switch(CRT2Index) {
case 2: TVPtr = SiS_Pr->SiS_ExtHiTVData; break;
case 3: TVPtr = SiS_Pr->SiS_ExtPALData; break;
case 4: TVPtr = SiS_Pr->SiS_ExtNTSCData; break;
case 5: TVPtr = SiS_Pr->SiS_Ext525iData; break;
case 6: TVPtr = SiS_Pr->SiS_Ext525pData; break;
case 7: TVPtr = SiS_Pr->SiS_Ext750pData; break;
case 8: TVPtr = SiS_Pr->SiS_StPALData; break;
case 9: TVPtr = SiS_Pr->SiS_StNTSCData; break;
case 10: TVPtr = SiS_Pr->SiS_St525iData; break;
case 11: TVPtr = SiS_Pr->SiS_St525pData; break;
case 12: TVPtr = SiS_Pr->SiS_St750pData; break;
case 13: TVPtr = SiS_Pr->SiS_St1HiTVData; break;
case 14: TVPtr = SiS_Pr->SiS_St2HiTVData; break;
default: TVPtr = SiS_Pr->SiS_StPALData; break;
}
SiS_Pr->SiS_RVBHCMAX = (TVPtr+ResIndex)->RVBHCMAX;
SiS_Pr->SiS_RVBHCFACT = (TVPtr+ResIndex)->RVBHCFACT;
SiS_Pr->SiS_VGAHT = (TVPtr+ResIndex)->VGAHT;
SiS_Pr->SiS_VGAVT = (TVPtr+ResIndex)->VGAVT;
SiS_Pr->SiS_HDE = (TVPtr+ResIndex)->TVHDE;
SiS_Pr->SiS_VDE = (TVPtr+ResIndex)->TVVDE;
SiS_Pr->SiS_RVBHRS2 = (TVPtr+ResIndex)->RVBHRS2 & 0x0fff;
if(modeflag & HalfDCLK) {
SiS_Pr->SiS_RVBHRS = (TVPtr+ResIndex)->HALFRVBHRS;
if(SiS_Pr->SiS_RVBHRS2) {
SiS_Pr->SiS_RVBHRS2 = ((SiS_Pr->SiS_RVBHRS2 + 3) >> 1) - 3;
tempax = ((TVPtr+ResIndex)->RVBHRS2 >> 12) & 0x07;
if((TVPtr+ResIndex)->RVBHRS2 & 0x8000) SiS_Pr->SiS_RVBHRS2 -= tempax;
else SiS_Pr->SiS_RVBHRS2 += tempax;
}
} else {
SiS_Pr->SiS_RVBHRS = (TVPtr+ResIndex)->RVBHRS;
}
SiS_Pr->SiS_NewFlickerMode = ((TVPtr+ResIndex)->FlickerMode) << 7;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
if((resinfo == SIS_RI_960x600) ||
(resinfo == SIS_RI_1024x768) ||
(resinfo == SIS_RI_1280x1024) ||
(resinfo == SIS_RI_1280x720)) {
SiS_Pr->SiS_NewFlickerMode = 0x40;
}
if(SiS_Pr->SiS_VGAVDE == 350) SiS_Pr->SiS_TVMode |= TVSetTVSimuMode;
SiS_Pr->SiS_HT = ExtHiTVHT;
SiS_Pr->SiS_VT = ExtHiTVVT;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) {
SiS_Pr->SiS_HT = StHiTVHT;
SiS_Pr->SiS_VT = StHiTVVT;
}
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) {
SiS_Pr->SiS_HT = 1650;
SiS_Pr->SiS_VT = 750;
} else if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) {
SiS_Pr->SiS_HT = NTSCHT;
if(SiS_Pr->SiS_TVMode & TVSet525p1024) SiS_Pr->SiS_HT = NTSC2HT;
SiS_Pr->SiS_VT = NTSCVT;
} else {
SiS_Pr->SiS_HT = NTSCHT;
if(SiS_Pr->SiS_TVMode & TVSetNTSC1024) SiS_Pr->SiS_HT = NTSC2HT;
SiS_Pr->SiS_VT = NTSCVT;
}
} else {
SiS_Pr->SiS_RY1COE = (TVPtr+ResIndex)->RY1COE;
SiS_Pr->SiS_RY2COE = (TVPtr+ResIndex)->RY2COE;
SiS_Pr->SiS_RY3COE = (TVPtr+ResIndex)->RY3COE;
SiS_Pr->SiS_RY4COE = (TVPtr+ResIndex)->RY4COE;
if(modeflag & HalfDCLK) {
SiS_Pr->SiS_RY1COE = 0x00;
SiS_Pr->SiS_RY2COE = 0xf4;
SiS_Pr->SiS_RY3COE = 0x10;
SiS_Pr->SiS_RY4COE = 0x38;
}
if(!(SiS_Pr->SiS_TVMode & TVSetPAL)) {
SiS_Pr->SiS_HT = NTSCHT;
if(SiS_Pr->SiS_TVMode & TVSetNTSC1024) SiS_Pr->SiS_HT = NTSC2HT;
SiS_Pr->SiS_VT = NTSCVT;
} else {
SiS_Pr->SiS_HT = PALHT;
SiS_Pr->SiS_VT = PALVT;
}
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
SiS_Pr->SiS_RVBHCMAX = 1;
SiS_Pr->SiS_RVBHCFACT = 1;
if(SiS_Pr->UseCustomMode) {
SiS_Pr->SiS_HDE = SiS_Pr->SiS_VGAHDE;
SiS_Pr->SiS_VDE = SiS_Pr->SiS_VGAVDE;
tempax = SiS_Pr->CHTotal;
if(modeflag & HalfDCLK) tempax <<= 1;
SiS_Pr->SiS_VGAHT = SiS_Pr->SiS_HT = tempax;
SiS_Pr->SiS_VGAVT = SiS_Pr->SiS_VT = SiS_Pr->CVTotal;
} else {
bool gotit = false;
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (!(SiS_Pr->SiS_LCDInfo & LCDPass11))) {
SiS_Pr->SiS_VGAHT = SiS_Pr->PanelHT;
SiS_Pr->SiS_VGAVT = SiS_Pr->PanelVT;
SiS_Pr->SiS_HT = SiS_Pr->PanelHT;
SiS_Pr->SiS_VT = SiS_Pr->PanelVT;
gotit = true;
} else if( (!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) && (romptr) && (ROMAddr) ) {
#ifdef CONFIG_FB_SIS_315
SiS_Pr->SiS_RVBHCMAX = ROMAddr[romptr];
SiS_Pr->SiS_RVBHCFACT = ROMAddr[romptr+1];
SiS_Pr->SiS_VGAHT = ROMAddr[romptr+2] | ((ROMAddr[romptr+3] & 0x0f) << 8);
SiS_Pr->SiS_VGAVT = (ROMAddr[romptr+4] << 4) | ((ROMAddr[romptr+3] & 0xf0) >> 4);
SiS_Pr->SiS_HT = ROMAddr[romptr+5] | ((ROMAddr[romptr+6] & 0x0f) << 8);
SiS_Pr->SiS_VT = (ROMAddr[romptr+7] << 4) | ((ROMAddr[romptr+6] & 0xf0) >> 4);
SiS_Pr->SiS_RVBHRS2 = ROMAddr[romptr+8] | ((ROMAddr[romptr+9] & 0x0f) << 8);
if((SiS_Pr->SiS_RVBHRS2) && (modeflag & HalfDCLK)) {
SiS_Pr->SiS_RVBHRS2 = ((SiS_Pr->SiS_RVBHRS2 + 3) >> 1) - 3;
tempax = (ROMAddr[romptr+9] >> 4) & 0x07;
if(ROMAddr[romptr+9] & 0x80) SiS_Pr->SiS_RVBHRS2 -= tempax;
else SiS_Pr->SiS_RVBHRS2 += tempax;
}
if(SiS_Pr->SiS_VGAHT) gotit = true;
else {
SiS_Pr->SiS_LCDInfo |= DontExpandLCD;
SiS_Pr->SiS_LCDInfo &= ~LCDPass11;
SiS_Pr->SiS_RVBHCMAX = 1;
SiS_Pr->SiS_RVBHCFACT = 1;
SiS_Pr->SiS_VGAHT = SiS_Pr->PanelHT;
SiS_Pr->SiS_VGAVT = SiS_Pr->PanelVT;
SiS_Pr->SiS_HT = SiS_Pr->PanelHT;
SiS_Pr->SiS_VT = SiS_Pr->PanelVT;
SiS_Pr->SiS_RVBHRS2 = 0;
gotit = true;
}
#endif
}
if(!gotit) {
SiS_GetCRT2Ptr(SiS_Pr,ModeNo,ModeIdIndex,RefreshRateTableIndex,
&CRT2Index,&ResIndex);
switch(CRT2Index) {
case Panel_1024x768 : LCDPtr = SiS_Pr->SiS_ExtLCD1024x768Data; break;
case Panel_1024x768 + 32: LCDPtr = SiS_Pr->SiS_St2LCD1024x768Data; break;
case Panel_1280x720 :
case Panel_1280x720 + 32: LCDPtr = SiS_Pr->SiS_LCD1280x720Data; break;
case Panel_1280x768_2 : LCDPtr = SiS_Pr->SiS_ExtLCD1280x768_2Data; break;
case Panel_1280x768_2+ 32: LCDPtr = SiS_Pr->SiS_StLCD1280x768_2Data; break;
case Panel_1280x800 :
case Panel_1280x800 + 32: LCDPtr = SiS_Pr->SiS_LCD1280x800Data; break;
case Panel_1280x800_2 :
case Panel_1280x800_2+ 32: LCDPtr = SiS_Pr->SiS_LCD1280x800_2Data; break;
case Panel_1280x854 :
case Panel_1280x854 + 32: LCDPtr = SiS_Pr->SiS_LCD1280x854Data; break;
case Panel_1280x960 :
case Panel_1280x960 + 32: LCDPtr = SiS_Pr->SiS_LCD1280x960Data; break;
case Panel_1280x1024 : LCDPtr = SiS_Pr->SiS_ExtLCD1280x1024Data; break;
case Panel_1280x1024 + 32: LCDPtr = SiS_Pr->SiS_St2LCD1280x1024Data; break;
case Panel_1400x1050 : LCDPtr = SiS_Pr->SiS_ExtLCD1400x1050Data; break;
case Panel_1400x1050 + 32: LCDPtr = SiS_Pr->SiS_StLCD1400x1050Data; break;
case Panel_1600x1200 : LCDPtr = SiS_Pr->SiS_ExtLCD1600x1200Data; break;
case Panel_1600x1200 + 32: LCDPtr = SiS_Pr->SiS_StLCD1600x1200Data; break;
case Panel_1680x1050 :
case Panel_1680x1050 + 32: LCDPtr = SiS_Pr->SiS_LCD1680x1050Data; break;
case 100 : LCDPtr = SiS_Pr->SiS_NoScaleData; break;
#ifdef CONFIG_FB_SIS_315
case 200 : LCDPtr = SiS310_ExtCompaq1280x1024Data; break;
case 201 : LCDPtr = SiS_Pr->SiS_St2LCD1280x1024Data; break;
#endif
default : LCDPtr = SiS_Pr->SiS_ExtLCD1024x768Data; break;
}
SiS_Pr->SiS_RVBHCMAX = (LCDPtr+ResIndex)->RVBHCMAX;
SiS_Pr->SiS_RVBHCFACT = (LCDPtr+ResIndex)->RVBHCFACT;
SiS_Pr->SiS_VGAHT = (LCDPtr+ResIndex)->VGAHT;
SiS_Pr->SiS_VGAVT = (LCDPtr+ResIndex)->VGAVT;
SiS_Pr->SiS_HT = (LCDPtr+ResIndex)->LCDHT;
SiS_Pr->SiS_VT = (LCDPtr+ResIndex)->LCDVT;
}
tempax = SiS_Pr->PanelXRes;
tempbx = SiS_Pr->PanelYRes;
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_1024x768:
if(SiS_Pr->SiS_SetFlag & LCDVESATiming) {
if(SiS_Pr->ChipType < SIS_315H) {
if (SiS_Pr->SiS_VGAVDE == 350) tempbx = 560;
else if(SiS_Pr->SiS_VGAVDE == 400) tempbx = 640;
}
} else {
if (SiS_Pr->SiS_VGAVDE == 357) tempbx = 527;
else if(SiS_Pr->SiS_VGAVDE == 420) tempbx = 620;
else if(SiS_Pr->SiS_VGAVDE == 525) tempbx = 775;
else if(SiS_Pr->SiS_VGAVDE == 600) tempbx = 775;
else if(SiS_Pr->SiS_VGAVDE == 350) tempbx = 560;
else if(SiS_Pr->SiS_VGAVDE == 400) tempbx = 640;
}
break;
case Panel_1280x960:
if (SiS_Pr->SiS_VGAVDE == 350) tempbx = 700;
else if(SiS_Pr->SiS_VGAVDE == 400) tempbx = 800;
else if(SiS_Pr->SiS_VGAVDE == 1024) tempbx = 960;
break;
case Panel_1280x1024:
if (SiS_Pr->SiS_VGAVDE == 360) tempbx = 768;
else if(SiS_Pr->SiS_VGAVDE == 375) tempbx = 800;
else if(SiS_Pr->SiS_VGAVDE == 405) tempbx = 864;
break;
case Panel_1600x1200:
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) {
if (SiS_Pr->SiS_VGAVDE == 350) tempbx = 875;
else if(SiS_Pr->SiS_VGAVDE == 400) tempbx = 1000;
}
break;
}
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
tempax = SiS_Pr->SiS_VGAHDE;
tempbx = SiS_Pr->SiS_VGAVDE;
}
SiS_Pr->SiS_HDE = tempax;
SiS_Pr->SiS_VDE = tempbx;
}
}
}
static void
SiS_GetCRT2Data(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_GetCRT2DataLVDS(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
} else {
if((SiS_Pr->SiS_VBType & VB_NoLCD) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD)) {
/* Need LVDS Data for LCD on 301B-DH */
SiS_GetCRT2DataLVDS(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
} else {
SiS_GetCRT2Data301(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
}
} else {
SiS_GetCRT2DataLVDS(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
}
/*********************************************/
/* GET LVDS DES (SKEW) DATA */
/*********************************************/
static const struct SiS_LVDSDes *
SiS_GetLVDSDesPtr(struct SiS_Private *SiS_Pr)
{
const struct SiS_LVDSDes *PanelDesPtr = NULL;
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_LCDTypeInfo == 4) {
if(SiS_Pr->SiS_CustomT == CUT_BARCO1366) {
PanelDesPtr = SiS_Pr->SiS_PanelType04_1a;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
PanelDesPtr = SiS_Pr->SiS_PanelType04_2a;
}
} else if(SiS_Pr->SiS_CustomT == CUT_BARCO1024) {
PanelDesPtr = SiS_Pr->SiS_PanelType04_1b;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
PanelDesPtr = SiS_Pr->SiS_PanelType04_2b;
}
}
}
}
}
#endif
return PanelDesPtr;
}
static void
SiS_GetLVDSDesData(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short modeflag, ResIndex;
const struct SiS_LVDSDes *PanelDesPtr = NULL;
SiS_Pr->SiS_LCDHDES = 0;
SiS_Pr->SiS_LCDVDES = 0;
/* Some special cases */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
/* Trumpion */
if(SiS_Pr->SiS_IF_DEF_TRUMPION) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(SiS_Pr->SiS_VGAVDE == SiS_Pr->PanelYRes) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
}
}
return;
}
/* 640x480 on LVDS */
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_LCDResInfo == Panel_640x480 && SiS_Pr->SiS_LCDTypeInfo == 3) {
SiS_Pr->SiS_LCDHDES = 8;
if (SiS_Pr->SiS_VGAVDE >= 480) SiS_Pr->SiS_LCDVDES = 512;
else if(SiS_Pr->SiS_VGAVDE >= 400) SiS_Pr->SiS_LCDVDES = 436;
else if(SiS_Pr->SiS_VGAVDE >= 350) SiS_Pr->SiS_LCDVDES = 440;
return;
}
}
} /* LCD */
if( (SiS_Pr->UseCustomMode) ||
(SiS_Pr->SiS_LCDResInfo == Panel_Custom) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL848) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL856) ||
(SiS_Pr->SiS_LCDInfo & LCDPass11) ) {
return;
}
if(ModeNo <= 0x13) ResIndex = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
else ResIndex = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
if((SiS_Pr->SiS_VBType & VB_SIS30xBLV) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
/* non-pass 1:1 only, see above */
if(SiS_Pr->SiS_VGAHDE != SiS_Pr->PanelXRes) {
SiS_Pr->SiS_LCDHDES = SiS_Pr->SiS_HT - ((SiS_Pr->PanelXRes - SiS_Pr->SiS_VGAHDE) / 2);
}
if(SiS_Pr->SiS_VGAVDE != SiS_Pr->PanelYRes) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->SiS_VT - ((SiS_Pr->PanelYRes - SiS_Pr->SiS_VGAVDE) / 2);
}
}
if(SiS_Pr->SiS_VGAVDE == SiS_Pr->PanelYRes) {
switch(SiS_Pr->SiS_CustomT) {
case CUT_UNIWILL1024:
case CUT_UNIWILL10242:
case CUT_CLEVO1400:
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
}
break;
}
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_1280x1024:
if(SiS_Pr->SiS_CustomT != CUT_COMPAQ1280) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
}
break;
case Panel_1280x800: /* Verified for Averatec 6240 */
case Panel_1280x800_2: /* Verified for Asus A4L */
case Panel_1280x854: /* Not verified yet FIXME */
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
break;
}
}
#endif
} else {
if((SiS_Pr->SiS_IF_DEF_CH70xx != 0) && (SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) {
if((SiS_Pr->SiS_TVMode & TVSetPAL) && (!(SiS_Pr->SiS_TVMode & TVSetPALM))) {
if(ResIndex <= 3) SiS_Pr->SiS_LCDHDES = 256;
}
} else if((PanelDesPtr = SiS_GetLVDSDesPtr(SiS_Pr))) {
SiS_Pr->SiS_LCDHDES = (PanelDesPtr+ResIndex)->LCDHDES;
SiS_Pr->SiS_LCDVDES = (PanelDesPtr+ResIndex)->LCDVDES;
} else if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
if(SiS_Pr->SiS_VGAHDE != SiS_Pr->PanelXRes) {
SiS_Pr->SiS_LCDHDES = SiS_Pr->SiS_HT - ((SiS_Pr->PanelXRes - SiS_Pr->SiS_VGAHDE) / 2);
}
if(SiS_Pr->SiS_VGAVDE != SiS_Pr->PanelYRes) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->SiS_VT - ((SiS_Pr->PanelYRes - SiS_Pr->SiS_VGAVDE) / 2);
} else {
if(SiS_Pr->ChipType < SIS_315H) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
} else {
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_800x600:
case Panel_1024x768:
case Panel_1280x1024:
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT;
break;
case Panel_1400x1050:
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
break;
}
}
}
} else {
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_800x600:
if(SiS_Pr->SiS_VGAVDE == SiS_Pr->PanelYRes) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
} else {
SiS_Pr->SiS_LCDHDES = SiS_Pr->PanelHT + 3;
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT;
if(SiS_Pr->SiS_VGAVDE == 400) SiS_Pr->SiS_LCDVDES -= 2;
else SiS_Pr->SiS_LCDVDES -= 4;
}
break;
case Panel_1024x768:
if(SiS_Pr->SiS_VGAVDE == SiS_Pr->PanelYRes) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
} else {
SiS_Pr->SiS_LCDHDES = SiS_Pr->PanelHT - 1;
if(SiS_Pr->SiS_VGAVDE <= 400) SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 8;
if(SiS_Pr->SiS_VGAVDE <= 350) SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 12;
}
break;
case Panel_1024x600:
default:
if( (SiS_Pr->SiS_VGAHDE == SiS_Pr->PanelXRes) &&
(SiS_Pr->SiS_VGAVDE == SiS_Pr->PanelYRes) ) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
} else {
SiS_Pr->SiS_LCDHDES = SiS_Pr->PanelHT - 1;
}
break;
}
switch(SiS_Pr->SiS_LCDTypeInfo) {
case 1:
SiS_Pr->SiS_LCDHDES = SiS_Pr->SiS_LCDVDES = 0;
break;
case 3: /* 640x480 only? */
SiS_Pr->SiS_LCDHDES = 8;
if (SiS_Pr->SiS_VGAVDE >= 480) SiS_Pr->SiS_LCDVDES = 512;
else if(SiS_Pr->SiS_VGAVDE >= 400) SiS_Pr->SiS_LCDVDES = 436;
else if(SiS_Pr->SiS_VGAVDE >= 350) SiS_Pr->SiS_LCDVDES = 440;
break;
}
#endif
} else {
#ifdef CONFIG_FB_SIS_315
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_1024x768:
case Panel_1280x1024:
if(SiS_Pr->SiS_VGAVDE == SiS_Pr->PanelYRes) {
SiS_Pr->SiS_LCDVDES = SiS_Pr->PanelVT - 1;
}
break;
case Panel_320x240_1:
case Panel_320x240_2:
case Panel_320x240_3:
SiS_Pr->SiS_LCDVDES = 524;
break;
}
#endif
}
}
if((ModeNo <= 0x13) && (SiS_Pr->SiS_LCDInfo & DontExpandLCD)) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
if((SiS_Pr->SiS_VBType & VB_SIS30xBLV) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
if(!(modeflag & HalfDCLK)) SiS_Pr->SiS_LCDHDES = 632;
} else if(!(SiS_Pr->SiS_SetFlag & SetDOSMode)) {
if(SiS_Pr->SiS_LCDResInfo != Panel_1280x1024) {
if(SiS_Pr->SiS_LCDResInfo >= Panel_1024x768) {
if(SiS_Pr->ChipType < SIS_315H) {
if(!(modeflag & HalfDCLK)) SiS_Pr->SiS_LCDHDES = 320;
} else {
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) SiS_Pr->SiS_LCDHDES = 480;
if(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) SiS_Pr->SiS_LCDHDES = 804;
if(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) SiS_Pr->SiS_LCDHDES = 704;
if(!(modeflag & HalfDCLK)) {
SiS_Pr->SiS_LCDHDES = 320;
if(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) SiS_Pr->SiS_LCDHDES = 632;
if(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) SiS_Pr->SiS_LCDHDES = 542;
}
#endif
}
}
}
}
}
}
}
/*********************************************/
/* DISABLE VIDEO BRIDGE */
/*********************************************/
#ifdef CONFIG_FB_SIS_315
static int
SiS_HandlePWD(struct SiS_Private *SiS_Pr)
{
int ret = 0;
#ifdef SET_PWD
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romptr = GetLCDStructPtr661_2(SiS_Pr);
unsigned char drivermode = SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40;
unsigned short temp;
if( (SiS_Pr->SiS_VBType & VB_SISPWD) &&
(romptr) &&
(SiS_Pr->SiS_PWDOffset) ) {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x2b,ROMAddr[romptr + SiS_Pr->SiS_PWDOffset + 0]);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x2c,ROMAddr[romptr + SiS_Pr->SiS_PWDOffset + 1]);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x2d,ROMAddr[romptr + SiS_Pr->SiS_PWDOffset + 2]);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x2e,ROMAddr[romptr + SiS_Pr->SiS_PWDOffset + 3]);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x2f,ROMAddr[romptr + SiS_Pr->SiS_PWDOffset + 4]);
temp = 0x00;
if((ROMAddr[romptr + 2] & (0x06 << 1)) && !drivermode) {
temp = 0x80;
ret = 1;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x27,0x7f,temp);
}
#endif
return ret;
}
#endif
/* NEVER use any variables (VBInfo), this will be called
* from outside the context of modeswitch!
* MUST call getVBType before calling this
*/
void
SiS_DisableBridge(struct SiS_Private *SiS_Pr)
{
#ifdef CONFIG_FB_SIS_315
unsigned short tempah, pushax=0, modenum;
#endif
unsigned short temp=0;
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) { /* ===== For 30xB/C/LV ===== */
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300 /* 300 series */
if(!(SiS_CR36BIOSWord23b(SiS_Pr))) {
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x26,0xFE);
} else {
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x08);
}
SiS_PanelDelay(SiS_Pr, 3);
}
if(SiS_Is301B(SiS_Pr)) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x1f,0x3f);
SiS_ShortDelay(SiS_Pr,1);
}
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x00,0xDF);
SiS_DisplayOff(SiS_Pr);
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x32,0xDF);
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1E,0xDF);
SiS_UnLockCRT2(SiS_Pr);
if(!(SiS_Pr->SiS_VBType & VB_SISLVDS)) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x01,0x80);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x02,0x40);
}
if( (!(SiS_CRT2IsLCD(SiS_Pr))) ||
(!(SiS_CR36BIOSWord23d(SiS_Pr))) ) {
SiS_PanelDelay(SiS_Pr, 2);
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x26,0xFD);
} else {
SiS_SetRegSR11ANDOR(SiS_Pr,0xFB,0x04);
}
}
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* 315 series */
int didpwd = 0;
bool custom1 = (SiS_Pr->SiS_CustomT == CUT_COMPAQ1280) ||
(SiS_Pr->SiS_CustomT == CUT_CLEVO1400);
modenum = SiS_GetReg(SiS_Pr->SiS_P3d4,0x34) & 0x7f;
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
#ifdef SET_EMI
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
if(SiS_Pr->SiS_CustomT != CUT_CLEVO1400) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x30,0x0c);
}
}
#endif
didpwd = SiS_HandlePWD(SiS_Pr);
if( (modenum <= 0x13) ||
(SiS_IsVAMode(SiS_Pr)) ||
(!(SiS_IsDualEdge(SiS_Pr))) ) {
if(!didpwd) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x26,0xfe);
if(custom1) SiS_PanelDelay(SiS_Pr, 3);
} else {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x26,0xfc);
}
}
if(!custom1) {
SiS_DDC2Delay(SiS_Pr,0xff00);
SiS_DDC2Delay(SiS_Pr,0xe000);
SiS_SetRegByte(SiS_Pr->SiS_P3c6,0x00);
pushax = SiS_GetReg(SiS_Pr->SiS_P3c4,0x06);
if(IS_SIS740) {
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x06,0xE3);
}
SiS_PanelDelay(SiS_Pr, 3);
}
}
if(!(SiS_IsNotM650orLater(SiS_Pr))) {
/* if(SiS_Pr->ChipType < SIS_340) {*/
tempah = 0xef;
if(SiS_IsVAMode(SiS_Pr)) tempah = 0xf7;
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x4c,tempah);
/*}*/
}
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x1F,~0x10);
}
tempah = 0x3f;
if(SiS_IsDualEdge(SiS_Pr)) {
tempah = 0x7f;
if(!(SiS_IsVAMode(SiS_Pr))) tempah = 0xbf;
}
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x1F,tempah);
if((SiS_IsVAMode(SiS_Pr)) ||
((SiS_Pr->SiS_VBType & VB_SISLVDS) && (modenum <= 0x13))) {
SiS_DisplayOff(SiS_Pr);
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_PanelDelay(SiS_Pr, 2);
}
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x32,0xDF);
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x1E,0xDF);
}
if((!(SiS_IsVAMode(SiS_Pr))) ||
((SiS_Pr->SiS_VBType & VB_SISLVDS) && (modenum <= 0x13))) {
if(!(SiS_IsDualEdge(SiS_Pr))) {
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x00,0xdf);
SiS_DisplayOff(SiS_Pr);
}
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x00,0x80);
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_PanelDelay(SiS_Pr, 2);
}
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x32,0xDF);
temp = SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x00,0x10);
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1E,0xDF);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x00,temp);
}
if(SiS_IsNotM650orLater(SiS_Pr)) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2e,0x7f);
}
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
if( (!(SiS_IsVAMode(SiS_Pr))) &&
(!(SiS_CRT2IsLCD(SiS_Pr))) &&
(!(SiS_IsDualEdge(SiS_Pr))) ) {
if(custom1) SiS_PanelDelay(SiS_Pr, 2);
if(!didpwd) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x26,0xFD);
}
if(custom1) SiS_PanelDelay(SiS_Pr, 4);
}
if(!custom1) {
SiS_SetReg(SiS_Pr->SiS_P3c4,0x06,pushax);
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
if(SiS_IsVAorLCD(SiS_Pr)) {
SiS_PanelDelayLoop(SiS_Pr, 3, 20);
}
}
}
}
#endif /* CONFIG_FB_SIS_315 */
}
} else { /* ============ For 301 ================ */
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300
if(!(SiS_CR36BIOSWord23b(SiS_Pr))) {
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x08);
SiS_PanelDelay(SiS_Pr, 3);
}
#endif
}
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x00,0xDF); /* disable VB */
SiS_DisplayOff(SiS_Pr);
if(SiS_Pr->ChipType >= SIS_315H) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x00,0x80);
}
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x32,0xDF); /* disable lock mode */
if(SiS_Pr->ChipType >= SIS_315H) {
temp = SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x00,0x10);
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x20);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x00,temp);
} else {
#ifdef CONFIG_FB_SIS_300
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1E,0xDF); /* disable CRT2 */
if( (!(SiS_CRT2IsLCD(SiS_Pr))) ||
(!(SiS_CR36BIOSWord23d(SiS_Pr))) ) {
SiS_PanelDelay(SiS_Pr, 2);
SiS_SetRegSR11ANDOR(SiS_Pr,0xFB,0x04);
}
#endif
}
}
} else { /* ============ For LVDS =============*/
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300 /* 300 series */
if(SiS_Pr->SiS_IF_DEF_CH70xx == 1) {
SiS_SetCH700x(SiS_Pr,0x0E,0x09);
}
if(SiS_Pr->ChipType == SIS_730) {
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x11) & 0x08)) {
SiS_WaitVBRetrace(SiS_Pr);
}
if(!(SiS_CR36BIOSWord23b(SiS_Pr))) {
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x08);
SiS_PanelDelay(SiS_Pr, 3);
}
} else {
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x11) & 0x08)) {
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x13) & 0x40)) {
if(!(SiS_CR36BIOSWord23b(SiS_Pr))) {
SiS_WaitVBRetrace(SiS_Pr);
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x06) & 0x1c)) {
SiS_DisplayOff(SiS_Pr);
}
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x08);
SiS_PanelDelay(SiS_Pr, 3);
}
}
}
}
SiS_DisplayOff(SiS_Pr);
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x32,0xDF);
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1E,0xDF);
SiS_UnLockCRT2(SiS_Pr);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x01,0x80);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x02,0x40);
if( (!(SiS_CRT2IsLCD(SiS_Pr))) ||
(!(SiS_CR36BIOSWord23d(SiS_Pr))) ) {
SiS_PanelDelay(SiS_Pr, 2);
SiS_SetRegSR11ANDOR(SiS_Pr,0xFB,0x04);
}
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* 315 series */
if(!(SiS_IsNotM650orLater(SiS_Pr))) {
/*if(SiS_Pr->ChipType < SIS_340) { */ /* XGI needs this */
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x4c,~0x18);
/* } */
}
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_Pr->ChipType == SIS_740) {
temp = SiS_GetCH701x(SiS_Pr,0x61);
if(temp < 1) {
SiS_SetCH701x(SiS_Pr,0x76,0xac);
SiS_SetCH701x(SiS_Pr,0x66,0x00);
}
if( (!(SiS_IsDualEdge(SiS_Pr))) ||
(SiS_IsTVOrYPbPrOrScart(SiS_Pr)) ) {
SiS_SetCH701x(SiS_Pr,0x49,0x3e);
}
}
if( (!(SiS_IsDualEdge(SiS_Pr))) ||
(SiS_IsVAMode(SiS_Pr)) ) {
SiS_Chrontel701xBLOff(SiS_Pr);
SiS_Chrontel701xOff(SiS_Pr);
}
if(SiS_Pr->ChipType != SIS_740) {
if( (!(SiS_IsDualEdge(SiS_Pr))) ||
(SiS_IsTVOrYPbPrOrScart(SiS_Pr)) ) {
SiS_SetCH701x(SiS_Pr,0x49,0x01);
}
}
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 0) {
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x08);
SiS_PanelDelay(SiS_Pr, 3);
}
if( (SiS_Pr->SiS_IF_DEF_CH70xx == 0) ||
(!(SiS_IsDualEdge(SiS_Pr))) ||
(!(SiS_IsTVOrYPbPrOrScart(SiS_Pr))) ) {
SiS_DisplayOff(SiS_Pr);
}
if( (SiS_Pr->SiS_IF_DEF_CH70xx == 0) ||
(!(SiS_IsDualEdge(SiS_Pr))) ||
(!(SiS_IsVAMode(SiS_Pr))) ) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x00,0x80);
}
if(SiS_Pr->ChipType == SIS_740) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2e,0x7f);
}
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x32,0xDF);
if( (SiS_Pr->SiS_IF_DEF_CH70xx == 0) ||
(!(SiS_IsDualEdge(SiS_Pr))) ||
(!(SiS_IsVAMode(SiS_Pr))) ) {
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1E,0xDF);
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 0) {
if(SiS_CRT2IsLCD(SiS_Pr)) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x1e,0xdf);
if(SiS_Pr->ChipType == SIS_550) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x1e,0xbf);
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x1e,0xef);
}
}
} else {
if(SiS_Pr->ChipType == SIS_740) {
if(SiS_IsLCDOrLCDA(SiS_Pr)) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x1e,0xdf);
}
} else if(SiS_IsVAMode(SiS_Pr)) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x1e,0xdf);
}
}
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_IsDualEdge(SiS_Pr)) {
/* SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xff); */
} else {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xfb);
}
}
SiS_UnLockCRT2(SiS_Pr);
if(SiS_Pr->ChipType == SIS_550) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x01,0x80); /* DirectDVD PAL?*/
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x02,0x40); /* VB clock / 4 ? */
} else if( (SiS_Pr->SiS_IF_DEF_CH70xx == 0) ||
(!(SiS_IsDualEdge(SiS_Pr))) ||
(!(SiS_IsVAMode(SiS_Pr))) ) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2e,0xf7);
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 0) {
if(SiS_CRT2IsLCD(SiS_Pr)) {
if(!(SiS_WeHaveBacklightCtrl(SiS_Pr))) {
SiS_PanelDelay(SiS_Pr, 2);
SiS_SetRegSR11ANDOR(SiS_Pr,0xFB,0x04);
}
}
}
#endif /* CONFIG_FB_SIS_315 */
} /* 315 series */
} /* LVDS */
}
/*********************************************/
/* ENABLE VIDEO BRIDGE */
/*********************************************/
/* NEVER use any variables (VBInfo), this will be called
* from outside the context of a mode switch!
* MUST call getVBType before calling this
*/
static
void
SiS_EnableBridge(struct SiS_Private *SiS_Pr)
{
unsigned short temp=0, tempah;
#ifdef CONFIG_FB_SIS_315
unsigned short temp1, pushax=0;
bool delaylong = false;
#endif
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) { /* ====== For 301B et al ====== */
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300 /* 300 series */
if(SiS_CRT2IsLCD(SiS_Pr)) {
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x26,0x02);
} else if(SiS_Pr->SiS_VBType & VB_NoLCD) {
SiS_SetRegSR11ANDOR(SiS_Pr,0xFB,0x00);
}
if(SiS_Pr->SiS_VBType & (VB_SISLVDS | VB_NoLCD)) {
if(!(SiS_CR36BIOSWord23d(SiS_Pr))) {
SiS_PanelDelay(SiS_Pr, 0);
}
}
}
if((SiS_Pr->SiS_VBType & VB_NoLCD) &&
(SiS_CRT2IsLCD(SiS_Pr))) {
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x20); /* Enable CRT2 */
SiS_DisplayOn(SiS_Pr);
SiS_UnLockCRT2(SiS_Pr);
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x02,0xBF);
if(SiS_BridgeInSlavemode(SiS_Pr)) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x01,0x1F);
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x01,0x1F,0x40);
}
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x13) & 0x40)) {
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) & 0x10)) {
if(!(SiS_CR36BIOSWord23b(SiS_Pr))) {
SiS_PanelDelay(SiS_Pr, 1);
}
SiS_WaitVBRetrace(SiS_Pr);
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x00);
}
}
} else {
temp = SiS_GetReg(SiS_Pr->SiS_P3c4,0x32) & 0xDF; /* lock mode */
if(SiS_BridgeInSlavemode(SiS_Pr)) {
tempah = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
if(!(tempah & SetCRT2ToRAMDAC)) temp |= 0x20;
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x32,temp);
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x20);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x00,0x1F,0x20); /* enable VB processor */
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x1F,0xC0);
SiS_DisplayOn(SiS_Pr);
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
if(SiS_CRT2IsLCD(SiS_Pr)) {
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) & 0x10)) {
if(!(SiS_CR36BIOSWord23b(SiS_Pr))) {
SiS_PanelDelay(SiS_Pr, 1);
}
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x26,0x01);
}
}
}
}
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* 315 series */
#ifdef SET_EMI
unsigned char r30=0, r31=0, r32=0, r33=0, cr36=0;
int didpwd = 0;
/* unsigned short emidelay=0; */
#endif
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x1f,0xef);
#ifdef SET_EMI
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x30,0x0c);
}
#endif
}
if(!(SiS_IsNotM650orLater(SiS_Pr))) {
/*if(SiS_Pr->ChipType < SIS_340) { */
tempah = 0x10;
if(SiS_LCDAEnabled(SiS_Pr)) {
if(SiS_TVEnabled(SiS_Pr)) tempah = 0x18;
else tempah = 0x08;
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x4c,tempah);
/*}*/
}
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_SetRegByte(SiS_Pr->SiS_P3c6,0x00);
SiS_DisplayOff(SiS_Pr);
pushax = SiS_GetReg(SiS_Pr->SiS_P3c4,0x06);
if(IS_SIS740) {
SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x06,0xE3);
}
didpwd = SiS_HandlePWD(SiS_Pr);
if(SiS_IsVAorLCD(SiS_Pr)) {
if(!didpwd) {
if(!(SiS_GetReg(SiS_Pr->SiS_Part4Port,0x26) & 0x02)) {
SiS_PanelDelayLoop(SiS_Pr, 3, 2);
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x26,0x02);
SiS_PanelDelayLoop(SiS_Pr, 3, 2);
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
SiS_GenericDelay(SiS_Pr, 17664);
}
}
} else {
SiS_PanelDelayLoop(SiS_Pr, 3, 2);
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
SiS_GenericDelay(SiS_Pr, 17664);
}
}
}
if(!(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40)) {
SiS_PanelDelayLoop(SiS_Pr, 3, 10);
delaylong = true;
}
}
if(!(SiS_IsVAMode(SiS_Pr))) {
temp = SiS_GetReg(SiS_Pr->SiS_P3c4,0x32) & 0xDF;
if(SiS_BridgeInSlavemode(SiS_Pr)) {
tempah = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
if(!(tempah & SetCRT2ToRAMDAC)) {
if(!(SiS_LCDAEnabled(SiS_Pr))) temp |= 0x20;
}
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x32,temp);
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x20); /* enable CRT2 */
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2e,0x7f);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2e,0x80);
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_PanelDelay(SiS_Pr, 2);
}
} else {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1e,0x20);
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x00,0x1f,0x20);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2e,0x80);
if(SiS_Pr->SiS_VBType & VB_SISPOWER) {
if( (SiS_LCDAEnabled(SiS_Pr)) ||
(SiS_CRT2IsLCD(SiS_Pr)) ) {
/* Enable "LVDS PLL power on" (even on 301C) */
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x2a,0x7f);
/* Enable "LVDS Driver Power on" (even on 301C) */
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x30,0x7f);
}
}
tempah = 0xc0;
if(SiS_IsDualEdge(SiS_Pr)) {
tempah = 0x80;
if(!(SiS_IsVAMode(SiS_Pr))) tempah = 0x40;
}
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x1F,tempah);
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
SiS_PanelDelay(SiS_Pr, 2);
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x1f,0x10);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2e,0x80);
if(SiS_Pr->SiS_CustomT != CUT_CLEVO1400) {
#ifdef SET_EMI
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x30,0x0c);
SiS_GenericDelay(SiS_Pr, 2048);
}
#endif
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x27,0x0c);
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
#ifdef SET_EMI
cr36 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36);
if(SiS_Pr->SiS_ROMNew) {
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romptr = GetLCDStructPtr661_2(SiS_Pr);
if(romptr) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x30,0x20); /* Reset */
SiS_Pr->EMI_30 = 0;
SiS_Pr->EMI_31 = ROMAddr[romptr + SiS_Pr->SiS_EMIOffset + 0];
SiS_Pr->EMI_32 = ROMAddr[romptr + SiS_Pr->SiS_EMIOffset + 1];
SiS_Pr->EMI_33 = ROMAddr[romptr + SiS_Pr->SiS_EMIOffset + 2];
if(ROMAddr[romptr + 1] & 0x10) SiS_Pr->EMI_30 = 0x40;
/* emidelay = SISGETROMW((romptr + 0x22)); */
SiS_Pr->HaveEMI = SiS_Pr->HaveEMILCD = SiS_Pr->OverruleEMI = true;
}
}
/* (P4_30|0x40) */
/* Compal 1400x1050: 0x05, 0x60, 0x00 YES (1.10.7w; CR36=69) */
/* Compal 1400x1050: 0x0d, 0x70, 0x40 YES (1.10.7x; CR36=69) */
/* Acer 1280x1024: 0x12, 0xd0, 0x6b NO (1.10.9k; CR36=73) */
/* Compaq 1280x1024: 0x0d, 0x70, 0x6b YES (1.12.04b; CR36=03) */
/* Clevo 1024x768: 0x05, 0x60, 0x33 NO (1.10.8e; CR36=12, DL!) */
/* Clevo 1024x768: 0x0d, 0x70, 0x40 (if type == 3) YES (1.10.8y; CR36=?2) */
/* Clevo 1024x768: 0x05, 0x60, 0x33 (if type != 3) YES (1.10.8y; CR36=?2) */
/* Asus 1024x768: ? ? (1.10.8o; CR36=?2) */
/* Asus 1024x768: 0x08, 0x10, 0x3c (problematic) YES (1.10.8q; CR36=22) */
if(SiS_Pr->HaveEMI) {
r30 = SiS_Pr->EMI_30; r31 = SiS_Pr->EMI_31;
r32 = SiS_Pr->EMI_32; r33 = SiS_Pr->EMI_33;
} else {
r30 = 0;
}
/* EMI_30 is read at driver start; however, the BIOS sets this
* (if it is used) only if the LCD is in use. In case we caught
* the machine while on TV output, this bit is not set and we
* don't know if it should be set - hence our detection is wrong.
* Work-around this here:
*/
if((!SiS_Pr->HaveEMI) || (!SiS_Pr->HaveEMILCD)) {
switch((cr36 & 0x0f)) {
case 2:
r30 |= 0x40;
if(SiS_Pr->SiS_CustomT == CUT_CLEVO1024) r30 &= ~0x40;
if(!SiS_Pr->HaveEMI) {
r31 = 0x05; r32 = 0x60; r33 = 0x33;
if((cr36 & 0xf0) == 0x30) {
r31 = 0x0d; r32 = 0x70; r33 = 0x40;
}
}
break;
case 3: /* 1280x1024 */
if(SiS_Pr->SiS_CustomT == CUT_COMPAQ1280) r30 |= 0x40;
if(!SiS_Pr->HaveEMI) {
r31 = 0x12; r32 = 0xd0; r33 = 0x6b;
if(SiS_Pr->SiS_CustomT == CUT_COMPAQ1280) {
r31 = 0x0d; r32 = 0x70; r33 = 0x6b;
}
}
break;
case 9: /* 1400x1050 */
r30 |= 0x40;
if(!SiS_Pr->HaveEMI) {
r31 = 0x05; r32 = 0x60; r33 = 0x00;
if(SiS_Pr->SiS_CustomT == CUT_COMPAL1400_2) {
r31 = 0x0d; r32 = 0x70; r33 = 0x40; /* BIOS values */
}
}
break;
case 11: /* 1600x1200 - unknown */
r30 |= 0x40;
if(!SiS_Pr->HaveEMI) {
r31 = 0x05; r32 = 0x60; r33 = 0x00;
}
}
}
/* BIOS values don't work so well sometimes */
if(!SiS_Pr->OverruleEMI) {
#ifdef COMPAL_HACK
if(SiS_Pr->SiS_CustomT == CUT_COMPAL1400_2) {
if((cr36 & 0x0f) == 0x09) {
r30 = 0x60; r31 = 0x05; r32 = 0x60; r33 = 0x00;
}
}
#endif
#ifdef COMPAQ_HACK
if(SiS_Pr->SiS_CustomT == CUT_COMPAQ1280) {
if((cr36 & 0x0f) == 0x03) {
r30 = 0x20; r31 = 0x12; r32 = 0xd0; r33 = 0x6b;
}
}
#endif
#ifdef ASUS_HACK
if(SiS_Pr->SiS_CustomT == CUT_ASUSA2H_2) {
if((cr36 & 0x0f) == 0x02) {
/* r30 = 0x60; r31 = 0x05; r32 = 0x60; r33 = 0x33; */ /* rev 2 */
/* r30 = 0x20; r31 = 0x05; r32 = 0x60; r33 = 0x33; */ /* rev 3 */
/* r30 = 0x60; r31 = 0x0d; r32 = 0x70; r33 = 0x40; */ /* rev 4 */
/* r30 = 0x20; r31 = 0x0d; r32 = 0x70; r33 = 0x40; */ /* rev 5 */
}
}
#endif
}
if(!(SiS_Pr->OverruleEMI && (!r30) && (!r31) && (!r32) && (!r33))) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x30,0x20); /* Reset */
SiS_GenericDelay(SiS_Pr, 2048);
}
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x31,r31);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x32,r32);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x33,r33);
#endif /* SET_EMI */
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x34,0x10);
#ifdef SET_EMI
if( (SiS_LCDAEnabled(SiS_Pr)) ||
(SiS_CRT2IsLCD(SiS_Pr)) ) {
if(r30 & 0x40) {
/*SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x2a,0x80);*/
SiS_PanelDelayLoop(SiS_Pr, 3, 5);
if(delaylong) {
SiS_PanelDelayLoop(SiS_Pr, 3, 5);
delaylong = false;
}
SiS_WaitVBRetrace(SiS_Pr);
SiS_WaitVBRetrace(SiS_Pr);
if(SiS_Pr->SiS_CustomT == CUT_ASUSA2H_2) {
SiS_GenericDelay(SiS_Pr, 1280);
}
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x30,0x40); /* Enable */
/*SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x2a,0x7f);*/
}
}
#endif
}
}
if(!(SiS_WeHaveBacklightCtrl(SiS_Pr))) {
if(SiS_IsVAorLCD(SiS_Pr)) {
SiS_PanelDelayLoop(SiS_Pr, 3, 10);
if(delaylong) {
SiS_PanelDelayLoop(SiS_Pr, 3, 10);
}
SiS_WaitVBRetrace(SiS_Pr);
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
SiS_GenericDelay(SiS_Pr, 2048);
SiS_WaitVBRetrace(SiS_Pr);
}
if(!didpwd) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x26,0x01);
} else {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x26,0x03);
}
}
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x06,pushax);
SiS_DisplayOn(SiS_Pr);
SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xff);
}
if(!(SiS_WeHaveBacklightCtrl(SiS_Pr))) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x00,0x7f);
}
#endif /* CONFIG_FB_SIS_315 */
}
} else { /* ============ For 301 ================ */
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_CRT2IsLCD(SiS_Pr)) {
SiS_SetRegSR11ANDOR(SiS_Pr,0xFB,0x00);
SiS_PanelDelay(SiS_Pr, 0);
}
}
temp = SiS_GetReg(SiS_Pr->SiS_P3c4,0x32) & 0xDF; /* lock mode */
if(SiS_BridgeInSlavemode(SiS_Pr)) {
tempah = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
if(!(tempah & SetCRT2ToRAMDAC)) temp |= 0x20;
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x32,temp);
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x20); /* enable CRT2 */
if(SiS_Pr->ChipType >= SIS_315H) {
temp = SiS_GetReg(SiS_Pr->SiS_Part1Port,0x2E);
if(!(temp & 0x80)) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2E,0x80); /* BVBDOENABLE=1 */
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x00,0x1F,0x20); /* enable VB processor */
SiS_VBLongWait(SiS_Pr);
SiS_DisplayOn(SiS_Pr);
if(SiS_Pr->ChipType >= SIS_315H) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x00,0x7f);
}
SiS_VBLongWait(SiS_Pr);
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_CRT2IsLCD(SiS_Pr)) {
SiS_PanelDelay(SiS_Pr, 1);
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x00);
}
}
}
} else { /* =================== For LVDS ================== */
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300 /* 300 series */
if(SiS_CRT2IsLCD(SiS_Pr)) {
if(SiS_Pr->ChipType == SIS_730) {
SiS_PanelDelay(SiS_Pr, 1);
SiS_PanelDelay(SiS_Pr, 1);
SiS_PanelDelay(SiS_Pr, 1);
}
SiS_SetRegSR11ANDOR(SiS_Pr,0xFB,0x00);
if(!(SiS_CR36BIOSWord23d(SiS_Pr))) {
SiS_PanelDelay(SiS_Pr, 0);
}
}
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x20);
SiS_DisplayOn(SiS_Pr);
SiS_UnLockCRT2(SiS_Pr);
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x02,0xBF);
if(SiS_BridgeInSlavemode(SiS_Pr)) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x01,0x1F);
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x01,0x1F,0x40);
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 1) {
if(!(SiS_CRT2IsLCD(SiS_Pr))) {
SiS_WaitVBRetrace(SiS_Pr);
SiS_SetCH700x(SiS_Pr,0x0E,0x0B);
}
}
if(SiS_CRT2IsLCD(SiS_Pr)) {
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x13) & 0x40)) {
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) & 0x10)) {
if(!(SiS_CR36BIOSWord23b(SiS_Pr))) {
SiS_PanelDelay(SiS_Pr, 1);
SiS_PanelDelay(SiS_Pr, 1);
}
SiS_WaitVBRetrace(SiS_Pr);
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x00);
}
}
}
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* 315 series */
if(!(SiS_IsNotM650orLater(SiS_Pr))) {
/*if(SiS_Pr->ChipType < SIS_340) {*/ /* XGI needs this */
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x4c,0x18);
/*}*/
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 0) {
if(SiS_CRT2IsLCD(SiS_Pr)) {
SiS_SetRegSR11ANDOR(SiS_Pr,0xFB,0x00);
SiS_PanelDelay(SiS_Pr, 0);
}
}
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x20);
SiS_UnLockCRT2(SiS_Pr);
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2e,0xf7);
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
temp = SiS_GetCH701x(SiS_Pr,0x66);
temp &= 0x20;
SiS_Chrontel701xBLOff(SiS_Pr);
}
if(SiS_Pr->ChipType != SIS_550) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2e,0x7f);
}
if(SiS_Pr->ChipType == SIS_740) {
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
if(SiS_IsLCDOrLCDA(SiS_Pr)) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1E,0x20);
}
}
}
temp1 = SiS_GetReg(SiS_Pr->SiS_Part1Port,0x2E);
if(!(temp1 & 0x80)) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2E,0x80);
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
if(temp) {
SiS_Chrontel701xBLOn(SiS_Pr);
}
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 0) {
if(SiS_CRT2IsLCD(SiS_Pr)) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1E,0x20);
if(SiS_Pr->ChipType == SIS_550) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1E,0x40);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1E,0x10);
}
}
} else if(SiS_IsVAMode(SiS_Pr)) {
if(SiS_Pr->ChipType != SIS_740) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1E,0x20);
}
}
if(!(SiS_WeHaveBacklightCtrl(SiS_Pr))) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x00,0x7f);
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
if(SiS_IsTVOrYPbPrOrScart(SiS_Pr)) {
SiS_Chrontel701xOn(SiS_Pr);
}
if( (SiS_IsVAMode(SiS_Pr)) ||
(SiS_IsLCDOrLCDA(SiS_Pr)) ) {
SiS_ChrontelDoSomething1(SiS_Pr);
}
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
if(!(SiS_WeHaveBacklightCtrl(SiS_Pr))) {
if( (SiS_IsVAMode(SiS_Pr)) ||
(SiS_IsLCDOrLCDA(SiS_Pr)) ) {
SiS_Chrontel701xBLOn(SiS_Pr);
SiS_ChrontelInitTVVSync(SiS_Pr);
}
}
} else if(SiS_Pr->SiS_IF_DEF_CH70xx == 0) {
if(!(SiS_WeHaveBacklightCtrl(SiS_Pr))) {
if(SiS_CRT2IsLCD(SiS_Pr)) {
SiS_PanelDelay(SiS_Pr, 1);
SiS_SetRegSR11ANDOR(SiS_Pr,0xF7,0x00);
}
}
}
#endif /* CONFIG_FB_SIS_315 */
} /* 310 series */
} /* LVDS */
}
/*********************************************/
/* SET PART 1 REGISTER GROUP */
/*********************************************/
/* Set CRT2 OFFSET / PITCH */
static void
SiS_SetCRT2Offset(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RRTI)
{
unsigned short offset;
unsigned char temp;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) return;
offset = SiS_GetOffset(SiS_Pr,ModeNo,ModeIdIndex,RRTI);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x07,(offset & 0xFF));
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x09,(offset >> 8));
temp = (unsigned char)(((offset >> 3) & 0xFF) + 1);
if(offset & 0x07) temp++;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x03,temp);
}
/* Set CRT2 sync and PanelLink mode */
static void
SiS_SetCRT2Sync(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short RefreshRateTableIndex)
{
unsigned short tempah=0, tempbl, infoflag;
tempbl = 0xC0;
if(SiS_Pr->UseCustomMode) {
infoflag = SiS_Pr->CInfoFlag;
} else {
infoflag = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_InfoFlag;
}
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) { /* LVDS */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
tempah = 0;
} else if((SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) && (SiS_Pr->SiS_LCDInfo & LCDSync)) {
tempah = SiS_Pr->SiS_LCDInfo;
} else tempah = infoflag >> 8;
tempah &= 0xC0;
tempah |= 0x20;
if(!(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit)) tempah |= 0x10;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if((SiS_Pr->SiS_CustomT == CUT_BARCO1366) ||
(SiS_Pr->SiS_CustomT == CUT_BARCO1024)) {
tempah |= 0xf0;
}
if( (SiS_Pr->SiS_IF_DEF_FSTN) ||
(SiS_Pr->SiS_IF_DEF_DSTN) ||
(SiS_Pr->SiS_IF_DEF_TRUMPION) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL848) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL856) ) {
tempah |= 0x30;
}
if( (SiS_Pr->SiS_IF_DEF_FSTN) ||
(SiS_Pr->SiS_IF_DEF_DSTN) ) {
tempah &= ~0xc0;
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(SiS_Pr->ChipType >= SIS_315H) {
tempah >>= 3;
tempah &= 0x18;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,0xE7,tempah);
/* Don't care about 12/18/24 bit mode - TV is via VGA, not PL */
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x19,0x0F,0xe0);
}
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x19,0x0F,tempah);
}
} else if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300 /* ---- 300 series --- */
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) { /* 630 - 301B(-DH) */
tempah = infoflag >> 8;
tempbl = 0;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->SiS_LCDInfo & LCDSync) {
tempah = SiS_Pr->SiS_LCDInfo;
tempbl = (tempah >> 6) & 0x03;
}
}
tempah &= 0xC0;
tempah |= 0x20;
if(!(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit)) tempah |= 0x10;
tempah |= 0xc0;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x19,0x0F,tempah);
if((SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) && (!(SiS_Pr->SiS_VBType & VB_NoLCD))) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1a,0xf0,tempbl);
}
} else { /* 630 - 301 */
tempah = ((infoflag >> 8) & 0xc0) | 0x20;
if(!(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit)) tempah |= 0x10;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x19,0x0F,tempah);
}
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* ------- 315 series ------ */
if(SiS_Pr->SiS_VBType & VB_SISLVDS) { /* 315 - LVDS */
tempbl = 0;
if((SiS_Pr->SiS_CustomT == CUT_COMPAQ1280) &&
(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024)) {
tempah = infoflag >> 8;
if(SiS_Pr->SiS_LCDInfo & LCDSync) {
tempbl = ((SiS_Pr->SiS_LCDInfo & 0xc0) >> 6);
}
} else if((SiS_Pr->SiS_CustomT == CUT_CLEVO1400) &&
(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050)) {
tempah = infoflag >> 8;
tempbl = 0x03;
} else {
tempah = SiS_GetReg(SiS_Pr->SiS_P3d4,0x37);
tempbl = (tempah >> 6) & 0x03;
tempbl |= 0x08;
if(!(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit)) tempbl |= 0x04;
}
tempah &= 0xC0;
tempah |= 0x20;
if(!(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit)) tempah |= 0x10;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) tempah |= 0xc0;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x19,0x0F,tempah);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1a,0xf0,tempbl);
}
}
} else { /* 315 - TMDS */
tempah = tempbl = infoflag >> 8;
if(!SiS_Pr->UseCustomMode) {
tempbl = 0;
if((SiS_Pr->SiS_VBType & VB_SIS30xC) && (SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC)) {
if(ModeNo <= 0x13) {
tempah = SiS_GetRegByte((SiS_Pr->SiS_P3ca+0x02));
}
}
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
if(SiS_Pr->SiS_LCDInfo & LCDSync) {
tempah = SiS_Pr->SiS_LCDInfo;
tempbl = (tempah >> 6) & 0x03;
}
}
}
}
tempah &= 0xC0;
tempah |= 0x20;
if(!(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit)) tempah |= 0x10;
if(SiS_Pr->SiS_VBType & VB_NoLCD) {
/* Imitate BIOS bug */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) tempah |= 0xc0;
}
if((SiS_Pr->SiS_VBType & VB_SIS30xC) && (SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC)) {
tempah >>= 3;
tempah &= 0x18;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,0xe7,tempah);
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x19,0x0F,tempah);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1a,0xf0,tempbl);
}
}
}
}
#endif /* CONFIG_FB_SIS_315 */
}
}
}
/* Set CRT2 FIFO on 300/540/630/730 */
#ifdef CONFIG_FB_SIS_300
static void
SiS_SetCRT2FIFO_300(struct SiS_Private *SiS_Pr,unsigned short ModeNo)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short temp, index, modeidindex, refreshratetableindex;
unsigned short VCLK = 0, MCLK, colorth = 0, data2 = 0;
unsigned short tempbx, tempcl, CRT1ModeNo, CRT2ModeNo, SelectRate_backup;
unsigned int data, pci50, pciA0;
static const unsigned char colortharray[] = {
1, 1, 2, 2, 3, 4
};
SelectRate_backup = SiS_Pr->SiS_SelectCRT2Rate;
if(!SiS_Pr->CRT1UsesCustomMode) {
CRT1ModeNo = SiS_Pr->SiS_CRT1Mode; /* get CRT1 ModeNo */
SiS_SearchModeID(SiS_Pr, &CRT1ModeNo, &modeidindex);
SiS_Pr->SiS_SetFlag &= (~ProgrammingCRT2);
SiS_Pr->SiS_SelectCRT2Rate = 0;
refreshratetableindex = SiS_GetRatePtr(SiS_Pr, CRT1ModeNo, modeidindex);
if(CRT1ModeNo >= 0x13) {
/* Get VCLK */
index = SiS_GetRefCRTVCLK(SiS_Pr, refreshratetableindex, SiS_Pr->SiS_UseWide);
VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK;
/* Get colordepth */
colorth = SiS_GetColorDepth(SiS_Pr,CRT1ModeNo,modeidindex) >> 1;
if(!colorth) colorth++;
}
} else {
CRT1ModeNo = 0xfe;
/* Get VCLK */
VCLK = SiS_Pr->CSRClock_CRT1;
/* Get color depth */
colorth = colortharray[((SiS_Pr->CModeFlag_CRT1 & ModeTypeMask) - 2)];
}
if(CRT1ModeNo >= 0x13) {
/* Get MCLK */
if(SiS_Pr->ChipType == SIS_300) {
index = SiS_GetReg(SiS_Pr->SiS_P3c4,0x3A);
} else {
index = SiS_GetReg(SiS_Pr->SiS_P3c4,0x1A);
}
index &= 0x07;
MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK;
temp = ((SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) >> 6) & 0x03) << 1;
if(!temp) temp++;
temp <<= 2;
data2 = temp - ((colorth * VCLK) / MCLK);
temp = (28 * 16) % data2;
data2 = (28 * 16) / data2;
if(temp) data2++;
if(SiS_Pr->ChipType == SIS_300) {
SiS_GetFIFOThresholdIndex300(SiS_Pr, &tempbx, &tempcl);
data = SiS_GetFIFOThresholdB300(tempbx, tempcl);
} else {
pci50 = sisfb_read_nbridge_pci_dword(SiS_Pr, 0x50);
pciA0 = sisfb_read_nbridge_pci_dword(SiS_Pr, 0xa0);
if(SiS_Pr->ChipType == SIS_730) {
index = (unsigned short)(((pciA0 >> 28) & 0x0f) * 3);
index += (unsigned short)(((pci50 >> 9)) & 0x03);
/* BIOS BUG (2.04.5d, 2.04.6a use ah here, which is unset!) */
index = 0; /* -- do it like the BIOS anyway... */
} else {
pci50 >>= 24;
pciA0 >>= 24;
index = (pci50 >> 1) & 0x07;
if(pci50 & 0x01) index += 6;
if(!(pciA0 & 0x01)) index += 24;
if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) & 0x80) index += 12;
}
data = SiS_GetLatencyFactor630(SiS_Pr, index) + 15;
if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) & 0x80)) data += 5;
}
data += data2; /* CRT1 Request Period */
SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
SiS_Pr->SiS_SelectCRT2Rate = SelectRate_backup;
if(!SiS_Pr->UseCustomMode) {
CRT2ModeNo = ModeNo;
SiS_SearchModeID(SiS_Pr, &CRT2ModeNo, &modeidindex);
refreshratetableindex = SiS_GetRatePtr(SiS_Pr, CRT2ModeNo, modeidindex);
/* Get VCLK */
index = SiS_GetVCLK2Ptr(SiS_Pr, CRT2ModeNo, modeidindex, refreshratetableindex);
VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK;
if((SiS_Pr->SiS_CustomT == CUT_BARCO1366) || (SiS_Pr->SiS_CustomT == CUT_BARCO1024)) {
if(SiS_Pr->SiS_UseROM) {
if(ROMAddr[0x220] & 0x01) {
VCLK = ROMAddr[0x229] | (ROMAddr[0x22a] << 8);
}
}
}
} else {
/* Get VCLK */
CRT2ModeNo = 0xfe;
VCLK = SiS_Pr->CSRClock;
}
/* Get colordepth */
colorth = SiS_GetColorDepth(SiS_Pr,CRT2ModeNo,modeidindex) >> 1;
if(!colorth) colorth++;
data = data * VCLK * colorth;
temp = data % (MCLK << 4);
data = data / (MCLK << 4);
if(temp) data++;
if(data < 6) data = 6;
else if(data > 0x14) data = 0x14;
if(SiS_Pr->ChipType == SIS_300) {
temp = 0x16;
if((data <= 0x0f) || (SiS_Pr->SiS_LCDResInfo == Panel_1280x1024))
temp = 0x13;
} else {
temp = 0x16;
if(( (SiS_Pr->ChipType == SIS_630) ||
(SiS_Pr->ChipType == SIS_730) ) &&
(SiS_Pr->ChipRevision >= 0x30))
temp = 0x1b;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x01,0xe0,temp);
if((SiS_Pr->ChipType == SIS_630) &&
(SiS_Pr->ChipRevision >= 0x30)) {
if(data > 0x13) data = 0x13;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x02,0xe0,data);
} else { /* If mode <= 0x13, we just restore everything */
SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
SiS_Pr->SiS_SelectCRT2Rate = SelectRate_backup;
}
}
#endif
/* Set CRT2 FIFO on 315/330 series */
#ifdef CONFIG_FB_SIS_315
static void
SiS_SetCRT2FIFO_310(struct SiS_Private *SiS_Pr)
{
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x01,0x3B);
if( (SiS_Pr->ChipType == SIS_760) &&
(SiS_Pr->SiS_SysFlags & SF_760LFB) &&
(SiS_Pr->SiS_ModeType == Mode32Bpp) &&
(SiS_Pr->SiS_VGAHDE >= 1280) &&
(SiS_Pr->SiS_VGAVDE >= 1024) ) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2f,0x03);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x01,0x3b);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x4d,0xc0);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2f,0x01);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x4d,0xc0);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,0x6e);
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x02,~0x3f,0x04);
}
}
#endif
static unsigned short
SiS_GetVGAHT2(struct SiS_Private *SiS_Pr)
{
unsigned int tempax,tempbx;
tempbx = (SiS_Pr->SiS_VGAVT - SiS_Pr->SiS_VGAVDE) * SiS_Pr->SiS_RVBHCMAX;
tempax = (SiS_Pr->SiS_VT - SiS_Pr->SiS_VDE) * SiS_Pr->SiS_RVBHCFACT;
tempax = (tempax * SiS_Pr->SiS_HT) / tempbx;
return (unsigned short)tempax;
}
/* Set Part 1 / SiS bridge slave mode */
static void
SiS_SetGroup1_301(struct SiS_Private *SiS_Pr, unsigned short ModeNo,unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short temp, modeflag, i, j, xres=0, VGAVDE;
static const unsigned short CRTranslation[] = {
/* CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 */
0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
/* CR8 CR9 SR0A SR0B SR0C SR0D SR0E CR0F */
0x00, 0x0b, 0x17, 0x18, 0x19, 0x00, 0x1a, 0x00,
/* CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 */
0x0c, 0x0d, 0x0e, 0x00, 0x0f, 0x10, 0x11, 0x00
};
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
} else if(SiS_Pr->UseCustomMode) {
modeflag = SiS_Pr->CModeFlag;
xres = SiS_Pr->CHDisplay;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
xres = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].XRes;
}
/* The following is only done if bridge is in slave mode: */
if(SiS_Pr->ChipType >= SIS_315H) {
if(xres >= 1600) { /* BIOS: == 1600 */
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x31,0x04);
}
}
SiS_Pr->CHTotal = 8224; /* Max HT, 0x2020, results in 0x3ff in registers */
SiS_Pr->CHDisplay = SiS_Pr->SiS_VGAHDE;
if(modeflag & HalfDCLK) SiS_Pr->CHDisplay >>= 1;
SiS_Pr->CHBlankStart = SiS_Pr->CHDisplay;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
SiS_Pr->CHBlankStart += 16;
}
SiS_Pr->CHBlankEnd = 32;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(xres == 1600) SiS_Pr->CHBlankEnd += 80;
}
temp = SiS_Pr->SiS_VGAHT - 96;
if(!(modeflag & HalfDCLK)) temp -= 32;
if(SiS_Pr->SiS_LCDInfo & LCDPass11) {
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x04);
temp |= ((SiS_GetReg(SiS_Pr->SiS_P3c4,0x0b) & 0xc0) << 2);
temp -= 3;
temp <<= 3;
} else {
if(SiS_Pr->SiS_RVBHRS2) temp = SiS_Pr->SiS_RVBHRS2;
}
SiS_Pr->CHSyncStart = temp;
SiS_Pr->CHSyncEnd = 0xffe8; /* results in 0x2000 in registers */
SiS_Pr->CVTotal = 2049; /* Max VT, 0x0801, results in 0x7ff in registers */
VGAVDE = SiS_Pr->SiS_VGAVDE;
if (VGAVDE == 357) VGAVDE = 350;
else if(VGAVDE == 360) VGAVDE = 350;
else if(VGAVDE == 375) VGAVDE = 350;
else if(VGAVDE == 405) VGAVDE = 400;
else if(VGAVDE == 420) VGAVDE = 400;
else if(VGAVDE == 525) VGAVDE = 480;
else if(VGAVDE == 1056) VGAVDE = 1024;
SiS_Pr->CVDisplay = VGAVDE;
SiS_Pr->CVBlankStart = SiS_Pr->CVDisplay;
SiS_Pr->CVBlankEnd = 1;
if(ModeNo == 0x3c) SiS_Pr->CVBlankEnd = 226;
temp = (SiS_Pr->SiS_VGAVT - VGAVDE) >> 1;
SiS_Pr->CVSyncStart = VGAVDE + temp;
temp >>= 3;
SiS_Pr->CVSyncEnd = SiS_Pr->CVSyncStart + temp;
SiS_CalcCRRegisters(SiS_Pr, 0);
SiS_Pr->CCRT1CRTC[16] &= ~0xE0;
for(i = 0; i <= 7; i++) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,CRTranslation[i],SiS_Pr->CCRT1CRTC[i]);
}
for(i = 0x10, j = 8; i <= 0x12; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,CRTranslation[i],SiS_Pr->CCRT1CRTC[j]);
}
for(i = 0x15, j = 11; i <= 0x16; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,CRTranslation[i],SiS_Pr->CCRT1CRTC[j]);
}
for(i = 0x0a, j = 13; i <= 0x0c; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,CRTranslation[i],SiS_Pr->CCRT1CRTC[j]);
}
temp = SiS_Pr->CCRT1CRTC[16] & 0xE0;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,CRTranslation[0x0E],0x1F,temp);
temp = (SiS_Pr->CCRT1CRTC[16] & 0x01) << 5;
if(modeflag & DoubleScanMode) temp |= 0x80;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,CRTranslation[0x09],0x5F,temp);
temp = 0;
temp |= (SiS_GetReg(SiS_Pr->SiS_P3c4,0x01) & 0x01);
if(modeflag & HalfDCLK) temp |= 0x08;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x16,temp); /* SR01: HalfDCLK[3], 8/9 div dotclock[0] */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x0F,0x00); /* CR14: (text mode: underline location) */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x12,0x00); /* CR17: n/a */
temp = 0;
if(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit) {
temp = (SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0x01) << 7;
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1A,temp); /* SR0E, dither[7] */
temp = SiS_GetRegByte((SiS_Pr->SiS_P3ca+0x02));
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,temp); /* ? */
}
/* Setup panel link
* This is used for LVDS, LCDA and Chrontel TV output
* 300/LVDS+TV, 300/301B-DH, 315/LVDS+TV, 315/LCDA
*/
static void
SiS_SetGroup1_LVDS(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short modeflag, resinfo = 0;
unsigned short push2, tempax, tempbx, tempcx, temp;
unsigned int tempeax = 0, tempebx, tempecx, tempvcfact = 0;
bool islvds = false, issis = false, chkdclkfirst = false;
#ifdef CONFIG_FB_SIS_300
unsigned short crt2crtc = 0;
#endif
#ifdef CONFIG_FB_SIS_315
unsigned short pushcx;
#endif
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
resinfo = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ResInfo;
#ifdef CONFIG_FB_SIS_300
crt2crtc = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
#endif
} else if(SiS_Pr->UseCustomMode) {
modeflag = SiS_Pr->CModeFlag;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
#ifdef CONFIG_FB_SIS_300
crt2crtc = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
#endif
}
/* is lvds if really LVDS, or 301B-DH with external LVDS transmitter */
if((SiS_Pr->SiS_IF_DEF_LVDS == 1) || (SiS_Pr->SiS_VBType & VB_NoLCD)) {
islvds = true;
}
/* is really sis if sis bridge, but not 301B-DH */
if((SiS_Pr->SiS_VBType & VB_SISVB) && (!(SiS_Pr->SiS_VBType & VB_NoLCD))) {
issis = true;
}
if((SiS_Pr->ChipType >= SIS_315H) && (islvds) && (!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA))) {
if((!SiS_Pr->SiS_IF_DEF_FSTN) && (!SiS_Pr->SiS_IF_DEF_DSTN)) {
chkdclkfirst = true;
}
}
#ifdef CONFIG_FB_SIS_315
if((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
if(IS_SIS330) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2D,0x10);
} else if(IS_SIS740) {
if(islvds) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,0xfb,0x04);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2D,0x03);
} else if(SiS_Pr->SiS_VBType & VB_SISVB) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2D,0x10);
}
} else {
if(islvds) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,0xfb,0x04);
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2D,0x00);
} else if(SiS_Pr->SiS_VBType & VB_SISVB) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x2D,0x0f);
if(SiS_Pr->SiS_VBType & VB_SIS30xC) {
if((SiS_Pr->SiS_LCDResInfo == Panel_1024x768) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024)) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2D,0x20);
}
}
}
}
}
#endif
/* Horizontal */
tempax = SiS_Pr->SiS_LCDHDES;
if(islvds) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(!SiS_Pr->SiS_IF_DEF_FSTN && !SiS_Pr->SiS_IF_DEF_DSTN) {
if((SiS_Pr->SiS_LCDResInfo == Panel_640x480) &&
(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode))) {
tempax -= 8;
}
}
}
}
temp = (tempax & 0x0007);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1A,temp); /* BPLHDESKEW[2:0] */
temp = (tempax >> 3) & 0x00FF;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x16,temp); /* BPLHDESKEW[10:3] */
tempbx = SiS_Pr->SiS_HDE;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
tempbx = SiS_Pr->PanelXRes;
}
if((SiS_Pr->SiS_LCDResInfo == Panel_320x240_1) ||
(SiS_Pr->SiS_LCDResInfo == Panel_320x240_2) ||
(SiS_Pr->SiS_LCDResInfo == Panel_320x240_3)) {
tempbx >>= 1;
}
}
tempax += tempbx;
if(tempax >= SiS_Pr->SiS_HT) tempax -= SiS_Pr->SiS_HT;
temp = tempax;
if(temp & 0x07) temp += 8;
temp >>= 3;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x17,temp); /* BPLHDEE */
tempcx = (SiS_Pr->SiS_HT - tempbx) >> 2;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
if(SiS_Pr->PanelHRS != 999) tempcx = SiS_Pr->PanelHRS;
}
}
tempcx += tempax;
if(tempcx >= SiS_Pr->SiS_HT) tempcx -= SiS_Pr->SiS_HT;
temp = (tempcx >> 3) & 0x00FF;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(SiS_Pr->SiS_IF_DEF_TRUMPION) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
switch(ModeNo) {
case 0x04:
case 0x05:
case 0x0d: temp = 0x56; break;
case 0x10: temp = 0x60; break;
case 0x13: temp = 0x5f; break;
case 0x40:
case 0x41:
case 0x4f:
case 0x43:
case 0x44:
case 0x62:
case 0x56:
case 0x53:
case 0x5d:
case 0x5e: temp = 0x54; break;
}
}
}
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x14,temp); /* BPLHRS */
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
temp += 2;
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
temp += 8;
if(SiS_Pr->PanelHRE != 999) {
temp = tempcx + SiS_Pr->PanelHRE;
if(temp >= SiS_Pr->SiS_HT) temp -= SiS_Pr->SiS_HT;
temp >>= 3;
}
}
} else {
temp += 10;
}
temp &= 0x1F;
temp |= ((tempcx & 0x07) << 5);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x15,temp); /* BPLHRE */
/* Vertical */
tempax = SiS_Pr->SiS_VGAVDE;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
tempax = SiS_Pr->PanelYRes;
}
}
tempbx = SiS_Pr->SiS_LCDVDES + tempax;
if(tempbx >= SiS_Pr->SiS_VT) tempbx -= SiS_Pr->SiS_VT;
push2 = tempbx;
tempcx = SiS_Pr->SiS_VGAVT - SiS_Pr->SiS_VGAVDE;
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
tempcx = SiS_Pr->SiS_VGAVT - SiS_Pr->PanelYRes;
}
}
}
if(islvds) tempcx >>= 1;
else tempcx >>= 2;
if( (SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) &&
(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) &&
(SiS_Pr->PanelVRS != 999) ) {
tempcx = SiS_Pr->PanelVRS;
tempbx += tempcx;
if(issis) tempbx++;
} else {
tempbx += tempcx;
if(SiS_Pr->ChipType < SIS_315H) tempbx++;
else if(issis) tempbx++;
}
if(tempbx >= SiS_Pr->SiS_VT) tempbx -= SiS_Pr->SiS_VT;
temp = tempbx & 0x00FF;
if(SiS_Pr->SiS_IF_DEF_TRUMPION) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(ModeNo == 0x10) temp = 0xa9;
}
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,temp); /* BPLVRS */
tempcx >>= 3;
tempcx++;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
if(SiS_Pr->PanelVRE != 999) tempcx = SiS_Pr->PanelVRE;
}
}
tempcx += tempbx;
temp = tempcx & 0x000F;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x19,0xF0,temp); /* BPLVRE */
temp = ((tempbx >> 8) & 0x07) << 3;
if(SiS_Pr->SiS_IF_DEF_FSTN || SiS_Pr->SiS_IF_DEF_DSTN) {
if(SiS_Pr->SiS_HDE != 640) {
if(SiS_Pr->SiS_VGAVDE != SiS_Pr->SiS_VDE) temp |= 0x40;
}
} else if(SiS_Pr->SiS_VGAVDE != SiS_Pr->SiS_VDE) temp |= 0x40;
if(SiS_Pr->SiS_SetFlag & EnableLVDSDDA) temp |= 0x40;
tempbx = 0x87;
if((SiS_Pr->ChipType >= SIS_315H) ||
(SiS_Pr->ChipRevision >= 0x30)) {
tempbx = 0x07;
if((SiS_Pr->SiS_IF_DEF_CH70xx == 1) && (SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) {
if(SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0x03) temp |= 0x80;
}
/* Chrontel 701x operates in 24bit mode (8-8-8, 2x12bit multiplexed) via VGA2 */
if(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x06) & 0x10) temp |= 0x80;
} else {
if(SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0x01) temp |= 0x80;
}
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x1A,tempbx,temp);
tempbx = push2; /* BPLVDEE */
tempcx = SiS_Pr->SiS_LCDVDES; /* BPLVDES */
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_640x480:
tempbx = SiS_Pr->SiS_VGAVDE - 1;
tempcx = SiS_Pr->SiS_VGAVDE;
break;
case Panel_800x600:
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) {
if(resinfo == SIS_RI_800x600) tempcx++;
}
break;
case Panel_1024x600:
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) {
if(resinfo == SIS_RI_1024x600) tempcx++;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
if(resinfo == SIS_RI_800x600) tempcx++;
}
}
break;
case Panel_1024x768:
if(SiS_Pr->ChipType < SIS_315H) {
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) {
if(resinfo == SIS_RI_1024x768) tempcx++;
}
}
break;
}
}
temp = ((tempbx >> 8) & 0x07) << 3;
temp |= ((tempcx >> 8) & 0x07);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1D,temp);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1C,tempbx);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1B,tempcx);
/* Vertical scaling */
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300 /* 300 series */
tempeax = SiS_Pr->SiS_VGAVDE << 6;
temp = (tempeax % (unsigned int)SiS_Pr->SiS_VDE);
tempeax = tempeax / (unsigned int)SiS_Pr->SiS_VDE;
if(temp) tempeax++;
if(SiS_Pr->SiS_SetFlag & EnableLVDSDDA) tempeax = 0x3F;
temp = (unsigned short)(tempeax & 0x00FF);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1E,temp); /* BPLVCFACT */
tempvcfact = temp;
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* 315 series */
tempeax = SiS_Pr->SiS_VGAVDE << 18;
tempebx = SiS_Pr->SiS_VDE;
temp = (tempeax % tempebx);
tempeax = tempeax / tempebx;
if(temp) tempeax++;
tempvcfact = tempeax;
temp = (unsigned short)(tempeax & 0x00FF);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x37,temp);
temp = (unsigned short)((tempeax & 0x00FF00) >> 8);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x36,temp);
temp = (unsigned short)((tempeax & 0x00030000) >> 16);
if(SiS_Pr->SiS_VDE == SiS_Pr->SiS_VGAVDE) temp |= 0x04;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x35,temp);
if(SiS_Pr->SiS_VBType & VB_SISPART4SCALER) {
temp = (unsigned short)(tempeax & 0x00FF);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x3c,temp);
temp = (unsigned short)((tempeax & 0x00FF00) >> 8);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x3b,temp);
temp = (unsigned short)(((tempeax & 0x00030000) >> 16) << 6);
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x3a,0x3f,temp);
temp = 0;
if(SiS_Pr->SiS_VDE != SiS_Pr->SiS_VGAVDE) temp |= 0x08;
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x30,0xf3,temp);
}
#endif
}
/* Horizontal scaling */
tempeax = SiS_Pr->SiS_VGAHDE; /* 1f = ( (VGAHDE * 65536) / ( (VGAHDE * 65536) / HDE ) ) - 1*/
if(chkdclkfirst) {
if(modeflag & HalfDCLK) tempeax >>= 1;
}
tempebx = tempeax << 16;
if(SiS_Pr->SiS_HDE == tempeax) {
tempecx = 0xFFFF;
} else {
tempecx = tempebx / SiS_Pr->SiS_HDE;
if(SiS_Pr->ChipType >= SIS_315H) {
if(tempebx % SiS_Pr->SiS_HDE) tempecx++;
}
}
if(SiS_Pr->ChipType >= SIS_315H) {
tempeax = (tempebx / tempecx) - 1;
} else {
tempeax = ((SiS_Pr->SiS_VGAHT << 16) / tempecx) - 1;
}
tempecx = (tempecx << 16) | (tempeax & 0xFFFF);
temp = (unsigned short)(tempecx & 0x00FF);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1F,temp);
if(SiS_Pr->ChipType >= SIS_315H) {
tempeax = (SiS_Pr->SiS_VGAVDE << 18) / tempvcfact;
tempbx = (unsigned short)(tempeax & 0xFFFF);
} else {
tempeax = SiS_Pr->SiS_VGAVDE << 6;
tempbx = tempvcfact & 0x3f;
if(tempbx == 0) tempbx = 64;
tempeax /= tempbx;
tempbx = (unsigned short)(tempeax & 0xFFFF);
}
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) tempbx--;
if(SiS_Pr->SiS_SetFlag & EnableLVDSDDA) {
if((!SiS_Pr->SiS_IF_DEF_FSTN) && (!SiS_Pr->SiS_IF_DEF_DSTN)) tempbx = 1;
else if(SiS_Pr->SiS_LCDResInfo != Panel_640x480) tempbx = 1;
}
temp = ((tempbx >> 8) & 0x07) << 3;
temp = temp | ((tempecx >> 8) & 0x07);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x20,temp);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x21,tempbx);
tempecx >>= 16; /* BPLHCFACT */
if(!chkdclkfirst) {
if(modeflag & HalfDCLK) tempecx >>= 1;
}
temp = (unsigned short)((tempecx & 0xFF00) >> 8);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x22,temp);
temp = (unsigned short)(tempecx & 0x00FF);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x23,temp);
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
if((islvds) || (SiS_Pr->SiS_VBInfo & VB_SISLVDS)) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1e,0x20);
}
} else {
if(islvds) {
if(SiS_Pr->ChipType == SIS_740) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1e,0x03);
} else {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1e,0x23);
}
}
}
}
#endif
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->SiS_IF_DEF_TRUMPION) {
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned char *trumpdata;
int i, j = crt2crtc;
unsigned char TrumpMode13[4] = { 0x01, 0x10, 0x2c, 0x00 };
unsigned char TrumpMode10_1[4] = { 0x01, 0x10, 0x27, 0x00 };
unsigned char TrumpMode10_2[4] = { 0x01, 0x16, 0x10, 0x00 };
if(SiS_Pr->SiS_UseROM) {
trumpdata = &ROMAddr[0x8001 + (j * 80)];
} else {
if(SiS_Pr->SiS_LCDTypeInfo == 0x0e) j += 7;
trumpdata = &SiS300_TrumpionData[j][0];
}
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x02,0xbf);
for(i=0; i<5; i++) {
SiS_SetTrumpionBlock(SiS_Pr, trumpdata);
}
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(ModeNo == 0x13) {
for(i=0; i<4; i++) {
SiS_SetTrumpionBlock(SiS_Pr, &TrumpMode13[0]);
}
} else if(ModeNo == 0x10) {
for(i=0; i<4; i++) {
SiS_SetTrumpionBlock(SiS_Pr, &TrumpMode10_1[0]);
SiS_SetTrumpionBlock(SiS_Pr, &TrumpMode10_2[0]);
}
}
}
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x02,0x40);
}
#endif
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->SiS_IF_DEF_FSTN || SiS_Pr->SiS_IF_DEF_DSTN) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x25,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x26,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x27,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x28,0x87);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x29,0x5A);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2A,0x4B);
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x44,~0x07,0x03);
tempax = SiS_Pr->SiS_HDE; /* Blps = lcdhdee(lcdhdes+HDE) + 64 */
if(SiS_Pr->SiS_LCDResInfo == Panel_320x240_1 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_2 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_3) tempax >>= 1;
tempax += 64;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x38,tempax & 0xff);
temp = (tempax >> 8) << 3;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x35,~0x078,temp);
tempax += 32; /* Blpe = lBlps+32 */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x39,tempax & 0xff);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3A,0x00); /* Bflml = 0 */
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x3C,~0x007);
tempax = SiS_Pr->SiS_VDE;
if(SiS_Pr->SiS_LCDResInfo == Panel_320x240_1 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_2 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_3) tempax >>= 1;
tempax >>= 1;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3B,tempax & 0xff);
temp = (tempax >> 8) << 3;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x3C,~0x038,temp);
tempeax = SiS_Pr->SiS_HDE;
if(SiS_Pr->SiS_LCDResInfo == Panel_320x240_1 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_2 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_3) tempeax >>= 1;
tempeax <<= 2; /* BDxFIFOSTOP = (HDE*4)/128 */
temp = tempeax & 0x7f;
tempeax >>= 7;
if(temp) tempeax++;
temp = tempeax & 0x3f;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x45,temp);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3F,0x00); /* BDxWadrst0 */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3E,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3D,0x10);
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x3C,~0x040);
tempax = SiS_Pr->SiS_HDE;
if(SiS_Pr->SiS_LCDResInfo == Panel_320x240_1 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_2 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_3) tempax >>= 1;
tempax >>= 4; /* BDxWadroff = HDE*4/8/8 */
pushcx = tempax;
temp = tempax & 0x00FF;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x43,temp);
temp = ((tempax & 0xFF00) >> 8) << 3;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port, 0x44, 0x07, temp);
tempax = SiS_Pr->SiS_VDE; /* BDxWadrst1 = BDxWadrst0 + BDxWadroff * VDE */
if(SiS_Pr->SiS_LCDResInfo == Panel_320x240_1 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_2 ||
SiS_Pr->SiS_LCDResInfo == Panel_320x240_3) tempax >>= 1;
tempeax = tempax * pushcx;
temp = tempeax & 0xFF;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x42,temp);
temp = (tempeax & 0xFF00) >> 8;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x41,temp);
temp = ((tempeax & 0xFF0000) >> 16) | 0x10;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x40,temp);
temp = ((tempeax & 0x01000000) >> 24) << 7;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port, 0x3C, 0x7F, temp);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2F,0x03);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x03,0x50);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x04,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2F,0x01);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x19,0x38);
if(SiS_Pr->SiS_IF_DEF_FSTN) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2b,0x02);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2c,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2d,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x35,0x0c);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x36,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x37,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x38,0x80);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x39,0xA0);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3a,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3b,0xf0);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3c,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3d,0x10);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3e,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x3f,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x40,0x10);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x41,0x25);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x42,0x80);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x43,0x14);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x44,0x03);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x45,0x0a);
}
}
#endif /* CONFIG_FB_SIS_315 */
}
/* Set Part 1 */
static void
SiS_SetGroup1(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
#if defined(CONFIG_FB_SIS_300) || defined(CONFIG_FB_SIS_315)
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
#endif
unsigned short temp=0, tempax=0, tempbx=0, tempcx=0, bridgeadd=0;
unsigned short pushbx=0, CRT1Index=0, modeflag, resinfo=0;
#ifdef CONFIG_FB_SIS_315
unsigned short tempbl=0;
#endif
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_SetGroup1_LVDS(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
return;
}
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
} else if(SiS_Pr->UseCustomMode) {
modeflag = SiS_Pr->CModeFlag;
} else {
CRT1Index = SiS_GetRefCRT1CRTC(SiS_Pr, RefreshRateTableIndex, SiS_Pr->SiS_UseWideCRT2);
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
SiS_SetCRT2Offset(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
if( ! ((SiS_Pr->ChipType >= SIS_315H) &&
(SiS_Pr->SiS_IF_DEF_LVDS == 1) &&
(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) ) {
if(SiS_Pr->ChipType < SIS_315H ) {
#ifdef CONFIG_FB_SIS_300
SiS_SetCRT2FIFO_300(SiS_Pr, ModeNo);
#endif
} else {
#ifdef CONFIG_FB_SIS_315
SiS_SetCRT2FIFO_310(SiS_Pr);
#endif
}
/* 1. Horizontal setup */
if(SiS_Pr->ChipType < SIS_315H ) {
#ifdef CONFIG_FB_SIS_300 /* ------------- 300 series --------------*/
temp = (SiS_Pr->SiS_VGAHT - 1) & 0x0FF; /* BTVGA2HT 0x08,0x09 */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x08,temp); /* CRT2 Horizontal Total */
temp = (((SiS_Pr->SiS_VGAHT - 1) & 0xFF00) >> 8) << 4;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x09,0x0f,temp); /* CRT2 Horizontal Total Overflow [7:4] */
temp = (SiS_Pr->SiS_VGAHDE + 12) & 0x0FF; /* BTVGA2HDEE 0x0A,0x0C */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x0A,temp); /* CRT2 Horizontal Display Enable End */
pushbx = SiS_Pr->SiS_VGAHDE + 12; /* bx BTVGA2HRS 0x0B,0x0C */
tempcx = (SiS_Pr->SiS_VGAHT - SiS_Pr->SiS_VGAHDE) >> 2;
tempbx = pushbx + tempcx;
tempcx <<= 1;
tempcx += tempbx;
bridgeadd = 12;
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* ------------------- 315/330 series --------------- */
tempcx = SiS_Pr->SiS_VGAHT; /* BTVGA2HT 0x08,0x09 */
if(modeflag & HalfDCLK) {
if(SiS_Pr->SiS_VBType & VB_SISVB) {
tempcx >>= 1;
} else {
tempax = SiS_Pr->SiS_VGAHDE >> 1;
tempcx = SiS_Pr->SiS_HT - SiS_Pr->SiS_HDE + tempax;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
tempcx = SiS_Pr->SiS_HT - tempax;
}
}
}
tempcx--;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x08,tempcx); /* CRT2 Horizontal Total */
temp = (tempcx >> 4) & 0xF0;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x09,0x0F,temp); /* CRT2 Horizontal Total Overflow [7:4] */
tempcx = SiS_Pr->SiS_VGAHT; /* BTVGA2HDEE 0x0A,0x0C */
tempbx = SiS_Pr->SiS_VGAHDE;
tempcx -= tempbx;
tempcx >>= 2;
if(modeflag & HalfDCLK) {
tempbx >>= 1;
tempcx >>= 1;
}
tempbx += 16;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x0A,tempbx); /* CRT2 Horizontal Display Enable End */
pushbx = tempbx;
tempcx >>= 1;
tempbx += tempcx;
tempcx += tempbx;
bridgeadd = 16;
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->ChipType >= SIS_661) {
if((SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024)) {
if(resinfo == SIS_RI_1280x1024) {
tempcx = (tempcx & 0xff00) | 0x30;
} else if(resinfo == SIS_RI_1600x1200) {
tempcx = (tempcx & 0xff00) | 0xff;
}
}
}
}
#endif /* CONFIG_FB_SIS_315 */
} /* 315/330 series */
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->UseCustomMode) {
tempbx = SiS_Pr->CHSyncStart + bridgeadd;
tempcx = SiS_Pr->CHSyncEnd + bridgeadd;
tempax = SiS_Pr->SiS_VGAHT;
if(modeflag & HalfDCLK) tempax >>= 1;
tempax--;
if(tempcx > tempax) tempcx = tempax;
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC) {
unsigned char cr4, cr14, cr5, cr15;
if(SiS_Pr->UseCustomMode) {
cr4 = SiS_Pr->CCRT1CRTC[4];
cr14 = SiS_Pr->CCRT1CRTC[14];
cr5 = SiS_Pr->CCRT1CRTC[5];
cr15 = SiS_Pr->CCRT1CRTC[15];
} else {
cr4 = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[4];
cr14 = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[14];
cr5 = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[5];
cr15 = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[15];
}
tempbx = ((cr4 | ((cr14 & 0xC0) << 2)) - 3) << 3; /* (VGAHRS-3)*8 */
tempcx = (((cr5 & 0x1f) | ((cr15 & 0x04) << (5-2))) - 3) << 3; /* (VGAHRE-3)*8 */
tempcx &= 0x00FF;
tempcx |= (tempbx & 0xFF00);
tempbx += bridgeadd;
tempcx += bridgeadd;
tempax = SiS_Pr->SiS_VGAHT;
if(modeflag & HalfDCLK) tempax >>= 1;
tempax--;
if(tempcx > tempax) tempcx = tempax;
}
if(SiS_Pr->SiS_TVMode & (TVSetNTSC1024 | TVSet525p1024)) {
tempbx = 1040;
tempcx = 1044; /* HWCursor bug! */
}
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x0B,tempbx); /* CRT2 Horizontal Retrace Start */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x0D,tempcx); /* CRT2 Horizontal Retrace End */
temp = ((tempbx >> 8) & 0x0F) | ((pushbx >> 4) & 0xF0);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x0C,temp); /* Overflow */
/* 2. Vertical setup */
tempcx = SiS_Pr->SiS_VGAVT - 1;
temp = tempcx & 0x00FF;
if(SiS_Pr->ChipType < SIS_661) {
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)) {
temp--;
}
}
} else {
temp--;
}
} else if(SiS_Pr->ChipType >= SIS_315H) {
temp--;
}
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x0E,temp); /* CRT2 Vertical Total */
tempbx = SiS_Pr->SiS_VGAVDE - 1;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x0F,tempbx); /* CRT2 Vertical Display Enable End */
temp = ((tempbx >> 5) & 0x38) | ((tempcx >> 8) & 0x07);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x12,temp); /* Overflow */
if((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->ChipType < SIS_661)) {
tempbx++;
tempax = tempbx;
tempcx++;
tempcx -= tempax;
tempcx >>= 2;
tempbx += tempcx;
if(tempcx < 4) tempcx = 4;
tempcx >>= 2;
tempcx += tempbx;
tempcx++;
} else {
tempbx = (SiS_Pr->SiS_VGAVT + SiS_Pr->SiS_VGAVDE) >> 1; /* BTVGA2VRS 0x10,0x11 */
tempcx = ((SiS_Pr->SiS_VGAVT - SiS_Pr->SiS_VGAVDE) >> 4) + tempbx + 1; /* BTVGA2VRE 0x11 */
}
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->UseCustomMode) {
tempbx = SiS_Pr->CVSyncStart;
tempcx = SiS_Pr->CVSyncEnd;
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC) {
unsigned char cr8, cr7, cr13;
if(SiS_Pr->UseCustomMode) {
cr8 = SiS_Pr->CCRT1CRTC[8];
cr7 = SiS_Pr->CCRT1CRTC[7];
cr13 = SiS_Pr->CCRT1CRTC[13];
tempcx = SiS_Pr->CCRT1CRTC[9];
} else {
cr8 = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[8];
cr7 = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[7];
cr13 = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[13];
tempcx = SiS_Pr->SiS_CRT1Table[CRT1Index].CR[9];
}
tempbx = cr8;
if(cr7 & 0x04) tempbx |= 0x0100;
if(cr7 & 0x80) tempbx |= 0x0200;
if(cr13 & 0x08) tempbx |= 0x0400;
}
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x10,tempbx); /* CRT2 Vertical Retrace Start */
temp = ((tempbx >> 4) & 0x70) | (tempcx & 0x0F);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x11,temp); /* CRT2 Vert. Retrace End; Overflow */
/* 3. Panel delay compensation */
if(SiS_Pr->ChipType < SIS_315H) {
#ifdef CONFIG_FB_SIS_300 /* ---------- 300 series -------------- */
if(SiS_Pr->SiS_VBType & VB_SISVB) {
temp = 0x20;
if(SiS_Pr->ChipType == SIS_300) {
temp = 0x10;
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) temp = 0x2c;
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) temp = 0x20;
}
if(SiS_Pr->SiS_VBType & VB_SIS301) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) temp = 0x20;
}
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x960) temp = 0x24;
if(SiS_Pr->SiS_LCDResInfo == Panel_Custom) temp = 0x2c;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) temp = 0x08;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) temp = 0x2c;
else temp = 0x20;
}
if(SiS_Pr->SiS_UseROM) {
if(ROMAddr[0x220] & 0x80) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTVNoYPbPrHiVision)
temp = ROMAddr[0x221];
else if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision)
temp = ROMAddr[0x222];
else if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024)
temp = ROMAddr[0x223];
else
temp = ROMAddr[0x224];
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->PDC != -1) temp = SiS_Pr->PDC;
}
} else {
temp = 0x20;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) {
if(SiS_Pr->SiS_LCDResInfo == Panel_640x480) temp = 0x04;
}
if(SiS_Pr->SiS_UseROM) {
if(ROMAddr[0x220] & 0x80) {
temp = ROMAddr[0x220];
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->PDC != -1) temp = SiS_Pr->PDC;
}
}
temp &= 0x3c;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,~0x3C,temp); /* Panel Link Delay Compensation; (Software Command Reset; Power Saving) */
#endif /* CONFIG_FB_SIS_300 */
} else {
#ifdef CONFIG_FB_SIS_315 /* --------------- 315/330 series ---------------*/
if(SiS_Pr->ChipType < SIS_661) {
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if(SiS_Pr->ChipType == SIS_740) temp = 0x03;
else temp = 0x00;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) temp = 0x0a;
tempbl = 0xF0;
if(SiS_Pr->ChipType == SIS_650) {
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) tempbl = 0x0F;
}
}
if(SiS_Pr->SiS_IF_DEF_DSTN || SiS_Pr->SiS_IF_DEF_FSTN) {
temp = 0x08;
tempbl = 0;
if((SiS_Pr->SiS_UseROM) && (!(SiS_Pr->SiS_ROMNew))) {
if(ROMAddr[0x13c] & 0x80) tempbl = 0xf0;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2D,tempbl,temp); /* Panel Link Delay Compensation */
}
} /* < 661 */
tempax = 0;
if(modeflag & DoubleScanMode) tempax |= 0x80;
if(modeflag & HalfDCLK) tempax |= 0x40;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2C,0x3f,tempax);
#endif /* CONFIG_FB_SIS_315 */
}
} /* Slavemode */
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if((SiS_Pr->SiS_VBType & VB_NoLCD) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD)) {
/* For 301BDH with LCD, we set up the Panel Link */
SiS_SetGroup1_LVDS(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
} else if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
SiS_SetGroup1_301(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
} else {
if(SiS_Pr->ChipType < SIS_315H) {
SiS_SetGroup1_LVDS(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
} else {
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if((!(SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) || (SiS_Pr->SiS_VBInfo & SetInSlaveMode)) {
SiS_SetGroup1_LVDS(SiS_Pr, ModeNo,ModeIdIndex,RefreshRateTableIndex);
}
} else {
SiS_SetGroup1_LVDS(SiS_Pr, ModeNo,ModeIdIndex,RefreshRateTableIndex);
}
}
}
}
/*********************************************/
/* SET PART 2 REGISTER GROUP */
/*********************************************/
#ifdef CONFIG_FB_SIS_315
static unsigned char *
SiS_GetGroup2CLVXPtr(struct SiS_Private *SiS_Pr, int tabletype)
{
const unsigned char *tableptr = NULL;
unsigned short a, b, p = 0;
a = SiS_Pr->SiS_VGAHDE;
b = SiS_Pr->SiS_HDE;
if(tabletype) {
a = SiS_Pr->SiS_VGAVDE;
b = SiS_Pr->SiS_VDE;
}
if(a < b) {
tableptr = SiS_Part2CLVX_1;
} else if(a == b) {
tableptr = SiS_Part2CLVX_2;
} else {
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
tableptr = SiS_Part2CLVX_4;
} else {
tableptr = SiS_Part2CLVX_3;
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525i) tableptr = SiS_Part2CLVX_3;
else if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) tableptr = SiS_Part2CLVX_3;
else tableptr = SiS_Part2CLVX_5;
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
tableptr = SiS_Part2CLVX_6;
}
do {
if((tableptr[p] | tableptr[p+1] << 8) == a) break;
p += 0x42;
} while((tableptr[p] | tableptr[p+1] << 8) != 0xffff);
if((tableptr[p] | tableptr[p+1] << 8) == 0xffff) p -= 0x42;
}
p += 2;
return ((unsigned char *)&tableptr[p]);
}
static void
SiS_SetGroup2_C_ELV(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned char *tableptr;
unsigned char temp;
int i, j;
if(!(SiS_Pr->SiS_VBType & VB_SISTAP4SCALER)) return;
tableptr = SiS_GetGroup2CLVXPtr(SiS_Pr, 0);
for(i = 0x80, j = 0; i <= 0xbf; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port, i, tableptr[j]);
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
tableptr = SiS_GetGroup2CLVXPtr(SiS_Pr, 1);
for(i = 0xc0, j = 0; i <= 0xff; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port, i, tableptr[j]);
}
}
temp = 0x10;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) temp |= 0x04;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x4e,0xeb,temp);
}
static bool
SiS_GetCRT2Part2Ptr(struct SiS_Private *SiS_Pr,unsigned short ModeNo,unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex,unsigned short *CRT2Index,
unsigned short *ResIndex)
{
if(SiS_Pr->ChipType < SIS_315H) return false;
if(ModeNo <= 0x13)
(*ResIndex) = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
else
(*ResIndex) = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
(*ResIndex) &= 0x3f;
(*CRT2Index) = 0;
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) {
(*CRT2Index) = 200;
}
}
if(SiS_Pr->SiS_CustomT == CUT_ASUSA2H_2) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(SiS_Pr->SiS_SetFlag & LCDVESATiming) (*CRT2Index) = 206;
}
}
return (((*CRT2Index) != 0));
}
#endif
#ifdef CONFIG_FB_SIS_300
static void
SiS_Group2LCDSpecial(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short crt2crtc)
{
unsigned short tempcx;
static const unsigned char atable[] = {
0xc3,0x9e,0xc3,0x9e,0x02,0x02,0x02,
0xab,0x87,0xab,0x9e,0xe7,0x02,0x02
};
if(!SiS_Pr->UseCustomMode) {
if( ( ( (SiS_Pr->ChipType == SIS_630) ||
(SiS_Pr->ChipType == SIS_730) ) &&
(SiS_Pr->ChipRevision > 2) ) &&
(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) &&
(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) &&
(!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) ) {
if(ModeNo == 0x13) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x04,0xB9);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x05,0xCC);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x06,0xA6);
} else if((crt2crtc & 0x3F) == 4) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,0x2B);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,0x13);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x04,0xE5);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x05,0x08);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x06,0xE2);
}
}
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_LCDTypeInfo == 0x0c) {
crt2crtc &= 0x1f;
tempcx = 0;
if(!(SiS_Pr->SiS_VBInfo & SetNotSimuMode)) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
tempcx += 7;
}
}
tempcx += crt2crtc;
if(crt2crtc >= 4) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x06,0xff);
}
if(!(SiS_Pr->SiS_VBInfo & SetNotSimuMode)) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
if(crt2crtc == 4) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,0x28);
}
}
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,0x18);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x04,atable[tempcx]);
}
}
}
}
/* For ECS A907. Highly preliminary. */
static void
SiS_Set300Part2Regs(struct SiS_Private *SiS_Pr, unsigned short ModeIdIndex, unsigned short RefreshRateTableIndex,
unsigned short ModeNo)
{
const struct SiS_Part2PortTbl *CRT2Part2Ptr = NULL;
unsigned short crt2crtc, resindex;
int i, j;
if(SiS_Pr->ChipType != SIS_300) return;
if(!(SiS_Pr->SiS_VBType & VB_SIS30xBLV)) return;
if(SiS_Pr->UseCustomMode) return;
if(ModeNo <= 0x13) {
crt2crtc = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else {
crt2crtc = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
}
resindex = crt2crtc & 0x3F;
if(SiS_Pr->SiS_SetFlag & LCDVESATiming) CRT2Part2Ptr = SiS_Pr->SiS_CRT2Part2_1024x768_1;
else CRT2Part2Ptr = SiS_Pr->SiS_CRT2Part2_1024x768_2;
/* The BIOS code (1.16.51,56) is obviously a fragment! */
if(ModeNo > 0x13) {
CRT2Part2Ptr = SiS_Pr->SiS_CRT2Part2_1024x768_1;
resindex = 4;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x01,0x80,(CRT2Part2Ptr+resindex)->CR[0]);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x02,0x80,(CRT2Part2Ptr+resindex)->CR[1]);
for(i = 2, j = 0x04; j <= 0x06; i++, j++ ) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,j,(CRT2Part2Ptr+resindex)->CR[i]);
}
for(j = 0x1c; j <= 0x1d; i++, j++ ) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,j,(CRT2Part2Ptr+resindex)->CR[i]);
}
for(j = 0x1f; j <= 0x21; i++, j++ ) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,j,(CRT2Part2Ptr+resindex)->CR[i]);
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x23,(CRT2Part2Ptr+resindex)->CR[10]);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x25,0x0f,(CRT2Part2Ptr+resindex)->CR[11]);
}
#endif
static void
SiS_SetTVSpecial(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
if(!(SiS_Pr->SiS_VBType & VB_SIS30xBLV)) return;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToTVNoHiVision)) return;
if(SiS_Pr->SiS_TVMode & (TVSetYPbPr525p | TVSetYPbPr750p)) return;
if(!(SiS_Pr->SiS_TVMode & TVSetPAL)) {
if(SiS_Pr->SiS_TVMode & TVSetNTSC1024) {
static const unsigned char specialtv[] = {
0xa7,0x07,0xf2,0x6e,0x17,0x8b,0x73,0x53,
0x13,0x40,0x34,0xf4,0x63,0xbb,0xcc,0x7a,
0x58,0xe4,0x73,0xda,0x13
};
int i, j;
for(i = 0x1c, j = 0; i <= 0x30; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,specialtv[j]);
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x43,0x72);
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750)) {
if(SiS_Pr->SiS_TVMode & TVSetPALM) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,0x14);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,0x1b);
} else {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,0x14); /* 15 */
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,0x1a); /* 1b */
}
}
}
} else {
if((ModeNo == 0x38) || (ModeNo == 0x4a) || (ModeNo == 0x64) ||
(ModeNo == 0x52) || (ModeNo == 0x58) || (ModeNo == 0x5c)) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,0x1b); /* 21 */
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,0x54); /* 5a */
} else {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,0x1a); /* 21 */
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,0x53); /* 5a */
}
}
}
static void
SiS_SetGroup2_Tail(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
unsigned short temp;
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) {
if(SiS_Pr->SiS_VGAVDE == 525) {
temp = 0xc3;
if(SiS_Pr->SiS_ModeType <= ModeVGA) {
temp++;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) temp += 2;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x2f,temp);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x30,0xb3);
} else if(SiS_Pr->SiS_VGAVDE == 420) {
temp = 0x4d;
if(SiS_Pr->SiS_ModeType <= ModeVGA) {
temp++;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) temp++;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x2f,temp);
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) {
if(SiS_Pr->SiS_VBType & VB_SIS30xB) {
SiS_SetRegOR(SiS_Pr->SiS_Part2Port,0x1a,0x03);
/* Not always for LV, see SetGrp2 */
}
temp = 1;
if(ModeNo <= 0x13) temp = 3;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x0b,temp);
}
#if 0
/* 651+301C, for 1280x768 - do I really need that? */
if((SiS_Pr->SiS_PanelXRes == 1280) && (SiS_Pr->SiS_PanelYRes == 768)) {
if(SiS_Pr->SiS_VBInfo & SetSimuScanMode) {
if(((SiS_Pr->SiS_HDE == 640) && (SiS_Pr->SiS_VDE == 480)) ||
((SiS_Pr->SiS_HDE == 320) && (SiS_Pr->SiS_VDE == 240))) {
SiS_SetReg(SiS_Part2Port,0x01,0x2b);
SiS_SetReg(SiS_Part2Port,0x02,0x13);
SiS_SetReg(SiS_Part2Port,0x04,0xe5);
SiS_SetReg(SiS_Part2Port,0x05,0x08);
SiS_SetReg(SiS_Part2Port,0x06,0xe2);
SiS_SetReg(SiS_Part2Port,0x1c,0x21);
SiS_SetReg(SiS_Part2Port,0x1d,0x45);
SiS_SetReg(SiS_Part2Port,0x1f,0x0b);
SiS_SetReg(SiS_Part2Port,0x20,0x00);
SiS_SetReg(SiS_Part2Port,0x21,0xa9);
SiS_SetReg(SiS_Part2Port,0x23,0x0b);
SiS_SetReg(SiS_Part2Port,0x25,0x04);
}
}
}
#endif
}
}
static void
SiS_SetGroup2(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short i, j, tempax, tempbx, tempcx, tempch, tempcl, temp;
unsigned short push2, modeflag, crt2crtc, bridgeoffset;
unsigned int longtemp, PhaseIndex;
bool newtvphase;
const unsigned char *TimingPoint;
#ifdef CONFIG_FB_SIS_315
unsigned short resindex, CRT2Index;
const struct SiS_Part2PortTbl *CRT2Part2Ptr = NULL;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) return;
#endif
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
crt2crtc = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else if(SiS_Pr->UseCustomMode) {
modeflag = SiS_Pr->CModeFlag;
crt2crtc = 0;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
crt2crtc = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
}
temp = 0;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToAVIDEO)) temp |= 0x08;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToSVIDEO)) temp |= 0x04;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToSCART) temp |= 0x02;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) temp |= 0x01;
if(!(SiS_Pr->SiS_TVMode & TVSetPAL)) temp |= 0x10;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x00,temp);
PhaseIndex = 0x01; /* SiS_PALPhase */
TimingPoint = SiS_Pr->SiS_PALTiming;
newtvphase = false;
if( (SiS_Pr->SiS_VBType & VB_SIS30xBLV) &&
( (!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) ||
(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) ) ) {
newtvphase = true;
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
TimingPoint = SiS_Pr->SiS_HiTVExtTiming;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
TimingPoint = SiS_Pr->SiS_HiTVSt2Timing;
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) {
TimingPoint = SiS_Pr->SiS_HiTVSt1Timing;
}
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
i = 0;
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) i = 2;
else if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) i = 1;
TimingPoint = &SiS_YPbPrTable[i][0];
PhaseIndex = 0x00; /* SiS_NTSCPhase */
} else if(SiS_Pr->SiS_TVMode & TVSetPAL) {
if(newtvphase) PhaseIndex = 0x09; /* SiS_PALPhase2 */
} else {
TimingPoint = SiS_Pr->SiS_NTSCTiming;
PhaseIndex = (SiS_Pr->SiS_TVMode & TVSetNTSCJ) ? 0x01 : 0x00; /* SiS_PALPhase : SiS_NTSCPhase */
if(newtvphase) PhaseIndex += 8; /* SiS_PALPhase2 : SiS_NTSCPhase2 */
}
if(SiS_Pr->SiS_TVMode & (TVSetPALM | TVSetPALN)) {
PhaseIndex = (SiS_Pr->SiS_TVMode & TVSetPALM) ? 0x02 : 0x03; /* SiS_PALMPhase : SiS_PALNPhase */
if(newtvphase) PhaseIndex += 8; /* SiS_PALMPhase2 : SiS_PALNPhase2 */
}
if(SiS_Pr->SiS_TVMode & TVSetNTSC1024) {
if(SiS_Pr->SiS_TVMode & TVSetPALM) {
PhaseIndex = 0x05; /* SiS_SpecialPhaseM */
} else if(SiS_Pr->SiS_TVMode & TVSetNTSCJ) {
PhaseIndex = 0x11; /* SiS_SpecialPhaseJ */
} else {
PhaseIndex = 0x10; /* SiS_SpecialPhase */
}
}
for(i = 0x31, j = 0; i <= 0x34; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS_TVPhase[(PhaseIndex * 4) + j]);
}
for(i = 0x01, j = 0; i <= 0x2D; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,TimingPoint[j]);
}
for(i = 0x39; i <= 0x45; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,TimingPoint[j]);
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(SiS_Pr->SiS_ModeType != ModeText) {
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x3A,0x1F);
}
}
SiS_SetRegOR(SiS_Pr->SiS_Part2Port,0x0A,SiS_Pr->SiS_NewFlickerMode);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x35,SiS_Pr->SiS_RY1COE);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x36,SiS_Pr->SiS_RY2COE);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x37,SiS_Pr->SiS_RY3COE);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x38,SiS_Pr->SiS_RY4COE);
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) tempax = 950;
else if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) tempax = 680;
else if(SiS_Pr->SiS_TVMode & TVSetPAL) tempax = 520;
else tempax = 440; /* NTSC, YPbPr 525 */
if( ((SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) && (SiS_Pr->SiS_VDE <= tempax)) ||
( (SiS_Pr->SiS_VBInfo & SetCRT2ToTVNoHiVision) &&
((SiS_Pr->SiS_VGAHDE == 1024) || (SiS_Pr->SiS_VDE <= tempax)) ) ) {
tempax -= SiS_Pr->SiS_VDE;
tempax >>= 1;
if(!(SiS_Pr->SiS_TVMode & (TVSetYPbPr525p | TVSetYPbPr750p))) {
tempax >>= 1;
}
tempax &= 0x00ff;
temp = tempax + (unsigned short)TimingPoint[0];
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,temp);
temp = tempax + (unsigned short)TimingPoint[1];
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,temp);
if((SiS_Pr->SiS_VBInfo & SetCRT2ToTVNoYPbPrHiVision) && (SiS_Pr->SiS_VGAHDE >= 1024)) {
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,0x1b);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,0x54);
} else {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,0x17);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,0x1d);
}
}
}
tempcx = SiS_Pr->SiS_HT;
if(SiS_IsDualLink(SiS_Pr)) tempcx >>= 1;
tempcx--;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) tempcx--;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x1B,tempcx);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1D,0xF0,((tempcx >> 8) & 0x0f));
tempcx = SiS_Pr->SiS_HT >> 1;
if(SiS_IsDualLink(SiS_Pr)) tempcx >>= 1;
tempcx += 7;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) tempcx -= 4;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x22,0x0F,((tempcx << 4) & 0xf0));
tempbx = TimingPoint[j] | (TimingPoint[j+1] << 8);
tempbx += tempcx;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x24,tempbx);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x25,0x0F,((tempbx >> 4) & 0xf0));
tempbx += 8;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
tempbx -= 4;
tempcx = tempbx;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x29,0x0F,((tempbx << 4) & 0xf0));
j += 2;
tempcx += (TimingPoint[j] | (TimingPoint[j+1] << 8));
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x27,tempcx);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x28,0x0F,((tempcx >> 4) & 0xf0));
tempcx += 8;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) tempcx -= 4;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x2A,0x0F,((tempcx << 4) & 0xf0));
tempcx = SiS_Pr->SiS_HT >> 1;
if(SiS_IsDualLink(SiS_Pr)) tempcx >>= 1;
j += 2;
tempcx -= (TimingPoint[j] | ((TimingPoint[j+1]) << 8));
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x2D,0x0F,((tempcx << 4) & 0xf0));
tempcx -= 11;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) {
tempcx = SiS_GetVGAHT2(SiS_Pr) - 1;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x2E,tempcx);
tempbx = SiS_Pr->SiS_VDE;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->SiS_VGAVDE == 360) tempbx = 746;
if(SiS_Pr->SiS_VGAVDE == 375) tempbx = 746;
if(SiS_Pr->SiS_VGAVDE == 405) tempbx = 853;
} else if( (SiS_Pr->SiS_VBInfo & SetCRT2ToTV) &&
(!(SiS_Pr->SiS_TVMode & (TVSetYPbPr525p|TVSetYPbPr750p))) ) {
tempbx >>= 1;
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) {
if((ModeNo <= 0x13) && (crt2crtc == 1)) tempbx++;
} else if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
if(SiS_Pr->SiS_ModeType <= ModeVGA) {
if(crt2crtc == 4) tempbx++;
}
}
}
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
if((ModeNo == 0x2f) || (ModeNo == 0x5d) || (ModeNo == 0x5e)) tempbx++;
}
if(!(SiS_Pr->SiS_TVMode & TVSetPAL)) {
if(ModeNo == 0x03) tempbx++; /* From 1.10.7w - doesn't make sense */
}
}
}
tempbx -= 2;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x2F,tempbx);
temp = (tempcx >> 8) & 0x0F;
temp |= ((tempbx >> 2) & 0xC0);
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToSVIDEO | SetCRT2ToAVIDEO)) {
temp |= 0x10;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToAVIDEO) temp |= 0x20;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x30,temp);
if(SiS_Pr->SiS_VBType & VB_SISPART4OVERFLOW) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x10,0xdf,((tempbx & 0x0400) >> 5));
}
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
tempbx = SiS_Pr->SiS_VDE;
if( (SiS_Pr->SiS_VBInfo & SetCRT2ToTV) &&
(!(SiS_Pr->SiS_TVMode & (TVSetYPbPr525p | TVSetYPbPr750p))) ) {
tempbx >>= 1;
}
tempbx -= 3;
temp = ((tempbx >> 3) & 0x60) | 0x18;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x46,temp);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x47,tempbx);
if(SiS_Pr->SiS_VBType & VB_SISPART4OVERFLOW) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x10,0xbf,((tempbx & 0x0400) >> 4));
}
}
tempbx = 0;
if(!(modeflag & HalfDCLK)) {
if(SiS_Pr->SiS_VGAHDE >= SiS_Pr->SiS_HDE) {
tempax = 0;
tempbx |= 0x20;
}
}
tempch = tempcl = 0x01;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(SiS_Pr->SiS_VGAHDE >= 960) {
if((!(modeflag & HalfDCLK)) || (SiS_Pr->ChipType < SIS_315H)) {
tempcl = 0x20;
if(SiS_Pr->SiS_VGAHDE >= 1280) {
tempch = 20;
tempbx &= ~0x20;
} else {
tempch = 25; /* OK */
}
}
}
}
if(!(tempbx & 0x20)) {
if(modeflag & HalfDCLK) tempcl <<= 1;
longtemp = ((SiS_Pr->SiS_VGAHDE * tempch) / tempcl) << 13;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) longtemp <<= 3;
tempax = longtemp / SiS_Pr->SiS_HDE;
if(longtemp % SiS_Pr->SiS_HDE) tempax++;
tempbx |= ((tempax >> 8) & 0x1F);
tempcx = tempax >> 13;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x44,tempax);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x45,0xC0,tempbx);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
tempcx &= 0x07;
if(tempbx & 0x20) tempcx = 0;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x46,0xF8,tempcx);
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
tempbx = 0x0382;
tempcx = 0x007e;
} else {
tempbx = 0x0369;
tempcx = 0x0061;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x4B,tempbx);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x4C,tempcx);
temp = (tempcx & 0x0300) >> 6;
temp |= ((tempbx >> 8) & 0x03);
if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
temp |= 0x10;
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) temp |= 0x20;
else if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) temp |= 0x40;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x4D,temp);
temp = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x43);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x43,(temp - 3));
SiS_SetTVSpecial(SiS_Pr, ModeNo);
if(SiS_Pr->SiS_VBType & VB_SIS30xCLV) {
temp = 0;
if(SiS_Pr->SiS_TVMode & TVSetPALM) temp = 8;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x4e,0xf7,temp);
}
}
if(SiS_Pr->SiS_TVMode & TVSetPALM) {
if(!(SiS_Pr->SiS_TVMode & TVSetNTSC1024)) {
temp = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x01);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,(temp - 1));
}
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x00,0xEF);
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x0B,0x00);
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) return;
/* From here: Part2 LCD setup */
tempbx = SiS_Pr->SiS_HDE;
if(SiS_IsDualLink(SiS_Pr)) tempbx >>= 1;
tempbx--; /* RHACTE = HDE - 1 */
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x2C,tempbx);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x2B,0x0F,((tempbx >> 4) & 0xf0));
temp = 0x01;
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) {
if(SiS_Pr->SiS_ModeType == ModeEGA) {
if(SiS_Pr->SiS_VGAHDE >= 1024) {
temp = 0x02;
if(SiS_Pr->SiS_SetFlag & LCDVESATiming) {
temp = 0x01;
}
}
}
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x0B,temp);
tempbx = SiS_Pr->SiS_VDE - 1;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x03,tempbx);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x0C,0xF8,((tempbx >> 8) & 0x07));
tempcx = SiS_Pr->SiS_VT - 1;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x19,tempcx);
temp = (tempcx >> 3) & 0xE0;
if(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit) {
/* Enable dithering; only do this for 32bpp mode */
if(SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0x01) {
temp |= 0x10;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1A,0x0f,temp);
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x09,0xF0);
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x0A,0xF0);
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x17,0xFB);
SiS_SetRegAND(SiS_Pr->SiS_Part2Port,0x18,0xDF);
#ifdef CONFIG_FB_SIS_315
if(SiS_GetCRT2Part2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex,
&CRT2Index, &resindex)) {
switch(CRT2Index) {
case 206: CRT2Part2Ptr = SiS310_CRT2Part2_Asus1024x768_3; break;
default:
case 200: CRT2Part2Ptr = SiS_Pr->SiS_CRT2Part2_1024x768_1; break;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x01,0x80,(CRT2Part2Ptr+resindex)->CR[0]);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x02,0x80,(CRT2Part2Ptr+resindex)->CR[1]);
for(i = 2, j = 0x04; j <= 0x06; i++, j++ ) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,j,(CRT2Part2Ptr+resindex)->CR[i]);
}
for(j = 0x1c; j <= 0x1d; i++, j++ ) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,j,(CRT2Part2Ptr+resindex)->CR[i]);
}
for(j = 0x1f; j <= 0x21; i++, j++ ) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,j,(CRT2Part2Ptr+resindex)->CR[i]);
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x23,(CRT2Part2Ptr+resindex)->CR[10]);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x25,0x0f,(CRT2Part2Ptr+resindex)->CR[11]);
SiS_SetGroup2_Tail(SiS_Pr, ModeNo);
} else {
#endif
/* Checked for 1024x768, 1280x1024, 1400x1050, 1600x1200 */
/* Clevo dual-link 1024x768 */
/* Compaq 1280x1024 has HT 1696 sometimes (calculation OK, if given HT is correct) */
/* Acer: OK, but uses different setting for VESA timing at 640/800/1024 and 640x400 */
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
if((SiS_Pr->SiS_LCDInfo & LCDPass11) || (SiS_Pr->PanelYRes == SiS_Pr->SiS_VDE)) {
tempbx = SiS_Pr->SiS_VDE - 1;
tempcx = SiS_Pr->SiS_VT - 1;
} else {
tempbx = SiS_Pr->SiS_VDE + ((SiS_Pr->PanelYRes - SiS_Pr->SiS_VDE) / 2);
tempcx = SiS_Pr->SiS_VT - ((SiS_Pr->PanelYRes - SiS_Pr->SiS_VDE) / 2);
}
} else {
tempbx = SiS_Pr->PanelYRes;
tempcx = SiS_Pr->SiS_VT;
tempax = 1;
if(SiS_Pr->PanelYRes != SiS_Pr->SiS_VDE) {
tempax = SiS_Pr->PanelYRes;
/* if(SiS_Pr->SiS_VGAVDE == 525) tempax += 0x3c; */ /* 651+301C */
if(SiS_Pr->PanelYRes < SiS_Pr->SiS_VDE) {
tempax = tempcx = 0;
} else {
tempax -= SiS_Pr->SiS_VDE;
}
tempax >>= 1;
}
tempcx -= tempax; /* lcdvdes */
tempbx -= tempax; /* lcdvdee */
}
/* Non-expanding: lcdvdes = tempcx = VT-1; lcdvdee = tempbx = VDE-1 */
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x05,tempcx); /* lcdvdes */
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x06,tempbx); /* lcdvdee */
temp = (tempbx >> 5) & 0x38;
temp |= ((tempcx >> 8) & 0x07);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x02,temp);
tempax = SiS_Pr->SiS_VDE;
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (!(SiS_Pr->SiS_LCDInfo & LCDPass11))) {
tempax = SiS_Pr->PanelYRes;
}
tempcx = (SiS_Pr->SiS_VT - tempax) >> 4;
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (!(SiS_Pr->SiS_LCDInfo & LCDPass11))) {
if(SiS_Pr->PanelYRes != SiS_Pr->SiS_VDE) {
tempcx = (SiS_Pr->SiS_VT - tempax) / 10;
}
}
tempbx = ((SiS_Pr->SiS_VT + SiS_Pr->SiS_VDE) >> 1) - 1;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
if(SiS_Pr->PanelYRes != SiS_Pr->SiS_VDE) {
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) { /* ? */
tempax = SiS_Pr->SiS_VT - SiS_Pr->PanelYRes;
if(tempax % 4) { tempax >>= 2; tempax++; }
else { tempax >>= 2; }
tempbx -= (tempax - 1);
} else {
tempbx -= 10;
if(tempbx <= SiS_Pr->SiS_VDE) tempbx = SiS_Pr->SiS_VDE + 1;
}
}
}
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
tempbx++;
if((!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) || (crt2crtc == 6)) {
if(SiS_Pr->SiS_SetFlag & LCDVESATiming) {
tempbx = 770;
tempcx = 3;
}
}
}
/* non-expanding: lcdvrs = ((VT + VDE) / 2) - 10 */
if(SiS_Pr->UseCustomMode) {
tempbx = SiS_Pr->CVSyncStart;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x04,tempbx); /* lcdvrs */
temp = (tempbx >> 4) & 0xF0;
tempbx += (tempcx + 1);
temp |= (tempbx & 0x0F);
if(SiS_Pr->UseCustomMode) {
temp &= 0xf0;
temp |= (SiS_Pr->CVSyncEnd & 0x0f);
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x01,temp);
#ifdef CONFIG_FB_SIS_300
SiS_Group2LCDSpecial(SiS_Pr, ModeNo, crt2crtc);
#endif
bridgeoffset = 7;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) bridgeoffset += 2;
if(SiS_Pr->SiS_VBType & VB_SIS30xCLV) bridgeoffset += 2; /* OK for Averatec 1280x800 (301C) */
if(SiS_IsDualLink(SiS_Pr)) bridgeoffset++;
else if(SiS_Pr->SiS_VBType & VB_SIS302LV) bridgeoffset++; /* OK for Asus A4L 1280x800 */
/* Higher bridgeoffset shifts to the LEFT */
temp = 0;
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (!(SiS_Pr->SiS_LCDInfo & LCDPass11))) {
if(SiS_Pr->PanelXRes != SiS_Pr->SiS_HDE) {
temp = SiS_Pr->SiS_HT - ((SiS_Pr->PanelXRes - SiS_Pr->SiS_HDE) / 2);
if(SiS_IsDualLink(SiS_Pr)) temp >>= 1;
}
}
temp += bridgeoffset;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x1F,temp); /* lcdhdes */
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x20,0x0F,((temp >> 4) & 0xf0));
tempcx = SiS_Pr->SiS_HT;
tempax = tempbx = SiS_Pr->SiS_HDE;
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (!(SiS_Pr->SiS_LCDInfo & LCDPass11))) {
if(SiS_Pr->PanelXRes != SiS_Pr->SiS_HDE) {
tempax = SiS_Pr->PanelXRes;
tempbx = SiS_Pr->PanelXRes - ((SiS_Pr->PanelXRes - SiS_Pr->SiS_HDE) / 2);
}
}
if(SiS_IsDualLink(SiS_Pr)) {
tempcx >>= 1;
tempbx >>= 1;
tempax >>= 1;
}
tempbx += bridgeoffset;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x23,tempbx); /* lcdhdee */
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x25,0xF0,((tempbx >> 8) & 0x0f));
tempcx = (tempcx - tempax) >> 2;
tempbx += tempcx;
push2 = tempbx;
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) {
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
if(SiS_Pr->SiS_LCDInfo & LCDPass11) {
if(SiS_Pr->SiS_HDE == 1280) tempbx = (tempbx & 0xff00) | 0x47;
}
}
}
if(SiS_Pr->UseCustomMode) {
tempbx = SiS_Pr->CHSyncStart;
if(modeflag & HalfDCLK) tempbx <<= 1;
if(SiS_IsDualLink(SiS_Pr)) tempbx >>= 1;
tempbx += bridgeoffset;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x1C,tempbx); /* lcdhrs */
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1D,0x0F,((tempbx >> 4) & 0xf0));
tempbx = push2;
tempcx <<= 1;
if((SiS_Pr->SiS_LCDInfo & DontExpandLCD) && (!(SiS_Pr->SiS_LCDInfo & LCDPass11))) {
if(SiS_Pr->PanelXRes != SiS_Pr->SiS_HDE) tempcx >>= 2;
}
tempbx += tempcx;
if(SiS_Pr->UseCustomMode) {
tempbx = SiS_Pr->CHSyncEnd;
if(modeflag & HalfDCLK) tempbx <<= 1;
if(SiS_IsDualLink(SiS_Pr)) tempbx >>= 1;
tempbx += bridgeoffset;
}
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x21,tempbx); /* lcdhre */
SiS_SetGroup2_Tail(SiS_Pr, ModeNo);
#ifdef CONFIG_FB_SIS_300
SiS_Set300Part2Regs(SiS_Pr, ModeIdIndex, RefreshRateTableIndex, ModeNo);
#endif
#ifdef CONFIG_FB_SIS_315
} /* CRT2-LCD from table */
#endif
}
/*********************************************/
/* SET PART 3 REGISTER GROUP */
/*********************************************/
static void
SiS_SetGroup3(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short i;
const unsigned char *tempdi;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) return;
#ifndef SIS_CP
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x00,0x00);
#else
SIS_CP_INIT301_CP
#endif
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x13,0xFA);
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x14,0xC8);
} else {
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x13,0xF5);
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x14,0xB7);
}
if(SiS_Pr->SiS_TVMode & TVSetPALM) {
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x13,0xFA);
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x14,0xC8);
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x3D,0xA8);
}
tempdi = NULL;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
tempdi = SiS_Pr->SiS_HiTVGroup3Data;
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) {
tempdi = SiS_Pr->SiS_HiTVGroup3Simu;
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) {
if(!(SiS_Pr->SiS_TVMode & TVSetYPbPr525i)) {
tempdi = SiS_HiTVGroup3_1;
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) tempdi = SiS_HiTVGroup3_2;
}
}
if(tempdi) {
for(i=0; i<=0x3E; i++) {
SiS_SetReg(SiS_Pr->SiS_Part3Port,i,tempdi[i]);
}
if(SiS_Pr->SiS_VBType & VB_SIS30xCLV) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) {
SiS_SetReg(SiS_Pr->SiS_Part3Port,0x28,0x3f);
}
}
}
#ifdef SIS_CP
SIS_CP_INIT301_CP2
#endif
}
/*********************************************/
/* SET PART 4 REGISTER GROUP */
/*********************************************/
#ifdef CONFIG_FB_SIS_315
#if 0
static void
SiS_ShiftXPos(struct SiS_Private *SiS_Pr, int shift)
{
unsigned short temp, temp1, temp2;
temp1 = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x1f);
temp2 = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x20);
temp = (unsigned short)((int)((temp1 | ((temp2 & 0xf0) << 4))) + shift);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x1f,temp);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x20,0x0f,((temp >> 4) & 0xf0));
temp = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x2b) & 0x0f;
temp = (unsigned short)((int)(temp) + shift);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x2b,0xf0,(temp & 0x0f));
temp1 = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x43);
temp2 = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x42);
temp = (unsigned short)((int)((temp1 | ((temp2 & 0xf0) << 4))) + shift);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x43,temp);
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x42,0x0f,((temp >> 4) & 0xf0));
}
#endif
static void
SiS_SetGroup4_C_ELV(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short temp, temp1;
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
if(!(SiS_Pr->SiS_VBType & VB_SIS30xCLV)) return;
if(!(SiS_Pr->SiS_VBInfo & (SetCRT2ToHiVision | SetCRT2ToYPbPr525750))) return;
if(SiS_Pr->ChipType >= XGI_20) return;
if((SiS_Pr->ChipType >= SIS_661) && (SiS_Pr->SiS_ROMNew)) {
if(!(ROMAddr[0x61] & 0x04)) return;
}
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x3a,0x08);
temp = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x3a);
if(!(temp & 0x01)) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x3a,0xdf);
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x25,0xfc);
if((SiS_Pr->ChipType < SIS_661) && (!(SiS_Pr->SiS_ROMNew))) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x25,0xf8);
}
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x0f,0xfb);
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) temp = 0x0000;
else if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) temp = 0x0002;
else if(SiS_Pr->SiS_TVMode & TVSetHiVision) temp = 0x0400;
else temp = 0x0402;
if((SiS_Pr->ChipType >= SIS_661) || (SiS_Pr->SiS_ROMNew)) {
temp1 = 0;
if(SiS_Pr->SiS_TVMode & TVAspect43) temp1 = 4;
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x0f,0xfb,temp1);
if(SiS_Pr->SiS_TVMode & TVAspect43LB) temp |= 0x01;
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x26,0x7c,(temp & 0xff));
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x3a,0xfb,(temp >> 8));
if(ModeNo > 0x13) {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x39,0xfd);
}
} else {
temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x3b) & 0x03;
if(temp1 == 0x01) temp |= 0x01;
if(temp1 == 0x03) temp |= 0x04; /* ? why not 0x10? */
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x26,0xf8,(temp & 0xff));
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x3a,0xfb,(temp >> 8));
if(ModeNo > 0x13) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x3b,0xfd);
}
}
#if 0
if(SiS_Pr->ChipType >= SIS_661) { /* ? */
if(SiS_Pr->SiS_TVMode & TVAspect43) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) {
if(resinfo == SIS_RI_1024x768) {
SiS_ShiftXPos(SiS_Pr, 97);
} else {
SiS_ShiftXPos(SiS_Pr, 111);
}
} else if(SiS_Pr->SiS_TVMode & TVSetHiVision) {
SiS_ShiftXPos(SiS_Pr, 136);
}
}
}
#endif
}
}
#endif
static void
SiS_SetCRT2VCLK(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short vclkindex, temp, reg1, reg2;
if(SiS_Pr->UseCustomMode) {
reg1 = SiS_Pr->CSR2B;
reg2 = SiS_Pr->CSR2C;
} else {
vclkindex = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
reg1 = SiS_Pr->SiS_VBVCLKData[vclkindex].Part4_A;
reg2 = SiS_Pr->SiS_VBVCLKData[vclkindex].Part4_B;
}
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(SiS_Pr->SiS_TVMode & (TVSetNTSC1024 | TVSet525p1024)) {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,0x57);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0b,0x46);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x1f,0xf6);
} else {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,reg1);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0b,reg2);
}
} else {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,0x01);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0b,reg2);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,reg1);
}
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x12,0x00);
temp = 0x08;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC) temp |= 0x20;
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x12,temp);
}
static void
SiS_SetDualLinkEtc(struct SiS_Private *SiS_Pr)
{
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_VBType & VB_SISDUALLINK) {
if((SiS_CRT2IsLCD(SiS_Pr)) ||
(SiS_IsVAMode(SiS_Pr))) {
if(SiS_Pr->SiS_LCDInfo & LCDDualLink) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x27,0x2c);
} else {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x27,~0x20);
}
}
}
}
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x2a,0x00);
#ifdef SET_EMI
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x30,0x0c);
#endif
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x34,0x10);
}
}
static void
SiS_SetGroup4(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short tempax, tempcx, tempbx, modeflag, temp, resinfo;
unsigned int tempebx, tempeax, templong;
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
resinfo = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ResInfo;
} else if(SiS_Pr->UseCustomMode) {
modeflag = SiS_Pr->CModeFlag;
resinfo = 0;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x24,0x0e);
}
}
}
if(SiS_Pr->SiS_VBType & (VB_SIS30xCLV | VB_SIS302LV)) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x10,0x9f);
}
}
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_SetDualLinkEtc(SiS_Pr);
return;
}
}
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x13,SiS_Pr->SiS_RVBHCFACT);
tempbx = SiS_Pr->SiS_RVBHCMAX;
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x14,tempbx);
temp = (tempbx >> 1) & 0x80;
tempcx = SiS_Pr->SiS_VGAHT - 1;
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x16,tempcx);
temp |= ((tempcx >> 5) & 0x78);
tempcx = SiS_Pr->SiS_VGAVT - 1;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) tempcx -= 5;
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x17,tempcx);
temp |= ((tempcx >> 8) & 0x07);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x15,temp);
tempbx = SiS_Pr->SiS_VGAHDE;
if(modeflag & HalfDCLK) tempbx >>= 1;
if(SiS_IsDualLink(SiS_Pr)) tempbx >>= 1;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
temp = 0;
if(tempbx > 800) temp = 0x60;
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
temp = 0;
if(tempbx > 1024) temp = 0xC0;
else if(tempbx >= 960) temp = 0xA0;
} else if(SiS_Pr->SiS_TVMode & (TVSetYPbPr525p | TVSetYPbPr750p)) {
temp = 0;
if(tempbx >= 1280) temp = 0x40;
else if(tempbx >= 1024) temp = 0x20;
} else {
temp = 0x80;
if(tempbx >= 1024) temp = 0xA0;
}
temp |= SiS_Pr->Init_P4_0E;
if(SiS_Pr->SiS_VBType & VB_SIS301) {
if(SiS_Pr->SiS_LCDResInfo != Panel_1280x1024) {
temp &= 0xf0;
temp |= 0x0A;
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x0E,0x10,temp);
tempeax = SiS_Pr->SiS_VGAVDE;
tempebx = SiS_Pr->SiS_VDE;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
if(!(temp & 0xE0)) tempebx >>=1;
}
tempcx = SiS_Pr->SiS_RVBHRS;
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x18,tempcx);
tempcx >>= 8;
tempcx |= 0x40;
if(tempeax <= tempebx) {
tempcx ^= 0x40;
} else {
tempeax -= tempebx;
}
tempeax *= (256 * 1024);
templong = tempeax % tempebx;
tempeax /= tempebx;
if(templong) tempeax++;
temp = (unsigned short)(tempeax & 0x000000FF);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x1B,temp);
temp = (unsigned short)((tempeax & 0x0000FF00) >> 8);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x1A,temp);
temp = (unsigned short)((tempeax >> 12) & 0x70); /* sic! */
temp |= (tempcx & 0x4F);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x19,temp);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x1C,0x28);
/* Calc Linebuffer max address and set/clear decimode */
tempbx = 0;
if(SiS_Pr->SiS_TVMode & (TVSetHiVision | TVSetYPbPr750p)) tempbx = 0x08;
tempax = SiS_Pr->SiS_VGAHDE;
if(modeflag & HalfDCLK) tempax >>= 1;
if(SiS_IsDualLink(SiS_Pr)) tempax >>= 1;
if(tempax > 800) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
tempax -= 800;
} else {
tempbx = 0x08;
if(tempax == 960) tempax *= 25; /* Correct */
else if(tempax == 1024) tempax *= 25;
else tempax *= 20;
temp = tempax % 32;
tempax /= 32;
if(temp) tempax++;
tempax++;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(resinfo == SIS_RI_1024x768 ||
resinfo == SIS_RI_1024x576 ||
resinfo == SIS_RI_1280x1024 ||
resinfo == SIS_RI_1280x720) {
/* Otherwise white line or garbage at right edge */
tempax = (tempax & 0xff00) | 0x20;
}
}
}
}
tempax--;
temp = ((tempax >> 4) & 0x30) | tempbx;
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x1D,tempax);
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x1E,temp);
temp = 0x0036; tempbx = 0xD0;
if((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->SiS_VBType & VB_SISLVDS)) {
temp = 0x0026; tempbx = 0xC0; /* See En/DisableBridge() */
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
if(!(SiS_Pr->SiS_TVMode & (TVSetNTSC1024 | TVSetHiVision | TVSetYPbPr750p | TVSetYPbPr525p))) {
temp |= 0x01;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
if(!(SiS_Pr->SiS_TVMode & TVSetTVSimuMode)) {
temp &= ~0x01;
}
}
}
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x1F,tempbx,temp);
tempbx = SiS_Pr->SiS_HT >> 1;
if(SiS_IsDualLink(SiS_Pr)) tempbx >>= 1;
tempbx -= 2;
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x22,tempbx);
temp = (tempbx >> 5) & 0x38;
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x21,0xC0,temp);
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x24,0x0e);
/* LCD-too-dark-error-source, see FinalizeLCD() */
}
}
SiS_SetDualLinkEtc(SiS_Pr);
} /* 301B */
SiS_SetCRT2VCLK(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
/*********************************************/
/* SET PART 5 REGISTER GROUP */
/*********************************************/
static void
SiS_SetGroup5(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) return;
if(SiS_Pr->SiS_ModeType == ModeVGA) {
if(!(SiS_Pr->SiS_VBInfo & (SetInSlaveMode | LoadDACFlag))) {
SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x20);
SiS_LoadDAC(SiS_Pr, ModeNo, ModeIdIndex);
}
}
}
/*********************************************/
/* MODIFY CRT1 GROUP FOR SLAVE MODE */
/*********************************************/
static bool
SiS_GetLVDSCRT1Ptr(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex, unsigned short *ResIndex,
unsigned short *DisplayType)
{
unsigned short modeflag = 0;
bool checkhd = true;
/* Pass 1:1 not supported here */
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
(*ResIndex) = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
(*ResIndex) = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
}
(*ResIndex) &= 0x3F;
if((SiS_Pr->SiS_IF_DEF_CH70xx) && (SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) {
(*DisplayType) = 80;
if((SiS_Pr->SiS_TVMode & TVSetPAL) && (!(SiS_Pr->SiS_TVMode & TVSetPALM))) {
(*DisplayType) = 82;
if(SiS_Pr->SiS_ModeType > ModeVGA) {
if(SiS_Pr->SiS_CHSOverScan) (*DisplayType) = 84;
}
}
if((*DisplayType) != 84) {
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) (*DisplayType)++;
}
} else {
(*DisplayType = 0);
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_320x240_1: (*DisplayType) = 50;
checkhd = false;
break;
case Panel_320x240_2: (*DisplayType) = 14;
break;
case Panel_320x240_3: (*DisplayType) = 18;
break;
case Panel_640x480: (*DisplayType) = 10;
break;
case Panel_1024x600: (*DisplayType) = 26;
break;
default: return true;
}
if(checkhd) {
if(modeflag & HalfDCLK) (*DisplayType)++;
}
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x600) {
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) (*DisplayType) += 2;
}
}
return true;
}
static void
SiS_ModCRT1CRTC(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short tempah, i, modeflag, j, ResIndex, DisplayType;
const struct SiS_LVDSCRT1Data *LVDSCRT1Ptr=NULL;
static const unsigned short CRIdx[] = {
0x00, 0x02, 0x03, 0x04, 0x05, 0x06,
0x07, 0x10, 0x11, 0x15, 0x16
};
if((SiS_Pr->SiS_CustomT == CUT_BARCO1366) ||
(SiS_Pr->SiS_CustomT == CUT_BARCO1024) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL848) ||
(SiS_Pr->SiS_CustomT == CUT_PANEL856) )
return;
if(SiS_Pr->SiS_IF_DEF_LVDS) {
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) return;
}
} else if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) return;
} else return;
if(SiS_Pr->SiS_LCDInfo & LCDPass11) return;
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_SetFlag & SetDOSMode) return;
}
if(!(SiS_GetLVDSCRT1Ptr(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex,
&ResIndex, &DisplayType))) {
return;
}
switch(DisplayType) {
case 50: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT1320x240_1; break; /* xSTN */
case 14: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT1320x240_2; break; /* xSTN */
case 15: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT1320x240_2_H; break; /* xSTN */
case 18: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT1320x240_3; break; /* xSTN */
case 19: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT1320x240_3_H; break; /* xSTN */
case 10: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT1640x480_1; break;
case 11: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT1640x480_1_H; break;
#if 0 /* Works better with calculated numbers */
case 26: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT11024x600_1; break;
case 27: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT11024x600_1_H; break;
case 28: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT11024x600_2; break;
case 29: LVDSCRT1Ptr = SiS_Pr->SiS_LVDSCRT11024x600_2_H; break;
#endif
case 80: LVDSCRT1Ptr = SiS_Pr->SiS_CHTVCRT1UNTSC; break;
case 81: LVDSCRT1Ptr = SiS_Pr->SiS_CHTVCRT1ONTSC; break;
case 82: LVDSCRT1Ptr = SiS_Pr->SiS_CHTVCRT1UPAL; break;
case 83: LVDSCRT1Ptr = SiS_Pr->SiS_CHTVCRT1OPAL; break;
case 84: LVDSCRT1Ptr = SiS_Pr->SiS_CHTVCRT1SOPAL; break;
}
if(LVDSCRT1Ptr) {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
for(i = 0; i <= 10; i++) {
tempah = (LVDSCRT1Ptr + ResIndex)->CR[i];
SiS_SetReg(SiS_Pr->SiS_P3d4,CRIdx[i],tempah);
}
for(i = 0x0A, j = 11; i <= 0x0C; i++, j++) {
tempah = (LVDSCRT1Ptr + ResIndex)->CR[j];
SiS_SetReg(SiS_Pr->SiS_P3c4,i,tempah);
}
tempah = (LVDSCRT1Ptr + ResIndex)->CR[14] & 0xE0;
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0E,0x1f,tempah);
if(ModeNo <= 0x13) modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
else modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
tempah = ((LVDSCRT1Ptr + ResIndex)->CR[14] & 0x01) << 5;
if(modeflag & DoubleScanMode) tempah |= 0x80;
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x09,~0x020,tempah);
} else {
SiS_CalcLCDACRT1Timing(SiS_Pr, ModeNo, ModeIdIndex);
}
}
/*********************************************/
/* SET CRT2 ECLK */
/*********************************************/
static void
SiS_SetCRT2ECLK(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short clkbase, vclkindex = 0;
unsigned char sr2b, sr2c;
if(SiS_Pr->SiS_LCDInfo & LCDPass11) {
SiS_Pr->SiS_SetFlag &= (~ProgrammingCRT2);
if(SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRTVCLK == 2) {
RefreshRateTableIndex--;
}
vclkindex = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex,
RefreshRateTableIndex);
SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
} else {
vclkindex = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex,
RefreshRateTableIndex);
}
sr2b = SiS_Pr->SiS_VCLKData[vclkindex].SR2B;
sr2c = SiS_Pr->SiS_VCLKData[vclkindex].SR2C;
if((SiS_Pr->SiS_CustomT == CUT_BARCO1366) || (SiS_Pr->SiS_CustomT == CUT_BARCO1024)) {
if(SiS_Pr->SiS_UseROM) {
if(ROMAddr[0x220] & 0x01) {
sr2b = ROMAddr[0x227];
sr2c = ROMAddr[0x228];
}
}
}
clkbase = 0x02B;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) {
clkbase += 3;
}
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x31,0x20);
SiS_SetReg(SiS_Pr->SiS_P3c4,clkbase,sr2b);
SiS_SetReg(SiS_Pr->SiS_P3c4,clkbase+1,sr2c);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x31,0x10);
SiS_SetReg(SiS_Pr->SiS_P3c4,clkbase,sr2b);
SiS_SetReg(SiS_Pr->SiS_P3c4,clkbase+1,sr2c);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x31,0x00);
SiS_SetReg(SiS_Pr->SiS_P3c4,clkbase,sr2b);
SiS_SetReg(SiS_Pr->SiS_P3c4,clkbase+1,sr2c);
}
/*********************************************/
/* SET UP CHRONTEL CHIPS */
/*********************************************/
static void
SiS_SetCHTVReg(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex)
{
unsigned short TVType, resindex;
const struct SiS_CHTVRegData *CHTVRegData = NULL;
if(ModeNo <= 0x13)
resindex = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
else
resindex = SiS_Pr->SiS_RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
resindex &= 0x3F;
TVType = 0;
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) TVType += 1;
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
TVType += 2;
if(SiS_Pr->SiS_ModeType > ModeVGA) {
if(SiS_Pr->SiS_CHSOverScan) TVType = 8;
}
if(SiS_Pr->SiS_TVMode & TVSetPALM) {
TVType = 4;
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) TVType += 1;
} else if(SiS_Pr->SiS_TVMode & TVSetPALN) {
TVType = 6;
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) TVType += 1;
}
}
switch(TVType) {
case 0: CHTVRegData = SiS_Pr->SiS_CHTVReg_UNTSC; break;
case 1: CHTVRegData = SiS_Pr->SiS_CHTVReg_ONTSC; break;
case 2: CHTVRegData = SiS_Pr->SiS_CHTVReg_UPAL; break;
case 3: CHTVRegData = SiS_Pr->SiS_CHTVReg_OPAL; break;
case 4: CHTVRegData = SiS_Pr->SiS_CHTVReg_UPALM; break;
case 5: CHTVRegData = SiS_Pr->SiS_CHTVReg_OPALM; break;
case 6: CHTVRegData = SiS_Pr->SiS_CHTVReg_UPALN; break;
case 7: CHTVRegData = SiS_Pr->SiS_CHTVReg_OPALN; break;
case 8: CHTVRegData = SiS_Pr->SiS_CHTVReg_SOPAL; break;
default: CHTVRegData = SiS_Pr->SiS_CHTVReg_OPAL; break;
}
if(SiS_Pr->SiS_IF_DEF_CH70xx == 1) {
#ifdef CONFIG_FB_SIS_300
/* Chrontel 7005 - I assume that it does not come with a 315 series chip */
/* We don't support modes >800x600 */
if (resindex > 5) return;
if(SiS_Pr->SiS_TVMode & TVSetPAL) {
SiS_SetCH700x(SiS_Pr,0x04,0x43); /* 0x40=76uA (PAL); 0x03=15bit non-multi RGB*/
SiS_SetCH700x(SiS_Pr,0x09,0x69); /* Black level for PAL (105)*/
} else {
SiS_SetCH700x(SiS_Pr,0x04,0x03); /* upper nibble=71uA (NTSC), 0x03=15bit non-multi RGB*/
SiS_SetCH700x(SiS_Pr,0x09,0x71); /* Black level for NTSC (113)*/
}
SiS_SetCH700x(SiS_Pr,0x00,CHTVRegData[resindex].Reg[0]); /* Mode register */
SiS_SetCH700x(SiS_Pr,0x07,CHTVRegData[resindex].Reg[1]); /* Start active video register */
SiS_SetCH700x(SiS_Pr,0x08,CHTVRegData[resindex].Reg[2]); /* Position overflow register */
SiS_SetCH700x(SiS_Pr,0x0a,CHTVRegData[resindex].Reg[3]); /* Horiz Position register */
SiS_SetCH700x(SiS_Pr,0x0b,CHTVRegData[resindex].Reg[4]); /* Vertical Position register */
/* Set minimum flicker filter for Luma channel (SR1-0=00),
minimum text enhancement (S3-2=10),
maximum flicker filter for Chroma channel (S5-4=10)
=00101000=0x28 (When reading, S1-0->S3-2, and S3-2->S1-0!)
*/
SiS_SetCH700x(SiS_Pr,0x01,0x28);
/* Set video bandwidth
High bandwidth Luma composite video filter(S0=1)
low bandwidth Luma S-video filter (S2-1=00)
disable peak filter in S-video channel (S3=0)
high bandwidth Chroma Filter (S5-4=11)
=00110001=0x31
*/
SiS_SetCH700x(SiS_Pr,0x03,0xb1); /* old: 3103 */
/* Register 0x3D does not exist in non-macrovision register map
(Maybe this is a macrovision register?)
*/
#ifndef SIS_CP
SiS_SetCH70xx(SiS_Pr,0x3d,0x00);
#endif
/* Register 0x10 only contains 1 writable bit (S0) for sensing,
all other bits a read-only. Macrovision?
*/
SiS_SetCH70xxANDOR(SiS_Pr,0x10,0x00,0x1F);
/* Register 0x11 only contains 3 writable bits (S0-S2) for
contrast enhancement (set to 010 -> gain 1 Yout = 17/16*(Yin-30) )
*/
SiS_SetCH70xxANDOR(SiS_Pr,0x11,0x02,0xF8);
/* Clear DSEN
*/
SiS_SetCH70xxANDOR(SiS_Pr,0x1c,0x00,0xEF);
if(!(SiS_Pr->SiS_TVMode & TVSetPAL)) { /* ---- NTSC ---- */
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) {
if(resindex == 0x04) { /* 640x480 overscan: Mode 16 */
SiS_SetCH70xxANDOR(SiS_Pr,0x20,0x00,0xEF); /* loop filter off */
SiS_SetCH70xxANDOR(SiS_Pr,0x21,0x01,0xFE); /* ACIV on, no need to set FSCI */
} else if(resindex == 0x05) { /* 800x600 overscan: Mode 23 */
SiS_SetCH70xxANDOR(SiS_Pr,0x18,0x01,0xF0); /* 0x18-0x1f: FSCI 469,762,048 */
SiS_SetCH70xxANDOR(SiS_Pr,0x19,0x0C,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1a,0x00,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1b,0x00,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1c,0x00,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1d,0x00,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1e,0x00,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1f,0x00,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x20,0x01,0xEF); /* Loop filter on for mode 23 */
SiS_SetCH70xxANDOR(SiS_Pr,0x21,0x00,0xFE); /* ACIV off, need to set FSCI */
}
} else {
if(resindex == 0x04) { /* ----- 640x480 underscan; Mode 17 */
SiS_SetCH70xxANDOR(SiS_Pr,0x20,0x00,0xEF); /* loop filter off */
SiS_SetCH70xxANDOR(SiS_Pr,0x21,0x01,0xFE);
} else if(resindex == 0x05) { /* ----- 800x600 underscan: Mode 24 */
#if 0
SiS_SetCH70xxANDOR(SiS_Pr,0x18,0x01,0xF0); /* (FSCI was 0x1f1c71c7 - this is for mode 22) */
SiS_SetCH70xxANDOR(SiS_Pr,0x19,0x09,0xF0); /* FSCI for mode 24 is 428,554,851 */
SiS_SetCH70xxANDOR(SiS_Pr,0x1a,0x08,0xF0); /* 198b3a63 */
SiS_SetCH70xxANDOR(SiS_Pr,0x1b,0x0b,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1c,0x04,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1d,0x01,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1e,0x06,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x1f,0x05,0xF0);
SiS_SetCH70xxANDOR(SiS_Pr,0x20,0x00,0xEF); /* loop filter off for mode 24 */
SiS_SetCH70xxANDOR(SiS_Pr,0x21,0x00,0xFE); * ACIV off, need to set FSCI */
#endif /* All alternatives wrong (datasheet wrong?), don't use FSCI */
SiS_SetCH70xxANDOR(SiS_Pr,0x20,0x00,0xEF); /* loop filter off */
SiS_SetCH70xxANDOR(SiS_Pr,0x21,0x01,0xFE);
}
}
} else { /* ---- PAL ---- */
/* We don't play around with FSCI in PAL mode */
SiS_SetCH70xxANDOR(SiS_Pr, 0x20, 0x00, 0xEF); /* loop filter off */
SiS_SetCH70xxANDOR(SiS_Pr, 0x21, 0x01, 0xFE); /* ACIV on */
}
#endif /* 300 */
} else {
/* Chrontel 7019 - assumed that it does not come with a 300 series chip */
#ifdef CONFIG_FB_SIS_315
unsigned short temp;
/* We don't support modes >1024x768 */
if (resindex > 6) return;
temp = CHTVRegData[resindex].Reg[0];
if(SiS_Pr->SiS_TVMode & TVSetNTSCJ) temp |= 0x10;
SiS_SetCH701x(SiS_Pr,0x00,temp);
SiS_SetCH701x(SiS_Pr,0x01,CHTVRegData[resindex].Reg[1]);
SiS_SetCH701x(SiS_Pr,0x02,CHTVRegData[resindex].Reg[2]);
SiS_SetCH701x(SiS_Pr,0x04,CHTVRegData[resindex].Reg[3]);
SiS_SetCH701x(SiS_Pr,0x03,CHTVRegData[resindex].Reg[4]);
SiS_SetCH701x(SiS_Pr,0x05,CHTVRegData[resindex].Reg[5]);
SiS_SetCH701x(SiS_Pr,0x06,CHTVRegData[resindex].Reg[6]);
temp = CHTVRegData[resindex].Reg[7];
if(SiS_Pr->SiS_TVMode & TVSetNTSCJ) temp = 0x66;
SiS_SetCH701x(SiS_Pr,0x07,temp);
SiS_SetCH701x(SiS_Pr,0x08,CHTVRegData[resindex].Reg[8]);
SiS_SetCH701x(SiS_Pr,0x15,CHTVRegData[resindex].Reg[9]);
SiS_SetCH701x(SiS_Pr,0x1f,CHTVRegData[resindex].Reg[10]);
SiS_SetCH701x(SiS_Pr,0x0c,CHTVRegData[resindex].Reg[11]);
SiS_SetCH701x(SiS_Pr,0x0d,CHTVRegData[resindex].Reg[12]);
SiS_SetCH701x(SiS_Pr,0x0e,CHTVRegData[resindex].Reg[13]);
SiS_SetCH701x(SiS_Pr,0x0f,CHTVRegData[resindex].Reg[14]);
SiS_SetCH701x(SiS_Pr,0x10,CHTVRegData[resindex].Reg[15]);
temp = SiS_GetCH701x(SiS_Pr,0x21) & ~0x02;
/* D1 should be set for PAL, PAL-N and NTSC-J,
but I won't do that for PAL unless somebody
tells me to do so. Since the BIOS uses
non-default CIV values and blacklevels,
this might be compensated anyway.
*/
if(SiS_Pr->SiS_TVMode & (TVSetPALN | TVSetNTSCJ)) temp |= 0x02;
SiS_SetCH701x(SiS_Pr,0x21,temp);
#endif /* 315 */
}
#ifdef SIS_CP
SIS_CP_INIT301_CP3
#endif
}
#ifdef CONFIG_FB_SIS_315 /* ----------- 315 series only ---------- */
void
SiS_Chrontel701xBLOn(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
/* Enable Chrontel 7019 LCD panel backlight */
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
if(SiS_Pr->ChipType == SIS_740) {
SiS_SetCH701x(SiS_Pr,0x66,0x65);
} else {
temp = SiS_GetCH701x(SiS_Pr,0x66);
temp |= 0x20;
SiS_SetCH701x(SiS_Pr,0x66,temp);
}
}
}
void
SiS_Chrontel701xBLOff(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
/* Disable Chrontel 7019 LCD panel backlight */
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
temp = SiS_GetCH701x(SiS_Pr,0x66);
temp &= 0xDF;
SiS_SetCH701x(SiS_Pr,0x66,temp);
}
}
static void
SiS_ChrontelPowerSequencing(struct SiS_Private *SiS_Pr)
{
static const unsigned char regtable[] = { 0x67, 0x68, 0x69, 0x6a, 0x6b };
static const unsigned char table1024_740[] = { 0x01, 0x02, 0x01, 0x01, 0x01 };
static const unsigned char table1400_740[] = { 0x01, 0x6e, 0x01, 0x01, 0x01 };
static const unsigned char asus1024_740[] = { 0x19, 0x6e, 0x01, 0x19, 0x09 };
static const unsigned char asus1400_740[] = { 0x19, 0x6e, 0x01, 0x19, 0x09 };
static const unsigned char table1024_650[] = { 0x01, 0x02, 0x01, 0x01, 0x02 };
static const unsigned char table1400_650[] = { 0x01, 0x02, 0x01, 0x01, 0x02 };
const unsigned char *tableptr = NULL;
int i;
/* Set up Power up/down timing */
if(SiS_Pr->ChipType == SIS_740) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(SiS_Pr->SiS_CustomT == CUT_ASUSL3000D) tableptr = asus1024_740;
else tableptr = table1024_740;
} else if((SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200)) {
if(SiS_Pr->SiS_CustomT == CUT_ASUSL3000D) tableptr = asus1400_740;
else tableptr = table1400_740;
} else return;
} else {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
tableptr = table1024_650;
} else if((SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) ||
(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200)) {
tableptr = table1400_650;
} else return;
}
for(i=0; i<5; i++) {
SiS_SetCH701x(SiS_Pr, regtable[i], tableptr[i]);
}
}
static void
SiS_SetCH701xForLCD(struct SiS_Private *SiS_Pr)
{
const unsigned char *tableptr = NULL;
unsigned short tempbh;
int i;
static const unsigned char regtable[] = {
0x1c, 0x5f, 0x64, 0x6f, 0x70, 0x71,
0x72, 0x73, 0x74, 0x76, 0x78, 0x7d, 0x66
};
static const unsigned char table1024_740[] = {
0x60, 0x02, 0x00, 0x07, 0x40, 0xed,
0xa3, 0xc8, 0xc7, 0xac, 0xe0, 0x02, 0x44
};
static const unsigned char table1280_740[] = {
0x60, 0x03, 0x11, 0x00, 0x40, 0xe3,
0xad, 0xdb, 0xf6, 0xac, 0xe0, 0x02, 0x44
};
static const unsigned char table1400_740[] = {
0x60, 0x03, 0x11, 0x00, 0x40, 0xe3,
0xad, 0xdb, 0xf6, 0xac, 0xe0, 0x02, 0x44
};
static const unsigned char table1600_740[] = {
0x60, 0x04, 0x11, 0x00, 0x40, 0xe3,
0xad, 0xde, 0xf6, 0xac, 0x60, 0x1a, 0x44
};
static const unsigned char table1024_650[] = {
0x60, 0x02, 0x00, 0x07, 0x40, 0xed,
0xa3, 0xc8, 0xc7, 0xac, 0x60, 0x02
};
static const unsigned char table1280_650[] = {
0x60, 0x03, 0x11, 0x00, 0x40, 0xe3,
0xad, 0xdb, 0xf6, 0xac, 0xe0, 0x02
};
static const unsigned char table1400_650[] = {
0x60, 0x03, 0x11, 0x00, 0x40, 0xef,
0xad, 0xdb, 0xf6, 0xac, 0x60, 0x02
};
static const unsigned char table1600_650[] = {
0x60, 0x04, 0x11, 0x00, 0x40, 0xe3,
0xad, 0xde, 0xf6, 0xac, 0x60, 0x1a
};
if(SiS_Pr->ChipType == SIS_740) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) tableptr = table1024_740;
else if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) tableptr = table1280_740;
else if(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) tableptr = table1400_740;
else if(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) tableptr = table1600_740;
else return;
} else {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) tableptr = table1024_650;
else if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) tableptr = table1280_650;
else if(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) tableptr = table1400_650;
else if(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) tableptr = table1600_650;
else return;
}
tempbh = SiS_GetCH701x(SiS_Pr,0x74);
if((tempbh == 0xf6) || (tempbh == 0xc7)) {
tempbh = SiS_GetCH701x(SiS_Pr,0x73);
if(tempbh == 0xc8) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) return;
} else if(tempbh == 0xdb) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) return;
if(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) return;
} else if(tempbh == 0xde) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) return;
}
}
if(SiS_Pr->ChipType == SIS_740) tempbh = 0x0d;
else tempbh = 0x0c;
for(i = 0; i < tempbh; i++) {
SiS_SetCH701x(SiS_Pr, regtable[i], tableptr[i]);
}
SiS_ChrontelPowerSequencing(SiS_Pr);
tempbh = SiS_GetCH701x(SiS_Pr,0x1e);
tempbh |= 0xc0;
SiS_SetCH701x(SiS_Pr,0x1e,tempbh);
if(SiS_Pr->ChipType == SIS_740) {
tempbh = SiS_GetCH701x(SiS_Pr,0x1c);
tempbh &= 0xfb;
SiS_SetCH701x(SiS_Pr,0x1c,tempbh);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2d,0x03);
tempbh = SiS_GetCH701x(SiS_Pr,0x64);
tempbh |= 0x40;
SiS_SetCH701x(SiS_Pr,0x64,tempbh);
tempbh = SiS_GetCH701x(SiS_Pr,0x03);
tempbh &= 0x3f;
SiS_SetCH701x(SiS_Pr,0x03,tempbh);
}
}
static void
SiS_ChrontelResetVSync(struct SiS_Private *SiS_Pr)
{
unsigned char temp, temp1;
temp1 = SiS_GetCH701x(SiS_Pr,0x49);
SiS_SetCH701x(SiS_Pr,0x49,0x3e);
temp = SiS_GetCH701x(SiS_Pr,0x47);
temp &= 0x7f; /* Use external VSYNC */
SiS_SetCH701x(SiS_Pr,0x47,temp);
SiS_LongDelay(SiS_Pr, 3);
temp = SiS_GetCH701x(SiS_Pr,0x47);
temp |= 0x80; /* Use internal VSYNC */
SiS_SetCH701x(SiS_Pr,0x47,temp);
SiS_SetCH701x(SiS_Pr,0x49,temp1);
}
static void
SiS_Chrontel701xOn(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
if(SiS_Pr->ChipType == SIS_740) {
temp = SiS_GetCH701x(SiS_Pr,0x1c);
temp |= 0x04; /* Invert XCLK phase */
SiS_SetCH701x(SiS_Pr,0x1c,temp);
}
if(SiS_IsYPbPr(SiS_Pr)) {
temp = SiS_GetCH701x(SiS_Pr,0x01);
temp &= 0x3f;
temp |= 0x80; /* Enable YPrPb (HDTV) */
SiS_SetCH701x(SiS_Pr,0x01,temp);
}
if(SiS_IsChScart(SiS_Pr)) {
temp = SiS_GetCH701x(SiS_Pr,0x01);
temp &= 0x3f;
temp |= 0xc0; /* Enable SCART + CVBS */
SiS_SetCH701x(SiS_Pr,0x01,temp);
}
if(SiS_Pr->ChipType == SIS_740) {
SiS_ChrontelResetVSync(SiS_Pr);
SiS_SetCH701x(SiS_Pr,0x49,0x20); /* Enable TV path */
} else {
SiS_SetCH701x(SiS_Pr,0x49,0x20); /* Enable TV path */
temp = SiS_GetCH701x(SiS_Pr,0x49);
if(SiS_IsYPbPr(SiS_Pr)) {
temp = SiS_GetCH701x(SiS_Pr,0x73);
temp |= 0x60;
SiS_SetCH701x(SiS_Pr,0x73,temp);
}
temp = SiS_GetCH701x(SiS_Pr,0x47);
temp &= 0x7f;
SiS_SetCH701x(SiS_Pr,0x47,temp);
SiS_LongDelay(SiS_Pr, 2);
temp = SiS_GetCH701x(SiS_Pr,0x47);
temp |= 0x80;
SiS_SetCH701x(SiS_Pr,0x47,temp);
}
}
}
static void
SiS_Chrontel701xOff(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
/* Complete power down of LVDS */
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
if(SiS_Pr->ChipType == SIS_740) {
SiS_LongDelay(SiS_Pr, 1);
SiS_GenericDelay(SiS_Pr, 5887);
SiS_SetCH701x(SiS_Pr,0x76,0xac);
SiS_SetCH701x(SiS_Pr,0x66,0x00);
} else {
SiS_LongDelay(SiS_Pr, 2);
temp = SiS_GetCH701x(SiS_Pr,0x76);
temp &= 0xfc;
SiS_SetCH701x(SiS_Pr,0x76,temp);
SiS_SetCH701x(SiS_Pr,0x66,0x00);
}
}
}
static void
SiS_ChrontelResetDB(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
if(SiS_Pr->ChipType == SIS_740) {
temp = SiS_GetCH701x(SiS_Pr,0x4a); /* Version ID */
temp &= 0x01;
if(!temp) {
if(SiS_WeHaveBacklightCtrl(SiS_Pr)) {
temp = SiS_GetCH701x(SiS_Pr,0x49);
SiS_SetCH701x(SiS_Pr,0x49,0x3e);
}
/* Reset Chrontel 7019 datapath */
SiS_SetCH701x(SiS_Pr,0x48,0x10);
SiS_LongDelay(SiS_Pr, 1);
SiS_SetCH701x(SiS_Pr,0x48,0x18);
if(SiS_WeHaveBacklightCtrl(SiS_Pr)) {
SiS_ChrontelResetVSync(SiS_Pr);
SiS_SetCH701x(SiS_Pr,0x49,temp);
}
} else {
/* Clear/set/clear GPIO */
temp = SiS_GetCH701x(SiS_Pr,0x5c);
temp &= 0xef;
SiS_SetCH701x(SiS_Pr,0x5c,temp);
temp = SiS_GetCH701x(SiS_Pr,0x5c);
temp |= 0x10;
SiS_SetCH701x(SiS_Pr,0x5c,temp);
temp = SiS_GetCH701x(SiS_Pr,0x5c);
temp &= 0xef;
SiS_SetCH701x(SiS_Pr,0x5c,temp);
temp = SiS_GetCH701x(SiS_Pr,0x61);
if(!temp) {
SiS_SetCH701xForLCD(SiS_Pr);
}
}
} else { /* 650 */
/* Reset Chrontel 7019 datapath */
SiS_SetCH701x(SiS_Pr,0x48,0x10);
SiS_LongDelay(SiS_Pr, 1);
SiS_SetCH701x(SiS_Pr,0x48,0x18);
}
}
static void
SiS_ChrontelInitTVVSync(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
if(SiS_Pr->ChipType == SIS_740) {
if(SiS_WeHaveBacklightCtrl(SiS_Pr)) {
SiS_ChrontelResetVSync(SiS_Pr);
}
} else {
SiS_SetCH701x(SiS_Pr,0x76,0xaf); /* Power up LVDS block */
temp = SiS_GetCH701x(SiS_Pr,0x49);
temp &= 1;
if(temp != 1) { /* TV block powered? (0 = yes, 1 = no) */
temp = SiS_GetCH701x(SiS_Pr,0x47);
temp &= 0x70;
SiS_SetCH701x(SiS_Pr,0x47,temp); /* enable VSYNC */
SiS_LongDelay(SiS_Pr, 3);
temp = SiS_GetCH701x(SiS_Pr,0x47);
temp |= 0x80;
SiS_SetCH701x(SiS_Pr,0x47,temp); /* disable VSYNC */
}
}
}
static void
SiS_ChrontelDoSomething3(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
unsigned short temp,temp1;
if(SiS_Pr->ChipType == SIS_740) {
temp = SiS_GetCH701x(SiS_Pr,0x61);
if(temp < 1) {
temp++;
SiS_SetCH701x(SiS_Pr,0x61,temp);
}
SiS_SetCH701x(SiS_Pr,0x66,0x45); /* Panel power on */
SiS_SetCH701x(SiS_Pr,0x76,0xaf); /* All power on */
SiS_LongDelay(SiS_Pr, 1);
SiS_GenericDelay(SiS_Pr, 5887);
} else { /* 650 */
temp1 = 0;
temp = SiS_GetCH701x(SiS_Pr,0x61);
if(temp < 2) {
temp++;
SiS_SetCH701x(SiS_Pr,0x61,temp);
temp1 = 1;
}
SiS_SetCH701x(SiS_Pr,0x76,0xac);
temp = SiS_GetCH701x(SiS_Pr,0x66);
temp |= 0x5f;
SiS_SetCH701x(SiS_Pr,0x66,temp);
if(ModeNo > 0x13) {
if(SiS_WeHaveBacklightCtrl(SiS_Pr)) {
SiS_GenericDelay(SiS_Pr, 1023);
} else {
SiS_GenericDelay(SiS_Pr, 767);
}
} else {
if(!temp1)
SiS_GenericDelay(SiS_Pr, 767);
}
temp = SiS_GetCH701x(SiS_Pr,0x76);
temp |= 0x03;
SiS_SetCH701x(SiS_Pr,0x76,temp);
temp = SiS_GetCH701x(SiS_Pr,0x66);
temp &= 0x7f;
SiS_SetCH701x(SiS_Pr,0x66,temp);
SiS_LongDelay(SiS_Pr, 1);
}
}
static void
SiS_ChrontelDoSomething2(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
SiS_LongDelay(SiS_Pr, 1);
do {
temp = SiS_GetCH701x(SiS_Pr,0x66);
temp &= 0x04; /* PLL stable? -> bail out */
if(temp == 0x04) break;
if(SiS_Pr->ChipType == SIS_740) {
/* Power down LVDS output, PLL normal operation */
SiS_SetCH701x(SiS_Pr,0x76,0xac);
}
SiS_SetCH701xForLCD(SiS_Pr);
temp = SiS_GetCH701x(SiS_Pr,0x76);
temp &= 0xfb; /* Reset PLL */
SiS_SetCH701x(SiS_Pr,0x76,temp);
SiS_LongDelay(SiS_Pr, 2);
temp = SiS_GetCH701x(SiS_Pr,0x76);
temp |= 0x04; /* PLL normal operation */
SiS_SetCH701x(SiS_Pr,0x76,temp);
if(SiS_Pr->ChipType == SIS_740) {
SiS_SetCH701x(SiS_Pr,0x78,0xe0); /* PLL loop filter */
} else {
SiS_SetCH701x(SiS_Pr,0x78,0x60);
}
SiS_LongDelay(SiS_Pr, 2);
} while(0);
SiS_SetCH701x(SiS_Pr,0x77,0x00); /* MV? */
}
static void
SiS_ChrontelDoSomething1(struct SiS_Private *SiS_Pr)
{
unsigned short temp;
temp = SiS_GetCH701x(SiS_Pr,0x03);
temp |= 0x80; /* Set datapath 1 to TV */
temp &= 0xbf; /* Set datapath 2 to LVDS */
SiS_SetCH701x(SiS_Pr,0x03,temp);
if(SiS_Pr->ChipType == SIS_740) {
temp = SiS_GetCH701x(SiS_Pr,0x1c);
temp &= 0xfb; /* Normal XCLK phase */
SiS_SetCH701x(SiS_Pr,0x1c,temp);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2d,0x03);
temp = SiS_GetCH701x(SiS_Pr,0x64);
temp |= 0x40; /* ? Bit not defined */
SiS_SetCH701x(SiS_Pr,0x64,temp);
temp = SiS_GetCH701x(SiS_Pr,0x03);
temp &= 0x3f; /* D1 input to both LVDS and TV */
SiS_SetCH701x(SiS_Pr,0x03,temp);
if(SiS_Pr->SiS_CustomT == CUT_ASUSL3000D) {
SiS_SetCH701x(SiS_Pr,0x63,0x40); /* LVDS off */
SiS_LongDelay(SiS_Pr, 1);
SiS_SetCH701x(SiS_Pr,0x63,0x00); /* LVDS on */
SiS_ChrontelResetDB(SiS_Pr);
SiS_ChrontelDoSomething2(SiS_Pr);
SiS_ChrontelDoSomething3(SiS_Pr, 0);
} else {
temp = SiS_GetCH701x(SiS_Pr,0x66);
if(temp != 0x45) {
SiS_ChrontelResetDB(SiS_Pr);
SiS_ChrontelDoSomething2(SiS_Pr);
SiS_ChrontelDoSomething3(SiS_Pr, 0);
}
}
} else { /* 650 */
SiS_ChrontelResetDB(SiS_Pr);
SiS_ChrontelDoSomething2(SiS_Pr);
temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x34);
SiS_ChrontelDoSomething3(SiS_Pr,temp);
SiS_SetCH701x(SiS_Pr,0x76,0xaf); /* All power on, LVDS normal operation */
}
}
#endif /* 315 series */
/*********************************************/
/* MAIN: SET CRT2 REGISTER GROUP */
/*********************************************/
bool
SiS_SetCRT2Group(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
#ifdef CONFIG_FB_SIS_300
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
#endif
unsigned short ModeIdIndex, RefreshRateTableIndex;
SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
if(!SiS_Pr->UseCustomMode) {
SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex);
} else {
ModeIdIndex = 0;
}
/* Used for shifting CR33 */
SiS_Pr->SiS_SelectCRT2Rate = 4;
SiS_UnLockCRT2(SiS_Pr);
RefreshRateTableIndex = SiS_GetRatePtr(SiS_Pr, ModeNo, ModeIdIndex);
SiS_SaveCRT2Info(SiS_Pr,ModeNo);
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
SiS_DisableBridge(SiS_Pr);
if((SiS_Pr->SiS_IF_DEF_LVDS == 1) && (SiS_Pr->ChipType == SIS_730)) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x00,0x80);
}
SiS_SetCRT2ModeRegs(SiS_Pr, ModeNo, ModeIdIndex);
}
if(SiS_Pr->SiS_VBInfo & DisableCRT2Display) {
SiS_LockCRT2(SiS_Pr);
SiS_DisplayOn(SiS_Pr);
return true;
}
SiS_GetCRT2Data(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
/* Set up Panel Link for LVDS and LCDA */
SiS_Pr->SiS_LCDHDES = SiS_Pr->SiS_LCDVDES = 0;
if( (SiS_Pr->SiS_IF_DEF_LVDS == 1) ||
((SiS_Pr->SiS_VBType & VB_NoLCD) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD)) ||
((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->SiS_VBType & VB_SIS30xBLV)) ) {
SiS_GetLVDSDesData(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
SiS_SetGroup1(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
SiS_SetGroup2(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
#ifdef CONFIG_FB_SIS_315
SiS_SetGroup2_C_ELV(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
#endif
SiS_SetGroup3(SiS_Pr, ModeNo, ModeIdIndex);
SiS_SetGroup4(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
#ifdef CONFIG_FB_SIS_315
SiS_SetGroup4_C_ELV(SiS_Pr, ModeNo, ModeIdIndex);
#endif
SiS_SetGroup5(SiS_Pr, ModeNo, ModeIdIndex);
SiS_SetCRT2Sync(SiS_Pr, ModeNo, RefreshRateTableIndex);
/* For 301BDH (Panel link initialization): */
if((SiS_Pr->SiS_VBType & VB_NoLCD) && (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD)) {
if(!((SiS_Pr->SiS_SetFlag & SetDOSMode) && ((ModeNo == 0x03) || (ModeNo == 0x10)))) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
SiS_ModCRT1CRTC(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
}
SiS_SetCRT2ECLK(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
}
} else {
SiS_SetCRT2Sync(SiS_Pr, ModeNo, RefreshRateTableIndex);
SiS_ModCRT1CRTC(SiS_Pr,ModeNo,ModeIdIndex,RefreshRateTableIndex);
SiS_SetCRT2ECLK(SiS_Pr,ModeNo,ModeIdIndex,RefreshRateTableIndex);
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(SiS_Pr->SiS_IF_DEF_CH70xx == 2) {
#ifdef CONFIG_FB_SIS_315
SiS_SetCH701xForLCD(SiS_Pr);
#endif
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
SiS_SetCHTVReg(SiS_Pr,ModeNo,ModeIdIndex,RefreshRateTableIndex);
}
}
}
}
#ifdef CONFIG_FB_SIS_300
if(SiS_Pr->ChipType < SIS_315H) {
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
if(SiS_Pr->SiS_UseOEM) {
if((SiS_Pr->SiS_UseROM) && (SiS_Pr->SiS_UseOEM == -1)) {
if((ROMAddr[0x233] == 0x12) && (ROMAddr[0x234] == 0x34)) {
SiS_OEM300Setting(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
} else {
SiS_OEM300Setting(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
}
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if((SiS_Pr->SiS_CustomT == CUT_BARCO1366) ||
(SiS_Pr->SiS_CustomT == CUT_BARCO1024)) {
SetOEMLCDData2(SiS_Pr, ModeNo, ModeIdIndex,RefreshRateTableIndex);
}
SiS_DisplayOn(SiS_Pr);
}
}
}
#endif
#ifdef CONFIG_FB_SIS_315
if(SiS_Pr->ChipType >= SIS_315H) {
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
if(SiS_Pr->ChipType < SIS_661) {
SiS_FinalizeLCD(SiS_Pr, ModeNo, ModeIdIndex);
SiS_OEM310Setting(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
} else {
SiS_OEM661Setting(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
}
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x01,0x40);
}
}
#endif
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
SiS_EnableBridge(SiS_Pr);
}
SiS_DisplayOn(SiS_Pr);
if(SiS_Pr->SiS_IF_DEF_CH70xx == 1) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
/* Disable LCD panel when using TV */
SiS_SetRegSR11ANDOR(SiS_Pr,0xFF,0x0C);
} else {
/* Disable TV when using LCD */
SiS_SetCH70xxANDOR(SiS_Pr,0x0e,0x01,0xf8);
}
}
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
SiS_LockCRT2(SiS_Pr);
}
return true;
}
/*********************************************/
/* ENABLE/DISABLE LCD BACKLIGHT (SIS) */
/*********************************************/
void
SiS_SiS30xBLOn(struct SiS_Private *SiS_Pr)
{
/* Switch on LCD backlight on SiS30xLV */
SiS_DDC2Delay(SiS_Pr,0xff00);
if(!(SiS_GetReg(SiS_Pr->SiS_Part4Port,0x26) & 0x02)) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x26,0x02);
SiS_WaitVBRetrace(SiS_Pr);
}
if(!(SiS_GetReg(SiS_Pr->SiS_Part4Port,0x26) & 0x01)) {
SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x26,0x01);
}
}
void
SiS_SiS30xBLOff(struct SiS_Private *SiS_Pr)
{
/* Switch off LCD backlight on SiS30xLV */
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x26,0xFE);
SiS_DDC2Delay(SiS_Pr,0xff00);
}
/*********************************************/
/* DDC RELATED FUNCTIONS */
/*********************************************/
static void
SiS_SetupDDCN(struct SiS_Private *SiS_Pr)
{
SiS_Pr->SiS_DDC_NData = ~SiS_Pr->SiS_DDC_Data;
SiS_Pr->SiS_DDC_NClk = ~SiS_Pr->SiS_DDC_Clk;
if((SiS_Pr->SiS_DDC_Index == 0x11) && (SiS_Pr->SiS_SensibleSR11)) {
SiS_Pr->SiS_DDC_NData &= 0x0f;
SiS_Pr->SiS_DDC_NClk &= 0x0f;
}
}
#ifdef CONFIG_FB_SIS_300
static unsigned char *
SiS_SetTrumpBlockLoop(struct SiS_Private *SiS_Pr, unsigned char *dataptr)
{
int i, j, num;
unsigned short tempah,temp;
unsigned char *mydataptr;
for(i=0; i<20; i++) { /* Do 20 attempts to write */
mydataptr = dataptr;
num = *mydataptr++;
if(!num) return mydataptr;
if(i) {
SiS_SetStop(SiS_Pr);
SiS_DDC2Delay(SiS_Pr,SiS_I2CDELAYSHORT * 2);
}
if(SiS_SetStart(SiS_Pr)) continue; /* Set start condition */
tempah = SiS_Pr->SiS_DDC_DeviceAddr;
temp = SiS_WriteDDC2Data(SiS_Pr,tempah); /* Write DAB (S0=0=write) */
if(temp) continue; /* (ERROR: no ack) */
tempah = *mydataptr++;
temp = SiS_WriteDDC2Data(SiS_Pr,tempah); /* Write register number */
if(temp) continue; /* (ERROR: no ack) */
for(j=0; j<num; j++) {
tempah = *mydataptr++;
temp = SiS_WriteDDC2Data(SiS_Pr,tempah);/* Write DAB (S0=0=write) */
if(temp) break;
}
if(temp) continue;
if(SiS_SetStop(SiS_Pr)) continue;
return mydataptr;
}
return NULL;
}
static bool
SiS_SetTrumpionBlock(struct SiS_Private *SiS_Pr, unsigned char *dataptr)
{
SiS_Pr->SiS_DDC_DeviceAddr = 0xF0; /* DAB (Device Address Byte) */
SiS_Pr->SiS_DDC_Index = 0x11; /* Bit 0 = SC; Bit 1 = SD */
SiS_Pr->SiS_DDC_Data = 0x02; /* Bitmask in IndexReg for Data */
SiS_Pr->SiS_DDC_Clk = 0x01; /* Bitmask in IndexReg for Clk */
SiS_SetupDDCN(SiS_Pr);
SiS_SetSwitchDDC2(SiS_Pr);
while(*dataptr) {
dataptr = SiS_SetTrumpBlockLoop(SiS_Pr, dataptr);
if(!dataptr) return false;
}
return true;
}
#endif
/* The Chrontel 700x is connected to the 630/730 via
* the 630/730's DDC/I2C port.
*
* On 630(S)T chipset, the index changed from 0x11 to
* 0x0a, possibly for working around the DDC problems
*/
static bool
SiS_SetChReg(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val, unsigned short myor)
{
unsigned short temp, i;
for(i=0; i<20; i++) { /* Do 20 attempts to write */
if(i) {
SiS_SetStop(SiS_Pr);
SiS_DDC2Delay(SiS_Pr,SiS_I2CDELAYSHORT * 4);
}
if(SiS_SetStart(SiS_Pr)) continue; /* Set start condition */
temp = SiS_WriteDDC2Data(SiS_Pr, SiS_Pr->SiS_DDC_DeviceAddr); /* Write DAB (S0=0=write) */
if(temp) continue; /* (ERROR: no ack) */
temp = SiS_WriteDDC2Data(SiS_Pr, (reg | myor)); /* Write RAB (700x: set bit 7, see datasheet) */
if(temp) continue; /* (ERROR: no ack) */
temp = SiS_WriteDDC2Data(SiS_Pr, val); /* Write data */
if(temp) continue; /* (ERROR: no ack) */
if(SiS_SetStop(SiS_Pr)) continue; /* Set stop condition */
SiS_Pr->SiS_ChrontelInit = 1;
return true;
}
return false;
}
/* Write to Chrontel 700x */
void
SiS_SetCH700x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val)
{
SiS_Pr->SiS_DDC_DeviceAddr = 0xEA; /* DAB (Device Address Byte) */
SiS_DDC2Delay(SiS_Pr,SiS_I2CDELAYSHORT);
if(!(SiS_Pr->SiS_ChrontelInit)) {
SiS_Pr->SiS_DDC_Index = 0x11; /* Bit 0 = SC; Bit 1 = SD */
SiS_Pr->SiS_DDC_Data = 0x02; /* Bitmask in IndexReg for Data */
SiS_Pr->SiS_DDC_Clk = 0x01; /* Bitmask in IndexReg for Clk */
SiS_SetupDDCN(SiS_Pr);
}
if( (!(SiS_SetChReg(SiS_Pr, reg, val, 0x80))) &&
(!(SiS_Pr->SiS_ChrontelInit)) ) {
SiS_Pr->SiS_DDC_Index = 0x0a;
SiS_Pr->SiS_DDC_Data = 0x80;
SiS_Pr->SiS_DDC_Clk = 0x40;
SiS_SetupDDCN(SiS_Pr);
SiS_SetChReg(SiS_Pr, reg, val, 0x80);
}
}
/* Write to Chrontel 701x */
/* Parameter is [Data (S15-S8) | Register no (S7-S0)] */
void
SiS_SetCH701x(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val)
{
SiS_Pr->SiS_DDC_Index = 0x11; /* Bit 0 = SC; Bit 1 = SD */
SiS_Pr->SiS_DDC_Data = 0x08; /* Bitmask in IndexReg for Data */
SiS_Pr->SiS_DDC_Clk = 0x04; /* Bitmask in IndexReg for Clk */
SiS_SetupDDCN(SiS_Pr);
SiS_Pr->SiS_DDC_DeviceAddr = 0xEA; /* DAB (Device Address Byte) */
SiS_SetChReg(SiS_Pr, reg, val, 0);
}
static
void
SiS_SetCH70xx(struct SiS_Private *SiS_Pr, unsigned short reg, unsigned char val)
{
if(SiS_Pr->SiS_IF_DEF_CH70xx == 1)
SiS_SetCH700x(SiS_Pr, reg, val);
else
SiS_SetCH701x(SiS_Pr, reg, val);
}
static unsigned short
SiS_GetChReg(struct SiS_Private *SiS_Pr, unsigned short myor)
{
unsigned short tempah, temp, i;
for(i=0; i<20; i++) { /* Do 20 attempts to read */
if(i) {
SiS_SetStop(SiS_Pr);
SiS_DDC2Delay(SiS_Pr,SiS_I2CDELAYSHORT * 4);
}
if(SiS_SetStart(SiS_Pr)) continue; /* Set start condition */
temp = SiS_WriteDDC2Data(SiS_Pr,SiS_Pr->SiS_DDC_DeviceAddr); /* Write DAB (S0=0=write) */
if(temp) continue; /* (ERROR: no ack) */
temp = SiS_WriteDDC2Data(SiS_Pr,SiS_Pr->SiS_DDC_ReadAddr | myor); /* Write RAB (700x: | 0x80) */
if(temp) continue; /* (ERROR: no ack) */
if (SiS_SetStart(SiS_Pr)) continue; /* Re-start */
temp = SiS_WriteDDC2Data(SiS_Pr,SiS_Pr->SiS_DDC_DeviceAddr | 0x01);/* DAB (S0=1=read) */
if(temp) continue; /* (ERROR: no ack) */
tempah = SiS_ReadDDC2Data(SiS_Pr); /* Read byte */
if(SiS_SetStop(SiS_Pr)) continue; /* Stop condition */
SiS_Pr->SiS_ChrontelInit = 1;
return tempah;
}
return 0xFFFF;
}
/* Read from Chrontel 700x */
/* Parameter is [Register no (S7-S0)] */
unsigned short
SiS_GetCH700x(struct SiS_Private *SiS_Pr, unsigned short tempbx)
{
unsigned short result;
SiS_Pr->SiS_DDC_DeviceAddr = 0xEA; /* DAB */
SiS_DDC2Delay(SiS_Pr,SiS_I2CDELAYSHORT);
if(!(SiS_Pr->SiS_ChrontelInit)) {
SiS_Pr->SiS_DDC_Index = 0x11; /* Bit 0 = SC; Bit 1 = SD */
SiS_Pr->SiS_DDC_Data = 0x02; /* Bitmask in IndexReg for Data */
SiS_Pr->SiS_DDC_Clk = 0x01; /* Bitmask in IndexReg for Clk */
SiS_SetupDDCN(SiS_Pr);
}
SiS_Pr->SiS_DDC_ReadAddr = tempbx;
if( ((result = SiS_GetChReg(SiS_Pr,0x80)) == 0xFFFF) &&
(!SiS_Pr->SiS_ChrontelInit) ) {
SiS_Pr->SiS_DDC_Index = 0x0a;
SiS_Pr->SiS_DDC_Data = 0x80;
SiS_Pr->SiS_DDC_Clk = 0x40;
SiS_SetupDDCN(SiS_Pr);
result = SiS_GetChReg(SiS_Pr,0x80);
}
return result;
}
/* Read from Chrontel 701x */
/* Parameter is [Register no (S7-S0)] */
unsigned short
SiS_GetCH701x(struct SiS_Private *SiS_Pr, unsigned short tempbx)
{
SiS_Pr->SiS_DDC_Index = 0x11; /* Bit 0 = SC; Bit 1 = SD */
SiS_Pr->SiS_DDC_Data = 0x08; /* Bitmask in IndexReg for Data */
SiS_Pr->SiS_DDC_Clk = 0x04; /* Bitmask in IndexReg for Clk */
SiS_SetupDDCN(SiS_Pr);
SiS_Pr->SiS_DDC_DeviceAddr = 0xEA; /* DAB */
SiS_Pr->SiS_DDC_ReadAddr = tempbx;
return SiS_GetChReg(SiS_Pr,0);
}
/* Read from Chrontel 70xx */
/* Parameter is [Register no (S7-S0)] */
static
unsigned short
SiS_GetCH70xx(struct SiS_Private *SiS_Pr, unsigned short tempbx)
{
if(SiS_Pr->SiS_IF_DEF_CH70xx == 1)
return SiS_GetCH700x(SiS_Pr, tempbx);
else
return SiS_GetCH701x(SiS_Pr, tempbx);
}
void
SiS_SetCH70xxANDOR(struct SiS_Private *SiS_Pr, unsigned short reg,
unsigned char myor, unsigned short myand)
{
unsigned short tempbl;
tempbl = (SiS_GetCH70xx(SiS_Pr, (reg & 0xFF)) & myand) | myor;
SiS_SetCH70xx(SiS_Pr, reg, tempbl);
}
/* Our own DDC functions */
static
unsigned short
SiS_InitDDCRegs(struct SiS_Private *SiS_Pr, unsigned int VBFlags, int VGAEngine,
unsigned short adaptnum, unsigned short DDCdatatype, bool checkcr32,
unsigned int VBFlags2)
{
unsigned char ddcdtype[] = { 0xa0, 0xa0, 0xa0, 0xa2, 0xa6 };
unsigned char flag, cr32;
unsigned short temp = 0, myadaptnum = adaptnum;
if(adaptnum != 0) {
if(!(VBFlags2 & VB2_SISTMDSBRIDGE)) return 0xFFFF;
if((VBFlags2 & VB2_30xBDH) && (adaptnum == 1)) return 0xFFFF;
}
/* adapternum for SiS bridges: 0 = CRT1, 1 = LCD, 2 = VGA2 */
SiS_Pr->SiS_ChrontelInit = 0; /* force re-detection! */
SiS_Pr->SiS_DDC_SecAddr = 0;
SiS_Pr->SiS_DDC_DeviceAddr = ddcdtype[DDCdatatype];
SiS_Pr->SiS_DDC_Port = SiS_Pr->SiS_P3c4;
SiS_Pr->SiS_DDC_Index = 0x11;
flag = 0xff;
cr32 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x32);
#if 0
if(VBFlags2 & VB2_SISBRIDGE) {
if(myadaptnum == 0) {
if(!(cr32 & 0x20)) {
myadaptnum = 2;
if(!(cr32 & 0x10)) {
myadaptnum = 1;
if(!(cr32 & 0x08)) {
myadaptnum = 0;
}
}
}
}
}
#endif
if(VGAEngine == SIS_300_VGA) { /* 300 series */
if(myadaptnum != 0) {
flag = 0;
if(VBFlags2 & VB2_SISBRIDGE) {
SiS_Pr->SiS_DDC_Port = SiS_Pr->SiS_Part4Port;
SiS_Pr->SiS_DDC_Index = 0x0f;
}
}
if(!(VBFlags2 & VB2_301)) {
if((cr32 & 0x80) && (checkcr32)) {
if(myadaptnum >= 1) {
if(!(cr32 & 0x08)) {
myadaptnum = 1;
if(!(cr32 & 0x10)) return 0xFFFF;
}
}
}
}
temp = 4 - (myadaptnum * 2);
if(flag) temp = 0;
} else { /* 315/330 series */
/* here we simplify: 0 = CRT1, 1 = CRT2 (VGA, LCD) */
if(VBFlags2 & VB2_SISBRIDGE) {
if(myadaptnum == 2) {
myadaptnum = 1;
}
}
if(myadaptnum == 1) {
flag = 0;
if(VBFlags2 & VB2_SISBRIDGE) {
SiS_Pr->SiS_DDC_Port = SiS_Pr->SiS_Part4Port;
SiS_Pr->SiS_DDC_Index = 0x0f;
}
}
if((cr32 & 0x80) && (checkcr32)) {
if(myadaptnum >= 1) {
if(!(cr32 & 0x08)) {
myadaptnum = 1;
if(!(cr32 & 0x10)) return 0xFFFF;
}
}
}
temp = myadaptnum;
if(myadaptnum == 1) {
temp = 0;
if(VBFlags2 & VB2_LVDS) flag = 0xff;
}
if(flag) temp = 0;
}
SiS_Pr->SiS_DDC_Data = 0x02 << temp;
SiS_Pr->SiS_DDC_Clk = 0x01 << temp;
SiS_SetupDDCN(SiS_Pr);
return 0;
}
static unsigned short
SiS_WriteDABDDC(struct SiS_Private *SiS_Pr)
{
if(SiS_SetStart(SiS_Pr)) return 0xFFFF;
if(SiS_WriteDDC2Data(SiS_Pr, SiS_Pr->SiS_DDC_DeviceAddr)) {
return 0xFFFF;
}
if(SiS_WriteDDC2Data(SiS_Pr, SiS_Pr->SiS_DDC_SecAddr)) {
return 0xFFFF;
}
return 0;
}
static unsigned short
SiS_PrepareReadDDC(struct SiS_Private *SiS_Pr)
{
if(SiS_SetStart(SiS_Pr)) return 0xFFFF;
if(SiS_WriteDDC2Data(SiS_Pr, (SiS_Pr->SiS_DDC_DeviceAddr | 0x01))) {
return 0xFFFF;
}
return 0;
}
static unsigned short
SiS_PrepareDDC(struct SiS_Private *SiS_Pr)
{
if(SiS_WriteDABDDC(SiS_Pr)) SiS_WriteDABDDC(SiS_Pr);
if(SiS_PrepareReadDDC(SiS_Pr)) return (SiS_PrepareReadDDC(SiS_Pr));
return 0;
}
static void
SiS_SendACK(struct SiS_Private *SiS_Pr, unsigned short yesno)
{
SiS_SetSCLKLow(SiS_Pr);
if(yesno) {
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
SiS_Pr->SiS_DDC_Data);
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
0);
}
SiS_SetSCLKHigh(SiS_Pr);
}
static unsigned short
SiS_DoProbeDDC(struct SiS_Private *SiS_Pr)
{
unsigned char mask, value;
unsigned short temp, ret=0;
bool failed = false;
SiS_SetSwitchDDC2(SiS_Pr);
if(SiS_PrepareDDC(SiS_Pr)) {
SiS_SetStop(SiS_Pr);
return 0xFFFF;
}
mask = 0xf0;
value = 0x20;
if(SiS_Pr->SiS_DDC_DeviceAddr == 0xa0) {
temp = (unsigned char)SiS_ReadDDC2Data(SiS_Pr);
SiS_SendACK(SiS_Pr, 0);
if(temp == 0) {
mask = 0xff;
value = 0xff;
} else {
failed = true;
ret = 0xFFFF;
}
}
if(!failed) {
temp = (unsigned char)SiS_ReadDDC2Data(SiS_Pr);
SiS_SendACK(SiS_Pr, 1);
temp &= mask;
if(temp == value) ret = 0;
else {
ret = 0xFFFF;
if(SiS_Pr->SiS_DDC_DeviceAddr == 0xa0) {
if(temp == 0x30) ret = 0;
}
}
}
SiS_SetStop(SiS_Pr);
return ret;
}
static
unsigned short
SiS_ProbeDDC(struct SiS_Private *SiS_Pr)
{
unsigned short flag;
flag = 0x180;
SiS_Pr->SiS_DDC_DeviceAddr = 0xa0;
if(!(SiS_DoProbeDDC(SiS_Pr))) flag |= 0x02;
SiS_Pr->SiS_DDC_DeviceAddr = 0xa2;
if(!(SiS_DoProbeDDC(SiS_Pr))) flag |= 0x08;
SiS_Pr->SiS_DDC_DeviceAddr = 0xa6;
if(!(SiS_DoProbeDDC(SiS_Pr))) flag |= 0x10;
if(!(flag & 0x1a)) flag = 0;
return flag;
}
static
unsigned short
SiS_ReadDDC(struct SiS_Private *SiS_Pr, unsigned short DDCdatatype, unsigned char *buffer)
{
unsigned short flag, length, i;
unsigned char chksum,gotcha;
if(DDCdatatype > 4) return 0xFFFF;
flag = 0;
SiS_SetSwitchDDC2(SiS_Pr);
if(!(SiS_PrepareDDC(SiS_Pr))) {
length = 127;
if(DDCdatatype != 1) length = 255;
chksum = 0;
gotcha = 0;
for(i=0; i<length; i++) {
buffer[i] = (unsigned char)SiS_ReadDDC2Data(SiS_Pr);
chksum += buffer[i];
gotcha |= buffer[i];
SiS_SendACK(SiS_Pr, 0);
}
buffer[i] = (unsigned char)SiS_ReadDDC2Data(SiS_Pr);
chksum += buffer[i];
SiS_SendACK(SiS_Pr, 1);
if(gotcha) flag = (unsigned short)chksum;
else flag = 0xFFFF;
} else {
flag = 0xFFFF;
}
SiS_SetStop(SiS_Pr);
return flag;
}
/* Our private DDC functions
It complies somewhat with the corresponding VESA function
in arguments and return values.
Since this is probably called before the mode is changed,
we use our pre-detected pSiS-values instead of SiS_Pr as
regards chipset and video bridge type.
Arguments:
adaptnum: 0=CRT1(analog), 1=CRT2/LCD(digital), 2=CRT2/VGA2(analog)
CRT2 DDC is only supported on SiS301, 301B, 301C, 302B.
LCDA is CRT1, but DDC is read from CRT2 port.
DDCdatatype: 0=Probe, 1=EDID, 2=EDID+VDIF, 3=EDID V2 (P&D), 4=EDID V2 (FPDI-2)
buffer: ptr to 256 data bytes which will be filled with read data.
Returns 0xFFFF if error, otherwise
if DDCdatatype > 0: Returns 0 if reading OK (included a correct checksum)
if DDCdatatype = 0: Returns supported DDC modes
*/
unsigned short
SiS_HandleDDC(struct SiS_Private *SiS_Pr, unsigned int VBFlags, int VGAEngine,
unsigned short adaptnum, unsigned short DDCdatatype, unsigned char *buffer,
unsigned int VBFlags2)
{
unsigned char sr1f, cr17=1;
unsigned short result;
if(adaptnum > 2)
return 0xFFFF;
if(DDCdatatype > 4)
return 0xFFFF;
if((!(VBFlags2 & VB2_VIDEOBRIDGE)) && (adaptnum > 0))
return 0xFFFF;
if(SiS_InitDDCRegs(SiS_Pr, VBFlags, VGAEngine, adaptnum, DDCdatatype, false, VBFlags2) == 0xFFFF)
return 0xFFFF;
sr1f = SiS_GetReg(SiS_Pr->SiS_P3c4,0x1f);
SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x1f,0x3f,0x04);
if(VGAEngine == SIS_300_VGA) {
cr17 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x17) & 0x80;
if(!cr17) {
SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x17,0x80);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x00,0x01);
SiS_SetReg(SiS_Pr->SiS_P3c4,0x00,0x03);
}
}
if((sr1f) || (!cr17)) {
SiS_WaitRetrace1(SiS_Pr);
SiS_WaitRetrace1(SiS_Pr);
SiS_WaitRetrace1(SiS_Pr);
SiS_WaitRetrace1(SiS_Pr);
}
if(DDCdatatype == 0) {
result = SiS_ProbeDDC(SiS_Pr);
} else {
result = SiS_ReadDDC(SiS_Pr, DDCdatatype, buffer);
if((!result) && (DDCdatatype == 1)) {
if((buffer[0] == 0x00) && (buffer[1] == 0xff) &&
(buffer[2] == 0xff) && (buffer[3] == 0xff) &&
(buffer[4] == 0xff) && (buffer[5] == 0xff) &&
(buffer[6] == 0xff) && (buffer[7] == 0x00) &&
(buffer[0x12] == 1)) {
if(!SiS_Pr->DDCPortMixup) {
if(adaptnum == 1) {
if(!(buffer[0x14] & 0x80)) result = 0xFFFE;
} else {
if(buffer[0x14] & 0x80) result = 0xFFFE;
}
}
}
}
}
SiS_SetReg(SiS_Pr->SiS_P3c4,0x1f,sr1f);
if(VGAEngine == SIS_300_VGA) {
SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x17,0x7f,cr17);
}
return result;
}
/* Generic I2C functions for Chrontel & DDC --------- */
static void
SiS_SetSwitchDDC2(struct SiS_Private *SiS_Pr)
{
SiS_SetSCLKHigh(SiS_Pr);
SiS_WaitRetrace1(SiS_Pr);
SiS_SetSCLKLow(SiS_Pr);
SiS_WaitRetrace1(SiS_Pr);
}
unsigned short
SiS_ReadDDC1Bit(struct SiS_Private *SiS_Pr)
{
SiS_WaitRetrace1(SiS_Pr);
return ((SiS_GetReg(SiS_Pr->SiS_P3c4,0x11) & 0x02) >> 1);
}
/* Set I2C start condition */
/* This is done by a SD high-to-low transition while SC is high */
static unsigned short
SiS_SetStart(struct SiS_Private *SiS_Pr)
{
if(SiS_SetSCLKLow(SiS_Pr)) return 0xFFFF; /* (SC->low) */
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
SiS_Pr->SiS_DDC_Data); /* SD->high */
if(SiS_SetSCLKHigh(SiS_Pr)) return 0xFFFF; /* SC->high */
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
0x00); /* SD->low = start condition */
if(SiS_SetSCLKHigh(SiS_Pr)) return 0xFFFF; /* (SC->low) */
return 0;
}
/* Set I2C stop condition */
/* This is done by a SD low-to-high transition while SC is high */
static unsigned short
SiS_SetStop(struct SiS_Private *SiS_Pr)
{
if(SiS_SetSCLKLow(SiS_Pr)) return 0xFFFF; /* (SC->low) */
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
0x00); /* SD->low */
if(SiS_SetSCLKHigh(SiS_Pr)) return 0xFFFF; /* SC->high */
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
SiS_Pr->SiS_DDC_Data); /* SD->high = stop condition */
if(SiS_SetSCLKHigh(SiS_Pr)) return 0xFFFF; /* (SC->high) */
return 0;
}
/* Write 8 bits of data */
static unsigned short
SiS_WriteDDC2Data(struct SiS_Private *SiS_Pr, unsigned short tempax)
{
unsigned short i,flag,temp;
flag = 0x80;
for(i = 0; i < 8; i++) {
SiS_SetSCLKLow(SiS_Pr); /* SC->low */
if(tempax & flag) {
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
SiS_Pr->SiS_DDC_Data); /* Write bit (1) to SD */
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
0x00); /* Write bit (0) to SD */
}
SiS_SetSCLKHigh(SiS_Pr); /* SC->high */
flag >>= 1;
}
temp = SiS_CheckACK(SiS_Pr); /* Check acknowledge */
return temp;
}
static unsigned short
SiS_ReadDDC2Data(struct SiS_Private *SiS_Pr)
{
unsigned short i, temp, getdata;
getdata = 0;
for(i = 0; i < 8; i++) {
getdata <<= 1;
SiS_SetSCLKLow(SiS_Pr);
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
SiS_Pr->SiS_DDC_Data);
SiS_SetSCLKHigh(SiS_Pr);
temp = SiS_GetReg(SiS_Pr->SiS_DDC_Port,SiS_Pr->SiS_DDC_Index);
if(temp & SiS_Pr->SiS_DDC_Data) getdata |= 0x01;
}
return getdata;
}
static unsigned short
SiS_SetSCLKLow(struct SiS_Private *SiS_Pr)
{
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NClk,
0x00); /* SetSCLKLow() */
SiS_DDC2Delay(SiS_Pr,SiS_I2CDELAYSHORT);
return 0;
}
static unsigned short
SiS_SetSCLKHigh(struct SiS_Private *SiS_Pr)
{
unsigned short temp, watchdog=1000;
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NClk,
SiS_Pr->SiS_DDC_Clk); /* SetSCLKHigh() */
do {
temp = SiS_GetReg(SiS_Pr->SiS_DDC_Port,SiS_Pr->SiS_DDC_Index);
} while((!(temp & SiS_Pr->SiS_DDC_Clk)) && --watchdog);
if (!watchdog) {
return 0xFFFF;
}
SiS_DDC2Delay(SiS_Pr,SiS_I2CDELAYSHORT);
return 0;
}
/* Check I2C acknowledge */
/* Returns 0 if ack ok, non-0 if ack not ok */
static unsigned short
SiS_CheckACK(struct SiS_Private *SiS_Pr)
{
unsigned short tempah;
SiS_SetSCLKLow(SiS_Pr); /* (SC->low) */
SiS_SetRegANDOR(SiS_Pr->SiS_DDC_Port,
SiS_Pr->SiS_DDC_Index,
SiS_Pr->SiS_DDC_NData,
SiS_Pr->SiS_DDC_Data); /* (SD->high) */
SiS_SetSCLKHigh(SiS_Pr); /* SC->high = clock impulse for ack */
tempah = SiS_GetReg(SiS_Pr->SiS_DDC_Port,SiS_Pr->SiS_DDC_Index); /* Read SD */
SiS_SetSCLKLow(SiS_Pr); /* SC->low = end of clock impulse */
if(tempah & SiS_Pr->SiS_DDC_Data) return 1; /* Ack OK if bit = 0 */
return 0;
}
/* End of I2C functions ----------------------- */
/* =============== SiS 315/330 O.E.M. ================= */
#ifdef CONFIG_FB_SIS_315
static unsigned short
GetRAMDACromptr(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romptr;
if(SiS_Pr->ChipType < SIS_330) {
romptr = SISGETROMW(0x128);
if(SiS_Pr->SiS_VBType & VB_SIS30xB)
romptr = SISGETROMW(0x12a);
} else {
romptr = SISGETROMW(0x1a8);
if(SiS_Pr->SiS_VBType & VB_SIS30xB)
romptr = SISGETROMW(0x1aa);
}
return romptr;
}
static unsigned short
GetLCDromptr(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romptr;
if(SiS_Pr->ChipType < SIS_330) {
romptr = SISGETROMW(0x120);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV)
romptr = SISGETROMW(0x122);
} else {
romptr = SISGETROMW(0x1a0);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV)
romptr = SISGETROMW(0x1a2);
}
return romptr;
}
static unsigned short
GetTVromptr(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romptr;
if(SiS_Pr->ChipType < SIS_330) {
romptr = SISGETROMW(0x114);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV)
romptr = SISGETROMW(0x11a);
} else {
romptr = SISGETROMW(0x194);
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV)
romptr = SISGETROMW(0x19a);
}
return romptr;
}
static unsigned short
GetLCDPtrIndexBIOS(struct SiS_Private *SiS_Pr)
{
unsigned short index;
if((IS_SIS650) && (SiS_Pr->SiS_VBType & VB_SISLVDS)) {
if(!(SiS_IsNotM650orLater(SiS_Pr))) {
if((index = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) & 0xf0)) {
index >>= 4;
index *= 3;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) index += 2;
else if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) index++;
return index;
}
}
}
index = SiS_GetBIOSLCDResInfo(SiS_Pr) & 0x0F;
if(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) index -= 5;
if(SiS_Pr->SiS_VBType & VB_SIS301C) { /* 1.15.20 and later (not VB specific) */
if(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) index -= 5;
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x768) index -= 5;
} else {
if(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) index -= 6;
}
index--;
index *= 3;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) index += 2;
else if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) index++;
return index;
}
static unsigned short
GetLCDPtrIndex(struct SiS_Private *SiS_Pr)
{
unsigned short index;
index = ((SiS_GetBIOSLCDResInfo(SiS_Pr) & 0x0F) - 1) * 3;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) index += 2;
else if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) index++;
return index;
}
static unsigned short
GetTVPtrIndex(struct SiS_Private *SiS_Pr)
{
unsigned short index;
index = 0;
if(SiS_Pr->SiS_TVMode & TVSetPAL) index = 1;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) index = 2;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToYPbPr525750) index = 0;
index <<= 1;
if((SiS_Pr->SiS_VBInfo & SetInSlaveMode) &&
(SiS_Pr->SiS_TVMode & TVSetTVSimuMode)) {
index++;
}
return index;
}
static unsigned int
GetOEMTVPtr661_2_GEN(struct SiS_Private *SiS_Pr, int addme)
{
unsigned short index = 0, temp = 0;
if(SiS_Pr->SiS_TVMode & TVSetPAL) index = 1;
if(SiS_Pr->SiS_TVMode & TVSetPALM) index = 2;
if(SiS_Pr->SiS_TVMode & TVSetPALN) index = 3;
if(SiS_Pr->SiS_TVMode & TVSetNTSCJ) index = 6;
if(SiS_Pr->SiS_TVMode & TVSetNTSC1024) {
index = 4;
if(SiS_Pr->SiS_TVMode & TVSetPALM) index++;
if(SiS_Pr->SiS_TVMode & TVSetNTSCJ) index = 7;
}
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if((!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) ||
(SiS_Pr->SiS_TVMode & TVSetTVSimuMode)) {
index += addme;
temp++;
}
temp += 0x0100;
}
return (unsigned int)(index | (temp << 16));
}
static unsigned int
GetOEMTVPtr661_2_OLD(struct SiS_Private *SiS_Pr)
{
return (GetOEMTVPtr661_2_GEN(SiS_Pr, 8));
}
#if 0
static unsigned int
GetOEMTVPtr661_2_NEW(struct SiS_Private *SiS_Pr)
{
return (GetOEMTVPtr661_2_GEN(SiS_Pr, 6));
}
#endif
static int
GetOEMTVPtr661(struct SiS_Private *SiS_Pr)
{
int index = 0;
if(SiS_Pr->SiS_TVMode & TVSetPAL) index = 2;
if(SiS_Pr->SiS_ROMNew) {
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525i) index = 4;
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) index = 6;
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) index = 8;
if(SiS_Pr->SiS_TVMode & TVSetHiVision) index = 10;
} else {
if(SiS_Pr->SiS_TVMode & TVSetHiVision) index = 4;
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525i) index = 6;
if(SiS_Pr->SiS_TVMode & TVSetYPbPr525p) index = 8;
if(SiS_Pr->SiS_TVMode & TVSetYPbPr750p) index = 10;
}
if(SiS_Pr->SiS_TVMode & TVSetTVSimuMode) index++;
return index;
}
static void
SetDelayComp(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short delay=0,index,myindex,temp,romptr=0;
bool dochiptest = true;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x20,0xbf);
} else {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x35,0x7f);
}
/* Find delay (from ROM, internal tables, PCI subsystem) */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC) { /* ------------ VGA */
if((SiS_Pr->SiS_UseROM) && (!(SiS_Pr->SiS_ROMNew))) {
romptr = GetRAMDACromptr(SiS_Pr);
}
if(romptr) delay = ROMAddr[romptr];
else {
delay = 0x04;
if(SiS_Pr->SiS_VBType & VB_SIS30xB) {
if(IS_SIS650) {
delay = 0x0a;
} else if(IS_SIS740) {
delay = 0x00;
} else {
delay = 0x0c;
}
} else if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
delay = 0x00;
}
}
} else if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD|SetCRT2ToLCDA)) { /* ---------- LCD/LCDA */
bool gotitfrompci = false;
/* Could we detect a PDC for LCD or did we get a user-defined? If yes, use it */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->PDC != -1) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2d,0xf0,((SiS_Pr->PDC >> 1) & 0x0f));
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x35,0x7f,((SiS_Pr->PDC & 0x01) << 7));
return;
}
} else {
if(SiS_Pr->PDCA != -1) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2d,0x0f,((SiS_Pr->PDCA << 3) & 0xf0));
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x20,0xbf,((SiS_Pr->PDCA & 0x01) << 6));
return;
}
}
/* Custom Panel? */
if(SiS_Pr->SiS_LCDResInfo == Panel_Custom) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
delay = 0x00;
if((SiS_Pr->PanelXRes <= 1280) && (SiS_Pr->PanelYRes <= 1024)) {
delay = 0x20;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2d,0x0f,delay);
} else {
delay = 0x0c;
if(SiS_Pr->SiS_VBType & VB_SIS301C) {
delay = 0x03;
if((SiS_Pr->PanelXRes > 1280) && (SiS_Pr->PanelYRes > 1024)) {
delay = 0x00;
}
} else if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
if(IS_SIS740) delay = 0x01;
else delay = 0x03;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2d,0xf0,delay);
}
return;
}
/* This is a piece of typical SiS crap: They code the OEM LCD
* delay into the code, at no defined place in the BIOS.
* We now have to start doing a PCI subsystem check here.
*/
switch(SiS_Pr->SiS_CustomT) {
case CUT_COMPAQ1280:
case CUT_COMPAQ12802:
if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) {
gotitfrompci = true;
dochiptest = false;
delay = 0x03;
}
break;
case CUT_CLEVO1400:
case CUT_CLEVO14002:
gotitfrompci = true;
dochiptest = false;
delay = 0x02;
break;
case CUT_CLEVO1024:
case CUT_CLEVO10242:
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
gotitfrompci = true;
dochiptest = false;
delay = 0x33;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2D,delay);
delay &= 0x0f;
}
break;
}
/* Could we find it through the PCI ID? If no, use ROM or table */
if(!gotitfrompci) {
index = GetLCDPtrIndexBIOS(SiS_Pr);
myindex = GetLCDPtrIndex(SiS_Pr);
if(IS_SIS650 && (SiS_Pr->SiS_VBType & VB_SISLVDS)) {
if(SiS_IsNotM650orLater(SiS_Pr)) {
if((SiS_Pr->SiS_UseROM) && (!(SiS_Pr->SiS_ROMNew))) {
/* Always use the second pointer on 650; some BIOSes */
/* still carry old 301 data at the first location */
/* romptr = SISGETROMW(0x120); */
/* if(SiS_Pr->SiS_VBType & VB_SIS302LV) */
romptr = SISGETROMW(0x122);
if(!romptr) return;
delay = ROMAddr[(romptr + index)];
} else {
delay = SiS310_LCDDelayCompensation_650301LV[myindex];
}
} else {
delay = SiS310_LCDDelayCompensation_651301LV[myindex];
if(SiS_Pr->SiS_VBType & (VB_SIS302LV | VB_SIS302ELV))
delay = SiS310_LCDDelayCompensation_651302LV[myindex];
}
} else if(SiS_Pr->SiS_UseROM &&
(!(SiS_Pr->SiS_ROMNew)) &&
(SiS_Pr->SiS_LCDResInfo != Panel_1280x1024) &&
(SiS_Pr->SiS_LCDResInfo != Panel_1280x768) &&
(SiS_Pr->SiS_LCDResInfo != Panel_1280x960) &&
(SiS_Pr->SiS_LCDResInfo != Panel_1600x1200) &&
((romptr = GetLCDromptr(SiS_Pr)))) {
/* Data for 1280x1024 wrong in 301B BIOS */
/* Data for 1600x1200 wrong in 301C BIOS */
delay = ROMAddr[(romptr + index)];
} else if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
if(IS_SIS740) delay = 0x03;
else delay = 0x00;
} else {
delay = SiS310_LCDDelayCompensation_301[myindex];
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
if(IS_SIS740) delay = 0x01;
else if(SiS_Pr->ChipType <= SIS_315PRO) delay = SiS310_LCDDelayCompensation_3xx301LV[myindex];
else delay = SiS310_LCDDelayCompensation_650301LV[myindex];
} else if(SiS_Pr->SiS_VBType & VB_SIS301C) {
if(IS_SIS740) delay = 0x01; /* ? */
else delay = 0x03;
if(SiS_Pr->SiS_LCDResInfo == Panel_1600x1200) delay = 0x00; /* experience */
} else if(SiS_Pr->SiS_VBType & VB_SIS30xB) {
if(IS_SIS740) delay = 0x01;
else delay = SiS310_LCDDelayCompensation_3xx301B[myindex];
}
}
} /* got it from PCI */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2D,0x0F,((delay << 4) & 0xf0));
dochiptest = false;
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) { /* ------------ TV */
index = GetTVPtrIndex(SiS_Pr);
if(IS_SIS650 && (SiS_Pr->SiS_VBType & VB_SISLVDS)) {
if(SiS_IsNotM650orLater(SiS_Pr)) {
if((SiS_Pr->SiS_UseROM) && (!(SiS_Pr->SiS_ROMNew))) {
/* Always use the second pointer on 650; some BIOSes */
/* still carry old 301 data at the first location */
/* romptr = SISGETROMW(0x114); */
/* if(SiS_Pr->SiS_VBType & VB_SIS302LV) */
romptr = SISGETROMW(0x11a);
if(!romptr) return;
delay = ROMAddr[romptr + index];
} else {
delay = SiS310_TVDelayCompensation_301B[index];
}
} else {
switch(SiS_Pr->SiS_CustomT) {
case CUT_COMPAQ1280:
case CUT_COMPAQ12802:
case CUT_CLEVO1400:
case CUT_CLEVO14002:
delay = 0x02;
dochiptest = false;
break;
case CUT_CLEVO1024:
case CUT_CLEVO10242:
delay = 0x03;
dochiptest = false;
break;
default:
delay = SiS310_TVDelayCompensation_651301LV[index];
if(SiS_Pr->SiS_VBType & VB_SIS302LV) {
delay = SiS310_TVDelayCompensation_651302LV[index];
}
}
}
} else if((SiS_Pr->SiS_UseROM) && (!(SiS_Pr->SiS_ROMNew))) {
romptr = GetTVromptr(SiS_Pr);
if(!romptr) return;
delay = ROMAddr[romptr + index];
} else if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
delay = SiS310_TVDelayCompensation_LVDS[index];
} else {
delay = SiS310_TVDelayCompensation_301[index];
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
if(IS_SIS740) {
delay = SiS310_TVDelayCompensation_740301B[index];
/* LV: use 301 data? BIOS bug? */
} else {
delay = SiS310_TVDelayCompensation_301B[index];
if(SiS_Pr->SiS_VBType & VB_SIS301C) delay = 0x02;
}
}
}
if(SiS_LCDAEnabled(SiS_Pr)) {
delay &= 0x0f;
dochiptest = false;
}
} else return;
/* Write delay */
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(IS_SIS650 && (SiS_Pr->SiS_VBType & VB_SISLVDS) && dochiptest) {
temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) & 0xf0) >> 4;
if(temp == 8) { /* 1400x1050 BIOS (COMPAL) */
delay &= 0x0f;
delay |= 0xb0;
} else if(temp == 6) {
delay &= 0x0f;
delay |= 0xc0;
} else if(temp > 7) { /* 1280x1024 BIOS (which one?) */
delay = 0x35;
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x2D,delay);
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2D,0xF0,delay);
}
} else { /* LVDS */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2D,0xF0,delay);
} else {
if(IS_SIS650 && (SiS_Pr->SiS_IF_DEF_CH70xx != 0)) {
delay <<= 4;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2D,0x0F,delay);
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2D,0xF0,delay);
}
}
}
}
static void
SetAntiFlicker(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,temp,temp1,romptr=0;
if(SiS_Pr->SiS_TVMode & (TVSetYPbPr750p|TVSetYPbPr525p)) return;
if(ModeNo<=0x13)
index = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].VB_StTVFlickerIndex;
else
index = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].VB_ExtTVFlickerIndex;
temp = GetTVPtrIndex(SiS_Pr);
temp >>= 1; /* 0: NTSC/YPbPr, 1: PAL, 2: HiTV */
temp1 = temp;
if(SiS_Pr->SiS_UseROM && (!(SiS_Pr->SiS_ROMNew))) {
if(SiS_Pr->ChipType >= SIS_661) {
temp1 = GetOEMTVPtr661(SiS_Pr);
temp1 >>= 1;
romptr = SISGETROMW(0x260);
if(SiS_Pr->ChipType >= SIS_760) {
romptr = SISGETROMW(0x360);
}
} else if(SiS_Pr->ChipType >= SIS_330) {
romptr = SISGETROMW(0x192);
} else {
romptr = SISGETROMW(0x112);
}
}
if(romptr) {
temp1 <<= 1;
temp = ROMAddr[romptr + temp1 + index];
} else {
temp = SiS310_TVAntiFlick1[temp][index];
}
temp <<= 4;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x0A,0x8f,temp); /* index 0A D[6:4] */
}
static void
SetEdgeEnhance(struct SiS_Private *SiS_Pr, unsigned short ModeNo,unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,temp,temp1,romptr=0;
temp = temp1 = GetTVPtrIndex(SiS_Pr) >> 1; /* 0: NTSC/YPbPr, 1: PAL, 2: HiTV */
if(ModeNo <= 0x13)
index = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].VB_StTVEdgeIndex;
else
index = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].VB_ExtTVEdgeIndex;
if(SiS_Pr->SiS_UseROM && (!(SiS_Pr->SiS_ROMNew))) {
if(SiS_Pr->ChipType >= SIS_661) {
romptr = SISGETROMW(0x26c);
if(SiS_Pr->ChipType >= SIS_760) {
romptr = SISGETROMW(0x36c);
}
temp1 = GetOEMTVPtr661(SiS_Pr);
temp1 >>= 1;
} else if(SiS_Pr->ChipType >= SIS_330) {
romptr = SISGETROMW(0x1a4);
} else {
romptr = SISGETROMW(0x124);
}
}
if(romptr) {
temp1 <<= 1;
temp = ROMAddr[romptr + temp1 + index];
} else {
temp = SiS310_TVEdge1[temp][index];
}
temp <<= 5;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x3A,0x1F,temp); /* index 0A D[7:5] */
}
static void
SetYFilter(struct SiS_Private *SiS_Pr, unsigned short ModeNo,unsigned short ModeIdIndex)
{
unsigned short index, temp, i, j;
if(ModeNo <= 0x13) {
index = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].VB_StTVYFilterIndex;
} else {
index = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].VB_ExtTVYFilterIndex;
}
temp = GetTVPtrIndex(SiS_Pr) >> 1; /* 0: NTSC/YPbPr, 1: PAL, 2: HiTV */
if(SiS_Pr->SiS_TVMode & TVSetNTSCJ) temp = 1; /* NTSC-J uses PAL */
else if(SiS_Pr->SiS_TVMode & TVSetPALM) temp = 3; /* PAL-M */
else if(SiS_Pr->SiS_TVMode & TVSetPALN) temp = 4; /* PAL-N */
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) temp = 1; /* HiVision uses PAL */
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
for(i=0x35, j=0; i<=0x38; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS310_TVYFilter2[temp][index][j]);
}
for(i=0x48; i<=0x4A; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS310_TVYFilter2[temp][index][j]);
}
} else {
for(i=0x35, j=0; i<=0x38; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS310_TVYFilter1[temp][index][j]);
}
}
}
static void
SetPhaseIncr(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,temp,i,j,resinfo,romptr=0;
unsigned int lindex;
if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) return;
/* NTSC-J data not in BIOS, and already set in SetGroup2 */
if(SiS_Pr->SiS_TVMode & TVSetNTSCJ) return;
if((SiS_Pr->ChipType >= SIS_661) || SiS_Pr->SiS_ROMNew) {
lindex = GetOEMTVPtr661_2_OLD(SiS_Pr) & 0xffff;
lindex <<= 2;
for(j=0, i=0x31; i<=0x34; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS_TVPhase[lindex + j]);
}
return;
}
/* PAL-M, PAL-N not in BIOS, and already set in SetGroup2 */
if(SiS_Pr->SiS_TVMode & (TVSetPALM | TVSetPALN)) return;
if(ModeNo<=0x13) {
resinfo = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ResInfo;
} else {
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
temp = GetTVPtrIndex(SiS_Pr);
/* 0: NTSC Graphics, 1: NTSC Text, 2: PAL Graphics,
* 3: PAL Text, 4: HiTV Graphics 5: HiTV Text
*/
if(SiS_Pr->SiS_UseROM) {
romptr = SISGETROMW(0x116);
if(SiS_Pr->ChipType >= SIS_330) {
romptr = SISGETROMW(0x196);
}
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
romptr = SISGETROMW(0x11c);
if(SiS_Pr->ChipType >= SIS_330) {
romptr = SISGETROMW(0x19c);
}
if((SiS_Pr->SiS_VBInfo & SetInSlaveMode) && (!(SiS_Pr->SiS_TVMode & TVSetTVSimuMode))) {
romptr = SISGETROMW(0x116);
if(SiS_Pr->ChipType >= SIS_330) {
romptr = SISGETROMW(0x196);
}
}
}
}
if(romptr) {
romptr += (temp << 2);
for(j=0, i=0x31; i<=0x34; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,ROMAddr[romptr + j]);
}
} else {
index = temp % 2;
temp >>= 1; /* 0:NTSC, 1:PAL, 2:HiTV */
for(j=0, i=0x31; i<=0x34; i++, j++) {
if(!(SiS_Pr->SiS_VBType & VB_SIS30xBLV))
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS310_TVPhaseIncr1[temp][index][j]);
else if((!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) || (SiS_Pr->SiS_TVMode & TVSetTVSimuMode))
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS310_TVPhaseIncr2[temp][index][j]);
else
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS310_TVPhaseIncr1[temp][index][j]);
}
}
if((SiS_Pr->SiS_VBType & VB_SIS30xBLV) && (!(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision))) {
if((!(SiS_Pr->SiS_TVMode & (TVSetPAL | TVSetYPbPr525p | TVSetYPbPr750p))) && (ModeNo > 0x13)) {
if((resinfo == SIS_RI_640x480) ||
(resinfo == SIS_RI_800x600)) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x31,0x21);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x32,0xf0);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x33,0xf5);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x34,0x7f);
} else if(resinfo == SIS_RI_1024x768) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x31,0x1e);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x32,0x8b);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x33,0xfb);
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x34,0x7b);
}
}
}
}
static void
SetDelayComp661(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, unsigned short RTI)
{
unsigned short delay = 0, romptr = 0, index, lcdpdcindex;
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
if(!(SiS_Pr->SiS_VBInfo & (SetCRT2ToTV | SetCRT2ToLCD | SetCRT2ToLCDA | SetCRT2ToRAMDAC)))
return;
/* 1. New ROM: VGA2 and LCD/LCDA-Pass1:1 */
/* (If a custom mode is used, Pass1:1 is always set; hence we do this:) */
if(SiS_Pr->SiS_ROMNew) {
if((SiS_Pr->SiS_VBInfo & SetCRT2ToRAMDAC) ||
((SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) &&
(SiS_Pr->SiS_LCDInfo & LCDPass11))) {
index = 25;
if(SiS_Pr->UseCustomMode) {
index = SiS_Pr->CSRClock;
} else if(ModeNo > 0x13) {
index = SiS_GetVCLK2Ptr(SiS_Pr,ModeNo,ModeIdIndex,RTI);
index = SiS_Pr->SiS_VCLKData[index].CLOCK;
}
if(index < 25) index = 25;
index = ((index / 25) - 1) << 1;
if((ROMAddr[0x5b] & 0x80) || (SiS_Pr->SiS_VBInfo & (SetCRT2ToRAMDAC | SetCRT2ToLCD))) {
index++;
}
romptr = SISGETROMW(0x104);
delay = ROMAddr[romptr + index];
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToRAMDAC | SetCRT2ToLCD)) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2d,0xf0,((delay >> 1) & 0x0f));
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x35,0x7f,((delay & 0x01) << 7));
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2d,0x0f,((delay << 3) & 0xf0));
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x20,0xbf,((delay & 0x01) << 6));
}
return;
}
}
/* 2. Old ROM: VGA2 and LCD/LCDA-Pass 1:1 */
if(SiS_Pr->UseCustomMode) delay = 0x04;
else if(ModeNo <= 0x13) delay = 0x04;
else delay = (SiS_Pr->SiS_RefIndex[RTI].Ext_PDC >> 4);
delay |= (delay << 8);
if(SiS_Pr->ChipType >= XGI_20) {
delay = 0x0606;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
delay = 0x0404;
if(SiS_Pr->SiS_XGIROM) {
index = GetTVPtrIndex(SiS_Pr);
if((romptr = SISGETROMW(0x35e))) {
delay = (ROMAddr[romptr + index] & 0x0f) << 1;
delay |= (delay << 8);
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) {
if(SiS_Pr->ChipType == XGI_40 && SiS_Pr->ChipRevision == 0x02) {
delay -= 0x0404;
}
}
}
} else if(SiS_Pr->ChipType >= SIS_340) {
delay = 0x0606;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
delay = 0x0404;
}
/* TODO (eventually) */
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
/* 3. TV */
index = GetOEMTVPtr661(SiS_Pr);
if(SiS_Pr->SiS_ROMNew) {
romptr = SISGETROMW(0x106);
if(SiS_Pr->SiS_VBType & VB_UMC) romptr += 12;
delay = ROMAddr[romptr + index];
} else {
delay = 0x04;
if(index > 3) delay = 0;
}
} else if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
/* 4. LCD, LCDA (for new ROM only LV and non-Pass 1:1) */
if( (SiS_Pr->SiS_LCDResInfo != Panel_Custom) &&
((romptr = GetLCDStructPtr661_2(SiS_Pr))) ) {
lcdpdcindex = (SiS_Pr->SiS_VBType & VB_UMC) ? 14 : 12;
/* For LVDS (and sometimes TMDS), the BIOS must know about the correct value */
delay = ROMAddr[romptr + lcdpdcindex + 1]; /* LCD */
delay |= (ROMAddr[romptr + lcdpdcindex] << 8); /* LCDA */
} else {
/* TMDS: Set our own, since BIOS has no idea */
/* (This is done on >=661 only, since <661 is calling this only for LVDS) */
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
switch(SiS_Pr->SiS_LCDResInfo) {
case Panel_1024x768: delay = 0x0008; break;
case Panel_1280x720: delay = 0x0004; break;
case Panel_1280x768:
case Panel_1280x768_2:delay = 0x0004; break;
case Panel_1280x800:
case Panel_1280x800_2:delay = 0x0004; break; /* Verified for 1280x800 */
case Panel_1280x854: delay = 0x0004; break; /* FIXME */
case Panel_1280x1024: delay = 0x1e04; break;
case Panel_1400x1050: delay = 0x0004; break;
case Panel_1600x1200: delay = 0x0400; break;
case Panel_1680x1050: delay = 0x0e04; break;
default:
if((SiS_Pr->PanelXRes <= 1024) && (SiS_Pr->PanelYRes <= 768)) {
delay = 0x0008;
} else if((SiS_Pr->PanelXRes == 1280) && (SiS_Pr->PanelYRes == 1024)) {
delay = 0x1e04;
} else if((SiS_Pr->PanelXRes <= 1400) && (SiS_Pr->PanelYRes <= 1050)) {
delay = 0x0004;
} else if((SiS_Pr->PanelXRes <= 1600) && (SiS_Pr->PanelYRes <= 1200)) {
delay = 0x0400;
} else
delay = 0x0e04;
break;
}
}
/* Override by detected or user-set values */
/* (but only if, for some reason, we can't read value from BIOS) */
if((SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) && (SiS_Pr->PDC != -1)) {
delay = SiS_Pr->PDC & 0x1f;
}
if((SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) && (SiS_Pr->PDCA != -1)) {
delay = (SiS_Pr->PDCA & 0x1f) << 8;
}
}
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
delay >>= 8;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2d,0x0f,((delay << 3) & 0xf0));
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x20,0xbf,((delay & 0x01) << 6));
} else {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x2d,0xf0,((delay >> 1) & 0x0f));
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x35,0x7f,((delay & 0x01) << 7));
}
}
static void
SetCRT2SyncDither661(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short RTI)
{
unsigned short infoflag;
unsigned char temp;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(ModeNo <= 0x13) {
infoflag = SiS_GetRegByte(SiS_Pr->SiS_P3ca+2);
} else if(SiS_Pr->UseCustomMode) {
infoflag = SiS_Pr->CInfoFlag;
} else {
infoflag = SiS_Pr->SiS_RefIndex[RTI].Ext_InfoFlag;
}
if(!(SiS_Pr->SiS_LCDInfo & LCDPass11)) {
infoflag = SiS_GetReg(SiS_Pr->SiS_P3d4,0x37); /* No longer check D5 */
}
infoflag &= 0xc0;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
temp = (infoflag >> 6) | 0x0c;
if(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit) {
temp ^= 0x04;
if(SiS_Pr->SiS_ModeType >= Mode24Bpp) temp |= 0x10;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x1a,0xe0,temp);
} else {
temp = 0x30;
if(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit) temp = 0x20;
temp |= infoflag;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x19,0x0f,temp);
temp = 0;
if(SiS_Pr->SiS_LCDInfo & LCDRGB18Bit) {
if(SiS_Pr->SiS_ModeType >= Mode24Bpp) temp |= 0x80;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x1a,0x7f,temp);
}
}
}
static void
SetPanelParms661(struct SiS_Private *SiS_Pr)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short romptr, temp1, temp2;
if(SiS_Pr->SiS_VBType & (VB_SISLVDS | VB_SIS30xC)) {
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x24,0x0f);
}
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
if(SiS_Pr->LVDSHL != -1) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x24,0xfc,SiS_Pr->LVDSHL);
}
}
if(SiS_Pr->SiS_ROMNew) {
if((romptr = GetLCDStructPtr661_2(SiS_Pr))) {
if(SiS_Pr->SiS_VBType & VB_SISLVDS) {
temp1 = (ROMAddr[romptr] & 0x03) | 0x0c;
temp2 = 0xfc;
if(SiS_Pr->LVDSHL != -1) {
temp1 &= 0xfc;
temp2 = 0xf3;
}
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x24,temp2,temp1);
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
temp1 = (ROMAddr[romptr + 1] & 0x80) >> 1;
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x0d,0xbf,temp1);
}
}
}
}
static void
SiS_OEM310Setting(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex, unsigned short RRTI)
{
if((SiS_Pr->SiS_ROMNew) && (SiS_Pr->SiS_VBType & VB_SISLVDS)) {
SetDelayComp661(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
SetCRT2SyncDither661(SiS_Pr, ModeNo, RRTI);
SetPanelParms661(SiS_Pr);
}
} else {
SetDelayComp(SiS_Pr,ModeNo);
}
if((SiS_Pr->SiS_VBType & VB_SISVB) && (SiS_Pr->SiS_VBInfo & SetCRT2ToTV)) {
SetAntiFlicker(SiS_Pr,ModeNo,ModeIdIndex);
SetPhaseIncr(SiS_Pr,ModeNo,ModeIdIndex);
SetYFilter(SiS_Pr,ModeNo,ModeIdIndex);
if(SiS_Pr->SiS_VBType & VB_SIS301) {
SetEdgeEnhance(SiS_Pr,ModeNo,ModeIdIndex);
}
}
}
static void
SiS_OEM661Setting(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
unsigned short ModeIdIndex, unsigned short RRTI)
{
if(SiS_Pr->SiS_VBType & VB_SISVB) {
SetDelayComp661(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
SetCRT2SyncDither661(SiS_Pr, ModeNo, RRTI);
SetPanelParms661(SiS_Pr);
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
SetPhaseIncr(SiS_Pr, ModeNo, ModeIdIndex);
SetYFilter(SiS_Pr, ModeNo, ModeIdIndex);
SetAntiFlicker(SiS_Pr, ModeNo, ModeIdIndex);
if(SiS_Pr->SiS_VBType & VB_SIS301) {
SetEdgeEnhance(SiS_Pr, ModeNo, ModeIdIndex);
}
}
}
}
/* FinalizeLCD
* This finalizes some CRT2 registers for the very panel used.
* If we have a backup if these registers, we use it; otherwise
* we set the register according to most BIOSes. However, this
* function looks quite different in every BIOS, so you better
* pray that we have a backup...
*/
static void
SiS_FinalizeLCD(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned short tempcl,tempch,tempbl,tempbh,tempbx,tempax,temp;
unsigned short resinfo,modeflag;
if(!(SiS_Pr->SiS_VBType & VB_SISLVDS)) return;
if(SiS_Pr->SiS_ROMNew) return;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(SiS_Pr->LVDSHL != -1) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x24,0xfc,SiS_Pr->LVDSHL);
}
}
if(SiS_Pr->SiS_LCDResInfo == Panel_Custom) return;
if(SiS_Pr->UseCustomMode) return;
switch(SiS_Pr->SiS_CustomT) {
case CUT_COMPAQ1280:
case CUT_COMPAQ12802:
case CUT_CLEVO1400:
case CUT_CLEVO14002:
return;
}
if(ModeNo <= 0x13) {
resinfo = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ResInfo;
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
} else {
resinfo = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_RESINFO;
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
if(IS_SIS650) {
if(!(SiS_GetReg(SiS_Pr->SiS_P3d4, 0x5f) & 0xf0)) {
if(SiS_Pr->SiS_CustomT == CUT_CLEVO1024) {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1e,0x02);
} else {
SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x1e,0x03);
}
}
}
if(SiS_Pr->SiS_CustomT == CUT_CLEVO1024) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
/* Maybe all panels? */
if(SiS_Pr->LVDSHL == -1) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x24,0xfc,0x01);
}
return;
}
}
if(SiS_Pr->SiS_CustomT == CUT_CLEVO10242) {
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(SiS_Pr->LVDSHL == -1) {
/* Maybe all panels? */
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x24,0xfc,0x01);
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
tempch = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) >> 4;
if(tempch == 3) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x02);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,0x25);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1c,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1d,0x1b);
}
}
return;
}
}
}
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(SiS_Pr->SiS_VBType & VB_SISEMI) {
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x2a,0x00);
#ifdef SET_EMI
SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x30,0x0c);
#endif
SiS_SetReg(SiS_Pr->SiS_Part4Port,0x34,0x10);
}
} else if(SiS_Pr->SiS_LCDResInfo == Panel_1280x1024) {
if(SiS_Pr->LVDSHL == -1) {
/* Maybe ACER only? */
SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x24,0xfc,0x01);
}
}
tempch = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) >> 4;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
if(SiS_Pr->SiS_LCDResInfo == Panel_1400x1050) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1f,0x76);
} else if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(tempch == 0x03) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x02);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,0x25);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1c,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1d,0x1b);
}
if(SiS_Pr->Backup && (SiS_Pr->Backup_Mode == ModeNo)) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x14,SiS_Pr->Backup_14);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x15,SiS_Pr->Backup_15);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x16,SiS_Pr->Backup_16);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x17,SiS_Pr->Backup_17);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,SiS_Pr->Backup_18);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x19,SiS_Pr->Backup_19);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1a,SiS_Pr->Backup_1a);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,SiS_Pr->Backup_1b);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1c,SiS_Pr->Backup_1c);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1d,SiS_Pr->Backup_1d);
} else if(!(SiS_Pr->SiS_LCDInfo & DontExpandLCD)) { /* 1.10.8w */
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x14,0x90);
if(ModeNo <= 0x13) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x11);
if((resinfo == 0) || (resinfo == 2)) return;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x18);
if((resinfo == 1) || (resinfo == 3)) return;
}
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x02);
if((ModeNo > 0x13) && (resinfo == SIS_RI_1024x768)) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x02); /* 1.10.7u */
#if 0
tempbx = 806; /* 0x326 */ /* other older BIOSes */
tempbx--;
temp = tempbx & 0xff;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,temp);
temp = (tempbx >> 8) & 0x03;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x1d,0xf8,temp);
#endif
}
} else if(ModeNo <= 0x13) {
if(ModeNo <= 1) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x70);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x19,0xff);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,0x48);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1d,0x12);
}
if(!(modeflag & HalfDCLK)) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x14,0x20);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x15,0x1a);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x16,0x28);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x17,0x00);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x4c);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x19,0xdc);
if(ModeNo == 0x12) {
switch(tempch) {
case 0:
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x95);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x19,0xdc);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1a,0x10);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,0x95);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1c,0x48);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1d,0x12);
break;
case 2:
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,0x95);
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,0x48);
break;
case 3:
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x1b,0x95);
break;
}
}
}
}
}
} else {
tempcl = tempbh = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x01);
tempcl &= 0x0f;
tempbh &= 0x70;
tempbh >>= 4;
tempbl = SiS_GetReg(SiS_Pr->SiS_Part2Port,0x04);
tempbx = (tempbh << 8) | tempbl;
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if((resinfo == SIS_RI_1024x768) || (!(SiS_Pr->SiS_LCDInfo & DontExpandLCD))) {
if(SiS_Pr->SiS_SetFlag & LCDVESATiming) {
tempbx = 770;
} else {
if(tempbx > 770) tempbx = 770;
if(SiS_Pr->SiS_VGAVDE < 600) {
tempax = 768 - SiS_Pr->SiS_VGAVDE;
tempax >>= 4; /* 1.10.7w; 1.10.6s: 3; */
if(SiS_Pr->SiS_VGAVDE <= 480) tempax >>= 4; /* 1.10.7w; 1.10.6s: < 480; >>=1; */
tempbx -= tempax;
}
}
} else return;
}
temp = tempbx & 0xff;
SiS_SetReg(SiS_Pr->SiS_Part2Port,0x04,temp);
temp = ((tempbx & 0xff00) >> 4) | tempcl;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x01,0x80,temp);
}
}
}
#endif
/* ================= SiS 300 O.E.M. ================== */
#ifdef CONFIG_FB_SIS_300
static void
SetOEMLCDData2(struct SiS_Private *SiS_Pr, unsigned short ModeNo,unsigned short ModeIdIndex,
unsigned short RefTabIndex)
{
unsigned short crt2crtc=0, modeflag, myindex=0;
unsigned char temp;
int i;
if(ModeNo <= 0x13) {
modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
crt2crtc = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else {
modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
crt2crtc = SiS_Pr->SiS_RefIndex[RefTabIndex].Ext_CRT2CRTC;
}
crt2crtc &= 0x3f;
if(SiS_Pr->SiS_CustomT == CUT_BARCO1024) {
SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xdf);
}
if(SiS_Pr->SiS_CustomT == CUT_BARCO1366) {
if(modeflag & HalfDCLK) myindex = 1;
if(SiS_Pr->SiS_SetFlag & LowModeTests) {
for(i=0; i<7; i++) {
if(barco_p1[myindex][crt2crtc][i][0]) {
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,
barco_p1[myindex][crt2crtc][i][0],
barco_p1[myindex][crt2crtc][i][2],
barco_p1[myindex][crt2crtc][i][1]);
}
}
}
temp = SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00);
if(temp & 0x80) {
temp = SiS_GetReg(SiS_Pr->SiS_Part1Port,0x18);
temp++;
SiS_SetReg(SiS_Pr->SiS_Part1Port,0x18,temp);
}
}
}
static unsigned short
GetOEMLCDPtr(struct SiS_Private *SiS_Pr, int Flag)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short tempbx=0,romptr=0;
static const unsigned char customtable300[] = {
0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff
};
static const unsigned char customtable630[] = {
0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff
};
if(SiS_Pr->ChipType == SIS_300) {
tempbx = SiS_GetReg(SiS_Pr->SiS_P3d4,0x36) & 0x0f;
if(SiS_Pr->SiS_VBType & VB_SIS301) tempbx &= 0x07;
tempbx -= 2;
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) tempbx += 4;
if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) tempbx += 3;
}
if(SiS_Pr->SiS_UseROM) {
if(ROMAddr[0x235] & 0x80) {
tempbx = SiS_Pr->SiS_LCDTypeInfo;
if(Flag) {
romptr = SISGETROMW(0x255);
if(romptr) tempbx = ROMAddr[romptr + SiS_Pr->SiS_LCDTypeInfo];
else tempbx = customtable300[SiS_Pr->SiS_LCDTypeInfo];
if(tempbx == 0xFF) return 0xFFFF;
}
tempbx <<= 1;
if(!(SiS_Pr->SiS_SetFlag & LCDVESATiming)) tempbx++;
}
}
} else {
if(Flag) {
if(SiS_Pr->SiS_UseROM) {
romptr = SISGETROMW(0x255);
if(romptr) tempbx = ROMAddr[romptr + SiS_Pr->SiS_LCDTypeInfo];
else tempbx = 0xff;
} else {
tempbx = customtable630[SiS_Pr->SiS_LCDTypeInfo];
}
if(tempbx == 0xFF) return 0xFFFF;
tempbx <<= 2;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) tempbx += 2;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) tempbx++;
return tempbx;
}
tempbx = SiS_Pr->SiS_LCDTypeInfo << 2;
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) tempbx += 2;
if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) tempbx++;
}
return tempbx;
}
static void
SetOEMLCDDelay(struct SiS_Private *SiS_Pr, unsigned short ModeNo,unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,temp,romptr=0;
if(SiS_Pr->SiS_LCDResInfo == Panel_Custom) return;
if(SiS_Pr->SiS_UseROM) {
if(!(ROMAddr[0x237] & 0x01)) return;
if(!(ROMAddr[0x237] & 0x02)) return;
romptr = SISGETROMW(0x24b);
}
/* The Panel Compensation Delay should be set according to tables
* here. Unfortunately, various BIOS versions don't care about
* a uniform way using eg. ROM byte 0x220, but use different
* hard coded delays (0x04, 0x20, 0x18) in SetGroup1().
* Thus we don't set this if the user selected a custom pdc or if
* we otherwise detected a valid pdc.
*/
if(SiS_Pr->PDC != -1) return;
temp = GetOEMLCDPtr(SiS_Pr, 0);
if(SiS_Pr->UseCustomMode)
index = 0;
else
index = SiS_Pr->SiS_VBModeIDTable[ModeIdIndex].VB_LCDDelayIndex;
if(SiS_Pr->ChipType != SIS_300) {
if(romptr) {
romptr += (temp * 2);
romptr = SISGETROMW(romptr);
romptr += index;
temp = ROMAddr[romptr];
} else {
if(SiS_Pr->SiS_VBType & VB_SISVB) {
temp = SiS300_OEMLCDDelay2[temp][index];
} else {
temp = SiS300_OEMLCDDelay3[temp][index];
}
}
} else {
if(SiS_Pr->SiS_UseROM && (ROMAddr[0x235] & 0x80)) {
if(romptr) {
romptr += (temp * 2);
romptr = SISGETROMW(romptr);
romptr += index;
temp = ROMAddr[romptr];
} else {
temp = SiS300_OEMLCDDelay5[temp][index];
}
} else {
if(SiS_Pr->SiS_UseROM) {
romptr = ROMAddr[0x249] | (ROMAddr[0x24a] << 8);
if(romptr) {
romptr += (temp * 2);
romptr = SISGETROMW(romptr);
romptr += index;
temp = ROMAddr[romptr];
} else {
temp = SiS300_OEMLCDDelay4[temp][index];
}
} else {
temp = SiS300_OEMLCDDelay4[temp][index];
}
}
}
temp &= 0x3c;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,~0x3C,temp); /* index 0A D[6:4] */
}
static void
SetOEMLCDData(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
#if 0 /* Unfinished; Data table missing */
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,temp;
if((SiS_Pr->SiS_UseROM) {
if(!(ROMAddr[0x237] & 0x01)) return;
if(!(ROMAddr[0x237] & 0x04)) return;
/* No rom pointer in BIOS header! */
}
temp = GetOEMLCDPtr(SiS_Pr, 1);
if(temp == 0xFFFF) return;
index = SiS_Pr->SiS_VBModeIDTable[ModeIdIndex]._VB_LCDHIndex;
for(i=0x14, j=0; i<=0x17; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,i,SiS300_LCDHData[temp][index][j]);
}
SiS_SetRegANDOR(SiS_SiS_Part1Port,0x1a, 0xf8, (SiS300_LCDHData[temp][index][j] & 0x07));
index = SiS_Pr->SiS_VBModeIDTable[ModeIdIndex]._VB_LCDVIndex;
SiS_SetReg(SiS_SiS_Part1Port,0x18, SiS300_LCDVData[temp][index][0]);
SiS_SetRegANDOR(SiS_SiS_Part1Port,0x19, 0xF0, SiS300_LCDVData[temp][index][1]);
SiS_SetRegANDOR(SiS_SiS_Part1Port,0x1A, 0xC7, (SiS300_LCDVData[temp][index][2] & 0x38));
for(i=0x1b, j=3; i<=0x1d; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part1Port,i,SiS300_LCDVData[temp][index][j]);
}
#endif
}
static unsigned short
GetOEMTVPtr(struct SiS_Private *SiS_Pr)
{
unsigned short index;
index = 0;
if(!(SiS_Pr->SiS_VBInfo & SetInSlaveMode)) index += 4;
if(SiS_Pr->SiS_VBType & VB_SISVB) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToSCART) index += 2;
else if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) index += 3;
else if(SiS_Pr->SiS_TVMode & TVSetPAL) index += 1;
} else {
if(SiS_Pr->SiS_TVMode & TVSetCHOverScan) index += 2;
if(SiS_Pr->SiS_TVMode & TVSetPAL) index += 1;
}
return index;
}
static void
SetOEMTVDelay(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,temp,romptr=0;
if(SiS_Pr->SiS_UseROM) {
if(!(ROMAddr[0x238] & 0x01)) return;
if(!(ROMAddr[0x238] & 0x02)) return;
romptr = SISGETROMW(0x241);
}
temp = GetOEMTVPtr(SiS_Pr);
index = SiS_Pr->SiS_VBModeIDTable[ModeIdIndex].VB_TVDelayIndex;
if(romptr) {
romptr += (temp * 2);
romptr = SISGETROMW(romptr);
romptr += index;
temp = ROMAddr[romptr];
} else {
if(SiS_Pr->SiS_VBType & VB_SISVB) {
temp = SiS300_OEMTVDelay301[temp][index];
} else {
temp = SiS300_OEMTVDelayLVDS[temp][index];
}
}
temp &= 0x3c;
SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x13,~0x3C,temp);
}
static void
SetOEMAntiFlicker(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,temp,romptr=0;
if(SiS_Pr->SiS_UseROM) {
if(!(ROMAddr[0x238] & 0x01)) return;
if(!(ROMAddr[0x238] & 0x04)) return;
romptr = SISGETROMW(0x243);
}
temp = GetOEMTVPtr(SiS_Pr);
index = SiS_Pr->SiS_VBModeIDTable[ModeIdIndex].VB_TVFlickerIndex;
if(romptr) {
romptr += (temp * 2);
romptr = SISGETROMW(romptr);
romptr += index;
temp = ROMAddr[romptr];
} else {
temp = SiS300_OEMTVFlicker[temp][index];
}
temp &= 0x70;
SiS_SetRegANDOR(SiS_Pr->SiS_Part2Port,0x0A,0x8F,temp);
}
static void
SetOEMPhaseIncr(struct SiS_Private *SiS_Pr, unsigned short ModeNo,unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,i,j,temp,romptr=0;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToHiVision) return;
if(SiS_Pr->SiS_TVMode & (TVSetNTSC1024 | TVSetNTSCJ | TVSetPALM | TVSetPALN)) return;
if(SiS_Pr->SiS_UseROM) {
if(!(ROMAddr[0x238] & 0x01)) return;
if(!(ROMAddr[0x238] & 0x08)) return;
romptr = SISGETROMW(0x245);
}
temp = GetOEMTVPtr(SiS_Pr);
index = SiS_Pr->SiS_VBModeIDTable[ModeIdIndex].VB_TVPhaseIndex;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
for(i=0x31, j=0; i<=0x34; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS300_Phase2[temp][index][j]);
}
} else {
if(romptr) {
romptr += (temp * 2);
romptr = SISGETROMW(romptr);
romptr += (index * 4);
for(i=0x31, j=0; i<=0x34; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,ROMAddr[romptr + j]);
}
} else {
for(i=0x31, j=0; i<=0x34; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS300_Phase1[temp][index][j]);
}
}
}
}
static void
SetOEMYFilter(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
{
unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
unsigned short index,temp,i,j,romptr=0;
if(SiS_Pr->SiS_VBInfo & (SetCRT2ToSCART | SetCRT2ToHiVision | SetCRT2ToYPbPr525750)) return;
if(SiS_Pr->SiS_UseROM) {
if(!(ROMAddr[0x238] & 0x01)) return;
if(!(ROMAddr[0x238] & 0x10)) return;
romptr = SISGETROMW(0x247);
}
temp = GetOEMTVPtr(SiS_Pr);
if(SiS_Pr->SiS_TVMode & TVSetPALM) temp = 8;
else if(SiS_Pr->SiS_TVMode & TVSetPALN) temp = 9;
/* NTSCJ uses NTSC filters */
index = SiS_Pr->SiS_VBModeIDTable[ModeIdIndex].VB_TVYFilterIndex;
if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
for(i=0x35, j=0; i<=0x38; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS300_Filter2[temp][index][j]);
}
for(i=0x48; i<=0x4A; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS300_Filter2[temp][index][j]);
}
} else {
if((romptr) && (!(SiS_Pr->SiS_TVMode & (TVSetPALM|TVSetPALN)))) {
romptr += (temp * 2);
romptr = SISGETROMW(romptr);
romptr += (index * 4);
for(i=0x35, j=0; i<=0x38; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,ROMAddr[romptr + j]);
}
} else {
for(i=0x35, j=0; i<=0x38; i++, j++) {
SiS_SetReg(SiS_Pr->SiS_Part2Port,i,SiS300_Filter1[temp][index][j]);
}
}
}
}
static unsigned short
SiS_SearchVBModeID(struct SiS_Private *SiS_Pr, unsigned short *ModeNo)
{
unsigned short ModeIdIndex;
unsigned char VGAINFO = SiS_Pr->SiS_VGAINFO;
if(*ModeNo <= 5) *ModeNo |= 1;
for(ModeIdIndex=0; ; ModeIdIndex++) {
if(SiS_Pr->SiS_VBModeIDTable[ModeIdIndex].ModeID == *ModeNo) break;
if(SiS_Pr->SiS_VBModeIDTable[ModeIdIndex].ModeID == 0xFF) return 0;
}
if(*ModeNo != 0x07) {
if(*ModeNo > 0x03) return ModeIdIndex;
if(VGAINFO & 0x80) return ModeIdIndex;
ModeIdIndex++;
}
if(VGAINFO & 0x10) ModeIdIndex++; /* 400 lines */
/* else 350 lines */
return ModeIdIndex;
}
static void
SiS_OEM300Setting(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex,
unsigned short RefTableIndex)
{
unsigned short OEMModeIdIndex = 0;
if(!SiS_Pr->UseCustomMode) {
OEMModeIdIndex = SiS_SearchVBModeID(SiS_Pr,&ModeNo);
if(!(OEMModeIdIndex)) return;
}
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
SetOEMLCDDelay(SiS_Pr, ModeNo, OEMModeIdIndex);
if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
SetOEMLCDData(SiS_Pr, ModeNo, OEMModeIdIndex);
}
}
if(SiS_Pr->UseCustomMode) return;
if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
SetOEMTVDelay(SiS_Pr, ModeNo,OEMModeIdIndex);
if(SiS_Pr->SiS_VBType & VB_SISVB) {
SetOEMAntiFlicker(SiS_Pr, ModeNo, OEMModeIdIndex);
SetOEMPhaseIncr(SiS_Pr, ModeNo, OEMModeIdIndex);
SetOEMYFilter(SiS_Pr, ModeNo, OEMModeIdIndex);
}
}
}
#endif
| linux-master | drivers/video/fbdev/sis/init301.c |
// SPDX-License-Identifier: GPL-2.0
#include "radeonfb.h"
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <asm/io.h>
#include <video/radeon.h>
#include "../edid.h"
static void radeon_gpio_setscl(void* data, int state)
{
struct radeon_i2c_chan *chan = data;
struct radeonfb_info *rinfo = chan->rinfo;
u32 val;
val = INREG(chan->ddc_reg) & ~(VGA_DDC_CLK_OUT_EN);
if (!state)
val |= VGA_DDC_CLK_OUT_EN;
OUTREG(chan->ddc_reg, val);
(void)INREG(chan->ddc_reg);
}
static void radeon_gpio_setsda(void* data, int state)
{
struct radeon_i2c_chan *chan = data;
struct radeonfb_info *rinfo = chan->rinfo;
u32 val;
val = INREG(chan->ddc_reg) & ~(VGA_DDC_DATA_OUT_EN);
if (!state)
val |= VGA_DDC_DATA_OUT_EN;
OUTREG(chan->ddc_reg, val);
(void)INREG(chan->ddc_reg);
}
static int radeon_gpio_getscl(void* data)
{
struct radeon_i2c_chan *chan = data;
struct radeonfb_info *rinfo = chan->rinfo;
u32 val;
val = INREG(chan->ddc_reg);
return (val & VGA_DDC_CLK_INPUT) ? 1 : 0;
}
static int radeon_gpio_getsda(void* data)
{
struct radeon_i2c_chan *chan = data;
struct radeonfb_info *rinfo = chan->rinfo;
u32 val;
val = INREG(chan->ddc_reg);
return (val & VGA_DDC_DATA_INPUT) ? 1 : 0;
}
static int radeon_setup_i2c_bus(struct radeon_i2c_chan *chan, const char *name)
{
int rc;
snprintf(chan->adapter.name, sizeof(chan->adapter.name),
"radeonfb %s", name);
chan->adapter.owner = THIS_MODULE;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->rinfo->pdev->dev;
chan->algo.setsda = radeon_gpio_setsda;
chan->algo.setscl = radeon_gpio_setscl;
chan->algo.getsda = radeon_gpio_getsda;
chan->algo.getscl = radeon_gpio_getscl;
chan->algo.udelay = 10;
chan->algo.timeout = 20;
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
/* Raise SCL and SDA */
radeon_gpio_setsda(chan, 1);
radeon_gpio_setscl(chan, 1);
udelay(20);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
dev_dbg(&chan->rinfo->pdev->dev, "I2C bus %s registered.\n", name);
else
dev_warn(&chan->rinfo->pdev->dev, "Failed to register I2C bus %s.\n", name);
return rc;
}
void radeon_create_i2c_busses(struct radeonfb_info *rinfo)
{
rinfo->i2c[0].rinfo = rinfo;
rinfo->i2c[0].ddc_reg = GPIO_MONID;
#ifndef CONFIG_PPC
rinfo->i2c[0].adapter.class = I2C_CLASS_HWMON;
#endif
radeon_setup_i2c_bus(&rinfo->i2c[0], "monid");
rinfo->i2c[1].rinfo = rinfo;
rinfo->i2c[1].ddc_reg = GPIO_DVI_DDC;
radeon_setup_i2c_bus(&rinfo->i2c[1], "dvi");
rinfo->i2c[2].rinfo = rinfo;
rinfo->i2c[2].ddc_reg = GPIO_VGA_DDC;
radeon_setup_i2c_bus(&rinfo->i2c[2], "vga");
rinfo->i2c[3].rinfo = rinfo;
rinfo->i2c[3].ddc_reg = GPIO_CRT2_DDC;
radeon_setup_i2c_bus(&rinfo->i2c[3], "crt2");
}
void radeon_delete_i2c_busses(struct radeonfb_info *rinfo)
{
if (rinfo->i2c[0].rinfo)
i2c_del_adapter(&rinfo->i2c[0].adapter);
rinfo->i2c[0].rinfo = NULL;
if (rinfo->i2c[1].rinfo)
i2c_del_adapter(&rinfo->i2c[1].adapter);
rinfo->i2c[1].rinfo = NULL;
if (rinfo->i2c[2].rinfo)
i2c_del_adapter(&rinfo->i2c[2].adapter);
rinfo->i2c[2].rinfo = NULL;
if (rinfo->i2c[3].rinfo)
i2c_del_adapter(&rinfo->i2c[3].adapter);
rinfo->i2c[3].rinfo = NULL;
}
int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn,
u8 **out_edid)
{
u8 *edid;
edid = fb_ddc_read(&rinfo->i2c[conn-1].adapter);
if (out_edid)
*out_edid = edid;
if (!edid) {
pr_debug("radeonfb: I2C (port %d) ... not found\n", conn);
return MT_NONE;
}
if (edid[0x14] & 0x80) {
/* Fix detection using BIOS tables */
if (rinfo->is_mobility /*&& conn == ddc_dvi*/ &&
(INREG(LVDS_GEN_CNTL) & LVDS_ON)) {
pr_debug("radeonfb: I2C (port %d) ... found LVDS panel\n", conn);
return MT_LCD;
} else {
pr_debug("radeonfb: I2C (port %d) ... found TMDS panel\n", conn);
return MT_DFP;
}
}
pr_debug("radeonfb: I2C (port %d) ... found CRT display\n", conn);
return MT_CRT;
}
| linux-master | drivers/video/fbdev/aty/radeon_i2c.c |
// SPDX-License-Identifier: GPL-2.0
#include "radeonfb.h"
#include <linux/slab.h>
#include "../edid.h"
static const struct fb_var_screeninfo radeonfb_default_var = {
.xres = 640,
.yres = 480,
.xres_virtual = 640,
.yres_virtual = 480,
.bits_per_pixel = 8,
.red = { .length = 8 },
.green = { .length = 8 },
.blue = { .length = 8 },
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
.pixclock = 39721,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.vmode = FB_VMODE_NONINTERLACED
};
static char *radeon_get_mon_name(int type)
{
char *pret = NULL;
switch (type) {
case MT_NONE:
pret = "no";
break;
case MT_CRT:
pret = "CRT";
break;
case MT_DFP:
pret = "DFP";
break;
case MT_LCD:
pret = "LCD";
break;
case MT_CTV:
pret = "CTV";
break;
case MT_STV:
pret = "STV";
break;
}
return pret;
}
#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
/*
* Try to find monitor informations & EDID data out of the Open Firmware
* device-tree. This also contains some "hacks" to work around a few machine
* models with broken OF probing by hard-coding known EDIDs for some Mac
* laptops internal LVDS panel. (XXX: not done yet)
*/
static int radeon_parse_montype_prop(struct device_node *dp, u8 **out_EDID,
int hdno)
{
static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID",
"EDID1", "EDID2", NULL };
const u8 *pedid = NULL;
const u8 *pmt = NULL;
u8 *tmp;
int i, mt = MT_NONE;
pr_debug("analyzing OF properties...\n");
pmt = of_get_property(dp, "display-type", NULL);
if (!pmt)
return MT_NONE;
pr_debug("display-type: %s\n", pmt);
/* OF says "LCD" for DFP as well, we discriminate from the caller of this
* function
*/
if (!strcmp(pmt, "LCD") || !strcmp(pmt, "DFP"))
mt = MT_DFP;
else if (!strcmp(pmt, "CRT"))
mt = MT_CRT;
else {
if (strcmp(pmt, "NONE") != 0)
printk(KERN_WARNING "radeonfb: Unknown OF display-type: %s\n",
pmt);
return MT_NONE;
}
for (i = 0; propnames[i] != NULL; ++i) {
pedid = of_get_property(dp, propnames[i], NULL);
if (pedid != NULL)
break;
}
/* We didn't find the EDID in the leaf node, some cards will actually
* put EDID1/EDID2 in the parent, look for these (typically M6 tipb).
* single-head cards have hdno == -1 and skip this step
*/
if (pedid == NULL && dp->parent && (hdno != -1))
pedid = of_get_property(dp->parent,
(hdno == 0) ? "EDID1" : "EDID2", NULL);
if (pedid == NULL && dp->parent && (hdno == 0))
pedid = of_get_property(dp->parent, "EDID", NULL);
if (pedid == NULL)
return mt;
tmp = kmemdup(pedid, EDID_LENGTH, GFP_KERNEL);
if (!tmp)
return mt;
*out_EDID = tmp;
return mt;
}
static int radeon_probe_OF_head(struct radeonfb_info *rinfo, int head_no,
u8 **out_EDID)
{
struct device_node *dp;
pr_debug("radeon_probe_OF_head\n");
dp = rinfo->of_node;
while (dp == NULL)
return MT_NONE;
if (rinfo->has_CRTC2) {
const char *pname;
int len, second = 0;
dp = dp->child;
do {
if (!dp)
return MT_NONE;
pname = of_get_property(dp, "name", NULL);
if (!pname)
return MT_NONE;
len = strlen(pname);
pr_debug("head: %s (letter: %c, head_no: %d)\n",
pname, pname[len-1], head_no);
if (pname[len-1] == 'A' && head_no == 0) {
int mt = radeon_parse_montype_prop(dp, out_EDID, 0);
/* Maybe check for LVDS_GEN_CNTL here ? I need to check out
* what OF does when booting with lid closed
*/
if (mt == MT_DFP && rinfo->is_mobility)
mt = MT_LCD;
return mt;
} else if (pname[len-1] == 'B' && head_no == 1)
return radeon_parse_montype_prop(dp, out_EDID, 1);
second = 1;
dp = dp->sibling;
} while(!second);
} else {
if (head_no > 0)
return MT_NONE;
return radeon_parse_montype_prop(dp, out_EDID, -1);
}
return MT_NONE;
}
#endif /* CONFIG_PPC || CONFIG_SPARC */
static int radeon_get_panel_info_BIOS(struct radeonfb_info *rinfo)
{
unsigned long tmp, tmp0;
char stmp[30];
int i;
if (!rinfo->bios_seg)
return 0;
if (!(tmp = BIOS_IN16(rinfo->fp_bios_start + 0x40))) {
printk(KERN_ERR "radeonfb: Failed to detect DFP panel info using BIOS\n");
rinfo->panel_info.pwr_delay = 200;
return 0;
}
for(i=0; i<24; i++)
stmp[i] = BIOS_IN8(tmp+i+1);
stmp[24] = 0;
printk("radeonfb: panel ID string: %s\n", stmp);
rinfo->panel_info.xres = BIOS_IN16(tmp + 25);
rinfo->panel_info.yres = BIOS_IN16(tmp + 27);
printk("radeonfb: detected LVDS panel size from BIOS: %dx%d\n",
rinfo->panel_info.xres, rinfo->panel_info.yres);
rinfo->panel_info.pwr_delay = BIOS_IN16(tmp + 44);
pr_debug("BIOS provided panel power delay: %d\n", rinfo->panel_info.pwr_delay);
if (rinfo->panel_info.pwr_delay > 2000 || rinfo->panel_info.pwr_delay <= 0)
rinfo->panel_info.pwr_delay = 2000;
/*
* Some panels only work properly with some divider combinations
*/
rinfo->panel_info.ref_divider = BIOS_IN16(tmp + 46);
rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48);
rinfo->panel_info.fbk_divider = BIOS_IN16(tmp + 49);
if (rinfo->panel_info.ref_divider != 0 &&
rinfo->panel_info.fbk_divider > 3) {
rinfo->panel_info.use_bios_dividers = 1;
printk(KERN_INFO "radeondb: BIOS provided dividers will be used\n");
pr_debug("ref_divider = %x\n", rinfo->panel_info.ref_divider);
pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider);
pr_debug("fbk_divider = %x\n", rinfo->panel_info.fbk_divider);
}
pr_debug("Scanning BIOS table ...\n");
for(i=0; i<32; i++) {
tmp0 = BIOS_IN16(tmp+64+i*2);
if (tmp0 == 0)
break;
pr_debug(" %d x %d\n", BIOS_IN16(tmp0), BIOS_IN16(tmp0+2));
if ((BIOS_IN16(tmp0) == rinfo->panel_info.xres) &&
(BIOS_IN16(tmp0+2) == rinfo->panel_info.yres)) {
rinfo->panel_info.hblank = (BIOS_IN16(tmp0+17) - BIOS_IN16(tmp0+19)) * 8;
rinfo->panel_info.hOver_plus = ((BIOS_IN16(tmp0+21) -
BIOS_IN16(tmp0+19) -1) * 8) & 0x7fff;
rinfo->panel_info.hSync_width = BIOS_IN8(tmp0+23) * 8;
rinfo->panel_info.vblank = BIOS_IN16(tmp0+24) - BIOS_IN16(tmp0+26);
rinfo->panel_info.vOver_plus = (BIOS_IN16(tmp0+28) & 0x7ff) - BIOS_IN16(tmp0+26);
rinfo->panel_info.vSync_width = (BIOS_IN16(tmp0+28) & 0xf800) >> 11;
rinfo->panel_info.clock = BIOS_IN16(tmp0+9);
/* Assume high active syncs for now until ATI tells me more... maybe we
* can probe register values here ?
*/
rinfo->panel_info.hAct_high = 1;
rinfo->panel_info.vAct_high = 1;
/* Mark panel infos valid */
rinfo->panel_info.valid = 1;
pr_debug("Found panel in BIOS table:\n");
pr_debug(" hblank: %d\n", rinfo->panel_info.hblank);
pr_debug(" hOver_plus: %d\n", rinfo->panel_info.hOver_plus);
pr_debug(" hSync_width: %d\n", rinfo->panel_info.hSync_width);
pr_debug(" vblank: %d\n", rinfo->panel_info.vblank);
pr_debug(" vOver_plus: %d\n", rinfo->panel_info.vOver_plus);
pr_debug(" vSync_width: %d\n", rinfo->panel_info.vSync_width);
pr_debug(" clock: %d\n", rinfo->panel_info.clock);
return 1;
}
}
pr_debug("Didn't find panel in BIOS table !\n");
return 0;
}
/* Try to extract the connector informations from the BIOS. This
* doesn't quite work yet, but it's output is still useful for
* debugging
*/
static void radeon_parse_connector_info(struct radeonfb_info *rinfo)
{
int offset, chips, connectors, tmp, i, conn, type;
static char* __conn_type_table[16] = {
"NONE", "Proprietary", "CRT", "DVI-I", "DVI-D", "Unknown", "Unknown",
"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown",
"Unknown", "Unknown", "Unknown"
};
if (!rinfo->bios_seg)
return;
offset = BIOS_IN16(rinfo->fp_bios_start + 0x50);
if (offset == 0) {
printk(KERN_WARNING "radeonfb: No connector info table detected\n");
return;
}
/* Don't do much more at this point but displaying the data if
* DEBUG is enabled
*/
chips = BIOS_IN8(offset++) >> 4;
pr_debug("%d chips in connector info\n", chips);
for (i = 0; i < chips; i++) {
tmp = BIOS_IN8(offset++);
connectors = tmp & 0x0f;
pr_debug(" - chip %d has %d connectors\n", tmp >> 4, connectors);
for (conn = 0; ; conn++) {
tmp = BIOS_IN16(offset);
if (tmp == 0)
break;
offset += 2;
type = (tmp >> 12) & 0x0f;
pr_debug(" * connector %d of type %d (%s) : %04x\n",
conn, type, __conn_type_table[type], tmp);
}
}
}
/*
* Probe physical connection of a CRT. This code comes from XFree
* as well and currently is only implemented for the CRT DAC, the
* code for the TVDAC is commented out in XFree as "non working"
*/
static int radeon_crt_is_connected(struct radeonfb_info *rinfo, int is_crt_dac)
{
int connected = 0;
/* the monitor either wasn't connected or it is a non-DDC CRT.
* try to probe it
*/
if (is_crt_dac) {
unsigned long ulOrigVCLK_ECP_CNTL;
unsigned long ulOrigDAC_CNTL;
unsigned long ulOrigDAC_EXT_CNTL;
unsigned long ulOrigCRTC_EXT_CNTL;
unsigned long ulData;
unsigned long ulMask;
ulOrigVCLK_ECP_CNTL = INPLL(VCLK_ECP_CNTL);
ulData = ulOrigVCLK_ECP_CNTL;
ulData &= ~(PIXCLK_ALWAYS_ONb
| PIXCLK_DAC_ALWAYS_ONb);
ulMask = ~(PIXCLK_ALWAYS_ONb
| PIXCLK_DAC_ALWAYS_ONb);
OUTPLLP(VCLK_ECP_CNTL, ulData, ulMask);
ulOrigCRTC_EXT_CNTL = INREG(CRTC_EXT_CNTL);
ulData = ulOrigCRTC_EXT_CNTL;
ulData |= CRTC_CRT_ON;
OUTREG(CRTC_EXT_CNTL, ulData);
ulOrigDAC_EXT_CNTL = INREG(DAC_EXT_CNTL);
ulData = ulOrigDAC_EXT_CNTL;
ulData &= ~DAC_FORCE_DATA_MASK;
ulData |= (DAC_FORCE_BLANK_OFF_EN
|DAC_FORCE_DATA_EN
|DAC_FORCE_DATA_SEL_MASK);
if ((rinfo->family == CHIP_FAMILY_RV250) ||
(rinfo->family == CHIP_FAMILY_RV280))
ulData |= (0x01b6 << DAC_FORCE_DATA_SHIFT);
else
ulData |= (0x01ac << DAC_FORCE_DATA_SHIFT);
OUTREG(DAC_EXT_CNTL, ulData);
ulOrigDAC_CNTL = INREG(DAC_CNTL);
ulData = ulOrigDAC_CNTL;
ulData |= DAC_CMP_EN;
ulData &= ~(DAC_RANGE_CNTL_MASK
| DAC_PDWN);
ulData |= 0x2;
OUTREG(DAC_CNTL, ulData);
mdelay(1);
ulData = INREG(DAC_CNTL);
connected = (DAC_CMP_OUTPUT & ulData) ? 1 : 0;
ulData = ulOrigVCLK_ECP_CNTL;
ulMask = 0xFFFFFFFFL;
OUTPLLP(VCLK_ECP_CNTL, ulData, ulMask);
OUTREG(DAC_CNTL, ulOrigDAC_CNTL );
OUTREG(DAC_EXT_CNTL, ulOrigDAC_EXT_CNTL );
OUTREG(CRTC_EXT_CNTL, ulOrigCRTC_EXT_CNTL);
}
return connected ? MT_CRT : MT_NONE;
}
/*
* Parse the "monitor_layout" string if any. This code is mostly
* copied from XFree's radeon driver
*/
static int radeon_parse_monitor_layout(struct radeonfb_info *rinfo,
const char *monitor_layout)
{
char s1[5], s2[5];
int i = 0, second = 0;
const char *s;
if (!monitor_layout)
return 0;
s = monitor_layout;
do {
switch(*s) {
case ',':
s1[i] = '\0';
i = 0;
second = 1;
break;
case ' ':
case '\0':
break;
default:
if (i > 4)
break;
if (second)
s2[i] = *s;
else
s1[i] = *s;
i++;
}
if (i > 4)
i = 4;
} while (*s++);
if (second)
s2[i] = 0;
else {
s1[i] = 0;
s2[0] = 0;
}
if (strcmp(s1, "CRT") == 0)
rinfo->mon1_type = MT_CRT;
else if (strcmp(s1, "TMDS") == 0)
rinfo->mon1_type = MT_DFP;
else if (strcmp(s1, "LVDS") == 0)
rinfo->mon1_type = MT_LCD;
if (strcmp(s2, "CRT") == 0)
rinfo->mon2_type = MT_CRT;
else if (strcmp(s2, "TMDS") == 0)
rinfo->mon2_type = MT_DFP;
else if (strcmp(s2, "LVDS") == 0)
rinfo->mon2_type = MT_LCD;
return 1;
}
/*
* Probe display on both primary and secondary card's connector (if any)
* by various available techniques (i2c, OF device tree, BIOS, ...) and
* try to retrieve EDID. The algorithm here comes from XFree's radeon
* driver
*/
void radeon_probe_screens(struct radeonfb_info *rinfo,
const char *monitor_layout, int ignore_edid)
{
#ifdef CONFIG_FB_RADEON_I2C
int ddc_crt2_used = 0;
#endif
int tmp, i;
radeon_parse_connector_info(rinfo);
if (radeon_parse_monitor_layout(rinfo, monitor_layout)) {
/*
* If user specified a monitor_layout option, use it instead
* of auto-detecting. Maybe we should only use this argument
* on the first radeon card probed or provide a way to specify
* a layout for each card ?
*/
pr_debug("Using specified monitor layout: %s", monitor_layout);
#ifdef CONFIG_FB_RADEON_I2C
if (!ignore_edid) {
if (rinfo->mon1_type != MT_NONE)
if (!radeon_probe_i2c_connector(rinfo, ddc_dvi, &rinfo->mon1_EDID)) {
radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon1_EDID);
ddc_crt2_used = 1;
}
if (rinfo->mon2_type != MT_NONE)
if (!radeon_probe_i2c_connector(rinfo, ddc_vga, &rinfo->mon2_EDID) &&
!ddc_crt2_used)
radeon_probe_i2c_connector(rinfo, ddc_crt2, &rinfo->mon2_EDID);
}
#endif /* CONFIG_FB_RADEON_I2C */
if (rinfo->mon1_type == MT_NONE) {
if (rinfo->mon2_type != MT_NONE) {
rinfo->mon1_type = rinfo->mon2_type;
rinfo->mon1_EDID = rinfo->mon2_EDID;
} else {
rinfo->mon1_type = MT_CRT;
printk(KERN_INFO "radeonfb: No valid monitor, assuming CRT on first port\n");
}
rinfo->mon2_type = MT_NONE;
rinfo->mon2_EDID = NULL;
}
} else {
/*
* Auto-detecting display type (well... trying to ...)
*/
pr_debug("Starting monitor auto detection...\n");
#if defined(DEBUG) && defined(CONFIG_FB_RADEON_I2C)
{
u8 *EDIDs[4] = { NULL, NULL, NULL, NULL };
int i;
for (i = 0; i < 4; i++)
radeon_probe_i2c_connector(rinfo, i + 1, &EDIDs[i]);
}
#endif /* DEBUG */
/*
* Old single head cards
*/
if (!rinfo->has_CRTC2) {
#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
if (rinfo->mon1_type == MT_NONE)
rinfo->mon1_type = radeon_probe_OF_head(rinfo, 0,
&rinfo->mon1_EDID);
#endif /* CONFIG_PPC || CONFIG_SPARC */
#ifdef CONFIG_FB_RADEON_I2C
if (rinfo->mon1_type == MT_NONE)
rinfo->mon1_type =
radeon_probe_i2c_connector(rinfo, ddc_dvi,
&rinfo->mon1_EDID);
if (rinfo->mon1_type == MT_NONE)
rinfo->mon1_type =
radeon_probe_i2c_connector(rinfo, ddc_vga,
&rinfo->mon1_EDID);
if (rinfo->mon1_type == MT_NONE)
rinfo->mon1_type =
radeon_probe_i2c_connector(rinfo, ddc_crt2,
&rinfo->mon1_EDID);
#endif /* CONFIG_FB_RADEON_I2C */
if (rinfo->mon1_type == MT_NONE)
rinfo->mon1_type = MT_CRT;
goto bail;
}
/*
* Check for cards with reversed DACs or TMDS controllers using BIOS
*/
if (rinfo->bios_seg &&
(tmp = BIOS_IN16(rinfo->fp_bios_start + 0x50))) {
for (i = 1; i < 4; i++) {
unsigned int tmp0;
if (!BIOS_IN8(tmp + i*2) && i > 1)
break;
tmp0 = BIOS_IN16(tmp + i*2);
if ((!(tmp0 & 0x01)) && (((tmp0 >> 8) & 0x0f) == ddc_dvi)) {
rinfo->reversed_DAC = 1;
printk(KERN_INFO "radeonfb: Reversed DACs detected\n");
}
if ((((tmp0 >> 8) & 0x0f) == ddc_dvi) && ((tmp0 >> 4) & 0x01)) {
rinfo->reversed_TMDS = 1;
printk(KERN_INFO "radeonfb: Reversed TMDS detected\n");
}
}
}
/*
* Probe primary head (DVI or laptop internal panel)
*/
#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
if (rinfo->mon1_type == MT_NONE)
rinfo->mon1_type = radeon_probe_OF_head(rinfo, 0,
&rinfo->mon1_EDID);
#endif /* CONFIG_PPC || CONFIG_SPARC */
#ifdef CONFIG_FB_RADEON_I2C
if (rinfo->mon1_type == MT_NONE)
rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi,
&rinfo->mon1_EDID);
if (rinfo->mon1_type == MT_NONE) {
rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_crt2,
&rinfo->mon1_EDID);
if (rinfo->mon1_type != MT_NONE)
ddc_crt2_used = 1;
}
#endif /* CONFIG_FB_RADEON_I2C */
if (rinfo->mon1_type == MT_NONE && rinfo->is_mobility &&
((rinfo->bios_seg && (INREG(BIOS_4_SCRATCH) & 4))
|| (INREG(LVDS_GEN_CNTL) & LVDS_ON))) {
rinfo->mon1_type = MT_LCD;
printk("Non-DDC laptop panel detected\n");
}
if (rinfo->mon1_type == MT_NONE)
rinfo->mon1_type = radeon_crt_is_connected(rinfo, rinfo->reversed_DAC);
/*
* Probe secondary head (mostly VGA, can be DVI)
*/
#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
if (rinfo->mon2_type == MT_NONE)
rinfo->mon2_type = radeon_probe_OF_head(rinfo, 1,
&rinfo->mon2_EDID);
#endif /* CONFIG_PPC || defined(CONFIG_SPARC) */
#ifdef CONFIG_FB_RADEON_I2C
if (rinfo->mon2_type == MT_NONE)
rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_vga,
&rinfo->mon2_EDID);
if (rinfo->mon2_type == MT_NONE && !ddc_crt2_used)
rinfo->mon2_type = radeon_probe_i2c_connector(rinfo, ddc_crt2,
&rinfo->mon2_EDID);
#endif /* CONFIG_FB_RADEON_I2C */
if (rinfo->mon2_type == MT_NONE)
rinfo->mon2_type = radeon_crt_is_connected(rinfo, !rinfo->reversed_DAC);
/*
* If we only detected port 2, we swap them, if none detected,
* assume CRT (maybe fallback to old BIOS_SCRATCH stuff ? or look
* at FP registers ?)
*/
if (rinfo->mon1_type == MT_NONE) {
if (rinfo->mon2_type != MT_NONE) {
rinfo->mon1_type = rinfo->mon2_type;
rinfo->mon1_EDID = rinfo->mon2_EDID;
} else
rinfo->mon1_type = MT_CRT;
rinfo->mon2_type = MT_NONE;
rinfo->mon2_EDID = NULL;
}
/*
* Deal with reversed TMDS
*/
if (rinfo->reversed_TMDS) {
/* Always keep internal TMDS as primary head */
if (rinfo->mon1_type == MT_DFP || rinfo->mon2_type == MT_DFP) {
int tmp_type = rinfo->mon1_type;
u8 *tmp_EDID = rinfo->mon1_EDID;
rinfo->mon1_type = rinfo->mon2_type;
rinfo->mon1_EDID = rinfo->mon2_EDID;
rinfo->mon2_type = tmp_type;
rinfo->mon2_EDID = tmp_EDID;
if (rinfo->mon1_type == MT_CRT || rinfo->mon2_type == MT_CRT)
rinfo->reversed_DAC ^= 1;
}
}
}
if (ignore_edid) {
kfree(rinfo->mon1_EDID);
rinfo->mon1_EDID = NULL;
kfree(rinfo->mon2_EDID);
rinfo->mon2_EDID = NULL;
}
bail:
printk(KERN_INFO "radeonfb: Monitor 1 type %s found\n",
radeon_get_mon_name(rinfo->mon1_type));
if (rinfo->mon1_EDID)
printk(KERN_INFO "radeonfb: EDID probed\n");
if (!rinfo->has_CRTC2)
return;
printk(KERN_INFO "radeonfb: Monitor 2 type %s found\n",
radeon_get_mon_name(rinfo->mon2_type));
if (rinfo->mon2_EDID)
printk(KERN_INFO "radeonfb: EDID probed\n");
}
/*
* This function applies any arch/model/machine specific fixups
* to the panel info. It may eventually alter EDID block as
* well or whatever is specific to a given model and not probed
* properly by the default code
*/
static void radeon_fixup_panel_info(struct radeonfb_info *rinfo)
{
#ifdef CONFIG_PPC
/*
* LCD Flat panels should use fixed dividers, we enfore that on
* PPC only for now...
*/
if (!rinfo->panel_info.use_bios_dividers && rinfo->mon1_type == MT_LCD
&& rinfo->is_mobility) {
int ppll_div_sel;
u32 ppll_divn;
ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
radeon_pll_errata_after_index(rinfo);
ppll_divn = INPLL(PPLL_DIV_0 + ppll_div_sel);
rinfo->panel_info.ref_divider = rinfo->pll.ref_div;
rinfo->panel_info.fbk_divider = ppll_divn & 0x7ff;
rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7;
rinfo->panel_info.use_bios_dividers = 1;
printk(KERN_DEBUG "radeonfb: Using Firmware dividers 0x%08x "
"from PPLL %d\n",
rinfo->panel_info.fbk_divider |
(rinfo->panel_info.post_divider << 16),
ppll_div_sel);
}
#endif /* CONFIG_PPC */
}
/*
* Fill up panel infos from a mode definition, either returned by the EDID
* or from the default mode when we can't do any better
*/
static void radeon_var_to_panel_info(struct radeonfb_info *rinfo, struct fb_var_screeninfo *var)
{
rinfo->panel_info.xres = var->xres;
rinfo->panel_info.yres = var->yres;
rinfo->panel_info.clock = 100000000 / var->pixclock;
rinfo->panel_info.hOver_plus = var->right_margin;
rinfo->panel_info.hSync_width = var->hsync_len;
rinfo->panel_info.hblank = var->left_margin +
(var->right_margin + var->hsync_len);
rinfo->panel_info.vOver_plus = var->lower_margin;
rinfo->panel_info.vSync_width = var->vsync_len;
rinfo->panel_info.vblank = var->upper_margin +
(var->lower_margin + var->vsync_len);
rinfo->panel_info.hAct_high =
(var->sync & FB_SYNC_HOR_HIGH_ACT) != 0;
rinfo->panel_info.vAct_high =
(var->sync & FB_SYNC_VERT_HIGH_ACT) != 0;
rinfo->panel_info.valid = 1;
/* We use a default of 200ms for the panel power delay,
* I need to have a real schedule() instead of mdelay's in the panel code.
* we might be possible to figure out a better power delay either from
* MacOS OF tree or from the EDID block (proprietary extensions ?)
*/
rinfo->panel_info.pwr_delay = 200;
}
static void radeon_videomode_to_var(struct fb_var_screeninfo *var,
const struct fb_videomode *mode)
{
var->xres = mode->xres;
var->yres = mode->yres;
var->xres_virtual = mode->xres;
var->yres_virtual = mode->yres;
var->xoffset = 0;
var->yoffset = 0;
var->pixclock = mode->pixclock;
var->left_margin = mode->left_margin;
var->right_margin = mode->right_margin;
var->upper_margin = mode->upper_margin;
var->lower_margin = mode->lower_margin;
var->hsync_len = mode->hsync_len;
var->vsync_len = mode->vsync_len;
var->sync = mode->sync;
var->vmode = mode->vmode;
}
#ifdef CONFIG_PPC_PSERIES
static int is_powerblade(const char *model)
{
struct device_node *root;
const char* cp;
int len, l, rc = 0;
root = of_find_node_by_path("/");
if (root && model) {
l = strlen(model);
cp = of_get_property(root, "model", &len);
if (cp)
rc = memcmp(model, cp, min(len, l)) == 0;
of_node_put(root);
}
return rc;
}
#endif
/*
* Build the modedb for head 1 (head 2 will come later), check panel infos
* from either BIOS or EDID, and pick up the default mode
*/
void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option)
{
struct fb_info * info = rinfo->info;
int has_default_mode = 0;
/*
* Fill default var first
*/
info->var = radeonfb_default_var;
INIT_LIST_HEAD(&info->modelist);
/*
* First check out what BIOS has to say
*/
if (rinfo->mon1_type == MT_LCD)
radeon_get_panel_info_BIOS(rinfo);
/*
* Parse EDID detailed timings and deduce panel infos if any. Right now
* we only deal with first entry returned by parse_EDID, we may do better
* some day...
*/
if (!rinfo->panel_info.use_bios_dividers && rinfo->mon1_type != MT_CRT
&& rinfo->mon1_EDID) {
struct fb_var_screeninfo var;
pr_debug("Parsing EDID data for panel info\n");
if (fb_parse_edid(rinfo->mon1_EDID, &var) == 0) {
if (var.xres >= rinfo->panel_info.xres &&
var.yres >= rinfo->panel_info.yres)
radeon_var_to_panel_info(rinfo, &var);
}
}
/*
* Do any additional platform/arch fixups to the panel infos
*/
radeon_fixup_panel_info(rinfo);
/*
* If we have some valid panel infos, we setup the default mode based on
* those
*/
if (rinfo->mon1_type != MT_CRT && rinfo->panel_info.valid) {
struct fb_var_screeninfo *var = &info->var;
pr_debug("Setting up default mode based on panel info\n");
var->xres = rinfo->panel_info.xres;
var->yres = rinfo->panel_info.yres;
var->xres_virtual = rinfo->panel_info.xres;
var->yres_virtual = rinfo->panel_info.yres;
var->xoffset = var->yoffset = 0;
var->bits_per_pixel = 8;
var->pixclock = 100000000 / rinfo->panel_info.clock;
var->left_margin = (rinfo->panel_info.hblank - rinfo->panel_info.hOver_plus
- rinfo->panel_info.hSync_width);
var->right_margin = rinfo->panel_info.hOver_plus;
var->upper_margin = (rinfo->panel_info.vblank - rinfo->panel_info.vOver_plus
- rinfo->panel_info.vSync_width);
var->lower_margin = rinfo->panel_info.vOver_plus;
var->hsync_len = rinfo->panel_info.hSync_width;
var->vsync_len = rinfo->panel_info.vSync_width;
var->sync = 0;
if (rinfo->panel_info.hAct_high)
var->sync |= FB_SYNC_HOR_HIGH_ACT;
if (rinfo->panel_info.vAct_high)
var->sync |= FB_SYNC_VERT_HIGH_ACT;
var->vmode = 0;
has_default_mode = 1;
}
/*
* Now build modedb from EDID
*/
if (rinfo->mon1_EDID) {
fb_edid_to_monspecs(rinfo->mon1_EDID, &info->monspecs);
fb_videomode_to_modelist(info->monspecs.modedb,
info->monspecs.modedb_len,
&info->modelist);
rinfo->mon1_modedb = info->monspecs.modedb;
rinfo->mon1_dbsize = info->monspecs.modedb_len;
}
/*
* Finally, if we don't have panel infos we need to figure some (or
* we try to read it from card), we try to pick a default mode
* and create some panel infos. Whatever...
*/
if (rinfo->mon1_type != MT_CRT && !rinfo->panel_info.valid) {
struct fb_videomode *modedb;
int dbsize;
char modename[32];
pr_debug("Guessing panel info...\n");
if (rinfo->panel_info.xres == 0 || rinfo->panel_info.yres == 0) {
u32 tmp = INREG(FP_HORZ_STRETCH) & HORZ_PANEL_SIZE;
rinfo->panel_info.xres = ((tmp >> HORZ_PANEL_SHIFT) + 1) * 8;
tmp = INREG(FP_VERT_STRETCH) & VERT_PANEL_SIZE;
rinfo->panel_info.yres = (tmp >> VERT_PANEL_SHIFT) + 1;
}
if (rinfo->panel_info.xres == 0 || rinfo->panel_info.yres == 0) {
printk(KERN_WARNING "radeonfb: Can't find panel size, going back to CRT\n");
rinfo->mon1_type = MT_CRT;
goto pickup_default;
}
printk(KERN_WARNING "radeonfb: Assuming panel size %dx%d\n",
rinfo->panel_info.xres, rinfo->panel_info.yres);
modedb = rinfo->mon1_modedb;
dbsize = rinfo->mon1_dbsize;
snprintf(modename, 31, "%dx%d", rinfo->panel_info.xres, rinfo->panel_info.yres);
if (fb_find_mode(&info->var, info, modename,
modedb, dbsize, NULL, 8) == 0) {
printk(KERN_WARNING "radeonfb: Can't find mode for panel size, going back to CRT\n");
rinfo->mon1_type = MT_CRT;
goto pickup_default;
}
has_default_mode = 1;
radeon_var_to_panel_info(rinfo, &info->var);
}
pickup_default:
/*
* Apply passed-in mode option if any
*/
if (mode_option) {
if (fb_find_mode(&info->var, info, mode_option,
info->monspecs.modedb,
info->monspecs.modedb_len, NULL, 8) != 0)
has_default_mode = 1;
}
#ifdef CONFIG_PPC_PSERIES
if (!has_default_mode && (
is_powerblade("IBM,8842") || /* JS20 */
is_powerblade("IBM,8844") || /* JS21 */
is_powerblade("IBM,7998") || /* JS12/JS21/JS22 */
is_powerblade("IBM,0792") || /* QS21 */
is_powerblade("IBM,0793") /* QS22 */
)) {
printk("Falling back to 800x600 on JSxx hardware\n");
if (fb_find_mode(&info->var, info, "800x600@60",
info->monspecs.modedb,
info->monspecs.modedb_len, NULL, 8) != 0)
has_default_mode = 1;
}
#endif
/*
* Still no mode, let's pick up a default from the db
*/
if (!has_default_mode && info->monspecs.modedb != NULL) {
struct fb_monspecs *specs = &info->monspecs;
struct fb_videomode *modedb = NULL;
/* get preferred timing */
if (specs->misc & FB_MISC_1ST_DETAIL) {
int i;
for (i = 0; i < specs->modedb_len; i++) {
if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
modedb = &specs->modedb[i];
break;
}
}
} else {
/* otherwise, get first mode in database */
modedb = &specs->modedb[0];
}
if (modedb != NULL) {
info->var.bits_per_pixel = 8;
radeon_videomode_to_var(&info->var, modedb);
has_default_mode = 1;
}
}
if (1) {
struct fb_videomode mode;
/* Make sure that whatever mode got selected is actually in the
* modelist or the kernel may die
*/
fb_var_to_videomode(&mode, &info->var);
fb_add_videomode(&mode, &info->modelist);
}
}
/*
* The code below is used to pick up a mode in check_var and
* set_var. It should be made generic
*/
/*
* This is used when looking for modes. We assign a "distance" value
* to a mode in the modedb depending how "close" it is from what we
* are looking for.
* Currently, we don't compare that much, we could do better but
* the current fbcon doesn't quite mind ;)
*/
static int radeon_compare_modes(const struct fb_var_screeninfo *var,
const struct fb_videomode *mode)
{
int distance = 0;
distance = mode->yres - var->yres;
distance += (mode->xres - var->xres)/2;
return distance;
}
/*
* This function is called by check_var, it gets the passed in mode parameter, and
* outputs a valid mode matching the passed-in one as closely as possible.
* We need something better ultimately. Things like fbcon basically pass us out
* current mode with xres/yres hacked, while things like XFree will actually
* produce a full timing that we should respect as much as possible.
*
* This is why I added the FB_ACTIVATE_FIND that is used by fbcon. Without this,
* we do a simple spec match, that's all. With it, we actually look for a mode in
* either our monitor modedb or the vesa one if none
*
*/
int radeon_match_mode(struct radeonfb_info *rinfo,
struct fb_var_screeninfo *dest,
const struct fb_var_screeninfo *src)
{
const struct fb_videomode *db = vesa_modes;
int i, dbsize = 34;
int has_rmx, native_db = 0;
int distance = INT_MAX;
const struct fb_videomode *candidate = NULL;
/* Start with a copy of the requested mode */
memcpy(dest, src, sizeof(struct fb_var_screeninfo));
/* Check if we have a modedb built from EDID */
if (rinfo->mon1_modedb) {
db = rinfo->mon1_modedb;
dbsize = rinfo->mon1_dbsize;
native_db = 1;
}
/* Check if we have a scaler allowing any fancy mode */
has_rmx = rinfo->mon1_type == MT_LCD || rinfo->mon1_type == MT_DFP;
/* If we have a scaler and are passed FB_ACTIVATE_TEST or
* FB_ACTIVATE_NOW, just do basic checking and return if the
* mode match
*/
if ((src->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_TEST ||
(src->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
/* We don't have an RMX, validate timings. If we don't have
* monspecs, we should be paranoid and not let use go above
* 640x480-60, but I assume userland knows what it's doing here
* (though I may be proven wrong...)
*/
if (has_rmx == 0 && rinfo->mon1_modedb)
if (fb_validate_mode((struct fb_var_screeninfo *)src, rinfo->info))
return -EINVAL;
return 0;
}
/* Now look for a mode in the database */
while (db) {
for (i = 0; i < dbsize; i++) {
int d;
if (db[i].yres < src->yres)
continue;
if (db[i].xres < src->xres)
continue;
d = radeon_compare_modes(src, &db[i]);
/* If the new mode is at least as good as the previous one,
* then it's our new candidate
*/
if (d < distance) {
candidate = &db[i];
distance = d;
}
}
db = NULL;
/* If we have a scaler, we allow any mode from the database */
if (native_db && has_rmx) {
db = vesa_modes;
dbsize = 34;
native_db = 0;
}
}
/* If we have found a match, return it */
if (candidate != NULL) {
radeon_videomode_to_var(dest, candidate);
return 0;
}
/* If we haven't and don't have a scaler, fail */
if (!has_rmx)
return -EINVAL;
return 0;
}
| linux-master | drivers/video/fbdev/aty/radeon_monitor.c |
// SPDX-License-Identifier: GPL-2.0
/*
* drivers/video/aty/radeon_pm.c
*
* Copyright 2003,2004 Ben. Herrenschmidt <[email protected]>
* Copyright 2004 Paul Mackerras <[email protected]>
*
* This is the power management code for ATI radeon chipsets. It contains
* some dynamic clock PM enable/disable code similar to what X.org does,
* some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs,
* and the necessary bits to re-initialize from scratch a few chips found
* on PowerMacs as well. The later could be extended to more platforms
* provided the memory controller configuration code be made more generic,
* and you can get the proper mode register commands for your RAMs.
* Those things may be found in the BIOS image...
*/
#include "radeonfb.h"
#include <linux/console.h>
#include <linux/agp_backend.h>
#ifdef CONFIG_PPC_PMAC
#include <asm/machdep.h>
#include <asm/pmac_feature.h>
#endif
#include "ati_ids.h"
/*
* Workarounds for bugs in PC laptops:
* - enable D2 sleep in some IBM Thinkpads
* - special case for Samsung P35
*
* Whitelist by subsystem vendor/device because
* its the subsystem vendor's fault!
*/
#if defined(CONFIG_PM) && defined(CONFIG_X86)
static void radeon_reinitialize_M10(struct radeonfb_info *rinfo);
struct radeon_device_id {
const char *ident; /* (arbitrary) Name */
const unsigned short subsystem_vendor; /* Subsystem Vendor ID */
const unsigned short subsystem_device; /* Subsystem Device ID */
const enum radeon_pm_mode pm_mode_modifier; /* modify pm_mode */
const reinit_function_ptr new_reinit_func; /* changed reinit_func */
};
#define BUGFIX(model, sv, sd, pm, fn) { \
.ident = model, \
.subsystem_vendor = sv, \
.subsystem_device = sd, \
.pm_mode_modifier = pm, \
.new_reinit_func = fn \
}
static struct radeon_device_id radeon_workaround_list[] = {
BUGFIX("IBM Thinkpad R32",
PCI_VENDOR_ID_IBM, 0x1905,
radeon_pm_d2, NULL),
BUGFIX("IBM Thinkpad R40",
PCI_VENDOR_ID_IBM, 0x0526,
radeon_pm_d2, NULL),
BUGFIX("IBM Thinkpad R40",
PCI_VENDOR_ID_IBM, 0x0527,
radeon_pm_d2, NULL),
BUGFIX("IBM Thinkpad R50/R51/T40/T41",
PCI_VENDOR_ID_IBM, 0x0531,
radeon_pm_d2, NULL),
BUGFIX("IBM Thinkpad R51/T40/T41/T42",
PCI_VENDOR_ID_IBM, 0x0530,
radeon_pm_d2, NULL),
BUGFIX("IBM Thinkpad T30",
PCI_VENDOR_ID_IBM, 0x0517,
radeon_pm_d2, NULL),
BUGFIX("IBM Thinkpad T40p",
PCI_VENDOR_ID_IBM, 0x054d,
radeon_pm_d2, NULL),
BUGFIX("IBM Thinkpad T42",
PCI_VENDOR_ID_IBM, 0x0550,
radeon_pm_d2, NULL),
BUGFIX("IBM Thinkpad X31/X32",
PCI_VENDOR_ID_IBM, 0x052f,
radeon_pm_d2, NULL),
BUGFIX("Samsung P35",
PCI_VENDOR_ID_SAMSUNG, 0xc00c,
radeon_pm_off, radeon_reinitialize_M10),
BUGFIX("Acer Aspire 2010",
PCI_VENDOR_ID_AI, 0x0061,
radeon_pm_off, radeon_reinitialize_M10),
BUGFIX("Acer Travelmate 290D/292LMi",
PCI_VENDOR_ID_AI, 0x005a,
radeon_pm_off, radeon_reinitialize_M10),
{ .ident = NULL }
};
static int radeon_apply_workarounds(struct radeonfb_info *rinfo)
{
struct radeon_device_id *id;
for (id = radeon_workaround_list; id->ident != NULL; id++ )
if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) &&
(id->subsystem_device == rinfo->pdev->subsystem_device )) {
/* we found a device that requires workaround */
printk(KERN_DEBUG "radeonfb: %s detected"
", enabling workaround\n", id->ident);
rinfo->pm_mode |= id->pm_mode_modifier;
if (id->new_reinit_func != NULL)
rinfo->reinit_func = id->new_reinit_func;
return 1;
}
return 0; /* not found */
}
#else /* defined(CONFIG_PM) && defined(CONFIG_X86) */
static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo)
{
return 0;
}
#endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */
static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
{
u32 tmp;
/* RV100 */
if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
if (rinfo->has_CRTC2) {
tmp = INPLL(pllSCLK_CNTL);
tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK;
tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK;
OUTPLL(pllSCLK_CNTL, tmp);
}
tmp = INPLL(pllMCLK_CNTL);
tmp |= (MCLK_CNTL__FORCE_MCLKA |
MCLK_CNTL__FORCE_MCLKB |
MCLK_CNTL__FORCE_YCLKA |
MCLK_CNTL__FORCE_YCLKB |
MCLK_CNTL__FORCE_AIC |
MCLK_CNTL__FORCE_MC);
OUTPLL(pllMCLK_CNTL, tmp);
return;
}
/* R100 */
if (!rinfo->has_CRTC2) {
tmp = INPLL(pllSCLK_CNTL);
tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP |
SCLK_CNTL__FORCE_DISP1 | SCLK_CNTL__FORCE_TOP |
SCLK_CNTL__FORCE_E2 | SCLK_CNTL__FORCE_SE |
SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_VIP |
SCLK_CNTL__FORCE_RE | SCLK_CNTL__FORCE_PB |
SCLK_CNTL__FORCE_TAM | SCLK_CNTL__FORCE_TDM |
SCLK_CNTL__FORCE_RB);
OUTPLL(pllSCLK_CNTL, tmp);
return;
}
/* RV350 (M10/M11) */
if (rinfo->family == CHIP_FAMILY_RV350) {
/* for RV350/M10/M11, no delays are required. */
tmp = INPLL(pllSCLK_CNTL2);
tmp |= (SCLK_CNTL2__R300_FORCE_TCL |
SCLK_CNTL2__R300_FORCE_GA |
SCLK_CNTL2__R300_FORCE_CBA);
OUTPLL(pllSCLK_CNTL2, tmp);
tmp = INPLL(pllSCLK_CNTL);
tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
OUTPLL(pllSCLK_CNTL, tmp);
tmp = INPLL(pllSCLK_MORE_CNTL);
tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI |
SCLK_MORE_CNTL__FORCE_MC_HOST);
OUTPLL(pllSCLK_MORE_CNTL, tmp);
tmp = INPLL(pllMCLK_CNTL);
tmp |= (MCLK_CNTL__FORCE_MCLKA |
MCLK_CNTL__FORCE_MCLKB |
MCLK_CNTL__FORCE_YCLKA |
MCLK_CNTL__FORCE_YCLKB |
MCLK_CNTL__FORCE_MC);
OUTPLL(pllMCLK_CNTL, tmp);
tmp = INPLL(pllVCLK_ECP_CNTL);
tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb |
VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
OUTPLL(pllVCLK_ECP_CNTL, tmp);
tmp = INPLL(pllPIXCLKS_CNTL);
tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
OUTPLL(pllPIXCLKS_CNTL, tmp);
return;
}
/* Default */
/* Force Core Clocks */
tmp = INPLL(pllSCLK_CNTL);
tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2);
/* XFree doesn't do that case, but we had this code from Apple and it
* seem necessary for proper suspend/resume operations
*/
if (rinfo->is_mobility) {
tmp |= SCLK_CNTL__FORCE_HDP|
SCLK_CNTL__FORCE_DISP1|
SCLK_CNTL__FORCE_DISP2|
SCLK_CNTL__FORCE_TOP|
SCLK_CNTL__FORCE_SE|
SCLK_CNTL__FORCE_IDCT|
SCLK_CNTL__FORCE_VIP|
SCLK_CNTL__FORCE_PB|
SCLK_CNTL__FORCE_RE|
SCLK_CNTL__FORCE_TAM|
SCLK_CNTL__FORCE_TDM|
SCLK_CNTL__FORCE_RB|
SCLK_CNTL__FORCE_TV_SCLK|
SCLK_CNTL__FORCE_SUBPIC|
SCLK_CNTL__FORCE_OV0;
}
else if (rinfo->family == CHIP_FAMILY_R300 ||
rinfo->family == CHIP_FAMILY_R350) {
tmp |= SCLK_CNTL__FORCE_HDP |
SCLK_CNTL__FORCE_DISP1 |
SCLK_CNTL__FORCE_DISP2 |
SCLK_CNTL__FORCE_TOP |
SCLK_CNTL__FORCE_IDCT |
SCLK_CNTL__FORCE_VIP;
}
OUTPLL(pllSCLK_CNTL, tmp);
radeon_msleep(16);
if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
tmp = INPLL(pllSCLK_CNTL2);
tmp |= SCLK_CNTL2__R300_FORCE_TCL |
SCLK_CNTL2__R300_FORCE_GA |
SCLK_CNTL2__R300_FORCE_CBA;
OUTPLL(pllSCLK_CNTL2, tmp);
radeon_msleep(16);
}
tmp = INPLL(pllCLK_PIN_CNTL);
tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
OUTPLL(pllCLK_PIN_CNTL, tmp);
radeon_msleep(15);
if (rinfo->is_IGP) {
/* Weird ... X is _un_ forcing clocks here, I think it's
* doing backward. Imitate it for now...
*/
tmp = INPLL(pllMCLK_CNTL);
tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
MCLK_CNTL__FORCE_YCLKA);
OUTPLL(pllMCLK_CNTL, tmp);
radeon_msleep(16);
}
/* Hrm... same shit, X doesn't do that but I have to */
else if (rinfo->is_mobility) {
tmp = INPLL(pllMCLK_CNTL);
tmp |= (MCLK_CNTL__FORCE_MCLKA |
MCLK_CNTL__FORCE_MCLKB |
MCLK_CNTL__FORCE_YCLKA |
MCLK_CNTL__FORCE_YCLKB);
OUTPLL(pllMCLK_CNTL, tmp);
radeon_msleep(16);
tmp = INPLL(pllMCLK_MISC);
tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
MCLK_MISC__MC_MCLK_DYN_ENABLE|
MCLK_MISC__IO_MCLK_DYN_ENABLE);
OUTPLL(pllMCLK_MISC, tmp);
radeon_msleep(15);
}
if (rinfo->is_mobility) {
tmp = INPLL(pllSCLK_MORE_CNTL);
tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS|
SCLK_MORE_CNTL__FORCE_MC_GUI|
SCLK_MORE_CNTL__FORCE_MC_HOST;
OUTPLL(pllSCLK_MORE_CNTL, tmp);
radeon_msleep(16);
}
tmp = INPLL(pllPIXCLKS_CNTL);
tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
OUTPLL(pllPIXCLKS_CNTL, tmp);
radeon_msleep(16);
tmp = INPLL( pllVCLK_ECP_CNTL);
tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
OUTPLL( pllVCLK_ECP_CNTL, tmp);
radeon_msleep(16);
}
static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
{
u32 tmp;
/* R100 */
if (!rinfo->has_CRTC2) {
tmp = INPLL(pllSCLK_CNTL);
if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13)
tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB);
tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE |
SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_RE |
SCLK_CNTL__FORCE_PB | SCLK_CNTL__FORCE_TAM |
SCLK_CNTL__FORCE_TDM);
OUTPLL(pllSCLK_CNTL, tmp);
return;
}
/* M10/M11 */
if (rinfo->family == CHIP_FAMILY_RV350) {
tmp = INPLL(pllSCLK_CNTL2);
tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
SCLK_CNTL2__R300_FORCE_GA |
SCLK_CNTL2__R300_FORCE_CBA);
tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT |
SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT |
SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT);
OUTPLL(pllSCLK_CNTL2, tmp);
tmp = INPLL(pllSCLK_CNTL);
tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP |
SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 |
SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 |
SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT |
SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR |
SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX |
SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK |
SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0);
tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK;
OUTPLL(pllSCLK_CNTL, tmp);
tmp = INPLL(pllSCLK_MORE_CNTL);
tmp &= ~SCLK_MORE_CNTL__FORCEON;
tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT |
SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT |
SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT;
OUTPLL(pllSCLK_MORE_CNTL, tmp);
tmp = INPLL(pllVCLK_ECP_CNTL);
tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
OUTPLL(pllVCLK_ECP_CNTL, tmp);
tmp = INPLL(pllPIXCLKS_CNTL);
tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb |
PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb |
PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb |
PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb |
PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb |
PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb);
OUTPLL(pllPIXCLKS_CNTL, tmp);
tmp = INPLL(pllMCLK_MISC);
tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE |
MCLK_MISC__IO_MCLK_DYN_ENABLE);
OUTPLL(pllMCLK_MISC, tmp);
tmp = INPLL(pllMCLK_CNTL);
tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB);
tmp &= ~(MCLK_CNTL__FORCE_YCLKA |
MCLK_CNTL__FORCE_YCLKB |
MCLK_CNTL__FORCE_MC);
/* Some releases of vbios have set DISABLE_MC_MCLKA
* and DISABLE_MC_MCLKB bits in the vbios table. Setting these
* bits will cause H/W hang when reading video memory with dynamic
* clocking enabled.
*/
if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) &&
(tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) {
/* If both bits are set, then check the active channels */
tmp = INPLL(pllMCLK_CNTL);
if (rinfo->vram_width == 64) {
if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB;
else
tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA;
} else {
tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA |
MCLK_CNTL__R300_DISABLE_MC_MCLKB);
}
}
OUTPLL(pllMCLK_CNTL, tmp);
return;
}
/* R300 */
if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
tmp = INPLL(pllSCLK_CNTL);
tmp &= ~(SCLK_CNTL__R300_FORCE_VAP);
tmp |= SCLK_CNTL__FORCE_CP;
OUTPLL(pllSCLK_CNTL, tmp);
radeon_msleep(15);
tmp = INPLL(pllSCLK_CNTL2);
tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL |
SCLK_CNTL2__R300_FORCE_GA |
SCLK_CNTL2__R300_FORCE_CBA);
OUTPLL(pllSCLK_CNTL2, tmp);
}
/* Others */
tmp = INPLL( pllCLK_PWRMGT_CNTL);
tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK|
CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK);
tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK |
(0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT);
OUTPLL( pllCLK_PWRMGT_CNTL, tmp);
radeon_msleep(15);
tmp = INPLL(pllCLK_PIN_CNTL);
tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL;
OUTPLL(pllCLK_PIN_CNTL, tmp);
radeon_msleep(15);
/* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
* to lockup randomly, leave them as set by BIOS.
*/
tmp = INPLL(pllSCLK_CNTL);
tmp &= ~SCLK_CNTL__FORCEON_MASK;
/*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
if ((rinfo->family == CHIP_FAMILY_RV250 &&
((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) ||
((rinfo->family == CHIP_FAMILY_RV100) &&
((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) {
tmp |= SCLK_CNTL__FORCE_CP;
tmp |= SCLK_CNTL__FORCE_VIP;
}
OUTPLL(pllSCLK_CNTL, tmp);
radeon_msleep(15);
if ((rinfo->family == CHIP_FAMILY_RV200) ||
(rinfo->family == CHIP_FAMILY_RV250) ||
(rinfo->family == CHIP_FAMILY_RV280)) {
tmp = INPLL(pllSCLK_MORE_CNTL);
tmp &= ~SCLK_MORE_CNTL__FORCEON;
/* RV200::A11 A12 RV250::A11 A12 */
if (((rinfo->family == CHIP_FAMILY_RV200) ||
(rinfo->family == CHIP_FAMILY_RV250)) &&
((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13))
tmp |= SCLK_MORE_CNTL__FORCEON;
OUTPLL(pllSCLK_MORE_CNTL, tmp);
radeon_msleep(15);
}
/* RV200::A11 A12, RV250::A11 A12 */
if (((rinfo->family == CHIP_FAMILY_RV200) ||
(rinfo->family == CHIP_FAMILY_RV250)) &&
((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) {
tmp = INPLL(pllPLL_PWRMGT_CNTL);
tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE;
OUTPLL(pllPLL_PWRMGT_CNTL, tmp);
radeon_msleep(15);
}
tmp = INPLL(pllPIXCLKS_CNTL);
tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb |
PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb;
OUTPLL(pllPIXCLKS_CNTL, tmp);
radeon_msleep(15);
tmp = INPLL(pllVCLK_ECP_CNTL);
tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb |
VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb;
OUTPLL(pllVCLK_ECP_CNTL, tmp);
/* X doesn't do that ... hrm, we do on mobility && Macs */
#ifdef CONFIG_PPC
if (rinfo->is_mobility) {
tmp = INPLL(pllMCLK_CNTL);
tmp &= ~(MCLK_CNTL__FORCE_MCLKA |
MCLK_CNTL__FORCE_MCLKB |
MCLK_CNTL__FORCE_YCLKA |
MCLK_CNTL__FORCE_YCLKB);
OUTPLL(pllMCLK_CNTL, tmp);
radeon_msleep(15);
tmp = INPLL(pllMCLK_MISC);
tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT|
MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT|
MCLK_MISC__MC_MCLK_DYN_ENABLE|
MCLK_MISC__IO_MCLK_DYN_ENABLE;
OUTPLL(pllMCLK_MISC, tmp);
radeon_msleep(15);
}
#endif /* CONFIG_PPC */
}
#ifdef CONFIG_PM
static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
{
OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN);
OUTREG( MC_IND_DATA, value);
}
static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
{
OUTREG( MC_IND_INDEX, indx);
return INREG( MC_IND_DATA);
}
static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
{
rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
rinfo->save_regs[2] = INPLL(MCLK_CNTL);
rinfo->save_regs[3] = INPLL(SCLK_CNTL);
rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
rinfo->save_regs[7] = INPLL(MCLK_MISC);
rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
rinfo->save_regs[14] = INREG(BUS_CNTL1);
rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
rinfo->save_regs[16] = INREG(AGP_CNTL);
rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
rinfo->save_regs[19] = INREG(GPIOPAD_A);
rinfo->save_regs[20] = INREG(GPIOPAD_EN);
rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
rinfo->save_regs[27] = INREG(GPIO_MONID);
rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
rinfo->save_regs[29] = INREG(SURFACE_CNTL);
rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
rinfo->save_regs[36] = INREG(BUS_CNTL);
rinfo->save_regs[39] = INREG(RBBM_CNTL);
rinfo->save_regs[40] = INREG(DAC_CNTL);
rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
rinfo->save_regs[38] = INREG(FCP_CNTL);
if (rinfo->is_mobility) {
rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
}
if (rinfo->family >= CHIP_FAMILY_RV200) {
rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
rinfo->save_regs[46] = INREG(MC_CNTL);
rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
rinfo->save_regs[53] = INREG(MC_DEBUG);
}
rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
rinfo->save_regs[57] = INREG(FW_CNTL);
if (rinfo->family >= CHIP_FAMILY_R300) {
rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
} else {
rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
}
rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
rinfo->save_regs[84] = INREG(TMDS_CNTL);
rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
rinfo->save_regs[96] = INREG(HDP_DEBUG);
rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
}
static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
{
OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
if (rinfo->family == CHIP_FAMILY_RV350)
OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
OUTREG(AGP_CNTL, rinfo->save_regs[16]);
OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
OUTREG(GPIO_MONID, rinfo->save_regs[27]);
OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
}
static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
{
OUTREG(GPIOPAD_MASK, 0x0001ffff);
OUTREG(GPIOPAD_EN, 0x00000400);
OUTREG(GPIOPAD_A, 0x00000000);
OUTREG(ZV_LCDPAD_MASK, 0x00000000);
OUTREG(ZV_LCDPAD_EN, 0x00000000);
OUTREG(ZV_LCDPAD_A, 0x00000000);
OUTREG(GPIO_VGA_DDC, 0x00030000);
OUTREG(GPIO_DVI_DDC, 0x00000000);
OUTREG(GPIO_MONID, 0x00030000);
OUTREG(GPIO_CRT2_DDC, 0x00000000);
}
static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
{
/* Set v2clk to 65MHz */
if (rinfo->family <= CHIP_FAMILY_RV280) {
OUTPLL(pllPIXCLKS_CNTL,
__INPLL(rinfo, pllPIXCLKS_CNTL)
& ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK);
OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
OUTPLL(pllP2PLL_CNTL, 0x0000bf00);
} else {
OUTPLL(pllP2PLL_REF_DIV, 0x0000000c);
INPLL(pllP2PLL_REF_DIV);
OUTPLL(pllP2PLL_CNTL, 0x0000a700);
}
OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W);
OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP);
mdelay(1);
OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET);
mdelay( 1);
OUTPLL(pllPIXCLKS_CNTL,
(INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK)
| (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT));
mdelay( 1);
}
static void radeon_pm_low_current(struct radeonfb_info *rinfo)
{
u32 reg;
reg = INREG(BUS_CNTL1);
if (rinfo->family <= CHIP_FAMILY_RV280) {
reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
} else {
reg |= 0x4080;
}
OUTREG(BUS_CNTL1, reg);
reg = INPLL(PLL_PWRMGT_CNTL);
reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
OUTPLL(PLL_PWRMGT_CNTL, reg);
reg = INREG(TV_DAC_CNTL);
reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
TV_DAC_CNTL_BDACPD |
(8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
OUTREG(TV_DAC_CNTL, reg);
reg = INREG(TMDS_TRANSMITTER_CNTL);
reg &= ~(TMDS_PLL_EN | TMDS_PLLRST);
OUTREG(TMDS_TRANSMITTER_CNTL, reg);
reg = INREG(DAC_CNTL);
reg &= ~DAC_CMP_EN;
OUTREG(DAC_CNTL, reg);
reg = INREG(DAC_CNTL2);
reg &= ~DAC2_CMP_EN;
OUTREG(DAC_CNTL2, reg);
reg = INREG(TV_DAC_CNTL);
reg &= ~TV_DAC_CNTL_DETECT;
OUTREG(TV_DAC_CNTL, reg);
}
static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
{
u32 sclk_cntl, mclk_cntl, sclk_more_cntl;
u32 pll_pwrmgt_cntl;
u32 clk_pwrmgt_cntl;
u32 clk_pin_cntl;
u32 vclk_ecp_cntl;
u32 pixclks_cntl;
u32 disp_mis_cntl;
u32 disp_pwr_man;
u32 tmp;
/* Force Core Clocks */
sclk_cntl = INPLL( pllSCLK_CNTL);
sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
SCLK_CNTL__VIP_MAX_DYN_STOP_LAT|
SCLK_CNTL__RE_MAX_DYN_STOP_LAT|
SCLK_CNTL__PB_MAX_DYN_STOP_LAT|
SCLK_CNTL__TAM_MAX_DYN_STOP_LAT|
SCLK_CNTL__TDM_MAX_DYN_STOP_LAT|
SCLK_CNTL__RB_MAX_DYN_STOP_LAT|
SCLK_CNTL__FORCE_DISP2|
SCLK_CNTL__FORCE_CP|
SCLK_CNTL__FORCE_HDP|
SCLK_CNTL__FORCE_DISP1|
SCLK_CNTL__FORCE_TOP|
SCLK_CNTL__FORCE_E2|
SCLK_CNTL__FORCE_SE|
SCLK_CNTL__FORCE_IDCT|
SCLK_CNTL__FORCE_VIP|
SCLK_CNTL__FORCE_PB|
SCLK_CNTL__FORCE_TAM|
SCLK_CNTL__FORCE_TDM|
SCLK_CNTL__FORCE_RB|
SCLK_CNTL__FORCE_TV_SCLK|
SCLK_CNTL__FORCE_SUBPIC|
SCLK_CNTL__FORCE_OV0;
if (rinfo->family <= CHIP_FAMILY_RV280)
sclk_cntl |= SCLK_CNTL__FORCE_RE;
else
sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
SCLK_CNTL__CP_MAX_DYN_STOP_LAT;
OUTPLL( pllSCLK_CNTL, sclk_cntl);
sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL);
sclk_more_cntl |= SCLK_MORE_CNTL__FORCE_DISPREGS |
SCLK_MORE_CNTL__FORCE_MC_GUI |
SCLK_MORE_CNTL__FORCE_MC_HOST;
OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl);
mclk_cntl = INPLL( pllMCLK_CNTL);
mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA |
MCLK_CNTL__FORCE_MCLKB |
MCLK_CNTL__FORCE_YCLKA |
MCLK_CNTL__FORCE_YCLKB |
MCLK_CNTL__FORCE_MC
);
OUTPLL( pllMCLK_CNTL, mclk_cntl);
/* Force Display clocks */
vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL);
vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
| VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb);
vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON;
OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl);
pixclks_cntl = INPLL( pllPIXCLKS_CNTL);
pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb |
PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb|
PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb|
PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb|
PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb);
OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl);
/* Switch off LVDS interface */
OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) &
~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON));
/* Enable System power management */
pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL);
pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF |
PLL_PWRMGT_CNTL__MPLL_TURNOFF|
PLL_PWRMGT_CNTL__PPLL_TURNOFF|
PLL_PWRMGT_CNTL__P2PLL_TURNOFF|
PLL_PWRMGT_CNTL__TVPLL_TURNOFF;
OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF|
CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF|
CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF|
CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF|
CLK_PWRMGT_CNTL__MCLK_TURNOFF|
CLK_PWRMGT_CNTL__SCLK_TURNOFF|
CLK_PWRMGT_CNTL__PCLK_TURNOFF|
CLK_PWRMGT_CNTL__P2CLK_TURNOFF|
CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF|
CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN|
CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE|
CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK|
CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK
);
clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN
| CLK_PWRMGT_CNTL__DISP_PM;
OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND;
/* because both INPLL and OUTPLL take the same lock, that's why. */
tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND;
OUTPLL( pllMCLK_MISC, tmp);
/* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset
* and radeon chip dependent. Thus we only enable it on Mac for
* now (until we get more info on how to compute the correct
* value for various X86 bridges).
*/
#ifdef CONFIG_PPC_PMAC
if (machine_is(powermac)) {
/* AGP PLL control */
if (rinfo->family <= CHIP_FAMILY_RV280) {
OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID);
OUTREG(BUS_CNTL1,
(INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK)
| (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX
} else {
OUTREG(BUS_CNTL1, INREG(BUS_CNTL1));
OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000);
}
}
#endif
OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL)
& ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN));
clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN;
clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
/* Solano2M */
OUTREG(AGP_CNTL,
(INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK))
| (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT));
/* ACPI mode */
/* because both INPLL and OUTPLL take the same lock, that's why. */
tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL;
OUTPLL( pllPLL_PWRMGT_CNTL, tmp);
disp_mis_cntl = INREG(DISP_MISC_CNTL);
disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP |
DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP |
DISP_MISC_CNTL__SOFT_RESET_OV0_PP |
DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK|
DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK|
DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK|
DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP|
DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK|
DISP_MISC_CNTL__SOFT_RESET_LVDS|
DISP_MISC_CNTL__SOFT_RESET_TMDS|
DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS|
DISP_MISC_CNTL__SOFT_RESET_TV);
OUTREG(DISP_MISC_CNTL, disp_mis_cntl);
disp_pwr_man = INREG(DISP_PWR_MAN);
disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN |
DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK|
DISP_PWR_MAN__DISP_D3_RST|
DISP_PWR_MAN__DISP_D3_REG_RST
);
disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST|
DISP_PWR_MAN__DISP_D3_SUBPIC_RST|
DISP_PWR_MAN__DISP_D3_OV0_RST|
DISP_PWR_MAN__DISP_D1D2_GRPH_RST|
DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST|
DISP_PWR_MAN__DISP_D1D2_OV0_RST|
DISP_PWR_MAN__DIG_TMDS_ENABLE_RST|
DISP_PWR_MAN__TV_ENABLE_RST|
// DISP_PWR_MAN__AUTO_PWRUP_EN|
0;
OUTREG(DISP_PWR_MAN, disp_pwr_man);
clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL);
pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ;
clk_pin_cntl = INPLL( pllCLK_PIN_CNTL);
disp_pwr_man = INREG(DISP_PWR_MAN);
/* D2 */
clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM;
pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK;
clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb;
disp_pwr_man &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK
| DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK);
OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl);
OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl);
OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl);
OUTREG(DISP_PWR_MAN, disp_pwr_man);
/* disable display request & disable display */
OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN)
| CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN)
| CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
mdelay(17);
}
static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
{
u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
& ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
& ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
| (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
| (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
mdelay( 1);
}
static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
{
u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1;
mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
& ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK;
mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
& ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK;
OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT));
OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT));
OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
mdelay( 1);
}
static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
u8 delay_required)
{
u32 mem_sdram_mode;
mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG);
mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK;
mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT)
| MEM_SDRAM_MODE_REG__MEM_CFG_TYPE;
OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
if (delay_required >= 2)
mdelay(1);
mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
if (delay_required >= 2)
mdelay(1);
mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET;
OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode);
if (delay_required >= 2)
mdelay(1);
if (delay_required) {
do {
if (delay_required >= 2)
mdelay(1);
} while ((INREG(MC_STATUS)
& (MC_STATUS__MEM_PWRUP_COMPL_A |
MC_STATUS__MEM_PWRUP_COMPL_B)) == 0);
}
}
static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
{
int cnt;
for (cnt = 0; cnt < 100; ++cnt) {
mdelay(1);
if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A
| MC_STATUS__MEM_PWRUP_COMPL_B))
break;
}
}
static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
{
#define DLL_RESET_DELAY 5
#define DLL_SLEEP_DELAY 1
u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP
| MDLL_CKO__MCKOA_RESET;
u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP
| MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET
| MDLL_RDCKA__MRDCKA1_RESET;
u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP
| MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET
| MDLL_RDCKB__MRDCKB1_RESET;
/* Setting up the DLL range for write */
OUTPLL(pllMDLL_CKO, cko);
OUTPLL(pllMDLL_RDCKA, cka);
OUTPLL(pllMDLL_RDCKB, ckb);
mdelay(DLL_RESET_DELAY*2);
cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
OUTPLL(pllMDLL_CKO, cko);
mdelay(DLL_SLEEP_DELAY);
cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
OUTPLL(pllMDLL_CKO, cko);
mdelay(DLL_RESET_DELAY);
cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
OUTPLL(pllMDLL_RDCKA, cka);
mdelay(DLL_SLEEP_DELAY);
cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
OUTPLL(pllMDLL_RDCKA, cka);
mdelay(DLL_RESET_DELAY);
ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
OUTPLL(pllMDLL_RDCKB, ckb);
mdelay(DLL_SLEEP_DELAY);
ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
OUTPLL(pllMDLL_RDCKB, ckb);
mdelay(DLL_RESET_DELAY);
#undef DLL_RESET_DELAY
#undef DLL_SLEEP_DELAY
}
static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
{
u32 dll_value;
u32 dll_sleep_mask = 0;
u32 dll_reset_mask = 0;
u32 mc;
#define DLL_RESET_DELAY 5
#define DLL_SLEEP_DELAY 1
OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
mc = INREG(MC_CNTL);
/* Check which channels are enabled */
switch (mc & 0x3) {
case 1:
if (mc & 0x4)
break;
fallthrough;
case 2:
dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP;
dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET;
fallthrough;
case 0:
dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP;
dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET;
}
switch (mc & 0x3) {
case 1:
if (!(mc & 0x4))
break;
fallthrough;
case 2:
dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP;
dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET;
dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP;
dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET;
}
dll_value = INPLL(pllMDLL_RDCKA);
/* Power Up */
dll_value &= ~(dll_sleep_mask);
OUTPLL(pllMDLL_RDCKA, dll_value);
mdelay( DLL_SLEEP_DELAY);
dll_value &= ~(dll_reset_mask);
OUTPLL(pllMDLL_RDCKA, dll_value);
mdelay( DLL_RESET_DELAY);
#undef DLL_RESET_DELAY
#undef DLL_SLEEP_DELAY
}
static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
{
u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl,
fp_gen_cntl, fp2_gen_cntl;
crtcGenCntl = INREG( CRTC_GEN_CNTL);
crtcGenCntl2 = INREG( CRTC2_GEN_CNTL);
crtc_more_cntl = INREG( CRTC_MORE_CNTL);
fp_gen_cntl = INREG( FP_GEN_CNTL);
fp2_gen_cntl = INREG( FP2_GEN_CNTL);
OUTREG( CRTC_MORE_CNTL, 0);
OUTREG( FP_GEN_CNTL, 0);
OUTREG( FP2_GEN_CNTL,0);
OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) );
OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) );
/* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */
if (rinfo->family == CHIP_FAMILY_RV350) {
u32 sdram_mode_reg = rinfo->save_regs[35];
static const u32 default_mrtable[] =
{ 0x21320032,
0x21321000, 0xa1321000, 0x21321000, 0xffffffff,
0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
0x21321002, 0xa1321002, 0x21321002, 0xffffffff,
0x21320132, 0xa1320132, 0x21320132, 0xffffffff,
0x21320032, 0xa1320032, 0x21320032, 0xffffffff,
0x31320032 };
const u32 *mrtable = default_mrtable;
int i, mrtable_size = ARRAY_SIZE(default_mrtable);
mdelay(30);
/* Disable refresh */
memRefreshCntl = INREG( MEM_REFRESH_CNTL)
& ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
| MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
/* Configure and enable M & SPLLs */
radeon_pm_enable_dll_m10(rinfo);
radeon_pm_yclk_mclk_sync_m10(rinfo);
#ifdef CONFIG_PPC
if (rinfo->of_node != NULL) {
int size;
mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size);
if (mrtable)
mrtable_size = size >> 2;
else
mrtable = default_mrtable;
}
#endif /* CONFIG_PPC */
/* Program the SDRAM */
sdram_mode_reg = mrtable[0];
OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
for (i = 0; i < mrtable_size; i++) {
if (mrtable[i] == 0xffffffffu)
radeon_pm_m10_program_mode_wait(rinfo);
else {
sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK
| MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE
| MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET);
sdram_mode_reg |= mrtable[i];
OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg);
mdelay(1);
}
}
/* Restore memory refresh */
OUTREG(MEM_REFRESH_CNTL, memRefreshCntl);
mdelay(30);
}
/* Here come the desktop RV200 "QW" card */
else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
/* Disable refresh */
memRefreshCntl = INREG( MEM_REFRESH_CNTL)
& ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
OUTREG(MEM_REFRESH_CNTL, memRefreshCntl
| MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
mdelay(30);
/* Reset memory */
OUTREG(MEM_SDRAM_MODE_REG,
INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
OUTREG(MEM_SDRAM_MODE_REG,
INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
}
/* The M6 */
else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
/* Disable refresh */
memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20);
OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20));
/* Reset memory */
OUTREG( MEM_SDRAM_MODE_REG,
INREG( MEM_SDRAM_MODE_REG)
& ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
/* DLL */
radeon_pm_enable_dll(rinfo);
/* MLCK / YCLK sync */
radeon_pm_yclk_mclk_sync(rinfo);
/* Program Mode Register */
radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
/* Complete & re-enable refresh */
OUTREG( MEM_SDRAM_MODE_REG,
INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
OUTREG(EXT_MEM_CNTL, memRefreshCntl);
}
/* And finally, the M7..M9 models, including M9+ (RV280) */
else if (rinfo->is_mobility) {
/* Disable refresh */
memRefreshCntl = INREG( MEM_REFRESH_CNTL)
& ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS;
OUTREG( MEM_REFRESH_CNTL, memRefreshCntl
| MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
/* Reset memory */
OUTREG( MEM_SDRAM_MODE_REG,
INREG( MEM_SDRAM_MODE_REG)
& ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
/* DLL */
radeon_pm_enable_dll(rinfo);
/* MLCK / YCLK sync */
radeon_pm_yclk_mclk_sync(rinfo);
/* M6, M7 and M9 so far ... */
if (rinfo->family <= CHIP_FAMILY_RV250) {
radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
}
/* M9+ (iBook G4) */
else if (rinfo->family == CHIP_FAMILY_RV280) {
radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
}
/* Complete & re-enable refresh */
OUTREG( MEM_SDRAM_MODE_REG,
INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
OUTREG( MEM_REFRESH_CNTL, memRefreshCntl);
}
OUTREG( CRTC_GEN_CNTL, crtcGenCntl);
OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2);
OUTREG( FP_GEN_CNTL, fp_gen_cntl);
OUTREG( FP2_GEN_CNTL, fp2_gen_cntl);
OUTREG( CRTC_MORE_CNTL, crtc_more_cntl);
mdelay( 15);
}
#if defined(CONFIG_X86) || defined(CONFIG_PPC_PMAC)
static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
{
u32 tmp, tmp2;
int i,j;
/* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */
INREG(PAD_CTLR_STRENGTH);
OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE);
tmp = INREG(PAD_CTLR_STRENGTH);
for (i = j = 0; i < 65; ++i) {
mdelay(1);
tmp2 = INREG(PAD_CTLR_STRENGTH);
if (tmp != tmp2) {
tmp = tmp2;
i = 0;
j++;
if (j > 10) {
printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't "
"stabilize !\n");
break;
}
}
}
}
static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
{
u32 tmp;
tmp = INPLL(pllPPLL_CNTL);
OUTPLL(pllPPLL_CNTL, tmp | 0x3);
tmp = INPLL(pllP2PLL_CNTL);
OUTPLL(pllP2PLL_CNTL, tmp | 0x3);
tmp = INPLL(pllSPLL_CNTL);
OUTPLL(pllSPLL_CNTL, tmp | 0x3);
tmp = INPLL(pllMPLL_CNTL);
OUTPLL(pllMPLL_CNTL, tmp | 0x3);
}
static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
{
u32 tmp;
/* Switch SPLL to PCI source */
tmp = INPLL(pllSCLK_CNTL);
OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK);
/* Reconfigure SPLL charge pump, VCO gain, duty cycle */
tmp = INPLL(pllSPLL_CNTL);
OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
radeon_pll_errata_after_index(rinfo);
OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
radeon_pll_errata_after_data(rinfo);
/* Set SPLL feedback divider */
tmp = INPLL(pllM_SPLL_REF_FB_DIV);
tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
/* Power up SPLL */
tmp = INPLL(pllSPLL_CNTL);
OUTPLL(pllSPLL_CNTL, tmp & ~1);
(void)INPLL(pllSPLL_CNTL);
mdelay(10);
/* Release SPLL reset */
tmp = INPLL(pllSPLL_CNTL);
OUTPLL(pllSPLL_CNTL, tmp & ~0x2);
(void)INPLL(pllSPLL_CNTL);
mdelay(10);
/* Select SCLK source */
tmp = INPLL(pllSCLK_CNTL);
tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK;
tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
OUTPLL(pllSCLK_CNTL, tmp);
(void)INPLL(pllSCLK_CNTL);
mdelay(10);
/* Reconfigure MPLL charge pump, VCO gain, duty cycle */
tmp = INPLL(pllMPLL_CNTL);
OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN);
radeon_pll_errata_after_index(rinfo);
OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
radeon_pll_errata_after_data(rinfo);
/* Set MPLL feedback divider */
tmp = INPLL(pllM_SPLL_REF_FB_DIV);
tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
OUTPLL(pllM_SPLL_REF_FB_DIV, tmp);
/* Power up MPLL */
tmp = INPLL(pllMPLL_CNTL);
OUTPLL(pllMPLL_CNTL, tmp & ~0x2);
(void)INPLL(pllMPLL_CNTL);
mdelay(10);
/* Un-reset MPLL */
tmp = INPLL(pllMPLL_CNTL);
OUTPLL(pllMPLL_CNTL, tmp & ~0x1);
(void)INPLL(pllMPLL_CNTL);
mdelay(10);
/* Select source for MCLK */
tmp = INPLL(pllMCLK_CNTL);
tmp |= rinfo->save_regs[2] & 0xffff;
OUTPLL(pllMCLK_CNTL, tmp);
(void)INPLL(pllMCLK_CNTL);
mdelay(10);
}
static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
{
u32 r2ec;
/* GACK ! I though we didn't have a DDA on Radeon's anymore
* here we rewrite with the same value, ... I suppose we clear
* some bits that are already clear ? Or maybe this 0x2ec
* register is something new ?
*/
mdelay(20);
r2ec = INREG(VGA_DDA_ON_OFF);
OUTREG(VGA_DDA_ON_OFF, r2ec);
mdelay(1);
/* Spread spectrum PLLL off */
OUTPLL(pllSSPLL_CNTL, 0xbf03);
/* Spread spectrum disabled */
OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
/* The trace shows read & rewrite of LVDS_PLL_CNTL here with same
* value, not sure what for...
*/
r2ec |= 0x3f0;
OUTREG(VGA_DDA_ON_OFF, r2ec);
mdelay(1);
}
static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
{
u32 r2ec, tmp;
/* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore
* here we rewrite with the same value, ... I suppose we clear/set
* some bits that are already clear/set ?
*/
r2ec = INREG(VGA_DDA_ON_OFF);
OUTREG(VGA_DDA_ON_OFF, r2ec);
mdelay(1);
/* Enable spread spectrum */
OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
mdelay(3);
OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
tmp = INPLL(pllSSPLL_CNTL);
OUTPLL(pllSSPLL_CNTL, tmp & ~0x2);
mdelay(6);
tmp = INPLL(pllSSPLL_CNTL);
OUTPLL(pllSSPLL_CNTL, tmp & ~0x1);
mdelay(5);
OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
r2ec |= 8;
OUTREG(VGA_DDA_ON_OFF, r2ec);
mdelay(20);
/* Enable LVDS interface */
tmp = INREG(LVDS_GEN_CNTL);
OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN);
/* Enable LVDS_PLL */
tmp = INREG(LVDS_PLL_CNTL);
tmp &= ~0x30000;
tmp |= 0x10000;
OUTREG(LVDS_PLL_CNTL, tmp);
OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
/* The trace reads that one here, waiting for something to settle down ? */
INREG(RBBM_STATUS);
/* Ugh ? SS_TST_DEC is supposed to be a read register in the
* R300 register spec at least...
*/
tmp = INPLL(pllSS_TST_CNTL);
tmp |= 0x00400000;
OUTPLL(pllSS_TST_CNTL, tmp);
}
static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
{
u32 tmp;
OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN);
radeon_pll_errata_after_index(rinfo);
OUTREG8(CLOCK_CNTL_DATA, 0);
radeon_pll_errata_after_data(rinfo);
tmp = INPLL(pllVCLK_ECP_CNTL);
OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80);
mdelay(5);
tmp = INPLL(pllPPLL_REF_DIV);
tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
OUTPLL(pllPPLL_REF_DIV, tmp);
INPLL(pllPPLL_REF_DIV);
/* Reconfigure SPLL charge pump, VCO gain, duty cycle,
* probably useless since we already did it ...
*/
tmp = INPLL(pllPPLL_CNTL);
OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN);
radeon_pll_errata_after_index(rinfo);
OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
radeon_pll_errata_after_data(rinfo);
/* Restore our "reference" PPLL divider set by firmware
* according to proper spread spectrum calculations
*/
OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
tmp = INPLL(pllPPLL_CNTL);
OUTPLL(pllPPLL_CNTL, tmp & ~0x2);
mdelay(5);
tmp = INPLL(pllPPLL_CNTL);
OUTPLL(pllPPLL_CNTL, tmp & ~0x1);
mdelay(5);
tmp = INPLL(pllVCLK_ECP_CNTL);
OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
mdelay(5);
tmp = INPLL(pllVCLK_ECP_CNTL);
OUTPLL(pllVCLK_ECP_CNTL, tmp | 3);
mdelay(5);
/* Switch pixel clock to firmware default div 0 */
OUTREG8(CLOCK_CNTL_INDEX+1, 0);
radeon_pll_errata_after_index(rinfo);
radeon_pll_errata_after_data(rinfo);
}
static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
{
OUTREG(MC_CNTL, rinfo->save_regs[46]);
OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
OUTREG(MEM_SDRAM_MODE_REG,
rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
OUTREG(MC_DEBUG, rinfo->save_regs[53]);
OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
OUTREG(MC_IND_INDEX, 0);
}
static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
{
u32 tmp, i;
/* Restore a bunch of registers first */
OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
OUTREG(BUS_CNTL, rinfo->save_regs[36]);
OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
OUTREG(FCP_CNTL, rinfo->save_regs[38]);
OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
OUTREG(DAC_CNTL, rinfo->save_regs[40]);
OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8);
/* Hrm... */
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
/* Reset the PAD CTLR */
radeon_pm_reset_pad_ctlr_strength(rinfo);
/* Some PLLs are Read & written identically in the trace here...
* I suppose it's actually to switch them all off & reset,
* let's assume off is what we want. I'm just doing that for all major PLLs now.
*/
radeon_pm_all_ppls_off(rinfo);
/* Clear tiling, reset swappers */
INREG(SURFACE_CNTL);
OUTREG(SURFACE_CNTL, 0);
/* Some black magic with TV_DAC_CNTL, we should restore those from backups
* rather than hard coding...
*/
tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT;
OUTREG(TV_DAC_CNTL, tmp);
tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT;
OUTREG(TV_DAC_CNTL, tmp);
/* More registers restored */
OUTREG(AGP_CNTL, rinfo->save_regs[16]);
OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
/* Hrmmm ... What is that ? */
tmp = rinfo->save_regs[1]
& ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
CLK_PWRMGT_CNTL__MC_BUSY);
OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
OUTREG(FW_CNTL, rinfo->save_regs[57]);
OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
/* Restore Memory Controller configuration */
radeon_pm_m10_reconfigure_mc(rinfo);
/* Make sure CRTC's dont touch memory */
OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)
| CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B);
OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)
| CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B);
mdelay(30);
/* Disable SDRAM refresh */
OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
| MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
/* Restore XTALIN routing (CLK_PIN_CNTL) */
OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
/* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */
tmp = rinfo->save_regs[2] & 0xff000000;
tmp |= MCLK_CNTL__FORCE_MCLKA |
MCLK_CNTL__FORCE_MCLKB |
MCLK_CNTL__FORCE_YCLKA |
MCLK_CNTL__FORCE_YCLKB |
MCLK_CNTL__FORCE_MC;
OUTPLL(pllMCLK_CNTL, tmp);
/* Force all clocks on in SCLK */
tmp = INPLL(pllSCLK_CNTL);
tmp |= SCLK_CNTL__FORCE_DISP2|
SCLK_CNTL__FORCE_CP|
SCLK_CNTL__FORCE_HDP|
SCLK_CNTL__FORCE_DISP1|
SCLK_CNTL__FORCE_TOP|
SCLK_CNTL__FORCE_E2|
SCLK_CNTL__FORCE_SE|
SCLK_CNTL__FORCE_IDCT|
SCLK_CNTL__FORCE_VIP|
SCLK_CNTL__FORCE_PB|
SCLK_CNTL__FORCE_TAM|
SCLK_CNTL__FORCE_TDM|
SCLK_CNTL__FORCE_RB|
SCLK_CNTL__FORCE_TV_SCLK|
SCLK_CNTL__FORCE_SUBPIC|
SCLK_CNTL__FORCE_OV0;
tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT |
SCLK_CNTL__HDP_MAX_DYN_STOP_LAT |
SCLK_CNTL__TV_MAX_DYN_STOP_LAT |
SCLK_CNTL__E2_MAX_DYN_STOP_LAT |
SCLK_CNTL__SE_MAX_DYN_STOP_LAT |
SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT|
SCLK_CNTL__VIP_MAX_DYN_STOP_LAT |
SCLK_CNTL__RE_MAX_DYN_STOP_LAT |
SCLK_CNTL__PB_MAX_DYN_STOP_LAT |
SCLK_CNTL__TAM_MAX_DYN_STOP_LAT |
SCLK_CNTL__TDM_MAX_DYN_STOP_LAT |
SCLK_CNTL__RB_MAX_DYN_STOP_LAT;
OUTPLL(pllSCLK_CNTL, tmp);
OUTPLL(pllVCLK_ECP_CNTL, 0);
OUTPLL(pllPIXCLKS_CNTL, 0);
OUTPLL(pllMCLK_MISC,
MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
mdelay(5);
/* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */
OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
/* Now restore the major PLLs settings, keeping them off & reset though */
OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
/* Restore MC DLL state and switch it off/reset too */
OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
/* Switch MDLL off & reset */
OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
mdelay(5);
/* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved
* 0xa1100007... and MacOS writes 0xa1000007 ..
*/
OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
/* Restore more stuffs */
OUTPLL(pllHTOTAL_CNTL, 0);
OUTPLL(pllHTOTAL2_CNTL, 0);
/* More PLL initial configuration */
tmp = INPLL(pllSCLK_CNTL2); /* What for ? */
OUTPLL(pllSCLK_CNTL2, tmp);
tmp = INPLL(pllSCLK_MORE_CNTL);
tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */
SCLK_MORE_CNTL__FORCE_MC_GUI |
SCLK_MORE_CNTL__FORCE_MC_HOST;
OUTPLL(pllSCLK_MORE_CNTL, tmp);
/* Now we actually start MCLK and SCLK */
radeon_pm_start_mclk_sclk(rinfo);
/* Full reset sdrams, this also re-inits the MDLL */
radeon_pm_full_reset_sdram(rinfo);
/* Fill palettes */
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
for (i=0; i<256; i++)
OUTREG(PALETTE_30_DATA, 0x15555555);
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
udelay(20);
for (i=0; i<256; i++)
OUTREG(PALETTE_30_DATA, 0x15555555);
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
mdelay(3);
/* Restore TMDS */
OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
/* Set LVDS registers but keep interface & pll down */
OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
/* Restore GPIOPAD state */
OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
/* write some stuff to the framebuffer... */
for (i = 0; i < 0x8000; ++i)
writeb(0, rinfo->fb_base + i);
mdelay(40);
OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
mdelay(40);
/* Restore a few more things */
OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
/* Take care of spread spectrum & PPLLs now */
radeon_pm_m10_disable_spread_spectrum(rinfo);
radeon_pm_restore_pixel_pll(rinfo);
/* GRRRR... I can't figure out the proper LVDS power sequence, and the
* code I have for blank/unblank doesn't quite work on some laptop models
* it seems ... Hrm. What I have here works most of the time ...
*/
radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
}
#endif
#ifdef CONFIG_PPC
#ifdef CONFIG_PPC_PMAC
static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
{
OUTREG(MC_CNTL, rinfo->save_regs[46]);
OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
OUTREG(MEM_SDRAM_MODE_REG,
rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
OUTREG(MC_DEBUG, rinfo->save_regs[53]);
OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
OUTREG(MC_IND_INDEX, 0);
OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
mdelay(20);
}
static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
{
u32 tmp, i;
/* Restore a bunch of registers first */
OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
OUTREG(BUS_CNTL, rinfo->save_regs[36]);
OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
OUTREG(FCP_CNTL, rinfo->save_regs[38]);
OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
OUTREG(DAC_CNTL, rinfo->save_regs[40]);
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE);
/* Reset the PAD CTLR */
radeon_pm_reset_pad_ctlr_strength(rinfo);
/* Some PLLs are Read & written identically in the trace here...
* I suppose it's actually to switch them all off & reset,
* let's assume off is what we want. I'm just doing that for all major PLLs now.
*/
radeon_pm_all_ppls_off(rinfo);
/* Clear tiling, reset swappers */
INREG(SURFACE_CNTL);
OUTREG(SURFACE_CNTL, 0);
/* Some black magic with TV_DAC_CNTL, we should restore those from backups
* rather than hard coding...
*/
tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK;
tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT;
OUTREG(TV_DAC_CNTL, tmp);
tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK;
tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT;
OUTREG(TV_DAC_CNTL, tmp);
OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
OUTREG(AGP_CNTL, rinfo->save_regs[16]);
OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
tmp = rinfo->save_regs[1]
& ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK |
CLK_PWRMGT_CNTL__MC_BUSY);
OUTPLL(pllCLK_PWRMGT_CNTL, tmp);
OUTREG(FW_CNTL, rinfo->save_regs[57]);
/* Disable SDRAM refresh */
OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL)
| MEM_REFRESH_CNTL__MEM_REFRESH_DIS);
/* Restore XTALIN routing (CLK_PIN_CNTL) */
OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
/* Force MCLK to be PCI sourced and forced ON */
tmp = rinfo->save_regs[2] & 0xff000000;
tmp |= MCLK_CNTL__FORCE_MCLKA |
MCLK_CNTL__FORCE_MCLKB |
MCLK_CNTL__FORCE_YCLKA |
MCLK_CNTL__FORCE_YCLKB |
MCLK_CNTL__FORCE_MC |
MCLK_CNTL__FORCE_AIC;
OUTPLL(pllMCLK_CNTL, tmp);
/* Force SCLK to be PCI sourced with a bunch forced */
tmp = 0 |
SCLK_CNTL__FORCE_DISP2|
SCLK_CNTL__FORCE_CP|
SCLK_CNTL__FORCE_HDP|
SCLK_CNTL__FORCE_DISP1|
SCLK_CNTL__FORCE_TOP|
SCLK_CNTL__FORCE_E2|
SCLK_CNTL__FORCE_SE|
SCLK_CNTL__FORCE_IDCT|
SCLK_CNTL__FORCE_VIP|
SCLK_CNTL__FORCE_RE|
SCLK_CNTL__FORCE_PB|
SCLK_CNTL__FORCE_TAM|
SCLK_CNTL__FORCE_TDM|
SCLK_CNTL__FORCE_RB;
OUTPLL(pllSCLK_CNTL, tmp);
/* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */
OUTPLL(pllVCLK_ECP_CNTL, 0);
OUTPLL(pllPIXCLKS_CNTL, 0);
/* Setup MCLK_MISC, non dynamic mode */
OUTPLL(pllMCLK_MISC,
MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT |
MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT);
mdelay(5);
/* Set back the default clock dividers */
OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
/* PPLL and P2PLL default values & off */
OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
/* S and M PLLs are reset & off, configure them */
OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
/* Default values for MDLL ... fixme */
OUTPLL(pllMDLL_CKO, 0x9c009c);
OUTPLL(pllMDLL_RDCKA, 0x08830883);
OUTPLL(pllMDLL_RDCKB, 0x08830883);
mdelay(5);
/* Restore PLL_PWRMGT_CNTL */ // XXXX
tmp = rinfo->save_regs[0];
tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK;
tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
OUTPLL(PLL_PWRMGT_CNTL, tmp);
/* Clear HTOTAL_CNTL & HTOTAL2_CNTL */
OUTPLL(pllHTOTAL_CNTL, 0);
OUTPLL(pllHTOTAL2_CNTL, 0);
/* All outputs off */
OUTREG(CRTC_GEN_CNTL, 0x04000000);
OUTREG(CRTC2_GEN_CNTL, 0x04000000);
OUTREG(FP_GEN_CNTL, 0x00004008);
OUTREG(FP2_GEN_CNTL, 0x00000008);
OUTREG(LVDS_GEN_CNTL, 0x08000008);
/* Restore Memory Controller configuration */
radeon_pm_m9p_reconfigure_mc(rinfo);
/* Now we actually start MCLK and SCLK */
radeon_pm_start_mclk_sclk(rinfo);
/* Full reset sdrams, this also re-inits the MDLL */
radeon_pm_full_reset_sdram(rinfo);
/* Fill palettes */
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20);
for (i=0; i<256; i++)
OUTREG(PALETTE_30_DATA, 0x15555555);
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20);
udelay(20);
for (i=0; i<256; i++)
OUTREG(PALETTE_30_DATA, 0x15555555);
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20);
mdelay(3);
/* Restore TV stuff, make sure TV DAC is down */
OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
/* Restore GPIOS. MacOS does some magic here with one of the GPIO bits,
* possibly related to the weird PLL related workarounds and to the
* fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand,
* but we keep things the simple way here
*/
OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
/* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy
* high bits from backup
*/
tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
tmp |= rinfo->save_regs[34] & 0xffff0000;
tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
OUTPLL(pllSCLK_MORE_CNTL, tmp);
tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff;
tmp |= rinfo->save_regs[34] & 0xffff0000;
tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS;
OUTPLL(pllSCLK_MORE_CNTL, tmp);
OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN));
OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON);
OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
mdelay(20);
/* write some stuff to the framebuffer... */
for (i = 0; i < 0x8000; ++i)
writeb(0, rinfo->fb_base + i);
OUTREG(0x2ec, 0x6332a020);
OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
tmp = INPLL(pllSSPLL_CNTL);
tmp &= ~2;
OUTPLL(pllSSPLL_CNTL, tmp);
mdelay(6);
tmp &= ~1;
OUTPLL(pllSSPLL_CNTL, tmp);
mdelay(5);
tmp |= 3;
OUTPLL(pllSSPLL_CNTL, tmp);
mdelay(5);
OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
OUTREG(0x2ec, 0x6332a3f0);
mdelay(17);
OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
mdelay(40);
OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON);
mdelay(40);
/* Restore a few more things */
OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
/* Restore PPLL, spread spectrum & LVDS */
radeon_pm_m10_disable_spread_spectrum(rinfo);
radeon_pm_restore_pixel_pll(rinfo);
radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
}
#endif
#if 0 /* Not ready yet */
static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
{
int i;
u32 tmp, tmp2;
u32 cko, cka, ckb;
u32 cgc, cec, c2gc;
OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
OUTREG(BUS_CNTL, rinfo->save_regs[36]);
OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
INREG(PAD_CTLR_STRENGTH);
OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
for (i = 0; i < 65; ++i) {
mdelay(1);
INREG(PAD_CTLR_STRENGTH);
}
OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
OUTREG(DAC_CNTL, 0xff00410a);
OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
OUTREG(AGP_CNTL, rinfo->save_regs[16]);
OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
OUTREG(MC_IND_INDEX, 0);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
OUTREG(MC_IND_INDEX, 0);
OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
tmp = INPLL(pllVCLK_ECP_CNTL);
OUTPLL(pllVCLK_ECP_CNTL, tmp);
tmp = INPLL(pllPIXCLKS_CNTL);
OUTPLL(pllPIXCLKS_CNTL, tmp);
OUTPLL(MCLK_CNTL, 0xaa3f0000);
OUTPLL(SCLK_CNTL, 0xffff0000);
OUTPLL(pllMPLL_AUX_CNTL, 6);
OUTPLL(pllSPLL_AUX_CNTL, 1);
OUTPLL(MDLL_CKO, 0x9f009f);
OUTPLL(MDLL_RDCKA, 0x830083);
OUTPLL(pllMDLL_RDCKB, 0x830083);
OUTPLL(PPLL_CNTL, 0xa433);
OUTPLL(P2PLL_CNTL, 0xa433);
OUTPLL(MPLL_CNTL, 0x0400a403);
OUTPLL(SPLL_CNTL, 0x0400a433);
tmp = INPLL(M_SPLL_REF_FB_DIV);
OUTPLL(M_SPLL_REF_FB_DIV, tmp);
tmp = INPLL(M_SPLL_REF_FB_DIV);
OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc);
INPLL(M_SPLL_REF_FB_DIV);
tmp = INPLL(MPLL_CNTL);
OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN);
radeon_pll_errata_after_index(rinfo);
OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
radeon_pll_errata_after_data(rinfo);
tmp = INPLL(M_SPLL_REF_FB_DIV);
OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900);
tmp = INPLL(MPLL_CNTL);
OUTPLL(MPLL_CNTL, tmp & ~0x2);
mdelay(1);
tmp = INPLL(MPLL_CNTL);
OUTPLL(MPLL_CNTL, tmp & ~0x1);
mdelay(10);
OUTPLL(MCLK_CNTL, 0xaa3f1212);
mdelay(1);
INPLL(M_SPLL_REF_FB_DIV);
INPLL(MCLK_CNTL);
INPLL(M_SPLL_REF_FB_DIV);
tmp = INPLL(SPLL_CNTL);
OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN);
radeon_pll_errata_after_index(rinfo);
OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff);
radeon_pll_errata_after_data(rinfo);
tmp = INPLL(M_SPLL_REF_FB_DIV);
OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000);
tmp = INPLL(SPLL_CNTL);
OUTPLL(SPLL_CNTL, tmp & ~0x1);
mdelay(1);
tmp = INPLL(SPLL_CNTL);
OUTPLL(SPLL_CNTL, tmp & ~0x2);
mdelay(10);
tmp = INPLL(SCLK_CNTL);
OUTPLL(SCLK_CNTL, tmp | 2);
mdelay(1);
cko = INPLL(pllMDLL_CKO);
cka = INPLL(pllMDLL_RDCKA);
ckb = INPLL(pllMDLL_RDCKB);
cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP);
OUTPLL(pllMDLL_CKO, cko);
mdelay(1);
cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET);
OUTPLL(pllMDLL_CKO, cko);
mdelay(5);
cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP);
OUTPLL(pllMDLL_RDCKA, cka);
mdelay(1);
cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET);
OUTPLL(pllMDLL_RDCKA, cka);
mdelay(5);
ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP);
OUTPLL(pllMDLL_RDCKB, ckb);
mdelay(1);
ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET);
OUTPLL(pllMDLL_RDCKB, ckb);
mdelay(5);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
OUTREG(MC_IND_INDEX, 0);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
OUTREG(MC_IND_INDEX, 0);
mdelay(1);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
OUTREG(MC_IND_INDEX, 0);
OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
OUTREG(MC_IND_INDEX, 0);
mdelay(1);
OUTPLL(pllHTOTAL_CNTL, 0);
OUTPLL(pllHTOTAL2_CNTL, 0);
OUTREG(MEM_CNTL, 0x29002901);
OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */
OUTREG(EXT_MEM_CNTL, 0x1a394333);
OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac);
OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444);
OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */
OUTREG(MC_DEBUG, 0);
OUTREG(MEM_IO_OE_CNTL, 0x04300430);
OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
OUTREG(MC_IND_INDEX, 0);
OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
OUTREG(MC_IND_INDEX, 0);
OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
radeon_pm_full_reset_sdram(rinfo);
INREG(FP_GEN_CNTL);
OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */
tmp = INREG(FP_GEN_CNTL);
tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200;
OUTREG(FP_GEN_CNTL, tmp);
tmp = INREG(DISP_OUTPUT_CNTL);
tmp &= ~0x400;
OUTREG(DISP_OUTPUT_CNTL, tmp);
OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
tmp = INPLL(MCLK_MISC);
tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE;
OUTPLL(MCLK_MISC, tmp);
tmp = INPLL(SCLK_CNTL);
OUTPLL(SCLK_CNTL, tmp);
OUTREG(CRTC_MORE_CNTL, 0);
OUTREG8(CRTC_GEN_CNTL+1, 6);
OUTREG8(CRTC_GEN_CNTL+3, 1);
OUTREG(CRTC_PITCH, 32);
tmp = INPLL(VCLK_ECP_CNTL);
OUTPLL(VCLK_ECP_CNTL, tmp);
tmp = INPLL(PPLL_CNTL);
OUTPLL(PPLL_CNTL, tmp);
/* palette stuff and BIOS_1_SCRATCH... */
tmp = INREG(FP_GEN_CNTL);
tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
tmp |= 2;
OUTREG(FP_GEN_CNTL, tmp);
mdelay(5);
OUTREG(FP_GEN_CNTL, tmp);
mdelay(5);
OUTREG(TMDS_TRANSMITTER_CNTL, tmp2);
OUTREG(CRTC_MORE_CNTL, 0);
mdelay(20);
tmp = INREG(CRTC_MORE_CNTL);
OUTREG(CRTC_MORE_CNTL, tmp);
cgc = INREG(CRTC_GEN_CNTL);
cec = INREG(CRTC_EXT_CNTL);
c2gc = INREG(CRTC2_GEN_CNTL);
OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580);
OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2);
OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN);
radeon_pll_errata_after_index(rinfo);
OUTREG8(CLOCK_CNTL_DATA, 0);
radeon_pll_errata_after_data(rinfo);
OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403);
OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429);
OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033);
OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080);
OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080);
OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a);
OUTREG(FP_V_SYNC_STRT_WID, 0x00830004);
OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004);
OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff);
OUTREG(FP_HORZ_STRETCH, 0);
OUTREG(FP_VERT_STRETCH, 0);
OUTREG(OVR_CLR, 0);
OUTREG(OVR_WID_LEFT_RIGHT, 0);
OUTREG(OVR_WID_TOP_BOTTOM, 0);
tmp = INPLL(PPLL_REF_DIV);
tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
OUTPLL(PPLL_REF_DIV, tmp);
INPLL(PPLL_REF_DIV);
OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN);
radeon_pll_errata_after_index(rinfo);
OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc);
radeon_pll_errata_after_data(rinfo);
tmp = INREG(CLOCK_CNTL_INDEX);
radeon_pll_errata_after_index(rinfo);
OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff);
radeon_pll_errata_after_index(rinfo);
radeon_pll_errata_after_data(rinfo);
OUTPLL(PPLL_DIV_0, 0x48090);
tmp = INPLL(PPLL_CNTL);
OUTPLL(PPLL_CNTL, tmp & ~0x2);
mdelay(1);
tmp = INPLL(PPLL_CNTL);
OUTPLL(PPLL_CNTL, tmp & ~0x1);
mdelay(10);
tmp = INPLL(VCLK_ECP_CNTL);
OUTPLL(VCLK_ECP_CNTL, tmp | 3);
mdelay(1);
tmp = INPLL(VCLK_ECP_CNTL);
OUTPLL(VCLK_ECP_CNTL, tmp);
c2gc |= CRTC2_DISP_REQ_EN_B;
OUTREG(CRTC2_GEN_CNTL, c2gc);
cgc |= CRTC_EN;
OUTREG(CRTC_GEN_CNTL, cgc);
OUTREG(CRTC_EXT_CNTL, cec);
OUTREG(CRTC_PITCH, 0xa0);
OUTREG(CRTC_OFFSET, 0);
OUTREG(CRTC_OFFSET_CNTL, 0);
OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c);
OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c);
tmp2 = INREG(FP_GEN_CNTL);
tmp = INREG(TMDS_TRANSMITTER_CNTL);
OUTREG(0x2a8, 0x0000061b);
tmp |= TMDS_PLL_EN;
OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
mdelay(1);
tmp &= ~TMDS_PLLRST;
OUTREG(TMDS_TRANSMITTER_CNTL, tmp);
tmp2 &= ~2;
tmp2 |= FP_TMDS_EN;
OUTREG(FP_GEN_CNTL, tmp2);
mdelay(5);
tmp2 |= FP_FPON;
OUTREG(FP_GEN_CNTL, tmp2);
OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1);
cgc = INREG(CRTC_GEN_CNTL);
OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff);
cgc |= 0x10000;
OUTREG(CUR_OFFSET, 0);
}
#endif /* 0 */
#endif /* CONFIG_PPC */
static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state)
{
u16 pwr_cmd;
for (;;) {
pci_read_config_word(rinfo->pdev,
rinfo->pdev->pm_cap + PCI_PM_CTRL,
&pwr_cmd);
if (pwr_cmd & state)
break;
pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | state;
pci_write_config_word(rinfo->pdev,
rinfo->pdev->pm_cap + PCI_PM_CTRL,
pwr_cmd);
msleep(500);
}
rinfo->pdev->current_state = state;
}
static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
{
u32 tmp;
if (!rinfo->pdev->pm_cap)
return;
/* Set the chip into appropriate suspend mode (we use D2,
* D3 would require a compete re-initialization of the chip,
* including PCI config registers, clocks, AGP conf, ...)
*/
if (suspend) {
printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n",
pci_name(rinfo->pdev));
/* Disable dynamic power management of clocks for the
* duration of the suspend/resume process
*/
radeon_pm_disable_dynamic_mode(rinfo);
/* Save some registers */
radeon_pm_save_regs(rinfo, 0);
/* Prepare mobility chips for suspend.
*/
if (rinfo->is_mobility) {
/* Program V2CLK */
radeon_pm_program_v2clk(rinfo);
/* Disable IO PADs */
radeon_pm_disable_iopad(rinfo);
/* Set low current */
radeon_pm_low_current(rinfo);
/* Prepare chip for power management */
radeon_pm_setup_for_suspend(rinfo);
if (rinfo->family <= CHIP_FAMILY_RV280) {
/* Reset the MDLL */
/* because both INPLL and OUTPLL take the same
* lock, that's why. */
tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET
| MDLL_CKO__MCKOB_RESET;
OUTPLL( pllMDLL_CKO, tmp );
}
}
/* Switch PCI power management to D2. */
pci_disable_device(rinfo->pdev);
pci_save_state(rinfo->pdev);
/* The chip seems to need us to whack the PM register
* repeatedly until it sticks. We do that -prior- to
* calling pci_set_power_state()
*/
radeonfb_whack_power_state(rinfo, PCI_D2);
pci_platform_power_transition(rinfo->pdev, PCI_D2);
} else {
printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n",
pci_name(rinfo->pdev));
if (rinfo->family <= CHIP_FAMILY_RV250) {
/* Reset the SDRAM controller */
radeon_pm_full_reset_sdram(rinfo);
/* Restore some registers */
radeon_pm_restore_regs(rinfo);
} else {
/* Restore registers first */
radeon_pm_restore_regs(rinfo);
/* init sdram controller */
radeon_pm_full_reset_sdram(rinfo);
}
}
}
static int radeonfb_pci_suspend_late(struct device *dev, pm_message_t mesg)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct fb_info *info = pci_get_drvdata(pdev);
struct radeonfb_info *rinfo = info->par;
if (mesg.event == pdev->dev.power.power_state.event)
return 0;
printk(KERN_DEBUG "radeonfb (%s): suspending for event: %d...\n",
pci_name(pdev), mesg.event);
/* For suspend-to-disk, we cheat here. We don't suspend anything and
* let fbcon continue drawing until we are all set. That shouldn't
* really cause any problem at this point, provided that the wakeup
* code knows that any state in memory may not match the HW
*/
switch (mesg.event) {
case PM_EVENT_FREEZE: /* about to take snapshot */
case PM_EVENT_PRETHAW: /* before restoring snapshot */
goto done;
}
console_lock();
fb_set_suspend(info, 1);
if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
/* Make sure engine is reset */
radeon_engine_idle();
radeonfb_engine_reset(rinfo);
radeon_engine_idle();
}
/* Blank display and LCD */
radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
/* Sleep */
rinfo->asleep = 1;
rinfo->lock_blank = 1;
del_timer_sync(&rinfo->lvds_timer);
#ifdef CONFIG_PPC_PMAC
/* On powermac, we have hooks to properly suspend/resume AGP now,
* use them here. We'll ultimately need some generic support here,
* but the generic code isn't quite ready for that yet
*/
pmac_suspend_agp_for_card(pdev);
#endif /* CONFIG_PPC_PMAC */
/* If we support wakeup from poweroff, we save all regs we can including cfg
* space
*/
if (rinfo->pm_mode & radeon_pm_off) {
/* Always disable dynamic clocks or weird things are happening when
* the chip goes off (basically the panel doesn't shut down properly
* and we crash on wakeup),
* also, we want the saved regs context to have no dynamic clocks in
* it, we'll restore the dynamic clocks state on wakeup
*/
radeon_pm_disable_dynamic_mode(rinfo);
msleep(50);
radeon_pm_save_regs(rinfo, 1);
if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
/* Switch off LVDS interface */
usleep_range(1000, 2000);
OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN));
usleep_range(1000, 2000);
OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON));
OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000);
msleep(20);
OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON));
}
}
/* If we support D2, we go to it (should be fixed later with a flag forcing
* D3 only for some laptops)
*/
if (rinfo->pm_mode & radeon_pm_d2)
radeon_set_suspend(rinfo, 1);
console_unlock();
done:
pdev->dev.power.power_state = mesg;
return 0;
}
static int radeonfb_pci_suspend(struct device *dev)
{
return radeonfb_pci_suspend_late(dev, PMSG_SUSPEND);
}
static int radeonfb_pci_hibernate(struct device *dev)
{
return radeonfb_pci_suspend_late(dev, PMSG_HIBERNATE);
}
static int radeonfb_pci_freeze(struct device *dev)
{
return radeonfb_pci_suspend_late(dev, PMSG_FREEZE);
}
static int radeon_check_power_loss(struct radeonfb_info *rinfo)
{
return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) ||
rinfo->save_regs[2] != INPLL(MCLK_CNTL) ||
rinfo->save_regs[3] != INPLL(SCLK_CNTL);
}
static int radeonfb_pci_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct fb_info *info = pci_get_drvdata(pdev);
struct radeonfb_info *rinfo = info->par;
int rc = 0;
if (pdev->dev.power.power_state.event == PM_EVENT_ON)
return 0;
if (rinfo->no_schedule) {
if (!console_trylock())
return 0;
} else
console_lock();
printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n",
pci_name(pdev), pdev->dev.power.power_state.event);
/* PCI state will have been restored by the core, so
* we should be in D0 now with our config space fully
* restored
*/
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
/* Wakeup chip */
if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) {
if (rinfo->reinit_func != NULL)
rinfo->reinit_func(rinfo);
else {
printk(KERN_ERR "radeonfb (%s): can't resume radeon from"
" D3 cold, need softboot !", pci_name(pdev));
rc = -EIO;
goto bail;
}
}
/* If we support D2, try to resume... we should check what was our
* state though... (were we really in D2 state ?). Right now, this code
* is only enable on Macs so it's fine.
*/
else if (rinfo->pm_mode & radeon_pm_d2)
radeon_set_suspend(rinfo, 0);
rinfo->asleep = 0;
} else
radeon_engine_idle();
/* Restore display & engine */
radeon_write_mode (rinfo, &rinfo->state, 1);
if (!(info->flags & FBINFO_HWACCEL_DISABLED))
radeonfb_engine_init (rinfo);
fb_pan_display(info, &info->var);
fb_set_cmap(&info->cmap, info);
/* Refresh */
fb_set_suspend(info, 0);
/* Unblank */
rinfo->lock_blank = 0;
radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
#ifdef CONFIG_PPC_PMAC
/* On powermac, we have hooks to properly suspend/resume AGP now,
* use them here. We'll ultimately need some generic support here,
* but the generic code isn't quite ready for that yet
*/
pmac_resume_agp_for_card(pdev);
#endif /* CONFIG_PPC_PMAC */
/* Check status of dynclk */
if (rinfo->dynclk == 1)
radeon_pm_enable_dynamic_mode(rinfo);
else if (rinfo->dynclk == 0)
radeon_pm_disable_dynamic_mode(rinfo);
pdev->dev.power.power_state = PMSG_ON;
bail:
console_unlock();
return rc;
}
const struct dev_pm_ops radeonfb_pci_pm_ops = {
.suspend = radeonfb_pci_suspend,
.resume = radeonfb_pci_resume,
.freeze = radeonfb_pci_freeze,
.thaw = radeonfb_pci_resume,
.poweroff = radeonfb_pci_hibernate,
.restore = radeonfb_pci_resume,
};
#ifdef CONFIG_PPC__disabled
static void radeonfb_early_resume(void *data)
{
struct radeonfb_info *rinfo = data;
rinfo->no_schedule = 1;
pci_restore_state(rinfo->pdev);
radeonfb_pci_resume(rinfo->pdev);
rinfo->no_schedule = 0;
}
#endif /* CONFIG_PPC */
#endif /* CONFIG_PM */
void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep)
{
/* Enable/Disable dynamic clocks: TODO add sysfs access */
if (rinfo->family == CHIP_FAMILY_RS480)
rinfo->dynclk = -1;
else
rinfo->dynclk = dynclk;
if (rinfo->dynclk == 1) {
radeon_pm_enable_dynamic_mode(rinfo);
printk("radeonfb: Dynamic Clock Power Management enabled\n");
} else if (rinfo->dynclk == 0) {
radeon_pm_disable_dynamic_mode(rinfo);
printk("radeonfb: Dynamic Clock Power Management disabled\n");
}
#if defined(CONFIG_PM)
#if defined(CONFIG_PPC_PMAC)
/* Check if we can power manage on suspend/resume. We can do
* D2 on M6, M7 and M9, and we can resume from D3 cold a few other
* "Mac" cards, but that's all. We need more infos about what the
* BIOS does tho. Right now, all this PM stuff is pmac-only for that
* reason. --BenH
*/
if (machine_is(powermac) && rinfo->of_node) {
if (rinfo->is_mobility && rinfo->pdev->pm_cap &&
rinfo->family <= CHIP_FAMILY_RV250)
rinfo->pm_mode |= radeon_pm_d2;
/* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip
* in some desktop G4s), Via (M9+ chip on iBook G4) and
* Snowy (M11 chip on iBook G4 manufactured after July 2005)
*/
if (of_node_name_eq(rinfo->of_node, "ATY,JasperParent") ||
of_node_name_eq(rinfo->of_node, "ATY,SnowyParent")) {
rinfo->reinit_func = radeon_reinitialize_M10;
rinfo->pm_mode |= radeon_pm_off;
}
#if 0 /* Not ready yet */
if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
rinfo->reinit_func = radeon_reinitialize_QW;
rinfo->pm_mode |= radeon_pm_off;
}
#endif
if (of_node_name_eq(rinfo->of_node, "ATY,ViaParent")) {
rinfo->reinit_func = radeon_reinitialize_M9P;
rinfo->pm_mode |= radeon_pm_off;
}
/* If any of the above is set, we assume the machine can sleep/resume.
* It's a bit of a "shortcut" but will work fine. Ideally, we need infos
* from the platform about what happens to the chip...
* Now we tell the platform about our capability
*/
if (rinfo->pm_mode != radeon_pm_none) {
pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
#if 0 /* Disable the early video resume hack for now as it's causing problems, among
* others we now rely on the PCI core restoring the config space for us, which
* isn't the case with that hack, and that code path causes various things to
* be called with interrupts off while they shouldn't. I'm leaving the code in
* as it can be useful for debugging purposes
*/
pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
#endif
}
#if 0
/* Power down TV DAC, that saves a significant amount of power,
* we'll have something better once we actually have some TVOut
* support
*/
OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000);
#endif
}
#endif /* defined(CONFIG_PPC_PMAC) */
#endif /* defined(CONFIG_PM) */
if (ignore_devlist)
printk(KERN_DEBUG
"radeonfb: skipping test for device workarounds\n");
else
radeon_apply_workarounds(rinfo);
if (force_sleep) {
printk(KERN_DEBUG
"radeonfb: forcefully enabling D2 sleep mode\n");
rinfo->pm_mode |= radeon_pm_d2;
}
}
void radeonfb_pm_exit(struct radeonfb_info *rinfo)
{
#if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC)
if (rinfo->pm_mode != radeon_pm_none)
pmac_set_early_video_resume(NULL, NULL);
#endif
}
| linux-master | drivers/video/fbdev/aty/radeon_pm.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
* Backlight code for ATI Radeon based graphic cards
*
* Copyright (c) 2000 Ani Joshi <[email protected]>
* Copyright (c) 2003 Benjamin Herrenschmidt <[email protected]>
* Copyright (c) 2006 Michael Hanselmann <[email protected]>
*/
#include "radeonfb.h"
#include <linux/backlight.h>
#include <linux/slab.h>
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
#define MAX_RADEON_LEVEL 0xFF
struct radeon_bl_privdata {
struct radeonfb_info *rinfo;
uint8_t negative;
};
static int radeon_bl_get_level_brightness(struct radeon_bl_privdata *pdata,
int level)
{
int rlevel;
/* Get and convert the value */
/* No locking of bl_curve since we read a single value */
rlevel = pdata->rinfo->info->bl_curve[level] *
FB_BACKLIGHT_MAX / MAX_RADEON_LEVEL;
if (rlevel < 0)
rlevel = 0;
else if (rlevel > MAX_RADEON_LEVEL)
rlevel = MAX_RADEON_LEVEL;
if (pdata->negative)
rlevel = MAX_RADEON_LEVEL - rlevel;
return rlevel;
}
static int radeon_bl_update_status(struct backlight_device *bd)
{
struct radeon_bl_privdata *pdata = bl_get_data(bd);
struct radeonfb_info *rinfo = pdata->rinfo;
u32 lvds_gen_cntl, tmpPixclksCntl;
int level;
if (rinfo->mon1_type != MT_LCD)
return 0;
/* We turn off the LCD completely instead of just dimming the
* backlight. This provides some greater power saving and the display
* is useless without backlight anyway.
*/
level = backlight_get_brightness(bd);
del_timer_sync(&rinfo->lvds_timer);
radeon_engine_idle();
lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
if (level > 0) {
lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
lvds_gen_cntl |=
(radeon_bl_get_level_brightness(pdata, level) <<
LVDS_BL_MOD_LEVEL_SHIFT);
lvds_gen_cntl |= LVDS_ON;
lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
mod_timer(&rinfo->lvds_timer,
jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
} else {
lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
lvds_gen_cntl |=
(radeon_bl_get_level_brightness(pdata, level) <<
LVDS_BL_MOD_LEVEL_SHIFT);
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
}
rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl
& LVDS_STATE_MASK;
} else {
/* Asic bug, when turning off LVDS_ON, we have to make sure
RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
*/
tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
if (rinfo->is_mobility || rinfo->is_IGP)
OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
lvds_gen_cntl |= (radeon_bl_get_level_brightness(pdata, 0) <<
LVDS_BL_MOD_LEVEL_SHIFT);
lvds_gen_cntl |= LVDS_DISPLAY_DIS;
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
udelay(100);
lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
lvds_gen_cntl &= ~(LVDS_DIGON);
rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
mod_timer(&rinfo->lvds_timer,
jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
if (rinfo->is_mobility || rinfo->is_IGP)
OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
}
rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
return 0;
}
static const struct backlight_ops radeon_bl_data = {
.update_status = radeon_bl_update_status,
};
void radeonfb_bl_init(struct radeonfb_info *rinfo)
{
struct backlight_properties props;
struct backlight_device *bd;
struct radeon_bl_privdata *pdata;
char name[12];
if (rinfo->mon1_type != MT_LCD)
return;
#ifdef CONFIG_PMAC_BACKLIGHT
if (!pmac_has_backlight_type("ati") &&
!pmac_has_backlight_type("mnca"))
return;
#endif
pdata = kmalloc(sizeof(struct radeon_bl_privdata), GFP_KERNEL);
if (!pdata) {
printk("radeonfb: Memory allocation failed\n");
goto error;
}
snprintf(name, sizeof(name), "radeonbl%d", rinfo->info->node);
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
bd = backlight_device_register(name, rinfo->info->device, pdata,
&radeon_bl_data, &props);
if (IS_ERR(bd)) {
rinfo->info->bl_dev = NULL;
printk("radeonfb: Backlight registration failed\n");
goto error;
}
pdata->rinfo = rinfo;
/* Pardon me for that hack... maybe some day we can figure out in what
* direction backlight should work on a given panel?
*/
pdata->negative =
(rinfo->family != CHIP_FAMILY_RV200 &&
rinfo->family != CHIP_FAMILY_RV250 &&
rinfo->family != CHIP_FAMILY_RV280 &&
rinfo->family != CHIP_FAMILY_RV350);
#ifdef CONFIG_PMAC_BACKLIGHT
pdata->negative = pdata->negative ||
of_machine_is_compatible("PowerBook4,3") ||
of_machine_is_compatible("PowerBook6,3") ||
of_machine_is_compatible("PowerBook6,5");
#endif
rinfo->info->bl_dev = bd;
fb_bl_default_curve(rinfo->info, 0,
63 * FB_BACKLIGHT_MAX / MAX_RADEON_LEVEL,
217 * FB_BACKLIGHT_MAX / MAX_RADEON_LEVEL);
bd->props.brightness = bd->props.max_brightness;
bd->props.power = FB_BLANK_UNBLANK;
backlight_update_status(bd);
printk("radeonfb: Backlight initialized (%s)\n", name);
return;
error:
kfree(pdata);
return;
}
void radeonfb_bl_exit(struct radeonfb_info *rinfo)
{
struct backlight_device *bd = rinfo->info->bl_dev;
if (bd) {
struct radeon_bl_privdata *pdata;
pdata = bl_get_data(bd);
backlight_device_unregister(bd);
kfree(pdata);
rinfo->info->bl_dev = NULL;
printk("radeonfb: Backlight unloaded\n");
}
}
| linux-master | drivers/video/fbdev/aty/radeon_backlight.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ATI Mach64 GX Support
*/
#include <linux/delay.h>
#include <linux/fb.h>
#include <asm/io.h>
#include <video/mach64.h>
#include "atyfb.h"
/* Definitions for the ICS 2595 == ATI 18818_1 Clockchip */
#define REF_FREQ_2595 1432 /* 14.33 MHz (exact 14.31818) */
#define REF_DIV_2595 46 /* really 43 on ICS 2595 !!! */
/* ohne Prescaler */
#define MAX_FREQ_2595 15938 /* 159.38 MHz (really 170.486) */
#define MIN_FREQ_2595 8000 /* 80.00 MHz ( 85.565) */
/* mit Prescaler 2, 4, 8 */
#define ABS_MIN_FREQ_2595 1000 /* 10.00 MHz (really 10.697) */
#define N_ADJ_2595 257
#define STOP_BITS_2595 0x1800
#define MIN_N_408 2
#define MIN_N_1703 6
#define MIN_M 2
#define MAX_M 30
#define MIN_N 35
#define MAX_N 255-8
/*
* Support Functions
*/
static void aty_dac_waste4(const struct atyfb_par *par)
{
(void) aty_ld_8(DAC_REGS, par);
(void) aty_ld_8(DAC_REGS + 2, par);
(void) aty_ld_8(DAC_REGS + 2, par);
(void) aty_ld_8(DAC_REGS + 2, par);
(void) aty_ld_8(DAC_REGS + 2, par);
}
static void aty_StrobeClock(const struct atyfb_par *par)
{
u8 tmp;
udelay(26);
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par);
return;
}
/*
* IBM RGB514 DAC and Clock Chip
*/
static void aty_st_514(int offset, u8 val, const struct atyfb_par *par)
{
aty_st_8(DAC_CNTL, 1, par);
/* right addr byte */
aty_st_8(DAC_W_INDEX, offset & 0xff, par);
/* left addr byte */
aty_st_8(DAC_DATA, (offset >> 8) & 0xff, par);
aty_st_8(DAC_MASK, val, par);
aty_st_8(DAC_CNTL, 0, par);
}
static int aty_set_dac_514(const struct fb_info *info,
const union aty_pll *pll, u32 bpp, u32 accel)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
static struct {
u8 pixel_dly;
u8 misc2_cntl;
u8 pixel_rep;
u8 pixel_cntl_index;
u8 pixel_cntl_v1;
} tab[3] = {
{
0, 0x41, 0x03, 0x71, 0x45}, /* 8 bpp */
{
0, 0x45, 0x04, 0x0c, 0x01}, /* 555 */
{
0, 0x45, 0x06, 0x0e, 0x00}, /* XRGB */
};
int i;
switch (bpp) {
case 8:
default:
i = 0;
break;
case 16:
i = 1;
break;
case 32:
i = 2;
break;
}
aty_st_514(0x90, 0x00, par); /* VRAM Mask Low */
aty_st_514(0x04, tab[i].pixel_dly, par); /* Horizontal Sync Control */
aty_st_514(0x05, 0x00, par); /* Power Management */
aty_st_514(0x02, 0x01, par); /* Misc Clock Control */
aty_st_514(0x71, tab[i].misc2_cntl, par); /* Misc Control 2 */
aty_st_514(0x0a, tab[i].pixel_rep, par); /* Pixel Format */
aty_st_514(tab[i].pixel_cntl_index, tab[i].pixel_cntl_v1, par);
/* Misc Control 2 / 16 BPP Control / 32 BPP Control */
return 0;
}
static int aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per,
u32 bpp, union aty_pll *pll)
{
/*
* FIXME: use real calculations instead of using fixed values from the old
* driver
*/
static struct {
u32 limit; /* pixlock rounding limit (arbitrary) */
u8 m; /* (df<<6) | vco_div_count */
u8 n; /* ref_div_count */
} RGB514_clocks[7] = {
{
8000, (3 << 6) | 20, 9}, /* 7395 ps / 135.2273 MHz */
{
10000, (1 << 6) | 19, 3}, /* 9977 ps / 100.2273 MHz */
{
13000, (1 << 6) | 2, 3}, /* 12509 ps / 79.9432 MHz */
{
14000, (2 << 6) | 8, 7}, /* 13394 ps / 74.6591 MHz */
{
16000, (1 << 6) | 44, 6}, /* 15378 ps / 65.0284 MHz */
{
25000, (1 << 6) | 15, 5}, /* 17460 ps / 57.2727 MHz */
{
50000, (0 << 6) | 53, 7}, /* 33145 ps / 30.1705 MHz */
};
int i;
for (i = 0; i < ARRAY_SIZE(RGB514_clocks); i++)
if (vclk_per <= RGB514_clocks[i].limit) {
pll->ibm514.m = RGB514_clocks[i].m;
pll->ibm514.n = RGB514_clocks[i].n;
return 0;
}
return -EINVAL;
}
static u32 aty_pll_514_to_var(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u8 df, vco_div_count, ref_div_count;
df = pll->ibm514.m >> 6;
vco_div_count = pll->ibm514.m & 0x3f;
ref_div_count = pll->ibm514.n;
return ((par->ref_clk_per * ref_div_count) << (3 - df))/
(vco_div_count + 65);
}
static void aty_set_pll_514(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
aty_st_514(0x06, 0x02, par); /* DAC Operation */
aty_st_514(0x10, 0x01, par); /* PLL Control 1 */
aty_st_514(0x70, 0x01, par); /* Misc Control 1 */
aty_st_514(0x8f, 0x1f, par); /* PLL Ref. Divider Input */
aty_st_514(0x03, 0x00, par); /* Sync Control */
aty_st_514(0x05, 0x00, par); /* Power Management */
aty_st_514(0x20, pll->ibm514.m, par); /* F0 / M0 */
aty_st_514(0x21, pll->ibm514.n, par); /* F1 / N0 */
}
const struct aty_dac_ops aty_dac_ibm514 = {
.set_dac = aty_set_dac_514,
};
const struct aty_pll_ops aty_pll_ibm514 = {
.var_to_pll = aty_var_to_pll_514,
.pll_to_var = aty_pll_514_to_var,
.set_pll = aty_set_pll_514,
};
/*
* ATI 68860-B DAC
*/
static int aty_set_dac_ATI68860_B(const struct fb_info *info,
const union aty_pll *pll, u32 bpp,
u32 accel)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 gModeReg, devSetupRegA, temp, mask;
gModeReg = 0;
devSetupRegA = 0;
switch (bpp) {
case 8:
gModeReg = 0x83;
devSetupRegA =
0x60 | 0x00 /*(info->mach64DAC8Bit ? 0x00 : 0x01) */ ;
break;
case 15:
gModeReg = 0xA0;
devSetupRegA = 0x60;
break;
case 16:
gModeReg = 0xA1;
devSetupRegA = 0x60;
break;
case 24:
gModeReg = 0xC0;
devSetupRegA = 0x60;
break;
case 32:
gModeReg = 0xE3;
devSetupRegA = 0x60;
break;
}
if (!accel) {
gModeReg = 0x80;
devSetupRegA = 0x61;
}
temp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, (temp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3,
par);
aty_st_8(DAC_REGS + 2, 0x1D, par);
aty_st_8(DAC_REGS + 3, gModeReg, par);
aty_st_8(DAC_REGS, 0x02, par);
temp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, temp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par);
if (info->fix.smem_len < ONE_MB)
mask = 0x04;
else if (info->fix.smem_len == ONE_MB)
mask = 0x08;
else
mask = 0x0C;
/* The following assumes that the BIOS has correctly set R7 of the
* Device Setup Register A at boot time.
*/
#define A860_DELAY_L 0x80
temp = aty_ld_8(DAC_REGS, par);
aty_st_8(DAC_REGS, (devSetupRegA | mask) | (temp & A860_DELAY_L),
par);
temp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, (temp & ~(DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3)),
par);
aty_st_le32(BUS_CNTL, 0x890e20f1, par);
aty_st_le32(DAC_CNTL, 0x47052100, par);
return 0;
}
const struct aty_dac_ops aty_dac_ati68860b = {
.set_dac = aty_set_dac_ATI68860_B,
};
/*
* AT&T 21C498 DAC
*/
static int aty_set_dac_ATT21C498(const struct fb_info *info,
const union aty_pll *pll, u32 bpp,
u32 accel)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 dotClock;
int muxmode = 0;
int DACMask = 0;
dotClock = 100000000 / pll->ics2595.period_in_ps;
switch (bpp) {
case 8:
if (dotClock > 8000) {
DACMask = 0x24;
muxmode = 1;
} else
DACMask = 0x04;
break;
case 15:
DACMask = 0x16;
break;
case 16:
DACMask = 0x36;
break;
case 24:
DACMask = 0xE6;
break;
case 32:
DACMask = 0xE6;
break;
}
if (1 /* info->mach64DAC8Bit */ )
DACMask |= 0x02;
aty_dac_waste4(par);
aty_st_8(DAC_REGS + 2, DACMask, par);
aty_st_le32(BUS_CNTL, 0x890e20f1, par);
aty_st_le32(DAC_CNTL, 0x00072000, par);
return muxmode;
}
const struct aty_dac_ops aty_dac_att21c498 = {
.set_dac = aty_set_dac_ATT21C498,
};
/*
* ATI 18818 / ICS 2595 Clock Chip
*/
static int aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per,
u32 bpp, union aty_pll *pll)
{
u32 MHz100; /* in 0.01 MHz */
u32 program_bits;
u32 post_divider;
/* Calculate the programming word */
MHz100 = 100000000 / vclk_per;
program_bits = -1;
post_divider = 1;
if (MHz100 > MAX_FREQ_2595) {
return -EINVAL;
} else if (MHz100 < ABS_MIN_FREQ_2595) {
return -EINVAL;
} else {
while (MHz100 < MIN_FREQ_2595) {
MHz100 *= 2;
post_divider *= 2;
}
}
MHz100 *= 1000;
MHz100 = (REF_DIV_2595 * MHz100) / REF_FREQ_2595;
MHz100 += 500; /* + 0.5 round */
MHz100 /= 1000;
if (program_bits == -1) {
program_bits = MHz100 - N_ADJ_2595;
switch (post_divider) {
case 1:
program_bits |= 0x0600;
break;
case 2:
program_bits |= 0x0400;
break;
case 4:
program_bits |= 0x0200;
break;
case 8:
default:
break;
}
}
program_bits |= STOP_BITS_2595;
pll->ics2595.program_bits = program_bits;
pll->ics2595.locationAddr = 0;
pll->ics2595.post_divider = post_divider;
pll->ics2595.period_in_ps = vclk_per;
return 0;
}
static u32 aty_pll_18818_to_var(const struct fb_info *info,
const union aty_pll *pll)
{
return (pll->ics2595.period_in_ps); /* default for now */
}
static void aty_ICS2595_put1bit(u8 data, const struct atyfb_par *par)
{
u8 tmp;
data &= 0x01;
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
(tmp & ~0x04) | (data << 2), par);
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (0 << 3),
par);
aty_StrobeClock(par);
tmp = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (1 << 3),
par);
aty_StrobeClock(par);
return;
}
static void aty_set_pll18818(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 program_bits;
u32 locationAddr;
u32 i;
u8 old_clock_cntl;
u8 old_crtc_ext_disp;
old_clock_cntl = aty_ld_8(CLOCK_CNTL, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par);
old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
aty_st_8(CRTC_GEN_CNTL + 3,
old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
mdelay(15); /* delay for 50 (15) ms */
program_bits = pll->ics2595.program_bits;
locationAddr = pll->ics2595.locationAddr;
/* Program the clock chip */
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 0, par); /* Strobe = 0 */
aty_StrobeClock(par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 1, par); /* Strobe = 0 */
aty_StrobeClock(par);
aty_ICS2595_put1bit(1, par); /* Send start bits */
aty_ICS2595_put1bit(0, par); /* Start bit */
aty_ICS2595_put1bit(0, par); /* Read / ~Write */
for (i = 0; i < 5; i++) { /* Location 0..4 */
aty_ICS2595_put1bit(locationAddr & 1, par);
locationAddr >>= 1;
}
for (i = 0; i < 8 + 1 + 2 + 2; i++) {
aty_ICS2595_put1bit(program_bits & 1, par);
program_bits >>= 1;
}
mdelay(1); /* delay for 1 ms */
(void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
old_clock_cntl | CLOCK_STROBE, par);
mdelay(50); /* delay for 50 (15) ms */
aty_st_8(CLOCK_CNTL + par->clk_wr_offset,
((pll->ics2595.locationAddr & 0x0F) | CLOCK_STROBE), par);
return;
}
const struct aty_pll_ops aty_pll_ati18818_1 = {
.var_to_pll = aty_var_to_pll_18818,
.pll_to_var = aty_pll_18818_to_var,
.set_pll = aty_set_pll18818,
};
/*
* STG 1703 Clock Chip
*/
static int aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per,
u32 bpp, union aty_pll *pll)
{
u32 mhz100; /* in 0.01 MHz */
u32 program_bits;
/* u32 post_divider; */
u32 mach64MinFreq, mach64MaxFreq, mach64RefFreq;
u32 temp, tempB;
u16 remainder, preRemainder;
short divider = 0, tempA;
/* Calculate the programming word */
mhz100 = 100000000 / vclk_per;
mach64MinFreq = MIN_FREQ_2595;
mach64MaxFreq = MAX_FREQ_2595;
mach64RefFreq = REF_FREQ_2595; /* 14.32 MHz */
/* Calculate program word */
if (mhz100 == 0)
program_bits = 0xE0;
else {
if (mhz100 < mach64MinFreq)
mhz100 = mach64MinFreq;
if (mhz100 > mach64MaxFreq)
mhz100 = mach64MaxFreq;
divider = 0;
while (mhz100 < (mach64MinFreq << 3)) {
mhz100 <<= 1;
divider += 0x20;
}
temp = (unsigned int) (mhz100);
temp = (unsigned int) (temp * (MIN_N_1703 + 2));
temp -= (short) (mach64RefFreq << 1);
tempA = MIN_N_1703;
preRemainder = 0xffff;
do {
tempB = temp;
remainder = tempB % mach64RefFreq;
tempB = tempB / mach64RefFreq;
if ((tempB & 0xffff) <= 127
&& (remainder <= preRemainder)) {
preRemainder = remainder;
divider &= ~0x1f;
divider |= tempA;
divider =
(divider & 0x00ff) +
((tempB & 0xff) << 8);
}
temp += mhz100;
tempA++;
} while (tempA <= (MIN_N_1703 << 1));
program_bits = divider;
}
pll->ics2595.program_bits = program_bits;
pll->ics2595.locationAddr = 0;
pll->ics2595.post_divider = divider; /* fuer nix */
pll->ics2595.period_in_ps = vclk_per;
return 0;
}
static u32 aty_pll_1703_to_var(const struct fb_info *info,
const union aty_pll *pll)
{
return (pll->ics2595.period_in_ps); /* default for now */
}
static void aty_set_pll_1703(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 program_bits;
u32 locationAddr;
char old_crtc_ext_disp;
old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
aty_st_8(CRTC_GEN_CNTL + 3,
old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
program_bits = pll->ics2595.program_bits;
locationAddr = pll->ics2595.locationAddr;
/* Program clock */
aty_dac_waste4(par);
(void) aty_ld_8(DAC_REGS + 2, par);
aty_st_8(DAC_REGS + 2, (locationAddr << 1) + 0x20, par);
aty_st_8(DAC_REGS + 2, 0, par);
aty_st_8(DAC_REGS + 2, (program_bits & 0xFF00) >> 8, par);
aty_st_8(DAC_REGS + 2, (program_bits & 0xFF), par);
(void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
return;
}
const struct aty_pll_ops aty_pll_stg1703 = {
.var_to_pll = aty_var_to_pll_1703,
.pll_to_var = aty_pll_1703_to_var,
.set_pll = aty_set_pll_1703,
};
/*
* Chrontel 8398 Clock Chip
*/
static int aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per,
u32 bpp, union aty_pll *pll)
{
u32 tempA, tempB, fOut, longMHz100, diff, preDiff;
u32 mhz100; /* in 0.01 MHz */
u32 program_bits;
/* u32 post_divider; */
u32 mach64MinFreq, mach64MaxFreq;
u16 m, n, k = 0, save_m, save_n, twoToKth;
/* Calculate the programming word */
mhz100 = 100000000 / vclk_per;
mach64MinFreq = MIN_FREQ_2595;
mach64MaxFreq = MAX_FREQ_2595;
save_m = 0;
save_n = 0;
/* Calculate program word */
if (mhz100 == 0)
program_bits = 0xE0;
else {
if (mhz100 < mach64MinFreq)
mhz100 = mach64MinFreq;
if (mhz100 > mach64MaxFreq)
mhz100 = mach64MaxFreq;
longMHz100 = mhz100 * 256 / 100; /* 8 bit scale this */
while (mhz100 < (mach64MinFreq << 3)) {
mhz100 <<= 1;
k++;
}
twoToKth = 1 << k;
diff = 0;
preDiff = 0xFFFFFFFF;
for (m = MIN_M; m <= MAX_M; m++) {
for (n = MIN_N; n <= MAX_N; n++) {
tempA = 938356; /* 14.31818 * 65536 */
tempA *= (n + 8); /* 43..256 */
tempB = twoToKth * 256;
tempB *= (m + 2); /* 4..32 */
fOut = tempA / tempB; /* 8 bit scale */
if (longMHz100 > fOut)
diff = longMHz100 - fOut;
else
diff = fOut - longMHz100;
if (diff < preDiff) {
save_m = m;
save_n = n;
preDiff = diff;
}
}
}
program_bits = (k << 6) + (save_m) + (save_n << 8);
}
pll->ics2595.program_bits = program_bits;
pll->ics2595.locationAddr = 0;
pll->ics2595.post_divider = 0;
pll->ics2595.period_in_ps = vclk_per;
return 0;
}
static u32 aty_pll_8398_to_var(const struct fb_info *info,
const union aty_pll *pll)
{
return (pll->ics2595.period_in_ps); /* default for now */
}
static void aty_set_pll_8398(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 program_bits;
u32 locationAddr;
char old_crtc_ext_disp;
char tmp;
old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
aty_st_8(CRTC_GEN_CNTL + 3,
old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
program_bits = pll->ics2595.program_bits;
locationAddr = pll->ics2595.locationAddr;
/* Program clock */
tmp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, tmp | DAC_EXT_SEL_RS2 | DAC_EXT_SEL_RS3, par);
aty_st_8(DAC_REGS, locationAddr, par);
aty_st_8(DAC_REGS + 1, (program_bits & 0xff00) >> 8, par);
aty_st_8(DAC_REGS + 1, (program_bits & 0xff), par);
tmp = aty_ld_8(DAC_CNTL, par);
aty_st_8(DAC_CNTL, (tmp & ~DAC_EXT_SEL_RS2) | DAC_EXT_SEL_RS3,
par);
(void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
return;
}
const struct aty_pll_ops aty_pll_ch8398 = {
.var_to_pll = aty_var_to_pll_8398,
.pll_to_var = aty_pll_8398_to_var,
.set_pll = aty_set_pll_8398,
};
/*
* AT&T 20C408 Clock Chip
*/
static int aty_var_to_pll_408(const struct fb_info *info, u32 vclk_per,
u32 bpp, union aty_pll *pll)
{
u32 mhz100; /* in 0.01 MHz */
u32 program_bits;
/* u32 post_divider; */
u32 mach64MinFreq, mach64MaxFreq, mach64RefFreq;
u32 temp, tempB;
u16 remainder, preRemainder;
short divider = 0, tempA;
/* Calculate the programming word */
mhz100 = 100000000 / vclk_per;
mach64MinFreq = MIN_FREQ_2595;
mach64MaxFreq = MAX_FREQ_2595;
mach64RefFreq = REF_FREQ_2595; /* 14.32 MHz */
/* Calculate program word */
if (mhz100 == 0)
program_bits = 0xFF;
else {
if (mhz100 < mach64MinFreq)
mhz100 = mach64MinFreq;
if (mhz100 > mach64MaxFreq)
mhz100 = mach64MaxFreq;
while (mhz100 < (mach64MinFreq << 3)) {
mhz100 <<= 1;
divider += 0x40;
}
temp = (unsigned int) mhz100;
temp = (unsigned int) (temp * (MIN_N_408 + 2));
temp -= ((short) (mach64RefFreq << 1));
tempA = MIN_N_408;
preRemainder = 0xFFFF;
do {
tempB = temp;
remainder = tempB % mach64RefFreq;
tempB = tempB / mach64RefFreq;
if (((tempB & 0xFFFF) <= 255)
&& (remainder <= preRemainder)) {
preRemainder = remainder;
divider &= ~0x3f;
divider |= tempA;
divider =
(divider & 0x00FF) +
((tempB & 0xFF) << 8);
}
temp += mhz100;
tempA++;
} while (tempA <= 32);
program_bits = divider;
}
pll->ics2595.program_bits = program_bits;
pll->ics2595.locationAddr = 0;
pll->ics2595.post_divider = divider; /* fuer nix */
pll->ics2595.period_in_ps = vclk_per;
return 0;
}
static u32 aty_pll_408_to_var(const struct fb_info *info,
const union aty_pll *pll)
{
return (pll->ics2595.period_in_ps); /* default for now */
}
static void aty_set_pll_408(const struct fb_info *info,
const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 program_bits;
u32 locationAddr;
u8 tmpA, tmpB, tmpC;
char old_crtc_ext_disp;
old_crtc_ext_disp = aty_ld_8(CRTC_GEN_CNTL + 3, par);
aty_st_8(CRTC_GEN_CNTL + 3,
old_crtc_ext_disp | (CRTC_EXT_DISP_EN >> 24), par);
program_bits = pll->ics2595.program_bits;
locationAddr = pll->ics2595.locationAddr;
/* Program clock */
aty_dac_waste4(par);
tmpB = aty_ld_8(DAC_REGS + 2, par) | 1;
aty_dac_waste4(par);
aty_st_8(DAC_REGS + 2, tmpB, par);
tmpA = tmpB;
tmpC = tmpA;
tmpA |= 8;
tmpB = 1;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
udelay(400); /* delay for 400 us */
locationAddr = (locationAddr << 2) + 0x40;
tmpB = locationAddr;
tmpA = program_bits >> 8;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
tmpB = locationAddr + 1;
tmpA = (u8) program_bits;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
tmpB = locationAddr + 2;
tmpA = 0x77;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
udelay(400); /* delay for 400 us */
tmpA = tmpC & (~(1 | 8));
tmpB = 1;
aty_st_8(DAC_REGS, tmpB, par);
aty_st_8(DAC_REGS + 2, tmpA, par);
(void) aty_ld_8(DAC_REGS, par); /* Clear DAC Counter */
aty_st_8(CRTC_GEN_CNTL + 3, old_crtc_ext_disp, par);
return;
}
const struct aty_pll_ops aty_pll_att20c408 = {
.var_to_pll = aty_var_to_pll_408,
.pll_to_var = aty_pll_408_to_var,
.set_pll = aty_set_pll_408,
};
/*
* Unsupported DAC and Clock Chip
*/
static int aty_set_dac_unsupported(const struct fb_info *info,
const union aty_pll *pll, u32 bpp,
u32 accel)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
aty_st_le32(BUS_CNTL, 0x890e20f1, par);
aty_st_le32(DAC_CNTL, 0x47052100, par);
/* new in 2.2.3p1 from Geert. ???????? */
aty_st_le32(BUS_CNTL, 0x590e10ff, par);
aty_st_le32(DAC_CNTL, 0x47012100, par);
return 0;
}
static int dummy(void)
{
return 0;
}
const struct aty_dac_ops aty_dac_unsupported = {
.set_dac = aty_set_dac_unsupported,
};
const struct aty_pll_ops aty_pll_unsupported = {
.var_to_pll = (void *) dummy,
.pll_to_var = (void *) dummy,
.set_pll = (void *) dummy,
};
| linux-master | drivers/video/fbdev/aty/mach64_gx.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ATI Mach64 CT/VT/GT/LT Cursor Support
*/
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/string.h>
#include "../core/fb_draw.h"
#include <asm/io.h>
#ifdef __sparc__
#include <asm/fbio.h>
#endif
#include <video/mach64.h>
#include "atyfb.h"
/*
* The hardware cursor definition requires 2 bits per pixel. The
* Cursor size reguardless of the visible cursor size is 64 pixels
* by 64 lines. The total memory required to define the cursor is
* 16 bytes / line for 64 lines or 1024 bytes of data. The data
* must be in a contigiuos format. The 2 bit cursor code values are
* as follows:
*
* 00 - pixel colour = CURSOR_CLR_0
* 01 - pixel colour = CURSOR_CLR_1
* 10 - pixel colour = transparent (current display pixel)
* 11 - pixel colour = 1's complement of current display pixel
*
* Cursor Offset 64 pixels Actual Displayed Area
* \_________________________/
* | | | |
* |<--------------->| | |
* | CURS_HORZ_OFFSET| | |
* | |_______| | 64 Lines
* | ^ | |
* | | | |
* | CURS_VERT_OFFSET| |
* | | | |
* |____________________|____| |
*
*
* The Screen position of the top left corner of the displayed
* cursor is specificed by CURS_HORZ_VERT_POSN. Care must be taken
* when the cursor hot spot is not the top left corner and the
* physical cursor position becomes negative. It will be displayed
* if either the horizontal or vertical cursor position is negative
*
* If x becomes negative the cursor manager must adjust the CURS_HORZ_OFFSET
* to a larger number and saturate CUR_HORZ_POSN to zero.
*
* if Y becomes negative, CUR_VERT_OFFSET must be adjusted to a larger number,
* CUR_OFFSET must be adjusted to a point to the appropriate line in the cursor
* definitation and CUR_VERT_POSN must be saturated to zero.
*/
/*
* Hardware Cursor support.
*/
static const u8 cursor_bits_lookup[16] = {
0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
};
static int atyfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u16 xoff, yoff;
int x, y, h;
#ifdef __sparc__
if (par->mmaped)
return -EPERM;
#endif
if (par->asleep)
return -EPERM;
wait_for_fifo(1, par);
if (cursor->enable)
aty_st_le32(GEN_TEST_CNTL, aty_ld_le32(GEN_TEST_CNTL, par)
| HWCURSOR_ENABLE, par);
else
aty_st_le32(GEN_TEST_CNTL, aty_ld_le32(GEN_TEST_CNTL, par)
& ~HWCURSOR_ENABLE, par);
/* set position */
if (cursor->set & FB_CUR_SETPOS) {
x = cursor->image.dx - cursor->hot.x - info->var.xoffset;
if (x < 0) {
xoff = -x;
x = 0;
} else {
xoff = 0;
}
y = cursor->image.dy - cursor->hot.y - info->var.yoffset;
if (y < 0) {
yoff = -y;
y = 0;
} else {
yoff = 0;
}
h = cursor->image.height;
/*
* In doublescan mode, the cursor location
* and heigh also needs to be doubled.
*/
if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN) {
y<<=1;
h<<=1;
}
wait_for_fifo(3, par);
aty_st_le32(CUR_OFFSET, (info->fix.smem_len >> 3) + (yoff << 1), par);
aty_st_le32(CUR_HORZ_VERT_OFF,
((u32) (64 - h + yoff) << 16) | xoff, par);
aty_st_le32(CUR_HORZ_VERT_POSN, ((u32) y << 16) | x, par);
}
/* Set color map */
if (cursor->set & FB_CUR_SETCMAP) {
u32 fg_idx, bg_idx, fg, bg;
fg_idx = cursor->image.fg_color;
bg_idx = cursor->image.bg_color;
fg = ((info->cmap.red[fg_idx] & 0xff) << 24) |
((info->cmap.green[fg_idx] & 0xff) << 16) |
((info->cmap.blue[fg_idx] & 0xff) << 8) | 0xff;
bg = ((info->cmap.red[bg_idx] & 0xff) << 24) |
((info->cmap.green[bg_idx] & 0xff) << 16) |
((info->cmap.blue[bg_idx] & 0xff) << 8);
wait_for_fifo(2, par);
aty_st_le32(CUR_CLR0, bg, par);
aty_st_le32(CUR_CLR1, fg, par);
}
if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
u8 *src = (u8 *)cursor->image.data;
u8 *msk = (u8 *)cursor->mask;
u8 __iomem *dst = (u8 __iomem *)info->sprite.addr;
unsigned int width = (cursor->image.width + 7) >> 3;
unsigned int height = cursor->image.height;
unsigned int align = info->sprite.scan_align;
unsigned int i, j, offset;
u8 m, b;
// Clear cursor image with 1010101010...
fb_memset_io(dst, 0xaa, 1024);
offset = align - width*2;
for (i = 0; i < height; i++) {
for (j = 0; j < width; j++) {
u16 l = 0xaaaa;
b = *src++;
m = *msk++;
switch (cursor->rop) {
case ROP_XOR:
// Upper 4 bits of mask data
l = cursor_bits_lookup[(b ^ m) >> 4] |
// Lower 4 bits of mask
(cursor_bits_lookup[(b ^ m) & 0x0f] << 8);
break;
case ROP_COPY:
// Upper 4 bits of mask data
l = cursor_bits_lookup[(b & m) >> 4] |
// Lower 4 bits of mask
(cursor_bits_lookup[(b & m) & 0x0f] << 8);
break;
}
/*
* If cursor size is not a multiple of 8 characters
* we must pad it with transparent pattern (0xaaaa).
*/
if ((j + 1) * 8 > cursor->image.width) {
l = comp(l, 0xaaaa,
(1 << ((cursor->image.width & 7) * 2)) - 1);
}
fb_writeb(l & 0xff, dst++);
fb_writeb(l >> 8, dst++);
}
dst += offset;
}
}
return 0;
}
int aty_init_cursor(struct fb_info *info, struct fb_ops *atyfb_ops)
{
unsigned long addr;
info->fix.smem_len -= PAGE_SIZE;
#ifdef __sparc__
addr = (unsigned long) info->screen_base - 0x800000 + info->fix.smem_len;
info->sprite.addr = (u8 *) addr;
#else
#ifdef __BIG_ENDIAN
addr = info->fix.smem_start - 0x800000 + info->fix.smem_len;
info->sprite.addr = (u8 *) ioremap(addr, 1024);
#else
addr = (unsigned long) info->screen_base + info->fix.smem_len;
info->sprite.addr = (u8 *) addr;
#endif
#endif
if (!info->sprite.addr)
return -ENXIO;
info->sprite.size = PAGE_SIZE;
info->sprite.scan_align = 16; /* Scratch pad 64 bytes wide */
info->sprite.buf_align = 16; /* and 64 lines tall. */
info->sprite.flags = FB_PIXMAP_IO;
atyfb_ops->fb_cursor = atyfb_cursor;
return 0;
}
| linux-master | drivers/video/fbdev/aty/mach64_cursor.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ATI Mach64 Hardware Acceleration
*/
#include <linux/delay.h>
#include <asm/unaligned.h>
#include <linux/fb.h>
#include <video/mach64.h>
#include "atyfb.h"
/*
* Generic Mach64 routines
*/
/* this is for DMA GUI engine! work in progress */
typedef struct {
u32 frame_buf_offset;
u32 system_mem_addr;
u32 command;
u32 reserved;
} BM_DESCRIPTOR_ENTRY;
#define LAST_DESCRIPTOR (1 << 31)
#define SYSTEM_TO_FRAME_BUFFER 0
static u32 rotation24bpp(u32 dx, u32 direction)
{
u32 rotation;
if (direction & DST_X_LEFT_TO_RIGHT) {
rotation = (dx / 4) % 6;
} else {
rotation = ((dx + 2) / 4) % 6;
}
return ((rotation << 8) | DST_24_ROTATION_ENABLE);
}
void aty_reset_engine(struct atyfb_par *par)
{
/* reset engine */
aty_st_le32(GEN_TEST_CNTL,
aty_ld_le32(GEN_TEST_CNTL, par) &
~(GUI_ENGINE_ENABLE | HWCURSOR_ENABLE), par);
/* enable engine */
aty_st_le32(GEN_TEST_CNTL,
aty_ld_le32(GEN_TEST_CNTL, par) | GUI_ENGINE_ENABLE, par);
/* ensure engine is not locked up by clearing any FIFO or */
/* HOST errors */
aty_st_le32(BUS_CNTL,
aty_ld_le32(BUS_CNTL, par) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK, par);
par->fifo_space = 0;
}
static void reset_GTC_3D_engine(const struct atyfb_par *par)
{
aty_st_le32(SCALE_3D_CNTL, 0xc0, par);
mdelay(GTC_3D_RESET_DELAY);
aty_st_le32(SETUP_CNTL, 0x00, par);
mdelay(GTC_3D_RESET_DELAY);
aty_st_le32(SCALE_3D_CNTL, 0x00, par);
mdelay(GTC_3D_RESET_DELAY);
}
void aty_init_engine(struct atyfb_par *par, struct fb_info *info)
{
u32 pitch_value;
u32 vxres;
/* determine modal information from global mode structure */
pitch_value = info->fix.line_length / (info->var.bits_per_pixel / 8);
vxres = info->var.xres_virtual;
if (info->var.bits_per_pixel == 24) {
/* In 24 bpp, the engine is in 8 bpp - this requires that all */
/* horizontal coordinates and widths must be adjusted */
pitch_value *= 3;
vxres *= 3;
}
/* On GTC (RagePro), we need to reset the 3D engine before */
if (M64_HAS(RESET_3D))
reset_GTC_3D_engine(par);
/* Reset engine, enable, and clear any engine errors */
aty_reset_engine(par);
/* Ensure that vga page pointers are set to zero - the upper */
/* page pointers are set to 1 to handle overflows in the */
/* lower page */
aty_st_le32(MEM_VGA_WP_SEL, 0x00010000, par);
aty_st_le32(MEM_VGA_RP_SEL, 0x00010000, par);
/* ---- Setup standard engine context ---- */
/* All GUI registers here are FIFOed - therefore, wait for */
/* the appropriate number of empty FIFO entries */
wait_for_fifo(14, par);
/* enable all registers to be loaded for context loads */
aty_st_le32(CONTEXT_MASK, 0xFFFFFFFF, par);
/* set destination pitch to modal pitch, set offset to zero */
aty_st_le32(DST_OFF_PITCH, (pitch_value / 8) << 22, par);
/* zero these registers (set them to a known state) */
aty_st_le32(DST_Y_X, 0, par);
aty_st_le32(DST_HEIGHT, 0, par);
aty_st_le32(DST_BRES_ERR, 0, par);
aty_st_le32(DST_BRES_INC, 0, par);
aty_st_le32(DST_BRES_DEC, 0, par);
/* set destination drawing attributes */
aty_st_le32(DST_CNTL, DST_LAST_PEL | DST_Y_TOP_TO_BOTTOM |
DST_X_LEFT_TO_RIGHT, par);
/* set source pitch to modal pitch, set offset to zero */
aty_st_le32(SRC_OFF_PITCH, (pitch_value / 8) << 22, par);
/* set these registers to a known state */
aty_st_le32(SRC_Y_X, 0, par);
aty_st_le32(SRC_HEIGHT1_WIDTH1, 1, par);
aty_st_le32(SRC_Y_X_START, 0, par);
aty_st_le32(SRC_HEIGHT2_WIDTH2, 1, par);
/* set source pixel retrieving attributes */
aty_st_le32(SRC_CNTL, SRC_LINE_X_LEFT_TO_RIGHT, par);
/* set host attributes */
wait_for_fifo(13, par);
aty_st_le32(HOST_CNTL, HOST_BYTE_ALIGN, par);
/* set pattern attributes */
aty_st_le32(PAT_REG0, 0, par);
aty_st_le32(PAT_REG1, 0, par);
aty_st_le32(PAT_CNTL, 0, par);
/* set scissors to modal size */
aty_st_le32(SC_LEFT, 0, par);
aty_st_le32(SC_TOP, 0, par);
aty_st_le32(SC_BOTTOM, par->crtc.vyres - 1, par);
aty_st_le32(SC_RIGHT, vxres - 1, par);
/* set background color to minimum value (usually BLACK) */
aty_st_le32(DP_BKGD_CLR, 0, par);
/* set foreground color to maximum value (usually WHITE) */
aty_st_le32(DP_FRGD_CLR, 0xFFFFFFFF, par);
/* set write mask to effect all pixel bits */
aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF, par);
/* set foreground mix to overpaint and background mix to */
/* no-effect */
aty_st_le32(DP_MIX, FRGD_MIX_S | BKGD_MIX_D, par);
/* set primary source pixel channel to foreground color */
/* register */
aty_st_le32(DP_SRC, FRGD_SRC_FRGD_CLR, par);
/* set compare functionality to false (no-effect on */
/* destination) */
wait_for_fifo(3, par);
aty_st_le32(CLR_CMP_CLR, 0, par);
aty_st_le32(CLR_CMP_MASK, 0xFFFFFFFF, par);
aty_st_le32(CLR_CMP_CNTL, 0, par);
/* set pixel depth */
wait_for_fifo(2, par);
aty_st_le32(DP_PIX_WIDTH, par->crtc.dp_pix_width, par);
aty_st_le32(DP_CHAIN_MASK, par->crtc.dp_chain_mask, par);
wait_for_fifo(5, par);
aty_st_le32(SCALE_3D_CNTL, 0, par);
aty_st_le32(Z_CNTL, 0, par);
aty_st_le32(CRTC_INT_CNTL, aty_ld_le32(CRTC_INT_CNTL, par) & ~0x20,
par);
aty_st_le32(GUI_TRAJ_CNTL, 0x100023, par);
/* insure engine is idle before leaving */
wait_for_idle(par);
}
/*
* Accelerated functions
*/
static inline void draw_rect(s16 x, s16 y, u16 width, u16 height,
struct atyfb_par *par)
{
/* perform rectangle fill */
wait_for_fifo(2, par);
aty_st_le32(DST_Y_X, (x << 16) | y, par);
aty_st_le32(DST_HEIGHT_WIDTH, (width << 16) | height, par);
par->blitter_may_be_busy = 1;
}
void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 dy = area->dy, sy = area->sy, direction = DST_LAST_PEL;
u32 sx = area->sx, dx = area->dx, width = area->width, rotation = 0;
if (par->asleep)
return;
if (!area->width || !area->height)
return;
if (!par->accel_flags) {
cfb_copyarea(info, area);
return;
}
if (info->var.bits_per_pixel == 24) {
/* In 24 bpp, the engine is in 8 bpp - this requires that all */
/* horizontal coordinates and widths must be adjusted */
sx *= 3;
dx *= 3;
width *= 3;
}
if (area->sy < area->dy) {
dy += area->height - 1;
sy += area->height - 1;
} else
direction |= DST_Y_TOP_TO_BOTTOM;
if (sx < dx) {
dx += width - 1;
sx += width - 1;
} else
direction |= DST_X_LEFT_TO_RIGHT;
if (info->var.bits_per_pixel == 24) {
rotation = rotation24bpp(dx, direction);
}
wait_for_fifo(5, par);
aty_st_le32(DP_PIX_WIDTH, par->crtc.dp_pix_width, par);
aty_st_le32(DP_SRC, FRGD_SRC_BLIT, par);
aty_st_le32(SRC_Y_X, (sx << 16) | sy, par);
aty_st_le32(SRC_HEIGHT1_WIDTH1, (width << 16) | area->height, par);
aty_st_le32(DST_CNTL, direction | rotation, par);
draw_rect(dx, dy, width, area->height, par);
}
void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 color, dx = rect->dx, width = rect->width, rotation = 0;
if (par->asleep)
return;
if (!rect->width || !rect->height)
return;
if (!par->accel_flags) {
cfb_fillrect(info, rect);
return;
}
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR)
color = ((u32 *)(info->pseudo_palette))[rect->color];
else
color = rect->color;
if (info->var.bits_per_pixel == 24) {
/* In 24 bpp, the engine is in 8 bpp - this requires that all */
/* horizontal coordinates and widths must be adjusted */
dx *= 3;
width *= 3;
rotation = rotation24bpp(dx, DST_X_LEFT_TO_RIGHT);
}
wait_for_fifo(4, par);
aty_st_le32(DP_PIX_WIDTH, par->crtc.dp_pix_width, par);
aty_st_le32(DP_FRGD_CLR, color, par);
aty_st_le32(DP_SRC,
BKGD_SRC_BKGD_CLR | FRGD_SRC_FRGD_CLR | MONO_SRC_ONE,
par);
aty_st_le32(DST_CNTL,
DST_LAST_PEL | DST_Y_TOP_TO_BOTTOM |
DST_X_LEFT_TO_RIGHT | rotation, par);
draw_rect(dx, rect->dy, width, rect->height, par);
}
void atyfb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 src_bytes, dx = image->dx, dy = image->dy, width = image->width;
u32 pix_width, rotation = 0, src, mix;
if (par->asleep)
return;
if (!image->width || !image->height)
return;
if (!par->accel_flags ||
(image->depth != 1 && info->var.bits_per_pixel != image->depth)) {
cfb_imageblit(info, image);
return;
}
pix_width = par->crtc.dp_pix_width;
switch (image->depth) {
case 1:
pix_width &= ~(BYTE_ORDER_MASK | HOST_MASK);
pix_width |= (BYTE_ORDER_MSB_TO_LSB | HOST_1BPP);
break;
case 4:
pix_width &= ~(BYTE_ORDER_MASK | HOST_MASK);
pix_width |= (BYTE_ORDER_MSB_TO_LSB | HOST_4BPP);
break;
case 8:
pix_width &= ~HOST_MASK;
pix_width |= HOST_8BPP;
break;
case 15:
pix_width &= ~HOST_MASK;
pix_width |= HOST_15BPP;
break;
case 16:
pix_width &= ~HOST_MASK;
pix_width |= HOST_16BPP;
break;
case 24:
pix_width &= ~HOST_MASK;
pix_width |= HOST_24BPP;
break;
case 32:
pix_width &= ~HOST_MASK;
pix_width |= HOST_32BPP;
break;
}
if (info->var.bits_per_pixel == 24) {
/* In 24 bpp, the engine is in 8 bpp - this requires that all */
/* horizontal coordinates and widths must be adjusted */
dx *= 3;
width *= 3;
rotation = rotation24bpp(dx, DST_X_LEFT_TO_RIGHT);
pix_width &= ~DST_MASK;
pix_width |= DST_8BPP;
/*
* since Rage 3D IIc we have DP_HOST_TRIPLE_EN bit
* this hwaccelerated triple has an issue with not aligned data
*/
if (image->depth == 1 && M64_HAS(HW_TRIPLE) && image->width % 8 == 0)
pix_width |= DP_HOST_TRIPLE_EN;
}
if (image->depth == 1) {
u32 fg, bg;
if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
fg = ((u32*)(info->pseudo_palette))[image->fg_color];
bg = ((u32*)(info->pseudo_palette))[image->bg_color];
} else {
fg = image->fg_color;
bg = image->bg_color;
}
wait_for_fifo(2, par);
aty_st_le32(DP_BKGD_CLR, bg, par);
aty_st_le32(DP_FRGD_CLR, fg, par);
src = MONO_SRC_HOST | FRGD_SRC_FRGD_CLR | BKGD_SRC_BKGD_CLR;
mix = FRGD_MIX_S | BKGD_MIX_S;
} else {
src = MONO_SRC_ONE | FRGD_SRC_HOST;
mix = FRGD_MIX_D_XOR_S | BKGD_MIX_D;
}
wait_for_fifo(5, par);
aty_st_le32(DP_PIX_WIDTH, pix_width, par);
aty_st_le32(DP_MIX, mix, par);
aty_st_le32(DP_SRC, src, par);
aty_st_le32(HOST_CNTL, HOST_BYTE_ALIGN, par);
aty_st_le32(DST_CNTL, DST_Y_TOP_TO_BOTTOM | DST_X_LEFT_TO_RIGHT | rotation, par);
draw_rect(dx, dy, width, image->height, par);
src_bytes = (((image->width * image->depth) + 7) / 8) * image->height;
/* manual triple each pixel */
if (image->depth == 1 && info->var.bits_per_pixel == 24 && !(pix_width & DP_HOST_TRIPLE_EN)) {
int inbit, outbit, mult24, byte_id_in_dword, width;
u8 *pbitmapin = (u8*)image->data, *pbitmapout;
u32 hostdword;
for (width = image->width, inbit = 7, mult24 = 0; src_bytes; ) {
for (hostdword = 0, pbitmapout = (u8*)&hostdword, byte_id_in_dword = 0;
byte_id_in_dword < 4 && src_bytes;
byte_id_in_dword++, pbitmapout++) {
for (outbit = 7; outbit >= 0; outbit--) {
*pbitmapout |= (((*pbitmapin >> inbit) & 1) << outbit);
mult24++;
/* next bit */
if (mult24 == 3) {
mult24 = 0;
inbit--;
width--;
}
/* next byte */
if (inbit < 0 || width == 0) {
src_bytes--;
pbitmapin++;
inbit = 7;
if (width == 0) {
width = image->width;
outbit = 0;
}
}
}
}
wait_for_fifo(1, par);
aty_st_le32(HOST_DATA0, le32_to_cpu(hostdword), par);
}
} else {
u32 *pbitmap, dwords = (src_bytes + 3) / 4;
for (pbitmap = (u32*)(image->data); dwords; dwords--, pbitmap++) {
wait_for_fifo(1, par);
aty_st_le32(HOST_DATA0, get_unaligned_le32(pbitmap), par);
}
}
}
| linux-master | drivers/video/fbdev/aty/mach64_accel.c |
// SPDX-License-Identifier: GPL-2.0-only
/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
* linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
*
* Copyright (C) 1999-2003, Brad Douglas <[email protected]>
* Copyright (C) 1999, Anthony Tong <[email protected]>
*
* Ani Joshi / Jeff Garzik
* - Code cleanup
*
* Michel Danzer <[email protected]>
* - 15/16 bit cleanup
* - fix panning
*
* Benjamin Herrenschmidt
* - pmac-specific PM stuff
* - various fixes & cleanups
*
* Andreas Hundt <[email protected]>
* - FB_ACTIVATE fixes
*
* Paul Mackerras <[email protected]>
* - Convert to new framebuffer API,
* fix colormap setting at 16 bits/pixel (565)
*
* Paul Mundt
* - PCI hotplug
*
* Jon Smirl <[email protected]>
* - PCI ID update
* - replace ROM BIOS search
*
* Based off of Geert's atyfb.c and vfb.c.
*
* TODO:
* - monitor sensing (DDC)
* - virtual display
* - other platform support (only ppc/x86 supported)
* - hardware cursor support
*
* Please cc: your patches to [email protected].
*/
/*
* A special note of gratitude to ATI's devrel for providing documentation,
* example code and hardware. Thanks Nitya. -atong and brad
*/
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/uaccess.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/console.h>
#include <linux/backlight.h>
#include <asm/io.h>
#ifdef CONFIG_PPC_PMAC
#include <asm/machdep.h>
#include <asm/pmac_feature.h>
#include "../macmodes.h"
#endif
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
#ifdef CONFIG_BOOTX_TEXT
#include <asm/btext.h>
#endif /* CONFIG_BOOTX_TEXT */
#include <video/aty128.h>
/* Debug flag */
#undef DEBUG
#ifdef DEBUG
#define DBG(fmt, args...) \
printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
#else
#define DBG(fmt, args...)
#endif
#ifndef CONFIG_PPC_PMAC
/* default mode */
static const struct fb_var_screeninfo default_var = {
/* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
640, 480, 640, 480, 0, 0, 8, 0,
{0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED
};
#else /* CONFIG_PPC_PMAC */
/* default to 1024x768 at 75Hz on PPC - this will work
* on the iMac, the usual 640x480 @ 60Hz doesn't. */
static const struct fb_var_screeninfo default_var = {
/* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
1024, 768, 1024, 768, 0, 0, 8, 0,
{0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED
};
#endif /* CONFIG_PPC_PMAC */
/* default modedb mode */
/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
static const struct fb_videomode defaultmode = {
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39722,
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
/* Chip generations */
enum {
rage_128,
rage_128_pci,
rage_128_pro,
rage_128_pro_pci,
rage_M3,
rage_M3_pci,
rage_M4,
rage_128_ultra,
};
/* Must match above enum */
static char * const r128_family[] = {
"AGP",
"PCI",
"PRO AGP",
"PRO PCI",
"M3 AGP",
"M3 PCI",
"M4 AGP",
"Ultra AGP",
};
/*
* PCI driver prototypes
*/
static int aty128_probe(struct pci_dev *pdev,
const struct pci_device_id *ent);
static void aty128_remove(struct pci_dev *pdev);
static int aty128_pci_suspend_late(struct device *dev, pm_message_t state);
static int __maybe_unused aty128_pci_suspend(struct device *dev);
static int __maybe_unused aty128_pci_hibernate(struct device *dev);
static int __maybe_unused aty128_pci_freeze(struct device *dev);
static int __maybe_unused aty128_pci_resume(struct device *dev);
static int aty128_do_resume(struct pci_dev *pdev);
static const struct dev_pm_ops aty128_pci_pm_ops = {
.suspend = aty128_pci_suspend,
.resume = aty128_pci_resume,
.freeze = aty128_pci_freeze,
.thaw = aty128_pci_resume,
.poweroff = aty128_pci_hibernate,
.restore = aty128_pci_resume,
};
/* supported Rage128 chipsets */
static const struct pci_device_id aty128_pci_tbl[] = {
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
static struct pci_driver aty128fb_driver = {
.name = "aty128fb",
.id_table = aty128_pci_tbl,
.probe = aty128_probe,
.remove = aty128_remove,
.driver.pm = &aty128_pci_pm_ops,
};
/* packed BIOS settings */
#ifndef CONFIG_PPC
typedef struct {
u8 clock_chip_type;
u8 struct_size;
u8 accelerator_entry;
u8 VGA_entry;
u16 VGA_table_offset;
u16 POST_table_offset;
u16 XCLK;
u16 MCLK;
u8 num_PLL_blocks;
u8 size_PLL_blocks;
u16 PCLK_ref_freq;
u16 PCLK_ref_divider;
u32 PCLK_min_freq;
u32 PCLK_max_freq;
u16 MCLK_ref_freq;
u16 MCLK_ref_divider;
u32 MCLK_min_freq;
u32 MCLK_max_freq;
u16 XCLK_ref_freq;
u16 XCLK_ref_divider;
u32 XCLK_min_freq;
u32 XCLK_max_freq;
} __attribute__ ((packed)) PLL_BLOCK;
#endif /* !CONFIG_PPC */
/* onboard memory information */
struct aty128_meminfo {
u8 ML;
u8 MB;
u8 Trcd;
u8 Trp;
u8 Twr;
u8 CL;
u8 Tr2w;
u8 LoopLatency;
u8 DspOn;
u8 Rloop;
const char *name;
};
/* various memory configurations */
static const struct aty128_meminfo sdr_128 = {
.ML = 4,
.MB = 4,
.Trcd = 3,
.Trp = 3,
.Twr = 1,
.CL = 3,
.Tr2w = 1,
.LoopLatency = 16,
.DspOn = 30,
.Rloop = 16,
.name = "128-bit SDR SGRAM (1:1)",
};
static const struct aty128_meminfo sdr_sgram = {
.ML = 4,
.MB = 4,
.Trcd = 1,
.Trp = 2,
.Twr = 1,
.CL = 2,
.Tr2w = 1,
.LoopLatency = 16,
.DspOn = 24,
.Rloop = 16,
.name = "64-bit SDR SGRAM (2:1)",
};
static const struct aty128_meminfo ddr_sgram = {
.ML = 4,
.MB = 4,
.Trcd = 3,
.Trp = 3,
.Twr = 2,
.CL = 3,
.Tr2w = 1,
.LoopLatency = 16,
.DspOn = 31,
.Rloop = 16,
.name = "64-bit DDR SGRAM",
};
static const struct fb_fix_screeninfo aty128fb_fix = {
.id = "ATY Rage128",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 8,
.ypanstep = 1,
.mmio_len = 0x2000,
.accel = FB_ACCEL_ATI_RAGE128,
};
static char *mode_option = NULL;
#ifdef CONFIG_PPC_PMAC
static int default_vmode = VMODE_1024_768_60;
static int default_cmode = CMODE_8;
#endif
static int default_crt_on = 0;
static int default_lcd_on = 1;
static bool mtrr = true;
#ifdef CONFIG_FB_ATY128_BACKLIGHT
static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
#endif
/* PLL constants */
struct aty128_constants {
u32 ref_clk;
u32 ppll_min;
u32 ppll_max;
u32 ref_divider;
u32 xclk;
u32 fifo_width;
u32 fifo_depth;
};
struct aty128_crtc {
u32 gen_cntl;
u32 h_total, h_sync_strt_wid;
u32 v_total, v_sync_strt_wid;
u32 pitch;
u32 offset, offset_cntl;
u32 xoffset, yoffset;
u32 vxres, vyres;
u32 depth, bpp;
};
struct aty128_pll {
u32 post_divider;
u32 feedback_divider;
u32 vclk;
};
struct aty128_ddafifo {
u32 dda_config;
u32 dda_on_off;
};
/* register values for a specific mode */
struct aty128fb_par {
struct aty128_crtc crtc;
struct aty128_pll pll;
struct aty128_ddafifo fifo_reg;
u32 accel_flags;
struct aty128_constants constants; /* PLL and others */
void __iomem *regbase; /* remapped mmio */
u32 vram_size; /* onboard video ram */
int chip_gen;
const struct aty128_meminfo *mem; /* onboard mem info */
int wc_cookie;
int blitter_may_be_busy;
int fifo_slots; /* free slots in FIFO (64 max) */
int crt_on, lcd_on;
struct pci_dev *pdev;
struct fb_info *next;
int asleep;
int lock_blank;
u8 red[32]; /* see aty128fb_setcolreg */
u8 green[64];
u8 blue[32];
u32 pseudo_palette[16]; /* used for TRUECOLOR */
};
#define round_div(n, d) ((n+(d/2))/d)
static int aty128fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info);
static int aty128fb_set_par(struct fb_info *info);
static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int aty128fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *fb);
static int aty128fb_blank(int blank, struct fb_info *fb);
static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
static int aty128fb_sync(struct fb_info *info);
/*
* Internal routines
*/
static int aty128_encode_var(struct fb_var_screeninfo *var,
const struct aty128fb_par *par);
static int aty128_decode_var(struct fb_var_screeninfo *var,
struct aty128fb_par *par);
static void aty128_timings(struct aty128fb_par *par);
static void aty128_init_engine(struct aty128fb_par *par);
static void aty128_reset_engine(const struct aty128fb_par *par);
static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
static void wait_for_idle(struct aty128fb_par *par);
static u32 depth_to_dst(u32 depth);
#ifdef CONFIG_FB_ATY128_BACKLIGHT
static void aty128_bl_set_power(struct fb_info *info, int power);
#endif
#define BIOS_IN8(v) (readb(bios + (v)))
#define BIOS_IN16(v) (readb(bios + (v)) | \
(readb(bios + (v) + 1) << 8))
#define BIOS_IN32(v) (readb(bios + (v)) | \
(readb(bios + (v) + 1) << 8) | \
(readb(bios + (v) + 2) << 16) | \
(readb(bios + (v) + 3) << 24))
static const struct fb_ops aty128fb_ops = {
.owner = THIS_MODULE,
FB_DEFAULT_IOMEM_OPS,
.fb_check_var = aty128fb_check_var,
.fb_set_par = aty128fb_set_par,
.fb_setcolreg = aty128fb_setcolreg,
.fb_pan_display = aty128fb_pan_display,
.fb_blank = aty128fb_blank,
.fb_ioctl = aty128fb_ioctl,
.fb_sync = aty128fb_sync,
};
/*
* Functions to read from/write to the mmio registers
* - endian conversions may possibly be avoided by
* using the other register aperture. TODO.
*/
static inline u32 _aty_ld_le32(volatile unsigned int regindex,
const struct aty128fb_par *par)
{
return readl (par->regbase + regindex);
}
static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
const struct aty128fb_par *par)
{
writel (val, par->regbase + regindex);
}
static inline u8 _aty_ld_8(unsigned int regindex,
const struct aty128fb_par *par)
{
return readb (par->regbase + regindex);
}
static inline void _aty_st_8(unsigned int regindex, u8 val,
const struct aty128fb_par *par)
{
writeb (val, par->regbase + regindex);
}
#define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
#define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
#define aty_ld_8(regindex) _aty_ld_8(regindex, par)
#define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
/*
* Functions to read from/write to the pll registers
*/
#define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
#define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
static u32 _aty_ld_pll(unsigned int pll_index,
const struct aty128fb_par *par)
{
aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
return aty_ld_le32(CLOCK_CNTL_DATA);
}
static void _aty_st_pll(unsigned int pll_index, u32 val,
const struct aty128fb_par *par)
{
aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
aty_st_le32(CLOCK_CNTL_DATA, val);
}
/* return true when the PLL has completed an atomic update */
static int aty_pll_readupdate(const struct aty128fb_par *par)
{
return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
}
static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
{
unsigned long timeout = jiffies + HZ/100; // should be more than enough
int reset = 1;
while (time_before(jiffies, timeout))
if (aty_pll_readupdate(par)) {
reset = 0;
break;
}
if (reset) /* reset engine?? */
printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
}
/* tell PLL to update */
static void aty_pll_writeupdate(const struct aty128fb_par *par)
{
aty_pll_wait_readupdate(par);
aty_st_pll(PPLL_REF_DIV,
aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
}
/* write to the scratch register to test r/w functionality */
static int register_test(const struct aty128fb_par *par)
{
u32 val;
int flag = 0;
val = aty_ld_le32(BIOS_0_SCRATCH);
aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
flag = 1;
}
aty_st_le32(BIOS_0_SCRATCH, val); // restore value
return flag;
}
/*
* Accelerator engine functions
*/
static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
{
int i;
for (;;) {
for (i = 0; i < 2000000; i++) {
par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
if (par->fifo_slots >= entries)
return;
}
aty128_reset_engine(par);
}
}
static void wait_for_idle(struct aty128fb_par *par)
{
int i;
do_wait_for_fifo(64, par);
for (;;) {
for (i = 0; i < 2000000; i++) {
if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
aty128_flush_pixel_cache(par);
par->blitter_may_be_busy = 0;
return;
}
}
aty128_reset_engine(par);
}
}
static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
{
if (par->fifo_slots < entries)
do_wait_for_fifo(64, par);
par->fifo_slots -= entries;
}
static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
{
int i;
u32 tmp;
tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
tmp &= ~(0x00ff);
tmp |= 0x00ff;
aty_st_le32(PC_NGUI_CTLSTAT, tmp);
for (i = 0; i < 2000000; i++)
if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
break;
}
static void aty128_reset_engine(const struct aty128fb_par *par)
{
u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
aty128_flush_pixel_cache(par);
clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
mclk_cntl = aty_ld_pll(MCLK_CNTL);
aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
aty_ld_le32(GEN_RESET_CNTL);
aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
aty_ld_le32(GEN_RESET_CNTL);
aty_st_pll(MCLK_CNTL, mclk_cntl);
aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
/* use old pio mode */
aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
DBG("engine reset");
}
static void aty128_init_engine(struct aty128fb_par *par)
{
u32 pitch_value;
wait_for_idle(par);
/* 3D scaler not spoken here */
wait_for_fifo(1, par);
aty_st_le32(SCALE_3D_CNTL, 0x00000000);
aty128_reset_engine(par);
pitch_value = par->crtc.pitch;
if (par->crtc.bpp == 24) {
pitch_value = pitch_value * 3;
}
wait_for_fifo(4, par);
/* setup engine offset registers */
aty_st_le32(DEFAULT_OFFSET, 0x00000000);
/* setup engine pitch registers */
aty_st_le32(DEFAULT_PITCH, pitch_value);
/* set the default scissor register to max dimensions */
aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
/* set the drawing controls registers */
aty_st_le32(DP_GUI_MASTER_CNTL,
GMC_SRC_PITCH_OFFSET_DEFAULT |
GMC_DST_PITCH_OFFSET_DEFAULT |
GMC_SRC_CLIP_DEFAULT |
GMC_DST_CLIP_DEFAULT |
GMC_BRUSH_SOLIDCOLOR |
(depth_to_dst(par->crtc.depth) << 8) |
GMC_SRC_DSTCOLOR |
GMC_BYTE_ORDER_MSB_TO_LSB |
GMC_DP_CONVERSION_TEMP_6500 |
ROP3_PATCOPY |
GMC_DP_SRC_RECT |
GMC_3D_FCN_EN_CLR |
GMC_DST_CLR_CMP_FCN_CLEAR |
GMC_AUX_CLIP_CLEAR |
GMC_WRITE_MASK_SET);
wait_for_fifo(8, par);
/* clear the line drawing registers */
aty_st_le32(DST_BRES_ERR, 0);
aty_st_le32(DST_BRES_INC, 0);
aty_st_le32(DST_BRES_DEC, 0);
/* set brush color registers */
aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
/* set source color registers */
aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
/* default write mask */
aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
/* Wait for all the writes to be completed before returning */
wait_for_idle(par);
}
/* convert depth values to their register representation */
static u32 depth_to_dst(u32 depth)
{
if (depth <= 8)
return DST_8BPP;
else if (depth <= 15)
return DST_15BPP;
else if (depth == 16)
return DST_16BPP;
else if (depth <= 24)
return DST_24BPP;
else if (depth <= 32)
return DST_32BPP;
return -EINVAL;
}
/*
* PLL informations retreival
*/
#ifndef __sparc__
static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
struct pci_dev *dev)
{
u16 dptr;
u8 rom_type;
void __iomem *bios;
size_t rom_size;
/* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
unsigned int temp;
temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
temp &= 0x00ffffffu;
temp |= 0x04 << 24;
aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
bios = pci_map_rom(dev, &rom_size);
if (!bios) {
printk(KERN_ERR "aty128fb: ROM failed to map\n");
return NULL;
}
/* Very simple test to make sure it appeared */
if (BIOS_IN16(0) != 0xaa55) {
printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
" be 0xaa55\n", BIOS_IN16(0));
goto failed;
}
/* Look for the PCI data to check the ROM type */
dptr = BIOS_IN16(0x18);
/* Check the PCI data signature. If it's wrong, we still assume a normal
* x86 ROM for now, until I've verified this works everywhere.
* The goal here is more to phase out Open Firmware images.
*
* Currently, we only look at the first PCI data, we could iteratre and
* deal with them all, and we should use fb_bios_start relative to start
* of image and not relative start of ROM, but so far, I never found a
* dual-image ATI card.
*
* typedef struct {
* u32 signature; + 0x00
* u16 vendor; + 0x04
* u16 device; + 0x06
* u16 reserved_1; + 0x08
* u16 dlen; + 0x0a
* u8 drevision; + 0x0c
* u8 class_hi; + 0x0d
* u16 class_lo; + 0x0e
* u16 ilen; + 0x10
* u16 irevision; + 0x12
* u8 type; + 0x14
* u8 indicator; + 0x15
* u16 reserved_2; + 0x16
* } pci_data_t;
*/
if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
BIOS_IN32(dptr));
goto anyway;
}
rom_type = BIOS_IN8(dptr + 0x14);
switch(rom_type) {
case 0:
printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
break;
case 1:
printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
goto failed;
case 2:
printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
goto failed;
default:
printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
rom_type);
goto failed;
}
anyway:
return bios;
failed:
pci_unmap_rom(dev, bios);
return NULL;
}
static void aty128_get_pllinfo(struct aty128fb_par *par,
unsigned char __iomem *bios)
{
unsigned int bios_hdr;
unsigned int bios_pll;
bios_hdr = BIOS_IN16(0x48);
bios_pll = BIOS_IN16(bios_hdr + 0x30);
par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
par->constants.ppll_max, par->constants.ppll_min,
par->constants.xclk, par->constants.ref_divider,
par->constants.ref_clk);
}
#ifdef CONFIG_X86
static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
{
/* I simplified this code as we used to miss the signatures in
* a lot of case. It's now closer to XFree, we just don't check
* for signatures at all... Something better will have to be done
* if we end up having conflicts
*/
u32 segstart;
unsigned char __iomem *rom_base = NULL;
for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
rom_base = ioremap(segstart, 0x10000);
if (rom_base == NULL)
return NULL;
if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
break;
iounmap(rom_base);
rom_base = NULL;
}
return rom_base;
}
#endif
#endif /* ndef(__sparc__) */
/* fill in known card constants if pll_block is not available */
static void aty128_timings(struct aty128fb_par *par)
{
#ifdef CONFIG_PPC
/* instead of a table lookup, assume OF has properly
* setup the PLL registers and use their values
* to set the XCLK values and reference divider values */
u32 x_mpll_ref_fb_div;
u32 xclk_cntl;
u32 Nx, M;
static const unsigned int PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
#endif
if (!par->constants.ref_clk)
par->constants.ref_clk = 2950;
#ifdef CONFIG_PPC
x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
M = x_mpll_ref_fb_div & 0x0000ff;
par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
(M * PostDivSet[xclk_cntl]));
par->constants.ref_divider =
aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
#endif
if (!par->constants.ref_divider) {
par->constants.ref_divider = 0x3b;
aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
aty_pll_writeupdate(par);
}
aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
aty_pll_writeupdate(par);
/* from documentation */
if (!par->constants.ppll_min)
par->constants.ppll_min = 12500;
if (!par->constants.ppll_max)
par->constants.ppll_max = 25000; /* 23000 on some cards? */
if (!par->constants.xclk)
par->constants.xclk = 0x1d4d; /* same as mclk */
par->constants.fifo_width = 128;
par->constants.fifo_depth = 32;
switch (aty_ld_le32(MEM_CNTL) & 0x3) {
case 0:
par->mem = &sdr_128;
break;
case 1:
par->mem = &sdr_sgram;
break;
case 2:
par->mem = &ddr_sgram;
break;
default:
par->mem = &sdr_sgram;
}
}
/*
* CRTC programming
*/
/* Program the CRTC registers */
static void aty128_set_crtc(const struct aty128_crtc *crtc,
const struct aty128fb_par *par)
{
aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
aty_st_le32(CRTC_PITCH, crtc->pitch);
aty_st_le32(CRTC_OFFSET, crtc->offset);
aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
/* Disable ATOMIC updating. Is this the right place? */
aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
}
static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
struct aty128_crtc *crtc,
const struct aty128fb_par *par)
{
u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
u32 left, right, upper, lower, hslen, vslen, sync, vmode;
u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
u32 depth, bytpp;
u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
/* input */
xres = var->xres;
yres = var->yres;
vxres = var->xres_virtual;
vyres = var->yres_virtual;
xoffset = var->xoffset;
yoffset = var->yoffset;
bpp = var->bits_per_pixel;
left = var->left_margin;
right = var->right_margin;
upper = var->upper_margin;
lower = var->lower_margin;
hslen = var->hsync_len;
vslen = var->vsync_len;
sync = var->sync;
vmode = var->vmode;
if (bpp != 16)
depth = bpp;
else
depth = (var->green.length == 6) ? 16 : 15;
/* check for mode eligibility
* accept only non interlaced modes */
if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
return -EINVAL;
/* convert (and round up) and validate */
xres = (xres + 7) & ~7;
xoffset = (xoffset + 7) & ~7;
if (vxres < xres + xoffset)
vxres = xres + xoffset;
if (vyres < yres + yoffset)
vyres = yres + yoffset;
/* convert depth into ATI register depth */
dst = depth_to_dst(depth);
if (dst == -EINVAL) {
printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
return -EINVAL;
}
/* convert register depth to bytes per pixel */
bytpp = mode_bytpp[dst];
/* make sure there is enough video ram for the mode */
if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
return -EINVAL;
}
h_disp = (xres >> 3) - 1;
h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
v_disp = yres - 1;
v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
/* check to make sure h_total and v_total are in range */
if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
printk(KERN_ERR "aty128fb: invalid width ranges\n");
return -EINVAL;
}
h_sync_wid = (hslen + 7) >> 3;
if (h_sync_wid == 0)
h_sync_wid = 1;
else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
h_sync_wid = 0x3f;
h_sync_strt = (h_disp << 3) + right;
v_sync_wid = vslen;
if (v_sync_wid == 0)
v_sync_wid = 1;
else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
v_sync_wid = 0x1f;
v_sync_strt = v_disp + lower;
h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
crtc->h_total = h_total | (h_disp << 16);
crtc->v_total = v_total | (v_disp << 16);
crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
(h_sync_pol << 23);
crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
(v_sync_pol << 23);
crtc->pitch = vxres >> 3;
crtc->offset = 0;
if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
crtc->offset_cntl = 0x00010000;
else
crtc->offset_cntl = 0;
crtc->vxres = vxres;
crtc->vyres = vyres;
crtc->xoffset = xoffset;
crtc->yoffset = yoffset;
crtc->depth = depth;
crtc->bpp = bpp;
return 0;
}
static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
{
/* fill in pixel info */
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.offset = 0;
var->blue.msb_right = 0;
var->transp.offset = 0;
var->transp.length = 0;
var->transp.msb_right = 0;
switch (pix_width) {
case CRTC_PIX_WIDTH_8BPP:
var->bits_per_pixel = 8;
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.length = 8;
break;
case CRTC_PIX_WIDTH_15BPP:
var->bits_per_pixel = 16;
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.length = 5;
break;
case CRTC_PIX_WIDTH_16BPP:
var->bits_per_pixel = 16;
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.length = 5;
break;
case CRTC_PIX_WIDTH_24BPP:
var->bits_per_pixel = 24;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.length = 8;
break;
case CRTC_PIX_WIDTH_32BPP:
var->bits_per_pixel = 32;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
default:
printk(KERN_ERR "aty128fb: Invalid pixel width\n");
return -EINVAL;
}
return 0;
}
static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
struct fb_var_screeninfo *var)
{
u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
u32 pix_width;
/* fun with masking */
h_total = crtc->h_total & 0x1ff;
h_disp = (crtc->h_total >> 16) & 0xff;
h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
h_sync_dly = crtc->h_sync_strt_wid & 0x7;
h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
v_total = crtc->v_total & 0x7ff;
v_disp = (crtc->v_total >> 16) & 0x7ff;
v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
/* do conversions */
xres = (h_disp + 1) << 3;
yres = v_disp + 1;
left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
hslen = h_sync_wid << 3;
upper = v_total - v_sync_strt - v_sync_wid;
lower = v_sync_strt - v_disp;
vslen = v_sync_wid;
sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
(v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
(c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
aty128_pix_width_to_var(pix_width, var);
var->xres = xres;
var->yres = yres;
var->xres_virtual = crtc->vxres;
var->yres_virtual = crtc->vyres;
var->xoffset = crtc->xoffset;
var->yoffset = crtc->yoffset;
var->left_margin = left;
var->right_margin = right;
var->upper_margin = upper;
var->lower_margin = lower;
var->hsync_len = hslen;
var->vsync_len = vslen;
var->sync = sync;
var->vmode = FB_VMODE_NONINTERLACED;
return 0;
}
static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
{
if (on) {
aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
CRT_CRTC_ON);
aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
DAC_PALETTE2_SNOOP_EN));
} else
aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
~CRT_CRTC_ON);
}
static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
{
u32 reg;
#ifdef CONFIG_FB_ATY128_BACKLIGHT
struct fb_info *info = pci_get_drvdata(par->pdev);
#endif
if (on) {
reg = aty_ld_le32(LVDS_GEN_CNTL);
reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
reg &= ~LVDS_DISPLAY_DIS;
aty_st_le32(LVDS_GEN_CNTL, reg);
#ifdef CONFIG_FB_ATY128_BACKLIGHT
aty128_bl_set_power(info, FB_BLANK_UNBLANK);
#endif
} else {
#ifdef CONFIG_FB_ATY128_BACKLIGHT
aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
#endif
reg = aty_ld_le32(LVDS_GEN_CNTL);
reg |= LVDS_DISPLAY_DIS;
aty_st_le32(LVDS_GEN_CNTL, reg);
mdelay(100);
reg &= ~(LVDS_ON /*| LVDS_EN*/);
aty_st_le32(LVDS_GEN_CNTL, reg);
}
}
static void aty128_set_pll(struct aty128_pll *pll,
const struct aty128fb_par *par)
{
u32 div3;
/* register values for post dividers */
static const unsigned char post_conv[] = {
2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7
};
/* select PPLL_DIV_3 */
aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
/* reset PLL */
aty_st_pll(PPLL_CNTL,
aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
/* write the reference divider */
aty_pll_wait_readupdate(par);
aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
aty_pll_writeupdate(par);
div3 = aty_ld_pll(PPLL_DIV_3);
div3 &= ~PPLL_FB3_DIV_MASK;
div3 |= pll->feedback_divider;
div3 &= ~PPLL_POST3_DIV_MASK;
div3 |= post_conv[pll->post_divider] << 16;
/* write feedback and post dividers */
aty_pll_wait_readupdate(par);
aty_st_pll(PPLL_DIV_3, div3);
aty_pll_writeupdate(par);
aty_pll_wait_readupdate(par);
aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
aty_pll_writeupdate(par);
/* clear the reset, just in case */
aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
}
static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
const struct aty128fb_par *par)
{
const struct aty128_constants c = par->constants;
static const unsigned char post_dividers[] = { 1, 2, 4, 8, 3, 6, 12 };
u32 output_freq;
u32 vclk; /* in .01 MHz */
int i = 0;
u32 n, d;
vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
/* adjust pixel clock if necessary */
if (vclk > c.ppll_max)
vclk = c.ppll_max;
if (vclk * 12 < c.ppll_min)
vclk = c.ppll_min/12;
/* now, find an acceptable divider */
for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
output_freq = post_dividers[i] * vclk;
if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
pll->post_divider = post_dividers[i];
break;
}
}
if (i == ARRAY_SIZE(post_dividers))
return -EINVAL;
/* calculate feedback divider */
n = c.ref_divider * output_freq;
d = c.ref_clk;
pll->feedback_divider = round_div(n, d);
pll->vclk = vclk;
DBG("post %d feedback %d vlck %d output %d ref_divider %d "
"vclk_per: %d\n", pll->post_divider,
pll->feedback_divider, vclk, output_freq,
c.ref_divider, period_in_ps);
return 0;
}
static int aty128_pll_to_var(const struct aty128_pll *pll,
struct fb_var_screeninfo *var)
{
var->pixclock = 100000000 / pll->vclk;
return 0;
}
static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
const struct aty128fb_par *par)
{
aty_st_le32(DDA_CONFIG, dsp->dda_config);
aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
}
static int aty128_ddafifo(struct aty128_ddafifo *dsp,
const struct aty128_pll *pll,
u32 depth,
const struct aty128fb_par *par)
{
const struct aty128_meminfo *m = par->mem;
u32 xclk = par->constants.xclk;
u32 fifo_width = par->constants.fifo_width;
u32 fifo_depth = par->constants.fifo_depth;
s32 x, b, p, ron, roff;
u32 n, d, bpp;
/* round up to multiple of 8 */
bpp = (depth+7) & ~7;
n = xclk * fifo_width;
d = pll->vclk * bpp;
x = round_div(n, d);
ron = 4 * m->MB +
3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
2 * m->Trp +
m->Twr +
m->CL +
m->Tr2w +
x;
DBG("x %x\n", x);
b = 0;
while (x) {
x >>= 1;
b++;
}
p = b + 1;
ron <<= (11 - p);
n <<= (11 - p);
x = round_div(n, d);
roff = x * (fifo_depth - 4);
if ((ron + m->Rloop) >= roff) {
printk(KERN_ERR "aty128fb: Mode out of range!\n");
return -EINVAL;
}
DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
p, m->Rloop, x, ron, roff);
dsp->dda_config = p << 16 | m->Rloop << 20 | x;
dsp->dda_on_off = ron << 16 | roff;
return 0;
}
/*
* This actually sets the video mode.
*/
static int aty128fb_set_par(struct fb_info *info)
{
struct aty128fb_par *par = info->par;
u32 config;
int err;
if ((err = aty128_decode_var(&info->var, par)) != 0)
return err;
if (par->blitter_may_be_busy)
wait_for_idle(par);
/* clear all registers that may interfere with mode setting */
aty_st_le32(OVR_CLR, 0);
aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
aty_st_le32(OV0_SCALE_CNTL, 0);
aty_st_le32(MPP_TB_CONFIG, 0);
aty_st_le32(MPP_GP_CONFIG, 0);
aty_st_le32(SUBPIC_CNTL, 0);
aty_st_le32(VIPH_CONTROL, 0);
aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
aty_st_le32(CAP0_TRIG_CNTL, 0);
aty_st_le32(CAP1_TRIG_CNTL, 0);
aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
aty128_set_crtc(&par->crtc, par);
aty128_set_pll(&par->pll, par);
aty128_set_fifo(&par->fifo_reg, par);
config = aty_ld_le32(CNFG_CNTL) & ~3;
#if defined(__BIG_ENDIAN)
if (par->crtc.bpp == 32)
config |= 2; /* make aperture do 32 bit swapping */
else if (par->crtc.bpp == 16)
config |= 1; /* make aperture do 16 bit swapping */
#endif
aty_st_le32(CNFG_CNTL, config);
aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_DIRECTCOLOR;
if (par->chip_gen == rage_M3) {
aty128_set_crt_enable(par, par->crt_on);
aty128_set_lcd_enable(par, par->lcd_on);
}
if (par->accel_flags & FB_ACCELF_TEXT)
aty128_init_engine(par);
#ifdef CONFIG_BOOTX_TEXT
btext_update_display(info->fix.smem_start,
(((par->crtc.h_total>>16) & 0xff)+1)*8,
((par->crtc.v_total>>16) & 0x7ff)+1,
par->crtc.bpp,
par->crtc.vxres*par->crtc.bpp/8);
#endif /* CONFIG_BOOTX_TEXT */
return 0;
}
/*
* encode/decode the User Defined Part of the Display
*/
static int aty128_decode_var(struct fb_var_screeninfo *var,
struct aty128fb_par *par)
{
int err;
struct aty128_crtc crtc;
struct aty128_pll pll;
struct aty128_ddafifo fifo_reg;
if ((err = aty128_var_to_crtc(var, &crtc, par)))
return err;
if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
return err;
if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
return err;
par->crtc = crtc;
par->pll = pll;
par->fifo_reg = fifo_reg;
par->accel_flags = var->accel_flags;
return 0;
}
static int aty128_encode_var(struct fb_var_screeninfo *var,
const struct aty128fb_par *par)
{
int err;
if ((err = aty128_crtc_to_var(&par->crtc, var)))
return err;
if ((err = aty128_pll_to_var(&par->pll, var)))
return err;
var->nonstd = 0;
var->activate = 0;
var->height = -1;
var->width = -1;
var->accel_flags = par->accel_flags;
return 0;
}
static int aty128fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct aty128fb_par par;
int err;
par = *(struct aty128fb_par *)info->par;
if ((err = aty128_decode_var(var, &par)) != 0)
return err;
aty128_encode_var(var, &par);
return 0;
}
/*
* Pan or Wrap the Display
*/
static int aty128fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *fb)
{
struct aty128fb_par *par = fb->par;
u32 xoffset, yoffset;
u32 offset;
u32 xres, yres;
xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
xoffset = (var->xoffset +7) & ~7;
yoffset = var->yoffset;
if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
return -EINVAL;
par->crtc.xoffset = xoffset;
par->crtc.yoffset = yoffset;
offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
& ~7;
if (par->crtc.bpp == 24)
offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
aty_st_le32(CRTC_OFFSET, offset);
return 0;
}
/*
* Helper function to store a single palette register
*/
static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
struct aty128fb_par *par)
{
if (par->chip_gen == rage_M3) {
aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
~DAC_PALETTE_ACCESS_CNTL);
}
aty_st_8(PALETTE_INDEX, regno);
aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
}
static int aty128fb_sync(struct fb_info *info)
{
struct aty128fb_par *par = info->par;
if (par->blitter_may_be_busy)
wait_for_idle(par);
return 0;
}
#ifndef MODULE
static int aty128fb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "lcd:", 4)) {
default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
continue;
} else if (!strncmp(this_opt, "crt:", 4)) {
default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
continue;
} else if (!strncmp(this_opt, "backlight:", 10)) {
#ifdef CONFIG_FB_ATY128_BACKLIGHT
backlight = simple_strtoul(this_opt+10, NULL, 0);
#endif
continue;
}
if(!strncmp(this_opt, "nomtrr", 6)) {
mtrr = false;
continue;
}
#ifdef CONFIG_PPC_PMAC
/* vmode and cmode deprecated */
if (!strncmp(this_opt, "vmode:", 6)) {
unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
if (vmode > 0 && vmode <= VMODE_MAX)
default_vmode = vmode;
continue;
} else if (!strncmp(this_opt, "cmode:", 6)) {
unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
switch (cmode) {
case 0:
case 8:
default_cmode = CMODE_8;
break;
case 15:
case 16:
default_cmode = CMODE_16;
break;
case 24:
case 32:
default_cmode = CMODE_32;
break;
}
continue;
}
#endif /* CONFIG_PPC_PMAC */
mode_option = this_opt;
}
return 0;
}
#endif /* MODULE */
/* Backlight */
#ifdef CONFIG_FB_ATY128_BACKLIGHT
#define MAX_LEVEL 0xFF
static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
int level)
{
struct fb_info *info = pci_get_drvdata(par->pdev);
int atylevel;
/* Get and convert the value */
/* No locking of bl_curve since we read a single value */
atylevel = MAX_LEVEL -
(info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
if (atylevel < 0)
atylevel = 0;
else if (atylevel > MAX_LEVEL)
atylevel = MAX_LEVEL;
return atylevel;
}
/* We turn off the LCD completely instead of just dimming the backlight.
* This provides greater power saving and the display is useless without
* backlight anyway
*/
#define BACKLIGHT_LVDS_OFF
/* That one prevents proper CRT output with LCD off */
#undef BACKLIGHT_DAC_OFF
static int aty128_bl_update_status(struct backlight_device *bd)
{
struct aty128fb_par *par = bl_get_data(bd);
unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
int level;
if (!par->lcd_on)
level = 0;
else
level = backlight_get_brightness(bd);
reg |= LVDS_BL_MOD_EN | LVDS_BLON;
if (level > 0) {
reg |= LVDS_DIGION;
if (!(reg & LVDS_ON)) {
reg &= ~LVDS_BLON;
aty_st_le32(LVDS_GEN_CNTL, reg);
aty_ld_le32(LVDS_GEN_CNTL);
mdelay(10);
reg |= LVDS_BLON;
aty_st_le32(LVDS_GEN_CNTL, reg);
}
reg &= ~LVDS_BL_MOD_LEVEL_MASK;
reg |= (aty128_bl_get_level_brightness(par, level) <<
LVDS_BL_MOD_LEVEL_SHIFT);
#ifdef BACKLIGHT_LVDS_OFF
reg |= LVDS_ON | LVDS_EN;
reg &= ~LVDS_DISPLAY_DIS;
#endif
aty_st_le32(LVDS_GEN_CNTL, reg);
#ifdef BACKLIGHT_DAC_OFF
aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
#endif
} else {
reg &= ~LVDS_BL_MOD_LEVEL_MASK;
reg |= (aty128_bl_get_level_brightness(par, 0) <<
LVDS_BL_MOD_LEVEL_SHIFT);
#ifdef BACKLIGHT_LVDS_OFF
reg |= LVDS_DISPLAY_DIS;
aty_st_le32(LVDS_GEN_CNTL, reg);
aty_ld_le32(LVDS_GEN_CNTL);
udelay(10);
reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
#endif
aty_st_le32(LVDS_GEN_CNTL, reg);
#ifdef BACKLIGHT_DAC_OFF
aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
#endif
}
return 0;
}
static const struct backlight_ops aty128_bl_data = {
.update_status = aty128_bl_update_status,
};
static void aty128_bl_set_power(struct fb_info *info, int power)
{
if (info->bl_dev) {
info->bl_dev->props.power = power;
backlight_update_status(info->bl_dev);
}
}
static void aty128_bl_init(struct aty128fb_par *par)
{
struct backlight_properties props;
struct fb_info *info = pci_get_drvdata(par->pdev);
struct backlight_device *bd;
char name[12];
/* Could be extended to Rage128Pro LVDS output too */
if (par->chip_gen != rage_M3)
return;
#ifdef CONFIG_PMAC_BACKLIGHT
if (!pmac_has_backlight_type("ati"))
return;
#endif
snprintf(name, sizeof(name), "aty128bl%d", info->node);
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
bd = backlight_device_register(name, info->device, par, &aty128_bl_data,
&props);
if (IS_ERR(bd)) {
info->bl_dev = NULL;
printk(KERN_WARNING "aty128: Backlight registration failed\n");
goto error;
}
info->bl_dev = bd;
fb_bl_default_curve(info, 0,
63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
bd->props.brightness = bd->props.max_brightness;
bd->props.power = FB_BLANK_UNBLANK;
backlight_update_status(bd);
printk("aty128: Backlight initialized (%s)\n", name);
return;
error:
return;
}
static void aty128_bl_exit(struct backlight_device *bd)
{
backlight_device_unregister(bd);
printk("aty128: Backlight unloaded\n");
}
#endif /* CONFIG_FB_ATY128_BACKLIGHT */
/*
* Initialisation
*/
#ifdef CONFIG_PPC_PMAC__disabled
static void aty128_early_resume(void *data)
{
struct aty128fb_par *par = data;
if (!console_trylock())
return;
pci_restore_state(par->pdev);
aty128_do_resume(par->pdev);
console_unlock();
}
#endif /* CONFIG_PPC_PMAC */
static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct aty128fb_par *par = info->par;
struct fb_var_screeninfo var;
char video_card[50];
u8 chip_rev;
u32 dac;
/* Get the chip revision */
chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
strcpy(video_card, "Rage128 XX ");
video_card[8] = ent->device >> 8;
video_card[9] = ent->device & 0xFF;
/* range check to make sure */
if (ent->driver_data < ARRAY_SIZE(r128_family))
strlcat(video_card, r128_family[ent->driver_data],
sizeof(video_card));
printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
if (par->vram_size % (1024 * 1024) == 0)
printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
else
printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
par->chip_gen = ent->driver_data;
/* fill in info */
info->fbops = &aty128fb_ops;
par->lcd_on = default_lcd_on;
par->crt_on = default_crt_on;
var = default_var;
#ifdef CONFIG_PPC_PMAC
if (machine_is(powermac)) {
/* Indicate sleep capability */
if (par->chip_gen == rage_M3) {
pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
#if 0 /* Disable the early video resume hack for now as it's causing problems,
* among others we now rely on the PCI core restoring the config space
* for us, which isn't the case with that hack, and that code path causes
* various things to be called with interrupts off while they shouldn't.
* I'm leaving the code in as it can be useful for debugging purposes
*/
pmac_set_early_video_resume(aty128_early_resume, par);
#endif
}
/* Find default mode */
if (mode_option) {
if (!mac_find_mode(&var, info, mode_option, 8))
var = default_var;
} else {
if (default_vmode <= 0 || default_vmode > VMODE_MAX)
default_vmode = VMODE_1024_768_60;
/* iMacs need that resolution
* PowerMac2,1 first r128 iMacs
* PowerMac2,2 summer 2000 iMacs
* PowerMac4,1 january 2001 iMacs "flower power"
*/
if (of_machine_is_compatible("PowerMac2,1") ||
of_machine_is_compatible("PowerMac2,2") ||
of_machine_is_compatible("PowerMac4,1"))
default_vmode = VMODE_1024_768_75;
/* iBook SE */
if (of_machine_is_compatible("PowerBook2,2"))
default_vmode = VMODE_800_600_60;
/* PowerBook Firewire (Pismo), iBook Dual USB */
if (of_machine_is_compatible("PowerBook3,1") ||
of_machine_is_compatible("PowerBook4,1"))
default_vmode = VMODE_1024_768_60;
/* PowerBook Titanium */
if (of_machine_is_compatible("PowerBook3,2"))
default_vmode = VMODE_1152_768_60;
if (default_cmode > 16)
default_cmode = CMODE_32;
else if (default_cmode > 8)
default_cmode = CMODE_16;
else
default_cmode = CMODE_8;
if (mac_vmode_to_var(default_vmode, default_cmode, &var))
var = default_var;
}
} else
#endif /* CONFIG_PPC_PMAC */
{
if (mode_option)
if (fb_find_mode(&var, info, mode_option, NULL,
0, &defaultmode, 8) == 0)
var = default_var;
}
var.accel_flags &= ~FB_ACCELF_TEXT;
// var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
if (aty128fb_check_var(&var, info)) {
printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
return 0;
}
/* setup the DAC the way we like it */
dac = aty_ld_le32(DAC_CNTL);
dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
dac |= DAC_MASK;
if (par->chip_gen == rage_M3)
dac |= DAC_PALETTE2_SNOOP_EN;
aty_st_le32(DAC_CNTL, dac);
/* turn off bus mastering, just in case */
aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
info->var = var;
fb_alloc_cmap(&info->cmap, 256, 0);
var.activate = FB_ACTIVATE_NOW;
aty128_init_engine(par);
par->pdev = pdev;
par->asleep = 0;
par->lock_blank = 0;
if (register_framebuffer(info) < 0)
return 0;
#ifdef CONFIG_FB_ATY128_BACKLIGHT
if (backlight)
aty128_bl_init(par);
#endif
fb_info(info, "%s frame buffer device on %s\n",
info->fix.id, video_card);
return 1; /* success! */
}
#ifdef CONFIG_PCI
/* register a card ++ajoshi */
static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
unsigned long fb_addr, reg_addr;
struct aty128fb_par *par;
struct fb_info *info;
int err;
#ifndef __sparc__
void __iomem *bios = NULL;
#endif
err = aperture_remove_conflicting_pci_devices(pdev, "aty128fb");
if (err)
return err;
/* Enable device in PCI config */
if ((err = pci_enable_device(pdev))) {
printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
err);
return -ENODEV;
}
fb_addr = pci_resource_start(pdev, 0);
if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
"aty128fb FB")) {
printk(KERN_ERR "aty128fb: cannot reserve frame "
"buffer memory\n");
return -ENODEV;
}
reg_addr = pci_resource_start(pdev, 2);
if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
"aty128fb MMIO")) {
printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
goto err_free_fb;
}
/* We have the resources. Now virtualize them */
info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
if (!info)
goto err_free_mmio;
par = info->par;
info->pseudo_palette = par->pseudo_palette;
/* Virtualize mmio region */
info->fix.mmio_start = reg_addr;
par->regbase = pci_ioremap_bar(pdev, 2);
if (!par->regbase)
goto err_free_info;
/* Grab memory size from the card */
// How does this relate to the resource length from the PCI hardware?
par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
/* Virtualize the framebuffer */
info->screen_base = ioremap_wc(fb_addr, par->vram_size);
if (!info->screen_base)
goto err_unmap_out;
/* Set up info->fix */
info->fix = aty128fb_fix;
info->fix.smem_start = fb_addr;
info->fix.smem_len = par->vram_size;
info->fix.mmio_start = reg_addr;
/* If we can't test scratch registers, something is seriously wrong */
if (!register_test(par)) {
printk(KERN_ERR "aty128fb: Can't write to video register!\n");
goto err_out;
}
#ifndef __sparc__
bios = aty128_map_ROM(par, pdev);
#ifdef CONFIG_X86
if (bios == NULL)
bios = aty128_find_mem_vbios(par);
#endif
if (bios == NULL)
printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
else {
printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
aty128_get_pllinfo(par, bios);
pci_unmap_rom(pdev, bios);
}
#endif /* __sparc__ */
aty128_timings(par);
pci_set_drvdata(pdev, info);
if (!aty128_init(pdev, ent))
goto err_out;
if (mtrr)
par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
par->vram_size);
return 0;
err_out:
iounmap(info->screen_base);
err_unmap_out:
iounmap(par->regbase);
err_free_info:
framebuffer_release(info);
err_free_mmio:
release_mem_region(pci_resource_start(pdev, 2),
pci_resource_len(pdev, 2));
err_free_fb:
release_mem_region(pci_resource_start(pdev, 0),
pci_resource_len(pdev, 0));
return -ENODEV;
}
static void aty128_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct aty128fb_par *par;
if (!info)
return;
par = info->par;
#ifdef CONFIG_FB_ATY128_BACKLIGHT
aty128_bl_exit(info->bl_dev);
#endif
unregister_framebuffer(info);
arch_phys_wc_del(par->wc_cookie);
iounmap(par->regbase);
iounmap(info->screen_base);
release_mem_region(pci_resource_start(pdev, 0),
pci_resource_len(pdev, 0));
release_mem_region(pci_resource_start(pdev, 2),
pci_resource_len(pdev, 2));
framebuffer_release(info);
}
#endif /* CONFIG_PCI */
/*
* Blank the display.
*/
static int aty128fb_blank(int blank, struct fb_info *fb)
{
struct aty128fb_par *par = fb->par;
u8 state;
if (par->lock_blank || par->asleep)
return 0;
switch (blank) {
case FB_BLANK_NORMAL:
state = 4;
break;
case FB_BLANK_VSYNC_SUSPEND:
state = 6;
break;
case FB_BLANK_HSYNC_SUSPEND:
state = 5;
break;
case FB_BLANK_POWERDOWN:
state = 7;
break;
case FB_BLANK_UNBLANK:
default:
state = 0;
break;
}
aty_st_8(CRTC_EXT_CNTL+1, state);
if (par->chip_gen == rage_M3) {
aty128_set_crt_enable(par, par->crt_on && !blank);
aty128_set_lcd_enable(par, par->lcd_on && !blank);
}
return 0;
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
*/
static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct aty128fb_par *par = info->par;
if (regno > 255
|| (par->crtc.depth == 16 && regno > 63)
|| (par->crtc.depth == 15 && regno > 31))
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
if (regno < 16) {
int i;
u32 *pal = info->pseudo_palette;
switch (par->crtc.depth) {
case 15:
pal[regno] = (regno << 10) | (regno << 5) | regno;
break;
case 16:
pal[regno] = (regno << 11) | (regno << 6) | regno;
break;
case 24:
pal[regno] = (regno << 16) | (regno << 8) | regno;
break;
case 32:
i = (regno << 8) | regno;
pal[regno] = (i << 16) | i;
break;
}
}
if (par->crtc.depth == 16 && regno > 0) {
/*
* With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
* have 32 slots for R and B values but 64 slots for G values.
* Thus the R and B values go in one slot but the G value
* goes in a different slot, and we have to avoid disturbing
* the other fields in the slots we touch.
*/
par->green[regno] = green;
if (regno < 32) {
par->red[regno] = red;
par->blue[regno] = blue;
aty128_st_pal(regno * 8, red, par->green[regno*2],
blue, par);
}
red = par->red[regno/2];
blue = par->blue[regno/2];
regno <<= 2;
} else if (par->crtc.bpp == 16)
regno <<= 3;
aty128_st_pal(regno, red, green, blue, par);
return 0;
}
#define ATY_MIRROR_LCD_ON 0x00000001
#define ATY_MIRROR_CRT_ON 0x00000002
/* out param: u32* backlight value: 0 to 15 */
#define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
/* in param: u32* backlight value: 0 to 15 */
#define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
{
struct aty128fb_par *par = info->par;
u32 value;
int rc;
switch (cmd) {
case FBIO_ATY128_SET_MIRROR:
if (par->chip_gen != rage_M3)
return -EINVAL;
rc = get_user(value, (__u32 __user *)arg);
if (rc)
return rc;
par->lcd_on = (value & 0x01) != 0;
par->crt_on = (value & 0x02) != 0;
if (!par->crt_on && !par->lcd_on)
par->lcd_on = 1;
aty128_set_crt_enable(par, par->crt_on);
aty128_set_lcd_enable(par, par->lcd_on);
return 0;
case FBIO_ATY128_GET_MIRROR:
if (par->chip_gen != rage_M3)
return -EINVAL;
value = (par->crt_on << 1) | par->lcd_on;
return put_user(value, (__u32 __user *)arg);
}
return -EINVAL;
}
static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
{
u32 pmgt;
if (!par->pdev->pm_cap)
return;
/* Set the chip into the appropriate suspend mode (we use D2,
* D3 would require a complete re-initialisation of the chip,
* including PCI config registers, clocks, AGP configuration, ...)
*
* For resume, the core will have already brought us back to D0
*/
if (suspend) {
/* Make sure CRTC2 is reset. Remove that the day we decide to
* actually use CRTC2 and replace it with real code for disabling
* the CRTC2 output during sleep
*/
aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
~(CRTC2_EN));
/* Set the power management mode to be PCI based */
/* Use this magic value for now */
pmgt = 0x0c005407;
aty_st_pll(POWER_MANAGEMENT, pmgt);
(void)aty_ld_pll(POWER_MANAGEMENT);
aty_st_le32(BUS_CNTL1, 0x00000010);
aty_st_le32(MEM_POWER_MISC, 0x0c830000);
msleep(100);
}
}
static int aty128_pci_suspend_late(struct device *dev, pm_message_t state)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct fb_info *info = pci_get_drvdata(pdev);
struct aty128fb_par *par = info->par;
/* We don't do anything but D2, for now we return 0, but
* we may want to change that. How do we know if the BIOS
* can properly take care of D3 ? Also, with swsusp, we
* know we'll be rebooted, ...
*/
#ifndef CONFIG_PPC_PMAC
/* HACK ALERT ! Once I find a proper way to say to each driver
* individually what will happen with it's PCI slot, I'll change
* that. On laptops, the AGP slot is just unclocked, so D2 is
* expected, while on desktops, the card is powered off
*/
return 0;
#endif /* CONFIG_PPC_PMAC */
if (state.event == pdev->dev.power.power_state.event)
return 0;
printk(KERN_DEBUG "aty128fb: suspending...\n");
console_lock();
fb_set_suspend(info, 1);
/* Make sure engine is reset */
wait_for_idle(par);
aty128_reset_engine(par);
wait_for_idle(par);
/* Blank display and LCD */
aty128fb_blank(FB_BLANK_POWERDOWN, info);
/* Sleep */
par->asleep = 1;
par->lock_blank = 1;
#ifdef CONFIG_PPC_PMAC
/* On powermac, we have hooks to properly suspend/resume AGP now,
* use them here. We'll ultimately need some generic support here,
* but the generic code isn't quite ready for that yet
*/
pmac_suspend_agp_for_card(pdev);
#endif /* CONFIG_PPC_PMAC */
/* We need a way to make sure the fbdev layer will _not_ touch the
* framebuffer before we put the chip to suspend state. On 2.4, I
* used dummy fb ops, 2.5 need proper support for this at the
* fbdev level
*/
if (state.event != PM_EVENT_ON)
aty128_set_suspend(par, 1);
console_unlock();
pdev->dev.power.power_state = state;
return 0;
}
static int __maybe_unused aty128_pci_suspend(struct device *dev)
{
return aty128_pci_suspend_late(dev, PMSG_SUSPEND);
}
static int __maybe_unused aty128_pci_hibernate(struct device *dev)
{
return aty128_pci_suspend_late(dev, PMSG_HIBERNATE);
}
static int __maybe_unused aty128_pci_freeze(struct device *dev)
{
return aty128_pci_suspend_late(dev, PMSG_FREEZE);
}
static int aty128_do_resume(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct aty128fb_par *par = info->par;
if (pdev->dev.power.power_state.event == PM_EVENT_ON)
return 0;
/* PCI state will have been restored by the core, so
* we should be in D0 now with our config space fully
* restored
*/
/* Wakeup chip */
aty128_set_suspend(par, 0);
par->asleep = 0;
/* Restore display & engine */
aty128_reset_engine(par);
wait_for_idle(par);
aty128fb_set_par(info);
fb_pan_display(info, &info->var);
fb_set_cmap(&info->cmap, info);
/* Refresh */
fb_set_suspend(info, 0);
/* Unblank */
par->lock_blank = 0;
aty128fb_blank(0, info);
#ifdef CONFIG_PPC_PMAC
/* On powermac, we have hooks to properly suspend/resume AGP now,
* use them here. We'll ultimately need some generic support here,
* but the generic code isn't quite ready for that yet
*/
pmac_resume_agp_for_card(pdev);
#endif /* CONFIG_PPC_PMAC */
pdev->dev.power.power_state = PMSG_ON;
printk(KERN_DEBUG "aty128fb: resumed !\n");
return 0;
}
static int __maybe_unused aty128_pci_resume(struct device *dev)
{
int rc;
console_lock();
rc = aty128_do_resume(to_pci_dev(dev));
console_unlock();
return rc;
}
static int aty128fb_init(void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("aty128fb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("aty128fb", &option))
return -ENODEV;
aty128fb_setup(option);
#endif
return pci_register_driver(&aty128fb_driver);
}
static void __exit aty128fb_exit(void)
{
pci_unregister_driver(&aty128fb_driver);
}
module_init(aty128fb_init);
module_exit(aty128fb_exit);
MODULE_AUTHOR("(c)1999-2003 Brad Douglas <[email protected]>");
MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
MODULE_LICENSE("GPL");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
module_param_named(nomtrr, mtrr, invbool, 0);
MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
| linux-master | drivers/video/fbdev/aty/aty128fb.c |
// SPDX-License-Identifier: GPL-2.0
/*
* ATI Mach64 CT/VT/GT/LT Support
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <video/mach64.h>
#include "atyfb.h"
#ifdef CONFIG_PPC
#include <asm/machdep.h>
#endif
#undef DEBUG
static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par)
{
/* write addr byte */
aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par);
/* read the register value */
return aty_ld_8(CLOCK_CNTL_DATA, par);
}
static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
{
/* write addr byte */
aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
/* write the register value */
aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par);
aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
}
/*
* by Daniel Mantione
* <[email protected]>
*
*
* ATI Mach64 CT clock synthesis description.
*
* All clocks on the Mach64 can be calculated using the same principle:
*
* XTALIN * x * FB_DIV
* CLK = ----------------------
* PLL_REF_DIV * POST_DIV
*
* XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz.
* PLL_REF_DIV can be set by the user, but is the same for all clocks.
* FB_DIV can be set by the user for each clock individually, it should be set
* between 128 and 255, the chip will generate a bad clock signal for too low
* values.
* x depends on the type of clock; usually it is 2, but for the MCLK it can also
* be set to 4.
* POST_DIV can be set by the user for each clock individually, Possible values
* are 1,2,4,8 and for some clocks other values are available too.
* CLK is of course the clock speed that is generated.
*
* The Mach64 has these clocks:
*
* MCLK The clock rate of the chip
* XCLK The clock rate of the on-chip memory
* VCLK0 First pixel clock of first CRT controller
* VCLK1 Second pixel clock of first CRT controller
* VCLK2 Third pixel clock of first CRT controller
* VCLK3 Fourth pixel clock of first CRT controller
* VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
* V2CLK Pixel clock of the second CRT controller.
* SCLK Multi-purpose clock
*
* - MCLK and XCLK use the same FB_DIV
* - VCLK0 .. VCLK3 use the same FB_DIV
* - V2CLK is needed when the second CRTC is used (can be used for dualhead);
* i.e. CRT monitor connected to laptop has different resolution than built
* in LCD monitor.
* - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO,
* Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT.
* - V2CLK is not available on all cards, most likely only the Rage LT-PRO,
* the Rage XL and the Rage Mobility
*
* SCLK can be used to:
* - Clock the chip instead of MCLK
* - Replace XTALIN with a user defined frequency
* - Generate the pixel clock for the LCD monitor (instead of VCLK)
*/
/*
* It can be quite hard to calculate XCLK and MCLK if they don't run at the
* same frequency. Luckily, until now all cards that need asynchrone clock
* speeds seem to have SCLK.
* So this driver uses SCLK to clock the chip and XCLK to clock the memory.
*/
/* ------------------------------------------------------------------------- */
/*
* PLL programming (Mach64 CT family)
*
*
* This procedure sets the display fifo. The display fifo is a buffer that
* contains data read from the video memory that waits to be processed by
* the CRT controller.
*
* On the more modern Mach64 variants, the chip doesn't calculate the
* interval after which the display fifo has to be reloaded from memory
* automatically, the driver has to do it instead.
*/
#define Maximum_DSP_PRECISION 7
const u8 aty_postdividers[8] = {1,2,4,8,3,5,6,12};
static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
{
u32 dsp_off, dsp_on, dsp_xclks;
u32 multiplier, divider, ras_multiplier, ras_divider, tmp;
u8 vshift, xshift;
s8 dsp_precision;
multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
ras_multiplier = pll->xclkmaxrasdelay;
ras_divider = 1;
if (bpp>=8)
divider = divider * (bpp >> 2);
vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */
if (bpp == 0)
vshift--; /* ... but only 32 bits in VGA mode. */
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (pll->xres != 0) {
struct atyfb_par *par = (struct atyfb_par *) info->par;
multiplier = multiplier * par->lcd_width;
divider = divider * pll->xres & ~7;
ras_multiplier = ras_multiplier * par->lcd_width;
ras_divider = ras_divider * pll->xres & ~7;
}
#endif
/* If we don't do this, 32 bits for multiplier & divider won't be
enough in certain situations! */
while (((multiplier | divider) & 1) == 0) {
multiplier = multiplier >> 1;
divider = divider >> 1;
}
/* Determine DSP precision first */
tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
for (dsp_precision = -5; tmp; dsp_precision++)
tmp >>= 1;
if (dsp_precision < 0)
dsp_precision = 0;
else if (dsp_precision > Maximum_DSP_PRECISION)
dsp_precision = Maximum_DSP_PRECISION;
xshift = 6 - dsp_precision;
vshift += xshift;
/* Move on to dsp_off */
dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
(1 << (vshift - xshift));
/* if (bpp == 0)
dsp_on = ((multiplier * 20 << vshift) + divider) / divider;
else */
{
dsp_on = ((multiplier << vshift) + divider) / divider;
tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider;
if (dsp_on < tmp)
dsp_on = tmp;
dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
}
/* Calculate rounding factor and apply it to dsp_on */
tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1;
dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1);
if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) {
dsp_on = dsp_off - (multiplier << vshift) / divider;
dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1);
}
/* Last but not least: dsp_xclks */
dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider;
/* Get register values. */
pll->dsp_on_off = (dsp_on << 16) + dsp_off;
pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
#ifdef DEBUG
printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n",
__func__, pll->dsp_config, pll->dsp_on_off);
#endif
return 0;
}
static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
{
u32 q;
struct atyfb_par *par = (struct atyfb_par *) info->par;
int pllvclk;
/* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
if (q < 16*8 || q > 255*8) {
printk(KERN_CRIT "atyfb: vclk out of range\n");
return -EINVAL;
} else {
pll->vclk_post_div = (q < 128*8);
pll->vclk_post_div += (q < 64*8);
pll->vclk_post_div += (q < 32*8);
}
pll->vclk_post_div_real = aty_postdividers[pll->vclk_post_div];
// pll->vclk_post_div <<= 6;
pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
(par->ref_clk_per * pll->pll_ref_div);
#ifdef DEBUG
printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n",
__func__, pllvclk, pllvclk / pll->vclk_post_div_real);
#endif
pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
/* Set ECP (scaler/overlay clock) divider */
if (par->pll_limits.ecp_max) {
int ecp = pllvclk / pll->vclk_post_div_real;
int ecp_div = 0;
while (ecp > par->pll_limits.ecp_max && ecp_div < 2) {
ecp >>= 1;
ecp_div++;
}
pll->pll_vclk_cntl |= ecp_div << 4;
}
return 0;
}
static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
int err;
if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
return err;
if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
return err;
/*aty_calc_pll_ct(info, &pll->ct);*/
return 0;
}
static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 ret;
ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if(pll->ct.xres > 0) {
ret *= par->lcd_width;
ret /= pll->ct.xres;
}
#endif
#ifdef DEBUG
printk("atyfb(%s): calculated 0x%08X(%i)\n", __func__, ret, ret);
#endif
return ret;
}
void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 crtc_gen_cntl;
u8 tmp, tmp2;
#ifdef CONFIG_FB_ATY_GENERIC_LCD
u32 lcd_gen_cntrl = 0;
#endif
#ifdef DEBUG
printk("atyfb(%s): about to program:\n"
"pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n",
__func__,
pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n",
__func__,
par->clk_wr_offset, pll->ct.vclk_fb_div,
pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
#endif
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table != 0) {
/* turn off LCD */
lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par);
aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par);
}
#endif
aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par);
/* Temporarily switch to accelerator mode */
crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par);
/* Reset VCLK generator */
aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
/* Set post-divider */
tmp2 = par->clk_wr_offset << 1;
tmp = aty_ld_pll_ct(VCLK_POST_DIV, par);
tmp &= ~(0x03U << tmp2);
tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
aty_st_pll_ct(VCLK_POST_DIV, tmp, par);
/* Set extended post-divider */
tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par);
tmp &= ~(0x10U << par->clk_wr_offset);
tmp &= 0xF0U;
tmp |= pll->ct.pll_ext_cntl;
aty_st_pll_ct(PLL_EXT_CNTL, tmp, par);
/* Set feedback divider */
tmp = VCLK0_FB_DIV + par->clk_wr_offset;
aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
/* End VCLK generator reset */
aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
mdelay(5);
aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
mdelay(1);
/* Restore mode register */
if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par);
if (M64_HAS(GTB_DSP)) {
u8 dll_cntl;
if (M64_HAS(XL_DLL))
dll_cntl = 0x80;
else if (par->ram_type >= SDRAM)
dll_cntl = 0xa6;
else
dll_cntl = 0xa0;
aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
aty_st_pll_ct(VFC_CNTL, 0x1b, par);
aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
mdelay(10);
aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
mdelay(10);
aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par);
mdelay(10);
aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par);
}
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table != 0) {
/* restore LCD */
aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par);
}
#endif
}
static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u8 tmp, clock;
clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
tmp = clock << 1;
pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
if (M64_HAS(GTB_DSP)) {
pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
}
}
static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u8 mpost_div, xpost_div, sclk_post_div_real;
u32 q, memcntl, trp;
u32 dsp_config;
#ifdef DEBUG
int pllmclk, pllsclk;
#endif
pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
pll->ct.xclk_ref_div = 1;
switch (pll->ct.xclk_post_div) {
case 0: case 1: case 2: case 3:
break;
case 4:
pll->ct.xclk_ref_div = 3;
pll->ct.xclk_post_div = 0;
break;
default:
printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
return -EINVAL;
}
pll->ct.mclk_fb_mult = 2;
if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
pll->ct.mclk_fb_mult = 4;
pll->ct.xclk_post_div -= 1;
}
#ifdef DEBUG
printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n",
__func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
#endif
memcntl = aty_ld_le32(MEM_CNTL, par);
trp = (memcntl & 0x300) >> 8;
pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
if (M64_HAS(FIFO_32)) {
pll->ct.fifo_size = 32;
} else {
pll->ct.fifo_size = 24;
pll->ct.xclkpagefaultdelay += 2;
pll->ct.xclkmaxrasdelay += 3;
}
switch (par->ram_type) {
case DRAM:
if (info->fix.smem_len<=ONE_MB) {
pll->ct.dsp_loop_latency = 10;
} else {
pll->ct.dsp_loop_latency = 8;
pll->ct.xclkpagefaultdelay += 2;
}
break;
case EDO:
case PSEUDO_EDO:
if (info->fix.smem_len<=ONE_MB) {
pll->ct.dsp_loop_latency = 9;
} else {
pll->ct.dsp_loop_latency = 8;
pll->ct.xclkpagefaultdelay += 1;
}
break;
case SDRAM:
if (info->fix.smem_len<=ONE_MB) {
pll->ct.dsp_loop_latency = 11;
} else {
pll->ct.dsp_loop_latency = 10;
pll->ct.xclkpagefaultdelay += 1;
}
break;
case SGRAM:
pll->ct.dsp_loop_latency = 8;
pll->ct.xclkpagefaultdelay += 3;
break;
default:
pll->ct.dsp_loop_latency = 11;
pll->ct.xclkpagefaultdelay += 3;
break;
}
if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
/* Allow BIOS to override */
dsp_config = aty_ld_le32(DSP_CONFIG, par);
aty_ld_le32(DSP_ON_OFF, par);
aty_ld_le32(VGA_DSP_CONFIG, par);
aty_ld_le32(VGA_DSP_ON_OFF, par);
if (dsp_config)
pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
#if 0
FIXME: is it relevant for us?
if ((!dsp_on_off && !M64_HAS(RESET_3D)) ||
((dsp_on_off == vga_dsp_on_off) &&
(!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW)))) {
vga_dsp_on_off &= VGA_DSP_OFF;
vga_dsp_config &= VGA_DSP_XCLKS_PER_QW;
if (ATIDivide(vga_dsp_on_off, vga_dsp_config, 5, 1) > 24)
pll->ct.fifo_size = 32;
else
pll->ct.fifo_size = 24;
}
#endif
/* Exit if the user does not want us to tamper with the clock
rates of her chip. */
if (par->mclk_per == 0) {
u8 mclk_fb_div, pll_ext_cntl;
pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
pll->ct.xclk_post_div_real = aty_postdividers[pll_ext_cntl & 0x07];
mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
if (pll_ext_cntl & PLL_MFB_TIMES_4_2B)
mclk_fb_div <<= 1;
pll->ct.mclk_fb_div = mclk_fb_div;
return 0;
}
pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
/* FIXME: use the VTB/GTB /3 post divider if it's better suited */
q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
(pll->ct.mclk_fb_mult * par->xclk_per);
if (q < 16*8 || q > 255*8) {
printk(KERN_CRIT "atxfb: xclk out of range\n");
return -EINVAL;
} else {
xpost_div = (q < 128*8);
xpost_div += (q < 64*8);
xpost_div += (q < 32*8);
}
pll->ct.xclk_post_div_real = aty_postdividers[xpost_div];
pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
#ifdef CONFIG_PPC
if (machine_is(powermac)) {
/* Override PLL_EXT_CNTL & 0x07. */
pll->ct.xclk_post_div = xpost_div;
pll->ct.xclk_ref_div = 1;
}
#endif
#ifdef DEBUG
pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
(par->ref_clk_per * pll->ct.pll_ref_div);
printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n",
__func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
#endif
if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
pll->ct.pll_gen_cntl = OSC_EN;
else
pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
if (M64_HAS(MAGIC_POSTDIV))
pll->ct.pll_ext_cntl = 0;
else
pll->ct.pll_ext_cntl = xpost_div;
if (pll->ct.mclk_fb_mult == 4)
pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
if (par->mclk_per == par->xclk_per) {
pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
} else {
/*
* The chip clock is not equal to the memory clock.
* Therefore we will use sclk to clock the chip.
*/
pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
if (q < 16*8 || q > 255*8) {
printk(KERN_CRIT "atyfb: mclk out of range\n");
return -EINVAL;
} else {
mpost_div = (q < 128*8);
mpost_div += (q < 64*8);
mpost_div += (q < 32*8);
}
sclk_post_div_real = aty_postdividers[mpost_div];
pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
pll->ct.spll_cntl2 = mpost_div << 4;
#ifdef DEBUG
pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
(par->ref_clk_per * pll->ct.pll_ref_div);
printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n",
__func__, pllsclk, pllsclk / sclk_post_div_real);
#endif
}
/* Disable the extra precision pixel clock controls since we do not use them. */
pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
return 0;
}
static void aty_resume_pll_ct(const struct fb_info *info,
union aty_pll *pll)
{
struct atyfb_par *par = info->par;
if (par->mclk_per != par->xclk_per) {
/*
* This disables the sclk, crashes the computer as reported:
* aty_st_pll_ct(SPLL_CNTL2, 3, info);
*
* So it seems the sclk must be enabled before it is used;
* so PLL_GEN_CNTL must be programmed *after* the sclk.
*/
aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
/*
* SCLK has been started. Wait for the PLL to lock. 5 ms
* should be enough according to mach64 programmer's guide.
*/
mdelay(5);
}
aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);
}
static int dummy(void)
{
return 0;
}
const struct aty_dac_ops aty_dac_ct = {
.set_dac = (void *) dummy,
};
const struct aty_pll_ops aty_pll_ct = {
.var_to_pll = aty_var_to_pll_ct,
.pll_to_var = aty_pll_to_var_ct,
.set_pll = aty_set_pll_ct,
.get_pll = aty_get_pll_ct,
.init_pll = aty_init_pll_ct,
.resume_pll = aty_resume_pll_ct,
};
| linux-master | drivers/video/fbdev/aty/mach64_ct.c |
// SPDX-License-Identifier: GPL-2.0
#include "radeonfb.h"
/* the accelerated functions here are patterned after the
* "ACCEL_MMIO" ifdef branches in XFree86
* --dte
*/
static void radeon_fixup_offset(struct radeonfb_info *rinfo)
{
u32 local_base;
/* *** Ugly workaround *** */
/*
* On some platforms, the video memory is mapped at 0 in radeon chip space
* (like PPCs) by the firmware. X will always move it up so that it's seen
* by the chip to be at the same address as the PCI BAR.
* That means that when switching back from X, there is a mismatch between
* the offsets programmed into the engine. This means that potentially,
* accel operations done before radeonfb has a chance to re-init the engine
* will have incorrect offsets, and potentially trash system memory !
*
* The correct fix is for fbcon to never call any accel op before the engine
* has properly been re-initialized (by a call to set_var), but this is a
* complex fix. This workaround in the meantime, called before every accel
* operation, makes sure the offsets are in sync.
*/
radeon_fifo_wait (1);
local_base = INREG(MC_FB_LOCATION) << 16;
if (local_base == rinfo->fb_local_base)
return;
rinfo->fb_local_base = local_base;
radeon_fifo_wait (3);
OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
(rinfo->fb_local_base >> 10));
OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
}
static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
const struct fb_fillrect *region)
{
radeon_fifo_wait(4);
OUTREG(DP_GUI_MASTER_CNTL,
rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */
| GMC_BRUSH_SOLID_COLOR
| ROP3_P);
if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP)
OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]);
else
OUTREG(DP_BRUSH_FRGD_CLR, region->color);
OUTREG(DP_WRITE_MSK, 0xffffffff);
OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
radeon_fifo_wait(2);
OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
radeon_fifo_wait(2);
OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
}
void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
{
struct radeonfb_info *rinfo = info->par;
struct fb_fillrect modded;
int vxres, vyres;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_fillrect(info, region);
return;
}
radeon_fixup_offset(rinfo);
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
memcpy(&modded, region, sizeof(struct fb_fillrect));
if(!modded.width || !modded.height ||
modded.dx >= vxres || modded.dy >= vyres)
return;
if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
radeonfb_prim_fillrect(rinfo, &modded);
}
static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
const struct fb_copyarea *area)
{
int xdir, ydir;
u32 sx, sy, dx, dy, w, h;
w = area->width; h = area->height;
dx = area->dx; dy = area->dy;
sx = area->sx; sy = area->sy;
xdir = sx - dx;
ydir = sy - dy;
if ( xdir < 0 ) { sx += w-1; dx += w-1; }
if ( ydir < 0 ) { sy += h-1; dy += h-1; }
radeon_fifo_wait(3);
OUTREG(DP_GUI_MASTER_CNTL,
rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */
| GMC_BRUSH_NONE
| GMC_SRC_DSTCOLOR
| ROP3_S
| DP_SRC_SOURCE_MEMORY );
OUTREG(DP_WRITE_MSK, 0xffffffff);
OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
| (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
radeon_fifo_wait(2);
OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
radeon_fifo_wait(3);
OUTREG(SRC_Y_X, (sy << 16) | sx);
OUTREG(DST_Y_X, (dy << 16) | dx);
OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
}
void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
{
struct radeonfb_info *rinfo = info->par;
struct fb_copyarea modded;
u32 vxres, vyres;
modded.sx = area->sx;
modded.sy = area->sy;
modded.dx = area->dx;
modded.dy = area->dy;
modded.width = area->width;
modded.height = area->height;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_copyarea(info, area);
return;
}
radeon_fixup_offset(rinfo);
vxres = info->var.xres_virtual;
vyres = info->var.yres_virtual;
if(!modded.width || !modded.height ||
modded.sx >= vxres || modded.sy >= vyres ||
modded.dx >= vxres || modded.dy >= vyres)
return;
if(modded.sx + modded.width > vxres) modded.width = vxres - modded.sx;
if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
if(modded.sy + modded.height > vyres) modded.height = vyres - modded.sy;
if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
radeonfb_prim_copyarea(rinfo, &modded);
}
void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct radeonfb_info *rinfo = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return;
radeon_engine_idle();
cfb_imageblit(info, image);
}
int radeonfb_sync(struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return 0;
radeon_engine_idle();
return 0;
}
void radeonfb_engine_reset(struct radeonfb_info *rinfo)
{
u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
u32 host_path_cntl;
radeon_engine_flush (rinfo);
clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
mclk_cntl = INPLL(MCLK_CNTL);
OUTPLL(MCLK_CNTL, (mclk_cntl |
FORCEON_MCLKA |
FORCEON_MCLKB |
FORCEON_YCLKA |
FORCEON_YCLKB |
FORCEON_MC |
FORCEON_AIC));
host_path_cntl = INREG(HOST_PATH_CNTL);
rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
if (IS_R300_VARIANT(rinfo)) {
u32 tmp;
OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |
SOFT_RESET_CP |
SOFT_RESET_HI |
SOFT_RESET_E2));
INREG(RBBM_SOFT_RESET);
OUTREG(RBBM_SOFT_RESET, 0);
tmp = INREG(RB2D_DSTCACHE_MODE);
OUTREG(RB2D_DSTCACHE_MODE, tmp | (1 << 17)); /* FIXME */
} else {
OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
SOFT_RESET_CP |
SOFT_RESET_HI |
SOFT_RESET_SE |
SOFT_RESET_RE |
SOFT_RESET_PP |
SOFT_RESET_E2 |
SOFT_RESET_RB);
INREG(RBBM_SOFT_RESET);
OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
~(SOFT_RESET_CP |
SOFT_RESET_HI |
SOFT_RESET_SE |
SOFT_RESET_RE |
SOFT_RESET_PP |
SOFT_RESET_E2 |
SOFT_RESET_RB));
INREG(RBBM_SOFT_RESET);
}
OUTREG(HOST_PATH_CNTL, host_path_cntl | HDP_SOFT_RESET);
INREG(HOST_PATH_CNTL);
OUTREG(HOST_PATH_CNTL, host_path_cntl);
if (!IS_R300_VARIANT(rinfo))
OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
OUTPLL(MCLK_CNTL, mclk_cntl);
}
void radeonfb_engine_init (struct radeonfb_info *rinfo)
{
unsigned long temp;
/* disable 3D engine */
OUTREG(RB3D_CNTL, 0);
radeonfb_engine_reset(rinfo);
radeon_fifo_wait (1);
if (IS_R300_VARIANT(rinfo)) {
OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) |
RB2D_DC_AUTOFLUSH_ENABLE |
RB2D_DC_DC_DISABLE_IGNORE_PE);
} else {
/* This needs to be double checked with ATI. Latest X driver
* completely "forgets" to set this register on < r3xx, and
* we used to just write 0 there... I'll keep the 0 and update
* that when we have sorted things out on X side.
*/
OUTREG(RB2D_DSTCACHE_MODE, 0);
}
radeon_fifo_wait (3);
/* We re-read MC_FB_LOCATION from card as it can have been
* modified by XFree drivers (ouch !)
*/
rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) |
(rinfo->fb_local_base >> 10));
OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
radeon_fifo_wait (1);
#if defined(__BIG_ENDIAN)
OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
#else
OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
#endif
radeon_fifo_wait (2);
OUTREG(DEFAULT_SC_TOP_LEFT, 0);
OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
DEFAULT_SC_BOTTOM_MAX));
temp = radeon_get_dstbpp(rinfo->depth);
rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
radeon_fifo_wait (1);
OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
GMC_BRUSH_SOLID_COLOR |
GMC_SRC_DATATYPE_COLOR));
radeon_fifo_wait (7);
/* clear line drawing regs */
OUTREG(DST_LINE_START, 0);
OUTREG(DST_LINE_END, 0);
/* set brush color regs */
OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
/* set source color regs */
OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
/* default write mask */
OUTREG(DP_WRITE_MSK, 0xffffffff);
radeon_engine_idle ();
}
| linux-master | drivers/video/fbdev/aty/radeon_accel.c |
/*
* drivers/video/aty/radeon_base.c
*
* framebuffer driver for ATI Radeon chipset video boards
*
* Copyright 2003 Ben. Herrenschmidt <[email protected]>
* Copyright 2000 Ani Joshi <[email protected]>
*
* i2c bits from Luca Tettamanti <[email protected]>
*
* Special thanks to ATI DevRel team for their hardware donations.
*
* ...Insert GPL boilerplate here...
*
* Significant portions of this driver apdated from XFree86 Radeon
* driver which has the following copyright notice:
*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* XFree86 driver authors:
*
* Kevin E. Martin <[email protected]>
* Rickard E. Faith <[email protected]>
* Alan Hourihane <[email protected]>
*
*/
#define RADEON_VERSION "0.2.0"
#include "radeonfb.h"
#include <linux/aperture.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/time.h>
#include <linux/fb.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/vmalloc.h>
#include <linux/device.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#ifdef CONFIG_PPC
#include "../macmodes.h"
#ifdef CONFIG_BOOTX_TEXT
#include <asm/btext.h>
#endif
#endif /* CONFIG_PPC */
#include <video/radeon.h>
#include <linux/radeonfb.h>
#include "../edid.h" // MOVE THAT TO include/video
#include "ati_ids.h"
#define MAX_MAPPED_VRAM (2048*2048*4)
#define MIN_MAPPED_VRAM (1024*768*1)
#define CHIP_DEF(id, family, flags) \
{ PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
static const struct pci_device_id radeonfb_pci_table[] = {
/* Radeon Xpress 200m */
CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
/* Mobility M6 */
CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
/* Radeon VE/7000 */
CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
/* Radeon IGP320M (U1) */
CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
/* Radeon IGP320 (A3) */
CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
/* IGP330M/340M/350M (U2) */
CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
/* IGP330/340/350 (A4) */
CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
/* Mobility 7000 IGP */
CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
/* 7000 IGP (A4+) */
CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
/* 8500 AIW */
CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
/* 8700/8800 */
CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
/* 8500 */
CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
/* 9100 */
CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
/* Mobility M7 */
CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
/* 7500 */
CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
/* Mobility M9 */
CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
/* 9000/Pro */
CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
/* Mobility 9100 IGP (U3) */
CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
/* 9100 IGP (A5) */
CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
/* Mobility 9200 (M9+) */
CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
/* 9200 */
CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
/* 9500 */
CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
/* 9600TX / FireGL Z1 */
CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
/* 9700/9500/Pro/FireGL X1 */
CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
/* Mobility M10/M11 */
CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
/* 9600/FireGL T2 */
CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
/* 9800/Pro/FileGL X2 */
CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
/* Newer stuff */
CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
/* Original Radeon/7200 */
CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
{ 0, }
};
MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
typedef struct {
u16 reg;
u32 val;
} reg_val;
/* these common regs are cleared before mode setting so they do not
* interfere with anything
*/
static reg_val common_regs[] = {
{ OVR_CLR, 0 },
{ OVR_WID_LEFT_RIGHT, 0 },
{ OVR_WID_TOP_BOTTOM, 0 },
{ OV0_SCALE_CNTL, 0 },
{ SUBPIC_CNTL, 0 },
{ VIPH_CONTROL, 0 },
{ I2C_CNTL_1, 0 },
{ GEN_INT_CNTL, 0 },
{ CAP0_TRIG_CNTL, 0 },
{ CAP1_TRIG_CNTL, 0 },
};
/*
* globals
*/
static char *mode_option;
static char *monitor_layout;
static bool noaccel = 0;
static int default_dynclk = -2;
static bool nomodeset = 0;
static bool ignore_edid = 0;
static bool mirror = 0;
static int panel_yres = 0;
static bool force_dfp = 0;
static bool force_measure_pll = 0;
static bool nomtrr = 0;
static bool force_sleep;
static bool ignore_devlist;
static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
/* Note about this function: we have some rare cases where we must not schedule,
* this typically happen with our special "wake up early" hook which allows us to
* wake up the graphic chip (and thus get the console back) before everything else
* on some machines that support that mechanism. At this point, interrupts are off
* and scheduling is not permitted
*/
void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
{
if (rinfo->no_schedule || oops_in_progress)
mdelay(ms);
else
msleep(ms);
}
void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo)
{
/* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */
(void)INREG(CLOCK_CNTL_DATA);
(void)INREG(CRTC_GEN_CNTL);
}
void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo)
{
if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
/* we can't deal with posted writes here ... */
_radeon_msleep(rinfo, 5);
}
if (rinfo->errata & CHIP_ERRATA_R300_CG) {
u32 save, tmp;
save = INREG(CLOCK_CNTL_INDEX);
tmp = save & ~(0x3f | PLL_WR_EN);
OUTREG(CLOCK_CNTL_INDEX, tmp);
tmp = INREG(CLOCK_CNTL_DATA);
OUTREG(CLOCK_CNTL_INDEX, save);
}
}
void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask)
{
unsigned long flags;
unsigned int tmp;
spin_lock_irqsave(&rinfo->reg_lock, flags);
tmp = INREG(addr);
tmp &= (mask);
tmp |= (val);
OUTREG(addr, tmp);
spin_unlock_irqrestore(&rinfo->reg_lock, flags);
}
u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
{
u32 data;
OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
radeon_pll_errata_after_index(rinfo);
data = INREG(CLOCK_CNTL_DATA);
radeon_pll_errata_after_data(rinfo);
return data;
}
void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
{
OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
radeon_pll_errata_after_index(rinfo);
OUTREG(CLOCK_CNTL_DATA, val);
radeon_pll_errata_after_data(rinfo);
}
void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
u32 val, u32 mask)
{
unsigned int tmp;
tmp = __INPLL(rinfo, index);
tmp &= (mask);
tmp |= (val);
__OUTPLL(rinfo, index, tmp);
}
void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{
int i;
for (i=0; i<2000000; i++) {
if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
return;
udelay(1);
}
printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
}
void radeon_engine_flush(struct radeonfb_info *rinfo)
{
int i;
/* Initiate flush */
OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
~RB2D_DC_FLUSH_ALL);
/* Ensure FIFO is empty, ie, make sure the flush commands
* has reached the cache
*/
_radeon_fifo_wait(rinfo, 64);
/* Wait for the flush to complete */
for (i=0; i < 2000000; i++) {
if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
return;
udelay(1);
}
printk(KERN_ERR "radeonfb: Flush Timeout !\n");
}
void _radeon_engine_idle(struct radeonfb_info *rinfo)
{
int i;
/* ensure FIFO is empty before waiting for idle */
_radeon_fifo_wait(rinfo, 64);
for (i=0; i<2000000; i++) {
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
radeon_engine_flush(rinfo);
return;
}
udelay(1);
}
printk(KERN_ERR "radeonfb: Idle Timeout !\n");
}
static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
{
if (!rinfo->bios_seg)
return;
pci_unmap_rom(dev, rinfo->bios_seg);
}
static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
{
void __iomem *rom;
u16 dptr;
u8 rom_type;
size_t rom_size;
/* If this is a primary card, there is a shadow copy of the
* ROM somewhere in the first meg. We will just ignore the copy
* and use the ROM directly.
*/
/* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
unsigned int temp;
temp = INREG(MPP_TB_CONFIG);
temp &= 0x00ffffffu;
temp |= 0x04 << 24;
OUTREG(MPP_TB_CONFIG, temp);
temp = INREG(MPP_TB_CONFIG);
rom = pci_map_rom(dev, &rom_size);
if (!rom) {
printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
pci_name(rinfo->pdev));
return -ENOMEM;
}
rinfo->bios_seg = rom;
/* Very simple test to make sure it appeared */
if (BIOS_IN16(0) != 0xaa55) {
printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
"should be 0xaa55\n",
pci_name(rinfo->pdev), BIOS_IN16(0));
goto failed;
}
/* Look for the PCI data to check the ROM type */
dptr = BIOS_IN16(0x18);
/* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
* for now, until I've verified this works everywhere. The goal here is more
* to phase out Open Firmware images.
*
* Currently, we only look at the first PCI data, we could iteratre and deal with
* them all, and we should use fb_bios_start relative to start of image and not
* relative start of ROM, but so far, I never found a dual-image ATI card
*
* typedef struct {
* u32 signature; + 0x00
* u16 vendor; + 0x04
* u16 device; + 0x06
* u16 reserved_1; + 0x08
* u16 dlen; + 0x0a
* u8 drevision; + 0x0c
* u8 class_hi; + 0x0d
* u16 class_lo; + 0x0e
* u16 ilen; + 0x10
* u16 irevision; + 0x12
* u8 type; + 0x14
* u8 indicator; + 0x15
* u16 reserved_2; + 0x16
* } pci_data_t;
*/
if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
"incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
goto anyway;
}
rom_type = BIOS_IN8(dptr + 0x14);
switch(rom_type) {
case 0:
printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
break;
case 1:
printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
goto failed;
case 2:
printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
goto failed;
default:
printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
goto failed;
}
anyway:
/* Locate the flat panel infos, do some sanity checking !!! */
rinfo->fp_bios_start = BIOS_IN16(0x48);
return 0;
failed:
rinfo->bios_seg = NULL;
radeon_unmap_ROM(rinfo, dev);
return -ENXIO;
}
#ifdef CONFIG_X86
static int radeon_find_mem_vbios(struct radeonfb_info *rinfo)
{
/* I simplified this code as we used to miss the signatures in
* a lot of case. It's now closer to XFree, we just don't check
* for signatures at all... Something better will have to be done
* if we end up having conflicts
*/
u32 segstart;
void __iomem *rom_base = NULL;
for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
rom_base = ioremap(segstart, 0x10000);
if (rom_base == NULL)
return -ENOMEM;
if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
break;
iounmap(rom_base);
rom_base = NULL;
}
if (rom_base == NULL)
return -ENXIO;
/* Locate the flat panel infos, do some sanity checking !!! */
rinfo->bios_seg = rom_base;
rinfo->fp_bios_start = BIOS_IN16(0x48);
return 0;
}
#endif
#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
/*
* Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
* tree. Hopefully, ATI OF driver is kind enough to fill these
*/
static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
{
struct device_node *dp = rinfo->of_node;
const u32 *val;
if (dp == NULL)
return -ENODEV;
val = of_get_property(dp, "ATY,RefCLK", NULL);
if (!val || !*val) {
printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
return -EINVAL;
}
rinfo->pll.ref_clk = (*val) / 10;
val = of_get_property(dp, "ATY,SCLK", NULL);
if (val && *val)
rinfo->pll.sclk = (*val) / 10;
val = of_get_property(dp, "ATY,MCLK", NULL);
if (val && *val)
rinfo->pll.mclk = (*val) / 10;
return 0;
}
#endif /* CONFIG_PPC || CONFIG_SPARC */
/*
* Read PLL infos from chip registers
*/
static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
{
unsigned char ppll_div_sel;
unsigned Ns, Nm, M;
unsigned sclk, mclk, tmp, ref_div;
int hTotal, vTotal, num, denom, m, n;
unsigned long long hz, vclk;
long xtal;
ktime_t start_time, stop_time;
u64 total_usecs;
int i;
/* Ugh, we cut interrupts, bad bad bad, but we want some precision
* here, so... --BenH
*/
/* Flush PCI buffers ? */
tmp = INREG16(DEVICE_ID);
local_irq_disable();
for(i=0; i<1000000; i++)
if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
break;
start_time = ktime_get();
for(i=0; i<1000000; i++)
if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
break;
for(i=0; i<1000000; i++)
if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
break;
stop_time = ktime_get();
local_irq_enable();
total_usecs = ktime_us_delta(stop_time, start_time);
if (total_usecs >= 10 * USEC_PER_SEC || total_usecs == 0)
return -1;
hz = USEC_PER_SEC/(u32)total_usecs;
hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
vclk = (long long)hTotal * (long long)vTotal * hz;
switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
case 0:
default:
num = 1;
denom = 1;
break;
case 1:
n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
num = 2*n;
denom = 2*m;
break;
case 2:
n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
num = 2*n;
denom = 2*m;
break;
}
ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
radeon_pll_errata_after_index(rinfo);
n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
m = (INPLL(PPLL_REF_DIV) & 0x3ff);
num *= n;
denom *= m;
switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
case 1:
denom *= 2;
break;
case 2:
denom *= 4;
break;
case 3:
denom *= 8;
break;
case 4:
denom *= 3;
break;
case 6:
denom *= 6;
break;
case 7:
denom *= 12;
break;
}
vclk *= denom;
do_div(vclk, 1000 * num);
xtal = vclk;
if ((xtal > 26900) && (xtal < 27100))
xtal = 2700;
else if ((xtal > 14200) && (xtal < 14400))
xtal = 1432;
else if ((xtal > 29400) && (xtal < 29600))
xtal = 2950;
else {
printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
return -1;
}
tmp = INPLL(M_SPLL_REF_FB_DIV);
ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
Ns = (tmp & 0xff0000) >> 16;
Nm = (tmp & 0xff00) >> 8;
M = (tmp & 0xff);
sclk = round_div((2 * Ns * xtal), (2 * M));
mclk = round_div((2 * Nm * xtal), (2 * M));
/* we're done, hopefully these are sane values */
rinfo->pll.ref_clk = xtal;
rinfo->pll.ref_div = ref_div;
rinfo->pll.sclk = sclk;
rinfo->pll.mclk = mclk;
return 0;
}
/*
* Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
*/
static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
{
/*
* In the case nothing works, these are defaults; they are mostly
* incomplete, however. It does provide ppll_max and _min values
* even for most other methods, however.
*/
switch (rinfo->chipset) {
case PCI_DEVICE_ID_ATI_RADEON_QW:
case PCI_DEVICE_ID_ATI_RADEON_QX:
rinfo->pll.ppll_max = 35000;
rinfo->pll.ppll_min = 12000;
rinfo->pll.mclk = 23000;
rinfo->pll.sclk = 23000;
rinfo->pll.ref_clk = 2700;
break;
case PCI_DEVICE_ID_ATI_RADEON_QL:
case PCI_DEVICE_ID_ATI_RADEON_QN:
case PCI_DEVICE_ID_ATI_RADEON_QO:
case PCI_DEVICE_ID_ATI_RADEON_Ql:
case PCI_DEVICE_ID_ATI_RADEON_BB:
rinfo->pll.ppll_max = 35000;
rinfo->pll.ppll_min = 12000;
rinfo->pll.mclk = 27500;
rinfo->pll.sclk = 27500;
rinfo->pll.ref_clk = 2700;
break;
case PCI_DEVICE_ID_ATI_RADEON_Id:
case PCI_DEVICE_ID_ATI_RADEON_Ie:
case PCI_DEVICE_ID_ATI_RADEON_If:
case PCI_DEVICE_ID_ATI_RADEON_Ig:
rinfo->pll.ppll_max = 35000;
rinfo->pll.ppll_min = 12000;
rinfo->pll.mclk = 25000;
rinfo->pll.sclk = 25000;
rinfo->pll.ref_clk = 2700;
break;
case PCI_DEVICE_ID_ATI_RADEON_ND:
case PCI_DEVICE_ID_ATI_RADEON_NE:
case PCI_DEVICE_ID_ATI_RADEON_NF:
case PCI_DEVICE_ID_ATI_RADEON_NG:
rinfo->pll.ppll_max = 40000;
rinfo->pll.ppll_min = 20000;
rinfo->pll.mclk = 27000;
rinfo->pll.sclk = 27000;
rinfo->pll.ref_clk = 2700;
break;
case PCI_DEVICE_ID_ATI_RADEON_QD:
case PCI_DEVICE_ID_ATI_RADEON_QE:
case PCI_DEVICE_ID_ATI_RADEON_QF:
case PCI_DEVICE_ID_ATI_RADEON_QG:
default:
rinfo->pll.ppll_max = 35000;
rinfo->pll.ppll_min = 12000;
rinfo->pll.mclk = 16600;
rinfo->pll.sclk = 16600;
rinfo->pll.ref_clk = 2700;
break;
}
rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
/*
* Retrieve PLL infos from Open Firmware first
*/
if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
goto found;
}
#endif /* CONFIG_PPC || CONFIG_SPARC */
/*
* Check out if we have an X86 which gave us some PLL informations
* and if yes, retrieve them
*/
if (!force_measure_pll && rinfo->bios_seg) {
u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
goto found;
}
/*
* We didn't get PLL parameters from either OF or BIOS, we try to
* probe them
*/
if (radeon_probe_pll_params(rinfo) == 0) {
printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
goto found;
}
/*
* Fall back to already-set defaults...
*/
printk(KERN_INFO "radeonfb: Used default PLL infos\n");
found:
/*
* Some methods fail to retrieve SCLK and MCLK values, we apply default
* settings in this case (200Mhz). If that really happens often, we
* could fetch from registers instead...
*/
if (rinfo->pll.mclk == 0)
rinfo->pll.mclk = 20000;
if (rinfo->pll.sclk == 0)
rinfo->pll.sclk = 20000;
printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
rinfo->pll.ref_div,
rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
}
static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
struct fb_var_screeninfo v;
int nom, den;
unsigned int pitch;
if (radeon_match_mode(rinfo, &v, var))
return -EINVAL;
switch (v.bits_per_pixel) {
case 0 ... 8:
v.bits_per_pixel = 8;
break;
case 9 ... 16:
v.bits_per_pixel = 16;
break;
case 25 ... 32:
v.bits_per_pixel = 32;
break;
default:
return -EINVAL;
}
switch (var_to_depth(&v)) {
case 8:
nom = den = 1;
v.red.offset = v.green.offset = v.blue.offset = 0;
v.red.length = v.green.length = v.blue.length = 8;
v.transp.offset = v.transp.length = 0;
break;
case 15:
nom = 2;
den = 1;
v.red.offset = 10;
v.green.offset = 5;
v.blue.offset = 0;
v.red.length = v.green.length = v.blue.length = 5;
v.transp.offset = v.transp.length = 0;
break;
case 16:
nom = 2;
den = 1;
v.red.offset = 11;
v.green.offset = 5;
v.blue.offset = 0;
v.red.length = 5;
v.green.length = 6;
v.blue.length = 5;
v.transp.offset = v.transp.length = 0;
break;
case 24:
nom = 4;
den = 1;
v.red.offset = 16;
v.green.offset = 8;
v.blue.offset = 0;
v.red.length = v.blue.length = v.green.length = 8;
v.transp.offset = v.transp.length = 0;
break;
case 32:
nom = 4;
den = 1;
v.red.offset = 16;
v.green.offset = 8;
v.blue.offset = 0;
v.red.length = v.blue.length = v.green.length = 8;
v.transp.offset = 24;
v.transp.length = 8;
break;
default:
printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
var->xres, var->yres, var->bits_per_pixel);
return -EINVAL;
}
if (v.yres_virtual < v.yres)
v.yres_virtual = v.yres;
if (v.xres_virtual < v.xres)
v.xres_virtual = v.xres;
/* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
* with some panels, though I don't quite like this solution
*/
if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
v.xres_virtual = v.xres_virtual & ~7ul;
} else {
pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
& ~(0x3f)) >> 6;
v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
}
if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
return -EINVAL;
if (v.xres_virtual < v.xres)
v.xres = v.xres_virtual;
if (v.xoffset > v.xres_virtual - v.xres)
v.xoffset = v.xres_virtual - v.xres - 1;
if (v.yoffset > v.yres_virtual - v.yres)
v.yoffset = v.yres_virtual - v.yres - 1;
v.red.msb_right = v.green.msb_right = v.blue.msb_right =
v.transp.offset = v.transp.length =
v.transp.msb_right = 0;
memcpy(var, &v, sizeof(v));
return 0;
}
static int radeonfb_pan_display (struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
if ((var->xoffset + info->var.xres > info->var.xres_virtual)
|| (var->yoffset + info->var.yres > info->var.yres_virtual))
return -EINVAL;
if (rinfo->asleep)
return 0;
radeon_fifo_wait(2);
OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +
var->xoffset * info->var.bits_per_pixel / 8) & ~7);
return 0;
}
static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct radeonfb_info *rinfo = info->par;
unsigned int tmp;
u32 value = 0;
int rc;
switch (cmd) {
/*
* TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
* and do something better using 2nd CRTC instead of just hackish
* routing to second output
*/
case FBIO_RADEON_SET_MIRROR:
if (!rinfo->is_mobility)
return -EINVAL;
rc = get_user(value, (__u32 __user *)arg);
if (rc)
return rc;
radeon_fifo_wait(2);
if (value & 0x01) {
tmp = INREG(LVDS_GEN_CNTL);
tmp |= (LVDS_ON | LVDS_BLON);
} else {
tmp = INREG(LVDS_GEN_CNTL);
tmp &= ~(LVDS_ON | LVDS_BLON);
}
OUTREG(LVDS_GEN_CNTL, tmp);
if (value & 0x02) {
tmp = INREG(CRTC_EXT_CNTL);
tmp |= CRTC_CRT_ON;
mirror = 1;
} else {
tmp = INREG(CRTC_EXT_CNTL);
tmp &= ~CRTC_CRT_ON;
mirror = 0;
}
OUTREG(CRTC_EXT_CNTL, tmp);
return 0;
case FBIO_RADEON_GET_MIRROR:
if (!rinfo->is_mobility)
return -EINVAL;
tmp = INREG(LVDS_GEN_CNTL);
if ((LVDS_ON | LVDS_BLON) & tmp)
value |= 0x01;
tmp = INREG(CRTC_EXT_CNTL);
if (CRTC_CRT_ON & tmp)
value |= 0x02;
return put_user(value, (__u32 __user *)arg);
default:
return -EINVAL;
}
return -EINVAL;
}
int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
{
u32 val;
u32 tmp_pix_clks;
int unblank = 0;
if (rinfo->lock_blank)
return 0;
radeon_engine_idle();
val = INREG(CRTC_EXT_CNTL);
val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
CRTC_VSYNC_DIS);
switch (blank) {
case FB_BLANK_VSYNC_SUSPEND:
val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
break;
case FB_BLANK_HSYNC_SUSPEND:
val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
break;
case FB_BLANK_POWERDOWN:
val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
CRTC_HSYNC_DIS);
break;
case FB_BLANK_NORMAL:
val |= CRTC_DISPLAY_DIS;
break;
case FB_BLANK_UNBLANK:
default:
unblank = 1;
}
OUTREG(CRTC_EXT_CNTL, val);
switch (rinfo->mon1_type) {
case MT_DFP:
if (unblank)
OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
~(FP_FPON | FP_TMDS_EN));
else {
if (mode_switch || blank == FB_BLANK_NORMAL)
break;
OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
}
break;
case MT_LCD:
del_timer_sync(&rinfo->lvds_timer);
val = INREG(LVDS_GEN_CNTL);
if (unblank) {
u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
| LVDS_EN | (rinfo->init_state.lvds_gen_cntl
& (LVDS_DIGON | LVDS_BL_MOD_EN));
if ((val ^ target_val) == LVDS_DISPLAY_DIS)
OUTREG(LVDS_GEN_CNTL, target_val);
else if ((val ^ target_val) != 0) {
OUTREG(LVDS_GEN_CNTL, target_val
& ~(LVDS_ON | LVDS_BL_MOD_EN));
rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
rinfo->init_state.lvds_gen_cntl |=
target_val & LVDS_STATE_MASK;
if (mode_switch) {
radeon_msleep(rinfo->panel_info.pwr_delay);
OUTREG(LVDS_GEN_CNTL, target_val);
}
else {
rinfo->pending_lvds_gen_cntl = target_val;
mod_timer(&rinfo->lvds_timer,
jiffies +
msecs_to_jiffies(rinfo->panel_info.pwr_delay));
}
}
} else {
val |= LVDS_DISPLAY_DIS;
OUTREG(LVDS_GEN_CNTL, val);
/* We don't do a full switch-off on a simple mode switch */
if (mode_switch || blank == FB_BLANK_NORMAL)
break;
/* Asic bug, when turning off LVDS_ON, we have to make sure
* RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
*/
tmp_pix_clks = INPLL(PIXCLKS_CNTL);
if (rinfo->is_mobility || rinfo->is_IGP)
OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
val &= ~(LVDS_BL_MOD_EN);
OUTREG(LVDS_GEN_CNTL, val);
udelay(100);
val &= ~(LVDS_ON | LVDS_EN);
OUTREG(LVDS_GEN_CNTL, val);
val &= ~LVDS_DIGON;
rinfo->pending_lvds_gen_cntl = val;
mod_timer(&rinfo->lvds_timer,
jiffies +
msecs_to_jiffies(rinfo->panel_info.pwr_delay));
rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
if (rinfo->is_mobility || rinfo->is_IGP)
OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
}
break;
case MT_CRT:
// todo: powerdown DAC
default:
break;
}
return 0;
}
static int radeonfb_blank (int blank, struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
if (rinfo->asleep)
return 0;
return radeon_screen_blank(rinfo, blank, 0);
}
static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct radeonfb_info *rinfo)
{
u32 pindex;
unsigned int i;
if (regno > 255)
return -EINVAL;
red >>= 8;
green >>= 8;
blue >>= 8;
rinfo->palette[regno].red = red;
rinfo->palette[regno].green = green;
rinfo->palette[regno].blue = blue;
/* default */
pindex = regno;
if (!rinfo->asleep) {
radeon_fifo_wait(9);
if (rinfo->bpp == 16) {
pindex = regno * 8;
if (rinfo->depth == 16 && regno > 63)
return -EINVAL;
if (rinfo->depth == 15 && regno > 31)
return -EINVAL;
/* For 565, the green component is mixed one order
* below
*/
if (rinfo->depth == 16) {
OUTREG(PALETTE_INDEX, pindex>>1);
OUTREG(PALETTE_DATA,
(rinfo->palette[regno>>1].red << 16) |
(green << 8) |
(rinfo->palette[regno>>1].blue));
green = rinfo->palette[regno<<1].green;
}
}
if (rinfo->depth != 16 || regno < 32) {
OUTREG(PALETTE_INDEX, pindex);
OUTREG(PALETTE_DATA, (red << 16) |
(green << 8) | blue);
}
}
if (regno < 16) {
u32 *pal = rinfo->info->pseudo_palette;
switch (rinfo->depth) {
case 15:
pal[regno] = (regno << 10) | (regno << 5) | regno;
break;
case 16:
pal[regno] = (regno << 11) | (regno << 5) | regno;
break;
case 24:
pal[regno] = (regno << 16) | (regno << 8) | regno;
break;
case 32:
i = (regno << 8) | regno;
pal[regno] = (i << 16) | i;
break;
}
}
return 0;
}
static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
u32 dac_cntl2, vclk_cntl = 0;
int rc;
if (!rinfo->asleep) {
if (rinfo->is_mobility) {
vclk_cntl = INPLL(VCLK_ECP_CNTL);
OUTPLL(VCLK_ECP_CNTL,
vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
}
/* Make sure we are on first palette */
if (rinfo->has_CRTC2) {
dac_cntl2 = INREG(DAC_CNTL2);
dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
OUTREG(DAC_CNTL2, dac_cntl2);
}
}
rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
if (!rinfo->asleep && rinfo->is_mobility)
OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
return rc;
}
static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
u16 *red, *green, *blue, *transp;
u32 dac_cntl2, vclk_cntl = 0;
int i, start, rc = 0;
if (!rinfo->asleep) {
if (rinfo->is_mobility) {
vclk_cntl = INPLL(VCLK_ECP_CNTL);
OUTPLL(VCLK_ECP_CNTL,
vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
}
/* Make sure we are on first palette */
if (rinfo->has_CRTC2) {
dac_cntl2 = INREG(DAC_CNTL2);
dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
OUTREG(DAC_CNTL2, dac_cntl2);
}
}
red = cmap->red;
green = cmap->green;
blue = cmap->blue;
transp = cmap->transp;
start = cmap->start;
for (i = 0; i < cmap->len; i++) {
u_int hred, hgreen, hblue, htransp = 0xffff;
hred = *red++;
hgreen = *green++;
hblue = *blue++;
if (transp)
htransp = *transp++;
rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
rinfo);
if (rc)
break;
}
if (!rinfo->asleep && rinfo->is_mobility)
OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
return rc;
}
static void radeon_save_state (struct radeonfb_info *rinfo,
struct radeon_regs *save)
{
/* CRTC regs */
save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
save->dac_cntl = INREG(DAC_CNTL);
save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
save->crtc_pitch = INREG(CRTC_PITCH);
save->surface_cntl = INREG(SURFACE_CNTL);
/* FP regs */
save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
save->fp_gen_cntl = INREG(FP_GEN_CNTL);
save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
save->tmds_crc = INREG(TMDS_CRC);
save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
/* PLL regs */
save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
radeon_pll_errata_after_index(rinfo);
save->ppll_div_3 = INPLL(PPLL_DIV_3);
save->ppll_ref_div = INPLL(PPLL_REF_DIV);
}
static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
{
int i;
radeon_fifo_wait(20);
/* Workaround from XFree */
if (rinfo->is_mobility) {
/* A temporal workaround for the occasional blanking on certain laptop
* panels. This appears to related to the PLL divider registers
* (fail to lock?). It occurs even when all dividers are the same
* with their old settings. In this case we really don't need to
* fiddle with PLL registers. By doing this we can avoid the blanking
* problem with some panels.
*/
if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
(mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
(PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
/* We still have to force a switch to selected PPLL div thanks to
* an XFree86 driver bug which will switch it away in some cases
* even when using UseFDev */
OUTREGP(CLOCK_CNTL_INDEX,
mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
~PPLL_DIV_SEL_MASK);
radeon_pll_errata_after_index(rinfo);
radeon_pll_errata_after_data(rinfo);
return;
}
}
/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
/* Reset PPLL & enable atomic update */
OUTPLLP(PPLL_CNTL,
PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
/* Switch to selected PPLL divider */
OUTREGP(CLOCK_CNTL_INDEX,
mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
~PPLL_DIV_SEL_MASK);
radeon_pll_errata_after_index(rinfo);
radeon_pll_errata_after_data(rinfo);
/* Set PPLL ref. div */
if (IS_R300_VARIANT(rinfo) ||
rinfo->family == CHIP_FAMILY_RS300 ||
rinfo->family == CHIP_FAMILY_RS400 ||
rinfo->family == CHIP_FAMILY_RS480) {
if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
/* When restoring console mode, use saved PPLL_REF_DIV
* setting.
*/
OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
} else {
/* R300 uses ref_div_acc field as real ref divider */
OUTPLLP(PPLL_REF_DIV,
(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
~R300_PPLL_REF_DIV_ACC_MASK);
}
} else
OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
/* Set PPLL divider 3 & post divider*/
OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
/* Write update */
while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
;
OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
/* Wait read update complete */
/* FIXME: Certain revisions of R300 can't recover here. Not sure of
the cause yet, but this workaround will mask the problem for now.
Other chips usually will pass at the very first test, so the
workaround shouldn't have any effect on them. */
for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
;
OUTPLL(HTOTAL_CNTL, 0);
/* Clear reset & atomic update */
OUTPLLP(PPLL_CNTL, 0,
~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
/* We may want some locking ... oh well */
radeon_msleep(5);
/* Switch back VCLK source to PPLL */
OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
}
/*
* Timer function for delayed LVDS panel power up/down
*/
static void radeon_lvds_timer_func(struct timer_list *t)
{
struct radeonfb_info *rinfo = from_timer(rinfo, t, lvds_timer);
radeon_engine_idle();
OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
}
/*
* Apply a video mode. This will apply the whole register set, including
* the PLL registers, to the card
*/
void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
int regs_only)
{
int i;
int primary_mon = PRIMARY_MONITOR(rinfo);
if (nomodeset)
return;
if (!regs_only)
radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
radeon_fifo_wait(31);
for (i=0; i<10; i++)
OUTREG(common_regs[i].reg, common_regs[i].val);
/* Apply surface registers */
for (i=0; i<8; i++) {
OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
}
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
OUTREG(CRTC_OFFSET, 0);
OUTREG(CRTC_OFFSET_CNTL, 0);
OUTREG(CRTC_PITCH, mode->crtc_pitch);
OUTREG(SURFACE_CNTL, mode->surface_cntl);
radeon_write_pll_regs(rinfo, mode);
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
radeon_fifo_wait(10);
OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
OUTREG(TMDS_CRC, mode->tmds_crc);
OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
}
if (!regs_only)
radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
radeon_fifo_wait(2);
OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
return;
}
/*
* Calculate the PLL values for a given mode
*/
static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
unsigned long freq)
{
static const struct {
int divider;
int bitvalue;
} *post_div,
post_divs[] = {
{ 1, 0 },
{ 2, 1 },
{ 4, 2 },
{ 8, 3 },
{ 3, 4 },
{ 16, 5 },
{ 6, 6 },
{ 12, 7 },
{ 0, 0 },
};
int fb_div, pll_output_freq = 0;
int uses_dvo = 0;
/* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
* not sure which model starts having FP2_GEN_CNTL, I assume anything more
* recent than an r(v)100...
*/
#if 1
/* XXX I had reports of flicker happening with the cinema display
* on TMDS1 that seem to be fixed if I also forbit odd dividers in
* this case. This could just be a bandwidth calculation issue, I
* haven't implemented the bandwidth code yet, but in the meantime,
* forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
* I haven't seen a case were were absolutely needed an odd PLL
* divider. I'll find a better fix once I have more infos on the
* real cause of the problem.
*/
while (rinfo->has_CRTC2) {
u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
u32 disp_output_cntl;
int source;
/* FP2 path not enabled */
if ((fp2_gen_cntl & FP2_ON) == 0)
break;
/* Not all chip revs have the same format for this register,
* extract the source selection
*/
if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
source = (fp2_gen_cntl >> 10) & 0x3;
/* sourced from transform unit, check for transform unit
* own source
*/
if (source == 3) {
disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
source = (disp_output_cntl >> 12) & 0x3;
}
} else
source = (fp2_gen_cntl >> 13) & 0x1;
/* sourced from CRTC2 -> exit */
if (source == 1)
break;
/* so we end up on CRTC1, let's set uses_dvo to 1 now */
uses_dvo = 1;
break;
}
#else
uses_dvo = 1;
#endif
if (freq > rinfo->pll.ppll_max)
freq = rinfo->pll.ppll_max;
if (freq*12 < rinfo->pll.ppll_min)
freq = rinfo->pll.ppll_min / 12;
pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
pll_output_freq = post_div->divider * freq;
/* If we output to the DVO port (external TMDS), we don't allow an
* odd PLL divider as those aren't supported on this path
*/
if (uses_dvo && (post_div->divider & 1))
continue;
if (pll_output_freq >= rinfo->pll.ppll_min &&
pll_output_freq <= rinfo->pll.ppll_max)
break;
}
/* If we fall through the bottom, try the "default value"
given by the terminal post_div->bitvalue */
if ( !post_div->divider ) {
post_div = &post_divs[post_div->bitvalue];
pll_output_freq = post_div->divider * freq;
}
pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
rinfo->pll.ref_div, rinfo->pll.ref_clk,
pll_output_freq);
/* If we fall through the bottom, try the "default value"
given by the terminal post_div->bitvalue */
if ( !post_div->divider ) {
post_div = &post_divs[post_div->bitvalue];
pll_output_freq = post_div->divider * freq;
}
pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
rinfo->pll.ref_div, rinfo->pll.ref_clk,
pll_output_freq);
fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
rinfo->pll.ref_clk);
regs->ppll_ref_div = rinfo->pll.ref_div;
regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
pr_debug("post div = 0x%x\n", post_div->bitvalue);
pr_debug("fb_div = 0x%x\n", fb_div);
pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
}
static int radeonfb_set_par(struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
struct fb_var_screeninfo *mode = &info->var;
struct radeon_regs *newmode;
int hTotal, vTotal, hSyncStart, hSyncEnd,
vSyncStart, vSyncEnd;
u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
int i, freq;
int format = 0;
int nopllcalc = 0;
int hsync_start, hsync_fudge, hsync_wid, vsync_wid;
int primary_mon = PRIMARY_MONITOR(rinfo);
int depth = var_to_depth(mode);
int use_rmx = 0;
newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
if (!newmode)
return -ENOMEM;
/* We always want engine to be idle on a mode switch, even
* if we won't actually change the mode
*/
radeon_engine_idle();
hSyncStart = mode->xres + mode->right_margin;
hSyncEnd = hSyncStart + mode->hsync_len;
hTotal = hSyncEnd + mode->left_margin;
vSyncStart = mode->yres + mode->lower_margin;
vSyncEnd = vSyncStart + mode->vsync_len;
vTotal = vSyncEnd + mode->upper_margin;
pixClock = mode->pixclock;
sync = mode->sync;
h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
if (rinfo->panel_info.xres < mode->xres)
mode->xres = rinfo->panel_info.xres;
if (rinfo->panel_info.yres < mode->yres)
mode->yres = rinfo->panel_info.yres;
hTotal = mode->xres + rinfo->panel_info.hblank;
hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
vTotal = mode->yres + rinfo->panel_info.vblank;
vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
h_sync_pol = !rinfo->panel_info.hAct_high;
v_sync_pol = !rinfo->panel_info.vAct_high;
pixClock = 100000000 / rinfo->panel_info.clock;
if (rinfo->panel_info.use_bios_dividers) {
nopllcalc = 1;
newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
(rinfo->panel_info.post_divider << 16);
newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
}
}
dotClock = 1000000000 / pixClock;
freq = dotClock / 10; /* x100 */
pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
hSyncStart, hSyncEnd, hTotal);
pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
vSyncStart, vSyncEnd, vTotal);
hsync_wid = (hSyncEnd - hSyncStart) / 8;
vsync_wid = vSyncEnd - vSyncStart;
if (hsync_wid == 0)
hsync_wid = 1;
else if (hsync_wid > 0x3f) /* max */
hsync_wid = 0x3f;
if (vsync_wid == 0)
vsync_wid = 1;
else if (vsync_wid > 0x1f) /* max */
vsync_wid = 0x1f;
format = radeon_get_dstbpp(depth);
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
hsync_fudge = hsync_fudge_fp[format-1];
else
hsync_fudge = hsync_adj_tab[format-1];
hsync_start = hSyncStart - 8 + hsync_fudge;
newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
(format << 8);
/* Clear auto-center etc... */
newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
newmode->crtc_more_cntl &= 0xfffffff0;
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
if (mirror)
newmode->crtc_ext_cntl |= CRTC_CRT_ON;
newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
CRTC_INTERLACE_EN);
} else {
newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
CRTC_CRT_ON;
}
newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
DAC_8BIT_EN;
newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
(((mode->xres / 8) - 1) << 16));
newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
(hsync_wid << 16) | (h_sync_pol << 23));
newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
((mode->yres - 1) << 16);
newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
(vsync_wid << 16) | (v_sync_pol << 23));
if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
/* We first calculate the engine pitch */
rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
& ~(0x3f)) >> 6;
/* Then, re-multiply it to get the CRTC pitch */
newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
} else
newmode->crtc_pitch = (mode->xres_virtual >> 3);
newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
/*
* It looks like recent chips have a problem with SURFACE_CNTL,
* setting SURF_TRANSLATION_DIS completely disables the
* swapper as well, so we leave it unset now.
*/
newmode->surface_cntl = 0;
#if defined(__BIG_ENDIAN)
/* Setup swapping on both apertures, though we currently
* only use aperture 0, enabling swapper on aperture 1
* won't harm
*/
switch (mode->bits_per_pixel) {
case 16:
newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
break;
case 24:
case 32:
newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
break;
}
#endif
/* Clear surface registers */
for (i=0; i<8; i++) {
newmode->surf_lower_bound[i] = 0;
newmode->surf_upper_bound[i] = 0x1f;
newmode->surf_info[i] = 0;
}
pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
rinfo->bpp = mode->bits_per_pixel;
rinfo->depth = depth;
pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
pr_debug("freq = %lu\n", (unsigned long)freq);
/* We use PPLL_DIV_3 */
newmode->clk_cntl_index = 0x300;
/* Calculate PPLL value if necessary */
if (!nopllcalc)
radeon_calc_pll_regs(rinfo, newmode, freq);
newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
unsigned int hRatio, vRatio;
if (mode->xres > rinfo->panel_info.xres)
mode->xres = rinfo->panel_info.xres;
if (mode->yres > rinfo->panel_info.yres)
mode->yres = rinfo->panel_info.yres;
newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
<< HORZ_PANEL_SHIFT);
newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
<< VERT_PANEL_SHIFT);
if (mode->xres != rinfo->panel_info.xres) {
hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
rinfo->panel_info.xres);
newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
(newmode->fp_horz_stretch &
(HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
HORZ_AUTO_RATIO_INC)));
newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
HORZ_STRETCH_ENABLE);
use_rmx = 1;
}
newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
if (mode->yres != rinfo->panel_info.yres) {
vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
rinfo->panel_info.yres);
newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
(newmode->fp_vert_stretch &
(VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
VERT_STRETCH_ENABLE);
use_rmx = 1;
}
newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
~(FP_SEL_CRTC2 |
FP_RMX_HVSYNC_CONTROL_EN |
FP_DFP_SYNC_SEL |
FP_CRT_SYNC_SEL |
FP_CRTC_LOCK_8DOT |
FP_USE_SHADOW_EN |
FP_CRTC_USE_SHADOW_VEND |
FP_CRT_SYNC_ALT));
newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
FP_CRTC_DONT_SHADOW_HEND |
FP_PANEL_FORMAT);
if (IS_R300_VARIANT(rinfo) ||
(rinfo->family == CHIP_FAMILY_R200)) {
newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
if (use_rmx)
newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
else
newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
} else
newmode->fp_gen_cntl |= FP_SEL_CRTC1;
newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
newmode->tmds_crc = rinfo->init_state.tmds_crc;
newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
if (primary_mon == MT_LCD) {
newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
} else {
/* DFP */
newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
/* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
if (IS_R300_VARIANT(rinfo) ||
(rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
else
newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
}
newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
(((mode->xres / 8) - 1) << 16));
newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
((mode->yres - 1) << 16);
newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
(hsync_wid << 16) | (h_sync_pol << 23));
newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
(vsync_wid << 16) | (v_sync_pol << 23));
}
/* do it! */
if (!rinfo->asleep) {
memcpy(&rinfo->state, newmode, sizeof(*newmode));
radeon_write_mode (rinfo, newmode, 0);
/* (re)initialize the engine */
if (!(info->flags & FBINFO_HWACCEL_DISABLED))
radeonfb_engine_init (rinfo);
}
/* Update fix */
if (!(info->flags & FBINFO_HWACCEL_DISABLED))
info->fix.line_length = rinfo->pitch*64;
else
info->fix.line_length = mode->xres_virtual
* ((mode->bits_per_pixel + 1) / 8);
info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
: FB_VISUAL_DIRECTCOLOR;
#ifdef CONFIG_BOOTX_TEXT
/* Update debug text engine */
btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
rinfo->depth, info->fix.line_length);
#endif
kfree(newmode);
return 0;
}
static const struct fb_ops radeonfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = radeonfb_check_var,
.fb_set_par = radeonfb_set_par,
.fb_setcolreg = radeonfb_setcolreg,
.fb_setcmap = radeonfb_setcmap,
.fb_pan_display = radeonfb_pan_display,
.fb_blank = radeonfb_blank,
.fb_ioctl = radeonfb_ioctl,
.fb_sync = radeonfb_sync,
.fb_fillrect = radeonfb_fillrect,
.fb_copyarea = radeonfb_copyarea,
.fb_imageblit = radeonfb_imageblit,
};
static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
{
struct fb_info *info = rinfo->info;
info->par = rinfo;
info->pseudo_palette = rinfo->pseudo_palette;
info->flags = FBINFO_HWACCEL_COPYAREA
| FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_XPAN
| FBINFO_HWACCEL_YPAN;
info->fbops = &radeonfb_ops;
info->screen_base = rinfo->fb_base;
info->screen_size = rinfo->mapped_vram;
/* Fill fix common fields */
strscpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
info->fix.smem_start = rinfo->fb_base_phys;
info->fix.smem_len = rinfo->video_ram;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
info->fix.xpanstep = 8;
info->fix.ypanstep = 1;
info->fix.ywrapstep = 0;
info->fix.type_aux = 0;
info->fix.mmio_start = rinfo->mmio_base_phys;
info->fix.mmio_len = RADEON_REGSIZE;
info->fix.accel = FB_ACCEL_ATI_RADEON;
fb_alloc_cmap(&info->cmap, 256, 0);
if (noaccel)
info->flags |= FBINFO_HWACCEL_DISABLED;
return 0;
}
/*
* This reconfigure the card's internal memory map. In theory, we'd like
* to setup the card's memory at the same address as it's PCI bus address,
* and the AGP aperture right after that so that system RAM on 32 bits
* machines at least, is directly accessible. However, doing so would
* conflict with the current XFree drivers...
* Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
* on the proper way to set this up and duplicate this here. In the meantime,
* I put the card's memory at 0 in card space and AGP at some random high
* local (0xe0000000 for now) that will be changed by XFree/DRI anyway
*/
#ifdef CONFIG_PPC
#undef SET_MC_FB_FROM_APERTURE
static void fixup_memory_mappings(struct radeonfb_info *rinfo)
{
u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
u32 save_crtc_ext_cntl;
u32 aper_base, aper_size;
u32 agp_base;
/* First, we disable display to avoid interfering */
if (rinfo->has_CRTC2) {
save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
}
save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
mdelay(100);
aper_base = INREG(CNFG_APER_0_BASE);
aper_size = INREG(CNFG_APER_SIZE);
#ifdef SET_MC_FB_FROM_APERTURE
/* Set framebuffer to be at the same address as set in PCI BAR */
OUTREG(MC_FB_LOCATION,
((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
rinfo->fb_local_base = aper_base;
#else
OUTREG(MC_FB_LOCATION, 0x7fff0000);
rinfo->fb_local_base = 0;
#endif
agp_base = aper_base + aper_size;
if (agp_base & 0xf0000000)
agp_base = (aper_base | 0x0fffffff) + 1;
/* Set AGP to be just after the framebuffer on a 256Mb boundary. This
* assumes the FB isn't mapped to 0xf0000000 or above, but this is
* always the case on PPCs afaik.
*/
#ifdef SET_MC_FB_FROM_APERTURE
OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
#else
OUTREG(MC_AGP_LOCATION, 0xffffe000);
#endif
/* Fixup the display base addresses & engine offsets while we
* are at it as well
*/
#ifdef SET_MC_FB_FROM_APERTURE
OUTREG(DISPLAY_BASE_ADDR, aper_base);
if (rinfo->has_CRTC2)
OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
OUTREG(OV0_BASE_ADDR, aper_base);
#else
OUTREG(DISPLAY_BASE_ADDR, 0);
if (rinfo->has_CRTC2)
OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
OUTREG(OV0_BASE_ADDR, 0);
#endif
mdelay(100);
/* Restore display settings */
OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
if (rinfo->has_CRTC2)
OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
aper_base,
((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
0xffff0000 | (agp_base >> 16));
}
#endif /* CONFIG_PPC */
static void radeon_identify_vram(struct radeonfb_info *rinfo)
{
u32 tmp;
/* framebuffer size */
if ((rinfo->family == CHIP_FAMILY_RS100) ||
(rinfo->family == CHIP_FAMILY_RS200) ||
(rinfo->family == CHIP_FAMILY_RS300) ||
(rinfo->family == CHIP_FAMILY_RC410) ||
(rinfo->family == CHIP_FAMILY_RS400) ||
(rinfo->family == CHIP_FAMILY_RS480) ) {
u32 tom = INREG(NB_TOM);
tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
radeon_fifo_wait(6);
OUTREG(MC_FB_LOCATION, tom);
OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
/* This is supposed to fix the crtc2 noise problem. */
OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
if ((rinfo->family == CHIP_FAMILY_RS100) ||
(rinfo->family == CHIP_FAMILY_RS200)) {
/* This is to workaround the asic bug for RMX, some versions
* of BIOS doesn't have this register initialized correctly.
*/
OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
~CRTC_H_CUTOFF_ACTIVE_EN);
}
} else {
tmp = INREG(CNFG_MEMSIZE);
}
/* mem size is bits [28:0], mask off the rest */
rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
/*
* Hack to get around some busted production M6's
* reporting no ram
*/
if (rinfo->video_ram == 0) {
switch (rinfo->pdev->device) {
case PCI_CHIP_RADEON_LY:
case PCI_CHIP_RADEON_LZ:
rinfo->video_ram = 8192 * 1024;
break;
default:
break;
}
}
/*
* Now try to identify VRAM type
*/
if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
(INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
rinfo->vram_ddr = 1;
else
rinfo->vram_ddr = 0;
tmp = INREG(MEM_CNTL);
if (IS_R300_VARIANT(rinfo)) {
tmp &= R300_MEM_NUM_CHANNELS_MASK;
switch (tmp) {
case 0: rinfo->vram_width = 64; break;
case 1: rinfo->vram_width = 128; break;
case 2: rinfo->vram_width = 256; break;
default: rinfo->vram_width = 128; break;
}
} else if ((rinfo->family == CHIP_FAMILY_RV100) ||
(rinfo->family == CHIP_FAMILY_RS100) ||
(rinfo->family == CHIP_FAMILY_RS200)){
if (tmp & RV100_MEM_HALF_MODE)
rinfo->vram_width = 32;
else
rinfo->vram_width = 64;
} else {
if (tmp & MEM_NUM_CHANNELS_MASK)
rinfo->vram_width = 128;
else
rinfo->vram_width = 64;
}
/* This may not be correct, as some cards can have half of channel disabled
* ToDo: identify these cases
*/
pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
pci_name(rinfo->pdev),
rinfo->video_ram / 1024,
rinfo->vram_ddr ? "DDR" : "SDRAM",
rinfo->vram_width);
}
/*
* Sysfs
*/
static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
{
return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH);
}
static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
struct device *dev = kobj_to_dev(kobj);
struct fb_info *info = dev_get_drvdata(dev);
struct radeonfb_info *rinfo = info->par;
return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
}
static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
struct device *dev = kobj_to_dev(kobj);
struct fb_info *info = dev_get_drvdata(dev);
struct radeonfb_info *rinfo = info->par;
return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
}
static const struct bin_attribute edid1_attr = {
.attr = {
.name = "edid1",
.mode = 0444,
},
.size = EDID_LENGTH,
.read = radeon_show_edid1,
};
static const struct bin_attribute edid2_attr = {
.attr = {
.name = "edid2",
.mode = 0444,
},
.size = EDID_LENGTH,
.read = radeon_show_edid2,
};
static int radeonfb_pci_register(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct fb_info *info;
struct radeonfb_info *rinfo;
int ret;
unsigned char c1, c2;
int err = 0;
pr_debug("radeonfb_pci_register BEGIN\n");
/* Enable device in PCI config */
ret = pci_enable_device(pdev);
if (ret < 0) {
printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
pci_name(pdev));
goto err_out;
}
info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
if (!info) {
ret = -ENOMEM;
goto err_disable;
}
rinfo = info->par;
rinfo->info = info;
rinfo->pdev = pdev;
spin_lock_init(&rinfo->reg_lock);
timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0);
c1 = ent->device >> 8;
c2 = ent->device & 0xff;
if (isprint(c1) && isprint(c2))
snprintf(rinfo->name, sizeof(rinfo->name),
"ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
else
snprintf(rinfo->name, sizeof(rinfo->name),
"ATI Radeon %x", ent->device & 0xffff);
rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
rinfo->chipset = pdev->device;
rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
/* Set base addrs */
rinfo->fb_base_phys = pci_resource_start (pdev, 0);
rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
ret = aperture_remove_conflicting_pci_devices(pdev, KBUILD_MODNAME);
if (ret)
goto err_release_fb;
/* request the mem regions */
ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
if (ret < 0) {
printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
pci_name(rinfo->pdev));
goto err_release_fb;
}
ret = pci_request_region(pdev, 2, "radeonfb mmio");
if (ret < 0) {
printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
pci_name(rinfo->pdev));
goto err_release_pci0;
}
/* map the regions */
rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
if (!rinfo->mmio_base) {
printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
pci_name(rinfo->pdev));
ret = -EIO;
goto err_release_pci2;
}
rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
/*
* Check for errata
*/
rinfo->errata = 0;
if (rinfo->family == CHIP_FAMILY_R300 &&
(INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK)
== CFG_ATI_REV_A11)
rinfo->errata |= CHIP_ERRATA_R300_CG;
if (rinfo->family == CHIP_FAMILY_RV200 ||
rinfo->family == CHIP_FAMILY_RS200)
rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
if (rinfo->family == CHIP_FAMILY_RV100 ||
rinfo->family == CHIP_FAMILY_RS100 ||
rinfo->family == CHIP_FAMILY_RS200)
rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
#if defined(CONFIG_PPC) || defined(CONFIG_SPARC)
/* On PPC, we obtain the OF device-node pointer to the firmware
* data for this chip
*/
rinfo->of_node = pci_device_to_OF_node(pdev);
if (rinfo->of_node == NULL)
printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
pci_name(rinfo->pdev));
#endif /* CONFIG_PPC || CONFIG_SPARC */
#ifdef CONFIG_PPC
/* On PPC, the firmware sets up a memory mapping that tends
* to cause lockups when enabling the engine. We reconfigure
* the card internal memory mappings properly
*/
fixup_memory_mappings(rinfo);
#endif /* CONFIG_PPC */
/* Get VRAM size and type */
radeon_identify_vram(rinfo);
rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
do {
rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys,
rinfo->mapped_vram);
} while (rinfo->fb_base == NULL &&
((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
if (rinfo->fb_base == NULL) {
printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
pci_name(rinfo->pdev));
ret = -EIO;
goto err_unmap_rom;
}
pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
rinfo->mapped_vram/1024);
/*
* Map the BIOS ROM if any and retrieve PLL parameters from
* the BIOS. We skip that on mobility chips as the real panel
* values we need aren't in the ROM but in the BIOS image in
* memory. This is definitely not the best meacnism though,
* we really need the arch code to tell us which is the "primary"
* video adapter to use the memory image (or better, the arch
* should provide us a copy of the BIOS image to shield us from
* archs who would store that elsewhere and/or could initialize
* more than one adapter during boot).
*/
if (!rinfo->is_mobility)
radeon_map_ROM(rinfo, pdev);
/*
* On x86, the primary display on laptop may have it's BIOS
* ROM elsewhere, try to locate it at the legacy memory hole.
* We probably need to make sure this is the primary display,
* but that is difficult without some arch support.
*/
#ifdef CONFIG_X86
if (rinfo->bios_seg == NULL)
radeon_find_mem_vbios(rinfo);
#endif
/* If both above failed, try the BIOS ROM again for mobility
* chips
*/
if (rinfo->bios_seg == NULL && rinfo->is_mobility)
radeon_map_ROM(rinfo, pdev);
/* Get informations about the board's PLL */
radeon_get_pllinfo(rinfo);
#ifdef CONFIG_FB_RADEON_I2C
/* Register I2C bus */
radeon_create_i2c_busses(rinfo);
#endif
/* set all the vital stuff */
radeon_set_fbinfo (rinfo);
/* Probe screen types */
radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
/* Build mode list, check out panel native model */
radeon_check_modes(rinfo, mode_option);
/* Register some sysfs stuff (should be done better) */
if (rinfo->mon1_EDID)
err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
&edid1_attr);
if (rinfo->mon2_EDID)
err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
&edid2_attr);
if (err)
pr_warn("%s() Creating sysfs files failed, continuing\n",
__func__);
/* save current mode regs before we switch into the new one
* so we can restore this upon __exit
*/
radeon_save_state (rinfo, &rinfo->init_state);
memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
/* Setup Power Management capabilities */
if (default_dynclk < -1) {
/* -2 is special: means ON on mobility chips and do not
* change on others
*/
radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
} else
radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
pci_set_drvdata(pdev, info);
/* Register with fbdev layer */
ret = register_framebuffer(info);
if (ret < 0) {
printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
pci_name(rinfo->pdev));
goto err_unmap_fb;
}
if (!nomtrr)
rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys,
rinfo->video_ram);
if (backlight)
radeonfb_bl_init(rinfo);
printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
if (rinfo->bios_seg)
radeon_unmap_ROM(rinfo, pdev);
pr_debug("radeonfb_pci_register END\n");
return 0;
err_unmap_fb:
iounmap(rinfo->fb_base);
err_unmap_rom:
kfree(rinfo->mon1_EDID);
kfree(rinfo->mon2_EDID);
if (rinfo->mon1_modedb)
fb_destroy_modedb(rinfo->mon1_modedb);
fb_dealloc_cmap(&info->cmap);
#ifdef CONFIG_FB_RADEON_I2C
radeon_delete_i2c_busses(rinfo);
#endif
if (rinfo->bios_seg)
radeon_unmap_ROM(rinfo, pdev);
iounmap(rinfo->mmio_base);
err_release_pci2:
pci_release_region(pdev, 2);
err_release_pci0:
pci_release_region(pdev, 0);
err_release_fb:
framebuffer_release(info);
err_disable:
err_out:
return ret;
}
static void radeonfb_pci_unregister(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct radeonfb_info *rinfo = info->par;
if (!rinfo)
return;
radeonfb_pm_exit(rinfo);
if (rinfo->mon1_EDID)
sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
if (rinfo->mon2_EDID)
sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
del_timer_sync(&rinfo->lvds_timer);
arch_phys_wc_del(rinfo->wc_cookie);
radeonfb_bl_exit(rinfo);
unregister_framebuffer(info);
iounmap(rinfo->mmio_base);
iounmap(rinfo->fb_base);
pci_release_region(pdev, 2);
pci_release_region(pdev, 0);
kfree(rinfo->mon1_EDID);
kfree(rinfo->mon2_EDID);
if (rinfo->mon1_modedb)
fb_destroy_modedb(rinfo->mon1_modedb);
#ifdef CONFIG_FB_RADEON_I2C
radeon_delete_i2c_busses(rinfo);
#endif
fb_dealloc_cmap(&info->cmap);
framebuffer_release(info);
}
#ifdef CONFIG_PM
#define RADEONFB_PCI_PM_OPS (&radeonfb_pci_pm_ops)
#else
#define RADEONFB_PCI_PM_OPS NULL
#endif
static struct pci_driver radeonfb_driver = {
.name = "radeonfb",
.id_table = radeonfb_pci_table,
.probe = radeonfb_pci_register,
.remove = radeonfb_pci_unregister,
.driver.pm = RADEONFB_PCI_PM_OPS,
};
#ifndef MODULE
static int __init radeonfb_setup (char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep (&options, ",")) != NULL) {
if (!*this_opt)
continue;
if (!strncmp(this_opt, "noaccel", 7)) {
noaccel = 1;
} else if (!strncmp(this_opt, "mirror", 6)) {
mirror = 1;
} else if (!strncmp(this_opt, "force_dfp", 9)) {
force_dfp = 1;
} else if (!strncmp(this_opt, "panel_yres:", 11)) {
panel_yres = simple_strtoul((this_opt+11), NULL, 0);
} else if (!strncmp(this_opt, "backlight:", 10)) {
backlight = simple_strtoul(this_opt+10, NULL, 0);
} else if (!strncmp(this_opt, "nomtrr", 6)) {
nomtrr = 1;
} else if (!strncmp(this_opt, "nomodeset", 9)) {
nomodeset = 1;
} else if (!strncmp(this_opt, "force_measure_pll", 17)) {
force_measure_pll = 1;
} else if (!strncmp(this_opt, "ignore_edid", 11)) {
ignore_edid = 1;
#if defined(CONFIG_PM) && defined(CONFIG_X86)
} else if (!strncmp(this_opt, "force_sleep", 11)) {
force_sleep = 1;
} else if (!strncmp(this_opt, "ignore_devlist", 14)) {
ignore_devlist = 1;
#endif
} else
mode_option = this_opt;
}
return 0;
}
#endif /* MODULE */
static int __init radeonfb_init (void)
{
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("radeonfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("radeonfb", &option))
return -ENODEV;
radeonfb_setup(option);
#endif
return pci_register_driver (&radeonfb_driver);
}
static void __exit radeonfb_exit (void)
{
pci_unregister_driver (&radeonfb_driver);
}
module_init(radeonfb_init);
module_exit(radeonfb_exit);
MODULE_AUTHOR("Ani Joshi");
MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
MODULE_LICENSE("GPL");
module_param(noaccel, bool, 0);
module_param(default_dynclk, int, 0);
MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
module_param(nomodeset, bool, 0);
MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
module_param(mirror, bool, 0);
MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
module_param(force_dfp, bool, 0);
MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
module_param(ignore_edid, bool, 0);
MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
module_param(monitor_layout, charp, 0);
MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
module_param(force_measure_pll, bool, 0);
MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
module_param(nomtrr, bool, 0);
MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
module_param(panel_yres, int, 0);
MODULE_PARM_DESC(panel_yres, "int: set panel yres");
module_param(mode_option, charp, 0);
MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
#if defined(CONFIG_PM) && defined(CONFIG_X86)
module_param(force_sleep, bool, 0);
MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
module_param(ignore_devlist, bool, 0);
MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
#endif
| linux-master | drivers/video/fbdev/aty/radeon_base.c |
/*
* ATI Frame Buffer Device Driver Core
*
* Copyright (C) 2004 Alex Kern <[email protected]>
* Copyright (C) 1997-2001 Geert Uytterhoeven
* Copyright (C) 1998 Bernd Harries
* Copyright (C) 1998 Eddie C. Dost ([email protected])
*
* This driver supports the following ATI graphics chips:
* - ATI Mach64
*
* To do: add support for
* - ATI Rage128 (from aty128fb.c)
* - ATI Radeon (from radeonfb.c)
*
* This driver is partly based on the PowerMac console driver:
*
* Copyright (C) 1996 Paul Mackerras
*
* and on the PowerMac ATI/mach64 display driver:
*
* Copyright (C) 1997 Michael AK Tesch
*
* with work by Jon Howell
* Harry AC Eaton
* Anthony Tong <[email protected]>
*
* Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
* Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Many thanks to Nitya from ATI devrel for support and patience !
*/
/******************************************************************************
TODO:
- cursor support on all cards and all ramdacs.
- cursor parameters controlable via ioctl()s.
- guess PLL and MCLK based on the original PLL register values initialized
by Open Firmware (if they are initialized). BIOS is done
(Anyone with Mac to help with this?)
******************************************************************************/
#include <linux/aperture.h>
#include <linux/compat.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/compiler.h>
#include <linux/console.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/backlight.h>
#include <linux/reboot.h>
#include <linux/dmi.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <video/mach64.h>
#include "atyfb.h"
#include "ati_ids.h"
#ifdef __powerpc__
#include <asm/machdep.h>
#include "../macmodes.h"
#endif
#ifdef __sparc__
#include <asm/fbio.h>
#include <asm/oplib.h>
#include <asm/prom.h>
#endif
#ifdef CONFIG_ADB_PMU
#include <linux/adb.h>
#include <linux/pmu.h>
#endif
#ifdef CONFIG_BOOTX_TEXT
#include <asm/btext.h>
#endif
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
/*
* Debug flags.
*/
#undef DEBUG
/*#define DEBUG*/
/* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
/* - must be large enough to catch all GUI-Regs */
/* - must be aligned to a PAGE boundary */
#define GUI_RESERVE (1 * PAGE_SIZE)
/* FIXME: remove the FAIL definition */
#define FAIL(msg) do { \
if (!(var->activate & FB_ACTIVATE_TEST)) \
printk(KERN_CRIT "atyfb: " msg "\n"); \
return -EINVAL; \
} while (0)
#define FAIL_MAX(msg, x, _max_) do { \
if (x > _max_) { \
if (!(var->activate & FB_ACTIVATE_TEST)) \
printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
return -EINVAL; \
} \
} while (0)
#ifdef DEBUG
#define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
#else
#define DPRINTK(fmt, args...) no_printk(fmt, ##args)
#endif
#define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
#define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
#if defined(CONFIG_PMAC_BACKLIGHT) || defined(CONFIG_FB_ATY_GENERIC_LCD) || \
defined(CONFIG_FB_ATY_BACKLIGHT) || defined (CONFIG_PPC_PMAC)
static const u32 lt_lcd_regs[] = {
CNFG_PANEL_LG,
LCD_GEN_CNTL_LG,
DSTN_CONTROL_LG,
HFB_PITCH_ADDR_LG,
HORZ_STRETCHING_LG,
VERT_STRETCHING_LG,
0, /* EXT_VERT_STRETCH */
LT_GIO_LG,
POWER_MANAGEMENT_LG
};
void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
{
if (M64_HAS(LT_LCD_REGS)) {
aty_st_le32(lt_lcd_regs[index], val, par);
} else {
unsigned long temp;
/* write addr byte */
temp = aty_ld_le32(LCD_INDEX, par);
aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
/* write the register value */
aty_st_le32(LCD_DATA, val, par);
}
}
u32 aty_ld_lcd(int index, const struct atyfb_par *par)
{
if (M64_HAS(LT_LCD_REGS)) {
return aty_ld_le32(lt_lcd_regs[index], par);
} else {
unsigned long temp;
/* write addr byte */
temp = aty_ld_le32(LCD_INDEX, par);
aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
/* read the register value */
return aty_ld_le32(LCD_DATA, par);
}
}
#else /* defined(CONFIG_PMAC_BACKLIGHT) || defined(CONFIG_FB_ATY_BACKLIGHT) ||
defined(CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_PPC_PMAC) */
void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
{ }
u32 aty_ld_lcd(int index, const struct atyfb_par *par)
{
return 0;
}
#endif /* defined(CONFIG_PMAC_BACKLIGHT) || defined(CONFIG_FB_ATY_BACKLIGHT) ||
defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_PPC_PMAC) */
#ifdef CONFIG_FB_ATY_GENERIC_LCD
/*
* ATIReduceRatio --
*
* Reduce a fraction by factoring out the largest common divider of the
* fraction's numerator and denominator.
*/
static void ATIReduceRatio(int *Numerator, int *Denominator)
{
int Multiplier, Divider, Remainder;
Multiplier = *Numerator;
Divider = *Denominator;
while ((Remainder = Multiplier % Divider)) {
Multiplier = Divider;
Divider = Remainder;
}
*Numerator /= Divider;
*Denominator /= Divider;
}
#endif
/*
* The Hardware parameters for each card
*/
struct pci_mmap_map {
unsigned long voff;
unsigned long poff;
unsigned long size;
unsigned long prot_flag;
unsigned long prot_mask;
};
static const struct fb_fix_screeninfo atyfb_fix = {
.id = "ATY Mach64",
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 8,
.ypanstep = 1,
};
/*
* Frame buffer device API
*/
static int atyfb_open(struct fb_info *info, int user);
static int atyfb_release(struct fb_info *info, int user);
static int atyfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info);
static int atyfb_set_par(struct fb_info *info);
static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info);
static int atyfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info);
static int atyfb_blank(int blank, struct fb_info *info);
static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
#ifdef CONFIG_COMPAT
static int atyfb_compat_ioctl(struct fb_info *info, u_int cmd, u_long arg)
{
return atyfb_ioctl(info, cmd, (u_long)compat_ptr(arg));
}
#endif
#ifdef __sparc__
static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
#endif
static int atyfb_sync(struct fb_info *info);
/*
* Internal routines
*/
static int aty_init(struct fb_info *info);
static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
static int aty_var_to_crtc(const struct fb_info *info,
const struct fb_var_screeninfo *var,
struct crtc *crtc);
static int aty_crtc_to_var(const struct crtc *crtc,
struct fb_var_screeninfo *var);
static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
#ifdef CONFIG_PPC
static int read_aty_sense(const struct atyfb_par *par);
#endif
static DEFINE_MUTEX(reboot_lock);
static struct fb_info *reboot_info;
/*
* Interface used by the world
*/
static struct fb_var_screeninfo default_var = {
/* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
640, 480, 640, 480, 0, 0, 8, 0,
{0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED
};
static const struct fb_videomode defmode = {
/* 640x480 @ 60 Hz, 31.5 kHz hsync */
NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
0, FB_VMODE_NONINTERLACED
};
static struct fb_ops atyfb_ops = {
.owner = THIS_MODULE,
.fb_open = atyfb_open,
.fb_release = atyfb_release,
.fb_check_var = atyfb_check_var,
.fb_set_par = atyfb_set_par,
.fb_setcolreg = atyfb_setcolreg,
.fb_pan_display = atyfb_pan_display,
.fb_blank = atyfb_blank,
.fb_ioctl = atyfb_ioctl,
#ifdef CONFIG_COMPAT
.fb_compat_ioctl = atyfb_compat_ioctl,
#endif
.fb_fillrect = atyfb_fillrect,
.fb_copyarea = atyfb_copyarea,
.fb_imageblit = atyfb_imageblit,
#ifdef __sparc__
.fb_mmap = atyfb_mmap,
#endif
.fb_sync = atyfb_sync,
};
static bool noaccel;
static bool nomtrr;
static int vram;
static int pll;
static int mclk;
static int xclk;
static int comp_sync = -1;
static char *mode;
static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
#ifdef CONFIG_PPC
static int default_vmode = VMODE_CHOOSE;
static int default_cmode = CMODE_CHOOSE;
module_param_named(vmode, default_vmode, int, 0);
MODULE_PARM_DESC(vmode, "int: video mode for mac");
module_param_named(cmode, default_cmode, int, 0);
MODULE_PARM_DESC(cmode, "int: color mode for mac");
#endif
#ifdef CONFIG_ATARI
static unsigned int mach64_count = 0;
static unsigned long phys_vmembase[FB_MAX] = { 0, };
static unsigned long phys_size[FB_MAX] = { 0, };
static unsigned long phys_guiregbase[FB_MAX] = { 0, };
#endif
/* top -> down is an evolution of mach64 chipset, any corrections? */
#define ATI_CHIP_88800GX (M64F_GX)
#define ATI_CHIP_88800CX (M64F_GX)
#define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
#define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
#define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
#define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
#define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
#define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
#define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
/* FIXME what is this chip? */
#define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
/* make sets shorter */
#define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
#define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
/*#define ATI_CHIP_264GTDVD ?*/
#define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
#define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
#define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
#define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
#define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_XL_MEM)
#define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_XL_MEM | M64F_MOBIL_BUS)
static struct {
u16 pci_id;
const char *name;
int pll, mclk, xclk, ecp_max;
u32 features;
} aty_chips[] = {
#ifdef CONFIG_FB_ATY_GX
/* Mach64 GX */
{ PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
{ PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
#endif /* CONFIG_FB_ATY_GX */
#ifdef CONFIG_FB_ATY_CT
{ PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
{ PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
/* FIXME what is this chip? */
{ PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
{ PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
{ PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
{ PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
{ PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
{ PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
{ PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
{ PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
{ PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
{ PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
{ PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
{ PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
{ PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
{ PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
{ PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
{ PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
{ PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
{ PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
{ PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
{ PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
{ PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
{ PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
{ PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
{ PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
{ PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
{ PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
{ PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
{ PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
{ PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
{ PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
{ PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
#endif /* CONFIG_FB_ATY_CT */
};
/*
* Last page of 8 MB (4 MB on ISA) aperture is MMIO,
* unless the auxiliary register aperture is used.
*/
static void aty_fudge_framebuffer_len(struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
if (!par->aux_start &&
(info->fix.smem_len == 0x800000 ||
(par->bus_type == ISA && info->fix.smem_len == 0x400000)))
info->fix.smem_len -= GUI_RESERVE;
}
static int correct_chipset(struct atyfb_par *par)
{
u8 rev;
u16 type;
u32 chip_id;
const char *name;
int i;
for (i = (int)ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
if (par->pci_id == aty_chips[i].pci_id)
break;
if (i < 0)
return -ENODEV;
name = aty_chips[i].name;
par->pll_limits.pll_max = aty_chips[i].pll;
par->pll_limits.mclk = aty_chips[i].mclk;
par->pll_limits.xclk = aty_chips[i].xclk;
par->pll_limits.ecp_max = aty_chips[i].ecp_max;
par->features = aty_chips[i].features;
chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
type = chip_id & CFG_CHIP_TYPE;
rev = (chip_id & CFG_CHIP_REV) >> 24;
switch (par->pci_id) {
#ifdef CONFIG_FB_ATY_GX
case PCI_CHIP_MACH64GX:
if (type != 0x00d7)
return -ENODEV;
break;
case PCI_CHIP_MACH64CX:
if (type != 0x0057)
return -ENODEV;
break;
#endif
#ifdef CONFIG_FB_ATY_CT
case PCI_CHIP_MACH64VT:
switch (rev & 0x07) {
case 0x00:
switch (rev & 0xc0) {
case 0x00:
name = "ATI264VT (A3) (Mach64 VT)";
par->pll_limits.pll_max = 170;
par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264VT;
break;
case 0x40:
name = "ATI264VT2 (A4) (Mach64 VT)";
par->pll_limits.pll_max = 200;
par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
break;
}
break;
case 0x01:
name = "ATI264VT3 (B1) (Mach64 VT)";
par->pll_limits.pll_max = 200;
par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264VTB;
break;
case 0x02:
name = "ATI264VT3 (B2) (Mach64 VT)";
par->pll_limits.pll_max = 200;
par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264VT3;
break;
}
break;
case PCI_CHIP_MACH64GT:
switch (rev & 0x07) {
case 0x01:
name = "3D RAGE II (Mach64 GT)";
par->pll_limits.pll_max = 170;
par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264GTB;
break;
case 0x02:
name = "3D RAGE II+ (Mach64 GT)";
par->pll_limits.pll_max = 200;
par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 100;
par->features = ATI_CHIP_264GTB;
break;
}
break;
#endif
}
PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
return 0;
}
static char ram_dram[] __maybe_unused = "DRAM";
static char ram_resv[] __maybe_unused = "RESV";
#ifdef CONFIG_FB_ATY_GX
static char ram_vram[] = "VRAM";
#endif /* CONFIG_FB_ATY_GX */
#ifdef CONFIG_FB_ATY_CT
static char ram_edo[] = "EDO";
static char ram_sdram[] = "SDRAM (1:1)";
static char ram_sgram[] = "SGRAM (1:1)";
static char ram_sdram32[] = "SDRAM (2:1) (32-bit)";
static char ram_wram[] = "WRAM";
static char ram_off[] = "OFF";
#endif /* CONFIG_FB_ATY_CT */
#ifdef CONFIG_FB_ATY_GX
static char *aty_gx_ram[8] = {
ram_dram, ram_vram, ram_vram, ram_dram,
ram_dram, ram_vram, ram_vram, ram_resv
};
#endif /* CONFIG_FB_ATY_GX */
#ifdef CONFIG_FB_ATY_CT
static char *aty_ct_ram[8] = {
ram_off, ram_dram, ram_edo, ram_edo,
ram_sdram, ram_sgram, ram_wram, ram_resv
};
static char *aty_xl_ram[8] = {
ram_off, ram_dram, ram_edo, ram_edo,
ram_sdram, ram_sgram, ram_sdram32, ram_resv
};
#endif /* CONFIG_FB_ATY_CT */
static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var,
struct atyfb_par *par)
{
u32 pixclock = var->pixclock;
#ifdef CONFIG_FB_ATY_GENERIC_LCD
u32 lcd_on_off;
par->pll.ct.xres = 0;
if (par->lcd_table != 0) {
lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
if (lcd_on_off & LCD_ON) {
par->pll.ct.xres = var->xres;
pixclock = par->lcd_pixclock;
}
}
#endif
return pixclock;
}
#if defined(CONFIG_PPC)
/*
* Apple monitor sense
*/
static int read_aty_sense(const struct atyfb_par *par)
{
int sense, i;
aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
__delay(200);
aty_st_le32(GP_IO, 0, par); /* turn off outputs */
__delay(2000);
i = aty_ld_le32(GP_IO, par); /* get primary sense value */
sense = ((i & 0x3000) >> 3) | (i & 0x100);
/* drive each sense line low in turn and collect the other 2 */
aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
__delay(2000);
i = aty_ld_le32(GP_IO, par);
sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
__delay(200);
aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
__delay(2000);
i = aty_ld_le32(GP_IO, par);
sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
__delay(200);
aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
__delay(2000);
sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
aty_st_le32(GP_IO, 0, par); /* turn off outputs */
return sense;
}
#endif /* defined(CONFIG_PPC) */
/* ------------------------------------------------------------------------- */
/*
* CRTC programming
*/
static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
{
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table != 0) {
if (!M64_HAS(LT_LCD_REGS)) {
crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
}
crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par);
crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
/* switch to non shadow registers */
aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
/* save stretching */
crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
if (!M64_HAS(LT_LCD_REGS))
crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
}
#endif
crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table != 0) {
/* switch to shadow registers */
aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
SHADOW_EN | SHADOW_RW_EN, par);
crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
}
#endif /* CONFIG_FB_ATY_GENERIC_LCD */
}
static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
{
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table != 0) {
/* stop CRTC */
aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl &
~(CRTC_EXT_DISP_EN | CRTC_EN), par);
/* update non-shadow registers first */
aty_st_lcd(CNFG_PANEL, crtc->lcd_config_panel, par);
aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
/* temporarily disable stretching */
aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching &
~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching &
~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
}
#endif
/* turn off CRT */
aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
DPRINTK("setting up CRTC\n");
DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
((((crtc->h_tot_disp >> 16) & 0xff) + 1) << 3),
(((crtc->v_tot_disp >> 16) & 0x7ff) + 1),
(crtc->h_sync_strt_wid & 0x200000) ? 'N' : 'P',
(crtc->v_sync_strt_wid & 0x200000) ? 'N' : 'P',
(crtc->gen_cntl & CRTC_CSYNC_EN) ? 'P' : 'N');
DPRINTK("CRTC_H_TOTAL_DISP: %x\n", crtc->h_tot_disp);
DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n", crtc->h_sync_strt_wid);
DPRINTK("CRTC_V_TOTAL_DISP: %x\n", crtc->v_tot_disp);
DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n", crtc->v_sync_strt_wid);
DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
DPRINTK("CRTC_GEN_CNTL: %x\n", crtc->gen_cntl);
aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
#if 0
FIXME
if (par->accel_flags & FB_ACCELF_TEXT)
aty_init_engine(par, info);
#endif
#ifdef CONFIG_FB_ATY_GENERIC_LCD
/* after setting the CRTC registers we should set the LCD registers. */
if (par->lcd_table != 0) {
/* switch to shadow registers */
aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
SHADOW_EN | SHADOW_RW_EN, par);
DPRINTK("set shadow CRT to %ix%i %c%c\n",
((((crtc->shadow_h_tot_disp >> 16) & 0xff) + 1) << 3),
(((crtc->shadow_v_tot_disp >> 16) & 0x7ff) + 1),
(crtc->shadow_h_sync_strt_wid & 0x200000) ? 'N' : 'P',
(crtc->shadow_v_sync_strt_wid & 0x200000) ? 'N' : 'P');
DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n",
crtc->shadow_h_tot_disp);
DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n",
crtc->shadow_h_sync_strt_wid);
DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n",
crtc->shadow_v_tot_disp);
DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n",
crtc->shadow_v_sync_strt_wid);
aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
/* restore CRTC selection & shadow state and enable stretching */
DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
if (!M64_HAS(LT_LCD_REGS))
DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
if (!M64_HAS(LT_LCD_REGS)) {
aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
aty_ld_le32(LCD_INDEX, par);
aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
}
}
#endif /* CONFIG_FB_ATY_GENERIC_LCD */
}
static u32 calc_line_length(struct atyfb_par *par, u32 vxres, u32 bpp)
{
u32 line_length = vxres * bpp / 8;
if (par->ram_type == SGRAM ||
(!M64_HAS(XL_MEM) && par->ram_type == WRAM))
line_length = (line_length + 63) & ~63;
return line_length;
}
static int aty_var_to_crtc(const struct fb_info *info,
const struct fb_var_screeninfo *var,
struct crtc *crtc)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
u32 sync, vmode;
u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
u32 pix_width, dp_pix_width, dp_chain_mask;
u32 line_length;
/* input */
xres = (var->xres + 7) & ~7;
yres = var->yres;
vxres = (var->xres_virtual + 7) & ~7;
vyres = var->yres_virtual;
xoffset = (var->xoffset + 7) & ~7;
yoffset = var->yoffset;
bpp = var->bits_per_pixel;
if (bpp == 16)
bpp = (var->green.length == 5) ? 15 : 16;
sync = var->sync;
vmode = var->vmode;
/* convert (and round up) and validate */
if (vxres < xres + xoffset)
vxres = xres + xoffset;
h_disp = xres;
if (vyres < yres + yoffset)
vyres = yres + yoffset;
v_disp = yres;
if (bpp <= 8) {
bpp = 8;
pix_width = CRTC_PIX_WIDTH_8BPP;
dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP |
BYTE_ORDER_LSB_TO_MSB;
dp_chain_mask = DP_CHAIN_8BPP;
} else if (bpp <= 15) {
bpp = 16;
pix_width = CRTC_PIX_WIDTH_15BPP;
dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
BYTE_ORDER_LSB_TO_MSB;
dp_chain_mask = DP_CHAIN_15BPP;
} else if (bpp <= 16) {
bpp = 16;
pix_width = CRTC_PIX_WIDTH_16BPP;
dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
BYTE_ORDER_LSB_TO_MSB;
dp_chain_mask = DP_CHAIN_16BPP;
} else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
bpp = 24;
pix_width = CRTC_PIX_WIDTH_24BPP;
dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP |
BYTE_ORDER_LSB_TO_MSB;
dp_chain_mask = DP_CHAIN_24BPP;
} else if (bpp <= 32) {
bpp = 32;
pix_width = CRTC_PIX_WIDTH_32BPP;
dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
BYTE_ORDER_LSB_TO_MSB;
dp_chain_mask = DP_CHAIN_32BPP;
} else
FAIL("invalid bpp");
line_length = calc_line_length(par, vxres, bpp);
if (vyres * line_length > info->fix.smem_len)
FAIL("not enough video RAM");
h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
if ((xres > 1920) || (yres > 1200)) {
FAIL("MACH64 chips are designed for max 1920x1200\n"
"select another resolution.");
}
h_sync_strt = h_disp + var->right_margin;
h_sync_end = h_sync_strt + var->hsync_len;
h_sync_dly = var->right_margin & 7;
h_total = h_sync_end + h_sync_dly + var->left_margin;
v_sync_strt = v_disp + var->lower_margin;
v_sync_end = v_sync_strt + var->vsync_len;
v_total = v_sync_end + var->upper_margin;
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table != 0) {
if (!M64_HAS(LT_LCD_REGS)) {
u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
crtc->lcd_index = lcd_index &
~(LCD_INDEX_MASK | LCD_DISPLAY_DIS |
LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
aty_st_le32(LCD_INDEX, lcd_index, par);
}
if (!M64_HAS(MOBIL_BUS))
crtc->lcd_index |= CRTC2_DISPLAY_DIS;
crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par) | 0x4000;
crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
crtc->lcd_gen_cntl &=
~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
/*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
if ((crtc->lcd_gen_cntl & LCD_ON) &&
((xres > par->lcd_width) || (yres > par->lcd_height))) {
/*
* We cannot display the mode on the LCD. If the CRT is
* enabled we can turn off the LCD.
* If the CRT is off, it isn't a good idea to switch it
* on; we don't know if one is connected. So it's better
* to fail then.
*/
if (crtc->lcd_gen_cntl & CRT_ON) {
if (!(var->activate & FB_ACTIVATE_TEST))
PRINTKI("Disable LCD panel, because video mode does not fit.\n");
crtc->lcd_gen_cntl &= ~LCD_ON;
/*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
} else {
if (!(var->activate & FB_ACTIVATE_TEST))
PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
return -EINVAL;
}
}
}
if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
int VScan = 1;
/* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
/*
* This is horror! When we simulate, say 640x480 on an 800x600
* LCD monitor, the CRTC should be programmed 800x600 values for
* the non visible part, but 640x480 for the visible part.
* This code has been tested on a laptop with it's 1400x1050 LCD
* monitor and a conventional monitor both switched on.
* Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
* works with little glitches also with DOUBLESCAN modes
*/
if (yres < par->lcd_height) {
VScan = par->lcd_height / yres;
if (VScan > 1) {
VScan = 2;
vmode |= FB_VMODE_DOUBLE;
}
}
h_sync_strt = h_disp + par->lcd_right_margin;
h_sync_end = h_sync_strt + par->lcd_hsync_len;
h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
h_total = h_disp + par->lcd_hblank_len;
v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
v_total = v_disp + par->lcd_vblank_len / VScan;
}
#endif /* CONFIG_FB_ATY_GENERIC_LCD */
h_disp = (h_disp >> 3) - 1;
h_sync_strt = (h_sync_strt >> 3) - 1;
h_sync_end = (h_sync_end >> 3) - 1;
h_total = (h_total >> 3) - 1;
h_sync_wid = h_sync_end - h_sync_strt;
FAIL_MAX("h_disp too large", h_disp, 0xff);
FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
/*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
if (h_sync_wid > 0x1f)
h_sync_wid = 0x1f;
FAIL_MAX("h_total too large", h_total, 0x1ff);
if (vmode & FB_VMODE_DOUBLE) {
v_disp <<= 1;
v_sync_strt <<= 1;
v_sync_end <<= 1;
v_total <<= 1;
}
v_disp--;
v_sync_strt--;
v_sync_end--;
v_total--;
v_sync_wid = v_sync_end - v_sync_strt;
FAIL_MAX("v_disp too large", v_disp, 0x7ff);
FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
/*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
if (v_sync_wid > 0x1f)
v_sync_wid = 0x1f;
FAIL_MAX("v_total too large", v_total, 0x7ff);
c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
/* output */
crtc->vxres = vxres;
crtc->vyres = vyres;
crtc->xoffset = xoffset;
crtc->yoffset = yoffset;
crtc->bpp = bpp;
crtc->off_pitch =
((yoffset * line_length + xoffset * bpp / 8) / 8) |
((line_length / bpp) << 22);
crtc->vline_crnt_vline = 0;
crtc->h_tot_disp = h_total | (h_disp << 16);
crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly << 8) |
((h_sync_strt & 0x100) << 4) | (h_sync_wid << 16) |
(h_sync_pol << 21);
crtc->v_tot_disp = v_total | (v_disp << 16);
crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
(v_sync_pol << 21);
/* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
crtc->gen_cntl |= CRTC_VGA_LINEAR;
/* Enable doublescan mode if requested */
if (vmode & FB_VMODE_DOUBLE)
crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
/* Enable interlaced mode if requested */
if (vmode & FB_VMODE_INTERLACED)
crtc->gen_cntl |= CRTC_INTERLACE_EN;
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table != 0) {
u32 vdisplay = yres;
if (vmode & FB_VMODE_DOUBLE)
vdisplay <<= 1;
crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
/*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
USE_SHADOWED_VEND |
USE_SHADOWED_ROWCUR |
SHADOW_EN | SHADOW_RW_EN);
crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR/* | LOCK_8DOT*/;
/* MOBILITY M1 tested, FIXME: LT */
crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
if (!M64_HAS(LT_LCD_REGS))
crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
crtc->horz_stretching &= ~(HORZ_STRETCH_RATIO |
HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
do {
/*
* The horizontal blender misbehaves when
* HDisplay is less than a certain threshold
* (440 for a 1024-wide panel). It doesn't
* stretch such modes enough. Use pixel
* replication instead of blending to stretch
* modes that can be made to exactly fit the
* panel width. The undocumented "NoLCDBlend"
* option allows the pixel-replicated mode to
* be slightly wider or narrower than the
* panel width. It also causes a mode that is
* exactly half as wide as the panel to be
* pixel-replicated, rather than blended.
*/
int HDisplay = xres & ~7;
int nStretch = par->lcd_width / HDisplay;
int Remainder = par->lcd_width % HDisplay;
if ((!Remainder && ((nStretch > 2))) ||
(((HDisplay * 16) / par->lcd_width) < 7)) {
static const char StretchLoops[] = { 10, 12, 13, 15, 16 };
int horz_stretch_loop = -1, BestRemainder;
int Numerator = HDisplay, Denominator = par->lcd_width;
int Index = 5;
ATIReduceRatio(&Numerator, &Denominator);
BestRemainder = (Numerator * 16) / Denominator;
while (--Index >= 0) {
Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
Denominator;
if (Remainder < BestRemainder) {
horz_stretch_loop = Index;
if (!(BestRemainder = Remainder))
break;
}
}
if ((horz_stretch_loop >= 0) && !BestRemainder) {
int horz_stretch_ratio = 0, Accumulator = 0;
int reuse_previous = 1;
Index = StretchLoops[horz_stretch_loop];
while (--Index >= 0) {
if (Accumulator > 0)
horz_stretch_ratio |= reuse_previous;
else
Accumulator += Denominator;
Accumulator -= Numerator;
reuse_previous <<= 1;
}
crtc->horz_stretching |= (HORZ_STRETCH_EN |
((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
(horz_stretch_ratio & HORZ_STRETCH_RATIO));
break; /* Out of the do { ... } while (0) */
}
}
crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
(((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
} while (0);
}
if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
(((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
if (!M64_HAS(LT_LCD_REGS) &&
xres <= (M64_HAS(MOBIL_BUS) ? 1024 : 800))
crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
} else {
/*
* Don't use vertical blending if the mode is too wide
* or not vertically stretched.
*/
crtc->vert_stretching = 0;
}
/* copy to shadow crtc */
crtc->shadow_h_tot_disp = crtc->h_tot_disp;
crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
crtc->shadow_v_tot_disp = crtc->v_tot_disp;
crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
}
#endif /* CONFIG_FB_ATY_GENERIC_LCD */
if (M64_HAS(MAGIC_FIFO)) {
/* FIXME: display FIFO low watermark values */
crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
}
crtc->dp_pix_width = dp_pix_width;
crtc->dp_chain_mask = dp_chain_mask;
return 0;
}
static int aty_crtc_to_var(const struct crtc *crtc,
struct fb_var_screeninfo *var)
{
u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
u32 pix_width;
u32 double_scan, interlace;
/* input */
h_total = crtc->h_tot_disp & 0x1ff;
h_disp = (crtc->h_tot_disp >> 16) & 0xff;
h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
v_total = crtc->v_tot_disp & 0x7ff;
v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
/* convert */
xres = (h_disp + 1) * 8;
yres = v_disp + 1;
left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
hslen = h_sync_wid * 8;
upper = v_total - v_sync_strt - v_sync_wid;
lower = v_sync_strt - v_disp;
vslen = v_sync_wid;
sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
(v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
(c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
switch (pix_width) {
case CRTC_PIX_WIDTH_8BPP:
bpp = 8;
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
bpp = 16;
var->red.offset = 10;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 5;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
bpp = 16;
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
bpp = 24;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
bpp = 32;
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 24;
var->transp.length = 8;
break;
default:
PRINTKE("Invalid pixel width\n");
return -EINVAL;
}
/* output */
var->xres = xres;
var->yres = yres;
var->xres_virtual = crtc->vxres;
var->yres_virtual = crtc->vyres;
var->bits_per_pixel = bpp;
var->left_margin = left;
var->right_margin = right;
var->upper_margin = upper;
var->lower_margin = lower;
var->hsync_len = hslen;
var->vsync_len = vslen;
var->sync = sync;
var->vmode = FB_VMODE_NONINTERLACED;
/*
* In double scan mode, the vertical parameters are doubled,
* so we need to halve them to get the right values.
* In interlaced mode the values are already correct,
* so no correction is necessary.
*/
if (interlace)
var->vmode = FB_VMODE_INTERLACED;
if (double_scan) {
var->vmode = FB_VMODE_DOUBLE;
var->yres >>= 1;
var->upper_margin >>= 1;
var->lower_margin >>= 1;
var->vsync_len >>= 1;
}
return 0;
}
/* ------------------------------------------------------------------------- */
static int atyfb_set_par(struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
struct fb_var_screeninfo *var = &info->var;
u32 tmp, pixclock;
int err;
#ifdef DEBUG
struct fb_var_screeninfo debug;
u32 pixclock_in_ps;
#endif
if (par->asleep)
return 0;
err = aty_var_to_crtc(info, var, &par->crtc);
if (err)
return err;
pixclock = atyfb_get_pixclock(var, par);
if (pixclock == 0) {
PRINTKE("Invalid pixclock\n");
return -EINVAL;
} else {
err = par->pll_ops->var_to_pll(info, pixclock,
var->bits_per_pixel, &par->pll);
if (err)
return err;
}
par->accel_flags = var->accel_flags; /* hack */
if (var->accel_flags) {
atyfb_ops.fb_sync = atyfb_sync;
info->flags &= ~FBINFO_HWACCEL_DISABLED;
} else {
atyfb_ops.fb_sync = NULL;
info->flags |= FBINFO_HWACCEL_DISABLED;
}
if (par->blitter_may_be_busy)
wait_for_idle(par);
aty_set_crtc(par, &par->crtc);
par->dac_ops->set_dac(info, &par->pll,
var->bits_per_pixel, par->accel_flags);
par->pll_ops->set_pll(info, &par->pll);
#ifdef DEBUG
if (par->pll_ops && par->pll_ops->pll_to_var)
pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll);
else
pixclock_in_ps = 0;
if (0 == pixclock_in_ps) {
PRINTKE("ALERT ops->pll_to_var get 0\n");
pixclock_in_ps = pixclock;
}
memset(&debug, 0, sizeof(debug));
if (!aty_crtc_to_var(&par->crtc, &debug)) {
u32 hSync, vRefresh;
u32 h_disp, h_sync_strt, h_sync_end, h_total;
u32 v_disp, v_sync_strt, v_sync_end, v_total;
h_disp = debug.xres;
h_sync_strt = h_disp + debug.right_margin;
h_sync_end = h_sync_strt + debug.hsync_len;
h_total = h_sync_end + debug.left_margin;
v_disp = debug.yres;
v_sync_strt = v_disp + debug.lower_margin;
v_sync_end = v_sync_strt + debug.vsync_len;
v_total = v_sync_end + debug.upper_margin;
hSync = 1000000000 / (pixclock_in_ps * h_total);
vRefresh = (hSync * 1000) / v_total;
if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
vRefresh *= 2;
if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
vRefresh /= 2;
DPRINTK("atyfb_set_par\n");
DPRINTK(" Set Visible Mode to %ix%i-%i\n",
var->xres, var->yres, var->bits_per_pixel);
DPRINTK(" Virtual resolution %ix%i, "
"pixclock_in_ps %i (calculated %i)\n",
var->xres_virtual, var->yres_virtual,
pixclock, pixclock_in_ps);
DPRINTK(" Dot clock: %i MHz\n",
1000000 / pixclock_in_ps);
DPRINTK(" Horizontal sync: %i kHz\n", hSync);
DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
h_disp, h_sync_strt, h_sync_end, h_total,
v_disp, v_sync_strt, v_sync_end, v_total);
DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
pixclock_in_ps,
debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
}
#endif /* DEBUG */
if (!M64_HAS(INTEGRATED)) {
/* Don't forget MEM_CNTL */
tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
switch (var->bits_per_pixel) {
case 8:
tmp |= 0x02000000;
break;
case 16:
tmp |= 0x03000000;
break;
case 32:
tmp |= 0x06000000;
break;
}
aty_st_le32(MEM_CNTL, tmp, par);
} else {
tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
if (!M64_HAS(MAGIC_POSTDIV))
tmp |= par->mem_refresh_rate << 20;
switch (var->bits_per_pixel) {
case 8:
case 24:
tmp |= 0x00000000;
break;
case 16:
tmp |= 0x04000000;
break;
case 32:
tmp |= 0x08000000;
break;
}
if (M64_HAS(CT_BUS)) {
aty_st_le32(DAC_CNTL, 0x87010184, par);
aty_st_le32(BUS_CNTL, 0x680000f9, par);
} else if (M64_HAS(VT_BUS)) {
aty_st_le32(DAC_CNTL, 0x87010184, par);
aty_st_le32(BUS_CNTL, 0x680000f9, par);
} else if (M64_HAS(MOBIL_BUS)) {
aty_st_le32(DAC_CNTL, 0x80010102, par);
aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
} else {
/* GT */
aty_st_le32(DAC_CNTL, 0x86010102, par);
aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
}
aty_st_le32(MEM_CNTL, tmp, par);
}
aty_st_8(DAC_MASK, 0xff, par);
info->fix.line_length = calc_line_length(par, var->xres_virtual,
var->bits_per_pixel);
info->fix.visual = var->bits_per_pixel <= 8 ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
/* Initialize the graphics engine */
if (par->accel_flags & FB_ACCELF_TEXT)
aty_init_engine(par, info);
#ifdef CONFIG_BOOTX_TEXT
btext_update_display(info->fix.smem_start,
(((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
var->bits_per_pixel,
par->crtc.vxres * var->bits_per_pixel / 8);
#endif /* CONFIG_BOOTX_TEXT */
#ifdef DEBUG
{
/* dump non shadow CRTC, pll, LCD registers */
int i; u32 base;
/* CRTC registers */
base = 0x2000;
printk("debug atyfb: Mach64 non-shadow register values:");
for (i = 0; i < 256; i = i+4) {
if (i % 16 == 0) {
pr_cont("\n");
printk("debug atyfb: 0x%04X: ", base + i);
}
pr_cont(" %08X", aty_ld_le32(i, par));
}
pr_cont("\n\n");
#ifdef CONFIG_FB_ATY_CT
/* PLL registers */
base = 0x00;
printk("debug atyfb: Mach64 PLL register values:");
for (i = 0; i < 64; i++) {
if (i % 16 == 0) {
pr_cont("\n");
printk("debug atyfb: 0x%02X: ", base + i);
}
if (i % 4 == 0)
pr_cont(" ");
pr_cont("%02X", aty_ld_pll_ct(i, par));
}
pr_cont("\n\n");
#endif /* CONFIG_FB_ATY_CT */
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table != 0) {
/* LCD registers */
base = 0x00;
printk("debug atyfb: LCD register values:");
if (M64_HAS(LT_LCD_REGS)) {
for (i = 0; i <= POWER_MANAGEMENT; i++) {
if (i == EXT_VERT_STRETCH)
continue;
pr_cont("\ndebug atyfb: 0x%04X: ",
lt_lcd_regs[i]);
pr_cont(" %08X", aty_ld_lcd(i, par));
}
} else {
for (i = 0; i < 64; i++) {
if (i % 4 == 0)
pr_cont("\ndebug atyfb: 0x%02X: ",
base + i);
pr_cont(" %08X", aty_ld_lcd(i, par));
}
}
pr_cont("\n\n");
}
#endif /* CONFIG_FB_ATY_GENERIC_LCD */
}
#endif /* DEBUG */
return 0;
}
static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
int err;
struct crtc crtc;
union aty_pll pll;
u32 pixclock;
memcpy(&pll, &par->pll, sizeof(pll));
err = aty_var_to_crtc(info, var, &crtc);
if (err)
return err;
pixclock = atyfb_get_pixclock(var, par);
if (pixclock == 0) {
if (!(var->activate & FB_ACTIVATE_TEST))
PRINTKE("Invalid pixclock\n");
return -EINVAL;
} else {
err = par->pll_ops->var_to_pll(info, pixclock,
var->bits_per_pixel, &pll);
if (err)
return err;
}
if (var->accel_flags & FB_ACCELF_TEXT)
info->var.accel_flags = FB_ACCELF_TEXT;
else
info->var.accel_flags = 0;
aty_crtc_to_var(&crtc, var);
var->pixclock = par->pll_ops->pll_to_var(info, &pll);
return 0;
}
static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
{
u32 xoffset = info->var.xoffset;
u32 yoffset = info->var.yoffset;
u32 line_length = info->fix.line_length;
u32 bpp = info->var.bits_per_pixel;
par->crtc.off_pitch =
((yoffset * line_length + xoffset * bpp / 8) / 8) |
((line_length / bpp) << 22);
}
/*
* Open/Release the frame buffer device
*/
static int atyfb_open(struct fb_info *info, int user)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
if (user) {
par->open++;
#ifdef __sparc__
par->mmaped = 0;
#endif
}
return 0;
}
static irqreturn_t aty_irq(int irq, void *dev_id)
{
struct atyfb_par *par = dev_id;
int handled = 0;
u32 int_cntl;
spin_lock(&par->int_lock);
int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
if (int_cntl & CRTC_VBLANK_INT) {
/* clear interrupt */
aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) |
CRTC_VBLANK_INT_AK, par);
par->vblank.count++;
if (par->vblank.pan_display) {
par->vblank.pan_display = 0;
aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
}
wake_up_interruptible(&par->vblank.wait);
handled = 1;
}
spin_unlock(&par->int_lock);
return IRQ_RETVAL(handled);
}
static int aty_enable_irq(struct atyfb_par *par, int reenable)
{
u32 int_cntl;
if (!test_and_set_bit(0, &par->irq_flags)) {
if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
clear_bit(0, &par->irq_flags);
return -EINVAL;
}
spin_lock_irq(&par->int_lock);
int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
/* clear interrupt */
aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
/* enable interrupt */
aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
spin_unlock_irq(&par->int_lock);
} else if (reenable) {
spin_lock_irq(&par->int_lock);
int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
printk("atyfb: someone disabled IRQ [%08x]\n",
int_cntl);
/* re-enable interrupt */
aty_st_le32(CRTC_INT_CNTL, int_cntl |
CRTC_VBLANK_INT_EN, par);
}
spin_unlock_irq(&par->int_lock);
}
return 0;
}
static int aty_disable_irq(struct atyfb_par *par)
{
u32 int_cntl;
if (test_and_clear_bit(0, &par->irq_flags)) {
if (par->vblank.pan_display) {
par->vblank.pan_display = 0;
aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
}
spin_lock_irq(&par->int_lock);
int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
/* disable interrupt */
aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par);
spin_unlock_irq(&par->int_lock);
free_irq(par->irq, par);
}
return 0;
}
static int atyfb_release(struct fb_info *info, int user)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
#ifdef __sparc__
int was_mmaped;
#endif
if (!user)
return 0;
par->open--;
mdelay(1);
wait_for_idle(par);
if (par->open)
return 0;
#ifdef __sparc__
was_mmaped = par->mmaped;
par->mmaped = 0;
if (was_mmaped) {
struct fb_var_screeninfo var;
/*
* Now reset the default display config, we have
* no idea what the program(s) which mmap'd the
* chip did to the configuration, nor whether it
* restored it correctly.
*/
var = default_var;
if (noaccel)
var.accel_flags &= ~FB_ACCELF_TEXT;
else
var.accel_flags |= FB_ACCELF_TEXT;
if (var.yres == var.yres_virtual) {
u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
var.yres_virtual =
((videoram * 8) / var.bits_per_pixel) /
var.xres_virtual;
if (var.yres_virtual < var.yres)
var.yres_virtual = var.yres;
}
}
#endif
aty_disable_irq(par);
return 0;
}
/*
* Pan or Wrap the Display
*
* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
*/
static int atyfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 xres, yres, xoffset, yoffset;
xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
yres >>= 1;
xoffset = (var->xoffset + 7) & ~7;
yoffset = var->yoffset;
if (xoffset + xres > par->crtc.vxres ||
yoffset + yres > par->crtc.vyres)
return -EINVAL;
info->var.xoffset = xoffset;
info->var.yoffset = yoffset;
if (par->asleep)
return 0;
set_off_pitch(par, info);
if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
par->vblank.pan_display = 1;
} else {
par->vblank.pan_display = 0;
aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
}
return 0;
}
static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
{
struct aty_interrupt *vbl;
unsigned int count;
int ret;
switch (crtc) {
case 0:
vbl = &par->vblank;
break;
default:
return -ENODEV;
}
ret = aty_enable_irq(par, 0);
if (ret)
return ret;
count = vbl->count;
ret = wait_event_interruptible_timeout(vbl->wait,
count != vbl->count, HZ/10);
if (ret < 0)
return ret;
if (ret == 0) {
aty_enable_irq(par, 1);
return -ETIMEDOUT;
}
return 0;
}
#ifdef DEBUG
#define ATYIO_CLKR 0x41545900 /* ATY\00 */
#define ATYIO_CLKW 0x41545901 /* ATY\01 */
struct atyclk {
u32 ref_clk_per;
u8 pll_ref_div;
u8 mclk_fb_div;
u8 mclk_post_div; /* 1,2,3,4,8 */
u8 mclk_fb_mult; /* 2 or 4 */
u8 xclk_post_div; /* 1,2,3,4,8 */
u8 vclk_fb_div;
u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
u32 dsp_xclks_per_row; /* 0-16383 */
u32 dsp_loop_latency; /* 0-15 */
u32 dsp_precision; /* 0-7 */
u32 dsp_on; /* 0-2047 */
u32 dsp_off; /* 0-2047 */
};
#define ATYIO_FEATR 0x41545902 /* ATY\02 */
#define ATYIO_FEATW 0x41545903 /* ATY\03 */
#endif
static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
#ifdef __sparc__
struct fbtype fbtyp;
#endif
switch (cmd) {
#ifdef __sparc__
case FBIOGTYPE:
fbtyp.fb_type = FBTYPE_PCI_GENERIC;
fbtyp.fb_width = par->crtc.vxres;
fbtyp.fb_height = par->crtc.vyres;
fbtyp.fb_depth = info->var.bits_per_pixel;
fbtyp.fb_cmsize = info->cmap.len;
fbtyp.fb_size = info->fix.smem_len;
if (copy_to_user((struct fbtype __user *) arg, &fbtyp,
sizeof(fbtyp)))
return -EFAULT;
break;
#endif /* __sparc__ */
case FBIO_WAITFORVSYNC:
{
u32 crtc;
if (get_user(crtc, (__u32 __user *) arg))
return -EFAULT;
return aty_waitforvblank(par, crtc);
}
#if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
case ATYIO_CLKR:
if (M64_HAS(INTEGRATED)) {
struct atyclk clk = { 0 };
union aty_pll *pll = &par->pll;
u32 dsp_config = pll->ct.dsp_config;
u32 dsp_on_off = pll->ct.dsp_on_off;
clk.ref_clk_per = par->ref_clk_per;
clk.pll_ref_div = pll->ct.pll_ref_div;
clk.mclk_fb_div = pll->ct.mclk_fb_div;
clk.mclk_post_div = pll->ct.mclk_post_div_real;
clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
clk.xclk_post_div = pll->ct.xclk_post_div_real;
clk.vclk_fb_div = pll->ct.vclk_fb_div;
clk.vclk_post_div = pll->ct.vclk_post_div_real;
clk.dsp_xclks_per_row = dsp_config & 0x3fff;
clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
clk.dsp_precision = (dsp_config >> 20) & 7;
clk.dsp_off = dsp_on_off & 0x7ff;
clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
if (copy_to_user((struct atyclk __user *) arg, &clk,
sizeof(clk)))
return -EFAULT;
} else
return -EINVAL;
break;
case ATYIO_CLKW:
if (M64_HAS(INTEGRATED)) {
struct atyclk clk;
union aty_pll *pll = &par->pll;
if (copy_from_user(&clk, (struct atyclk __user *) arg,
sizeof(clk)))
return -EFAULT;
par->ref_clk_per = clk.ref_clk_per;
pll->ct.pll_ref_div = clk.pll_ref_div;
pll->ct.mclk_fb_div = clk.mclk_fb_div;
pll->ct.mclk_post_div_real = clk.mclk_post_div;
pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
pll->ct.xclk_post_div_real = clk.xclk_post_div;
pll->ct.vclk_fb_div = clk.vclk_fb_div;
pll->ct.vclk_post_div_real = clk.vclk_post_div;
pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
((clk.dsp_loop_latency & 0xf) << 16) |
((clk.dsp_precision & 7) << 20);
pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) |
((clk.dsp_on & 0x7ff) << 16);
/*aty_calc_pll_ct(info, &pll->ct);*/
aty_set_pll_ct(info, pll);
} else
return -EINVAL;
break;
case ATYIO_FEATR:
if (get_user(par->features, (u32 __user *) arg))
return -EFAULT;
break;
case ATYIO_FEATW:
if (put_user(par->features, (u32 __user *) arg))
return -EFAULT;
break;
#endif /* DEBUG && CONFIG_FB_ATY_CT */
default:
return -EINVAL;
}
return 0;
}
static int atyfb_sync(struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
if (par->blitter_may_be_busy)
wait_for_idle(par);
return 0;
}
#ifdef __sparc__
static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
unsigned int size, page, map_size = 0;
unsigned long map_offset = 0;
unsigned long off;
int i;
if (!par->mmap_map)
return -ENXIO;
if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
return -EINVAL;
off = vma->vm_pgoff << PAGE_SHIFT;
size = vma->vm_end - vma->vm_start;
/* VM_IO | VM_DONTEXPAND | VM_DONTDUMP are set by remap_pfn_range() */
if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
((off == info->fix.smem_len) && (size == PAGE_SIZE)))
off += 0x8000000000000000UL;
vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
/* Each page, see which map applies */
for (page = 0; page < size;) {
map_size = 0;
for (i = 0; par->mmap_map[i].size; i++) {
unsigned long start = par->mmap_map[i].voff;
unsigned long end = start + par->mmap_map[i].size;
unsigned long offset = off + page;
if (start > offset)
continue;
if (offset >= end)
continue;
map_size = par->mmap_map[i].size - (offset - start);
map_offset = par->mmap_map[i].poff + (offset - start);
break;
}
if (!map_size) {
page += PAGE_SIZE;
continue;
}
if (page + map_size > size)
map_size = size - page;
pgprot_val(vma->vm_page_prot) &= ~(par->mmap_map[i].prot_mask);
pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
if (remap_pfn_range(vma, vma->vm_start + page,
map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
return -EAGAIN;
page += map_size;
}
if (!map_size)
return -EINVAL;
if (!par->mmaped)
par->mmaped = 1;
return 0;
}
#endif /* __sparc__ */
#if defined(CONFIG_PCI)
#ifdef CONFIG_PPC_PMAC
/* Power management routines. Those are used for PowerBook sleep.
*/
static int aty_power_mgmt(int sleep, struct atyfb_par *par)
{
u32 pm;
int timeout;
pm = aty_ld_lcd(POWER_MANAGEMENT, par);
pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
aty_st_lcd(POWER_MANAGEMENT, pm, par);
pm = aty_ld_lcd(POWER_MANAGEMENT, par);
timeout = 2000;
if (sleep) {
/* Sleep */
pm &= ~PWR_MGT_ON;
aty_st_lcd(POWER_MANAGEMENT, pm, par);
pm = aty_ld_lcd(POWER_MANAGEMENT, par);
udelay(10);
pm &= ~(PWR_BLON | AUTO_PWR_UP);
pm |= SUSPEND_NOW;
aty_st_lcd(POWER_MANAGEMENT, pm, par);
pm = aty_ld_lcd(POWER_MANAGEMENT, par);
udelay(10);
pm |= PWR_MGT_ON;
aty_st_lcd(POWER_MANAGEMENT, pm, par);
do {
pm = aty_ld_lcd(POWER_MANAGEMENT, par);
mdelay(1);
if ((--timeout) == 0)
break;
} while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
} else {
/* Wakeup */
pm &= ~PWR_MGT_ON;
aty_st_lcd(POWER_MANAGEMENT, pm, par);
pm = aty_ld_lcd(POWER_MANAGEMENT, par);
udelay(10);
pm &= ~SUSPEND_NOW;
pm |= (PWR_BLON | AUTO_PWR_UP);
aty_st_lcd(POWER_MANAGEMENT, pm, par);
pm = aty_ld_lcd(POWER_MANAGEMENT, par);
udelay(10);
pm |= PWR_MGT_ON;
aty_st_lcd(POWER_MANAGEMENT, pm, par);
do {
pm = aty_ld_lcd(POWER_MANAGEMENT, par);
mdelay(1);
if ((--timeout) == 0)
break;
} while ((pm & PWR_MGT_STATUS_MASK) != 0);
}
mdelay(500);
return timeout ? 0 : -EIO;
}
#endif /* CONFIG_PPC_PMAC */
static int atyfb_pci_suspend_late(struct device *dev, pm_message_t state)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct fb_info *info = pci_get_drvdata(pdev);
struct atyfb_par *par = (struct atyfb_par *) info->par;
if (state.event == pdev->dev.power.power_state.event)
return 0;
console_lock();
fb_set_suspend(info, 1);
/* Idle & reset engine */
wait_for_idle(par);
aty_reset_engine(par);
/* Blank display and LCD */
atyfb_blank(FB_BLANK_POWERDOWN, info);
par->asleep = 1;
par->lock_blank = 1;
/*
* Because we may change PCI D state ourselves, we need to
* first save the config space content so the core can
* restore it properly on resume.
*/
#ifdef CONFIG_PPC_PMAC
/* Set chip to "suspend" mode */
if (machine_is(powermac) && aty_power_mgmt(1, par)) {
par->asleep = 0;
par->lock_blank = 0;
atyfb_blank(FB_BLANK_UNBLANK, info);
fb_set_suspend(info, 0);
console_unlock();
return -EIO;
}
#endif
console_unlock();
pdev->dev.power.power_state = state;
return 0;
}
static int __maybe_unused atyfb_pci_suspend(struct device *dev)
{
return atyfb_pci_suspend_late(dev, PMSG_SUSPEND);
}
static int __maybe_unused atyfb_pci_hibernate(struct device *dev)
{
return atyfb_pci_suspend_late(dev, PMSG_HIBERNATE);
}
static int __maybe_unused atyfb_pci_freeze(struct device *dev)
{
return atyfb_pci_suspend_late(dev, PMSG_FREEZE);
}
static void aty_resume_chip(struct fb_info *info)
{
struct atyfb_par *par = info->par;
aty_st_le32(MEM_CNTL, par->mem_cntl, par);
if (par->pll_ops->resume_pll)
par->pll_ops->resume_pll(info, &par->pll);
if (par->aux_start)
aty_st_le32(BUS_CNTL,
aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
}
static int __maybe_unused atyfb_pci_resume(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
struct fb_info *info = pci_get_drvdata(pdev);
struct atyfb_par *par = (struct atyfb_par *) info->par;
if (pdev->dev.power.power_state.event == PM_EVENT_ON)
return 0;
console_lock();
/*
* PCI state will have been restored by the core, so
* we should be in D0 now with our config space fully
* restored
*/
#ifdef CONFIG_PPC_PMAC
if (machine_is(powermac) &&
pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
aty_power_mgmt(0, par);
#endif
aty_resume_chip(info);
par->asleep = 0;
/* Restore display */
atyfb_set_par(info);
/* Refresh */
fb_set_suspend(info, 0);
/* Unblank */
par->lock_blank = 0;
atyfb_blank(FB_BLANK_UNBLANK, info);
console_unlock();
pdev->dev.power.power_state = PMSG_ON;
return 0;
}
static const struct dev_pm_ops atyfb_pci_pm_ops = {
#ifdef CONFIG_PM_SLEEP
.suspend = atyfb_pci_suspend,
.resume = atyfb_pci_resume,
.freeze = atyfb_pci_freeze,
.thaw = atyfb_pci_resume,
.poweroff = atyfb_pci_hibernate,
.restore = atyfb_pci_resume,
#endif /* CONFIG_PM_SLEEP */
};
#endif /* defined(CONFIG_PCI) */
/* Backlight */
#ifdef CONFIG_FB_ATY_BACKLIGHT
#define MAX_LEVEL 0xFF
static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
{
struct fb_info *info = pci_get_drvdata(par->pdev);
int atylevel;
/* Get and convert the value */
/* No locking of bl_curve since we read a single value */
atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
if (atylevel < 0)
atylevel = 0;
else if (atylevel > MAX_LEVEL)
atylevel = MAX_LEVEL;
return atylevel;
}
static int aty_bl_update_status(struct backlight_device *bd)
{
struct atyfb_par *par = bl_get_data(bd);
unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
int level = backlight_get_brightness(bd);
reg |= (BLMOD_EN | BIASMOD_EN);
if (level > 0) {
reg &= ~BIAS_MOD_LEVEL_MASK;
reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
} else {
reg &= ~BIAS_MOD_LEVEL_MASK;
reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
}
aty_st_lcd(LCD_MISC_CNTL, reg, par);
return 0;
}
static const struct backlight_ops aty_bl_data = {
.update_status = aty_bl_update_status,
};
static void aty_bl_init(struct atyfb_par *par)
{
struct backlight_properties props;
struct fb_info *info = pci_get_drvdata(par->pdev);
struct backlight_device *bd;
char name[12];
#ifdef CONFIG_PMAC_BACKLIGHT
if (!pmac_has_backlight_type("ati"))
return;
#endif
snprintf(name, sizeof(name), "atybl%d", info->node);
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
bd = backlight_device_register(name, info->device, par, &aty_bl_data,
&props);
if (IS_ERR(bd)) {
info->bl_dev = NULL;
printk(KERN_WARNING "aty: Backlight registration failed\n");
goto error;
}
info->bl_dev = bd;
fb_bl_default_curve(info, 0,
0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
bd->props.brightness = bd->props.max_brightness;
bd->props.power = FB_BLANK_UNBLANK;
backlight_update_status(bd);
printk("aty: Backlight initialized (%s)\n", name);
return;
error:
return;
}
#ifdef CONFIG_PCI
static void aty_bl_exit(struct backlight_device *bd)
{
backlight_device_unregister(bd);
printk("aty: Backlight unloaded\n");
}
#endif /* CONFIG_PCI */
#endif /* CONFIG_FB_ATY_BACKLIGHT */
static void aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
{
static const int ragepro_tbl[] = {
44, 50, 55, 66, 75, 80, 100
};
static const int ragexl_tbl[] = {
50, 66, 75, 83, 90, 95, 100, 105,
110, 115, 120, 125, 133, 143, 166
};
const int *refresh_tbl;
int i, size;
if (M64_HAS(XL_MEM)) {
refresh_tbl = ragexl_tbl;
size = ARRAY_SIZE(ragexl_tbl);
} else {
refresh_tbl = ragepro_tbl;
size = ARRAY_SIZE(ragepro_tbl);
}
for (i = 0; i < size; i++) {
if (xclk < refresh_tbl[i])
break;
}
par->mem_refresh_rate = i;
}
/*
* Initialisation
*/
static struct fb_info *fb_list = NULL;
#if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
static int atyfb_get_timings_from_lcd(struct atyfb_par *par,
struct fb_var_screeninfo *var)
{
int ret = -EINVAL;
if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
*var = default_var;
var->xres = var->xres_virtual = par->lcd_hdisp;
var->right_margin = par->lcd_right_margin;
var->left_margin = par->lcd_hblank_len -
(par->lcd_right_margin + par->lcd_hsync_dly +
par->lcd_hsync_len);
var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
var->yres = var->yres_virtual = par->lcd_vdisp;
var->lower_margin = par->lcd_lower_margin;
var->upper_margin = par->lcd_vblank_len -
(par->lcd_lower_margin + par->lcd_vsync_len);
var->vsync_len = par->lcd_vsync_len;
var->pixclock = par->lcd_pixclock;
ret = 0;
}
return ret;
}
#endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
static int aty_init(struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
const char *ramname = NULL, *xtal;
int gtb_memsize, has_var = 0;
struct fb_var_screeninfo var;
int ret;
#ifdef CONFIG_ATARI
u8 dac_type;
#endif
init_waitqueue_head(&par->vblank.wait);
spin_lock_init(&par->int_lock);
#ifdef CONFIG_FB_ATY_GX
if (!M64_HAS(INTEGRATED)) {
u32 stat0;
u8 dac_subtype, clk_type;
stat0 = aty_ld_le32(CNFG_STAT0, par);
par->bus_type = (stat0 >> 0) & 0x07;
par->ram_type = (stat0 >> 3) & 0x07;
ramname = aty_gx_ram[par->ram_type];
/* FIXME: clockchip/RAMDAC probing? */
#ifdef CONFIG_ATARI
clk_type = CLK_ATI18818_1;
dac_type = (stat0 >> 9) & 0x07;
if (dac_type == 0x07)
dac_subtype = DAC_ATT20C408;
else
dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
#else
dac_subtype = DAC_IBMRGB514;
clk_type = CLK_IBMRGB514;
#endif
switch (dac_subtype) {
case DAC_IBMRGB514:
par->dac_ops = &aty_dac_ibm514;
break;
#ifdef CONFIG_ATARI
case DAC_ATI68860_B:
case DAC_ATI68860_C:
par->dac_ops = &aty_dac_ati68860b;
break;
case DAC_ATT20C408:
case DAC_ATT21C498:
par->dac_ops = &aty_dac_att21c498;
break;
#endif
default:
PRINTKI("aty_init: DAC type not implemented yet!\n");
par->dac_ops = &aty_dac_unsupported;
break;
}
switch (clk_type) {
#ifdef CONFIG_ATARI
case CLK_ATI18818_1:
par->pll_ops = &aty_pll_ati18818_1;
break;
#else
case CLK_IBMRGB514:
par->pll_ops = &aty_pll_ibm514;
break;
#endif
default:
PRINTKI("aty_init: CLK type not implemented yet!");
par->pll_ops = &aty_pll_unsupported;
break;
}
}
#endif /* CONFIG_FB_ATY_GX */
#ifdef CONFIG_FB_ATY_CT
if (M64_HAS(INTEGRATED)) {
par->dac_ops = &aty_dac_ct;
par->pll_ops = &aty_pll_ct;
par->bus_type = PCI;
par->ram_type = (aty_ld_le32(CNFG_STAT0, par) & 0x07);
if (M64_HAS(XL_MEM))
ramname = aty_xl_ram[par->ram_type];
else
ramname = aty_ct_ram[par->ram_type];
/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
par->pll_limits.mclk = 63;
/* Mobility + 32bit memory interface need halved XCLK. */
if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32)
par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1;
}
#endif
#ifdef CONFIG_PPC_PMAC
/*
* The Apple iBook1 uses non-standard memory frequencies.
* We detect it and set the frequency manually.
*/
if (of_machine_is_compatible("PowerBook2,1")) {
par->pll_limits.mclk = 70;
par->pll_limits.xclk = 53;
}
#endif
/* Allow command line to override clocks. */
if (pll)
par->pll_limits.pll_max = pll;
if (mclk)
par->pll_limits.mclk = mclk;
if (xclk)
par->pll_limits.xclk = xclk;
aty_calc_mem_refresh(par, par->pll_limits.xclk);
par->pll_per = 1000000/par->pll_limits.pll_max;
par->mclk_per = 1000000/par->pll_limits.mclk;
par->xclk_per = 1000000/par->pll_limits.xclk;
par->ref_clk_per = 1000000000000ULL / 14318180;
xtal = "14.31818";
#ifdef CONFIG_FB_ATY_CT
if (M64_HAS(GTB_DSP)) {
u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
if (pll_ref_div) {
int diff1, diff2;
diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
if (diff1 < 0)
diff1 = -diff1;
if (diff2 < 0)
diff2 = -diff2;
if (diff2 < diff1) {
par->ref_clk_per = 1000000000000ULL / 29498928;
xtal = "29.498928";
}
}
}
#endif /* CONFIG_FB_ATY_CT */
/* save previous video mode */
aty_get_crtc(par, &par->saved_crtc);
if (par->pll_ops->get_pll)
par->pll_ops->get_pll(info, &par->saved_pll);
par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
gtb_memsize = M64_HAS(GTB_DSP);
if (gtb_memsize)
/* 0xF used instead of MEM_SIZE_ALIAS */
switch (par->mem_cntl & 0xF) {
case MEM_SIZE_512K:
info->fix.smem_len = 0x80000;
break;
case MEM_SIZE_1M:
info->fix.smem_len = 0x100000;
break;
case MEM_SIZE_2M_GTB:
info->fix.smem_len = 0x200000;
break;
case MEM_SIZE_4M_GTB:
info->fix.smem_len = 0x400000;
break;
case MEM_SIZE_6M_GTB:
info->fix.smem_len = 0x600000;
break;
case MEM_SIZE_8M_GTB:
info->fix.smem_len = 0x800000;
break;
default:
info->fix.smem_len = 0x80000;
} else
switch (par->mem_cntl & MEM_SIZE_ALIAS) {
case MEM_SIZE_512K:
info->fix.smem_len = 0x80000;
break;
case MEM_SIZE_1M:
info->fix.smem_len = 0x100000;
break;
case MEM_SIZE_2M:
info->fix.smem_len = 0x200000;
break;
case MEM_SIZE_4M:
info->fix.smem_len = 0x400000;
break;
case MEM_SIZE_6M:
info->fix.smem_len = 0x600000;
break;
case MEM_SIZE_8M:
info->fix.smem_len = 0x800000;
break;
default:
info->fix.smem_len = 0x80000;
}
if (M64_HAS(MAGIC_VRAM_SIZE)) {
if (aty_ld_le32(CNFG_STAT1, par) & 0x40000000)
info->fix.smem_len += 0x400000;
}
if (vram) {
info->fix.smem_len = vram * 1024;
par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
if (info->fix.smem_len <= 0x80000)
par->mem_cntl |= MEM_SIZE_512K;
else if (info->fix.smem_len <= 0x100000)
par->mem_cntl |= MEM_SIZE_1M;
else if (info->fix.smem_len <= 0x200000)
par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
else if (info->fix.smem_len <= 0x400000)
par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
else if (info->fix.smem_len <= 0x600000)
par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
else
par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
aty_st_le32(MEM_CNTL, par->mem_cntl, par);
}
/*
* Reg Block 0 (CT-compatible block) is at mmio_start
* Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
*/
if (M64_HAS(GX)) {
info->fix.mmio_len = 0x400;
info->fix.accel = FB_ACCEL_ATI_MACH64GX;
} else if (M64_HAS(CT)) {
info->fix.mmio_len = 0x400;
info->fix.accel = FB_ACCEL_ATI_MACH64CT;
} else if (M64_HAS(VT)) {
info->fix.mmio_start -= 0x400;
info->fix.mmio_len = 0x800;
info->fix.accel = FB_ACCEL_ATI_MACH64VT;
} else {/* GT */
info->fix.mmio_start -= 0x400;
info->fix.mmio_len = 0x800;
info->fix.accel = FB_ACCEL_ATI_MACH64GT;
}
PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len>>20),
info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal,
par->pll_limits.pll_max, par->pll_limits.mclk,
par->pll_limits.xclk);
#if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
if (M64_HAS(INTEGRATED)) {
int i;
printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL "
"EXT_MEM_CNTL CRTC_GEN_CNTL DSP_CONFIG "
"DSP_ON_OFF CLOCK_CNTL\n"
"debug atyfb: %08x %08x %08x "
"%08x %08x %08x "
"%08x %08x\n"
"debug atyfb: PLL",
aty_ld_le32(BUS_CNTL, par),
aty_ld_le32(DAC_CNTL, par),
aty_ld_le32(MEM_CNTL, par),
aty_ld_le32(EXT_MEM_CNTL, par),
aty_ld_le32(CRTC_GEN_CNTL, par),
aty_ld_le32(DSP_CONFIG, par),
aty_ld_le32(DSP_ON_OFF, par),
aty_ld_le32(CLOCK_CNTL, par));
for (i = 0; i < 40; i++)
pr_cont(" %02x", aty_ld_pll_ct(i, par));
pr_cont("\n");
}
#endif
if (par->pll_ops->init_pll)
par->pll_ops->init_pll(info, &par->pll);
if (par->pll_ops->resume_pll)
par->pll_ops->resume_pll(info, &par->pll);
aty_fudge_framebuffer_len(info);
/*
* Disable register access through the linear aperture
* if the auxiliary aperture is used so we can access
* the full 8 MB of video RAM on 8 MB boards.
*/
if (par->aux_start)
aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) |
BUS_APER_REG_DIS, par);
if (!nomtrr)
/*
* Only the ioremap_wc()'d area will get WC here
* since ioremap_uc() was used on the entire PCI BAR.
*/
par->wc_cookie = arch_phys_wc_add(par->res_start,
par->res_size);
info->fbops = &atyfb_ops;
info->pseudo_palette = par->pseudo_palette;
info->flags = FBINFO_HWACCEL_IMAGEBLIT |
FBINFO_HWACCEL_FILLRECT |
FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_YPAN |
FBINFO_READS_FAST;
#ifdef CONFIG_PMAC_BACKLIGHT
if (M64_HAS(G3_PB_1_1) && of_machine_is_compatible("PowerBook1,1")) {
/*
* these bits let the 101 powerbook
* wake up from sleep -- paulus
*/
aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par) |
USE_F32KHZ | TRISTATE_MEM_EN, par);
} else
#endif
memset(&var, 0, sizeof(var));
#ifdef CONFIG_PPC
if (machine_is(powermac)) {
/*
* FIXME: The NVRAM stuff should be put in a Mac-specific file,
* as it applies to all Mac video cards
*/
if (mode) {
if (mac_find_mode(&var, info, mode, 8))
has_var = 1;
} else {
if (default_vmode == VMODE_CHOOSE) {
int sense;
if (M64_HAS(G3_PB_1024x768))
/* G3 PowerBook with 1024x768 LCD */
default_vmode = VMODE_1024_768_60;
else if (of_machine_is_compatible("iMac"))
default_vmode = VMODE_1024_768_75;
else if (of_machine_is_compatible("PowerBook2,1"))
/* iBook with 800x600 LCD */
default_vmode = VMODE_800_600_60;
else
default_vmode = VMODE_640_480_67;
sense = read_aty_sense(par);
PRINTKI("monitor sense=%x, mode %d\n",
sense, mac_map_monitor_sense(sense));
}
if (default_vmode <= 0 || default_vmode > VMODE_MAX)
default_vmode = VMODE_640_480_60;
if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
default_cmode = CMODE_8;
if (!mac_vmode_to_var(default_vmode, default_cmode,
&var))
has_var = 1;
}
}
#endif /* !CONFIG_PPC */
#if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
if (!atyfb_get_timings_from_lcd(par, &var))
has_var = 1;
#endif
if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
has_var = 1;
if (!has_var)
var = default_var;
if (noaccel)
var.accel_flags &= ~FB_ACCELF_TEXT;
else
var.accel_flags |= FB_ACCELF_TEXT;
if (comp_sync != -1) {
if (!comp_sync)
var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
else
var.sync |= FB_SYNC_COMP_HIGH_ACT;
}
if (var.yres == var.yres_virtual) {
u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
if (var.yres_virtual < var.yres)
var.yres_virtual = var.yres;
}
ret = atyfb_check_var(&var, info);
if (ret) {
PRINTKE("can't set default video mode\n");
goto aty_init_exit;
}
#ifdef CONFIG_FB_ATY_CT
if (!noaccel && M64_HAS(INTEGRATED))
aty_init_cursor(info, &atyfb_ops);
#endif /* CONFIG_FB_ATY_CT */
info->var = var;
ret = fb_alloc_cmap(&info->cmap, 256, 0);
if (ret < 0)
goto aty_init_exit;
ret = register_framebuffer(info);
if (ret < 0) {
fb_dealloc_cmap(&info->cmap);
goto aty_init_exit;
}
if (M64_HAS(MOBIL_BUS) && backlight) {
#ifdef CONFIG_FB_ATY_BACKLIGHT
aty_bl_init(par);
#endif
}
fb_list = info;
PRINTKI("fb%d: %s frame buffer device on %s\n",
info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
return 0;
aty_init_exit:
/* restore video mode */
aty_set_crtc(par, &par->saved_crtc);
par->pll_ops->set_pll(info, &par->saved_pll);
arch_phys_wc_del(par->wc_cookie);
return ret;
}
#if defined(CONFIG_ATARI) && !defined(MODULE)
static int store_video_par(char *video_str, unsigned char m64_num)
{
char *p;
unsigned long vmembase, size, guiregbase;
PRINTKI("store_video_par() '%s' \n", video_str);
if (!(p = strsep(&video_str, ";")) || !*p)
goto mach64_invalid;
vmembase = simple_strtoul(p, NULL, 0);
if (!(p = strsep(&video_str, ";")) || !*p)
goto mach64_invalid;
size = simple_strtoul(p, NULL, 0);
if (!(p = strsep(&video_str, ";")) || !*p)
goto mach64_invalid;
guiregbase = simple_strtoul(p, NULL, 0);
phys_vmembase[m64_num] = vmembase;
phys_size[m64_num] = size;
phys_guiregbase[m64_num] = guiregbase;
PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
guiregbase);
return 0;
mach64_invalid:
phys_vmembase[m64_num] = 0;
return -1;
}
#endif /* CONFIG_ATARI && !MODULE */
/*
* Blank the display.
*/
static int atyfb_blank(int blank, struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
u32 gen_cntl;
if (par->lock_blank || par->asleep)
return 0;
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table && blank > FB_BLANK_NORMAL &&
(aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
pm &= ~PWR_BLON;
aty_st_lcd(POWER_MANAGEMENT, pm, par);
}
#endif
gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
gen_cntl &= ~0x400004c;
switch (blank) {
case FB_BLANK_UNBLANK:
break;
case FB_BLANK_NORMAL:
gen_cntl |= 0x4000040;
break;
case FB_BLANK_VSYNC_SUSPEND:
gen_cntl |= 0x4000048;
break;
case FB_BLANK_HSYNC_SUSPEND:
gen_cntl |= 0x4000044;
break;
case FB_BLANK_POWERDOWN:
gen_cntl |= 0x400004c;
break;
}
aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
#ifdef CONFIG_FB_ATY_GENERIC_LCD
if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
(aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
pm |= PWR_BLON;
aty_st_lcd(POWER_MANAGEMENT, pm, par);
}
#endif
return 0;
}
static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
const struct atyfb_par *par)
{
aty_st_8(DAC_W_INDEX, regno, par);
aty_st_8(DAC_DATA, red, par);
aty_st_8(DAC_DATA, green, par);
aty_st_8(DAC_DATA, blue, par);
}
/*
* Set a single color register. The values supplied are already
* rounded down to the hardware's capabilities (according to the
* entries in the var structure). Return != 0 for invalid regno.
* !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
*/
static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int transp, struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
int i, depth;
u32 *pal = info->pseudo_palette;
depth = info->var.bits_per_pixel;
if (depth == 16)
depth = (info->var.green.length == 5) ? 15 : 16;
if (par->asleep)
return 0;
if (regno > 255 ||
(depth == 16 && regno > 63) ||
(depth == 15 && regno > 31))
return 1;
red >>= 8;
green >>= 8;
blue >>= 8;
par->palette[regno].red = red;
par->palette[regno].green = green;
par->palette[regno].blue = blue;
if (regno < 16) {
switch (depth) {
case 15:
pal[regno] = (regno << 10) | (regno << 5) | regno;
break;
case 16:
pal[regno] = (regno << 11) | (regno << 5) | regno;
break;
case 24:
pal[regno] = (regno << 16) | (regno << 8) | regno;
break;
case 32:
i = (regno << 8) | regno;
pal[regno] = (i << 16) | i;
break;
}
}
i = aty_ld_8(DAC_CNTL, par) & 0xfc;
if (M64_HAS(EXTRA_BRIGHT))
i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
aty_st_8(DAC_CNTL, i, par);
aty_st_8(DAC_MASK, 0xff, par);
if (M64_HAS(INTEGRATED)) {
if (depth == 16) {
if (regno < 32)
aty_st_pal(regno << 3, red,
par->palette[regno << 1].green,
blue, par);
red = par->palette[regno >> 1].red;
blue = par->palette[regno >> 1].blue;
regno <<= 2;
} else if (depth == 15) {
regno <<= 3;
for (i = 0; i < 8; i++)
aty_st_pal(regno + i, red, green, blue, par);
}
}
aty_st_pal(regno, red, green, blue, par);
return 0;
}
#ifdef CONFIG_PCI
#ifdef __sparc__
static int atyfb_setup_sparc(struct pci_dev *pdev, struct fb_info *info,
unsigned long addr)
{
struct atyfb_par *par = info->par;
struct device_node *dp;
u32 mem, chip_id;
int i, j, ret;
/*
* Map memory-mapped registers.
*/
par->ati_regbase = (void *)addr + 0x7ffc00UL;
info->fix.mmio_start = addr + 0x7ffc00UL;
/*
* Map in big-endian aperture.
*/
info->screen_base = (char *) (addr + 0x800000UL);
info->fix.smem_start = addr + 0x800000UL;
/*
* Figure mmap addresses from PCI config space.
* Split Framebuffer in big- and little-endian halfs.
*/
for (i = 0; i < 6 && pdev->resource[i].start; i++)
/* nothing */ ;
j = i + 4;
par->mmap_map = kcalloc(j, sizeof(*par->mmap_map), GFP_ATOMIC);
if (!par->mmap_map) {
PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
return -ENOMEM;
}
for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
struct resource *rp = &pdev->resource[i];
int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
unsigned long base;
u32 size, pbase;
base = rp->start;
io = (rp->flags & IORESOURCE_IO);
size = rp->end - base + 1;
pci_read_config_dword(pdev, breg, &pbase);
if (io)
size &= ~1;
/*
* Map the framebuffer a second time, this time without
* the braindead _PAGE_IE setting. This is used by the
* fixed Xserver, but we need to maintain the old mapping
* to stay compatible with older ones...
*/
if (base == addr) {
par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
par->mmap_map[j].poff = base & PAGE_MASK;
par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
par->mmap_map[j].prot_mask = _PAGE_CACHE;
par->mmap_map[j].prot_flag = _PAGE_E;
j++;
}
/*
* Here comes the old framebuffer mapping with _PAGE_IE
* set for the big endian half of the framebuffer...
*/
if (base == addr) {
par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
par->mmap_map[j].size = 0x800000;
par->mmap_map[j].prot_mask = _PAGE_CACHE;
par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
size -= 0x800000;
j++;
}
par->mmap_map[j].voff = pbase & PAGE_MASK;
par->mmap_map[j].poff = base & PAGE_MASK;
par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
par->mmap_map[j].prot_mask = _PAGE_CACHE;
par->mmap_map[j].prot_flag = _PAGE_E;
j++;
}
ret = correct_chipset(par);
if (ret)
return ret;
if (IS_XL(pdev->device)) {
/*
* Fix PROMs idea of MEM_CNTL settings...
*/
mem = aty_ld_le32(MEM_CNTL, par);
chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
switch (mem & 0x0f) {
case 3:
mem = (mem & ~(0x0f)) | 2;
break;
case 7:
mem = (mem & ~(0x0f)) | 3;
break;
case 9:
mem = (mem & ~(0x0f)) | 4;
break;
case 11:
mem = (mem & ~(0x0f)) | 5;
break;
default:
break;
}
if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
mem &= ~(0x00700000);
}
mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
aty_st_le32(MEM_CNTL, mem, par);
}
dp = pci_device_to_OF_node(pdev);
if (dp == of_console_device) {
struct fb_var_screeninfo *var = &default_var;
unsigned int N, P, Q, M, T, R;
struct crtc crtc;
u8 pll_regs[16];
u8 clock_cntl;
crtc.vxres = of_getintprop_default(dp, "width", 1024);
crtc.vyres = of_getintprop_default(dp, "height", 768);
var->bits_per_pixel = of_getintprop_default(dp, "depth", 8);
var->xoffset = var->yoffset = 0;
crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
aty_crtc_to_var(&crtc, var);
/*
* Read the PLL to figure actual Refresh Rate.
*/
clock_cntl = aty_ld_8(CLOCK_CNTL, par);
/* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
for (i = 0; i < 16; i++)
pll_regs[i] = aty_ld_pll_ct(i, par);
/*
* PLL Reference Divider M:
*/
M = pll_regs[PLL_REF_DIV];
/*
* PLL Feedback Divider N (Dependent on CLOCK_CNTL):
*/
N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)];
/*
* PLL Post Divider P (Dependent on CLOCK_CNTL):
*/
P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) |
((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)];
/*
* PLL Divider Q:
*/
Q = N / P;
/*
* Target Frequency:
*
* T * M
* Q = -------
* 2 * R
*
* where R is XTALIN (= 14318 or 29498 kHz).
*/
if (IS_XL(pdev->device))
R = 29498;
else
R = 14318;
T = 2 * Q * R / M;
default_var.pixclock = 1000000000 / T;
}
return 0;
}
#else /* __sparc__ */
#ifdef __i386__
#ifdef CONFIG_FB_ATY_GENERIC_LCD
static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
{
u32 driv_inf_tab, sig;
u16 lcd_ofs;
/*
* To support an LCD panel, we should know it's dimensions and
* it's desired pixel clock.
* There are two ways to do it:
* - Check the startup video mode and calculate the panel
* size from it. This is unreliable.
* - Read it from the driver information table in the video BIOS.
*/
/* Address of driver information table is at offset 0x78. */
driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
/* Check for the driver information table signature. */
sig = *(u32 *)driv_inf_tab;
if ((sig == 0x54504c24) || /* Rage LT pro */
(sig == 0x544d5224) || /* Rage mobility */
(sig == 0x54435824) || /* Rage XC */
(sig == 0x544c5824)) { /* Rage XL */
PRINTKI("BIOS contains driver information table.\n");
lcd_ofs = *(u16 *)(driv_inf_tab + 10);
par->lcd_table = 0;
if (lcd_ofs != 0)
par->lcd_table = bios_base + lcd_ofs;
}
if (par->lcd_table != 0) {
char model[24];
char strbuf[16];
char refresh_rates_buf[100];
int id, tech, f, i, m, default_refresh_rate;
char *txtcolour;
char *txtmonitor;
char *txtdual;
char *txtformat;
u16 width, height, panel_type, refresh_rates;
u16 *lcdmodeptr;
u32 format;
u8 lcd_refresh_rates[16] = { 50, 56, 60, 67, 70, 72, 75, 76, 85,
90, 100, 120, 140, 150, 160, 200 };
/*
* The most important information is the panel size at
* offset 25 and 27, but there's some other nice information
* which we print to the screen.
*/
id = *(u8 *)par->lcd_table;
strscpy(model, (char *)par->lcd_table+1, sizeof(model));
width = par->lcd_width = *(u16 *)(par->lcd_table+25);
height = par->lcd_height = *(u16 *)(par->lcd_table+27);
panel_type = *(u16 *)(par->lcd_table+29);
if (panel_type & 1)
txtcolour = "colour";
else
txtcolour = "monochrome";
if (panel_type & 2)
txtdual = "dual (split) ";
else
txtdual = "";
tech = (panel_type >> 2) & 63;
switch (tech) {
case 0:
txtmonitor = "passive matrix";
break;
case 1:
txtmonitor = "active matrix";
break;
case 2:
txtmonitor = "active addressed STN";
break;
case 3:
txtmonitor = "EL";
break;
case 4:
txtmonitor = "plasma";
break;
default:
txtmonitor = "unknown";
}
format = *(u32 *)(par->lcd_table+57);
if (tech == 0 || tech == 2) {
switch (format & 7) {
case 0:
txtformat = "12 bit interface";
break;
case 1:
txtformat = "16 bit interface";
break;
case 2:
txtformat = "24 bit interface";
break;
default:
txtformat = "unknown format";
}
} else {
switch (format & 7) {
case 0:
txtformat = "8 colours";
break;
case 1:
txtformat = "512 colours";
break;
case 2:
txtformat = "4096 colours";
break;
case 4:
txtformat = "262144 colours (LT mode)";
break;
case 5:
txtformat = "16777216 colours";
break;
case 6:
txtformat = "262144 colours (FDPI-2 mode)";
break;
default:
txtformat = "unknown format";
}
}
PRINTKI("%s%s %s monitor detected: %s\n",
txtdual, txtcolour, txtmonitor, model);
PRINTKI(" id=%d, %dx%d pixels, %s\n",
id, width, height, txtformat);
refresh_rates_buf[0] = 0;
refresh_rates = *(u16 *)(par->lcd_table+62);
m = 1;
f = 0;
for (i = 0; i < 16; i++) {
if (refresh_rates & m) {
if (f == 0) {
sprintf(strbuf, "%d",
lcd_refresh_rates[i]);
f++;
} else {
sprintf(strbuf, ",%d",
lcd_refresh_rates[i]);
}
strcat(refresh_rates_buf, strbuf);
}
m = m << 1;
}
default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
PRINTKI(" supports refresh rates [%s], default %d Hz\n",
refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
/*
* We now need to determine the crtc parameters for the
* LCD monitor. This is tricky, because they are not stored
* individually in the BIOS. Instead, the BIOS contains a
* table of display modes that work for this monitor.
*
* The idea is that we search for a mode of the same dimensions
* as the dimensions of the LCD monitor. Say our LCD monitor
* is 800x600 pixels, we search for a 800x600 monitor.
* The CRTC parameters we find here are the ones that we need
* to use to simulate other resolutions on the LCD screen.
*/
lcdmodeptr = (u16 *)(par->lcd_table + 64);
while (*lcdmodeptr != 0) {
u32 modeptr;
u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
modeptr = bios_base + *lcdmodeptr;
mwidth = *((u16 *)(modeptr+0));
mheight = *((u16 *)(modeptr+2));
if (mwidth == width && mheight == height) {
par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
par->lcd_htotal = (par->lcd_htotal + 1) * 8;
par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
lcd_hsync_start = (lcd_hsync_start + 1) * 8;
par->lcd_hsync_len = par->lcd_hsync_len * 8;
par->lcd_vtotal++;
par->lcd_vdisp++;
lcd_vsync_start++;
par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
break;
}
lcdmodeptr++;
}
if (*lcdmodeptr == 0) {
PRINTKE("LCD monitor CRTC parameters not found!!!\n");
/* To do: Switch to CRT if possible. */
} else {
PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
par->lcd_hdisp,
par->lcd_hdisp + par->lcd_right_margin,
par->lcd_hdisp + par->lcd_right_margin
+ par->lcd_hsync_dly + par->lcd_hsync_len,
par->lcd_htotal,
par->lcd_vdisp,
par->lcd_vdisp + par->lcd_lower_margin,
par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
par->lcd_vtotal);
PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
par->lcd_pixclock,
par->lcd_hblank_len - (par->lcd_right_margin +
par->lcd_hsync_dly + par->lcd_hsync_len),
par->lcd_hdisp,
par->lcd_right_margin,
par->lcd_hsync_len,
par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
par->lcd_vdisp,
par->lcd_lower_margin,
par->lcd_vsync_len);
}
}
}
#endif /* CONFIG_FB_ATY_GENERIC_LCD */
static int init_from_bios(struct atyfb_par *par)
{
u32 bios_base, rom_addr;
int ret;
rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
/* The BIOS starts with 0xaa55. */
if (*((u16 *)bios_base) == 0xaa55) {
u8 *bios_ptr;
u16 rom_table_offset, freq_table_offset;
PLL_BLOCK_MACH64 pll_block;
PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
/* check for frequncy table */
bios_ptr = (u8*)bios_base;
rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
PRINTKI("BIOS frequency table:\n");
PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
pll_block.ref_freq, pll_block.ref_divider);
PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
pll_block.XCLK_max_freq, pll_block.SCLK_freq);
par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
par->pll_limits.ref_clk = pll_block.ref_freq/100;
par->pll_limits.ref_div = pll_block.ref_divider;
par->pll_limits.sclk = pll_block.SCLK_freq/100;
par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
#ifdef CONFIG_FB_ATY_GENERIC_LCD
aty_init_lcd(par, bios_base);
#endif
ret = 0;
} else {
PRINTKE("no BIOS frequency table found, use parameters\n");
ret = -ENXIO;
}
iounmap((void __iomem *)bios_base);
return ret;
}
#endif /* __i386__ */
static int atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info,
unsigned long addr)
{
struct atyfb_par *par = info->par;
u16 tmp;
unsigned long raddr;
struct resource *rrp;
int ret = 0;
raddr = addr + 0x7ff000UL;
rrp = &pdev->resource[2];
if ((rrp->flags & IORESOURCE_MEM) &&
request_mem_region(rrp->start, resource_size(rrp), "atyfb")) {
par->aux_start = rrp->start;
par->aux_size = resource_size(rrp);
raddr = rrp->start;
PRINTKI("using auxiliary register aperture\n");
}
info->fix.mmio_start = raddr;
/*
* By using strong UC we force the MTRR to never have an
* effect on the MMIO region on both non-PAT and PAT systems.
*/
par->ati_regbase = ioremap_uc(info->fix.mmio_start, 0x1000);
if (par->ati_regbase == NULL)
return -ENOMEM;
info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
/*
* Enable memory-space accesses using config-space
* command register.
*/
pci_read_config_word(pdev, PCI_COMMAND, &tmp);
if (!(tmp & PCI_COMMAND_MEMORY)) {
tmp |= PCI_COMMAND_MEMORY;
pci_write_config_word(pdev, PCI_COMMAND, tmp);
}
#ifdef __BIG_ENDIAN
/* Use the big-endian aperture */
addr += 0x800000;
#endif
/* Map in frame buffer */
info->fix.smem_start = addr;
/*
* The framebuffer is not always 8 MiB, that's just the size of the
* PCI BAR. We temporarily abuse smem_len here to store the size
* of the BAR. aty_init() will later correct it to match the actual
* framebuffer size.
*
* On devices that don't have the auxiliary register aperture, the
* registers are housed at the top end of the framebuffer PCI BAR.
* aty_fudge_framebuffer_len() is used to reduce smem_len to not
* overlap with the registers.
*/
info->fix.smem_len = 0x800000;
aty_fudge_framebuffer_len(info);
info->screen_base = ioremap_wc(info->fix.smem_start,
info->fix.smem_len);
if (info->screen_base == NULL) {
ret = -ENOMEM;
goto atyfb_setup_generic_fail;
}
ret = correct_chipset(par);
if (ret)
goto atyfb_setup_generic_fail;
#ifdef __i386__
ret = init_from_bios(par);
if (ret)
goto atyfb_setup_generic_fail;
#endif
/* according to ATI, we should use clock 3 for acelerated mode */
par->clk_wr_offset = 3;
return 0;
atyfb_setup_generic_fail:
iounmap(par->ati_regbase);
par->ati_regbase = NULL;
if (info->screen_base) {
iounmap(info->screen_base);
info->screen_base = NULL;
}
return ret;
}
#endif /* !__sparc__ */
static int atyfb_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
unsigned long addr, res_start, res_size;
struct fb_info *info;
struct resource *rp;
struct atyfb_par *par;
int rc;
rc = aperture_remove_conflicting_pci_devices(pdev, "atyfb");
if (rc)
return rc;
/* Enable device in PCI config */
if (pci_enable_device(pdev)) {
PRINTKE("Cannot enable PCI device\n");
return -ENXIO;
}
/* Find which resource to use */
rp = &pdev->resource[0];
if (rp->flags & IORESOURCE_IO)
rp = &pdev->resource[1];
addr = rp->start;
if (!addr)
return -ENXIO;
/* Reserve space */
res_start = rp->start;
res_size = resource_size(rp);
if (!request_mem_region(res_start, res_size, "atyfb"))
return -EBUSY;
/* Allocate framebuffer */
info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
if (!info)
return -ENOMEM;
par = info->par;
par->bus_type = PCI;
info->fix = atyfb_fix;
info->device = &pdev->dev;
par->pci_id = pdev->device;
par->res_start = res_start;
par->res_size = res_size;
par->irq = pdev->irq;
par->pdev = pdev;
/* Setup "info" structure */
#ifdef __sparc__
rc = atyfb_setup_sparc(pdev, info, addr);
#else
rc = atyfb_setup_generic(pdev, info, addr);
#endif
if (rc)
goto err_release_mem;
pci_set_drvdata(pdev, info);
/* Init chip & register framebuffer */
rc = aty_init(info);
if (rc)
goto err_release_io;
#ifdef __sparc__
/*
* Add /dev/fb mmap values.
*/
par->mmap_map[0].voff = 0x8000000000000000UL;
par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
par->mmap_map[0].size = info->fix.smem_len;
par->mmap_map[0].prot_mask = _PAGE_CACHE;
par->mmap_map[0].prot_flag = _PAGE_E;
par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
par->mmap_map[1].size = PAGE_SIZE;
par->mmap_map[1].prot_mask = _PAGE_CACHE;
par->mmap_map[1].prot_flag = _PAGE_E;
#endif /* __sparc__ */
mutex_lock(&reboot_lock);
if (!reboot_info)
reboot_info = info;
mutex_unlock(&reboot_lock);
return 0;
err_release_io:
#ifdef __sparc__
kfree(par->mmap_map);
#else
if (par->ati_regbase)
iounmap(par->ati_regbase);
if (info->screen_base)
iounmap(info->screen_base);
#endif
err_release_mem:
if (par->aux_start)
release_mem_region(par->aux_start, par->aux_size);
release_mem_region(par->res_start, par->res_size);
framebuffer_release(info);
return rc;
}
#endif /* CONFIG_PCI */
#ifdef CONFIG_ATARI
static int __init atyfb_atari_probe(void)
{
struct atyfb_par *par;
struct fb_info *info;
int m64_num;
u32 clock_r;
int num_found = 0;
for (m64_num = 0; m64_num < mach64_count; m64_num++) {
if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
!phys_guiregbase[m64_num]) {
PRINTKI("phys_*[%d] parameters not set => "
"returning early. \n", m64_num);
continue;
}
info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
if (!info)
return -ENOMEM;
par = info->par;
info->fix = atyfb_fix;
par->irq = (unsigned int) -1; /* something invalid */
/*
* Map the video memory (physical address given)
* to somewhere in the kernel address space.
*/
info->screen_base = ioremap_wc(phys_vmembase[m64_num],
phys_size[m64_num]);
info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
0xFC00ul;
info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
aty_st_le32(CLOCK_CNTL, 0x12345678, par);
clock_r = aty_ld_le32(CLOCK_CNTL, par);
switch (clock_r & 0x003F) {
case 0x12:
par->clk_wr_offset = 3; /* */
break;
case 0x34:
par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
break;
case 0x16:
par->clk_wr_offset = 1; /* */
break;
case 0x38:
par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
break;
}
/* Fake pci_id for correct_chipset() */
switch (aty_ld_le32(CNFG_CHIP_ID, par) & CFG_CHIP_TYPE) {
case 0x00d7:
par->pci_id = PCI_CHIP_MACH64GX;
break;
case 0x0057:
par->pci_id = PCI_CHIP_MACH64CX;
break;
default:
break;
}
if (correct_chipset(par) || aty_init(info)) {
iounmap(info->screen_base);
iounmap(par->ati_regbase);
framebuffer_release(info);
} else {
num_found++;
}
}
return num_found ? 0 : -ENXIO;
}
#endif /* CONFIG_ATARI */
#ifdef CONFIG_PCI
static void atyfb_remove(struct fb_info *info)
{
struct atyfb_par *par = (struct atyfb_par *) info->par;
/* restore video mode */
aty_set_crtc(par, &par->saved_crtc);
par->pll_ops->set_pll(info, &par->saved_pll);
#ifdef CONFIG_FB_ATY_BACKLIGHT
if (M64_HAS(MOBIL_BUS))
aty_bl_exit(info->bl_dev);
#endif
unregister_framebuffer(info);
arch_phys_wc_del(par->wc_cookie);
#ifndef __sparc__
if (par->ati_regbase)
iounmap(par->ati_regbase);
if (info->screen_base)
iounmap(info->screen_base);
#ifdef __BIG_ENDIAN
if (info->sprite.addr)
iounmap(info->sprite.addr);
#endif
#endif
#ifdef __sparc__
kfree(par->mmap_map);
#endif
if (par->aux_start)
release_mem_region(par->aux_start, par->aux_size);
if (par->res_start)
release_mem_region(par->res_start, par->res_size);
framebuffer_release(info);
}
static void atyfb_pci_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
mutex_lock(&reboot_lock);
if (reboot_info == info)
reboot_info = NULL;
mutex_unlock(&reboot_lock);
atyfb_remove(info);
}
static const struct pci_device_id atyfb_pci_tbl[] = {
#ifdef CONFIG_FB_ATY_GX
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GX) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64CX) },
#endif /* CONFIG_FB_ATY_GX */
#ifdef CONFIG_FB_ATY_CT
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64CT) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64ET) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LT) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VT) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GT) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VU) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GU) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LG) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VV) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GV) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GW) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GY) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GZ) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GB) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GD) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GI) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GP) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GQ) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LB) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LD) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LI) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LP) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LQ) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GM) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GN) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GO) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GL) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GR) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GS) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LM) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LN) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LR) },
{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LS) },
#endif /* CONFIG_FB_ATY_CT */
{ }
};
MODULE_DEVICE_TABLE(pci, atyfb_pci_tbl);
static struct pci_driver atyfb_driver = {
.name = "atyfb",
.id_table = atyfb_pci_tbl,
.probe = atyfb_pci_probe,
.remove = atyfb_pci_remove,
.driver.pm = &atyfb_pci_pm_ops,
};
#endif /* CONFIG_PCI */
#ifndef MODULE
static int __init atyfb_setup(char *options)
{
char *this_opt;
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!strncmp(this_opt, "noaccel", 7)) {
noaccel = true;
} else if (!strncmp(this_opt, "nomtrr", 6)) {
nomtrr = true;
} else if (!strncmp(this_opt, "vram:", 5))
vram = simple_strtoul(this_opt + 5, NULL, 0);
else if (!strncmp(this_opt, "pll:", 4))
pll = simple_strtoul(this_opt + 4, NULL, 0);
else if (!strncmp(this_opt, "mclk:", 5))
mclk = simple_strtoul(this_opt + 5, NULL, 0);
else if (!strncmp(this_opt, "xclk:", 5))
xclk = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "comp_sync:", 10))
comp_sync = simple_strtoul(this_opt+10, NULL, 0);
else if (!strncmp(this_opt, "backlight:", 10))
backlight = simple_strtoul(this_opt+10, NULL, 0);
#ifdef CONFIG_PPC
else if (!strncmp(this_opt, "vmode:", 6)) {
unsigned int vmode =
simple_strtoul(this_opt + 6, NULL, 0);
if (vmode > 0 && vmode <= VMODE_MAX)
default_vmode = vmode;
} else if (!strncmp(this_opt, "cmode:", 6)) {
unsigned int cmode =
simple_strtoul(this_opt + 6, NULL, 0);
switch (cmode) {
case 0:
case 8:
default_cmode = CMODE_8;
break;
case 15:
case 16:
default_cmode = CMODE_16;
break;
case 24:
case 32:
default_cmode = CMODE_32;
break;
}
}
#endif
#ifdef CONFIG_ATARI
/*
* Why do we need this silly Mach64 argument?
* We are already here because of mach64= so its redundant.
*/
else if (MACH_IS_ATARI
&& (!strncmp(this_opt, "Mach64:", 7))) {
static unsigned char m64_num;
static char mach64_str[80];
strscpy(mach64_str, this_opt + 7, sizeof(mach64_str));
if (!store_video_par(mach64_str, m64_num)) {
m64_num++;
mach64_count = m64_num;
}
}
#endif
else
mode = this_opt;
}
return 0;
}
#endif /* MODULE */
static int atyfb_reboot_notify(struct notifier_block *nb,
unsigned long code, void *unused)
{
struct atyfb_par *par;
if (code != SYS_RESTART)
return NOTIFY_DONE;
mutex_lock(&reboot_lock);
if (!reboot_info)
goto out;
lock_fb_info(reboot_info);
par = reboot_info->par;
/*
* HP OmniBook 500's BIOS doesn't like the state of the
* hardware after atyfb has been used. Restore the hardware
* to the original state to allow successful reboots.
*/
aty_set_crtc(par, &par->saved_crtc);
par->pll_ops->set_pll(reboot_info, &par->saved_pll);
unlock_fb_info(reboot_info);
out:
mutex_unlock(&reboot_lock);
return NOTIFY_DONE;
}
static struct notifier_block atyfb_reboot_notifier = {
.notifier_call = atyfb_reboot_notify,
};
static const struct dmi_system_id atyfb_reboot_ids[] __initconst = {
{
.ident = "HP OmniBook 500",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
DMI_MATCH(DMI_PRODUCT_NAME, "HP OmniBook PC"),
DMI_MATCH(DMI_PRODUCT_VERSION, "HP OmniBook 500 FA"),
},
},
{ }
};
static bool registered_notifier = false;
static int __init atyfb_init(void)
{
int err1 = 1, err2 = 1;
#ifndef MODULE
char *option = NULL;
#endif
if (fb_modesetting_disabled("atyfb"))
return -ENODEV;
#ifndef MODULE
if (fb_get_options("atyfb", &option))
return -ENODEV;
atyfb_setup(option);
#endif
#ifdef CONFIG_PCI
err1 = pci_register_driver(&atyfb_driver);
#endif
#ifdef CONFIG_ATARI
err2 = atyfb_atari_probe();
#endif
if (err1 && err2)
return -ENODEV;
if (dmi_check_system(atyfb_reboot_ids)) {
register_reboot_notifier(&atyfb_reboot_notifier);
registered_notifier = true;
}
return 0;
}
static void __exit atyfb_exit(void)
{
if (registered_notifier)
unregister_reboot_notifier(&atyfb_reboot_notifier);
#ifdef CONFIG_PCI
pci_unregister_driver(&atyfb_driver);
#endif
}
module_init(atyfb_init);
module_exit(atyfb_exit);
MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
MODULE_LICENSE("GPL");
module_param(noaccel, bool, 0);
MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
module_param(vram, int, 0);
MODULE_PARM_DESC(vram, "int: override size of video ram");
module_param(pll, int, 0);
MODULE_PARM_DESC(pll, "int: override video clock");
module_param(mclk, int, 0);
MODULE_PARM_DESC(mclk, "int: override memory clock");
module_param(xclk, int, 0);
MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
module_param(comp_sync, int, 0);
MODULE_PARM_DESC(comp_sync, "Set composite sync signal to low (0) or high (1)");
module_param(mode, charp, 0);
MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
module_param(nomtrr, bool, 0);
MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
| linux-master | drivers/video/fbdev/aty/atyfb_base.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Portions Copyright (c) 2001 Matrox Graphics Inc.
*
* Version: 1.65 2002/08/14
*
* MTRR stuff: 1998 Tom Rini <[email protected]>
*
* Contributors: "menion?" <[email protected]>
* Betatesting, fixes, ideas
*
* "Kurt Garloff" <[email protected]>
* Betatesting, fixes, ideas, videomodes, videomodes timmings
*
* "Tom Rini" <[email protected]>
* MTRR stuff, PPC cleanups, betatesting, fixes, ideas
*
* "Bibek Sahu" <[email protected]>
* Access device through readb|w|l and write b|w|l
* Extensive debugging stuff
*
* "Daniel Haun" <[email protected]>
* Testing, hardware cursor fixes
*
* "Scott Wood" <[email protected]>
* Fixes
*
* "Gerd Knorr" <[email protected]>
* Betatesting
*
* "Kelly French" <[email protected]>
* "Fernando Herrera" <[email protected]>
* Betatesting, bug reporting
*
* "Pablo Bianucci" <[email protected]>
* Fixes, ideas, betatesting
*
* "Inaky Perez Gonzalez" <[email protected]>
* Fixes, enhandcements, ideas, betatesting
*
* "Ryuichi Oikawa" <[email protected]>
* PPC betatesting, PPC support, backward compatibility
*
* "Paul Womar" <[email protected]>
* "Owen Waller" <[email protected]>
* PPC betatesting
*
* "Thomas Pornin" <[email protected]>
* Alpha betatesting
*
* "Pieter van Leuven" <[email protected]>
* "Ulf Jaenicke-Roessler" <[email protected]>
* G100 testing
*
* "H. Peter Arvin" <[email protected]>
* Ideas
*
* "Cort Dougan" <[email protected]>
* CHRP fixes and PReP cleanup
*
* "Mark Vojkovich" <[email protected]>
* G400 support
*
* "Samuel Hocevar" <[email protected]>
* Fixes
*
* "Anton Altaparmakov" <[email protected]>
* G400 MAX/non-MAX distinction
*
* "Ken Aaker" <[email protected]>
* memtype extension (needed for GXT130P RS/6000 adapter)
*
* "Uns Lider" <[email protected]>
* G100 PLNWT fixes
*
* "Denis Zaitsev" <[email protected]>
* Fixes
*
* "Mike Pieper" <[email protected]>
* TVOut enhandcements, V4L2 control interface.
*
* "Diego Biurrun" <[email protected]>
* DFP testing
*
* (following author is not in any relation with this code, but his code
* is included in this driver)
*
* Based on framebuffer driver for VBE 2.0 compliant graphic boards
* (c) 1998 Gerd Knorr <[email protected]>
*
* (following author is not in any relation with this code, but his ideas
* were used when writing this driver)
*
* FreeVBE/AF (Matrox), "Shawn Hargreaves" <[email protected]>
*
*/
#include <linux/aperture.h>
#include <linux/version.h>
#include "matroxfb_base.h"
#include "matroxfb_misc.h"
#include "matroxfb_accel.h"
#include "matroxfb_DAC1064.h"
#include "matroxfb_Ti3026.h"
#include "matroxfb_maven.h"
#include "matroxfb_crtc2.h"
#include "matroxfb_g450.h"
#include <linux/matroxfb.h>
#include <linux/interrupt.h>
#include <linux/nvram.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#ifdef CONFIG_PPC_PMAC
#include <asm/machdep.h>
static int default_vmode = VMODE_NVRAM;
static int default_cmode = CMODE_NVRAM;
#endif
static void matroxfb_unregister_device(struct matrox_fb_info* minfo);
/* --------------------------------------------------------------------- */
/*
* card parameters
*/
/* --------------------------------------------------------------------- */
static struct fb_var_screeninfo vesafb_defined = {
640,480,640,480,/* W,H, W, H (virtual) load xres,xres_virtual*/
0,0, /* virtual -> visible no offset */
8, /* depth -> load bits_per_pixel */
0, /* greyscale ? */
{0,0,0}, /* R */
{0,0,0}, /* G */
{0,0,0}, /* B */
{0,0,0}, /* transparency */
0, /* standard pixel format */
FB_ACTIVATE_NOW,
-1,-1,
FB_ACCELF_TEXT, /* accel flags */
39721L,48L,16L,33L,10L,
96L,2L,~0, /* No sync info */
FB_VMODE_NONINTERLACED,
};
/* --------------------------------------------------------------------- */
static void update_crtc2(struct matrox_fb_info *minfo, unsigned int pos)
{
struct matroxfb_dh_fb_info *info = minfo->crtc2.info;
/* Make sure that displays are compatible */
if (info && (info->fbcon.var.bits_per_pixel == minfo->fbcon.var.bits_per_pixel)
&& (info->fbcon.var.xres_virtual == minfo->fbcon.var.xres_virtual)
&& (info->fbcon.var.green.length == minfo->fbcon.var.green.length)
) {
switch (minfo->fbcon.var.bits_per_pixel) {
case 16:
case 32:
pos = pos * 8;
if (info->interlaced) {
mga_outl(0x3C2C, pos);
mga_outl(0x3C28, pos + minfo->fbcon.var.xres_virtual * minfo->fbcon.var.bits_per_pixel / 8);
} else {
mga_outl(0x3C28, pos);
}
break;
}
}
}
static void matroxfb_crtc1_panpos(struct matrox_fb_info *minfo)
{
if (minfo->crtc1.panpos >= 0) {
unsigned long flags;
int panpos;
matroxfb_DAC_lock_irqsave(flags);
panpos = minfo->crtc1.panpos;
if (panpos >= 0) {
unsigned int extvga_reg;
minfo->crtc1.panpos = -1; /* No update pending anymore */
extvga_reg = mga_inb(M_EXTVGA_INDEX);
mga_setr(M_EXTVGA_INDEX, 0x00, panpos);
if (extvga_reg != 0x00) {
mga_outb(M_EXTVGA_INDEX, extvga_reg);
}
}
matroxfb_DAC_unlock_irqrestore(flags);
}
}
static irqreturn_t matrox_irq(int irq, void *dev_id)
{
u_int32_t status;
int handled = 0;
struct matrox_fb_info *minfo = dev_id;
status = mga_inl(M_STATUS);
if (status & 0x20) {
mga_outl(M_ICLEAR, 0x20);
minfo->crtc1.vsync.cnt++;
matroxfb_crtc1_panpos(minfo);
wake_up_interruptible(&minfo->crtc1.vsync.wait);
handled = 1;
}
if (status & 0x200) {
mga_outl(M_ICLEAR, 0x200);
minfo->crtc2.vsync.cnt++;
wake_up_interruptible(&minfo->crtc2.vsync.wait);
handled = 1;
}
return IRQ_RETVAL(handled);
}
int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable)
{
u_int32_t bm;
if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
bm = 0x220;
else
bm = 0x020;
if (!test_and_set_bit(0, &minfo->irq_flags)) {
if (request_irq(minfo->pcidev->irq, matrox_irq,
IRQF_SHARED, "matroxfb", minfo)) {
clear_bit(0, &minfo->irq_flags);
return -EINVAL;
}
/* Clear any pending field interrupts */
mga_outl(M_ICLEAR, bm);
mga_outl(M_IEN, mga_inl(M_IEN) | bm);
} else if (reenable) {
u_int32_t ien;
ien = mga_inl(M_IEN);
if ((ien & bm) != bm) {
printk(KERN_DEBUG "matroxfb: someone disabled IRQ [%08X]\n", ien);
mga_outl(M_IEN, ien | bm);
}
}
return 0;
}
static void matroxfb_disable_irq(struct matrox_fb_info *minfo)
{
if (test_and_clear_bit(0, &minfo->irq_flags)) {
/* Flush pending pan-at-vbl request... */
matroxfb_crtc1_panpos(minfo);
if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
mga_outl(M_IEN, mga_inl(M_IEN) & ~0x220);
else
mga_outl(M_IEN, mga_inl(M_IEN) & ~0x20);
free_irq(minfo->pcidev->irq, minfo);
}
}
int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc)
{
struct matrox_vsync *vs;
unsigned int cnt;
int ret;
switch (crtc) {
case 0:
vs = &minfo->crtc1.vsync;
break;
case 1:
if (minfo->devflags.accelerator != FB_ACCEL_MATROX_MGAG400) {
return -ENODEV;
}
vs = &minfo->crtc2.vsync;
break;
default:
return -ENODEV;
}
ret = matroxfb_enable_irq(minfo, 0);
if (ret) {
return ret;
}
cnt = vs->cnt;
ret = wait_event_interruptible_timeout(vs->wait, cnt != vs->cnt, HZ/10);
if (ret < 0) {
return ret;
}
if (ret == 0) {
matroxfb_enable_irq(minfo, 1);
return -ETIMEDOUT;
}
return 0;
}
/* --------------------------------------------------------------------- */
static void matrox_pan_var(struct matrox_fb_info *minfo,
struct fb_var_screeninfo *var)
{
unsigned int pos;
unsigned short p0, p1, p2;
unsigned int p3;
int vbl;
unsigned long flags;
CRITFLAGS
DBG(__func__)
if (minfo->dead)
return;
minfo->fbcon.var.xoffset = var->xoffset;
minfo->fbcon.var.yoffset = var->yoffset;
pos = (minfo->fbcon.var.yoffset * minfo->fbcon.var.xres_virtual + minfo->fbcon.var.xoffset) * minfo->curr.final_bppShift / 32;
pos += minfo->curr.ydstorg.chunks;
p0 = minfo->hw.CRTC[0x0D] = pos & 0xFF;
p1 = minfo->hw.CRTC[0x0C] = (pos & 0xFF00) >> 8;
p2 = minfo->hw.CRTCEXT[0] = (minfo->hw.CRTCEXT[0] & 0xB0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40);
p3 = minfo->hw.CRTCEXT[8] = pos >> 21;
/* FB_ACTIVATE_VBL and we can acquire interrupts? Honor FB_ACTIVATE_VBL then... */
vbl = (var->activate & FB_ACTIVATE_VBL) && (matroxfb_enable_irq(minfo, 0) == 0);
CRITBEGIN
matroxfb_DAC_lock_irqsave(flags);
mga_setr(M_CRTC_INDEX, 0x0D, p0);
mga_setr(M_CRTC_INDEX, 0x0C, p1);
if (minfo->devflags.support32MB)
mga_setr(M_EXTVGA_INDEX, 0x08, p3);
if (vbl) {
minfo->crtc1.panpos = p2;
} else {
/* Abort any pending change */
minfo->crtc1.panpos = -1;
mga_setr(M_EXTVGA_INDEX, 0x00, p2);
}
matroxfb_DAC_unlock_irqrestore(flags);
update_crtc2(minfo, pos);
CRITEND
}
static void matroxfb_remove(struct matrox_fb_info *minfo, int dummy)
{
/* Currently we are holding big kernel lock on all dead & usecount updates.
* Destroy everything after all users release it. Especially do not unregister
* framebuffer and iounmap memory, neither fbmem nor fbcon-cfb* does not check
* for device unplugged when in use.
* In future we should point mmio.vbase & video.vbase somewhere where we can
* write data without causing too much damage...
*/
minfo->dead = 1;
if (minfo->usecount) {
/* destroy it later */
return;
}
matroxfb_unregister_device(minfo);
unregister_framebuffer(&minfo->fbcon);
matroxfb_g450_shutdown(minfo);
arch_phys_wc_del(minfo->wc_cookie);
iounmap(minfo->mmio.vbase.vaddr);
iounmap(minfo->video.vbase.vaddr);
release_mem_region(minfo->video.base, minfo->video.len_maximum);
release_mem_region(minfo->mmio.base, 16384);
kfree(minfo);
}
/*
* Open/Release the frame buffer device
*/
static int matroxfb_open(struct fb_info *info, int user)
{
struct matrox_fb_info *minfo = info2minfo(info);
DBG_LOOP(__func__)
if (minfo->dead) {
return -ENXIO;
}
minfo->usecount++;
if (user) {
minfo->userusecount++;
}
return(0);
}
static int matroxfb_release(struct fb_info *info, int user)
{
struct matrox_fb_info *minfo = info2minfo(info);
DBG_LOOP(__func__)
if (user) {
if (0 == --minfo->userusecount) {
matroxfb_disable_irq(minfo);
}
}
if (!(--minfo->usecount) && minfo->dead) {
matroxfb_remove(minfo, 0);
}
return(0);
}
static int matroxfb_pan_display(struct fb_var_screeninfo *var,
struct fb_info* info) {
struct matrox_fb_info *minfo = info2minfo(info);
DBG(__func__)
matrox_pan_var(minfo, var);
return 0;
}
static int matroxfb_get_final_bppShift(const struct matrox_fb_info *minfo,
int bpp)
{
int bppshft2;
DBG(__func__)
bppshft2 = bpp;
if (!bppshft2) {
return 8;
}
if (isInterleave(minfo))
bppshft2 >>= 1;
if (minfo->devflags.video64bits)
bppshft2 >>= 1;
return bppshft2;
}
static int matroxfb_test_and_set_rounding(const struct matrox_fb_info *minfo,
int xres, int bpp)
{
int over;
int rounding;
DBG(__func__)
switch (bpp) {
case 0: return xres;
case 4: rounding = 128;
break;
case 8: rounding = 64; /* doc says 64; 32 is OK for G400 */
break;
case 16: rounding = 32;
break;
case 24: rounding = 64; /* doc says 64; 32 is OK for G400 */
break;
default: rounding = 16;
/* on G400, 16 really does not work */
if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400)
rounding = 32;
break;
}
if (isInterleave(minfo)) {
rounding *= 2;
}
over = xres % rounding;
if (over)
xres += rounding-over;
return xres;
}
static int matroxfb_pitch_adjust(const struct matrox_fb_info *minfo, int xres,
int bpp)
{
const int* width;
int xres_new;
DBG(__func__)
if (!bpp) return xres;
width = minfo->capable.vxres;
if (minfo->devflags.precise_width) {
while (*width) {
if ((*width >= xres) && (matroxfb_test_and_set_rounding(minfo, *width, bpp) == *width)) {
break;
}
width++;
}
xres_new = *width;
} else {
xres_new = matroxfb_test_and_set_rounding(minfo, xres, bpp);
}
return xres_new;
}
static int matroxfb_get_cmap_len(struct fb_var_screeninfo *var) {
DBG(__func__)
switch (var->bits_per_pixel) {
case 4:
return 16; /* pseudocolor... 16 entries HW palette */
case 8:
return 256; /* pseudocolor... 256 entries HW palette */
case 16:
return 16; /* directcolor... 16 entries SW palette */
/* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */
case 24:
return 16; /* directcolor... 16 entries SW palette */
/* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */
case 32:
return 16; /* directcolor... 16 entries SW palette */
/* Mystique: truecolor, 16 entries SW palette, HW palette hardwired into 1:1 mapping */
}
return 16; /* return something reasonable... or panic()? */
}
static int matroxfb_decode_var(const struct matrox_fb_info *minfo,
struct fb_var_screeninfo *var, int *visual,
int *video_cmap_len, unsigned int* ydstorg)
{
struct RGBT {
unsigned char bpp;
struct {
unsigned char offset,
length;
} red,
green,
blue,
transp;
signed char visual;
};
static const struct RGBT table[]= {
{ 8,{ 0,8},{0,8},{0,8},{ 0,0},MX_VISUAL_PSEUDOCOLOR},
{15,{10,5},{5,5},{0,5},{15,1},MX_VISUAL_DIRECTCOLOR},
{16,{11,5},{5,6},{0,5},{ 0,0},MX_VISUAL_DIRECTCOLOR},
{24,{16,8},{8,8},{0,8},{ 0,0},MX_VISUAL_DIRECTCOLOR},
{32,{16,8},{8,8},{0,8},{24,8},MX_VISUAL_DIRECTCOLOR}
};
struct RGBT const *rgbt;
unsigned int bpp = var->bits_per_pixel;
unsigned int vramlen;
unsigned int memlen;
DBG(__func__)
switch (bpp) {
case 4: if (!minfo->capable.cfb4) return -EINVAL;
break;
case 8: break;
case 16: break;
case 24: break;
case 32: break;
default: return -EINVAL;
}
*ydstorg = 0;
vramlen = minfo->video.len_usable;
if (var->yres_virtual < var->yres)
var->yres_virtual = var->yres;
if (var->xres_virtual < var->xres)
var->xres_virtual = var->xres;
var->xres_virtual = matroxfb_pitch_adjust(minfo, var->xres_virtual, bpp);
memlen = var->xres_virtual * bpp * var->yres_virtual / 8;
if (memlen > vramlen) {
var->yres_virtual = vramlen * 8 / (var->xres_virtual * bpp);
memlen = var->xres_virtual * bpp * var->yres_virtual / 8;
}
/* There is hardware bug that no line can cross 4MB boundary */
/* give up for CFB24, it is impossible to easy workaround it */
/* for other try to do something */
if (!minfo->capable.cross4MB && (memlen > 0x400000)) {
if (bpp == 24) {
/* sorry */
} else {
unsigned int linelen;
unsigned int m1 = linelen = var->xres_virtual * bpp / 8;
unsigned int m2 = PAGE_SIZE; /* or 128 if you do not need PAGE ALIGNED address */
unsigned int max_yres;
while (m1) {
while (m2 >= m1) m2 -= m1;
swap(m1, m2);
}
m2 = linelen * PAGE_SIZE / m2;
*ydstorg = m2 = 0x400000 % m2;
max_yres = (vramlen - m2) / linelen;
if (var->yres_virtual > max_yres)
var->yres_virtual = max_yres;
}
}
/* YDSTLEN contains only signed 16bit value */
if (var->yres_virtual > 32767)
var->yres_virtual = 32767;
/* we must round yres/xres down, we already rounded y/xres_virtual up
if it was possible. We should return -EINVAL, but I disagree */
if (var->yres_virtual < var->yres)
var->yres = var->yres_virtual;
if (var->xres_virtual < var->xres)
var->xres = var->xres_virtual;
if (var->xoffset + var->xres > var->xres_virtual)
var->xoffset = var->xres_virtual - var->xres;
if (var->yoffset + var->yres > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
if (bpp == 16 && var->green.length == 5) {
bpp--; /* an artificial value - 15 */
}
for (rgbt = table; rgbt->bpp < bpp; rgbt++);
#define SETCLR(clr)\
var->clr.offset = rgbt->clr.offset;\
var->clr.length = rgbt->clr.length
SETCLR(red);
SETCLR(green);
SETCLR(blue);
SETCLR(transp);
#undef SETCLR
*visual = rgbt->visual;
if (bpp > 8)
dprintk("matroxfb: truecolor: "
"size=%d:%d:%d:%d, shift=%d:%d:%d:%d\n",
var->transp.length, var->red.length, var->green.length, var->blue.length,
var->transp.offset, var->red.offset, var->green.offset, var->blue.offset);
*video_cmap_len = matroxfb_get_cmap_len(var);
dprintk(KERN_INFO "requested %d*%d/%dbpp (%d*%d)\n", var->xres, var->yres, var->bits_per_pixel,
var->xres_virtual, var->yres_virtual);
return 0;
}
static int matroxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *fb_info)
{
struct matrox_fb_info* minfo = container_of(fb_info, struct matrox_fb_info, fbcon);
DBG(__func__)
/*
* Set a single color register. The values supplied are
* already rounded down to the hardware's capabilities
* (according to the entries in the `var' structure). Return
* != 0 for invalid regno.
*/
if (regno >= minfo->curr.cmap_len)
return 1;
if (minfo->fbcon.var.grayscale) {
/* gray = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
red = CNVT_TOHW(red, minfo->fbcon.var.red.length);
green = CNVT_TOHW(green, minfo->fbcon.var.green.length);
blue = CNVT_TOHW(blue, minfo->fbcon.var.blue.length);
transp = CNVT_TOHW(transp, minfo->fbcon.var.transp.length);
switch (minfo->fbcon.var.bits_per_pixel) {
case 4:
case 8:
mga_outb(M_DAC_REG, regno);
mga_outb(M_DAC_VAL, red);
mga_outb(M_DAC_VAL, green);
mga_outb(M_DAC_VAL, blue);
break;
case 16:
if (regno >= 16)
break;
{
u_int16_t col =
(red << minfo->fbcon.var.red.offset) |
(green << minfo->fbcon.var.green.offset) |
(blue << minfo->fbcon.var.blue.offset) |
(transp << minfo->fbcon.var.transp.offset); /* for 1:5:5:5 */
minfo->cmap[regno] = col | (col << 16);
}
break;
case 24:
case 32:
if (regno >= 16)
break;
minfo->cmap[regno] =
(red << minfo->fbcon.var.red.offset) |
(green << minfo->fbcon.var.green.offset) |
(blue << minfo->fbcon.var.blue.offset) |
(transp << minfo->fbcon.var.transp.offset); /* 8:8:8:8 */
break;
}
return 0;
}
static void matroxfb_init_fix(struct matrox_fb_info *minfo)
{
struct fb_fix_screeninfo *fix = &minfo->fbcon.fix;
DBG(__func__)
strcpy(fix->id,"MATROX");
fix->xpanstep = 8; /* 8 for 8bpp, 4 for 16bpp, 2 for 32bpp */
fix->ypanstep = 1;
fix->ywrapstep = 0;
fix->mmio_start = minfo->mmio.base;
fix->mmio_len = minfo->mmio.len;
fix->accel = minfo->devflags.accelerator;
}
static void matroxfb_update_fix(struct matrox_fb_info *minfo)
{
struct fb_fix_screeninfo *fix = &minfo->fbcon.fix;
DBG(__func__)
mutex_lock(&minfo->fbcon.mm_lock);
fix->smem_start = minfo->video.base + minfo->curr.ydstorg.bytes;
fix->smem_len = minfo->video.len_usable - minfo->curr.ydstorg.bytes;
mutex_unlock(&minfo->fbcon.mm_lock);
}
static int matroxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
int err;
int visual;
int cmap_len;
unsigned int ydstorg;
struct matrox_fb_info *minfo = info2minfo(info);
if (minfo->dead) {
return -ENXIO;
}
if ((err = matroxfb_decode_var(minfo, var, &visual, &cmap_len, &ydstorg)) != 0)
return err;
return 0;
}
static int matroxfb_set_par(struct fb_info *info)
{
int err;
int visual;
int cmap_len;
unsigned int ydstorg;
struct fb_var_screeninfo *var;
struct matrox_fb_info *minfo = info2minfo(info);
DBG(__func__)
if (minfo->dead) {
return -ENXIO;
}
var = &info->var;
if ((err = matroxfb_decode_var(minfo, var, &visual, &cmap_len, &ydstorg)) != 0)
return err;
minfo->fbcon.screen_base = vaddr_va(minfo->video.vbase) + ydstorg;
matroxfb_update_fix(minfo);
minfo->fbcon.fix.visual = visual;
minfo->fbcon.fix.type = FB_TYPE_PACKED_PIXELS;
minfo->fbcon.fix.type_aux = 0;
minfo->fbcon.fix.line_length = (var->xres_virtual * var->bits_per_pixel) >> 3;
{
unsigned int pos;
minfo->curr.cmap_len = cmap_len;
ydstorg += minfo->devflags.ydstorg;
minfo->curr.ydstorg.bytes = ydstorg;
minfo->curr.ydstorg.chunks = ydstorg >> (isInterleave(minfo) ? 3 : 2);
if (var->bits_per_pixel == 4)
minfo->curr.ydstorg.pixels = ydstorg;
else
minfo->curr.ydstorg.pixels = (ydstorg * 8) / var->bits_per_pixel;
minfo->curr.final_bppShift = matroxfb_get_final_bppShift(minfo, var->bits_per_pixel);
{ struct my_timming mt;
struct matrox_hw_state* hw;
int out;
matroxfb_var2my(var, &mt);
mt.crtc = MATROXFB_SRC_CRTC1;
/* CRTC1 delays */
switch (var->bits_per_pixel) {
case 0: mt.delay = 31 + 0; break;
case 16: mt.delay = 21 + 8; break;
case 24: mt.delay = 17 + 8; break;
case 32: mt.delay = 16 + 8; break;
default: mt.delay = 31 + 8; break;
}
hw = &minfo->hw;
down_read(&minfo->altout.lock);
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
minfo->outputs[out].output->compute) {
minfo->outputs[out].output->compute(minfo->outputs[out].data, &mt);
}
}
up_read(&minfo->altout.lock);
minfo->crtc1.pixclock = mt.pixclock;
minfo->crtc1.mnp = mt.mnp;
minfo->hw_switch->init(minfo, &mt);
pos = (var->yoffset * var->xres_virtual + var->xoffset) * minfo->curr.final_bppShift / 32;
pos += minfo->curr.ydstorg.chunks;
hw->CRTC[0x0D] = pos & 0xFF;
hw->CRTC[0x0C] = (pos & 0xFF00) >> 8;
hw->CRTCEXT[0] = (hw->CRTCEXT[0] & 0xF0) | ((pos >> 16) & 0x0F) | ((pos >> 14) & 0x40);
hw->CRTCEXT[8] = pos >> 21;
minfo->hw_switch->restore(minfo);
update_crtc2(minfo, pos);
down_read(&minfo->altout.lock);
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
minfo->outputs[out].output->program) {
minfo->outputs[out].output->program(minfo->outputs[out].data);
}
}
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC1 &&
minfo->outputs[out].output->start) {
minfo->outputs[out].output->start(minfo->outputs[out].data);
}
}
up_read(&minfo->altout.lock);
matrox_cfbX_init(minfo);
}
}
minfo->initialized = 1;
return 0;
}
static int matroxfb_get_vblank(struct matrox_fb_info *minfo,
struct fb_vblank *vblank)
{
unsigned int sts1;
matroxfb_enable_irq(minfo, 0);
memset(vblank, 0, sizeof(*vblank));
vblank->flags = FB_VBLANK_HAVE_VCOUNT | FB_VBLANK_HAVE_VSYNC |
FB_VBLANK_HAVE_VBLANK | FB_VBLANK_HAVE_HBLANK;
sts1 = mga_inb(M_INSTS1);
vblank->vcount = mga_inl(M_VCOUNT);
/* BTW, on my PIII/450 with G400, reading M_INSTS1
byte makes this call about 12% slower (1.70 vs. 2.05 us
per ioctl()) */
if (sts1 & 1)
vblank->flags |= FB_VBLANK_HBLANKING;
if (sts1 & 8)
vblank->flags |= FB_VBLANK_VSYNCING;
if (vblank->vcount >= minfo->fbcon.var.yres)
vblank->flags |= FB_VBLANK_VBLANKING;
if (test_bit(0, &minfo->irq_flags)) {
vblank->flags |= FB_VBLANK_HAVE_COUNT;
/* Only one writer, aligned int value...
it should work without lock and without atomic_t */
vblank->count = minfo->crtc1.vsync.cnt;
}
return 0;
}
static struct matrox_altout panellink_output = {
.name = "Panellink output",
};
static int matroxfb_ioctl(struct fb_info *info,
unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
struct matrox_fb_info *minfo = info2minfo(info);
DBG(__func__)
if (minfo->dead) {
return -ENXIO;
}
switch (cmd) {
case FBIOGET_VBLANK:
{
struct fb_vblank vblank;
int err;
err = matroxfb_get_vblank(minfo, &vblank);
if (err)
return err;
if (copy_to_user(argp, &vblank, sizeof(vblank)))
return -EFAULT;
return 0;
}
case FBIO_WAITFORVSYNC:
{
u_int32_t crt;
if (get_user(crt, (u_int32_t __user *)arg))
return -EFAULT;
return matroxfb_wait_for_sync(minfo, crt);
}
case MATROXFB_SET_OUTPUT_MODE:
{
struct matroxioc_output_mode mom;
struct matrox_altout *oproc;
int val;
if (copy_from_user(&mom, argp, sizeof(mom)))
return -EFAULT;
if (mom.output >= MATROXFB_MAX_OUTPUTS)
return -ENXIO;
down_read(&minfo->altout.lock);
oproc = minfo->outputs[mom.output].output;
if (!oproc) {
val = -ENXIO;
} else if (!oproc->verifymode) {
if (mom.mode == MATROXFB_OUTPUT_MODE_MONITOR) {
val = 0;
} else {
val = -EINVAL;
}
} else {
val = oproc->verifymode(minfo->outputs[mom.output].data, mom.mode);
}
if (!val) {
if (minfo->outputs[mom.output].mode != mom.mode) {
minfo->outputs[mom.output].mode = mom.mode;
val = 1;
}
}
up_read(&minfo->altout.lock);
if (val != 1)
return val;
switch (minfo->outputs[mom.output].src) {
case MATROXFB_SRC_CRTC1:
matroxfb_set_par(info);
break;
case MATROXFB_SRC_CRTC2:
{
struct matroxfb_dh_fb_info* crtc2;
down_read(&minfo->crtc2.lock);
crtc2 = minfo->crtc2.info;
if (crtc2)
crtc2->fbcon.fbops->fb_set_par(&crtc2->fbcon);
up_read(&minfo->crtc2.lock);
}
break;
}
return 0;
}
case MATROXFB_GET_OUTPUT_MODE:
{
struct matroxioc_output_mode mom;
struct matrox_altout *oproc;
int val;
if (copy_from_user(&mom, argp, sizeof(mom)))
return -EFAULT;
if (mom.output >= MATROXFB_MAX_OUTPUTS)
return -ENXIO;
down_read(&minfo->altout.lock);
oproc = minfo->outputs[mom.output].output;
if (!oproc) {
val = -ENXIO;
} else {
mom.mode = minfo->outputs[mom.output].mode;
val = 0;
}
up_read(&minfo->altout.lock);
if (val)
return val;
if (copy_to_user(argp, &mom, sizeof(mom)))
return -EFAULT;
return 0;
}
case MATROXFB_SET_OUTPUT_CONNECTION:
{
u_int32_t tmp;
int i;
int changes;
if (copy_from_user(&tmp, argp, sizeof(tmp)))
return -EFAULT;
for (i = 0; i < 32; i++) {
if (tmp & (1 << i)) {
if (i >= MATROXFB_MAX_OUTPUTS)
return -ENXIO;
if (!minfo->outputs[i].output)
return -ENXIO;
switch (minfo->outputs[i].src) {
case MATROXFB_SRC_NONE:
case MATROXFB_SRC_CRTC1:
break;
default:
return -EBUSY;
}
}
}
if (minfo->devflags.panellink) {
if (tmp & MATROXFB_OUTPUT_CONN_DFP) {
if (tmp & MATROXFB_OUTPUT_CONN_SECONDARY)
return -EINVAL;
for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
if (minfo->outputs[i].src == MATROXFB_SRC_CRTC2) {
return -EBUSY;
}
}
}
}
changes = 0;
for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
if (tmp & (1 << i)) {
if (minfo->outputs[i].src != MATROXFB_SRC_CRTC1) {
changes = 1;
minfo->outputs[i].src = MATROXFB_SRC_CRTC1;
}
} else if (minfo->outputs[i].src == MATROXFB_SRC_CRTC1) {
changes = 1;
minfo->outputs[i].src = MATROXFB_SRC_NONE;
}
}
if (!changes)
return 0;
matroxfb_set_par(info);
return 0;
}
case MATROXFB_GET_OUTPUT_CONNECTION:
{
u_int32_t conn = 0;
int i;
for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
if (minfo->outputs[i].src == MATROXFB_SRC_CRTC1) {
conn |= 1 << i;
}
}
if (put_user(conn, (u_int32_t __user *)arg))
return -EFAULT;
return 0;
}
case MATROXFB_GET_AVAILABLE_OUTPUTS:
{
u_int32_t conn = 0;
int i;
for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
if (minfo->outputs[i].output) {
switch (minfo->outputs[i].src) {
case MATROXFB_SRC_NONE:
case MATROXFB_SRC_CRTC1:
conn |= 1 << i;
break;
}
}
}
if (minfo->devflags.panellink) {
if (conn & MATROXFB_OUTPUT_CONN_DFP)
conn &= ~MATROXFB_OUTPUT_CONN_SECONDARY;
if (conn & MATROXFB_OUTPUT_CONN_SECONDARY)
conn &= ~MATROXFB_OUTPUT_CONN_DFP;
}
if (put_user(conn, (u_int32_t __user *)arg))
return -EFAULT;
return 0;
}
case MATROXFB_GET_ALL_OUTPUTS:
{
u_int32_t conn = 0;
int i;
for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
if (minfo->outputs[i].output) {
conn |= 1 << i;
}
}
if (put_user(conn, (u_int32_t __user *)arg))
return -EFAULT;
return 0;
}
case VIDIOC_QUERYCAP:
{
struct v4l2_capability r;
memset(&r, 0, sizeof(r));
strcpy(r.driver, "matroxfb");
strcpy(r.card, "Matrox");
sprintf(r.bus_info, "PCI:%s", pci_name(minfo->pcidev));
r.version = KERNEL_VERSION(1,0,0);
r.capabilities = V4L2_CAP_VIDEO_OUTPUT;
if (copy_to_user(argp, &r, sizeof(r)))
return -EFAULT;
return 0;
}
case VIDIOC_QUERYCTRL:
{
struct v4l2_queryctrl qctrl;
int err;
if (copy_from_user(&qctrl, argp, sizeof(qctrl)))
return -EFAULT;
down_read(&minfo->altout.lock);
if (!minfo->outputs[1].output) {
err = -ENXIO;
} else if (minfo->outputs[1].output->getqueryctrl) {
err = minfo->outputs[1].output->getqueryctrl(minfo->outputs[1].data, &qctrl);
} else {
err = -EINVAL;
}
up_read(&minfo->altout.lock);
if (err >= 0 &&
copy_to_user(argp, &qctrl, sizeof(qctrl)))
return -EFAULT;
return err;
}
case VIDIOC_G_CTRL:
{
struct v4l2_control ctrl;
int err;
if (copy_from_user(&ctrl, argp, sizeof(ctrl)))
return -EFAULT;
down_read(&minfo->altout.lock);
if (!minfo->outputs[1].output) {
err = -ENXIO;
} else if (minfo->outputs[1].output->getctrl) {
err = minfo->outputs[1].output->getctrl(minfo->outputs[1].data, &ctrl);
} else {
err = -EINVAL;
}
up_read(&minfo->altout.lock);
if (err >= 0 &&
copy_to_user(argp, &ctrl, sizeof(ctrl)))
return -EFAULT;
return err;
}
case VIDIOC_S_CTRL:
{
struct v4l2_control ctrl;
int err;
if (copy_from_user(&ctrl, argp, sizeof(ctrl)))
return -EFAULT;
down_read(&minfo->altout.lock);
if (!minfo->outputs[1].output) {
err = -ENXIO;
} else if (minfo->outputs[1].output->setctrl) {
err = minfo->outputs[1].output->setctrl(minfo->outputs[1].data, &ctrl);
} else {
err = -EINVAL;
}
up_read(&minfo->altout.lock);
return err;
}
}
return -ENOTTY;
}
/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
static int matroxfb_blank(int blank, struct fb_info *info)
{
int seq;
int crtc;
CRITFLAGS
struct matrox_fb_info *minfo = info2minfo(info);
DBG(__func__)
if (minfo->dead)
return 1;
switch (blank) {
case FB_BLANK_NORMAL: seq = 0x20; crtc = 0x00; break; /* works ??? */
case FB_BLANK_VSYNC_SUSPEND: seq = 0x20; crtc = 0x10; break;
case FB_BLANK_HSYNC_SUSPEND: seq = 0x20; crtc = 0x20; break;
case FB_BLANK_POWERDOWN: seq = 0x20; crtc = 0x30; break;
default: seq = 0x00; crtc = 0x00; break;
}
CRITBEGIN
mga_outb(M_SEQ_INDEX, 1);
mga_outb(M_SEQ_DATA, (mga_inb(M_SEQ_DATA) & ~0x20) | seq);
mga_outb(M_EXTVGA_INDEX, 1);
mga_outb(M_EXTVGA_DATA, (mga_inb(M_EXTVGA_DATA) & ~0x30) | crtc);
CRITEND
return 0;
}
static const struct fb_ops matroxfb_ops = {
.owner = THIS_MODULE,
.fb_open = matroxfb_open,
.fb_release = matroxfb_release,
.fb_check_var = matroxfb_check_var,
.fb_set_par = matroxfb_set_par,
.fb_setcolreg = matroxfb_setcolreg,
.fb_pan_display =matroxfb_pan_display,
.fb_blank = matroxfb_blank,
.fb_ioctl = matroxfb_ioctl,
/* .fb_fillrect = <set by matrox_cfbX_init>, */
/* .fb_copyarea = <set by matrox_cfbX_init>, */
/* .fb_imageblit = <set by matrox_cfbX_init>, */
/* .fb_cursor = <set by matrox_cfbX_init>, */
};
#define RSDepth(X) (((X) >> 8) & 0x0F)
#define RS8bpp 0x1
#define RS15bpp 0x2
#define RS16bpp 0x3
#define RS32bpp 0x4
#define RS4bpp 0x5
#define RS24bpp 0x6
#define RSText 0x7
#define RSText8 0x8
/* 9-F */
static struct { struct fb_bitfield red, green, blue, transp; int bits_per_pixel; } colors[] = {
{ { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 8 },
{ { 10, 5, 0}, { 5, 5, 0}, { 0, 5, 0}, { 15, 1, 0}, 16 },
{ { 11, 5, 0}, { 5, 6, 0}, { 0, 5, 0}, { 0, 0, 0}, 16 },
{ { 16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 24, 8, 0}, 32 },
{ { 0, 8, 0}, { 0, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 4 },
{ { 16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 0, 0, 0}, 24 },
{ { 0, 6, 0}, { 0, 6, 0}, { 0, 6, 0}, { 0, 0, 0}, 0 }, /* textmode with (default) VGA8x16 */
{ { 0, 6, 0}, { 0, 6, 0}, { 0, 6, 0}, { 0, 0, 0}, 0 }, /* textmode hardwired to VGA8x8 */
};
/* initialized by setup, see explanation at end of file (search for MODULE_PARM_DESC) */
static unsigned int mem; /* "matroxfb:mem:xxxxxM" */
static int option_precise_width = 1; /* cannot be changed, option_precise_width==0 must imply noaccel */
static int inv24; /* "matroxfb:inv24" */
static int cross4MB = -1; /* "matroxfb:cross4MB" */
static int disabled; /* "matroxfb:disabled" */
static int noaccel; /* "matroxfb:noaccel" */
static int nopan; /* "matroxfb:nopan" */
static int no_pci_retry; /* "matroxfb:nopciretry" */
static int novga; /* "matroxfb:novga" */
static int nobios; /* "matroxfb:nobios" */
static int noinit = 1; /* "matroxfb:init" */
static int inverse; /* "matroxfb:inverse" */
static int sgram; /* "matroxfb:sgram" */
static int mtrr = 1; /* "matroxfb:nomtrr" */
static int grayscale; /* "matroxfb:grayscale" */
static int dev = -1; /* "matroxfb:dev:xxxxx" */
static unsigned int vesa = ~0; /* "matroxfb:vesa:xxxxx" */
static int depth = -1; /* "matroxfb:depth:xxxxx" */
static unsigned int xres; /* "matroxfb:xres:xxxxx" */
static unsigned int yres; /* "matroxfb:yres:xxxxx" */
static unsigned int upper = ~0; /* "matroxfb:upper:xxxxx" */
static unsigned int lower = ~0; /* "matroxfb:lower:xxxxx" */
static unsigned int vslen; /* "matroxfb:vslen:xxxxx" */
static unsigned int left = ~0; /* "matroxfb:left:xxxxx" */
static unsigned int right = ~0; /* "matroxfb:right:xxxxx" */
static unsigned int hslen; /* "matroxfb:hslen:xxxxx" */
static unsigned int pixclock; /* "matroxfb:pixclock:xxxxx" */
static int sync = -1; /* "matroxfb:sync:xxxxx" */
static unsigned int fv; /* "matroxfb:fv:xxxxx" */
static unsigned int fh; /* "matroxfb:fh:xxxxxk" */
static unsigned int maxclk; /* "matroxfb:maxclk:xxxxM" */
static int dfp; /* "matroxfb:dfp */
static int dfp_type = -1; /* "matroxfb:dfp:xxx */
static int memtype = -1; /* "matroxfb:memtype:xxx" */
static char outputs[8]; /* "matroxfb:outputs:xxx" */
#ifndef MODULE
static char videomode[64]; /* "matroxfb:mode:xxxxx" or "matroxfb:xxxxx" */
#endif
static int matroxfb_getmemory(struct matrox_fb_info *minfo,
unsigned int maxSize, unsigned int *realSize)
{
vaddr_t vm;
unsigned int offs;
unsigned int offs2;
unsigned char orig;
unsigned char bytes[32];
unsigned char* tmp;
DBG(__func__)
vm = minfo->video.vbase;
maxSize &= ~0x1FFFFF; /* must be X*2MB (really it must be 2 or X*4MB) */
/* at least 2MB */
if (maxSize < 0x0200000) return 0;
if (maxSize > 0x2000000) maxSize = 0x2000000;
mga_outb(M_EXTVGA_INDEX, 0x03);
orig = mga_inb(M_EXTVGA_DATA);
mga_outb(M_EXTVGA_DATA, orig | 0x80);
tmp = bytes;
for (offs = 0x100000; offs < maxSize; offs += 0x200000)
*tmp++ = mga_readb(vm, offs);
for (offs = 0x100000; offs < maxSize; offs += 0x200000)
mga_writeb(vm, offs, 0x02);
mga_outb(M_CACHEFLUSH, 0x00);
for (offs = 0x100000; offs < maxSize; offs += 0x200000) {
if (mga_readb(vm, offs) != 0x02)
break;
mga_writeb(vm, offs, mga_readb(vm, offs) - 0x02);
if (mga_readb(vm, offs))
break;
}
tmp = bytes;
for (offs2 = 0x100000; offs2 < maxSize; offs2 += 0x200000)
mga_writeb(vm, offs2, *tmp++);
mga_outb(M_EXTVGA_INDEX, 0x03);
mga_outb(M_EXTVGA_DATA, orig);
*realSize = offs - 0x100000;
#ifdef CONFIG_FB_MATROX_MILLENIUM
minfo->interleave = !(!isMillenium(minfo) || ((offs - 0x100000) & 0x3FFFFF));
#endif
return 1;
}
struct video_board {
int maxvram;
int maxdisplayable;
int accelID;
struct matrox_switch* lowlevel;
};
#ifdef CONFIG_FB_MATROX_MILLENIUM
static struct video_board vbMillennium = {
.maxvram = 0x0800000,
.maxdisplayable = 0x0800000,
.accelID = FB_ACCEL_MATROX_MGA2064W,
.lowlevel = &matrox_millennium
};
static struct video_board vbMillennium2 = {
.maxvram = 0x1000000,
.maxdisplayable = 0x0800000,
.accelID = FB_ACCEL_MATROX_MGA2164W,
.lowlevel = &matrox_millennium
};
static struct video_board vbMillennium2A = {
.maxvram = 0x1000000,
.maxdisplayable = 0x0800000,
.accelID = FB_ACCEL_MATROX_MGA2164W_AGP,
.lowlevel = &matrox_millennium
};
#endif /* CONFIG_FB_MATROX_MILLENIUM */
#ifdef CONFIG_FB_MATROX_MYSTIQUE
static struct video_board vbMystique = {
.maxvram = 0x0800000,
.maxdisplayable = 0x0800000,
.accelID = FB_ACCEL_MATROX_MGA1064SG,
.lowlevel = &matrox_mystique
};
#endif /* CONFIG_FB_MATROX_MYSTIQUE */
#ifdef CONFIG_FB_MATROX_G
static struct video_board vbG100 = {
.maxvram = 0x0800000,
.maxdisplayable = 0x0800000,
.accelID = FB_ACCEL_MATROX_MGAG100,
.lowlevel = &matrox_G100
};
static struct video_board vbG200 = {
.maxvram = 0x1000000,
.maxdisplayable = 0x1000000,
.accelID = FB_ACCEL_MATROX_MGAG200,
.lowlevel = &matrox_G100
};
static struct video_board vbG200eW = {
.maxvram = 0x1000000,
.maxdisplayable = 0x0800000,
.accelID = FB_ACCEL_MATROX_MGAG200,
.lowlevel = &matrox_G100
};
/* from doc it looks like that accelerator can draw only to low 16MB :-( Direct accesses & displaying are OK for
whole 32MB */
static struct video_board vbG400 = {
.maxvram = 0x2000000,
.maxdisplayable = 0x1000000,
.accelID = FB_ACCEL_MATROX_MGAG400,
.lowlevel = &matrox_G100
};
#endif
#define DEVF_VIDEO64BIT 0x0001
#define DEVF_SWAPS 0x0002
#define DEVF_SRCORG 0x0004
#define DEVF_DUALHEAD 0x0008
#define DEVF_CROSS4MB 0x0010
#define DEVF_TEXT4B 0x0020
/* #define DEVF_recycled 0x0040 */
/* #define DEVF_recycled 0x0080 */
#define DEVF_SUPPORT32MB 0x0100
#define DEVF_ANY_VXRES 0x0200
#define DEVF_TEXT16B 0x0400
#define DEVF_CRTC2 0x0800
#define DEVF_MAVEN_CAPABLE 0x1000
#define DEVF_PANELLINK_CAPABLE 0x2000
#define DEVF_G450DAC 0x4000
#define DEVF_GCORE (DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB)
#define DEVF_G2CORE (DEVF_GCORE | DEVF_ANY_VXRES | DEVF_MAVEN_CAPABLE | DEVF_PANELLINK_CAPABLE | DEVF_SRCORG | DEVF_DUALHEAD)
#define DEVF_G100 (DEVF_GCORE) /* no doc, no vxres... */
#define DEVF_G200 (DEVF_G2CORE)
#define DEVF_G400 (DEVF_G2CORE | DEVF_SUPPORT32MB | DEVF_TEXT16B | DEVF_CRTC2)
/* if you'll find how to drive DFP... */
#define DEVF_G450 (DEVF_GCORE | DEVF_ANY_VXRES | DEVF_SUPPORT32MB | DEVF_TEXT16B | DEVF_CRTC2 | DEVF_G450DAC | DEVF_SRCORG | DEVF_DUALHEAD)
#define DEVF_G550 (DEVF_G450)
static struct board {
unsigned short vendor, device, rev, svid, sid;
unsigned int flags;
unsigned int maxclk;
enum mga_chip chip;
struct video_board* base;
const char* name;
} dev_list[] = {
#ifdef CONFIG_FB_MATROX_MILLENIUM
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL, 0xFF,
0, 0,
DEVF_TEXT4B,
230000,
MGA_2064,
&vbMillennium,
"Millennium (PCI)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2, 0xFF,
0, 0,
DEVF_SWAPS,
220000,
MGA_2164,
&vbMillennium2,
"Millennium II (PCI)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2_AGP, 0xFF,
0, 0,
DEVF_SWAPS,
250000,
MGA_2164,
&vbMillennium2A,
"Millennium II (AGP)"},
#endif
#ifdef CONFIG_FB_MATROX_MYSTIQUE
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS, 0x02,
0, 0,
DEVF_VIDEO64BIT | DEVF_CROSS4MB,
180000,
MGA_1064,
&vbMystique,
"Mystique (PCI)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS, 0xFF,
0, 0,
DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB,
220000,
MGA_1164,
&vbMystique,
"Mystique 220 (PCI)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS_AGP, 0x02,
0, 0,
DEVF_VIDEO64BIT | DEVF_CROSS4MB,
180000,
MGA_1064,
&vbMystique,
"Mystique (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS_AGP, 0xFF,
0, 0,
DEVF_VIDEO64BIT | DEVF_SWAPS | DEVF_CROSS4MB,
220000,
MGA_1164,
&vbMystique,
"Mystique 220 (AGP)"},
#endif
#ifdef CONFIG_FB_MATROX_G
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_MM, 0xFF,
0, 0,
DEVF_G100,
230000,
MGA_G100,
&vbG100,
"MGA-G100 (PCI)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_AGP, 0xFF,
0, 0,
DEVF_G100,
230000,
MGA_G100,
&vbG100,
"MGA-G100 (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, 0xFF,
0, 0,
DEVF_G200,
250000,
MGA_G200,
&vbG200,
"MGA-G200 (PCI)"},
{PCI_VENDOR_ID_MATROX, 0x0532, 0xFF,
0, 0,
DEVF_G200,
250000,
MGA_G200,
&vbG200eW,
"MGA-G200eW (PCI)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_GENERIC,
DEVF_G200,
220000,
MGA_G200,
&vbG200,
"MGA-G200 (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP,
DEVF_G200,
230000,
MGA_G200,
&vbG200,
"Mystique G200 (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MILLENIUM_G200_AGP,
DEVF_G200,
250000,
MGA_G200,
&vbG200,
"Millennium G200 (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MARVEL_G200_AGP,
DEVF_G200,
230000,
MGA_G200,
&vbG200,
"Marvel G200 (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
PCI_SS_VENDOR_ID_SIEMENS_NIXDORF, PCI_SS_ID_SIEMENS_MGA_G200_AGP,
DEVF_G200,
230000,
MGA_G200,
&vbG200,
"MGA-G200 (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, 0xFF,
0, 0,
DEVF_G200,
230000,
MGA_G200,
&vbG200,
"G200 (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0x80,
PCI_SS_VENDOR_ID_MATROX, PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP,
DEVF_G400,
360000,
MGA_G400,
&vbG400,
"Millennium G400 MAX (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0x80,
0, 0,
DEVF_G400,
300000,
MGA_G400,
&vbG400,
"G400 (AGP)"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, 0xFF,
0, 0,
DEVF_G450,
360000,
MGA_G450,
&vbG400,
"G450"},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550, 0xFF,
0, 0,
DEVF_G550,
360000,
MGA_G550,
&vbG400,
"G550"},
#endif
{0, 0, 0xFF,
0, 0,
0,
0,
0,
NULL,
NULL}};
#ifndef MODULE
static const struct fb_videomode defaultmode = {
/* 640x480 @ 60Hz, 31.5 kHz */
NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
0, FB_VMODE_NONINTERLACED
};
static int hotplug = 0;
#endif /* !MODULE */
static void setDefaultOutputs(struct matrox_fb_info *minfo)
{
unsigned int i;
const char* ptr;
minfo->outputs[0].default_src = MATROXFB_SRC_CRTC1;
if (minfo->devflags.g450dac) {
minfo->outputs[1].default_src = MATROXFB_SRC_CRTC1;
minfo->outputs[2].default_src = MATROXFB_SRC_CRTC1;
} else if (dfp) {
minfo->outputs[2].default_src = MATROXFB_SRC_CRTC1;
}
ptr = outputs;
for (i = 0; i < MATROXFB_MAX_OUTPUTS; i++) {
char c = *ptr++;
if (c == 0) {
break;
}
if (c == '0') {
minfo->outputs[i].default_src = MATROXFB_SRC_NONE;
} else if (c == '1') {
minfo->outputs[i].default_src = MATROXFB_SRC_CRTC1;
} else if (c == '2' && minfo->devflags.crtc2) {
minfo->outputs[i].default_src = MATROXFB_SRC_CRTC2;
} else {
printk(KERN_ERR "matroxfb: Unknown outputs setting\n");
break;
}
}
/* Nullify this option for subsequent adapters */
outputs[0] = 0;
}
static int initMatrox2(struct matrox_fb_info *minfo, struct board *b)
{
unsigned long ctrlptr_phys = 0;
unsigned long video_base_phys = 0;
unsigned int memsize;
int err;
static const struct pci_device_id intel_82437[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437) },
{ },
};
DBG(__func__)
/* set default values... */
vesafb_defined.accel_flags = FB_ACCELF_TEXT;
minfo->hw_switch = b->base->lowlevel;
minfo->devflags.accelerator = b->base->accelID;
minfo->max_pixel_clock = b->maxclk;
printk(KERN_INFO "matroxfb: Matrox %s detected\n", b->name);
minfo->capable.plnwt = 1;
minfo->chip = b->chip;
minfo->capable.srcorg = b->flags & DEVF_SRCORG;
minfo->devflags.video64bits = b->flags & DEVF_VIDEO64BIT;
if (b->flags & DEVF_TEXT4B) {
minfo->devflags.vgastep = 4;
minfo->devflags.textmode = 4;
minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP16;
} else if (b->flags & DEVF_TEXT16B) {
minfo->devflags.vgastep = 16;
minfo->devflags.textmode = 1;
minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP16;
} else {
minfo->devflags.vgastep = 8;
minfo->devflags.textmode = 1;
minfo->devflags.text_type_aux = FB_AUX_TEXT_MGA_STEP8;
}
minfo->devflags.support32MB = (b->flags & DEVF_SUPPORT32MB) != 0;
minfo->devflags.precise_width = !(b->flags & DEVF_ANY_VXRES);
minfo->devflags.crtc2 = (b->flags & DEVF_CRTC2) != 0;
minfo->devflags.maven_capable = (b->flags & DEVF_MAVEN_CAPABLE) != 0;
minfo->devflags.dualhead = (b->flags & DEVF_DUALHEAD) != 0;
minfo->devflags.dfp_type = dfp_type;
minfo->devflags.g450dac = (b->flags & DEVF_G450DAC) != 0;
minfo->devflags.textstep = minfo->devflags.vgastep * minfo->devflags.textmode;
minfo->devflags.textvram = 65536 / minfo->devflags.textmode;
setDefaultOutputs(minfo);
if (b->flags & DEVF_PANELLINK_CAPABLE) {
minfo->outputs[2].data = minfo;
minfo->outputs[2].output = &panellink_output;
minfo->outputs[2].src = minfo->outputs[2].default_src;
minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
minfo->devflags.panellink = 1;
}
if (minfo->capable.cross4MB < 0)
minfo->capable.cross4MB = b->flags & DEVF_CROSS4MB;
if (b->flags & DEVF_SWAPS) {
ctrlptr_phys = pci_resource_start(minfo->pcidev, 1);
video_base_phys = pci_resource_start(minfo->pcidev, 0);
minfo->devflags.fbResource = PCI_BASE_ADDRESS_0;
} else {
ctrlptr_phys = pci_resource_start(minfo->pcidev, 0);
video_base_phys = pci_resource_start(minfo->pcidev, 1);
minfo->devflags.fbResource = PCI_BASE_ADDRESS_1;
}
err = -EINVAL;
if (!ctrlptr_phys) {
printk(KERN_ERR "matroxfb: control registers are not available, matroxfb disabled\n");
goto fail;
}
if (!video_base_phys) {
printk(KERN_ERR "matroxfb: video RAM is not available in PCI address space, matroxfb disabled\n");
goto fail;
}
memsize = b->base->maxvram;
if (!request_mem_region(ctrlptr_phys, 16384, "matroxfb MMIO")) {
goto fail;
}
if (!request_mem_region(video_base_phys, memsize, "matroxfb FB")) {
goto failCtrlMR;
}
minfo->video.len_maximum = memsize;
/* convert mem (autodetect k, M) */
if (mem < 1024) mem *= 1024;
if (mem < 0x00100000) mem *= 1024;
if (mem && (mem < memsize))
memsize = mem;
err = -ENOMEM;
minfo->mmio.vbase.vaddr = ioremap(ctrlptr_phys, 16384);
if (!minfo->mmio.vbase.vaddr) {
printk(KERN_ERR "matroxfb: cannot ioremap(%lX, 16384), matroxfb disabled\n", ctrlptr_phys);
goto failVideoMR;
}
minfo->mmio.base = ctrlptr_phys;
minfo->mmio.len = 16384;
minfo->video.base = video_base_phys;
minfo->video.vbase.vaddr = ioremap_wc(video_base_phys, memsize);
if (!minfo->video.vbase.vaddr) {
printk(KERN_ERR "matroxfb: cannot ioremap(%lX, %d), matroxfb disabled\n",
video_base_phys, memsize);
goto failCtrlIO;
}
{
u_int32_t cmd;
u_int32_t mga_option;
pci_read_config_dword(minfo->pcidev, PCI_OPTION_REG, &mga_option);
pci_read_config_dword(minfo->pcidev, PCI_COMMAND, &cmd);
mga_option &= 0x7FFFFFFF; /* clear BIG_ENDIAN */
mga_option |= MX_OPTION_BSWAP;
/* disable palette snooping */
cmd &= ~PCI_COMMAND_VGA_PALETTE;
if (pci_dev_present(intel_82437)) {
if (!(mga_option & 0x20000000) && !minfo->devflags.nopciretry) {
printk(KERN_WARNING "matroxfb: Disabling PCI retries due to i82437 present\n");
}
mga_option |= 0x20000000;
minfo->devflags.nopciretry = 1;
}
pci_write_config_dword(minfo->pcidev, PCI_COMMAND, cmd);
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mga_option);
minfo->hw.MXoptionReg = mga_option;
/* select non-DMA memory for PCI_MGA_DATA, otherwise dump of PCI cfg space can lock PCI bus */
/* maybe preinit() candidate, but it is same... for all devices... at this time... */
pci_write_config_dword(minfo->pcidev, PCI_MGA_INDEX, 0x00003C00);
}
err = -ENXIO;
matroxfb_read_pins(minfo);
if (minfo->hw_switch->preinit(minfo)) {
goto failVideoIO;
}
err = -ENOMEM;
if (!matroxfb_getmemory(minfo, memsize, &minfo->video.len) || !minfo->video.len) {
printk(KERN_ERR "matroxfb: cannot determine memory size\n");
goto failVideoIO;
}
minfo->devflags.ydstorg = 0;
minfo->video.base = video_base_phys;
minfo->video.len_usable = minfo->video.len;
if (minfo->video.len_usable > b->base->maxdisplayable)
minfo->video.len_usable = b->base->maxdisplayable;
if (mtrr)
minfo->wc_cookie = arch_phys_wc_add(video_base_phys,
minfo->video.len);
if (!minfo->devflags.novga)
request_region(0x3C0, 32, "matrox");
matroxfb_g450_connect(minfo);
minfo->hw_switch->reset(minfo);
minfo->fbcon.monspecs.hfmin = 0;
minfo->fbcon.monspecs.hfmax = fh;
minfo->fbcon.monspecs.vfmin = 0;
minfo->fbcon.monspecs.vfmax = fv;
minfo->fbcon.monspecs.dpms = 0; /* TBD */
/* static settings */
vesafb_defined.red = colors[depth-1].red;
vesafb_defined.green = colors[depth-1].green;
vesafb_defined.blue = colors[depth-1].blue;
vesafb_defined.bits_per_pixel = colors[depth-1].bits_per_pixel;
vesafb_defined.grayscale = grayscale;
vesafb_defined.vmode = 0;
if (noaccel)
vesafb_defined.accel_flags &= ~FB_ACCELF_TEXT;
minfo->fbops = matroxfb_ops;
minfo->fbcon.fbops = &minfo->fbops;
minfo->fbcon.pseudo_palette = minfo->cmap;
minfo->fbcon.flags = FBINFO_PARTIAL_PAN_OK | /* Prefer panning for scroll under MC viewer/edit */
FBINFO_HWACCEL_COPYAREA | /* We have hw-assisted bmove */
FBINFO_HWACCEL_FILLRECT | /* And fillrect */
FBINFO_HWACCEL_IMAGEBLIT | /* And imageblit */
FBINFO_HWACCEL_XPAN | /* And we support both horizontal */
FBINFO_HWACCEL_YPAN | /* And vertical panning */
FBINFO_READS_FAST;
minfo->video.len_usable &= PAGE_MASK;
fb_alloc_cmap(&minfo->fbcon.cmap, 256, 1);
#ifndef MODULE
/* mode database is marked __init!!! */
if (!hotplug) {
fb_find_mode(&vesafb_defined, &minfo->fbcon, videomode[0] ? videomode : NULL,
NULL, 0, &defaultmode, vesafb_defined.bits_per_pixel);
}
#endif /* !MODULE */
/* mode modifiers */
if (hslen)
vesafb_defined.hsync_len = hslen;
if (vslen)
vesafb_defined.vsync_len = vslen;
if (left != ~0)
vesafb_defined.left_margin = left;
if (right != ~0)
vesafb_defined.right_margin = right;
if (upper != ~0)
vesafb_defined.upper_margin = upper;
if (lower != ~0)
vesafb_defined.lower_margin = lower;
if (xres)
vesafb_defined.xres = xres;
if (yres)
vesafb_defined.yres = yres;
if (sync != -1)
vesafb_defined.sync = sync;
else if (vesafb_defined.sync == ~0) {
vesafb_defined.sync = 0;
if (yres < 400)
vesafb_defined.sync |= FB_SYNC_HOR_HIGH_ACT;
else if (yres < 480)
vesafb_defined.sync |= FB_SYNC_VERT_HIGH_ACT;
}
/* fv, fh, maxclk limits was specified */
{
unsigned int tmp;
if (fv) {
tmp = fv * (vesafb_defined.upper_margin + vesafb_defined.yres
+ vesafb_defined.lower_margin + vesafb_defined.vsync_len);
if ((tmp < fh) || (fh == 0)) fh = tmp;
}
if (fh) {
tmp = fh * (vesafb_defined.left_margin + vesafb_defined.xres
+ vesafb_defined.right_margin + vesafb_defined.hsync_len);
if ((tmp < maxclk) || (maxclk == 0)) maxclk = tmp;
}
tmp = (maxclk + 499) / 500;
if (tmp) {
tmp = (2000000000 + tmp) / tmp;
if (tmp > pixclock) pixclock = tmp;
}
}
if (pixclock) {
if (pixclock < 2000) /* > 500MHz */
pixclock = 4000; /* 250MHz */
if (pixclock > 1000000)
pixclock = 1000000; /* 1MHz */
vesafb_defined.pixclock = pixclock;
}
/* FIXME: Where to move this?! */
#if defined(CONFIG_PPC_PMAC)
#ifndef MODULE
if (machine_is(powermac)) {
struct fb_var_screeninfo var;
if (default_vmode <= 0 || default_vmode > VMODE_MAX)
default_vmode = VMODE_640_480_60;
#if defined(CONFIG_PPC32)
if (IS_REACHABLE(CONFIG_NVRAM) && default_cmode == CMODE_NVRAM)
default_cmode = nvram_read_byte(NV_CMODE);
#endif
if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
default_cmode = CMODE_8;
if (!mac_vmode_to_var(default_vmode, default_cmode, &var)) {
var.accel_flags = vesafb_defined.accel_flags;
var.xoffset = var.yoffset = 0;
/* Note: mac_vmode_to_var() does not set all parameters */
vesafb_defined = var;
}
}
#endif /* !MODULE */
#endif /* CONFIG_PPC_PMAC */
vesafb_defined.xres_virtual = vesafb_defined.xres;
if (nopan) {
vesafb_defined.yres_virtual = vesafb_defined.yres;
} else {
vesafb_defined.yres_virtual = 65536; /* large enough to be INF, but small enough
to yres_virtual * xres_virtual < 2^32 */
}
matroxfb_init_fix(minfo);
minfo->fbcon.screen_base = vaddr_va(minfo->video.vbase);
/* Normalize values (namely yres_virtual) */
matroxfb_check_var(&vesafb_defined, &minfo->fbcon);
/* And put it into "current" var. Do NOT program hardware yet, or we'll not take over
* vgacon correctly. fbcon_startup will call fb_set_par for us, WITHOUT check_var,
* and unfortunately it will do it BEFORE vgacon contents is saved, so it won't work
* anyway. But we at least tried... */
minfo->fbcon.var = vesafb_defined;
err = -EINVAL;
printk(KERN_INFO "matroxfb: %dx%dx%dbpp (virtual: %dx%d)\n",
vesafb_defined.xres, vesafb_defined.yres, vesafb_defined.bits_per_pixel,
vesafb_defined.xres_virtual, vesafb_defined.yres_virtual);
printk(KERN_INFO "matroxfb: framebuffer at 0x%lX, mapped to 0x%p, size %d\n",
minfo->video.base, vaddr_va(minfo->video.vbase), minfo->video.len);
/* We do not have to set currcon to 0... register_framebuffer do it for us on first console
* and we do not want currcon == 0 for subsequent framebuffers */
minfo->fbcon.device = &minfo->pcidev->dev;
if (register_framebuffer(&minfo->fbcon) < 0) {
goto failVideoIO;
}
fb_info(&minfo->fbcon, "%s frame buffer device\n", minfo->fbcon.fix.id);
/* there is no console on this fb... but we have to initialize hardware
* until someone tells me what is proper thing to do */
if (!minfo->initialized) {
fb_info(&minfo->fbcon, "initializing hardware\n");
/* We have to use FB_ACTIVATE_FORCE, as we had to put vesafb_defined to the fbcon.var
* already before, so register_framebuffer works correctly. */
vesafb_defined.activate |= FB_ACTIVATE_FORCE;
fb_set_var(&minfo->fbcon, &vesafb_defined);
}
return 0;
failVideoIO:;
matroxfb_g450_shutdown(minfo);
iounmap(minfo->video.vbase.vaddr);
failCtrlIO:;
iounmap(minfo->mmio.vbase.vaddr);
failVideoMR:;
release_mem_region(video_base_phys, minfo->video.len_maximum);
failCtrlMR:;
release_mem_region(ctrlptr_phys, 16384);
fail:;
return err;
}
static LIST_HEAD(matroxfb_list);
static LIST_HEAD(matroxfb_driver_list);
#define matroxfb_l(x) list_entry(x, struct matrox_fb_info, next_fb)
#define matroxfb_driver_l(x) list_entry(x, struct matroxfb_driver, node)
int matroxfb_register_driver(struct matroxfb_driver* drv) {
struct matrox_fb_info* minfo;
list_add(&drv->node, &matroxfb_driver_list);
list_for_each_entry(minfo, &matroxfb_list, next_fb) {
void* p;
if (minfo->drivers_count == MATROXFB_MAX_FB_DRIVERS)
continue;
p = drv->probe(minfo);
if (p) {
minfo->drivers_data[minfo->drivers_count] = p;
minfo->drivers[minfo->drivers_count++] = drv;
}
}
return 0;
}
void matroxfb_unregister_driver(struct matroxfb_driver* drv) {
struct matrox_fb_info* minfo;
list_del(&drv->node);
list_for_each_entry(minfo, &matroxfb_list, next_fb) {
int i;
for (i = 0; i < minfo->drivers_count; ) {
if (minfo->drivers[i] == drv) {
if (drv && drv->remove)
drv->remove(minfo, minfo->drivers_data[i]);
minfo->drivers[i] = minfo->drivers[--minfo->drivers_count];
minfo->drivers_data[i] = minfo->drivers_data[minfo->drivers_count];
} else
i++;
}
}
}
static void matroxfb_register_device(struct matrox_fb_info* minfo) {
struct matroxfb_driver* drv;
int i = 0;
list_add(&minfo->next_fb, &matroxfb_list);
for (drv = matroxfb_driver_l(matroxfb_driver_list.next);
drv != matroxfb_driver_l(&matroxfb_driver_list);
drv = matroxfb_driver_l(drv->node.next)) {
if (drv->probe) {
void *p = drv->probe(minfo);
if (p) {
minfo->drivers_data[i] = p;
minfo->drivers[i++] = drv;
if (i == MATROXFB_MAX_FB_DRIVERS)
break;
}
}
}
minfo->drivers_count = i;
}
static void matroxfb_unregister_device(struct matrox_fb_info* minfo) {
int i;
list_del(&minfo->next_fb);
for (i = 0; i < minfo->drivers_count; i++) {
struct matroxfb_driver* drv = minfo->drivers[i];
if (drv && drv->remove)
drv->remove(minfo, minfo->drivers_data[i]);
}
}
static int matroxfb_probe(struct pci_dev* pdev, const struct pci_device_id* dummy) {
struct board* b;
u_int16_t svid;
u_int16_t sid;
struct matrox_fb_info* minfo;
int err;
u_int32_t cmd;
DBG(__func__)
err = aperture_remove_conflicting_pci_devices(pdev, "matroxfb");
if (err)
return err;
svid = pdev->subsystem_vendor;
sid = pdev->subsystem_device;
for (b = dev_list; b->vendor; b++) {
if ((b->vendor != pdev->vendor) || (b->device != pdev->device) || (b->rev < pdev->revision)) continue;
if (b->svid)
if ((b->svid != svid) || (b->sid != sid)) continue;
break;
}
/* not match... */
if (!b->vendor)
return -ENODEV;
if (dev > 0) {
/* not requested one... */
dev--;
return -ENODEV;
}
pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
if (pci_enable_device(pdev)) {
return -1;
}
minfo = kzalloc(sizeof(*minfo), GFP_KERNEL);
if (!minfo)
return -ENOMEM;
minfo->pcidev = pdev;
minfo->dead = 0;
minfo->usecount = 0;
minfo->userusecount = 0;
pci_set_drvdata(pdev, minfo);
/* DEVFLAGS */
minfo->devflags.memtype = memtype;
if (memtype != -1)
noinit = 0;
if (cmd & PCI_COMMAND_MEMORY) {
minfo->devflags.novga = novga;
minfo->devflags.nobios = nobios;
minfo->devflags.noinit = noinit;
/* subsequent heads always needs initialization and must not enable BIOS */
novga = 1;
nobios = 1;
noinit = 0;
} else {
minfo->devflags.novga = 1;
minfo->devflags.nobios = 1;
minfo->devflags.noinit = 0;
}
minfo->devflags.nopciretry = no_pci_retry;
minfo->devflags.mga_24bpp_fix = inv24;
minfo->devflags.precise_width = option_precise_width;
minfo->devflags.sgram = sgram;
minfo->capable.cross4MB = cross4MB;
spin_lock_init(&minfo->lock.DAC);
spin_lock_init(&minfo->lock.accel);
init_rwsem(&minfo->crtc2.lock);
init_rwsem(&minfo->altout.lock);
mutex_init(&minfo->fbcon.mm_lock);
minfo->irq_flags = 0;
init_waitqueue_head(&minfo->crtc1.vsync.wait);
init_waitqueue_head(&minfo->crtc2.vsync.wait);
minfo->crtc1.panpos = -1;
err = initMatrox2(minfo, b);
if (!err) {
matroxfb_register_device(minfo);
return 0;
}
kfree(minfo);
return -1;
}
static void pci_remove_matrox(struct pci_dev* pdev) {
struct matrox_fb_info* minfo;
minfo = pci_get_drvdata(pdev);
matroxfb_remove(minfo, 1);
}
static const struct pci_device_id matroxfb_devices[] = {
#ifdef CONFIG_FB_MATROX_MILLENIUM
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MIL_2_AGP,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
#endif
#ifdef CONFIG_FB_MATROX_MYSTIQUE
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_MYS,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
#endif
#ifdef CONFIG_FB_MATROX_G
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_MM,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G100_AGP,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MATROX, 0x0532,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
#endif
{0, 0,
0, 0, 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, matroxfb_devices);
static struct pci_driver matroxfb_driver = {
.name = "matroxfb",
.id_table = matroxfb_devices,
.probe = matroxfb_probe,
.remove = pci_remove_matrox,
};
/* **************************** init-time only **************************** */
#define RSResolution(X) ((X) & 0x0F)
#define RS640x400 1
#define RS640x480 2
#define RS800x600 3
#define RS1024x768 4
#define RS1280x1024 5
#define RS1600x1200 6
#define RS768x576 7
#define RS960x720 8
#define RS1152x864 9
#define RS1408x1056 10
#define RS640x350 11
#define RS1056x344 12 /* 132 x 43 text */
#define RS1056x400 13 /* 132 x 50 text */
#define RS1056x480 14 /* 132 x 60 text */
#define RSNoxNo 15
/* 10-FF */
static struct { int xres, yres, left, right, upper, lower, hslen, vslen, vfreq; } timmings[] __initdata = {
{ 640, 400, 48, 16, 39, 8, 96, 2, 70 },
{ 640, 480, 48, 16, 33, 10, 96, 2, 60 },
{ 800, 600, 144, 24, 28, 8, 112, 6, 60 },
{ 1024, 768, 160, 32, 30, 4, 128, 4, 60 },
{ 1280, 1024, 224, 32, 32, 4, 136, 4, 60 },
{ 1600, 1200, 272, 48, 32, 5, 152, 5, 60 },
{ 768, 576, 144, 16, 28, 6, 112, 4, 60 },
{ 960, 720, 144, 24, 28, 8, 112, 4, 60 },
{ 1152, 864, 192, 32, 30, 4, 128, 4, 60 },
{ 1408, 1056, 256, 40, 32, 5, 144, 5, 60 },
{ 640, 350, 48, 16, 39, 8, 96, 2, 70 },
{ 1056, 344, 96, 24, 59, 44, 160, 2, 70 },
{ 1056, 400, 96, 24, 39, 8, 160, 2, 70 },
{ 1056, 480, 96, 24, 36, 12, 160, 3, 60 },
{ 0, 0, ~0, ~0, ~0, ~0, 0, 0, 0 }
};
#define RSCreate(X,Y) ((X) | ((Y) << 8))
static struct { unsigned int vesa; unsigned int info; } *RSptr, vesamap[] __initdata = {
/* default must be first */
{ ~0, RSCreate(RSNoxNo, RS8bpp ) },
{ 0x101, RSCreate(RS640x480, RS8bpp ) },
{ 0x100, RSCreate(RS640x400, RS8bpp ) },
{ 0x180, RSCreate(RS768x576, RS8bpp ) },
{ 0x103, RSCreate(RS800x600, RS8bpp ) },
{ 0x188, RSCreate(RS960x720, RS8bpp ) },
{ 0x105, RSCreate(RS1024x768, RS8bpp ) },
{ 0x190, RSCreate(RS1152x864, RS8bpp ) },
{ 0x107, RSCreate(RS1280x1024, RS8bpp ) },
{ 0x198, RSCreate(RS1408x1056, RS8bpp ) },
{ 0x11C, RSCreate(RS1600x1200, RS8bpp ) },
{ 0x110, RSCreate(RS640x480, RS15bpp) },
{ 0x181, RSCreate(RS768x576, RS15bpp) },
{ 0x113, RSCreate(RS800x600, RS15bpp) },
{ 0x189, RSCreate(RS960x720, RS15bpp) },
{ 0x116, RSCreate(RS1024x768, RS15bpp) },
{ 0x191, RSCreate(RS1152x864, RS15bpp) },
{ 0x119, RSCreate(RS1280x1024, RS15bpp) },
{ 0x199, RSCreate(RS1408x1056, RS15bpp) },
{ 0x11D, RSCreate(RS1600x1200, RS15bpp) },
{ 0x111, RSCreate(RS640x480, RS16bpp) },
{ 0x182, RSCreate(RS768x576, RS16bpp) },
{ 0x114, RSCreate(RS800x600, RS16bpp) },
{ 0x18A, RSCreate(RS960x720, RS16bpp) },
{ 0x117, RSCreate(RS1024x768, RS16bpp) },
{ 0x192, RSCreate(RS1152x864, RS16bpp) },
{ 0x11A, RSCreate(RS1280x1024, RS16bpp) },
{ 0x19A, RSCreate(RS1408x1056, RS16bpp) },
{ 0x11E, RSCreate(RS1600x1200, RS16bpp) },
{ 0x1B2, RSCreate(RS640x480, RS24bpp) },
{ 0x184, RSCreate(RS768x576, RS24bpp) },
{ 0x1B5, RSCreate(RS800x600, RS24bpp) },
{ 0x18C, RSCreate(RS960x720, RS24bpp) },
{ 0x1B8, RSCreate(RS1024x768, RS24bpp) },
{ 0x194, RSCreate(RS1152x864, RS24bpp) },
{ 0x1BB, RSCreate(RS1280x1024, RS24bpp) },
{ 0x19C, RSCreate(RS1408x1056, RS24bpp) },
{ 0x1BF, RSCreate(RS1600x1200, RS24bpp) },
{ 0x112, RSCreate(RS640x480, RS32bpp) },
{ 0x183, RSCreate(RS768x576, RS32bpp) },
{ 0x115, RSCreate(RS800x600, RS32bpp) },
{ 0x18B, RSCreate(RS960x720, RS32bpp) },
{ 0x118, RSCreate(RS1024x768, RS32bpp) },
{ 0x193, RSCreate(RS1152x864, RS32bpp) },
{ 0x11B, RSCreate(RS1280x1024, RS32bpp) },
{ 0x19B, RSCreate(RS1408x1056, RS32bpp) },
{ 0x11F, RSCreate(RS1600x1200, RS32bpp) },
{ 0x010, RSCreate(RS640x350, RS4bpp ) },
{ 0x012, RSCreate(RS640x480, RS4bpp ) },
{ 0x102, RSCreate(RS800x600, RS4bpp ) },
{ 0x104, RSCreate(RS1024x768, RS4bpp ) },
{ 0x106, RSCreate(RS1280x1024, RS4bpp ) },
{ 0, 0 }};
static void __init matroxfb_init_params(void) {
/* fh from kHz to Hz */
if (fh < 1000)
fh *= 1000; /* 1kHz minimum */
/* maxclk */
if (maxclk < 1000) maxclk *= 1000; /* kHz -> Hz, MHz -> kHz */
if (maxclk < 1000000) maxclk *= 1000; /* kHz -> Hz, 1MHz minimum */
/* fix VESA number */
if (vesa != ~0)
vesa &= 0x1DFF; /* mask out clearscreen, acceleration and so on */
/* static settings */
for (RSptr = vesamap; RSptr->vesa; RSptr++) {
if (RSptr->vesa == vesa) break;
}
if (!RSptr->vesa) {
printk(KERN_ERR "Invalid vesa mode 0x%04X\n", vesa);
RSptr = vesamap;
}
{
int res = RSResolution(RSptr->info)-1;
if (left == ~0)
left = timmings[res].left;
if (!xres)
xres = timmings[res].xres;
if (right == ~0)
right = timmings[res].right;
if (!hslen)
hslen = timmings[res].hslen;
if (upper == ~0)
upper = timmings[res].upper;
if (!yres)
yres = timmings[res].yres;
if (lower == ~0)
lower = timmings[res].lower;
if (!vslen)
vslen = timmings[res].vslen;
if (!(fv||fh||maxclk||pixclock))
fv = timmings[res].vfreq;
if (depth == -1)
depth = RSDepth(RSptr->info);
}
}
static int __init matrox_init(void) {
int err;
if (fb_modesetting_disabled("matroxfb"))
return -ENODEV;
matroxfb_init_params();
err = pci_register_driver(&matroxfb_driver);
dev = -1; /* accept all new devices... */
return err;
}
/* **************************** exit-time only **************************** */
static void __exit matrox_done(void) {
pci_unregister_driver(&matroxfb_driver);
}
#ifndef MODULE
/* ************************* init in-kernel code ************************** */
static int __init matroxfb_setup(char *options) {
char *this_opt;
DBG(__func__)
if (!options || !*options)
return 0;
while ((this_opt = strsep(&options, ",")) != NULL) {
if (!*this_opt) continue;
dprintk("matroxfb_setup: option %s\n", this_opt);
if (!strncmp(this_opt, "dev:", 4))
dev = simple_strtoul(this_opt+4, NULL, 0);
else if (!strncmp(this_opt, "depth:", 6)) {
switch (simple_strtoul(this_opt+6, NULL, 0)) {
case 0: depth = RSText; break;
case 4: depth = RS4bpp; break;
case 8: depth = RS8bpp; break;
case 15:depth = RS15bpp; break;
case 16:depth = RS16bpp; break;
case 24:depth = RS24bpp; break;
case 32:depth = RS32bpp; break;
default:
printk(KERN_ERR "matroxfb: unsupported color depth\n");
}
} else if (!strncmp(this_opt, "xres:", 5))
xres = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "yres:", 5))
yres = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "vslen:", 6))
vslen = simple_strtoul(this_opt+6, NULL, 0);
else if (!strncmp(this_opt, "hslen:", 6))
hslen = simple_strtoul(this_opt+6, NULL, 0);
else if (!strncmp(this_opt, "left:", 5))
left = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "right:", 6))
right = simple_strtoul(this_opt+6, NULL, 0);
else if (!strncmp(this_opt, "upper:", 6))
upper = simple_strtoul(this_opt+6, NULL, 0);
else if (!strncmp(this_opt, "lower:", 6))
lower = simple_strtoul(this_opt+6, NULL, 0);
else if (!strncmp(this_opt, "pixclock:", 9))
pixclock = simple_strtoul(this_opt+9, NULL, 0);
else if (!strncmp(this_opt, "sync:", 5))
sync = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "vesa:", 5))
vesa = simple_strtoul(this_opt+5, NULL, 0);
else if (!strncmp(this_opt, "maxclk:", 7))
maxclk = simple_strtoul(this_opt+7, NULL, 0);
else if (!strncmp(this_opt, "fh:", 3))
fh = simple_strtoul(this_opt+3, NULL, 0);
else if (!strncmp(this_opt, "fv:", 3))
fv = simple_strtoul(this_opt+3, NULL, 0);
else if (!strncmp(this_opt, "mem:", 4))
mem = simple_strtoul(this_opt+4, NULL, 0);
else if (!strncmp(this_opt, "mode:", 5))
strscpy(videomode, this_opt + 5, sizeof(videomode));
else if (!strncmp(this_opt, "outputs:", 8))
strscpy(outputs, this_opt + 8, sizeof(outputs));
else if (!strncmp(this_opt, "dfp:", 4)) {
dfp_type = simple_strtoul(this_opt+4, NULL, 0);
dfp = 1;
}
#ifdef CONFIG_PPC_PMAC
else if (!strncmp(this_opt, "vmode:", 6)) {
unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
if (vmode > 0 && vmode <= VMODE_MAX)
default_vmode = vmode;
} else if (!strncmp(this_opt, "cmode:", 6)) {
unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
switch (cmode) {
case 0:
case 8:
default_cmode = CMODE_8;
break;
case 15:
case 16:
default_cmode = CMODE_16;
break;
case 24:
case 32:
default_cmode = CMODE_32;
break;
}
}
#endif
else if (!strcmp(this_opt, "disabled")) /* nodisabled does not exist */
disabled = 1;
else if (!strcmp(this_opt, "enabled")) /* noenabled does not exist */
disabled = 0;
else if (!strcmp(this_opt, "sgram")) /* nosgram == sdram */
sgram = 1;
else if (!strcmp(this_opt, "sdram"))
sgram = 0;
else if (!strncmp(this_opt, "memtype:", 8))
memtype = simple_strtoul(this_opt+8, NULL, 0);
else {
int value = 1;
if (!strncmp(this_opt, "no", 2)) {
value = 0;
this_opt += 2;
}
if (! strcmp(this_opt, "inverse"))
inverse = value;
else if (!strcmp(this_opt, "accel"))
noaccel = !value;
else if (!strcmp(this_opt, "pan"))
nopan = !value;
else if (!strcmp(this_opt, "pciretry"))
no_pci_retry = !value;
else if (!strcmp(this_opt, "vga"))
novga = !value;
else if (!strcmp(this_opt, "bios"))
nobios = !value;
else if (!strcmp(this_opt, "init"))
noinit = !value;
else if (!strcmp(this_opt, "mtrr"))
mtrr = value;
else if (!strcmp(this_opt, "inv24"))
inv24 = value;
else if (!strcmp(this_opt, "cross4MB"))
cross4MB = value;
else if (!strcmp(this_opt, "grayscale"))
grayscale = value;
else if (!strcmp(this_opt, "dfp"))
dfp = value;
else {
strscpy(videomode, this_opt, sizeof(videomode));
}
}
}
return 0;
}
static int __initdata initialized = 0;
static int __init matroxfb_init(void)
{
char *option = NULL;
int err = 0;
DBG(__func__)
if (fb_get_options("matroxfb", &option))
return -ENODEV;
matroxfb_setup(option);
if (disabled)
return -ENXIO;
if (!initialized) {
initialized = 1;
err = matrox_init();
}
hotplug = 1;
/* never return failure, user can hotplug matrox later... */
return err;
}
#else
/* *************************** init module code **************************** */
MODULE_AUTHOR("(c) 1998-2002 Petr Vandrovec <[email protected]>");
MODULE_DESCRIPTION("Accelerated FBDev driver for Matrox Millennium/Mystique/G100/G200/G400/G450/G550");
MODULE_LICENSE("GPL");
module_param(mem, int, 0);
MODULE_PARM_DESC(mem, "Size of available memory in MB, KB or B (2,4,8,12,16MB, default=autodetect)");
module_param(disabled, int, 0);
MODULE_PARM_DESC(disabled, "Disabled (0 or 1=disabled) (default=0)");
module_param(noaccel, int, 0);
MODULE_PARM_DESC(noaccel, "Do not use accelerating engine (0 or 1=disabled) (default=0)");
module_param(nopan, int, 0);
MODULE_PARM_DESC(nopan, "Disable pan on startup (0 or 1=disabled) (default=0)");
module_param(no_pci_retry, int, 0);
MODULE_PARM_DESC(no_pci_retry, "PCI retries enabled (0 or 1=disabled) (default=0)");
module_param(novga, int, 0);
MODULE_PARM_DESC(novga, "VGA I/O (0x3C0-0x3DF) disabled (0 or 1=disabled) (default=0)");
module_param(nobios, int, 0);
MODULE_PARM_DESC(nobios, "Disables ROM BIOS (0 or 1=disabled) (default=do not change BIOS state)");
module_param(noinit, int, 0);
MODULE_PARM_DESC(noinit, "Disables W/SG/SD-RAM and bus interface initialization (0 or 1=do not initialize) (default=0)");
module_param(memtype, int, 0);
MODULE_PARM_DESC(memtype, "Memory type for G200/G400 (see Documentation/fb/matroxfb.rst for explanation) (default=3 for G200, 0 for G400)");
module_param(mtrr, int, 0);
MODULE_PARM_DESC(mtrr, "This speeds up video memory accesses (0=disabled or 1) (default=1)");
module_param(sgram, int, 0);
MODULE_PARM_DESC(sgram, "Indicates that G100/G200/G400 has SGRAM memory (0=SDRAM, 1=SGRAM) (default=0)");
module_param(inv24, int, 0);
MODULE_PARM_DESC(inv24, "Inverts clock polarity for 24bpp and loop frequency > 100MHz (default=do not invert polarity)");
module_param(inverse, int, 0);
MODULE_PARM_DESC(inverse, "Inverse (0 or 1) (default=0)");
module_param(dev, int, 0);
MODULE_PARM_DESC(dev, "Multihead support, attach to device ID (0..N) (default=all working)");
module_param(vesa, int, 0);
MODULE_PARM_DESC(vesa, "Startup videomode (0x000-0x1FF) (default=0x101)");
module_param(xres, int, 0);
MODULE_PARM_DESC(xres, "Horizontal resolution (px), overrides xres from vesa (default=vesa)");
module_param(yres, int, 0);
MODULE_PARM_DESC(yres, "Vertical resolution (scans), overrides yres from vesa (default=vesa)");
module_param(upper, int, 0);
MODULE_PARM_DESC(upper, "Upper blank space (scans), overrides upper from vesa (default=vesa)");
module_param(lower, int, 0);
MODULE_PARM_DESC(lower, "Lower blank space (scans), overrides lower from vesa (default=vesa)");
module_param(vslen, int, 0);
MODULE_PARM_DESC(vslen, "Vertical sync length (scans), overrides lower from vesa (default=vesa)");
module_param(left, int, 0);
MODULE_PARM_DESC(left, "Left blank space (px), overrides left from vesa (default=vesa)");
module_param(right, int, 0);
MODULE_PARM_DESC(right, "Right blank space (px), overrides right from vesa (default=vesa)");
module_param(hslen, int, 0);
MODULE_PARM_DESC(hslen, "Horizontal sync length (px), overrides hslen from vesa (default=vesa)");
module_param(pixclock, int, 0);
MODULE_PARM_DESC(pixclock, "Pixelclock (ns), overrides pixclock from vesa (default=vesa)");
module_param(sync, int, 0);
MODULE_PARM_DESC(sync, "Sync polarity, overrides sync from vesa (default=vesa)");
module_param(depth, int, 0);
MODULE_PARM_DESC(depth, "Color depth (0=text,8,15,16,24,32) (default=vesa)");
module_param(maxclk, int, 0);
MODULE_PARM_DESC(maxclk, "Startup maximal clock, 0-999MHz, 1000-999999kHz, 1000000-INF Hz");
module_param(fh, int, 0);
MODULE_PARM_DESC(fh, "Startup horizontal frequency, 0-999kHz, 1000-INF Hz");
module_param(fv, int, 0);
MODULE_PARM_DESC(fv, "Startup vertical frequency, 0-INF Hz\n"
"You should specify \"fv:max_monitor_vsync,fh:max_monitor_hsync,maxclk:max_monitor_dotclock\"");
module_param(grayscale, int, 0);
MODULE_PARM_DESC(grayscale, "Sets display into grayscale. Works perfectly with paletized videomode (4, 8bpp), some limitations apply to 16, 24 and 32bpp videomodes (default=nograyscale)");
module_param(cross4MB, int, 0);
MODULE_PARM_DESC(cross4MB, "Specifies that 4MB boundary can be in middle of line. (default=autodetected)");
module_param(dfp, int, 0);
MODULE_PARM_DESC(dfp, "Specifies whether to use digital flat panel interface of G200/G400 (0 or 1) (default=0)");
module_param(dfp_type, int, 0);
MODULE_PARM_DESC(dfp_type, "Specifies DFP interface type (0 to 255) (default=read from hardware)");
module_param_string(outputs, outputs, sizeof(outputs), 0);
MODULE_PARM_DESC(outputs, "Specifies which CRTC is mapped to which output (string of up to three letters, consisting of 0 (disabled), 1 (CRTC1), 2 (CRTC2)) (default=111 for Gx50, 101 for G200/G400 with DFP, and 100 for all other devices)");
#ifdef CONFIG_PPC_PMAC
module_param_named(vmode, default_vmode, int, 0);
MODULE_PARM_DESC(vmode, "Specify the vmode mode number that should be used (640x480 default)");
module_param_named(cmode, default_cmode, int, 0);
MODULE_PARM_DESC(cmode, "Specify the video depth that should be used (8bit default)");
#endif
static int __init matroxfb_init(void){
DBG(__func__)
if (disabled)
return -ENXIO;
if (depth == 0)
depth = RSText;
else if (depth == 4)
depth = RS4bpp;
else if (depth == 8)
depth = RS8bpp;
else if (depth == 15)
depth = RS15bpp;
else if (depth == 16)
depth = RS16bpp;
else if (depth == 24)
depth = RS24bpp;
else if (depth == 32)
depth = RS32bpp;
else if (depth != -1) {
printk(KERN_ERR "matroxfb: depth %d is not supported, using default\n", depth);
depth = -1;
}
matrox_init();
/* never return failure; user can hotplug matrox later... */
return 0;
}
#endif /* MODULE */
module_init(matroxfb_init);
module_exit(matrox_done);
EXPORT_SYMBOL(matroxfb_register_driver);
EXPORT_SYMBOL(matroxfb_unregister_driver);
EXPORT_SYMBOL(matroxfb_wait_for_sync);
EXPORT_SYMBOL(matroxfb_enable_irq);
| linux-master | drivers/video/fbdev/matrox/matroxfb_base.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Portions Copyright (c) 2001 Matrox Graphics Inc.
*
* Version: 1.65 2002/08/14
*
* MTRR stuff: 1998 Tom Rini <[email protected]>
*
* Contributors: "menion?" <[email protected]>
* Betatesting, fixes, ideas
*
* "Kurt Garloff" <[email protected]>
* Betatesting, fixes, ideas, videomodes, videomodes timmings
*
* "Tom Rini" <[email protected]>
* MTRR stuff, PPC cleanups, betatesting, fixes, ideas
*
* "Bibek Sahu" <[email protected]>
* Access device through readb|w|l and write b|w|l
* Extensive debugging stuff
*
* "Daniel Haun" <[email protected]>
* Testing, hardware cursor fixes
*
* "Scott Wood" <[email protected]>
* Fixes
*
* "Gerd Knorr" <[email protected]>
* Betatesting
*
* "Kelly French" <[email protected]>
* "Fernando Herrera" <[email protected]>
* Betatesting, bug reporting
*
* "Pablo Bianucci" <[email protected]>
* Fixes, ideas, betatesting
*
* "Inaky Perez Gonzalez" <[email protected]>
* Fixes, enhandcements, ideas, betatesting
*
* "Ryuichi Oikawa" <[email protected]>
* PPC betatesting, PPC support, backward compatibility
*
* "Paul Womar" <[email protected]>
* "Owen Waller" <[email protected]>
* PPC betatesting
*
* "Thomas Pornin" <[email protected]>
* Alpha betatesting
*
* "Pieter van Leuven" <[email protected]>
* "Ulf Jaenicke-Roessler" <[email protected]>
* G100 testing
*
* "H. Peter Arvin" <[email protected]>
* Ideas
*
* "Cort Dougan" <[email protected]>
* CHRP fixes and PReP cleanup
*
* "Mark Vojkovich" <[email protected]>
* G400 support
*
* (following author is not in any relation with this code, but his code
* is included in this driver)
*
* Based on framebuffer driver for VBE 2.0 compliant graphic boards
* (c) 1998 Gerd Knorr <[email protected]>
*
* (following author is not in any relation with this code, but his ideas
* were used when writing this driver)
*
* FreeVBE/AF (Matrox), "Shawn Hargreaves" <[email protected]>
*
*/
#include "matroxfb_Ti3026.h"
#include "matroxfb_misc.h"
#include "matroxfb_accel.h"
#include <linux/matroxfb.h>
#ifdef CONFIG_FB_MATROX_MILLENIUM
#define outTi3026 matroxfb_DAC_out
#define inTi3026 matroxfb_DAC_in
#define TVP3026_INDEX 0x00
#define TVP3026_PALWRADD 0x00
#define TVP3026_PALDATA 0x01
#define TVP3026_PIXRDMSK 0x02
#define TVP3026_PALRDADD 0x03
#define TVP3026_CURCOLWRADD 0x04
#define TVP3026_CLOVERSCAN 0x00
#define TVP3026_CLCOLOR0 0x01
#define TVP3026_CLCOLOR1 0x02
#define TVP3026_CLCOLOR2 0x03
#define TVP3026_CURCOLDATA 0x05
#define TVP3026_CURCOLRDADD 0x07
#define TVP3026_CURCTRL 0x09
#define TVP3026_X_DATAREG 0x0A
#define TVP3026_CURRAMDATA 0x0B
#define TVP3026_CURPOSXL 0x0C
#define TVP3026_CURPOSXH 0x0D
#define TVP3026_CURPOSYL 0x0E
#define TVP3026_CURPOSYH 0x0F
#define TVP3026_XSILICONREV 0x01
#define TVP3026_XCURCTRL 0x06
#define TVP3026_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */
#define TVP3026_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
#define TVP3026_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
#define TVP3026_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
#define TVP3026_XCURCTRL_BLANK2048 0x00
#define TVP3026_XCURCTRL_BLANK4096 0x10
#define TVP3026_XCURCTRL_INTERLACED 0x20
#define TVP3026_XCURCTRL_ODD 0x00 /* ext.signal ODD/\EVEN */
#define TVP3026_XCURCTRL_EVEN 0x40 /* ext.signal EVEN/\ODD */
#define TVP3026_XCURCTRL_INDIRECT 0x00
#define TVP3026_XCURCTRL_DIRECT 0x80
#define TVP3026_XLATCHCTRL 0x0F
#define TVP3026_XLATCHCTRL_1_1 0x06
#define TVP3026_XLATCHCTRL_2_1 0x07
#define TVP3026_XLATCHCTRL_4_1 0x06
#define TVP3026_XLATCHCTRL_8_1 0x06
#define TVP3026_XLATCHCTRL_16_1 0x06
#define TVP3026A_XLATCHCTRL_4_3 0x06 /* ??? do not understand... but it works... !!! */
#define TVP3026A_XLATCHCTRL_8_3 0x07
#define TVP3026B_XLATCHCTRL_4_3 0x08
#define TVP3026B_XLATCHCTRL_8_3 0x06 /* ??? do not understand... but it works... !!! */
#define TVP3026_XTRUECOLORCTRL 0x18
#define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL 0x00
#define TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP 0x20
#define TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR 0x80
#define TVP3026_XTRUECOLORCTRL_TRUECOLOR 0x40 /* paletized */
#define TVP3026_XTRUECOLORCTRL_DIRECTCOLOR 0x00
#define TVP3026_XTRUECOLORCTRL_24_ALTERNATE 0x08 /* 5:4/5:2 instead of 4:3/8:3 */
#define TVP3026_XTRUECOLORCTRL_RGB_888 0x16 /* 4:3/8:3 (or 5:4/5:2) */
#define TVP3026_XTRUECOLORCTRL_BGR_888 0x17
#define TVP3026_XTRUECOLORCTRL_ORGB_8888 0x06
#define TVP3026_XTRUECOLORCTRL_BGRO_8888 0x07
#define TVP3026_XTRUECOLORCTRL_RGB_565 0x05
#define TVP3026_XTRUECOLORCTRL_ORGB_1555 0x04
#define TVP3026_XTRUECOLORCTRL_RGB_664 0x03
#define TVP3026_XTRUECOLORCTRL_RGBO_4444 0x01
#define TVP3026_XMUXCTRL 0x19
#define TVP3026_XMUXCTRL_MEMORY_8BIT 0x01 /* - */
#define TVP3026_XMUXCTRL_MEMORY_16BIT 0x02 /* - */
#define TVP3026_XMUXCTRL_MEMORY_32BIT 0x03 /* 2MB RAM, 512K * 4 */
#define TVP3026_XMUXCTRL_MEMORY_64BIT 0x04 /* >2MB RAM, 512K * 8 & more */
#define TVP3026_XMUXCTRL_PIXEL_4BIT 0x40 /* L0,H0,L1,H1... */
#define TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED 0x60 /* H0,L0,H1,L1... */
#define TVP3026_XMUXCTRL_PIXEL_8BIT 0x48
#define TVP3026_XMUXCTRL_PIXEL_16BIT 0x50
#define TVP3026_XMUXCTRL_PIXEL_32BIT 0x58
#define TVP3026_XMUXCTRL_VGA 0x98 /* VGA MEMORY, 8BIT PIXEL */
#define TVP3026_XCLKCTRL 0x1A
#define TVP3026_XCLKCTRL_DIV1 0x00
#define TVP3026_XCLKCTRL_DIV2 0x10
#define TVP3026_XCLKCTRL_DIV4 0x20
#define TVP3026_XCLKCTRL_DIV8 0x30
#define TVP3026_XCLKCTRL_DIV16 0x40
#define TVP3026_XCLKCTRL_DIV32 0x50
#define TVP3026_XCLKCTRL_DIV64 0x60
#define TVP3026_XCLKCTRL_CLKSTOPPED 0x70
#define TVP3026_XCLKCTRL_SRC_CLK0 0x00
#define TVP3026_XCLKCTRL_SRC_CLK1 0x01
#define TVP3026_XCLKCTRL_SRC_CLK2 0x02 /* CLK2 is TTL source*/
#define TVP3026_XCLKCTRL_SRC_NCLK2 0x03 /* not CLK2 is TTL source */
#define TVP3026_XCLKCTRL_SRC_ECLK2 0x04 /* CLK2 and not CLK2 is ECL source */
#define TVP3026_XCLKCTRL_SRC_PLL 0x05
#define TVP3026_XCLKCTRL_SRC_DIS 0x06 /* disable & poweroff internal clock */
#define TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
#define TVP3026_XPALETTEPAGE 0x1C
#define TVP3026_XGENCTRL 0x1D
#define TVP3026_XGENCTRL_HSYNC_POS 0x00
#define TVP3026_XGENCTRL_HSYNC_NEG 0x01
#define TVP3026_XGENCTRL_VSYNC_POS 0x00
#define TVP3026_XGENCTRL_VSYNC_NEG 0x02
#define TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
#define TVP3026_XGENCTRL_BIG_ENDIAN 0x08
#define TVP3026_XGENCTRL_BLACK_0IRE 0x00
#define TVP3026_XGENCTRL_BLACK_75IRE 0x10
#define TVP3026_XGENCTRL_NO_SYNC_ON_GREEN 0x00
#define TVP3026_XGENCTRL_SYNC_ON_GREEN 0x20
#define TVP3026_XGENCTRL_OVERSCAN_DIS 0x00
#define TVP3026_XGENCTRL_OVERSCAN_EN 0x40
#define TVP3026_XMISCCTRL 0x1E
#define TVP3026_XMISCCTRL_DAC_PUP 0x00
#define TVP3026_XMISCCTRL_DAC_PDOWN 0x01
#define TVP3026_XMISCCTRL_DAC_EXT 0x00 /* or 8, bit 3 is ignored */
#define TVP3026_XMISCCTRL_DAC_6BIT 0x04
#define TVP3026_XMISCCTRL_DAC_8BIT 0x0C
#define TVP3026_XMISCCTRL_PSEL_DIS 0x00
#define TVP3026_XMISCCTRL_PSEL_EN 0x10
#define TVP3026_XMISCCTRL_PSEL_LOW 0x00 /* PSEL high selects directcolor */
#define TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
#define TVP3026_XGENIOCTRL 0x2A
#define TVP3026_XGENIODATA 0x2B
#define TVP3026_XPLLADDR 0x2C
#define TVP3026_XPLLADDR_X(LOOP,MCLK,PIX) (((LOOP)<<4) | ((MCLK)<<2) | (PIX))
#define TVP3026_XPLLDATA_N 0x00
#define TVP3026_XPLLDATA_M 0x01
#define TVP3026_XPLLDATA_P 0x02
#define TVP3026_XPLLDATA_STAT 0x03
#define TVP3026_XPIXPLLDATA 0x2D
#define TVP3026_XMEMPLLDATA 0x2E
#define TVP3026_XLOOPPLLDATA 0x2F
#define TVP3026_XCOLKEYOVRMIN 0x30
#define TVP3026_XCOLKEYOVRMAX 0x31
#define TVP3026_XCOLKEYREDMIN 0x32
#define TVP3026_XCOLKEYREDMAX 0x33
#define TVP3026_XCOLKEYGREENMIN 0x34
#define TVP3026_XCOLKEYGREENMAX 0x35
#define TVP3026_XCOLKEYBLUEMIN 0x36
#define TVP3026_XCOLKEYBLUEMAX 0x37
#define TVP3026_XCOLKEYCTRL 0x38
#define TVP3026_XCOLKEYCTRL_OVR_EN 0x01
#define TVP3026_XCOLKEYCTRL_RED_EN 0x02
#define TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
#define TVP3026_XCOLKEYCTRL_BLUE_EN 0x08
#define TVP3026_XCOLKEYCTRL_NEGATE 0x10
#define TVP3026_XCOLKEYCTRL_ZOOM1 0x00
#define TVP3026_XCOLKEYCTRL_ZOOM2 0x20
#define TVP3026_XCOLKEYCTRL_ZOOM4 0x40
#define TVP3026_XCOLKEYCTRL_ZOOM8 0x60
#define TVP3026_XCOLKEYCTRL_ZOOM16 0x80
#define TVP3026_XCOLKEYCTRL_ZOOM32 0xA0
#define TVP3026_XMEMPLLCTRL 0x39
#define TVP3026_XMEMPLLCTRL_DIV(X) (((X)-1)>>1) /* 2,4,6,8,10,12,14,16, division applied to LOOP PLL after divide by 2^P */
#define TVP3026_XMEMPLLCTRL_STROBEMKC4 0x08
#define TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK 0x00 /* MKC4 */
#define TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL 0x10 /* MKC4 */
#define TVP3026_XMEMPLLCTRL_RCLK_PIXPLL 0x00
#define TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL 0x20
#define TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN 0x40 /* dot clock divided by loop pclk N prescaler */
#define TVP3026_XSENSETEST 0x3A
#define TVP3026_XTESTMODEDATA 0x3B
#define TVP3026_XCRCREML 0x3C
#define TVP3026_XCRCREMH 0x3D
#define TVP3026_XCRCBITSEL 0x3E
#define TVP3026_XID 0x3F
static const unsigned char DACseq[] =
{ TVP3026_XLATCHCTRL, TVP3026_XTRUECOLORCTRL,
TVP3026_XMUXCTRL, TVP3026_XCLKCTRL,
TVP3026_XPALETTEPAGE,
TVP3026_XGENCTRL,
TVP3026_XMISCCTRL,
TVP3026_XGENIOCTRL,
TVP3026_XGENIODATA,
TVP3026_XCOLKEYOVRMIN, TVP3026_XCOLKEYOVRMAX, TVP3026_XCOLKEYREDMIN, TVP3026_XCOLKEYREDMAX,
TVP3026_XCOLKEYGREENMIN, TVP3026_XCOLKEYGREENMAX, TVP3026_XCOLKEYBLUEMIN, TVP3026_XCOLKEYBLUEMAX,
TVP3026_XCOLKEYCTRL,
TVP3026_XMEMPLLCTRL, TVP3026_XSENSETEST, TVP3026_XCURCTRL };
#define POS3026_XLATCHCTRL 0
#define POS3026_XTRUECOLORCTRL 1
#define POS3026_XMUXCTRL 2
#define POS3026_XCLKCTRL 3
#define POS3026_XGENCTRL 5
#define POS3026_XMISCCTRL 6
#define POS3026_XMEMPLLCTRL 18
#define POS3026_XCURCTRL 20
static const unsigned char MGADACbpp32[] =
{ TVP3026_XLATCHCTRL_2_1, TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_8888,
0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
0x00,
TVP3026_XGENCTRL_HSYNC_POS | TVP3026_XGENCTRL_VSYNC_POS | TVP3026_XGENCTRL_LITTLE_ENDIAN | TVP3026_XGENCTRL_BLACK_0IRE | TVP3026_XGENCTRL_NO_SYNC_ON_GREEN | TVP3026_XGENCTRL_OVERSCAN_DIS,
TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_HIGH,
0x00,
0x1E,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
TVP3026_XCOLKEYCTRL_ZOOM1,
0x00, 0x00, TVP3026_XCURCTRL_DIS };
static int Ti3026_calcclock(const struct matrox_fb_info *minfo,
unsigned int freq, unsigned int fmax, int *in,
int *feed, int *post)
{
unsigned int fvco;
unsigned int lin, lfeed, lpost;
DBG(__func__)
fvco = PLL_calcclock(minfo, freq, fmax, &lin, &lfeed, &lpost);
fvco >>= (*post = lpost);
*in = 64 - lin;
*feed = 64 - lfeed;
return fvco;
}
static int Ti3026_setpclk(struct matrox_fb_info *minfo, int clk)
{
unsigned int f_pll;
unsigned int pixfeed, pixin, pixpost;
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
f_pll = Ti3026_calcclock(minfo, clk, minfo->max_pixel_clock, &pixin, &pixfeed, &pixpost);
hw->DACclk[0] = pixin | 0xC0;
hw->DACclk[1] = pixfeed;
hw->DACclk[2] = pixpost | 0xB0;
{
unsigned int loopfeed, loopin, looppost, loopdiv, z;
unsigned int Bpp;
Bpp = minfo->curr.final_bppShift;
if (minfo->fbcon.var.bits_per_pixel == 24) {
loopfeed = 3; /* set lm to any possible value */
loopin = 3 * 32 / Bpp;
} else {
loopfeed = 4;
loopin = 4 * 32 / Bpp;
}
z = (110000 * loopin) / (f_pll * loopfeed);
loopdiv = 0; /* div 2 */
if (z < 2)
looppost = 0;
else if (z < 4)
looppost = 1;
else if (z < 8)
looppost = 2;
else {
looppost = 3;
loopdiv = z/16;
}
if (minfo->fbcon.var.bits_per_pixel == 24) {
hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
hw->DACclk[4] = (65 - loopfeed) | 0x80;
if (minfo->accel.ramdac_rev > 0x20) {
if (isInterleave(minfo))
hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
else {
hw->DACclk[4] &= ~0xC0;
hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
}
} else {
if (isInterleave(minfo))
; /* default... */
else {
hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
hw->DACreg[POS3026_XLATCHCTRL] = TVP3026A_XLATCHCTRL_4_3;
}
}
hw->DACclk[5] = looppost | 0xF8;
if (minfo->devflags.mga_24bpp_fix)
hw->DACclk[5] ^= 0x40;
} else {
hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
hw->DACclk[4] = 65 - loopfeed;
hw->DACclk[5] = looppost | 0xF0;
}
hw->DACreg[POS3026_XMEMPLLCTRL] = loopdiv | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL;
}
return 0;
}
static int Ti3026_init(struct matrox_fb_info *minfo, struct my_timming *m)
{
u_int8_t muxctrl = isInterleave(minfo) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
memcpy(hw->DACreg, MGADACbpp32, sizeof(MGADACbpp32));
switch (minfo->fbcon.var.bits_per_pixel) {
case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV8;
hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
break;
case 8: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_8_1; /* or _4_1, they are same */
hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_8BIT;
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
hw->DACreg[POS3026_XMISCCTRL] = TVP3026_XMISCCTRL_DAC_PUP | TVP3026_XMISCCTRL_DAC_8BIT | TVP3026_XMISCCTRL_PSEL_DIS | TVP3026_XMISCCTRL_PSEL_LOW;
break;
case 16:
/* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used every time) */
hw->DACreg[POS3026_XTRUECOLORCTRL] = (minfo->fbcon.var.green.length == 5) ? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
break;
case 24:
/* XLATCHCTRL is: for (A) use _4_3 (?_8_3 is same? TBD), for (B) it is set in setpclk */
hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_888;
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV4;
break;
case 32:
/* XLATCHCTRL should be _2_1 / _1_1... Why is not? (_2_1 is used every time) */
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_32BIT;
break;
default:
return 1; /* TODO: failed */
}
if (matroxfb_vgaHWinit(minfo, m)) return 1;
/* set SYNC */
hw->MiscOutReg = 0xCB;
if (m->sync & FB_SYNC_HOR_HIGH_ACT)
hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_HSYNC_NEG;
if (m->sync & FB_SYNC_VERT_HIGH_ACT)
hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_VSYNC_NEG;
if (m->sync & FB_SYNC_ON_GREEN)
hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
/* set DELAY */
if (minfo->video.len < 0x400000)
hw->CRTCEXT[3] |= 0x08;
else if (minfo->video.len > 0x400000)
hw->CRTCEXT[3] |= 0x10;
/* set HWCURSOR */
if (m->interlaced) {
hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_INTERLACED;
}
if (m->HTotal >= 1536)
hw->DACreg[POS3026_XCURCTRL] |= TVP3026_XCURCTRL_BLANK4096;
/* set interleaving */
hw->MXoptionReg &= ~0x00001000;
if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000;
/* set DAC */
Ti3026_setpclk(minfo, m->pixclock);
return 0;
}
static void ti3026_setMCLK(struct matrox_fb_info *minfo, int fout)
{
unsigned int f_pll;
unsigned int pclk_m, pclk_n, pclk_p;
unsigned int mclk_m, mclk_n, mclk_p;
unsigned int rfhcnt, mclk_ctl;
int tmout;
DBG(__func__)
f_pll = Ti3026_calcclock(minfo, fout, minfo->max_pixel_clock, &mclk_n, &mclk_m, &mclk_p);
/* save pclk */
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
pclk_n = inTi3026(minfo, TVP3026_XPIXPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFD);
pclk_m = inTi3026(minfo, TVP3026_XPIXPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
pclk_p = inTi3026(minfo, TVP3026_XPIXPLLDATA);
/* stop pclk */
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
/* set pclk to new mclk */
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_m);
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
/* wait for PLL to lock */
for (tmout = 500000; tmout; tmout--) {
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
break;
udelay(10);
}
if (!tmout)
printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
/* output pclk on mclk pin */
mclk_ctl = inTi3026(minfo, TVP3026_XMEMPLLCTRL);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
/* stop MCLK */
outTi3026(minfo, TVP3026_XPLLADDR, 0xFB);
outTi3026(minfo, TVP3026_XMEMPLLDATA, 0x00);
/* set mclk to new freq */
outTi3026(minfo, TVP3026_XPLLADDR, 0xF3);
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_m);
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
/* wait for PLL to lock */
for (tmout = 500000; tmout; tmout--) {
if (inTi3026(minfo, TVP3026_XMEMPLLDATA) & 0x40)
break;
udelay(10);
}
if (!tmout)
printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
f_pll = f_pll * 333 / (10000 << mclk_p);
if (isMilleniumII(minfo)) {
rfhcnt = (f_pll - 128) / 256;
if (rfhcnt > 15)
rfhcnt = 15;
} else {
rfhcnt = (f_pll - 64) / 128;
if (rfhcnt > 15)
rfhcnt = 0;
}
minfo->hw.MXoptionReg = (minfo->hw.MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
/* output MCLK to MCLK pin */
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
/* stop PCLK */
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
/* restore pclk */
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_n);
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_m);
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_p);
/* wait for PLL to lock */
for (tmout = 500000; tmout; tmout--) {
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
break;
udelay(10);
}
if (!tmout)
printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
}
static void ti3026_ramdac_init(struct matrox_fb_info *minfo)
{
DBG(__func__)
minfo->features.pll.vco_freq_min = 110000;
minfo->features.pll.ref_freq = 114545;
minfo->features.pll.feed_div_min = 2;
minfo->features.pll.feed_div_max = 24;
minfo->features.pll.in_div_min = 2;
minfo->features.pll.in_div_max = 63;
minfo->features.pll.post_shift_max = 3;
if (minfo->devflags.noinit)
return;
ti3026_setMCLK(minfo, 60000);
}
static void Ti3026_restore(struct matrox_fb_info *minfo)
{
int i;
unsigned char progdac[6];
struct matrox_hw_state *hw = &minfo->hw;
CRITFLAGS
DBG(__func__)
#ifdef DEBUG
dprintk(KERN_INFO "EXTVGA regs: ");
for (i = 0; i < 6; i++)
dprintk("%02X:", hw->CRTCEXT[i]);
dprintk("\n");
#endif
CRITBEGIN
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
CRITEND
matroxfb_vgaHWrestore(minfo);
CRITBEGIN
minfo->crtc1.panpos = -1;
for (i = 0; i < 6; i++)
mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
for (i = 0; i < 21; i++) {
outTi3026(minfo, DACseq[i], hw->DACreg[i]);
}
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
progdac[0] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
progdac[3] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0x15);
progdac[1] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
progdac[4] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
progdac[2] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
progdac[5] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
CRITEND
if (memcmp(hw->DACclk, progdac, 6)) {
/* agrhh... setting up PLL is very slow on Millennium... */
/* Mystique PLL is locked in few ms, but Millennium PLL lock takes about 0.15 s... */
/* Maybe even we should call schedule() ? */
CRITBEGIN
outTi3026(minfo, TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0);
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0);
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
for (i = 0; i < 3; i++)
outTi3026(minfo, TVP3026_XPIXPLLDATA, hw->DACclk[i]);
/* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
if (hw->MiscOutReg & 0x08) {
int tmout;
outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
for (tmout = 500000; tmout; --tmout) {
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
break;
udelay(10);
}
CRITEND
if (!tmout)
printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
else
dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
CRITBEGIN
}
outTi3026(minfo, TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
for (i = 3; i < 6; i++)
outTi3026(minfo, TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
CRITEND
if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
int tmout;
CRITBEGIN
outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
for (tmout = 500000; tmout; --tmout) {
if (inTi3026(minfo, TVP3026_XLOOPPLLDATA) & 0x40)
break;
udelay(10);
}
CRITEND
if (!tmout)
printk(KERN_ERR "matroxfb: Loop PLL not locked after 5 secs\n");
else
dprintk(KERN_INFO "LoopPLL: %d\n", 500000-tmout);
}
}
#ifdef DEBUG
dprintk(KERN_DEBUG "3026DACregs ");
for (i = 0; i < 21; i++) {
dprintk("R%02X=%02X ", DACseq[i], hw->DACreg[i]);
if ((i & 0x7) == 0x7) dprintk(KERN_DEBUG "continuing... ");
}
dprintk(KERN_DEBUG "DACclk ");
for (i = 0; i < 6; i++)
dprintk("C%02X=%02X ", i, hw->DACclk[i]);
dprintk("\n");
#endif
}
static void Ti3026_reset(struct matrox_fb_info *minfo)
{
DBG(__func__)
ti3026_ramdac_init(minfo);
}
static struct matrox_altout ti3026_output = {
.name = "Primary output",
};
static int Ti3026_preinit(struct matrox_fb_info *minfo)
{
static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
1024, 1152, 1280, 1600, 1664, 1920,
2048, 0};
static const int vxres_mill1[] = { 640, 768, 800, 960,
1024, 1152, 1280, 1600, 1920,
2048, 0};
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
minfo->millenium = 1;
minfo->milleniumII = (minfo->pcidev->device != PCI_DEVICE_ID_MATROX_MIL);
minfo->capable.cfb4 = 1;
minfo->capable.text = 1; /* isMilleniumII(minfo); */
minfo->capable.vxres = isMilleniumII(minfo) ? vxres_mill2 : vxres_mill1;
minfo->outputs[0].data = minfo;
minfo->outputs[0].output = &ti3026_output;
minfo->outputs[0].src = minfo->outputs[0].default_src;
minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
if (minfo->devflags.noinit)
return 0;
/* preserve VGA I/O, BIOS and PPC */
hw->MXoptionReg &= 0xC0000100;
hw->MXoptionReg |= 0x002C0000;
if (minfo->devflags.novga)
hw->MXoptionReg &= ~0x00000100;
if (minfo->devflags.nobios)
hw->MXoptionReg &= ~0x40000000;
if (minfo->devflags.nopciretry)
hw->MXoptionReg |= 0x20000000;
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
minfo->accel.ramdac_rev = inTi3026(minfo, TVP3026_XSILICONREV);
outTi3026(minfo, TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
outTi3026(minfo, TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
outTi3026(minfo, TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0x00);
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
mga_outb(M_MISC_REG, 0x67);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
mga_outl(M_RESET, 1);
udelay(250);
mga_outl(M_RESET, 0);
udelay(250);
mga_outl(M_MACCESS, 0x00008000);
udelay(10);
return 0;
}
struct matrox_switch matrox_millennium = {
.preinit = Ti3026_preinit,
.reset = Ti3026_reset,
.init = Ti3026_init,
.restore = Ti3026_restore
};
EXPORT_SYMBOL(matrox_millennium);
#endif
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/matrox/matroxfb_Ti3026.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Portions Copyright (c) 2001 Matrox Graphics Inc.
*
* Version: 1.65 2002/08/14
*
* See matroxfb_base.c for contributors.
*
*/
#include "matroxfb_maven.h"
#include "matroxfb_misc.h"
#include "matroxfb_DAC1064.h"
#include <linux/i2c.h>
#include <linux/matroxfb.h>
#include <linux/slab.h>
#include <asm/div64.h>
#define MGATVO_B 1
#define MGATVO_C 2
static const struct maven_gamma {
unsigned char reg83;
unsigned char reg84;
unsigned char reg85;
unsigned char reg86;
unsigned char reg87;
unsigned char reg88;
unsigned char reg89;
unsigned char reg8a;
unsigned char reg8b;
} maven_gamma[] = {
{ 131, 57, 223, 15, 117, 212, 251, 91, 156},
{ 133, 61, 128, 63, 180, 147, 195, 100, 180},
{ 131, 19, 63, 31, 50, 66, 171, 64, 176},
{ 0, 0, 0, 31, 16, 16, 16, 100, 200},
{ 8, 23, 47, 73, 147, 244, 220, 80, 195},
{ 22, 43, 64, 80, 147, 115, 58, 85, 168},
{ 34, 60, 80, 214, 147, 212, 188, 85, 167},
{ 45, 77, 96, 216, 147, 99, 91, 85, 159},
{ 56, 76, 112, 107, 147, 212, 148, 64, 144},
{ 65, 91, 128, 137, 147, 196, 17, 69, 148},
{ 72, 104, 136, 138, 147, 180, 245, 73, 147},
{ 87, 116, 143, 126, 16, 83, 229, 77, 144},
{ 95, 119, 152, 254, 244, 83, 221, 77, 151},
{ 100, 129, 159, 156, 244, 148, 197, 77, 160},
{ 105, 141, 167, 247, 244, 132, 181, 84, 166},
{ 105, 147, 168, 247, 244, 245, 181, 90, 170},
{ 120, 153, 175, 248, 212, 229, 165, 90, 180},
{ 119, 156, 176, 248, 244, 229, 84, 74, 160},
{ 119, 158, 183, 248, 244, 229, 149, 78, 165}
};
/* Definition of the various controls */
struct mctl {
struct v4l2_queryctrl desc;
size_t control;
};
#define BLMIN 0x0FF
#define WLMAX 0x3FF
static const struct mctl maven_controls[] =
{ { { V4L2_CID_BRIGHTNESS, V4L2_CTRL_TYPE_INTEGER,
"brightness",
0, WLMAX - BLMIN, 1, 379 - BLMIN,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.brightness) },
{ { V4L2_CID_CONTRAST, V4L2_CTRL_TYPE_INTEGER,
"contrast",
0, 1023, 1, 127,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.contrast) },
{ { V4L2_CID_SATURATION, V4L2_CTRL_TYPE_INTEGER,
"saturation",
0, 255, 1, 155,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.saturation) },
{ { V4L2_CID_HUE, V4L2_CTRL_TYPE_INTEGER,
"hue",
0, 255, 1, 0,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.hue) },
{ { V4L2_CID_GAMMA, V4L2_CTRL_TYPE_INTEGER,
"gamma",
0, ARRAY_SIZE(maven_gamma) - 1, 1, 3,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.gamma) },
{ { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN,
"test output",
0, 1, 1, 0,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
{ { MATROXFB_CID_DEFLICKER, V4L2_CTRL_TYPE_INTEGER,
"deflicker mode",
0, 2, 1, 0,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.deflicker) },
};
#define MAVCTRLS ARRAY_SIZE(maven_controls)
/* Return: positive number: id found
-EINVAL: id not found, return failure
-ENOENT: id not found, create fake disabled control */
static int get_ctrl_id(__u32 v4l2_id) {
int i;
for (i = 0; i < MAVCTRLS; i++) {
if (v4l2_id < maven_controls[i].desc.id) {
if (maven_controls[i].desc.id == 0x08000000) {
return -EINVAL;
}
return -ENOENT;
}
if (v4l2_id == maven_controls[i].desc.id) {
return i;
}
}
return -EINVAL;
}
struct maven_data {
struct matrox_fb_info* primary_head;
struct i2c_client *client;
int version;
};
static int* get_ctrl_ptr(struct maven_data* md, int idx) {
return (int*)((char*)(md->primary_head) + maven_controls[idx].control);
}
static int maven_get_reg(struct i2c_client* c, char reg) {
char dst;
struct i2c_msg msgs[] = {
{
.addr = c->addr,
.flags = I2C_M_REV_DIR_ADDR,
.len = sizeof(reg),
.buf = ®
},
{
.addr = c->addr,
.flags = I2C_M_RD | I2C_M_NOSTART,
.len = sizeof(dst),
.buf = &dst
}
};
s32 err;
err = i2c_transfer(c->adapter, msgs, 2);
if (err < 0)
printk(KERN_INFO "ReadReg(%d) failed\n", reg);
return dst & 0xFF;
}
static int maven_set_reg(struct i2c_client* c, int reg, int val) {
s32 err;
err = i2c_smbus_write_byte_data(c, reg, val);
if (err)
printk(KERN_INFO "WriteReg(%d) failed\n", reg);
return err;
}
static int maven_set_reg_pair(struct i2c_client* c, int reg, int val) {
s32 err;
err = i2c_smbus_write_word_data(c, reg, val);
if (err)
printk(KERN_INFO "WriteRegPair(%d) failed\n", reg);
return err;
}
static const struct matrox_pll_features maven_pll = {
50000,
27000,
4, 127,
2, 31,
3
};
struct matrox_pll_features2 {
unsigned int vco_freq_min;
unsigned int vco_freq_max;
unsigned int feed_div_min;
unsigned int feed_div_max;
unsigned int in_div_min;
unsigned int in_div_max;
unsigned int post_shift_max;
};
struct matrox_pll_ctl {
unsigned int ref_freq;
unsigned int den;
};
static const struct matrox_pll_features2 maven1000_pll = {
.vco_freq_min = 50000000,
.vco_freq_max = 300000000,
.feed_div_min = 5,
.feed_div_max = 128,
.in_div_min = 3,
.in_div_max = 32,
.post_shift_max = 3
};
static const struct matrox_pll_ctl maven_PAL = {
.ref_freq = 540000,
.den = 50
};
static const struct matrox_pll_ctl maven_NTSC = {
.ref_freq = 450450, /* 27027000/60 == 27000000/59.94005994 */
.den = 60
};
static int matroxfb_PLL_mavenclock(const struct matrox_pll_features2* pll,
const struct matrox_pll_ctl* ctl,
unsigned int htotal, unsigned int vtotal,
unsigned int* in, unsigned int* feed, unsigned int* post,
unsigned int* h2) {
unsigned int besth2 = 0;
unsigned int fxtal = ctl->ref_freq;
unsigned int fmin = pll->vco_freq_min / ctl->den;
unsigned int fwant;
unsigned int p;
unsigned int scrlen;
unsigned int fmax;
DBG(__func__)
scrlen = htotal * (vtotal - 1);
fwant = htotal * vtotal;
fmax = pll->vco_freq_max / ctl->den;
dprintk(KERN_DEBUG "want: %u, xtal: %u, h: %u, v: %u, fmax: %u\n",
fwant, fxtal, htotal, vtotal, fmax);
for (p = 1; p <= pll->post_shift_max; p++) {
if (fwant * 2 > fmax)
break;
fwant *= 2;
}
if (fwant > fmax)
return 0;
for (; p-- > 0; fwant >>= 1) {
unsigned int m;
if (fwant < fmin) break;
for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
unsigned int n;
unsigned int dvd;
unsigned int ln;
n = (fwant * m) / fxtal;
if (n < pll->feed_div_min)
continue;
if (n > pll->feed_div_max)
break;
ln = fxtal * n;
dvd = m << p;
if (ln % dvd)
continue;
ln = ln / dvd;
if (ln < scrlen + 2)
continue;
ln = ln - scrlen;
if (ln > htotal)
continue;
dprintk(KERN_DEBUG "Match: %u / %u / %u / %u\n", n, m, p, ln);
if (ln > besth2) {
dprintk(KERN_DEBUG "Better...\n");
*h2 = besth2 = ln;
*post = p;
*in = m;
*feed = n;
}
}
}
/* if h2/post/in/feed have not been assigned, return zero (error) */
if (besth2 < 2)
return 0;
dprintk(KERN_ERR "clk: %02X %02X %02X %d %d\n", *in, *feed, *post, fxtal, fwant);
return fxtal * (*feed) / (*in) * ctl->den;
}
static int matroxfb_mavenclock(const struct matrox_pll_ctl *ctl,
unsigned int htotal, unsigned int vtotal,
unsigned int* in, unsigned int* feed, unsigned int* post,
unsigned int* htotal2) {
unsigned int fvco;
unsigned int p;
fvco = matroxfb_PLL_mavenclock(&maven1000_pll, ctl, htotal, vtotal, in, feed, &p, htotal2);
if (!fvco)
return -EINVAL;
p = (1 << p) - 1;
if (fvco <= 100000000)
;
else if (fvco <= 140000000)
p |= 0x08;
else if (fvco <= 180000000)
p |= 0x10;
else
p |= 0x18;
*post = p;
return 0;
}
static void DAC1064_calcclock(unsigned int freq, unsigned int fmax,
unsigned int* in, unsigned int* feed, unsigned int* post) {
unsigned int fvco;
unsigned int p;
fvco = matroxfb_PLL_calcclock(&maven_pll, freq, fmax, in, feed, &p);
p = (1 << p) - 1;
if (fvco <= 100000)
;
else if (fvco <= 140000)
p |= 0x08;
else if (fvco <= 180000)
p |= 0x10;
else
p |= 0x18;
*post = p;
return;
}
static unsigned char maven_compute_deflicker (const struct maven_data* md) {
unsigned char df;
df = (md->version == MGATVO_B?0x40:0x00);
switch (md->primary_head->altout.tvo_params.deflicker) {
case 0:
/* df |= 0x00; */
break;
case 1:
df |= 0xB1;
break;
case 2:
df |= 0xA2;
break;
}
return df;
}
static void maven_compute_bwlevel (const struct maven_data* md,
int *bl, int *wl) {
const int b = md->primary_head->altout.tvo_params.brightness + BLMIN;
const int c = md->primary_head->altout.tvo_params.contrast;
*bl = max(b - c, BLMIN);
*wl = min(b + c, WLMAX);
}
static const struct maven_gamma* maven_compute_gamma (const struct maven_data* md) {
return maven_gamma + md->primary_head->altout.tvo_params.gamma;
}
static void maven_init_TVdata(const struct maven_data* md, struct mavenregs* data) {
static struct mavenregs palregs = { {
0x2A, 0x09, 0x8A, 0xCB, /* 00: chroma subcarrier */
0x00,
0x00, /* ? not written */
0x00, /* modified by code (F9 written...) */
0x00, /* ? not written */
0x7E, /* 08 */
0x44, /* 09 */
0x9C, /* 0A */
0x2E, /* 0B */
0x21, /* 0C */
0x00, /* ? not written */
0x3F, 0x03, /* 0E-0F */
0x3F, 0x03, /* 10-11 */
0x1A, /* 12 */
0x2A, /* 13 */
0x1C, 0x3D, 0x14, /* 14-16 */
0x9C, 0x01, /* 17-18 */
0x00, /* 19 */
0xFE, /* 1A */
0x7E, /* 1B */
0x60, /* 1C */
0x05, /* 1D */
0x89, 0x03, /* 1E-1F */
0x72, /* 20 */
0x07, /* 21 */
0x72, /* 22 */
0x00, /* 23 */
0x00, /* 24 */
0x00, /* 25 */
0x08, /* 26 */
0x04, /* 27 */
0x00, /* 28 */
0x1A, /* 29 */
0x55, 0x01, /* 2A-2B */
0x26, /* 2C */
0x07, 0x7E, /* 2D-2E */
0x02, 0x54, /* 2F-30 */
0xB0, 0x00, /* 31-32 */
0x14, /* 33 */
0x49, /* 34 */
0x00, /* 35 written multiple times */
0x00, /* 36 not written */
0xA3, /* 37 */
0xC8, /* 38 */
0x22, /* 39 */
0x02, /* 3A */
0x22, /* 3B */
0x3F, 0x03, /* 3C-3D */
0x00, /* 3E written multiple times */
0x00, /* 3F not written */
}, MATROXFB_OUTPUT_MODE_PAL, 625, 50 };
static struct mavenregs ntscregs = { {
0x21, 0xF0, 0x7C, 0x1F, /* 00: chroma subcarrier */
0x00,
0x00, /* ? not written */
0x00, /* modified by code (F9 written...) */
0x00, /* ? not written */
0x7E, /* 08 */
0x43, /* 09 */
0x7E, /* 0A */
0x3D, /* 0B */
0x00, /* 0C */
0x00, /* ? not written */
0x41, 0x00, /* 0E-0F */
0x3C, 0x00, /* 10-11 */
0x17, /* 12 */
0x21, /* 13 */
0x1B, 0x1B, 0x24, /* 14-16 */
0x83, 0x01, /* 17-18 */
0x00, /* 19 */
0x0F, /* 1A */
0x0F, /* 1B */
0x60, /* 1C */
0x05, /* 1D */
0x89, 0x02, /* 1E-1F */
0x5F, /* 20 */
0x04, /* 21 */
0x5F, /* 22 */
0x01, /* 23 */
0x02, /* 24 */
0x00, /* 25 */
0x0A, /* 26 */
0x05, /* 27 */
0x00, /* 28 */
0x10, /* 29 */
0xFF, 0x03, /* 2A-2B */
0x24, /* 2C */
0x0F, 0x78, /* 2D-2E */
0x00, 0x00, /* 2F-30 */
0xB2, 0x04, /* 31-32 */
0x14, /* 33 */
0x02, /* 34 */
0x00, /* 35 written multiple times */
0x00, /* 36 not written */
0xA3, /* 37 */
0xC8, /* 38 */
0x15, /* 39 */
0x05, /* 3A */
0x3B, /* 3B */
0x3C, 0x00, /* 3C-3D */
0x00, /* 3E written multiple times */
0x00, /* never written */
}, MATROXFB_OUTPUT_MODE_NTSC, 525, 60 };
struct matrox_fb_info *minfo = md->primary_head;
if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_PAL)
*data = palregs;
else
*data = ntscregs;
/* Set deflicker */
data->regs[0x93] = maven_compute_deflicker(md);
/* set gamma */
{
const struct maven_gamma* g;
g = maven_compute_gamma(md);
data->regs[0x83] = g->reg83;
data->regs[0x84] = g->reg84;
data->regs[0x85] = g->reg85;
data->regs[0x86] = g->reg86;
data->regs[0x87] = g->reg87;
data->regs[0x88] = g->reg88;
data->regs[0x89] = g->reg89;
data->regs[0x8A] = g->reg8a;
data->regs[0x8B] = g->reg8b;
}
/* Set contrast / brightness */
{
int bl, wl;
maven_compute_bwlevel (md, &bl, &wl);
data->regs[0x0e] = bl >> 2;
data->regs[0x0f] = bl & 3;
data->regs[0x1e] = wl >> 2;
data->regs[0x1f] = wl & 3;
}
/* Set saturation */
{
data->regs[0x20] =
data->regs[0x22] = minfo->altout.tvo_params.saturation;
}
/* Set HUE */
data->regs[0x25] = minfo->altout.tvo_params.hue;
return;
}
#define LR(x) maven_set_reg(c, (x), m->regs[(x)])
#define LRP(x) maven_set_reg_pair(c, (x), m->regs[(x)] | (m->regs[(x)+1] << 8))
static void maven_init_TV(struct i2c_client* c, const struct mavenregs* m) {
int val;
maven_set_reg(c, 0x3E, 0x01);
maven_get_reg(c, 0x82); /* fetch oscillator state? */
maven_set_reg(c, 0x8C, 0x00);
maven_get_reg(c, 0x94); /* get 0x82 */
maven_set_reg(c, 0x94, 0xA2);
/* xmiscctrl */
maven_set_reg_pair(c, 0x8E, 0x1EFF);
maven_set_reg(c, 0xC6, 0x01);
/* removed code... */
maven_get_reg(c, 0x06);
maven_set_reg(c, 0x06, 0xF9); /* or read |= 0xF0 ? */
/* removed code here... */
/* real code begins here? */
/* chroma subcarrier */
LR(0x00); LR(0x01); LR(0x02); LR(0x03);
LR(0x04);
LR(0x2C);
LR(0x08);
LR(0x0A);
LR(0x09);
LR(0x29);
LRP(0x31);
LRP(0x17);
LR(0x0B);
LR(0x0C);
if (m->mode == MATROXFB_OUTPUT_MODE_PAL) {
maven_set_reg(c, 0x35, 0x10); /* ... */
} else {
maven_set_reg(c, 0x35, 0x0F); /* ... */
}
LRP(0x10);
LRP(0x0E);
LRP(0x1E);
LR(0x20); /* saturation #1 */
LR(0x22); /* saturation #2 */
LR(0x25); /* hue */
LR(0x34);
LR(0x33);
LR(0x19);
LR(0x12);
LR(0x3B);
LR(0x13);
LR(0x39);
LR(0x1D);
LR(0x3A);
LR(0x24);
LR(0x14);
LR(0x15);
LR(0x16);
LRP(0x2D);
LRP(0x2F);
LR(0x1A);
LR(0x1B);
LR(0x1C);
LR(0x23);
LR(0x26);
LR(0x28);
LR(0x27);
LR(0x21);
LRP(0x2A);
if (m->mode == MATROXFB_OUTPUT_MODE_PAL)
maven_set_reg(c, 0x35, 0x1D); /* ... */
else
maven_set_reg(c, 0x35, 0x1C);
LRP(0x3C);
LR(0x37);
LR(0x38);
maven_set_reg(c, 0xB3, 0x01);
maven_get_reg(c, 0xB0); /* read 0x80 */
maven_set_reg(c, 0xB0, 0x08); /* ugh... */
maven_get_reg(c, 0xB9); /* read 0x7C */
maven_set_reg(c, 0xB9, 0x78);
maven_get_reg(c, 0xBF); /* read 0x00 */
maven_set_reg(c, 0xBF, 0x02);
maven_get_reg(c, 0x94); /* read 0x82 */
maven_set_reg(c, 0x94, 0xB3);
LR(0x80); /* 04 1A 91 or 05 21 91 */
LR(0x81);
LR(0x82);
maven_set_reg(c, 0x8C, 0x20);
maven_get_reg(c, 0x8D);
maven_set_reg(c, 0x8D, 0x10);
LR(0x90); /* 4D 50 52 or 4E 05 45 */
LR(0x91);
LR(0x92);
LRP(0x9A); /* 0049 or 004F */
LRP(0x9C); /* 0004 or 0004 */
LRP(0x9E); /* 0458 or 045E */
LRP(0xA0); /* 05DA or 051B */
LRP(0xA2); /* 00CC or 00CF */
LRP(0xA4); /* 007D or 007F */
LRP(0xA6); /* 007C or 007E */
LRP(0xA8); /* 03CB or 03CE */
LRP(0x98); /* 0000 or 0000 */
LRP(0xAE); /* 0044 or 003A */
LRP(0x96); /* 05DA or 051B */
LRP(0xAA); /* 04BC or 046A */
LRP(0xAC); /* 004D or 004E */
LR(0xBE);
LR(0xC2);
maven_get_reg(c, 0x8D);
maven_set_reg(c, 0x8D, 0x04);
LR(0x20); /* saturation #1 */
LR(0x22); /* saturation #2 */
LR(0x93); /* whoops */
LR(0x20); /* oh, saturation #1 again */
LR(0x22); /* oh, saturation #2 again */
LR(0x25); /* hue */
LRP(0x0E);
LRP(0x1E);
LRP(0x0E); /* problems with memory? */
LRP(0x1E); /* yes, matrox must have problems in memory area... */
/* load gamma correction stuff */
LR(0x83);
LR(0x84);
LR(0x85);
LR(0x86);
LR(0x87);
LR(0x88);
LR(0x89);
LR(0x8A);
LR(0x8B);
val = maven_get_reg(c, 0x8D);
val &= 0x14; /* 0x10 or anything ored with it */
maven_set_reg(c, 0x8D, val);
LR(0x33);
LR(0x19);
LR(0x12);
LR(0x3B);
LR(0x13);
LR(0x39);
LR(0x1D);
LR(0x3A);
LR(0x24);
LR(0x14);
LR(0x15);
LR(0x16);
LRP(0x2D);
LRP(0x2F);
LR(0x1A);
LR(0x1B);
LR(0x1C);
LR(0x23);
LR(0x26);
LR(0x28);
LR(0x27);
LR(0x21);
LRP(0x2A);
if (m->mode == MATROXFB_OUTPUT_MODE_PAL)
maven_set_reg(c, 0x35, 0x1D);
else
maven_set_reg(c, 0x35, 0x1C);
LRP(0x3C);
LR(0x37);
LR(0x38);
maven_get_reg(c, 0xB0);
LR(0xB0); /* output mode */
LR(0x90);
LR(0xBE);
LR(0xC2);
LRP(0x9A);
LRP(0xA2);
LRP(0x9E);
LRP(0xA6);
LRP(0xAA);
LRP(0xAC);
maven_set_reg(c, 0x3E, 0x00);
maven_set_reg(c, 0x95, 0x20);
}
static int maven_find_exact_clocks(unsigned int ht, unsigned int vt,
struct mavenregs* m) {
unsigned int x;
unsigned int err = ~0;
/* 1:1 */
m->regs[0x80] = 0x0F;
m->regs[0x81] = 0x07;
m->regs[0x82] = 0x81;
for (x = 0; x < 8; x++) {
unsigned int c;
unsigned int a, b,
h2;
unsigned int h = ht + 2 + x;
if (!matroxfb_mavenclock((m->mode == MATROXFB_OUTPUT_MODE_PAL) ? &maven_PAL : &maven_NTSC, h, vt, &a, &b, &c, &h2)) {
unsigned int diff = h - h2;
if (diff < err) {
err = diff;
m->regs[0x80] = a - 1;
m->regs[0x81] = b - 1;
m->regs[0x82] = c | 0x80;
m->hcorr = h2 - 2;
m->htotal = h - 2;
}
}
}
return err != ~0U;
}
static inline int maven_compute_timming(struct maven_data* md,
struct my_timming* mt,
struct mavenregs* m) {
unsigned int tmpi;
unsigned int a, bv, c;
struct matrox_fb_info *minfo = md->primary_head;
m->mode = minfo->outputs[1].mode;
if (m->mode != MATROXFB_OUTPUT_MODE_MONITOR) {
unsigned int lmargin;
unsigned int umargin;
unsigned int vslen;
unsigned int hcrt;
unsigned int slen;
maven_init_TVdata(md, m);
if (maven_find_exact_clocks(mt->HTotal, mt->VTotal, m) == 0)
return -EINVAL;
lmargin = mt->HTotal - mt->HSyncEnd;
slen = mt->HSyncEnd - mt->HSyncStart;
hcrt = mt->HTotal - slen - mt->delay;
umargin = mt->VTotal - mt->VSyncEnd;
vslen = mt->VSyncEnd - mt->VSyncStart;
if (m->hcorr < mt->HTotal)
hcrt += m->hcorr;
if (hcrt > mt->HTotal)
hcrt -= mt->HTotal;
if (hcrt + 2 > mt->HTotal)
hcrt = 0; /* or issue warning? */
/* last (first? middle?) line in picture can have different length */
/* hlen - 2 */
m->regs[0x96] = m->hcorr;
m->regs[0x97] = m->hcorr >> 8;
/* ... */
m->regs[0x98] = 0x00; m->regs[0x99] = 0x00;
/* hblanking end */
m->regs[0x9A] = lmargin; /* 100% */
m->regs[0x9B] = lmargin >> 8; /* 100% */
/* who knows */
m->regs[0x9C] = 0x04;
m->regs[0x9D] = 0x00;
/* htotal - 2 */
m->regs[0xA0] = m->htotal;
m->regs[0xA1] = m->htotal >> 8;
/* vblanking end */
m->regs[0xA2] = mt->VTotal - mt->VSyncStart - 1; /* stop vblanking */
m->regs[0xA3] = (mt->VTotal - mt->VSyncStart - 1) >> 8;
/* something end... [A6]+1..[A8] */
if (md->version == MGATVO_B) {
m->regs[0xA4] = 0x04;
m->regs[0xA5] = 0x00;
} else {
m->regs[0xA4] = 0x01;
m->regs[0xA5] = 0x00;
}
/* something start... 0..[A4]-1 */
m->regs[0xA6] = 0x00;
m->regs[0xA7] = 0x00;
/* vertical line count - 1 */
m->regs[0xA8] = mt->VTotal - 1;
m->regs[0xA9] = (mt->VTotal - 1) >> 8;
/* horizontal vidrst pos */
m->regs[0xAA] = hcrt; /* 0 <= hcrt <= htotal - 2 */
m->regs[0xAB] = hcrt >> 8;
/* vertical vidrst pos */
m->regs[0xAC] = mt->VTotal - 2;
m->regs[0xAD] = (mt->VTotal - 2) >> 8;
/* moves picture up/down and so on... */
m->regs[0xAE] = 0x01; /* Fix this... 0..VTotal */
m->regs[0xAF] = 0x00;
{
int hdec;
int hlen;
unsigned int ibmin = 4 + lmargin + mt->HDisplay;
unsigned int ib;
int i;
/* Verify! */
/* Where 94208 came from? */
if (mt->HTotal)
hdec = 94208 / (mt->HTotal);
else
hdec = 0x81;
if (hdec > 0x81)
hdec = 0x81;
if (hdec < 0x41)
hdec = 0x41;
hdec--;
hlen = 98304 - 128 - ((lmargin + mt->HDisplay - 8) * hdec);
if (hlen < 0)
hlen = 0;
hlen = hlen >> 8;
if (hlen > 0xFF)
hlen = 0xFF;
/* Now we have to compute input buffer length.
If you want any picture, it must be between
4 + lmargin + xres
and
94208 / hdec
If you want perfect picture even on the top
of screen, it must be also
0x3C0000 * i / hdec + Q - R / hdec
where
R Qmin Qmax
0x07000 0x5AE 0x5BF
0x08000 0x5CF 0x5FF
0x0C000 0x653 0x67F
0x10000 0x6F8 0x6FF
*/
i = 1;
do {
ib = ((0x3C0000 * i - 0x8000)/ hdec + 0x05E7) >> 8;
i++;
} while (ib < ibmin);
if (ib >= m->htotal + 2) {
ib = ibmin;
}
m->regs[0x90] = hdec; /* < 0x40 || > 0x80 is bad... 0x80 is questionable */
m->regs[0xC2] = hlen;
/* 'valid' input line length */
m->regs[0x9E] = ib;
m->regs[0x9F] = ib >> 8;
}
{
int vdec;
int vlen;
#define MATROX_USE64BIT_DIVIDE
if (mt->VTotal) {
#ifdef MATROX_USE64BIT_DIVIDE
u64 f1;
u32 a;
u32 b;
a = m->vlines * (m->htotal + 2);
b = (mt->VTotal - 1) * (m->htotal + 2) + m->hcorr + 2;
f1 = ((u64)a) << 15; /* *32768 */
do_div(f1, b);
vdec = f1;
#else
vdec = m->vlines * 32768 / mt->VTotal;
#endif
} else
vdec = 0x8000;
if (vdec > 0x8000)
vdec = 0x8000;
vlen = (vslen + umargin + mt->VDisplay) * vdec;
vlen = (vlen >> 16) - 146; /* FIXME: 146?! */
if (vlen < 0)
vlen = 0;
if (vlen > 0xFF)
vlen = 0xFF;
vdec--;
m->regs[0x91] = vdec;
m->regs[0x92] = vdec >> 8;
m->regs[0xBE] = vlen;
}
m->regs[0xB0] = 0x08; /* output: SVideo/Composite */
return 0;
}
DAC1064_calcclock(mt->pixclock, 450000, &a, &bv, &c);
m->regs[0x80] = a;
m->regs[0x81] = bv;
m->regs[0x82] = c | 0x80;
m->regs[0xB3] = 0x01;
m->regs[0x94] = 0xB2;
/* htotal... */
m->regs[0x96] = mt->HTotal;
m->regs[0x97] = mt->HTotal >> 8;
/* ?? */
m->regs[0x98] = 0x00;
m->regs[0x99] = 0x00;
/* hsync len */
tmpi = mt->HSyncEnd - mt->HSyncStart;
m->regs[0x9A] = tmpi;
m->regs[0x9B] = tmpi >> 8;
/* hblank end */
tmpi = mt->HTotal - mt->HSyncStart;
m->regs[0x9C] = tmpi;
m->regs[0x9D] = tmpi >> 8;
/* hblank start */
tmpi += mt->HDisplay;
m->regs[0x9E] = tmpi;
m->regs[0x9F] = tmpi >> 8;
/* htotal + 1 */
tmpi = mt->HTotal + 1;
m->regs[0xA0] = tmpi;
m->regs[0xA1] = tmpi >> 8;
/* vsync?! */
tmpi = mt->VSyncEnd - mt->VSyncStart - 1;
m->regs[0xA2] = tmpi;
m->regs[0xA3] = tmpi >> 8;
/* ignored? */
tmpi = mt->VTotal - mt->VSyncStart;
m->regs[0xA4] = tmpi;
m->regs[0xA5] = tmpi >> 8;
/* ignored? */
tmpi = mt->VTotal - 1;
m->regs[0xA6] = tmpi;
m->regs[0xA7] = tmpi >> 8;
/* vtotal - 1 */
m->regs[0xA8] = tmpi;
m->regs[0xA9] = tmpi >> 8;
/* hor vidrst */
tmpi = mt->HTotal - mt->delay;
m->regs[0xAA] = tmpi;
m->regs[0xAB] = tmpi >> 8;
/* vert vidrst */
tmpi = mt->VTotal - 2;
m->regs[0xAC] = tmpi;
m->regs[0xAD] = tmpi >> 8;
/* ignored? */
m->regs[0xAE] = 0x00;
m->regs[0xAF] = 0x00;
m->regs[0xB0] = 0x03; /* output: monitor */
m->regs[0xB1] = 0xA0; /* ??? */
m->regs[0x8C] = 0x20; /* must be set... */
m->regs[0x8D] = 0x04; /* defaults to 0x10: test signal */
m->regs[0xB9] = 0x1A; /* defaults to 0x2C: too bright */
m->regs[0xBF] = 0x22; /* makes picture stable */
return 0;
}
static int maven_program_timming(struct maven_data* md,
const struct mavenregs* m) {
struct i2c_client *c = md->client;
if (m->mode == MATROXFB_OUTPUT_MODE_MONITOR) {
LR(0x80);
LR(0x81);
LR(0x82);
LR(0xB3);
LR(0x94);
LRP(0x96);
LRP(0x98);
LRP(0x9A);
LRP(0x9C);
LRP(0x9E);
LRP(0xA0);
LRP(0xA2);
LRP(0xA4);
LRP(0xA6);
LRP(0xA8);
LRP(0xAA);
LRP(0xAC);
LRP(0xAE);
LR(0xB0); /* output: monitor */
LR(0xB1); /* ??? */
LR(0x8C); /* must be set... */
LR(0x8D); /* defaults to 0x10: test signal */
LR(0xB9); /* defaults to 0x2C: too bright */
LR(0xBF); /* makes picture stable */
} else {
maven_init_TV(c, m);
}
return 0;
}
static inline int maven_resync(struct maven_data* md) {
struct i2c_client *c = md->client;
maven_set_reg(c, 0x95, 0x20); /* start whole thing */
return 0;
}
static int maven_get_queryctrl (struct maven_data* md,
struct v4l2_queryctrl *p) {
int i;
i = get_ctrl_id(p->id);
if (i >= 0) {
*p = maven_controls[i].desc;
return 0;
}
if (i == -ENOENT) {
static const struct v4l2_queryctrl disctrl =
{ .flags = V4L2_CTRL_FLAG_DISABLED };
i = p->id;
*p = disctrl;
p->id = i;
sprintf(p->name, "Ctrl #%08X", i);
return 0;
}
return -EINVAL;
}
static int maven_set_control (struct maven_data* md,
struct v4l2_control *p) {
int i;
i = get_ctrl_id(p->id);
if (i < 0) return -EINVAL;
/*
* Check if changed.
*/
if (p->value == *get_ctrl_ptr(md, i)) return 0;
/*
* Check limits.
*/
if (p->value > maven_controls[i].desc.maximum) return -EINVAL;
if (p->value < maven_controls[i].desc.minimum) return -EINVAL;
/*
* Store new value.
*/
*get_ctrl_ptr(md, i) = p->value;
switch (p->id) {
case V4L2_CID_BRIGHTNESS:
case V4L2_CID_CONTRAST:
{
int blacklevel, whitelevel;
maven_compute_bwlevel(md, &blacklevel, &whitelevel);
blacklevel = (blacklevel >> 2) | ((blacklevel & 3) << 8);
whitelevel = (whitelevel >> 2) | ((whitelevel & 3) << 8);
maven_set_reg_pair(md->client, 0x0e, blacklevel);
maven_set_reg_pair(md->client, 0x1e, whitelevel);
}
break;
case V4L2_CID_SATURATION:
{
maven_set_reg(md->client, 0x20, p->value);
maven_set_reg(md->client, 0x22, p->value);
}
break;
case V4L2_CID_HUE:
{
maven_set_reg(md->client, 0x25, p->value);
}
break;
case V4L2_CID_GAMMA:
{
const struct maven_gamma* g;
g = maven_compute_gamma(md);
maven_set_reg(md->client, 0x83, g->reg83);
maven_set_reg(md->client, 0x84, g->reg84);
maven_set_reg(md->client, 0x85, g->reg85);
maven_set_reg(md->client, 0x86, g->reg86);
maven_set_reg(md->client, 0x87, g->reg87);
maven_set_reg(md->client, 0x88, g->reg88);
maven_set_reg(md->client, 0x89, g->reg89);
maven_set_reg(md->client, 0x8a, g->reg8a);
maven_set_reg(md->client, 0x8b, g->reg8b);
}
break;
case MATROXFB_CID_TESTOUT:
{
unsigned char val
= maven_get_reg(md->client, 0x8d);
if (p->value) val |= 0x10;
else val &= ~0x10;
maven_set_reg(md->client, 0x8d, val);
}
break;
case MATROXFB_CID_DEFLICKER:
{
maven_set_reg(md->client, 0x93, maven_compute_deflicker(md));
}
break;
}
return 0;
}
static int maven_get_control (struct maven_data* md,
struct v4l2_control *p) {
int i;
i = get_ctrl_id(p->id);
if (i < 0) return -EINVAL;
p->value = *get_ctrl_ptr(md, i);
return 0;
}
/******************************************************/
static int maven_out_compute(void* md, struct my_timming* mt) {
#define mdinfo ((struct maven_data*)md)
#define minfo (mdinfo->primary_head)
return maven_compute_timming(md, mt, &minfo->hw.maven);
#undef minfo
#undef mdinfo
}
static int maven_out_program(void* md) {
#define mdinfo ((struct maven_data*)md)
#define minfo (mdinfo->primary_head)
return maven_program_timming(md, &minfo->hw.maven);
#undef minfo
#undef mdinfo
}
static int maven_out_start(void* md) {
return maven_resync(md);
}
static int maven_out_verify_mode(void* md, u_int32_t arg) {
switch (arg) {
case MATROXFB_OUTPUT_MODE_PAL:
case MATROXFB_OUTPUT_MODE_NTSC:
case MATROXFB_OUTPUT_MODE_MONITOR:
return 0;
}
return -EINVAL;
}
static int maven_out_get_queryctrl(void* md, struct v4l2_queryctrl* p) {
return maven_get_queryctrl(md, p);
}
static int maven_out_get_ctrl(void* md, struct v4l2_control* p) {
return maven_get_control(md, p);
}
static int maven_out_set_ctrl(void* md, struct v4l2_control* p) {
return maven_set_control(md, p);
}
static struct matrox_altout maven_altout = {
.name = "Secondary output",
.compute = maven_out_compute,
.program = maven_out_program,
.start = maven_out_start,
.verifymode = maven_out_verify_mode,
.getqueryctrl = maven_out_get_queryctrl,
.getctrl = maven_out_get_ctrl,
.setctrl = maven_out_set_ctrl,
};
static int maven_init_client(struct i2c_client* clnt) {
struct maven_data* md = i2c_get_clientdata(clnt);
struct matrox_fb_info *minfo = container_of(clnt->adapter,
struct i2c_bit_adapter,
adapter)->minfo;
md->primary_head = minfo;
md->client = clnt;
down_write(&minfo->altout.lock);
minfo->outputs[1].output = &maven_altout;
minfo->outputs[1].src = minfo->outputs[1].default_src;
minfo->outputs[1].data = md;
minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&minfo->altout.lock);
if (maven_get_reg(clnt, 0xB2) < 0x14) {
md->version = MGATVO_B;
/* Tweak some things for this old chip */
} else {
md->version = MGATVO_C;
}
/*
* Set all parameters to its initial values.
*/
{
unsigned int i;
for (i = 0; i < MAVCTRLS; ++i) {
*get_ctrl_ptr(md, i) = maven_controls[i].desc.default_value;
}
}
return 0;
}
static int maven_shutdown_client(struct i2c_client* clnt) {
struct maven_data* md = i2c_get_clientdata(clnt);
if (md->primary_head) {
struct matrox_fb_info *minfo = md->primary_head;
down_write(&minfo->altout.lock);
minfo->outputs[1].src = MATROXFB_SRC_NONE;
minfo->outputs[1].output = NULL;
minfo->outputs[1].data = NULL;
minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&minfo->altout.lock);
md->primary_head = NULL;
}
return 0;
}
static int maven_probe(struct i2c_client *client)
{
struct i2c_adapter *adapter = client->adapter;
int err = -ENODEV;
struct maven_data* data;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WRITE_WORD_DATA |
I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_NOSTART |
I2C_FUNC_PROTOCOL_MANGLING))
goto ERROR0;
if (!(data = kzalloc(sizeof(*data), GFP_KERNEL))) {
err = -ENOMEM;
goto ERROR0;
}
i2c_set_clientdata(client, data);
err = maven_init_client(client);
if (err)
goto ERROR4;
return 0;
ERROR4:;
kfree(data);
ERROR0:;
return err;
}
static void maven_remove(struct i2c_client *client)
{
maven_shutdown_client(client);
kfree(i2c_get_clientdata(client));
}
static const struct i2c_device_id maven_id[] = {
{ "maven", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, maven_id);
static struct i2c_driver maven_driver={
.driver = {
.name = "maven",
},
.probe = maven_probe,
.remove = maven_remove,
.id_table = maven_id,
};
module_i2c_driver(maven_driver);
MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <[email protected]>");
MODULE_DESCRIPTION("Matrox G200/G400 Matrox MGA-TVO driver");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/matrox/matroxfb_maven.c |
// SPDX-License-Identifier: GPL-2.0-only
/*
*
* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
*
* (c) 1998-2002 Petr Vandrovec <[email protected]>
*
* Portions Copyright (c) 2001 Matrox Graphics Inc.
*
* Version: 1.65 2002/08/14
*
* MTRR stuff: 1998 Tom Rini <[email protected]>
*
* Contributors: "menion?" <[email protected]>
* Betatesting, fixes, ideas
*
* "Kurt Garloff" <[email protected]>
* Betatesting, fixes, ideas, videomodes, videomodes timmings
*
* "Tom Rini" <[email protected]>
* MTRR stuff, PPC cleanups, betatesting, fixes, ideas
*
* "Bibek Sahu" <[email protected]>
* Access device through readb|w|l and write b|w|l
* Extensive debugging stuff
*
* "Daniel Haun" <[email protected]>
* Testing, hardware cursor fixes
*
* "Scott Wood" <[email protected]>
* Fixes
*
* "Gerd Knorr" <[email protected]>
* Betatesting
*
* "Kelly French" <[email protected]>
* "Fernando Herrera" <[email protected]>
* Betatesting, bug reporting
*
* "Pablo Bianucci" <[email protected]>
* Fixes, ideas, betatesting
*
* "Inaky Perez Gonzalez" <[email protected]>
* Fixes, enhandcements, ideas, betatesting
*
* "Ryuichi Oikawa" <[email protected]>
* PPC betatesting, PPC support, backward compatibility
*
* "Paul Womar" <[email protected]>
* "Owen Waller" <[email protected]>
* PPC betatesting
*
* "Thomas Pornin" <[email protected]>
* Alpha betatesting
*
* "Pieter van Leuven" <[email protected]>
* "Ulf Jaenicke-Roessler" <[email protected]>
* G100 testing
*
* "H. Peter Arvin" <[email protected]>
* Ideas
*
* "Cort Dougan" <[email protected]>
* CHRP fixes and PReP cleanup
*
* "Mark Vojkovich" <[email protected]>
* G400 support
*
* "David C. Hansen" <[email protected]>
* Fixes
*
* "Ian Romanick" <[email protected]>
* Find PInS data in BIOS on PowerPC systems.
*
* (following author is not in any relation with this code, but his code
* is included in this driver)
*
* Based on framebuffer driver for VBE 2.0 compliant graphic boards
* (c) 1998 Gerd Knorr <[email protected]>
*
* (following author is not in any relation with this code, but his ideas
* were used when writing this driver)
*
* FreeVBE/AF (Matrox), "Shawn Hargreaves" <[email protected]>
*
*/
#include "matroxfb_misc.h"
#include <linux/interrupt.h>
#include <linux/matroxfb.h>
void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
{
DBG_REG(__func__)
mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
}
int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
{
DBG_REG(__func__)
mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
}
void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) {
unsigned int pixclock = var->pixclock;
DBG(__func__)
if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
mt->pixclock = 1000000000 / pixclock;
if (mt->pixclock < 1) mt->pixclock = 1;
mt->mnp = -1;
mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
mt->HDisplay = var->xres;
mt->HSyncStart = mt->HDisplay + var->right_margin;
mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
mt->HTotal = mt->HSyncEnd + var->left_margin;
mt->VDisplay = var->yres;
mt->VSyncStart = mt->VDisplay + var->lower_margin;
mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
mt->VTotal = mt->VSyncEnd + var->upper_margin;
mt->sync = var->sync;
}
int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
unsigned int* in, unsigned int* feed, unsigned int* post) {
unsigned int bestdiff = ~0;
unsigned int bestvco = 0;
unsigned int fxtal = pll->ref_freq;
unsigned int fwant;
unsigned int p;
DBG(__func__)
fwant = freq;
#ifdef DEBUG
printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
printk(KERN_ERR "freq: %d\n", freq);
printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
printk(KERN_ERR "fmax: %d\n", fmax);
#endif
for (p = 1; p <= pll->post_shift_max; p++) {
if (fwant * 2 > fmax)
break;
fwant *= 2;
}
if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
if (fwant > fmax) fwant = fmax;
for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
unsigned int m;
if (fwant < pll->vco_freq_min) break;
for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
unsigned int diff, fvco;
unsigned int n;
n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
if (n > pll->feed_div_max)
break;
if (n < pll->feed_div_min)
n = pll->feed_div_min;
fvco = (fxtal * (n + 1)) / (m + 1);
if (fvco < fwant)
diff = fwant - fvco;
else
diff = fvco - fwant;
if (diff < bestdiff) {
bestdiff = diff;
*post = p;
*in = m;
*feed = n;
bestvco = fvco;
}
}
}
dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant);
return bestvco;
}
int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
{
unsigned int hd, hs, he, hbe, ht;
unsigned int vd, vs, ve, vt, lc;
unsigned int wd;
unsigned int divider;
int i;
struct matrox_hw_state * const hw = &minfo->hw;
DBG(__func__)
hw->SEQ[0] = 0x00;
hw->SEQ[1] = 0x01; /* or 0x09 */
hw->SEQ[2] = 0x0F; /* bitplanes */
hw->SEQ[3] = 0x00;
hw->SEQ[4] = 0x0E;
/* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */
if (m->dblscan) {
m->VTotal <<= 1;
m->VDisplay <<= 1;
m->VSyncStart <<= 1;
m->VSyncEnd <<= 1;
}
if (m->interlaced) {
m->VTotal >>= 1;
m->VDisplay >>= 1;
m->VSyncStart >>= 1;
m->VSyncEnd >>= 1;
}
/* GCTL is ignored when not using 0xA0000 aperture */
hw->GCTL[0] = 0x00;
hw->GCTL[1] = 0x00;
hw->GCTL[2] = 0x00;
hw->GCTL[3] = 0x00;
hw->GCTL[4] = 0x00;
hw->GCTL[5] = 0x40;
hw->GCTL[6] = 0x05;
hw->GCTL[7] = 0x0F;
hw->GCTL[8] = 0xFF;
/* Whole ATTR is ignored in PowerGraphics mode */
for (i = 0; i < 16; i++)
hw->ATTR[i] = i;
hw->ATTR[16] = 0x41;
hw->ATTR[17] = 0xFF;
hw->ATTR[18] = 0x0F;
hw->ATTR[19] = 0x00;
hw->ATTR[20] = 0x00;
hd = m->HDisplay >> 3;
hs = m->HSyncStart >> 3;
he = m->HSyncEnd >> 3;
ht = m->HTotal >> 3;
/* standard timmings are in 8pixels, but for interleaved we cannot */
/* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
/* using 16 or more pixels per unit can save us */
divider = minfo->curr.final_bppShift;
while (divider & 3) {
hd >>= 1;
hs >>= 1;
he >>= 1;
ht >>= 1;
divider <<= 1;
}
divider = divider / 4;
/* divider can be from 1 to 8 */
while (divider > 8) {
hd <<= 1;
hs <<= 1;
he <<= 1;
ht <<= 1;
divider >>= 1;
}
hd = hd - 1;
hs = hs - 1;
he = he - 1;
ht = ht - 1;
vd = m->VDisplay - 1;
vs = m->VSyncStart - 1;
ve = m->VSyncEnd - 1;
vt = m->VTotal - 2;
lc = vd;
/* G200 cannot work with (ht & 7) == 6 */
if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
ht++;
hbe = ht;
wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
hw->CRTCEXT[0] = 0;
hw->CRTCEXT[5] = 0;
if (m->interlaced) {
hw->CRTCEXT[0] = 0x80;
hw->CRTCEXT[5] = (hs + he - ht) >> 1;
if (!m->dblscan)
wd <<= 1;
vt &= ~1;
}
hw->CRTCEXT[0] |= (wd & 0x300) >> 4;
hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
((hd & 0x100) >> 7) | /* blanking */
((hs & 0x100) >> 6) | /* sync start */
(hbe & 0x040); /* end hor. blanking */
/* FIXME: Enable vidrst only on G400, and only if TV-out is used */
if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
((vd & 0x400) >> 8) | /* disp end */
((vd & 0xC00) >> 7) | /* vblanking start */
((vs & 0xC00) >> 5) |
((lc & 0x400) >> 3);
hw->CRTCEXT[3] = (divider - 1) | 0x80;
hw->CRTCEXT[4] = 0;
hw->CRTC[0] = ht-4;
hw->CRTC[1] = hd;
hw->CRTC[2] = hd;
hw->CRTC[3] = (hbe & 0x1F) | 0x80;
hw->CRTC[4] = hs;
hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
hw->CRTC[6] = vt & 0xFF;
hw->CRTC[7] = ((vt & 0x100) >> 8) |
((vd & 0x100) >> 7) |
((vs & 0x100) >> 6) |
((vd & 0x100) >> 5) |
((lc & 0x100) >> 4) |
((vt & 0x200) >> 4) |
((vd & 0x200) >> 3) |
((vs & 0x200) >> 2);
hw->CRTC[8] = 0x00;
hw->CRTC[9] = ((vd & 0x200) >> 4) |
((lc & 0x200) >> 3);
if (m->dblscan && !m->interlaced)
hw->CRTC[9] |= 0x80;
for (i = 10; i < 16; i++)
hw->CRTC[i] = 0x00;
hw->CRTC[16] = vs /* & 0xFF */;
hw->CRTC[17] = (ve & 0x0F) | 0x20;
hw->CRTC[18] = vd /* & 0xFF */;
hw->CRTC[19] = wd /* & 0xFF */;
hw->CRTC[20] = 0x00;
hw->CRTC[21] = vd /* & 0xFF */;
hw->CRTC[22] = (vt + 1) /* & 0xFF */;
hw->CRTC[23] = 0xC3;
hw->CRTC[24] = lc;
return 0;
};
void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
{
int i;
struct matrox_hw_state * const hw = &minfo->hw;
CRITFLAGS
DBG(__func__)
dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
dprintk(KERN_INFO "SEQ regs: ");
for (i = 0; i < 5; i++)
dprintk("%02X:", hw->SEQ[i]);
dprintk("\n");
dprintk(KERN_INFO "GDC regs: ");
for (i = 0; i < 9; i++)
dprintk("%02X:", hw->GCTL[i]);
dprintk("\n");
dprintk(KERN_INFO "CRTC regs: ");
for (i = 0; i < 25; i++)
dprintk("%02X:", hw->CRTC[i]);
dprintk("\n");
dprintk(KERN_INFO "ATTR regs: ");
for (i = 0; i < 21; i++)
dprintk("%02X:", hw->ATTR[i]);
dprintk("\n");
CRITBEGIN
mga_inb(M_ATTR_RESET);
mga_outb(M_ATTR_INDEX, 0);
mga_outb(M_MISC_REG, hw->MiscOutReg);
for (i = 1; i < 5; i++)
mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
for (i = 0; i < 25; i++)
mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
for (i = 0; i < 9; i++)
mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
for (i = 0; i < 21; i++) {
mga_inb(M_ATTR_RESET);
mga_outb(M_ATTR_INDEX, i);
mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
}
mga_outb(M_PALETTE_MASK, 0xFF);
mga_outb(M_DAC_REG, 0x00);
for (i = 0; i < 768; i++)
mga_outb(M_DAC_VAL, hw->DACpal[i]);
mga_inb(M_ATTR_RESET);
mga_outb(M_ATTR_INDEX, 0x20);
CRITEND
}
static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) {
unsigned int b0 = readb(pins);
if (b0 == 0x2E && readb(pins+1) == 0x41) {
unsigned int pins_len = readb(pins+2);
unsigned int i;
unsigned char cksum;
unsigned char* dst = bd->pins;
if (pins_len < 3 || pins_len > 128) {
return;
}
*dst++ = 0x2E;
*dst++ = 0x41;
*dst++ = pins_len;
cksum = 0x2E + 0x41 + pins_len;
for (i = 3; i < pins_len; i++) {
cksum += *dst++ = readb(pins+i);
}
if (cksum) {
return;
}
bd->pins_len = pins_len;
} else if (b0 == 0x40 && readb(pins+1) == 0x00) {
unsigned int i;
unsigned char* dst = bd->pins;
*dst++ = 0x40;
*dst++ = 0;
for (i = 2; i < 0x40; i++) {
*dst++ = readb(pins+i);
}
bd->pins_len = 0x40;
}
}
static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) {
unsigned int pcir_offset;
pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8);
if (pcir_offset >= 26 && pcir_offset < 0xFFE0 &&
readb(vbios + pcir_offset ) == 'P' &&
readb(vbios + pcir_offset + 1) == 'C' &&
readb(vbios + pcir_offset + 2) == 'I' &&
readb(vbios + pcir_offset + 3) == 'R') {
unsigned char h;
h = readb(vbios + pcir_offset + 0x12);
bd->version.vMaj = (h >> 4) & 0xF;
bd->version.vMin = h & 0xF;
bd->version.vRev = readb(vbios + pcir_offset + 0x13);
} else {
unsigned char h;
h = readb(vbios + 5);
bd->version.vMaj = (h >> 4) & 0xF;
bd->version.vMin = h & 0xF;
bd->version.vRev = 0;
}
}
static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) {
unsigned char b;
b = readb(vbios + 0x7FF1);
if (b == 0xFF) {
b = 0;
}
bd->output.state = b;
}
static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) {
unsigned int i;
/* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
bd->output.tvout = 0;
if (readb(vbios + 0x1D) != 'I' ||
readb(vbios + 0x1E) != 'B' ||
readb(vbios + 0x1F) != 'M' ||
readb(vbios + 0x20) != ' ') {
return;
}
for (i = 0x2D; i < 0x2D + 128; i++) {
unsigned char b = readb(vbios + i);
if (b == '(' && readb(vbios + i + 1) == 'V') {
if (readb(vbios + i + 6) == 'T' &&
readb(vbios + i + 7) == 'V' &&
readb(vbios + i + 8) == 'O') {
bd->output.tvout = 1;
}
return;
}
if (b == 0)
break;
}
}
static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
unsigned int pins_offset;
if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) {
return;
}
bd->bios_valid = 1;
get_bios_version(vbios, bd);
get_bios_output(vbios, bd);
get_bios_tvout(vbios, bd);
#if defined(__powerpc__)
/* On PowerPC cards, the PInS offset isn't stored at the end of the
* BIOS image. Instead, you must search the entire BIOS image for
* the magic PInS signature.
*
* This actually applies to all OpenFirmware base cards. Since these
* cards could be put in a MIPS or SPARC system, should the condition
* be something different?
*/
for ( pins_offset = 0 ; pins_offset <= 0xFF80 ; pins_offset++ ) {
unsigned char header[3];
header[0] = readb(vbios + pins_offset);
header[1] = readb(vbios + pins_offset + 1);
header[2] = readb(vbios + pins_offset + 2);
if ( (header[0] == 0x2E) && (header[1] == 0x41)
&& ((header[2] == 0x40) || (header[2] == 0x80)) ) {
printk(KERN_INFO "PInS data found at offset %u\n",
pins_offset);
get_pins(vbios + pins_offset, bd);
break;
}
}
#else
pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8);
if (pins_offset <= 0xFF80) {
get_pins(vbios + pins_offset, bd);
}
#endif
}
static int parse_pins1(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
unsigned int maxdac;
switch (bd->pins[22]) {
case 0: maxdac = 175000; break;
case 1: maxdac = 220000; break;
default: maxdac = 240000; break;
}
if (get_unaligned_le16(bd->pins + 24)) {
maxdac = get_unaligned_le16(bd->pins + 24) * 10;
}
minfo->limits.pixel.vcomax = maxdac;
minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
get_unaligned_le16(bd->pins + 28) * 10 : 50000;
/* ignore 4MB, 8MB, module clocks */
minfo->features.pll.ref_freq = 14318;
minfo->values.reg.mctlwtst = 0x00030101;
return 0;
}
static void default_pins1(struct matrox_fb_info *minfo)
{
/* Millennium */
minfo->limits.pixel.vcomax = 220000;
minfo->values.pll.system = 50000;
minfo->features.pll.ref_freq = 14318;
minfo->values.reg.mctlwtst = 0x00030101;
}
static int parse_pins2(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
((bd->pins[51] & 0x08) ? 0x00020000 : 0);
minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
minfo->features.pll.ref_freq = 14318;
return 0;
}
static void default_pins2(struct matrox_fb_info *minfo)
{
/* Millennium II, Mystique */
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = 230000;
minfo->values.reg.mctlwtst = 0x00030101;
minfo->values.pll.system = 50000;
minfo->features.pll.ref_freq = 14318;
}
static int parse_pins3(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
0x01250A21 : get_unaligned_le32(bd->pins + 48);
/* memory config */
minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
((bd->pins[57] << 22) & 0x00C00000) |
((bd->pins[56] << 1) & 0x000001E0) |
( bd->pins[56] & 0x0000000F);
minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
minfo->values.reg.opt2 = bd->pins[58] << 12;
minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
return 0;
}
static void default_pins3(struct matrox_fb_info *minfo)
{
/* G100, G200 */
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = 230000;
minfo->values.reg.mctlwtst = 0x01250A21;
minfo->values.reg.memrdbk = 0x00000000;
minfo->values.reg.opt = 0x00000C00;
minfo->values.reg.opt2 = 0x00000000;
minfo->features.pll.ref_freq = 27000;
}
static int parse_pins4(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
((bd->pins[87] << 22) & 0x00C00000) |
((bd->pins[86] << 1) & 0x000001E0) |
( bd->pins[86] & 0x0000000F);
minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
((bd->pins[53] << 22) & 0x10000000) |
((bd->pins[53] << 7) & 0x00001C00);
minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
return 0;
}
static void default_pins4(struct matrox_fb_info *minfo)
{
/* G400 */
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = 252000;
minfo->values.reg.mctlwtst = 0x04A450A1;
minfo->values.reg.memrdbk = 0x000000E7;
minfo->values.reg.opt = 0x10000400;
minfo->values.reg.opt3 = 0x0190A419;
minfo->values.pll.system = 200000;
minfo->features.pll.ref_freq = 27000;
}
static int parse_pins5(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
unsigned int mult;
mult = bd->pins[4]?8000:6000;
minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
minfo->values.pll.system =
minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
if (bd->pins[115] & 4) {
minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
} else {
static const u8 wtst_xlat[] = {
0, 1, 5, 6, 7, 5, 2, 3
};
minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
wtst_xlat[minfo->values.reg.mctlwtst & 7];
}
minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
return 0;
}
static void default_pins5(struct matrox_fb_info *minfo)
{
/* Mine 16MB G450 with SDRAM DDR */
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax =
minfo->limits.video.vcomax = 600000;
minfo->limits.pixel.vcomin =
minfo->limits.system.vcomin =
minfo->limits.video.vcomin = 256000;
minfo->values.pll.system =
minfo->values.pll.video = 284000;
minfo->values.reg.opt = 0x404A1160;
minfo->values.reg.opt2 = 0x0000AC00;
minfo->values.reg.opt3 = 0x0090A409;
minfo->values.reg.mctlwtst_core =
minfo->values.reg.mctlwtst = 0x0C81462B;
minfo->values.reg.memmisc = 0x80000004;
minfo->values.reg.memrdbk = 0x01001103;
minfo->features.pll.ref_freq = 27000;
minfo->values.memory.ddr = 1;
minfo->values.memory.dll = 1;
minfo->values.memory.emrswen = 1;
minfo->values.reg.maccess = 0x00004000;
}
static int matroxfb_set_limits(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
unsigned int pins_version;
static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
switch (minfo->chip) {
case MGA_2064: default_pins1(minfo); break;
case MGA_2164:
case MGA_1064:
case MGA_1164: default_pins2(minfo); break;
case MGA_G100:
case MGA_G200: default_pins3(minfo); break;
case MGA_G400: default_pins4(minfo); break;
case MGA_G450:
case MGA_G550: default_pins5(minfo); break;
}
if (!bd->bios_valid) {
printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
return -1;
}
if (bd->pins_len < 64) {
printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n");
return -1;
}
if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
pins_version = bd->pins[5];
if (pins_version < 2 || pins_version > 5) {
printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version);
return -1;
}
} else {
pins_version = 1;
}
if (bd->pins_len != pinslen[pins_version - 1]) {
printk(KERN_INFO "matroxfb: Invalid powerup info\n");
return -1;
}
switch (pins_version) {
case 1:
return parse_pins1(minfo, bd);
case 2:
return parse_pins2(minfo, bd);
case 3:
return parse_pins3(minfo, bd);
case 4:
return parse_pins4(minfo, bd);
case 5:
return parse_pins5(minfo, bd);
default:
printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
return -1;
}
}
void matroxfb_read_pins(struct matrox_fb_info *minfo)
{
u32 opt;
u32 biosbase;
u32 fbbase;
struct pci_dev *pdev = minfo->pcidev;
memset(&minfo->bios, 0, sizeof(minfo->bios));
pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
#ifdef CONFIG_X86
if (!minfo->bios.bios_valid) {
unsigned char __iomem* b;
b = ioremap(0x000C0000, 65536);
if (!b) {
printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n");
} else {
unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8);
unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8);
if (ven != pdev->vendor || dev != pdev->device) {
printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
ven, dev, pdev->vendor, pdev->device);
} else {
parse_bios(b, &minfo->bios);
}
iounmap(b);
}
}
#endif
matroxfb_set_limits(minfo, &minfo->bios);
printk(KERN_INFO "PInS memtype = %u\n",
(minfo->values.reg.opt & 0x1C00) >> 10);
}
EXPORT_SYMBOL(matroxfb_DAC_in);
EXPORT_SYMBOL(matroxfb_DAC_out);
EXPORT_SYMBOL(matroxfb_var2my);
EXPORT_SYMBOL(matroxfb_PLL_calcclock);
EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
EXPORT_SYMBOL(matroxfb_read_pins);
MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <[email protected]>");
MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards");
MODULE_LICENSE("GPL");
| linux-master | drivers/video/fbdev/matrox/matroxfb_misc.c |
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